From 3e185bca9ccb897650c4759be9423ca583e6c30d Mon Sep 17 00:00:00 2001 From: ArdaFu Date: Tue, 25 Apr 2017 18:02:51 +0800 Subject: [PATCH] 1. [bsp] tm4c129x update TivaWare to 2.1.4.178 --- bsp/tm4c129x/applications/board.h | 8 +- bsp/tm4c129x/libraries/driverlib/adc.c | 128 +- bsp/tm4c129x/libraries/driverlib/adc.h | 5 +- bsp/tm4c129x/libraries/driverlib/aes.c | 4 +- bsp/tm4c129x/libraries/driverlib/aes.h | 4 +- bsp/tm4c129x/libraries/driverlib/can.c | 4 +- bsp/tm4c129x/libraries/driverlib/can.h | 4 +- bsp/tm4c129x/libraries/driverlib/comp.c | 4 +- bsp/tm4c129x/libraries/driverlib/comp.h | 4 +- bsp/tm4c129x/libraries/driverlib/cpu.c | 4 +- bsp/tm4c129x/libraries/driverlib/cpu.h | 4 +- bsp/tm4c129x/libraries/driverlib/crc.c | 4 +- bsp/tm4c129x/libraries/driverlib/crc.h | 6 +- bsp/tm4c129x/libraries/driverlib/debug.h | 4 +- bsp/tm4c129x/libraries/driverlib/des.c | 4 +- bsp/tm4c129x/libraries/driverlib/des.h | 4 +- bsp/tm4c129x/libraries/driverlib/eeprom.c | 4 +- bsp/tm4c129x/libraries/driverlib/eeprom.h | 4 +- bsp/tm4c129x/libraries/driverlib/emac.c | 301 +- bsp/tm4c129x/libraries/driverlib/emac.h | 22 +- bsp/tm4c129x/libraries/driverlib/epi.c | 4 +- bsp/tm4c129x/libraries/driverlib/epi.h | 4 +- bsp/tm4c129x/libraries/driverlib/flash.c | 132 +- bsp/tm4c129x/libraries/driverlib/flash.h | 13 +- bsp/tm4c129x/libraries/driverlib/fpu.c | 4 +- bsp/tm4c129x/libraries/driverlib/fpu.h | 4 +- bsp/tm4c129x/libraries/driverlib/gpio.c | 601 ++-- bsp/tm4c129x/libraries/driverlib/gpio.h | 12 +- bsp/tm4c129x/libraries/driverlib/hibernate.c | 16 +- bsp/tm4c129x/libraries/driverlib/hibernate.h | 4 +- bsp/tm4c129x/libraries/driverlib/i2c.c | 68 +- bsp/tm4c129x/libraries/driverlib/i2c.h | 7 +- bsp/tm4c129x/libraries/driverlib/interrupt.c | 4 +- bsp/tm4c129x/libraries/driverlib/interrupt.h | 4 +- bsp/tm4c129x/libraries/driverlib/lcd.c | 4 +- bsp/tm4c129x/libraries/driverlib/lcd.h | 4 +- bsp/tm4c129x/libraries/driverlib/mpu.c | 4 +- bsp/tm4c129x/libraries/driverlib/mpu.h | 4 +- bsp/tm4c129x/libraries/driverlib/onewire.c | 8 +- bsp/tm4c129x/libraries/driverlib/onewire.h | 4 +- bsp/tm4c129x/libraries/driverlib/pin_map.h | 464 ++- bsp/tm4c129x/libraries/driverlib/pwm.c | 4 +- bsp/tm4c129x/libraries/driverlib/pwm.h | 4 +- bsp/tm4c129x/libraries/driverlib/qei.c | 94 +- bsp/tm4c129x/libraries/driverlib/qei.h | 30 +- bsp/tm4c129x/libraries/driverlib/readme.txt | 4 +- bsp/tm4c129x/libraries/driverlib/rom.h | 3168 ++++++++++++----- bsp/tm4c129x/libraries/driverlib/rom_map.h | 11 +- .../libraries/driverlib/rtos_bindings.h | 4 +- bsp/tm4c129x/libraries/driverlib/shamd5.c | 4 +- bsp/tm4c129x/libraries/driverlib/shamd5.h | 4 +- bsp/tm4c129x/libraries/driverlib/ssi.c | 20 +- bsp/tm4c129x/libraries/driverlib/ssi.h | 4 +- bsp/tm4c129x/libraries/driverlib/sw_crc.c | 4 +- bsp/tm4c129x/libraries/driverlib/sw_crc.h | 4 +- bsp/tm4c129x/libraries/driverlib/sysctl.c | 290 +- bsp/tm4c129x/libraries/driverlib/sysctl.h | 5 +- bsp/tm4c129x/libraries/driverlib/sysexc.c | 4 +- bsp/tm4c129x/libraries/driverlib/sysexc.h | 4 +- bsp/tm4c129x/libraries/driverlib/systick.c | 4 +- bsp/tm4c129x/libraries/driverlib/systick.h | 4 +- bsp/tm4c129x/libraries/driverlib/tiva_timer.c | 7 +- bsp/tm4c129x/libraries/driverlib/tiva_timer.h | 8 +- bsp/tm4c129x/libraries/driverlib/uart.c | 52 +- bsp/tm4c129x/libraries/driverlib/uart.h | 5 +- bsp/tm4c129x/libraries/driverlib/udma.c | 14 +- bsp/tm4c129x/libraries/driverlib/udma.h | 13 +- bsp/tm4c129x/libraries/driverlib/usb.c | 13 +- bsp/tm4c129x/libraries/driverlib/usb.h | 4 +- bsp/tm4c129x/libraries/driverlib/watchdog.c | 4 +- bsp/tm4c129x/libraries/driverlib/watchdog.h | 4 +- bsp/tm4c129x/libraries/inc/asmdefs.h | 4 +- bsp/tm4c129x/libraries/inc/hw_adc.h | 5 +- bsp/tm4c129x/libraries/inc/hw_aes.h | 4 +- bsp/tm4c129x/libraries/inc/hw_can.h | 4 +- bsp/tm4c129x/libraries/inc/hw_ccm.h | 4 +- bsp/tm4c129x/libraries/inc/hw_comp.h | 4 +- bsp/tm4c129x/libraries/inc/hw_des.h | 4 +- bsp/tm4c129x/libraries/inc/hw_eeprom.h | 4 +- bsp/tm4c129x/libraries/inc/hw_emac.h | 201 +- bsp/tm4c129x/libraries/inc/hw_epi.h | 4 +- bsp/tm4c129x/libraries/inc/hw_fan.h | 4 +- bsp/tm4c129x/libraries/inc/hw_flash.h | 4 +- bsp/tm4c129x/libraries/inc/hw_gpio.h | 4 +- bsp/tm4c129x/libraries/inc/hw_hibernate.h | 4 +- bsp/tm4c129x/libraries/inc/hw_i2c.h | 4 +- bsp/tm4c129x/libraries/inc/hw_ints.h | 6 +- bsp/tm4c129x/libraries/inc/hw_lcd.h | 4 +- bsp/tm4c129x/libraries/inc/hw_memmap.h | 4 +- bsp/tm4c129x/libraries/inc/hw_nvic.h | 4 +- bsp/tm4c129x/libraries/inc/hw_onewire.h | 223 ++ bsp/tm4c129x/libraries/inc/hw_pwm.h | 4 +- bsp/tm4c129x/libraries/inc/hw_qei.h | 4 +- bsp/tm4c129x/libraries/inc/hw_shamd5.h | 4 +- bsp/tm4c129x/libraries/inc/hw_ssi.h | 5 +- bsp/tm4c129x/libraries/inc/hw_sysctl.h | 57 +- bsp/tm4c129x/libraries/inc/hw_sysexc.h | 4 +- bsp/tm4c129x/libraries/inc/hw_timer.h | 4 +- bsp/tm4c129x/libraries/inc/hw_types.h | 4 +- bsp/tm4c129x/libraries/inc/hw_uart.h | 4 +- bsp/tm4c129x/libraries/inc/hw_udma.h | 4 +- bsp/tm4c129x/libraries/inc/hw_usb.h | 4 +- bsp/tm4c129x/libraries/inc/hw_watchdog.h | 4 +- bsp/tm4c129x/libraries/inc/tm4c1294ncpdt.h | 6 +- .../libraries/startup/startup_ewarm.c | 6 +- bsp/tm4c129x/libraries/startup/startup_gcc.c | 8 +- .../libraries/startup/startup_rvmdk.S | 6 +- bsp/tm4c129x/rtconfig.py | 2 +- bsp/tm4c129x/tm4c_rom.icf | 5 +- bsp/tm4c129x/tm4c_rom.ld | 125 +- bsp/tm4c129x/tm4c_rom.sct | 59 +- 111 files changed, 4654 insertions(+), 1853 deletions(-) create mode 100644 bsp/tm4c129x/libraries/inc/hw_onewire.h diff --git a/bsp/tm4c129x/applications/board.h b/bsp/tm4c129x/applications/board.h index 9423c80edf..31682d762c 100644 --- a/bsp/tm4c129x/applications/board.h +++ b/bsp/tm4c129x/applications/board.h @@ -35,14 +35,14 @@ extern uint32_t SysClock; // #ifdef __CC_ARM -extern int Image$$RW_IRAM1$$ZI$$Limit; -#define HEAP_BEGIN ((void *)&Image$$RW_IRAM1$$ZI$$Limit) +extern int Image$$RW_IRAM$$ZI$$Limit; +#define HEAP_BEGIN ((void *)&Image$$RW_IRAM$$ZI$$Limit) #elif __ICCARM__ #pragma section="HEAP" #define HEAP_BEGIN (__segment_end("HEAP")) #else -extern int __bss_end; -#define HEAP_BEGIN ((void *)&__bss_end) +extern int _ebss; +#define HEAP_BEGIN ((void *)&_ebss) #endif #define HEAP_END (0x20000000 + 256*1024) diff --git a/bsp/tm4c129x/libraries/driverlib/adc.c b/bsp/tm4c129x/libraries/driverlib/adc.c index ac2000e0ba..81e7dc05fc 100644 --- a/bsp/tm4c129x/libraries/driverlib/adc.c +++ b/bsp/tm4c129x/libraries/driverlib/adc.c @@ -2,7 +2,7 @@ // // adc.c - Driver for the ADC. // -// Copyright (c) 2005-2014 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Redistribution and use in source and binary forms, with or without @@ -33,7 +33,7 @@ // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library. +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. // //***************************************************************************** @@ -78,7 +78,7 @@ // sequencers. // //***************************************************************************** -static uint8_t g_pui8OversampleFactor[3]; +static uint8_t g_pui8OversampleFactor[2][3]; //***************************************************************************** // @@ -107,7 +107,7 @@ _ADCIntNumberGet(uint32_t ui32Base, uint32_t ui32SequenceNum) { ui8Int = ((ui32Base == ADC0_BASE) ? (INT_ADC0SS0_TM4C123 + ui32SequenceNum) : - (INT_ADC0SS0_TM4C123 + ui32SequenceNum)); + (INT_ADC1SS0_TM4C123 + ui32SequenceNum)); } else if(CLASS_IS_TM4C129) { @@ -502,6 +502,8 @@ void ADCSequenceConfigure(uint32_t ui32Base, uint32_t ui32SequenceNum, uint32_t ui32Trigger, uint32_t ui32Priority) { + uint32_t ui32Gen; + // // Check the arugments. // @@ -545,11 +547,18 @@ ADCSequenceConfigure(uint32_t ui32Base, uint32_t ui32SequenceNum, // // Set the source PWM module for this sequence's PWM triggers. // - ui32SequenceNum *= 2; - HWREG(ui32Base + ADC_O_TSSEL) = ((HWREG(ui32Base + ADC_O_TSSEL) & - ~(0x30 << ui32SequenceNum)) | - ((ui32Trigger & 0x30) << - ui32SequenceNum)); + ui32Gen = ui32Trigger & 0x0f; + if(ui32Gen >= ADC_TRIGGER_PWM0 && ui32Gen <= ADC_TRIGGER_PWM3) + { + // + // Set the shift for the module and generator + // + ui32Gen = (ui32Gen - ADC_TRIGGER_PWM0) * 8; + + HWREG(ui32Base + ADC_O_TSSEL) = ((HWREG(ui32Base + ADC_O_TSSEL) & + ~(0x30 << ui32Gen)) | + ((ui32Trigger & 0x30) << ui32Gen)); + } } //***************************************************************************** @@ -924,6 +933,7 @@ ADCSoftwareOversampleConfigure(uint32_t ui32Base, uint32_t ui32SequenceNum, uint32_t ui32Factor) { uint32_t ui32Value; + uint32_t ui32ADCInst; // // Check the arguments. @@ -941,10 +951,22 @@ ADCSoftwareOversampleConfigure(uint32_t ui32Base, uint32_t ui32SequenceNum, { } + // + // Evaluate the ADC Instance. + // + if(ui32Base == ADC0_BASE) + { + ui32ADCInst = 0; + } + else + { + ui32ADCInst = 1; + } + // // Save the shift factor. // - g_pui8OversampleFactor[ui32SequenceNum] = ui32Value; + g_pui8OversampleFactor[ui32ADCInst][ui32SequenceNum] = ui32Value; } //***************************************************************************** @@ -968,14 +990,30 @@ void ADCSoftwareOversampleStepConfigure(uint32_t ui32Base, uint32_t ui32SequenceNum, uint32_t ui32Step, uint32_t ui32Config) { + uint32_t ui32ADCInst; + + // + // Evaluate the ADC Instance. + // + if(ui32Base == ADC0_BASE) + { + ui32ADCInst = 0; + } + else + { + ui32ADCInst = 1; + } + // // Check the arguments. // ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE)); ASSERT(ui32SequenceNum < 3); ASSERT(((ui32SequenceNum == 0) && - (ui32Step < (8 >> g_pui8OversampleFactor[ui32SequenceNum]))) || - (ui32Step < (4 >> g_pui8OversampleFactor[ui32SequenceNum]))); + (ui32Step < + (8 >> g_pui8OversampleFactor[ui32ADCInst][ui32SequenceNum]))) || + (ui32Step < + (4 >> g_pui8OversampleFactor[ui32ADCInst][ui32SequenceNum]))); // // Get the offset of the sequence to be configured. @@ -985,13 +1023,14 @@ ADCSoftwareOversampleStepConfigure(uint32_t ui32Base, uint32_t ui32SequenceNum, // // Compute the shift for the bits that control this step. // - ui32Step *= 4 << g_pui8OversampleFactor[ui32SequenceNum]; + ui32Step *= 4 << g_pui8OversampleFactor[ui32ADCInst][ui32SequenceNum]; // // Loop through the hardware steps that make up this step of the software // oversampled sequence. // - for(ui32SequenceNum = 1 << g_pui8OversampleFactor[ui32SequenceNum]; + for(ui32SequenceNum = + (1 << g_pui8OversampleFactor[ui32ADCInst][ui32SequenceNum]); ui32SequenceNum; ui32SequenceNum--) { // @@ -1054,6 +1093,20 @@ ADCSoftwareOversampleDataGet(uint32_t ui32Base, uint32_t ui32SequenceNum, uint32_t *pui32Buffer, uint32_t ui32Count) { uint32_t ui32Idx, ui32Accum; + uint32_t ui32ADCInst; + + // + // Evaluate the ADC Instance. + // + if(ui32Base == ADC0_BASE) + { + ui32ADCInst = 0; + } + else + { + ui32ADCInst = 1; + } + // // Check the arguments. @@ -1061,8 +1114,10 @@ ADCSoftwareOversampleDataGet(uint32_t ui32Base, uint32_t ui32SequenceNum, ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE)); ASSERT(ui32SequenceNum < 3); ASSERT(((ui32SequenceNum == 0) && - (ui32Count < (8 >> g_pui8OversampleFactor[ui32SequenceNum]))) || - (ui32Count < (4 >> g_pui8OversampleFactor[ui32SequenceNum]))); + (ui32Count < + (8 >> g_pui8OversampleFactor[ui32ADCInst][ui32SequenceNum]))) || + (ui32Count < + (4 >> g_pui8OversampleFactor[ui32ADCInst][ui32SequenceNum]))); // // Get the offset of the sequence to be read. @@ -1078,8 +1133,8 @@ ADCSoftwareOversampleDataGet(uint32_t ui32Base, uint32_t ui32SequenceNum, // Compute the sum of the samples. // ui32Accum = 0; - for(ui32Idx = 1 << g_pui8OversampleFactor[ui32SequenceNum]; ui32Idx; - ui32Idx--) + for(ui32Idx = 1 << g_pui8OversampleFactor[ui32ADCInst][ui32SequenceNum]; + ui32Idx; ui32Idx--) { // // Read the FIFO and add it to the accumulator. @@ -1090,7 +1145,8 @@ ADCSoftwareOversampleDataGet(uint32_t ui32Base, uint32_t ui32SequenceNum, // // Write the averaged sample to the output buffer. // - *pui32Buffer++ = ui32Accum >> g_pui8OversampleFactor[ui32SequenceNum]; + *pui32Buffer++ = + ui32Accum >> g_pui8OversampleFactor[ui32ADCInst][ui32SequenceNum]; } } @@ -1605,7 +1661,12 @@ ADCIntStatusEx(uint32_t ui32Base, bool bMasked) void ADCIntClearEx(uint32_t ui32Base, uint32_t ui32IntFlags) { - HWREG(ui32Base + ADC_O_ISC) |= ui32IntFlags; + // + // Note: The interrupt bits are "W1C" so we DO NOT use a logical OR + // here to clear the requested bits. Doing so would clear all outstanding + // interrupts rather than just those which the caller has specified. + // + HWREG(ui32Base + ADC_O_ISC) = ui32IntFlags; } //***************************************************************************** @@ -1616,12 +1677,10 @@ ADCIntClearEx(uint32_t ui32Base, uint32_t ui32IntFlags) //! \param ui32Ref is the reference to use. //! //! The ADC reference is set as specified by \e ui32Ref. It must be one of -//! \b ADC_REF_INT, \b ADC_REF_EXT_3V, or \b ADC_REF_EXT_1V for internal or -//! external reference. If \b ADC_REF_INT is chosen, then an internal 3V -//! reference is used and no external reference is needed. If -//! \b ADC_REF_EXT_3V is chosen, then a 3V reference must be supplied to the -//! AVREF pin. If \b ADC_REF_EXT_1V is chosen, then a 1V external reference -//! must be supplied to the AVREF pin. +//! \b ADC_REF_INT, or \b ADC_REF_EXT_3V for internal or external reference +//! If \b ADC_REF_INT is chosen, then an internal 3V reference is used and +//! no external reference is needed. If \b ADC_REF_EXT_3V is chosen, then +//! a 3V reference must be supplied to the AVREF pin. //! //! \note The ADC reference can only be selected on parts that have an external //! reference. Consult the data sheet for your part to determine if there is @@ -1637,8 +1696,7 @@ ADCReferenceSet(uint32_t ui32Base, uint32_t ui32Ref) // Check the arguments. // ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE)); - ASSERT((ui32Ref == ADC_REF_INT) || (ui32Ref == ADC_REF_EXT_3V) || - (ui32Ref == ADC_REF_EXT_1V)); + ASSERT((ui32Ref == ADC_REF_INT) || (ui32Ref == ADC_REF_EXT_3V)); // // Set the reference. @@ -1654,7 +1712,7 @@ ADCReferenceSet(uint32_t ui32Base, uint32_t ui32Ref) //! \param ui32Base is the base address of the ADC module. //! //! Returns the value of the ADC reference setting. The returned value is one -//! of \b ADC_REF_INT, \b ADC_REF_EXT_3V, or \b ADC_REF_EXT_1V. +//! of \b ADC_REF_INT, or \b ADC_REF_EXT_3V. //! //! \note The value returned by this function is only meaningful if used on a //! part that is capable of using an external reference. Consult the data @@ -1919,18 +1977,14 @@ ADCClockConfigSet(uint32_t ui32Base, uint32_t ui32Config, // // Check the argument. // - ASSERT(ui32Base == ADC0_BASE); + ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE)); + ASSERT((ui32ClockDiv - 1) <= (ADC_CC_CLKDIV_M >> ADC_CC_CLKDIV_S)); // // A rate must be supplied. // ASSERT((ui32Config & ADC_CLOCK_RATE_FULL) != 0); - // - // Clock must be valid divider. - // - ASSERT(((ui32ClockDiv - 1) & ~ADC_CC_CLKDIV_M) == 0); - // // Write the sample conversion rate. // @@ -1982,7 +2036,7 @@ ADCClockConfigGet(uint32_t ui32Base, uint32_t *pui32ClockDiv) // // Check the argument. // - ASSERT(ui32Base == ADC0_BASE); + ASSERT((ui32Base == ADC0_BASE) || (ui32Base == ADC1_BASE)); // // Read the current configuration. @@ -2006,7 +2060,7 @@ ADCClockConfigGet(uint32_t ui32Base, uint32_t *pui32ClockDiv) // // Add in the sample interval to the configuration. // - ui32Config = (HWREG(ui32Base + ADC_O_PC) & ADC_PC_SR_M) << 4; + ui32Config |= (HWREG(ui32Base + ADC_O_PC) & ADC_PC_SR_M) << 4; return(ui32Config); } diff --git a/bsp/tm4c129x/libraries/driverlib/adc.h b/bsp/tm4c129x/libraries/driverlib/adc.h index a0e00e64b6..993b6a3fb5 100644 --- a/bsp/tm4c129x/libraries/driverlib/adc.h +++ b/bsp/tm4c129x/libraries/driverlib/adc.h @@ -2,7 +2,7 @@ // // adc.h - ADC headers for using the ADC driver functions. // -// Copyright (c) 2005-2014 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Redistribution and use in source and binary forms, with or without @@ -33,7 +33,7 @@ // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library. +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. // //***************************************************************************** @@ -206,7 +206,6 @@ extern "C" //***************************************************************************** #define ADC_REF_INT 0x00000000 // Internal reference #define ADC_REF_EXT_3V 0x00000001 // External 3V reference -#define ADC_REF_EXT_1V 0x00000003 // External 1V reference //***************************************************************************** // diff --git a/bsp/tm4c129x/libraries/driverlib/aes.c b/bsp/tm4c129x/libraries/driverlib/aes.c index f1d40d2b07..06cf55bb0b 100644 --- a/bsp/tm4c129x/libraries/driverlib/aes.c +++ b/bsp/tm4c129x/libraries/driverlib/aes.c @@ -2,7 +2,7 @@ // // aes.c - Driver for the AES module. // -// Copyright (c) 2012-2014 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2012-2017 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Redistribution and use in source and binary forms, with or without @@ -33,7 +33,7 @@ // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library. +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. // //***************************************************************************** diff --git a/bsp/tm4c129x/libraries/driverlib/aes.h b/bsp/tm4c129x/libraries/driverlib/aes.h index 0b8919f13e..6cf44780dd 100644 --- a/bsp/tm4c129x/libraries/driverlib/aes.h +++ b/bsp/tm4c129x/libraries/driverlib/aes.h @@ -2,7 +2,7 @@ // // aes.h - Defines and Macros for the AES module. // -// Copyright (c) 2012-2014 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2012-2017 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Redistribution and use in source and binary forms, with or without @@ -33,7 +33,7 @@ // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library. +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. // //***************************************************************************** diff --git a/bsp/tm4c129x/libraries/driverlib/can.c b/bsp/tm4c129x/libraries/driverlib/can.c index 173c216402..d53584585c 100644 --- a/bsp/tm4c129x/libraries/driverlib/can.c +++ b/bsp/tm4c129x/libraries/driverlib/can.c @@ -2,7 +2,7 @@ // // can.c - Driver for the CAN module. // -// Copyright (c) 2006-2014 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2006-2017 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Redistribution and use in source and binary forms, with or without @@ -33,7 +33,7 @@ // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library. +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. // //***************************************************************************** diff --git a/bsp/tm4c129x/libraries/driverlib/can.h b/bsp/tm4c129x/libraries/driverlib/can.h index b89cd7e57a..199721906b 100644 --- a/bsp/tm4c129x/libraries/driverlib/can.h +++ b/bsp/tm4c129x/libraries/driverlib/can.h @@ -2,7 +2,7 @@ // // can.h - Defines and Macros for the CAN controller. // -// Copyright (c) 2006-2014 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2006-2017 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Redistribution and use in source and binary forms, with or without @@ -33,7 +33,7 @@ // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library. +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. // //***************************************************************************** diff --git a/bsp/tm4c129x/libraries/driverlib/comp.c b/bsp/tm4c129x/libraries/driverlib/comp.c index c57dfa605c..6f03b7c01a 100644 --- a/bsp/tm4c129x/libraries/driverlib/comp.c +++ b/bsp/tm4c129x/libraries/driverlib/comp.c @@ -2,7 +2,7 @@ // // comp.c - Driver for the analog comparator. // -// Copyright (c) 2005-2014 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Redistribution and use in source and binary forms, with or without @@ -33,7 +33,7 @@ // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library. +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. // //***************************************************************************** diff --git a/bsp/tm4c129x/libraries/driverlib/comp.h b/bsp/tm4c129x/libraries/driverlib/comp.h index 538d0c2556..2f95df09c9 100644 --- a/bsp/tm4c129x/libraries/driverlib/comp.h +++ b/bsp/tm4c129x/libraries/driverlib/comp.h @@ -2,7 +2,7 @@ // // comp.h - Prototypes for the analog comparator driver. // -// Copyright (c) 2005-2014 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Redistribution and use in source and binary forms, with or without @@ -33,7 +33,7 @@ // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library. +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. // //***************************************************************************** diff --git a/bsp/tm4c129x/libraries/driverlib/cpu.c b/bsp/tm4c129x/libraries/driverlib/cpu.c index ab7efbe7ae..0cddffc340 100644 --- a/bsp/tm4c129x/libraries/driverlib/cpu.c +++ b/bsp/tm4c129x/libraries/driverlib/cpu.c @@ -3,7 +3,7 @@ // cpu.c - Instruction wrappers for special CPU instructions needed by the // drivers. // -// Copyright (c) 2006-2014 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2006-2017 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Redistribution and use in source and binary forms, with or without @@ -34,7 +34,7 @@ // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library. +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. // //***************************************************************************** diff --git a/bsp/tm4c129x/libraries/driverlib/cpu.h b/bsp/tm4c129x/libraries/driverlib/cpu.h index d87b81f612..11a07e88d0 100644 --- a/bsp/tm4c129x/libraries/driverlib/cpu.h +++ b/bsp/tm4c129x/libraries/driverlib/cpu.h @@ -2,7 +2,7 @@ // // cpu.h - Prototypes for the CPU instruction wrapper functions. // -// Copyright (c) 2006-2014 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2006-2017 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Redistribution and use in source and binary forms, with or without @@ -33,7 +33,7 @@ // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library. +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. // //***************************************************************************** diff --git a/bsp/tm4c129x/libraries/driverlib/crc.c b/bsp/tm4c129x/libraries/driverlib/crc.c index 0d7d2538ce..55bd4d6048 100644 --- a/bsp/tm4c129x/libraries/driverlib/crc.c +++ b/bsp/tm4c129x/libraries/driverlib/crc.c @@ -2,7 +2,7 @@ // // crc.c - Driver for the CRC module. // -// Copyright (c) 2012-2014 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2012-2017 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Redistribution and use in source and binary forms, with or without @@ -33,7 +33,7 @@ // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library. +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. // //***************************************************************************** diff --git a/bsp/tm4c129x/libraries/driverlib/crc.h b/bsp/tm4c129x/libraries/driverlib/crc.h index b6fc1f49fd..7d33e84cb6 100644 --- a/bsp/tm4c129x/libraries/driverlib/crc.h +++ b/bsp/tm4c129x/libraries/driverlib/crc.h @@ -2,7 +2,7 @@ // // crc.h - Defines and Macros for CRC module. // -// Copyright (c) 2012-2014 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2012-2017 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Redistribution and use in source and binary forms, with or without @@ -33,7 +33,7 @@ // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library. +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. // //***************************************************************************** @@ -65,7 +65,7 @@ extern "C" #define CRC_CFG_RESINV 0x00000200 // Result Inverse Enable #define CRC_CFG_OBR 0x00000100 // Output Reverse Enable #define CRC_CFG_IBR 0x00000080 // Bit reverse enable -#define CRC_CFG_ENDIAN_SBHW 0x00000000 // Swap byte in half-word +#define CRC_CFG_ENDIAN_SBHW 0x00000020 // Swap byte in half-word #define CRC_CFG_ENDIAN_SHW 0x00000010 // Swap half-word #define CRC_CFG_TYPE_P8005 0x00000000 // Polynomial 0x8005 #define CRC_CFG_TYPE_P1021 0x00000001 // Polynomial 0x1021 diff --git a/bsp/tm4c129x/libraries/driverlib/debug.h b/bsp/tm4c129x/libraries/driverlib/debug.h index 266df8d43e..fd2e3afba1 100644 --- a/bsp/tm4c129x/libraries/driverlib/debug.h +++ b/bsp/tm4c129x/libraries/driverlib/debug.h @@ -2,7 +2,7 @@ // // debug.h - Macros for assisting debug of the driver library. // -// Copyright (c) 2006-2014 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2006-2017 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Redistribution and use in source and binary forms, with or without @@ -33,7 +33,7 @@ // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library. +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. // //***************************************************************************** diff --git a/bsp/tm4c129x/libraries/driverlib/des.c b/bsp/tm4c129x/libraries/driverlib/des.c index 1e487b507b..1b6e86a2a8 100644 --- a/bsp/tm4c129x/libraries/driverlib/des.c +++ b/bsp/tm4c129x/libraries/driverlib/des.c @@ -2,7 +2,7 @@ // // des.c - Driver for the DES data transformation. // -// Copyright (c) 2012-2014 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2012-2017 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Redistribution and use in source and binary forms, with or without @@ -33,7 +33,7 @@ // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library. +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. // //***************************************************************************** diff --git a/bsp/tm4c129x/libraries/driverlib/des.h b/bsp/tm4c129x/libraries/driverlib/des.h index 5d1d229505..9f6c8d1853 100644 --- a/bsp/tm4c129x/libraries/driverlib/des.h +++ b/bsp/tm4c129x/libraries/driverlib/des.h @@ -2,7 +2,7 @@ // // des.h - Defines and Macros for the DES module. // -// Copyright (c) 2012-2014 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2012-2017 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Redistribution and use in source and binary forms, with or without @@ -33,7 +33,7 @@ // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library. +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. // //***************************************************************************** diff --git a/bsp/tm4c129x/libraries/driverlib/eeprom.c b/bsp/tm4c129x/libraries/driverlib/eeprom.c index bb0a99d683..6daae87be0 100644 --- a/bsp/tm4c129x/libraries/driverlib/eeprom.c +++ b/bsp/tm4c129x/libraries/driverlib/eeprom.c @@ -2,7 +2,7 @@ // // eeprom.c - Driver for programming the on-chip EEPROM. // -// Copyright (c) 2010-2014 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2010-2017 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Redistribution and use in source and binary forms, with or without @@ -33,7 +33,7 @@ // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library. +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. // //***************************************************************************** diff --git a/bsp/tm4c129x/libraries/driverlib/eeprom.h b/bsp/tm4c129x/libraries/driverlib/eeprom.h index 3ad36d3333..0336010e06 100644 --- a/bsp/tm4c129x/libraries/driverlib/eeprom.h +++ b/bsp/tm4c129x/libraries/driverlib/eeprom.h @@ -2,7 +2,7 @@ // // eeprom.h - Prototypes for the EEPROM driver. // -// Copyright (c) 2010-2014 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2010-2017 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Redistribution and use in source and binary forms, with or without @@ -33,7 +33,7 @@ // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library. +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. // //***************************************************************************** diff --git a/bsp/tm4c129x/libraries/driverlib/emac.c b/bsp/tm4c129x/libraries/driverlib/emac.c index a9e5d14a65..8c238d299e 100644 --- a/bsp/tm4c129x/libraries/driverlib/emac.c +++ b/bsp/tm4c129x/libraries/driverlib/emac.c @@ -3,7 +3,7 @@ // emac.c - Driver for the Integrated Ethernet Controller on Snowflake-class // Tiva devices. // -// Copyright (c) 2013-2014 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2013-2017 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Redistribution and use in source and binary forms, with or without @@ -34,7 +34,7 @@ // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library. +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. // //***************************************************************************** @@ -161,7 +161,8 @@ // masked (or enabled) via the DMAIM register. // //***************************************************************************** -#define EMAC_NON_MASKED_INTS (EMAC_DMARIS_TT | \ +#define EMAC_NON_MASKED_INTS (EMAC_DMARIS_LPI | \ + EMAC_DMARIS_TT | \ EMAC_DMARIS_PMT | \ EMAC_DMARIS_MMC) @@ -207,6 +208,14 @@ g_pi16MIIClockDiv[] = #define NUM_CLOCK_DIVISORS (sizeof(g_pi16MIIClockDiv) / \ sizeof(g_pi16MIIClockDiv[0])) +//***************************************************************************** +// +// The define for accessing PHY registers in the MMD address space. +// +//***************************************************************************** +#define DEV_ADDR(x) ((x & 0xF000) >> 12) +#define REG_ADDR(x) ((x & 0x0FFF)) + //***************************************************************************** // //! Initializes the Ethernet MAC and sets bus-related DMA parameters. @@ -2917,7 +2926,6 @@ EMACPHYRead(uint32_t ui32Base, uint8_t ui8PhyAddr, uint8_t ui8RegAddr) // HWREG(ui32Base + EMAC_O_MIIADDR) = ((HWREG(ui32Base + EMAC_O_MIIADDR) & EMAC_MIIADDR_CR_M) | - EMAC_MIIADDR_CR_100_150 | (ui8RegAddr << EMAC_MIIADDR_MII_S) | (ui8PhyAddr << EMAC_MIIADDR_PLA_S) | EMAC_MIIADDR_MIIB); @@ -4682,6 +4690,291 @@ EMACPowerManagementStatusGet(uint32_t ui32Base) EMAC_PMTCTLSTAT_PWRDWN)); } +//***************************************************************************** +// +//! Enables the wake-on-LAN feature of the MAC controller. +//! +//! \param ui32Base is the base address of the controller. +//! +//! This function is used to enable the wake-on-LAN feature of the MAC +//! controller. It is done by first checking if the transmit path is idle and +//! disabling the trasnmitter and the transmit DMA controller. Then it checks +//! if any data from the network is being actively received and if not then it +//! disables the receive DMA controller. +//! +//! \return None. +// +//***************************************************************************** +void +EMACWoLEnter(uint32_t ui32Base) +{ + // + // Parameter sanity check. + // + ASSERT(ui32Base == EMAC0_BASE); + + // + // Check if the Transmit interrupt bit is clear. + // + while(HWREG(ui32Base + EMAC_O_DMARIS) == EMAC_DMARIS_TI) + { + } + + // + // Disable transmission in the MAC configuration register. + // + HWREG(ui32Base + EMAC_O_CFG) &= ~EMAC_CFG_TE; + + // + // Disable the MAC transmit path in the opmode register. + // + HWREG(ui32Base + EMAC_O_DMAOPMODE) &= ~EMAC_DMAOPMODE_ST; + + // + // Check if the Receive FIFO is empty. + // + while((HWREG(ui32Base + EMAC_O_STATUS) & EMAC_STATUS_RX_FIFO_LEVEL_MASK) == + EMAC_STATUS_RX_FIFO_EMPTY) + { + } + + // + // Disable the MAC receive path. + // + HWREG(ui32Base + EMAC_O_DMAOPMODE) &= ~EMAC_DMAOPMODE_SR; +} + +//***************************************************************************** +// +//! Configures the LPI timers and control register. +//! +//! \param ui32Base is the base address of the controller. +//! \param bLPIConfig is state of LPI trasnmit automate bit. +//! \param ui16LPILSTimer is the value of LS timer in milli-seconds. +//! \param ui16LPITWTimer is the value of TW timer in micro-seconds. +//! +//! This function is used to configure the LPI timer and control registers when +//! the link is established as EEE mode or when the link is lost. When the link +//! is established as EEE, then \e ui16LPILSTimer is programmed as the link +//! status timer value and \e ui16LPITWTimer is programmed as the transmit wait +//! timer value. The parameter \e bLPIConfig is used to decide if the transmit +//! path must be automated or should be under user control. +//! +//! \return None. +// +//***************************************************************************** +void +EMACLPIConfig(uint32_t ui32Base, bool bLPIConfig, uint16_t ui16LPILSTimer, + uint16_t ui16LPITWTimer) +{ + uint32_t ui32TimerValue; + + // + // Parameter sanity check. + // + ASSERT(ui32Base == EMAC0_BASE); + + ui32TimerValue = ((ui16LPILSTimer << EMAC_LPITIMERCTL_LST_S) & + EMAC_LPITIMERCTL_LST_M); + ui32TimerValue |= ui16LPITWTimer & EMAC_LPITIMERCTL_TWT_M; + + // + // Update the LPI Timer. + // + HWREG(ui32Base + EMAC_O_LPITIMERCTL) = ui32TimerValue; + + // + // Configure the LPI Control registers. + // + if(bLPIConfig) + { + HWREG(ui32Base + EMAC_O_LPICTLSTAT) |= EMAC_LPICTLSTAT_LPITXA; + } + else + { + HWREG(ui32Base + EMAC_O_LPICTLSTAT) = 0x0; + } +} + +//***************************************************************************** +// +//! Enables the transmit path for LPI mode entry. +//! +//! \param ui32Base is the base address of the controller. +//! +//! This function is used to enable the transmit path in LPI mode when there +//! is no more data to be transmitted by the MAC controller. +//! +//! \return None. +// +//***************************************************************************** +void +EMACLPIEnter(uint32_t ui32Base) +{ + // + // Parameter sanity check. + // + ASSERT(ui32Base == EMAC0_BASE); + + HWREG(ui32Base + EMAC_O_LPICTLSTAT) |= EMAC_LPICTLSTAT_LPIEN; +} + +//***************************************************************************** +// +//! Returns the status of the LPI link. +//! +//! \param ui32Base is the base address of the controller. +//! +//! This function may be used to read the status of the transmit and receive +//! path when the link is configured in LPI mode. +//! +//! \return Returns the lower 16 bits of the LPI Control and Status register. +// +//***************************************************************************** +uint16_t +EMACLPIStatus(uint32_t ui32Base) +{ + // + // Parameter sanity check. + // + ASSERT(ui32Base == EMAC0_BASE); + + // + // Configure the LPI Control registers. + // + return(HWREG(ui32Base + EMAC_O_LPICTLSTAT) & 0xFFFF); +} + +//***************************************************************************** +// +//! Sets the link status of the external PHY. +//! +//! \param ui32Base is the base address of the controller. +//! +//! This function is used to set the link status of the external PHY when the +//! link is established in EEE mode. +//! +//! \return None. +// +//***************************************************************************** +void +EMACLPILinkSet(uint32_t ui32Base) +{ + // + // Parameter sanity check. + // + ASSERT(ui32Base == EMAC0_BASE); + + // + // Configure the LPI Control registers. + // + HWREG(ui32Base + EMAC_O_LPICTLSTAT) |= EMAC_LPICTLSTAT_PLS; +} + +//***************************************************************************** +// +//! Clears the link status of the external PHY. +//! +//! \param ui32Base is the base address of the controller. +//! +//! This function is used to clear the link status of the external PHY when the +//! link is lost due to a disconnect or EEE mode link is not established. +//! +//! \return None. +// +//***************************************************************************** +void +EMACLPILinkClear(uint32_t ui32Base) +{ + // + // Parameter sanity check. + // + ASSERT(ui32Base == EMAC0_BASE); + + // + // Configure the LPI Control registers. + // + HWREG(ui32Base + EMAC_O_LPICTLSTAT) &= ~(EMAC_LPICTLSTAT_PLS); +} + +//***************************************************************************** +// +//! Writes a value to an extended PHY register in MMD address space. +//! +//! \param ui32Base is the base address of the controller. +//! \param ui8PhyAddr is the physical address of the PHY to access. +//! \param ui16RegAddr is the address of the PHY extended register to be +//! accessed. +//! \param ui16Value is the value to write to the register. +//! +//! When uhen connected to an external PHY supporting extended registers in MMD +//! address space, this function allows a value to be written to the MMD +//! register specified by \e ui16RegAddr. +//! +//! \return None. +// +//***************************************************************************** +void +EMACPHYMMDWrite(uint32_t ui32Base, uint8_t ui8PhyAddr, uint16_t ui16RegAddr, + uint16_t ui16Data) +{ + // + // Parameter sanity check. + // + ASSERT(ui8PhyAddr < 32); + + // + // Set the address of the register we're about to write. + // + EMACPHYWrite(ui32Base, ui8PhyAddr, EPHY_REGCTL, DEV_ADDR(ui16RegAddr)); + EMACPHYWrite(ui32Base, ui8PhyAddr, EPHY_ADDAR, REG_ADDR(ui16RegAddr)); + + // + // Write the extended register value. + // + EMACPHYWrite(ui32Base, ui8PhyAddr, EPHY_REGCTL, + (0x4000 | DEV_ADDR(ui16RegAddr))); + EMACPHYWrite(ui32Base, ui8PhyAddr, EPHY_REGCTL, ui16Data); +} + +//***************************************************************************** +// +//! Reads from an extended PHY register in MMD address space. +//! +//! \param ui32Base is the base address of the controller. +//! \param ui8PhyAddr is the physical address of the PHY to access. +//! \param ui16RegAddr is the address of the PHY extended register to be +//! accessed. +//! +//! When connected to an external PHY supporting extended registers, this +//! this function returns the contents of the MMD register specified by +//! \e ui16RegAddr. +//! +//! \return Returns the 16-bit value read from the PHY. +// +//***************************************************************************** +uint16_t +EMACPHYMMDRead(uint32_t ui32Base, uint8_t ui8PhyAddr, uint16_t ui16RegAddr) +{ + // + // Parameter sanity check. + // + ASSERT(ui8PhyAddr < 32); + + // + // Set the address of the register we're about to read. + // + EMACPHYWrite(ui32Base, ui8PhyAddr, EPHY_REGCTL, DEV_ADDR(ui16RegAddr)); + EMACPHYWrite(ui32Base, ui8PhyAddr, EPHY_ADDAR, REG_ADDR(ui16RegAddr)); + + // + // Read the extended register value. + // + EMACPHYWrite(ui32Base, ui8PhyAddr, EPHY_REGCTL, + (0x4000 | DEV_ADDR(ui16RegAddr))); + return(EMACPHYRead(ui32Base, ui8PhyAddr, EPHY_ADDAR)); +} + //***************************************************************************** // // Close the Doxygen group. diff --git a/bsp/tm4c129x/libraries/driverlib/emac.h b/bsp/tm4c129x/libraries/driverlib/emac.h index 9c76ec776c..f82919c8c0 100644 --- a/bsp/tm4c129x/libraries/driverlib/emac.h +++ b/bsp/tm4c129x/libraries/driverlib/emac.h @@ -3,7 +3,7 @@ // emac.h - Defines and Macros for the Ethernet module on Snowflake-class // devices. // -// Copyright (c) 2012-2014 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2012-2017 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Redistribution and use in source and binary forms, with or without @@ -34,7 +34,7 @@ // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library. +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. // //***************************************************************************** @@ -708,6 +708,12 @@ struct tEMACDMADescriptor #define EMAC_INT_NORMAL_INT 0x00010000 #define EMAC_INT_ABNORMAL_INT 0x00008000 +// +// This interrupt source is readable using EMACIntStatus but must +// be cleared by calling the EMACEEEStatus(). +// +#define EMAC_INT_LPI 0x40000000 + // // This interrupt source is readable using EMACIntStatus but must // be cleared by calling the EMACTimestampIntStatus(). @@ -1012,7 +1018,17 @@ extern void EMACPowerManagementControlSet(uint32_t ui32Base, uint32_t ui32Flags); extern uint32_t EMACPowerManagementControlGet(uint32_t ui32Base); extern uint32_t EMACPowerManagementStatusGet(uint32_t ui32Base); - +extern void EMACWoLEnter(uint32_t ui32Base); +extern void EMACLPIConfig(uint32_t ui32Base, bool bLPIConfig, + uint16_t ui16LPILSTimer, uint16_t ui16LPITWTimer); +extern void EMACLPIEnter(uint32_t ui32Base); +extern uint16_t EMACLPIStatus(uint32_t ui32Base); +extern void EMACLPILinkSet(uint32_t ui32Base); +extern void EMACLPILinkClear(uint32_t ui32Base); +extern void EMACPHYMMDWrite(uint32_t ui32Base, uint8_t ui8PhyAddr, + uint16_t ui16RegAddr, uint16_t ui16Data); +extern uint16_t EMACPHYMMDRead(uint32_t ui32Base, uint8_t ui8PhyAddr, + uint16_t ui16RegAddr); //***************************************************************************** // // Mark the end of the C bindings section for C++ compilers. diff --git a/bsp/tm4c129x/libraries/driverlib/epi.c b/bsp/tm4c129x/libraries/driverlib/epi.c index 2fc44eabb3..c85a02621e 100644 --- a/bsp/tm4c129x/libraries/driverlib/epi.c +++ b/bsp/tm4c129x/libraries/driverlib/epi.c @@ -2,7 +2,7 @@ // // epi.c - Driver for the EPI module. // -// Copyright (c) 2008-2014 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2008-2017 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Redistribution and use in source and binary forms, with or without @@ -33,7 +33,7 @@ // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library. +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. // //***************************************************************************** diff --git a/bsp/tm4c129x/libraries/driverlib/epi.h b/bsp/tm4c129x/libraries/driverlib/epi.h index b6ada822f5..fc26a81469 100644 --- a/bsp/tm4c129x/libraries/driverlib/epi.h +++ b/bsp/tm4c129x/libraries/driverlib/epi.h @@ -2,7 +2,7 @@ // // epi.h - Prototypes and macros for the EPI module. // -// Copyright (c) 2008-2014 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2008-2017 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Redistribution and use in source and binary forms, with or without @@ -33,7 +33,7 @@ // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library. +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. // //***************************************************************************** diff --git a/bsp/tm4c129x/libraries/driverlib/flash.c b/bsp/tm4c129x/libraries/driverlib/flash.c index d1c8554a1f..158176a766 100644 --- a/bsp/tm4c129x/libraries/driverlib/flash.c +++ b/bsp/tm4c129x/libraries/driverlib/flash.c @@ -2,7 +2,7 @@ // // flash.c - Driver for programming the on-chip flash. // -// Copyright (c) 2005-2014 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Redistribution and use in source and binary forms, with or without @@ -33,7 +33,7 @@ // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library. +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. // //***************************************************************************** @@ -581,7 +581,81 @@ FlashUserSet(uint32_t ui32User0, uint32_t ui32User1) //***************************************************************************** // -//! Saves the user registers. +//! Gets all the user registers. +//! +//! \param pui32User0 is a pointer to the location to store USER Register 0. +//! \param pui32User1 is a pointer to the location to store USER Register 1. +//! \param pui32User2 is a pointer to the location to store USER Register 2. +//! \param pui32User3 is a pointer to the location to store USER Register 3. +//! +//! This function reads the contents of user registers 0, 1, 2 and 3, and +//! stores them in the specified locations. +//! +//! \return Returns 0 on success, or -1 if a hardware error is encountered. +// +//***************************************************************************** +int32_t +FlashAllUserRegisterGet(uint32_t *pui32User0, uint32_t *pui32User1, + uint32_t *pui32User2, uint32_t *pui32User3) +{ + // + // Verify that the pointers are valid. + // + ASSERT(pui32User0 != 0); + ASSERT(pui32User1 != 0); + ASSERT(pui32User2 != 0); + ASSERT(pui32User3 != 0); + + // + // Get and store the current value of the user registers. + // + *pui32User0 = HWREG(FLASH_USERREG0); + *pui32User1 = HWREG(FLASH_USERREG1); + *pui32User2 = HWREG(FLASH_USERREG2); + *pui32User3 = HWREG(FLASH_USERREG3); + + // + // Success. + // + return(0); +} + +//***************************************************************************** +// +//! Sets the user registers 0 to 3 +//! +//! \param ui32User0 is the value to store in USER Register 0. +//! \param ui32User1 is the value to store in USER Register 1. +//! \param ui32User2 is the value to store in USER Register 2. +//! \param ui32User3 is the value to store in USER Register 3. +//! +//! This function sets the contents of the user registers 0, 1, 2 and 3 to +//! the specified values. +//! +//! \return Returns 0 on success, or -1 if a hardware error is encountered. +// +//***************************************************************************** +int32_t +FlashAllUserRegisterSet(uint32_t ui32User0, uint32_t ui32User1, + uint32_t ui32User2, uint32_t ui32User3) +{ + // + // Save the new values into the user registers. + // + HWREG(FLASH_USERREG0) = ui32User0; + HWREG(FLASH_USERREG1) = ui32User1; + HWREG(FLASH_USERREG2) = ui32User2; + HWREG(FLASH_USERREG3) = ui32User3; + + // + // Success. + // + return(0); +} + +//***************************************************************************** +// +//! Saves the user registers 0 and 1. //! //! This function makes the currently programmed user register 0 and 1 settings //! permanent. This operation is non-reversible; a chip reset or power cycle @@ -628,6 +702,58 @@ FlashUserSave(void) return(0); } +//***************************************************************************** +// +//! Saves the user registers. +//! +//! This function makes the currently programmed user register 0, 1, 2 and 3 +//! settings permanent. This operation is non-reversible; a chip reset or +//! power cycle does not change the flash protection. +//! +//! This function does not return until the protection has been saved. +//! +//! \note To ensure data integrity of the user registers, the commits should +//! not be interrupted with a power loss. +//! +//! \return Returns 0 on success, or -1 if a hardware error is encountered. +// +//***************************************************************************** +int32_t +FlashAllUserRegisterSave(void) +{ + uint32_t ui32Index; + + // + // Setting the MSB of FMA will trigger a permanent save of a USER Register. + // The 2 least signigicant bits, specify the exact User Register to save. + // The value of the least significant bits for + // USER Register 0 is 00, + // USER Register 1 is 01, + // USER Register 2 is 10 and + // USER Register 3 is 11. + // + for(ui32Index = 0; ui32Index < 4; ui32Index++) + { + // + // Tell the flash controller to commit a USER Register. + // + HWREG(FLASH_FMA) = (0x80000000 + ui32Index); + HWREG(FLASH_FMC) = FLASH_FMC_WRKEY | FLASH_FMC_COMT; + + // + // Wait until the write has completed. + // + while(HWREG(FLASH_FMC) & FLASH_FMC_COMT) + { + } + } + + // + // Success. + // + return(0); +} + //***************************************************************************** // //! Registers an interrupt handler for the flash interrupt. diff --git a/bsp/tm4c129x/libraries/driverlib/flash.h b/bsp/tm4c129x/libraries/driverlib/flash.h index e28f25862b..0d20ab1c48 100644 --- a/bsp/tm4c129x/libraries/driverlib/flash.h +++ b/bsp/tm4c129x/libraries/driverlib/flash.h @@ -2,7 +2,7 @@ // // flash.h - Prototypes for the flash driver. // -// Copyright (c) 2005-2014 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Redistribution and use in source and binary forms, with or without @@ -33,7 +33,7 @@ // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library. +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. // //***************************************************************************** @@ -93,7 +93,16 @@ extern int32_t FlashProtectSet(uint32_t ui32Address, extern int32_t FlashProtectSave(void); extern int32_t FlashUserGet(uint32_t *pui32User0, uint32_t *pui32User1); extern int32_t FlashUserSet(uint32_t ui32User0, uint32_t ui32User1); +extern int32_t FlashAllUserRegisterGet(uint32_t *pui32User0, + uint32_t *pui32User1, + uint32_t *pui32User2, + uint32_t *pui32User3); +extern int32_t FlashAllUserRegisterSet(uint32_t ui32User0, + uint32_t ui32User1, + uint32_t ui32User2, + uint32_t ui32User3); extern int32_t FlashUserSave(void); +extern int32_t FlashAllUserRegisterSave(void); extern void FlashIntRegister(void (*pfnHandler)(void)); extern void FlashIntUnregister(void); extern void FlashIntEnable(uint32_t ui32IntFlags); diff --git a/bsp/tm4c129x/libraries/driverlib/fpu.c b/bsp/tm4c129x/libraries/driverlib/fpu.c index 8ada474cb2..8e0d793da6 100644 --- a/bsp/tm4c129x/libraries/driverlib/fpu.c +++ b/bsp/tm4c129x/libraries/driverlib/fpu.c @@ -3,7 +3,7 @@ // fpu.c - Routines for manipulating the floating-point unit in the Cortex-M // processor. // -// Copyright (c) 2011-2014 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2011-2017 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Redistribution and use in source and binary forms, with or without @@ -34,7 +34,7 @@ // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library. +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. // //***************************************************************************** diff --git a/bsp/tm4c129x/libraries/driverlib/fpu.h b/bsp/tm4c129x/libraries/driverlib/fpu.h index e6010f4e7c..c96d69a734 100644 --- a/bsp/tm4c129x/libraries/driverlib/fpu.h +++ b/bsp/tm4c129x/libraries/driverlib/fpu.h @@ -2,7 +2,7 @@ // // fpu.h - Prototypes for the floatint point manipulation routines. // -// Copyright (c) 2011-2014 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2011-2017 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Redistribution and use in source and binary forms, with or without @@ -33,7 +33,7 @@ // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library. +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. // //***************************************************************************** diff --git a/bsp/tm4c129x/libraries/driverlib/gpio.c b/bsp/tm4c129x/libraries/driverlib/gpio.c index 7154939246..5e55dd7f1c 100644 --- a/bsp/tm4c129x/libraries/driverlib/gpio.c +++ b/bsp/tm4c129x/libraries/driverlib/gpio.c @@ -2,7 +2,7 @@ // // gpio.c - API for GPIO ports // -// Copyright (c) 2005-2014 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Redistribution and use in source and binary forms, with or without @@ -33,7 +33,7 @@ // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library. +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. // //***************************************************************************** @@ -116,6 +116,9 @@ static const uint32_t g_ppui32GPIOIntMapSnowflake[][2] = { GPIO_PORTN_BASE, INT_GPION_TM4C129 }, { GPIO_PORTP_BASE, INT_GPIOP0_TM4C129 }, { GPIO_PORTQ_BASE, INT_GPIOQ0_TM4C129 }, + { GPIO_PORTR_BASE, INT_GPIOR_TM4C129 }, + { GPIO_PORTS_BASE, INT_GPIOS_TM4C129 }, + { GPIO_PORTT_BASE, INT_GPIOT_TM4C129 }, }; static const uint_fast32_t g_ui32GPIOIntMapSnowflakeRows = (sizeof(g_ppui32GPIOIntMapSnowflake) / @@ -406,11 +409,14 @@ GPIOIntTypeSet(uint32_t ui32Port, uint8_t ui8Pins, // Check the arguments. // ASSERT(_GPIOBaseValid(ui32Port)); - ASSERT((ui32IntType == GPIO_FALLING_EDGE) || - (ui32IntType == GPIO_RISING_EDGE) || - (ui32IntType == GPIO_BOTH_EDGES) || - (ui32IntType == GPIO_LOW_LEVEL) || - (ui32IntType == GPIO_HIGH_LEVEL)); + ASSERT(((ui32IntType & 0xF) == GPIO_FALLING_EDGE) || + ((ui32IntType & 0xF) == GPIO_RISING_EDGE) || + ((ui32IntType & 0xF) == GPIO_BOTH_EDGES) || + ((ui32IntType & 0xF) == GPIO_LOW_LEVEL) || + ((ui32IntType & 0xF) == GPIO_HIGH_LEVEL)); + ASSERT(((ui32IntType & 0x000F0000) == 0) || + (((ui32IntType & 0x000F0000) == GPIO_DISCRETE_INT) && + ((ui32Port == GPIO_PORTP_BASE) || (ui32Port == GPIO_PORTQ_BASE)))); // // Set the pin interrupt type. @@ -981,6 +987,99 @@ GPIOIntUnregister(uint32_t ui32Port) IntUnregister(ui32Int); } +//***************************************************************************** +// +//! Registers an interrupt handler for an individual pin of a GPIO port. +//! +//! \param ui32Port is the base address of the GPIO port. +//! \param ui32Pin is the pin whose interrupt is to be registered. +//! \param pfnIntHandler is a pointer to the GPIO port interrupt handling +//! function. +//! +//! This function ensures that the interrupt handler specified by +//! \e pfnIntHandler is called when an interrupt is detected from the selected +//! pin of a GPIO port. This function also enables the corresponding GPIO pin +//! interrupt in the interrupt controller. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +GPIOIntRegisterPin(uint32_t ui32Port, uint32_t ui32Pin, + void (*pfnIntHandler)(void)) +{ + uint32_t ui32Int; + + // + // Check the arguments. + // + ASSERT((ui32Port == GPIO_PORTP_BASE) || (ui32Port == GPIO_PORTQ_BASE)); + ASSERT((ui32Pin > 0) && (ui32Pin < 8)); + ASSERT(pfnIntHandler != 0); + + // + // Get the interrupt number associated with the specified GPIO. + // + ui32Int = _GPIOIntNumberGet(ui32Port); + + // + // Register the interrupt handler. + // + IntRegister((ui32Int + ui32Pin), pfnIntHandler); + + // + // Enable the GPIO pin interrupt. + // + IntEnable(ui32Int + ui32Pin); +} + +//***************************************************************************** +// +//! Removes an interrupt handler for an individual pin of a GPIO port. +//! +//! \param ui32Port is the base address of the GPIO port. +//! \param ui32Pin is the pin whose interrupt is to be unregistered. +//! +//! This function unregisters the interrupt handler for the specified pin of a +//! GPIO port. This function also disables the corresponding GPIO pin +//! interrupt in the interrupt controller. +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +GPIOIntUnregisterPin(uint32_t ui32Port, uint32_t ui32Pin) +{ + uint32_t ui32Int; + + // + // Check the arguments. + // + ASSERT((ui32Port == GPIO_PORTP_BASE) || (ui32Port == GPIO_PORTQ_BASE)); + ASSERT((ui32Pin > 0) && (ui32Pin < 8)); + + // + // Get the interrupt number associated with the specified GPIO. + // + ui32Int = _GPIOIntNumberGet(ui32Port); + + // + // Disable the GPIO pin interrupt. + // + IntDisable(ui32Int + ui32Pin); + + // + // UnRegister the interrupt handler. + // + IntUnregister(ui32Int + ui32Pin); +} + //***************************************************************************** // //! Reads the values present of the specified pin(s). @@ -1199,6 +1298,78 @@ GPIOPinTypeComparator(uint32_t ui32Port, uint8_t ui8Pins) GPIO_PIN_TYPE_ANALOG); } +//***************************************************************************** +// +//! Configures pin(s) for use as an analog comparator output. +//! +//! \param ui32Port is the base address of the GPIO port. +//! \param ui8Pins is the bit-packed representation of the pin(s). +//! +//! The analog comparator output pins must be properly configured for the analog +//! comparator to function correctly. This function provides the proper +//! configuration for those pin(s). +//! +//! The pin(s) are specified using a bit-packed byte, where each bit that is +//! set identifies the pin to be accessed, and where bit 0 of the byte +//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. +//! +//! \return None. +// +//***************************************************************************** +void GPIOPinTypeComparatorOutput(uint32_t ui32Port, uint8_t ui8Pins) +{ + // + // Check the arguments. + // + ASSERT(_GPIOBaseValid(ui32Port)); + + // + // Make the pin(s) be inputs. + // + GPIODirModeSet(ui32Port, ui8Pins, GPIO_DIR_MODE_HW); + + // + // Set the pad(s) for standard push-pull operation. + // + GPIOPadConfigSet(ui32Port, ui8Pins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD); +} + +//***************************************************************************** +// +//! Configures pin(s) for use as an clock to be output from the device. +//! +//! \param ui32Port is the base address of the GPIO port. +//! \param ui8Pins is the bit-packed representation of the pin(s). +//! +//! The system control output pin must be properly configured for the DIVSCLK to +//! function correctly. This function provides the proper configuration for +//! those pin(s). +//! +//! The pin(s) are specified using a bit-packed byte, where each bit that is +//! set identifies the pin to be accessed, and where bit 0 of the byte +//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. +//! +//! \return None. +// +//***************************************************************************** +void GPIOPinTypeDIVSCLK(uint32_t ui32Port, uint8_t ui8Pins) +{ + // + // Check the arguments. + // + ASSERT(_GPIOBaseValid(ui32Port)); + + // + // Make the pin(s) be inputs. + // + GPIODirModeSet(ui32Port, ui8Pins, GPIO_DIR_MODE_HW); + + // + // Set the pad(s) for standard push-pull operation. + // + GPIOPadConfigSet(ui32Port, ui8Pins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD); +} + //***************************************************************************** // //! Configures pin(s) for use by the external peripheral interface. @@ -1487,6 +1658,42 @@ GPIOPinTypeGPIOOutputOD(uint32_t ui32Port, uint8_t ui8Pins) GPIODirModeSet(ui32Port, ui8Pins, GPIO_DIR_MODE_OUT); } +//***************************************************************************** +// +//! Configures pin(s) for use as an Hibernate RTC Clock. +//! +//! \param ui32Port is the base address of the GPIO port. +//! \param ui8Pins is the bit-packed representation of the pin(s). +//! +//! The hibernate output pin must be properly configured for the RTCCLK to +//! function correctly. This function provides the proper configuration for the +//! RTC Clock to be output from the device. +//! +//! The pin(s) are specified using a bit-packed byte, where each bit that is +//! set identifies the pin to be accessed, and where bit 0 of the byte +//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. +//! +//! \return None. +// +//***************************************************************************** +void GPIOPinTypeHibernateRTCCLK(uint32_t ui32Port, uint8_t ui8Pins) +{ + // + // Check the arguments. + // + ASSERT(_GPIOBaseValid(ui32Port)); + + // + // Make the pin(s) be inputs. + // + GPIODirModeSet(ui32Port, ui8Pins, GPIO_DIR_MODE_HW); + + // + // Set the pad(s) for standard push-pull operation. + // + GPIOPadConfigSet(ui32Port, ui8Pins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD); +} + //***************************************************************************** // //! Configures pin for use as SDA by the I2C peripheral. @@ -1640,24 +1847,24 @@ GPIOPinTypeLCD(uint32_t ui32Port, uint8_t ui8Pins) //***************************************************************************** // -//! Configures pin(s) for use by the LPC module. +//! Configures pin(s) for use by the 1-Wire module. //! //! \param ui32Port is the base address of the GPIO port. //! \param ui8Pins is the bit-packed representation of the pin(s). //! -//! The LPC pins must be properly configured for the LPC module to function -//! correctly. This function provides a typical configuration for those -//! pin(s); other configurations may work as well depending upon the board -//! setup (for example, using the on-chip pull-ups). +//! The 1-Wire pin must be properly configured for the 1-Wire peripheral to +//! function correctly. This function provides a typical configuration for +//! those pin(s); other configurations may work as well depending upon the +//! board setup (for example, using the on-chip pull-ups). //! //! The pin(s) are specified using a bit-packed byte, where each bit that is //! set identifies the pin to be accessed, and where bit 0 of the byte //! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. //! -//! \note This function cannot be used to turn any pin into an LPC pin; it only -//! configures an LPC pin for proper operation. Note that a GPIOPinConfigure() -//! function call is also required to properly configure a pin for the LPC -//! function. +//! \note This function cannot be used to turn any pin into a 1-Wire pin; it +//! only configures a 1-Wire pin for proper operation. Note that a +//! GPIOPinConfigure() function call is also required to properly configure a +//! pin for the 1-Wire function. //! //! \note A subset of GPIO pins on Tiva devices, notably those used by the //! JTAG/SWD interface and any pin capable of acting as an NMI input, are @@ -1671,7 +1878,7 @@ GPIOPinTypeLCD(uint32_t ui32Port, uint8_t ui8Pins) // //***************************************************************************** void -GPIOPinTypeLPC(uint32_t ui32Port, uint8_t ui8Pins) +GPIOPinTypeOneWire(uint32_t ui32Port, uint8_t ui8Pins) { // // Check the arguments. @@ -1686,107 +1893,6 @@ GPIOPinTypeLPC(uint32_t ui32Port, uint8_t ui8Pins) // // Set the pad(s) for standard push-pull operation. // - GPIOPadConfigSet(ui32Port, ui8Pins, GPIO_STRENGTH_8MA, GPIO_PIN_TYPE_STD); -} - -//***************************************************************************** -// -//! Configures a pin for receive use by the PECI module. -//! -//! \param ui32Port is the base address of the GPIO port. -//! \param ui8Pins is the bit-packed representation of the pin(s). -//! -//! The PECI receive pin must be properly configured for the PECI module to -//! function correctly. This function provides a typical configuration for -//! that pin. -//! -//! The pin is specified using a bit-packed byte, where each bit that is set -//! identifies the pin to be accessed, and where bit 0 of the byte represents -//! GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. -//! -//! \note This function cannot be used to turn any pin into a PECI receive pin; -//! it only configures a PECI receive pin for proper operation. Note that a -//! GPIOPinConfigure() function call is also required to properly configure a -//! pin for the PECI receive function. -//! -//! \note A subset of GPIO pins on Tiva devices, notably those used by the -//! JTAG/SWD interface and any pin capable of acting as an NMI input, are -//! locked against inadvertent reconfiguration. These pins must be unlocked -//! using direct register writes to the relevant GPIO_O_LOCK and GPIO_O_CR -//! registers before this function can be called. Please see the ``gpio_jtag'' -//! example application for the mechanism required and consult your part -//! datasheet for information on affected pins. -//! -//! \return None. -// -//***************************************************************************** -void -GPIOPinTypePECIRx(uint32_t ui32Port, uint8_t ui8Pins) -{ - // - // Check the arguments. - // - ASSERT(_GPIOBaseValid(ui32Port)); - - // - // Make the pin(s) be inputs. - // - GPIODirModeSet(ui32Port, ui8Pins, GPIO_DIR_MODE_IN); - - // - // Set the pad(s) for analog operation. - // - GPIOPadConfigSet(ui32Port, ui8Pins, GPIO_STRENGTH_2MA, - GPIO_PIN_TYPE_ANALOG); -} - -//***************************************************************************** -// -//! Configures a pin for transmit use by the PECI module. -//! -//! \param ui32Port is the base address of the GPIO port. -//! \param ui8Pins is the bit-packed representation of the pin(s). -//! -//! The PECI transmit pin must be properly configured for the PECI module to -//! function correctly. This function provides a typical configuration for -//! that pin. -//! -//! The pin is specified using a bit-packed byte, where each bit that is set -//! identifies the pin to be accessed, and where bit 0 of the byte represents -//! GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. -//! -//! \note This function cannot be used to turn any pin into a PECI transmit -//! pin; it only configures a PECI transmit pin for proper operation. Note -//! that a GPIOPinConfigure() function call is also required to properly -//! configure the pin for the PECI transmit function. -//! -//! \note A subset of GPIO pins on Tiva devices, notably those used by the -//! JTAG/SWD interface and any pin capable of acting as an NMI input, are -//! locked against inadvertent reconfiguration. These pins must be unlocked -//! using direct register writes to the relevant GPIO_O_LOCK and GPIO_O_CR -//! registers before this function can be called. Please see the ``gpio_jtag'' -//! example application for the mechanism required and consult your part -//! datasheet for information on affected pins. -//! -//! \return None. -// -//***************************************************************************** -void -GPIOPinTypePECITx(uint32_t ui32Port, uint8_t ui8Pins) -{ - // - // Check the arguments. - // - ASSERT(_GPIOBaseValid(ui32Port)); - - // - // Make the pin(s) be inputs. - // - GPIODirModeSet(ui32Port, ui8Pins, GPIO_DIR_MODE_HW); - - // - // Set the pad(s) for analog operation. - // GPIOPadConfigSet(ui32Port, ui8Pins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD); } @@ -1995,6 +2101,56 @@ GPIOPinTypeTimer(uint32_t ui32Port, uint8_t ui8Pins) GPIOPadConfigSet(ui32Port, ui8Pins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD); } +//***************************************************************************** +// +//! Configures pin(s) for use by the Trace peripheral. +//! +//! \param ui32Port is the base address of the GPIO port. +//! \param ui8Pins is the bit-packed representation of the pin(s). +//! +//! The Trace pins must be properly configured for the Trace peripheral to +//! function correctly. This function provides a typical configuration for +//! those pin(s). +//! +//! The pin(s) are specified using a bit-packed byte, where each bit that is +//! set identifies the pin to be accessed, and where bit 0 of the byte +//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. +//! +//! \note This function cannot be used to turn any pin into a trace pin; it +//! only configures a trace pin for proper operation. Note that a +//! GPIOPinConfigure() function call is also required to properly configure a +//! pin for the Trace function. +//! +//! \note A subset of GPIO pins on Tiva devices, notably those used by the +//! JTAG/SWD interface and any pin capable of acting as an NMI input, are +//! locked against inadvertent reconfiguration. These pins must be unlocked +//! using direct register writes to the relevant GPIO_O_LOCK and GPIO_O_CR +//! registers before this function can be called. Please see the ``gpio_jtag'' +//! example application for the mechanism required and consult your part +//! datasheet for information on affected pins. +//! +//! \return None. +// +//***************************************************************************** +void +GPIOPinTypeTrace(uint32_t ui32Port, uint8_t ui8Pins) +{ + // + // Check the arguments. + // + ASSERT(_GPIOBaseValid(ui32Port)); + + // + // Make the pin(s) be peripheral controlled. + // + GPIODirModeSet(ui32Port, ui8Pins, GPIO_DIR_MODE_HW); + + // + // Set the pad(s) for standard push-pull operation. + // + GPIOPadConfigSet(ui32Port, ui8Pins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD); +} + //***************************************************************************** // //! Configures pin(s) for use by the UART peripheral. @@ -2244,211 +2400,6 @@ GPIOPinTypeWakeLow(uint32_t ui32Port, uint8_t ui8Pins) GPIO_PIN_TYPE_WAKE_LOW); } -//***************************************************************************** -// -//! Configures pin(s) for use as scan matrix keyboard rows (outputs). -//! -//! \param ui32Port is the base address of the GPIO port. -//! \param ui8Pins is the bit-packed representation of the pin(s). -//! -//! The GPIO pins must be properly configured in order to function correctly as -//! scan matrix keyboard outputs. This function provides the proper -//! configuration for those pin(s). -//! -//! The pin(s) are specified using a bit-packed byte, where each bit that is -//! set identifies the pin to be accessed, and where bit 0 of the byte -//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. -//! -//! \note This function cannot be used to turn any pin into a scan matrix -//! keyboard row pin; it only configures a scan matrix keyboard row pin for -//! proper operation. Note that a GPIOPinConfigure() function call is also -//! required to properly configure a pin for the scan matrix keyboard -//! function. -//! -//! \note A subset of GPIO pins on Tiva devices, notably those used by the -//! JTAG/SWD interface and any pin capable of acting as an NMI input, are -//! locked against inadvertent reconfiguration. These pins must be unlocked -//! using direct register writes to the relevant GPIO_O_LOCK and GPIO_O_CR -//! registers before this function can be called. Please see the ``gpio_jtag'' -//! example application for the mechanism required and consult your part -//! datasheet for information on affected pins. -//! -//! \return None. -// -//***************************************************************************** -void -GPIOPinTypeKBRow(uint32_t ui32Port, uint8_t ui8Pins) -{ - // - // Check the arguments. - // - ASSERT(_GPIOBaseValid(ui32Port)); - - // - // Make the pin(s) be peripheral controlled. - // - GPIODirModeSet(ui32Port, ui8Pins, GPIO_DIR_MODE_HW); - - // - // Set the pad(s) for push/pull operation. - // - GPIOPadConfigSet(ui32Port, ui8Pins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD); -} - -//***************************************************************************** -// -//! Configures pin(s) for use as scan matrix keyboard columns (inputs). -//! -//! \param ui32Port is the base address of the GPIO port. -//! \param ui8Pins is the bit-packed representation of the pin(s). -//! -//! The GPIO pins must be properly configured in order to function correctly as -//! scan matrix keyboard inputs. This function provides the proper -//! configuration for those pin(s). -//! -//! The pin(s) are specified using a bit-packed byte, where each bit that is -//! set identifies the pin to be accessed, and where bit 0 of the byte -//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. -//! -//! \note This function cannot be used to turn any pin into a scan matrix -//! keyboard column pin; it only configures a scan matrix keyboard column pin -//! for proper operation. Note that a GPIOPinConfigure() function call is also -//! required to properly configure a pin for the scan matrix keyboard -//! function. -//! -//! \note A subset of GPIO pins on Tiva devices, notably those used by the -//! JTAG/SWD interface and any pin capable of acting as an NMI input, are -//! locked against inadvertent reconfiguration. These pins must be unlocked -//! using direct register writes to the relevant GPIO_O_LOCK and GPIO_O_CR -//! registers before this function can be called. Please see the ``gpio_jtag'' -//! example application for the mechanism required and consult your part -//! datasheet for information on affected pins. -//! -//! \return None. -// -//***************************************************************************** -void -GPIOPinTypeKBColumn(uint32_t ui32Port, uint8_t ui8Pins) -{ - // - // Check the arguments. - // - ASSERT(_GPIOBaseValid(ui32Port)); - - // - // Make the pin(s) be peripheral controlled. - // - GPIODirModeSet(ui32Port, ui8Pins, GPIO_DIR_MODE_HW); - - // - // Set the pad(s) for standard push-pull operation. - // - GPIOPadConfigSet(ui32Port, ui8Pins, GPIO_STRENGTH_2MA, - GPIO_PIN_TYPE_STD_WPU); -} - -//***************************************************************************** -// -//! Configures pin(s) for use as an LED sequencer output. -//! -//! \param ui32Port is the base address of the GPIO port. -//! \param ui8Pins is the bit-packed representation of the pin(s). -//! -//! The GPIO pins must be properly configured in order to function correctly as -//! LED sequencers. This function provides the proper configuration for those -//! pin(s). -//! -//! The pin(s) are specified using a bit-packed byte, where each bit that is -//! set identifies the pin to be accessed, and where bit 0 of the byte -//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. -//! -//! \note This function cannot be used to turn any pin into an LED sequencer -//! output pin; it only configures an LED sequencer output pin for proper -//! operation. Note that a GPIOPinConfigure() function call is also -//! required to properly configure a pin for the LED sequencer function. -//! -//! \note A subset of GPIO pins on Tiva devices, notably those used by the -//! JTAG/SWD interface and any pin capable of acting as an NMI input, are -//! locked against inadvertent reconfiguration. These pins must be unlocked -//! using direct register writes to the relevant GPIO_O_LOCK and GPIO_O_CR -//! registers before this function can be called. Please see the ``gpio_jtag'' -//! example application for the mechanism required and consult your part -//! datasheet for information on affected pins. -//! -//! \return None. -// -//***************************************************************************** -void -GPIOPinTypeLEDSeq(uint32_t ui32Port, uint8_t ui8Pins) -{ - // - // Check the arguments. - // - ASSERT(_GPIOBaseValid(ui32Port)); - - // - // Make the pin(s) be peripheral controlled. - // - GPIODirModeSet(ui32Port, ui8Pins, GPIO_DIR_MODE_HW); - - // - // Set the pad(s) for push/pull operation and 8mA strength. The external - // hardware should be set up such that we sink current when the LED is - // turned on, hence the 8mA configuration choice. - // - GPIOPadConfigSet(ui32Port, ui8Pins, GPIO_STRENGTH_8MA, GPIO_PIN_TYPE_STD); -} - -//***************************************************************************** -// -//! Configures pin(s) for use as Consumer Infrared inputs or outputs. -//! -//! \param ui32Port is the base address of the GPIO port. -//! \param ui8Pins is the bit-packed representation of the pin(s). -//! -//! The GPIO pins must be properly configured in order to function correctly as -//! Consumer Infrared pins. This function provides the proper configuration -//! for those pin(s). -//! -//! The pin(s) are specified using a bit-packed byte, where each bit that is -//! set identifies the pin to be accessed, and where bit 0 of the byte -//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. -//! -//! \note This function cannot be used to turn any pin into a CIR pin; it only -//! configures a CIR pin for proper operation. Note that a GPIOPinConfigure() -//! function call is also required to properly configure a pin for the -//! Consumer Infrared function. -//! -//! \note A subset of GPIO pins on Tiva devices, notably those used by the -//! JTAG/SWD interface and any pin capable of acting as an NMI input, are -//! locked against inadvertent reconfiguration. These pins must be unlocked -//! using direct register writes to the relevant GPIO_O_LOCK and GPIO_O_CR -//! registers before this function can be called. Please see the ``gpio_jtag'' -//! example application for the mechanism required and consult your part -//! datasheet for information on affected pins. -//! -//! \return None. -// -//***************************************************************************** -void -GPIOPinTypeCIR(uint32_t ui32Port, uint8_t ui8Pins) -{ - // - // Check the arguments. - // - ASSERT(_GPIOBaseValid(ui32Port)); - - // - // Make the pin(s) be peripheral controlled. - // - GPIODirModeSet(ui32Port, ui8Pins, GPIO_DIR_MODE_HW); - - // - // Set the pad(s) for standard push-pull operation. - // - GPIOPadConfigSet(ui32Port, ui8Pins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD); -} - //***************************************************************************** // //! Retrieves the wake pins status. @@ -2475,7 +2426,7 @@ GPIOPinTypeCIR(uint32_t ui32Port, uint8_t ui8Pins) uint32_t GPIOPinWakeStatus(uint32_t ui32Port) { - return(ui32Port + GPIO_O_WAKESTAT); + return(HWREG(ui32Port + GPIO_O_WAKESTAT)); } //***************************************************************************** @@ -2513,7 +2464,7 @@ GPIOPinConfigure(uint32_t ui32PinConfig) // // Check the argument. // - ASSERT(((ui32PinConfig >> 16) & 0xff) < 15); + ASSERT(((ui32PinConfig >> 16) & 0xff) < 18); ASSERT(((ui32PinConfig >> 8) & 0xe3) == 0); // diff --git a/bsp/tm4c129x/libraries/driverlib/gpio.h b/bsp/tm4c129x/libraries/driverlib/gpio.h index 0cbeb987c0..47b0dd71b4 100644 --- a/bsp/tm4c129x/libraries/driverlib/gpio.h +++ b/bsp/tm4c129x/libraries/driverlib/gpio.h @@ -2,7 +2,7 @@ // // gpio.h - Defines and Macros for GPIO API. // -// Copyright (c) 2005-2014 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Redistribution and use in source and binary forms, with or without @@ -33,7 +33,7 @@ // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library. +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. // //***************************************************************************** @@ -154,25 +154,33 @@ extern uint32_t GPIOIntStatus(uint32_t ui32Port, bool bMasked); extern void GPIOIntClear(uint32_t ui32Port, uint32_t ui32IntFlags); extern void GPIOIntRegister(uint32_t ui32Port, void (*pfnIntHandler)(void)); extern void GPIOIntUnregister(uint32_t ui32Port); +extern void GPIOIntRegisterPin(uint32_t ui32Port, uint32_t ui32Pin, + void (*pfnIntHandler)(void)); +extern void GPIOIntUnregisterPin(uint32_t ui32Port, uint32_t ui32Pin); extern int32_t GPIOPinRead(uint32_t ui32Port, uint8_t ui8Pins); extern void GPIOPinWrite(uint32_t ui32Port, uint8_t ui8Pins, uint8_t ui8Val); extern void GPIOPinConfigure(uint32_t ui32PinConfig); extern void GPIOPinTypeADC(uint32_t ui32Port, uint8_t ui8Pins); extern void GPIOPinTypeCAN(uint32_t ui32Port, uint8_t ui8Pins); extern void GPIOPinTypeComparator(uint32_t ui32Port, uint8_t ui8Pins); +extern void GPIOPinTypeComparatorOutput(uint32_t ui32Port, uint8_t ui8Pins); +extern void GPIOPinTypeDIVSCLK(uint32_t ui32Port, uint8_t ui8Pins); extern void GPIOPinTypeEPI(uint32_t ui32Port, uint8_t ui8Pins); extern void GPIOPinTypeEthernetLED(uint32_t ui32Port, uint8_t ui8Pins); extern void GPIOPinTypeEthernetMII(uint32_t ui32Port, uint8_t ui8Pins); extern void GPIOPinTypeGPIOInput(uint32_t ui32Port, uint8_t ui8Pins); extern void GPIOPinTypeGPIOOutput(uint32_t ui32Port, uint8_t ui8Pins); extern void GPIOPinTypeGPIOOutputOD(uint32_t ui32Port, uint8_t ui8Pins); +extern void GPIOPinTypeHibernateRTCCLK(uint32_t ui32Port, uint8_t ui8Pins); extern void GPIOPinTypeI2C(uint32_t ui32Port, uint8_t ui8Pins); extern void GPIOPinTypeI2CSCL(uint32_t ui32Port, uint8_t ui8Pins); extern void GPIOPinTypeLCD(uint32_t ui32Port, uint8_t ui8Pins); +extern void GPIOPinTypeOneWire(uint32_t ui32Port, uint8_t ui8Pins); extern void GPIOPinTypePWM(uint32_t ui32Port, uint8_t ui8Pins); extern void GPIOPinTypeQEI(uint32_t ui32Port, uint8_t ui8Pins); extern void GPIOPinTypeSSI(uint32_t ui32Port, uint8_t ui8Pins); extern void GPIOPinTypeTimer(uint32_t ui32Port, uint8_t ui8Pins); +extern void GPIOPinTypeTrace(uint32_t ui32Port, uint8_t ui8Pins); extern void GPIOPinTypeUART(uint32_t ui32Port, uint8_t ui8Pins); extern void GPIOPinTypeUSBAnalog(uint32_t ui32Port, uint8_t ui8Pins); extern void GPIOPinTypeUSBDigital(uint32_t ui32Port, uint8_t ui8Pins); diff --git a/bsp/tm4c129x/libraries/driverlib/hibernate.c b/bsp/tm4c129x/libraries/driverlib/hibernate.c index 3dd7ca2d72..a371578387 100644 --- a/bsp/tm4c129x/libraries/driverlib/hibernate.c +++ b/bsp/tm4c129x/libraries/driverlib/hibernate.c @@ -2,7 +2,7 @@ // // hibernate.c - Driver for the Hibernation module // -// Copyright (c) 2007-2014 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2007-2017 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Redistribution and use in source and binary forms, with or without @@ -33,7 +33,7 @@ // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library. +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. // //***************************************************************************** @@ -124,10 +124,12 @@ _HibernateWriteComplete(void) //! This function enables the Hibernation module for operation. This function //! should be called before any of the Hibernation module features are used. //! -//! The peripheral clock is the same as the processor clock. This value is -//! returned by SysCtlClockGet(), or it can be explicitly hard-coded if it is -//! constant and known (to save the code/execution overhead of a call to -//! SysCtlClockGet()). +//! The peripheral clock is the same as the processor clock. The frequency of +//! the system clock is the value returned by SysCtlClockGet() for TM4C123x +//! devices or the value returned by SysCtlClockFreqSet() for TM4C129x devices, +//! or it can be explicitly hard coded if it is constant and known (to save the +//! code/execution overhead of a call to SysCtlClockGet() or fetch of the +//! variable call holding the return value of SysCtlClockFreqSet()). //! //! \return None. // @@ -2067,7 +2069,7 @@ HibernateTamperIOEnable(uint32_t ui32Input, uint32_t ui32Config) // // Set tamper I/O configuration for the requested input. // - ui32Temp |= (ui32Mask | ((ui32Config | HIB_TPIO_EN0) << (ui32Input << 3))); + ui32Temp = (ui32Mask | ((ui32Config | HIB_TPIO_EN0) << (ui32Input << 3))); // // Unlock the tamper registers. diff --git a/bsp/tm4c129x/libraries/driverlib/hibernate.h b/bsp/tm4c129x/libraries/driverlib/hibernate.h index 7c3b449a75..80633b950c 100644 --- a/bsp/tm4c129x/libraries/driverlib/hibernate.h +++ b/bsp/tm4c129x/libraries/driverlib/hibernate.h @@ -2,7 +2,7 @@ // // hibernate.h - API definition for the Hibernation module. // -// Copyright (c) 2007-2014 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2007-2017 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Redistribution and use in source and binary forms, with or without @@ -33,7 +33,7 @@ // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library. +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. // //***************************************************************************** diff --git a/bsp/tm4c129x/libraries/driverlib/i2c.c b/bsp/tm4c129x/libraries/driverlib/i2c.c index 05ebede8dc..37aa1d764b 100644 --- a/bsp/tm4c129x/libraries/driverlib/i2c.c +++ b/bsp/tm4c129x/libraries/driverlib/i2c.c @@ -2,7 +2,7 @@ // // i2c.c - Driver for Inter-IC (I2C) bus block. // -// Copyright (c) 2005-2014 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Redistribution and use in source and binary forms, with or without @@ -33,7 +33,7 @@ // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library. +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. // //***************************************************************************** @@ -190,10 +190,12 @@ _I2CIntNumberGet(uint32_t ui32Base) //! initial communication with the slave is done at either 100 Kbps or //! 400 Kbps. //! -//! The peripheral clock is the same as the processor clock. This value is -//! returned by SysCtlClockGet(), or it can be explicitly hard coded if it is -//! constant and known (to save the code/execution overhead of a call to -//! SysCtlClockGet()). +//! The peripheral clock is the same as the processor clock. The frequency of +//! the system clock is the value returned by SysCtlClockGet() for TM4C123x +//! devices or the value returned by SysCtlClockFreqSet() for TM4C129x devices, +//! or it can be explicitly hard coded if it is constant and known (to save the +//! code/execution overhead of a call to SysCtlClockGet() or fetch of the +//! variable call holding the return value of SysCtlClockFreqSet()). //! //! \return None. // @@ -1983,7 +1985,7 @@ I2CMasterBurstLengthSet(uint32_t ui32Base, uint8_t ui8Length) // // Check the arguments. // - ASSERT(_I2CBaseValid(ui32Base) && (ui8Length < 255)); + ASSERT(_I2CBaseValid(ui32Base) && (ui8Length < 256)); // // Set the burst length. @@ -2061,9 +2063,28 @@ I2CMasterGlitchFilterConfigSet(uint32_t ui32Base, uint32_t ui32Config) ASSERT(_I2CBaseValid(ui32Base)); // - // Configure the glitch filter field of MTPR. + // Configure the glitch filter field of MTPR if it is TM4C129 // - HWREG(ui32Base + I2C_O_MTPR) |= ui32Config; + if(CLASS_IS_TM4C129) + { + HWREG(ui32Base + I2C_O_MTPR) |= ui32Config; + } + + // + // Configure the glitch filter if it is TM4C123 + // + if(CLASS_IS_TM4C123) + { + // + // Configure the glitch filter pulse width + // + HWREG(ui32Base + I2C_O_MCR2) |= (ui32Config >> 12); + + // + // Enable the glitch filter by setting the GFE bit + // + HWREG(ui32Base + I2C_O_MCR) |= I2C_MCR_GFE; + } } //***************************************************************************** @@ -2135,6 +2156,35 @@ I2CSlaveFIFODisable(uint32_t ui32Base) HWREG(ui32Base + I2C_O_SCSR) = I2C_SCSR_DA; } +//***************************************************************************** +// +//! Enables internal loopback mode for an I2C port. +//! +//! \param ui32Base is the base address of the I2C module. +//! +//! This function configures an I2C port in internal loopback mode to help with +//! diagnostics and debug. In this mode, the SDA and SCL signals from master +//! and slave modules are internally connected. This allows data to be +//! transferred between the master and slave modules of the same I2C port, +//! without having to go through I/O's. I2CMasterDataPut(), I2CSlaveDataPut(), +//! I2CMasterDataGet(),I2CSlaveDataGet() can be used along with this function. +//! +//! \return None. +// +//***************************************************************************** +void I2CLoopbackEnable(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(_I2CBaseValid(ui32Base)); + + // + // Write the loopback enable bit to the register. + // + HWREG(ui32Base + I2C_O_MCR) |= I2C_MCR_LPBK; +} + //***************************************************************************** // // Close the Doxygen group. diff --git a/bsp/tm4c129x/libraries/driverlib/i2c.h b/bsp/tm4c129x/libraries/driverlib/i2c.h index 042862be63..ab7b44e4fe 100644 --- a/bsp/tm4c129x/libraries/driverlib/i2c.h +++ b/bsp/tm4c129x/libraries/driverlib/i2c.h @@ -2,7 +2,7 @@ // // i2c.h - Prototypes for the I2C Driver. // -// Copyright (c) 2005-2014 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Redistribution and use in source and binary forms, with or without @@ -33,7 +33,7 @@ // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library. +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. // //***************************************************************************** @@ -281,7 +281,7 @@ extern "C" // Prototypes for the APIs. // //***************************************************************************** -extern void I2CIntRegister(uint32_t ui32Base, void(pfnHandler)(void)); +extern void I2CIntRegister(uint32_t ui32Base, void(*pfnHandler)(void)); extern void I2CIntUnregister(uint32_t ui32Base); extern void I2CTxFIFOConfigSet(uint32_t ui32Base, uint32_t ui32Config); extern void I2CTxFIFOFlush(uint32_t ui32Base); @@ -348,6 +348,7 @@ extern bool I2CSlaveIntStatus(uint32_t ui32Base, bool bMasked); extern uint32_t I2CSlaveIntStatusEx(uint32_t ui32Base, bool bMasked); extern uint32_t I2CSlaveStatus(uint32_t ui32Base); +extern void I2CLoopbackEnable(uint32_t ui32Base); //***************************************************************************** // diff --git a/bsp/tm4c129x/libraries/driverlib/interrupt.c b/bsp/tm4c129x/libraries/driverlib/interrupt.c index 55aaa801a1..ebf5f95bd3 100644 --- a/bsp/tm4c129x/libraries/driverlib/interrupt.c +++ b/bsp/tm4c129x/libraries/driverlib/interrupt.c @@ -2,7 +2,7 @@ // // interrupt.c - Driver for the NVIC Interrupt Controller. // -// Copyright (c) 2005-2014 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Redistribution and use in source and binary forms, with or without @@ -33,7 +33,7 @@ // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library. +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. // //***************************************************************************** diff --git a/bsp/tm4c129x/libraries/driverlib/interrupt.h b/bsp/tm4c129x/libraries/driverlib/interrupt.h index 650a56fd1f..effb30c88a 100644 --- a/bsp/tm4c129x/libraries/driverlib/interrupt.h +++ b/bsp/tm4c129x/libraries/driverlib/interrupt.h @@ -2,7 +2,7 @@ // // interrupt.h - Prototypes for the NVIC Interrupt Controller Driver. // -// Copyright (c) 2005-2014 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Redistribution and use in source and binary forms, with or without @@ -33,7 +33,7 @@ // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library. +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. // //***************************************************************************** diff --git a/bsp/tm4c129x/libraries/driverlib/lcd.c b/bsp/tm4c129x/libraries/driverlib/lcd.c index db5af4fcd6..195d0ef0ba 100644 --- a/bsp/tm4c129x/libraries/driverlib/lcd.c +++ b/bsp/tm4c129x/libraries/driverlib/lcd.c @@ -2,7 +2,7 @@ // // lcd.c - Defines and Macros for the LCD Controller module. // -// Copyright (c) 2012-2014 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2012-2017 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Redistribution and use in source and binary forms, with or without @@ -33,7 +33,7 @@ // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library. +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. // //***************************************************************************** diff --git a/bsp/tm4c129x/libraries/driverlib/lcd.h b/bsp/tm4c129x/libraries/driverlib/lcd.h index d47451f2a0..766cf94361 100644 --- a/bsp/tm4c129x/libraries/driverlib/lcd.h +++ b/bsp/tm4c129x/libraries/driverlib/lcd.h @@ -2,7 +2,7 @@ // // lcd.h - Defines and Macros for the LCD Controller module. // -// Copyright (c) 2012-2014 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2012-2017 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Redistribution and use in source and binary forms, with or without @@ -33,7 +33,7 @@ // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library. +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. // //***************************************************************************** diff --git a/bsp/tm4c129x/libraries/driverlib/mpu.c b/bsp/tm4c129x/libraries/driverlib/mpu.c index e776356926..4d01f1b403 100644 --- a/bsp/tm4c129x/libraries/driverlib/mpu.c +++ b/bsp/tm4c129x/libraries/driverlib/mpu.c @@ -2,7 +2,7 @@ // // mpu.c - Driver for the Cortex-M3 memory protection unit (MPU). // -// Copyright (c) 2007-2014 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2007-2017 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Redistribution and use in source and binary forms, with or without @@ -33,7 +33,7 @@ // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library. +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. // //***************************************************************************** diff --git a/bsp/tm4c129x/libraries/driverlib/mpu.h b/bsp/tm4c129x/libraries/driverlib/mpu.h index a45435c92d..9c8377f8ce 100644 --- a/bsp/tm4c129x/libraries/driverlib/mpu.h +++ b/bsp/tm4c129x/libraries/driverlib/mpu.h @@ -2,7 +2,7 @@ // // mpu.h - Defines and Macros for the memory protection unit. // -// Copyright (c) 2005-2014 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Redistribution and use in source and binary forms, with or without @@ -33,7 +33,7 @@ // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library. +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. // //***************************************************************************** diff --git a/bsp/tm4c129x/libraries/driverlib/onewire.c b/bsp/tm4c129x/libraries/driverlib/onewire.c index b2f6e2300f..24d671f125 100644 --- a/bsp/tm4c129x/libraries/driverlib/onewire.c +++ b/bsp/tm4c129x/libraries/driverlib/onewire.c @@ -2,7 +2,7 @@ // // onewire.c - Driver for OneWire master module. // -// Copyright (c) 2012-2014 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2012-2017 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Redistribution and use in source and binary forms, with or without @@ -33,7 +33,7 @@ // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library. +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. // //***************************************************************************** @@ -454,10 +454,6 @@ _OneWireIntNumberGet(uint32_t ui32Base) // // Find the valid interrupt number for the 1-Wire module. // - if(CLASS_IS_TM4E111) - { - ui32Int = INT_ONEWIRE0_TM4E111; - } if(CLASS_IS_TM4C129) { ui32Int = INT_ONEWIRE0_TM4C129; diff --git a/bsp/tm4c129x/libraries/driverlib/onewire.h b/bsp/tm4c129x/libraries/driverlib/onewire.h index 6751f78d95..731f3f99bb 100644 --- a/bsp/tm4c129x/libraries/driverlib/onewire.h +++ b/bsp/tm4c129x/libraries/driverlib/onewire.h @@ -2,7 +2,7 @@ // // onewire.h - Prototypes for the OneWire Driver. // -// Copyright (c) 2012-2014 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2012-2017 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Redistribution and use in source and binary forms, with or without @@ -33,7 +33,7 @@ // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library. +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. // //***************************************************************************** diff --git a/bsp/tm4c129x/libraries/driverlib/pin_map.h b/bsp/tm4c129x/libraries/driverlib/pin_map.h index a2c94f46e7..9d68609861 100644 --- a/bsp/tm4c129x/libraries/driverlib/pin_map.h +++ b/bsp/tm4c129x/libraries/driverlib/pin_map.h @@ -2,7 +2,7 @@ // // pin_map.h - Mapping of peripherals to pins for all parts. // -// Copyright (c) 2007-2014 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2007-2017 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Redistribution and use in source and binary forms, with or without @@ -33,7 +33,7 @@ // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library. +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. // //***************************************************************************** @@ -11207,6 +11207,466 @@ #endif // PART_TM4C123GH6ZRB +//***************************************************************************** +// +// TM4C123GH6ZXR Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C123GH6ZXR + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_CAN1RX 0x00000008 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_CAN1TX 0x00000408 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 +#define GPIO_PA6_M1PWM2 0x00001805 + +#define GPIO_PA7_I2C1SDA 0x00001C03 +#define GPIO_PA7_M1PWM3 0x00001C05 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_M0PWM2 0x00011004 +#define GPIO_PB4_T1CCP0 0x00011007 +#define GPIO_PB4_CAN0RX 0x00011008 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_M0PWM3 0x00011404 +#define GPIO_PB5_T1CCP1 0x00011407 +#define GPIO_PB5_CAN0TX 0x00011408 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_I2C5SCL 0x00011803 +#define GPIO_PB6_M0PWM0 0x00011804 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_I2C5SDA 0x00011C03 +#define GPIO_PB7_M0PWM1 0x00011C04 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_M0PWM6 0x00021004 +#define GPIO_PC4_IDX1 0x00021006 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_M0PWM7 0x00021404 +#define GPIO_PC5_PHA1 0x00021406 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_PHB1 0x00021806 +#define GPIO_PC6_WT1CCP0 0x00021807 +#define GPIO_PC6_USB0EPEN 0x00021808 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 +#define GPIO_PC7_USB0PFLT 0x00021C08 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_M0PWM6 0x00030004 +#define GPIO_PD0_M1PWM0 0x00030005 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_M0PWM7 0x00030404 +#define GPIO_PD1_M1PWM1 0x00030405 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_M0FAULT0 0x00030804 +#define GPIO_PD2_WT3CCP0 0x00030807 +#define GPIO_PD2_USB0EPEN 0x00030808 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_IDX0 0x00030C06 +#define GPIO_PD3_WT3CCP1 0x00030C07 +#define GPIO_PD3_USB0PFLT 0x00030C08 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_M0FAULT0 0x00031804 +#define GPIO_PD6_PHA0 0x00031806 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_M0FAULT1 0x00031C04 +#define GPIO_PD7_PHB0 0x00031C06 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_M0PWM4 0x00041004 +#define GPIO_PE4_M1PWM2 0x00041005 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_M0PWM5 0x00041404 +#define GPIO_PE5_M1PWM3 0x00041405 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PE6_CAN1RX 0x00041808 + +#define GPIO_PE7_U1RI 0x00041C01 +#define GPIO_PE7_CAN1TX 0x00041C08 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_M1PWM4 0x00050005 +#define GPIO_PF0_PHA0 0x00050006 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_M1PWM5 0x00050405 +#define GPIO_PF1_PHB0 0x00050406 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_U1DCD 0x00050801 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_M0FAULT0 0x00050804 +#define GPIO_PF2_M1PWM6 0x00050805 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_C2O 0x00050809 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_U1DSR 0x00050C01 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_M0FAULT1 0x00050C04 +#define GPIO_PF3_M1PWM7 0x00050C05 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_U1DTR 0x00051001 +#define GPIO_PF4_M0FAULT2 0x00051004 +#define GPIO_PF4_M1FAULT0 0x00051005 +#define GPIO_PF4_IDX0 0x00051006 +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_USB0EPEN 0x00051008 +#define GPIO_PF4_TRD3 0x0005100E + +#define GPIO_PF5_M0FAULT3 0x00051404 +#define GPIO_PF5_T2CCP1 0x00051407 +#define GPIO_PF5_USB0PFLT 0x00051408 + +#define GPIO_PF6_I2C2SCL 0x00051803 +#define GPIO_PF6_T3CCP0 0x00051807 + +#define GPIO_PF7_I2C2SDA 0x00051C03 +#define GPIO_PF7_M1FAULT0 0x00051C05 +#define GPIO_PF7_T3CCP1 0x00051C07 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_M1FAULT1 0x00060005 +#define GPIO_PG0_PHA1 0x00060006 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_M1FAULT2 0x00060405 +#define GPIO_PG1_PHB1 0x00060406 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_M0FAULT1 0x00060804 +#define GPIO_PG2_M1PWM0 0x00060805 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_M0FAULT2 0x00060C04 +#define GPIO_PG3_M1PWM1 0x00060C05 +#define GPIO_PG3_PHA1 0x00060C06 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_M0PWM4 0x00061004 +#define GPIO_PG4_M1PWM2 0x00061005 +#define GPIO_PG4_PHB1 0x00061006 +#define GPIO_PG4_WT0CCP0 0x00061007 +#define GPIO_PG4_USB0EPEN 0x00061008 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_M0PWM5 0x00061404 +#define GPIO_PG5_M1PWM3 0x00061405 +#define GPIO_PG5_IDX1 0x00061406 +#define GPIO_PG5_WT0CCP1 0x00061407 +#define GPIO_PG5_USB0PFLT 0x00061408 + +#define GPIO_PG6_I2C5SCL 0x00061803 +#define GPIO_PG6_M0PWM6 0x00061804 +#define GPIO_PG6_WT1CCP0 0x00061807 + +#define GPIO_PG7_I2C5SDA 0x00061C03 +#define GPIO_PG7_M0PWM7 0x00061C04 +#define GPIO_PG7_IDX1 0x00061C05 +#define GPIO_PG7_WT1CCP1 0x00061C07 + +#define GPIO_PH0_SSI3CLK 0x00070002 +#define GPIO_PH0_M0PWM0 0x00070004 +#define GPIO_PH0_M0FAULT0 0x00070006 +#define GPIO_PH0_WT2CCP0 0x00070007 + +#define GPIO_PH1_SSI3FSS 0x00070402 +#define GPIO_PH1_M0PWM1 0x00070404 +#define GPIO_PH1_IDX0 0x00070405 +#define GPIO_PH1_M0FAULT1 0x00070406 +#define GPIO_PH1_WT2CCP1 0x00070407 + +#define GPIO_PH2_SSI3RX 0x00070802 +#define GPIO_PH2_M0PWM2 0x00070804 +#define GPIO_PH2_M0FAULT2 0x00070806 +#define GPIO_PH2_WT5CCP0 0x00070807 + +#define GPIO_PH3_SSI3TX 0x00070C02 +#define GPIO_PH3_M0PWM3 0x00070C04 +#define GPIO_PH3_M0FAULT3 0x00070C06 +#define GPIO_PH3_WT5CCP1 0x00070C07 + +#define GPIO_PH4_SSI2CLK 0x00071002 +#define GPIO_PH4_M0PWM4 0x00071004 +#define GPIO_PH4_PHA0 0x00071005 +#define GPIO_PH4_WT3CCP0 0x00071007 + +#define GPIO_PH5_SSI2FSS 0x00071402 +#define GPIO_PH5_M0PWM5 0x00071404 +#define GPIO_PH5_PHB0 0x00071405 +#define GPIO_PH5_WT3CCP1 0x00071407 + +#define GPIO_PH6_SSI2RX 0x00071802 +#define GPIO_PH6_M0PWM6 0x00071804 +#define GPIO_PH6_WT4CCP0 0x00071807 + +#define GPIO_PH7_SSI2TX 0x00071C02 +#define GPIO_PH7_M0PWM7 0x00071C04 +#define GPIO_PH7_WT4CCP1 0x00071C07 + +#define GPIO_PJ0_U4RX 0x00080001 +#define GPIO_PJ0_T1CCP0 0x00080007 + +#define GPIO_PJ1_U4TX 0x00080401 +#define GPIO_PJ1_T1CCP1 0x00080407 + +#define GPIO_PJ2_U5RX 0x00080801 +#define GPIO_PJ2_IDX0 0x00080805 +#define GPIO_PJ2_T2CCP0 0x00080807 + +#define GPIO_PJ3_U5TX 0x00080C01 +#define GPIO_PJ3_T2CCP1 0x00080C07 + +#define GPIO_PJ4_U6RX 0x00081001 +#define GPIO_PJ4_T3CCP0 0x00081007 + +#define GPIO_PJ5_U6TX 0x00081401 +#define GPIO_PJ5_T3CCP1 0x00081407 + +#define GPIO_PK0_SSI3CLK 0x00090002 +#define GPIO_PK0_M1FAULT0 0x00090006 + +#define GPIO_PK1_SSI3FSS 0x00090402 +#define GPIO_PK1_M1FAULT1 0x00090406 + +#define GPIO_PK2_SSI3RX 0x00090802 +#define GPIO_PK2_M1FAULT2 0x00090806 + +#define GPIO_PK3_SSI3TX 0x00090C02 +#define GPIO_PK3_M1FAULT3 0x00090C06 + +#define GPIO_PK4_U7RX 0x00091001 +#define GPIO_PK4_M0FAULT0 0x00091006 +#define GPIO_PK4_RTCCLK 0x00091007 +#define GPIO_PK4_C0O 0x00091008 + +#define GPIO_PK5_U7TX 0x00091401 +#define GPIO_PK5_M0FAULT1 0x00091406 +#define GPIO_PK5_C1O 0x00091408 + +#define GPIO_PK6_M0FAULT2 0x00091806 +#define GPIO_PK6_WT1CCP0 0x00091807 +#define GPIO_PK6_C2O 0x00091808 + +#define GPIO_PK7_M0FAULT3 0x00091C06 +#define GPIO_PK7_WT1CCP1 0x00091C07 + +#define GPIO_PL0_T0CCP0 0x000A0007 +#define GPIO_PL0_WT0CCP0 0x000A0008 + +#define GPIO_PL1_T0CCP1 0x000A0407 +#define GPIO_PL1_WT0CCP1 0x000A0408 + +#define GPIO_PL2_T1CCP0 0x000A0807 +#define GPIO_PL2_WT1CCP0 0x000A0808 + +#define GPIO_PL3_T1CCP1 0x000A0C07 +#define GPIO_PL3_WT1CCP1 0x000A0C08 + +#define GPIO_PL4_T2CCP0 0x000A1007 +#define GPIO_PL4_WT2CCP0 0x000A1008 + +#define GPIO_PL5_T2CCP1 0x000A1407 +#define GPIO_PL5_WT2CCP1 0x000A1408 + +#define GPIO_PL6_T3CCP0 0x000A1807 +#define GPIO_PL6_WT3CCP0 0x000A1808 + +#define GPIO_PL7_T3CCP1 0x000A1C07 +#define GPIO_PL7_WT3CCP1 0x000A1C08 + +#define GPIO_PM0_T4CCP0 0x000B0007 +#define GPIO_PM0_WT4CCP0 0x000B0008 + +#define GPIO_PM1_T4CCP1 0x000B0407 +#define GPIO_PM1_WT4CCP1 0x000B0408 + +#define GPIO_PM2_T5CCP0 0x000B0807 +#define GPIO_PM2_WT5CCP0 0x000B0808 + +#define GPIO_PM3_T5CCP1 0x000B0C07 +#define GPIO_PM3_WT5CCP1 0x000B0C08 + +#define GPIO_PM6_M0PWM4 0x000B1802 +#define GPIO_PM6_WT0CCP0 0x000B1807 + +#define GPIO_PM7_M0PWM5 0x000B1C02 +#define GPIO_PM7_WT0CCP1 0x000B1C07 + +#define GPIO_PN0_CAN0RX 0x000C0001 + +#define GPIO_PN1_CAN0TX 0x000C0401 + +#define GPIO_PN2_M0PWM6 0x000C0802 +#define GPIO_PN2_WT2CCP0 0x000C0807 + +#define GPIO_PN3_M0PWM7 0x000C0C02 +#define GPIO_PN3_WT2CCP1 0x000C0C07 + +#define GPIO_PN4_M1PWM4 0x000C1002 +#define GPIO_PN4_WT3CCP0 0x000C1007 + +#define GPIO_PN5_M1PWM5 0x000C1402 +#define GPIO_PN5_WT3CCP1 0x000C1407 + +#define GPIO_PN6_M1PWM6 0x000C1802 +#define GPIO_PN6_WT4CCP0 0x000C1807 + +#define GPIO_PN7_M1PWM7 0x000C1C02 +#define GPIO_PN7_WT4CCP1 0x000C1C07 + +#define GPIO_PP0_M0PWM0 0x000D0001 +#define GPIO_PP0_T4CCP0 0x000D0007 + +#define GPIO_PP1_M0PWM1 0x000D0401 +#define GPIO_PP1_T4CCP1 0x000D0407 + +#define GPIO_PP2_M0PWM2 0x000D0801 +#define GPIO_PP2_T5CCP0 0x000D0807 + +#define GPIO_PP3_M0PWM3 0x000D0C01 +#define GPIO_PP3_T5CCP1 0x000D0C07 + +#define GPIO_PP4_M0PWM4 0x000D1001 +#define GPIO_PP4_WT0CCP0 0x000D1007 + +#define GPIO_PP5_M0PWM5 0x000D1401 +#define GPIO_PP5_WT0CCP1 0x000D1407 + +#define GPIO_PP6_M0PWM6 0x000D1801 +#define GPIO_PP6_WT1CCP0 0x000D1807 + +#define GPIO_PP7_M0PWM7 0x000D1C01 +#define GPIO_PP7_WT1CCP1 0x000D1C07 + +#define GPIO_PQ0_M1PWM0 0x000E0001 +#define GPIO_PQ0_WT2CCP0 0x000E0007 + +#define GPIO_PQ1_M1PWM1 0x000E0401 +#define GPIO_PQ1_WT2CCP1 0x000E0407 + +#define GPIO_PQ2_M1PWM2 0x000E0801 +#define GPIO_PQ2_WT3CCP0 0x000E0807 + +#define GPIO_PQ3_M1PWM3 0x000E0C01 +#define GPIO_PQ3_WT3CCP1 0x000E0C07 + +#define GPIO_PQ4_M1PWM4 0x000E1001 +#define GPIO_PQ4_WT4CCP0 0x000E1007 + +#define GPIO_PQ5_M1PWM5 0x000E1401 +#define GPIO_PQ5_WT4CCP1 0x000E1407 + +#define GPIO_PQ6_M1PWM6 0x000E1801 +#define GPIO_PQ6_WT5CCP0 0x000E1807 + +#define GPIO_PQ7_M1PWM7 0x000E1C01 +#define GPIO_PQ7_WT5CCP1 0x000E1C07 + +#endif // PART_TM4C123GH6ZXR + //***************************************************************************** // // TM4C1290NCPDT Port/Pin Mapping Definitions diff --git a/bsp/tm4c129x/libraries/driverlib/pwm.c b/bsp/tm4c129x/libraries/driverlib/pwm.c index b74417ba8a..54fbe52e5c 100644 --- a/bsp/tm4c129x/libraries/driverlib/pwm.c +++ b/bsp/tm4c129x/libraries/driverlib/pwm.c @@ -2,7 +2,7 @@ // // pwm.c - API for the PWM modules // -// Copyright (c) 2005-2014 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Redistribution and use in source and binary forms, with or without @@ -33,7 +33,7 @@ // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library. +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. // //***************************************************************************** diff --git a/bsp/tm4c129x/libraries/driverlib/pwm.h b/bsp/tm4c129x/libraries/driverlib/pwm.h index 823b853bcc..c18d98acb2 100644 --- a/bsp/tm4c129x/libraries/driverlib/pwm.h +++ b/bsp/tm4c129x/libraries/driverlib/pwm.h @@ -2,7 +2,7 @@ // // pwm.h - API function protoypes for Pulse Width Modulation (PWM) ports // -// Copyright (c) 2005-2014 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Redistribution and use in source and binary forms, with or without @@ -33,7 +33,7 @@ // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library. +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. // //***************************************************************************** diff --git a/bsp/tm4c129x/libraries/driverlib/qei.c b/bsp/tm4c129x/libraries/driverlib/qei.c index d450615fb6..b4def78493 100644 --- a/bsp/tm4c129x/libraries/driverlib/qei.c +++ b/bsp/tm4c129x/libraries/driverlib/qei.c @@ -2,7 +2,7 @@ // // qei.c - Driver for the Quadrature Encoder with Index. // -// Copyright (c) 2005-2014 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Redistribution and use in source and binary forms, with or without @@ -33,7 +33,7 @@ // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library. +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. // //***************************************************************************** @@ -274,6 +274,96 @@ QEIErrorGet(uint32_t ui32Base) return((HWREG(ui32Base + QEI_O_STAT) & QEI_STAT_ERROR) ? true : false); } +//***************************************************************************** +// +//! Enables the input filter. +//! +//! \param ui32Base is the base address of the quadrature encoder module. +//! +//! This function enables operation of the input filter in the quadrature +//! encoder module. The module must be configured before input filter is +//! enabled. +//! +//! \sa QEIFilterConfigure() and QEIEnable() +//! +//! \return None. +// +//***************************************************************************** +void +QEIFilterEnable(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT((ui32Base == QEI0_BASE) || (ui32Base == QEI1_BASE)); + + // + // Enable the input filter. + // + HWREG(ui32Base + QEI_O_CTL) |= QEI_CTL_FILTEN; +} + +//***************************************************************************** +// +//! Disables the input filter. +//! +//! \param ui32Base is the base address of the quadrature encoder module. +//! +//! This function disables operation of the input filter in the quadrature +//! encoder module. +//! +//! \return None. +// +//***************************************************************************** +void +QEIFilterDisable(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT((ui32Base == QEI0_BASE) || (ui32Base == QEI1_BASE)); + + // + // Disable the input filter. + // + HWREG(ui32Base + QEI_O_CTL) &= ~(QEI_CTL_FILTEN); +} + +//***************************************************************************** +// +//! Configures the input filter. +//! +//! \param ui32Base is the base address of the quadrature encoder module. +//! \param ui32FiltCnt specifies the filter count applied to the input quadrature +//! signal before it is counted; can be one of \b QEI_FILTCNT_2, +//! \b QEI_FILTCNT_3, \b QEI_FILTCNT_4, \b QEI_FILTCNT_5, \b QEI_FILTCNT_6, +//! \b QEI_FILTCNT_7, \b QEI_FILTCNT_8, \b QEI_FILTCNT_9, \b QEI_FILTCNT_10, +//! \b QEI_FILTCNT_11, \b QEI_FILTCNT_12, \b QEI_FILTCNT_13, \b QEI_FILTCNT_14, +//! \b QEI_FILTCNT_15, \b QEI_FILTCNT_16 or \b QEI_FILTCNT_17 +//! +//! This function configures the operation of the input filter prescale count. +//! as specified by \e ui32FiltCnt before the input signals are sent to the +//! quadrature encoder module. +//! +//! \return None. +// +//***************************************************************************** +void +QEIFilterConfigure(uint32_t ui32Base, uint32_t ui32FiltCnt) +{ + // + // Check the arguments. + // + ASSERT((ui32Base == QEI0_BASE) || (ui32Base == QEI1_BASE)); + ASSERT(!(ui32FiltCnt & ~(QEI_CTL_FILTCNT_M))); + + // + // Set the input filter prescale count. + // + HWREG(ui32Base + QEI_O_CTL) = ((HWREG(ui32Base + QEI_O_CTL) & + ~(QEI_CTL_FILTCNT_M)) | ui32FiltCnt); +} + //***************************************************************************** // //! Enables the velocity capture. diff --git a/bsp/tm4c129x/libraries/driverlib/qei.h b/bsp/tm4c129x/libraries/driverlib/qei.h index 3ede01c933..031897ae31 100644 --- a/bsp/tm4c129x/libraries/driverlib/qei.h +++ b/bsp/tm4c129x/libraries/driverlib/qei.h @@ -2,7 +2,7 @@ // // qei.h - Prototypes for the Quadrature Encoder Driver. // -// Copyright (c) 2005-2014 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Redistribution and use in source and binary forms, with or without @@ -33,7 +33,7 @@ // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library. +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. // //***************************************************************************** @@ -65,6 +65,29 @@ extern "C" #define QEI_CONFIG_NO_SWAP 0x00000000 // Do not swap ChA and ChB #define QEI_CONFIG_SWAP 0x00000002 // Swap ChA and ChB +//***************************************************************************** +// +// Values that can be passed to QEIFilterConfigure as the ui32PreDiv +// parameter. +// +//***************************************************************************** +#define QEI_FILTCNT_2 0x00000000 // Filter Count of 2 System Clocks +#define QEI_FILTCNT_3 0x00010000 // Filter Count of 3 System Clocks +#define QEI_FILTCNT_4 0x00020000 // Filter Count of 4 System Clocks +#define QEI_FILTCNT_5 0x00030000 // Filter Count of 5 System Clocks +#define QEI_FILTCNT_6 0x00040000 // Filter Count of 6 System Clocks +#define QEI_FILTCNT_7 0x00050000 // Filter Count of 7 System Clocks +#define QEI_FILTCNT_8 0x00060000 // Filter Count of 8 System Clocks +#define QEI_FILTCNT_9 0x00070000 // Filter Count of 9 System Clocks +#define QEI_FILTCNT_10 0x00080000 // Filter Count of 10 System Clocks +#define QEI_FILTCNT_11 0x00090000 // Filter Count of 11 System Clocks +#define QEI_FILTCNT_12 0x000A0000 // Filter Count of 12 System Clocks +#define QEI_FILTCNT_13 0x000B0000 // Filter Count of 13 System Clocks +#define QEI_FILTCNT_14 0x000C0000 // Filter Count of 14 System Clocks +#define QEI_FILTCNT_15 0x000D0000 // Filter Count of 15 System Clocks +#define QEI_FILTCNT_16 0x000E0000 // Filter Count of 16 System Clocks +#define QEI_FILTCNT_17 0x000F0000 // Filter Count of 17 System Clocks + //***************************************************************************** // // Values that can be passed to QEIVelocityConfigure as the ui32PreDiv @@ -104,6 +127,9 @@ extern uint32_t QEIPositionGet(uint32_t ui32Base); extern void QEIPositionSet(uint32_t ui32Base, uint32_t ui32Position); extern int32_t QEIDirectionGet(uint32_t ui32Base); extern bool QEIErrorGet(uint32_t ui32Base); +extern void QEIFilterEnable(uint32_t ui32Base); +extern void QEIFilterDisable(uint32_t ui32Base); +extern void QEIFilterConfigure(uint32_t ui32Base, uint32_t ui32FiltCnt); extern void QEIVelocityEnable(uint32_t ui32Base); extern void QEIVelocityDisable(uint32_t ui32Base); extern void QEIVelocityConfigure(uint32_t ui32Base, uint32_t ui32PreDiv, diff --git a/bsp/tm4c129x/libraries/driverlib/readme.txt b/bsp/tm4c129x/libraries/driverlib/readme.txt index 719ddfcd9c..1f90c23656 100644 --- a/bsp/tm4c129x/libraries/driverlib/readme.txt +++ b/bsp/tm4c129x/libraries/driverlib/readme.txt @@ -2,7 +2,7 @@ This project will build the TivaWare Peripheral Driver Library. ------------------------------------------------------------------------------- -Copyright (c) 2006-2014 Texas Instruments Incorporated. All rights reserved. +Copyright (c) 2006-2017 Texas Instruments Incorporated. All rights reserved. Software License Agreement Redistribution and use in source and binary forms, with or without @@ -33,4 +33,4 @@ THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library. +This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. diff --git a/bsp/tm4c129x/libraries/driverlib/rom.h b/bsp/tm4c129x/libraries/driverlib/rom.h index ba01104676..2ffdab87e5 100644 --- a/bsp/tm4c129x/libraries/driverlib/rom.h +++ b/bsp/tm4c129x/libraries/driverlib/rom.h @@ -2,7 +2,7 @@ // // rom.h - Macros to facilitate calling functions in the ROM. // -// Copyright (c) 2007-2014 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2007-2017 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Redistribution and use in source and binary forms, with or without @@ -33,7 +33,7 @@ // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library. +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. // //***************************************************************************** @@ -54,6 +54,9 @@ #ifdef TARGET_IS_SNOWFLAKE_RA1 #define TARGET_IS_TM4C129_RA1 #endif +#ifdef TARGET_IS_SNOWFLAKE_RA2 +#define TARGET_IS_TM4C129_RA2 +#endif #ifdef TARGET_IS_BLIZZARD_RA1 #define TARGET_IS_TM4C123_RA1 #endif @@ -120,8 +123,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_ADCSequenceDataGet \ ((int32_t (*)(uint32_t ui32Base, \ uint32_t ui32SequenceNum, \ @@ -130,8 +135,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_ADCIntDisable \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32SequenceNum))ROM_ADCTABLE[1]) @@ -139,8 +146,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_ADCIntEnable \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32SequenceNum))ROM_ADCTABLE[2]) @@ -148,8 +157,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_ADCIntStatus \ ((uint32_t (*)(uint32_t ui32Base, \ uint32_t ui32SequenceNum, \ @@ -158,8 +169,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_ADCIntClear \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32SequenceNum))ROM_ADCTABLE[4]) @@ -167,8 +180,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_ADCSequenceEnable \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32SequenceNum))ROM_ADCTABLE[5]) @@ -176,8 +191,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_ADCSequenceDisable \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32SequenceNum))ROM_ADCTABLE[6]) @@ -185,8 +202,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_ADCSequenceConfigure \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32SequenceNum, \ @@ -196,8 +215,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_ADCSequenceStepConfigure \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32SequenceNum, \ @@ -207,8 +228,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_ADCSequenceOverflow \ ((int32_t (*)(uint32_t ui32Base, \ uint32_t ui32SequenceNum))ROM_ADCTABLE[9]) @@ -216,8 +239,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_ADCSequenceOverflowClear \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32SequenceNum))ROM_ADCTABLE[10]) @@ -225,8 +250,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_ADCSequenceUnderflow \ ((int32_t (*)(uint32_t ui32Base, \ uint32_t ui32SequenceNum))ROM_ADCTABLE[11]) @@ -234,8 +261,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_ADCSequenceUnderflowClear \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32SequenceNum))ROM_ADCTABLE[12]) @@ -243,8 +272,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_ADCProcessorTrigger \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32SequenceNum))ROM_ADCTABLE[13]) @@ -252,8 +283,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_ADCHardwareOversampleConfigure \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32Factor))ROM_ADCTABLE[14]) @@ -261,8 +294,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_ADCComparatorConfigure \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32Comp, \ @@ -271,8 +306,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_ADCComparatorRegionSet \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32Comp, \ @@ -282,8 +319,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_ADCComparatorReset \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32Comp, \ @@ -293,8 +332,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_ADCComparatorIntDisable \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32SequenceNum))ROM_ADCTABLE[18]) @@ -302,8 +343,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_ADCComparatorIntEnable \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32SequenceNum))ROM_ADCTABLE[19]) @@ -311,16 +354,20 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_ADCComparatorIntStatus \ ((uint32_t (*)(uint32_t ui32Base))ROM_ADCTABLE[20]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_ADCComparatorIntClear \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32Status))ROM_ADCTABLE[21]) @@ -328,8 +375,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_ADCReferenceSet \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32Ref))ROM_ADCTABLE[22]) @@ -337,16 +386,20 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_ADCReferenceGet \ ((uint32_t (*)(uint32_t ui32Base))ROM_ADCTABLE[23]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_ADCPhaseDelaySet \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32Phase))ROM_ADCTABLE[24]) @@ -354,49 +407,51 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_ADCPhaseDelayGet \ ((uint32_t (*)(uint32_t ui32Base))ROM_ADCTABLE[25]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) -#define ROM_ADCIntClearEx \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32IntFlags))ROM_ADCTABLE[28]) -#endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_ADCIntDisableEx \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32IntFlags))ROM_ADCTABLE[29]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_ADCIntEnableEx \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32IntFlags))ROM_ADCTABLE[30]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_ADCIntStatusEx \ ((uint32_t (*)(uint32_t ui32Base, \ bool bMasked))ROM_ADCTABLE[31]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_ADCSequenceDMAEnable \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32SequenceNum))ROM_ADCTABLE[32]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_ADCSequenceDMADisable \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32SequenceNum))ROM_ADCTABLE[33]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_ADCBusy \ ((bool (*)(uint32_t ui32Base))ROM_ADCTABLE[34]) #endif @@ -407,25 +462,29 @@ // //***************************************************************************** #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_AESIntStatus \ ((uint32_t (*)(uint32_t ui32Base, \ bool bMasked))ROM_AESTABLE[0]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_AESAuthLengthSet \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32Length))ROM_AESTABLE[1]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_AESConfigSet \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32Config))ROM_AESTABLE[2]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_AESDataAuth \ ((bool (*)(uint32_t ui32Base, \ uint32_t *pui32Src, \ @@ -433,7 +492,8 @@ uint32_t *pui32Tag))ROM_AESTABLE[3]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_AESDataProcess \ ((bool (*)(uint32_t ui32Base, \ uint32_t *pui32Src, \ @@ -441,7 +501,8 @@ uint32_t ui32Length))ROM_AESTABLE[4]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_AESDataProcessAuth \ ((bool (*)(uint32_t ui32Base, \ uint32_t *pui32Src, \ @@ -452,103 +513,120 @@ uint32_t *pui32Tag))ROM_AESTABLE[5]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_AESDataRead \ ((void (*)(uint32_t ui32Base, \ uint32_t *pui32Dest))ROM_AESTABLE[6]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_AESDataReadNonBlocking \ ((bool (*)(uint32_t ui32Base, \ uint32_t *pui32Dest))ROM_AESTABLE[7]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_AESDataWrite \ ((void (*)(uint32_t ui32Base, \ uint32_t *pui32Src))ROM_AESTABLE[8]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_AESDataWriteNonBlocking \ ((bool (*)(uint32_t ui32Base, \ uint32_t *pui32Src))ROM_AESTABLE[9]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_AESDMADisable \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32Flags))ROM_AESTABLE[10]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_AESDMAEnable \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32Flags))ROM_AESTABLE[11]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_AESIntClear \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32IntFlags))ROM_AESTABLE[12]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_AESIntDisable \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32IntFlags))ROM_AESTABLE[13]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_AESIntEnable \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32IntFlags))ROM_AESTABLE[14]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_AESIVSet \ ((void (*)(uint32_t ui32Base, \ uint32_t *pui32IVdata))ROM_AESTABLE[15]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_AESKey1Set \ ((void (*)(uint32_t ui32Base, \ uint32_t *pui32Key, \ uint32_t ui32Keysize))ROM_AESTABLE[16]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_AESKey2Set \ ((void (*)(uint32_t ui32Base, \ uint32_t *pui32Key, \ uint32_t ui32Keysize))ROM_AESTABLE[17]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_AESKey3Set \ ((void (*)(uint32_t ui32Base, \ uint32_t *pui32Key))ROM_AESTABLE[18]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_AESLengthSet \ ((void (*)(uint32_t ui32Base, \ uint64_t ui64Length))ROM_AESTABLE[19]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_AESReset \ ((void (*)(uint32_t ui32Base))ROM_AESTABLE[20]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_AESTagRead \ ((void (*)(uint32_t ui32Base, \ uint32_t *pui32TagData))ROM_AESTABLE[21]) #endif -#if defined(TARGET_IS_TM4C129_RA1) +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_AESIVRead \ ((void (*)(uint32_t ui32Base, \ uint32_t *pui32IVdata))ROM_AESTABLE[22]) @@ -562,8 +640,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_CANIntClear \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32IntClr))ROM_CANTABLE[0]) @@ -571,32 +651,40 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_CANInit \ ((void (*)(uint32_t ui32Base))ROM_CANTABLE[1]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_CANEnable \ ((void (*)(uint32_t ui32Base))ROM_CANTABLE[2]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_CANDisable \ ((void (*)(uint32_t ui32Base))ROM_CANTABLE[3]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_CANBitTimingSet \ ((void (*)(uint32_t ui32Base, \ tCANBitClkParms *psClkParms))ROM_CANTABLE[4]) @@ -604,8 +692,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_CANBitTimingGet \ ((void (*)(uint32_t ui32Base, \ tCANBitClkParms *psClkParms))ROM_CANTABLE[5]) @@ -613,8 +703,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_CANMessageSet \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32ObjID, \ @@ -624,8 +716,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_CANMessageGet \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32ObjID, \ @@ -635,8 +729,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_CANStatusGet \ ((uint32_t (*)(uint32_t ui32Base, \ tCANStsReg eStatusReg))ROM_CANTABLE[8]) @@ -644,8 +740,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_CANMessageClear \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32ObjID))ROM_CANTABLE[9]) @@ -653,8 +751,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_CANIntEnable \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32IntFlags))ROM_CANTABLE[10]) @@ -662,8 +762,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_CANIntDisable \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32IntFlags))ROM_CANTABLE[11]) @@ -671,8 +773,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_CANIntStatus \ ((uint32_t (*)(uint32_t ui32Base, \ tCANIntStsReg eIntStsReg))ROM_CANTABLE[12]) @@ -680,16 +784,20 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_CANRetryGet \ ((bool (*)(uint32_t ui32Base))ROM_CANTABLE[13]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_CANRetrySet \ ((void (*)(uint32_t ui32Base, \ bool bAutoRetry))ROM_CANTABLE[14]) @@ -697,8 +805,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_CANErrCntrGet \ ((bool (*)(uint32_t ui32Base, \ uint32_t *pui32RxCount, \ @@ -707,8 +817,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_CANBitRateSet \ ((uint32_t (*)(uint32_t ui32Base, \ uint32_t ui32SourceClock, \ @@ -723,8 +835,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_ComparatorIntClear \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32Comp))ROM_COMPARATORTABLE[0]) @@ -732,8 +846,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_ComparatorConfigure \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32Comp, \ @@ -742,8 +858,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_ComparatorRefSet \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32Ref))ROM_COMPARATORTABLE[2]) @@ -751,8 +869,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_ComparatorValueGet \ ((bool (*)(uint32_t ui32Base, \ uint32_t ui32Comp))ROM_COMPARATORTABLE[3]) @@ -760,8 +880,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_ComparatorIntEnable \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32Comp))ROM_COMPARATORTABLE[4]) @@ -769,8 +891,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_ComparatorIntDisable \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32Comp))ROM_COMPARATORTABLE[5]) @@ -778,8 +902,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_ComparatorIntStatus \ ((bool (*)(uint32_t ui32Base, \ uint32_t ui32Comp, \ @@ -792,13 +918,15 @@ // //***************************************************************************** #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_CRCConfigSet \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32CRCConfig))ROM_CRCTABLE[0]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_CRCDataProcess \ ((uint32_t (*)(uint32_t ui32Base, \ uint32_t *pui32DataIn, \ @@ -806,19 +934,22 @@ bool bPPResult))ROM_CRCTABLE[1]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_CRCDataWrite \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32Data))ROM_CRCTABLE[2]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_CRCResultRead \ ((uint32_t (*)(uint32_t ui32Base, \ bool bPPResult))ROM_CRCTABLE[3]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_CRCSeedSet \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32Seed))ROM_CRCTABLE[4]) @@ -830,31 +961,36 @@ // //***************************************************************************** #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_DESIntStatus \ ((uint32_t (*)(uint32_t ui32Base, \ bool bMasked))ROM_DESTABLE[0]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_DESConfigSet \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32Config))ROM_DESTABLE[1]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_DESDataRead \ ((void (*)(uint32_t ui32Base, \ uint32_t *pui32Dest))ROM_DESTABLE[2]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_DESDataReadNonBlocking \ ((bool (*)(uint32_t ui32Base, \ uint32_t *pui32Dest))ROM_DESTABLE[3]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_DESDataProcess \ ((bool (*)(uint32_t ui32Base, \ uint32_t *pui32Src, \ @@ -862,67 +998,78 @@ uint32_t ui32Length))ROM_DESTABLE[4]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_DESDataWrite \ ((void (*)(uint32_t ui32Base, \ uint32_t *pui32Src))ROM_DESTABLE[5]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_DESDataWriteNonBlocking \ ((bool (*)(uint32_t ui32Base, \ uint32_t *pui32Src))ROM_DESTABLE[6]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_DESDMADisable \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32Flags))ROM_DESTABLE[7]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_DESDMAEnable \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32Flags))ROM_DESTABLE[8]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_DESIntClear \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32IntFlags))ROM_DESTABLE[9]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_DESIntDisable \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32IntFlags))ROM_DESTABLE[10]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_DESIntEnable \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32IntFlags))ROM_DESTABLE[11]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_DESIVSet \ ((bool (*)(uint32_t ui32Base, \ uint32_t *pui32IVdata))ROM_DESTABLE[12]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_DESKeySet \ ((void (*)(uint32_t ui32Base, \ uint32_t *pui32Key))ROM_DESTABLE[13]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_DESLengthSet \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32Length))ROM_DESTABLE[14]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_DESReset \ ((void (*)(uint32_t ui32Base))ROM_DESTABLE[15]) #endif @@ -934,8 +1081,10 @@ //***************************************************************************** #if defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_EEPROMRead \ ((void (*)(uint32_t *pui32Data, \ uint32_t ui32Address, \ @@ -943,29 +1092,37 @@ #endif #if defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_EEPROMBlockCountGet \ ((uint32_t (*)(void))ROM_EEPROMTABLE[1]) #endif #if defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_EEPROMBlockHide \ ((void (*)(uint32_t ui32Block))ROM_EEPROMTABLE[2]) #endif #if defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_EEPROMBlockLock \ ((uint32_t (*)(uint32_t ui32Block))ROM_EEPROMTABLE[3]) #endif #if defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_EEPROMBlockPasswordSet \ ((uint32_t (*)(uint32_t ui32Block, \ uint32_t *pui32Password, \ @@ -973,23 +1130,29 @@ #endif #if defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_EEPROMBlockProtectGet \ ((uint32_t (*)(uint32_t ui32Block))ROM_EEPROMTABLE[5]) #endif #if defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_EEPROMBlockProtectSet \ ((uint32_t (*)(uint32_t ui32Block, \ uint32_t ui32Protect))ROM_EEPROMTABLE[6]) #endif #if defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_EEPROMBlockUnlock \ ((uint32_t (*)(uint32_t ui32Block, \ uint32_t *pui32Password, \ @@ -997,29 +1160,37 @@ #endif #if defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_EEPROMIntClear \ ((void (*)(uint32_t ui32IntFlags))ROM_EEPROMTABLE[8]) #endif #if defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_EEPROMIntDisable \ ((void (*)(uint32_t ui32IntFlags))ROM_EEPROMTABLE[9]) #endif #if defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_EEPROMIntEnable \ ((void (*)(uint32_t ui32IntFlags))ROM_EEPROMTABLE[10]) #endif #if defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_EEPROMIntStatus \ ((uint32_t (*)(bool bMasked))ROM_EEPROMTABLE[11]) #endif @@ -1030,8 +1201,10 @@ #endif #if defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_EEPROMProgram \ ((uint32_t (*)(uint32_t *pui32Data, \ uint32_t ui32Address, \ @@ -1039,30 +1212,38 @@ #endif #if defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_EEPROMProgramNonBlocking \ ((uint32_t (*)(uint32_t ui32Data, \ uint32_t ui32Address))ROM_EEPROMTABLE[14]) #endif #if defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_EEPROMSizeGet \ ((uint32_t (*)(void))ROM_EEPROMTABLE[15]) #endif #if defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_EEPROMStatusGet \ ((uint32_t (*)(void))ROM_EEPROMTABLE[16]) #endif #if defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_EEPROMInit \ ((uint32_t (*)(void))ROM_EEPROMTABLE[17]) #endif @@ -1073,32 +1254,37 @@ // //***************************************************************************** #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_EPIIntStatus \ ((uint32_t (*)(uint32_t ui32Base, \ bool bMasked))ROM_EPITABLE[0]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_EPIModeSet \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32Mode))ROM_EPITABLE[1]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_EPIDividerSet \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32Divider))ROM_EPITABLE[2]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_EPIConfigSDRAMSet \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32Config, \ uint32_t ui32Refresh))ROM_EPITABLE[3]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_EPIConfigGPModeSet \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32Config, \ @@ -1106,27 +1292,31 @@ uint32_t ui32MaxWait))ROM_EPITABLE[4]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_EPIConfigHB8Set \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32Config, \ uint32_t ui32MaxWait))ROM_EPITABLE[5]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_EPIConfigHB16Set \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32Config, \ uint32_t ui32MaxWait))ROM_EPITABLE[6]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_EPIAddressMapSet \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32Map))ROM_EPITABLE[7]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_EPINonBlockingReadConfigure \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32Channel, \ @@ -1134,147 +1324,170 @@ uint32_t ui32Address))ROM_EPITABLE[8]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_EPINonBlockingReadStart \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32Channel, \ uint32_t ui32Count))ROM_EPITABLE[9]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_EPINonBlockingReadStop \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32Channel))ROM_EPITABLE[10]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_EPINonBlockingReadCount \ ((uint32_t (*)(uint32_t ui32Base, \ uint32_t ui32Channel))ROM_EPITABLE[11]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_EPINonBlockingReadAvail \ ((uint32_t (*)(uint32_t ui32Base))ROM_EPITABLE[12]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_EPINonBlockingReadGet32 \ ((uint32_t (*)(uint32_t ui32Base, \ uint32_t ui32Count, \ uint32_t *pui32Buf))ROM_EPITABLE[13]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_EPINonBlockingReadGet16 \ ((uint32_t (*)(uint32_t ui32Base, \ uint32_t ui32Count, \ uint16_t *pui16Buf))ROM_EPITABLE[14]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_EPINonBlockingReadGet8 \ ((uint32_t (*)(uint32_t ui32Base, \ uint32_t ui32Count, \ uint8_t *pui8Buf))ROM_EPITABLE[15]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_EPIFIFOConfig \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32Config))ROM_EPITABLE[16]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_EPIWriteFIFOCountGet \ ((uint32_t (*)(uint32_t ui32Base))ROM_EPITABLE[17]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_EPIIntEnable \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32IntFlags))ROM_EPITABLE[18]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_EPIIntDisable \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32IntFlags))ROM_EPITABLE[19]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_EPIIntErrorStatus \ ((uint32_t (*)(uint32_t ui32Base))ROM_EPITABLE[20]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_EPIIntErrorClear \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32ErrFlags))ROM_EPITABLE[21]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_EPIDividerCSSet \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32CS, \ uint32_t ui32Divider))ROM_EPITABLE[22]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_EPIDMATxCount \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32Count))ROM_EPITABLE[23]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_EPIConfigHB8CSSet \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32CS, \ uint32_t ui32Config))ROM_EPITABLE[24]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_EPIConfigHB16CSSet \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32CS, \ uint32_t ui32Config))ROM_EPITABLE[25]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_EPIConfigHB8TimingSet \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32CS, \ uint32_t ui32Config))ROM_EPITABLE[26]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_EPIConfigHB16TimingSet \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32CS, \ uint32_t ui32Config))ROM_EPITABLE[27]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_EPIPSRAMConfigRegSet \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32CS, \ uint32_t ui32CR))ROM_EPITABLE[28]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_EPIPSRAMConfigRegRead \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32CS))ROM_EPITABLE[29]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_EPIPSRAMConfigRegGetNonBlocking \ ((bool (*)(uint32_t ui32Base, \ uint32_t ui32CS, \ uint32_t *pui32CR))ROM_EPITABLE[30]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_EPIPSRAMConfigRegGet \ ((uint32_t (*)(uint32_t ui32Base, \ uint32_t ui32CS))ROM_EPITABLE[31]) @@ -1286,27 +1499,31 @@ // //***************************************************************************** #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_EMACIntStatus \ ((uint32_t (*)(uint32_t ui32Base, \ bool bMasked))ROM_EMACTABLE[0]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_EMACAddrGet \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32Index, \ uint8_t *pui8MACAddr))ROM_EMACTABLE[1]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_EMACAddrSet \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32Index, \ const uint8_t *pui8MACAddr))ROM_EMACTABLE[2]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_EMACConfigGet \ ((void (*)(uint32_t ui32Base, \ uint32_t *pui32Config, \ @@ -1314,7 +1531,8 @@ uint32_t *pui32RxMaxFrameSize))ROM_EMACTABLE[3]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_EMACConfigSet \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32Config, \ @@ -1322,23 +1540,26 @@ uint32_t ui32RxMaxFrameSize))ROM_EMACTABLE[4]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_EMACDMAStateGet \ ((uint32_t (*)(uint32_t ui32Base))ROM_EMACTABLE[5]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_EMACFrameFilterGet \ ((uint32_t (*)(uint32_t ui32Base))ROM_EMACTABLE[6]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_EMACFrameFilterSet \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32FilterOpts))ROM_EMACTABLE[7]) #endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_EMACInit \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32SysClk, \ @@ -1348,49 +1569,57 @@ uint32_t ui32DescSkipSize))ROM_EMACTABLE[8]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_EMACIntClear \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32IntFlags))ROM_EMACTABLE[9]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_EMACIntDisable \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32IntFlags))ROM_EMACTABLE[10]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_EMACIntEnable \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32IntFlags))ROM_EMACTABLE[11]) #endif -#if defined(TARGET_IS_TM4C129_RA1) +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_EMACPHYConfigSet \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32Config))ROM_EMACTABLE[12]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_EMACPHYPowerOff \ ((void (*)(uint32_t ui32Base, \ uint8_t ui8PhyAddr))ROM_EMACTABLE[13]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_EMACPHYPowerOn \ ((void (*)(uint32_t ui32Base, \ uint8_t ui8PhyAddr))ROM_EMACTABLE[14]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_EMACPHYRead \ ((uint16_t (*)(uint32_t ui32Base, \ uint8_t ui8PhyAddr, \ uint8_t ui8RegAddr))ROM_EMACTABLE[15]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_EMACPHYWrite \ ((void (*)(uint32_t ui32Base, \ uint8_t ui8PhyAddr, \ @@ -1398,284 +1627,339 @@ uint16_t ui16Data))ROM_EMACTABLE[16]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_EMACReset \ ((void (*)(uint32_t ui32Base))ROM_EMACTABLE[17]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_EMACRxDisable \ ((void (*)(uint32_t ui32Base))ROM_EMACTABLE[18]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_EMACRxDMACurrentBufferGet \ ((uint8_t * (*)(uint32_t ui32Base))ROM_EMACTABLE[19]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_EMACRxDMACurrentDescriptorGet \ ((tEMACDMADescriptor * (*)(uint32_t ui32Base))ROM_EMACTABLE[20]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_EMACRxDMADescriptorListGet \ ((tEMACDMADescriptor * (*)(uint32_t ui32Base))ROM_EMACTABLE[21]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_EMACRxDMADescriptorListSet \ ((void (*)(uint32_t ui32Base, \ tEMACDMADescriptor *pDescriptor))ROM_EMACTABLE[22]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_EMACRxDMAPollDemand \ ((void (*)(uint32_t ui32Base))ROM_EMACTABLE[23]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_EMACRxEnable \ ((void (*)(uint32_t ui32Base))ROM_EMACTABLE[24]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_EMACRxWatchdogTimerSet \ ((void (*)(uint32_t ui32Base, \ uint8_t ui8Timeout))ROM_EMACTABLE[25]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_EMACStatusGet \ ((uint32_t (*)(uint32_t ui32Base))ROM_EMACTABLE[26]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_EMACTxDisable \ ((void (*)(uint32_t ui32Base))ROM_EMACTABLE[27]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_EMACTxDMACurrentBufferGet \ ((uint8_t * (*)(uint32_t ui32Base))ROM_EMACTABLE[28]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_EMACTxDMACurrentDescriptorGet \ ((tEMACDMADescriptor * (*)(uint32_t ui32Base))ROM_EMACTABLE[29]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_EMACTxDMADescriptorListGet \ ((tEMACDMADescriptor * (*)(uint32_t ui32Base))ROM_EMACTABLE[30]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_EMACTxDMADescriptorListSet \ ((void (*)(uint32_t ui32Base, \ tEMACDMADescriptor *pDescriptor))ROM_EMACTABLE[31]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_EMACTxDMAPollDemand \ ((void (*)(uint32_t ui32Base))ROM_EMACTABLE[32]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_EMACTxEnable \ ((void (*)(uint32_t ui32Base))ROM_EMACTABLE[33]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_EMACTxFlush \ ((void (*)(uint32_t ui32Base))ROM_EMACTABLE[34]) #endif -#if defined(TARGET_IS_TM4C129_RA1) +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_EMACAddrFilterGet \ ((uint32_t (*)(uint32_t ui32Base, \ uint32_t ui32Index))ROM_EMACTABLE[35]) #endif -#if defined(TARGET_IS_TM4C129_RA1) +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_EMACAddrFilterSet \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32Index, \ uint32_t ui32Config))ROM_EMACTABLE[36]) #endif -#if defined(TARGET_IS_TM4C129_RA1) +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_EMACHashFilterBitCalculate \ ((uint32_t (*)(uint8_t *pui8MACAddr))ROM_EMACTABLE[37]) #endif -#if defined(TARGET_IS_TM4C129_RA1) +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_EMACHashFilterGet \ ((void (*)(uint32_t ui32Base, \ uint32_t *pui32HashHi, \ uint32_t *pui32HashLo))ROM_EMACTABLE[38]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_EMACHashFilterSet \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32HashHi, \ uint32_t ui32HashLo))ROM_EMACTABLE[39]) #endif -#if defined(TARGET_IS_TM4C129_RA1) +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_EMACNumAddrGet \ ((uint32_t (*)(uint32_t ui32Base))ROM_EMACTABLE[40]) #endif -#if defined(TARGET_IS_TM4C129_RA1) +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_EMACPHYExtendedRead \ ((uint16_t (*)(uint32_t ui32Base, \ uint8_t ui8PhyAddr, \ uint16_t ui16RegAddr))ROM_EMACTABLE[41]) #endif -#if defined(TARGET_IS_TM4C129_RA1) +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_EMACPHYExtendedWrite \ ((void (*)(uint32_t ui32Base, \ uint8_t ui8PhyAddr, \ uint16_t ui16RegAddr, \ uint16_t ui16Data))ROM_EMACTABLE[42]) #endif -#if defined(TARGET_IS_TM4C129_RA1) +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_EMACPowerManagementControlGet \ ((uint32_t (*)(uint32_t ui32Base))ROM_EMACTABLE[43]) #endif -#if defined(TARGET_IS_TM4C129_RA1) +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_EMACPowerManagementControlSet \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32Flags))ROM_EMACTABLE[44]) #endif -#if defined(TARGET_IS_TM4C129_RA1) +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_EMACPowerManagementStatusGet \ ((uint32_t (*)(uint32_t ui32Base))ROM_EMACTABLE[45]) #endif -#if defined(TARGET_IS_TM4C129_RA1) +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_EMACRemoteWakeUpFrameFilterGet \ ((void (*)(uint32_t ui32Base, \ tEMACWakeUpFrameFilter *pFilter))ROM_EMACTABLE[46]) #endif -#if defined(TARGET_IS_TM4C129_RA1) +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_EMACRemoteWakeUpFrameFilterSet \ ((void (*)(uint32_t ui32Base, \ const tEMACWakeUpFrameFilter *pFilter))ROM_EMACTABLE[47]) #endif -#if defined(TARGET_IS_TM4C129_RA1) +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_EMACTimestampAddendSet \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32Seconds))ROM_EMACTABLE[48]) #endif -#if defined(TARGET_IS_TM4C129_RA1) +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_EMACTimestampConfigGet \ ((uint32_t (*)(uint32_t ui32Base, \ uint32_t *pui32SubSecondInc))ROM_EMACTABLE[49]) #endif -#if defined(TARGET_IS_TM4C129_RA1) +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_EMACTimestampConfigSet \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32Config, \ uint32_t ui32SubSecondInc))ROM_EMACTABLE[50]) #endif -#if defined(TARGET_IS_TM4C129_RA1) +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_EMACTimestampDisable \ ((void (*)(uint32_t ui32Base))ROM_EMACTABLE[51]) #endif -#if defined(TARGET_IS_TM4C129_RA1) +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_EMACTimestampEnable \ ((void (*)(uint32_t ui32Base))ROM_EMACTABLE[52]) #endif -#if defined(TARGET_IS_TM4C129_RA1) +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_EMACTimestampIntStatus \ ((uint32_t (*)(uint32_t ui32Base))ROM_EMACTABLE[53]) #endif -#if defined(TARGET_IS_TM4C129_RA1) +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_EMACTimestampPPSCommand \ ((void (*)(uint32_t ui32Base, \ uint8_t ui8Cmd))ROM_EMACTABLE[54]) #endif -#if defined(TARGET_IS_TM4C129_RA1) +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_EMACTimestampPPSCommandModeSet \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32Config))ROM_EMACTABLE[55]) #endif -#if defined(TARGET_IS_TM4C129_RA1) +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_EMACTimestampPPSPeriodSet \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32Period, \ uint32_t ui32Width))ROM_EMACTABLE[56]) #endif -#if defined(TARGET_IS_TM4C129_RA1) +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_EMACTimestampPPSSimpleModeSet \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32FreqConfig))ROM_EMACTABLE[57]) #endif -#if defined(TARGET_IS_TM4C129_RA1) +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_EMACTimestampSysTimeGet \ ((void (*)(uint32_t ui32Base, \ uint32_t *pui32Seconds, \ uint32_t *pui32SubSeconds))ROM_EMACTABLE[58]) #endif -#if defined(TARGET_IS_TM4C129_RA1) +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_EMACTimestampSysTimeSet \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32Seconds, \ uint32_t ui32SubSeconds))ROM_EMACTABLE[59]) #endif -#if defined(TARGET_IS_TM4C129_RA1) +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_EMACTimestampSysTimeUpdate \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32Seconds, \ uint32_t ui32SubSeconds, \ bool bInc))ROM_EMACTABLE[60]) #endif -#if defined(TARGET_IS_TM4C129_RA1) +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_EMACTimestampTargetIntDisable \ ((void (*)(uint32_t ui32Base))ROM_EMACTABLE[61]) #endif -#if defined(TARGET_IS_TM4C129_RA1) +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_EMACTimestampTargetIntEnable \ ((void (*)(uint32_t ui32Base))ROM_EMACTABLE[62]) #endif -#if defined(TARGET_IS_TM4C129_RA1) +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_EMACTimestampTargetSet \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32Seconds, \ uint32_t ui32Nanoseconds))ROM_EMACTABLE[63]) #endif -#if defined(TARGET_IS_TM4C129_RA1) +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_EMACVLANHashFilterBitCalculate \ ((uint32_t (*)(uint16_t ui16Tag))ROM_EMACTABLE[64]) #endif -#if defined(TARGET_IS_TM4C129_RA1) +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_EMACVLANHashFilterGet \ ((uint32_t (*)(uint32_t ui32Base))ROM_EMACTABLE[65]) #endif -#if defined(TARGET_IS_TM4C129_RA1) +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_EMACVLANHashFilterSet \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32Hash))ROM_EMACTABLE[66]) #endif -#if defined(TARGET_IS_TM4C129_RA1) +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_EMACVLANRxConfigGet \ ((uint32_t (*)(uint32_t ui32Base, \ uint16_t *pui16Tag))ROM_EMACTABLE[67]) #endif -#if defined(TARGET_IS_TM4C129_RA1) +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_EMACVLANRxConfigSet \ ((void (*)(uint32_t ui32Base, \ uint16_t ui16Tag, \ uint32_t ui32Config))ROM_EMACTABLE[68]) #endif -#if defined(TARGET_IS_TM4C129_RA1) +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_EMACVLANTxConfigGet \ ((uint32_t (*)(uint32_t ui32Base, \ uint16_t *pui16Tag))ROM_EMACTABLE[69]) #endif -#if defined(TARGET_IS_TM4C129_RA1) +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_EMACVLANTxConfigSet \ ((void (*)(uint32_t ui32Base, \ uint16_t ui16Tag, \ uint32_t ui32Config))ROM_EMACTABLE[70]) #endif -#if defined(TARGET_IS_TM4C129_RA1) +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_UpdateEMAC \ ((void (*)(uint32_t ui32Clock))ROM_EMACTABLE[71]) #endif @@ -1688,8 +1972,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_FlashProgram \ ((int32_t (*)(uint32_t *pui32Data, \ uint32_t ui32Address, \ @@ -1698,24 +1984,30 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_FlashErase \ ((int32_t (*)(uint32_t ui32Address))ROM_FLASHTABLE[3]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_FlashProtectGet \ ((tFlashProtection (*)(uint32_t ui32Address))ROM_FLASHTABLE[4]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_FlashProtectSet \ ((int32_t (*)(uint32_t ui32Address, \ tFlashProtection eProtect))ROM_FLASHTABLE[5]) @@ -1723,16 +2015,20 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_FlashProtectSave \ ((int32_t (*)(void))ROM_FLASHTABLE[6]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_FlashUserGet \ ((int32_t (*)(uint32_t *pui32User0, \ uint32_t *pui32User1))ROM_FLASHTABLE[7]) @@ -1740,8 +2036,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_FlashUserSet \ ((int32_t (*)(uint32_t ui32User0, \ uint32_t ui32User1))ROM_FLASHTABLE[8]) @@ -1749,40 +2047,50 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_FlashUserSave \ ((int32_t (*)(void))ROM_FLASHTABLE[9]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_FlashIntEnable \ ((void (*)(uint32_t ui32IntFlags))ROM_FLASHTABLE[10]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_FlashIntDisable \ ((void (*)(uint32_t ui32IntFlags))ROM_FLASHTABLE[11]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_FlashIntStatus \ ((uint32_t (*)(bool bMasked))ROM_FLASHTABLE[12]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_FlashIntClear \ ((void (*)(uint32_t ui32IntFlags))ROM_FLASHTABLE[13]) #endif @@ -1795,72 +2103,90 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_FPUEnable \ ((void (*)(void))ROM_FPUTABLE[0]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_FPUDisable \ ((void (*)(void))ROM_FPUTABLE[1]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_FPUFlushToZeroModeSet \ ((void (*)(uint32_t ui32Mode))ROM_FPUTABLE[2]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_FPUHalfPrecisionModeSet \ ((void (*)(uint32_t ui32Mode))ROM_FPUTABLE[3]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_FPULazyStackingEnable \ ((void (*)(void))ROM_FPUTABLE[4]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_FPUNaNModeSet \ ((void (*)(uint32_t ui32Mode))ROM_FPUTABLE[5]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_FPURoundingModeSet \ ((void (*)(uint32_t ui32Mode))ROM_FPUTABLE[6]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_FPUStackingDisable \ ((void (*)(void))ROM_FPUTABLE[7]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_FPUStackingEnable \ ((void (*)(void))ROM_FPUTABLE[8]) #endif @@ -1873,8 +2199,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_GPIOPinWrite \ ((void (*)(uint32_t ui32Port, \ uint8_t ui8Pins, \ @@ -1883,8 +2211,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_GPIODirModeSet \ ((void (*)(uint32_t ui32Port, \ uint8_t ui8Pins, \ @@ -1893,8 +2223,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_GPIODirModeGet \ ((uint32_t (*)(uint32_t ui32Port, \ uint8_t ui8Pin))ROM_GPIOTABLE[2]) @@ -1902,8 +2234,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_GPIOIntTypeSet \ ((void (*)(uint32_t ui32Port, \ uint8_t ui8Pins, \ @@ -1912,15 +2246,18 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_GPIOIntTypeGet \ ((uint32_t (*)(uint32_t ui32Port, \ uint8_t ui8Pin))ROM_GPIOTABLE[4]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) #define ROM_GPIOPadConfigSet \ ((void (*)(uint32_t ui32Port, \ uint8_t ui8Pins, \ @@ -1930,8 +2267,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_GPIOPadConfigGet \ ((void (*)(uint32_t ui32Port, \ uint8_t ui8Pin, \ @@ -1941,15 +2280,18 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_GPIOPinRead \ ((int32_t (*)(uint32_t ui32Port, \ uint8_t ui8Pins))ROM_GPIOTABLE[11]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) #define ROM_GPIOPinTypeCAN \ ((void (*)(uint32_t ui32Port, \ uint8_t ui8Pins))ROM_GPIOTABLE[12]) @@ -1957,8 +2299,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_GPIOPinTypeComparator \ ((void (*)(uint32_t ui32Port, \ uint8_t ui8Pins))ROM_GPIOTABLE[13]) @@ -1966,8 +2310,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_GPIOPinTypeGPIOInput \ ((void (*)(uint32_t ui32Port, \ uint8_t ui8Pins))ROM_GPIOTABLE[14]) @@ -1975,8 +2321,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_GPIOPinTypeGPIOOutput \ ((void (*)(uint32_t ui32Port, \ uint8_t ui8Pins))ROM_GPIOTABLE[15]) @@ -1984,8 +2332,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_GPIOPinTypeI2C \ ((void (*)(uint32_t ui32Port, \ uint8_t ui8Pins))ROM_GPIOTABLE[16]) @@ -1993,8 +2343,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_GPIOPinTypePWM \ ((void (*)(uint32_t ui32Port, \ uint8_t ui8Pins))ROM_GPIOTABLE[17]) @@ -2002,8 +2354,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_GPIOPinTypeQEI \ ((void (*)(uint32_t ui32Port, \ uint8_t ui8Pins))ROM_GPIOTABLE[18]) @@ -2011,8 +2365,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_GPIOPinTypeSSI \ ((void (*)(uint32_t ui32Port, \ uint8_t ui8Pins))ROM_GPIOTABLE[19]) @@ -2020,8 +2376,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_GPIOPinTypeTimer \ ((void (*)(uint32_t ui32Port, \ uint8_t ui8Pins))ROM_GPIOTABLE[20]) @@ -2029,8 +2387,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_GPIOPinTypeUART \ ((void (*)(uint32_t ui32Port, \ uint8_t ui8Pins))ROM_GPIOTABLE[21]) @@ -2038,8 +2398,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_GPIOPinTypeGPIOOutputOD \ ((void (*)(uint32_t ui32Port, \ uint8_t ui8Pins))ROM_GPIOTABLE[22]) @@ -2047,8 +2409,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_GPIOPinTypeADC \ ((void (*)(uint32_t ui32Port, \ uint8_t ui8Pins))ROM_GPIOTABLE[23]) @@ -2056,8 +2420,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_GPIOPinTypeUSBDigital \ ((void (*)(uint32_t ui32Port, \ uint8_t ui8Pins))ROM_GPIOTABLE[24]) @@ -2065,16 +2431,20 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_GPIOPinConfigure \ ((void (*)(uint32_t ui32PinConfig))ROM_GPIOTABLE[26]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_GPIOPinTypeUSBAnalog \ ((void (*)(uint32_t ui32Port, \ uint8_t ui8Pins))ROM_GPIOTABLE[28]) @@ -2082,8 +2452,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_GPIODMATriggerEnable \ ((void (*)(uint32_t ui32Port, \ uint8_t ui8Pins))ROM_GPIOTABLE[31]) @@ -2091,8 +2463,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_GPIODMATriggerDisable \ ((void (*)(uint32_t ui32Port, \ uint8_t ui8Pins))ROM_GPIOTABLE[32]) @@ -2100,8 +2474,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_GPIOADCTriggerEnable \ ((void (*)(uint32_t ui32Port, \ uint8_t ui8Pins))ROM_GPIOTABLE[33]) @@ -2109,67 +2485,73 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_GPIOADCTriggerDisable \ ((void (*)(uint32_t ui32Port, \ uint8_t ui8Pins))ROM_GPIOTABLE[34]) #endif #if defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_GPIOPinTypeI2CSCL \ ((void (*)(uint32_t ui32Port, \ uint8_t ui8Pins))ROM_GPIOTABLE[39]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_GPIOPinTypeOneWire \ ((void (*)(uint32_t ui32Port, \ uint8_t ui8Pins))ROM_GPIOTABLE[44]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_GPIOPinTypeWakeHigh \ ((void (*)(uint32_t ui32Port, \ uint8_t ui8Pins))ROM_GPIOTABLE[48]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_GPIOPinTypeWakeLow \ ((void (*)(uint32_t ui32Port, \ uint8_t ui8Pins))ROM_GPIOTABLE[49]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_GPIOIntClear \ ((void (*)(uint32_t ui32Port, \ uint32_t ui32IntFlags))ROM_GPIOTABLE[51]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_GPIOIntDisable \ ((void (*)(uint32_t ui32Port, \ uint32_t ui32IntFlags))ROM_GPIOTABLE[52]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_GPIOIntEnable \ ((void (*)(uint32_t ui32Port, \ uint32_t ui32IntFlags))ROM_GPIOTABLE[53]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_GPIOIntStatus \ ((uint32_t (*)(uint32_t ui32Port, \ bool bMasked))ROM_GPIOTABLE[54]) #endif -#if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) -#define ROM_GPIOPinWakeStatus \ - ((uint32_t (*)(uint32_t ui32Port))ROM_GPIOTABLE[55]) -#endif //***************************************************************************** // @@ -2179,112 +2561,140 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_HibernateIntClear \ ((void (*)(uint32_t ui32IntFlags))ROM_HIBERNATETABLE[0]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_HibernateEnableExpClk \ ((void (*)(uint32_t ui32HibClk))ROM_HIBERNATETABLE[1]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_HibernateDisable \ ((void (*)(void))ROM_HIBERNATETABLE[2]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_HibernateRTCEnable \ ((void (*)(void))ROM_HIBERNATETABLE[4]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_HibernateRTCDisable \ ((void (*)(void))ROM_HIBERNATETABLE[5]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_HibernateWakeSet \ ((void (*)(uint32_t ui32WakeFlags))ROM_HIBERNATETABLE[6]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_HibernateWakeGet \ ((uint32_t (*)(void))ROM_HIBERNATETABLE[7]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_HibernateLowBatSet \ ((void (*)(uint32_t ui32LowBatFlags))ROM_HIBERNATETABLE[8]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_HibernateLowBatGet \ ((uint32_t (*)(void))ROM_HIBERNATETABLE[9]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_HibernateRTCSet \ ((void (*)(uint32_t ui32RTCValue))ROM_HIBERNATETABLE[10]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_HibernateRTCGet \ ((uint32_t (*)(void))ROM_HIBERNATETABLE[11]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_HibernateRTCTrimSet \ ((void (*)(uint32_t ui32Trim))ROM_HIBERNATETABLE[16]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_HibernateRTCTrimGet \ ((uint32_t (*)(void))ROM_HIBERNATETABLE[17]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_HibernateDataSet \ ((void (*)(uint32_t *pui32Data, \ uint32_t ui32Count))ROM_HIBERNATETABLE[18]) @@ -2292,8 +2702,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_HibernateDataGet \ ((void (*)(uint32_t *pui32Data, \ uint32_t ui32Count))ROM_HIBERNATETABLE[19]) @@ -2301,186 +2713,226 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_HibernateRequest \ ((void (*)(void))ROM_HIBERNATETABLE[20]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_HibernateIntEnable \ ((void (*)(uint32_t ui32IntFlags))ROM_HIBERNATETABLE[21]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_HibernateIntDisable \ ((void (*)(uint32_t ui32IntFlags))ROM_HIBERNATETABLE[22]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_HibernateIntStatus \ ((uint32_t (*)(bool bMasked))ROM_HIBERNATETABLE[23]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_HibernateIsActive \ ((uint32_t (*)(void))ROM_HIBERNATETABLE[24]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_HibernateRTCSSGet \ ((uint32_t (*)(void))ROM_HIBERNATETABLE[27]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_HibernateClockConfig \ ((void (*)(uint32_t ui32Config))ROM_HIBERNATETABLE[28]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_HibernateBatCheckStart \ ((void (*)(void))ROM_HIBERNATETABLE[29]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_HibernateBatCheckDone \ ((uint32_t (*)(void))ROM_HIBERNATETABLE[30]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_HibernateGPIORetentionEnable \ ((void (*)(void))ROM_HIBERNATETABLE[31]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_HibernateGPIORetentionDisable \ ((void (*)(void))ROM_HIBERNATETABLE[32]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_HibernateGPIORetentionGet \ ((bool (*)(void))ROM_HIBERNATETABLE[33]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_HibernateCounterMode \ ((void (*)(uint32_t ui32Config))ROM_HIBERNATETABLE[34]) #endif #if defined(TARGET_IS_TM4C123_RB1) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_HibernateCalendarSet \ ((void (*)(struct tm *psTime))ROM_HIBERNATETABLE[35]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_HibernateCalendarGet \ ((int (*)(struct tm *psTime))ROM_HIBERNATETABLE[36]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_HibernateCalendarMatchSet \ ((void (*)(uint32_t ui32Index, \ struct tm *psTime))ROM_HIBERNATETABLE[37]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_HibernateCalendarMatchGet \ ((void (*)(uint32_t ui32Index, \ struct tm *psTime))ROM_HIBERNATETABLE[38]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_HibernateTamperDisable \ ((void (*)(void))ROM_HIBERNATETABLE[39]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_HibernateTamperEnable \ ((void (*)(void))ROM_HIBERNATETABLE[40]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_HibernateTamperEventsClear \ ((void (*)(void))ROM_HIBERNATETABLE[41]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_HibernateTamperEventsConfig \ ((void (*)(uint32_t ui32Config))ROM_HIBERNATETABLE[42]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_HibernateTamperEventsGet \ ((bool (*)(uint32_t ui32Index, \ uint32_t *pui32RTC, \ uint32_t *pui32Event))ROM_HIBERNATETABLE[43]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_HibernateTamperExtOscValid \ ((bool (*)(void))ROM_HIBERNATETABLE[44]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_HibernateTamperExtOscRecover \ ((void (*)(void))ROM_HIBERNATETABLE[45]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_HibernateTamperIODisable \ ((void (*)(uint32_t ui32Input))ROM_HIBERNATETABLE[46]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_HibernateTamperIOEnable \ ((void (*)(uint32_t ui32Input, \ uint32_t ui32Config))ROM_HIBERNATETABLE[47]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_HibernateTamperStatusGet \ ((uint32_t (*)(void))ROM_HIBERNATETABLE[48]) #endif -#if defined(TARGET_IS_TM4C129_RA1) +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_HibernateRTCMatchGet \ ((uint32_t (*)(uint32_t ui32Match))ROM_HIBERNATETABLE[49]) #endif -#if defined(TARGET_IS_TM4C129_RA1) +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_HibernateRTCMatchSet \ ((void (*)(uint32_t ui32Match, \ uint32_t ui32Value))ROM_HIBERNATETABLE[50]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_HibernateRTCSSMatchGet \ ((uint32_t (*)(uint32_t ui32Match))ROM_HIBERNATETABLE[51]) #endif -#if defined(TARGET_IS_TM4C129_RA1) +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_HibernateRTCSSMatchSet \ ((void (*)(uint32_t ui32Match, \ uint32_t ui32Value))ROM_HIBERNATETABLE[52]) @@ -2494,8 +2946,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_I2CMasterDataPut \ ((void (*)(uint32_t ui32Base, \ uint8_t ui8Data))ROM_I2CTABLE[0]) @@ -2503,14 +2957,17 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_I2CMasterInitExpClk \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32I2CClk, \ bool bFast))ROM_I2CTABLE[1]) #endif -#if defined(TARGET_IS_TM4C129_RA1) +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_I2CSlaveInit \ ((void (*)(uint32_t ui32Base, \ uint8_t ui8SlaveAddr))ROM_I2CTABLE[2]) @@ -2518,61 +2975,76 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_I2CMasterEnable \ ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[3]) #endif -#if defined(TARGET_IS_TM4C129_RA1) +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_I2CSlaveEnable \ ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[4]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_I2CMasterDisable \ ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[5]) #endif -#if defined(TARGET_IS_TM4C129_RA1) +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_I2CSlaveDisable \ ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[6]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_I2CMasterIntEnable \ ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[7]) #endif -#if defined(TARGET_IS_TM4C129_RA1) +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_I2CSlaveIntEnable \ ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[8]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_I2CMasterIntDisable \ ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[9]) #endif -#if defined(TARGET_IS_TM4C129_RA1) +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_I2CSlaveIntDisable \ ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[10]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_I2CMasterIntStatus \ ((bool (*)(uint32_t ui32Base, \ bool bMasked))ROM_I2CTABLE[11]) #endif -#if defined(TARGET_IS_TM4C129_RA1) +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_I2CSlaveIntStatus \ ((bool (*)(uint32_t ui32Base, \ bool bMasked))ROM_I2CTABLE[12]) @@ -2580,20 +3052,25 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_I2CMasterIntClear \ ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[13]) #endif -#if defined(TARGET_IS_TM4C129_RA1) +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_I2CSlaveIntClear \ ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[14]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_I2CMasterSlaveAddrSet \ ((void (*)(uint32_t ui32Base, \ uint8_t ui8SlaveAddr, \ @@ -2602,24 +3079,30 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_I2CMasterBusy \ ((bool (*)(uint32_t ui32Base))ROM_I2CTABLE[16]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_I2CMasterBusBusy \ ((bool (*)(uint32_t ui32Base))ROM_I2CTABLE[17]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_I2CMasterControl \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32Cmd))ROM_I2CTABLE[18]) @@ -2627,56 +3110,69 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_I2CMasterErr \ ((uint32_t (*)(uint32_t ui32Base))ROM_I2CTABLE[19]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_I2CMasterDataGet \ ((uint32_t (*)(uint32_t ui32Base))ROM_I2CTABLE[20]) #endif -#if defined(TARGET_IS_TM4C129_RA1) +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_I2CSlaveStatus \ ((uint32_t (*)(uint32_t ui32Base))ROM_I2CTABLE[21]) #endif -#if defined(TARGET_IS_TM4C129_RA1) +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_I2CSlaveDataPut \ ((void (*)(uint32_t ui32Base, \ uint8_t ui8Data))ROM_I2CTABLE[22]) #endif -#if defined(TARGET_IS_TM4C129_RA1) +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_I2CSlaveDataGet \ ((uint32_t (*)(uint32_t ui32Base))ROM_I2CTABLE[23]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_UpdateI2C \ ((void (*)(void))ROM_I2CTABLE[24]) #endif -#if defined(TARGET_IS_TM4C129_RA1) +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_I2CSlaveIntEnableEx \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32IntFlags))ROM_I2CTABLE[25]) #endif -#if defined(TARGET_IS_TM4C129_RA1) +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_I2CSlaveIntDisableEx \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32IntFlags))ROM_I2CTABLE[26]) #endif -#if defined(TARGET_IS_TM4C129_RA1) +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_I2CSlaveIntStatusEx \ ((uint32_t (*)(uint32_t ui32Base, \ bool bMasked))ROM_I2CTABLE[27]) #endif -#if defined(TARGET_IS_TM4C129_RA1) +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_I2CSlaveIntClearEx \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32IntFlags))ROM_I2CTABLE[28]) @@ -2684,8 +3180,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_I2CMasterIntEnableEx \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32IntFlags))ROM_I2CTABLE[29]) @@ -2693,8 +3191,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_I2CMasterIntDisableEx \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32IntFlags))ROM_I2CTABLE[30]) @@ -2702,8 +3202,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_I2CMasterIntStatusEx \ ((uint32_t (*)(uint32_t ui32Base, \ bool bMasked))ROM_I2CTABLE[31]) @@ -2711,8 +3213,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_I2CMasterIntClearEx \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32IntFlags))ROM_I2CTABLE[32]) @@ -2720,23 +3224,28 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_I2CMasterTimeoutSet \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32Value))ROM_I2CTABLE[33]) #endif -#if defined(TARGET_IS_TM4C129_RA1) +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_I2CSlaveACKOverride \ ((void (*)(uint32_t ui32Base, \ bool bEnable))ROM_I2CTABLE[34]) #endif -#if defined(TARGET_IS_TM4C129_RA1) +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_I2CSlaveACKValueSet \ ((void (*)(uint32_t ui32Base, \ bool bACK))ROM_I2CTABLE[35]) #endif -#if defined(TARGET_IS_TM4C129_RA1) +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_I2CSlaveAddressSet \ ((void (*)(uint32_t ui32Base, \ uint8_t ui8AddrNum, \ @@ -2745,83 +3254,99 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_I2CMasterLineStateGet \ ((uint32_t (*)(uint32_t ui32Base))ROM_I2CTABLE[38]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_I2CTxFIFOConfigSet \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32Config))ROM_I2CTABLE[39]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_I2CTxFIFOFlush \ ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[40]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_I2CRxFIFOConfigSet \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32Config))ROM_I2CTABLE[41]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_I2CRxFIFOFlush \ ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[42]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_I2CFIFOStatus \ ((uint32_t (*)(uint32_t ui32Base))ROM_I2CTABLE[43]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_I2CFIFODataPut \ ((void (*)(uint32_t ui32Base, \ uint8_t ui8Data))ROM_I2CTABLE[44]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_I2CFIFODataPutNonBlocking \ ((uint32_t (*)(uint32_t ui32Base, \ uint8_t ui8Data))ROM_I2CTABLE[45]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_I2CFIFODataGet \ ((uint32_t (*)(uint32_t ui32Base))ROM_I2CTABLE[46]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_I2CFIFODataGetNonBlocking \ ((uint32_t (*)(uint32_t ui32Base, \ uint8_t *pui8Data))ROM_I2CTABLE[47]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_I2CMasterBurstLengthSet \ ((void (*)(uint32_t ui32Base, \ uint8_t ui8Length))ROM_I2CTABLE[48]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_I2CMasterBurstCountGet \ ((uint32_t (*)(uint32_t ui32Base))ROM_I2CTABLE[49]) #endif -#if defined(TARGET_IS_TM4C129_RA1) +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_I2CSlaveFIFODisable \ ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[50]) #endif -#if defined(TARGET_IS_TM4C129_RA1) +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_I2CSlaveFIFOEnable \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32Config))ROM_I2CTABLE[51]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_I2CMasterGlitchFilterConfigSet \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32Config))ROM_I2CTABLE[54]) @@ -2835,56 +3360,70 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_IntEnable \ ((void (*)(uint32_t ui32Interrupt))ROM_INTERRUPTTABLE[0]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_IntMasterEnable \ ((bool (*)(void))ROM_INTERRUPTTABLE[1]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_IntMasterDisable \ ((bool (*)(void))ROM_INTERRUPTTABLE[2]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_IntDisable \ ((void (*)(uint32_t ui32Interrupt))ROM_INTERRUPTTABLE[3]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_IntPriorityGroupingSet \ ((void (*)(uint32_t ui32Bits))ROM_INTERRUPTTABLE[4]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_IntPriorityGroupingGet \ ((uint32_t (*)(void))ROM_INTERRUPTTABLE[5]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_IntPrioritySet \ ((void (*)(uint32_t ui32Interrupt, \ uint8_t ui8Priority))ROM_INTERRUPTTABLE[6]) @@ -2892,50 +3431,62 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_IntPriorityGet \ ((int32_t (*)(uint32_t ui32Interrupt))ROM_INTERRUPTTABLE[7]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_IntPendSet \ ((void (*)(uint32_t ui32Interrupt))ROM_INTERRUPTTABLE[8]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_IntPendClear \ ((void (*)(uint32_t ui32Interrupt))ROM_INTERRUPTTABLE[9]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_IntPriorityMaskSet \ ((void (*)(uint32_t ui32PriorityMask))ROM_INTERRUPTTABLE[10]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_IntPriorityMaskGet \ ((uint32_t (*)(void))ROM_INTERRUPTTABLE[11]) #endif #if defined(TARGET_IS_TM4C123_RB1) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_IntIsEnabled \ ((uint32_t (*)(uint32_t ui32Interrupt))ROM_INTERRUPTTABLE[12]) #endif -#if defined(TARGET_IS_TM4C129_RA1) +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_IntTrigger \ ((void (*)(uint32_t ui32Interrupt))ROM_INTERRUPTTABLE[13]) #endif @@ -2946,56 +3497,65 @@ // //***************************************************************************** #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_LCDIntStatus \ ((uint32_t (*)(uint32_t ui32Base, \ bool bMasked))ROM_LCDTABLE[0]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_LCDClockReset \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32Clocks))ROM_LCDTABLE[1]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_LCDDMAConfigSet \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32Config))ROM_LCDTABLE[2]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_LCDIDDCommandWrite \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32CS, \ uint16_t ui16Cmd))ROM_LCDTABLE[3]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_LCDIDDConfigSet \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32Config))ROM_LCDTABLE[4]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_LCDIDDDataRead \ ((uint16_t (*)(uint32_t ui32Base, \ uint32_t ui32CS))ROM_LCDTABLE[5]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_LCDIDDDataWrite \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32CS, \ uint16_t ui16Data))ROM_LCDTABLE[6]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_LCDIDDDMADisable \ ((void (*)(uint32_t ui32Base))ROM_LCDTABLE[7]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_LCDIDDDMAWrite \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32CS, \ @@ -3003,14 +3563,16 @@ uint32_t ui32Count))ROM_LCDTABLE[8]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_LCDIDDIndexedRead \ ((uint16_t (*)(uint32_t ui32Base, \ uint32_t ui32CS, \ uint16_t ui16Addr))ROM_LCDTABLE[9]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_LCDIDDIndexedWrite \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32CS, \ @@ -3018,38 +3580,44 @@ uint16_t ui16Data))ROM_LCDTABLE[10]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_LCDIDDStatusRead \ ((uint16_t (*)(uint32_t ui32Base, \ uint32_t ui32CS))ROM_LCDTABLE[11]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_LCDIDDTimingSet \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32CS, \ const tLCDIDDTiming *pTiming))ROM_LCDTABLE[12]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_LCDIntClear \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32IntFlags))ROM_LCDTABLE[13]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_LCDIntDisable \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32IntFlags))ROM_LCDTABLE[14]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_LCDIntEnable \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32IntFlags))ROM_LCDTABLE[15]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_LCDModeSet \ ((uint32_t (*)(uint32_t ui32Base, \ uint8_t ui8Mode, \ @@ -3057,30 +3625,35 @@ uint32_t ui32SysClk))ROM_LCDTABLE[16]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_LCDRasterACBiasIntCountSet \ ((void (*)(uint32_t ui32Base, \ uint8_t ui8Count))ROM_LCDTABLE[17]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_LCDRasterConfigSet \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32Config, \ uint8_t ui8PalLoadDelay))ROM_LCDTABLE[18]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_LCDRasterDisable \ ((void (*)(uint32_t ui32Base))ROM_LCDTABLE[19]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_LCDRasterEnable \ ((void (*)(uint32_t ui32Base))ROM_LCDTABLE[20]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_LCDRasterFrameBufferSet \ ((void (*)(uint32_t ui32Base, \ uint8_t ui8Buffer, \ @@ -3088,7 +3661,8 @@ uint32_t ui32NumBytes))ROM_LCDTABLE[21]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_LCDRasterPaletteSet \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32Type, \ @@ -3098,7 +3672,8 @@ uint32_t ui32Count))ROM_LCDTABLE[22]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_LCDRasterSubPanelConfigSet \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32Flags, \ @@ -3106,22 +3681,26 @@ uint32_t ui32DefaultPixel))ROM_LCDTABLE[23]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_LCDRasterSubPanelDisable \ ((void (*)(uint32_t ui32Base))ROM_LCDTABLE[24]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_LCDRasterSubPanelEnable \ ((void (*)(uint32_t ui32Base))ROM_LCDTABLE[25]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_LCDRasterTimingSet \ ((void (*)(uint32_t ui32Base, \ const tLCDRasterTiming *pTiming))ROM_LCDTABLE[26]) #endif -#if defined(TARGET_IS_TM4C129_RA1) +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_LCDRasterEnabled \ ((bool (*)(uint32_t ui32Base))ROM_LCDTABLE[27]) #endif @@ -3134,48 +3713,60 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_MPUEnable \ ((void (*)(uint32_t ui32MPUConfig))ROM_MPUTABLE[0]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_MPUDisable \ ((void (*)(void))ROM_MPUTABLE[1]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_MPURegionCountGet \ ((uint32_t (*)(void))ROM_MPUTABLE[2]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_MPURegionEnable \ ((void (*)(uint32_t ui32Region))ROM_MPUTABLE[3]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_MPURegionDisable \ ((void (*)(uint32_t ui32Region))ROM_MPUTABLE[4]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_MPURegionSet \ ((void (*)(uint32_t ui32Region, \ uint32_t ui32Addr, \ @@ -3184,8 +3775,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_MPURegionGet \ ((void (*)(uint32_t ui32Region, \ uint32_t *pui32Addr, \ @@ -3198,59 +3791,69 @@ // //***************************************************************************** #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_OneWireIntStatus \ ((uint32_t (*)(uint32_t ui32Base, \ bool bMasked))ROM_ONEWIRETABLE[0]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_OneWireBusReset \ ((void (*)(uint32_t ui32Base))ROM_ONEWIRETABLE[1]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_OneWireBusStatus \ ((uint32_t (*)(uint32_t ui32Base))ROM_ONEWIRETABLE[2]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_OneWireDataGet \ ((void (*)(uint32_t u3i2Base, \ uint32_t *pui32Data))ROM_ONEWIRETABLE[3]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_OneWireDataGetNonBlocking \ ((bool (*)(uint32_t ui32Base, \ uint32_t *pui32Data))ROM_ONEWIRETABLE[4]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_OneWireInit \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32InitFlags))ROM_ONEWIRETABLE[5]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_OneWireIntClear \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32IntFlags))ROM_ONEWIRETABLE[6]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_OneWireIntDisable \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32IntFlags))ROM_ONEWIRETABLE[7]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_OneWireIntEnable \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32IntFlags))ROM_ONEWIRETABLE[8]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_OneWireTransaction \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32OpFlags, \ @@ -3258,13 +3861,15 @@ uint32_t ui32BitCnt))ROM_ONEWIRETABLE[9]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_OneWireDMADisable \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32DMAFlags))ROM_ONEWIRETABLE[10]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_OneWireDMAEnable \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32DMAFlags))ROM_ONEWIRETABLE[11]) @@ -3278,8 +3883,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_PWMPulseWidthSet \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32PWMOut, \ @@ -3288,8 +3895,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_PWMGenConfigure \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32Gen, \ @@ -3298,8 +3907,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_PWMGenPeriodSet \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32Gen, \ @@ -3308,8 +3919,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_PWMGenPeriodGet \ ((uint32_t (*)(uint32_t ui32Base, \ uint32_t ui32Gen))ROM_PWMTABLE[3]) @@ -3317,8 +3930,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_PWMGenEnable \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32Gen))ROM_PWMTABLE[4]) @@ -3326,8 +3941,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_PWMGenDisable \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32Gen))ROM_PWMTABLE[5]) @@ -3335,8 +3952,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_PWMPulseWidthGet \ ((uint32_t (*)(uint32_t ui32Base, \ uint32_t ui32PWMOut))ROM_PWMTABLE[6]) @@ -3344,8 +3963,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_PWMDeadBandEnable \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32Gen, \ @@ -3355,8 +3976,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_PWMDeadBandDisable \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32Gen))ROM_PWMTABLE[8]) @@ -3364,8 +3987,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_PWMSyncUpdate \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32GenBits))ROM_PWMTABLE[9]) @@ -3373,8 +3998,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_PWMSyncTimeBase \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32GenBits))ROM_PWMTABLE[10]) @@ -3382,8 +4009,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_PWMOutputState \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32PWMOutBits, \ @@ -3392,8 +4021,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_PWMOutputInvert \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32PWMOutBits, \ @@ -3402,8 +4033,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_PWMOutputFault \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32PWMOutBits, \ @@ -3412,8 +4045,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_PWMGenIntTrigEnable \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32Gen, \ @@ -3422,8 +4057,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_PWMGenIntTrigDisable \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32Gen, \ @@ -3432,8 +4069,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_PWMGenIntStatus \ ((uint32_t (*)(uint32_t ui32Base, \ uint32_t ui32Gen, \ @@ -3442,8 +4081,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_PWMGenIntClear \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32Gen, \ @@ -3452,8 +4093,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_PWMIntEnable \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32GenFault))ROM_PWMTABLE[18]) @@ -3461,8 +4104,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_PWMIntDisable \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32GenFault))ROM_PWMTABLE[19]) @@ -3470,16 +4115,20 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_PWMFaultIntClear \ ((void (*)(uint32_t ui32Base))ROM_PWMTABLE[20]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_PWMIntStatus \ ((uint32_t (*)(uint32_t ui32Base, \ bool bMasked))ROM_PWMTABLE[21]) @@ -3487,8 +4136,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_PWMOutputFaultLevel \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32PWMOutBits, \ @@ -3497,8 +4148,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_PWMFaultIntClearExt \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32FaultInts))ROM_PWMTABLE[23]) @@ -3506,8 +4159,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_PWMGenFaultConfigure \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32Gen, \ @@ -3517,8 +4172,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_PWMGenFaultTriggerSet \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32Gen, \ @@ -3528,8 +4185,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_PWMGenFaultTriggerGet \ ((uint32_t (*)(uint32_t ui32Base, \ uint32_t ui32Gen, \ @@ -3538,8 +4197,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_PWMGenFaultStatus \ ((uint32_t (*)(uint32_t ui32Base, \ uint32_t ui32Gen, \ @@ -3548,8 +4209,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_PWMGenFaultClear \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32Gen, \ @@ -3557,19 +4220,22 @@ uint32_t ui32FaultTriggers))ROM_PWMTABLE[28]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_PWMClockSet \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32Config))ROM_PWMTABLE[29]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_PWMClockGet \ ((uint32_t (*)(uint32_t ui32Base))ROM_PWMTABLE[30]) #endif #if defined(TARGET_IS_TM4C123_RB1) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_PWMOutputUpdateMode \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32PWMOutBits, \ @@ -3584,32 +4250,40 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_QEIPositionGet \ ((uint32_t (*)(uint32_t ui32Base))ROM_QEITABLE[0]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_QEIEnable \ ((void (*)(uint32_t ui32Base))ROM_QEITABLE[1]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_QEIDisable \ ((void (*)(uint32_t ui32Base))ROM_QEITABLE[2]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_QEIConfigure \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32Config, \ @@ -3618,8 +4292,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_QEIPositionSet \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32Position))ROM_QEITABLE[4]) @@ -3627,40 +4303,50 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_QEIDirectionGet \ ((int32_t (*)(uint32_t ui32Base))ROM_QEITABLE[5]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_QEIErrorGet \ ((bool (*)(uint32_t ui32Base))ROM_QEITABLE[6]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_QEIVelocityEnable \ ((void (*)(uint32_t ui32Base))ROM_QEITABLE[7]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_QEIVelocityDisable \ ((void (*)(uint32_t ui32Base))ROM_QEITABLE[8]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_QEIVelocityConfigure \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32PreDiv, \ @@ -3669,16 +4355,20 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_QEIVelocityGet \ ((uint32_t (*)(uint32_t ui32Base))ROM_QEITABLE[10]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_QEIIntEnable \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32IntFlags))ROM_QEITABLE[11]) @@ -3686,8 +4376,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_QEIIntDisable \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32IntFlags))ROM_QEITABLE[12]) @@ -3695,8 +4387,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_QEIIntStatus \ ((uint32_t (*)(uint32_t ui32Base, \ bool bMasked))ROM_QEITABLE[13]) @@ -3704,8 +4398,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_QEIIntClear \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32IntFlags))ROM_QEITABLE[14]) @@ -3717,19 +4413,22 @@ // //***************************************************************************** #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SHAMD5IntStatus \ ((uint32_t (*)(uint32_t ui32Base, \ bool bMasked))ROM_SHAMD5TABLE[0]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SHAMD5ConfigSet \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32Mode))ROM_SHAMD5TABLE[1]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SHAMD5DataProcess \ ((void (*)(uint32_t ui32Base, \ uint32_t *pui32DataSrc, \ @@ -3737,54 +4436,63 @@ uint32_t *pui32HashResult))ROM_SHAMD5TABLE[2]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SHAMD5DataWrite \ ((void (*)(uint32_t ui32Base, \ uint32_t *pui32Src))ROM_SHAMD5TABLE[3]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SHAMD5DataWriteNonBlocking \ ((bool (*)(uint32_t ui32Base, \ uint32_t *pui32Src))ROM_SHAMD5TABLE[4]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SHAMD5DMADisable \ ((void (*)(uint32_t ui32Base))ROM_SHAMD5TABLE[5]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SHAMD5DMAEnable \ ((void (*)(uint32_t ui32Base))ROM_SHAMD5TABLE[6]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SHAMD5HashLengthSet \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32Length))ROM_SHAMD5TABLE[7]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SHAMD5HMACKeySet \ ((void (*)(uint32_t ui32Base, \ uint32_t *pui32Src))ROM_SHAMD5TABLE[8]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SHAMD5HMACPPKeyGenerate \ ((void (*)(uint32_t ui32Base, \ uint32_t *pui32Key, \ uint32_t *pui32PPKey))ROM_SHAMD5TABLE[9]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SHAMD5HMACPPKeySet \ ((void (*)(uint32_t ui32Base, \ uint32_t *pui32Src))ROM_SHAMD5TABLE[10]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SHAMD5HMACProcess \ ((void (*)(uint32_t ui32Base, \ uint32_t *pui32DataSrc, \ @@ -3792,30 +4500,35 @@ uint32_t *pui32HashResult))ROM_SHAMD5TABLE[11]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SHAMD5IntClear \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32IntFlags))ROM_SHAMD5TABLE[12]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SHAMD5IntDisable \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32IntFlags))ROM_SHAMD5TABLE[13]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SHAMD5IntEnable \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32IntFlags))ROM_SHAMD5TABLE[14]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SHAMD5Reset \ ((void (*)(uint32_t ui32Base))ROM_SHAMD5TABLE[15]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SHAMD5ResultRead \ ((void (*)(uint32_t ui32Base, \ uint32_t *pui32Dest))ROM_SHAMD5TABLE[16]) @@ -3829,32 +4542,40 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SMBusMasterIntProcess \ ((tSMBusStatus (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[0]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SMBusARPDisable \ ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[1]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SMBusARPEnable \ ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[2]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SMBusARPUDIDPacketDecode \ ((void (*)(tSMBusUDID *pUDID, \ uint8_t *pui8Address, \ @@ -3863,8 +4584,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SMBusARPUDIDPacketEncode \ ((void (*)(tSMBusUDID *pUDID, \ uint8_t ui8Address, \ @@ -3873,8 +4596,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SMBusMasterARPAssignAddress \ ((tSMBusStatus (*)(tSMBus *psSMBus, \ uint8_t *pui8Data))ROM_SMBUSTABLE[5]) @@ -3882,8 +4607,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SMBusMasterARPGetUDIDDir \ ((tSMBusStatus (*)(tSMBus *psSMBus, \ uint8_t ui8TargetAddress, \ @@ -3892,8 +4619,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SMBusMasterARPGetUDIDGen \ ((tSMBusStatus (*)(tSMBus *psSMBus, \ uint8_t *pui8Data))ROM_SMBUSTABLE[7]) @@ -3901,8 +4630,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SMBusMasterARPNotifyMaster \ ((tSMBusStatus (*)(tSMBus *psSMBus, \ uint8_t *pui8Data))ROM_SMBUSTABLE[8]) @@ -3910,16 +4641,20 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SMBusMasterARPPrepareToARP \ ((tSMBusStatus (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[9]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SMBusMasterARPResetDeviceDir \ ((tSMBusStatus (*)(tSMBus *psSMBus, \ uint8_t ui8TargetAddress))ROM_SMBUSTABLE[10]) @@ -3927,16 +4662,20 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SMBusMasterARPResetDeviceGen \ ((tSMBusStatus (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[11]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SMBusMasterBlockProcessCall \ ((tSMBusStatus (*)(tSMBus *psSMBus, \ uint8_t ui8TargetAddress, \ @@ -3947,8 +4686,10 @@ #endif #if defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SMBusMasterBlockRead \ ((tSMBusStatus (*)(tSMBus *psSMBus, \ uint8_t ui8TargetAddress, \ @@ -3958,8 +4699,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SMBusMasterBlockWrite \ ((tSMBusStatus (*)(tSMBus *psSMBus, \ uint8_t ui8TargetAddress, \ @@ -3970,8 +4713,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SMBusMasterByteReceive \ ((tSMBusStatus (*)(tSMBus *psSMBus, \ uint8_t ui8TargetAddress, \ @@ -3980,8 +4725,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SMBusMasterByteSend \ ((tSMBusStatus (*)(tSMBus *psSMBus, \ uint8_t ui8TargetAddress, \ @@ -3990,8 +4737,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SMBusMasterByteWordRead \ ((tSMBusStatus (*)(tSMBus *psSMBus, \ uint8_t ui8TargetAddress, \ @@ -4002,8 +4751,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SMBusMasterByteWordWrite \ ((tSMBusStatus (*)(tSMBus *psSMBus, \ uint8_t ui8TargetAddress, \ @@ -4014,8 +4765,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SMBusMasterHostNotify \ ((tSMBusStatus (*)(tSMBus *psSMBus, \ uint8_t ui8OwnSlaveAddress, \ @@ -4024,8 +4777,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SMBusMasterI2CRead \ ((tSMBusStatus (*)(tSMBus *psSMBus, \ uint8_t ui8TargetAddress, \ @@ -4035,8 +4790,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SMBusMasterI2CWrite \ ((tSMBusStatus (*)(tSMBus *psSMBus, \ uint8_t ui8TargetAddress, \ @@ -4046,8 +4803,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SMBusMasterI2CWriteRead \ ((tSMBusStatus (*)(tSMBus *psSMBus, \ uint8_t ui8TargetAddress, \ @@ -4059,8 +4818,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SMBusMasterInit \ ((void (*)(tSMBus *psSMBus, \ uint32_t ui32I2CBase, \ @@ -4069,16 +4830,20 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SMBusMasterIntEnable \ ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[24]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SMBusMasterProcessCall \ ((tSMBusStatus (*)(tSMBus *psSMBus, \ uint8_t ui8TargetAddress, \ @@ -4089,8 +4854,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SMBusMasterQuickCommand \ ((tSMBusStatus (*)(tSMBus *psSMBus, \ uint8_t ui8TargetAddress, \ @@ -4099,32 +4866,40 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SMBusPECDisable \ ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[27]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SMBusPECEnable \ ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[28]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SMBusRxPacketSizeGet \ ((uint8_t (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[29]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SMBusSlaveACKSend \ ((void (*)(tSMBus *psSMBus, \ bool bACK))ROM_SMBUSTABLE[30]) @@ -4132,8 +4907,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SMBusSlaveAddressSet \ ((void (*)(tSMBus *psSMBus, \ uint8_t ui8AddressNum, \ @@ -4142,16 +4919,20 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SMBusSlaveARPFlagARGet \ ((bool (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[32]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SMBusSlaveARPFlagARSet \ ((void (*)(tSMBus *psSMBus, \ bool bValue))ROM_SMBUSTABLE[33]) @@ -4159,16 +4940,20 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SMBusSlaveARPFlagAVGet \ ((bool (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[34]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SMBusSlaveARPFlagAVSet \ ((void (*)(tSMBus *psSMBus, \ bool bValue))ROM_SMBUSTABLE[35]) @@ -4176,48 +4961,60 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SMBusSlaveBlockTransferDisable \ ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[36]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SMBusSlaveBlockTransferEnable \ ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[37]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SMBusSlaveCommandGet \ ((uint8_t (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[38]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SMBusSlaveI2CDisable \ ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[39]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SMBusSlaveI2CEnable \ ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[40]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SMBusSlaveInit \ ((void (*)(tSMBus *psSMBus, \ uint32_t ui32I2CBase))ROM_SMBUSTABLE[41]) @@ -4225,72 +5022,90 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SMBusSlaveIntAddressGet \ ((tSMBusStatus (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[42]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SMBusSlaveIntEnable \ ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[43]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SMBusSlaveIntProcess \ ((tSMBusStatus (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[44]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SMBusSlaveManualACKDisable \ ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[45]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SMBusSlaveManualACKEnable \ ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[46]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SMBusSlaveManualACKStatusGet \ ((bool (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[47]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SMBusSlaveProcessCallDisable \ ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[48]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SMBusSlaveProcessCallEnable \ ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[49]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SMBusSlaveRxBufferSet \ ((void (*)(tSMBus *psSMBus, \ uint8_t *pui8Data, \ @@ -4299,16 +5114,20 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SMBusSlaveTransferInit \ ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[51]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SMBusSlaveTxBufferSet \ ((void (*)(tSMBus *psSMBus, \ uint8_t *pui8Data, \ @@ -4317,8 +5136,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SMBusSlaveUDIDSet \ ((void (*)(tSMBus *psSMBus, \ tSMBusUDID *pUDID))ROM_SMBUSTABLE[53]) @@ -4326,37 +5147,45 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SMBusStatusGet \ ((tSMBusStatus (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[54]) #endif #if defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SMBusSlaveDataSend \ ((tSMBusStatus (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[55]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SMBusFIFOEnable \ ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[56]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SMBusFIFODisable \ ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[57]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SMBusDMAEnable \ ((void (*)(tSMBus *psSMBus, \ uint8_t ui8TxChannel, \ uint8_t ui8RxChannel))ROM_SMBUSTABLE[58]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SMBusDMADisable \ ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[59]) #endif @@ -4367,25 +5196,29 @@ // //***************************************************************************** #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SPIFlashIntHandler \ ((uint32_t (*)(tSPIFlashState *pState))ROM_SPIFLASHTABLE[0]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SPIFlashInit \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32Clock, \ uint32_t ui32BitRate))ROM_SPIFLASHTABLE[1]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SPIFlashWriteStatus \ ((void (*)(uint32_t ui32Base, \ uint8_t ui8Status))ROM_SPIFLASHTABLE[2]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SPIFlashPageProgram \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32Addr, \ @@ -4393,7 +5226,8 @@ uint32_t ui32Count))ROM_SPIFLASHTABLE[3]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SPIFlashPageProgramNonBlocking \ ((void (*)(tSPIFlashState *pState, \ uint32_t ui32Base, \ @@ -4404,7 +5238,8 @@ uint32_t ui32TxChannel))ROM_SPIFLASHTABLE[4]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SPIFlashRead \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32Addr, \ @@ -4412,7 +5247,8 @@ uint32_t ui32Count))ROM_SPIFLASHTABLE[5]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SPIFlashReadNonBlocking \ ((void (*)(tSPIFlashState *pState, \ uint32_t ui32Base, \ @@ -4424,22 +5260,26 @@ uint32_t ui32RxChannel))ROM_SPIFLASHTABLE[6]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SPIFlashWriteDisable \ ((void (*)(uint32_t ui32Base))ROM_SPIFLASHTABLE[7]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SPIFlashReadStatus \ ((uint8_t (*)(uint32_t ui32Base))ROM_SPIFLASHTABLE[8]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SPIFlashWriteEnable \ ((void (*)(uint32_t ui32Base))ROM_SPIFLASHTABLE[9]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SPIFlashFastRead \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32Addr, \ @@ -4447,7 +5287,8 @@ uint32_t ui32Count))ROM_SPIFLASHTABLE[10]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SPIFlashFastReadNonBlocking \ ((void (*)(tSPIFlashState *pState, \ uint32_t ui32Base, \ @@ -4459,13 +5300,15 @@ uint32_t ui32RxChannel))ROM_SPIFLASHTABLE[11]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SPIFlashSectorErase \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32Addr))ROM_SPIFLASHTABLE[12]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SPIFlashDualRead \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32Addr, \ @@ -4473,7 +5316,8 @@ uint32_t ui32Count))ROM_SPIFLASHTABLE[13]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SPIFlashDualReadNonBlocking \ ((void (*)(tSPIFlashState *pState, \ uint32_t ui32Base, \ @@ -4485,13 +5329,15 @@ uint32_t ui32RxChannel))ROM_SPIFLASHTABLE[14]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SPIFlashBlockErase32 \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32Addr))ROM_SPIFLASHTABLE[15]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SPIFlashQuadRead \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32Addr, \ @@ -4499,7 +5345,8 @@ uint32_t ui32Count))ROM_SPIFLASHTABLE[16]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SPIFlashQuadReadNonBlocking \ ((void (*)(tSPIFlashState *pState, \ uint32_t ui32Base, \ @@ -4511,19 +5358,22 @@ uint32_t ui32RxChannel))ROM_SPIFLASHTABLE[17]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SPIFlashReadID \ ((void (*)(uint32_t ui32Base, \ uint8_t *pui8ManufacturerID, \ uint16_t *pui16DeviceID))ROM_SPIFLASHTABLE[18]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SPIFlashChipErase \ ((void (*)(uint32_t ui32Base))ROM_SPIFLASHTABLE[19]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SPIFlashBlockErase64 \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32Addr))ROM_SPIFLASHTABLE[20]) @@ -4537,8 +5387,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SSIDataPut \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32Data))ROM_SSITABLE[0]) @@ -4546,8 +5398,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SSIConfigSetExpClk \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32SSIClk, \ @@ -4559,24 +5413,30 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SSIEnable \ ((void (*)(uint32_t ui32Base))ROM_SSITABLE[2]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SSIDisable \ ((void (*)(uint32_t ui32Base))ROM_SSITABLE[3]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SSIIntEnable \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32IntFlags))ROM_SSITABLE[4]) @@ -4584,8 +5444,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SSIIntDisable \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32IntFlags))ROM_SSITABLE[5]) @@ -4593,8 +5455,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SSIIntStatus \ ((uint32_t (*)(uint32_t ui32Base, \ bool bMasked))ROM_SSITABLE[6]) @@ -4602,8 +5466,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SSIIntClear \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32IntFlags))ROM_SSITABLE[7]) @@ -4611,8 +5477,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SSIDataPutNonBlocking \ ((int32_t (*)(uint32_t ui32Base, \ uint32_t ui32Data))ROM_SSITABLE[8]) @@ -4620,8 +5488,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SSIDataGet \ ((void (*)(uint32_t ui32Base, \ uint32_t *pui32Data))ROM_SSITABLE[9]) @@ -4629,8 +5499,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SSIDataGetNonBlocking \ ((int32_t (*)(uint32_t ui32Base, \ uint32_t *pui32Data))ROM_SSITABLE[10]) @@ -4638,16 +5510,20 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_UpdateSSI \ ((void (*)(void))ROM_SSITABLE[11]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SSIDMAEnable \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32DMAFlags))ROM_SSITABLE[12]) @@ -4655,8 +5531,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SSIDMADisable \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32DMAFlags))ROM_SSITABLE[13]) @@ -4664,53 +5542,64 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SSIBusy \ ((bool (*)(uint32_t ui32Base))ROM_SSITABLE[14]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SSIClockSourceGet \ ((uint32_t (*)(uint32_t ui32Base))ROM_SSITABLE[15]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SSIClockSourceSet \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32Source))ROM_SSITABLE[16]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SSIAdvModeSet \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32Mode))ROM_SSITABLE[17]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SSIAdvDataPutFrameEnd \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32Data))ROM_SSITABLE[18]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SSIAdvDataPutFrameEndNonBlocking \ ((int32_t (*)(uint32_t ui32Base, \ uint32_t ui32Data))ROM_SSITABLE[19]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SSIAdvFrameHoldEnable \ ((void (*)(uint32_t ui32Base))ROM_SSITABLE[20]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SSIAdvFrameHoldDisable \ ((void (*)(uint32_t ui32Base))ROM_SSITABLE[21]) #endif @@ -4723,313 +5612,378 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SysCtlSleep \ ((void (*)(void))ROM_SYSCTLTABLE[0]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SysCtlSRAMSizeGet \ ((uint32_t (*)(void))ROM_SYSCTLTABLE[1]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SysCtlFlashSizeGet \ ((uint32_t (*)(void))ROM_SYSCTLTABLE[2]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SysCtlPeripheralPresent \ ((bool (*)(uint32_t ui32Peripheral))ROM_SYSCTLTABLE[4]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SysCtlPeripheralReset \ ((void (*)(uint32_t ui32Peripheral))ROM_SYSCTLTABLE[5]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SysCtlPeripheralEnable \ ((void (*)(uint32_t ui32Peripheral))ROM_SYSCTLTABLE[6]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SysCtlPeripheralDisable \ ((void (*)(uint32_t ui32Peripheral))ROM_SYSCTLTABLE[7]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SysCtlPeripheralSleepEnable \ ((void (*)(uint32_t ui32Peripheral))ROM_SYSCTLTABLE[8]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SysCtlPeripheralSleepDisable \ ((void (*)(uint32_t ui32Peripheral))ROM_SYSCTLTABLE[9]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SysCtlPeripheralDeepSleepEnable \ ((void (*)(uint32_t ui32Peripheral))ROM_SYSCTLTABLE[10]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SysCtlPeripheralDeepSleepDisable \ ((void (*)(uint32_t ui32Peripheral))ROM_SYSCTLTABLE[11]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SysCtlPeripheralClockGating \ ((void (*)(bool bEnable))ROM_SYSCTLTABLE[12]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SysCtlIntEnable \ ((void (*)(uint32_t ui32Ints))ROM_SYSCTLTABLE[13]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SysCtlIntDisable \ ((void (*)(uint32_t ui32Ints))ROM_SYSCTLTABLE[14]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SysCtlIntClear \ ((void (*)(uint32_t ui32Ints))ROM_SYSCTLTABLE[15]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SysCtlIntStatus \ ((uint32_t (*)(bool bMasked))ROM_SYSCTLTABLE[16]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SysCtlReset \ ((void (*)(void))ROM_SYSCTLTABLE[19]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SysCtlDeepSleep \ ((void (*)(void))ROM_SYSCTLTABLE[20]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SysCtlResetCauseGet \ ((uint32_t (*)(void))ROM_SYSCTLTABLE[21]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SysCtlResetCauseClear \ ((void (*)(uint32_t ui32Causes))ROM_SYSCTLTABLE[22]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) #define ROM_SysCtlClockSet \ ((void (*)(uint32_t ui32Config))ROM_SYSCTLTABLE[23]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) #define ROM_SysCtlClockGet \ ((uint32_t (*)(void))ROM_SYSCTLTABLE[24]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) #define ROM_SysCtlPWMClockSet \ ((void (*)(uint32_t ui32Config))ROM_SYSCTLTABLE[25]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) #define ROM_SysCtlPWMClockGet \ ((uint32_t (*)(void))ROM_SYSCTLTABLE[26]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) #define ROM_SysCtlUSBPLLEnable \ ((void (*)(void))ROM_SYSCTLTABLE[31]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) #define ROM_SysCtlUSBPLLDisable \ ((void (*)(void))ROM_SYSCTLTABLE[32]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SysCtlDelay \ ((void (*)(uint32_t ui32Count))ROM_SYSCTLTABLE[34]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SysCtlPeripheralReady \ ((bool (*)(uint32_t ui32Peripheral))ROM_SYSCTLTABLE[35]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SysCtlPeripheralPowerOn \ ((void (*)(uint32_t ui32Peripheral))ROM_SYSCTLTABLE[36]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SysCtlPeripheralPowerOff \ ((void (*)(uint32_t ui32Peripheral))ROM_SYSCTLTABLE[37]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SysCtlMOSCConfigSet \ ((void (*)(uint32_t ui32Config))ROM_SYSCTLTABLE[44]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SysCtlPIOSCCalibrate \ ((uint32_t (*)(uint32_t ui32Type))ROM_SYSCTLTABLE[45]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) #define ROM_SysCtlDeepSleepClockSet \ ((void (*)(uint32_t ui32Config))ROM_SYSCTLTABLE[46]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SysCtlDeepSleepClockConfigSet \ ((void (*)(uint32_t ui32Div, \ uint32_t ui32Config))ROM_SYSCTLTABLE[47]) #endif -#if defined(TARGET_IS_TM4C129_RA1) -#define ROM_SysCtlClockFreqSet \ - ((uint32_t (*)(uint32_t ui32Config, \ - uint32_t ui32SysClock))ROM_SYSCTLTABLE[48]) -#endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SysCtlResetBehaviorSet \ ((void (*)(uint32_t ui32Behavior))ROM_SYSCTLTABLE[51]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SysCtlResetBehaviorGet \ ((uint32_t (*)(void))ROM_SYSCTLTABLE[52]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SysCtlFlashSectorSizeGet \ ((uint32_t (*)(void))ROM_SYSCTLTABLE[54]) #endif #if defined(TARGET_IS_TM4C123_RB1) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SysCtlVoltageEventConfig \ ((void (*)(uint32_t ui32Config))ROM_SYSCTLTABLE[55]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SysCtlVoltageEventStatus \ ((uint32_t (*)(void))ROM_SYSCTLTABLE[56]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SysCtlVoltageEventClear \ ((void (*)(uint32_t ui32Status))ROM_SYSCTLTABLE[57]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SysCtlNMIStatus \ ((uint32_t (*)(void))ROM_SYSCTLTABLE[58]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SysCtlNMIClear \ ((void (*)(uint32_t ui32Status))ROM_SYSCTLTABLE[59]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SysCtlClockOutConfig \ ((void (*)(uint32_t ui32Config, \ uint32_t ui32Div))ROM_SYSCTLTABLE[60]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SysCtlAltClkConfig \ ((void (*)(uint32_t ui32Config))ROM_SYSCTLTABLE[61]) #endif @@ -5042,32 +5996,40 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SysExcIntStatus \ ((uint32_t (*)(bool bMasked))ROM_SYSEXCTABLE[0]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SysExcIntClear \ ((void (*)(uint32_t ui32IntFlags))ROM_SYSEXCTABLE[1]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SysExcIntDisable \ ((void (*)(uint32_t ui32IntFlags))ROM_SYSEXCTABLE[2]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SysExcIntEnable \ ((void (*)(uint32_t ui32IntFlags))ROM_SYSEXCTABLE[3]) #endif @@ -5080,56 +6042,70 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SysTickValueGet \ ((uint32_t (*)(void))ROM_SYSTICKTABLE[0]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SysTickEnable \ ((void (*)(void))ROM_SYSTICKTABLE[1]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SysTickDisable \ ((void (*)(void))ROM_SYSTICKTABLE[2]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SysTickIntEnable \ ((void (*)(void))ROM_SYSTICKTABLE[3]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SysTickIntDisable \ ((void (*)(void))ROM_SYSTICKTABLE[4]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SysTickPeriodSet \ ((void (*)(uint32_t ui32Period))ROM_SYSTICKTABLE[5]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_SysTickPeriodGet \ ((uint32_t (*)(void))ROM_SYSTICKTABLE[6]) #endif @@ -5142,8 +6118,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_TimerIntClear \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32IntFlags))ROM_TIMERTABLE[0]) @@ -5151,8 +6129,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_TimerEnable \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32Timer))ROM_TIMERTABLE[1]) @@ -5160,8 +6140,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_TimerDisable \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32Timer))ROM_TIMERTABLE[2]) @@ -5169,8 +6151,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_TimerConfigure \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32Config))ROM_TIMERTABLE[3]) @@ -5178,8 +6162,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_TimerControlLevel \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32Timer, \ @@ -5188,6 +6174,7 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA1) #define ROM_TimerControlTrigger \ ((void (*)(uint32_t ui32Base, \ @@ -5197,8 +6184,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_TimerControlEvent \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32Timer, \ @@ -5207,8 +6196,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_TimerControlStall \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32Timer, \ @@ -5217,24 +6208,30 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_TimerRTCEnable \ ((void (*)(uint32_t ui32Base))ROM_TIMERTABLE[8]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_TimerRTCDisable \ ((void (*)(uint32_t ui32Base))ROM_TIMERTABLE[9]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_TimerPrescaleSet \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32Timer, \ @@ -5243,8 +6240,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_TimerPrescaleGet \ ((uint32_t (*)(uint32_t ui32Base, \ uint32_t ui32Timer))ROM_TIMERTABLE[11]) @@ -5252,8 +6251,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_TimerPrescaleMatchSet \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32Timer, \ @@ -5262,8 +6263,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_TimerPrescaleMatchGet \ ((uint32_t (*)(uint32_t ui32Base, \ uint32_t ui32Timer))ROM_TIMERTABLE[13]) @@ -5271,8 +6274,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_TimerLoadSet \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32Timer, \ @@ -5281,8 +6286,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_TimerLoadGet \ ((uint32_t (*)(uint32_t ui32Base, \ uint32_t ui32Timer))ROM_TIMERTABLE[15]) @@ -5290,8 +6297,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_TimerValueGet \ ((uint32_t (*)(uint32_t ui32Base, \ uint32_t ui32Timer))ROM_TIMERTABLE[16]) @@ -5299,8 +6308,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_TimerMatchSet \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32Timer, \ @@ -5309,8 +6320,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_TimerMatchGet \ ((uint32_t (*)(uint32_t ui32Base, \ uint32_t ui32Timer))ROM_TIMERTABLE[18]) @@ -5318,8 +6331,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_TimerIntEnable \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32IntFlags))ROM_TIMERTABLE[19]) @@ -5327,8 +6342,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_TimerIntDisable \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32IntFlags))ROM_TIMERTABLE[20]) @@ -5336,8 +6353,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_TimerIntStatus \ ((uint32_t (*)(uint32_t ui32Base, \ bool bMasked))ROM_TIMERTABLE[21]) @@ -5345,8 +6364,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_TimerControlWaitOnTrigger \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32Timer, \ @@ -5354,71 +6375,83 @@ #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) #define ROM_TimerLoadSet64 \ ((void (*)(uint32_t ui32Base, \ uint64_t ui64Value))ROM_TIMERTABLE[23]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) #define ROM_TimerLoadGet64 \ ((uint64_t (*)(uint32_t ui32Base))ROM_TIMERTABLE[24]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) #define ROM_TimerValueGet64 \ ((uint64_t (*)(uint32_t ui32Base))ROM_TIMERTABLE[25]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) #define ROM_TimerMatchSet64 \ ((void (*)(uint32_t ui32Base, \ uint64_t ui64Value))ROM_TIMERTABLE[26]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ - defined(TARGET_IS_TM4C123_RB1) + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) #define ROM_TimerMatchGet64 \ ((uint64_t (*)(uint32_t ui32Base))ROM_TIMERTABLE[27]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_TimerClockSourceGet \ ((uint32_t (*)(uint32_t ui32Base))ROM_TIMERTABLE[28]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_TimerClockSourceSet \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32Source))ROM_TIMERTABLE[29]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_TimerADCEventGet \ ((uint32_t (*)(uint32_t ui32Base))ROM_TIMERTABLE[30]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_TimerADCEventSet \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32ADCEvent))ROM_TIMERTABLE[31]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_TimerDMAEventGet \ ((uint32_t (*)(uint32_t ui32Base))ROM_TIMERTABLE[32]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_TimerDMAEventSet \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32DMAEvent))ROM_TIMERTABLE[33]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_TimerSynchronize \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32Timers))ROM_TIMERTABLE[34]) @@ -5432,8 +6465,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_UARTCharPut \ ((void (*)(uint32_t ui32Base, \ unsigned char ucData))ROM_UARTTABLE[0]) @@ -5441,8 +6476,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_UARTParityModeSet \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32Parity))ROM_UARTTABLE[1]) @@ -5450,16 +6487,20 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_UARTParityModeGet \ ((uint32_t (*)(uint32_t ui32Base))ROM_UARTTABLE[2]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_UARTFIFOLevelSet \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32TxLevel, \ @@ -5468,8 +6509,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_UARTFIFOLevelGet \ ((void (*)(uint32_t ui32Base, \ uint32_t *pui32TxLevel, \ @@ -5478,8 +6521,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_UARTConfigSetExpClk \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32UARTClk, \ @@ -5489,8 +6534,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_UARTConfigGetExpClk \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32UARTClk, \ @@ -5500,24 +6547,30 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_UARTEnable \ ((void (*)(uint32_t ui32Base))ROM_UARTTABLE[7]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_UARTDisable \ ((void (*)(uint32_t ui32Base))ROM_UARTTABLE[8]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_UARTEnableSIR \ ((void (*)(uint32_t ui32Base, \ bool bLowPower))ROM_UARTTABLE[9]) @@ -5525,48 +6578,60 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_UARTDisableSIR \ ((void (*)(uint32_t ui32Base))ROM_UARTTABLE[10]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_UARTCharsAvail \ ((bool (*)(uint32_t ui32Base))ROM_UARTTABLE[11]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_UARTSpaceAvail \ ((bool (*)(uint32_t ui32Base))ROM_UARTTABLE[12]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_UARTCharGetNonBlocking \ ((int32_t (*)(uint32_t ui32Base))ROM_UARTTABLE[13]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_UARTCharGet \ ((int32_t (*)(uint32_t ui32Base))ROM_UARTTABLE[14]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_UARTCharPutNonBlocking \ ((bool (*)(uint32_t ui32Base, \ unsigned char ucData))ROM_UARTTABLE[15]) @@ -5574,8 +6639,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_UARTBreakCtl \ ((void (*)(uint32_t ui32Base, \ bool bBreakState))ROM_UARTTABLE[16]) @@ -5583,8 +6650,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_UARTIntEnable \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32IntFlags))ROM_UARTTABLE[17]) @@ -5592,8 +6661,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_UARTIntDisable \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32IntFlags))ROM_UARTTABLE[18]) @@ -5601,8 +6672,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_UARTIntStatus \ ((uint32_t (*)(uint32_t ui32Base, \ bool bMasked))ROM_UARTTABLE[19]) @@ -5610,8 +6683,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_UARTIntClear \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32IntFlags))ROM_UARTTABLE[20]) @@ -5619,16 +6694,20 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_UpdateUART \ ((void (*)(void))ROM_UARTTABLE[21]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_UARTDMAEnable \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32DMAFlags))ROM_UARTTABLE[22]) @@ -5636,8 +6715,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_UARTDMADisable \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32DMAFlags))ROM_UARTTABLE[23]) @@ -5645,32 +6726,40 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_UARTFIFOEnable \ ((void (*)(uint32_t ui32Base))ROM_UARTTABLE[24]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_UARTFIFODisable \ ((void (*)(uint32_t ui32Base))ROM_UARTTABLE[25]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_UARTBusy \ ((bool (*)(uint32_t ui32Base))ROM_UARTTABLE[26]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_UARTTxIntModeSet \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32Mode))ROM_UARTTABLE[27]) @@ -5678,32 +6767,40 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_UARTTxIntModeGet \ ((uint32_t (*)(uint32_t ui32Base))ROM_UARTTABLE[28]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_UARTRxErrorGet \ ((uint32_t (*)(uint32_t ui32Base))ROM_UARTTABLE[29]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_UARTRxErrorClear \ ((void (*)(uint32_t ui32Base))ROM_UARTTABLE[30]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_UARTClockSourceSet \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32Source))ROM_UARTTABLE[31]) @@ -5711,32 +6808,40 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_UARTClockSourceGet \ ((uint32_t (*)(uint32_t ui32Base))ROM_UARTTABLE[32]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_UART9BitEnable \ ((void (*)(uint32_t ui32Base))ROM_UARTTABLE[33]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_UART9BitDisable \ ((void (*)(uint32_t ui32Base))ROM_UARTTABLE[34]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_UART9BitAddrSet \ ((void (*)(uint32_t ui32Base, \ uint8_t ui8Addr, \ @@ -5745,52 +6850,62 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_UART9BitAddrSend \ ((void (*)(uint32_t ui32Base, \ uint8_t ui8Addr))ROM_UARTTABLE[36]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_UARTSmartCardDisable \ ((void (*)(uint32_t ui32Base))ROM_UARTTABLE[37]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_UARTSmartCardEnable \ ((void (*)(uint32_t ui32Base))ROM_UARTTABLE[38]) #endif #if defined(TARGET_IS_TM4C123_RB1) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_UARTModemControlClear \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32Control))ROM_UARTTABLE[39]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_UARTModemControlGet \ ((uint32_t (*)(uint32_t ui32Base))ROM_UARTTABLE[40]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_UARTModemControlSet \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32Control))ROM_UARTTABLE[41]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_UARTModemStatusGet \ ((uint32_t (*)(uint32_t ui32Base))ROM_UARTTABLE[42]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_UARTFlowControlGet \ ((uint32_t (*)(uint32_t ui32Base))ROM_UARTTABLE[43]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_UARTFlowControlSet \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32Mode))ROM_UARTTABLE[44]) @@ -5804,8 +6919,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_uDMAChannelTransferSet \ ((void (*)(uint32_t ui32ChannelStructIndex, \ uint32_t ui32Mode, \ @@ -5816,88 +6933,110 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_uDMAEnable \ ((void (*)(void))ROM_UDMATABLE[1]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_uDMADisable \ ((void (*)(void))ROM_UDMATABLE[2]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_uDMAErrorStatusGet \ ((uint32_t (*)(void))ROM_UDMATABLE[3]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_uDMAErrorStatusClear \ ((void (*)(void))ROM_UDMATABLE[4]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_uDMAChannelEnable \ ((void (*)(uint32_t ui32ChannelNum))ROM_UDMATABLE[5]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_uDMAChannelDisable \ ((void (*)(uint32_t ui32ChannelNum))ROM_UDMATABLE[6]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_uDMAChannelIsEnabled \ ((bool (*)(uint32_t ui32ChannelNum))ROM_UDMATABLE[7]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_uDMAControlBaseSet \ ((void (*)(void *pControlTable))ROM_UDMATABLE[8]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_uDMAControlBaseGet \ ((void * (*)(void))ROM_UDMATABLE[9]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_uDMAChannelRequest \ ((void (*)(uint32_t ui32ChannelNum))ROM_UDMATABLE[10]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_uDMAChannelAttributeEnable \ ((void (*)(uint32_t ui32ChannelNum, \ uint32_t ui32Attr))ROM_UDMATABLE[11]) @@ -5905,8 +7044,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_uDMAChannelAttributeDisable \ ((void (*)(uint32_t ui32ChannelNum, \ uint32_t ui32Attr))ROM_UDMATABLE[12]) @@ -5914,16 +7055,20 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_uDMAChannelAttributeGet \ ((uint32_t (*)(uint32_t ui32ChannelNum))ROM_UDMATABLE[13]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_uDMAChannelControlSet \ ((void (*)(uint32_t ui32ChannelStructIndex, \ uint32_t ui32Control))ROM_UDMATABLE[14]) @@ -5931,64 +7076,80 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_uDMAChannelSizeGet \ ((uint32_t (*)(uint32_t ui32ChannelStructIndex))ROM_UDMATABLE[15]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_uDMAChannelModeGet \ ((uint32_t (*)(uint32_t ui32ChannelStructIndex))ROM_UDMATABLE[16]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_uDMAChannelSelectSecondary \ ((void (*)(uint32_t ui32SecPeriphs))ROM_UDMATABLE[17]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_uDMAChannelSelectDefault \ ((void (*)(uint32_t ui32DefPeriphs))ROM_UDMATABLE[18]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_uDMAIntStatus \ ((uint32_t (*)(void))ROM_UDMATABLE[19]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_uDMAIntClear \ ((void (*)(uint32_t ui32ChanMask))ROM_UDMATABLE[20]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_uDMAControlAlternateBaseGet \ ((void * (*)(void))ROM_UDMATABLE[21]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_uDMAChannelScatterGatherSet \ ((void (*)(uint32_t ui32ChannelNum, \ uint32_t ui32TaskCount, \ @@ -5998,8 +7159,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_uDMAChannelAssign \ ((void (*)(uint32_t ui32Mapping))ROM_UDMATABLE[23]) #endif @@ -6012,16 +7175,20 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_USBDevAddrGet \ ((uint32_t (*)(uint32_t ui32Base))ROM_USBTABLE[1]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_USBDevAddrSet \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32Address))ROM_USBTABLE[2]) @@ -6029,24 +7196,30 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_USBDevConnect \ ((void (*)(uint32_t ui32Base))ROM_USBTABLE[3]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_USBDevDisconnect \ ((void (*)(uint32_t ui32Base))ROM_USBTABLE[4]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_USBDevEndpointConfigSet \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32Endpoint, \ @@ -6056,8 +7229,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_USBDevEndpointDataAck \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32Endpoint, \ @@ -6066,8 +7241,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_USBDevEndpointStall \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32Endpoint, \ @@ -6076,8 +7253,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_USBDevEndpointStallClear \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32Endpoint, \ @@ -6086,8 +7265,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_USBDevEndpointStatusClear \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32Endpoint, \ @@ -6096,8 +7277,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_USBEndpointDataGet \ ((int32_t (*)(uint32_t ui32Base, \ uint32_t ui32Endpoint, \ @@ -6107,8 +7290,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_USBEndpointDataPut \ ((int32_t (*)(uint32_t ui32Base, \ uint32_t ui32Endpoint, \ @@ -6118,8 +7303,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_USBEndpointDataSend \ ((int32_t (*)(uint32_t ui32Base, \ uint32_t ui32Endpoint, \ @@ -6128,8 +7315,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_USBEndpointDataToggleClear \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32Endpoint, \ @@ -6138,8 +7327,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_USBEndpointStatus \ ((uint32_t (*)(uint32_t ui32Base, \ uint32_t ui32Endpoint))ROM_USBTABLE[14]) @@ -6147,8 +7338,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_USBFIFOAddrGet \ ((uint32_t (*)(uint32_t ui32Base, \ uint32_t ui32Endpoint))ROM_USBTABLE[15]) @@ -6156,8 +7349,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_USBFIFOConfigGet \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32Endpoint, \ @@ -6168,8 +7363,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_USBFIFOConfigSet \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32Endpoint, \ @@ -6180,8 +7377,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_USBFIFOFlush \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32Endpoint, \ @@ -6190,16 +7389,20 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_USBFrameNumberGet \ ((uint32_t (*)(uint32_t ui32Base))ROM_USBTABLE[19]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_USBHostAddrGet \ ((uint32_t (*)(uint32_t ui32Base, \ uint32_t ui32Endpoint, \ @@ -6208,8 +7411,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_USBHostAddrSet \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32Endpoint, \ @@ -6218,8 +7423,10 @@ #endif #if defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_USBHostEndpointConfig \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32Endpoint, \ @@ -6231,8 +7438,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_USBHostEndpointDataAck \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32Endpoint))ROM_USBTABLE[23]) @@ -6240,8 +7449,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_USBHostEndpointDataToggle \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32Endpoint, \ @@ -6251,8 +7462,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_USBHostEndpointStatusClear \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32Endpoint, \ @@ -6261,8 +7474,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_USBHostHubAddrGet \ ((uint32_t (*)(uint32_t ui32Base, \ uint32_t ui32Endpoint, \ @@ -6271,8 +7486,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_USBHostHubAddrSet \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32Endpoint, \ @@ -6282,24 +7499,30 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_USBHostPwrDisable \ ((void (*)(uint32_t ui32Base))ROM_USBTABLE[28]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_USBHostPwrEnable \ ((void (*)(uint32_t ui32Base))ROM_USBTABLE[29]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_USBHostPwrConfig \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32Flags))ROM_USBTABLE[30]) @@ -6307,24 +7530,30 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_USBHostPwrFaultDisable \ ((void (*)(uint32_t ui32Base))ROM_USBTABLE[31]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_USBHostPwrFaultEnable \ ((void (*)(uint32_t ui32Base))ROM_USBTABLE[32]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_USBHostRequestIN \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32Endpoint))ROM_USBTABLE[33]) @@ -6332,16 +7561,20 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_USBHostRequestStatus \ ((void (*)(uint32_t ui32Base))ROM_USBTABLE[34]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_USBHostReset \ ((void (*)(uint32_t ui32Base, \ bool bStart))ROM_USBTABLE[35]) @@ -6349,8 +7582,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_USBHostResume \ ((void (*)(uint32_t ui32Base, \ bool bStart))ROM_USBTABLE[36]) @@ -6358,24 +7593,30 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_USBHostSpeedGet \ ((uint32_t (*)(uint32_t ui32Base))ROM_USBTABLE[37]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_USBHostSuspend \ ((void (*)(uint32_t ui32Base))ROM_USBTABLE[38]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_USBDevEndpointConfigGet \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32Endpoint, \ @@ -6385,8 +7626,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_USBEndpointDMAEnable \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32Endpoint, \ @@ -6395,8 +7638,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_USBEndpointDMADisable \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32Endpoint, \ @@ -6405,30 +7650,31 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_USBEndpointDataAvail \ ((uint32_t (*)(uint32_t ui32Base, \ uint32_t ui32Endpoint))ROM_USBTABLE[44]) #endif -#if defined(TARGET_IS_TM4C129_RA1) -#define ROM_USBOTGHostRequest \ - ((void (*)(uint32_t ui32Base, \ - bool bHNP))ROM_USBTABLE[45]) -#endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_USBModeGet \ ((uint32_t (*)(uint32_t ui32Base))ROM_USBTABLE[46]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_USBEndpointDMAChannel \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32Endpoint, \ @@ -6437,8 +7683,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_USBIntDisableControl \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32IntFlags))ROM_USBTABLE[48]) @@ -6446,8 +7694,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_USBIntEnableControl \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32IntFlags))ROM_USBTABLE[49]) @@ -6455,16 +7705,20 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_USBIntStatusControl \ ((uint32_t (*)(uint32_t ui32Base))ROM_USBTABLE[50]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_USBIntDisableEndpoint \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32IntFlags))ROM_USBTABLE[51]) @@ -6472,8 +7726,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_USBIntEnableEndpoint \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32IntFlags))ROM_USBTABLE[52]) @@ -6481,130 +7737,157 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_USBIntStatusEndpoint \ ((uint32_t (*)(uint32_t ui32Base))ROM_USBTABLE[53]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_USBHostMode \ ((void (*)(uint32_t ui32Base))ROM_USBTABLE[54]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_USBDevMode \ ((void (*)(uint32_t ui32Base))ROM_USBTABLE[55]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_USBPHYPowerOff \ ((void (*)(uint32_t ui32Base))ROM_USBTABLE[56]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_USBPHYPowerOn \ ((void (*)(uint32_t ui32Base))ROM_USBTABLE[57]) #endif #if defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_UpdateUSB \ ((void (*)(uint8_t *pui8DescriptorInfo))ROM_USBTABLE[58]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_USBOTGMode \ ((void (*)(uint32_t ui32Base))ROM_USBTABLE[59]) #endif #if defined(TARGET_IS_TM4C123_RB1) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_USBHostRequestINClear \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32Endpoint))ROM_USBTABLE[60]) #endif #if defined(TARGET_IS_TM4C123_RB1) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_USBNumEndpointsGet \ ((uint32_t (*)(uint32_t ui32Base))ROM_USBTABLE[61]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_USBClockDisable \ ((void (*)(uint32_t ui32Base))ROM_USBTABLE[62]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_USBClockEnable \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32Div, \ uint32_t ui32Flags))ROM_USBTABLE[63]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_USBControllerVersion \ ((uint32_t (*)(uint32_t ui32Base))ROM_USBTABLE[64]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_USBDevLPMConfig \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32Config))ROM_USBTABLE[65]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_USBDevLPMDisable \ ((void (*)(uint32_t ui32Base))ROM_USBTABLE[66]) #endif #if defined(TARGET_IS_TM4C123_RB1) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_USBDevLPMEnable \ ((void (*)(uint32_t ui32Base))ROM_USBTABLE[67]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_USBDevLPMRemoteWake \ ((void (*)(uint32_t ui32Base))ROM_USBTABLE[68]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_USBDevSpeedGet \ ((uint32_t (*)(uint32_t ui32Base))ROM_USBTABLE[69]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_USBDMAChannelAddressGet \ ((void * (*)(uint32_t ui32Base, \ uint32_t ui32Channel))ROM_USBTABLE[70]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_USBDMAChannelAddressSet \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32Channel, \ void *pvAddress))ROM_USBTABLE[71]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_USBDMAChannelConfigSet \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32Channel, \ @@ -6612,179 +7895,209 @@ uint32_t ui32Config))ROM_USBTABLE[72]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_USBDMAChannelDisable \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32Channel))ROM_USBTABLE[73]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_USBDMAChannelEnable \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32Channel))ROM_USBTABLE[74]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_USBDMAChannelIntDisable \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32Channel))ROM_USBTABLE[75]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_USBDMAChannelIntEnable \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32Channel))ROM_USBTABLE[76]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_USBDMAChannelCountGet \ ((uint32_t (*)(uint32_t ui32Base, \ uint32_t ui32Channel))ROM_USBTABLE[77]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_USBDMAChannelCountSet \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32Count, \ uint32_t ui32Channel))ROM_USBTABLE[78]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_USBDMAChannelIntStatus \ ((uint32_t (*)(uint32_t ui32Base))ROM_USBTABLE[79]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_USBDMAChannelStatus \ ((uint32_t (*)(uint32_t ui32Base, \ uint32_t ui32Channel))ROM_USBTABLE[80]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_USBDMAChannelStatusClear \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32Channel, \ uint32_t ui32Status))ROM_USBTABLE[81]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_USBHighSpeed \ ((void (*)(uint32_t ui32Base, \ bool bEnable))ROM_USBTABLE[82]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_USBHostEndpointPing \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32Endpoint, \ bool bEnable))ROM_USBTABLE[83]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_USBHostEndpointSpeed \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32Endpoint, \ uint32_t ui32Flags))ROM_USBTABLE[84]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_USBHostLPMConfig \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32ResumeTime, \ uint32_t ui32Config))ROM_USBTABLE[85]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_USBHostLPMResume \ ((void (*)(uint32_t ui32Base))ROM_USBTABLE[86]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_USBHostLPMSend \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32Address, \ uint32_t uiEndpoint))ROM_USBTABLE[87]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_USBLPMIntDisable \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32Ints))ROM_USBTABLE[88]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_USBLPMIntEnable \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32Ints))ROM_USBTABLE[89]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_USBLPMIntStatus \ ((uint32_t (*)(uint32_t ui32Base))ROM_USBTABLE[90]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_USBLPMLinkStateGet \ ((uint32_t (*)(uint32_t ui32Base))ROM_USBTABLE[91]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_USBEndpointPacketCountSet \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32Endpoint, \ uint32_t ui32Count))ROM_USBTABLE[92]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_USBULPIConfig \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32Config))ROM_USBTABLE[93]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_USBULPIDisable \ ((void (*)(uint32_t ui32Base))ROM_USBTABLE[94]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_USBULPIEnable \ ((void (*)(uint32_t ui32Base))ROM_USBTABLE[95]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_USBULPIRegRead \ ((uint8_t (*)(uint32_t ui32Base, \ uint8_t ui8Reg))ROM_USBTABLE[96]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_USBULPIRegWrite \ ((void (*)(uint32_t ui32Base, \ uint8_t ui8Reg, \ uint8_t ui8Data))ROM_USBTABLE[97]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_USBOTGSessionRequest \ ((void (*)(uint32_t ui32Base, \ bool bStart))ROM_USBTABLE[98]) #endif -#if defined(TARGET_IS_TM4C129_RA1) +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_USBDMANumChannels \ ((uint32_t (*)(uint32_t ui32Base))ROM_USBTABLE[99]) #endif -#if defined(TARGET_IS_TM4C129_RA1) +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_USBEndpointDMAConfigSet \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32Endpoint, \ uint32_t ui32Config))ROM_USBTABLE[100]) #endif -#if defined(TARGET_IS_TM4C129_RA1) +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_USBLPMRemoteWakeEnabled \ ((bool (*)(uint32_t ui32Base))ROM_USBTABLE[102]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_USBModeConfig \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32Mode))ROM_USBTABLE[103]) @@ -6798,72 +8111,90 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_WatchdogIntClear \ ((void (*)(uint32_t ui32Base))ROM_WATCHDOGTABLE[0]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_WatchdogRunning \ ((bool (*)(uint32_t ui32Base))ROM_WATCHDOGTABLE[1]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_WatchdogEnable \ ((void (*)(uint32_t ui32Base))ROM_WATCHDOGTABLE[2]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_WatchdogResetEnable \ ((void (*)(uint32_t ui32Base))ROM_WATCHDOGTABLE[3]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_WatchdogResetDisable \ ((void (*)(uint32_t ui32Base))ROM_WATCHDOGTABLE[4]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_WatchdogLock \ ((void (*)(uint32_t ui32Base))ROM_WATCHDOGTABLE[5]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_WatchdogUnlock \ ((void (*)(uint32_t ui32Base))ROM_WATCHDOGTABLE[6]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_WatchdogLockState \ ((bool (*)(uint32_t ui32Base))ROM_WATCHDOGTABLE[7]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_WatchdogReloadSet \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32LoadVal))ROM_WATCHDOGTABLE[8]) @@ -6871,32 +8202,40 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_WatchdogReloadGet \ ((uint32_t (*)(uint32_t ui32Base))ROM_WATCHDOGTABLE[9]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_WatchdogValueGet \ ((uint32_t (*)(uint32_t ui32Base))ROM_WATCHDOGTABLE[10]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_WatchdogIntEnable \ ((void (*)(uint32_t ui32Base))ROM_WATCHDOGTABLE[11]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_WatchdogIntStatus \ ((uint32_t (*)(uint32_t ui32Base, \ bool bMasked))ROM_WATCHDOGTABLE[12]) @@ -6904,24 +8243,30 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_WatchdogStallEnable \ ((void (*)(uint32_t ui32Base))ROM_WATCHDOGTABLE[13]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_WatchdogStallDisable \ ((void (*)(uint32_t ui32Base))ROM_WATCHDOGTABLE[14]) #endif #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_WatchdogIntTypeSet \ ((void (*)(uint32_t ui32Base, \ uint32_t ui32Type))ROM_WATCHDOGTABLE[15]) @@ -6935,8 +8280,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_Crc16Array \ ((uint16_t (*)(uint32_t ui32WordLen, \ const uint32_t *pui32Data))ROM_SOFTWARETABLE[1]) @@ -6944,8 +8291,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_Crc16Array3 \ ((void (*)(uint32_t ui32WordLen, \ const uint32_t *pui32Data, \ @@ -6954,8 +8303,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_Crc16 \ ((uint16_t (*)(uint16_t ui16Crc, \ const uint8_t *pui8Data, \ @@ -6964,15 +8315,18 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_Crc8CCITT \ ((uint8_t (*)(uint8_t ui8Crc, \ const uint8_t *pui8Data, \ uint32_t ui32Count))ROM_SOFTWARETABLE[4]) #endif #if defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_Crc32 \ ((uint32_t (*)(uint32_t ui32Crc, \ const uint8_t *pui8Data, \ @@ -6981,8 +8335,10 @@ #if defined(TARGET_IS_TM4C123_RA1) || \ defined(TARGET_IS_TM4C123_RA3) || \ defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ defined(TARGET_IS_TM4C129_RA0) || \ - defined(TARGET_IS_TM4C129_RA1) + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) #define ROM_pvAESTable \ ((void *)&(ROM_SOFTWARETABLE[7])) #endif diff --git a/bsp/tm4c129x/libraries/driverlib/rom_map.h b/bsp/tm4c129x/libraries/driverlib/rom_map.h index f7bcb0feed..e45ede445f 100644 --- a/bsp/tm4c129x/libraries/driverlib/rom_map.h +++ b/bsp/tm4c129x/libraries/driverlib/rom_map.h @@ -3,7 +3,7 @@ // rom_map.h - Macros to facilitate calling functions in the ROM when they are // available and in flash otherwise. // -// Copyright (c) 2008-2014 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2008-2017 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Redistribution and use in source and binary forms, with or without @@ -34,7 +34,7 @@ // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library. +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. // //***************************************************************************** @@ -5854,13 +5854,6 @@ #define MAP_USBEndpointDataAvail \ USBEndpointDataAvail #endif -#ifdef ROM_USBOTGHostRequest -#define MAP_USBOTGHostRequest \ - ROM_USBOTGHostRequest -#else -#define MAP_USBOTGHostRequest \ - USBOTGHostRequest -#endif #ifdef ROM_USBModeGet #define MAP_USBModeGet \ ROM_USBModeGet diff --git a/bsp/tm4c129x/libraries/driverlib/rtos_bindings.h b/bsp/tm4c129x/libraries/driverlib/rtos_bindings.h index d796ff0618..90762502c0 100644 --- a/bsp/tm4c129x/libraries/driverlib/rtos_bindings.h +++ b/bsp/tm4c129x/libraries/driverlib/rtos_bindings.h @@ -3,7 +3,7 @@ // rtos_bindings.h - Macros intended to aid porting of TivaWare modules // for use with an RTOS. // -// Copyright (c) 2012-2014 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2012-2017 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Redistribution and use in source and binary forms, with or without @@ -34,7 +34,7 @@ // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library. +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. // //***************************************************************************** diff --git a/bsp/tm4c129x/libraries/driverlib/shamd5.c b/bsp/tm4c129x/libraries/driverlib/shamd5.c index f04e07851a..d748ac4bb5 100644 --- a/bsp/tm4c129x/libraries/driverlib/shamd5.c +++ b/bsp/tm4c129x/libraries/driverlib/shamd5.c @@ -2,7 +2,7 @@ // // shamd5.c - Driver for the SHA/MD5 module. // -// Copyright (c) 2012-2014 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2012-2017 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Redistribution and use in source and binary forms, with or without @@ -33,7 +33,7 @@ // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library. +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. // //***************************************************************************** diff --git a/bsp/tm4c129x/libraries/driverlib/shamd5.h b/bsp/tm4c129x/libraries/driverlib/shamd5.h index f6091f8b46..3b0e793b4f 100644 --- a/bsp/tm4c129x/libraries/driverlib/shamd5.h +++ b/bsp/tm4c129x/libraries/driverlib/shamd5.h @@ -2,7 +2,7 @@ // // shamd5.h - Defines and Macros for the SHA/MD5. // -// Copyright (c) 2012-2014 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2012-2017 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Redistribution and use in source and binary forms, with or without @@ -33,7 +33,7 @@ // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library. +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. // //***************************************************************************** diff --git a/bsp/tm4c129x/libraries/driverlib/ssi.c b/bsp/tm4c129x/libraries/driverlib/ssi.c index edfec5589c..cf7a2d3bc2 100644 --- a/bsp/tm4c129x/libraries/driverlib/ssi.c +++ b/bsp/tm4c129x/libraries/driverlib/ssi.c @@ -2,7 +2,7 @@ // // ssi.c - Driver for Synchronous Serial Interface. // -// Copyright (c) 2005-2014 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Redistribution and use in source and binary forms, with or without @@ -33,7 +33,7 @@ // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library. +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. // //***************************************************************************** @@ -209,10 +209,12 @@ _SSIIntNumberGet(uint32_t ui32Base) //! The \e ui32DataWidth parameter defines the width of the data transfers and //! can be a value between 4 and 16, inclusive. //! -//! The peripheral clock is the same as the processor clock. This value is -//! returned by SysCtlClockGet(), or it can be explicitly hard coded if it is -//! constant and known (to save the code/execution overhead of a call to -//! SysCtlClockGet()). +//! The peripheral clock is the same as the processor clock. The frequency of +//! the system clock is the value returned by SysCtlClockGet() for TM4C123x +//! devices or the value returned by SysCtlClockFreqSet() for TM4C129x devices, +//! or it can be explicitly hard coded if it is constant and known (to save the +//! code/execution overhead of a call to SysCtlClockGet() or fetch of the +//! variable call holding the return value of SysCtlClockFreqSet()). //! //! \return None. // @@ -239,8 +241,7 @@ SSIConfigSetExpClk(uint32_t ui32Base, uint32_t ui32SSIClk, (ui32Protocol == SSI_FRF_TI) || (ui32Protocol == SSI_FRF_NMW)); ASSERT((ui32Mode == SSI_MODE_MASTER) || - (ui32Mode == SSI_MODE_SLAVE) || - (ui32Mode == SSI_MODE_SLAVE_OD)); + (ui32Mode == SSI_MODE_SLAVE)); ASSERT(((ui32Mode == SSI_MODE_MASTER) && (ui32BitRate <= (ui32SSIClk / 2))) || ((ui32Mode != SSI_MODE_MASTER) && @@ -251,8 +252,7 @@ SSIConfigSetExpClk(uint32_t ui32Base, uint32_t ui32SSIClk, // // Set the mode. // - ui32RegVal = (ui32Mode == SSI_MODE_SLAVE_OD) ? SSI_CR1_SOD : 0; - ui32RegVal |= (ui32Mode == SSI_MODE_MASTER) ? 0 : SSI_CR1_MS; + ui32RegVal = (ui32Mode == SSI_MODE_MASTER) ? 0 : SSI_CR1_MS; HWREG(ui32Base + SSI_O_CR1) = ui32RegVal; // diff --git a/bsp/tm4c129x/libraries/driverlib/ssi.h b/bsp/tm4c129x/libraries/driverlib/ssi.h index e27f2f6739..37d928dd1b 100644 --- a/bsp/tm4c129x/libraries/driverlib/ssi.h +++ b/bsp/tm4c129x/libraries/driverlib/ssi.h @@ -2,7 +2,7 @@ // // ssi.h - Prototypes for the Synchronous Serial Interface Driver. // -// Copyright (c) 2005-2014 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Redistribution and use in source and binary forms, with or without @@ -33,7 +33,7 @@ // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library. +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. // //***************************************************************************** diff --git a/bsp/tm4c129x/libraries/driverlib/sw_crc.c b/bsp/tm4c129x/libraries/driverlib/sw_crc.c index 9d4ead59bf..0706c34d50 100644 --- a/bsp/tm4c129x/libraries/driverlib/sw_crc.c +++ b/bsp/tm4c129x/libraries/driverlib/sw_crc.c @@ -2,7 +2,7 @@ // // sw_crc.c - Software CRC functions. // -// Copyright (c) 2010-2014 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2010-2017 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Redistribution and use in source and binary forms, with or without @@ -33,7 +33,7 @@ // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library. +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. // //***************************************************************************** diff --git a/bsp/tm4c129x/libraries/driverlib/sw_crc.h b/bsp/tm4c129x/libraries/driverlib/sw_crc.h index 6fd23b3310..0e60775ffc 100644 --- a/bsp/tm4c129x/libraries/driverlib/sw_crc.h +++ b/bsp/tm4c129x/libraries/driverlib/sw_crc.h @@ -2,7 +2,7 @@ // // sw_crc.h - Prototypes for the software CRC functions. // -// Copyright (c) 2010-2014 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2010-2017 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Redistribution and use in source and binary forms, with or without @@ -33,7 +33,7 @@ // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library. +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. // //***************************************************************************** diff --git a/bsp/tm4c129x/libraries/driverlib/sysctl.c b/bsp/tm4c129x/libraries/driverlib/sysctl.c index 8eb57ff864..161b5fa6d7 100644 --- a/bsp/tm4c129x/libraries/driverlib/sysctl.c +++ b/bsp/tm4c129x/libraries/driverlib/sysctl.c @@ -2,7 +2,7 @@ // // sysctl.c - Driver for the system controller. // -// Copyright (c) 2005-2014 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Redistribution and use in source and binary forms, with or without @@ -33,7 +33,7 @@ // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library. +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. // //***************************************************************************** @@ -128,59 +128,61 @@ static const uint32_t g_pui32Xtals[] = ((uint32_t)mi | (uint32_t)(mf << SYSCTL_PLLFREQ0_MFRAC_S)) #define PLL_N_TO_REG(n) \ ((uint32_t)(n - 1) << SYSCTL_PLLFREQ1_N_S) +#define PLL_Q_TO_REG(q) \ + ((uint32_t)(q - 1) << SYSCTL_PLLFREQ1_Q_S) //***************************************************************************** // // Look up of the values that go into the PLLFREQ0 and PLLFREQ1 registers. // //***************************************************************************** -static const uint32_t g_pppui32XTALtoVCO[MAX_VCO_ENTRIES][MAX_XTAL_ENTRIES][2] = +static const uint32_t g_pppui32XTALtoVCO[MAX_VCO_ENTRIES][MAX_XTAL_ENTRIES][3] = { { // // VCO 320 MHz // - { PLL_M_TO_REG(64, 0), PLL_N_TO_REG(1) }, // 5 MHz - { PLL_M_TO_REG(62, 512), PLL_N_TO_REG(1) }, // 5.12 MHz - { PLL_M_TO_REG(160, 0), PLL_N_TO_REG(3) }, // 6 MHz - { PLL_M_TO_REG(52, 85), PLL_N_TO_REG(1) }, // 6.144 MHz - { PLL_M_TO_REG(43, 412), PLL_N_TO_REG(1) }, // 7.3728 MHz - { PLL_M_TO_REG(40, 0), PLL_N_TO_REG(1) }, // 8 MHz - { PLL_M_TO_REG(39, 64), PLL_N_TO_REG(1) }, // 8.192 MHz - { PLL_M_TO_REG(32, 0), PLL_N_TO_REG(1) }, // 10 MHz - { PLL_M_TO_REG(80, 0), PLL_N_TO_REG(3) }, // 12 MHz - { PLL_M_TO_REG(26, 43), PLL_N_TO_REG(1) }, // 12.288 MHz - { PLL_M_TO_REG(23, 613), PLL_N_TO_REG(1) }, // 13.56 MHz - { PLL_M_TO_REG(22, 358), PLL_N_TO_REG(1) }, // 14.318180 MHz - { PLL_M_TO_REG(20, 0), PLL_N_TO_REG(1) }, // 16 MHz - { PLL_M_TO_REG(19, 544), PLL_N_TO_REG(1) }, // 16.384 MHz - { PLL_M_TO_REG(160, 0), PLL_N_TO_REG(9) }, // 18 MHz - { PLL_M_TO_REG(16, 0), PLL_N_TO_REG(1) }, // 20 MHz - { PLL_M_TO_REG(40, 0), PLL_N_TO_REG(3) }, // 24 MHz - { PLL_M_TO_REG(64, 0), PLL_N_TO_REG(5) }, // 25 MHz + { PLL_M_TO_REG(64, 0), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 5 MHz + { PLL_M_TO_REG(62, 512), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 5.12 MHz + { PLL_M_TO_REG(160, 0), PLL_N_TO_REG(3), PLL_Q_TO_REG(2) }, // 6 MHz + { PLL_M_TO_REG(52, 85), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 6.144 MHz + { PLL_M_TO_REG(43, 412), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 7.3728 MHz + { PLL_M_TO_REG(40, 0), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 8 MHz + { PLL_M_TO_REG(39, 64), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 8.192 MHz + { PLL_M_TO_REG(32, 0), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 10 MHz + { PLL_M_TO_REG(80, 0), PLL_N_TO_REG(3), PLL_Q_TO_REG(2) }, // 12 MHz + { PLL_M_TO_REG(26, 43), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 12.288 MHz + { PLL_M_TO_REG(23, 613), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 13.56 MHz + { PLL_M_TO_REG(22, 358), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 14.318180 MHz + { PLL_M_TO_REG(20, 0), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 16 MHz + { PLL_M_TO_REG(19, 544), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 16.384 MHz + { PLL_M_TO_REG(160, 0), PLL_N_TO_REG(9), PLL_Q_TO_REG(2) }, // 18 MHz + { PLL_M_TO_REG(16, 0), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 20 MHz + { PLL_M_TO_REG(40, 0), PLL_N_TO_REG(3), PLL_Q_TO_REG(2) }, // 24 MHz + { PLL_M_TO_REG(64, 0), PLL_N_TO_REG(5), PLL_Q_TO_REG(2) }, // 25 MHz }, { // // VCO 480 MHz // - { PLL_M_TO_REG(96, 0), PLL_N_TO_REG(1) }, // 5 MHz - { PLL_M_TO_REG(93, 768), PLL_N_TO_REG(1) }, // 5.12 MHz - { PLL_M_TO_REG(80, 0), PLL_N_TO_REG(1) }, // 6 MHz - { PLL_M_TO_REG(78, 128), PLL_N_TO_REG(1) }, // 6.144 MHz - { PLL_M_TO_REG(65, 107), PLL_N_TO_REG(1) }, // 7.3728 MHz - { PLL_M_TO_REG(60, 0), PLL_N_TO_REG(1) }, // 8 MHz - { PLL_M_TO_REG(58, 608), PLL_N_TO_REG(1) }, // 8.192 MHz - { PLL_M_TO_REG(48, 0), PLL_N_TO_REG(1) }, // 10 MHz - { PLL_M_TO_REG(40, 0), PLL_N_TO_REG(1) }, // 12 MHz - { PLL_M_TO_REG(39, 64), PLL_N_TO_REG(1) }, // 12.288 MHz - { PLL_M_TO_REG(35, 408), PLL_N_TO_REG(1) }, // 13.56 MHz - { PLL_M_TO_REG(33, 536), PLL_N_TO_REG(1) }, // 14.318180 MHz - { PLL_M_TO_REG(30, 0), PLL_N_TO_REG(1) }, // 16 MHz - { PLL_M_TO_REG(29, 304), PLL_N_TO_REG(1) }, // 16.384 MHz - { PLL_M_TO_REG(80, 0), PLL_N_TO_REG(3) }, // 18 MHz - { PLL_M_TO_REG(24, 0), PLL_N_TO_REG(1) }, // 20 MHz - { PLL_M_TO_REG(20, 0), PLL_N_TO_REG(1) }, // 24 MHz - { PLL_M_TO_REG(96, 0), PLL_N_TO_REG(5) }, // 25 MHz + { PLL_M_TO_REG(96, 0), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 5 MHz + { PLL_M_TO_REG(93, 768), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 5.12 MHz + { PLL_M_TO_REG(80, 0), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 6 MHz + { PLL_M_TO_REG(78, 128), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 6.144 MHz + { PLL_M_TO_REG(65, 107), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 7.3728 MHz + { PLL_M_TO_REG(60, 0), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 8 MHz + { PLL_M_TO_REG(58, 608), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 8.192 MHz + { PLL_M_TO_REG(48, 0), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 10 MHz + { PLL_M_TO_REG(40, 0), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 12 MHz + { PLL_M_TO_REG(39, 64), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 12.288 MHz + { PLL_M_TO_REG(35, 408), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 13.56 MHz + { PLL_M_TO_REG(33, 536), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 14.318180 MHz + { PLL_M_TO_REG(30, 0), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 16 MHz + { PLL_M_TO_REG(29, 304), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 16.384 MHz + { PLL_M_TO_REG(80, 0), PLL_N_TO_REG(3), PLL_Q_TO_REG(2) }, // 18 MHz + { PLL_M_TO_REG(24, 0), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 20 MHz + { PLL_M_TO_REG(20, 0), PLL_N_TO_REG(1), PLL_Q_TO_REG(2) }, // 24 MHz + { PLL_M_TO_REG(96, 0), PLL_N_TO_REG(5), PLL_Q_TO_REG(2) }, // 25 MHz }, }; @@ -202,7 +204,7 @@ g_sXTALtoMEMTIM[] = (0 << SYSCTL_MEMTIM0_EWS_S) | SYSCTL_MEMTIM0_MB1) }, { 40000000, (SYSCTL_MEMTIM0_FBCHT_1_5 | (1 << SYSCTL_MEMTIM0_FWS_S) | - SYSCTL_MEMTIM0_FBCHT_1_5 | (1 << SYSCTL_MEMTIM0_EWS_S) | + SYSCTL_MEMTIM0_EBCHT_1_5 | (1 << SYSCTL_MEMTIM0_EWS_S) | SYSCTL_MEMTIM0_MB1) }, { 60000000, (SYSCTL_MEMTIM0_FBCHT_2 | (2 << SYSCTL_MEMTIM0_FWS_S) | SYSCTL_MEMTIM0_EBCHT_2 | (2 << SYSCTL_MEMTIM0_EWS_S) | @@ -329,8 +331,8 @@ _SysCtlFrequencyGet(uint32_t ui32Xtal) //***************************************************************************** static const uint32_t g_pui32VCOFrequencies[MAX_VCO_ENTRIES] = { - 320000000, // VCO 320 - 480000000, // VCO 480 + 160000000, // VCO 320 + 240000000, // VCO 480 }; //***************************************************************************** @@ -418,6 +420,8 @@ _SysCtlPeripheralValid(uint32_t ui32Peripheral) (ui32Peripheral == SYSCTL_PERIPH_TIMER3) || (ui32Peripheral == SYSCTL_PERIPH_TIMER4) || (ui32Peripheral == SYSCTL_PERIPH_TIMER5) || + (ui32Peripheral == SYSCTL_PERIPH_TIMER6) || + (ui32Peripheral == SYSCTL_PERIPH_TIMER7) || (ui32Peripheral == SYSCTL_PERIPH_UART0) || (ui32Peripheral == SYSCTL_PERIPH_UART1) || (ui32Peripheral == SYSCTL_PERIPH_UART2) || @@ -2076,6 +2080,13 @@ SysCtlResetBehaviorGet(void) //! function returns the current system frequency which may not match the //! requested frequency. //! +//! If the application is using an external crystal then the frequency is +//! set by using one of the following values: +//! \b SYSCTL_XTAL_5MHZ, \b SYSCTL_XTAL_6MHZ, \b SYSCTL_XTAL_8MHZ, +//! \b SYSCTL_XTAL_10MHZ, \b SYSCTL_XTAL_12MHZ, \b SYSCTL_XTAL_16MHZ, +//! \b SYSCTL_XTAL_18MHZ, \b SYSCTL_XTAL_20MHZ, \b SYSCTL_XTAL_24MHZ, or +//! \b SYSCTL_XTAL_25MHz. +//! //! The oscillator source is chosen with one of the following values: //! //! - \b SYSCTL_OSC_MAIN to use an external crystal or oscillator. @@ -2116,8 +2127,8 @@ SysCtlClockFreqSet(uint32_t ui32Config, uint32_t ui32SysClock) { int32_t i32Timeout, i32VCOIdx, i32XtalIdx; uint32_t ui32MOSCCTL; + uint32_t ui32Delay; uint32_t ui32SysDiv, ui32Osc, ui32OscSelect, ui32RSClkConfig; - bool bNewPLL; // // TM4C123 devices should not use this function. @@ -2205,6 +2216,32 @@ SysCtlClockFreqSet(uint32_t ui32Config, uint32_t ui32SysClock) } HWREG(SYSCTL_MOSCCTL) = ui32MOSCCTL; + + // + // Timeout using the legacy delay value. + // + ui32Delay = 524288; + + while((HWREG(SYSCTL_RIS) & SYSCTL_RIS_MOSCPUPRIS) == 0) + { + ui32Delay--; + + if(ui32Delay == 0) + { + break; + } + } + + // + // If the main oscillator failed to start up then do not switch to + // it and return. + // + if(ui32Delay == 0) + { + return(0); + } + + } else { @@ -2271,54 +2308,32 @@ SysCtlClockFreqSet(uint32_t ui32Config, uint32_t ui32SysClock) i32XtalIdx -= SysCtlXtalCfgToIndex(SYSCTL_XTAL_5MHZ); // - // If there were no changes to the PLL do not force the PLL to lock by - // writing the PLL settings. + // Calculate the System divider such that we get a frequency that is + // the closest to the requested frequency without going over. // - if((HWREG(SYSCTL_PLLFREQ1) != - g_pppui32XTALtoVCO[i32VCOIdx][i32XtalIdx][1]) || - (HWREG(SYSCTL_PLLFREQ0) != - (g_pppui32XTALtoVCO[i32VCOIdx][i32XtalIdx][0] | - SYSCTL_PLLFREQ0_PLLPWR))) - { - bNewPLL = true; - } - else - { - bNewPLL = false; - } + ui32SysDiv = (g_pui32VCOFrequencies[i32VCOIdx] + ui32SysClock - 1) / + ui32SysClock; // - // If there are new PLL settings write them. + // Set the oscillator source. // - if(bNewPLL) - { - // - // Set the oscillator source. - // - HWREG(SYSCTL_RSCLKCFG) |= ui32OscSelect; - - // - // Set the M, N and Q values provided from the table and preserve - // the power state of the main PLL. - // - HWREG(SYSCTL_PLLFREQ1) = - g_pppui32XTALtoVCO[i32VCOIdx][i32XtalIdx][1]; - HWREG(SYSCTL_PLLFREQ0) = - (g_pppui32XTALtoVCO[i32VCOIdx][i32XtalIdx][0] | - (HWREG(SYSCTL_PLLFREQ0) & SYSCTL_PLLFREQ0_PLLPWR)); - } + HWREG(SYSCTL_RSCLKCFG) |= ui32OscSelect; // - // Calculate the System divider such that we get a frequency that is - // the closest to the requested frequency without going over. + // Set the M, N and Q values provided from the table and preserve + // the power state of the main PLL. // - ui32SysDiv = (g_pui32VCOFrequencies[i32VCOIdx] + ui32SysClock - 1) / - ui32SysClock; + HWREG(SYSCTL_PLLFREQ1) = + g_pppui32XTALtoVCO[i32VCOIdx][i32XtalIdx][1]; + HWREG(SYSCTL_PLLFREQ1) |= PLL_Q_TO_REG(ui32SysDiv); + HWREG(SYSCTL_PLLFREQ0) = + (g_pppui32XTALtoVCO[i32VCOIdx][i32XtalIdx][0] | + (HWREG(SYSCTL_PLLFREQ0) & SYSCTL_PLLFREQ0_PLLPWR)); // - // Calculate the actual system clock. + // Calculate the actual system clock as PSYSDIV is always div-by 2. // - ui32SysClock = _SysCtlFrequencyGet(ui32Osc) / ui32SysDiv; + ui32SysClock = _SysCtlFrequencyGet(ui32Osc) / 2; // // Set the Flash and EEPROM timing values. @@ -2330,13 +2345,10 @@ SysCtlClockFreqSet(uint32_t ui32Config, uint32_t ui32SysClock) // if(HWREG(SYSCTL_PLLFREQ0) & SYSCTL_PLLFREQ0_PLLPWR) { - if(bNewPLL == true) - { - // - // Trigger the PLL to lock to the new frequency. - // - HWREG(SYSCTL_RSCLKCFG) |= SYSCTL_RSCLKCFG_NEWFREQ; - } + // + // Trigger the PLL to lock to the new frequency. + // + HWREG(SYSCTL_RSCLKCFG) |= SYSCTL_RSCLKCFG_NEWFREQ; } else { @@ -2363,9 +2375,8 @@ SysCtlClockFreqSet(uint32_t ui32Config, uint32_t ui32SysClock) if(i32Timeout) { ui32RSClkConfig = HWREG(SYSCTL_RSCLKCFG); - ui32RSClkConfig |= ((ui32SysDiv - 1) << - SYSCTL_RSCLKCFG_PSYSDIV_S) | ui32OscSelect | - SYSCTL_RSCLKCFG_USEPLL; + ui32RSClkConfig |= (1 << SYSCTL_RSCLKCFG_PSYSDIV_S) | + ui32OscSelect | SYSCTL_RSCLKCFG_USEPLL; ui32RSClkConfig |= SYSCTL_RSCLKCFG_MEMTIMU; // @@ -2462,6 +2473,11 @@ SysCtlClockFreqSet(uint32_t ui32Config, uint32_t ui32SysClock) HWREG(SYSCTL_RSCLKCFG) = ui32RSClkConfig; } + // + // Finally change the OSCSRC back to PIOSC + // + HWREG(SYSCTL_RSCLKCFG) &= ~(SYSCTL_RSCLKCFG_OSCSRC_M); + return(ui32SysClock); } @@ -2865,11 +2881,6 @@ SysCtlClockGet(void) ui32Max = 80000000; break; } - case SYSCTL_DC1_MINSYSDIV_66: - { - ui32Max = 66666666; - break; - } case SYSCTL_DC1_MINSYSDIV_50: { ui32Max = 50000000; @@ -3507,6 +3518,93 @@ SysCtlVoltageEventClear(uint32_t ui32Status) HWREG(SYSCTL_PWRTC) |= ui32Status; } +//***************************************************************************** +// +//! Gets the effective VCO frequency. +//! +//! \param ui32Crystal holds the crystal value used for the PLL. +//! \param pui32VCOFrequency is a pointer to the storage location which holds +//! value of the VCO computed. +//! +//! This function calculates the VCO of the PLL before the system divider is +//! applied +//! +//! \return \b true if the PLL is configured correctly and a VCO is valid or +//! \b false if the device is not TM4C129x or the PLL is not used +// +//***************************************************************************** +bool +SysCtlVCOGet(uint32_t ui32Crystal, uint32_t *pui32VCOFrequency) +{ + int32_t i32XtalIdx; + uint32_t ui32RSClkConfig, ui32PLLFreq0, ui32PLLFreq1, ui32Osc; + uint32_t ui32MInt, ui32MFrac, ui32NDiv, ui32QDiv, ui32TempVCO; + + // + // Check if TM4C123 device is being used. should not use this function. + // + if(CLASS_IS_TM4C123) + { + // + // Return error if TM4C123. + // + *pui32VCOFrequency = 0; + return(false); + } + + // + // Read the RSCLKCFG register to determine if PLL is being used. + // + ui32RSClkConfig = HWREG(SYSCTL_RSCLKCFG); + + // + // Check if PLL is used. + // + if((ui32RSClkConfig & SYSCTL_RSCLKCFG_USEPLL) != SYSCTL_RSCLKCFG_USEPLL) + { + // + // Return error if PLL is not used. + // + *pui32VCOFrequency = 0; + return(false); + } + + // + // Get the index of the crystal from the ui32Config parameter. + // + i32XtalIdx = SysCtlXtalCfgToIndex(ui32Crystal); + + // + // Get the value of the crystal frequency based on the index + // + ui32Osc = g_pui32Xtals[i32XtalIdx]; + + // + // Read the PLLFREQ0 and PLLFREQ1 registers to get information on the + // MINT, MFRAC, N and Q values of the PLL + // + ui32PLLFreq0 = HWREG(SYSCTL_PLLFREQ0); + ui32PLLFreq1 = HWREG(SYSCTL_PLLFREQ1); + + ui32MInt = (ui32PLLFreq0 & SYSCTL_PLLFREQ0_MINT_M) >> + SYSCTL_PLLFREQ0_MINT_S; + ui32MFrac = (ui32PLLFreq0 & SYSCTL_PLLFREQ0_MFRAC_M) >> + SYSCTL_PLLFREQ0_MFRAC_S; + ui32NDiv = (ui32PLLFreq1 & SYSCTL_PLLFREQ1_N_M) >> + SYSCTL_PLLFREQ1_N_S; + ui32QDiv = (ui32PLLFreq1 & SYSCTL_PLLFREQ1_Q_M) >> + SYSCTL_PLLFREQ1_Q_S; + + // + // Calculate the VCO at the output of the PLL + // + ui32TempVCO = (ui32Osc * ui32MInt) + ((ui32Osc * ui32MFrac) / 1024); + ui32TempVCO /= ((ui32NDiv + 1) * (ui32QDiv + 1)); + + *pui32VCOFrequency = ui32TempVCO; + return(true); +} + //***************************************************************************** // //! Returns the current NMI status. diff --git a/bsp/tm4c129x/libraries/driverlib/sysctl.h b/bsp/tm4c129x/libraries/driverlib/sysctl.h index c19d214b27..0bce4852d7 100644 --- a/bsp/tm4c129x/libraries/driverlib/sysctl.h +++ b/bsp/tm4c129x/libraries/driverlib/sysctl.h @@ -2,7 +2,7 @@ // // sysctl.h - Prototypes for the system control driver. // -// Copyright (c) 2005-2014 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Redistribution and use in source and binary forms, with or without @@ -33,7 +33,7 @@ // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library. +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. // //***************************************************************************** @@ -642,6 +642,7 @@ extern void SysCtlNMIClear(uint32_t ui32Status); extern void SysCtlVoltageEventConfig(uint32_t ui32Config); extern uint32_t SysCtlVoltageEventStatus(void); extern void SysCtlVoltageEventClear(uint32_t ui32Status); +extern bool SysCtlVCOGet(uint32_t ui32Crystal, uint32_t *pui32VCOFrequency); //***************************************************************************** // diff --git a/bsp/tm4c129x/libraries/driverlib/sysexc.c b/bsp/tm4c129x/libraries/driverlib/sysexc.c index c34d73be33..d269b74bcd 100644 --- a/bsp/tm4c129x/libraries/driverlib/sysexc.c +++ b/bsp/tm4c129x/libraries/driverlib/sysexc.c @@ -2,7 +2,7 @@ // // sysexc.c - Routines for the System Exception Module. // -// Copyright (c) 2011-2014 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2011-2017 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Redistribution and use in source and binary forms, with or without @@ -33,7 +33,7 @@ // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library. +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. // //***************************************************************************** diff --git a/bsp/tm4c129x/libraries/driverlib/sysexc.h b/bsp/tm4c129x/libraries/driverlib/sysexc.h index 10febaa333..aece4409d1 100644 --- a/bsp/tm4c129x/libraries/driverlib/sysexc.h +++ b/bsp/tm4c129x/libraries/driverlib/sysexc.h @@ -2,7 +2,7 @@ // // sysexc.h - Prototypes for the System Exception Module routines. // -// Copyright (c) 2011-2014 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2011-2017 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Redistribution and use in source and binary forms, with or without @@ -33,7 +33,7 @@ // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library. +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. // //***************************************************************************** diff --git a/bsp/tm4c129x/libraries/driverlib/systick.c b/bsp/tm4c129x/libraries/driverlib/systick.c index e8b45b2f5b..662da1729e 100644 --- a/bsp/tm4c129x/libraries/driverlib/systick.c +++ b/bsp/tm4c129x/libraries/driverlib/systick.c @@ -2,7 +2,7 @@ // // systick.c - Driver for the SysTick timer in NVIC. // -// Copyright (c) 2005-2014 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Redistribution and use in source and binary forms, with or without @@ -33,7 +33,7 @@ // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library. +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. // //***************************************************************************** diff --git a/bsp/tm4c129x/libraries/driverlib/systick.h b/bsp/tm4c129x/libraries/driverlib/systick.h index 513f1ebdaa..35909ee3fb 100644 --- a/bsp/tm4c129x/libraries/driverlib/systick.h +++ b/bsp/tm4c129x/libraries/driverlib/systick.h @@ -2,7 +2,7 @@ // // systick.h - Prototypes for the SysTick driver. // -// Copyright (c) 2005-2014 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Redistribution and use in source and binary forms, with or without @@ -33,7 +33,7 @@ // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library. +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. // //***************************************************************************** diff --git a/bsp/tm4c129x/libraries/driverlib/tiva_timer.c b/bsp/tm4c129x/libraries/driverlib/tiva_timer.c index 7f1db43753..d348849570 100644 --- a/bsp/tm4c129x/libraries/driverlib/tiva_timer.c +++ b/bsp/tm4c129x/libraries/driverlib/tiva_timer.c @@ -2,7 +2,7 @@ // // timer.c - Driver for the timer module. // -// Copyright (c) 2005-2014 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Redistribution and use in source and binary forms, with or without @@ -33,7 +33,7 @@ // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library. +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. // //***************************************************************************** @@ -121,6 +121,7 @@ _TimerBaseValid(uint32_t ui32Base) return((ui32Base == TIMER0_BASE) || (ui32Base == TIMER1_BASE) || (ui32Base == TIMER2_BASE) || (ui32Base == TIMER3_BASE) || (ui32Base == TIMER4_BASE) || (ui32Base == TIMER5_BASE) || + (ui32Base == TIMER6_BASE) || (ui32Base == TIMER7_BASE) || (ui32Base == WTIMER0_BASE) || (ui32Base == WTIMER1_BASE) || (ui32Base == WTIMER2_BASE) || (ui32Base == WTIMER3_BASE) || (ui32Base == WTIMER4_BASE) || (ui32Base == WTIMER5_BASE)); @@ -362,7 +363,9 @@ TimerConfigure(uint32_t ui32Base, uint32_t ui32Config) ((ui32Config & 0x000000ff) == TIMER_CFG_A_PERIODIC) || ((ui32Config & 0x000000ff) == TIMER_CFG_A_PERIODIC_UP) || ((ui32Config & 0x000000ff) == TIMER_CFG_A_CAP_COUNT) || + ((ui32Config & 0x000000ff) == TIMER_CFG_A_CAP_COUNT_UP) || ((ui32Config & 0x000000ff) == TIMER_CFG_A_CAP_TIME) || + ((ui32Config & 0x000000ff) == TIMER_CFG_A_CAP_TIME_UP) || ((ui32Config & 0x000000ff) == TIMER_CFG_A_PWM)) && (((ui32Config & 0x0000ff00) == TIMER_CFG_B_ONE_SHOT) || ((ui32Config & 0x0000ff00) == TIMER_CFG_B_ONE_SHOT_UP) || diff --git a/bsp/tm4c129x/libraries/driverlib/tiva_timer.h b/bsp/tm4c129x/libraries/driverlib/tiva_timer.h index 3b52a8eba4..7eb619a7e0 100644 --- a/bsp/tm4c129x/libraries/driverlib/tiva_timer.h +++ b/bsp/tm4c129x/libraries/driverlib/tiva_timer.h @@ -2,7 +2,7 @@ // // timer.h - Prototypes for the timer module // -// Copyright (c) 2005-2014 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Redistribution and use in source and binary forms, with or without @@ -33,12 +33,12 @@ // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library. +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. // //***************************************************************************** -#ifndef __DRIVERLIB_TIVA_TIMER_H__ -#define __DRIVERLIB_TIVA_TIMER_H__ +#ifndef __DRIVERLIB_TIMER_H__ +#define __DRIVERLIB_TIMER_H__ //***************************************************************************** // diff --git a/bsp/tm4c129x/libraries/driverlib/uart.c b/bsp/tm4c129x/libraries/driverlib/uart.c index 9e31963cf6..847f464cea 100644 --- a/bsp/tm4c129x/libraries/driverlib/uart.c +++ b/bsp/tm4c129x/libraries/driverlib/uart.c @@ -2,7 +2,7 @@ // // uart.c - Driver for the UART. // -// Copyright (c) 2005-2014 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Redistribution and use in source and binary forms, with or without @@ -33,7 +33,7 @@ // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library. +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. // //***************************************************************************** @@ -352,9 +352,14 @@ UARTFIFOLevelGet(uint32_t ui32Base, uint32_t *pui32TxLevel, //! zero, respectively). //! //! The peripheral clock is the same as the processor clock. The frequency of -//! the system clock is the value returned by SysCtlClockGet(), or it can be -//! explicitly hard coded if it is constant and known (to save the -//! code/execution overhead of a call to SysCtlClockGet()). +//! the system clock is the value returned by SysCtlClockGet() for TM4C123x +//! devices or the value returned by SysCtlClockFreqSet() for TM4C129x devices, +//! or it can be explicitly hard coded if it is constant and known (to save the +//! code/execution overhead of a call to SysCtlClockGet() or fetch of the +//! variable call holding the return value of SysCtlClockFreqSet()). +//! +//! The function disables the UART by calling UARTDisable() before changing the +//! the parameters and enables the UART by calling UARTEnable(). //! //! For Tiva parts that have the ability to specify the UART baud clock //! source (via UARTClockSourceSet()), the peripheral clock can be changed to @@ -451,9 +456,11 @@ UARTConfigSetExpClk(uint32_t ui32Base, uint32_t ui32UARTClk, //! UARTConfigSetExpClk(). //! //! The peripheral clock is the same as the processor clock. The frequency of -//! the system clock is the value returned by SysCtlClockGet(), or it can be -//! explicitly hard coded if it is constant and known (to save the -//! code/execution overhead of a call to SysCtlClockGet()). +//! the system clock is the value returned by SysCtlClockGet() for TM4C123x +//! devices or the value returned by SysCtlClockFreqSet() for TM4C129x devices, +//! or it can be explicitly hard coded if it is constant and known (to save the +//! code/execution overhead of a call to SysCtlClockGet() or fetch of the +//! variable call holding the return value of SysCtlClockFreqSet()). //! //! For Tiva parts that have the ability to specify the UART baud clock //! source (via UARTClockSourceSet()), the peripheral clock can be changed to @@ -1950,6 +1957,35 @@ UART9BitAddrSend(uint32_t ui32Base, uint8_t ui8Addr) HWREG(ui32Base + UART_O_LCRH) = ui32LCRH; } +//***************************************************************************** +// +//! Enables internal loopback mode for a UART port +//! +//! \param ui32Base is the base address of the UART port. +//! +//! This function configures a UART port in internal loopback mode to help with +//! diagnostics and debug. In this mode, the transmit and receive terminals of +//! the same UART port are internally connected. Hence, the data transmitted +//! on the UnTx output is received on the UxRx input, without having to go +//! through I/O's. UARTCharPut(), UARTCharGet() functions can be used along +//! with this function. +//! +//! \return None. +// +//***************************************************************************** +void UARTLoopbackEnable(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(_UARTBaseValid(ui32Base)); + + // + // Write the Loopback Enable bit to register. + // + HWREG(ui32Base + UART_O_CTL) |= UART_CTL_LBE; +} + //***************************************************************************** // // Close the Doxygen group. diff --git a/bsp/tm4c129x/libraries/driverlib/uart.h b/bsp/tm4c129x/libraries/driverlib/uart.h index d898b6c4d8..3a9397550d 100644 --- a/bsp/tm4c129x/libraries/driverlib/uart.h +++ b/bsp/tm4c129x/libraries/driverlib/uart.h @@ -2,7 +2,7 @@ // // uart.h - Defines and Macros for the UART. // -// Copyright (c) 2005-2014 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Redistribution and use in source and binary forms, with or without @@ -33,7 +33,7 @@ // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library. +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. // //***************************************************************************** @@ -242,6 +242,7 @@ extern void UART9BitDisable(uint32_t ui32Base); extern void UART9BitAddrSet(uint32_t ui32Base, uint8_t ui8Addr, uint8_t ui8Mask); extern void UART9BitAddrSend(uint32_t ui32Base, uint8_t ui8Addr); +extern void UARTLoopbackEnable(uint32_t ui32Base); //***************************************************************************** // diff --git a/bsp/tm4c129x/libraries/driverlib/udma.c b/bsp/tm4c129x/libraries/driverlib/udma.c index c019a7dba5..bb2941af92 100644 --- a/bsp/tm4c129x/libraries/driverlib/udma.c +++ b/bsp/tm4c129x/libraries/driverlib/udma.c @@ -2,7 +2,7 @@ // // udma.c - Driver for the micro-DMA controller. // -// Copyright (c) 2007-2014 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2007-2017 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Redistribution and use in source and binary forms, with or without @@ -33,7 +33,7 @@ // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library. +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. // //***************************************************************************** @@ -1072,9 +1072,9 @@ uDMAChannelModeGet(uint32_t ui32ChannelStructIndex) //! controller generates an interrupt. The \e ui32IntChannel parameter should //! be one of the following: //! -//! - \b UDMA_INT_SW to register an interrupt handler to process interrupts +//! - \b INT_UDMA to register an interrupt handler to process interrupts //! from the uDMA software channel (UDMA_CHANNEL_SW) -//! - \b UDMA_INT_ERR to register an interrupt handler to process uDMA error +//! - \b INT_UDMAERR to register an interrupt handler to process uDMA error //! interrupts //! //! \sa IntRegister() for important information about registering interrupt @@ -1095,8 +1095,6 @@ uDMAIntRegister(uint32_t ui32IntChannel, void (*pfnHandler)(void)) // Check the arguments. // ASSERT(pfnHandler); - ASSERT((ui32IntChannel == UDMA_INT_SW) || - (ui32IntChannel == UDMA_INT_ERR)); // // Register the interrupt handler. @@ -1117,7 +1115,7 @@ uDMAIntRegister(uint32_t ui32IntChannel, void (*pfnHandler)(void)) //! //! This function disables and unregisters the handler to be called for the //! specified uDMA interrupt. The \e ui32IntChannel parameter should be one of -//! \b UDMA_INT_SW or \b UDMA_INT_ERR as documented for the function +//! \b INT_UDMA or \b INT_UDMAERR as documented for the function //! uDMAIntRegister(). //! //! \sa IntRegister() for important information about registering interrupt @@ -1230,7 +1228,7 @@ uDMAChannelAssign(uint32_t ui32Mapping) // // Check the parameters // - ASSERT((ui32Mapping & 0xffffff00) < 0x00050000); + ASSERT((ui32Mapping & 0xffffff00) < 0x00090000); // // Extract the channel number and map encoding value from the parameter. diff --git a/bsp/tm4c129x/libraries/driverlib/udma.h b/bsp/tm4c129x/libraries/driverlib/udma.h index 3412c84ba7..a8d3684489 100644 --- a/bsp/tm4c129x/libraries/driverlib/udma.h +++ b/bsp/tm4c129x/libraries/driverlib/udma.h @@ -2,7 +2,7 @@ // // udma.h - Prototypes and macros for the uDMA controller. // -// Copyright (c) 2007-2014 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2007-2017 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Redistribution and use in source and binary forms, with or without @@ -33,7 +33,7 @@ // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library. +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. // //***************************************************************************** @@ -290,15 +290,6 @@ tDMAControlTable; #define UDMA_PRI_SELECT 0x00000000 #define UDMA_ALT_SELECT 0x00000020 -//***************************************************************************** -// -// uDMA interrupt sources, to be passed to uDMAIntRegister() and -// uDMAIntUnregister(). -// -//***************************************************************************** -#define UDMA_INT_SW 62 -#define UDMA_INT_ERR 63 - //***************************************************************************** // // Channel numbers to be passed to API functions that require a channel number diff --git a/bsp/tm4c129x/libraries/driverlib/usb.c b/bsp/tm4c129x/libraries/driverlib/usb.c index 0f221f4448..839a5575ed 100644 --- a/bsp/tm4c129x/libraries/driverlib/usb.c +++ b/bsp/tm4c129x/libraries/driverlib/usb.c @@ -2,7 +2,7 @@ // // usb.c - Driver for the USB Interface. // -// Copyright (c) 2007-2014 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2007-2017 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Redistribution and use in source and binary forms, with or without @@ -33,7 +33,7 @@ // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library. +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. // //***************************************************************************** @@ -152,6 +152,7 @@ _USBIndexWrite(uint32_t ui32Base, uint32_t ui32Endpoint, // \param ui32Base specifies the USB module base address. // \param ui32Endpoint is the endpoint index to target for this write. // \param ui32IndexedReg is the indexed register to write to. +// \param ui32Size is a value of 1 or 2 indicating the byte size of the read. // // This function is used internally to access the indexed registers for each // endpoint. The only registers that are indexed are the FIFO configuration @@ -165,7 +166,7 @@ _USBIndexRead(uint32_t ui32Base, uint32_t ui32Endpoint, uint32_t ui32IndexedReg, uint32_t ui32Size) { uint8_t ui8Index; - uint8_t ui8Value; + uint32_t ui32Value; // // Check the arguments. @@ -193,14 +194,14 @@ _USBIndexRead(uint32_t ui32Base, uint32_t ui32Endpoint, // // Get the value. // - ui8Value = HWREGB(ui32Base + ui32IndexedReg); + ui32Value = HWREGB(ui32Base + ui32IndexedReg); } else { // // Get the value. // - ui8Value = HWREGH(ui32Base + ui32IndexedReg); + ui32Value = HWREGH(ui32Base + ui32IndexedReg); } // @@ -211,7 +212,7 @@ _USBIndexRead(uint32_t ui32Base, uint32_t ui32Endpoint, // // Return the register's value. // - return(ui8Value); + return(ui32Value); } //***************************************************************************** diff --git a/bsp/tm4c129x/libraries/driverlib/usb.h b/bsp/tm4c129x/libraries/driverlib/usb.h index 4ebad9d9a1..1fed815842 100644 --- a/bsp/tm4c129x/libraries/driverlib/usb.h +++ b/bsp/tm4c129x/libraries/driverlib/usb.h @@ -2,7 +2,7 @@ // // usb.h - Prototypes for the USB Interface Driver. // -// Copyright (c) 2007-2014 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2007-2017 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Redistribution and use in source and binary forms, with or without @@ -33,7 +33,7 @@ // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library. +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. // //***************************************************************************** diff --git a/bsp/tm4c129x/libraries/driverlib/watchdog.c b/bsp/tm4c129x/libraries/driverlib/watchdog.c index 62be8592df..e1761ff747 100644 --- a/bsp/tm4c129x/libraries/driverlib/watchdog.c +++ b/bsp/tm4c129x/libraries/driverlib/watchdog.c @@ -2,7 +2,7 @@ // // watchdog.c - Driver for the Watchdog Timer Module. // -// Copyright (c) 2005-2014 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Redistribution and use in source and binary forms, with or without @@ -33,7 +33,7 @@ // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library. +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. // //***************************************************************************** diff --git a/bsp/tm4c129x/libraries/driverlib/watchdog.h b/bsp/tm4c129x/libraries/driverlib/watchdog.h index b4dd66183c..a14a4fb04c 100644 --- a/bsp/tm4c129x/libraries/driverlib/watchdog.h +++ b/bsp/tm4c129x/libraries/driverlib/watchdog.h @@ -2,7 +2,7 @@ // // watchdog.h - Prototypes for the Watchdog Timer API // -// Copyright (c) 2005-2014 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Redistribution and use in source and binary forms, with or without @@ -33,7 +33,7 @@ // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library. +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. // //***************************************************************************** diff --git a/bsp/tm4c129x/libraries/inc/asmdefs.h b/bsp/tm4c129x/libraries/inc/asmdefs.h index dca0b2f0e0..b0e4cc217c 100644 --- a/bsp/tm4c129x/libraries/inc/asmdefs.h +++ b/bsp/tm4c129x/libraries/inc/asmdefs.h @@ -2,7 +2,7 @@ // // asmdefs.h - Macros to allow assembly code be portable among toolchains. // -// Copyright (c) 2005-2014 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Redistribution and use in source and binary forms, with or without @@ -33,7 +33,7 @@ // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 2.1.0.12573 of the Tiva Firmware Development Package. +// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. // //***************************************************************************** diff --git a/bsp/tm4c129x/libraries/inc/hw_adc.h b/bsp/tm4c129x/libraries/inc/hw_adc.h index 615bb7225a..41f8a33e4d 100644 --- a/bsp/tm4c129x/libraries/inc/hw_adc.h +++ b/bsp/tm4c129x/libraries/inc/hw_adc.h @@ -2,7 +2,7 @@ // // hw_adc.h - Macros used when accessing the ADC hardware. // -// Copyright (c) 2005-2014 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Redistribution and use in source and binary forms, with or without @@ -33,7 +33,7 @@ // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 2.1.0.12573 of the Tiva Firmware Development Package. +// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. // //***************************************************************************** @@ -412,7 +412,6 @@ // The following are defines for the bit fields in the ADC_O_CTL register. // //***************************************************************************** -#define ADC_CTL_DITHER 0x00000040 // Dither Mode Enable #define ADC_CTL_VREF_M 0x00000003 // Voltage Reference Select #define ADC_CTL_VREF_INTERNAL 0x00000000 // VDDA and GNDA are the voltage // references diff --git a/bsp/tm4c129x/libraries/inc/hw_aes.h b/bsp/tm4c129x/libraries/inc/hw_aes.h index 25e9bd95cc..79d56113d6 100644 --- a/bsp/tm4c129x/libraries/inc/hw_aes.h +++ b/bsp/tm4c129x/libraries/inc/hw_aes.h @@ -2,7 +2,7 @@ // // hw_aes.h - Macros used when accessing the AES hardware. // -// Copyright (c) 2012-2014 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2012-2017 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Redistribution and use in source and binary forms, with or without @@ -33,7 +33,7 @@ // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 2.1.0.12573 of the Tiva Firmware Development Package. +// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. // //***************************************************************************** diff --git a/bsp/tm4c129x/libraries/inc/hw_can.h b/bsp/tm4c129x/libraries/inc/hw_can.h index 604024a39d..398a83d6cb 100644 --- a/bsp/tm4c129x/libraries/inc/hw_can.h +++ b/bsp/tm4c129x/libraries/inc/hw_can.h @@ -2,7 +2,7 @@ // // hw_can.h - Defines and macros used when accessing the CAN controllers. // -// Copyright (c) 2006-2014 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2006-2017 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Redistribution and use in source and binary forms, with or without @@ -33,7 +33,7 @@ // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 2.1.0.12573 of the Tiva Firmware Development Package. +// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. // //***************************************************************************** diff --git a/bsp/tm4c129x/libraries/inc/hw_ccm.h b/bsp/tm4c129x/libraries/inc/hw_ccm.h index 1d134572ca..9664ceea75 100644 --- a/bsp/tm4c129x/libraries/inc/hw_ccm.h +++ b/bsp/tm4c129x/libraries/inc/hw_ccm.h @@ -2,7 +2,7 @@ // // hw_ccm.h - Macros used when accessing the CCM hardware. // -// Copyright (c) 2012-2014 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2012-2017 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Redistribution and use in source and binary forms, with or without @@ -33,7 +33,7 @@ // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 2.1.0.12573 of the Tiva Firmware Development Package. +// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. // //***************************************************************************** diff --git a/bsp/tm4c129x/libraries/inc/hw_comp.h b/bsp/tm4c129x/libraries/inc/hw_comp.h index 1d1a2a8731..24616aa954 100644 --- a/bsp/tm4c129x/libraries/inc/hw_comp.h +++ b/bsp/tm4c129x/libraries/inc/hw_comp.h @@ -2,7 +2,7 @@ // // hw_comp.h - Macros used when accessing the comparator hardware. // -// Copyright (c) 2005-2014 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Redistribution and use in source and binary forms, with or without @@ -33,7 +33,7 @@ // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 2.1.0.12573 of the Tiva Firmware Development Package. +// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. // //***************************************************************************** diff --git a/bsp/tm4c129x/libraries/inc/hw_des.h b/bsp/tm4c129x/libraries/inc/hw_des.h index f958d8f279..775c3a745c 100644 --- a/bsp/tm4c129x/libraries/inc/hw_des.h +++ b/bsp/tm4c129x/libraries/inc/hw_des.h @@ -2,7 +2,7 @@ // // hw_des.h - Macros used when accessing the DES hardware. // -// Copyright (c) 2012-2014 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2012-2017 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Redistribution and use in source and binary forms, with or without @@ -33,7 +33,7 @@ // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 2.1.0.12573 of the Tiva Firmware Development Package. +// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. // //***************************************************************************** diff --git a/bsp/tm4c129x/libraries/inc/hw_eeprom.h b/bsp/tm4c129x/libraries/inc/hw_eeprom.h index 4aeae0ba98..2118c958e6 100644 --- a/bsp/tm4c129x/libraries/inc/hw_eeprom.h +++ b/bsp/tm4c129x/libraries/inc/hw_eeprom.h @@ -2,7 +2,7 @@ // // hw_eeprom.h - Macros used when accessing the EEPROM controller. // -// Copyright (c) 2011-2014 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2011-2017 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Redistribution and use in source and binary forms, with or without @@ -33,7 +33,7 @@ // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 2.1.0.12573 of the Tiva Firmware Development Package. +// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. // //***************************************************************************** diff --git a/bsp/tm4c129x/libraries/inc/hw_emac.h b/bsp/tm4c129x/libraries/inc/hw_emac.h index ec5e7b309a..a836da9d21 100644 --- a/bsp/tm4c129x/libraries/inc/hw_emac.h +++ b/bsp/tm4c129x/libraries/inc/hw_emac.h @@ -2,7 +2,7 @@ // // hw_emac.h - Macros used when accessing the EMAC hardware. // -// Copyright (c) 2012-2014 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2012-2017 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Redistribution and use in source and binary forms, with or without @@ -33,7 +33,7 @@ // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 2.1.0.12573 of the Tiva Firmware Development Package. +// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. // //***************************************************************************** @@ -58,6 +58,10 @@ // Frame Filter #define EMAC_O_PMTCTLSTAT 0x0000002C // Ethernet MAC PMT Control and // Status Register +#define EMAC_O_LPICTLSTAT 0x00000030 // Ethernet MAC Low Power Idle + // Control and Status Register +#define EMAC_O_LPITIMERCTL 0x00000034 // Ethernet MAC Low Power Idle + // Timer Control Register #define EMAC_O_RIS 0x00000038 // Ethernet MAC Raw Interrupt // Status #define EMAC_O_IM 0x0000003C // Ethernet MAC Interrupt Mask @@ -295,19 +299,6 @@ //***************************************************************************** #define EMAC_FLOWCTL_PT_M 0xFFFF0000 // Pause Time #define EMAC_FLOWCTL_DZQP 0x00000080 // Disable Zero-Quanta Pause -#define EMAC_FLOWCTL_PLT_M 0x00000030 // Pause Low Threshold -#define EMAC_FLOWCTL_PLT_4 0x00000000 // The threshold is Pause time - // minus 4 slot times (PT - 4 slot - // times) -#define EMAC_FLOWCTL_PLT_28 0x00000010 // The threshold is Pause time - // minus 28 slot times (PT - 28 - // slot times) -#define EMAC_FLOWCTL_PLT_144 0x00000020 // The threshold is Pause time - // minus 144 slot times (PT - 144 - // slot times) -#define EMAC_FLOWCTL_PLT_156 0x00000030 // The threshold is Pause time - // minus 256 slot times (PT - 256 - // slot times) #define EMAC_FLOWCTL_UP 0x00000008 // Unicast Pause Frame Detect #define EMAC_FLOWCTL_RFE 0x00000004 // Receive Flow Control Enable #define EMAC_FLOWCTL_TFE 0x00000002 // Transmit Flow Control Enable @@ -418,11 +409,40 @@ #define EMAC_PMTCTLSTAT_RWKPTR_S \ 24 +//***************************************************************************** +// +// The following are defines for the bit fields in the EMAC_O_LPICTLSTAT +// register. +// +//***************************************************************************** +#define EMAC_LPICTLSTAT_LPITXA 0x00080000 // LPI TX Automate +#define EMAC_LPICTLSTAT_PLSEN 0x00040000 // PHY Link Status Enable +#define EMAC_LPICTLSTAT_PLS 0x00020000 // PHY Link Status +#define EMAC_LPICTLSTAT_LPIEN 0x00010000 // LPI Enable +#define EMAC_LPICTLSTAT_RLPIST 0x00000200 // Receive LPI State +#define EMAC_LPICTLSTAT_TLPIST 0x00000100 // Transmit LPI State +#define EMAC_LPICTLSTAT_RLPIEX 0x00000008 // Receive LPI Exit +#define EMAC_LPICTLSTAT_RLPIEN 0x00000004 // Receive LPI Entry +#define EMAC_LPICTLSTAT_TLPIEX 0x00000002 // Transmit LPI Exit +#define EMAC_LPICTLSTAT_TLPIEN 0x00000001 // Transmit LPI Entry + +//***************************************************************************** +// +// The following are defines for the bit fields in the EMAC_O_LPITIMERCTL +// register. +// +//***************************************************************************** +#define EMAC_LPITIMERCTL_LST_M 0x03FF0000 // Low Power Idle LS Timer +#define EMAC_LPITIMERCTL_LST_S 16 +#define EMAC_LPITIMERCTL_TWT_M 0x0000FFFF // Low Power Idle TW Timer +#define EMAC_LPITIMERCTL_TWT_S 0 + //***************************************************************************** // // The following are defines for the bit fields in the EMAC_O_RIS register. // //***************************************************************************** +#define EMAC_RIS_LPI 0x00000400 // LPI Interrupt Status #define EMAC_RIS_TS 0x00000200 // Timestamp Interrupt Status #define EMAC_RIS_MMCTX 0x00000040 // MMC Transmit Interrupt Status #define EMAC_RIS_MMCRX 0x00000020 // MMC Receive Interrupt Status @@ -434,6 +454,7 @@ // The following are defines for the bit fields in the EMAC_O_IM register. // //***************************************************************************** +#define EMAC_IM_LPI 0x00000400 // LPI Interrupt Mask #define EMAC_IM_TSI 0x00000200 // Timestamp Interrupt Mask #define EMAC_IM_PMT 0x00000008 // PMT Interrupt Mask @@ -875,77 +896,6 @@ #define EMAC_PPSCTRL_PPSCTRL_M 0x0000000F // EN0PPS Output Frequency Control // (PPSCTRL) or Command Control // (PPSCMD) -#define EMAC_PPSCTRL_PPSCTRL_1HZ \ - 0x00000000 // When the PPSEN0 bit = 0x0, the - // EN0PPS signal is 1 pulse of the - // PTP reference clock.(of width - // clk_ptp_i) every second -#define EMAC_PPSCTRL_PPSCTRL_2HZ \ - 0x00000001 // When the PPSEN0 bit = 0x0, the - // binary rollover is 2 Hz, and the - // digital rollover is 1 Hz -#define EMAC_PPSCTRL_PPSCTRL_4HZ \ - 0x00000002 // When the PPSEN0 bit = 0x0, the - // binary rollover is 4 Hz, and the - // digital rollover is 2 Hz -#define EMAC_PPSCTRL_PPSCTRL_8HZ \ - 0x00000003 // When thePPSEN0 bit = 0x0, the - // binary rollover is 8 Hz, and the - // digital rollover is 4 Hz, -#define EMAC_PPSCTRL_PPSCTRL_16HZ \ - 0x00000004 // When thePPSEN0 bit = 0x0, the - // binary rollover is 16 Hz, and - // the digital rollover is 8 Hz -#define EMAC_PPSCTRL_PPSCTRL_32HZ \ - 0x00000005 // When thePPSEN0 bit = 0x0, the - // binary rollover is 32 Hz, and - // the digital rollover is 16 Hz -#define EMAC_PPSCTRL_PPSCTRL_64HZ \ - 0x00000006 // When thePPSEN0 bit = 0x0, the - // binary rollover is 64 Hz, and - // the digital rollover is 32 Hz -#define EMAC_PPSCTRL_PPSCTRL_128HZ \ - 0x00000007 // When thePPSEN0 bit = 0x0, the - // binary rollover is 128 Hz, and - // the digital rollover is 64 Hz -#define EMAC_PPSCTRL_PPSCTRL_256HZ \ - 0x00000008 // When thePPSEN0 bit = 0x0, the - // binary rollover is 256 Hz, and - // the digital rollover is 128 Hz -#define EMAC_PPSCTRL_PPSCTRL_512HZ \ - 0x00000009 // When thePPSEN0 bit = 0x0, the - // binary rollover is 512 Hz, and - // the digital rollover is 256 Hz -#define EMAC_PPSCTRL_PPSCTRL_1024HZ \ - 0x0000000A // When the PPSEN0 bit = 0x0, the - // binary rollover is 1.024 kHz, - // and the digital rollover is 512 - // Hz -#define EMAC_PPSCTRL_PPSCTRL_2048HZ \ - 0x0000000B // When thePPSEN0 bit = 0x0, the - // binary rollover is 2.048 kHz, - // and the digital rollover is - // 1.024 kHz -#define EMAC_PPSCTRL_PPSCTRL_4096HZ \ - 0x0000000C // When thePPSEN0 bit = 0x0, the - // binary rollover is 4.096 kHz, - // and the digital rollover is - // 2.048 kHz -#define EMAC_PPSCTRL_PPSCTRL_8192HZ \ - 0x0000000D // When thePPSEN0 bit = 0x0, the - // binary rollover is 8.192 kHz, - // and the digital rollover is - // 4.096 kHz -#define EMAC_PPSCTRL_PPSCTRL_16384HZ \ - 0x0000000E // When thePPSEN0 bit = 0x0, the - // binary rollover is 16.384 kHz, - // and the digital rollover is - // 8.092 kHz -#define EMAC_PPSCTRL_PPSCTRL_32768HZ \ - 0x0000000F // When thePPSEN0 bit = 0x0, the - // binary rollover is 32.768 KHz, - // and the digital rollover is - // 16.384 KHz //***************************************************************************** // @@ -1039,6 +989,7 @@ // The following are defines for the bit fields in the EMAC_O_DMARIS register. // //***************************************************************************** +#define EMAC_DMARIS_LPI 0x40000000 // LPI Trigger Interrupt Status #define EMAC_DMARIS_TT 0x20000000 // Timestamp Trigger Interrupt // Status #define EMAC_DMARIS_PMT 0x10000000 // MAC PMT Interrupt Status @@ -1832,6 +1783,84 @@ //***************************************************************************** #ifndef DEPRECATED +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the +// EMAC_O_PPSCTRL register. +// +//***************************************************************************** +#define EMAC_PPSCTRL_PPSCTRL_1HZ \ + 0x00000000 // When the PPSEN0 bit = 0x0, the + // EN0PPS signal is 1 pulse of the + // PTP reference clock.(of width + // clk_ptp_i) every second +#define EMAC_PPSCTRL_PPSCTRL_2HZ \ + 0x00000001 // When the PPSEN0 bit = 0x0, the + // binary rollover is 2 Hz, and the + // digital rollover is 1 Hz +#define EMAC_PPSCTRL_PPSCTRL_4HZ \ + 0x00000002 // When the PPSEN0 bit = 0x0, the + // binary rollover is 4 Hz, and the + // digital rollover is 2 Hz +#define EMAC_PPSCTRL_PPSCTRL_8HZ \ + 0x00000003 // When thePPSEN0 bit = 0x0, the + // binary rollover is 8 Hz, and the + // digital rollover is 4 Hz, +#define EMAC_PPSCTRL_PPSCTRL_16HZ \ + 0x00000004 // When thePPSEN0 bit = 0x0, the + // binary rollover is 16 Hz, and + // the digital rollover is 8 Hz +#define EMAC_PPSCTRL_PPSCTRL_32HZ \ + 0x00000005 // When thePPSEN0 bit = 0x0, the + // binary rollover is 32 Hz, and + // the digital rollover is 16 Hz +#define EMAC_PPSCTRL_PPSCTRL_64HZ \ + 0x00000006 // When thePPSEN0 bit = 0x0, the + // binary rollover is 64 Hz, and + // the digital rollover is 32 Hz +#define EMAC_PPSCTRL_PPSCTRL_128HZ \ + 0x00000007 // When thePPSEN0 bit = 0x0, the + // binary rollover is 128 Hz, and + // the digital rollover is 64 Hz +#define EMAC_PPSCTRL_PPSCTRL_256HZ \ + 0x00000008 // When thePPSEN0 bit = 0x0, the + // binary rollover is 256 Hz, and + // the digital rollover is 128 Hz +#define EMAC_PPSCTRL_PPSCTRL_512HZ \ + 0x00000009 // When thePPSEN0 bit = 0x0, the + // binary rollover is 512 Hz, and + // the digital rollover is 256 Hz +#define EMAC_PPSCTRL_PPSCTRL_1024HZ \ + 0x0000000A // When the PPSEN0 bit = 0x0, the + // binary rollover is 1.024 kHz, + // and the digital rollover is 512 + // Hz +#define EMAC_PPSCTRL_PPSCTRL_2048HZ \ + 0x0000000B // When thePPSEN0 bit = 0x0, the + // binary rollover is 2.048 kHz, + // and the digital rollover is + // 1.024 kHz +#define EMAC_PPSCTRL_PPSCTRL_4096HZ \ + 0x0000000C // When thePPSEN0 bit = 0x0, the + // binary rollover is 4.096 kHz, + // and the digital rollover is + // 2.048 kHz +#define EMAC_PPSCTRL_PPSCTRL_8192HZ \ + 0x0000000D // When thePPSEN0 bit = 0x0, the + // binary rollover is 8.192 kHz, + // and the digital rollover is + // 4.096 kHz +#define EMAC_PPSCTRL_PPSCTRL_16384HZ \ + 0x0000000E // When thePPSEN0 bit = 0x0, the + // binary rollover is 16.384 kHz, + // and the digital rollover is + // 8.092 kHz +#define EMAC_PPSCTRL_PPSCTRL_32768HZ \ + 0x0000000F // When thePPSEN0 bit = 0x0, the + // binary rollover is 32.768 KHz, + // and the digital rollover is + // 16.384 KHz + //***************************************************************************** // // The following are deprecated defines for the bit fields in the EMAC_O_CC diff --git a/bsp/tm4c129x/libraries/inc/hw_epi.h b/bsp/tm4c129x/libraries/inc/hw_epi.h index 7a90282e38..ea9f065562 100644 --- a/bsp/tm4c129x/libraries/inc/hw_epi.h +++ b/bsp/tm4c129x/libraries/inc/hw_epi.h @@ -2,7 +2,7 @@ // // hw_epi.h - Macros for use in accessing the EPI registers. // -// Copyright (c) 2008-2014 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2008-2017 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Redistribution and use in source and binary forms, with or without @@ -33,7 +33,7 @@ // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 2.1.0.12573 of the Tiva Firmware Development Package. +// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. // //***************************************************************************** diff --git a/bsp/tm4c129x/libraries/inc/hw_fan.h b/bsp/tm4c129x/libraries/inc/hw_fan.h index 1332996170..9c191cf0af 100644 --- a/bsp/tm4c129x/libraries/inc/hw_fan.h +++ b/bsp/tm4c129x/libraries/inc/hw_fan.h @@ -2,7 +2,7 @@ // // hw_fan.h - Macros used when accessing the fan control hardware. // -// Copyright (c) 2010-2014 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2010-2017 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Redistribution and use in source and binary forms, with or without @@ -33,7 +33,7 @@ // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 2.1.0.12573 of the Tiva Firmware Development Package. +// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. // //***************************************************************************** diff --git a/bsp/tm4c129x/libraries/inc/hw_flash.h b/bsp/tm4c129x/libraries/inc/hw_flash.h index 971d4e0c27..e38e85b59d 100644 --- a/bsp/tm4c129x/libraries/inc/hw_flash.h +++ b/bsp/tm4c129x/libraries/inc/hw_flash.h @@ -2,7 +2,7 @@ // // hw_flash.h - Macros used when accessing the flash controller. // -// Copyright (c) 2005-2014 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Redistribution and use in source and binary forms, with or without @@ -33,7 +33,7 @@ // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 2.1.0.12573 of the Tiva Firmware Development Package. +// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. // //***************************************************************************** diff --git a/bsp/tm4c129x/libraries/inc/hw_gpio.h b/bsp/tm4c129x/libraries/inc/hw_gpio.h index 471ddd90c9..9e95aed435 100644 --- a/bsp/tm4c129x/libraries/inc/hw_gpio.h +++ b/bsp/tm4c129x/libraries/inc/hw_gpio.h @@ -2,7 +2,7 @@ // // hw_gpio.h - Defines and Macros for GPIO hardware. // -// Copyright (c) 2005-2014 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Redistribution and use in source and binary forms, with or without @@ -33,7 +33,7 @@ // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 2.1.0.12573 of the Tiva Firmware Development Package. +// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. // //***************************************************************************** diff --git a/bsp/tm4c129x/libraries/inc/hw_hibernate.h b/bsp/tm4c129x/libraries/inc/hw_hibernate.h index e5d36d887b..ce469a20e1 100644 --- a/bsp/tm4c129x/libraries/inc/hw_hibernate.h +++ b/bsp/tm4c129x/libraries/inc/hw_hibernate.h @@ -2,7 +2,7 @@ // // hw_hibernate.h - Defines and Macros for the Hibernation module. // -// Copyright (c) 2007-2014 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2007-2017 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Redistribution and use in source and binary forms, with or without @@ -33,7 +33,7 @@ // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 2.1.0.12573 of the Tiva Firmware Development Package. +// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. // //***************************************************************************** diff --git a/bsp/tm4c129x/libraries/inc/hw_i2c.h b/bsp/tm4c129x/libraries/inc/hw_i2c.h index 8544faaf46..d9d00b5d57 100644 --- a/bsp/tm4c129x/libraries/inc/hw_i2c.h +++ b/bsp/tm4c129x/libraries/inc/hw_i2c.h @@ -2,7 +2,7 @@ // // hw_i2c.h - Macros used when accessing the I2C master and slave hardware. // -// Copyright (c) 2005-2014 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Redistribution and use in source and binary forms, with or without @@ -33,7 +33,7 @@ // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 2.1.0.12573 of the Tiva Firmware Development Package. +// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. // //***************************************************************************** diff --git a/bsp/tm4c129x/libraries/inc/hw_ints.h b/bsp/tm4c129x/libraries/inc/hw_ints.h index df1a716690..c75a84a6bb 100644 --- a/bsp/tm4c129x/libraries/inc/hw_ints.h +++ b/bsp/tm4c129x/libraries/inc/hw_ints.h @@ -3,7 +3,7 @@ // hw_ints.h - Macros that define the interrupt assignment on Tiva C Series // MCUs. // -// Copyright (c) 2005-2014 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Redistribution and use in source and binary forms, with or without @@ -34,7 +34,7 @@ // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 2.1.0.12573 of the Tiva Firmware Development Package. +// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. // //***************************************************************************** @@ -313,7 +313,7 @@ defined(PART_TM4C1231H6PGE) || defined(PART_TM4C1233H6PGE) || \ defined(PART_TM4C1237H6PGE) || defined(PART_TM4C123BH6PGE) || \ defined(PART_TM4C123BH6ZRB) || defined(PART_TM4C123GH6PGE) || \ - defined(PART_TM4C123GH6ZRB) + defined(PART_TM4C123GH6ZRB) || defined(PART_TM4C123GH6ZXR) #define INT_RESOLVE(intname, class) intname##TM4C123 //***************************************************************************** diff --git a/bsp/tm4c129x/libraries/inc/hw_lcd.h b/bsp/tm4c129x/libraries/inc/hw_lcd.h index e2f80e08a0..bf0be0ae2f 100644 --- a/bsp/tm4c129x/libraries/inc/hw_lcd.h +++ b/bsp/tm4c129x/libraries/inc/hw_lcd.h @@ -2,7 +2,7 @@ // // hw_lcd.h - Defines and macros used when accessing the LCD controller. // -// Copyright (c) 2011-2014 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2011-2017 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Redistribution and use in source and binary forms, with or without @@ -33,7 +33,7 @@ // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 2.1.0.12573 of the Tiva Firmware Development Package. +// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. // //***************************************************************************** diff --git a/bsp/tm4c129x/libraries/inc/hw_memmap.h b/bsp/tm4c129x/libraries/inc/hw_memmap.h index b604c6cea3..87033ab823 100644 --- a/bsp/tm4c129x/libraries/inc/hw_memmap.h +++ b/bsp/tm4c129x/libraries/inc/hw_memmap.h @@ -2,7 +2,7 @@ // // hw_memmap.h - Macros defining the memory map of the device. // -// Copyright (c) 2005-2014 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Redistribution and use in source and binary forms, with or without @@ -33,7 +33,7 @@ // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 2.1.0.12573 of the Tiva Firmware Development Package. +// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. // //***************************************************************************** diff --git a/bsp/tm4c129x/libraries/inc/hw_nvic.h b/bsp/tm4c129x/libraries/inc/hw_nvic.h index 7811347721..be8becf0fb 100644 --- a/bsp/tm4c129x/libraries/inc/hw_nvic.h +++ b/bsp/tm4c129x/libraries/inc/hw_nvic.h @@ -2,7 +2,7 @@ // // hw_nvic.h - Macros used when accessing the NVIC hardware. // -// Copyright (c) 2005-2014 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Redistribution and use in source and binary forms, with or without @@ -33,7 +33,7 @@ // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 2.1.0.12573 of the Tiva Firmware Development Package. +// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. // //***************************************************************************** diff --git a/bsp/tm4c129x/libraries/inc/hw_onewire.h b/bsp/tm4c129x/libraries/inc/hw_onewire.h new file mode 100644 index 0000000000..bf810b7ce9 --- /dev/null +++ b/bsp/tm4c129x/libraries/inc/hw_onewire.h @@ -0,0 +1,223 @@ +//***************************************************************************** +// +// hw_onewire.h - Macros used when accessing the One wire hardware. +// +// Copyright (c) 2012-2017 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. +// +//***************************************************************************** + +#ifndef __HW_ONEWIRE_H__ +#define __HW_ONEWIRE_H__ + +//***************************************************************************** +// +// The following are defines for the One wire register offsets. +// +//***************************************************************************** +#define ONEWIRE_O_CS 0x00000000 // 1-Wire Control and Status +#define ONEWIRE_O_TIM 0x00000004 // 1-Wire Timing Override +#define ONEWIRE_O_DATW 0x00000008 // 1-Wire Data Write +#define ONEWIRE_O_DATR 0x0000000C // 1-Wire Data Read +#define ONEWIRE_O_IM 0x00000100 // 1-Wire Interrupt Mask +#define ONEWIRE_O_RIS 0x00000104 // 1-Wire Raw Interrupt Status +#define ONEWIRE_O_MIS 0x00000108 // 1-Wire Masked Interrupt Status +#define ONEWIRE_O_ICR 0x0000010C // 1-Wire Interrupt Clear +#define ONEWIRE_O_DMA 0x00000120 // 1-Wire uDMA Control +#define ONEWIRE_O_PP 0x00000FC0 // 1-Wire Peripheral Properties + +//***************************************************************************** +// +// The following are defines for the bit fields in the ONEWIRE_O_CS register. +// +//***************************************************************************** +#define ONEWIRE_CS_USEALT 0x80000000 // Two Wire Enable +#define ONEWIRE_CS_ALTP 0x40000000 // Alternate Polarity Enable +#define ONEWIRE_CS_BSIZE_M 0x00070000 // Last Byte Size +#define ONEWIRE_CS_BSIZE_8 0x00000000 // 8 bits (1 byte) +#define ONEWIRE_CS_BSIZE_1 0x00010000 // 1 bit +#define ONEWIRE_CS_BSIZE_2 0x00020000 // 2 bits +#define ONEWIRE_CS_BSIZE_3 0x00030000 // 3 bits +#define ONEWIRE_CS_BSIZE_4 0x00040000 // 4 bits +#define ONEWIRE_CS_BSIZE_5 0x00050000 // 5 bits +#define ONEWIRE_CS_BSIZE_6 0x00060000 // 6 bits +#define ONEWIRE_CS_BSIZE_7 0x00070000 // 7 bits +#define ONEWIRE_CS_STUCK 0x00000400 // STUCK Status +#define ONEWIRE_CS_NOATR 0x00000200 // Answer-to-Reset Status +#define ONEWIRE_CS_BUSY 0x00000100 // Busy Status +#define ONEWIRE_CS_SKATR 0x00000080 // Skip Answer-to-Reset Enable +#define ONEWIRE_CS_LSAM 0x00000040 // Late Sample Enable +#define ONEWIRE_CS_ODRV 0x00000020 // Overdrive Enable +#define ONEWIRE_CS_SZ_M 0x00000018 // Data Operation Size +#define ONEWIRE_CS_OP_M 0x00000006 // Operation Request +#define ONEWIRE_CS_OP_NONE 0x00000000 // No operation +#define ONEWIRE_CS_OP_RD 0x00000002 // Read +#define ONEWIRE_CS_OP_WR 0x00000004 // Write +#define ONEWIRE_CS_OP_WRRD 0x00000006 // Write/Read +#define ONEWIRE_CS_RST 0x00000001 // Reset Request +#define ONEWIRE_CS_SZ_S 3 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ONEWIRE_O_TIM register. +// +//***************************************************************************** +#define ONEWIRE_TIM_W1TIM_M 0xF0000000 // Value '1' Timing +#define ONEWIRE_TIM_W0TIM_M 0x0F800000 // Value '0' Timing +#define ONEWIRE_TIM_W0REST_M 0x00780000 // Rest Time +#define ONEWIRE_TIM_W1SAM_M 0x00078000 // Sample Time +#define ONEWIRE_TIM_ATRSAM_M 0x00007800 // Answer-to-Reset Sample +#define ONEWIRE_TIM_ATRTIM_M 0x000007C0 // Answer-to-Reset/Rest Period +#define ONEWIRE_TIM_RSTTIM_M 0x0000003F // Reset Low Time +#define ONEWIRE_TIM_W1TIM_S 28 +#define ONEWIRE_TIM_W0TIM_S 23 +#define ONEWIRE_TIM_W0REST_S 19 +#define ONEWIRE_TIM_W1SAM_S 15 +#define ONEWIRE_TIM_ATRSAM_S 11 +#define ONEWIRE_TIM_ATRTIM_S 6 +#define ONEWIRE_TIM_RSTTIM_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ONEWIRE_O_DATW register. +// +//***************************************************************************** +#define ONEWIRE_DATW_B3_M 0xFF000000 // Upper Data Byte +#define ONEWIRE_DATW_B2_M 0x00FF0000 // Upper Middle Data Byte +#define ONEWIRE_DATW_B1_M 0x0000FF00 // Lower Middle Data Byte +#define ONEWIRE_DATW_B0_M 0x000000FF // Lowest Data Byte +#define ONEWIRE_DATW_B3_S 24 +#define ONEWIRE_DATW_B2_S 16 +#define ONEWIRE_DATW_B1_S 8 +#define ONEWIRE_DATW_B0_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ONEWIRE_O_DATR register. +// +//***************************************************************************** +#define ONEWIRE_DATR_B3_M 0xFF000000 // Upper Data Byte +#define ONEWIRE_DATR_B2_M 0x00FF0000 // Upper Middle Data Byte +#define ONEWIRE_DATR_B1_M 0x0000FF00 // Lower Middle Data Byte +#define ONEWIRE_DATR_B0_M 0x000000FF // Lowest Data Byte +#define ONEWIRE_DATR_B3_S 24 +#define ONEWIRE_DATR_B2_S 16 +#define ONEWIRE_DATR_B1_S 8 +#define ONEWIRE_DATR_B0_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ONEWIRE_O_IM register. +// +//***************************************************************************** +#define ONEWIRE_IM_DMA 0x00000010 // DMA Done Interrupt Mask +#define ONEWIRE_IM_STUCK 0x00000008 // Stuck Status Interrupt Mask +#define ONEWIRE_IM_NOATR 0x00000004 // No Answer-to-Reset Interrupt + // Mask +#define ONEWIRE_IM_OPC 0x00000002 // Operation Complete Interrupt + // Mask +#define ONEWIRE_IM_RST 0x00000001 // Reset Interrupt Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the ONEWIRE_O_RIS register. +// +//***************************************************************************** +#define ONEWIRE_RIS_DMA 0x00000010 // DMA Done Raw Interrupt Status +#define ONEWIRE_RIS_STUCK 0x00000008 // Stuck Status Raw Interrupt + // Status +#define ONEWIRE_RIS_NOATR 0x00000004 // No Answer-to-Reset Raw Interrupt + // Status +#define ONEWIRE_RIS_OPC 0x00000002 // Operation Complete Raw Interrupt + // Status +#define ONEWIRE_RIS_RST 0x00000001 // Reset Raw Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the ONEWIRE_O_MIS register. +// +//***************************************************************************** +#define ONEWIRE_MIS_DMA 0x00000010 // DMA Done Masked Interrupt Status +#define ONEWIRE_MIS_STUCK 0x00000008 // Stuck Status Masked Interrupt + // Status +#define ONEWIRE_MIS_NOATR 0x00000004 // No Answer-to-Reset Masked + // Interrupt Status +#define ONEWIRE_MIS_OPC 0x00000002 // Operation Complete Masked + // Interrupt Status +#define ONEWIRE_MIS_RST 0x00000001 // Reset Interrupt Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the ONEWIRE_O_ICR register. +// +//***************************************************************************** +#define ONEWIRE_ICR_DMA 0x00000010 // DMA Done Interrupt Clear +#define ONEWIRE_ICR_STUCK 0x00000008 // Stuck Status Interrupt Clear +#define ONEWIRE_ICR_NOATR 0x00000004 // No Answer-to-Reset Interrupt + // Clear +#define ONEWIRE_ICR_OPC 0x00000002 // Operation Complete Interrupt + // Clear +#define ONEWIRE_ICR_RST 0x00000001 // Reset Interrupt Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the ONEWIRE_O_DMA register. +// +//***************************************************************************** +#define ONEWIRE_DMA_SG 0x00000008 // Scatter-Gather Enable +#define ONEWIRE_DMA_DMAOP_M 0x00000006 // uDMA Operation +#define ONEWIRE_DMA_DMAOP_DIS 0x00000000 // uDMA disabled +#define ONEWIRE_DMA_DMAOP_RDSNG 0x00000002 // uDMA single read: 1-Wire + // requests uDMA to read + // ONEWIREDATR register after each + // read transaction +#define ONEWIRE_DMA_DMAOP_WRMUL 0x00000004 // uDMA multiple write: 1-Wire + // requests uDMA to load whenever + // the ONEWIREDATW register is + // empty +#define ONEWIRE_DMA_DMAOP_RDMUL 0x00000006 // uDMA multiple read: An initial + // read occurs and subsequent reads + // start after uDMA has read the + // ONEWIREDATR register +#define ONEWIRE_DMA_RST 0x00000001 // uDMA Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the ONEWIRE_O_PP register. +// +//***************************************************************************** +#define ONEWIRE_PP_DMAP 0x00000010 // uDMA Present +#define ONEWIRE_PP_CNT_M 0x00000003 // 1-Wire Bus Count +#define ONEWIRE_PP_CNT_S 0 + +#endif // __HW_ONEWIRE_H__ diff --git a/bsp/tm4c129x/libraries/inc/hw_pwm.h b/bsp/tm4c129x/libraries/inc/hw_pwm.h index 0ad6bf6284..2167aad93a 100644 --- a/bsp/tm4c129x/libraries/inc/hw_pwm.h +++ b/bsp/tm4c129x/libraries/inc/hw_pwm.h @@ -2,7 +2,7 @@ // // hw_pwm.h - Defines and Macros for Pulse Width Modulation (PWM) ports. // -// Copyright (c) 2005-2014 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Redistribution and use in source and binary forms, with or without @@ -33,7 +33,7 @@ // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 2.1.0.12573 of the Tiva Firmware Development Package. +// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. // //***************************************************************************** diff --git a/bsp/tm4c129x/libraries/inc/hw_qei.h b/bsp/tm4c129x/libraries/inc/hw_qei.h index 693596805d..a86f5259bd 100644 --- a/bsp/tm4c129x/libraries/inc/hw_qei.h +++ b/bsp/tm4c129x/libraries/inc/hw_qei.h @@ -2,7 +2,7 @@ // // hw_qei.h - Macros used when accessing the QEI hardware. // -// Copyright (c) 2005-2014 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Redistribution and use in source and binary forms, with or without @@ -33,7 +33,7 @@ // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 2.1.0.12573 of the Tiva Firmware Development Package. +// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. // //***************************************************************************** diff --git a/bsp/tm4c129x/libraries/inc/hw_shamd5.h b/bsp/tm4c129x/libraries/inc/hw_shamd5.h index bdb31cd87c..d34c76092c 100644 --- a/bsp/tm4c129x/libraries/inc/hw_shamd5.h +++ b/bsp/tm4c129x/libraries/inc/hw_shamd5.h @@ -2,7 +2,7 @@ // // hw_shamd5.h - Macros used when accessing the SHA/MD5 hardware. // -// Copyright (c) 2012-2014 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2012-2017 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Redistribution and use in source and binary forms, with or without @@ -33,7 +33,7 @@ // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 2.1.0.12573 of the Tiva Firmware Development Package. +// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. // //***************************************************************************** diff --git a/bsp/tm4c129x/libraries/inc/hw_ssi.h b/bsp/tm4c129x/libraries/inc/hw_ssi.h index c58c795fc3..36a92cf1e4 100644 --- a/bsp/tm4c129x/libraries/inc/hw_ssi.h +++ b/bsp/tm4c129x/libraries/inc/hw_ssi.h @@ -2,7 +2,7 @@ // // hw_ssi.h - Macros used when accessing the SSI hardware. // -// Copyright (c) 2005-2014 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Redistribution and use in source and binary forms, with or without @@ -33,7 +33,7 @@ // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 2.1.0.12573 of the Tiva Firmware Development Package. +// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. // //***************************************************************************** @@ -102,7 +102,6 @@ #define SSI_CR1_MODE_ADVANCED 0x000000C0 // Advanced SSI Mode with 8-bit // packet size #define SSI_CR1_EOT 0x00000010 // End of Transmission -#define SSI_CR1_SOD 0x00000008 // SSI Slave Mode Output Disable #define SSI_CR1_MS 0x00000004 // SSI Master/Slave Select #define SSI_CR1_SSE 0x00000002 // SSI Synchronous Serial Port // Enable diff --git a/bsp/tm4c129x/libraries/inc/hw_sysctl.h b/bsp/tm4c129x/libraries/inc/hw_sysctl.h index 47d81911ab..cab5049da5 100644 --- a/bsp/tm4c129x/libraries/inc/hw_sysctl.h +++ b/bsp/tm4c129x/libraries/inc/hw_sysctl.h @@ -2,7 +2,7 @@ // // hw_sysctl.h - Macros used when accessing the system control hardware. // -// Copyright (c) 2005-2014 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Redistribution and use in source and binary forms, with or without @@ -33,7 +33,7 @@ // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 2.1.0.12573 of the Tiva Firmware Development Package. +// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. // //***************************************************************************** @@ -425,6 +425,10 @@ #define SYSCTL_PRLCD 0x400FEA90 // LCD Controller Peripheral Ready #define SYSCTL_PROWIRE 0x400FEA98 // 1-Wire Peripheral Ready #define SYSCTL_PREMAC 0x400FEA9C // Ethernet MAC Peripheral Ready +#define SYSCTL_UNIQUEID0 0x400FEF20 // Unique ID 0 +#define SYSCTL_UNIQUEID1 0x400FEF24 // Unique ID 1 +#define SYSCTL_UNIQUEID2 0x400FEF28 // Unique ID 2 +#define SYSCTL_UNIQUEID3 0x400FEF2C // Unique ID 3 #define SYSCTL_CCMCGREQ 0x44030204 // Cryptographic Modules Clock // Gating Request @@ -666,10 +670,8 @@ #define SYSCTL_DC1_ADC1 0x00020000 // ADC Module 1 Present #define SYSCTL_DC1_ADC0 0x00010000 // ADC Module 0 Present #define SYSCTL_DC1_MINSYSDIV_M 0x0000F000 // System Clock Divider -#define SYSCTL_DC1_MINSYSDIV_80 0x00001000 // Specifies an 80-MHz CPU clock +#define SYSCTL_DC1_MINSYSDIV_80 0x00002000 // Specifies an 80-MHz CPU clock // with a PLL divider of 2.5 -#define SYSCTL_DC1_MINSYSDIV_66 0x00002000 // Specifies a 66-MHz CPU clock - // with a PLL divider of 3 #define SYSCTL_DC1_MINSYSDIV_50 0x00003000 // Specifies a 50-MHz CPU clock // with a PLL divider of 4 #define SYSCTL_DC1_MINSYSDIV_40 0x00004000 // Specifies a 40-MHz CPU clock @@ -1040,7 +1042,6 @@ //***************************************************************************** #define SYSCTL_RESC_MOSCFAIL 0x00010000 // MOSC Failure Reset #define SYSCTL_RESC_HSSR 0x00001000 // HSSR Reset -#define SYSCTL_RESC_HIB 0x00000040 // HIB Reset #define SYSCTL_RESC_WDT1 0x00000020 // Watchdog Timer 1 Reset #define SYSCTL_RESC_SW 0x00000010 // Software Reset #define SYSCTL_RESC_WDT0 0x00000008 // Watchdog Timer 0 Reset @@ -3660,6 +3661,42 @@ #define SYSCTL_PREMAC_R0 0x00000001 // Ethernet MAC Module 0 Peripheral // Ready +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_UNIQUEID0 +// register. +// +//***************************************************************************** +#define SYSCTL_UNIQUEID0_ID_M 0xFFFFFFFF // Unique ID +#define SYSCTL_UNIQUEID0_ID_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_UNIQUEID1 +// register. +// +//***************************************************************************** +#define SYSCTL_UNIQUEID1_ID_M 0xFFFFFFFF // Unique ID +#define SYSCTL_UNIQUEID1_ID_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_UNIQUEID2 +// register. +// +//***************************************************************************** +#define SYSCTL_UNIQUEID2_ID_M 0xFFFFFFFF // Unique ID +#define SYSCTL_UNIQUEID2_ID_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_UNIQUEID3 +// register. +// +//***************************************************************************** +#define SYSCTL_UNIQUEID3_ID_M 0xFFFFFFFF // Unique ID +#define SYSCTL_UNIQUEID3_ID_S 0 + //***************************************************************************** // // The following are defines for the bit fields in the SYSCTL_CCMCGREQ @@ -3690,6 +3727,14 @@ 0x000A0000 // Tiva(TM) C Series TM4C129-class // microcontrollers +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the SYSCTL_RESC +// register. +// +//***************************************************************************** +#define SYSCTL_RESC_HIB 0x00000040 // HIB Reset + //***************************************************************************** // // The following are deprecated defines for the bit fields in the SYSCTL_PWRTC diff --git a/bsp/tm4c129x/libraries/inc/hw_sysexc.h b/bsp/tm4c129x/libraries/inc/hw_sysexc.h index 99ac066877..314d17a8a1 100644 --- a/bsp/tm4c129x/libraries/inc/hw_sysexc.h +++ b/bsp/tm4c129x/libraries/inc/hw_sysexc.h @@ -2,7 +2,7 @@ // // hw_sysexc.h - Macros used when accessing the system exception module. // -// Copyright (c) 2011-2014 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2011-2017 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Redistribution and use in source and binary forms, with or without @@ -33,7 +33,7 @@ // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 2.1.0.12573 of the Tiva Firmware Development Package. +// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. // //***************************************************************************** diff --git a/bsp/tm4c129x/libraries/inc/hw_timer.h b/bsp/tm4c129x/libraries/inc/hw_timer.h index af1750d812..47a857567a 100644 --- a/bsp/tm4c129x/libraries/inc/hw_timer.h +++ b/bsp/tm4c129x/libraries/inc/hw_timer.h @@ -2,7 +2,7 @@ // // hw_timer.h - Defines and macros used when accessing the timer. // -// Copyright (c) 2005-2014 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Redistribution and use in source and binary forms, with or without @@ -33,7 +33,7 @@ // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 2.1.0.12573 of the Tiva Firmware Development Package. +// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. // //***************************************************************************** diff --git a/bsp/tm4c129x/libraries/inc/hw_types.h b/bsp/tm4c129x/libraries/inc/hw_types.h index 1f358757bb..ec493b5061 100644 --- a/bsp/tm4c129x/libraries/inc/hw_types.h +++ b/bsp/tm4c129x/libraries/inc/hw_types.h @@ -2,7 +2,7 @@ // // hw_types.h - Common types and macros. // -// Copyright (c) 2005-2014 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Redistribution and use in source and binary forms, with or without @@ -33,7 +33,7 @@ // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 2.1.0.12573 of the Tiva Firmware Development Package. +// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. // //***************************************************************************** diff --git a/bsp/tm4c129x/libraries/inc/hw_uart.h b/bsp/tm4c129x/libraries/inc/hw_uart.h index 8480ae4f5b..1c40b79f3d 100644 --- a/bsp/tm4c129x/libraries/inc/hw_uart.h +++ b/bsp/tm4c129x/libraries/inc/hw_uart.h @@ -2,7 +2,7 @@ // // hw_uart.h - Macros and defines used when accessing the UART hardware. // -// Copyright (c) 2005-2014 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Redistribution and use in source and binary forms, with or without @@ -33,7 +33,7 @@ // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 2.1.0.12573 of the Tiva Firmware Development Package. +// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. // //***************************************************************************** diff --git a/bsp/tm4c129x/libraries/inc/hw_udma.h b/bsp/tm4c129x/libraries/inc/hw_udma.h index ea6cbbce4c..1d52b00901 100644 --- a/bsp/tm4c129x/libraries/inc/hw_udma.h +++ b/bsp/tm4c129x/libraries/inc/hw_udma.h @@ -2,7 +2,7 @@ // // hw_udma.h - Macros for use in accessing the UDMA registers. // -// Copyright (c) 2007-2014 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2007-2017 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Redistribution and use in source and binary forms, with or without @@ -33,7 +33,7 @@ // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 2.1.0.12573 of the Tiva Firmware Development Package. +// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. // //***************************************************************************** diff --git a/bsp/tm4c129x/libraries/inc/hw_usb.h b/bsp/tm4c129x/libraries/inc/hw_usb.h index 059ca12514..7aa3b50a29 100644 --- a/bsp/tm4c129x/libraries/inc/hw_usb.h +++ b/bsp/tm4c129x/libraries/inc/hw_usb.h @@ -2,7 +2,7 @@ // // hw_usb.h - Macros for use in accessing the USB registers. // -// Copyright (c) 2007-2014 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2007-2017 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Redistribution and use in source and binary forms, with or without @@ -33,7 +33,7 @@ // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 2.1.0.12573 of the Tiva Firmware Development Package. +// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. // //***************************************************************************** diff --git a/bsp/tm4c129x/libraries/inc/hw_watchdog.h b/bsp/tm4c129x/libraries/inc/hw_watchdog.h index d1e9b4d267..783b6f07f6 100644 --- a/bsp/tm4c129x/libraries/inc/hw_watchdog.h +++ b/bsp/tm4c129x/libraries/inc/hw_watchdog.h @@ -2,7 +2,7 @@ // // hw_watchdog.h - Macros used when accessing the Watchdog Timer hardware. // -// Copyright (c) 2005-2014 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Redistribution and use in source and binary forms, with or without @@ -33,7 +33,7 @@ // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 2.1.0.12573 of the Tiva Firmware Development Package. +// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. // //***************************************************************************** diff --git a/bsp/tm4c129x/libraries/inc/tm4c1294ncpdt.h b/bsp/tm4c129x/libraries/inc/tm4c1294ncpdt.h index bebf6fdc2c..458eaac395 100644 --- a/bsp/tm4c129x/libraries/inc/tm4c1294ncpdt.h +++ b/bsp/tm4c129x/libraries/inc/tm4c1294ncpdt.h @@ -2,7 +2,7 @@ // // tm4c1294ncpdt.h - TM4C1294NCPDT Register Definitions // -// Copyright (c) 2013-2014 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2013-2017 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Redistribution and use in source and binary forms, with or without @@ -33,7 +33,7 @@ // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // -// This is part of revision 2.1.0.12573 of the Tiva Firmware Development Package. +// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. // //***************************************************************************** @@ -6075,7 +6075,6 @@ // The following are defines for the bit fields in the ADC_O_CTL register. // //***************************************************************************** -#define ADC_CTL_DITHER 0x00000040 // Dither Mode Enable #define ADC_CTL_VREF_M 0x00000001 // Voltage Reference Select #define ADC_CTL_VREF_INTERNAL 0x00000000 // VDDA and GNDA are the voltage // references @@ -12084,7 +12083,6 @@ //***************************************************************************** #define SYSCTL_RESC_MOSCFAIL 0x00010000 // MOSC Failure Reset #define SYSCTL_RESC_HSSR 0x00001000 // HSSR Reset -#define SYSCTL_RESC_HIB 0x00000040 // HIB Reset #define SYSCTL_RESC_WDT1 0x00000020 // Watchdog Timer 1 Reset #define SYSCTL_RESC_SW 0x00000010 // Software Reset #define SYSCTL_RESC_WDT0 0x00000008 // Watchdog Timer 0 Reset diff --git a/bsp/tm4c129x/libraries/startup/startup_ewarm.c b/bsp/tm4c129x/libraries/startup/startup_ewarm.c index cbcbda31e5..a5dbd78756 100644 --- a/bsp/tm4c129x/libraries/startup/startup_ewarm.c +++ b/bsp/tm4c129x/libraries/startup/startup_ewarm.c @@ -3,7 +3,7 @@ // startup_ewarm.c - Startup code for use with IAR's Embedded Workbench, // version 5. // -// Copyright (c) 2013-2014 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2013-2017 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Texas Instruments (TI) is supplying this software for use solely and @@ -19,7 +19,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 2.1.0.12573 of the DK-TM4C129X Firmware Package. +// This is part of revision 2.1.4.178 of the DK-TM4C129X Firmware Package. // //***************************************************************************** @@ -59,7 +59,7 @@ extern void HardFault_Handler(void); // Reserve space for the system stack. // //***************************************************************************** -static uint32_t pui32Stack[64] @ ".noinit"; +static uint32_t pui32Stack[128] @ ".noinit"; //***************************************************************************** // diff --git a/bsp/tm4c129x/libraries/startup/startup_gcc.c b/bsp/tm4c129x/libraries/startup/startup_gcc.c index ae10bf8e6c..c4815b1ec4 100644 --- a/bsp/tm4c129x/libraries/startup/startup_gcc.c +++ b/bsp/tm4c129x/libraries/startup/startup_gcc.c @@ -2,7 +2,7 @@ // // startup_gcc.c - Startup code for use with GNU tools. // -// Copyright (c) 2013-2014 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2013-2017 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Texas Instruments (TI) is supplying this software for use solely and @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 2.1.0.12573 of the DK-TM4C129X Firmware Package. +// This is part of revision 2.1.4.178 of the DK-TM4C129X Firmware Package. // //***************************************************************************** @@ -201,7 +201,7 @@ void (* const g_pfnVectors[])(void) = // for the "data" segment resides immediately following the "text" segment. // //***************************************************************************** -extern uint32_t _etext; +extern uint32_t _ldata; extern uint32_t _data; extern uint32_t _edata; extern uint32_t _bss; @@ -225,7 +225,7 @@ ResetISR(void) // // Copy the data segment initializers from flash to SRAM. // - pui32Src = &_etext; + pui32Src = &_ldata; for(pui32Dest = &_data; pui32Dest < &_edata; ) { *pui32Dest++ = *pui32Src++; diff --git a/bsp/tm4c129x/libraries/startup/startup_rvmdk.S b/bsp/tm4c129x/libraries/startup/startup_rvmdk.S index 5bc77ad795..3554d00143 100644 --- a/bsp/tm4c129x/libraries/startup/startup_rvmdk.S +++ b/bsp/tm4c129x/libraries/startup/startup_rvmdk.S @@ -3,7 +3,7 @@ ; ; startup_rvmdk.S - Startup code for use with Keil's uVision. ; -; Copyright (c) 2013-2014 Texas Instruments Incorporated. All rights reserved. +; Copyright (c) 2013-2017 Texas Instruments Incorporated. All rights reserved. ; Software License Agreement ; ; Texas Instruments (TI) is supplying this software for use solely and @@ -19,7 +19,7 @@ ; CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL ; DAMAGES, FOR ANY REASON WHATSOEVER. ; -; This is part of revision 2.1.0.12573 of the DK-TM4C129X Firmware Package. +; This is part of revision 2.1.4.178 of the DK-TM4C129X Firmware Package. ; ;****************************************************************************** @@ -28,7 +28,7 @@ ; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> ; ;****************************************************************************** -Stack EQU 0x00000100 +Stack EQU 0x00000200 ;****************************************************************************** ; diff --git a/bsp/tm4c129x/rtconfig.py b/bsp/tm4c129x/rtconfig.py index ba3fc51c93..d92c9f1101 100644 --- a/bsp/tm4c129x/rtconfig.py +++ b/bsp/tm4c129x/rtconfig.py @@ -19,7 +19,7 @@ if CROSS_TOOL == 'gcc': EXEC_PATH = r'D:\ArdaArmTools\Sourcery_Lite\bin' elif CROSS_TOOL == 'keil': PLATFORM = 'armcc' - EXEC_PATH = r'C:\Keil_v5' + EXEC_PATH = r'D:\Keil_v5' elif CROSS_TOOL == 'iar': print '================ERROR============================' print 'Not support iar yet!' diff --git a/bsp/tm4c129x/tm4c_rom.icf b/bsp/tm4c129x/tm4c_rom.icf index c5838c98ea..a07b00da91 100644 --- a/bsp/tm4c129x/tm4c_rom.icf +++ b/bsp/tm4c129x/tm4c_rom.icf @@ -2,7 +2,7 @@ // // blinky.icf - Linker configuration file for blinky. // -// Copyright (c) 2013-2014 Texas Instruments Incorporated. All rights reserved. +// Copyright (c) 2013-2017 Texas Instruments Incorporated. All rights reserved. // Software License Agreement // // Texas Instruments (TI) is supplying this software for use solely and @@ -18,7 +18,7 @@ // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL // DAMAGES, FOR ANY REASON WHATSOEVER. // -// This is part of revision 2.1.0.12573 of the DK-TM4C129X Firmware Package. +// This is part of revision 2.1.4.178 of the DK-TM4C129X Firmware Package. // //***************************************************************************** @@ -76,6 +76,7 @@ place at start of SRAM { section VTABLE }; // Place all read/write items into SRAM. // place in SRAM { readwrite, block HEAP }; + keep { section FSymTab }; keep { section VSymTab }; keep { section .rti_fn* }; \ No newline at end of file diff --git a/bsp/tm4c129x/tm4c_rom.ld b/bsp/tm4c129x/tm4c_rom.ld index dfdde3ac9d..5a82f1605d 100644 --- a/bsp/tm4c129x/tm4c_rom.ld +++ b/bsp/tm4c129x/tm4c_rom.ld @@ -2,7 +2,7 @@ * * blinky.ld - Linker configuration file for blinky. * - * Copyright (c) 2013-2014 Texas Instruments Incorporated. All rights reserved. + * Copyright (c) 2013-2017 Texas Instruments Incorporated. All rights reserved. * Software License Agreement * * Texas Instruments (TI) is supplying this software for use solely and @@ -18,35 +18,26 @@ * CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL * DAMAGES, FOR ANY REASON WHATSOEVER. * - * This is part of revision 2.1.0.12573 of the DK-TM4C129X Firmware Package. + * This is part of revision 2.1.4.178 of the DK-TM4C129X Firmware Package. * *****************************************************************************/ MEMORY { - CODE (rx) : ORIGIN = 0x00000000, LENGTH = 0x00100000 - DATA (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00040000 + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x00100000 + SRAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00040000 } -ENTRY(ResetISR) -_system_stack_size = 0x100; SECTIONS { .text : { - . = ALIGN(4); - _stext = .; - KEEP(*(.isr_vector)) /* Startup code */ - . = ALIGN(4); - *(.text) /* remaining code */ - *(.text.*) /* remaining code */ - *(.rodata) /* read-only data (constants) */ + _text = .; + KEEP(*(.isr_vector)) + *(.text*) *(.rodata*) - *(.glue_7) - *(.glue_7t) - *(.gnu.linkonce.t*) - - /* section information for finsh shell */ + + /* section information for finsh shell */ . = ALIGN(4); __fsymtab_start = .; KEEP(*(FSymTab)) @@ -63,98 +54,24 @@ SECTIONS KEEP(*(SORT(.rti_fn*))) __rt_init_end = .; . = ALIGN(4); - - . = ALIGN(4); + _etext = .; - } > CODE = 0 - - /* .ARM.exidx is sorted, so has to go in its own output section. */ - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - - /* This is used by the startup in order to initialize the .data secion */ - _sidata = .; - } > CODE - __exidx_end = .; - - /* .data section which is used for initialized data */ - - .data : AT (_sidata) - { - . = ALIGN(4); - /* This is used by the startup in order to initialize the .data secion */ - _data = . ; - - *(.data) - *(.data.*) - *(.gnu.linkonce.d*) - - . = ALIGN(4); - /* This is used by the startup in order to initialize the .data secion */ - _edata = . ; - } >DATA + } > FLASH - .stack : + .data : AT(ADDR(.text) + SIZEOF(.text)) { - . = . + _system_stack_size; - . = ALIGN(4); - _estack = .; - } >DATA + _data = .; + _ldata = LOADADDR (.data); + *(vtable) + *(.data*) + _edata = .; + } > SRAM - __bss_start = .; .bss : { - . = ALIGN(4); - /* This is used by the startup in order to initialize the .bss secion */ _bss = .; - - *(.bss) - *(.bss.*) + *(.bss*) *(COMMON) - - . = ALIGN(4); - /* This is used by the startup in order to initialize the .bss secion */ - _ebss = . ; - - *(.bss.init) - } > DATA - __bss_end = .; - - _end = .; - - /* Stabs debugging sections. */ - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - /* DWARF debug sections. - * Symbols in the DWARF debugging sections are relative to the beginning - * of the section so we begin them at 0. */ - /* DWARF 1 */ - .debug 0 : { *(.debug) } - .line 0 : { *(.line) } - /* GNU DWARF 1 extensions */ - .debug_srcinfo 0 : { *(.debug_srcinfo) } - .debug_sfnames 0 : { *(.debug_sfnames) } - /* DWARF 1.1 and DWARF 2 */ - .debug_aranges 0 : { *(.debug_aranges) } - .debug_pubnames 0 : { *(.debug_pubnames) } - /* DWARF 2 */ - .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_line 0 : { *(.debug_line) } - .debug_frame 0 : { *(.debug_frame) } - .debug_str 0 : { *(.debug_str) } - .debug_loc 0 : { *(.debug_loc) } - .debug_macinfo 0 : { *(.debug_macinfo) } - /* SGI/MIPS DWARF 2 extensions */ - .debug_weaknames 0 : { *(.debug_weaknames) } - .debug_funcnames 0 : { *(.debug_funcnames) } - .debug_typenames 0 : { *(.debug_typenames) } - .debug_varnames 0 : { *(.debug_varnames) } + _ebss = .; + } > SRAM } diff --git a/bsp/tm4c129x/tm4c_rom.sct b/bsp/tm4c129x/tm4c_rom.sct index 727cfddbfb..9162ff8c44 100644 --- a/bsp/tm4c129x/tm4c_rom.sct +++ b/bsp/tm4c129x/tm4c_rom.sct @@ -1,16 +1,47 @@ -; ************************************************************* -; *** Scatter-Loading Description File generated by uVision *** -; ************************************************************* +;****************************************************************************** +; +; blinky.sct - Linker configuration file for blinky. +; +; Copyright (c) 2013-2017 Texas Instruments Incorporated. All rights reserved. +; Software License Agreement +; +; Texas Instruments (TI) is supplying this software for use solely and +; exclusively on TI's microcontroller products. The software is owned by +; TI and/or its suppliers, and is protected under applicable copyright +; laws. You may not combine this software with "viral" open-source +; software in order to form a larger program. +; +; THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS. +; NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT +; NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +; A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY +; CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL +; DAMAGES, FOR ANY REASON WHATSOEVER. +; +; This is part of revision 2.1.4.178 of the DK-TM4C129X Firmware Package. +; +;****************************************************************************** -LR_IROM1 0x00000000 0x00100000 { ; load region size_region - ER_IROM1 0x00000000 0x00100000 { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - } - RW_IRAM1 0x20000000 0x00040000 { ; RW data - *(vtable, +First) ; for using IntRegister(). - .ANY (+RW +ZI) - } -} +LR_IROM 0x00000000 0x00100000 +{ + ; + ; Specify the Execution Address of the code and the size. + ; + ER_IROM 0x00000000 0x00100000 + { + *.o (RESET, +First) + * (InRoot$$Sections, +RO) + } + ; + ; Specify the Execution Address of the data area. + ; + RW_IRAM 0x20000000 0x00040000 + { + ; + ; Uncomment the following line in order to use IntRegister(). + ; + ;* (vtable, +First) + * (+RW, +ZI) + } +} -- GitLab