diff --git a/bsp/nuvoton_m451/.gitignore b/bsp/nuvoton_m451/.gitignore
new file mode 100644
index 0000000000000000000000000000000000000000..bcf5a5ac45fbe4271fe36c539870dfb36cc5d6d0
--- /dev/null
+++ b/bsp/nuvoton_m451/.gitignore
@@ -0,0 +1,6 @@
+Nu_Link_Driver.ini
+rmf.py
+*.ewd
+*.ewt
+*.uvoptx
+*.uvguix.*
diff --git a/bsp/nuvoton_m451/Libraries/CMSIS/Include/arm_common_tables.h b/bsp/nuvoton_m451/Libraries/CMSIS/Include/arm_common_tables.h
new file mode 100644
index 0000000000000000000000000000000000000000..1940846e65de381e12b498b3209dbdbec82fb02d
--- /dev/null
+++ b/bsp/nuvoton_m451/Libraries/CMSIS/Include/arm_common_tables.h
@@ -0,0 +1,37 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010 ARM Limited. All rights reserved.
+*
+* $Date: 14/06/07 1:58a $Revision: V1.0.2
+*
+* Project: CMSIS DSP Library
+* Title: arm_common_tables.h
+*
+* Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Version 1.0.2 2010/11/11
+* Documentation updated.
+*
+* Version 1.0.1 2010/10/05
+* Production release and review comments incorporated.
+*
+* Version 1.0.0 2010/09/20
+* Production release and review comments incorporated.
+* -------------------------------------------------------------------- */
+
+#ifndef _ARM_COMMON_TABLES_H
+#define _ARM_COMMON_TABLES_H
+
+#include "arm_math.h"
+
+extern const uint16_t armBitRevTable[1024];
+extern const q15_t armRecipTableQ15[64];
+extern const q31_t armRecipTableQ31[64];
+extern const q31_t realCoefAQ31[1024];
+extern const q31_t realCoefBQ31[1024];
+extern const float32_t twiddleCoef[6144];
+extern const q31_t twiddleCoefQ31[6144];
+extern const q15_t twiddleCoefQ15[6144];
+
+#endif /* ARM_COMMON_TABLES_H */
diff --git a/bsp/nuvoton_m451/Libraries/CMSIS/Include/arm_math.h b/bsp/nuvoton_m451/Libraries/CMSIS/Include/arm_math.h
new file mode 100644
index 0000000000000000000000000000000000000000..78c55ed548bd73e90475b0acee66c1709d559bc8
--- /dev/null
+++ b/bsp/nuvoton_m451/Libraries/CMSIS/Include/arm_math.h
@@ -0,0 +1,7556 @@
+/* ----------------------------------------------------------------------
+ * Copyright (C) 2010-2011 ARM Limited. All rights reserved.
+ *
+ * $Date: 14/06/07 1:58a $Revision: V1.1.0
+ *
+ * Project: CMSIS DSP Library
+ * Title: arm_math.h
+ *
+ * Description: Public header file for CMSIS DSP Library
+ *
+ * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+ *
+ * Version 1.1.0 2012/02/15
+ * Updated with more optimizations, bug fixes and minor API changes.
+ *
+ * Version 1.0.10 2011/7/15
+ * Big Endian support added and Merged M0 and M3/M4 Source code.
+ *
+ * Version 1.0.3 2010/11/29
+ * Re-organized the CMSIS folders and updated documentation.
+ *
+ * Version 1.0.2 2010/11/11
+ * Documentation updated.
+ *
+ * Version 1.0.1 2010/10/05
+ * Production release and review comments incorporated.
+ *
+ * Version 1.0.0 2010/09/20
+ * Production release and review comments incorporated.
+ * -------------------------------------------------------------------- */
+
+/**
+ \mainpage CMSIS DSP Software Library
+ *
+ * Introduction
+ *
+ * This user manual describes the CMSIS DSP software library,
+ * a suite of common signal processing functions for use on Cortex-M processor based devices.
+ *
+ * The library is divided into a number of functions each covering a specific category:
+ * - Basic math functions
+ * - Fast math functions
+ * - Complex math functions
+ * - Filters
+ * - Matrix functions
+ * - Transforms
+ * - Motor control functions
+ * - Statistical functions
+ * - Support functions
+ * - Interpolation functions
+ *
+ * The library has separate functions for operating on 8-bit integers, 16-bit integers,
+ * 32-bit integer and 32-bit floating-point values.
+ *
+ * Pre-processor Macros
+ *
+ * Each library project have differant pre-processor macros.
+ *
+ * - UNALIGNED_SUPPORT_DISABLE:
+ *
+ * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access
+ *
+ * - ARM_MATH_BIG_ENDIAN:
+ *
+ * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets.
+ *
+ * - ARM_MATH_MATRIX_CHECK:
+ *
+ * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices
+ *
+ * - ARM_MATH_ROUNDING:
+ *
+ * Define macro ARM_MATH_ROUNDING for rounding on support functions
+ *
+ * - ARM_MATH_CMx:
+ *
+ * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target
+ * and ARM_MATH_CM0 for building library on cortex-M0 target.
+ *
+ * - __FPU_PRESENT:
+ *
+ * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for M4bf and M4lf libraries
+ *
+ * Toolchain Support
+ *
+ * The library has been developed and tested with MDK-ARM version 4.23.
+ * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly.
+ *
+ * Using the Library
+ *
+ * The library installer contains prebuilt versions of the libraries in the Lib folder.
+ * - arm_cortexM4lf_math.lib (Little endian and Floating Point Unit on Cortex-M4)
+ * - arm_cortexM4bf_math.lib (Big endian and Floating Point Unit on Cortex-M4)
+ * - arm_cortexM4l_math.lib (Little endian on Cortex-M4)
+ * - arm_cortexM4b_math.lib (Big endian on Cortex-M4)
+ * - arm_cortexM3l_math.lib (Little endian on Cortex-M3)
+ * - arm_cortexM3b_math.lib (Big endian on Cortex-M3)
+ * - arm_cortexM0l_math.lib (Little endian on Cortex-M0)
+ * - arm_cortexM0b_math.lib (Big endian on Cortex-M3)
+ *
+ * The library functions are declared in the public file arm_math.h which is placed in the Include folder.
+ * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single
+ * public header file arm_math.h for Cortex-M4/M3/M0 with little endian and big endian. Same header file will be used for floating point unit(FPU) variants.
+ * Define the appropriate pre processor MACRO ARM_MATH_CM4 or ARM_MATH_CM3 or
+ * ARM_MATH_CM0 depending on the target processor in the application.
+ *
+ * Examples
+ *
+ * The library ships with a number of examples which demonstrate how to use the library functions.
+ *
+ * Building the Library
+ *
+ * The library installer contains project files to re build libraries on MDK Tool chain in the CMSIS\\DSP_Lib\\Source\\ARM folder.
+ * - arm_cortexM0b_math.uvproj
+ * - arm_cortexM0l_math.uvproj
+ * - arm_cortexM3b_math.uvproj
+ * - arm_cortexM3l_math.uvproj
+ * - arm_cortexM4b_math.uvproj
+ * - arm_cortexM4l_math.uvproj
+ * - arm_cortexM4bf_math.uvproj
+ * - arm_cortexM4lf_math.uvproj
+ *
+ *
+ * The project can be built by opening the appropriate project in MDK-ARM 4.23 chain and defining the optional pre processor MACROs detailed above.
+ *
+ * Copyright Notice
+ *
+ * Copyright (C) 2010 ARM Limited. All rights reserved.
+ */
+
+
+/**
+ * @defgroup groupMath Basic Math Functions
+ */
+
+/**
+ * @defgroup groupFastMath Fast Math Functions
+ * This set of functions provides a fast approximation to sine, cosine, and square root.
+ * As compared to most of the other functions in the CMSIS math library, the fast math functions
+ * operate on individual values and not arrays.
+ * There are separate functions for Q15, Q31, and floating-point data.
+ *
+ */
+
+/**
+ * @defgroup groupCmplxMath Complex Math Functions
+ * This set of functions operates on complex data vectors.
+ * The data in the complex arrays is stored in an interleaved fashion
+ * (real, imag, real, imag, ...).
+ * In the API functions, the number of samples in a complex array refers
+ * to the number of complex values; the array contains twice this number of
+ * real values.
+ */
+
+/**
+ * @defgroup groupFilters Filtering Functions
+ */
+
+/**
+ * @defgroup groupMatrix Matrix Functions
+ *
+ * This set of functions provides basic matrix math operations.
+ * The functions operate on matrix data structures. For example,
+ * the type
+ * definition for the floating-point matrix structure is shown
+ * below:
+ *
+ * typedef struct
+ * {
+ * uint16_t numRows; // number of rows of the matrix.
+ * uint16_t numCols; // number of columns of the matrix.
+ * float32_t *pData; // points to the data of the matrix.
+ * } arm_matrix_instance_f32;
+ *
+ * There are similar definitions for Q15 and Q31 data types.
+ *
+ * The structure specifies the size of the matrix and then points to
+ * an array of data. The array is of size numRows X numCols
+ * and the values are arranged in row order. That is, the
+ * matrix element (i, j) is stored at:
+ *
+ * pData[i*numCols + j]
+ *
+ *
+ * \par Init Functions
+ * There is an associated initialization function for each type of matrix
+ * data structure.
+ * The initialization function sets the values of the internal structure fields.
+ * Refer to the function arm_mat_init_f32(), arm_mat_init_q31()
+ * and arm_mat_init_q15() for floating-point, Q31 and Q15 types, respectively.
+ *
+ * \par
+ * Use of the initialization function is optional. However, if initialization function is used
+ * then the instance structure cannot be placed into a const data section.
+ * To place the instance structure in a const data
+ * section, manually initialize the data structure. For example:
+ *
+ * arm_matrix_instance_f32 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q31 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q15 S = {nRows, nColumns, pData};
+ *
+ * where nRows specifies the number of rows, nColumns
+ * specifies the number of columns, and pData points to the
+ * data array.
+ *
+ * \par Size Checking
+ * By default all of the matrix functions perform size checking on the input and
+ * output matrices. For example, the matrix addition function verifies that the
+ * two input matrices and the output matrix all have the same number of rows and
+ * columns. If the size check fails the functions return:
+ *
+ * ARM_MATH_SIZE_MISMATCH
+ *
+ * Otherwise the functions return
+ *
+ * ARM_MATH_SUCCESS
+ *
+ * There is some overhead associated with this matrix size checking.
+ * The matrix size checking is enabled via the \#define
+ *
+ * ARM_MATH_MATRIX_CHECK
+ *
+ * within the library project settings. By default this macro is defined
+ * and size checking is enabled. By changing the project settings and
+ * undefining this macro size checking is eliminated and the functions
+ * run a bit faster. With size checking disabled the functions always
+ * return ARM_MATH_SUCCESS.
+ */
+
+/**
+ * @defgroup groupTransforms Transform Functions
+ */
+
+/**
+ * @defgroup groupController Controller Functions
+ */
+
+/**
+ * @defgroup groupStats Statistics Functions
+ */
+/**
+ * @defgroup groupSupport Support Functions
+ */
+
+/**
+ * @defgroup groupInterpolation Interpolation Functions
+ * These functions perform 1- and 2-dimensional interpolation of data.
+ * Linear interpolation is used for 1-dimensional data and
+ * bilinear interpolation is used for 2-dimensional data.
+ */
+
+/**
+ * @defgroup groupExamples Examples
+ */
+#ifndef _ARM_MATH_H
+#define _ARM_MATH_H
+
+#define __CMSIS_GENERIC /* disable NVIC and Systick functions */
+
+#if defined (ARM_MATH_CM4)
+#include "core_cm4.h"
+#elif defined (ARM_MATH_CM3)
+#include "core_cm3.h"
+#elif defined (ARM_MATH_CM0)
+#include "core_cm0.h"
+#else
+#include "ARMCM4.h"
+#warning "Define either ARM_MATH_CM4 OR ARM_MATH_CM3...By Default building on ARM_MATH_CM4....."
+#endif
+
+#undef __CMSIS_GENERIC /* enable NVIC and Systick functions */
+#include "string.h"
+#include "math.h"
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+ /**
+ * @brief Macros required for reciprocal calculation in Normalized LMS
+ */
+
+#define DELTA_Q31 (0x100)
+#define DELTA_Q15 0x5
+#define INDEX_MASK 0x0000003F
+#ifndef PI
+#define PI 3.14159265358979f
+#endif
+
+ /**
+ * @brief Macros required for SINE and COSINE Fast math approximations
+ */
+
+#define TABLE_SIZE 256
+#define TABLE_SPACING_Q31 0x800000
+#define TABLE_SPACING_Q15 0x80
+
+ /**
+ * @brief Macros required for SINE and COSINE Controller functions
+ */
+ /* 1.31(q31) Fixed value of 2/360 */
+ /* -1 to +1 is divided into 360 values so total spacing is (2/360) */
+#define INPUT_SPACING 0xB60B61
+
+ /**
+ * @brief Macro for Unaligned Support
+ */
+#ifndef UNALIGNED_SUPPORT_DISABLE
+ #define ALIGN4
+#else
+ #if defined (__GNUC__)
+ #define ALIGN4 __attribute__((aligned(4)))
+ #else
+ #define ALIGN4 __align(4)
+ #endif
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+ /**
+ * @brief Error status returned by some functions in the library.
+ */
+
+ typedef enum
+ {
+ ARM_MATH_SUCCESS = 0, /**< No error */
+ ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */
+ ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */
+ ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation. */
+ ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */
+ ARM_MATH_SINGULAR = -5, /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */
+ ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */
+ } arm_status;
+
+ /**
+ * @brief 8-bit fractional data type in 1.7 format.
+ */
+ typedef int8_t q7_t;
+
+ /**
+ * @brief 16-bit fractional data type in 1.15 format.
+ */
+ typedef int16_t q15_t;
+
+ /**
+ * @brief 32-bit fractional data type in 1.31 format.
+ */
+ typedef int32_t q31_t;
+
+ /**
+ * @brief 64-bit fractional data type in 1.63 format.
+ */
+ typedef int64_t q63_t;
+
+ /**
+ * @brief 32-bit floating-point type definition.
+ */
+ typedef float float32_t;
+
+ /**
+ * @brief 64-bit floating-point type definition.
+ */
+ typedef double float64_t;
+
+ /**
+ * @brief definition to read/write two 16 bit values.
+ */
+#if defined (__GNUC__)
+ #define __SIMD32(addr) (*( int32_t **) & (addr))
+ #define _SIMD32_OFFSET(addr) (*( int32_t * ) (addr))
+#else
+ #define __SIMD32(addr) (*(__packed int32_t **) & (addr))
+ #define _SIMD32_OFFSET(addr) (*(__packed int32_t * ) (addr))
+#endif
+
+ #define __SIMD64(addr) (*(int64_t **) & (addr))
+
+#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0)
+ /**
+ * @brief definition to pack two 16 bit values.
+ */
+#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \
+ (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) )
+#define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0xFFFF0000) | \
+ (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF) )
+
+#endif
+
+
+ /**
+ * @brief definition to pack four 8 bit values.
+ */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \
+ (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \
+ (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \
+ (((int32_t)(v3) << 24) & (int32_t)0xFF000000) )
+#else
+
+#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \
+ (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \
+ (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \
+ (((int32_t)(v0) << 24) & (int32_t)0xFF000000) )
+
+#endif
+
+
+ /**
+ * @brief Clips Q63 to Q31 values.
+ */
+ __STATIC_INLINE q31_t clip_q63_to_q31(
+ q63_t x)
+ {
+ return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
+ ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x;
+ }
+
+ /**
+ * @brief Clips Q63 to Q15 values.
+ */
+ __STATIC_INLINE q15_t clip_q63_to_q15(
+ q63_t x)
+ {
+ return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
+ ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15);
+ }
+
+ /**
+ * @brief Clips Q31 to Q7 values.
+ */
+ __STATIC_INLINE q7_t clip_q31_to_q7(
+ q31_t x)
+ {
+ return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ?
+ ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x;
+ }
+
+ /**
+ * @brief Clips Q31 to Q15 values.
+ */
+ __STATIC_INLINE q15_t clip_q31_to_q15(
+ q31_t x)
+ {
+ return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ?
+ ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x;
+ }
+
+ /**
+ * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format.
+ */
+
+ __STATIC_INLINE q63_t mult32x64(
+ q63_t x,
+ q31_t y)
+ {
+ return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) +
+ (((q63_t) (x >> 32) * y)));
+ }
+
+
+#if defined (ARM_MATH_CM0) && defined ( __CC_ARM )
+#define __CLZ __clz
+#endif
+
+#if defined (ARM_MATH_CM0) && defined ( __TASKING__ )
+/* No need to redefine __CLZ */
+#endif
+
+#if defined (ARM_MATH_CM0) && ((defined (__ICCARM__)) ||(defined (__GNUC__)) )
+
+ __STATIC_INLINE uint32_t __CLZ(q31_t data);
+
+
+ __STATIC_INLINE uint32_t __CLZ(q31_t data)
+ {
+ uint32_t count = 0;
+ uint32_t mask = 0x80000000;
+
+ while((data & mask) == 0)
+ {
+ count += 1u;
+ mask = mask >> 1u;
+ }
+
+ return (count);
+
+ }
+
+#endif
+
+ /**
+ * @brief Function to Calculates 1/in(reciprocal) value of Q31 Data type.
+ */
+
+ __STATIC_INLINE uint32_t arm_recip_q31(
+ q31_t in,
+ q31_t * dst,
+ q31_t * pRecipTable)
+ {
+
+ uint32_t out, tempVal;
+ uint32_t index, i;
+ uint32_t signBits;
+
+ if(in > 0)
+ {
+ signBits = __CLZ(in) - 1;
+ }
+ else
+ {
+ signBits = __CLZ(-in) - 1;
+ }
+
+ /* Convert input sample to 1.31 format */
+ in = in << signBits;
+
+ /* calculation of index for initial approximated Val */
+ index = (uint32_t) (in >> 24u);
+ index = (index & INDEX_MASK);
+
+ /* 1.31 with exp 1 */
+ out = pRecipTable[index];
+
+ /* calculation of reciprocal value */
+ /* running approximation for two iterations */
+ for (i = 0u; i < 2u; i++)
+ {
+ tempVal = (q31_t) (((q63_t) in * out) >> 31u);
+ tempVal = 0x7FFFFFFF - tempVal;
+ /* 1.31 with exp 1 */
+ //out = (q31_t) (((q63_t) out * tempVal) >> 30u);
+ out = (q31_t) clip_q63_to_q31(((q63_t) out * tempVal) >> 30u);
+ }
+
+ /* write output */
+ *dst = out;
+
+ /* return num of signbits of out = 1/in value */
+ return (signBits + 1u);
+
+ }
+
+ /**
+ * @brief Function to Calculates 1/in(reciprocal) value of Q15 Data type.
+ */
+ __STATIC_INLINE uint32_t arm_recip_q15(
+ q15_t in,
+ q15_t * dst,
+ q15_t * pRecipTable)
+ {
+
+ uint32_t out = 0, tempVal = 0;
+ uint32_t index = 0, i = 0;
+ uint32_t signBits = 0;
+
+ if(in > 0)
+ {
+ signBits = __CLZ(in) - 17;
+ }
+ else
+ {
+ signBits = __CLZ(-in) - 17;
+ }
+
+ /* Convert input sample to 1.15 format */
+ in = in << signBits;
+
+ /* calculation of index for initial approximated Val */
+ index = in >> 8;
+ index = (index & INDEX_MASK);
+
+ /* 1.15 with exp 1 */
+ out = pRecipTable[index];
+
+ /* calculation of reciprocal value */
+ /* running approximation for two iterations */
+ for (i = 0; i < 2; i++)
+ {
+ tempVal = (q15_t) (((q31_t) in * out) >> 15);
+ tempVal = 0x7FFF - tempVal;
+ /* 1.15 with exp 1 */
+ out = (q15_t) (((q31_t) out * tempVal) >> 14);
+ }
+
+ /* write output */
+ *dst = out;
+
+ /* return num of signbits of out = 1/in value */
+ return (signBits + 1);
+
+ }
+
+
+ /*
+ * @brief C custom defined intrinisic function for only M0 processors
+ */
+#if defined(ARM_MATH_CM0)
+
+ __STATIC_INLINE q31_t __SSAT(
+ q31_t x,
+ uint32_t y)
+ {
+ int32_t posMax, negMin;
+ uint32_t i;
+
+ posMax = 1;
+ for (i = 0; i < (y - 1); i++)
+ {
+ posMax = posMax * 2;
+ }
+
+ if(x > 0)
+ {
+ posMax = (posMax - 1);
+
+ if(x > posMax)
+ {
+ x = posMax;
+ }
+ }
+ else
+ {
+ negMin = -posMax;
+
+ if(x < negMin)
+ {
+ x = negMin;
+ }
+ }
+ return (x);
+
+
+ }
+
+#endif /* end of ARM_MATH_CM0 */
+
+
+
+ /*
+ * @brief C custom defined intrinsic function for M3 and M0 processors
+ */
+#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0)
+
+ /*
+ * @brief C custom defined QADD8 for M3 and M0 processors
+ */
+ __STATIC_INLINE q31_t __QADD8(
+ q31_t x,
+ q31_t y)
+ {
+
+ q31_t sum;
+ q7_t r, s, t, u;
+
+ r = (q7_t) x;
+ s = (q7_t) y;
+
+ r = __SSAT((q31_t) (r + s), 8);
+ s = __SSAT(((q31_t) (((x << 16) >> 24) + ((y << 16) >> 24))), 8);
+ t = __SSAT(((q31_t) (((x << 8) >> 24) + ((y << 8) >> 24))), 8);
+ u = __SSAT(((q31_t) ((x >> 24) + (y >> 24))), 8);
+
+ sum =
+ (((q31_t) u << 24) & 0xFF000000) | (((q31_t) t << 16) & 0x00FF0000) |
+ (((q31_t) s << 8) & 0x0000FF00) | (r & 0x000000FF);
+
+ return sum;
+
+ }
+
+ /*
+ * @brief C custom defined QSUB8 for M3 and M0 processors
+ */
+ __STATIC_INLINE q31_t __QSUB8(
+ q31_t x,
+ q31_t y)
+ {
+
+ q31_t sum;
+ q31_t r, s, t, u;
+
+ r = (q7_t) x;
+ s = (q7_t) y;
+
+ r = __SSAT((r - s), 8);
+ s = __SSAT(((q31_t) (((x << 16) >> 24) - ((y << 16) >> 24))), 8) << 8;
+ t = __SSAT(((q31_t) (((x << 8) >> 24) - ((y << 8) >> 24))), 8) << 16;
+ u = __SSAT(((q31_t) ((x >> 24) - (y >> 24))), 8) << 24;
+
+ sum =
+ (u & 0xFF000000) | (t & 0x00FF0000) | (s & 0x0000FF00) | (r &
+ 0x000000FF);
+
+ return sum;
+ }
+
+ /*
+ * @brief C custom defined QADD16 for M3 and M0 processors
+ */
+
+ /*
+ * @brief C custom defined QADD16 for M3 and M0 processors
+ */
+ __STATIC_INLINE q31_t __QADD16(
+ q31_t x,
+ q31_t y)
+ {
+
+ q31_t sum;
+ q31_t r, s;
+
+ r = (short) x;
+ s = (short) y;
+
+ r = __SSAT(r + s, 16);
+ s = __SSAT(((q31_t) ((x >> 16) + (y >> 16))), 16) << 16;
+
+ sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+ return sum;
+
+ }
+
+ /*
+ * @brief C custom defined SHADD16 for M3 and M0 processors
+ */
+ __STATIC_INLINE q31_t __SHADD16(
+ q31_t x,
+ q31_t y)
+ {
+
+ q31_t sum;
+ q31_t r, s;
+
+ r = (short) x;
+ s = (short) y;
+
+ r = ((r >> 1) + (s >> 1));
+ s = ((q31_t) ((x >> 17) + (y >> 17))) << 16;
+
+ sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+ return sum;
+
+ }
+
+ /*
+ * @brief C custom defined QSUB16 for M3 and M0 processors
+ */
+ __STATIC_INLINE q31_t __QSUB16(
+ q31_t x,
+ q31_t y)
+ {
+
+ q31_t sum;
+ q31_t r, s;
+
+ r = (short) x;
+ s = (short) y;
+
+ r = __SSAT(r - s, 16);
+ s = __SSAT(((q31_t) ((x >> 16) - (y >> 16))), 16) << 16;
+
+ sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+ return sum;
+ }
+
+ /*
+ * @brief C custom defined SHSUB16 for M3 and M0 processors
+ */
+ __STATIC_INLINE q31_t __SHSUB16(
+ q31_t x,
+ q31_t y)
+ {
+
+ q31_t diff;
+ q31_t r, s;
+
+ r = (short) x;
+ s = (short) y;
+
+ r = ((r >> 1) - (s >> 1));
+ s = (((x >> 17) - (y >> 17)) << 16);
+
+ diff = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+ return diff;
+ }
+
+ /*
+ * @brief C custom defined QASX for M3 and M0 processors
+ */
+ __STATIC_INLINE q31_t __QASX(
+ q31_t x,
+ q31_t y)
+ {
+
+ q31_t sum = 0;
+
+ sum =
+ ((sum +
+ clip_q31_to_q15((q31_t) ((short) (x >> 16) + (short) y))) << 16) +
+ clip_q31_to_q15((q31_t) ((short) x - (short) (y >> 16)));
+
+ return sum;
+ }
+
+ /*
+ * @brief C custom defined SHASX for M3 and M0 processors
+ */
+ __STATIC_INLINE q31_t __SHASX(
+ q31_t x,
+ q31_t y)
+ {
+
+ q31_t sum;
+ q31_t r, s;
+
+ r = (short) x;
+ s = (short) y;
+
+ r = ((r >> 1) - (y >> 17));
+ s = (((x >> 17) + (s >> 1)) << 16);
+
+ sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+ return sum;
+ }
+
+
+ /*
+ * @brief C custom defined QSAX for M3 and M0 processors
+ */
+ __STATIC_INLINE q31_t __QSAX(
+ q31_t x,
+ q31_t y)
+ {
+
+ q31_t sum = 0;
+
+ sum =
+ ((sum +
+ clip_q31_to_q15((q31_t) ((short) (x >> 16) - (short) y))) << 16) +
+ clip_q31_to_q15((q31_t) ((short) x + (short) (y >> 16)));
+
+ return sum;
+ }
+
+ /*
+ * @brief C custom defined SHSAX for M3 and M0 processors
+ */
+ __STATIC_INLINE q31_t __SHSAX(
+ q31_t x,
+ q31_t y)
+ {
+
+ q31_t sum;
+ q31_t r, s;
+
+ r = (short) x;
+ s = (short) y;
+
+ r = ((r >> 1) + (y >> 17));
+ s = (((x >> 17) - (s >> 1)) << 16);
+
+ sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+ return sum;
+ }
+
+ /*
+ * @brief C custom defined SMUSDX for M3 and M0 processors
+ */
+ __STATIC_INLINE q31_t __SMUSDX(
+ q31_t x,
+ q31_t y)
+ {
+
+ return ((q31_t) (((short) x * (short) (y >> 16)) -
+ ((short) (x >> 16) * (short) y)));
+ }
+
+ /*
+ * @brief C custom defined SMUADX for M3 and M0 processors
+ */
+ __STATIC_INLINE q31_t __SMUADX(
+ q31_t x,
+ q31_t y)
+ {
+
+ return ((q31_t) (((short) x * (short) (y >> 16)) +
+ ((short) (x >> 16) * (short) y)));
+ }
+
+ /*
+ * @brief C custom defined QADD for M3 and M0 processors
+ */
+ __STATIC_INLINE q31_t __QADD(
+ q31_t x,
+ q31_t y)
+ {
+ return clip_q63_to_q31((q63_t) x + y);
+ }
+
+ /*
+ * @brief C custom defined QSUB for M3 and M0 processors
+ */
+ __STATIC_INLINE q31_t __QSUB(
+ q31_t x,
+ q31_t y)
+ {
+ return clip_q63_to_q31((q63_t) x - y);
+ }
+
+ /*
+ * @brief C custom defined SMLAD for M3 and M0 processors
+ */
+ __STATIC_INLINE q31_t __SMLAD(
+ q31_t x,
+ q31_t y,
+ q31_t sum)
+ {
+
+ return (sum + ((short) (x >> 16) * (short) (y >> 16)) +
+ ((short) x * (short) y));
+ }
+
+ /*
+ * @brief C custom defined SMLADX for M3 and M0 processors
+ */
+ __STATIC_INLINE q31_t __SMLADX(
+ q31_t x,
+ q31_t y,
+ q31_t sum)
+ {
+
+ return (sum + ((short) (x >> 16) * (short) (y)) +
+ ((short) x * (short) (y >> 16)));
+ }
+
+ /*
+ * @brief C custom defined SMLSDX for M3 and M0 processors
+ */
+ __STATIC_INLINE q31_t __SMLSDX(
+ q31_t x,
+ q31_t y,
+ q31_t sum)
+ {
+
+ return (sum - ((short) (x >> 16) * (short) (y)) +
+ ((short) x * (short) (y >> 16)));
+ }
+
+ /*
+ * @brief C custom defined SMLALD for M3 and M0 processors
+ */
+ __STATIC_INLINE q63_t __SMLALD(
+ q31_t x,
+ q31_t y,
+ q63_t sum)
+ {
+
+ return (sum + ((short) (x >> 16) * (short) (y >> 16)) +
+ ((short) x * (short) y));
+ }
+
+ /*
+ * @brief C custom defined SMLALDX for M3 and M0 processors
+ */
+ __STATIC_INLINE q63_t __SMLALDX(
+ q31_t x,
+ q31_t y,
+ q63_t sum)
+ {
+
+ return (sum + ((short) (x >> 16) * (short) y)) +
+ ((short) x * (short) (y >> 16));
+ }
+
+ /*
+ * @brief C custom defined SMUAD for M3 and M0 processors
+ */
+ __STATIC_INLINE q31_t __SMUAD(
+ q31_t x,
+ q31_t y)
+ {
+
+ return (((x >> 16) * (y >> 16)) +
+ (((x << 16) >> 16) * ((y << 16) >> 16)));
+ }
+
+ /*
+ * @brief C custom defined SMUSD for M3 and M0 processors
+ */
+ __STATIC_INLINE q31_t __SMUSD(
+ q31_t x,
+ q31_t y)
+ {
+
+ return (-((x >> 16) * (y >> 16)) +
+ (((x << 16) >> 16) * ((y << 16) >> 16)));
+ }
+
+
+ /*
+ * @brief C custom defined SXTB16 for M3 and M0 processors
+ */
+ __STATIC_INLINE q31_t __SXTB16(
+ q31_t x)
+ {
+
+ return ((((x << 24) >> 24) & 0x0000FFFF) |
+ (((x << 8) >> 8) & 0xFFFF0000));
+ }
+
+
+#endif /* defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0) */
+
+
+ /**
+ * @brief Instance structure for the Q7 FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of filter coefficients in the filter. */
+ q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ } arm_fir_instance_q7;
+
+ /**
+ * @brief Instance structure for the Q15 FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of filter coefficients in the filter. */
+ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ } arm_fir_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of filter coefficients in the filter. */
+ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ } arm_fir_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of filter coefficients in the filter. */
+ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ } arm_fir_instance_f32;
+
+
+ /**
+ * @brief Processing function for the Q7 FIR filter.
+ * @param[in] *S points to an instance of the Q7 FIR filter structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+ void arm_fir_q7(
+ const arm_fir_instance_q7 * S,
+ q7_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q7 FIR filter.
+ * @param[in,out] *S points to an instance of the Q7 FIR structure.
+ * @param[in] numTaps Number of filter coefficients in the filter.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] blockSize number of samples that are processed.
+ * @return none
+ */
+ void arm_fir_init_q7(
+ arm_fir_instance_q7 * S,
+ uint16_t numTaps,
+ q7_t * pCoeffs,
+ q7_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q15 FIR filter.
+ * @param[in] *S points to an instance of the Q15 FIR structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+ void arm_fir_q15(
+ const arm_fir_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4.
+ * @param[in] *S points to an instance of the Q15 FIR filter structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+ void arm_fir_fast_q15(
+ const arm_fir_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the Q15 FIR filter.
+ * @param[in,out] *S points to an instance of the Q15 FIR filter structure.
+ * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] blockSize number of samples that are processed at a time.
+ * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if
+ * numTaps is not a supported value.
+ */
+
+ arm_status arm_fir_init_q15(
+ arm_fir_instance_q15 * S,
+ uint16_t numTaps,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the Q31 FIR filter.
+ * @param[in] *S points to an instance of the Q31 FIR filter structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+ void arm_fir_q31(
+ const arm_fir_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4.
+ * @param[in] *S points to an instance of the Q31 FIR structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+ void arm_fir_fast_q31(
+ const arm_fir_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the Q31 FIR filter.
+ * @param[in,out] *S points to an instance of the Q31 FIR structure.
+ * @param[in] numTaps Number of filter coefficients in the filter.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] blockSize number of samples that are processed at a time.
+ * @return none.
+ */
+ void arm_fir_init_q31(
+ arm_fir_instance_q31 * S,
+ uint16_t numTaps,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the floating-point FIR filter.
+ * @param[in] *S points to an instance of the floating-point FIR structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+ void arm_fir_f32(
+ const arm_fir_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the floating-point FIR filter.
+ * @param[in,out] *S points to an instance of the floating-point FIR filter structure.
+ * @param[in] numTaps Number of filter coefficients in the filter.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] blockSize number of samples that are processed at a time.
+ * @return none.
+ */
+ void arm_fir_init_f32(
+ arm_fir_instance_f32 * S,
+ uint16_t numTaps,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the Q15 Biquad cascade filter.
+ */
+ typedef struct
+ {
+ int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */
+ q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */
+ int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */
+
+ } arm_biquad_casd_df1_inst_q15;
+
+
+ /**
+ * @brief Instance structure for the Q31 Biquad cascade filter.
+ */
+ typedef struct
+ {
+ uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */
+ q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */
+ uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */
+
+ } arm_biquad_casd_df1_inst_q31;
+
+ /**
+ * @brief Instance structure for the floating-point Biquad cascade filter.
+ */
+ typedef struct
+ {
+ uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */
+ float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */
+
+
+ } arm_biquad_casd_df1_inst_f32;
+
+
+
+ /**
+ * @brief Processing function for the Q15 Biquad cascade filter.
+ * @param[in] *S points to an instance of the Q15 Biquad cascade structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_biquad_cascade_df1_q15(
+ const arm_biquad_casd_df1_inst_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the Q15 Biquad cascade filter.
+ * @param[in,out] *S points to an instance of the Q15 Biquad cascade structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format
+ * @return none
+ */
+
+ void arm_biquad_cascade_df1_init_q15(
+ arm_biquad_casd_df1_inst_q15 * S,
+ uint8_t numStages,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ int8_t postShift);
+
+
+ /**
+ * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4.
+ * @param[in] *S points to an instance of the Q15 Biquad cascade structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_biquad_cascade_df1_fast_q15(
+ const arm_biquad_casd_df1_inst_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q31 Biquad cascade filter
+ * @param[in] *S points to an instance of the Q31 Biquad cascade structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_biquad_cascade_df1_q31(
+ const arm_biquad_casd_df1_inst_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4.
+ * @param[in] *S points to an instance of the Q31 Biquad cascade structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_biquad_cascade_df1_fast_q31(
+ const arm_biquad_casd_df1_inst_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the Q31 Biquad cascade filter.
+ * @param[in,out] *S points to an instance of the Q31 Biquad cascade structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format
+ * @return none
+ */
+
+ void arm_biquad_cascade_df1_init_q31(
+ arm_biquad_casd_df1_inst_q31 * S,
+ uint8_t numStages,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ int8_t postShift);
+
+ /**
+ * @brief Processing function for the floating-point Biquad cascade filter.
+ * @param[in] *S points to an instance of the floating-point Biquad cascade structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_biquad_cascade_df1_f32(
+ const arm_biquad_casd_df1_inst_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the floating-point Biquad cascade filter.
+ * @param[in,out] *S points to an instance of the floating-point Biquad cascade structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @return none
+ */
+
+ void arm_biquad_cascade_df1_init_f32(
+ arm_biquad_casd_df1_inst_f32 * S,
+ uint8_t numStages,
+ float32_t * pCoeffs,
+ float32_t * pState);
+
+
+ /**
+ * @brief Instance structure for the floating-point matrix structure.
+ */
+
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows of the matrix. */
+ uint16_t numCols; /**< number of columns of the matrix. */
+ float32_t *pData; /**< points to the data of the matrix. */
+ } arm_matrix_instance_f32;
+
+ /**
+ * @brief Instance structure for the Q15 matrix structure.
+ */
+
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows of the matrix. */
+ uint16_t numCols; /**< number of columns of the matrix. */
+ q15_t *pData; /**< points to the data of the matrix. */
+
+ } arm_matrix_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 matrix structure.
+ */
+
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows of the matrix. */
+ uint16_t numCols; /**< number of columns of the matrix. */
+ q31_t *pData; /**< points to the data of the matrix. */
+
+ } arm_matrix_instance_q31;
+
+
+
+ /**
+ * @brief Floating-point matrix addition.
+ * @param[in] *pSrcA points to the first input matrix structure
+ * @param[in] *pSrcB points to the second input matrix structure
+ * @param[out] *pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_add_f32(
+ const arm_matrix_instance_f32 * pSrcA,
+ const arm_matrix_instance_f32 * pSrcB,
+ arm_matrix_instance_f32 * pDst);
+
+ /**
+ * @brief Q15 matrix addition.
+ * @param[in] *pSrcA points to the first input matrix structure
+ * @param[in] *pSrcB points to the second input matrix structure
+ * @param[out] *pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_add_q15(
+ const arm_matrix_instance_q15 * pSrcA,
+ const arm_matrix_instance_q15 * pSrcB,
+ arm_matrix_instance_q15 * pDst);
+
+ /**
+ * @brief Q31 matrix addition.
+ * @param[in] *pSrcA points to the first input matrix structure
+ * @param[in] *pSrcB points to the second input matrix structure
+ * @param[out] *pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_add_q31(
+ const arm_matrix_instance_q31 * pSrcA,
+ const arm_matrix_instance_q31 * pSrcB,
+ arm_matrix_instance_q31 * pDst);
+
+
+ /**
+ * @brief Floating-point matrix transpose.
+ * @param[in] *pSrc points to the input matrix
+ * @param[out] *pDst points to the output matrix
+ * @return The function returns either ARM_MATH_SIZE_MISMATCH
+ * or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_trans_f32(
+ const arm_matrix_instance_f32 * pSrc,
+ arm_matrix_instance_f32 * pDst);
+
+
+ /**
+ * @brief Q15 matrix transpose.
+ * @param[in] *pSrc points to the input matrix
+ * @param[out] *pDst points to the output matrix
+ * @return The function returns either ARM_MATH_SIZE_MISMATCH
+ * or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_trans_q15(
+ const arm_matrix_instance_q15 * pSrc,
+ arm_matrix_instance_q15 * pDst);
+
+ /**
+ * @brief Q31 matrix transpose.
+ * @param[in] *pSrc points to the input matrix
+ * @param[out] *pDst points to the output matrix
+ * @return The function returns either ARM_MATH_SIZE_MISMATCH
+ * or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_trans_q31(
+ const arm_matrix_instance_q31 * pSrc,
+ arm_matrix_instance_q31 * pDst);
+
+
+ /**
+ * @brief Floating-point matrix multiplication
+ * @param[in] *pSrcA points to the first input matrix structure
+ * @param[in] *pSrcB points to the second input matrix structure
+ * @param[out] *pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_mult_f32(
+ const arm_matrix_instance_f32 * pSrcA,
+ const arm_matrix_instance_f32 * pSrcB,
+ arm_matrix_instance_f32 * pDst);
+
+ /**
+ * @brief Q15 matrix multiplication
+ * @param[in] *pSrcA points to the first input matrix structure
+ * @param[in] *pSrcB points to the second input matrix structure
+ * @param[out] *pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_mult_q15(
+ const arm_matrix_instance_q15 * pSrcA,
+ const arm_matrix_instance_q15 * pSrcB,
+ arm_matrix_instance_q15 * pDst,
+ q15_t * pState);
+
+ /**
+ * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
+ * @param[in] *pSrcA points to the first input matrix structure
+ * @param[in] *pSrcB points to the second input matrix structure
+ * @param[out] *pDst points to output matrix structure
+ * @param[in] *pState points to the array for storing intermediate results
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_mult_fast_q15(
+ const arm_matrix_instance_q15 * pSrcA,
+ const arm_matrix_instance_q15 * pSrcB,
+ arm_matrix_instance_q15 * pDst,
+ q15_t * pState);
+
+ /**
+ * @brief Q31 matrix multiplication
+ * @param[in] *pSrcA points to the first input matrix structure
+ * @param[in] *pSrcB points to the second input matrix structure
+ * @param[out] *pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_mult_q31(
+ const arm_matrix_instance_q31 * pSrcA,
+ const arm_matrix_instance_q31 * pSrcB,
+ arm_matrix_instance_q31 * pDst);
+
+ /**
+ * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
+ * @param[in] *pSrcA points to the first input matrix structure
+ * @param[in] *pSrcB points to the second input matrix structure
+ * @param[out] *pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_mult_fast_q31(
+ const arm_matrix_instance_q31 * pSrcA,
+ const arm_matrix_instance_q31 * pSrcB,
+ arm_matrix_instance_q31 * pDst);
+
+
+ /**
+ * @brief Floating-point matrix subtraction
+ * @param[in] *pSrcA points to the first input matrix structure
+ * @param[in] *pSrcB points to the second input matrix structure
+ * @param[out] *pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_sub_f32(
+ const arm_matrix_instance_f32 * pSrcA,
+ const arm_matrix_instance_f32 * pSrcB,
+ arm_matrix_instance_f32 * pDst);
+
+ /**
+ * @brief Q15 matrix subtraction
+ * @param[in] *pSrcA points to the first input matrix structure
+ * @param[in] *pSrcB points to the second input matrix structure
+ * @param[out] *pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_sub_q15(
+ const arm_matrix_instance_q15 * pSrcA,
+ const arm_matrix_instance_q15 * pSrcB,
+ arm_matrix_instance_q15 * pDst);
+
+ /**
+ * @brief Q31 matrix subtraction
+ * @param[in] *pSrcA points to the first input matrix structure
+ * @param[in] *pSrcB points to the second input matrix structure
+ * @param[out] *pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_sub_q31(
+ const arm_matrix_instance_q31 * pSrcA,
+ const arm_matrix_instance_q31 * pSrcB,
+ arm_matrix_instance_q31 * pDst);
+
+ /**
+ * @brief Floating-point matrix scaling.
+ * @param[in] *pSrc points to the input matrix
+ * @param[in] scale scale factor
+ * @param[out] *pDst points to the output matrix
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_scale_f32(
+ const arm_matrix_instance_f32 * pSrc,
+ float32_t scale,
+ arm_matrix_instance_f32 * pDst);
+
+ /**
+ * @brief Q15 matrix scaling.
+ * @param[in] *pSrc points to input matrix
+ * @param[in] scaleFract fractional portion of the scale factor
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] *pDst points to output matrix
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_scale_q15(
+ const arm_matrix_instance_q15 * pSrc,
+ q15_t scaleFract,
+ int32_t shift,
+ arm_matrix_instance_q15 * pDst);
+
+ /**
+ * @brief Q31 matrix scaling.
+ * @param[in] *pSrc points to input matrix
+ * @param[in] scaleFract fractional portion of the scale factor
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] *pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_scale_q31(
+ const arm_matrix_instance_q31 * pSrc,
+ q31_t scaleFract,
+ int32_t shift,
+ arm_matrix_instance_q31 * pDst);
+
+
+ /**
+ * @brief Q31 matrix initialization.
+ * @param[in,out] *S points to an instance of the floating-point matrix structure.
+ * @param[in] nRows number of rows in the matrix.
+ * @param[in] nColumns number of columns in the matrix.
+ * @param[in] *pData points to the matrix data array.
+ * @return none
+ */
+
+ void arm_mat_init_q31(
+ arm_matrix_instance_q31 * S,
+ uint16_t nRows,
+ uint16_t nColumns,
+ q31_t * pData);
+
+ /**
+ * @brief Q15 matrix initialization.
+ * @param[in,out] *S points to an instance of the floating-point matrix structure.
+ * @param[in] nRows number of rows in the matrix.
+ * @param[in] nColumns number of columns in the matrix.
+ * @param[in] *pData points to the matrix data array.
+ * @return none
+ */
+
+ void arm_mat_init_q15(
+ arm_matrix_instance_q15 * S,
+ uint16_t nRows,
+ uint16_t nColumns,
+ q15_t * pData);
+
+ /**
+ * @brief Floating-point matrix initialization.
+ * @param[in,out] *S points to an instance of the floating-point matrix structure.
+ * @param[in] nRows number of rows in the matrix.
+ * @param[in] nColumns number of columns in the matrix.
+ * @param[in] *pData points to the matrix data array.
+ * @return none
+ */
+
+ void arm_mat_init_f32(
+ arm_matrix_instance_f32 * S,
+ uint16_t nRows,
+ uint16_t nColumns,
+ float32_t * pData);
+
+
+
+ /**
+ * @brief Instance structure for the Q15 PID Control.
+ */
+ typedef struct
+ {
+ q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */
+#ifdef ARM_MATH_CM0
+ q15_t A1;
+ q15_t A2;
+#else
+ q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/
+#endif
+ q15_t state[3]; /**< The state array of length 3. */
+ q15_t Kp; /**< The proportional gain. */
+ q15_t Ki; /**< The integral gain. */
+ q15_t Kd; /**< The derivative gain. */
+ } arm_pid_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 PID Control.
+ */
+ typedef struct
+ {
+ q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */
+ q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */
+ q31_t A2; /**< The derived gain, A2 = Kd . */
+ q31_t state[3]; /**< The state array of length 3. */
+ q31_t Kp; /**< The proportional gain. */
+ q31_t Ki; /**< The integral gain. */
+ q31_t Kd; /**< The derivative gain. */
+
+ } arm_pid_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point PID Control.
+ */
+ typedef struct
+ {
+ float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */
+ float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */
+ float32_t A2; /**< The derived gain, A2 = Kd . */
+ float32_t state[3]; /**< The state array of length 3. */
+ float32_t Kp; /**< The proportional gain. */
+ float32_t Ki; /**< The integral gain. */
+ float32_t Kd; /**< The derivative gain. */
+ } arm_pid_instance_f32;
+
+
+
+ /**
+ * @brief Initialization function for the floating-point PID Control.
+ * @param[in,out] *S points to an instance of the PID structure.
+ * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.
+ * @return none.
+ */
+ void arm_pid_init_f32(
+ arm_pid_instance_f32 * S,
+ int32_t resetStateFlag);
+
+ /**
+ * @brief Reset function for the floating-point PID Control.
+ * @param[in,out] *S is an instance of the floating-point PID Control structure
+ * @return none
+ */
+ void arm_pid_reset_f32(
+ arm_pid_instance_f32 * S);
+
+
+ /**
+ * @brief Initialization function for the Q31 PID Control.
+ * @param[in,out] *S points to an instance of the Q15 PID structure.
+ * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.
+ * @return none.
+ */
+ void arm_pid_init_q31(
+ arm_pid_instance_q31 * S,
+ int32_t resetStateFlag);
+
+
+ /**
+ * @brief Reset function for the Q31 PID Control.
+ * @param[in,out] *S points to an instance of the Q31 PID Control structure
+ * @return none
+ */
+
+ void arm_pid_reset_q31(
+ arm_pid_instance_q31 * S);
+
+ /**
+ * @brief Initialization function for the Q15 PID Control.
+ * @param[in,out] *S points to an instance of the Q15 PID structure.
+ * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.
+ * @return none.
+ */
+ void arm_pid_init_q15(
+ arm_pid_instance_q15 * S,
+ int32_t resetStateFlag);
+
+ /**
+ * @brief Reset function for the Q15 PID Control.
+ * @param[in,out] *S points to an instance of the q15 PID Control structure
+ * @return none
+ */
+ void arm_pid_reset_q15(
+ arm_pid_instance_q15 * S);
+
+
+ /**
+ * @brief Instance structure for the floating-point Linear Interpolate function.
+ */
+ typedef struct
+ {
+ uint32_t nValues; /**< nValues */
+ float32_t x1; /**< x1 */
+ float32_t xSpacing; /**< xSpacing */
+ float32_t *pYData; /**< pointer to the table of Y values */
+ } arm_linear_interp_instance_f32;
+
+ /**
+ * @brief Instance structure for the floating-point bilinear interpolation function.
+ */
+
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows in the data table. */
+ uint16_t numCols; /**< number of columns in the data table. */
+ float32_t *pData; /**< points to the data table. */
+ } arm_bilinear_interp_instance_f32;
+
+ /**
+ * @brief Instance structure for the Q31 bilinear interpolation function.
+ */
+
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows in the data table. */
+ uint16_t numCols; /**< number of columns in the data table. */
+ q31_t *pData; /**< points to the data table. */
+ } arm_bilinear_interp_instance_q31;
+
+ /**
+ * @brief Instance structure for the Q15 bilinear interpolation function.
+ */
+
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows in the data table. */
+ uint16_t numCols; /**< number of columns in the data table. */
+ q15_t *pData; /**< points to the data table. */
+ } arm_bilinear_interp_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q15 bilinear interpolation function.
+ */
+
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows in the data table. */
+ uint16_t numCols; /**< number of columns in the data table. */
+ q7_t *pData; /**< points to the data table. */
+ } arm_bilinear_interp_instance_q7;
+
+
+ /**
+ * @brief Q7 vector multiplication.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_mult_q7(
+ q7_t * pSrcA,
+ q7_t * pSrcB,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Q15 vector multiplication.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_mult_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Q31 vector multiplication.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_mult_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Floating-point vector multiplication.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_mult_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the Q15 CFFT/CIFFT function.
+ */
+
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ q15_t *pTwiddle; /**< points to the twiddle factor table. */
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ } arm_cfft_radix4_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 CFFT/CIFFT function.
+ */
+
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ q31_t *pTwiddle; /**< points to the twiddle factor table. */
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ } arm_cfft_radix4_instance_q31;
+
+
+ /**
+ * @brief Instance structure for the floating-point CFFT/CIFFT function.
+ */
+
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ float32_t *pTwiddle; /**< points to the twiddle factor table. */
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ float32_t onebyfftLen; /**< value of 1/fftLen. */
+ } arm_cfft_radix4_instance_f32;
+
+
+ /**
+ * @brief Instance structure for the Q15 CFFT/CIFFT function.
+ */
+
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ q15_t *pTwiddle; /**< points to the Sin twiddle factor table. */
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ } arm_cfft_radix2_instance_q15;
+
+ /**
+ * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function.
+ */
+
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ q31_t *pTwiddle; /**< points to the Twiddle factor table. */
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ } arm_cfft_radix2_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point CFFT/CIFFT function.
+ */
+
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ float32_t *pTwiddle; /**< points to the Twiddle factor table. */
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ float32_t onebyfftLen; /**< value of 1/fftLen. */
+ } arm_cfft_radix2_instance_f32;
+
+
+ /**
+ * @brief Processing function for the Q15 CFFT/CIFFT.
+ * @param[in] *S points to an instance of the Q15 CFFT/CIFFT structure.
+ * @param[in, out] *pSrc points to the complex data buffer. Processing occurs in-place.
+ * @return none.
+ */
+
+ void arm_cfft_radix4_q15(
+ const arm_cfft_radix4_instance_q15 * S,
+ q15_t * pSrc);
+
+ /**
+ * @brief Processing function for the Q15 CFFT/CIFFT.
+ * @param[in] *S points to an instance of the Q15 CFFT/CIFFT structure.
+ * @param[in, out] *pSrc points to the complex data buffer. Processing occurs in-place.
+ * @return none.
+ */
+
+ void arm_cfft_radix2_q15(
+ const arm_cfft_radix2_instance_q15 * S,
+ q15_t * pSrc);
+
+ /**
+ * @brief Initialization function for the Q15 CFFT/CIFFT.
+ * @param[in,out] *S points to an instance of the Q15 CFFT/CIFFT structure.
+ * @param[in] fftLen length of the FFT.
+ * @param[in] ifftFlag flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.
+ * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
+ * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value.
+ */
+
+ arm_status arm_cfft_radix4_init_q15(
+ arm_cfft_radix4_instance_q15 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+ /**
+ * @brief Initialization function for the Q15 CFFT/CIFFT.
+ * @param[in,out] *S points to an instance of the Q15 CFFT/CIFFT structure.
+ * @param[in] fftLen length of the FFT.
+ * @param[in] ifftFlag flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.
+ * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
+ * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value.
+ */
+
+ arm_status arm_cfft_radix2_init_q15(
+ arm_cfft_radix2_instance_q15 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+ /**
+ * @brief Processing function for the Q31 CFFT/CIFFT.
+ * @param[in] *S points to an instance of the Q31 CFFT/CIFFT structure.
+ * @param[in, out] *pSrc points to the complex data buffer. Processing occurs in-place.
+ * @return none.
+ */
+
+ void arm_cfft_radix4_q31(
+ const arm_cfft_radix4_instance_q31 * S,
+ q31_t * pSrc);
+
+ /**
+ * @brief Initialization function for the Q31 CFFT/CIFFT.
+ * @param[in,out] *S points to an instance of the Q31 CFFT/CIFFT structure.
+ * @param[in] fftLen length of the FFT.
+ * @param[in] ifftFlag flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.
+ * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
+ * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value.
+ */
+
+ arm_status arm_cfft_radix4_init_q31(
+ arm_cfft_radix4_instance_q31 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+ /**
+ * @brief Processing function for the Radix-2 Q31 CFFT/CIFFT.
+ * @param[in] *S points to an instance of the Radix-2 Q31 CFFT/CIFFT structure.
+ * @param[in, out] *pSrc points to the complex data buffer. Processing occurs in-place.
+ * @return none.
+ */
+
+ void arm_cfft_radix2_q31(
+ const arm_cfft_radix2_instance_q31 * S,
+ q31_t * pSrc);
+
+ /**
+ * @brief Initialization function for the Radix-2 Q31 CFFT/CIFFT.
+ * @param[in,out] *S points to an instance of the Radix-2 Q31 CFFT/CIFFT structure.
+ * @param[in] fftLen length of the FFT.
+ * @param[in] ifftFlag flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.
+ * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
+ * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value.
+ */
+
+ arm_status arm_cfft_radix2_init_q31(
+ arm_cfft_radix2_instance_q31 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+
+
+ /**
+ * @brief Processing function for the floating-point CFFT/CIFFT.
+ * @param[in] *S points to an instance of the floating-point CFFT/CIFFT structure.
+ * @param[in, out] *pSrc points to the complex data buffer. Processing occurs in-place.
+ * @return none.
+ */
+
+ void arm_cfft_radix2_f32(
+ const arm_cfft_radix2_instance_f32 * S,
+ float32_t * pSrc);
+
+ /**
+ * @brief Initialization function for the floating-point CFFT/CIFFT.
+ * @param[in,out] *S points to an instance of the floating-point CFFT/CIFFT structure.
+ * @param[in] fftLen length of the FFT.
+ * @param[in] ifftFlag flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.
+ * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value.
+ */
+
+ arm_status arm_cfft_radix2_init_f32(
+ arm_cfft_radix2_instance_f32 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+ /**
+ * @brief Processing function for the floating-point CFFT/CIFFT.
+ * @param[in] *S points to an instance of the floating-point CFFT/CIFFT structure.
+ * @param[in, out] *pSrc points to the complex data buffer. Processing occurs in-place.
+ * @return none.
+ */
+
+ void arm_cfft_radix4_f32(
+ const arm_cfft_radix4_instance_f32 * S,
+ float32_t * pSrc);
+
+ /**
+ * @brief Initialization function for the floating-point CFFT/CIFFT.
+ * @param[in,out] *S points to an instance of the floating-point CFFT/CIFFT structure.
+ * @param[in] fftLen length of the FFT.
+ * @param[in] ifftFlag flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.
+ * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value.
+ */
+
+ arm_status arm_cfft_radix4_init_f32(
+ arm_cfft_radix4_instance_f32 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+
+
+ /*----------------------------------------------------------------------
+ * Internal functions prototypes FFT function
+ ----------------------------------------------------------------------*/
+
+ /**
+ * @brief Core function for the floating-point CFFT butterfly process.
+ * @param[in, out] *pSrc points to the in-place buffer of floating-point data type.
+ * @param[in] fftLen length of the FFT.
+ * @param[in] *pCoef points to the twiddle coefficient buffer.
+ * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
+ * @return none.
+ */
+
+ void arm_radix4_butterfly_f32(
+ float32_t * pSrc,
+ uint16_t fftLen,
+ float32_t * pCoef,
+ uint16_t twidCoefModifier);
+
+ /**
+ * @brief Core function for the floating-point CIFFT butterfly process.
+ * @param[in, out] *pSrc points to the in-place buffer of floating-point data type.
+ * @param[in] fftLen length of the FFT.
+ * @param[in] *pCoef points to twiddle coefficient buffer.
+ * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
+ * @param[in] onebyfftLen value of 1/fftLen.
+ * @return none.
+ */
+
+ void arm_radix4_butterfly_inverse_f32(
+ float32_t * pSrc,
+ uint16_t fftLen,
+ float32_t * pCoef,
+ uint16_t twidCoefModifier,
+ float32_t onebyfftLen);
+
+ /**
+ * @brief In-place bit reversal function.
+ * @param[in, out] *pSrc points to the in-place buffer of floating-point data type.
+ * @param[in] fftSize length of the FFT.
+ * @param[in] bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table.
+ * @param[in] *pBitRevTab points to the bit reversal table.
+ * @return none.
+ */
+
+ void arm_bitreversal_f32(
+ float32_t * pSrc,
+ uint16_t fftSize,
+ uint16_t bitRevFactor,
+ uint16_t * pBitRevTab);
+
+ /**
+ * @brief Core function for the Q31 CFFT butterfly process.
+ * @param[in, out] *pSrc points to the in-place buffer of Q31 data type.
+ * @param[in] fftLen length of the FFT.
+ * @param[in] *pCoef points to Twiddle coefficient buffer.
+ * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
+ * @return none.
+ */
+
+ void arm_radix4_butterfly_q31(
+ q31_t * pSrc,
+ uint32_t fftLen,
+ q31_t * pCoef,
+ uint32_t twidCoefModifier);
+
+ /**
+ * @brief Core function for the f32 FFT butterfly process.
+ * @param[in, out] *pSrc points to the in-place buffer of f32 data type.
+ * @param[in] fftLen length of the FFT.
+ * @param[in] *pCoef points to Twiddle coefficient buffer.
+ * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
+ * @return none.
+ */
+
+ void arm_radix2_butterfly_f32(
+ float32_t * pSrc,
+ uint32_t fftLen,
+ float32_t * pCoef,
+ uint16_t twidCoefModifier);
+
+ /**
+ * @brief Core function for the Radix-2 Q31 CFFT butterfly process.
+ * @param[in, out] *pSrc points to the in-place buffer of Q31 data type.
+ * @param[in] fftLen length of the FFT.
+ * @param[in] *pCoef points to Twiddle coefficient buffer.
+ * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
+ * @return none.
+ */
+
+ void arm_radix2_butterfly_q31(
+ q31_t * pSrc,
+ uint32_t fftLen,
+ q31_t * pCoef,
+ uint16_t twidCoefModifier);
+
+ /**
+ * @brief Core function for the Radix-2 Q15 CFFT butterfly process.
+ * @param[in, out] *pSrc points to the in-place buffer of Q15 data type.
+ * @param[in] fftLen length of the FFT.
+ * @param[in] *pCoef points to Twiddle coefficient buffer.
+ * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
+ * @return none.
+ */
+
+ void arm_radix2_butterfly_q15(
+ q15_t * pSrc,
+ uint32_t fftLen,
+ q15_t * pCoef,
+ uint16_t twidCoefModifier);
+
+ /**
+ * @brief Core function for the Radix-2 Q15 CFFT Inverse butterfly process.
+ * @param[in, out] *pSrc points to the in-place buffer of Q15 data type.
+ * @param[in] fftLen length of the FFT.
+ * @param[in] *pCoef points to Twiddle coefficient buffer.
+ * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
+ * @return none.
+ */
+
+ void arm_radix2_butterfly_inverse_q15(
+ q15_t * pSrc,
+ uint32_t fftLen,
+ q15_t * pCoef,
+ uint16_t twidCoefModifier);
+
+ /**
+ * @brief Core function for the Radix-2 Q31 CFFT Inverse butterfly process.
+ * @param[in, out] *pSrc points to the in-place buffer of Q31 data type.
+ * @param[in] fftLen length of the FFT.
+ * @param[in] *pCoef points to Twiddle coefficient buffer.
+ * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
+ * @return none.
+ */
+
+ void arm_radix2_butterfly_inverse_q31(
+ q31_t * pSrc,
+ uint32_t fftLen,
+ q31_t * pCoef,
+ uint16_t twidCoefModifier);
+
+ /**
+ * @brief Core function for the f32 IFFT butterfly process.
+ * @param[in, out] *pSrc points to the in-place buffer of f32 data type.
+ * @param[in] fftLen length of the FFT.
+ * @param[in] *pCoef points to Twiddle coefficient buffer.
+ * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
+ * @param[in] onebyfftLen 1/fftLenfth
+ * @return none.
+ */
+
+ void arm_radix2_butterfly_inverse_f32(
+ float32_t * pSrc,
+ uint32_t fftLen,
+ float32_t * pCoef,
+ uint16_t twidCoefModifier,
+ float32_t onebyfftLen);
+
+ /**
+ * @brief Core function for the Q31 CIFFT butterfly process.
+ * @param[in, out] *pSrc points to the in-place buffer of Q31 data type.
+ * @param[in] fftLen length of the FFT.
+ * @param[in] *pCoef points to twiddle coefficient buffer.
+ * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
+ * @return none.
+ */
+
+ void arm_radix4_butterfly_inverse_q31(
+ q31_t * pSrc,
+ uint32_t fftLen,
+ q31_t * pCoef,
+ uint32_t twidCoefModifier);
+
+ /**
+ * @brief In-place bit reversal function.
+ * @param[in, out] *pSrc points to the in-place buffer of Q31 data type.
+ * @param[in] fftLen length of the FFT.
+ * @param[in] bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table
+ * @param[in] *pBitRevTab points to bit reversal table.
+ * @return none.
+ */
+
+ void arm_bitreversal_q31(
+ q31_t * pSrc,
+ uint32_t fftLen,
+ uint16_t bitRevFactor,
+ uint16_t * pBitRevTab);
+
+ /**
+ * @brief Core function for the Q15 CFFT butterfly process.
+ * @param[in, out] *pSrc16 points to the in-place buffer of Q15 data type.
+ * @param[in] fftLen length of the FFT.
+ * @param[in] *pCoef16 points to twiddle coefficient buffer.
+ * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
+ * @return none.
+ */
+
+ void arm_radix4_butterfly_q15(
+ q15_t * pSrc16,
+ uint32_t fftLen,
+ q15_t * pCoef16,
+ uint32_t twidCoefModifier);
+
+
+ /**
+ * @brief Core function for the Q15 CIFFT butterfly process.
+ * @param[in, out] *pSrc16 points to the in-place buffer of Q15 data type.
+ * @param[in] fftLen length of the FFT.
+ * @param[in] *pCoef16 points to twiddle coefficient buffer.
+ * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
+ * @return none.
+ */
+
+ void arm_radix4_butterfly_inverse_q15(
+ q15_t * pSrc16,
+ uint32_t fftLen,
+ q15_t * pCoef16,
+ uint32_t twidCoefModifier);
+
+ /**
+ * @brief In-place bit reversal function.
+ * @param[in, out] *pSrc points to the in-place buffer of Q15 data type.
+ * @param[in] fftLen length of the FFT.
+ * @param[in] bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table
+ * @param[in] *pBitRevTab points to bit reversal table.
+ * @return none.
+ */
+
+ void arm_bitreversal_q15(
+ q15_t * pSrc,
+ uint32_t fftLen,
+ uint16_t bitRevFactor,
+ uint16_t * pBitRevTab);
+
+
+ /**
+ * @brief Instance structure for the Q15 RFFT/RIFFT function.
+ */
+
+ typedef struct
+ {
+ uint32_t fftLenReal; /**< length of the real FFT. */
+ uint32_t fftLenBy2; /**< length of the complex FFT. */
+ uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+ uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+ uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */
+ q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */
+ arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */
+ } arm_rfft_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 RFFT/RIFFT function.
+ */
+
+ typedef struct
+ {
+ uint32_t fftLenReal; /**< length of the real FFT. */
+ uint32_t fftLenBy2; /**< length of the complex FFT. */
+ uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+ uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+ uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */
+ q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */
+ arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */
+ } arm_rfft_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point RFFT/RIFFT function.
+ */
+
+ typedef struct
+ {
+ uint32_t fftLenReal; /**< length of the real FFT. */
+ uint16_t fftLenBy2; /**< length of the complex FFT. */
+ uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+ uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+ uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */
+ float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */
+ arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */
+ } arm_rfft_instance_f32;
+
+ /**
+ * @brief Processing function for the Q15 RFFT/RIFFT.
+ * @param[in] *S points to an instance of the Q15 RFFT/RIFFT structure.
+ * @param[in] *pSrc points to the input buffer.
+ * @param[out] *pDst points to the output buffer.
+ * @return none.
+ */
+
+ void arm_rfft_q15(
+ const arm_rfft_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst);
+
+ /**
+ * @brief Initialization function for the Q15 RFFT/RIFFT.
+ * @param[in, out] *S points to an instance of the Q15 RFFT/RIFFT structure.
+ * @param[in] *S_CFFT points to an instance of the Q15 CFFT/CIFFT structure.
+ * @param[in] fftLenReal length of the FFT.
+ * @param[in] ifftFlagR flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform.
+ * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported value.
+ */
+
+ arm_status arm_rfft_init_q15(
+ arm_rfft_instance_q15 * S,
+ arm_cfft_radix4_instance_q15 * S_CFFT,
+ uint32_t fftLenReal,
+ uint32_t ifftFlagR,
+ uint32_t bitReverseFlag);
+
+ /**
+ * @brief Processing function for the Q31 RFFT/RIFFT.
+ * @param[in] *S points to an instance of the Q31 RFFT/RIFFT structure.
+ * @param[in] *pSrc points to the input buffer.
+ * @param[out] *pDst points to the output buffer.
+ * @return none.
+ */
+
+ void arm_rfft_q31(
+ const arm_rfft_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst);
+
+ /**
+ * @brief Initialization function for the Q31 RFFT/RIFFT.
+ * @param[in, out] *S points to an instance of the Q31 RFFT/RIFFT structure.
+ * @param[in, out] *S_CFFT points to an instance of the Q31 CFFT/CIFFT structure.
+ * @param[in] fftLenReal length of the FFT.
+ * @param[in] ifftFlagR flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform.
+ * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported value.
+ */
+
+ arm_status arm_rfft_init_q31(
+ arm_rfft_instance_q31 * S,
+ arm_cfft_radix4_instance_q31 * S_CFFT,
+ uint32_t fftLenReal,
+ uint32_t ifftFlagR,
+ uint32_t bitReverseFlag);
+
+ /**
+ * @brief Initialization function for the floating-point RFFT/RIFFT.
+ * @param[in,out] *S points to an instance of the floating-point RFFT/RIFFT structure.
+ * @param[in,out] *S_CFFT points to an instance of the floating-point CFFT/CIFFT structure.
+ * @param[in] fftLenReal length of the FFT.
+ * @param[in] ifftFlagR flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform.
+ * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported value.
+ */
+
+ arm_status arm_rfft_init_f32(
+ arm_rfft_instance_f32 * S,
+ arm_cfft_radix4_instance_f32 * S_CFFT,
+ uint32_t fftLenReal,
+ uint32_t ifftFlagR,
+ uint32_t bitReverseFlag);
+
+ /**
+ * @brief Processing function for the floating-point RFFT/RIFFT.
+ * @param[in] *S points to an instance of the floating-point RFFT/RIFFT structure.
+ * @param[in] *pSrc points to the input buffer.
+ * @param[out] *pDst points to the output buffer.
+ * @return none.
+ */
+
+ void arm_rfft_f32(
+ const arm_rfft_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst);
+
+ /**
+ * @brief Instance structure for the floating-point DCT4/IDCT4 function.
+ */
+
+ typedef struct
+ {
+ uint16_t N; /**< length of the DCT4. */
+ uint16_t Nby2; /**< half of the length of the DCT4. */
+ float32_t normalize; /**< normalizing factor. */
+ float32_t *pTwiddle; /**< points to the twiddle factor table. */
+ float32_t *pCosFactor; /**< points to the cosFactor table. */
+ arm_rfft_instance_f32 *pRfft; /**< points to the real FFT instance. */
+ arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */
+ } arm_dct4_instance_f32;
+
+ /**
+ * @brief Initialization function for the floating-point DCT4/IDCT4.
+ * @param[in,out] *S points to an instance of floating-point DCT4/IDCT4 structure.
+ * @param[in] *S_RFFT points to an instance of floating-point RFFT/RIFFT structure.
+ * @param[in] *S_CFFT points to an instance of floating-point CFFT/CIFFT structure.
+ * @param[in] N length of the DCT4.
+ * @param[in] Nby2 half of the length of the DCT4.
+ * @param[in] normalize normalizing factor.
+ * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported transform length.
+ */
+
+ arm_status arm_dct4_init_f32(
+ arm_dct4_instance_f32 * S,
+ arm_rfft_instance_f32 * S_RFFT,
+ arm_cfft_radix4_instance_f32 * S_CFFT,
+ uint16_t N,
+ uint16_t Nby2,
+ float32_t normalize);
+
+ /**
+ * @brief Processing function for the floating-point DCT4/IDCT4.
+ * @param[in] *S points to an instance of the floating-point DCT4/IDCT4 structure.
+ * @param[in] *pState points to state buffer.
+ * @param[in,out] *pInlineBuffer points to the in-place input and output buffer.
+ * @return none.
+ */
+
+ void arm_dct4_f32(
+ const arm_dct4_instance_f32 * S,
+ float32_t * pState,
+ float32_t * pInlineBuffer);
+
+ /**
+ * @brief Instance structure for the Q31 DCT4/IDCT4 function.
+ */
+
+ typedef struct
+ {
+ uint16_t N; /**< length of the DCT4. */
+ uint16_t Nby2; /**< half of the length of the DCT4. */
+ q31_t normalize; /**< normalizing factor. */
+ q31_t *pTwiddle; /**< points to the twiddle factor table. */
+ q31_t *pCosFactor; /**< points to the cosFactor table. */
+ arm_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */
+ arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */
+ } arm_dct4_instance_q31;
+
+ /**
+ * @brief Initialization function for the Q31 DCT4/IDCT4.
+ * @param[in,out] *S points to an instance of Q31 DCT4/IDCT4 structure.
+ * @param[in] *S_RFFT points to an instance of Q31 RFFT/RIFFT structure
+ * @param[in] *S_CFFT points to an instance of Q31 CFFT/CIFFT structure
+ * @param[in] N length of the DCT4.
+ * @param[in] Nby2 half of the length of the DCT4.
+ * @param[in] normalize normalizing factor.
+ * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length.
+ */
+
+ arm_status arm_dct4_init_q31(
+ arm_dct4_instance_q31 * S,
+ arm_rfft_instance_q31 * S_RFFT,
+ arm_cfft_radix4_instance_q31 * S_CFFT,
+ uint16_t N,
+ uint16_t Nby2,
+ q31_t normalize);
+
+ /**
+ * @brief Processing function for the Q31 DCT4/IDCT4.
+ * @param[in] *S points to an instance of the Q31 DCT4 structure.
+ * @param[in] *pState points to state buffer.
+ * @param[in,out] *pInlineBuffer points to the in-place input and output buffer.
+ * @return none.
+ */
+
+ void arm_dct4_q31(
+ const arm_dct4_instance_q31 * S,
+ q31_t * pState,
+ q31_t * pInlineBuffer);
+
+ /**
+ * @brief Instance structure for the Q15 DCT4/IDCT4 function.
+ */
+
+ typedef struct
+ {
+ uint16_t N; /**< length of the DCT4. */
+ uint16_t Nby2; /**< half of the length of the DCT4. */
+ q15_t normalize; /**< normalizing factor. */
+ q15_t *pTwiddle; /**< points to the twiddle factor table. */
+ q15_t *pCosFactor; /**< points to the cosFactor table. */
+ arm_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */
+ arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */
+ } arm_dct4_instance_q15;
+
+ /**
+ * @brief Initialization function for the Q15 DCT4/IDCT4.
+ * @param[in,out] *S points to an instance of Q15 DCT4/IDCT4 structure.
+ * @param[in] *S_RFFT points to an instance of Q15 RFFT/RIFFT structure.
+ * @param[in] *S_CFFT points to an instance of Q15 CFFT/CIFFT structure.
+ * @param[in] N length of the DCT4.
+ * @param[in] Nby2 half of the length of the DCT4.
+ * @param[in] normalize normalizing factor.
+ * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length.
+ */
+
+ arm_status arm_dct4_init_q15(
+ arm_dct4_instance_q15 * S,
+ arm_rfft_instance_q15 * S_RFFT,
+ arm_cfft_radix4_instance_q15 * S_CFFT,
+ uint16_t N,
+ uint16_t Nby2,
+ q15_t normalize);
+
+ /**
+ * @brief Processing function for the Q15 DCT4/IDCT4.
+ * @param[in] *S points to an instance of the Q15 DCT4 structure.
+ * @param[in] *pState points to state buffer.
+ * @param[in,out] *pInlineBuffer points to the in-place input and output buffer.
+ * @return none.
+ */
+
+ void arm_dct4_q15(
+ const arm_dct4_instance_q15 * S,
+ q15_t * pState,
+ q15_t * pInlineBuffer);
+
+ /**
+ * @brief Floating-point vector addition.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_add_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Q7 vector addition.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_add_q7(
+ q7_t * pSrcA,
+ q7_t * pSrcB,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Q15 vector addition.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_add_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Q31 vector addition.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_add_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Floating-point vector subtraction.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_sub_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Q7 vector subtraction.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_sub_q7(
+ q7_t * pSrcA,
+ q7_t * pSrcB,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Q15 vector subtraction.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_sub_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Q31 vector subtraction.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_sub_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Multiplies a floating-point vector by a scalar.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] scale scale factor to be applied
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+ void arm_scale_f32(
+ float32_t * pSrc,
+ float32_t scale,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Multiplies a Q7 vector by a scalar.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] scaleFract fractional portion of the scale value
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+ void arm_scale_q7(
+ q7_t * pSrc,
+ q7_t scaleFract,
+ int8_t shift,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Multiplies a Q15 vector by a scalar.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] scaleFract fractional portion of the scale value
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+ void arm_scale_q15(
+ q15_t * pSrc,
+ q15_t scaleFract,
+ int8_t shift,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Multiplies a Q31 vector by a scalar.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] scaleFract fractional portion of the scale value
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+ void arm_scale_q31(
+ q31_t * pSrc,
+ q31_t scaleFract,
+ int8_t shift,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Q7 vector absolute value.
+ * @param[in] *pSrc points to the input buffer
+ * @param[out] *pDst points to the output buffer
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_abs_q7(
+ q7_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Floating-point vector absolute value.
+ * @param[in] *pSrc points to the input buffer
+ * @param[out] *pDst points to the output buffer
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_abs_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Q15 vector absolute value.
+ * @param[in] *pSrc points to the input buffer
+ * @param[out] *pDst points to the output buffer
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_abs_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Q31 vector absolute value.
+ * @param[in] *pSrc points to the input buffer
+ * @param[out] *pDst points to the output buffer
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_abs_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Dot product of floating-point vectors.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[in] blockSize number of samples in each vector
+ * @param[out] *result output result returned here
+ * @return none.
+ */
+
+ void arm_dot_prod_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ uint32_t blockSize,
+ float32_t * result);
+
+ /**
+ * @brief Dot product of Q7 vectors.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[in] blockSize number of samples in each vector
+ * @param[out] *result output result returned here
+ * @return none.
+ */
+
+ void arm_dot_prod_q7(
+ q7_t * pSrcA,
+ q7_t * pSrcB,
+ uint32_t blockSize,
+ q31_t * result);
+
+ /**
+ * @brief Dot product of Q15 vectors.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[in] blockSize number of samples in each vector
+ * @param[out] *result output result returned here
+ * @return none.
+ */
+
+ void arm_dot_prod_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ uint32_t blockSize,
+ q63_t * result);
+
+ /**
+ * @brief Dot product of Q31 vectors.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[in] blockSize number of samples in each vector
+ * @param[out] *result output result returned here
+ * @return none.
+ */
+
+ void arm_dot_prod_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ uint32_t blockSize,
+ q63_t * result);
+
+ /**
+ * @brief Shifts the elements of a Q7 vector a specified number of bits.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+ void arm_shift_q7(
+ q7_t * pSrc,
+ int8_t shiftBits,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Shifts the elements of a Q15 vector a specified number of bits.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+ void arm_shift_q15(
+ q15_t * pSrc,
+ int8_t shiftBits,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Shifts the elements of a Q31 vector a specified number of bits.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+ void arm_shift_q31(
+ q31_t * pSrc,
+ int8_t shiftBits,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Adds a constant offset to a floating-point vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] offset is the offset to be added
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+ void arm_offset_f32(
+ float32_t * pSrc,
+ float32_t offset,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Adds a constant offset to a Q7 vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] offset is the offset to be added
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+ void arm_offset_q7(
+ q7_t * pSrc,
+ q7_t offset,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Adds a constant offset to a Q15 vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] offset is the offset to be added
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+ void arm_offset_q15(
+ q15_t * pSrc,
+ q15_t offset,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Adds a constant offset to a Q31 vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] offset is the offset to be added
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+ void arm_offset_q31(
+ q31_t * pSrc,
+ q31_t offset,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Negates the elements of a floating-point vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+ void arm_negate_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Negates the elements of a Q7 vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+ void arm_negate_q7(
+ q7_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Negates the elements of a Q15 vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+ void arm_negate_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Negates the elements of a Q31 vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+ void arm_negate_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+ /**
+ * @brief Copies the elements of a floating-point vector.
+ * @param[in] *pSrc input pointer
+ * @param[out] *pDst output pointer
+ * @param[in] blockSize number of samples to process
+ * @return none.
+ */
+ void arm_copy_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Copies the elements of a Q7 vector.
+ * @param[in] *pSrc input pointer
+ * @param[out] *pDst output pointer
+ * @param[in] blockSize number of samples to process
+ * @return none.
+ */
+ void arm_copy_q7(
+ q7_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Copies the elements of a Q15 vector.
+ * @param[in] *pSrc input pointer
+ * @param[out] *pDst output pointer
+ * @param[in] blockSize number of samples to process
+ * @return none.
+ */
+ void arm_copy_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Copies the elements of a Q31 vector.
+ * @param[in] *pSrc input pointer
+ * @param[out] *pDst output pointer
+ * @param[in] blockSize number of samples to process
+ * @return none.
+ */
+ void arm_copy_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+ /**
+ * @brief Fills a constant value into a floating-point vector.
+ * @param[in] value input value to be filled
+ * @param[out] *pDst output pointer
+ * @param[in] blockSize number of samples to process
+ * @return none.
+ */
+ void arm_fill_f32(
+ float32_t value,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Fills a constant value into a Q7 vector.
+ * @param[in] value input value to be filled
+ * @param[out] *pDst output pointer
+ * @param[in] blockSize number of samples to process
+ * @return none.
+ */
+ void arm_fill_q7(
+ q7_t value,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Fills a constant value into a Q15 vector.
+ * @param[in] value input value to be filled
+ * @param[out] *pDst output pointer
+ * @param[in] blockSize number of samples to process
+ * @return none.
+ */
+ void arm_fill_q15(
+ q15_t value,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Fills a constant value into a Q31 vector.
+ * @param[in] value input value to be filled
+ * @param[out] *pDst output pointer
+ * @param[in] blockSize number of samples to process
+ * @return none.
+ */
+ void arm_fill_q31(
+ q31_t value,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+/**
+ * @brief Convolution of floating-point sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1.
+ * @return none.
+ */
+
+ void arm_conv_f32(
+ float32_t * pSrcA,
+ uint32_t srcALen,
+ float32_t * pSrcB,
+ uint32_t srcBLen,
+ float32_t * pDst);
+
+
+ /**
+ * @brief Convolution of Q15 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1.
+ * @param[in] *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] *pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+ * @return none.
+ */
+
+
+ void arm_conv_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+/**
+ * @brief Convolution of Q15 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1.
+ * @return none.
+ */
+
+ void arm_conv_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst);
+
+ /**
+ * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1.
+ * @return none.
+ */
+
+ void arm_conv_fast_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst);
+
+ /**
+ * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1.
+ * @param[in] *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] *pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+ * @return none.
+ */
+
+ void arm_conv_fast_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+
+ /**
+ * @brief Convolution of Q31 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1.
+ * @return none.
+ */
+
+ void arm_conv_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst);
+
+ /**
+ * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1.
+ * @return none.
+ */
+
+ void arm_conv_fast_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst);
+
+
+ /**
+ * @brief Convolution of Q7 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1.
+ * @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+ * @return none.
+ */
+
+ void arm_conv_opt_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+
+ /**
+ * @brief Convolution of Q7 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1.
+ * @return none.
+ */
+
+ void arm_conv_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst);
+
+
+ /**
+ * @brief Partial convolution of floating-point sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+
+ arm_status arm_conv_partial_f32(
+ float32_t * pSrcA,
+ uint32_t srcALen,
+ float32_t * pSrcB,
+ uint32_t srcBLen,
+ float32_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+ /**
+ * @brief Partial convolution of Q15 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @param[in] * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] * pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+
+ arm_status arm_conv_partial_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+/**
+ * @brief Partial convolution of Q15 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+
+ arm_status arm_conv_partial_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+ /**
+ * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+
+ arm_status arm_conv_partial_fast_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+
+ /**
+ * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @param[in] * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] * pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+
+ arm_status arm_conv_partial_fast_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+ /**
+ * @brief Partial convolution of Q31 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+
+ arm_status arm_conv_partial_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+
+ /**
+ * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+
+ arm_status arm_conv_partial_fast_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+
+ /**
+ * @brief Partial convolution of Q7 sequences
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+
+ arm_status arm_conv_partial_opt_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+/**
+ * @brief Partial convolution of Q7 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+
+ arm_status arm_conv_partial_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+
+
+ /**
+ * @brief Instance structure for the Q15 FIR decimator.
+ */
+
+ typedef struct
+ {
+ uint8_t M; /**< decimation factor. */
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ } arm_fir_decimate_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 FIR decimator.
+ */
+
+ typedef struct
+ {
+ uint8_t M; /**< decimation factor. */
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+
+ } arm_fir_decimate_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point FIR decimator.
+ */
+
+ typedef struct
+ {
+ uint8_t M; /**< decimation factor. */
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+
+ } arm_fir_decimate_instance_f32;
+
+
+
+ /**
+ * @brief Processing function for the floating-point FIR decimator.
+ * @param[in] *S points to an instance of the floating-point FIR decimator structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none
+ */
+
+ void arm_fir_decimate_f32(
+ const arm_fir_decimate_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the floating-point FIR decimator.
+ * @param[in,out] *S points to an instance of the floating-point FIR decimator structure.
+ * @param[in] numTaps number of coefficients in the filter.
+ * @param[in] M decimation factor.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * blockSize is not a multiple of M.
+ */
+
+ arm_status arm_fir_decimate_init_f32(
+ arm_fir_decimate_instance_f32 * S,
+ uint16_t numTaps,
+ uint8_t M,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the Q15 FIR decimator.
+ * @param[in] *S points to an instance of the Q15 FIR decimator structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none
+ */
+
+ void arm_fir_decimate_q15(
+ const arm_fir_decimate_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
+ * @param[in] *S points to an instance of the Q15 FIR decimator structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none
+ */
+
+ void arm_fir_decimate_fast_q15(
+ const arm_fir_decimate_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+
+ /**
+ * @brief Initialization function for the Q15 FIR decimator.
+ * @param[in,out] *S points to an instance of the Q15 FIR decimator structure.
+ * @param[in] numTaps number of coefficients in the filter.
+ * @param[in] M decimation factor.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * blockSize is not a multiple of M.
+ */
+
+ arm_status arm_fir_decimate_init_q15(
+ arm_fir_decimate_instance_q15 * S,
+ uint16_t numTaps,
+ uint8_t M,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the Q31 FIR decimator.
+ * @param[in] *S points to an instance of the Q31 FIR decimator structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none
+ */
+
+ void arm_fir_decimate_q31(
+ const arm_fir_decimate_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
+ * @param[in] *S points to an instance of the Q31 FIR decimator structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none
+ */
+
+ void arm_fir_decimate_fast_q31(
+ arm_fir_decimate_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q31 FIR decimator.
+ * @param[in,out] *S points to an instance of the Q31 FIR decimator structure.
+ * @param[in] numTaps number of coefficients in the filter.
+ * @param[in] M decimation factor.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * blockSize is not a multiple of M.
+ */
+
+ arm_status arm_fir_decimate_init_q31(
+ arm_fir_decimate_instance_q31 * S,
+ uint16_t numTaps,
+ uint8_t M,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ uint32_t blockSize);
+
+
+
+ /**
+ * @brief Instance structure for the Q15 FIR interpolator.
+ */
+
+ typedef struct
+ {
+ uint8_t L; /**< upsample factor. */
+ uint16_t phaseLength; /**< length of each polyphase filter component. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */
+ q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
+ } arm_fir_interpolate_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 FIR interpolator.
+ */
+
+ typedef struct
+ {
+ uint8_t L; /**< upsample factor. */
+ uint16_t phaseLength; /**< length of each polyphase filter component. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */
+ q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
+ } arm_fir_interpolate_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point FIR interpolator.
+ */
+
+ typedef struct
+ {
+ uint8_t L; /**< upsample factor. */
+ uint16_t phaseLength; /**< length of each polyphase filter component. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */
+ float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */
+ } arm_fir_interpolate_instance_f32;
+
+
+ /**
+ * @brief Processing function for the Q15 FIR interpolator.
+ * @param[in] *S points to an instance of the Q15 FIR interpolator structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none.
+ */
+
+ void arm_fir_interpolate_q15(
+ const arm_fir_interpolate_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q15 FIR interpolator.
+ * @param[in,out] *S points to an instance of the Q15 FIR interpolator structure.
+ * @param[in] L upsample factor.
+ * @param[in] numTaps number of filter coefficients in the filter.
+ * @param[in] *pCoeffs points to the filter coefficient buffer.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * the filter length numTaps is not a multiple of the interpolation factor L.
+ */
+
+ arm_status arm_fir_interpolate_init_q15(
+ arm_fir_interpolate_instance_q15 * S,
+ uint8_t L,
+ uint16_t numTaps,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the Q31 FIR interpolator.
+ * @param[in] *S points to an instance of the Q15 FIR interpolator structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none.
+ */
+
+ void arm_fir_interpolate_q31(
+ const arm_fir_interpolate_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the Q31 FIR interpolator.
+ * @param[in,out] *S points to an instance of the Q31 FIR interpolator structure.
+ * @param[in] L upsample factor.
+ * @param[in] numTaps number of filter coefficients in the filter.
+ * @param[in] *pCoeffs points to the filter coefficient buffer.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * the filter length numTaps is not a multiple of the interpolation factor L.
+ */
+
+ arm_status arm_fir_interpolate_init_q31(
+ arm_fir_interpolate_instance_q31 * S,
+ uint8_t L,
+ uint16_t numTaps,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the floating-point FIR interpolator.
+ * @param[in] *S points to an instance of the floating-point FIR interpolator structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none.
+ */
+
+ void arm_fir_interpolate_f32(
+ const arm_fir_interpolate_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the floating-point FIR interpolator.
+ * @param[in,out] *S points to an instance of the floating-point FIR interpolator structure.
+ * @param[in] L upsample factor.
+ * @param[in] numTaps number of filter coefficients in the filter.
+ * @param[in] *pCoeffs points to the filter coefficient buffer.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * the filter length numTaps is not a multiple of the interpolation factor L.
+ */
+
+ arm_status arm_fir_interpolate_init_f32(
+ arm_fir_interpolate_instance_f32 * S,
+ uint8_t L,
+ uint16_t numTaps,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ uint32_t blockSize);
+
+ /**
+ * @brief Instance structure for the high precision Q31 Biquad cascade filter.
+ */
+
+ typedef struct
+ {
+ uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */
+ q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */
+ uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */
+
+ } arm_biquad_cas_df1_32x64_ins_q31;
+
+
+ /**
+ * @param[in] *S points to an instance of the high precision Q31 Biquad cascade filter structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_biquad_cas_df1_32x64_q31(
+ const arm_biquad_cas_df1_32x64_ins_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @param[in,out] *S points to an instance of the high precision Q31 Biquad cascade filter structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format
+ * @return none
+ */
+
+ void arm_biquad_cas_df1_32x64_init_q31(
+ arm_biquad_cas_df1_32x64_ins_q31 * S,
+ uint8_t numStages,
+ q31_t * pCoeffs,
+ q63_t * pState,
+ uint8_t postShift);
+
+
+
+ /**
+ * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
+ */
+
+ typedef struct
+ {
+ uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */
+ float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */
+ } arm_biquad_cascade_df2T_instance_f32;
+
+
+ /**
+ * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in] *S points to an instance of the filter data structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_biquad_cascade_df2T_f32(
+ const arm_biquad_cascade_df2T_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in,out] *S points to an instance of the filter data structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @return none
+ */
+
+ void arm_biquad_cascade_df2T_init_f32(
+ arm_biquad_cascade_df2T_instance_f32 * S,
+ uint8_t numStages,
+ float32_t * pCoeffs,
+ float32_t * pState);
+
+
+
+ /**
+ * @brief Instance structure for the Q15 FIR lattice filter.
+ */
+
+ typedef struct
+ {
+ uint16_t numStages; /**< number of filter stages. */
+ q15_t *pState; /**< points to the state variable array. The array is of length numStages. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */
+ } arm_fir_lattice_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 FIR lattice filter.
+ */
+
+ typedef struct
+ {
+ uint16_t numStages; /**< number of filter stages. */
+ q31_t *pState; /**< points to the state variable array. The array is of length numStages. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */
+ } arm_fir_lattice_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point FIR lattice filter.
+ */
+
+ typedef struct
+ {
+ uint16_t numStages; /**< number of filter stages. */
+ float32_t *pState; /**< points to the state variable array. The array is of length numStages. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */
+ } arm_fir_lattice_instance_f32;
+
+ /**
+ * @brief Initialization function for the Q15 FIR lattice filter.
+ * @param[in] *S points to an instance of the Q15 FIR lattice structure.
+ * @param[in] numStages number of filter stages.
+ * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages.
+ * @param[in] *pState points to the state buffer. The array is of length numStages.
+ * @return none.
+ */
+
+ void arm_fir_lattice_init_q15(
+ arm_fir_lattice_instance_q15 * S,
+ uint16_t numStages,
+ q15_t * pCoeffs,
+ q15_t * pState);
+
+
+ /**
+ * @brief Processing function for the Q15 FIR lattice filter.
+ * @param[in] *S points to an instance of the Q15 FIR lattice structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+ void arm_fir_lattice_q15(
+ const arm_fir_lattice_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the Q31 FIR lattice filter.
+ * @param[in] *S points to an instance of the Q31 FIR lattice structure.
+ * @param[in] numStages number of filter stages.
+ * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages.
+ * @param[in] *pState points to the state buffer. The array is of length numStages.
+ * @return none.
+ */
+
+ void arm_fir_lattice_init_q31(
+ arm_fir_lattice_instance_q31 * S,
+ uint16_t numStages,
+ q31_t * pCoeffs,
+ q31_t * pState);
+
+
+ /**
+ * @brief Processing function for the Q31 FIR lattice filter.
+ * @param[in] *S points to an instance of the Q31 FIR lattice structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_fir_lattice_q31(
+ const arm_fir_lattice_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+/**
+ * @brief Initialization function for the floating-point FIR lattice filter.
+ * @param[in] *S points to an instance of the floating-point FIR lattice structure.
+ * @param[in] numStages number of filter stages.
+ * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages.
+ * @param[in] *pState points to the state buffer. The array is of length numStages.
+ * @return none.
+ */
+
+ void arm_fir_lattice_init_f32(
+ arm_fir_lattice_instance_f32 * S,
+ uint16_t numStages,
+ float32_t * pCoeffs,
+ float32_t * pState);
+
+ /**
+ * @brief Processing function for the floating-point FIR lattice filter.
+ * @param[in] *S points to an instance of the floating-point FIR lattice structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_fir_lattice_f32(
+ const arm_fir_lattice_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Instance structure for the Q15 IIR lattice filter.
+ */
+ typedef struct
+ {
+ uint16_t numStages; /**< number of stages in the filter. */
+ q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */
+ q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */
+ q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */
+ } arm_iir_lattice_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 IIR lattice filter.
+ */
+ typedef struct
+ {
+ uint16_t numStages; /**< number of stages in the filter. */
+ q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */
+ q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */
+ q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */
+ } arm_iir_lattice_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point IIR lattice filter.
+ */
+ typedef struct
+ {
+ uint16_t numStages; /**< number of stages in the filter. */
+ float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */
+ float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */
+ float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */
+ } arm_iir_lattice_instance_f32;
+
+ /**
+ * @brief Processing function for the floating-point IIR lattice filter.
+ * @param[in] *S points to an instance of the floating-point IIR lattice structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_iir_lattice_f32(
+ const arm_iir_lattice_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the floating-point IIR lattice filter.
+ * @param[in] *S points to an instance of the floating-point IIR lattice structure.
+ * @param[in] numStages number of stages in the filter.
+ * @param[in] *pkCoeffs points to the reflection coefficient buffer. The array is of length numStages.
+ * @param[in] *pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1.
+ * @param[in] *pState points to the state buffer. The array is of length numStages+blockSize-1.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_iir_lattice_init_f32(
+ arm_iir_lattice_instance_f32 * S,
+ uint16_t numStages,
+ float32_t * pkCoeffs,
+ float32_t * pvCoeffs,
+ float32_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q31 IIR lattice filter.
+ * @param[in] *S points to an instance of the Q31 IIR lattice structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_iir_lattice_q31(
+ const arm_iir_lattice_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q31 IIR lattice filter.
+ * @param[in] *S points to an instance of the Q31 IIR lattice structure.
+ * @param[in] numStages number of stages in the filter.
+ * @param[in] *pkCoeffs points to the reflection coefficient buffer. The array is of length numStages.
+ * @param[in] *pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1.
+ * @param[in] *pState points to the state buffer. The array is of length numStages+blockSize.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_iir_lattice_init_q31(
+ arm_iir_lattice_instance_q31 * S,
+ uint16_t numStages,
+ q31_t * pkCoeffs,
+ q31_t * pvCoeffs,
+ q31_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q15 IIR lattice filter.
+ * @param[in] *S points to an instance of the Q15 IIR lattice structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_iir_lattice_q15(
+ const arm_iir_lattice_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the Q15 IIR lattice filter.
+ * @param[in] *S points to an instance of the fixed-point Q15 IIR lattice structure.
+ * @param[in] numStages number of stages in the filter.
+ * @param[in] *pkCoeffs points to reflection coefficient buffer. The array is of length numStages.
+ * @param[in] *pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1.
+ * @param[in] *pState points to state buffer. The array is of length numStages+blockSize.
+ * @param[in] blockSize number of samples to process per call.
+ * @return none.
+ */
+
+ void arm_iir_lattice_init_q15(
+ arm_iir_lattice_instance_q15 * S,
+ uint16_t numStages,
+ q15_t * pkCoeffs,
+ q15_t * pvCoeffs,
+ q15_t * pState,
+ uint32_t blockSize);
+
+ /**
+ * @brief Instance structure for the floating-point LMS filter.
+ */
+
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ float32_t mu; /**< step size that controls filter coefficient updates. */
+ } arm_lms_instance_f32;
+
+ /**
+ * @brief Processing function for floating-point LMS filter.
+ * @param[in] *S points to an instance of the floating-point LMS filter structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[in] *pRef points to the block of reference data.
+ * @param[out] *pOut points to the block of output data.
+ * @param[out] *pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_lms_f32(
+ const arm_lms_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pRef,
+ float32_t * pOut,
+ float32_t * pErr,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for floating-point LMS filter.
+ * @param[in] *S points to an instance of the floating-point LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] *pCoeffs points to the coefficient buffer.
+ * @param[in] *pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_lms_init_f32(
+ arm_lms_instance_f32 * S,
+ uint16_t numTaps,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ float32_t mu,
+ uint32_t blockSize);
+
+ /**
+ * @brief Instance structure for the Q15 LMS filter.
+ */
+
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ q15_t mu; /**< step size that controls filter coefficient updates. */
+ uint32_t postShift; /**< bit shift applied to coefficients. */
+ } arm_lms_instance_q15;
+
+
+ /**
+ * @brief Initialization function for the Q15 LMS filter.
+ * @param[in] *S points to an instance of the Q15 LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] *pCoeffs points to the coefficient buffer.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @param[in] postShift bit shift applied to coefficients.
+ * @return none.
+ */
+
+ void arm_lms_init_q15(
+ arm_lms_instance_q15 * S,
+ uint16_t numTaps,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ q15_t mu,
+ uint32_t blockSize,
+ uint32_t postShift);
+
+ /**
+ * @brief Processing function for Q15 LMS filter.
+ * @param[in] *S points to an instance of the Q15 LMS filter structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[in] *pRef points to the block of reference data.
+ * @param[out] *pOut points to the block of output data.
+ * @param[out] *pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_lms_q15(
+ const arm_lms_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pRef,
+ q15_t * pOut,
+ q15_t * pErr,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the Q31 LMS filter.
+ */
+
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ q31_t mu; /**< step size that controls filter coefficient updates. */
+ uint32_t postShift; /**< bit shift applied to coefficients. */
+
+ } arm_lms_instance_q31;
+
+ /**
+ * @brief Processing function for Q31 LMS filter.
+ * @param[in] *S points to an instance of the Q15 LMS filter structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[in] *pRef points to the block of reference data.
+ * @param[out] *pOut points to the block of output data.
+ * @param[out] *pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_lms_q31(
+ const arm_lms_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pRef,
+ q31_t * pOut,
+ q31_t * pErr,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for Q31 LMS filter.
+ * @param[in] *S points to an instance of the Q31 LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] *pCoeffs points to coefficient buffer.
+ * @param[in] *pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @param[in] postShift bit shift applied to coefficients.
+ * @return none.
+ */
+
+ void arm_lms_init_q31(
+ arm_lms_instance_q31 * S,
+ uint16_t numTaps,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ q31_t mu,
+ uint32_t blockSize,
+ uint32_t postShift);
+
+ /**
+ * @brief Instance structure for the floating-point normalized LMS filter.
+ */
+
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ float32_t mu; /**< step size that control filter coefficient updates. */
+ float32_t energy; /**< saves previous frame energy. */
+ float32_t x0; /**< saves previous input sample. */
+ } arm_lms_norm_instance_f32;
+
+ /**
+ * @brief Processing function for floating-point normalized LMS filter.
+ * @param[in] *S points to an instance of the floating-point normalized LMS filter structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[in] *pRef points to the block of reference data.
+ * @param[out] *pOut points to the block of output data.
+ * @param[out] *pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_lms_norm_f32(
+ arm_lms_norm_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pRef,
+ float32_t * pOut,
+ float32_t * pErr,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for floating-point normalized LMS filter.
+ * @param[in] *S points to an instance of the floating-point LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] *pCoeffs points to coefficient buffer.
+ * @param[in] *pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_lms_norm_init_f32(
+ arm_lms_norm_instance_f32 * S,
+ uint16_t numTaps,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ float32_t mu,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the Q31 normalized LMS filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ q31_t mu; /**< step size that controls filter coefficient updates. */
+ uint8_t postShift; /**< bit shift applied to coefficients. */
+ q31_t *recipTable; /**< points to the reciprocal initial value table. */
+ q31_t energy; /**< saves previous frame energy. */
+ q31_t x0; /**< saves previous input sample. */
+ } arm_lms_norm_instance_q31;
+
+ /**
+ * @brief Processing function for Q31 normalized LMS filter.
+ * @param[in] *S points to an instance of the Q31 normalized LMS filter structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[in] *pRef points to the block of reference data.
+ * @param[out] *pOut points to the block of output data.
+ * @param[out] *pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_lms_norm_q31(
+ arm_lms_norm_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pRef,
+ q31_t * pOut,
+ q31_t * pErr,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for Q31 normalized LMS filter.
+ * @param[in] *S points to an instance of the Q31 normalized LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] *pCoeffs points to coefficient buffer.
+ * @param[in] *pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @param[in] postShift bit shift applied to coefficients.
+ * @return none.
+ */
+
+ void arm_lms_norm_init_q31(
+ arm_lms_norm_instance_q31 * S,
+ uint16_t numTaps,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ q31_t mu,
+ uint32_t blockSize,
+ uint8_t postShift);
+
+ /**
+ * @brief Instance structure for the Q15 normalized LMS filter.
+ */
+
+ typedef struct
+ {
+ uint16_t numTaps; /**< Number of coefficients in the filter. */
+ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ q15_t mu; /**< step size that controls filter coefficient updates. */
+ uint8_t postShift; /**< bit shift applied to coefficients. */
+ q15_t *recipTable; /**< Points to the reciprocal initial value table. */
+ q15_t energy; /**< saves previous frame energy. */
+ q15_t x0; /**< saves previous input sample. */
+ } arm_lms_norm_instance_q15;
+
+ /**
+ * @brief Processing function for Q15 normalized LMS filter.
+ * @param[in] *S points to an instance of the Q15 normalized LMS filter structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[in] *pRef points to the block of reference data.
+ * @param[out] *pOut points to the block of output data.
+ * @param[out] *pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_lms_norm_q15(
+ arm_lms_norm_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pRef,
+ q15_t * pOut,
+ q15_t * pErr,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for Q15 normalized LMS filter.
+ * @param[in] *S points to an instance of the Q15 normalized LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] *pCoeffs points to coefficient buffer.
+ * @param[in] *pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @param[in] postShift bit shift applied to coefficients.
+ * @return none.
+ */
+
+ void arm_lms_norm_init_q15(
+ arm_lms_norm_instance_q15 * S,
+ uint16_t numTaps,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ q15_t mu,
+ uint32_t blockSize,
+ uint8_t postShift);
+
+ /**
+ * @brief Correlation of floating-point sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ * @return none.
+ */
+
+ void arm_correlate_f32(
+ float32_t * pSrcA,
+ uint32_t srcALen,
+ float32_t * pSrcB,
+ uint32_t srcBLen,
+ float32_t * pDst);
+
+
+ /**
+ * @brief Correlation of Q15 sequences
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ * @param[in] *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @return none.
+ */
+ void arm_correlate_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ q15_t * pScratch);
+
+
+ /**
+ * @brief Correlation of Q15 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ * @return none.
+ */
+
+ void arm_correlate_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst);
+
+ /**
+ * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ * @return none.
+ */
+
+ void arm_correlate_fast_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst);
+
+
+
+ /**
+ * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ * @param[in] *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @return none.
+ */
+
+ void arm_correlate_fast_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ q15_t * pScratch);
+
+ /**
+ * @brief Correlation of Q31 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ * @return none.
+ */
+
+ void arm_correlate_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst);
+
+ /**
+ * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ * @return none.
+ */
+
+ void arm_correlate_fast_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst);
+
+
+
+ /**
+ * @brief Correlation of Q7 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ * @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+ * @return none.
+ */
+
+ void arm_correlate_opt_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+ /**
+ * @brief Correlation of Q7 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ * @return none.
+ */
+
+ void arm_correlate_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst);
+
+
+ /**
+ * @brief Instance structure for the floating-point sparse FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */
+ float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */
+ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */
+ } arm_fir_sparse_instance_f32;
+
+ /**
+ * @brief Instance structure for the Q31 sparse FIR filter.
+ */
+
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */
+ q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */
+ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */
+ } arm_fir_sparse_instance_q31;
+
+ /**
+ * @brief Instance structure for the Q15 sparse FIR filter.
+ */
+
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */
+ q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */
+ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */
+ } arm_fir_sparse_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q7 sparse FIR filter.
+ */
+
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */
+ q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+ q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */
+ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */
+ } arm_fir_sparse_instance_q7;
+
+ /**
+ * @brief Processing function for the floating-point sparse FIR filter.
+ * @param[in] *S points to an instance of the floating-point sparse FIR structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] *pScratchIn points to a temporary buffer of size blockSize.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none.
+ */
+
+ void arm_fir_sparse_f32(
+ arm_fir_sparse_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ float32_t * pScratchIn,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the floating-point sparse FIR filter.
+ * @param[in,out] *S points to an instance of the floating-point sparse FIR structure.
+ * @param[in] numTaps number of nonzero coefficients in the filter.
+ * @param[in] *pCoeffs points to the array of filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] *pTapDelay points to the array of offset times.
+ * @param[in] maxDelay maximum offset time supported.
+ * @param[in] blockSize number of samples that will be processed per block.
+ * @return none
+ */
+
+ void arm_fir_sparse_init_f32(
+ arm_fir_sparse_instance_f32 * S,
+ uint16_t numTaps,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ int32_t * pTapDelay,
+ uint16_t maxDelay,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the Q31 sparse FIR filter.
+ * @param[in] *S points to an instance of the Q31 sparse FIR structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] *pScratchIn points to a temporary buffer of size blockSize.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none.
+ */
+
+ void arm_fir_sparse_q31(
+ arm_fir_sparse_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ q31_t * pScratchIn,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the Q31 sparse FIR filter.
+ * @param[in,out] *S points to an instance of the Q31 sparse FIR structure.
+ * @param[in] numTaps number of nonzero coefficients in the filter.
+ * @param[in] *pCoeffs points to the array of filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] *pTapDelay points to the array of offset times.
+ * @param[in] maxDelay maximum offset time supported.
+ * @param[in] blockSize number of samples that will be processed per block.
+ * @return none
+ */
+
+ void arm_fir_sparse_init_q31(
+ arm_fir_sparse_instance_q31 * S,
+ uint16_t numTaps,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ int32_t * pTapDelay,
+ uint16_t maxDelay,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the Q15 sparse FIR filter.
+ * @param[in] *S points to an instance of the Q15 sparse FIR structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] *pScratchIn points to a temporary buffer of size blockSize.
+ * @param[in] *pScratchOut points to a temporary buffer of size blockSize.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none.
+ */
+
+ void arm_fir_sparse_q15(
+ arm_fir_sparse_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ q15_t * pScratchIn,
+ q31_t * pScratchOut,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q15 sparse FIR filter.
+ * @param[in,out] *S points to an instance of the Q15 sparse FIR structure.
+ * @param[in] numTaps number of nonzero coefficients in the filter.
+ * @param[in] *pCoeffs points to the array of filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] *pTapDelay points to the array of offset times.
+ * @param[in] maxDelay maximum offset time supported.
+ * @param[in] blockSize number of samples that will be processed per block.
+ * @return none
+ */
+
+ void arm_fir_sparse_init_q15(
+ arm_fir_sparse_instance_q15 * S,
+ uint16_t numTaps,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ int32_t * pTapDelay,
+ uint16_t maxDelay,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the Q7 sparse FIR filter.
+ * @param[in] *S points to an instance of the Q7 sparse FIR structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] *pScratchIn points to a temporary buffer of size blockSize.
+ * @param[in] *pScratchOut points to a temporary buffer of size blockSize.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none.
+ */
+
+ void arm_fir_sparse_q7(
+ arm_fir_sparse_instance_q7 * S,
+ q7_t * pSrc,
+ q7_t * pDst,
+ q7_t * pScratchIn,
+ q31_t * pScratchOut,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the Q7 sparse FIR filter.
+ * @param[in,out] *S points to an instance of the Q7 sparse FIR structure.
+ * @param[in] numTaps number of nonzero coefficients in the filter.
+ * @param[in] *pCoeffs points to the array of filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] *pTapDelay points to the array of offset times.
+ * @param[in] maxDelay maximum offset time supported.
+ * @param[in] blockSize number of samples that will be processed per block.
+ * @return none
+ */
+
+ void arm_fir_sparse_init_q7(
+ arm_fir_sparse_instance_q7 * S,
+ uint16_t numTaps,
+ q7_t * pCoeffs,
+ q7_t * pState,
+ int32_t * pTapDelay,
+ uint16_t maxDelay,
+ uint32_t blockSize);
+
+
+ /*
+ * @brief Floating-point sin_cos function.
+ * @param[in] theta input value in degrees
+ * @param[out] *pSinVal points to the processed sine output.
+ * @param[out] *pCosVal points to the processed cos output.
+ * @return none.
+ */
+
+ void arm_sin_cos_f32(
+ float32_t theta,
+ float32_t * pSinVal,
+ float32_t * pCcosVal);
+
+ /*
+ * @brief Q31 sin_cos function.
+ * @param[in] theta scaled input value in degrees
+ * @param[out] *pSinVal points to the processed sine output.
+ * @param[out] *pCosVal points to the processed cosine output.
+ * @return none.
+ */
+
+ void arm_sin_cos_q31(
+ q31_t theta,
+ q31_t * pSinVal,
+ q31_t * pCosVal);
+
+
+ /**
+ * @brief Floating-point complex conjugate.
+ * @param[in] *pSrc points to the input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @return none.
+ */
+
+ void arm_cmplx_conj_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t numSamples);
+
+ /**
+ * @brief Q31 complex conjugate.
+ * @param[in] *pSrc points to the input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @return none.
+ */
+
+ void arm_cmplx_conj_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t numSamples);
+
+ /**
+ * @brief Q15 complex conjugate.
+ * @param[in] *pSrc points to the input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @return none.
+ */
+
+ void arm_cmplx_conj_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t numSamples);
+
+
+
+ /**
+ * @brief Floating-point complex magnitude squared
+ * @param[in] *pSrc points to the complex input vector
+ * @param[out] *pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ * @return none.
+ */
+
+ void arm_cmplx_mag_squared_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t numSamples);
+
+ /**
+ * @brief Q31 complex magnitude squared
+ * @param[in] *pSrc points to the complex input vector
+ * @param[out] *pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ * @return none.
+ */
+
+ void arm_cmplx_mag_squared_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t numSamples);
+
+ /**
+ * @brief Q15 complex magnitude squared
+ * @param[in] *pSrc points to the complex input vector
+ * @param[out] *pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ * @return none.
+ */
+
+ void arm_cmplx_mag_squared_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @ingroup groupController
+ */
+
+ /**
+ * @defgroup PID PID Motor Control
+ *
+ * A Proportional Integral Derivative (PID) controller is a generic feedback control
+ * loop mechanism widely used in industrial control systems.
+ * A PID controller is the most commonly used type of feedback controller.
+ *
+ * This set of functions implements (PID) controllers
+ * for Q15, Q31, and floating-point data types. The functions operate on a single sample
+ * of data and each call to the function returns a single processed value.
+ * S points to an instance of the PID control data structure. in
+ * is the input sample value. The functions return the output value.
+ *
+ * \par Algorithm:
+ *
+ * y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
+ * A0 = Kp + Ki + Kd
+ * A1 = (-Kp ) - (2 * Kd )
+ * A2 = Kd
+ *
+ * \par
+ * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant
+ *
+ * \par
+ * \image html PID.gif "Proportional Integral Derivative Controller"
+ *
+ * \par
+ * The PID controller calculates an "error" value as the difference between
+ * the measured output and the reference input.
+ * The controller attempts to minimize the error by adjusting the process control inputs.
+ * The proportional value determines the reaction to the current error,
+ * the integral value determines the reaction based on the sum of recent errors,
+ * and the derivative value determines the reaction based on the rate at which the error has been changing.
+ *
+ * \par Instance Structure
+ * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure.
+ * A separate instance structure must be defined for each PID Controller.
+ * There are separate instance structure declarations for each of the 3 supported data types.
+ *
+ * \par Reset Functions
+ * There is also an associated reset function for each data type which clears the state array.
+ *
+ * \par Initialization Functions
+ * There is also an associated initialization function for each data type.
+ * The initialization function performs the following operations:
+ * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains.
+ * - Zeros out the values in the state buffer.
+ *
+ * \par
+ * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function.
+ *
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the fixed-point versions of the PID Controller functions.
+ * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+ /**
+ * @addtogroup PID
+ * @{
+ */
+
+ /**
+ * @brief Process function for the floating-point PID Control.
+ * @param[in,out] *S is an instance of the floating-point PID Control structure
+ * @param[in] in input sample to process
+ * @return out processed output sample.
+ */
+
+
+ __STATIC_INLINE float32_t arm_pid_f32(
+ arm_pid_instance_f32 * S,
+ float32_t in)
+ {
+ float32_t out;
+
+ /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */
+ out = (S->A0 * in) +
+ (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]);
+
+ /* Update state */
+ S->state[1] = S->state[0];
+ S->state[0] = in;
+ S->state[2] = out;
+
+ /* return to application */
+ return (out);
+
+ }
+
+ /**
+ * @brief Process function for the Q31 PID Control.
+ * @param[in,out] *S points to an instance of the Q31 PID Control structure
+ * @param[in] in input sample to process
+ * @return out processed output sample.
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function is implemented using an internal 64-bit accumulator.
+ * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.
+ * Thus, if the accumulator result overflows it wraps around rather than clip.
+ * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions.
+ * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format.
+ */
+
+ __STATIC_INLINE q31_t arm_pid_q31(
+ arm_pid_instance_q31 * S,
+ q31_t in)
+ {
+ q63_t acc;
+ q31_t out;
+
+ /* acc = A0 * x[n] */
+ acc = (q63_t) S->A0 * in;
+
+ /* acc += A1 * x[n-1] */
+ acc += (q63_t) S->A1 * S->state[0];
+
+ /* acc += A2 * x[n-2] */
+ acc += (q63_t) S->A2 * S->state[1];
+
+ /* convert output to 1.31 format to add y[n-1] */
+ out = (q31_t) (acc >> 31u);
+
+ /* out += y[n-1] */
+ out += S->state[2];
+
+ /* Update state */
+ S->state[1] = S->state[0];
+ S->state[0] = in;
+ S->state[2] = out;
+
+ /* return to application */
+ return (out);
+
+ }
+
+ /**
+ * @brief Process function for the Q15 PID Control.
+ * @param[in,out] *S points to an instance of the Q15 PID Control structure
+ * @param[in] in input sample to process
+ * @return out processed output sample.
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function is implemented using a 64-bit internal accumulator.
+ * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result.
+ * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.
+ * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.
+ * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.
+ * Lastly, the accumulator is saturated to yield a result in 1.15 format.
+ */
+
+ __STATIC_INLINE q15_t arm_pid_q15(
+ arm_pid_instance_q15 * S,
+ q15_t in)
+ {
+ q63_t acc;
+ q15_t out;
+
+ /* Implementation of PID controller */
+
+#ifdef ARM_MATH_CM0
+
+ /* acc = A0 * x[n] */
+ acc = ((q31_t) S->A0) * in;
+
+#else
+
+ /* acc = A0 * x[n] */
+ acc = (q31_t) __SMUAD(S->A0, in);
+
+#endif
+
+#ifdef ARM_MATH_CM0
+
+ /* acc += A1 * x[n-1] + A2 * x[n-2] */
+ acc += (q31_t) S->A1 * S->state[0];
+ acc += (q31_t) S->A2 * S->state[1];
+
+#else
+
+ /* acc += A1 * x[n-1] + A2 * x[n-2] */
+ acc = __SMLALD(S->A1, (q31_t) __SIMD32(S->state), acc);
+
+#endif
+
+ /* acc += y[n-1] */
+ acc += (q31_t) S->state[2] << 15;
+
+ /* saturate the output */
+ out = (q15_t) (__SSAT((acc >> 15), 16));
+
+ /* Update state */
+ S->state[1] = S->state[0];
+ S->state[0] = in;
+ S->state[2] = out;
+
+ /* return to application */
+ return (out);
+
+ }
+
+ /**
+ * @} end of PID group
+ */
+
+
+ /**
+ * @brief Floating-point matrix inverse.
+ * @param[in] *src points to the instance of the input floating-point matrix structure.
+ * @param[out] *dst points to the instance of the output floating-point matrix structure.
+ * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
+ * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.
+ */
+
+ arm_status arm_mat_inverse_f32(
+ const arm_matrix_instance_f32 * src,
+ arm_matrix_instance_f32 * dst);
+
+
+
+ /**
+ * @ingroup groupController
+ */
+
+
+ /**
+ * @defgroup clarke Vector Clarke Transform
+ * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector.
+ * Generally the Clarke transform uses three-phase currents Ia, Ib and Ic to calculate currents
+ * in the two-phase orthogonal stator axis Ialpha and Ibeta.
+ * When Ialpha is superposed with Ia as shown in the figure below
+ * \image html clarke.gif Stator current space vector and its components in (a,b).
+ * and Ia + Ib + Ic = 0, in this condition Ialpha and Ibeta
+ * can be calculated using only Ia and Ib.
+ *
+ * The function operates on a single sample of data and each call to the function returns the processed output.
+ * The library provides separate functions for Q31 and floating-point data types.
+ * \par Algorithm
+ * \image html clarkeFormula.gif
+ * where Ia and Ib are the instantaneous stator phases and
+ * pIalpha and pIbeta are the two coordinates of time invariant vector.
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the Q31 version of the Clarke transform.
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+ /**
+ * @addtogroup clarke
+ * @{
+ */
+
+ /**
+ *
+ * @brief Floating-point Clarke transform
+ * @param[in] Ia input three-phase coordinate a
+ * @param[in] Ib input three-phase coordinate b
+ * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha
+ * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta
+ * @return none.
+ */
+
+ __STATIC_INLINE void arm_clarke_f32(
+ float32_t Ia,
+ float32_t Ib,
+ float32_t * pIalpha,
+ float32_t * pIbeta)
+ {
+ /* Calculate pIalpha using the equation, pIalpha = Ia */
+ *pIalpha = Ia;
+
+ /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */
+ *pIbeta =
+ ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib);
+
+ }
+
+ /**
+ * @brief Clarke transform for Q31 version
+ * @param[in] Ia input three-phase coordinate a
+ * @param[in] Ib input three-phase coordinate b
+ * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha
+ * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta
+ * @return none.
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function is implemented using an internal 32-bit accumulator.
+ * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+ * There is saturation on the addition, hence there is no risk of overflow.
+ */
+
+ __STATIC_INLINE void arm_clarke_q31(
+ q31_t Ia,
+ q31_t Ib,
+ q31_t * pIalpha,
+ q31_t * pIbeta)
+ {
+ q31_t product1, product2; /* Temporary variables used to store intermediate results */
+
+ /* Calculating pIalpha from Ia by equation pIalpha = Ia */
+ *pIalpha = Ia;
+
+ /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */
+ product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30);
+
+ /* Intermediate product is calculated by (2/sqrt(3) * Ib) */
+ product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30);
+
+ /* pIbeta is calculated by adding the intermediate products */
+ *pIbeta = __QADD(product1, product2);
+ }
+
+ /**
+ * @} end of clarke group
+ */
+
+ /**
+ * @brief Converts the elements of the Q7 vector to Q31 vector.
+ * @param[in] *pSrc input pointer
+ * @param[out] *pDst output pointer
+ * @param[in] blockSize number of samples to process
+ * @return none.
+ */
+ void arm_q7_to_q31(
+ q7_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+
+
+ /**
+ * @ingroup groupController
+ */
+
+ /**
+ * @defgroup inv_clarke Vector Inverse Clarke Transform
+ * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases.
+ *
+ * The function operates on a single sample of data and each call to the function returns the processed output.
+ * The library provides separate functions for Q31 and floating-point data types.
+ * \par Algorithm
+ * \image html clarkeInvFormula.gif
+ * where pIa and pIb are the instantaneous stator phases and
+ * Ialpha and Ibeta are the two coordinates of time invariant vector.
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the Q31 version of the Clarke transform.
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+ /**
+ * @addtogroup inv_clarke
+ * @{
+ */
+
+ /**
+ * @brief Floating-point Inverse Clarke transform
+ * @param[in] Ialpha input two-phase orthogonal vector axis alpha
+ * @param[in] Ibeta input two-phase orthogonal vector axis beta
+ * @param[out] *pIa points to output three-phase coordinate a
+ * @param[out] *pIb points to output three-phase coordinate b
+ * @return none.
+ */
+
+
+ __STATIC_INLINE void arm_inv_clarke_f32(
+ float32_t Ialpha,
+ float32_t Ibeta,
+ float32_t * pIa,
+ float32_t * pIb)
+ {
+ /* Calculating pIa from Ialpha by equation pIa = Ialpha */
+ *pIa = Ialpha;
+
+ /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */
+ *pIb = -0.5 * Ialpha + (float32_t) 0.8660254039 *Ibeta;
+
+ }
+
+ /**
+ * @brief Inverse Clarke transform for Q31 version
+ * @param[in] Ialpha input two-phase orthogonal vector axis alpha
+ * @param[in] Ibeta input two-phase orthogonal vector axis beta
+ * @param[out] *pIa points to output three-phase coordinate a
+ * @param[out] *pIb points to output three-phase coordinate b
+ * @return none.
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function is implemented using an internal 32-bit accumulator.
+ * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+ * There is saturation on the subtraction, hence there is no risk of overflow.
+ */
+
+ __STATIC_INLINE void arm_inv_clarke_q31(
+ q31_t Ialpha,
+ q31_t Ibeta,
+ q31_t * pIa,
+ q31_t * pIb)
+ {
+ q31_t product1, product2; /* Temporary variables used to store intermediate results */
+
+ /* Calculating pIa from Ialpha by equation pIa = Ialpha */
+ *pIa = Ialpha;
+
+ /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */
+ product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31);
+
+ /* Intermediate product is calculated by (1/sqrt(3) * pIb) */
+ product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31);
+
+ /* pIb is calculated by subtracting the products */
+ *pIb = __QSUB(product2, product1);
+
+ }
+
+ /**
+ * @} end of inv_clarke group
+ */
+
+ /**
+ * @brief Converts the elements of the Q7 vector to Q15 vector.
+ * @param[in] *pSrc input pointer
+ * @param[out] *pDst output pointer
+ * @param[in] blockSize number of samples to process
+ * @return none.
+ */
+ void arm_q7_to_q15(
+ q7_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+
+ /**
+ * @ingroup groupController
+ */
+
+ /**
+ * @defgroup park Vector Park Transform
+ *
+ * Forward Park transform converts the input two-coordinate vector to flux and torque components.
+ * The Park transform can be used to realize the transformation of the Ialpha and the Ibeta currents
+ * from the stationary to the moving reference frame and control the spatial relationship between
+ * the stator vector current and rotor flux vector.
+ * If we consider the d axis aligned with the rotor flux, the diagram below shows the
+ * current vector and the relationship from the two reference frames:
+ * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame"
+ *
+ * The function operates on a single sample of data and each call to the function returns the processed output.
+ * The library provides separate functions for Q31 and floating-point data types.
+ * \par Algorithm
+ * \image html parkFormula.gif
+ * where Ialpha and Ibeta are the stator vector components,
+ * pId and pIq are rotor vector components and cosVal and sinVal are the
+ * cosine and sine values of theta (rotor flux position).
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the Q31 version of the Park transform.
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+ /**
+ * @addtogroup park
+ * @{
+ */
+
+ /**
+ * @brief Floating-point Park transform
+ * @param[in] Ialpha input two-phase vector coordinate alpha
+ * @param[in] Ibeta input two-phase vector coordinate beta
+ * @param[out] *pId points to output rotor reference frame d
+ * @param[out] *pIq points to output rotor reference frame q
+ * @param[in] sinVal sine value of rotation angle theta
+ * @param[in] cosVal cosine value of rotation angle theta
+ * @return none.
+ *
+ * The function implements the forward Park transform.
+ *
+ */
+
+ __STATIC_INLINE void arm_park_f32(
+ float32_t Ialpha,
+ float32_t Ibeta,
+ float32_t * pId,
+ float32_t * pIq,
+ float32_t sinVal,
+ float32_t cosVal)
+ {
+ /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */
+ *pId = Ialpha * cosVal + Ibeta * sinVal;
+
+ /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */
+ *pIq = -Ialpha * sinVal + Ibeta * cosVal;
+
+ }
+
+ /**
+ * @brief Park transform for Q31 version
+ * @param[in] Ialpha input two-phase vector coordinate alpha
+ * @param[in] Ibeta input two-phase vector coordinate beta
+ * @param[out] *pId points to output rotor reference frame d
+ * @param[out] *pIq points to output rotor reference frame q
+ * @param[in] sinVal sine value of rotation angle theta
+ * @param[in] cosVal cosine value of rotation angle theta
+ * @return none.
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function is implemented using an internal 32-bit accumulator.
+ * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+ * There is saturation on the addition and subtraction, hence there is no risk of overflow.
+ */
+
+
+ __STATIC_INLINE void arm_park_q31(
+ q31_t Ialpha,
+ q31_t Ibeta,
+ q31_t * pId,
+ q31_t * pIq,
+ q31_t sinVal,
+ q31_t cosVal)
+ {
+ q31_t product1, product2; /* Temporary variables used to store intermediate results */
+ q31_t product3, product4; /* Temporary variables used to store intermediate results */
+
+ /* Intermediate product is calculated by (Ialpha * cosVal) */
+ product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31);
+
+ /* Intermediate product is calculated by (Ibeta * sinVal) */
+ product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31);
+
+
+ /* Intermediate product is calculated by (Ialpha * sinVal) */
+ product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31);
+
+ /* Intermediate product is calculated by (Ibeta * cosVal) */
+ product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31);
+
+ /* Calculate pId by adding the two intermediate products 1 and 2 */
+ *pId = __QADD(product1, product2);
+
+ /* Calculate pIq by subtracting the two intermediate products 3 from 4 */
+ *pIq = __QSUB(product4, product3);
+ }
+
+ /**
+ * @} end of park group
+ */
+
+ /**
+ * @brief Converts the elements of the Q7 vector to floating-point vector.
+ * @param[in] *pSrc is input pointer
+ * @param[out] *pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ * @return none.
+ */
+ void arm_q7_to_float(
+ q7_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @ingroup groupController
+ */
+
+ /**
+ * @defgroup inv_park Vector Inverse Park transform
+ * Inverse Park transform converts the input flux and torque components to two-coordinate vector.
+ *
+ * The function operates on a single sample of data and each call to the function returns the processed output.
+ * The library provides separate functions for Q31 and floating-point data types.
+ * \par Algorithm
+ * \image html parkInvFormula.gif
+ * where pIalpha and pIbeta are the stator vector components,
+ * Id and Iq are rotor vector components and cosVal and sinVal are the
+ * cosine and sine values of theta (rotor flux position).
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the Q31 version of the Park transform.
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+ /**
+ * @addtogroup inv_park
+ * @{
+ */
+
+ /**
+ * @brief Floating-point Inverse Park transform
+ * @param[in] Id input coordinate of rotor reference frame d
+ * @param[in] Iq input coordinate of rotor reference frame q
+ * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha
+ * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta
+ * @param[in] sinVal sine value of rotation angle theta
+ * @param[in] cosVal cosine value of rotation angle theta
+ * @return none.
+ */
+
+ __STATIC_INLINE void arm_inv_park_f32(
+ float32_t Id,
+ float32_t Iq,
+ float32_t * pIalpha,
+ float32_t * pIbeta,
+ float32_t sinVal,
+ float32_t cosVal)
+ {
+ /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */
+ *pIalpha = Id * cosVal - Iq * sinVal;
+
+ /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */
+ *pIbeta = Id * sinVal + Iq * cosVal;
+
+ }
+
+
+ /**
+ * @brief Inverse Park transform for Q31 version
+ * @param[in] Id input coordinate of rotor reference frame d
+ * @param[in] Iq input coordinate of rotor reference frame q
+ * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha
+ * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta
+ * @param[in] sinVal sine value of rotation angle theta
+ * @param[in] cosVal cosine value of rotation angle theta
+ * @return none.
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function is implemented using an internal 32-bit accumulator.
+ * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+ * There is saturation on the addition, hence there is no risk of overflow.
+ */
+
+
+ __STATIC_INLINE void arm_inv_park_q31(
+ q31_t Id,
+ q31_t Iq,
+ q31_t * pIalpha,
+ q31_t * pIbeta,
+ q31_t sinVal,
+ q31_t cosVal)
+ {
+ q31_t product1, product2; /* Temporary variables used to store intermediate results */
+ q31_t product3, product4; /* Temporary variables used to store intermediate results */
+
+ /* Intermediate product is calculated by (Id * cosVal) */
+ product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31);
+
+ /* Intermediate product is calculated by (Iq * sinVal) */
+ product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31);
+
+
+ /* Intermediate product is calculated by (Id * sinVal) */
+ product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31);
+
+ /* Intermediate product is calculated by (Iq * cosVal) */
+ product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31);
+
+ /* Calculate pIalpha by using the two intermediate products 1 and 2 */
+ *pIalpha = __QSUB(product1, product2);
+
+ /* Calculate pIbeta by using the two intermediate products 3 and 4 */
+ *pIbeta = __QADD(product4, product3);
+
+ }
+
+ /**
+ * @} end of Inverse park group
+ */
+
+
+ /**
+ * @brief Converts the elements of the Q31 vector to floating-point vector.
+ * @param[in] *pSrc is input pointer
+ * @param[out] *pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ * @return none.
+ */
+ void arm_q31_to_float(
+ q31_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @ingroup groupInterpolation
+ */
+
+ /**
+ * @defgroup LinearInterpolate Linear Interpolation
+ *
+ * Linear interpolation is a method of curve fitting using linear polynomials.
+ * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line
+ *
+ * \par
+ * \image html LinearInterp.gif "Linear interpolation"
+ *
+ * \par
+ * A Linear Interpolate function calculates an output value(y), for the input(x)
+ * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values)
+ *
+ * \par Algorithm:
+ *
+ * y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
+ * where x0, x1 are nearest values of input x
+ * y0, y1 are nearest values to output y
+ *
+ *
+ * \par
+ * This set of functions implements Linear interpolation process
+ * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single
+ * sample of data and each call to the function returns a single processed value.
+ * S points to an instance of the Linear Interpolate function data structure.
+ * x is the input sample value. The functions returns the output value.
+ *
+ * \par
+ * if x is outside of the table boundary, Linear interpolation returns first value of the table
+ * if x is below input range and returns last value of table if x is above range.
+ */
+
+ /**
+ * @addtogroup LinearInterpolate
+ * @{
+ */
+
+ /**
+ * @brief Process function for the floating-point Linear Interpolation Function.
+ * @param[in,out] *S is an instance of the floating-point Linear Interpolation structure
+ * @param[in] x input sample to process
+ * @return y processed output sample.
+ *
+ */
+
+ __STATIC_INLINE float32_t arm_linear_interp_f32(
+ arm_linear_interp_instance_f32 * S,
+ float32_t x)
+ {
+
+ float32_t y;
+ float32_t x0, x1; /* Nearest input values */
+ float32_t y0, y1; /* Nearest output values */
+ float32_t xSpacing = S->xSpacing; /* spacing between input values */
+ int32_t i; /* Index variable */
+ float32_t *pYData = S->pYData; /* pointer to output table */
+
+ /* Calculation of index */
+ i = (x - S->x1) / xSpacing;
+
+ if(i < 0)
+ {
+ /* Iniatilize output for below specified range as least output value of table */
+ y = pYData[0];
+ }
+ else if(i >= S->nValues)
+ {
+ /* Iniatilize output for above specified range as last output value of table */
+ y = pYData[S->nValues - 1];
+ }
+ else
+ {
+ /* Calculation of nearest input values */
+ x0 = S->x1 + i * xSpacing;
+ x1 = S->x1 + (i + 1) * xSpacing;
+
+ /* Read of nearest output values */
+ y0 = pYData[i];
+ y1 = pYData[i + 1];
+
+ /* Calculation of output */
+ y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0));
+
+ }
+
+ /* returns output value */
+ return (y);
+ }
+
+ /**
+ *
+ * @brief Process function for the Q31 Linear Interpolation Function.
+ * @param[in] *pYData pointer to Q31 Linear Interpolation table
+ * @param[in] x input sample to process
+ * @param[in] nValues number of table values
+ * @return y processed output sample.
+ *
+ * \par
+ * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+ * This function can support maximum of table size 2^12.
+ *
+ */
+
+
+ __STATIC_INLINE q31_t arm_linear_interp_q31(
+ q31_t * pYData,
+ q31_t x,
+ uint32_t nValues)
+ {
+ q31_t y; /* output */
+ q31_t y0, y1; /* Nearest output values */
+ q31_t fract; /* fractional part */
+ int32_t index; /* Index to read nearest output values */
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ index = ((x & 0xFFF00000) >> 20);
+
+ if(index >= (nValues - 1))
+ {
+ return (pYData[nValues - 1]);
+ }
+ else if(index < 0)
+ {
+ return (pYData[0]);
+ }
+ else
+ {
+
+ /* 20 bits for the fractional part */
+ /* shift left by 11 to keep fract in 1.31 format */
+ fract = (x & 0x000FFFFF) << 11;
+
+ /* Read two nearest output values from the index in 1.31(q31) format */
+ y0 = pYData[index];
+ y1 = pYData[index + 1u];
+
+ /* Calculation of y0 * (1-fract) and y is in 2.30 format */
+ y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32));
+
+ /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */
+ y += ((q31_t) (((q63_t) y1 * fract) >> 32));
+
+ /* Convert y to 1.31 format */
+ return (y << 1u);
+
+ }
+
+ }
+
+ /**
+ *
+ * @brief Process function for the Q15 Linear Interpolation Function.
+ * @param[in] *pYData pointer to Q15 Linear Interpolation table
+ * @param[in] x input sample to process
+ * @param[in] nValues number of table values
+ * @return y processed output sample.
+ *
+ * \par
+ * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+ * This function can support maximum of table size 2^12.
+ *
+ */
+
+
+ __STATIC_INLINE q15_t arm_linear_interp_q15(
+ q15_t * pYData,
+ q31_t x,
+ uint32_t nValues)
+ {
+ q63_t y; /* output */
+ q15_t y0, y1; /* Nearest output values */
+ q31_t fract; /* fractional part */
+ int32_t index; /* Index to read nearest output values */
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ index = ((x & 0xFFF00000) >> 20u);
+
+ if(index >= (nValues - 1))
+ {
+ return (pYData[nValues - 1]);
+ }
+ else if(index < 0)
+ {
+ return (pYData[0]);
+ }
+ else
+ {
+ /* 20 bits for the fractional part */
+ /* fract is in 12.20 format */
+ fract = (x & 0x000FFFFF);
+
+ /* Read two nearest output values from the index */
+ y0 = pYData[index];
+ y1 = pYData[index + 1u];
+
+ /* Calculation of y0 * (1-fract) and y is in 13.35 format */
+ y = ((q63_t) y0 * (0xFFFFF - fract));
+
+ /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */
+ y += ((q63_t) y1 * (fract));
+
+ /* convert y to 1.15 format */
+ return (y >> 20);
+ }
+
+
+ }
+
+ /**
+ *
+ * @brief Process function for the Q7 Linear Interpolation Function.
+ * @param[in] *pYData pointer to Q7 Linear Interpolation table
+ * @param[in] x input sample to process
+ * @param[in] nValues number of table values
+ * @return y processed output sample.
+ *
+ * \par
+ * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+ * This function can support maximum of table size 2^12.
+ */
+
+
+ __STATIC_INLINE q7_t arm_linear_interp_q7(
+ q7_t * pYData,
+ q31_t x,
+ uint32_t nValues)
+ {
+ q31_t y; /* output */
+ q7_t y0, y1; /* Nearest output values */
+ q31_t fract; /* fractional part */
+ int32_t index; /* Index to read nearest output values */
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ index = ((x & 0xFFF00000) >> 20u);
+
+
+ if(index >= (nValues - 1))
+ {
+ return (pYData[nValues - 1]);
+ }
+ else if(index < 0)
+ {
+ return (pYData[0]);
+ }
+ else
+ {
+
+ /* 20 bits for the fractional part */
+ /* fract is in 12.20 format */
+ fract = (x & 0x000FFFFF);
+
+ /* Read two nearest output values from the index and are in 1.7(q7) format */
+ y0 = pYData[index];
+ y1 = pYData[index + 1u];
+
+ /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */
+ y = ((y0 * (0xFFFFF - fract)));
+
+ /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */
+ y += (y1 * fract);
+
+ /* convert y to 1.7(q7) format */
+ return (y >> 20u);
+
+ }
+
+ }
+ /**
+ * @} end of LinearInterpolate group
+ */
+
+ /**
+ * @brief Fast approximation to the trigonometric sine function for floating-point data.
+ * @param[in] x input value in radians.
+ * @return sin(x).
+ */
+
+ float32_t arm_sin_f32(
+ float32_t x);
+
+ /**
+ * @brief Fast approximation to the trigonometric sine function for Q31 data.
+ * @param[in] x Scaled input value in radians.
+ * @return sin(x).
+ */
+
+ q31_t arm_sin_q31(
+ q31_t x);
+
+ /**
+ * @brief Fast approximation to the trigonometric sine function for Q15 data.
+ * @param[in] x Scaled input value in radians.
+ * @return sin(x).
+ */
+
+ q15_t arm_sin_q15(
+ q15_t x);
+
+ /**
+ * @brief Fast approximation to the trigonometric cosine function for floating-point data.
+ * @param[in] x input value in radians.
+ * @return cos(x).
+ */
+
+ float32_t arm_cos_f32(
+ float32_t x);
+
+ /**
+ * @brief Fast approximation to the trigonometric cosine function for Q31 data.
+ * @param[in] x Scaled input value in radians.
+ * @return cos(x).
+ */
+
+ q31_t arm_cos_q31(
+ q31_t x);
+
+ /**
+ * @brief Fast approximation to the trigonometric cosine function for Q15 data.
+ * @param[in] x Scaled input value in radians.
+ * @return cos(x).
+ */
+
+ q15_t arm_cos_q15(
+ q15_t x);
+
+
+ /**
+ * @ingroup groupFastMath
+ */
+
+
+ /**
+ * @defgroup SQRT Square Root
+ *
+ * Computes the square root of a number.
+ * There are separate functions for Q15, Q31, and floating-point data types.
+ * The square root function is computed using the Newton-Raphson algorithm.
+ * This is an iterative algorithm of the form:
+ *
+ * x1 = x0 - f(x0)/f'(x0)
+ *
+ * where x1 is the current estimate,
+ * x0 is the previous estimate and
+ * f'(x0) is the derivative of f() evaluated at x0.
+ * For the square root function, the algorithm reduces to:
+ *
+ * x0 = in/2 [initial guess]
+ * x1 = 1/2 * ( x0 + in / x0) [each iteration]
+ *
+ */
+
+
+ /**
+ * @addtogroup SQRT
+ * @{
+ */
+
+ /**
+ * @brief Floating-point square root function.
+ * @param[in] in input value.
+ * @param[out] *pOut square root of input value.
+ * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+ * in is negative value and returns zero output for negative values.
+ */
+
+ __STATIC_INLINE arm_status arm_sqrt_f32(
+ float32_t in,
+ float32_t * pOut)
+ {
+ if(in > 0)
+ {
+
+// #if __FPU_USED
+ #if (__FPU_USED == 1) && defined ( __CC_ARM )
+ *pOut = __sqrtf(in);
+ #elif (__FPU_USED == 1) && defined ( __TMS_740 )
+ *pOut = __builtin_sqrtf(in);
+ #else
+ *pOut = sqrtf(in);
+ #endif
+
+ return (ARM_MATH_SUCCESS);
+ }
+ else
+ {
+ *pOut = 0.0f;
+ return (ARM_MATH_ARGUMENT_ERROR);
+ }
+
+ }
+
+
+ /**
+ * @brief Q31 square root function.
+ * @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF.
+ * @param[out] *pOut square root of input value.
+ * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+ * in is negative value and returns zero output for negative values.
+ */
+ arm_status arm_sqrt_q31(
+ q31_t in,
+ q31_t * pOut);
+
+ /**
+ * @brief Q15 square root function.
+ * @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF.
+ * @param[out] *pOut square root of input value.
+ * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+ * in is negative value and returns zero output for negative values.
+ */
+ arm_status arm_sqrt_q15(
+ q15_t in,
+ q15_t * pOut);
+
+ /**
+ * @} end of SQRT group
+ */
+
+
+
+
+
+
+ /**
+ * @brief floating-point Circular write function.
+ */
+
+ __STATIC_INLINE void arm_circularWrite_f32(
+ int32_t * circBuffer,
+ int32_t L,
+ uint16_t * writeOffset,
+ int32_t bufferInc,
+ const int32_t * src,
+ int32_t srcInc,
+ uint32_t blockSize)
+ {
+ uint32_t i = 0u;
+ int32_t wOffset;
+
+ /* Copy the value of Index pointer that points
+ * to the current location where the input samples to be copied */
+ wOffset = *writeOffset;
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while(i > 0u)
+ {
+ /* copy the input sample to the circular buffer */
+ circBuffer[wOffset] = *src;
+
+ /* Update the input pointer */
+ src += srcInc;
+
+ /* Circularly update wOffset. Watch out for positive and negative value */
+ wOffset += bufferInc;
+ if(wOffset >= L)
+ wOffset -= L;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *writeOffset = wOffset;
+ }
+
+
+
+ /**
+ * @brief floating-point Circular Read function.
+ */
+ __STATIC_INLINE void arm_circularRead_f32(
+ int32_t * circBuffer,
+ int32_t L,
+ int32_t * readOffset,
+ int32_t bufferInc,
+ int32_t * dst,
+ int32_t * dst_base,
+ int32_t dst_length,
+ int32_t dstInc,
+ uint32_t blockSize)
+ {
+ uint32_t i = 0u;
+ int32_t rOffset, dst_end;
+
+ /* Copy the value of Index pointer that points
+ * to the current location from where the input samples to be read */
+ rOffset = *readOffset;
+ dst_end = (int32_t) (dst_base + dst_length);
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while(i > 0u)
+ {
+ /* copy the sample from the circular buffer to the destination buffer */
+ *dst = circBuffer[rOffset];
+
+ /* Update the input pointer */
+ dst += dstInc;
+
+ if(dst == (int32_t *) dst_end)
+ {
+ dst = dst_base;
+ }
+
+ /* Circularly update rOffset. Watch out for positive and negative value */
+ rOffset += bufferInc;
+
+ if(rOffset >= L)
+ {
+ rOffset -= L;
+ }
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *readOffset = rOffset;
+ }
+
+ /**
+ * @brief Q15 Circular write function.
+ */
+
+ __STATIC_INLINE void arm_circularWrite_q15(
+ q15_t * circBuffer,
+ int32_t L,
+ uint16_t * writeOffset,
+ int32_t bufferInc,
+ const q15_t * src,
+ int32_t srcInc,
+ uint32_t blockSize)
+ {
+ uint32_t i = 0u;
+ int32_t wOffset;
+
+ /* Copy the value of Index pointer that points
+ * to the current location where the input samples to be copied */
+ wOffset = *writeOffset;
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while(i > 0u)
+ {
+ /* copy the input sample to the circular buffer */
+ circBuffer[wOffset] = *src;
+
+ /* Update the input pointer */
+ src += srcInc;
+
+ /* Circularly update wOffset. Watch out for positive and negative value */
+ wOffset += bufferInc;
+ if(wOffset >= L)
+ wOffset -= L;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *writeOffset = wOffset;
+ }
+
+
+
+ /**
+ * @brief Q15 Circular Read function.
+ */
+ __STATIC_INLINE void arm_circularRead_q15(
+ q15_t * circBuffer,
+ int32_t L,
+ int32_t * readOffset,
+ int32_t bufferInc,
+ q15_t * dst,
+ q15_t * dst_base,
+ int32_t dst_length,
+ int32_t dstInc,
+ uint32_t blockSize)
+ {
+ uint32_t i = 0;
+ int32_t rOffset, dst_end;
+
+ /* Copy the value of Index pointer that points
+ * to the current location from where the input samples to be read */
+ rOffset = *readOffset;
+
+ dst_end = (int32_t) (dst_base + dst_length);
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while(i > 0u)
+ {
+ /* copy the sample from the circular buffer to the destination buffer */
+ *dst = circBuffer[rOffset];
+
+ /* Update the input pointer */
+ dst += dstInc;
+
+ if(dst == (q15_t *) dst_end)
+ {
+ dst = dst_base;
+ }
+
+ /* Circularly update wOffset. Watch out for positive and negative value */
+ rOffset += bufferInc;
+
+ if(rOffset >= L)
+ {
+ rOffset -= L;
+ }
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *readOffset = rOffset;
+ }
+
+
+ /**
+ * @brief Q7 Circular write function.
+ */
+
+ __STATIC_INLINE void arm_circularWrite_q7(
+ q7_t * circBuffer,
+ int32_t L,
+ uint16_t * writeOffset,
+ int32_t bufferInc,
+ const q7_t * src,
+ int32_t srcInc,
+ uint32_t blockSize)
+ {
+ uint32_t i = 0u;
+ int32_t wOffset;
+
+ /* Copy the value of Index pointer that points
+ * to the current location where the input samples to be copied */
+ wOffset = *writeOffset;
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while(i > 0u)
+ {
+ /* copy the input sample to the circular buffer */
+ circBuffer[wOffset] = *src;
+
+ /* Update the input pointer */
+ src += srcInc;
+
+ /* Circularly update wOffset. Watch out for positive and negative value */
+ wOffset += bufferInc;
+ if(wOffset >= L)
+ wOffset -= L;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *writeOffset = wOffset;
+ }
+
+
+
+ /**
+ * @brief Q7 Circular Read function.
+ */
+ __STATIC_INLINE void arm_circularRead_q7(
+ q7_t * circBuffer,
+ int32_t L,
+ int32_t * readOffset,
+ int32_t bufferInc,
+ q7_t * dst,
+ q7_t * dst_base,
+ int32_t dst_length,
+ int32_t dstInc,
+ uint32_t blockSize)
+ {
+ uint32_t i = 0;
+ int32_t rOffset, dst_end;
+
+ /* Copy the value of Index pointer that points
+ * to the current location from where the input samples to be read */
+ rOffset = *readOffset;
+
+ dst_end = (int32_t) (dst_base + dst_length);
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while(i > 0u)
+ {
+ /* copy the sample from the circular buffer to the destination buffer */
+ *dst = circBuffer[rOffset];
+
+ /* Update the input pointer */
+ dst += dstInc;
+
+ if(dst == (q7_t *) dst_end)
+ {
+ dst = dst_base;
+ }
+
+ /* Circularly update rOffset. Watch out for positive and negative value */
+ rOffset += bufferInc;
+
+ if(rOffset >= L)
+ {
+ rOffset -= L;
+ }
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *readOffset = rOffset;
+ }
+
+
+ /**
+ * @brief Sum of the squares of the elements of a Q31 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+
+ void arm_power_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q63_t * pResult);
+
+ /**
+ * @brief Sum of the squares of the elements of a floating-point vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+
+ void arm_power_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult);
+
+ /**
+ * @brief Sum of the squares of the elements of a Q15 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+
+ void arm_power_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q63_t * pResult);
+
+ /**
+ * @brief Sum of the squares of the elements of a Q7 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+
+ void arm_power_q7(
+ q7_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult);
+
+ /**
+ * @brief Mean value of a Q7 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+
+ void arm_mean_q7(
+ q7_t * pSrc,
+ uint32_t blockSize,
+ q7_t * pResult);
+
+ /**
+ * @brief Mean value of a Q15 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+ void arm_mean_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult);
+
+ /**
+ * @brief Mean value of a Q31 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+ void arm_mean_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult);
+
+ /**
+ * @brief Mean value of a floating-point vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+ void arm_mean_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult);
+
+ /**
+ * @brief Variance of the elements of a floating-point vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+
+ void arm_var_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult);
+
+ /**
+ * @brief Variance of the elements of a Q31 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+
+ void arm_var_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q63_t * pResult);
+
+ /**
+ * @brief Variance of the elements of a Q15 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+
+ void arm_var_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult);
+
+ /**
+ * @brief Root Mean Square of the elements of a floating-point vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+
+ void arm_rms_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult);
+
+ /**
+ * @brief Root Mean Square of the elements of a Q31 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+
+ void arm_rms_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult);
+
+ /**
+ * @brief Root Mean Square of the elements of a Q15 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+
+ void arm_rms_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult);
+
+ /**
+ * @brief Standard deviation of the elements of a floating-point vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+
+ void arm_std_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult);
+
+ /**
+ * @brief Standard deviation of the elements of a Q31 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+
+ void arm_std_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult);
+
+ /**
+ * @brief Standard deviation of the elements of a Q15 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+
+ void arm_std_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult);
+
+ /**
+ * @brief Floating-point complex magnitude
+ * @param[in] *pSrc points to the complex input vector
+ * @param[out] *pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ * @return none.
+ */
+
+ void arm_cmplx_mag_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t numSamples);
+
+ /**
+ * @brief Q31 complex magnitude
+ * @param[in] *pSrc points to the complex input vector
+ * @param[out] *pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ * @return none.
+ */
+
+ void arm_cmplx_mag_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t numSamples);
+
+ /**
+ * @brief Q15 complex magnitude
+ * @param[in] *pSrc points to the complex input vector
+ * @param[out] *pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ * @return none.
+ */
+
+ void arm_cmplx_mag_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t numSamples);
+
+ /**
+ * @brief Q15 complex dot product
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @param[out] *realResult real part of the result returned here
+ * @param[out] *imagResult imaginary part of the result returned here
+ * @return none.
+ */
+
+ void arm_cmplx_dot_prod_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ uint32_t numSamples,
+ q31_t * realResult,
+ q31_t * imagResult);
+
+ /**
+ * @brief Q31 complex dot product
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @param[out] *realResult real part of the result returned here
+ * @param[out] *imagResult imaginary part of the result returned here
+ * @return none.
+ */
+
+ void arm_cmplx_dot_prod_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ uint32_t numSamples,
+ q63_t * realResult,
+ q63_t * imagResult);
+
+ /**
+ * @brief Floating-point complex dot product
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @param[out] *realResult real part of the result returned here
+ * @param[out] *imagResult imaginary part of the result returned here
+ * @return none.
+ */
+
+ void arm_cmplx_dot_prod_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ uint32_t numSamples,
+ float32_t * realResult,
+ float32_t * imagResult);
+
+ /**
+ * @brief Q15 complex-by-real multiplication
+ * @param[in] *pSrcCmplx points to the complex input vector
+ * @param[in] *pSrcReal points to the real input vector
+ * @param[out] *pCmplxDst points to the complex output vector
+ * @param[in] numSamples number of samples in each vector
+ * @return none.
+ */
+
+ void arm_cmplx_mult_real_q15(
+ q15_t * pSrcCmplx,
+ q15_t * pSrcReal,
+ q15_t * pCmplxDst,
+ uint32_t numSamples);
+
+ /**
+ * @brief Q31 complex-by-real multiplication
+ * @param[in] *pSrcCmplx points to the complex input vector
+ * @param[in] *pSrcReal points to the real input vector
+ * @param[out] *pCmplxDst points to the complex output vector
+ * @param[in] numSamples number of samples in each vector
+ * @return none.
+ */
+
+ void arm_cmplx_mult_real_q31(
+ q31_t * pSrcCmplx,
+ q31_t * pSrcReal,
+ q31_t * pCmplxDst,
+ uint32_t numSamples);
+
+ /**
+ * @brief Floating-point complex-by-real multiplication
+ * @param[in] *pSrcCmplx points to the complex input vector
+ * @param[in] *pSrcReal points to the real input vector
+ * @param[out] *pCmplxDst points to the complex output vector
+ * @param[in] numSamples number of samples in each vector
+ * @return none.
+ */
+
+ void arm_cmplx_mult_real_f32(
+ float32_t * pSrcCmplx,
+ float32_t * pSrcReal,
+ float32_t * pCmplxDst,
+ uint32_t numSamples);
+
+ /**
+ * @brief Minimum value of a Q7 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *result is output pointer
+ * @param[in] index is the array index of the minimum value in the input buffer.
+ * @return none.
+ */
+
+ void arm_min_q7(
+ q7_t * pSrc,
+ uint32_t blockSize,
+ q7_t * result,
+ uint32_t * index);
+
+ /**
+ * @brief Minimum value of a Q15 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output pointer
+ * @param[in] *pIndex is the array index of the minimum value in the input buffer.
+ * @return none.
+ */
+
+ void arm_min_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult,
+ uint32_t * pIndex);
+
+ /**
+ * @brief Minimum value of a Q31 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output pointer
+ * @param[out] *pIndex is the array index of the minimum value in the input buffer.
+ * @return none.
+ */
+ void arm_min_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult,
+ uint32_t * pIndex);
+
+ /**
+ * @brief Minimum value of a floating-point vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output pointer
+ * @param[out] *pIndex is the array index of the minimum value in the input buffer.
+ * @return none.
+ */
+
+ void arm_min_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult,
+ uint32_t * pIndex);
+
+/**
+ * @brief Maximum value of a Q7 vector.
+ * @param[in] *pSrc points to the input buffer
+ * @param[in] blockSize length of the input vector
+ * @param[out] *pResult maximum value returned here
+ * @param[out] *pIndex index of maximum value returned here
+ * @return none.
+ */
+
+ void arm_max_q7(
+ q7_t * pSrc,
+ uint32_t blockSize,
+ q7_t * pResult,
+ uint32_t * pIndex);
+
+/**
+ * @brief Maximum value of a Q15 vector.
+ * @param[in] *pSrc points to the input buffer
+ * @param[in] blockSize length of the input vector
+ * @param[out] *pResult maximum value returned here
+ * @param[out] *pIndex index of maximum value returned here
+ * @return none.
+ */
+
+ void arm_max_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult,
+ uint32_t * pIndex);
+
+/**
+ * @brief Maximum value of a Q31 vector.
+ * @param[in] *pSrc points to the input buffer
+ * @param[in] blockSize length of the input vector
+ * @param[out] *pResult maximum value returned here
+ * @param[out] *pIndex index of maximum value returned here
+ * @return none.
+ */
+
+ void arm_max_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult,
+ uint32_t * pIndex);
+
+/**
+ * @brief Maximum value of a floating-point vector.
+ * @param[in] *pSrc points to the input buffer
+ * @param[in] blockSize length of the input vector
+ * @param[out] *pResult maximum value returned here
+ * @param[out] *pIndex index of maximum value returned here
+ * @return none.
+ */
+
+ void arm_max_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult,
+ uint32_t * pIndex);
+
+ /**
+ * @brief Q15 complex-by-complex multiplication
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @return none.
+ */
+
+ void arm_cmplx_mult_cmplx_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ q15_t * pDst,
+ uint32_t numSamples);
+
+ /**
+ * @brief Q31 complex-by-complex multiplication
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @return none.
+ */
+
+ void arm_cmplx_mult_cmplx_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ q31_t * pDst,
+ uint32_t numSamples);
+
+ /**
+ * @brief Floating-point complex-by-complex multiplication
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @return none.
+ */
+
+ void arm_cmplx_mult_cmplx_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ float32_t * pDst,
+ uint32_t numSamples);
+
+ /**
+ * @brief Converts the elements of the floating-point vector to Q31 vector.
+ * @param[in] *pSrc points to the floating-point input vector
+ * @param[out] *pDst points to the Q31 output vector
+ * @param[in] blockSize length of the input vector
+ * @return none.
+ */
+ void arm_float_to_q31(
+ float32_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Converts the elements of the floating-point vector to Q15 vector.
+ * @param[in] *pSrc points to the floating-point input vector
+ * @param[out] *pDst points to the Q15 output vector
+ * @param[in] blockSize length of the input vector
+ * @return none
+ */
+ void arm_float_to_q15(
+ float32_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Converts the elements of the floating-point vector to Q7 vector.
+ * @param[in] *pSrc points to the floating-point input vector
+ * @param[out] *pDst points to the Q7 output vector
+ * @param[in] blockSize length of the input vector
+ * @return none
+ */
+ void arm_float_to_q7(
+ float32_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the Q31 vector to Q15 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[out] *pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ * @return none.
+ */
+ void arm_q31_to_q15(
+ q31_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Converts the elements of the Q31 vector to Q7 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[out] *pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ * @return none.
+ */
+ void arm_q31_to_q7(
+ q31_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Converts the elements of the Q15 vector to floating-point vector.
+ * @param[in] *pSrc is input pointer
+ * @param[out] *pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ * @return none.
+ */
+ void arm_q15_to_float(
+ q15_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the Q15 vector to Q31 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[out] *pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ * @return none.
+ */
+ void arm_q15_to_q31(
+ q15_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the Q15 vector to Q7 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[out] *pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ * @return none.
+ */
+ void arm_q15_to_q7(
+ q15_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @ingroup groupInterpolation
+ */
+
+ /**
+ * @defgroup BilinearInterpolate Bilinear Interpolation
+ *
+ * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid.
+ * The underlying function f(x, y) is sampled on a regular grid and the interpolation process
+ * determines values between the grid points.
+ * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension.
+ * Bilinear interpolation is often used in image processing to rescale images.
+ * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types.
+ *
+ * Algorithm
+ * \par
+ * The instance structure used by the bilinear interpolation functions describes a two dimensional data table.
+ * For floating-point, the instance structure is defined as:
+ *
+ * typedef struct
+ * {
+ * uint16_t numRows;
+ * uint16_t numCols;
+ * float32_t *pData;
+ * } arm_bilinear_interp_instance_f32;
+ *
+ *
+ * \par
+ * where numRows specifies the number of rows in the table;
+ * numCols specifies the number of columns in the table;
+ * and pData points to an array of size numRows*numCols values.
+ * The data table pTable is organized in row order and the supplied data values fall on integer indexes.
+ * That is, table element (x,y) is located at pTable[x + y*numCols] where x and y are integers.
+ *
+ * \par
+ * Let (x, y) specify the desired interpolation point. Then define:
+ *
+ * XF = floor(x)
+ * YF = floor(y)
+ *
+ * \par
+ * The interpolated output point is computed as:
+ *
+ * f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
+ * + f(XF+1, YF) * (x-XF)*(1-(y-YF))
+ * + f(XF, YF+1) * (1-(x-XF))*(y-YF)
+ * + f(XF+1, YF+1) * (x-XF)*(y-YF)
+ *
+ * Note that the coordinates (x, y) contain integer and fractional components.
+ * The integer components specify which portion of the table to use while the
+ * fractional components control the interpolation processor.
+ *
+ * \par
+ * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output.
+ */
+
+ /**
+ * @addtogroup BilinearInterpolate
+ * @{
+ */
+
+ /**
+ *
+ * @brief Floating-point bilinear interpolation.
+ * @param[in,out] *S points to an instance of the interpolation structure.
+ * @param[in] X interpolation coordinate.
+ * @param[in] Y interpolation coordinate.
+ * @return out interpolated value.
+ */
+
+
+ __STATIC_INLINE float32_t arm_bilinear_interp_f32(
+ const arm_bilinear_interp_instance_f32 * S,
+ float32_t X,
+ float32_t Y)
+ {
+ float32_t out;
+ float32_t f00, f01, f10, f11;
+ float32_t *pData = S->pData;
+ int32_t xIndex, yIndex, index;
+ float32_t xdiff, ydiff;
+ float32_t b1, b2, b3, b4;
+
+ xIndex = (int32_t) X;
+ yIndex = (int32_t) Y;
+
+ /* Care taken for table outside boundary */
+ /* Returns zero output when values are outside table boundary */
+ if(xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0
+ || yIndex > (S->numCols - 1))
+ {
+ return (0);
+ }
+
+ /* Calculation of index for two nearest points in X-direction */
+ index = (xIndex - 1) + (yIndex - 1) * S->numCols;
+
+
+ /* Read two nearest points in X-direction */
+ f00 = pData[index];
+ f01 = pData[index + 1];
+
+ /* Calculation of index for two nearest points in Y-direction */
+ index = (xIndex - 1) + (yIndex) * S->numCols;
+
+
+ /* Read two nearest points in Y-direction */
+ f10 = pData[index];
+ f11 = pData[index + 1];
+
+ /* Calculation of intermediate values */
+ b1 = f00;
+ b2 = f01 - f00;
+ b3 = f10 - f00;
+ b4 = f00 - f01 - f10 + f11;
+
+ /* Calculation of fractional part in X */
+ xdiff = X - xIndex;
+
+ /* Calculation of fractional part in Y */
+ ydiff = Y - yIndex;
+
+ /* Calculation of bi-linear interpolated output */
+ out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff;
+
+ /* return to application */
+ return (out);
+
+ }
+
+ /**
+ *
+ * @brief Q31 bilinear interpolation.
+ * @param[in,out] *S points to an instance of the interpolation structure.
+ * @param[in] X interpolation coordinate in 12.20 format.
+ * @param[in] Y interpolation coordinate in 12.20 format.
+ * @return out interpolated value.
+ */
+
+ __STATIC_INLINE q31_t arm_bilinear_interp_q31(
+ arm_bilinear_interp_instance_q31 * S,
+ q31_t X,
+ q31_t Y)
+ {
+ q31_t out; /* Temporary output */
+ q31_t acc = 0; /* output */
+ q31_t xfract, yfract; /* X, Y fractional parts */
+ q31_t x1, x2, y1, y2; /* Nearest output values */
+ int32_t rI, cI; /* Row and column indices */
+ q31_t *pYData = S->pData; /* pointer to output table values */
+ uint32_t nCols = S->numCols; /* num of rows */
+
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ rI = ((X & 0xFFF00000) >> 20u);
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ cI = ((Y & 0xFFF00000) >> 20u);
+
+ /* Care taken for table outside boundary */
+ /* Returns zero output when values are outside table boundary */
+ if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
+ {
+ return (0);
+ }
+
+ /* 20 bits for the fractional part */
+ /* shift left xfract by 11 to keep 1.31 format */
+ xfract = (X & 0x000FFFFF) << 11u;
+
+ /* Read two nearest output values from the index */
+ x1 = pYData[(rI) + nCols * (cI)];
+ x2 = pYData[(rI) + nCols * (cI) + 1u];
+
+ /* 20 bits for the fractional part */
+ /* shift left yfract by 11 to keep 1.31 format */
+ yfract = (Y & 0x000FFFFF) << 11u;
+
+ /* Read two nearest output values from the index */
+ y1 = pYData[(rI) + nCols * (cI + 1)];
+ y2 = pYData[(rI) + nCols * (cI + 1) + 1u];
+
+ /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */
+ out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32));
+ acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32));
+
+ /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */
+ out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32));
+ acc += ((q31_t) ((q63_t) out * (xfract) >> 32));
+
+ /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */
+ out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32));
+ acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
+
+ /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */
+ out = ((q31_t) ((q63_t) y2 * (xfract) >> 32));
+ acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
+
+ /* Convert acc to 1.31(q31) format */
+ return (acc << 2u);
+
+ }
+
+ /**
+ * @brief Q15 bilinear interpolation.
+ * @param[in,out] *S points to an instance of the interpolation structure.
+ * @param[in] X interpolation coordinate in 12.20 format.
+ * @param[in] Y interpolation coordinate in 12.20 format.
+ * @return out interpolated value.
+ */
+
+ __STATIC_INLINE q15_t arm_bilinear_interp_q15(
+ arm_bilinear_interp_instance_q15 * S,
+ q31_t X,
+ q31_t Y)
+ {
+ q63_t acc = 0; /* output */
+ q31_t out; /* Temporary output */
+ q15_t x1, x2, y1, y2; /* Nearest output values */
+ q31_t xfract, yfract; /* X, Y fractional parts */
+ int32_t rI, cI; /* Row and column indices */
+ q15_t *pYData = S->pData; /* pointer to output table values */
+ uint32_t nCols = S->numCols; /* num of rows */
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ rI = ((X & 0xFFF00000) >> 20);
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ cI = ((Y & 0xFFF00000) >> 20);
+
+ /* Care taken for table outside boundary */
+ /* Returns zero output when values are outside table boundary */
+ if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
+ {
+ return (0);
+ }
+
+ /* 20 bits for the fractional part */
+ /* xfract should be in 12.20 format */
+ xfract = (X & 0x000FFFFF);
+
+ /* Read two nearest output values from the index */
+ x1 = pYData[(rI) + nCols * (cI)];
+ x2 = pYData[(rI) + nCols * (cI) + 1u];
+
+
+ /* 20 bits for the fractional part */
+ /* yfract should be in 12.20 format */
+ yfract = (Y & 0x000FFFFF);
+
+ /* Read two nearest output values from the index */
+ y1 = pYData[(rI) + nCols * (cI + 1)];
+ y2 = pYData[(rI) + nCols * (cI + 1) + 1u];
+
+ /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */
+
+ /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */
+ /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */
+ out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u);
+ acc = ((q63_t) out * (0xFFFFF - yfract));
+
+ /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */
+ out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u);
+ acc += ((q63_t) out * (xfract));
+
+ /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */
+ out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u);
+ acc += ((q63_t) out * (yfract));
+
+ /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */
+ out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u);
+ acc += ((q63_t) out * (yfract));
+
+ /* acc is in 13.51 format and down shift acc by 36 times */
+ /* Convert out to 1.15 format */
+ return (acc >> 36);
+
+ }
+
+ /**
+ * @brief Q7 bilinear interpolation.
+ * @param[in,out] *S points to an instance of the interpolation structure.
+ * @param[in] X interpolation coordinate in 12.20 format.
+ * @param[in] Y interpolation coordinate in 12.20 format.
+ * @return out interpolated value.
+ */
+
+ __STATIC_INLINE q7_t arm_bilinear_interp_q7(
+ arm_bilinear_interp_instance_q7 * S,
+ q31_t X,
+ q31_t Y)
+ {
+ q63_t acc = 0; /* output */
+ q31_t out; /* Temporary output */
+ q31_t xfract, yfract; /* X, Y fractional parts */
+ q7_t x1, x2, y1, y2; /* Nearest output values */
+ int32_t rI, cI; /* Row and column indices */
+ q7_t *pYData = S->pData; /* pointer to output table values */
+ uint32_t nCols = S->numCols; /* num of rows */
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ rI = ((X & 0xFFF00000) >> 20);
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ cI = ((Y & 0xFFF00000) >> 20);
+
+ /* Care taken for table outside boundary */
+ /* Returns zero output when values are outside table boundary */
+ if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
+ {
+ return (0);
+ }
+
+ /* 20 bits for the fractional part */
+ /* xfract should be in 12.20 format */
+ xfract = (X & 0x000FFFFF);
+
+ /* Read two nearest output values from the index */
+ x1 = pYData[(rI) + nCols * (cI)];
+ x2 = pYData[(rI) + nCols * (cI) + 1u];
+
+
+ /* 20 bits for the fractional part */
+ /* yfract should be in 12.20 format */
+ yfract = (Y & 0x000FFFFF);
+
+ /* Read two nearest output values from the index */
+ y1 = pYData[(rI) + nCols * (cI + 1)];
+ y2 = pYData[(rI) + nCols * (cI + 1) + 1u];
+
+ /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */
+ out = ((x1 * (0xFFFFF - xfract)));
+ acc = (((q63_t) out * (0xFFFFF - yfract)));
+
+ /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */
+ out = ((x2 * (0xFFFFF - yfract)));
+ acc += (((q63_t) out * (xfract)));
+
+ /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */
+ out = ((y1 * (0xFFFFF - xfract)));
+ acc += (((q63_t) out * (yfract)));
+
+ /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */
+ out = ((y2 * (yfract)));
+ acc += (((q63_t) out * (xfract)));
+
+ /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */
+ return (acc >> 40);
+
+ }
+
+ /**
+ * @} end of BilinearInterpolate group
+ */
+
+
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* _ARM_MATH_H */
+
+
+/**
+ *
+ * End of file.
+ */
diff --git a/bsp/nuvoton_m451/Libraries/CMSIS/Include/core_cm0.h b/bsp/nuvoton_m451/Libraries/CMSIS/Include/core_cm0.h
new file mode 100644
index 0000000000000000000000000000000000000000..19bad5ebeb941aa75498c6db77e4240aadd2e2dc
--- /dev/null
+++ b/bsp/nuvoton_m451/Libraries/CMSIS/Include/core_cm0.h
@@ -0,0 +1,667 @@
+/**************************************************************************//**
+ * @file core_cm0.h
+ * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
+ * @version V3.01
+ * @date 13. March 2012
+ *
+ * @note
+ * Copyright (C) 2009-2012 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers. This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#endif
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __CORE_CM0_H_GENERIC
+#define __CORE_CM0_H_GENERIC
+
+/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex_M0
+ @{
+ */
+
+/* CMSIS CM0 definitions */
+#define __CM0_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
+#define __CM0_CMSIS_VERSION_SUB (0x01) /*!< [15:0] CMSIS HAL sub version */
+#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | \
+ __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
+
+#define __CORTEX_M (0x00) /*!< Cortex-M Core */
+
+
+#if defined ( __CC_ARM )
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
+ #define __STATIC_INLINE static __inline
+
+#elif defined ( __ICCARM__ )
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __GNUC__ )
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TASKING__ )
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */
+ #define __STATIC_INLINE static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
+*/
+#define __FPU_USED 0
+
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+#endif
+
+#include /* standard types definitions */
+#include /* Core Instruction Access */
+#include /* Core Function Access */
+
+#endif /* __CORE_CM0_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM0_H_DEPENDANT
+#define __CORE_CM0_H_DEPENDANT
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM0_REV
+ #define __CM0_REV 0x0000
+ #warning "__CM0_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 2
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ IO Type Qualifiers are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/*@} end of group Cortex_M0 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/** \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+#if (__CORTEX_M != 0x04)
+ uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
+#else
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
+#endif
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+
+/** \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+
+/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+#if (__CORTEX_M != 0x04)
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+#else
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
+#endif
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+
+/** \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
+ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[31];
+ __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[31];
+ __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[31];
+ __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[31];
+ uint32_t RESERVED4[64];
+ __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
+} NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/** \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ uint32_t RESERVED0;
+ __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ uint32_t RESERVED1;
+ __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
+ __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/** \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR)
+ are only accessible over DAP and not via processor. Therefore
+ they are not covered by the Cortex-M0 header file.
+ @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Cortex-M0 Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 )
+#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) )
+#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) )
+
+
+/** \brief Enable External Interrupt
+
+ The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief Disable External Interrupt
+
+ The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief Get Pending Interrupt
+
+ The function reads the pending register in the NVIC and returns the pending bit
+ for the specified interrupt.
+
+ \param [in] IRQn Interrupt number.
+
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
+}
+
+
+/** \brief Set Pending Interrupt
+
+ The function sets the pending bit of an external interrupt.
+
+ \param [in] IRQn Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief Clear Pending Interrupt
+
+ The function clears the pending bit of an external interrupt.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief Set Interrupt Priority
+
+ The function sets the priority of an interrupt.
+
+ \note The priority cannot be set for every core interrupt.
+
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if(IRQn < 0) {
+ SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+ (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+ else {
+ NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+ (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+}
+
+
+/** \brief Get Interrupt Priority
+
+ The function reads the priority of an interrupt. The interrupt
+ number can be positive to specify an external (device specific)
+ interrupt, or negative to specify an internal (core) interrupt.
+
+
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority. Value is aligned automatically to the implemented
+ priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if(IRQn < 0) {
+ return((uint32_t)((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */
+ else {
+ return((uint32_t)((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
+}
+
+
+/** \brief System Reset
+
+ The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+ SCB_AIRCR_SYSRESETREQ_Msk);
+ __DSB(); /* Ensure completion of memory access */
+ while(1); /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief System Tick Configuration
+
+ The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+
+ \param [in] ticks Number of ticks between two interrupts.
+
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function SysTick_Config is not included. In this case, the file device.h
+ must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
+
+ SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#endif /* __CORE_CM0_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/bsp/nuvoton_m451/Libraries/CMSIS/Include/core_cm0plus.h b/bsp/nuvoton_m451/Libraries/CMSIS/Include/core_cm0plus.h
new file mode 100644
index 0000000000000000000000000000000000000000..aa20e6879f203e09efdeefe12d96f3dfb07901c0
--- /dev/null
+++ b/bsp/nuvoton_m451/Libraries/CMSIS/Include/core_cm0plus.h
@@ -0,0 +1,778 @@
+/**************************************************************************//**
+ * @file core_cm0plus.h
+ * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
+ * @version V3.01
+ * @date 22. March 2012
+ *
+ * @note
+ * Copyright (C) 2009-2012 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers. This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#endif
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __CORE_CM0PLUS_H_GENERIC
+#define __CORE_CM0PLUS_H_GENERIC
+
+/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex-M0+
+ @{
+ */
+
+/* CMSIS CM0P definitions */
+#define __CM0PLUS_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
+#define __CM0PLUS_CMSIS_VERSION_SUB (0x01) /*!< [15:0] CMSIS HAL sub version */
+#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \
+ __CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
+
+#define __CORTEX_M (0x00) /*!< Cortex-M Core */
+
+
+#if defined ( __CC_ARM )
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
+ #define __STATIC_INLINE static __inline
+
+#elif defined ( __ICCARM__ )
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __GNUC__ )
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TASKING__ )
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */
+ #define __STATIC_INLINE static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
+*/
+#define __FPU_USED 0
+
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+#endif
+
+#include /* standard types definitions */
+#include /* Core Instruction Access */
+#include /* Core Function Access */
+
+#endif /* __CORE_CM0PLUS_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM0PLUS_H_DEPENDANT
+#define __CORE_CM0PLUS_H_DEPENDANT
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM0PLUS_REV
+ #define __CM0PLUS_REV 0x0000
+ #warning "__CM0PLUS_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __VTOR_PRESENT
+ #define __VTOR_PRESENT 0
+ #warning "__VTOR_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 2
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ IO Type Qualifiers are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/*@} end of group Cortex-M0+ */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core MPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/** \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+#if (__CORTEX_M != 0x04)
+ uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
+#else
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
+#endif
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+
+/** \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+
+/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+#if (__CORTEX_M != 0x04)
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+#else
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
+#endif
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+
+/** \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
+ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[31];
+ __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[31];
+ __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[31];
+ __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[31];
+ uint32_t RESERVED4[64];
+ __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
+} NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/** \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+#if (__VTOR_PRESENT == 1)
+ __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+#else
+ uint32_t RESERVED0;
+#endif
+ __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ uint32_t RESERVED1;
+ __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
+ __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
+
+#if (__VTOR_PRESENT == 1)
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/** \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/** \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR)
+ are only accessible over DAP and not via processor. Therefore
+ they are not covered by the Cortex-M0 header file.
+ @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Cortex-M0+ Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+
+#if (__MPU_PRESENT == 1)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 )
+#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) )
+#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) )
+
+
+/** \brief Enable External Interrupt
+
+ The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief Disable External Interrupt
+
+ The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief Get Pending Interrupt
+
+ The function reads the pending register in the NVIC and returns the pending bit
+ for the specified interrupt.
+
+ \param [in] IRQn Interrupt number.
+
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
+}
+
+
+/** \brief Set Pending Interrupt
+
+ The function sets the pending bit of an external interrupt.
+
+ \param [in] IRQn Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief Clear Pending Interrupt
+
+ The function clears the pending bit of an external interrupt.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief Set Interrupt Priority
+
+ The function sets the priority of an interrupt.
+
+ \note The priority cannot be set for every core interrupt.
+
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if(IRQn < 0) {
+ SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+ (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+ else {
+ NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+ (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+}
+
+
+/** \brief Get Interrupt Priority
+
+ The function reads the priority of an interrupt. The interrupt
+ number can be positive to specify an external (device specific)
+ interrupt, or negative to specify an internal (core) interrupt.
+
+
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority. Value is aligned automatically to the implemented
+ priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if(IRQn < 0) {
+ return((uint32_t)((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0+ system interrupts */
+ else {
+ return((uint32_t)((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
+}
+
+
+/** \brief System Reset
+
+ The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+ SCB_AIRCR_SYSRESETREQ_Msk);
+ __DSB(); /* Ensure completion of memory access */
+ while(1); /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief System Tick Configuration
+
+ The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+
+ \param [in] ticks Number of ticks between two interrupts.
+
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function SysTick_Config is not included. In this case, the file device.h
+ must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
+
+ SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#endif /* __CORE_CM0PLUS_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/bsp/nuvoton_m451/Libraries/CMSIS/Include/core_cm3.h b/bsp/nuvoton_m451/Libraries/CMSIS/Include/core_cm3.h
new file mode 100644
index 0000000000000000000000000000000000000000..0173893fbd201ecdfe2a1d5bd18dc0118834dd01
--- /dev/null
+++ b/bsp/nuvoton_m451/Libraries/CMSIS/Include/core_cm3.h
@@ -0,0 +1,1612 @@
+/**************************************************************************//**
+ * @file core_cm3.h
+ * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
+ * @version V3.01
+ * @date 22. March 2012
+ *
+ * @note
+ * Copyright (C) 2009-2012 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers. This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#endif
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __CORE_CM3_H_GENERIC
+#define __CORE_CM3_H_GENERIC
+
+/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex_M3
+ @{
+ */
+
+/* CMSIS CM3 definitions */
+#define __CM3_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
+#define __CM3_CMSIS_VERSION_SUB (0x01) /*!< [15:0] CMSIS HAL sub version */
+#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | \
+ __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
+
+#define __CORTEX_M (0x03) /*!< Cortex-M Core */
+
+
+#if defined ( __CC_ARM )
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
+ #define __STATIC_INLINE static __inline
+
+#elif defined ( __ICCARM__ )
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TMS470__ )
+ #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __GNUC__ )
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TASKING__ )
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */
+ #define __STATIC_INLINE static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
+*/
+#define __FPU_USED 0
+
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TMS470__ )
+ #if defined __TI__VFP_SUPPORT____
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+#endif
+
+#include /* standard types definitions */
+#include /* Core Instruction Access */
+#include /* Core Function Access */
+
+#endif /* __CORE_CM3_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM3_H_DEPENDANT
+#define __CORE_CM3_H_DEPENDANT
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM3_REV
+ #define __CM3_REV 0x0200
+ #warning "__CM3_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 4
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ IO Type Qualifiers are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/*@} end of group Cortex_M3 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/** \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+#if (__CORTEX_M != 0x04)
+ uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
+#else
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
+#endif
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+
+/** \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+
+/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+#if (__CORTEX_M != 0x04)
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+#else
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
+#endif
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+
+/** \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
+ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[24];
+ __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[24];
+ __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[24];
+ __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[24];
+ __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[56];
+ __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED5[644];
+ __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/** \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ uint32_t RESERVED0[5];
+ __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#if (__CM3_REV < 0x0201) /* core r2p1 */
+#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */
+#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
+
+#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+#else
+#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Registers Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* SCB Hard Fault Status Registers Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/** \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1];
+ __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
+ __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+#else
+ uint32_t RESERVED1[1];
+#endif
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/** \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+ __O union
+ {
+ __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864];
+ __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15];
+ __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15];
+ __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[29];
+ __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
+ __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
+ __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
+ uint32_t RESERVED4[43];
+ __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[6];
+ __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
+ __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED0[1];
+ __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
+ __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED1[1];
+ __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
+ __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED2[1];
+ __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
+ __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/** \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2];
+ __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55];
+ __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131];
+ __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
+ uint32_t RESERVED3[759];
+ __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
+ __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
+ __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
+ uint32_t RESERVED4[1];
+ __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
+ __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
+ __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39];
+ __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8];
+ __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
+ __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/** \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+ __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
+ __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
+ __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
+ __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
+ __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
+ __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/** \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register */
+#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Cortex-M3 Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
+
+#if (__MPU_PRESENT == 1)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+/** \brief Set Priority Grouping
+
+ The function sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << 8)); /* Insert write key and priorty group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/** \brief Get Priority Grouping
+
+ The function reads the priority grouping field from the NVIC Interrupt Controller.
+
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
+{
+ return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */
+}
+
+
+/** \brief Enable External Interrupt
+
+ The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
+}
+
+
+/** \brief Disable External Interrupt
+
+ The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
+}
+
+
+/** \brief Get Pending Interrupt
+
+ The function reads the pending register in the NVIC and returns the pending bit
+ for the specified interrupt.
+
+ \param [in] IRQn Interrupt number.
+
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
+}
+
+
+/** \brief Set Pending Interrupt
+
+ The function sets the pending bit of an external interrupt.
+
+ \param [in] IRQn Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
+}
+
+
+/** \brief Clear Pending Interrupt
+
+ The function clears the pending bit of an external interrupt.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief Get Active Interrupt
+
+ The function reads the active register in NVIC and returns the active bit.
+
+ \param [in] IRQn Interrupt number.
+
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ */
+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+ return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
+}
+
+
+/** \brief Set Interrupt Priority
+
+ The function sets the priority of an interrupt.
+
+ \note The priority cannot be set for every core interrupt.
+
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if(IRQn < 0) {
+ SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */
+ else {
+ NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */
+}
+
+
+/** \brief Get Interrupt Priority
+
+ The function reads the priority of an interrupt. The interrupt
+ number can be positive to specify an external (device specific)
+ interrupt, or negative to specify an internal (core) interrupt.
+
+
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority. Value is aligned automatically to the implemented
+ priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if(IRQn < 0) {
+ return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */
+ else {
+ return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
+}
+
+
+/** \brief Encode Priority
+
+ The function encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set.
+
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+ SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+ return (
+ ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
+ ((SubPriority & ((1 << (SubPriorityBits )) - 1)))
+ );
+}
+
+
+/** \brief Decode Priority
+
+ The function decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
+
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+ SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
+ *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);
+}
+
+
+/** \brief System Reset
+
+ The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+ while(1); /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief System Tick Configuration
+
+ The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+
+ \param [in] ticks Number of ticks between two interrupts.
+
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function SysTick_Config is not included. In this case, the file device.h
+ must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
+
+ SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_core_DebugFunctions ITM Functions
+ \brief Functions that access the ITM debug interface.
+ @{
+ */
+
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
+#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/** \brief ITM Send Character
+
+ The function transmits a character via the ITM channel 0, and
+ \li Just returns when no debugger is connected that has booked the output.
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+
+ \param [in] ch Character to transmit.
+
+ \returns Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+ if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */
+ (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */
+ {
+ while (ITM->PORT[0].u32 == 0);
+ ITM->PORT[0].u8 = (uint8_t) ch;
+ }
+ return (ch);
+}
+
+
+/** \brief ITM Receive Character
+
+ The function inputs a character via the external variable \ref ITM_RxBuffer.
+
+ \return Received character.
+ \return -1 No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
+ int32_t ch = -1; /* no character available */
+
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+ ch = ITM_RxBuffer;
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
+ }
+
+ return (ch);
+}
+
+
+/** \brief ITM Check Character
+
+ The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+
+ \return 0 No character available.
+ \return 1 Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void) {
+
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
+ return (0); /* no character available */
+ } else {
+ return (1); /* character available */
+ }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+#endif /* __CORE_CM3_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/bsp/nuvoton_m451/Libraries/CMSIS/Include/core_cm4.h b/bsp/nuvoton_m451/Libraries/CMSIS/Include/core_cm4.h
new file mode 100644
index 0000000000000000000000000000000000000000..a9655374020c91e791fa60249f1e333616b709aa
--- /dev/null
+++ b/bsp/nuvoton_m451/Libraries/CMSIS/Include/core_cm4.h
@@ -0,0 +1,1757 @@
+/**************************************************************************//**
+ * @file core_cm4.h
+ * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File
+ * @version V3.01
+ * @date 22. March 2012
+ *
+ * @note
+ * Copyright (C) 2009-2012 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers. This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#endif
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __CORE_CM4_H_GENERIC
+#define __CORE_CM4_H_GENERIC
+
+/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex_M4
+ @{
+ */
+
+/* CMSIS CM4 definitions */
+#define __CM4_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
+#define __CM4_CMSIS_VERSION_SUB (0x01) /*!< [15:0] CMSIS HAL sub version */
+#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16) | \
+ __CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
+
+#define __CORTEX_M (0x04) /*!< Cortex-M Core */
+
+
+#if defined ( __CC_ARM )
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
+ #define __STATIC_INLINE static __inline
+
+#elif defined ( __ICCARM__ )
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TMS470__ )
+ #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __GNUC__ )
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TASKING__ )
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */
+ #define __STATIC_INLINE static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #if (__FPU_PRESENT == 1)
+ #define __FPU_USED 1
+ #else
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0
+ #endif
+ #else
+ #define __FPU_USED 0
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #if (__FPU_PRESENT == 1)
+ #define __FPU_USED 1
+ #else
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0
+ #endif
+ #else
+ #define __FPU_USED 0
+ #endif
+
+#elif defined ( __TMS470__ )
+ #if defined __TI_VFP_SUPPORT__
+ #if (__FPU_PRESENT == 1)
+ #define __FPU_USED 1
+ #else
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0
+ #endif
+ #else
+ #define __FPU_USED 0
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #if (__FPU_PRESENT == 1)
+ #define __FPU_USED 1
+ #else
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0
+ #endif
+ #else
+ #define __FPU_USED 0
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #if (__FPU_PRESENT == 1)
+ #define __FPU_USED 1
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0
+ #endif
+ #else
+ #define __FPU_USED 0
+ #endif
+#endif
+
+#include /* standard types definitions */
+#include /* Core Instruction Access */
+#include /* Core Function Access */
+#include /* Compiler specific SIMD Intrinsics */
+
+#endif /* __CORE_CM4_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM4_H_DEPENDANT
+#define __CORE_CM4_H_DEPENDANT
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM4_REV
+ #define __CM4_REV 0x0000
+ #warning "__CM4_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __FPU_PRESENT
+ #define __FPU_PRESENT 0
+ #warning "__FPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 4
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ IO Type Qualifiers are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/*@} end of group Cortex_M4 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ - Core FPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/** \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+#if (__CORTEX_M != 0x04)
+ uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
+#else
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
+#endif
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+
+/** \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+
+/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+#if (__CORTEX_M != 0x04)
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+#else
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
+#endif
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+
+/** \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
+ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[24];
+ __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[24];
+ __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[24];
+ __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[24];
+ __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[56];
+ __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED5[644];
+ __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/** \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ uint32_t RESERVED0[5];
+ __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Registers Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* SCB Hard Fault Status Registers Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/** \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1];
+ __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+ __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISOOFP_Pos 9 /*!< ACTLR: DISOOFP Position */
+#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */
+
+#define SCnSCB_ACTLR_DISFPCA_Pos 8 /*!< ACTLR: DISFPCA Position */
+#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/** \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+ __O union
+ {
+ __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864];
+ __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15];
+ __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15];
+ __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[29];
+ __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
+ __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
+ __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
+ uint32_t RESERVED4[43];
+ __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[6];
+ __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
+ __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED0[1];
+ __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
+ __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED1[1];
+ __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
+ __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED2[1];
+ __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
+ __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/** \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2];
+ __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55];
+ __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131];
+ __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
+ uint32_t RESERVED3[759];
+ __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
+ __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
+ __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
+ uint32_t RESERVED4[1];
+ __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
+ __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
+ __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39];
+ __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8];
+ __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
+ __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/** \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+ __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
+ __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
+ __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
+ __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
+ __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
+ __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if (__FPU_PRESENT == 1)
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_FPU Floating Point Unit (FPU)
+ \brief Type definitions for the Floating Point Unit (FPU)
+ @{
+ */
+
+/** \brief Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1];
+ __IO uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
+ __IO uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
+ __IO uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
+ __I uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
+ __I uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register */
+#define FPU_FPCCR_ASPEN_Pos 31 /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos 30 /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos 8 /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos 6 /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos 5 /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos 4 /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos 3 /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_USER_Pos 1 /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk (1UL << FPU_FPCCR_LSPACT_Pos) /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register */
+#define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register */
+#define FPU_FPDSCR_AHP_Pos 26 /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos 25 /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos 24 /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos 22 /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 */
+#define FPU_MVFR0_FP_rounding_modes_Pos 28 /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos 24 /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos 20 /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos 16 /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos 12 /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos 8 /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos 4 /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos) /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 */
+#define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos 24 /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos 4 /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk (0xFUL << FPU_MVFR1_FtZ_mode_Pos) /*!< MVFR1: FtZ mode bits Mask */
+
+/*@} end of group CMSIS_FPU */
+#endif
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/** \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register */
+#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Cortex-M4 Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
+
+#if (__MPU_PRESENT == 1)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+#if (__FPU_PRESENT == 1)
+ #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
+ #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+/** \brief Set Priority Grouping
+
+ The function sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << 8)); /* Insert write key and priorty group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/** \brief Get Priority Grouping
+
+ The function reads the priority grouping field from the NVIC Interrupt Controller.
+
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
+{
+ return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */
+}
+
+
+/** \brief Enable External Interrupt
+
+ The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+/* NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); enable interrupt */
+ NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */
+}
+
+
+/** \brief Disable External Interrupt
+
+ The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
+}
+
+
+/** \brief Get Pending Interrupt
+
+ The function reads the pending register in the NVIC and returns the pending bit
+ for the specified interrupt.
+
+ \param [in] IRQn Interrupt number.
+
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
+}
+
+
+/** \brief Set Pending Interrupt
+
+ The function sets the pending bit of an external interrupt.
+
+ \param [in] IRQn Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
+}
+
+
+/** \brief Clear Pending Interrupt
+
+ The function clears the pending bit of an external interrupt.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief Get Active Interrupt
+
+ The function reads the active register in NVIC and returns the active bit.
+
+ \param [in] IRQn Interrupt number.
+
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ */
+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+ return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
+}
+
+
+/** \brief Set Interrupt Priority
+
+ The function sets the priority of an interrupt.
+
+ \note The priority cannot be set for every core interrupt.
+
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if(IRQn < 0) {
+ SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */
+ else {
+ NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */
+}
+
+
+/** \brief Get Interrupt Priority
+
+ The function reads the priority of an interrupt. The interrupt
+ number can be positive to specify an external (device specific)
+ interrupt, or negative to specify an internal (core) interrupt.
+
+
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority. Value is aligned automatically to the implemented
+ priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if(IRQn < 0) {
+ return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */
+ else {
+ return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
+}
+
+
+/** \brief Encode Priority
+
+ The function encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set.
+
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+ SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+ return (
+ ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
+ ((SubPriority & ((1 << (SubPriorityBits )) - 1)))
+ );
+}
+
+
+/** \brief Decode Priority
+
+ The function decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
+
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+ SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
+ *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);
+}
+
+
+/** \brief System Reset
+
+ The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+ while(1); /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief System Tick Configuration
+
+ The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+
+ \param [in] ticks Number of ticks between two interrupts.
+
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function SysTick_Config is not included. In this case, the file device.h
+ must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
+
+ SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_core_DebugFunctions ITM Functions
+ \brief Functions that access the ITM debug interface.
+ @{
+ */
+
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
+#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/** \brief ITM Send Character
+
+ The function transmits a character via the ITM channel 0, and
+ \li Just returns when no debugger is connected that has booked the output.
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+
+ \param [in] ch Character to transmit.
+
+ \returns Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+ if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */
+ (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */
+ {
+ while (ITM->PORT[0].u32 == 0);
+ ITM->PORT[0].u8 = (uint8_t) ch;
+ }
+ return (ch);
+}
+
+
+/** \brief ITM Receive Character
+
+ The function inputs a character via the external variable \ref ITM_RxBuffer.
+
+ \return Received character.
+ \return -1 No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
+ int32_t ch = -1; /* no character available */
+
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+ ch = ITM_RxBuffer;
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
+ }
+
+ return (ch);
+}
+
+
+/** \brief ITM Check Character
+
+ The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+
+ \return 0 No character available.
+ \return 1 Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void) {
+
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
+ return (0); /* no character available */
+ } else {
+ return (1); /* character available */
+ }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+#endif /* __CORE_CM4_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/bsp/nuvoton_m451/Libraries/CMSIS/Include/core_cm4_simd.h b/bsp/nuvoton_m451/Libraries/CMSIS/Include/core_cm4_simd.h
new file mode 100644
index 0000000000000000000000000000000000000000..3bc7906152bdc3f578006cfe678ce1a60705c6e9
--- /dev/null
+++ b/bsp/nuvoton_m451/Libraries/CMSIS/Include/core_cm4_simd.h
@@ -0,0 +1,649 @@
+/**************************************************************************//**
+ * @file core_cm4_simd.h
+ * @brief CMSIS Cortex-M4 SIMD Header File
+ * @version V3.01
+ * @date 06. March 2012
+ *
+ * @note
+ * Copyright (C) 2010-2012 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers. This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __CORE_CM4_SIMD_H
+#define __CORE_CM4_SIMD_H
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ ******************************************************************************/
+
+
+/* ################### Compiler specific Intrinsics ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+ Access to dedicated SIMD instructions
+ @{
+*/
+
+#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
+#define __SADD8 __sadd8
+#define __QADD8 __qadd8
+#define __SHADD8 __shadd8
+#define __UADD8 __uadd8
+#define __UQADD8 __uqadd8
+#define __UHADD8 __uhadd8
+#define __SSUB8 __ssub8
+#define __QSUB8 __qsub8
+#define __SHSUB8 __shsub8
+#define __USUB8 __usub8
+#define __UQSUB8 __uqsub8
+#define __UHSUB8 __uhsub8
+#define __SADD16 __sadd16
+#define __QADD16 __qadd16
+#define __SHADD16 __shadd16
+#define __UADD16 __uadd16
+#define __UQADD16 __uqadd16
+#define __UHADD16 __uhadd16
+#define __SSUB16 __ssub16
+#define __QSUB16 __qsub16
+#define __SHSUB16 __shsub16
+#define __USUB16 __usub16
+#define __UQSUB16 __uqsub16
+#define __UHSUB16 __uhsub16
+#define __SASX __sasx
+#define __QASX __qasx
+#define __SHASX __shasx
+#define __UASX __uasx
+#define __UQASX __uqasx
+#define __UHASX __uhasx
+#define __SSAX __ssax
+#define __QSAX __qsax
+#define __SHSAX __shsax
+#define __USAX __usax
+#define __UQSAX __uqsax
+#define __UHSAX __uhsax
+#define __USAD8 __usad8
+#define __USADA8 __usada8
+#define __SSAT16 __ssat16
+#define __USAT16 __usat16
+#define __UXTB16 __uxtb16
+#define __UXTAB16 __uxtab16
+#define __SXTB16 __sxtb16
+#define __SXTAB16 __sxtab16
+#define __SMUAD __smuad
+#define __SMUADX __smuadx
+#define __SMLAD __smlad
+#define __SMLADX __smladx
+#define __SMLALD __smlald
+#define __SMLALDX __smlaldx
+#define __SMUSD __smusd
+#define __SMUSDX __smusdx
+#define __SMLSD __smlsd
+#define __SMLSDX __smlsdx
+#define __SMLSLD __smlsld
+#define __SMLSLDX __smlsldx
+#define __SEL __sel
+#define __QADD __qadd
+#define __QSUB __qsub
+
+#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
+ ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
+
+#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
+ ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
+
+
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
+#include
+
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
+#include
+
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#define __SSAT16(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+#define __USAT16(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
+{
+ uint32_t result;
+
+ __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
+{
+ uint32_t result;
+
+ __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#define __SMLALD(ARG1,ARG2,ARG3) \
+({ \
+ uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
+ (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
+ })
+
+#define __SMLALDX(ARG1,ARG2,ARG3) \
+({ \
+ uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
+ (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#define __SMLSLD(ARG1,ARG2,ARG3) \
+({ \
+ uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
+ (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
+ })
+
+#define __SMLSLDX(ARG1,ARG2,ARG3) \
+({ \
+ uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
+ (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+#define __PKHBT(ARG1,ARG2,ARG3) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+ __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
+ __RES; \
+ })
+
+#define __PKHTB(ARG1,ARG2,ARG3) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+ if (ARG3 == 0) \
+ __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
+ else \
+ __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
+ __RES; \
+ })
+
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+
+
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
+/* not yet supported */
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
+
+#endif
+
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CORE_CM4_SIMD_H */
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/bsp/nuvoton_m451/Libraries/CMSIS/Include/core_cmFunc.h b/bsp/nuvoton_m451/Libraries/CMSIS/Include/core_cmFunc.h
new file mode 100644
index 0000000000000000000000000000000000000000..3c932e0d6e9dc47a0b5a06c4130ae4dccf4144c0
--- /dev/null
+++ b/bsp/nuvoton_m451/Libraries/CMSIS/Include/core_cmFunc.h
@@ -0,0 +1,616 @@
+/**************************************************************************//**
+ * @file core_cmFunc.h
+ * @brief CMSIS Cortex-M Core Function Access Header File
+ * @version V3.01
+ * @date 06. March 2012
+ *
+ * @note
+ * Copyright (C) 2009-2012 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers. This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+#ifndef __CORE_CMFUNC_H
+#define __CORE_CMFUNC_H
+
+
+/* ########################### Core Function Access ########################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+ @{
+ */
+
+#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#if (__ARMCC_VERSION < 400677)
+ #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+/* intrinsic void __enable_irq(); */
+/* intrinsic void __disable_irq(); */
+
+/** \brief Get Control Register
+
+ This function returns the content of the Control Register.
+
+ \return Control Register value
+ */
+__STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+ register uint32_t __regControl __ASM("control");
+ return(__regControl);
+}
+
+
+/** \brief Set Control Register
+
+ This function writes the given value to the Control Register.
+
+ \param [in] control Control Register value to set
+ */
+__STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+ register uint32_t __regControl __ASM("control");
+ __regControl = control;
+}
+
+
+/** \brief Get IPSR Register
+
+ This function returns the content of the IPSR Register.
+
+ \return IPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_IPSR(void)
+{
+ register uint32_t __regIPSR __ASM("ipsr");
+ return(__regIPSR);
+}
+
+
+/** \brief Get APSR Register
+
+ This function returns the content of the APSR Register.
+
+ \return APSR Register value
+ */
+__STATIC_INLINE uint32_t __get_APSR(void)
+{
+ register uint32_t __regAPSR __ASM("apsr");
+ return(__regAPSR);
+}
+
+
+/** \brief Get xPSR Register
+
+ This function returns the content of the xPSR Register.
+
+ \return xPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_xPSR(void)
+{
+ register uint32_t __regXPSR __ASM("xpsr");
+ return(__regXPSR);
+}
+
+
+/** \brief Get Process Stack Pointer
+
+ This function returns the current value of the Process Stack Pointer (PSP).
+
+ \return PSP Register value
+ */
+__STATIC_INLINE uint32_t __get_PSP(void)
+{
+ register uint32_t __regProcessStackPointer __ASM("psp");
+ return(__regProcessStackPointer);
+}
+
+
+/** \brief Set Process Stack Pointer
+
+ This function assigns the given value to the Process Stack Pointer (PSP).
+
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+ register uint32_t __regProcessStackPointer __ASM("psp");
+ __regProcessStackPointer = topOfProcStack;
+}
+
+
+/** \brief Get Main Stack Pointer
+
+ This function returns the current value of the Main Stack Pointer (MSP).
+
+ \return MSP Register value
+ */
+__STATIC_INLINE uint32_t __get_MSP(void)
+{
+ register uint32_t __regMainStackPointer __ASM("msp");
+ return(__regMainStackPointer);
+}
+
+
+/** \brief Set Main Stack Pointer
+
+ This function assigns the given value to the Main Stack Pointer (MSP).
+
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+ register uint32_t __regMainStackPointer __ASM("msp");
+ __regMainStackPointer = topOfMainStack;
+}
+
+
+/** \brief Get Priority Mask
+
+ This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+ \return Priority Mask value
+ */
+__STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+ register uint32_t __regPriMask __ASM("primask");
+ return(__regPriMask);
+}
+
+
+/** \brief Set Priority Mask
+
+ This function assigns the given value to the Priority Mask Register.
+
+ \param [in] priMask Priority Mask
+ */
+__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+ register uint32_t __regPriMask __ASM("primask");
+ __regPriMask = (priMask);
+}
+
+
+#if (__CORTEX_M >= 0x03)
+
+/** \brief Enable FIQ
+
+ This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq __enable_fiq
+
+
+/** \brief Disable FIQ
+
+ This function disables FIQ interrupts by setting the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq __disable_fiq
+
+
+/** \brief Get Base Priority
+
+ This function returns the current value of the Base Priority register.
+
+ \return Base Priority register value
+ */
+__STATIC_INLINE uint32_t __get_BASEPRI(void)
+{
+ register uint32_t __regBasePri __ASM("basepri");
+ return(__regBasePri);
+}
+
+
+/** \brief Set Base Priority
+
+ This function assigns the given value to the Base Priority register.
+
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
+{
+ register uint32_t __regBasePri __ASM("basepri");
+ __regBasePri = (basePri & 0xff);
+}
+
+
+/** \brief Get Fault Mask
+
+ This function returns the current value of the Fault Mask register.
+
+ \return Fault Mask register value
+ */
+__STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+ register uint32_t __regFaultMask __ASM("faultmask");
+ return(__regFaultMask);
+}
+
+
+/** \brief Set Fault Mask
+
+ This function assigns the given value to the Fault Mask register.
+
+ \param [in] faultMask Fault Mask value to set
+ */
+__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ register uint32_t __regFaultMask __ASM("faultmask");
+ __regFaultMask = (faultMask & (uint32_t)1);
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+#if (__CORTEX_M == 0x04)
+
+/** \brief Get FPSCR
+
+ This function returns the current value of the Floating Point Status/Control register.
+
+ \return Floating Point Status/Control register value
+ */
+__STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ register uint32_t __regfpscr __ASM("fpscr");
+ return(__regfpscr);
+#else
+ return(0);
+#endif
+}
+
+
+/** \brief Set FPSCR
+
+ This function assigns the given value to the Floating Point Status/Control register.
+
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ register uint32_t __regfpscr __ASM("fpscr");
+ __regfpscr = (fpscr);
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04) */
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+
+#include
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+
+#include
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/** \brief Enable IRQ Interrupts
+
+ This function enables IRQ interrupts by clearing the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
+{
+ __ASM volatile ("cpsie i");
+}
+
+
+/** \brief Disable IRQ Interrupts
+
+ This function disables IRQ interrupts by setting the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
+{
+ __ASM volatile ("cpsid i");
+}
+
+
+/** \brief Get Control Register
+
+ This function returns the content of the Control Register.
+
+ \return Control Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Set Control Register
+
+ This function writes the given value to the Control Register.
+
+ \param [in] control Control Register value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+ __ASM volatile ("MSR control, %0" : : "r" (control) );
+}
+
+
+/** \brief Get IPSR Register
+
+ This function returns the content of the IPSR Register.
+
+ \return IPSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Get APSR Register
+
+ This function returns the content of the APSR Register.
+
+ \return APSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Get xPSR Register
+
+ This function returns the content of the xPSR Register.
+
+ \return xPSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Get Process Stack Pointer
+
+ This function returns the current value of the Process Stack Pointer (PSP).
+
+ \return PSP Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, psp\n" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Set Process Stack Pointer
+
+ This function assigns the given value to the Process Stack Pointer (PSP).
+
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) );
+}
+
+
+/** \brief Get Main Stack Pointer
+
+ This function returns the current value of the Main Stack Pointer (MSP).
+
+ \return MSP Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Set Main Stack Pointer
+
+ This function assigns the given value to the Main Stack Pointer (MSP).
+
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) );
+}
+
+
+/** \brief Get Priority Mask
+
+ This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+ \return Priority Mask value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Set Priority Mask
+
+ This function assigns the given value to the Priority Mask Register.
+
+ \param [in] priMask Priority Mask
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask, %0" : : "r" (priMask) );
+}
+
+
+#if (__CORTEX_M >= 0x03)
+
+/** \brief Enable FIQ
+
+ This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
+{
+ __ASM volatile ("cpsie f");
+}
+
+
+/** \brief Disable FIQ
+
+ This function disables FIQ interrupts by setting the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
+{
+ __ASM volatile ("cpsid f");
+}
+
+
+/** \brief Get Base Priority
+
+ This function returns the current value of the Base Priority register.
+
+ \return Base Priority register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Set Base Priority
+
+ This function assigns the given value to the Base Priority register.
+
+ \param [in] basePri Base Priority value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
+{
+ __ASM volatile ("MSR basepri, %0" : : "r" (value) );
+}
+
+
+/** \brief Get Fault Mask
+
+ This function returns the current value of the Fault Mask register.
+
+ \return Fault Mask register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Set Fault Mask
+
+ This function assigns the given value to the Fault Mask register.
+
+ \param [in] faultMask Fault Mask value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+#if (__CORTEX_M == 0x04)
+
+/** \brief Get FPSCR
+
+ This function returns the current value of the Floating Point Status/Control register.
+
+ \return Floating Point Status/Control register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ uint32_t result;
+
+ __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+ return(result);
+#else
+ return(0);
+#endif
+}
+
+
+/** \brief Set FPSCR
+
+ This function assigns the given value to the Floating Point Status/Control register.
+
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) );
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04) */
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all instrinsics,
+ * Including the CMSIS ones.
+ */
+
+#endif
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+#endif /* __CORE_CMFUNC_H */
diff --git a/bsp/nuvoton_m451/Libraries/CMSIS/Include/core_cmInstr.h b/bsp/nuvoton_m451/Libraries/CMSIS/Include/core_cmInstr.h
new file mode 100644
index 0000000000000000000000000000000000000000..597e64df04408c0085d031977eaa574648f8cf9c
--- /dev/null
+++ b/bsp/nuvoton_m451/Libraries/CMSIS/Include/core_cmInstr.h
@@ -0,0 +1,618 @@
+/**************************************************************************//**
+ * @file core_cmInstr.h
+ * @brief CMSIS Cortex-M Core Instruction Access Header File
+ * @version V3.01
+ * @date 06. March 2012
+ *
+ * @note
+ * Copyright (C) 2009-2012 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers. This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+#ifndef __CORE_CMINSTR_H
+#define __CORE_CMINSTR_H
+
+
+/* ########################## Core Instruction Access ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+ Access to dedicated instructions
+ @{
+*/
+
+#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#if (__ARMCC_VERSION < 400677)
+ #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+
+/** \brief No Operation
+
+ No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP __nop
+
+
+/** \brief Wait For Interrupt
+
+ Wait For Interrupt is a hint instruction that suspends execution
+ until one of a number of events occurs.
+ */
+#define __WFI __wfi
+
+
+/** \brief Wait For Event
+
+ Wait For Event is a hint instruction that permits the processor to enter
+ a low-power state until one of a number of events occurs.
+ */
+#define __WFE __wfe
+
+
+/** \brief Send Event
+
+ Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV __sev
+
+
+/** \brief Instruction Synchronization Barrier
+
+ Instruction Synchronization Barrier flushes the pipeline in the processor,
+ so that all instructions following the ISB are fetched from cache or
+ memory, after the instruction has been completed.
+ */
+#define __ISB() __isb(0xF)
+
+
+/** \brief Data Synchronization Barrier
+
+ This function acts as a special kind of Data Memory Barrier.
+ It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB() __dsb(0xF)
+
+
+/** \brief Data Memory Barrier
+
+ This function ensures the apparent order of the explicit memory operations before
+ and after the instruction, without ensuring their completion.
+ */
+#define __DMB() __dmb(0xF)
+
+
+/** \brief Reverse byte order (32 bit)
+
+ This function reverses the byte order in integer value.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REV __rev
+
+
+/** \brief Reverse byte order (16 bit)
+
+ This function reverses the byte order in two unsigned short values.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
+{
+ rev16 r0, r0
+ bx lr
+}
+
+
+/** \brief Reverse byte order in signed short value
+
+ This function reverses the byte order in a signed short value with sign extension to integer.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
+{
+ revsh r0, r0
+ bx lr
+}
+
+
+/** \brief Rotate Right in unsigned value (32 bit)
+
+ This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+
+ \param [in] value Value to rotate
+ \param [in] value Number of Bits to rotate
+ \return Rotated value
+ */
+#define __ROR __ror
+
+
+#if (__CORTEX_M >= 0x03)
+
+/** \brief Reverse bit order of value
+
+ This function reverses the bit order of the given value.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __RBIT __rbit
+
+
+/** \brief LDR Exclusive (8 bit)
+
+ This function performs a exclusive LDR command for 8 bit value.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
+
+
+/** \brief LDR Exclusive (16 bit)
+
+ This function performs a exclusive LDR command for 16 bit values.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
+
+
+/** \brief LDR Exclusive (32 bit)
+
+ This function performs a exclusive LDR command for 32 bit values.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
+
+
+/** \brief STR Exclusive (8 bit)
+
+ This function performs a exclusive STR command for 8 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXB(value, ptr) __strex(value, ptr)
+
+
+/** \brief STR Exclusive (16 bit)
+
+ This function performs a exclusive STR command for 16 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXH(value, ptr) __strex(value, ptr)
+
+
+/** \brief STR Exclusive (32 bit)
+
+ This function performs a exclusive STR command for 32 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXW(value, ptr) __strex(value, ptr)
+
+
+/** \brief Remove the exclusive lock
+
+ This function removes the exclusive lock which is created by LDREX.
+
+ */
+#define __CLREX __clrex
+
+
+/** \brief Signed Saturate
+
+ This function saturates a signed value.
+
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+#define __SSAT __ssat
+
+
+/** \brief Unsigned Saturate
+
+ This function saturates an unsigned value.
+
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+#define __USAT __usat
+
+
+/** \brief Count leading zeros
+
+ This function counts the number of leading zeros of a data value.
+
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+#define __CLZ __clz
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+
+#include
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+
+#include
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/** \brief No Operation
+
+ No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)
+{
+ __ASM volatile ("nop");
+}
+
+
+/** \brief Wait For Interrupt
+
+ Wait For Interrupt is a hint instruction that suspends execution
+ until one of a number of events occurs.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)
+{
+ __ASM volatile ("wfi");
+}
+
+
+/** \brief Wait For Event
+
+ Wait For Event is a hint instruction that permits the processor to enter
+ a low-power state until one of a number of events occurs.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)
+{
+ __ASM volatile ("wfe");
+}
+
+
+/** \brief Send Event
+
+ Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)
+{
+ __ASM volatile ("sev");
+}
+
+
+/** \brief Instruction Synchronization Barrier
+
+ Instruction Synchronization Barrier flushes the pipeline in the processor,
+ so that all instructions following the ISB are fetched from cache or
+ memory, after the instruction has been completed.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)
+{
+ __ASM volatile ("isb");
+}
+
+
+/** \brief Data Synchronization Barrier
+
+ This function acts as a special kind of Data Memory Barrier.
+ It completes when all explicit memory accesses before this instruction complete.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)
+{
+ __ASM volatile ("dsb");
+}
+
+
+/** \brief Data Memory Barrier
+
+ This function ensures the apparent order of the explicit memory operations before
+ and after the instruction, without ensuring their completion.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)
+{
+ __ASM volatile ("dmb");
+}
+
+
+/** \brief Reverse byte order (32 bit)
+
+ This function reverses the byte order in integer value.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );
+ return(result);
+}
+
+
+/** \brief Reverse byte order (16 bit)
+
+ This function reverses the byte order in two unsigned short values.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );
+ return(result);
+}
+
+
+/** \brief Reverse byte order in signed short value
+
+ This function reverses the byte order in a signed short value with sign extension to integer.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );
+ return(result);
+}
+
+
+/** \brief Rotate Right in unsigned value (32 bit)
+
+ This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+
+ \param [in] value Value to rotate
+ \param [in] value Number of Bits to rotate
+ \return Rotated value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+
+ __ASM volatile ("ror %0, %0, %1" : "+r" (op1) : "r" (op2) );
+ return(op1);
+}
+
+
+#if (__CORTEX_M >= 0x03)
+
+/** \brief Reverse bit order of value
+
+ This function reverses the bit order of the given value.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+ return(result);
+}
+
+
+/** \brief LDR Exclusive (8 bit)
+
+ This function performs a exclusive LDR command for 8 bit value.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
+{
+ uint8_t result;
+
+ __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );
+ return(result);
+}
+
+
+/** \brief LDR Exclusive (16 bit)
+
+ This function performs a exclusive LDR command for 16 bit values.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
+{
+ uint16_t result;
+
+ __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );
+ return(result);
+}
+
+
+/** \brief LDR Exclusive (32 bit)
+
+ This function performs a exclusive LDR command for 32 bit values.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );
+ return(result);
+}
+
+
+/** \brief STR Exclusive (8 bit)
+
+ This function performs a exclusive STR command for 8 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strexb %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
+ return(result);
+}
+
+
+/** \brief STR Exclusive (16 bit)
+
+ This function performs a exclusive STR command for 16 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strexh %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
+ return(result);
+}
+
+
+/** \brief STR Exclusive (32 bit)
+
+ This function performs a exclusive STR command for 32 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strex %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
+ return(result);
+}
+
+
+/** \brief Remove the exclusive lock
+
+ This function removes the exclusive lock which is created by LDREX.
+
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)
+{
+ __ASM volatile ("clrex");
+}
+
+
+/** \brief Signed Saturate
+
+ This function saturates a signed value.
+
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+#define __SSAT(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+
+/** \brief Unsigned Saturate
+
+ This function saturates an unsigned value.
+
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+#define __USAT(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+
+/** \brief Count leading zeros
+
+ This function counts the number of leading zeros of a data value.
+
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)
+{
+ uint8_t result;
+
+ __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
+ return(result);
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
+ * Including the CMSIS ones.
+ */
+
+#endif
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+#endif /* __CORE_CMINSTR_H */
diff --git a/bsp/nuvoton_m451/Libraries/CMSIS/Include/core_sc000.h b/bsp/nuvoton_m451/Libraries/CMSIS/Include/core_sc000.h
new file mode 100644
index 0000000000000000000000000000000000000000..39ee60c5e526e2f01c525e1065b3afe774f3430c
--- /dev/null
+++ b/bsp/nuvoton_m451/Libraries/CMSIS/Include/core_sc000.h
@@ -0,0 +1,798 @@
+/**************************************************************************//**
+ * @file core_sc000.h
+ * @brief CMSIS SC000 Core Peripheral Access Layer Header File
+ * @version V3.01
+ * @date 22. March 2012
+ *
+ * @note
+ * Copyright (C) 2009-2012 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers. This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#endif
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __CORE_SC000_H_GENERIC
+#define __CORE_SC000_H_GENERIC
+
+/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/** \ingroup SC000
+ @{
+ */
+
+/* CMSIS SC000 definitions */
+#define __SC000_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
+#define __SC000_CMSIS_VERSION_SUB (0x01) /*!< [15:0] CMSIS HAL sub version */
+#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16) | \
+ __SC000_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
+
+#define __CORTEX_SC (0) /*!< Cortex secure core */
+
+
+#if defined ( __CC_ARM )
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
+ #define __STATIC_INLINE static __inline
+
+#elif defined ( __ICCARM__ )
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __GNUC__ )
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TASKING__ )
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */
+ #define __STATIC_INLINE static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
+*/
+#define __FPU_USED 0
+
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+#endif
+
+#include /* standard types definitions */
+#include /* Core Instruction Access */
+#include /* Core Function Access */
+
+#endif /* __CORE_SC000_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_SC000_H_DEPENDANT
+#define __CORE_SC000_H_DEPENDANT
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __SC000_REV
+ #define __SC000_REV 0x0000
+ #warning "__SC000_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 2
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ IO Type Qualifiers are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/*@} end of group SC000 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core MPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/** \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+#if (__CORTEX_M != 0x04)
+ uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
+#else
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
+#endif
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+
+/** \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+
+/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+#if (__CORTEX_M != 0x04)
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+#else
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
+#endif
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+
+/** \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
+ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[31];
+ __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[31];
+ __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[31];
+ __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[31];
+ uint32_t RESERVED4[64];
+ __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
+} NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/** \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ uint32_t RESERVED0[1];
+ __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
+ __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ uint32_t RESERVED1[154];
+ __IO uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/* SCB Security Features Register Definitions */
+#define SCB_SFCR_UNIBRTIMING_Pos 0 /*!< SCB SFCR: UNIBRTIMING Position */
+#define SCB_SFCR_UNIBRTIMING_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SFCR: UNIBRTIMING Mask */
+
+#define SCB_SFCR_SECKEY_Pos 16 /*!< SCB SFCR: SECKEY Position */
+#define SCB_SFCR_SECKEY_Msk (0xFFFFUL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SFCR: SECKEY Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/** \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[2];
+ __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/** \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/** \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR)
+ are only accessible over DAP and not via processor. Therefore
+ they are not covered by the Cortex-M0 header file.
+ @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of SC000 Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+
+#if (__MPU_PRESENT == 1)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 )
+#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) )
+#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) )
+
+
+/** \brief Enable External Interrupt
+
+ The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief Disable External Interrupt
+
+ The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief Get Pending Interrupt
+
+ The function reads the pending register in the NVIC and returns the pending bit
+ for the specified interrupt.
+
+ \param [in] IRQn Interrupt number.
+
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
+}
+
+
+/** \brief Set Pending Interrupt
+
+ The function sets the pending bit of an external interrupt.
+
+ \param [in] IRQn Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief Clear Pending Interrupt
+
+ The function clears the pending bit of an external interrupt.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief Set Interrupt Priority
+
+ The function sets the priority of an interrupt.
+
+ \note The priority cannot be set for every core interrupt.
+
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if(IRQn < 0) {
+ SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+ (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+ else {
+ NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+ (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+}
+
+
+/** \brief Get Interrupt Priority
+
+ The function reads the priority of an interrupt. The interrupt
+ number can be positive to specify an external (device specific)
+ interrupt, or negative to specify an internal (core) interrupt.
+
+
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority. Value is aligned automatically to the implemented
+ priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if(IRQn < 0) {
+ return((uint32_t)((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for SC000 system interrupts */
+ else {
+ return((uint32_t)((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
+}
+
+
+/** \brief System Reset
+
+ The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+ SCB_AIRCR_SYSRESETREQ_Msk);
+ __DSB(); /* Ensure completion of memory access */
+ while(1); /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief System Tick Configuration
+
+ The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+
+ \param [in] ticks Number of ticks between two interrupts.
+
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function SysTick_Config is not included. In this case, the file device.h
+ must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
+
+ SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#endif /* __CORE_SC000_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/bsp/nuvoton_m451/Libraries/CMSIS/Include/core_sc300.h b/bsp/nuvoton_m451/Libraries/CMSIS/Include/core_sc300.h
new file mode 100644
index 0000000000000000000000000000000000000000..7e56b0f3322a7136ed47ee38ad024d08787703d3
--- /dev/null
+++ b/bsp/nuvoton_m451/Libraries/CMSIS/Include/core_sc300.h
@@ -0,0 +1,1583 @@
+/**************************************************************************//**
+ * @file core_sc300.h
+ * @brief CMSIS SC300 Core Peripheral Access Layer Header File
+ * @version V3.01
+ * @date 22. March 2012
+ *
+ * @note
+ * Copyright (C) 2009-2012 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers. This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#endif
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __CORE_SC300_H_GENERIC
+#define __CORE_SC300_H_GENERIC
+
+/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/** \ingroup SC3000
+ @{
+ */
+
+/* CMSIS SC300 definitions */
+#define __SC300_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
+#define __SC300_CMSIS_VERSION_SUB (0x01) /*!< [15:0] CMSIS HAL sub version */
+#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16) | \
+ __SC300_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
+
+#define __CORTEX_SC (300) /*!< Cortex secure core */
+
+
+#if defined ( __CC_ARM )
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
+ #define __STATIC_INLINE static __inline
+
+#elif defined ( __ICCARM__ )
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __GNUC__ )
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TASKING__ )
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */
+ #define __STATIC_INLINE static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
+*/
+#define __FPU_USED 0
+
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+#endif
+
+#include /* standard types definitions */
+#include /* Core Instruction Access */
+#include /* Core Function Access */
+
+#endif /* __CORE_SC300_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_SC300_H_DEPENDANT
+#define __CORE_SC300_H_DEPENDANT
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __SC300_REV
+ #define __SC300_REV 0x0000
+ #warning "__SC300_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 4
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ IO Type Qualifiers are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/*@} end of group SC300 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/** \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+#if (__CORTEX_M != 0x04)
+ uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
+#else
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
+#endif
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+
+/** \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+
+/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+#if (__CORTEX_M != 0x04)
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+#else
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
+#endif
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+
+/** \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
+ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[24];
+ __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[24];
+ __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[24];
+ __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[24];
+ __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[56];
+ __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED5[644];
+ __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/** \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ uint32_t RESERVED0[5];
+ __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */
+#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
+
+#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Registers Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* SCB Hard Fault Status Registers Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/** \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1];
+ __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+ uint32_t RESERVED1[1];
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/** \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+ __O union
+ {
+ __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864];
+ __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15];
+ __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15];
+ __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[29];
+ __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
+ __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
+ __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
+ uint32_t RESERVED4[43];
+ __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[6];
+ __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
+ __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED0[1];
+ __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
+ __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED1[1];
+ __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
+ __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED2[1];
+ __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
+ __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/** \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2];
+ __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55];
+ __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131];
+ __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
+ uint32_t RESERVED3[759];
+ __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
+ __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
+ __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
+ uint32_t RESERVED4[1];
+ __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
+ __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
+ __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39];
+ __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8];
+ __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
+ __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/** \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+ __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
+ __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
+ __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
+ __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
+ __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
+ __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/** \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register */
+#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Cortex-M3 Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
+
+#if (__MPU_PRESENT == 1)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+/** \brief Set Priority Grouping
+
+ The function sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << 8)); /* Insert write key and priorty group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/** \brief Get Priority Grouping
+
+ The function reads the priority grouping field from the NVIC Interrupt Controller.
+
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
+{
+ return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */
+}
+
+
+/** \brief Enable External Interrupt
+
+ The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
+}
+
+
+/** \brief Disable External Interrupt
+
+ The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
+}
+
+
+/** \brief Get Pending Interrupt
+
+ The function reads the pending register in the NVIC and returns the pending bit
+ for the specified interrupt.
+
+ \param [in] IRQn Interrupt number.
+
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
+}
+
+
+/** \brief Set Pending Interrupt
+
+ The function sets the pending bit of an external interrupt.
+
+ \param [in] IRQn Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
+}
+
+
+/** \brief Clear Pending Interrupt
+
+ The function clears the pending bit of an external interrupt.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief Get Active Interrupt
+
+ The function reads the active register in NVIC and returns the active bit.
+
+ \param [in] IRQn Interrupt number.
+
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ */
+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+ return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
+}
+
+
+/** \brief Set Interrupt Priority
+
+ The function sets the priority of an interrupt.
+
+ \note The priority cannot be set for every core interrupt.
+
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if(IRQn < 0) {
+ SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */
+ else {
+ NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */
+}
+
+
+/** \brief Get Interrupt Priority
+
+ The function reads the priority of an interrupt. The interrupt
+ number can be positive to specify an external (device specific)
+ interrupt, or negative to specify an internal (core) interrupt.
+
+
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority. Value is aligned automatically to the implemented
+ priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if(IRQn < 0) {
+ return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */
+ else {
+ return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
+}
+
+
+/** \brief Encode Priority
+
+ The function encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set.
+
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+ SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+ return (
+ ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
+ ((SubPriority & ((1 << (SubPriorityBits )) - 1)))
+ );
+}
+
+
+/** \brief Decode Priority
+
+ The function decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
+
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+ SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
+ *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);
+}
+
+
+/** \brief System Reset
+
+ The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+ while(1); /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief System Tick Configuration
+
+ The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+
+ \param [in] ticks Number of ticks between two interrupts.
+
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function SysTick_Config is not included. In this case, the file device.h
+ must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
+
+ SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_core_DebugFunctions ITM Functions
+ \brief Functions that access the ITM debug interface.
+ @{
+ */
+
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
+#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/** \brief ITM Send Character
+
+ The function transmits a character via the ITM channel 0, and
+ \li Just returns when no debugger is connected that has booked the output.
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+
+ \param [in] ch Character to transmit.
+
+ \returns Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+ if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */
+ (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */
+ {
+ while (ITM->PORT[0].u32 == 0);
+ ITM->PORT[0].u8 = (uint8_t) ch;
+ }
+ return (ch);
+}
+
+
+/** \brief ITM Receive Character
+
+ The function inputs a character via the external variable \ref ITM_RxBuffer.
+
+ \return Received character.
+ \return -1 No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
+ int32_t ch = -1; /* no character available */
+
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+ ch = ITM_RxBuffer;
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
+ }
+
+ return (ch);
+}
+
+
+/** \brief ITM Check Character
+
+ The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+
+ \return 0 No character available.
+ \return 1 Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void) {
+
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
+ return (0); /* no character available */
+ } else {
+ return (1); /* character available */
+ }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+#endif /* __CORE_SC300_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/bsp/nuvoton_m451/Libraries/Device/Nuvoton/M451Series/Include/M451Series.h b/bsp/nuvoton_m451/Libraries/Device/Nuvoton/M451Series/Include/M451Series.h
new file mode 100644
index 0000000000000000000000000000000000000000..4aaa3781aa8a34cc53cd7446c48a2db8843a4c04
--- /dev/null
+++ b/bsp/nuvoton_m451/Libraries/Device/Nuvoton/M451Series/Include/M451Series.h
@@ -0,0 +1,17150 @@
+/******************************************************************************
+ * @file M451Series.h
+ * @version V3.10
+ * $Revision: 179 $
+ * $Date: 15/09/04 3:45p $
+ * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File for M451 Series MCU
+ *
+ * @note
+ * Copyright (C) 2014~2015 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+
+
+/**
+ \mainpage Introduction
+ *
+ *
+ * This user manual describes the usage of M451 Series MCU device driver
+ *
+ * Disclaimer
+ *
+ * The Software is furnished "AS IS", without warranty as to performance or results, and
+ * the entire risk as to performance or results is assumed by YOU. Nuvoton disclaims all
+ * warranties, express, implied or otherwise, with regard to the Software, its use, or
+ * operation, including without limitation any and all warranties of merchantability, fitness
+ * for a particular purpose, and non-infringement of intellectual property rights.
+ *
+ * Copyright Notice
+ *
+ * Copyright (C) 2014~2015 Nuvoton Technology Corp. All rights reserved.
+ */
+
+/**
+ * \page PG_REV Revision History
+ *
+ * Revision 3.01.001
+ * \li Added Nu-LB-M451, NuEdu and USB device sample code.
+ * \li Added a lacking macro SYS_IS_LVR_RST() to SYS driver.
+ * \li Added a sample code DAC_PDMA_ScatterGather_PWMTrigger to use PDMA scatter gather mode and trigger DAC by PWM.
+ * \li Added counter type constant definitions: PWM_UP_COUNTER, PWM_DOWN_COUNTER, and PWM_UP_DOWN_COUNTER.
+ * \li Added DAC_PDMA_PWMTrigger sample code to use PDMA and trigger DAC by PWM.
+ * \li Added a sample code EADC_PDMA_PWM_Trigger to trigger EADC with PWM and copy result by PDMA.
+ * \li Added a new function to control systick and select systick clock source CLK_EnableSysTick() and CLK_DisableSysTick() in CLK driver.
+ * \li Added 'NMIEN' and 'NMISTS' control registers to M451Series.h for NMI control.
+ * \li Added PDMA_ScatterGather_PingPongBuffer sample code to create ping-pong buffer with PDMA scatter gather mode.
+ * \li Added 'PE_DRVCTL' register of GPIO to M451Series.h for GPIO driving strength control.
+ * \li Added a sample code PWM_PDMA_Capture to transfer PWM capture data by PDMA.
+ * \li Added SCLIB_ActivateDelay API for initial SC with non-standard H/W design in SC driver
+ * \li Fixed the bug of EADC_IS_INT_FLAG_OV() that accesses the incorrect register.
+ * \li Fixed the bug of EADC_IS_SAMPLE_MODULE_OV() that accesses the incorrect register.
+ * \li Fixed the bug of EADC_SetExtendSampleTime() for position shift error in EADC driver.
+ * \li Fixed the bug of EADC_SetTriggerDelayTime() for position shift error in EADC driver.
+ * \li Fixed the bug of PWM_ENABLE_OUTPUT_INVERTER () that output inverter function cannot be disabled.
+ * \li Fixed the bug of PWM_MASK_OUTPUT() in PWM driver that mask function cannot be disabled.
+ * \li Fixed CAN_STATUS_LEC_Msk from 0x03 to 0x07.
+ * \li Fixed the bug of CLK_SysTickDelay() that COUNTFLAG may not be cleared in CLK driver.
+ * \li Fixed CTL and PINCTL regsiter synchronize issue by waiting synchronized ready flag in SC driver.
+ * \li Fixed DAC_SetDelayTime() calculation error in DAC driver because the dac->TCTL only used 10 bits, not 14 bits.
+ * \li Fixed EADC_CMP_ADCMPIE_DISABLE definition error.
+ * \li Fixed EADC_CMP_ADCMPIE_DISABLE definition error.
+ * \li Fixed IAR entry point from __iar_program_start to Reset_Handler
+ * \li Fixed PWM_ConfigOutputChannel() return value bug in PWM driver.
+ * \li Fixed the bug of PWM_ConfigSyncPhase() that cannot configure synchronized source for channel2~5.
+ * \li Fixed SC_SET_STOP_BIT_LEN definition error.
+ * \li Fixed SCUART baudrate return error in SCUART_Open and SCUART_SetLineConfig API of SCUART driver.
+ * \li Fixed SCUART_PARITY_NONE/SCUART_PARITY_EVEN/SCUART_PARITY_ODD definition bug in SCUART driver.
+ * \li Fixed u32DataWidth setting error by sc->UARTCTL in SCUART_SetLineConfig API of SCUART driver.
+ * \li Fixed SMBD_Enable constant value definition error in I2C driver.
+ * \li Fixed the problem that MSC device detection is aborted due to REQUEST_SENSE command not ready.
+ * \li Fixed UART clock setting bug in UART_Open(), UART_SetLine_Config() and UART_SelectIrDAMode() of UART driver.
+ * \li Improved compatibility of USBH driver for pen driver.
+ * \li Improved EADC_ConfigSampleModule() to support rising and falling trigger at the same time.
+ * \li Improved EBI_SRAM sample code to add PDMA data transfer with EBI.
+ * \li Improved SC driver to support more than one SC port.
+ * \li Improved USBH driver to support composite HID devices
+ * \li Improved USBD driver to support more USB device sample code.
+ * \li Modified I2C_STOP() from #define to inline and add waiting STO bit clear to 0 . This modified is safe for next START coming soon.
+ * \li Removed CRC clock enabled in CRC_Open(). User should enable CRC clock in system initialization before any CRC operation.
+ * \li Removed FMC_ReadDID() in FMC driver. This function was no longer supported.
+ * \li Removed I2C_CTL_STA_STO_SI and I2C_CTL_STA_STO_SI_AA definitions to avoid STOP and START write to control bit at the same time.
+ *
+ * Revision 3.00.005
+ * \li Fixed EADC_CTL_DMOF_STRAIGHT_BINARY and EADC_CTL_DMOF_TWOS_COMPLEMENT definition error in EADC driver.
+ * \li Fixed EADC_FALLING_EDGE_TRIGGER definition error in EADC driver.
+ * \li Fixed EADC_RISING_EDGE_TRIGGER definition error in EADC driver.
+ * \li Fixed UART transmit data bug in UART_TEST_HANDLE() of UART_TxRxFunction sample code.
+ * \li Fixed the data missing bug when BULK IN transfer is end by max packet size packet at last packet in USBD_VCOM sample code.
+ * \li Fixed program user configuration area without erase in USBD_MassStorage_DataFlash sample code.
+ * \li Fixed the bug of switching HCLK to HIRC before enabling PLL in CLK_SetCoreClock() of CLK driver.
+ * \li Fixed isochronous transfer bugs of USB Host library.
+ * \li Fixed Clear Modem Status Interrupt flag bug in UART_ClearIntFlag() of UART driver.
+ * \li Fixed the time-out flag clear bug in I2C_ClearTimeoutFlag() of I2C driver.
+ * \li Replaced PERIOD0~5 with PERIOD[6] in PWM_T, and modified PERIOD bit field constant definition in M451Series.h.
+ * \li Replaced CMPDAT0~5 with CMPDAT0[6] in PWM_T, and modified CMPDAT bit field constant definition in M451Series.h.
+ * \li Replaced CNT0~5 with CNT[6] in PWM_T, and modified CNT bit field constant definition in M451Series.h.
+ * \li Replaced PBUF0~5 with PBUF[6] in PWM_T, and modified PBUF bit field constant definition in M451Series.h.
+ * \li Replaced CMPBUF0~5 with CMPBUF[6] in PWM_T, and modified CMPBUF bit field constant definition in M451Series.h.
+ * \li Replaced CURSCAT0~CURSCAT11 with CURSCAT[12] in PDMA_T of M451Series.h.
+ * \li Modified CLK_WaitClockReady() time-out to about 300 ms in CLK driver.
+ * \li Updated USB USBD_MassStorage_DataFlash sample code and USB Driver to pass USB-IF MSC test. (The MassStorage size must be greater than 64 KB; otherwise, Command Set test will fail in MSC test).
+ * \li Replaced old HID library file (open source) with Nuvoton HID library in USB Host library.
+ * \li Added USBH_Audio_Class and USBH_UAC_HID sample code for USB Host to support UAC + HID device.
+ *
+ * Revision 3.00.004
+ * \li Fixed the time-out from 5 ms to 300 ms in CLK_WaitClockReady() of CLK driver.
+ * \li Fixed the bug of UART_ClearIntFlag() in UART driver to only clear one flag at one time.
+ * \li Fixed the missing parameter, UART clock source LXT, for CLK_SetModuleClock() in UART driver.
+ * \li Fixed the bug of clearing data and CTS wake-up flag to clear one flag at one time in UART1_IRQHandler() of UART_Wakeup sample code.
+ * \li Fixed the bug of RS485_HANDLE() in the UART_RS485_Slave sample code to only clear one flag at one time.
+ * \li Fixed the bug of clearing auto baud rate detect finished and time-out flag to clear one flag at one time in AutoBaudRate_RxTest() of UART_AutoBaudRate_Slave sample code.
+ * \li Fixed NVIC_EnableIRQ() to NVIC_DisableIRQ() after chip wake-up in I2C_Wakeup_Slave sample code.
+ * \li Fixed multi-function setting error of SC CD pin in USBD_CCID sample code.
+ * \li Fixed PD.7 (Headphone output control pin) output mode configuration in WAU8822_Setup() of USBD_Audio_NAU8822 sample code.
+ * \li Fixed wrong CLK_WaitClockReady parameter in I2C_GCMode_Slave sample code.
+ * \li Fixed UART data transfer bug of USBD_VCOM sample code.
+ * \li Updated CLK driver to avoid HIRC force enabled in CLK_SetHCLK() and CLK_SetCoreClock().
+ * \li Updated USBD driver to pass USB-IF MSC test.
+ * \li Updated USBD_MassStorage_DataFlash sample code to pass USB-IF MSC test.
+ * \li Updated driver of VCOM for win8 certification in USBD_VCOM sample code.
+ * \li Added HID Media key supporting in USBD_Audio_HID_NAU8822 sample code.
+ * \li Added new sample code USBH_UAC_HID of USB Host to support UAC + HID device.
+ * \li Added new sample code USBH_Audio_Class to support USB audio class device (UAC).
+ *
+ * Revision 3.00.003
+ * \li Added USBD_Audio_HID_NAU8822 sample code.
+ *
+ * Revision 3.00.002
+ * \li Fixed serial number code in device descriptor.
+ * \li Fixed EBI_Open API did not perform u32CSActiveLevel parameters to set CS pin polar.
+ * \li Fixed SMBus bus time-out and Clock Lo time-out API.
+ * \li Fixed I2C0,1 IP reset of SYS_IPRST1.
+ * \li Fixed include path of CMSIS.
+ * \li Fixed SPI_CLR_UNIT_TRANS_INT_FLAG( ) definition.
+ * \li Fixed USBD_INT_WAKEUP definition.
+ * \li Modified USBD driver to support USB remote wake-up function.
+ *
+ * Revision 3.00.001
+ * \li Initial Release.
+*/
+
+#ifndef __M451SERIES_H__
+#define __M451SERIES_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/******************************************************************************/
+/* Processor and Core Peripherals */
+/******************************************************************************/
+/** @addtogroup CMSIS Device CMSIS Definitions
+ Configuration of the Cortex-M4 Processor and Core Peripherals
+ @{
+*/
+
+/*
+ * ==========================================================================
+ * ---------- Interrupt Number Definition -----------------------------------
+ * ==========================================================================
+ */
+
+typedef enum IRQn
+{
+ /****** Cortex-M4 Processor Exceptions Numbers ***************************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
+ MemoryManagement_IRQn = -12, /*!< 4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< 5 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< 6 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 System Tick Interrupt */
+
+ /****** M451 Specific Interrupt Numbers ********************************************************/
+
+ BOD_IRQn = 0, /*!< Brown Out detection Interrupt */
+ IRC_IRQn = 1, /*!< Internal RC Interrupt */
+ PWRWU_IRQn = 2, /*!< Power Down Wake Up Interrupt */
+ RAMPE_IRQn = 3, /*!< SRAM parity check failed Interrupt */
+ CKFAIL_IRQn = 4, /*!< Clock failed Interrupt */
+ RTC_IRQn = 6, /*!< Real Time Clock Interrupt */
+ TAMPER_IRQn = 7, /*!< Tamper detection Interrupt */
+ WDT_IRQn = 8, /*!< Watchdog Timer Interrupt */
+ WWDT_IRQn = 9, /*!< Window Watchdog Timer Interrupt */
+ EINT0_IRQn = 10, /*!< External Input 0 Interrupt */
+ EINT1_IRQn = 11, /*!< External Input 1 Interrupt */
+ EINT2_IRQn = 12, /*!< External Input 2 Interrupt */
+ EINT3_IRQn = 13, /*!< External Input 3 Interrupt */
+ EINT4_IRQn = 14, /*!< External Input 4 Interrupt */
+ EINT5_IRQn = 15, /*!< External Input 5 Interrupt */
+ GPA_IRQn = 16, /*!< GPIO Port A Interrupt */
+ GPB_IRQn = 17, /*!< GPIO Port B Interrupt */
+ GPC_IRQn = 18, /*!< GPIO Port C Interrupt */
+ GPD_IRQn = 19, /*!< GPIO Port D Interrupt */
+ GPE_IRQn = 20, /*!< GPIO Port E Interrupt */
+ GPF_IRQn = 21, /*!< GPIO Port F Interrupt */
+ SPI0_IRQn = 22, /*!< SPI0 Interrupt */
+ SPI1_IRQn = 23, /*!< SPI1 Interrupt */
+ BRAKE0_IRQn = 24, /*!< BRAKE0 Interrupt */
+ PWM0P0_IRQn = 25, /*!< PWM0P0 Interrupt */
+ PWM0P1_IRQn = 26, /*!< PWM0P1 Interrupt */
+ PWM0P2_IRQn = 27, /*!< PWM0P2 Interrupt */
+ BRAKE1_IRQn = 28, /*!< BRAKE1 Interrupt */
+ PWM1P0_IRQn = 29, /*!< PWM1P0 Interrupt */
+ PWM1P1_IRQn = 30, /*!< PWM1P1 Interrupt */
+ PWM1P2_IRQn = 31, /*!< PWM1P2 Interrupt */
+ TMR0_IRQn = 32, /*!< Timer 0 Interrupt */
+ TMR1_IRQn = 33, /*!< Timer 1 Interrupt */
+ TMR2_IRQn = 34, /*!< Timer 2 Interrupt */
+ TMR3_IRQn = 35, /*!< Timer 3 Interrupt */
+ UART0_IRQn = 36, /*!< UART 0 Interrupt */
+ UART1_IRQn = 37, /*!< UART 1 Interrupt */
+ I2C0_IRQn = 38, /*!< I2C 0 Interrupt */
+ I2C1_IRQn = 39, /*!< I2C 1 Interrupt */
+ PDMA_IRQn = 40, /*!< Peripheral DMA Interrupt */
+ DAC_IRQn = 41, /*!< DAC Interrupt */
+ ADC00_IRQn = 42, /*!< ADC0 Source 0 Interrupt */
+ ADC01_IRQn = 43, /*!< ADC0 Source 1 Interrupt */
+ ACMP01_IRQn = 44, /*!< Analog Comparator 0 and 1 Interrupt */
+ ADC02_IRQn = 46, /*!< ADC0 Source 2 Interrupt */
+ ADC03_IRQn = 47, /*!< ADC0 Source 3 Interrupt */
+ UART2_IRQn = 48, /*!< UART2 Interrupt */
+ UART3_IRQn = 49, /*!< UART3 Interrupt */
+ SPI2_IRQn = 51, /*!< SPI2 Interrupt */
+ USBD_IRQn = 53, /*!< USB device Interrupt */
+ USBH_IRQn = 54, /*!< USB host Interrupt */
+ USBOTG_IRQn = 55, /*!< USB OTG Interrupt */
+ CAN0_IRQn = 56, /*!< CAN0 Interrupt */
+ SC0_IRQn = 58, /*!< Smart Card 0 Interrupt */
+ TK_IRQn = 63 /*!< Touch Key Interrupt */
+} IRQn_Type;
+
+
+/*
+ * ==========================================================================
+ * ----------- Processor and Core Peripheral Section ------------------------
+ * ==========================================================================
+ */
+
+/* Configuration of the Cortex-M# Processor and Core Peripherals */
+#define __CM4_REV 0x0201 /*!< Core Revision r2p1 */
+#define __NVIC_PRIO_BITS 4 /*!< Number of Bits used for Priority Levels */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+#define __MPU_PRESENT 1 /*!< MPU present or not */
+#define __FPU_PRESENT 1 /*!< FPU present or not */
+
+/*@}*/ /* end of group CMSIS */
+
+#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
+#include "system_M451Series.h" /* M451 System include file */
+#include
+
+
+
+/******************************************************************************/
+/* Device Specific Peripheral registers structures */
+/******************************************************************************/
+
+/** @addtogroup REGISTER Control Register
+
+ @{
+
+*/
+
+
+/*---------------------- Analog Comparator Controller -------------------------*/
+/**
+ @addtogroup ACMP Analog Comparator Controller(ACMP)
+ Memory Mapped Structure for ACMP Controller
+@{ */
+
+
+typedef struct
+{
+
+
+/**
+ * @var ACMP_T::CTL
+ * Offset: 0x00 Analog Comparator 0 Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |ACMPEN |Comparator Enable Bit
+ * | | |0 = Comparator 0 Disabled.
+ * | | |1 = Comparator 0 Enabled.
+ * |[1] |ACMPIE |Comparator Interrupt Enable Bit
+ * | | |0 = Comparator 0 interrupt Disabled.
+ * | | |1 = Comparator 0 interrupt Enabled.
+ * | | |If WKEN (ACMP_CTL0[16]) is set to 1, the wake-up interrupt function will be enabled as well.
+ * |[2] |HYSEN |Comparator Hysteresis Enable Bit
+ * | | |0 = Comparator 0 hysteresis Disabled.
+ * | | |1 = Comparator 0 hysteresis Enabled.
+ * |[3] |ACMPOINV |Comparator Output Inverse
+ * | | |0 = Comparator 0 output inverse Disabled.
+ * | | |1 = Comparator 0 output inverse Enabled.
+ * |[5:4] |NEGSEL |Comparator Negative Input Selection
+ * | | |00 = ACMP0_N pin.
+ * | | |01 = Internal comparator reference voltage (CRV).
+ * | | |10 = Band-gap voltage.
+ * | | |11 = DAC output.
+ * |[7:6] |POSSEL |Comparator Positive Input Selection
+ * | | |00 = Input from ACMP0_P0.
+ * | | |01 = Input from ACMP0_P1.
+ * | | |10 = Input from ACMP0_P2.
+ * | | |11 = Input from ACMP0_P3.
+ * |[9:8] |INTPOL |Interrupt Condition Polarity Selection
+ * | | |ACMPIF0 will be set to 1 when comparator output edge condition is detected.
+ * | | |00 = Rising edge or falling edge.
+ * | | |01 = Rising edge.
+ * | | |10 = Falling edge.
+ * | | |11 = Reserved.
+ * |[12] |OUTSEL |Comparator Output Select
+ * | | |0 = Comparator 0 output to ACMP0_O pin is unfiltered comparator output.
+ * | | |1 = Comparator 0 output to ACMP0_O pin is from filter output.
+ * |[15:13] |FILTSEL |Comparator Output Filter Count Selection
+ * | | |000 = Filter function is Disabled.
+ * | | |001 = ACMP0 output is sampled 1 consecutive PCLK.
+ * | | |010 = ACMP0 output is sampled 2 consecutive PCLKs.
+ * | | |011 = ACMP0 output is sampled 4 consecutive PCLKs.
+ * | | |100 = ACMP0 output is sampled 8 consecutive PCLKs.
+ * | | |101 = ACMP0 output is sampled 16 consecutive PCLKs.
+ * | | |110 = ACMP0 output is sampled 32 consecutive PCLKs.
+ * | | |111 = ACMP0 output is sampled 64 consecutive PCLKs.
+ * |[16] |WKEN |Power Down Wake-Up Enable Bit
+ * | | |0 = Wake-up function Disabled.
+ * | | |1 = Wake-up function Enabled.
+ * ---------------------------------------------------------------------------------------------------
+ * Offset: 0x04 Analog Comparator 1 Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |ACMPEN |Comparator Enable Bit
+ * | | |0 = Comparator 1 Disabled.
+ * | | |1 = Comparator 1 Enabled.
+ * |[1] |ACMPIE |Comparator Interrupt Enable Bit
+ * | | |0 = Comparator 1 interrupt Disabled.
+ * | | |1 = Comparator 1 interrupt Enabled.
+ * | | |If WKEN (ACMP_CTL1[16]) is set to 1, the wake-up interrupt function will be enabled as well.
+ * |[2] |HYSEN |Comparator Hysteresis Enable Bit
+ * | | |0 = Comparator 1 hysteresis Disabled.
+ * | | |1 = Comparator 1 hysteresis Enabled.
+ * |[3] |ACMPOINV |Comparator Output Inverse Control
+ * | | |0 = Comparator 1 output inverse Disabled.
+ * | | |1 = Comparator 1 output inverse Enabled.
+ * |[5:4] |NEGSEL |Comparator Negative Input Selection
+ * | | |00 = ACMP1_N pin.
+ * | | |01 = Internal comparator reference voltage (CRV).
+ * | | |10 = Band-gap voltage.
+ * | | |11 = DAC output.
+ * |[7:6] |POSSEL |Comparator Positive Input Selection
+ * | | |00 = Input from ACMP1_P0.
+ * | | |01 = Input from ACMP1_P1.
+ * | | |10 = Input from ACMP1_P2.
+ * | | |11 = Input from ACMP1_P3.
+ * |[9:8] |INTPOL |Interrupt Condition Polarity Selection
+ * | | |ACMPIF1 will be set to 1 when comparator output edge condition is detected.
+ * | | |00 = Rising edge or falling edge.
+ * | | |01 = Rising edge.
+ * | | |10 = Falling edge.
+ * | | |11 = Reserved.
+ * |[12] |OUTSEL |Comparator Output Select
+ * | | |0 = Comparator 1 output to ACMP1_O pin is unfiltered comparator output.
+ * | | |1 = Comparator 1 output to ACMP1_O pin is from filter output.
+ * |[15:13] |FILTSEL |Comparator Output Filter Count Selection
+ * | | |000 = Filter function is Disabled.
+ * | | |001 = ACMP1 output is sampled 1 consecutive PCLK.
+ * | | |010 = ACMP1 output is sampled 2 consecutive PCLKs.
+ * | | |011 = ACMP1 output is sampled 4 consecutive PCLKs.
+ * | | |100 = ACMP1 output is sampled 8 consecutive PCLKs.
+ * | | |101 = ACMP1 output is sampled 16 consecutive PCLKs.
+ * | | |110 = ACMP1 output is sampled 32 consecutive PCLKs.
+ * | | |111 = ACMP1 output is sampled 64 consecutive PCLKs.
+ * |[16] |WKEN |Power Down Wakeup Enable Bit
+ * | | |0 = Wake-up function Disabled.
+ * | | |1 = Wake-up function Enabled.
+ * @var ACMP_T::STATUS
+ * Offset: 0x08 Analog Comparator Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |ACMPIF0 |Comparator 0 Interrupt Flag
+ * | | |This bit is set by hardware when the edge condition defined by INTPOL (ACMP_CTL0[9:8]) is detected on comparator 0 output.
+ * | | |This will generate an interrupt if ACMPIE (ACMP_CTL0[1]) is set to 1.
+ * | | |Note: Write 1 to clear this bit to 0.
+ * |[1] |ACMPIF1 |Comparator 1 Interrupt Flag
+ * | | |This bit is set by hardware when the edge condition defined by INTPOL (ACMP_CTL1[9:8]) is detected on comparator 1 output.
+ * | | |This will cause an interrupt if ACMPIE (ACMP_CTL1[1]) is set to 1.
+ * | | |Note: Write 1 to clear this bit to 0.
+ * |[4] |ACMPO0 |Comparator 0 Output
+ * | | |Synchronized to the PCLK to allow reading by software.
+ * | | |Cleared when the comparator 0 is disabled, i.e. ACMPEN (ACMP_CTL0[0]) is cleared to 0.
+ * |[5] |ACMPO1 |Comparator 1 Output
+ * | | |Synchronized to the PCLK to allow reading by software.
+ * | | |Cleared when the comparator 1 is disabled, i.e. ACMPEN (ACMP_CTL1[0]) is cleared to 0.
+ * |[8] |WKIF0 |Comparator 0 Power Down Wake-Up Interrupt Flag
+ * | | |This bit will be set to 1 when ACMP0 wake-up interrupt event occurs.
+ * | | |0 = No power down wake-up occurred.
+ * | | |1 = Power down wake-up occurred.
+ * | | |Note: Write 1 to clear this bit to 0.
+ * |[9] |WKIF1 |Comparator 1 Power Down Wake-Up Interrupt Flag
+ * | | |This bit will be set to 1 when ACMP1 wake-up interrupt event occurs.
+ * | | |0 = No power down wake-up occurred.
+ * | | |1 = Power down wake-up occurred.
+ * | | |Note: Write 1 to clear this bit to 0.
+ * @var ACMP_T::VREF
+ * Offset: 0x0C Analog Comparator Reference Voltage Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[3:0] |CRVCTL |Comparator Reference Voltage Setting
+ * | | |CRV = CRV source voltage * (1/6+CRVCTL/24).
+ * |[6] |CRVSSEL |CRV Source Voltage Selection
+ * | | |0 = VDDA is selected as CRV source voltage.
+ * | | |1 = The reference voltage defined by SYS_VREFCTL register is selected as CRV source voltage.
+ */
+
+ __IO uint32_t CTL[2]; /* Offset: 0x00 Analog Comparator Control Register */
+ __IO uint32_t STATUS; /* Offset: 0x08 Analog Comparator Status Register */
+ __IO uint32_t VREF; /* Offset: 0x0C Analog Comparator Reference Voltage Control Register */
+
+} ACMP_T;
+
+
+
+/**
+ @addtogroup ACMP_CONST ACMP Bit Field Definition
+ Constant Definitions for ACMP Controller
+@{ */
+
+#define ACMP_CTL_ACMPEN_Pos (0) /*!< ACMP_T::CTL: ACMPEN Position */
+#define ACMP_CTL_ACMPEN_Msk (0x1ul << ACMP_CTL_ACMPEN_Pos) /*!< ACMP_T::CTL: ACMPEN Mask */
+
+#define ACMP_CTL_ACMPIE_Pos (1) /*!< ACMP_T::CTL: ACMPIE Position */
+#define ACMP_CTL_ACMPIE_Msk (0x1ul << ACMP_CTL_ACMPIE_Pos) /*!< ACMP_T::CTL: ACMPIE Mask */
+
+#define ACMP_CTL_HYSEN_Pos (2) /*!< ACMP_T::CTL: HYSEN Position */
+#define ACMP_CTL_HYSEN_Msk (0x1ul << ACMP_CTL_HYSEN_Pos) /*!< ACMP_T::CTL: HYSEN Mask */
+
+#define ACMP_CTL_ACMPOINV_Pos (3) /*!< ACMP_T::CTL: ACMPOINV Position */
+#define ACMP_CTL_ACMPOINV_Msk (0x1ul << ACMP_CTL_ACMPOINV_Pos) /*!< ACMP_T::CTL: ACMPOINV Mask */
+
+#define ACMP_CTL_NEGSEL_Pos (4) /*!< ACMP_T::CTL: NEGSEL Position */
+#define ACMP_CTL_NEGSEL_Msk (0x3ul << ACMP_CTL_NEGSEL_Pos) /*!< ACMP_T::CTL: NEGSEL Mask */
+
+#define ACMP_CTL_POSSEL_Pos (6) /*!< ACMP_T::CTL: POSSEL Position */
+#define ACMP_CTL_POSSEL_Msk (0x3ul << ACMP_CTL_POSSEL_Pos) /*!< ACMP_T::CTL: POSSEL Mask */
+
+#define ACMP_CTL_INTPOL_Pos (8) /*!< ACMP_T::CTL: INTPOL Position */
+#define ACMP_CTL_INTPOL_Msk (0x3ul << ACMP_CTL_INTPOL_Pos) /*!< ACMP_T::CTL: INTPOL Mask */
+
+#define ACMP_CTL_OUTSEL_Pos (12) /*!< ACMP_T::CTL: OUTSEL Position */
+#define ACMP_CTL_OUTSEL_Msk (0x1ul << ACMP_CTL_OUTSEL_Pos) /*!< ACMP_T::CTL: OUTSEL Mask */
+
+#define ACMP_CTL_FILTSEL_Pos (13) /*!< ACMP_T::CTL: FILTSEL Position */
+#define ACMP_CTL_FILTSEL_Msk (0x7ul << ACMP_CTL_FILTSEL_Pos) /*!< ACMP_T::CTL: FILTSEL Mask */
+
+#define ACMP_CTL_WKEN_Pos (16) /*!< ACMP_T::CTL: WKEN Position */
+#define ACMP_CTL_WKEN_Msk (0x1ul << ACMP_CTL_WKEN_Pos) /*!< ACMP_T::CTL: WKEN Mask */
+
+#define ACMP_STATUS_ACMPIF0_Pos (0) /*!< ACMP_T::STATUS: ACMPIF0 Position */
+#define ACMP_STATUS_ACMPIF0_Msk (0x1ul << ACMP_STATUS_ACMPIF0_Pos) /*!< ACMP_T::STATUS: ACMPIF0 Mask */
+
+#define ACMP_STATUS_ACMPIF1_Pos (1) /*!< ACMP_T::STATUS: ACMPIF1 Position */
+#define ACMP_STATUS_ACMPIF1_Msk (0x1ul << ACMP_STATUS_ACMPIF1_Pos) /*!< ACMP_T::STATUS: ACMPIF1 Mask */
+
+#define ACMP_STATUS_ACMPO0_Pos (4) /*!< ACMP_T::STATUS: ACMPO0 Position */
+#define ACMP_STATUS_ACMPO0_Msk (0x1ul << ACMP_STATUS_ACMPO0_Pos) /*!< ACMP_T::STATUS: ACMPO0 Mask */
+
+#define ACMP_STATUS_ACMPO1_Pos (5) /*!< ACMP_T::STATUS: ACMPO1 Position */
+#define ACMP_STATUS_ACMPO1_Msk (0x1ul << ACMP_STATUS_ACMPO1_Pos) /*!< ACMP_T::STATUS: ACMPO1 Mask */
+
+#define ACMP_STATUS_WKIF0_Pos (8) /*!< ACMP_T::STATUS: WKIF0 Position */
+#define ACMP_STATUS_WKIF0_Msk (0x1ul << ACMP_STATUS_WKIF0_Pos) /*!< ACMP_T::STATUS: WKIF0 Mask */
+
+#define ACMP_STATUS_WKIF1_Pos (9) /*!< ACMP_T::STATUS: WKIF1 Position */
+#define ACMP_STATUS_WKIF1_Msk (0x1ul << ACMP_STATUS_WKIF1_Pos) /*!< ACMP_T::STATUS: WKIF1 Mask */
+
+#define ACMP_VREF_CRVCTL_Pos (0) /*!< ACMP_T::VREF: CRVCTL Position */
+#define ACMP_VREF_CRVCTL_Msk (0xful << ACMP_VREF_CRVCTL_Pos) /*!< ACMP_T::VREF: CRVCTL Mask */
+
+#define ACMP_VREF_CRVSSEL_Pos (6) /*!< ACMP_T::VREF: CRVSSEL Position */
+#define ACMP_VREF_CRVSSEL_Msk (0x1ul << ACMP_VREF_CRVSSEL_Pos) /*!< ACMP_T::VREF: CRVSSEL Mask */
+
+/**@}*/ /* ACMP_CONST */
+/**@}*/ /* end of ACMP register group */
+
+
+/*---------------------- Enhanced Analog to Digital Converter -------------------------*/
+/**
+ @addtogroup Enhanced Analog to Digital Converter(EADC)
+ Memory Mapped Structure for EADC Controller
+@{ */
+
+
+typedef struct
+{
+
+
+/**
+ * @var EADC_T::DAT
+ * Offset: 0x00-0x48 A/D Data Register n for Sample Module n, n=0~18
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |RESULT |A/D Conversion Result
+ * | | |This field contains 12 bits conversion result.
+ * | | |When DMOF (EADC_CTL[9]) is set to 0, 12-bit ADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].
+ * | | |When DMOF (EADC_CTL[9]) set to 1, 12-bit ADC conversion result with 2'complement format will be filled in RESULT[11:0] and signed bits to will be filled in RESULT[15:12].
+ * |[16] |OV |Overrun Flag
+ * | | |If converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register, OV is set to 1.
+ * | | |0 = Data in RESULT[11:0] is recent conversion result.
+ * | | |1 = Data in RESULT[11:0] is overwrite.
+ * | | |Note: It is cleared by hardware after EADC_DAT register is read.
+ * |[17] |VALID |Valid Flag
+ * | | |This bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is read.
+ * | | |0 = Data in RESULT[11:0] bits is not valid.
+ * | | |1 = Data in RESULT[11:0] bits is valid.
+ * @var EADC_T::CURDAT
+ * Offset: 0x4C EADC PDMA Current Transfer Data Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[17:0] |CURDAT |ADC PDMA Current Transfer Data Register
+ * | | |This register is a shadow register of EADC_DATn (n=0~18) for PDMA support.
+ * | | |This is a read only register.
+ * @var EADC_T::CTL
+ * Offset: 0x50 A/D Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |ADCEN |A/D Converter Enable Bit
+ * | | |0 = Disabled.
+ * | | |1 = Enabled.
+ * | | |Note: Before starting A/D conversion function, this bit should be set to 1.
+ * | | |Clear it to 0 to disable A/D converter analog circuit power consumption.
+ * |[1] |ADCRST |ADC A/D Converter Control Circuits Reset
+ * | | |0 = No effect.
+ * | | |1 = Cause ADC control circuits reset to initial state, but not change the ADC registers value.
+ * | | |Note: ADCRST bit remains 1 during ADC reset, when ADC reset end, the ADCRST bit is automatically cleared to 0.
+ * |[2] |ADCIEN0 |Specific Sample Module A/D ADINT0 Interrupt Enable Bit
+ * | | |The A/D converter generates a conversion end ADIF0 (EADC_STATUS2[0]) upon the end of specific sample module A/D conversion.
+ * | | |If ADCIEN0 bit is set then conversion end interrupt request ADINT0 is generated.
+ * | | |0 = Specific sample module A/D ADINT0 interrupt function Disabled.
+ * | | |1 = Specific sample module A/D ADINT0 interrupt function Enabled.
+ * |[3] |ADCIEN1 |Specific Sample Module A/D ADINT1 Interrupt Enable Bit
+ * | | |The A/D converter generates a conversion end ADIF1 (EADC_STATUS2[1]) upon the end of specific sample module A/D conversion.
+ * | | |If ADCIEN1 bit is set then conversion end interrupt request ADINT1 is generated.
+ * | | |0 = Specific sample module A/D ADINT1 interrupt function Disabled.
+ * | | |1 = Specific sample module A/D ADINT1 interrupt function Enabled.
+ * |[4] |ADCIEN2 |Specific Sample Module A/D ADINT2 Interrupt Enable Bit
+ * | | |The A/D converter generates a conversion end ADIF2 (EADC_STATUS2[2]) upon the end of specific sample module A/D conversion.
+ * | | |If ADCIEN2 bit is set then conversion end interrupt request ADINT2 is generated.
+ * | | |0 = Specific sample module A/D ADINT2 interrupt function Disabled.
+ * | | |1 = Specific sample module A/D ADINT2 interrupt function Enabled.
+ * |[5] |ADCIEN3 |Specific Sample Module A/D ADINT3 Interrupt Enable Bit
+ * | | |The A/D converter generates a conversion end ADIF3 (EADC_STATUS2[3]) upon the end of specific sample module A/D conversion.
+ * | | |If ADCIEN3 bit is set then conversion end interrupt request ADINT3 is generated.
+ * | | |0 = Specific sample module A/D ADINT3 interrupt function Disabled.
+ * | | |1 = Specific sample module A/D ADINT3 interrupt function Enabled.
+ * |[8] |DIFFEN |Differential Analog Input Mode Enable Bit
+ * | | |0 = Single-end analog input mode.
+ * | | |1 = Differential analog input mode.
+ * |[9] |DMOF |ADC Differential Input Mode Output Format
+ * | | |0 = A/D conversion result will be filled in RESULT (EADC_DATn[15:0] , n= 0 ~18) with unsigned format.
+ * | | |1 = A/D conversion result will be filled in RESULT (EADC_DATn[15:0] , n= 0 ~18) with 2'complement format.
+ * |[11] |PDMAEN |PDMA Transfer Enable Bit
+ * | | |When A/D conversion is completed, the converted data is loaded into EADC_DATn (n: 0 ~ 18) register, user can enable this bit to generate a PDMA data transfer request.
+ * | | |0 = PDMA data transfer Disabled.
+ * | | |1 = PDMA data transfer Enabled.
+ * | | |Note: When set this bit field to 1, user must set ADCIENn (EADC_CTL[5:2], n=0~3) = 0 to disable interrupt.
+ * |[18:16] |SMPTSEL |ADC Internal Sampling Time Selection
+ * | | |ADC internal sampling cycle = SMPTSEL + 1.
+ * | | |000 = 1 ADC clock sampling time.
+ * | | |001 = 2 ADC clock sampling time.
+ * | | |010 = 3 ADC clock sampling time.
+ * | | |011 = 4 ADC clock sampling time.
+ * | | |100 = 5 ADC clock sampling time.
+ * | | |101 = 6 ADC clock sampling time.
+ * | | |110 = 7 ADC clock sampling time.
+ * | | |111 = 8 ADC clock sampling time.
+ * @var EADC_T::SWTRG
+ * Offset: 0x54 A/D Sample Module Software Start Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[18:0] |SWTRG |A/D Sample Module
+ * | | |0~18 Software Force To Start ADC Conversion
+ * | | |0 = No effect.
+ * | | |1 = Cause an ADC conversion when the priority is given to sample module.
+ * | | |Note: After write this register to start ADC conversion, the EADC_PENDSTS register will show which sample module will conversion.
+ * | | |If user want to disable the conversion of the sample module, user can write EADC_PENDSTS register to clear it.
+ * @var EADC_T::PENDSTS
+ * Offset: 0x58 A/D Start of Conversion Pending Flag Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[18:0] |STPF |A/D Sample Module 0~18 Start Of Conversion Pending Flag
+ * | | |Read:
+ * | | |0 = There is no pending conversion for sample module.
+ * | | |1 = Sample module ADC start of conversion is pending.
+ * | | |Write:
+ * | | |1 = clear pending flag and cancel the conversion for sample module.
+ * | | |Note: This bit remains 1 during pending state, when the respective ADC conversion is end, the STPFn (n=0~18) bit is automatically cleared to 0
+ * @var EADC_T::OVSTS
+ * Offset: 0x5C A/D Sample Module Start of Conversion Overrun Flag Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[18:0] |SPOVF |A/D SAMPLE0~18 Overrun Flag
+ * | | |0 = No sample module event overrun.
+ * | | |1 = Indicates a new sample module event is generated while an old one event is pending.
+ * | | |Note: This bit is cleared by writing 1 to it.
+ * @var EADC_T::SCTL
+ * Offset: 0x80-0x8C A/D Sample Module n Control Register, n=0~3
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[3:0] |CHSEL |A/D Sample Module Channel Selection
+ * | | |00H = EADC_CH0.
+ * | | |01H = EADC_CH1.
+ * | | |02H = EADC_CH2.
+ * | | |03H = EADC_CH3.
+ * | | |04H = EADC_CH4.
+ * | | |05H = EADC_CH5.
+ * | | |06H = EADC_CH6.
+ * | | |07H = EADC_CH7.
+ * | | |08H = EADC_CH8.
+ * | | |09H = EADC_CH9.
+ * | | |0AH = EADC_CH10.
+ * | | |0BH = EADC_CH11.
+ * | | |0CH = EADC_CH12.
+ * | | |0DH = EADC_CH13.
+ * | | |0EH = EADC_CH14.
+ * | | |0FH = EADC_CH15.
+ * |[4] |EXTREN |A/D External Trigger Rising Edge Enable Bit
+ * | | |0 = Rising edge Disabled when A/D selects STADC as trigger source.
+ * | | |1 = Rising edge Enabled when A/D selects STADC as trigger source.
+ * |[5] |EXTFEN |A/D External Trigger Falling Edge Enable Bit
+ * | | |0 = Falling edge Disabled when A/D selects STADC as trigger source.
+ * | | |1 = Falling edge Enabled when A/D selects STADC as trigger source.
+ * |[7:6] |TRGDLYDIV |A/D Sample Module Start Of Conversion Trigger Delay Clock Divider Selection
+ * | | |Trigger delay clock frequency:
+ * | | |00 = ADC_CLK/1.
+ * | | |01 = ADC_CLK/2.
+ * | | |10 = ADC_CLK/4.
+ * | | |11 = ADC_CLK/16.
+ * |[15:8] |TRGDLYCNT |A/D Sample Module Start Of Conversion Trigger Delay Time
+ * | | |Trigger delay time = TRGDLYCNT x ADC_CLK x n (n=1,2,4,16 from TRGDLYDIV setting).
+ * |[20:16] |TRGSEL |A/D Sample Module Start Of Conversion Trigger Source Selection
+ * | | |0H = Disable trigger.
+ * | | |1H = External trigger from STADC pin input.
+ * | | |2H = ADC ADINT0 interrupt EOC (End of conversion) pulse trigger.
+ * | | |3H = ADC ADINT1 interrupt EOC (End of conversion) pulse trigger.
+ * | | |4H = Timer0 overflow pulse trigger.
+ * | | |5H = Timer1 overflow pulse trigger.
+ * | | |6H = Timer2 overflow pulse trigger.
+ * | | |7H = Timer3 overflow pulse trigger.
+ * | | |8H = PWM0TG0.
+ * | | |9H = PWM0TG1.
+ * | | |AH = PWM0TG2.
+ * | | |BH = PWM0TG3.
+ * | | |CH = PWM0TG4.
+ * | | |DH = PWM0TG5.
+ * | | |EH = PWM1TG0.
+ * | | |FH = PWM1TG1.
+ * | | |10H = PWM1TG2.
+ * | | |11H = PWM1TG3.
+ * | | |12H = PWM1TG4.
+ * | | |13H = PWM1TG5.
+ * | | |other = Reserved.
+ * |[22] |INTPOS |Interrupt Flag Position Select
+ * | | |0 = Set ADIFn (EADC_STATUS2[n], n=0~3) at A/D end of conversion.
+ * | | |1 = Set ADIFn (EADC_STATUS2[n], n=0~3) at A/D start of conversion.
+ * |[23] |DBMEN |Double Buffer Mode Enable Bit
+ * | | |0 = Sample has one sample result register. (default).
+ * | | |1 = Sample has two sample result registers.
+ * |[31:24] |EXTSMPT |ADC Sampling Time Extend
+ * | | |When A/D converting at high conversion rate, the sampling time of analog input voltage may not enough if input channel loading is heavy, user can extend A/D sampling time after trigger source is coming to get enough sampling time.
+ * | | |The range of start delay time is from 0~255 ADC clock.
+ * @var EADC_T::SCTL
+ * Offset: 0x90-0xBC A/D Sample Module n Control Register, n=4~15
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[3:0] |CHSEL |A/D Sample Module Channel Selection
+ * | | |00H = EADC_CH0.
+ * | | |01H = EADC_CH1.
+ * | | |02H = EADC_CH2.
+ * | | |03H = EADC_CH3.
+ * | | |04H = EADC_CH4.
+ * | | |05H = EADC_CH5.
+ * | | |06H = EADC_CH6.
+ * | | |07H = EADC_CH7.
+ * | | |08H = EADC_CH8.
+ * | | |09H = EADC_CH9.
+ * | | |0AH = EADC_CH10.
+ * | | |0BH = EADC_CH11.
+ * | | |0CH = EADC_CH12.
+ * | | |0DH = EADC_CH13.
+ * | | |0EH = EADC_CH14.
+ * | | |0FH = EADC_CH15.
+ * |[4] |EXTREN |A/D External Trigger Rising Edge Enable Bit
+ * | | |0 = Rising edge Disabled when A/D selects STADC as trigger source.
+ * | | |1 = Rising edge Enabled when A/D selects STADC as trigger source.
+ * |[5] |EXTFEN |A/D External Trigger Falling Edge Enable Bit
+ * | | |0 = Falling edge Disabled when A/D selects STADC as trigger source.
+ * | | |1 = Falling edge Enabled when A/D selects STADC as trigger source.
+ * |[7:6] |TRGDLYDIV[1:0]|A/D Sample Module Start Of Conversion Trigger Delay Clock Divider Selection
+ * | | |Trigger delay clock frequency:
+ * | | |00 = ADC_CLK/1.
+ * | | |01 = ADC_CLK/2.
+ * | | |10 = ADC_CLK/4.
+ * | | |11 = ADC_CLK/16.
+ * |[15:8] |TRGDLYCNT[7:0]|A/D Sample Module Start Of Conversion Trigger Delay Time
+ * | | |Trigger delay time = TRGDLYCNT x ADC_CLK x n (n=1,2,4,16 from TRGDLYDIV setting).
+ * |[20:16] |TRGSEL |A/D Sample Module Start Of Conversion Trigger Source Selection
+ * | | |0H = Disable trigger.
+ * | | |1H = External trigger from STADC pin input.
+ * | | |2H = ADC ADINT0 interrupt EOC pulse trigger.
+ * | | |3H = ADC ADINT1 interrupt EOC pulse trigger.
+ * | | |4H = Timer0 overflow pulse trigger.
+ * | | |5H = Timer1 overflow pulse trigger.
+ * | | |6H = Timer2 overflow pulse trigger.
+ * | | |7H = Timer3 overflow pulse trigger.
+ * | | |8H = PWM0TG0.
+ * | | |9H = PWM0TG1.
+ * | | |AH = PWM0TG2.
+ * | | |BH = PWM0TG3.
+ * | | |CH = PWM0TG4.
+ * | | |DH = PWM0TG5.
+ * | | |EH = PWM1TG0.
+ * | | |FH = PWM1TG1.
+ * | | |10H = PWM1TG2.
+ * | | |11H = PWM1TG3.
+ * | | |12H = PWM1TG4.
+ * | | |13H = PWM1TG5.
+ * | | |other = Reserved.
+ * |[22] |INTPOS |Interrupt Flag Position Select
+ * | | |0 = Set ADIFn (EADC_STATUS2[n], n=0~3) at A/D end of conversion.
+ * | | |1 = Set ADIFn (EADC_STATUS2[n], n=0~3) at A/D start of conversion.
+ * |[31:24] |EXTSMPT |ADC Sampling Time Extend
+ * | | |When A/D converting at high conversion rate, the sampling time of analog input voltage may not enough if input channel loading is heavy, SW can extend A/D sampling time after trigger source is coming to get enough sampling time.
+ * | | |The range of start delay time is from 0~255 ADC clock.
+ * @var EADC_T::SCTL
+ * Offset: 0xC0~0xC8 A/D Sample Module n Control Register, n=16~18
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:24] |EXTSMPT |ADC Sampling Time Extend
+ * | | |When A/D converting at high conversion rate, the sampling time of analog input voltage may not enough if input channel loading is heavy, SW can extend A/D sampling time after trigger source is coming to get enough sampling time.
+ * | | |The range of start delay time is from 0~255 ADC clock.
+ * @var EADC_T::INTSRC
+ * Offset: 0xDC ADC interrupt n Source Enable Control Register, n=0~3
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |SPLIE0 |Sample Module 0 Interrupt Enable Bit
+ * | | |0 = Sample Module 0 interrupt Disabled.
+ * | | |1 = Sample Module 0 interrupt Enabled.
+ * |[1] |SPLIE1 |Sample Module 1 Interrupt Enable Bit
+ * | | |0 = Sample Module 1 interrupt Disabled.
+ * | | |1 = Sample Module 1 interrupt Enabled.
+ * |[2] |SPLIE2 |Sample Module 2 Interrupt Enable Bit
+ * | | |0 = Sample Module 2 interrupt Disabled.
+ * | | |1 = Sample Module 2 interrupt Enabled.
+ * |[3] |SPLIE3 |Sample Module 3 Interrupt Enable Bit
+ * | | |0 = Sample Module 3 interrupt Disabled.
+ * | | |1 = Sample Module 3 interrupt Enabled.
+ * |[4] |SPLIE4 |Sample Module 4 Interrupt Enable Bit
+ * | | |0 = Sample Module 4 interrupt Disabled.
+ * | | |1 = Sample Module 4 interrupt Enabled.
+ * |[5] |SPLIE5 |Sample Module 5 Interrupt Enable Bit
+ * | | |0 = Sample Module 5 interrupt Disabled.
+ * | | |1 = Sample Module 5 interrupt Enabled.
+ * |[6] |SPLIE6 |Sample Module 6 Interrupt Enable Bit
+ * | | |0 = Sample Module 6 interrupt Disabled.
+ * | | |1 = Sample Module 6 interrupt Enabled.
+ * |[7] |SPLIE7 |Sample Module 7 Interrupt Enable Bit
+ * | | |0 = Sample Module 7 interrupt Disabled.
+ * | | |1 = Sample Module 7 interrupt Enabled.
+ * |[8] |SPLIE8 |Sample Module 8 Interrupt Enable Bit
+ * | | |0 = Sample Module 8 interrupt Disabled.
+ * | | |1 = Sample Module 8 interrupt Enabled.
+ * |[9] |SPLIE9 |Sample Module 9 Interrupt Enable Bit
+ * | | |0 = Sample Module 9 interrupt Disabled.
+ * | | |1 = Sample Module 9 interrupt Enabled.
+ * |[10] |SPLIE10 |Sample Module 10 Interrupt Enable Bit
+ * | | |0 = Sample Module 10 interrupt Disabled.
+ * | | |1 = Sample Module 10 interrupt Enabled.
+ * |[11] |SPLIE11 |Sample Module 11 Interrupt Enable Bit
+ * | | |0 = Sample Module 11 interrupt Disabled.
+ * | | |1 = Sample Module 11 interrupt Enabled.
+ * |[12] |SPLIE12 |Sample Module 12 Interrupt Enable Bit
+ * | | |0 = Sample Module 12 interrupt Disabled.
+ * | | |1 = Sample Module 12 interrupt Enabled.
+ * |[13] |SPLIE13 |Sample Module 13 Interrupt Enable Bit
+ * | | |0 = Sample Module 13 interrupt Disabled.
+ * | | |1 = Sample Module 13 interrupt Enabled.
+ * |[14] |SPLIE14 |Sample Module 14 Interrupt Enable Bit
+ * | | |0 = Sample Module 14 interrupt Disabled.
+ * | | |1 = Sample Module 14 interrupt Enabled.
+ * |[15] |SPLIE15 |Sample Module 15 Interrupt Enable Bit
+ * | | |0 = Sample Module 15 interrupt Disabled.
+ * | | |1 = Sample Module 15 interrupt Enabled.
+ * |[16] |SPLIE16 |Sample Module 16 Interrupt Enable Bit
+ * | | |0 = Sample Module 16 interrupt Disabled.
+ * | | |1 = Sample Module 16 interrupt Enabled.
+ * |[17] |SPLIE17 |Sample Module 17 Interrupt Enable Bit
+ * | | |0 = Sample Module 17 interrupt Disabled.
+ * | | |1 = Sample Module 17 interrupt Enabled.
+ * |[18] |SPLIE18 |Sample Module 18 Interrupt Enable Bit
+ * | | |0 = Sample Module 18 interrupt Disabled.
+ * | | |1 = Sample Module 18 interrupt Enabled.
+ * @var EADC_T::CMP
+ * Offset: 0xEC A/D Result Compare Register n, n=0~3
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |ADCMPEN |A/D Result Compare Enable Bit
+ * | | |0 = Compare Disabled.
+ * | | |1 = Compare Enabled.
+ * | | |Set this bit to 1 to enable compare CMPDAT (EADC_CMPn[27:16], n=0~3) with specified sample module conversion result when converted data is loaded into EADC_DAT register.
+ * |[1] |ADCMPIE |A/D Result Compare Interrupt Enable Bit
+ * | | |0 = Compare function interrupt Disabled.
+ * | | |1 = Compare function interrupt Enabled.
+ * | | |If the compare function is enabled and the compare condition matches the setting of CMPCOND (EADC_CMPn[2], n=0~3) and CMPMCNT (EADC_CMPn[11:8], n=0~3), ADCMPFn (EADC_STATUS2[7:4], n=0~3) will be asserted, in the meanwhile, if ADCMPIE is set to 1, a compare interrupt request is generated.
+ * |[2] |CMPCOND |Compare Condition
+ * | | |0= Set the compare condition as that when a 12-bit A/D conversion result is less than the 12-bit CMPDAT (EADC_CMPn
+ * | | |[27:16]), the internal match counter will increase one.
+ * | | |1= Set the compare condition as that when a 12-bit A/D conversion result is greater or equal to the 12-bit CMPDAT (EADC_CMPn [27:16]), the internal match counter will increase one.
+ * | | |Note: When the internal counter reaches the value to (CMPMCNT (EADC_CMPn[11:8], n=0~3) +1), the CMPF bit will be set.
+ * |[7:3] |CMPSPL |Compare Sample Module Selection
+ * | | |00000 = Sample Module 0 conversion result EADC_DAT0 is selected to be compared.
+ * | | |00001 = Sample Module 1 conversion result EADC_DAT1 is selected to be compared.
+ * | | |00010 = Sample Module 2 conversion result EADC_DAT2 is selected to be compared.
+ * | | |00011 = Sample Module 3 conversion result EADC_DAT3 is selected to be compared.
+ * | | |00100 = Sample Module 4 conversion result EADC_DAT4 is selected to be compared.
+ * | | |00101 = Sample Module 5 conversion result EADC_DAT5 is selected to be compared.
+ * | | |00110 = Sample Module 6 conversion result EADC_DAT6 is selected to be compared.
+ * | | |00111 = Sample Module 7 conversion result EADC_DAT7 is selected to be compared.
+ * | | |01000 = Sample Module 8 conversion result EADC_DAT8 is selected to be compared.
+ * | | |01001 = Sample Module 9 conversion result EADC_DAT9 is selected to be compared.
+ * | | |01010 = Sample Module 10 conversion result EADC_DAT10 is selected to be compared.
+ * | | |01011 = Sample Module 11 conversion result EADC_DAT11 is selected to be compared.
+ * | | |01100 = Sample Module 12 conversion result EADC_DAT12 is selected to be compared.
+ * | | |01101 = Sample Module 13 conversion result EADC_DAT13 is selected to be compared.
+ * | | |01110 = Sample Module 14 conversion result EADC_DAT14 is selected to be compared.
+ * | | |01111 = Sample Module 15 conversion result EADC_DAT15 is selected to be compared.
+ * | | |10000 = Sample Module 16 conversion result EADC_DAT16 is selected to be compared.
+ * | | |10001 = Sample Module 17 conversion result EADC_DAT17 is selected to be compared.
+ * | | |10010 = Sample Module 18 conversion result EADC_DAT18 is selected to be compared.
+ * |[11:8] |CMPMCNT |Compare Match Count
+ * | | |When the specified A/D sample module analog conversion result matches the compare condition defined by CMPCOND (EADC_CMPn[2], n=0~3), the internal match counter will increase 1.
+ * | | |If the compare result does not meet the compare condition, the internal compare match counter will reset to 0.
+ * | | |When the internal counter reaches the value to (CMPMCNT +1), the ADCMPFn (EADC_STATUS2[7:4], n=0~3) will be set.
+ * |[15] |CMPWEN |Compare Window Mode Enable Bit
+ * | | |0 = ADCMPF0 (EADC_STATUS2[4]) will be set when EADC_CMP0 compared condition matched.
+ * | | |ADCMPF2 (EADC_STATUS2[6]) will be set when EADC_CMP2 compared condition matched.
+ * | | |1 = ADCMPF0 (EADC_STATUS2[4]) will be set when both EADC_CMP0 and EADC_CMP1 compared condition matched.
+ * | | |ADCMPF2 (EADC_STATUS2[6]) will be set when both EADC_CMP2 and EADC_CMP3 compared condition matched.
+ * | | |Note: This bit is only present in EADC_CMP0 and EADC_CMP2 register.
+ * |[27:16] |CMPDAT |Comparison Data
+ * | | |The 12 bits data is used to compare with conversion result of specified sample module.
+ * | | |User can use it to monitor the external analog input pin voltage transition without imposing a load on software.
+ * @var EADC_T::STATUS0
+ * Offset: 0xF0 A/D Status Register 0
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |VALID |EADC_DAT0~15 Data Valid Flag
+ * | | |It is a mirror of VALID bit in sample module A/D result data register EADC_DATn. (n=0~18).
+ * |[31:16] |OV |EADC_DAT0~15 Overrun Flag
+ * | | |It is a mirror to OV bit in sample module A/D result data register EADC_DATn. (n=0~18).
+ * @var EADC_T::STATUS1
+ * Offset: 0xF4 A/D Status Register 1
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[2:0] |VALID |EADC_DAT16~18 Data Valid Flag
+ * | | |It is a mirror of VALID bit in sample module A/D result data register EADC_DATn. (n=0~18).
+ * |[18:16] |OV |EADC_DAT16~18 Overrun Flag
+ * | | |It is a mirror to OV bit in sample module A/D result data register EADC_DATn. (n=0~18).
+ * @var EADC_T::STATUS2
+ * Offset: 0xF8 A/D Status Register 2
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |ADIF0 |A/D ADINT0 Interrupt Flag
+ * | | |0 = No ADINT0 interrupt pulse received.
+ * | | |1 = ADINT0 interrupt pulse has been received.
+ * | | |Note1: This bit is cleared by writing 1 to it.
+ * | | |Note2:This bit indicates whether an A/D conversion of specific sample module has been completed
+ * |[1] |ADIF1 |A/D ADINT1 Interrupt Flag
+ * | | |0 = No ADINT1 interrupt pulse received.
+ * | | |1 = ADINT1 interrupt pulse has been received.
+ * | | |Note1: This bit is cleared by writing 1 to it.
+ * | | |Note2:This bit indicates whether an A/D conversion of specific sample module has been completed
+ * |[2] |ADIF2 |A/D ADINT2 Interrupt Flag
+ * | | |0 = No ADINT2 interrupt pulse received.
+ * | | |1 = ADINT2 interrupt pulse has been received.
+ * | | |Note1: This bit is cleared by writing 1 to it.
+ * | | |Note2:This bit indicates whether an A/D conversion of specific sample module has been completed
+ * |[3] |ADIF3 |A/D ADINT3 Interrupt Flag
+ * | | |0 = No ADINT3 interrupt pulse received.
+ * | | |1 = ADINT3 interrupt pulse has been received.
+ * | | |Note1: This bit is cleared by writing 1 to it.
+ * | | |Note2:This bit indicates whether an A/D conversion of specific sample module has been completed
+ * |[4] |ADCMPF0 |ADC Compare 0 Flag
+ * | | |When the specific sample module A/D conversion result meets setting condition in EADC_CMP0 then this bit is set to 1.
+ * | | |0 = Conversion result in EADC_DAT does not meet EADC_CMP0 register setting.
+ * | | |1 = Conversion result in EADC_DAT meets EADC_CMP0 register setting.
+ * | | |Note: This bit is cleared by writing 1 to it.
+ * |[5] |ADCMPF1 |ADC Compare 1 Flag
+ * | | |When the specific sample module A/D conversion result meets setting condition in EADC_CMP1 then this bit is set to 1.
+ * | | |0 = Conversion result in EADC_DAT does not meet EADC_CMP1 register setting.
+ * | | |1 = Conversion result in EADC_DAT meets EADC_CMP1 register setting.
+ * | | |Note: This bit is cleared by writing 1 to it.
+ * |[6] |ADCMPF2 |ADC Compare 2 Flag
+ * | | |When the specific sample module A/D conversion result meets setting condition in EADC_CMP2 then this bit is set to 1.
+ * | | |0 = Conversion result in EADC_DAT does not meet EADC_CMP2 register setting.
+ * | | |1 = Conversion result in EADC_DAT meets EADC_CMP2 register setting.
+ * | | |Note: This bit is cleared by writing 1 to it.
+ * |[7] |ADCMPF3 |ADC Compare 3 Flag
+ * | | |When the specific sample module A/D conversion result meets setting condition in EADC_CMP3 then this bit is set to 1.
+ * | | |0 = Conversion result in EADC_DAT does not meet EADC_CMP3 register setting.
+ * | | |1 = Conversion result in EADC_DAT meets EADC_CMP3 register setting.
+ * | | |Note: This bit is cleared by writing 1 to it.
+ * |[8] |ADOVIF0 |A/D ADINT0 Interrupt Flag Overrun
+ * | | |0 = ADINT0 interrupt flag is not overwritten to 1.
+ * | | |1 = ADINT0 interrupt flag is overwritten to 1.
+ * | | |Note: This bit is cleared by writing 1 to it.
+ * |[9] |ADOVIF1 |A/D ADINT1 Interrupt Flag Overrun
+ * | | |0 = ADINT1 interrupt flag is not overwritten to 1.
+ * | | |1 = ADINT1 interrupt flag is overwritten to 1.
+ * | | |Note: This bit is cleared by writing 1 to it.
+ * |[10] |ADOVIF2 |A/D ADINT2 Interrupt Flag Overrun
+ * | | |0 = ADINT2 interrupt flag is not overwritten to 1.
+ * | | |1 = ADINT2 interrupt flag is s overwritten to 1.
+ * | | |Note: This bit is cleared by writing 1 to it.
+ * |[11] |ADOVIF3 |A/D ADINT3 Interrupt Flag Overrun
+ * | | |0 = ADINT3 interrupt flag is not overwritten to 1.
+ * | | |1 = ADINT3 interrupt flag is overwritten to 1.
+ * | | |Note: This bit is cleared by writing 1 to it.
+ * |[12] |ADCMPO0 |ADC Compare 0 Output Status
+ * | | |The 12 bits compare0 data CMPDAT0 (EADC_CMP0[27:16]) is used to compare with conversion result of specified sample module.
+ * | | |User can use it to monitor the external analog input pin voltage status.
+ * | | |0 = Conversion result in EADC_DAT less than CMPDAT0 setting.
+ * | | |1 = Conversion result in EADC_DAT great than or equal CMPDAT0
+ * | | |setting.
+ * |[13] |ADCMPO1 |ADC Compare 1 Output Status
+ * | | |The 12 bits compare1 data CMPDAT1 (EADC_CMP1[27:16]) is used to compare with conversion result of specified sample module.
+ * | | |User can use it to monitor the external analog input pin voltage status.
+ * | | |0 = Conversion result in EADC_DAT less than CMPDAT1 setting.
+ * | | |1 = Conversion result in EADC_DAT great than or equal CMPDAT1
+ * | | |setting.
+ * |[14] |ADCMPO2 |ADC Compare 2 Output Status
+ * | | |The 12 bits compare2 data CMPDAT2 (EADC_CMP2[27:16]) is used to compare with conversion result of specified sample module.
+ * | | |User can use it to monitor the external analog input pin voltage status.
+ * | | |0 = Conversion result in EADC_DAT less than CMPDAT2 setting.
+ * | | |1 = Conversion result in EADC_DAT great than or equal CMPDAT2
+ * | | |setting.
+ * |[15] |ADCMPO3 |ADC Compare 3 Output Status
+ * | | |The 12 bits compare3 data CMPDAT3 (EADC_CMP3[27:16]) is used to compare with conversion result of specified sample module.
+ * | | |User can use it to monitor the external analog input pin voltage status.
+ * | | |0 = Conversion result in EADC_DAT less than CMPDAT3 setting.
+ * | | |1 = Conversion result in EADC_DAT great than or equal CMPDAT3
+ * | | |setting.
+ * |[20:16] |CHANNEL |Current Conversion Channel
+ * | | |This filed reflects ADC current conversion channel when BUSY=1.
+ * | | |It is read only.
+ * | | |00H = EADC_CH0.
+ * | | |01H = EADC_CH1.
+ * | | |02H = EADC_CH2.
+ * | | |03H = EADC_CH3.
+ * | | |04H = EADC_CH4.
+ * | | |05H = EADC_CH5.
+ * | | |06H = EADC_CH6.
+ * | | |07H = EADC_CH7.
+ * | | |08H = EADC_CH8.
+ * | | |09H = EADC_CH9.
+ * | | |0AH = EADC_CH10.
+ * | | |0BH = EADC_CH11.
+ * | | |0CH = EADC_CH12.
+ * | | |0DH = EADC_CH13.
+ * | | |0EH = EADC_CH14.
+ * | | |0FH = EADC_CH15.
+ * | | |10H = VBG.
+ * | | |11H = VTEMP.
+ * | | |12H = VBAT.
+ * |[23] |BUSY |Busy/Idle
+ * | | |0 = EADC is in idle state.
+ * | | |1 = EADC is busy at conversion.
+ * | | |Note: This bit is read only.
+ * |[24] |ADOVIF |All A/D Interrupt Flag Overrun Bits Check
+ * | | |n=0~3.
+ * | | |0 = None of ADINT interrupt flag ADOVIFn (EADC_STATUS2[11:8]) is overwritten to 1.
+ * | | |1 = Any one of ADINT interrupt flag ADOVIFn (EADC_STATUS2[11:8]) is overwritten to 1.
+ * | | |Note: This bit will keep 1 when any ADOVIFn Flag is equal to 1.
+ * |[25] |STOVF |For All A/D Sample Module Start Of Conversion Overrun Flags Check
+ * | | |n=0~18.
+ * | | |0 = None of sample module event overrun flag SPOVFn (EADC_OVSTS[n]) is set to 1.
+ * | | |1 = Any one of sample module event overrun flag SPOVFn (EADC_OVSTS[n]) is set to 1.
+ * | | |Note: This bit will keep 1 when any SPOVFn Flag is equal to 1.
+ * |[26] |AVALID |For All Sample Module A/D Result Data Register EADC_DAT Data Valid Flag Check
+ * | | |n=0~18.
+ * | | |0 = None of sample module data register valid flag VALIDn (EADC_DATn[17]) is set to 1.
+ * | | |1 = Any one of sample module data register valid flag VALIDn (EADC_DATn[17]) is set to 1.
+ * | | |Note: This bit will keep 1 when any VALIDn Flag is equal to 1.
+ * |[27] |AOV |For All Sample Module A/D Result Data Register Overrun Flags Check
+ * | | |n=0~18.
+ * | | |0 = None of sample module data register overrun flag OVn (EADC_DATn[16]) is set to 1.
+ * | | |1 = Any one of sample module data register overrun flag OVn (EADC_DATn[16]) is set to 1.
+ * | | |Note: This bit will keep 1 when any OVn Flag is equal to 1.
+ * @var EADC_T::STATUS3
+ * Offset: 0xFC A/D Status Register 3
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[4:0] |CURSPL |ADC Current Sample Module
+ * | | |This register show the current ADC is controlled by which sample module control logic modules.
+ * | | |If the ADC is Idle, this bit filed will set to 0x1F.
+ * | | |This is a read only register.
+ * @var EADC_T::DDAT
+ * Offset: 0x100-0x10C A/D Double Data Register n for Sample Module n, n=0~3
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |RESULT |A/D Conversion Results
+ * | | |This field contains 12 bits conversion results.
+ * | | |When the DMOF (EADC_CTL[9]) is set to 0, 12-bit ADC conversion result with unsigned format will be filled in RESULT [11:0] and zero will be filled in RESULT [15:12].
+ * | | |When DMOF (EADC_CTL[9]) set to 1, 12-bit ADC conversion result with 2'complement format will be filled in RESULT [11:0] and signed bits to will be filled in RESULT [15:12].
+ * |[16] |OV |Overrun Flag
+ * | | |0 = Data in RESULT (EADC_DATn[15:0], n=0~3) is recent conversion result.
+ * | | |1 = Data in RESULT (EADC_DATn[15:0], n=0~3) is overwrite.
+ * | | |If converted data in RESULT[15:0] has not been read before new conversion result is loaded to this register, OV is set to 1.
+ * | | |It is cleared by hardware after EADC_DDAT register is read.
+ * |[17] |VALID |Valid Flag
+ * | | |0 = Double data in RESULT (EADC_DDATn[15:0]) is not valid.
+ * | | |1 = Double data in RESULT (EADC_DDATn[15:0]) is valid.
+ * | | |This bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DDATn register is read.
+ * | | |(n=0~3).
+ */
+
+ __I uint32_t DAT[19]; /* Offset: 0x00-0x48 A/D Data Register n for Sample Module n, n=0~18 */
+ __I uint32_t CURDAT; /* Offset: 0x4C EADC PDMA Current Transfer Data Register */
+ __IO uint32_t CTL; /* Offset: 0x50 A/D Control Register */
+ __O uint32_t SWTRG; /* Offset: 0x54 A/D Sample Module Software Start Register */
+ __IO uint32_t PENDSTS; /* Offset: 0x58 A/D Start of Conversion Pending Flag Register */
+ __IO uint32_t OVSTS; /* Offset: 0x5C A/D Sample Module Start of Conversion Overrun Flag Register */
+ __I uint32_t RESERVE0[8];
+ __IO uint32_t SCTL[19]; /* Offset: 0x80-0xC8 A/D Sample Module n Control Register, n=0~3 */
+ __I uint32_t RESERVE1[1];
+ __IO uint32_t INTSRC[4]; /* Offset: 0xDC ADC interrupt n Source Enable Control Register, n=0~3 */
+ __IO uint32_t CMP[4]; /* Offset: 0xEC A/D Result Compare Register n, n=0~3 */
+ __I uint32_t STATUS0; /* Offset: 0xF0 A/D Status Register 0 */
+ __I uint32_t STATUS1; /* Offset: 0xF4 A/D Status Register 1 */
+ __IO uint32_t STATUS2; /* Offset: 0xF8 A/D Status Register 2 */
+ __I uint32_t STATUS3; /* Offset: 0xFC A/D Status Register 3 */
+ __I uint32_t DDAT[4]; /* Offset: 0x100-0x10C A/D Double Data Register n for Sample Module n, n=0~3 */
+
+} EADC_T;
+
+
+
+/**
+ @addtogroup EADC_CONST EADC Bit Field Definition
+ Constant Definitions for EADC Controller
+@{ */
+#define EADC_DAT_RESULT_Pos (0) /*!< EADC_T::DAT: RESULT Position */
+#define EADC_DAT_RESULT_Msk (0xfffful << EADC_DAT_RESULT_Pos) /*!< EADC_T::DAT: RESULT Mask */
+
+#define EADC_DAT_OV_Pos (16) /*!< EADC_T::DAT: OV Position */
+#define EADC_DAT_OV_Msk (0x1ul << EADC_DAT_OV_Pos) /*!< EADC_T::DAT: OV Mask */
+
+#define EADC_DAT_VALID_Pos (17) /*!< EADC_T::DAT: VALID Position */
+#define EADC_DAT_VALID_Msk (0x1ul << EADC_DAT_VALID_Pos) /*!< EADC_T::DAT: VALID Mask */
+
+#define EADC_CURDAT_CURDAT_Pos (0) /*!< EADC_T::CURDAT: CURDAT Position */
+#define EADC_CURDAT_CURDAT_Msk (0x3fffful << EADC_CURDAT_CURDAT_Pos) /*!< EADC_T::CURDAT: CURDAT Mask */
+
+#define EADC_CTL_ADCEN_Pos (0) /*!< EADC_T::CTL: ADCEN Position */
+#define EADC_CTL_ADCEN_Msk (0x1ul << EADC_CTL_ADCEN_Pos) /*!< EADC_T::CTL: ADCEN Mask */
+
+#define EADC_CTL_ADRST_Pos (1) /*!< EADC_T::CTL: ADRST Position */
+#define EADC_CTL_ADRST_Msk (0x1ul << EADC_CTL_ADRST_Pos) /*!< EADC_T::CTL: ADRST Mask */
+
+#define EADC_CTL_ADCIEN0_Pos (2) /*!< EADC_T::CTL: ADCIEN0 Position */
+#define EADC_CTL_ADCIEN0_Msk (0x1ul << EADC_CTL_ADCIEN0_Pos) /*!< EADC_T::CTL: ADCIEN0 Mask */
+
+#define EADC_CTL_ADCIEN1_Pos (3) /*!< EADC_T::CTL: ADCIEN1 Position */
+#define EADC_CTL_ADCIEN1_Msk (0x1ul << EADC_CTL_ADCIEN1_Pos) /*!< EADC_T::CTL: ADCIEN1 Mask */
+
+#define EADC_CTL_ADCIEN2_Pos (4) /*!< EADC_T::CTL: ADCIEN2 Position */
+#define EADC_CTL_ADCIEN2_Msk (0x1ul << EADC_CTL_ADCIEN2_Pos) /*!< EADC_T::CTL: ADCIEN2 Mask */
+
+#define EADC_CTL_ADCIEN3_Pos (5) /*!< EADC_T::CTL: ADCIEN3 Position */
+#define EADC_CTL_ADCIEN3_Msk (0x1ul << EADC_CTL_ADCIEN3_Pos) /*!< EADC_T::CTL: ADCIEN3 Mask */
+
+#define EADC_CTL_DIFFEN_Pos (8) /*!< EADC_T::CTL: DIFFEN Position */
+#define EADC_CTL_DIFFEN_Msk (0x1ul << EADC_CTL_DIFFEN_Pos) /*!< EADC_T::CTL: DIFFEN Mask */
+
+#define EADC_CTL_DMOF_Pos (9) /*!< EADC_T::CTL: DMOF Position */
+#define EADC_CTL_DMOF_Msk (0x1ul << EADC_CTL_DMOF_Pos) /*!< EADC_T::CTL: DMOF Mask */
+
+#define EADC_CTL_PDMAEN_Pos (11) /*!< EADC_T::CTL: PDMAEN Position */
+#define EADC_CTL_PDMAEN_Msk (0x1ul << EADC_CTL_PDMAEN_Pos) /*!< EADC_T::CTL: PDMAEN Mask */
+
+#define EADC_CTL_SMPTSEL_Pos (16) /*!< EADC_T::CTL: SMPTSEL Position */
+#define EADC_CTL_SMPTSEL_Msk (0x7ul << EADC_CTL_SMPTSEL_Pos) /*!< EADC_T::CTL: SMPTSEL Mask */
+
+#define EADC_SWTRG_SWTRG_Pos (0) /*!< EADC_T::SWTRG: SWTRG Position */
+#define EADC_SWTRG_SWTRG_Msk (0x7fffful << EADC_SWTRG_SWTRG_Pos) /*!< EADC_T::SWTRG: SWTRG Mask */
+
+#define EADC_PENDSTS_STPF_Pos (0) /*!< EADC_T::PENDSTS: STPF Position */
+#define EADC_PENDSTS_STPF_Msk (0x7fffful << EADC_PENDSTS_STPF_Pos) /*!< EADC_T::PENDSTS: STPF Mask */
+
+#define EADC_OVSTS_SPOVF_Pos (0) /*!< EADC_T::OVSTS: SPOVF Position */
+#define EADC_OVSTS_SPOVF_Msk (0x7fffful << EADC_OVSTS_SPOVF_Pos) /*!< EADC_T::OVSTS: SPOVF Mask */
+
+#define EADC_SCTL_CHSEL_Pos (0) /*!< EADC_T::SCTL: CHSEL Position */
+#define EADC_SCTL_CHSEL_Msk (0xful << EADC_SCTL_CHSEL_Pos) /*!< EADC_T::SCTL: CHSEL Mask */
+
+#define EADC_SCTL_EXTREN_Pos (4) /*!< EADC_T::SCTL: EXTREN Position */
+#define EADC_SCTL_EXTREN_Msk (0x1ul << EADC_SCTL_EXTREN_Pos) /*!< EADC_T::SCTL: EXTREN Mask */
+
+#define EADC_SCTL_EXTFEN_Pos (5) /*!< EADC_T::SCTL: EXTFEN Position */
+#define EADC_SCTL_EXTFEN_Msk (0x1ul << EADC_SCTL_EXTFEN_Pos) /*!< EADC_T::SCTL: EXTFEN Mask */
+
+#define EADC_SCTL_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL: TRGDLYDIV Position */
+#define EADC_SCTL_TRGDLYDIV_Msk (0x3ul << EADC_SCTL_TRGDLYDIV_Pos) /*!< EADC_T::SCTL: TRGDLYDIV Mask */
+
+#define EADC_SCTL_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL: TRGDLYCNT Position */
+#define EADC_SCTL_TRGDLYCNT_Msk (0xfful << EADC_SCTL_TRGDLYCNT_Pos) /*!< EADC_T::SCTL: TRGDLYCNT Mask */
+
+#define EADC_SCTL_TRGSEL_Pos (16) /*!< EADC_T::SCTL: TRGSEL Position */
+#define EADC_SCTL_TRGSEL_Msk (0x1ful << EADC_SCTL_TRGSEL_Pos) /*!< EADC_T::SCTL: TRGSEL Mask */
+
+#define EADC_SCTL_INTPOS_Pos (22) /*!< EADC_T::SCTL: INTPOS Position */
+#define EADC_SCTL_INTPOS_Msk (0x1ul << EADC_SCTL_INTPOS_Pos) /*!< EADC_T::SCTL: INTPOS Mask */
+
+#define EADC_SCTL_DBMEN_Pos (23) /*!< EADC_T::SCTL: DBMEN Position */
+#define EADC_SCTL_DBMEN_Msk (0x1ul << EADC_SCTL_DBMEN_Pos) /*!< EADC_T::SCTL: DBMEN Mask */
+
+#define EADC_SCTL_EXTSMPT_Pos (24) /*!< EADC_T::SCTL: EXTSMPT Position */
+#define EADC_SCTL_EXTSMPT_Msk (0xfful << EADC_SCTL_EXTSMPT_Pos) /*!< EADC_T::SCTL: EXTSMPT Mask */
+
+#define EADC_INTSRC_SPLIE_Pos (0) /*!< EADC_T::INTSRC: SPLIE Position */
+#define EADC_INTSRC_SPLIE_Msk (0x7FFFFul << EADC_INTSRC_SPLIE_Pos) /*!< EADC_T::INTSRC: SPLIE Mask */
+
+#define EADC_CMP_ADCMPEN_Pos (0) /*!< EADC_T::CMP: ADCMPEN Position */
+#define EADC_CMP_ADCMPEN_Msk (0x1ul << EADC_CMP_ADCMPEN_Pos) /*!< EADC_T::CMP: ADCMPEN Mask */
+
+#define EADC_CMP_ADCMPIE_Pos (1) /*!< EADC_T::CMP: ADCMPIE Position */
+#define EADC_CMP_ADCMPIE_Msk (0x1ul << EADC_CMP_ADCMPIE_Pos) /*!< EADC_T::CMP: ADCMPIE Mask */
+
+#define EADC_CMP_CMPCOND_Pos (2) /*!< EADC_T::CMP: CMPCOND Position */
+#define EADC_CMP_CMPCOND_Msk (0x1ul << EADC_CMP_CMPCOND_Pos) /*!< EADC_T::CMP: CMPCOND Mask */
+
+#define EADC_CMP_CMPSPL_Pos (3) /*!< EADC_T::CMP: CMPSPL Position */
+#define EADC_CMP_CMPSPL_Msk (0x1ful << EADC_CMP_CMPSPL_Pos) /*!< EADC_T::CMP: CMPSPL Mask */
+
+#define EADC_CMP_CMPMCNT_Pos (8) /*!< EADC_T::CMP: CMPMCNT Position */
+#define EADC_CMP_CMPMCNT_Msk (0xful << EADC_CMP_CMPMCNT_Pos) /*!< EADC_T::CMP: CMPMCNT Mask */
+
+#define EADC_CMP_CMPWEN_Pos (15) /*!< EADC_T::CMP: CMPWEN Position */
+#define EADC_CMP_CMPWEN_Msk (0x1ul << EADC_CMP_CMPWEN_Pos) /*!< EADC_T::CMP: CMPWEN Mask */
+
+#define EADC_CMP_CMPDAT_Pos (16) /*!< EADC_T::CMP: CMPDAT Position */
+#define EADC_CMP_CMPDAT_Msk (0xffful << EADC_CMP_CMPDAT_Pos) /*!< EADC_T::CMP: CMPDAT Mask */
+
+#define EADC_STATUS0_VALID_Pos (0) /*!< EADC_T::STATUS0: VALID Position */
+#define EADC_STATUS0_VALID_Msk (0xfffful << EADC_STATUS0_VALID_Pos) /*!< EADC_T::STATUS0: VALID Mask */
+
+#define EADC_STATUS0_OV_Pos (16) /*!< EADC_T::STATUS0: OV Position */
+#define EADC_STATUS0_OV_Msk (0xfffful << EADC_STATUS0_OV_Pos) /*!< EADC_T::STATUS0: OV Mask */
+
+#define EADC_STATUS1_VALID_Pos (0) /*!< EADC_T::STATUS1: VALID Position */
+#define EADC_STATUS1_VALID_Msk (0x7ul << EADC_STATUS1_VALID_Pos) /*!< EADC_T::STATUS1: VALID Mask */
+
+#define EADC_STATUS1_OV_Pos (16) /*!< EADC_T::STATUS1: OV Position */
+#define EADC_STATUS1_OV_Msk (0x7ul << EADC_STATUS1_OV_Pos) /*!< EADC_T::STATUS1: OV Mask */
+
+#define EADC_STATUS2_ADIF0_Pos (0) /*!< EADC_T::STATUS2: ADIF0 Position */
+#define EADC_STATUS2_ADIF0_Msk (0x1ul << EADC_STATUS2_ADIF0_Pos) /*!< EADC_T::STATUS2: ADIF0 Mask */
+
+#define EADC_STATUS2_ADIF1_Pos (1) /*!< EADC_T::STATUS2: ADIF1 Position */
+#define EADC_STATUS2_ADIF1_Msk (0x1ul << EADC_STATUS2_ADIF1_Pos) /*!< EADC_T::STATUS2: ADIF1 Mask */
+
+#define EADC_STATUS2_ADIF2_Pos (2) /*!< EADC_T::STATUS2: ADIF2 Position */
+#define EADC_STATUS2_ADIF2_Msk (0x1ul << EADC_STATUS2_ADIF2_Pos) /*!< EADC_T::STATUS2: ADIF2 Mask */
+
+#define EADC_STATUS2_ADIF3_Pos (3) /*!< EADC_T::STATUS2: ADIF3 Position */
+#define EADC_STATUS2_ADIF3_Msk (0x1ul << EADC_STATUS2_ADIF3_Pos) /*!< EADC_T::STATUS2: ADIF3 Mask */
+
+#define EADC_STATUS2_ADCMPF0_Pos (4) /*!< EADC_T::STATUS2: ADCMPF0 Position */
+#define EADC_STATUS2_ADCMPF0_Msk (0x1ul << EADC_STATUS2_ADCMPF0_Pos) /*!< EADC_T::STATUS2: ADCMPF0 Mask */
+
+#define EADC_STATUS2_ADCMPF1_Pos (5) /*!< EADC_T::STATUS2: ADCMPF1 Position */
+#define EADC_STATUS2_ADCMPF1_Msk (0x1ul << EADC_STATUS2_ADCMPF1_Pos) /*!< EADC_T::STATUS2: ADCMPF1 Mask */
+
+#define EADC_STATUS2_ADCMPF2_Pos (6) /*!< EADC_T::STATUS2: ADCMPF2 Position */
+#define EADC_STATUS2_ADCMPF2_Msk (0x1ul << EADC_STATUS2_ADCMPF2_Pos) /*!< EADC_T::STATUS2: ADCMPF2 Mask */
+
+#define EADC_STATUS2_ADCMPF3_Pos (7) /*!< EADC_T::STATUS2: ADCMPF3 Position */
+#define EADC_STATUS2_ADCMPF3_Msk (0x1ul << EADC_STATUS2_ADCMPF3_Pos) /*!< EADC_T::STATUS2: ADCMPF3 Mask */
+
+#define EADC_STATUS2_ADOVIF0_Pos (8) /*!< EADC_T::STATUS2: ADOVIF0 Position */
+#define EADC_STATUS2_ADOVIF0_Msk (0x1ul << EADC_STATUS2_ADOVIF0_Pos) /*!< EADC_T::STATUS2: ADOVIF0 Mask */
+
+#define EADC_STATUS2_ADOVIF1_Pos (9) /*!< EADC_T::STATUS2: ADOVIF1 Position */
+#define EADC_STATUS2_ADOVIF1_Msk (0x1ul << EADC_STATUS2_ADOVIF1_Pos) /*!< EADC_T::STATUS2: ADOVIF1 Mask */
+
+#define EADC_STATUS2_ADOVIF2_Pos (10) /*!< EADC_T::STATUS2: ADOVIF2 Position */
+#define EADC_STATUS2_ADOVIF2_Msk (0x1ul << EADC_STATUS2_ADOVIF2_Pos) /*!< EADC_T::STATUS2: ADOVIF2 Mask */
+
+#define EADC_STATUS2_ADOVIF3_Pos (11) /*!< EADC_T::STATUS2: ADOVIF3 Position */
+#define EADC_STATUS2_ADOVIF3_Msk (0x1ul << EADC_STATUS2_ADOVIF3_Pos) /*!< EADC_T::STATUS2: ADOVIF3 Mask */
+
+#define EADC_STATUS2_ADCMPO0_Pos (12) /*!< EADC_T::STATUS2: ADCMPO0 Position */
+#define EADC_STATUS2_ADCMPO0_Msk (0x1ul << EADC_STATUS2_ADCMPO0_Pos) /*!< EADC_T::STATUS2: ADCMPO0 Mask */
+
+#define EADC_STATUS2_ADCMPO1_Pos (13) /*!< EADC_T::STATUS2: ADCMPO1 Position */
+#define EADC_STATUS2_ADCMPO1_Msk (0x1ul << EADC_STATUS2_ADCMPO1_Pos) /*!< EADC_T::STATUS2: ADCMPO1 Mask */
+
+#define EADC_STATUS2_ADCMPO2_Pos (14) /*!< EADC_T::STATUS2: ADCMPO2 Position */
+#define EADC_STATUS2_ADCMPO2_Msk (0x1ul << EADC_STATUS2_ADCMPO2_Pos) /*!< EADC_T::STATUS2: ADCMPO2 Mask */
+
+#define EADC_STATUS2_ADCMPO3_Pos (15) /*!< EADC_T::STATUS2: ADCMPO3 Position */
+#define EADC_STATUS2_ADCMPO3_Msk (0x1ul << EADC_STATUS2_ADCMPO3_Pos) /*!< EADC_T::STATUS2: ADCMPO3 Mask */
+
+#define EADC_STATUS2_CHANNEL_Pos (16) /*!< EADC_T::STATUS2: CHANNEL Position */
+#define EADC_STATUS2_CHANNEL_Msk (0x1ful << EADC_STATUS2_CHANNEL_Pos) /*!< EADC_T::STATUS2: CHANNEL Mask */
+
+#define EADC_STATUS2_BUSY_Pos (23) /*!< EADC_T::STATUS2: BUSY Position */
+#define EADC_STATUS2_BUSY_Msk (0x1ul << EADC_STATUS2_BUSY_Pos) /*!< EADC_T::STATUS2: BUSY Mask */
+
+#define EADC_STATUS2_ADOVIF_Pos (24) /*!< EADC_T::STATUS2: ADOVIF Position */
+#define EADC_STATUS2_ADOVIF_Msk (0x1ul << EADC_STATUS2_ADOVIF_Pos) /*!< EADC_T::STATUS2: ADOVIF Mask */
+
+#define EADC_STATUS2_STOVF_Pos (25) /*!< EADC_T::STATUS2: STOVF Position */
+#define EADC_STATUS2_STOVF_Msk (0x1ul << EADC_STATUS2_STOVF_Pos) /*!< EADC_T::STATUS2: STOVF Mask */
+
+#define EADC_STATUS2_AVALID_Pos (26) /*!< EADC_T::STATUS2: AVALID Position */
+#define EADC_STATUS2_AVALID_Msk (0x1ul << EADC_STATUS2_AVALID_Pos) /*!< EADC_T::STATUS2: AVALID Mask */
+
+#define EADC_STATUS2_AOV_Pos (27) /*!< EADC_T::STATUS2: AOV Position */
+#define EADC_STATUS2_AOV_Msk (0x1ul << EADC_STATUS2_AOV_Pos) /*!< EADC_T::STATUS2: AOV Mask */
+
+#define EADC_STATUS3_CURSPL_Pos (0) /*!< EADC_T::STATUS3: CURSPL Position */
+#define EADC_STATUS3_CURSPL_Msk (0x1ful << EADC_STATUS3_CURSPL_Pos) /*!< EADC_T::STATUS3: CURSPL Mask */
+
+#define EADC_DDAT_RESULT_Pos (0) /*!< EADC_T::DDAT: RESULT Position */
+#define EADC_DDAT_RESULT_Msk (0xfffful << EADC_DDAT_RESULT_Pos) /*!< EADC_T::DDAT: RESULT Mask */
+
+#define EADC_DDAT_OV_Pos (16) /*!< EADC_T::DDAT: OV Position */
+#define EADC_DDAT_OV_Msk (0x1ul << EADC_DDAT_OV_Pos) /*!< EADC_T::DDAT: OV Mask */
+
+#define EADC_DDAT_VALID_Pos (17) /*!< EADC_T::DDAT: VALID Position */
+#define EADC_DDAT_VALID_Msk (0x1ul << EADC_DDAT_VALID_Pos) /*!< EADC_T::DDAT: VALID Mask */
+
+
+/**@}*/ /* EADC_CONST */
+/**@}*/ /* end of EADC register group */
+
+
+/*---------------------- Controller Area Network Controller -------------------------*/
+/**
+ @addtogroup CAN Controller Area Network Controller(CAN)
+ Memory Mapped Structure for CAN Controller
+@{ */
+
+
+typedef struct
+{
+
+
+
+/**
+ * @var CAN_IF_T::CREQ
+ * Offset: 0x20, 0x80 IFn (Register Map Note 2) Command Request Registers
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[5:0] |MessageNumber|Message Number
+ * | | |0x01-0x20: Valid Message Number, the Message Object in the Message
+ * | | |RAM is selected for data transfer.
+ * | | |0x00: Not a valid Message Number, interpreted as 0x20.
+ * | | |0x21-0x3F: Not a valid Message Number, interpreted as 0x01-0x1F.
+ * |[15] |Busy |Busy Flag
+ * | | |0 = Read/write action has finished.
+ * | | |1 = Writing to the IFn Command Request Register is in progress.
+ * | | |This bit can only be read by the software.
+ * @var CAN_IF_T::CMASK
+ * Offset: 0x24, 0x84 IFn Command Mask Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |DAT_B |Access Data Bytes [7:4]
+ * | | |Write Operation:
+ * | | |0 = Data Bytes [7:4] unchanged.
+ * | | |1 = Transfer Data Bytes [7:4] to Message Object.
+ * | | |Read Operation:
+ * | | |0 = Data Bytes [7:4] unchanged.
+ * | | |1 = Transfer Data Bytes [7:4] to IFn Message Buffer Register.
+ * |[1] |DAT_A |Access Data Bytes [3:0]
+ * | | |Write Operation:
+ * | | |0 = Data Bytes [3:0] unchanged.
+ * | | |1 = Transfer Data Bytes [3:0] to Message Object.
+ * | | |Read Operation:
+ * | | |0 = Data Bytes [3:0] unchanged.
+ * | | |1 = Transfer Data Bytes [3:0] to IFn Message Buffer Register.
+ * |[2] |TxRqst_NewDat|Access Transmission Request Bit When Write Operation
+ * | | |0 = TxRqst bit unchanged.
+ * | | |1 = Set TxRqst bit.
+ * | | |Note: If a transmission is requested by programming bit TxRqst/NewDat in the IFn Command Mask Register, bit TxRqst in the IFn Message Control Register will be ignored.
+ * | | |Access New Data Bit when Read Operation.
+ * | | |0 = NewDat bit remains unchanged.
+ * | | |1 = Clear NewDat bit in the Message Object.
+ * | | |Note: A read access to a Message Object can be combined with the reset of the control bits IntPnd and NewDat.
+ * | | |The values of these bits transferred to the IFn Message Control Register always reflect the status before resetting these bits.
+ * |[3] |ClrIntPnd |Clear Interrupt Pending Bit
+ * | | |Write Operation:
+ * | | |When writing to a Message Object, this bit is ignored.
+ * | | |Read Operation:
+ * | | |0 = IntPnd bit (CAN_IFn_MCON[13]) remains unchanged.
+ * | | |1 = Clear IntPnd bit in the Message Object.
+ * |[4] |Control |Control Access Control Bits
+ * | | |Write Operation:
+ * | | |0 = Control Bits unchanged.
+ * | | |1 = Transfer Control Bits to Message Object.
+ * | | |Read Operation:
+ * | | |0 = Control Bits unchanged.
+ * | | |1 = Transfer Control Bits to IFn Message Buffer Register.
+ * |[5] |Arb |Access Arbitration Bits
+ * | | |Write Operation:
+ * | | |0 = Arbitration bits unchanged.
+ * | | |1 = Transfer Identifier + Dir (CAN_IFn_ARB2[13]) + Xtd (CAN_IFn_ARB2[14]) + MsgVal (CAN_IFn_APB2[15]) to Message Object.
+ * | | |Read Operation:
+ * | | |0 = Arbitration bits unchanged.
+ * | | |1 = Transfer Identifier + Dir + Xtd + MsgVal to IFn Message Buffer Register.
+ * |[6] |Mask |Access Mask Bits
+ * | | |Write Operation:
+ * | | |0 = Mask bits unchanged.
+ * | | |1 = Transfer Identifier Mask + MDir + MXtd to Message Object.
+ * | | |Read Operation:
+ * | | |0 = Mask bits unchanged.
+ * | | |1 = Transfer Identifier Mask + MDir + MXtd to IFn Message Buffer Register.
+ * |[7] |WR_RD |Write / Read Mode
+ * | | |0 = Read: Transfer data from the Message Object addressed by the Command Request Register into the selected Message Buffer Registers.
+ * | | |1 = Write: Transfer data from the selected Message Buffer Registers to the Message Object addressed by the Command Request Register.
+ * @var CAN_IF_T::MASK1
+ * Offset: 0x28, 0x88 IFn Mask 1 Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |Msk[15:0] |Identifier Mask 15-0
+ * | | |0 = The corresponding bit in the identifier of the message object cannot inhibit the match in the acceptance filtering.
+ * | | |1 = The corresponding identifier bit is used for acceptance filtering.
+ * @var CAN_IF_T::MASK2
+ * Offset: 0x2C, 0x8C IFn Mask 2 Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[12:0] |Msk[28:16]|Identifier Mask 28-16
+ * | | |0 = The corresponding bit in the identifier of the message object cannot inhibit the match in the acceptance filtering.
+ * | | |1 = The corresponding identifier bit is used for acceptance filtering.
+ * |[14] |MDir |Mask Message Direction
+ * | | |0 = The message direction bit (Dir (CAN_IFn_ARB2[13])) has no effect on the acceptance filtering.
+ * | | |1 = The message direction bit (Dir) is used for acceptance filtering.
+ * |[15] |MXtd |Mask Extended Identifier
+ * | | |0 = The extended identifier bit (IDE) has no effect on the acceptance filtering.
+ * | | |1 = The extended identifier bit (IDE) is used for acceptance filtering.
+ * | | |Note: When 11-bit ("standard") Identifiers are used for a Message Object, the identifiers of received Data Frames are written into bits ID28 to ID18 (CAN_IFn_ARB2[12:2]).
+ * | | |For acceptance filtering, only these bits together with mask bits Msk28 to Msk18 (CAN_IFn_MASK2[12:2]) are considered.
+ * @var CAN_IF_T::ARB1
+ * Offset: 0x30, 0x90 IFn Arbitration 1 Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |ID[15:0] |Message Identifier 15-0
+ * | | |ID28 - ID0, 29-bit Identifier ("Extended Frame").
+ * | | |ID28 - ID18, 11-bit Identifier ("Standard Frame")
+ * @var CAN_IF_T::ARB2
+ * Offset: 0x34, 0x94 IFn Arbitration 2 Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[12:0] |ID[28:16] |Message Identifier 28-16
+ * | | |ID28 - ID0, 29-bit Identifier ("Extended Frame").
+ * | | |ID28 - ID18, 11-bit Identifier ("Standard Frame")
+ * |[13] |Dir |Message Direction
+ * | | |0 = Direction is receive.
+ * | | |On TxRqst, a Remote Frame with the identifier of this Message Object is transmitted.
+ * | | |On reception of a Data Frame with matching identifier, that message is stored in this Message Object.
+ * | | |1 = Direction is transmit.
+ * | | |On TxRqst, the respective Message Object is transmitted as a Data Frame.
+ * | | |On reception of a Remote Frame with matching identifier, the TxRqst bit (CAN_IFn_CMASK[2]) of this Message Object is set (if RmtEn (CAN_IFn_MCON[9]) = one).
+ * |[14] |Xtd |Extended Identifier
+ * | | |0 = The 11-bit ("standard") Identifier will be used for this Message Object.
+ * | | |1 = The 29-bit ("extended") Identifier will be used for this Message Object.
+ * |[15] |MsgVal |Message Valid
+ * | | |0 = The Message Object is ignored by the Message Handler.
+ * | | |1 = The Message Object is configured and should be considered by the Message Handler.
+ * | | |Note: The application software must reset the MsgVal bit of all unused Messages Objects during the initialization before it resets bit Init (CAN_CON[0]).
+ * | | |This bit must also be reset before the identifier Id28-0 (CAN_IFn_ARB1/2), the control bits Xtd (CAN_IFn_ARB2[14]), Dir (CAN_IFn_APB2[13]), or the Data Length Code DLC3-0 (CAN_IFn_MCON[3:0]) are modified, or if the Messages Object is no longer required.
+ * @var CAN_IF_T::MCON
+ * Offset: 0x38, 0x98 IFn Message Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[3:0] |DLC |Data Length Code
+ * | | |0-8: Data Frame has 0-8 data bytes.
+ * | | |9-15: Data Frame has 8 data bytes
+ * | | |Note: The Data Length Code of a Message Object must be defined the same as in all the corresponding objects with the same identifier at other nodes.
+ * | | |When the Message Handler stores a data frame, it will write the DLC to the value given by the received message.
+ * | | |Data 0: 1st data byte of a CAN Data Frame
+ * | | |Data 1: 2nd data byte of a CAN Data Frame
+ * | | |Data 2: 3rd data byte of a CAN Data Frame
+ * | | |Data 3: 4th data byte of a CAN Data Frame
+ * | | |Data 4: 5th data byte of a CAN Data Frame
+ * | | |Data 5: 6th data byte of a CAN Data Frame
+ * | | |Data 6: 7th data byte of a CAN Data Frame
+ * | | |Data 7 : 8th data byte of a CAN Data Frame
+ * | | |Note: The Data 0 Byte is the first data byte shifted into the shift register of the CAN Core during a reception while the Data 7 byte is the last.
+ * | | |When the Message Handler stores a Data Frame, it will write all the eight data bytes into a Message Object.
+ * | | |If the Data Length Code is less than 8, the remaining bytes of the Message Object will be overwritten by unspecified values.
+ * |[7] |EoB |End Of Buffer
+ * | | |0 = Message Object belongs to a FIFO Buffer and is not the last Message Object of that FIFO Buffer.
+ * | | |1 = Single Message Object or last Message Object of a FIFO Buffer.
+ * | | |Note: This bit is used to concatenate two or more Message Objects (up to 32) to build a FIFO Buffer.
+ * | | |For single Message Objects (not belonging to a FIFO Buffer), this bit must always be set to one.
+ * |[8] |TxRqst |Transmit Request
+ * | | |0 = This Message Object is not waiting for transmission.
+ * | | |1 = The transmission of this Message Object is requested and is not yet done.
+ * |[9] |RmtEn |Remote Enable Control
+ * | | |0 = At the reception of a Remote Frame, TxRqst (CAN_IFn_MCON[8]) is left unchanged.
+ * | | |1 = At the reception of a Remote Frame, TxRqst is set.
+ * |[10] |RxIE |Receive Interrupt Enable Control
+ * | | |0 = IntPnd (CAN_IFn_MCON[13]) will be left unchanged after a successful reception of a frame.
+ * | | |1 = IntPnd will be set after a successful reception of a frame.
+ * |[11] |TxIE |Transmit Interrupt Enable Control
+ * | | |0 = IntPnd (CAN_IFn_MCON[13]) will be left unchanged after the successful transmission of a frame.
+ * | | |1 = IntPnd will be set after a successful transmission of a frame.
+ * |[12] |UMask |Use Acceptance Mask
+ * | | |0 = Mask ignored.
+ * | | |1 = Use Mask (Msk28-0, MXtd, and MDir) for acceptance filtering.
+ * | | |Note: If the UMask bit is set to one, the Message Object's mask bits have to be programmed during initialization of the Message Object before MsgVal bit (CAN_IFn_APB2[15]) is set to one.
+ * |[13] |IntPnd |Interrupt Pending
+ * | | |0 = This message object is not the source of an interrupt.
+ * | | |1 = This message object is the source of an interrupt.
+ * | | |The Interrupt Identifier in the Interrupt Register will point to this message object if there is no other interrupt source with higher priority.
+ * |[14] |MsgLst |Message Lost (only valid for Message Objects with direction = receive).
+ * | | |0 = No message lost since last time this bit was reset by the CPU.
+ * | | |1 = The Message Handler stored a new message into this object when NewDat was still set, the CPU has lost a message.
+ * |[15] |NewDat |New Data
+ * | | |0 = No new data has been written into the data portion of this Message Object by the Message Handler since last time this flag was cleared by the application software.
+ * | | |1 = The Message Handler or the application software has written new data into the data portion of this Message Object.
+ * @var CAN_IF_T::DAT_A1
+ * Offset: 0x3C, 0x9C IFn Data A1 Register (Register Map Note 3)
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:0] |Data0 |Data Byte 0
+ * | | |1st data byte of a CAN Data Frame
+ * |[15:8] |Data1 |Data Byte 1
+ * | | |2nd data byte of a CAN Data Frame
+ * @var CAN_IF_T::DAT_A2
+ * Offset: 0x40, 0xA0 IFn Data A2 Register (Register Map Note 3)
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:0] |Data2 |Data Byte 2
+ * | | |3rd data byte of CAN Data Frame
+ * |[15:8] |Data3 |Data Byte 3
+ * | | |4th data byte of CAN Data Frame
+ * @var CAN_IF_T::DAT_B1
+ * Offset: 0x44, 0xA4 IFn Data B1 Register (Register Map Note 3)
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:0] |Data4 |Data Byte 4
+ * | | |5th data byte of CAN Data Frame
+ * |[15:8] |Data5 |Data Byte 5
+ * | | |6th data byte of CAN Data Frame
+ * @var CAN_IF_T::DAT_B2
+ * Offset: 0x48, 0xA8 IFn Data B2 Register (Register Map Note 3)
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:0] |Data6 |Data Byte 6
+ * | | |7th data byte of CAN Data Frame.
+ * |[15:8] |Data7 |Data Byte 7
+ * | | |8th data byte of CAN Data Frame.
+ */
+
+ __IO uint32_t CREQ; /* Offset: 0x20, 0x80 IFn (Register Map Note 2) Command Request Registers */
+ __IO uint32_t CMASK; /* Offset: 0x24, 0x84 IFn Command Mask Register */
+ __IO uint32_t MASK1; /* Offset: 0x28, 0x88 IFn Mask 1 Register */
+ __IO uint32_t MASK2; /* Offset: 0x2C, 0x8C IFn Mask 2 Register */
+ __IO uint32_t ARB1; /* Offset: 0x30, 0x90 IFn Arbitration 1 Register */
+ __IO uint32_t ARB2; /* Offset: 0x34, 0x94 IFn Arbitration 2 Register */
+ __IO uint32_t MCON; /* Offset: 0x38, 0x98 IFn Message Control Register */
+ __IO uint32_t DAT_A1; /* Offset: 0x3C, 0x9C IFn Data A1 Register (Register Map Note 3) */
+ __IO uint32_t DAT_A2; /* Offset: 0x40, 0xA0 IFn Data A2 Register (Register Map Note 3) */
+ __IO uint32_t DAT_B1; /* Offset: 0x44, 0xA4 IFn Data B1 Register (Register Map Note 3) */
+ __IO uint32_t DAT_B2; /* Offset: 0x48, 0xA8 IFn Data B2 Register (Register Map Note 3) */
+ __I uint32_t RESERVE0[13];
+
+} CAN_IF_T;
+
+
+
+
+typedef struct
+{
+
+
+
+/**
+ * @var CAN_T::CON
+ * Offset: 0x00 Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |Init |Init Initialization
+ * | | |0 = Normal Operation.
+ * | | |1 = Initialization is started.
+ * |[1] |IE |Module Interrupt Enable Control
+ * | | |0 = Disabled.
+ * | | |1 = Enabled.
+ * |[2] |SIE |Status Change Interrupt Enable Control
+ * | | |0 = Disabled - No Status Change Interrupt will be generated.
+ * | | |1 = Enabled - An interrupt will be generated when a message transfer is successfully completed or a CAN bus error is detected.
+ * |[3] |EIE |Error Interrupt Enable Control
+ * | | |0 = Disabled - No Error Status Interrupt will be generated.
+ * | | |1 = Enabled - A change in the bits BOff (CAN_STATUS[7]) or EWarn (CAN_STATUS[6]) in the Status Register will generate an interrupt.
+ * |[5] |DAR |Automatic Re-Transmission Disable Control
+ * | | |0 = Automatic Retransmission of disturbed messages enabled.
+ * | | |1 = Automatic Retransmission disabled.
+ * |[6] |CCE |Configuration Change Enable Control
+ * | | |0 = No write access to the Bit Timing Register.
+ * | | |1 = Write access to the Bit Timing Register (CAN_BTIME) allowed. (while Init bit (CAN_CON[0]) = 1).
+ * |[7] |Test |Test Mode Enable Control
+ * | | |0 = Normal Operation.
+ * | | |1 = Test Mode.
+ * @var CAN_T::STATUS
+ * Offset: 0x04 Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[2:0] |LEC |Last Error Code (Type Of The Last Error To Occur On The CAN Bus)
+ * | | |The LEC field holds a code, which indicates the type of the last error to occur on the CAN bus.
+ * | | |This field will be cleared to '0' when a message has been transferred (reception or transmission) without error.
+ * | | |The unused code '7' may be written by the CPU to check for updates.
+ * | | |The following table describes the error code.
+ * |[3] |TxOK |Transmitted A Message Successfully
+ * | | |0 = Since this bit was reset by the CPU, no message has been successfully transmitted.
+ * | | |This bit is never reset by the CAN Core.
+ * | | |1 = Since this bit was last reset by the CPU, a message has been successfully (error free and acknowledged by at least one other node) transmitted.
+ * |[4] |RxOK |Received A Message Successfully
+ * | | |0 = No message has been successfully received since this bit was last reset by the CPU.
+ * | | |This bit is never reset by the CAN Core.
+ * | | |1 = A message has been successfully received since this bit was last reset by the CPU (independent of the result of acceptance filtering).
+ * |[5] |EPass |Error Passive (Read Only)
+ * | | |0 = The CAN Core is error active.
+ * | | |1 = The CAN Core is in the error passive state as defined in the CAN Specification.
+ * |[6] |EWarn |Error Warning Status (Read Only)
+ * | | |0 = Both error counters are below the error warning limit of 96.
+ * | | |1 = At least one of the error counters in the EML has reached the error warning limit of 96.
+ * |[7] |BOff |Bus-Off Status (Read Only)
+ * | | |0 = The CAN module is not in bus-off state.
+ * | | |1 = The CAN module is in bus-off state.
+ * @var CAN_T::ERR
+ * Offset: 0x08 Error Counter Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:0] |TEC |Transmit Error Counter
+ * | | |Actual state of the Transmit Error Counter. Values between 0 and 255.
+ * |[14:8] |REC |Receive Error Counter
+ * | | |Actual state of the Receive Error Counter. Values between 0 and 127.
+ * |[15] |RP |Receive Error Passive
+ * | | |0 = The Receive Error Counter is below the error passive level.
+ * | | |1 = The Receive Error Counter has reached the error passive level as defined in the CAN Specification.
+ * @var CAN_T::BTIME
+ * Offset: 0x0C Bit Timing Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[5:0] |BRP |Baud Rate Prescaler
+ * | | |0x01-0x3F: The value by which the oscillator frequency is divided for generating the bit time quanta.
+ * | | |The bit time is built up from a multiple of this quanta.
+ * | | |Valid values for the Baud Rate Prescaler are [ 0 ... 63 ].
+ * | | |The actual interpretation by the hardware of this value is such that one more than the value programmed here is used.
+ * |[7:6] |SJW |(Re)Synchronization Jump Width
+ * | | |0x0-0x3: Valid programmed values are [0 ... 3].
+ * | | |The actual interpretation by the hardware of this value is such that one more than the value programmed here is used.
+ * |[11:8] |TSeg1 |Time Segment Before The Sample Point Minus Sync_Seg
+ * | | |0x01-0x0F: valid values for TSeg1 are [1 ... 15].
+ * | | |The actual interpretation by the hardware of this value is such that one more than the value programmed is used.
+ * |[14:12] |TSeg2 |Time Segment After Sample Point
+ * | | |0x0-0x7: Valid values for TSeg2 are [0 ... 7].
+ * | | |The actual interpretation by the hardware of this value is such that one more than the value programmed here is used.
+ * @var CAN_T::IIDR
+ * Offset: 0x10 Interrupt Identifier Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |IntId |Interrupt Identifier (Indicates The Source Of The Interrupt)
+ * | | |If several interrupts are pending, the CAN Interrupt Register will point to the pending interrupt with the highest priority, disregarding their chronological order.
+ * | | |An interrupt remains pending until the application software has cleared it.
+ * | | |If IntId is different from 0x0000 and IE (CAN_IFn_MCON[1]) is set, the IRQ interrupt signal to the EIC is active.
+ * | | |The interrupt remains active until IntId is back to value 0x0000 (the cause of the interrupt is reset) or until IE is reset.
+ * | | |The Status Interrupt has the highest priority.
+ * | | |Among the message interrupts, the Message Object' s interrupt priority decreases with increasing message number.
+ * | | |A message interrupt is cleared by clearing the Message Object's IntPnd bit (CAN_IFn_MCON[13]).
+ * | | |The Status Interrupt is cleared by reading the Status Register.
+ * @var CAN_T::TEST
+ * Offset: 0x14 Test Register (Register Map Note 1)
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[1:0] |Res |Reserved
+ * | | |There are reserved bits.
+ * | | |These bits are always read as '0' and must always be written with '0'.
+ * |[2] |Basic |Basic Mode
+ * | | |0 = Basic Mode disabled.
+ * | | |1= IF1 Registers used as Tx Buffer, IF2 Registers used as Rx Buffer.
+ * |[3] |Silent |Silent Mode
+ * | | |0 = Normal operation.
+ * | | |1 = The module is in Silent Mode.
+ * |[4] |LBack |Loop Back Mode Enable Control
+ * | | |0 = Loop Back Mode is disabled.
+ * | | |1 = Loop Back Mode is enabled.
+ * |[6:5] |Tx10 |Tx[1:0]: Control Of CAN_TX Pin
+ * | | |00 = Reset value, CAN_TX pin is controlled by the CAN Core.
+ * | | |01 = Sample Point can be monitored at CAN_TX pin.
+ * | | |10 = CAN_TX pin drives a dominant ('0') value.
+ * | | |11 = CAN_TX pin drives a recessive ('1') value.
+ * |[7] |Rx |Monitors The Actual Value Of CAN_RX Pin (Read Only)
+ * | | |0 = The CAN bus is dominant (CAN_RX = '0').
+ * | | |1 = The CAN bus is recessive (CAN_RX = '1').
+ * @var CAN_T::BRPE
+ * Offset: 0x18 Baud Rate Prescaler Extension Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[3:0] |BRPE |BRPE: Baud Rate Prescaler Extension
+ * | | |0x00-0x0F: By programming BRPE, the Baud Rate Prescaler can be extended to values up to 1023.
+ * | | |The actual interpretation by the hardware is that one more than the value programmed by BRPE (MSBs) and BTIME (LSBs) is used.
+ * @var CAN_T::IF
+ * Offset: 0x20~0xFC CAN Interface Registers
+ * ---------------------------------------------------------------------------------------------------
+ * CAN interface structure. Refer to \ref CAN_IF_T for detail information.
+ *
+ * @var CAN_T::TXREQ1
+ * Offset: 0x100 Transmission Request Register 1
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |TxRqst[16:1]|Transmission Request Bits 16-1 (Of All Message Objects)
+ * | | |0 = This Message Object is not waiting for transmission.
+ * | | |1 = The transmission of this Message Object is requested and is not yet done.
+ * | | |These bits are read only.
+ * @var CAN_T::TXREQ2
+ * Offset: 0x104 Transmission Request Register 2
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |TxRqst[32:17]|Transmission Request Bits 32-17 (Of All Message Objects)
+ * | | |0 = This Message Object is not waiting for transmission.
+ * | | |1 = The transmission of this Message Object is requested and is not yet done.
+ * | | |These bits are read only.
+ * @var CAN_T::NDAT1
+ * Offset: 0x120 New Data Register 1
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |NewData[16:1]|New Data Bits 16-1 (Of All Message Objects)
+ * | | |0 = No new data has been written into the data portion of this Message Object by the Message Handler since the last time this flag was cleared by the application software.
+ * | | |1 = The Message Handler or the application software has written new data into the data portion of this Message Object.
+ * @var CAN_T::NDAT2
+ * Offset: 0x124 New Data Register 2
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |NewData[32:17]|New Data Bits 32-17 (Of All Message Objects)
+ * | | |0 = No new data has been written into the data portion of this Message Object by the Message Handler since the last time this flag was cleared by the application software.
+ * | | |1 = The Message Handler or the application software has written new data into the data portion of this Message Object.
+ * @var CAN_T::IPND1
+ * Offset: 0x140 Interrupt Pending Register 1
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |IntPnd[16:1]|Interrupt Pending Bits 16-1 (Of All Message Objects)
+ * | | |0 = This message object is not the source of an interrupt.
+ * | | |1 = This message object is the source of an interrupt.
+ * @var CAN_T::IPND2
+ * Offset: 0x144 Interrupt Pending Register 2
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |IntPnd[32:17]|Interrupt Pending Bits 32-17(Of All Message Objects)
+ * | | |0 = This message object is not the source of an interrupt.
+ * | | |1 = This message object is the source of an interrupt.
+ * @var CAN_T::MVLD1
+ * Offset: 0x160 Message Valid Register 1
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |MsgVal[16:1]|Message Valid Bits 16-1 (Of All Message Objects) (Read Only)
+ * | | |0 = This Message Object is ignored by the Message Handler.
+ * | | |1 = This Message Object is configured and should be considered by the Message Handler.
+ * | | |Ex.
+ * | | |CAN_MVLD1[0] means Message object No.1 is valid or not.
+ * | | |If CAN_MVLD1[0] is set, message object No.1 is configured.
+ * @var CAN_T::MVLD2
+ * Offset: 0x164 Message Valid Register 2
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |MsgVal[32:17]|Message Valid Bits 32-17 (Of All Message Objects) (Read Only)
+ * | | |0 = This Message Object is ignored by the Message Handler.
+ * | | |1 = This Message Object is configured and should be considered by the Message Handler.
+ * | | |Ex.CAN_MVLD2[15] means Message object No.32 is valid or not.
+ * | | |If CAN_MVLD2[15] is set, message object No.32 is configured.
+ * @var CAN_T::WU_EN
+ * Offset: 0x168 Wake-up Enable Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |WAKUP_EN |Wake-Up Enable Control
+ * | | |0 = The wake-up function Disabled.
+ * | | |1 = The wake-up function Enabled.
+ * | | |Note: User can wake-up system when there is a falling edge in the CAN_Rx pin.
+ * @var CAN_T::WU_STATUS
+ * Offset: 0x16C Wake-up Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |WAKUP_STS |Wake-Up Status
+ * | | |0 = No wake-up event occurred.
+ * | | |1 = Wake-up event occurred.
+ * | | |Note: This bit can be cleared by writing '0'.
+ */
+
+ __IO uint32_t CON; /* Offset: 0x00 Control Register */
+ __IO uint32_t STATUS; /* Offset: 0x04 Status Register */
+ __I uint32_t ERR; /* Offset: 0x08 Error Counter Register */
+ __IO uint32_t BTIME; /* Offset: 0x0C Bit Timing Register */
+ __I uint32_t IIDR; /* Offset: 0x10 Interrupt Identifier Register */
+ __IO uint32_t TEST; /* Offset: 0x14 Test Register (Register Map Note 1) */
+ __IO uint32_t BRPE; /* Offset: 0x18 Baud Rate Prescaler Extension Register */
+ __I uint32_t RESERVE0[1];
+ __IO CAN_IF_T IF[2]; /* Offset: 0x20~0xFC CAN Interface Registers */
+ __I uint32_t RESERVE1[8];
+ __I uint32_t TXREQ1; /* Offset: 0x100 Transmission Request Register 1 */
+ __I uint32_t TXREQ2; /* Offset: 0x104 Transmission Request Register 2 */
+ __I uint32_t RESERVE3[6];
+ __I uint32_t NDAT1; /* Offset: 0x120 New Data Register 1 */
+ __I uint32_t NDAT2; /* Offset: 0x124 New Data Register 2 */
+ __I uint32_t RESERVE4[6];
+ __I uint32_t IPND1; /* Offset: 0x140 Interrupt Pending Register 1 */
+ __I uint32_t IPND2; /* Offset: 0x144 Interrupt Pending Register 2 */
+ __I uint32_t RESERVE5[6];
+ __I uint32_t MVLD1; /* Offset: 0x160 Message Valid Register 1 */
+ __I uint32_t MVLD2; /* Offset: 0x164 Message Valid Register 2 */
+ __IO uint32_t WU_EN; /* Offset: 0x168 Wake-up Enable Register */
+ __IO uint32_t WU_STATUS; /* Offset: 0x16C Wake-up Status Register */
+
+} CAN_T;
+
+
+
+/**
+ @addtogroup CAN_CONST CAN Bit Field Definition
+ Constant Definitions for CAN Controller
+@{ */
+/* CAN CON Bit Field Definitions */
+#define CAN_CON_TEST_Pos 7 /*!< CAN_T::CON: TEST Position */
+#define CAN_CON_TEST_Msk (0x1ul << CAN_CON_TEST_Pos) /*!< CAN_T::CON: TEST Mask */
+
+#define CAN_CON_CCE_Pos 6 /*!< CAN_T::CON: CCE Position */
+#define CAN_CON_CCE_Msk (0x1ul << CAN_CON_CCE_Pos) /*!< CAN_T::CON: CCE Mask */
+
+#define CAN_CON_DAR_Pos 5 /*!< CAN_T::CON: DAR Position */
+#define CAN_CON_DAR_Msk (0x1ul << CAN_CON_DAR_Pos) /*!< CAN_T::CON: DAR Mask */
+
+#define CAN_CON_EIE_Pos 3 /*!< CAN_T::CON: EIE Position */
+#define CAN_CON_EIE_Msk (0x1ul << CAN_CON_EIE_Pos) /*!< CAN_T::CON: EIE Mask */
+
+#define CAN_CON_SIE_Pos 2 /*!< CAN_T::CON: SIE Position */
+#define CAN_CON_SIE_Msk (0x1ul << CAN_CON_SIE_Pos) /*!< CAN_T::CON: SIE Mask */
+
+#define CAN_CON_IE_Pos 1 /*!< CAN_T::CON: IE Position */
+#define CAN_CON_IE_Msk (0x1ul << CAN_CON_IE_Pos) /*!< CAN_T::CON: IE Mask */
+
+#define CAN_CON_INIT_Pos 0 /*!< CAN_T::CON: INIT Position */
+#define CAN_CON_INIT_Msk (0x1ul << CAN_CON_INIT_Pos) /*!< CAN_T::CON: INIT Mask */
+
+/* CAN STATUS Bit Field Definitions */
+#define CAN_STATUS_BOFF_Pos 7 /*!< CAN_T::STATUS: BOFF Position */
+#define CAN_STATUS_BOFF_Msk (0x1ul << CAN_STATUS_BOFF_Pos) /*!< CAN_T::STATUS: BOFF Mask */
+
+#define CAN_STATUS_EWARN_Pos 6 /*!< CAN_T::STATUS: EWARN Position */
+#define CAN_STATUS_EWARN_Msk (0x1ul << CAN_STATUS_EWARN_Pos) /*!< CAN_T::STATUS: EWARN Mask */
+
+#define CAN_STATUS_EPASS_Pos 5 /*!< CAN_T::STATUS: EPASS Position */
+#define CAN_STATUS_EPASS_Msk (0x1ul << CAN_STATUS_EPASS_Pos) /*!< CAN_T::STATUS: EPASS Mask */
+
+#define CAN_STATUS_RXOK_Pos 4 /*!< CAN_T::STATUS: RXOK Position */
+#define CAN_STATUS_RXOK_Msk (0x1ul << CAN_STATUS_RXOK_Pos) /*!< CAN_T::STATUS: RXOK Mask */
+
+#define CAN_STATUS_TXOK_Pos 3 /*!< CAN_T::STATUS: TXOK Position */
+#define CAN_STATUS_TXOK_Msk (0x1ul << CAN_STATUS_TXOK_Pos) /*!< CAN_T::STATUS: TXOK Mask */
+
+#define CAN_STATUS_LEC_Pos 0 /*!< CAN_T::STATUS: LEC Position */
+#define CAN_STATUS_LEC_Msk (0x7ul << CAN_STATUS_LEC_Pos) /*!< CAN_T::STATUS: LEC Mask */
+
+/* CAN ERR Bit Field Definitions */
+#define CAN_ERR_RP_Pos 15 /*!< CAN_T::ERR: RP Position */
+#define CAN_ERR_RP_Msk (0x1ul << CAN_ERR_RP_Pos) /*!< CAN_T::ERR: RP Mask */
+
+#define CAN_ERR_REC_Pos 8 /*!< CAN_T::ERR: REC Position */
+#define CAN_ERR_REC_Msk (0x7Ful << CAN_ERR_REC_Pos) /*!< CAN_T::ERR: REC Mask */
+
+#define CAN_ERR_TEC_Pos 0 /*!< CAN_T::ERR: TEC Position */
+#define CAN_ERR_TEC_Msk (0xFFul << CAN_ERR_TEC_Pos) /*!< CAN_T::ERR: TEC Mask */
+
+/* CAN BTIME Bit Field Definitions */
+#define CAN_BTIME_TSEG2_Pos 12 /*!< CAN_T::BTIME: TSEG2 Position */
+#define CAN_BTIME_TSEG2_Msk (0x7ul << CAN_BTIME_TSEG2_Pos) /*!< CAN_T::BTIME: TSEG2 Mask */
+
+#define CAN_BTIME_TSEG1_Pos 8 /*!< CAN_T::BTIME: TSEG1 Position */
+#define CAN_BTIME_TSEG1_Msk (0xFul << CAN_BTIME_TSEG1_Pos) /*!< CAN_T::BTIME: TSEG1 Mask */
+
+#define CAN_BTIME_SJW_Pos 6 /*!< CAN_T::BTIME: SJW Position */
+#define CAN_BTIME_SJW_Msk (0x3ul << CAN_BTIME_SJW_Pos) /*!< CAN_T::BTIME: SJW Mask */
+
+#define CAN_BTIME_BRP_Pos 0 /*!< CAN_T::BTIME: BRP Position */
+#define CAN_BTIME_BRP_Msk (0x3Ful << CAN_BTIME_BRP_Pos) /*!< CAN_T::BTIME: BRP Mask */
+
+/* CAN IIDR Bit Field Definitions */
+#define CAN_IIDR_INTID_Pos 0 /*!< CAN_T::IIDR: INTID Position */
+#define CAN_IIDR_INTID_Msk (0xFFFFul << CAN_IIDR_INTID_Pos) /*!< CAN_T::IIDR: INTID Mask */
+
+/* CAN TEST Bit Field Definitions */
+#define CAN_TEST_RX_Pos 7 /*!< CAN_T::TEST: RX Position */
+#define CAN_TEST_RX_Msk (0x1ul << CAN_TEST_RX_Pos) /*!< CAN_T::TEST: RX Mask */
+
+#define CAN_TEST_TX_Pos 5 /*!< CAN_T::TEST: TX Position */
+#define CAN_TEST_TX_Msk (0x3ul << CAN_TEST_TX_Pos) /*!< CAN_T::TEST: TX Mask */
+
+#define CAN_TEST_LBACK_Pos 4 /*!< CAN_T::TEST: LBACK Position */
+#define CAN_TEST_LBACK_Msk (0x1ul << CAN_TEST_LBACK_Pos) /*!< CAN_T::TEST: LBACK Mask */
+
+#define CAN_TEST_SILENT_Pos 3 /*!< CAN_T::TEST: Silent Position */
+#define CAN_TEST_SILENT_Msk (0x1ul << CAN_TEST_SILENT_Pos) /*!< CAN_T::TEST: Silent Mask */
+
+#define CAN_TEST_BASIC_Pos 2 /*!< CAN_T::TEST: Basic Position */
+#define CAN_TEST_BASIC_Msk (0x1ul << CAN_TEST_BASIC_Pos) /*!< CAN_T::TEST: Basic Mask */
+
+/* CAN BPRE Bit Field Definitions */
+#define CAN_BRPE_BRPE_Pos 0 /*!< CAN_T::BRPE: BRPE Position */
+#define CAN_BRPE_BRPE_Msk (0xFul << CAN_BRPE_BRPE_Pos) /*!< CAN_T::BRPE: BRPE Mask */
+
+/* CAN IFn_CREQ Bit Field Definitions */
+#define CAN_IF_CREQ_BUSY_Pos 15 /*!< CAN_IF_T::CREQ: BUSY Position */
+#define CAN_IF_CREQ_BUSY_Msk (0x1ul << CAN_IF_CREQ_BUSY_Pos) /*!< CAN_IF_T::CREQ: BUSY Mask */
+
+#define CAN_IF_CREQ_MSGNUM_Pos 0 /*!< CAN_IF_T::CREQ: MSGNUM Position */
+#define CAN_IF_CREQ_MSGNUM_Msk (0x3Ful << CAN_IF_CREQ_MSGNUM_Pos) /*!< CAN_IF_T::CREQ: MSGNUM Mask */
+
+/* CAN IFn_CMASK Bit Field Definitions */
+#define CAN_IF_CMASK_WRRD_Pos 7 /*!< CAN_IF_T::CMASK: WRRD Position */
+#define CAN_IF_CMASK_WRRD_Msk (0x1ul << CAN_IF_CMASK_WRRD_Pos) /*!< CAN_IF_T::CMASK: WRRD Mask */
+
+#define CAN_IF_CMASK_MASK_Pos 6 /*!< CAN_IF_T::CMASK: MASK Position */
+#define CAN_IF_CMASK_MASK_Msk (0x1ul << CAN_IF_CMASK_MASK_Pos) /*!< CAN_IF_T::CMASK: MASK Mask */
+
+#define CAN_IF_CMASK_ARB_Pos 5 /*!< CAN_IF_T::CMASK: ARB Position */
+#define CAN_IF_CMASK_ARB_Msk (0x1ul << CAN_IF_CMASK_ARB_Pos) /*!< CAN_IF_T::CMASK: ARB Mask */
+
+#define CAN_IF_CMASK_CONTROL_Pos 4 /*!< CAN_IF_T::CMASK: CONTROL Position */
+#define CAN_IF_CMASK_CONTROL_Msk (0x1ul << CAN_IF_CMASK_CONTROL_Pos) /*!< CAN_IF_T::CMASK: CONTROL Mask */
+
+#define CAN_IF_CMASK_CLRINTPND_Pos 3 /*!< CAN_IF_T::CMASK: CLRINTPND Position */
+#define CAN_IF_CMASK_CLRINTPND_Msk (0x1ul << CAN_IF_CMASK_CLRINTPND_Pos) /*!< CAN_IF_T::CMASK: CLRINTPND Mask */
+
+#define CAN_IF_CMASK_TXRQSTNEWDAT_Pos 2 /*!< CAN_IF_T::CMASK: TXRQSTNEWDAT Position */
+#define CAN_IF_CMASK_TXRQSTNEWDAT_Msk (0x1ul << CAN_IF_CMASK_TXRQSTNEWDAT_Pos) /*!< CAN_IF_T::CMASK: TXRQSTNEWDAT Mask */
+
+#define CAN_IF_CMASK_DATAA_Pos 1 /*!< CAN_IF_T::CMASK: DATAA Position */
+#define CAN_IF_CMASK_DATAA_Msk (0x1ul << CAN_IF_CMASK_DATAA_Pos) /*!< CAN_IF_T::CMASK: DATAA Mask */
+
+#define CAN_IF_CMASK_DATAB_Pos 0 /*!< CAN_IF_T::CMASK: DATAB Position */
+#define CAN_IF_CMASK_DATAB_Msk (0x1ul << CAN_IF_CMASK_DATAB_Pos) /*!< CAN_IF_T::CMASK: DATAB Mask */
+
+/* CAN IFn_MASK1 Bit Field Definitions */
+#define CAN_IF_MASK1_MSK_Pos 0 /*!< CAN_IF_T::MASK1: MSK Position */
+#define CAN_IF_MASK1_MSK_Msk (0xFFul << CAN_IF_MASK1_MSK_Pos) /*!< CAN_IF_T::MASK1: MSK Mask */
+
+/* CAN IFn_MASK2 Bit Field Definitions */
+#define CAN_IF_MASK2_MXTD_Pos 15 /*!< CAN_IF_T::MASK2: MXTD Position */
+#define CAN_IF_MASK2_MXTD_Msk (0x1ul << CAN_IF_MASK2_MXTD_Pos) /*!< CAN_IF_T::MASK2: MXTD Mask */
+
+#define CAN_IF_MASK2_MDIR_Pos 14 /*!< CAN_IF_T::MASK2: MDIR Position */
+#define CAN_IF_MASK2_MDIR_Msk (0x1ul << CAN_IF_MASK2_MDIR_Pos) /*!< CAN_IF_T::MASK2: MDIR Mask */
+
+#define CAN_IF_MASK2_MSK_Pos 0 /*!< CAN_IF_T::MASK2: MSK Position */
+#define CAN_IF_MASK2_MSK_Msk (0x1FFul << CAN_IF_MASK2_MSK_Pos) /*!< CAN_IF_T::MASK2: MSK Mask */
+
+/* CAN IFn_ARB1 Bit Field Definitions */
+#define CAN_IF_ARB1_ID_Pos 0 /*!< CAN_IF_T::ARB1: ID Position */
+#define CAN_IF_ARB1_ID_Msk (0xFFFFul << CAN_IF_ARB1_ID_Pos) /*!< CAN_IF_T::ARB1: ID Mask */
+
+/* CAN IFn_ARB2 Bit Field Definitions */
+#define CAN_IF_ARB2_MSGVAL_Pos 15 /*!< CAN_IF_T::ARB2: MSGVAL Position */
+#define CAN_IF_ARB2_MSGVAL_Msk (0x1ul << CAN_IF_ARB2_MSGVAL_Pos) /*!< CAN_IF_T::ARB2: MSGVAL Mask */
+
+#define CAN_IF_ARB2_XTD_Pos 14 /*!< CAN_IF_T::ARB2: XTD Position */
+#define CAN_IF_ARB2_XTD_Msk (0x1ul << CAN_IF_ARB2_XTD_Pos) /*!< CAN_IF_T::ARB2: XTD Mask */
+
+#define CAN_IF_ARB2_DIR_Pos 13 /*!< CAN_IF_T::ARB2: DIR Position */
+#define CAN_IF_ARB2_DIR_Msk (0x1ul << CAN_IF_ARB2_DIR_Pos) /*!< CAN_IF_T::ARB2: DIR Mask */
+
+#define CAN_IF_ARB2_ID_Pos 0 /*!< CAN_IF_T::ARB2: ID Position */
+#define CAN_IF_ARB2_ID_Msk (0x1FFFul << CAN_IF_ARB2_ID_Pos) /*!< CAN_IF_T::ARB2: ID Mask */
+
+/* CAN IFn_MCON Bit Field Definitions */
+#define CAN_IF_MCON_NEWDAT_Pos 15 /*!< CAN_IF_T::MCON: NEWDAT Position */
+#define CAN_IF_MCON_NEWDAT_Msk (0x1ul << CAN_IF_MCON_NEWDAT_Pos) /*!< CAN_IF_T::MCON: NEWDAT Mask */
+
+#define CAN_IF_MCON_MSGLST_Pos 14 /*!< CAN_IF_T::MCON: MSGLST Position */
+#define CAN_IF_MCON_MSGLST_Msk (0x1ul << CAN_IF_MCON_MSGLST_Pos) /*!< CAN_IF_T::MCON: MSGLST Mask */
+
+#define CAN_IF_MCON_INTPND_Pos 13 /*!< CAN_IF_T::MCON: INTPND Position */
+#define CAN_IF_MCON_INTPND_Msk (0x1ul << CAN_IF_MCON_INTPND_Pos) /*!< CAN_IF_T::MCON: INTPND Mask */
+
+#define CAN_IF_MCON_UMASK_Pos 12 /*!< CAN_IF_T::MCON: UMASK Position */
+#define CAN_IF_MCON_UMASK_Msk (0x1ul << CAN_IF_MCON_UMASK_Pos) /*!< CAN_IF_T::MCON: UMASK Mask */
+
+#define CAN_IF_MCON_TXIE_Pos 11 /*!< CAN_IF_T::MCON: TXIE Position */
+#define CAN_IF_MCON_TXIE_Msk (0x1ul << CAN_IF_MCON_TXIE_Pos) /*!< CAN_IF_T::MCON: TXIE Mask */
+
+#define CAN_IF_MCON_RXIE_Pos 10 /*!< CAN_IF_T::MCON: RXIE Position */
+#define CAN_IF_MCON_RXIE_Msk (0x1ul << CAN_IF_MCON_RXIE_Pos) /*!< CAN_IF_T::MCON: RXIE Mask */
+
+#define CAN_IF_MCON_RMTEN_Pos 9 /*!< CAN_IF_T::MCON: RMTEN Position */
+#define CAN_IF_MCON_RMTEN_Msk (0x1ul << CAN_IF_MCON_RMTEN_Pos) /*!< CAN_IF_T::MCON: RMTEN Mask */
+
+#define CAN_IF_MCON_TXRQST_Pos 8 /*!< CAN_IF_T::MCON: TXRQST Position */
+#define CAN_IF_MCON_TXRQST_Msk (0x1ul << CAN_IF_MCON_TXRQST_Pos) /*!< CAN_IF_T::MCON: TXRQST Mask */
+
+#define CAN_IF_MCON_EOB_Pos 7 /*!< CAN_IF_T::MCON: EOB Position */
+#define CAN_IF_MCON_EOB_Msk (0x1ul << CAN_IF_MCON_EOB_Pos) /*!< CAN_IF_T::MCON: EOB Mask */
+
+#define CAN_IF_MCON_DLC_Pos 0 /*!< CAN_IF_T::MCON: DLC Position */
+#define CAN_IF_MCON_DLC_Msk (0xFul << CAN_IF_MCON_DLC_Pos) /*!< CAN_IF_T::MCON: DLC Mask */
+
+/* CAN IFn_DATA_A1 Bit Field Definitions */
+#define CAN_IF_DAT_A1_DATA1_Pos 8 /*!< CAN_IF_T::DATAA1: DATA1 Position */
+#define CAN_IF_DAT_A1_DATA1_Msk (0xFFul << CAN_IF_DAT_A1_DATA1_Pos) /*!< CAN_IF_T::DATAA1: DATA1 Mask */
+
+#define CAN_IF_DAT_A1_DATA0_Pos 0 /*!< CAN_IF_T::DATAA1: DATA0 Position */
+#define CAN_IF_DAT_A1_DATA0_Msk (0xFFul << CAN_IF_DAT_A1_DATA0_Pos) /*!< CAN_IF_T::DATAA1: DATA0 Mask */
+
+/* CAN IFn_DATA_A2 Bit Field Definitions */
+#define CAN_IF_DAT_A2_DATA3_Pos 8 /*!< CAN_IF_T::DATAA1: DATA3 Position */
+#define CAN_IF_DAT_A2_DATA3_Msk (0xFFul << CAN_IF_DAT_A2_DATA3_Pos) /*!< CAN_IF_T::DATAA1: DATA3 Mask */
+
+#define CAN_IF_DAT_A2_DATA2_Pos 0 /*!< CAN_IF_T::DATAA1: DATA2 Position */
+#define CAN_IF_DAT_A2_DATA2_Msk (0xFFul << CAN_IF_DAT_A2_DATA2_Pos) /*!< CAN_IF_T::DATAA1: DATA2 Mask */
+
+/* CAN IFn_DATA_B1 Bit Field Definitions */
+#define CAN_IF_DAT_B1_DATA5_Pos 8 /*!< CAN_IF_T::DATAB1: DATA5 Position */
+#define CAN_IF_DAT_B1_DATA5_Msk (0xFFul << CAN_IF_DAT_B1_DATA5_Pos) /*!< CAN_IF_T::DATAB1: DATA5 Mask */
+
+#define CAN_IF_DAT_B1_DATA4_Pos 0 /*!< CAN_IF_T::DATAB1: DATA4 Position */
+#define CAN_IF_DAT_B1_DATA4_Msk (0xFFul << CAN_IF_DAT_B1_DATA4_Pos) /*!< CAN_IF_T::DATAB1: DATA4 Mask */
+
+/* CAN IFn_DATA_B2 Bit Field Definitions */
+#define CAN_IF_DAT_B2_DATA7_Pos 8 /*!< CAN_IF_T::DATAB2: DATA7 Position */
+#define CAN_IF_DAT_B2_DATA7_Msk (0xFFul << CAN_IF_DAT_B2_DATA7_Pos) /*!< CAN_IF_T::DATAB2: DATA7 Mask */
+
+#define CAN_IF_DAT_B2_DATA6_Pos 0 /*!< CAN_IF_T::DATAB2: DATA6 Position */
+#define CAN_IF_DAT_B2_DATA6_Msk (0xFFul << CAN_IF_DAT_B2_DATA6_Pos) /*!< CAN_IF_T::DATAB2: DATA6 Mask */
+
+/* CAN IFn_TXRQST1 Bit Field Definitions */
+#define CAN_TXRQST1_TXRQST_Pos 0 /*!< CAN_T::TXRQST1: TXRQST Position */
+#define CAN_TXRQST1_TXRQST_Msk (0xFFFFul << CAN_TXRQST1_TXRQST_Pos) /*!< CAN_T::TXRQST1: TXRQST Mask */
+
+/* CAN IFn_TXRQST2 Bit Field Definitions */
+#define CAN_TXRQST2_TXRQST_Pos 0 /*!< CAN_T::TXRQST2: TXRQST Position */
+#define CAN_TXRQST2_TXRQST_Msk (0xFFFFul << CAN_TXRQST2_TXRQST_Pos) /*!< CAN_T::TXRQST2: TXRQST Mask */
+
+/* CAN IFn_NDAT1 Bit Field Definitions */
+#define CAN_NDAT1_NEWDATA_Pos 0 /*!< CAN_T::NDAT1: NEWDATA Position */
+#define CAN_NDAT1_NEWDATA_Msk (0xFFFFul << CAN_NDAT1_NEWDATA_Pos) /*!< CAN_T::NDAT1: NEWDATA Mask */
+
+/* CAN IFn_NDAT2 Bit Field Definitions */
+#define CAN_NDAT2_NEWDATA_Pos 0 /*!< CAN_T::NDAT2: NEWDATA Position */
+#define CAN_NDAT2_NEWDATA_Msk (0xFFFFul << CAN_NDAT2_NEWDATA_Pos) /*!< CAN_T::NDAT2: NEWDATA Mask */
+
+/* CAN IFn_IPND1 Bit Field Definitions */
+#define CAN_IPND1_INTPND_Pos 0 /*!< CAN_T::IPND1: INTPND Position */
+#define CAN_IPND1_INTPND_Msk (0xFFFFul << CAN_IPND1_INTPND_Pos) /*!< CAN_T::IPND1: INTPND Mask */
+
+/* CAN IFn_IPND2 Bit Field Definitions */
+#define CAN_IPND2_INTPND_Pos 0 /*!< CAN_T::IPND2: INTPND Position */
+#define CAN_IPND2_INTPND_Msk (0xFFFFul << CAN_IPND2_INTPND_Pos) /*!< CAN_T::IPND2: INTPND Mask */
+
+/* CAN IFn_MVLD1 Bit Field Definitions */
+#define CAN_MVLD1_MSGVAL_Pos 0 /*!< CAN_T::MVLD1: MSGVAL Position */
+#define CAN_MVLD1_MSGVAL_Msk (0xFFFFul << CAN_MVLD1_MSGVAL_Pos) /*!< CAN_T::MVLD1: MSGVAL Mask */
+
+/* CAN IFn_MVLD2 Bit Field Definitions */
+#define CAN_MVLD2_MSGVAL_Pos 0 /*!< CAN_T::MVLD2: MSGVAL Position */
+#define CAN_MVLD2_MSGVAL_Msk (0xFFFFul << CAN_MVLD2_MSGVAL_Pos) /*!< CAN_T::MVLD2: MSGVAL Mask */
+
+/* CAN WUEN Bit Field Definitions */
+#define CAN_WUEN_WAKUP_EN_Pos 0 /*!< CAN_T::WU_EN: WAKUP_EN Position */
+#define CAN_WUEN_WAKUP_EN_Msk (0x1ul << CAN_WUEN_WAKUP_EN_Pos) /*!< CAN_T::WU_EN: WAKUP_EN Mask */
+
+/* CAN WUSTATUS Bit Field Definitions */
+#define CAN_WUSTATUS_WAKUP_STS_Pos 0 /*!< CAN_T::WU_STATUS: WAKUP_STS Position */
+#define CAN_WUSTATUS_WAKUP_STS_Msk (0x1ul << CAN_WUSTATUS_WAKUP_STS_Pos) /*!< CAN_T::WU_STATUS: WAKUP_STS Mask */
+
+
+/**@}*/ /* CAN_CONST */
+/**@}*/ /* end of CAN register group */
+
+
+/*---------------------- System Clock Controller -------------------------*/
+/**
+ @addtogroup CLK System Clock Controller(CLK)
+ Memory Mapped Structure for CLK Controller
+@{ */
+
+
+typedef struct
+{
+
+
+
+
+/**
+ * @var CLK_T::PWRCTL
+ * Offset: 0x00 System Power-down Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |HXTEN |External 4~24 MHz High-Speed Crystal Enable Bit (Write Protect)
+ * | | |The bit default value is set by flash controller user configuration register CONFIG0 [26:24].
+ * | | |When the default clock source is from external 4~24 MHz high-speed crystal, this bit is set to 1 automatically.
+ * | | |0 = External 4 ~ 24 MHz high speed crystal oscillator (HXT) Disabled.
+ * | | |1 = External 4 MH~ 24 z high speed crystal oscillator (HXT) Enabled.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[1] |LXTEN |External 32.768 KHz Low-Speed Crystal Enable Bit (Write Protect)
+ * | | |0 = External 32.768 kHz low-speed crystal oscillator (LXT) Disabled.
+ * | | |1 = External 32.768 kHz low-speed crystal oscillator (LXT) Enabled.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[2] |HIRCEN |Internal 22.1184 MHz High-Speed Oscillator Enable Bit (Write Protect)
+ * | | |0 = Internal 22.1184 MHz high-speed RC oscillator (HIRC) Disabled.
+ * | | |1 = Internal 22.1184 MHz high-speed RC oscillator (HIRC) Enabled.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[3] |LIRCEN |Internal 10 KHz Low-Speed Oscillator Enable Bit (Write Protect)
+ * | | |0 = Internal 10 kHz low speed RC oscillator (LIRC) Disabled.
+ * | | |1 = Internal 10 kHz low speed RC oscillator (LIRC) Enabled.
+ * |[4] |PDWKDLY |Enable The Wake-Up Delay Counter (Write Protect)
+ * | | |When the chip wakes up from Power-down mode, the clock control will delay certain clock cycles to wait system clock stable.
+ * | | |The delayed clock cycle is 4096 clock cycles when chip work at external 4~24 MHz high-speed crystal, and 256 clock cycles when chip work at internal 22.1184 MHz high-speed oscillator.
+ * | | |0 = Clock cycles delay Disabled.
+ * | | |1 = Clock cycles delay Enabled.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[5] |PDWKIEN |Power-Down Mode Wake-Up Interrupt Enable Bit (Write Protect)
+ * | | |0 = Power-down Mode Wake-up Interrupt Disabled.
+ * | | |1 = Power-down Mode Wake-up Interrupt Enabled.
+ * | | |Note1: The interrupt will occur when both PDWKIF and PDWKIEN are high.
+ * | | |Note2: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[6] |PDWKIF |Power-Down Mode Wake-Up Interrupt Status
+ * | | |Set by "Power-down wake-up event", it indicates that resume from Power-down mode
+ * | | |The flag is set if the EINT0~5, GPIO, USBH, USBD, OTG, UART0~3, WDT, CAN0, ACMP01, BOD, RTC, TMR0~3, I2C0~1 or TK wake-up occurred.
+ * | | |Note1: Write 1 to clear the bit to 0.
+ * | | |Note2: This bit works only if PDWKIEN (CLK_PWRCTL[5]) set to 1.
+ * |[7] |PDEN |System Power-Down Enable (Write Protect)
+ * | | |When this bit is set to 1, Power-down mode is enabled and chip Power-down behavior will depend on the PDWTCPU bit.
+ * | | |(a) If the PDWTCPU is 0, then the chip enters Power-down mode immediately after the PDEN bit set.(default)
+ * | | |(b) if the PDWTCPU is 1, then the chip keeps active till the CPU sleep mode is also active and then the chip enters Power-down mode.
+ * | | |When chip wakes up from Power-down mode, this bit is auto cleared.
+ * | | |Users need to set this bit again for next Power-down.
+ * | | |In Power-down mode, external 4~24 MHz high-speed crystal and the internal 22.1184 MHz high-speed oscillator will be disabled in this mode, but the external 32.768 kHz low-speed crystal and internal 10 kHz low-speed oscillator are not controlled by Power-down mode.
+ * | | |In Power-down mode, the PLL and system clock are disabled, and ignored the clock source selection.
+ * | | |The clocks of peripheral are not controlled by Power-down mode, if the peripheral clock source is from external 32.768 kHz low-speed crystal or the internal 10 kHz low-speed oscillator.
+ * | | |0 = Chip operating normally or chip in idle mode because of WFI command.
+ * | | |1 = Chip enters Power-down mode instant or wait CPU sleep command WFI.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[8] |PDWTCPU |This Bit Control The Power-Down Entry Condition (Write Protect)
+ * | | |0 = Chip enters Power-down mode when the PDEN bit is set to 1.
+ * | | |1 = Chip enters Power-down mode when the both PDWTCPU and PDEN bits are set to 1 and CPU run WFI instruction.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[11:10] |HXTGAIN |4~24 MHz High-Speed Crystal Gain Control Bit
+ * | | |(Write Protect)
+ * | | |This is a protected register. Please refer to open lock sequence to program it.
+ * | | |Gain control is used to enlarge the gain of crystal to make sure crystal work normally.
+ * | | |If gain control is enabled, crystal will consume more power than gain control off.
+ * | | |00 = HXT frequency is lower than from 8 MHz.
+ * | | |01 = HXT frequency is from 8 MHz to 12 MHz.
+ * | | |10 = HXT frequency is from 12 MHz to 16 MHz.
+ * | | |11 = HXT frequency is higher than 16 MHz.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[12] |HXTSELTYP |4~24 MHz High-Speed Crystal Type Select Bit (Write Protect)
+ * | | |This is a protected register. Please refer to open lock sequence to program it.
+ * | | |0 = Select INV type.
+ * | | |1 = Select GM type.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * @var CLK_T::AHBCLK
+ * Offset: 0x04 AHB Devices Clock Enable Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[1] |PDMACKEN |PDMA Controller Clock Enable Bit
+ * | | |0 = PDMA peripheral clock Disabled.
+ * | | |1 = PDMA peripheral clock Enabled.
+ * |[2] |ISPCKEN |Flash ISP Controller Clock Enable Bit
+ * | | |0 = Flash ISP peripheral clock Disabled.
+ * | | |1 = Flash ISP peripheral clock Enabled.
+ * |[3] |EBICKEN |EBI Controller Clock Enable Bit
+ * | | |0 = EBI peripheral clock Disabled.
+ * | | |1 = EBI peripheral clock Enabled.
+ * |[4] |USBHCKEN |USB HOST Controller Clock Enable Bit
+ * | | |0 = USB HOST peripheral clock Disabled.
+ * | | |1 = USB HOST peripheral clock Enabled.
+ * |[7] |CRCCKEN |CRC Generator Controller Clock Enable Bit
+ * | | |0 = CRC peripheral clock Disabled.
+ * | | |1 = CRC peripheral clock Enabled.
+ * |[15] |FMCIDLE |Flash Memory Controller Clock Enable Bit In IDLE Mode
+ * | | |0 = FMC peripheral clock Disabled when chip operating at IDLE mode.
+ * | | |1 = FMC peripheral clock Enabled when chip operating at IDLE mode.
+ * @var CLK_T::APBCLK0
+ * Offset: 0x08 APB Devices Clock Enable Control Register 0
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |WDTCKEN |Watchdog Timer Clock Enable Bit (Write Protect)
+ * | | |0 = Watchdog Timer Clock Disabled.
+ * | | |1 = Watchdog Timer Clock Enabled.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[1] |RTCCKEN |Real-Time-Clock APB Interface Clock Enable Bit
+ * | | |This bit is used to control the RTC APB clock only.
+ * | | |The RTC peripheral clock source is selected from RTCSEL(CLK_CLKSEL3[8]).
+ * | | |It can be selected to external 32.768 kHz low speed crystal or internal 10 kHz low speed oscillator.
+ * | | |0 = RTC Clock Disabled.
+ * | | |1 = RTC Clock Enabled.
+ * |[2] |TMR0CKEN |Timer0 Clock Enable Bit
+ * | | |0 = Timer0 Clock Disabled.
+ * | | |1 = Timer0 Clock Enabled.
+ * |[3] |TMR1CKEN |Timer1 Clock Enable Bit
+ * | | |0 = Timer1 Clock Disabled.
+ * | | |1 = Timer1 Clock Enabled.
+ * |[4] |TMR2CKEN |Timer2 Clock Enable Bit
+ * | | |0 = Timer2 Clock Disabled.
+ * | | |1 = Timer2 Clock Enabled.
+ * |[5] |TMR3CKEN |Timer3 Clock Enable Bit
+ * | | |0 = Timer3 Clock Disabled.
+ * | | |1 = Timer3 Clock Enabled.
+ * |[6] |CLKOCKEN |CLKO Clock Enable Bit
+ * | | |0 = CLKO Clock Disabled.
+ * | | |1 = CLKO Clock Enabled.
+ * |[7] |ACMP01CKEN|Analog Comparator 0/1 Clock Enable Bit
+ * | | |0 = Analog Comparator 0/1 Clock Disabled.
+ * | | |1 = Analog Comparator 0/1 Clock Enabled.
+ * |[8] |I2C0CKEN |I2C0 Clock Enable Bit
+ * | | |0 = I2C0 Clock Disabled.
+ * | | |1 = I2C0 Clock Enabled.
+ * |[9] |I2C1CKEN |I2C1 Clock Enable Bit
+ * | | |0 = I2C1 Clock Disabled.
+ * | | |1 = I2C1 Clock Enabled.
+ * |[12] |SPI0CKEN |SPI0 Clock Enable Bit
+ * | | |0 = SPI0 Clock Disabled.
+ * | | |1 = SPI0 Clock Enabled.
+ * |[13] |SPI1CKEN |SPI1 Clock Enable Bit
+ * | | |0 = SPI1 Clock Disabled.
+ * | | |1 = SPI1 Clock Enabled.
+ * |[14] |SPI2CKEN |SPI2 Clock Enable Bit
+ * | | |0 = SPI2 Clock Disabled.
+ * | | |1 = SPI2 Clock Enabled.
+ * |[16] |UART0CKEN |UART0 Clock Enable Bit
+ * | | |0 = UART0 clock Disabled.
+ * | | |1 = UART0 clock Enabled.
+ * |[17] |UART1CKEN |UART1 Clock Enable Bit
+ * | | |0 = UART1 clock Disabled.
+ * | | |1 = UART1 clock Enabled.
+ * |[18] |UART2CKEN |UART2 Clock Enable Bit
+ * | | |0 = UART2 clock Disabled.
+ * | | |1 = UART2 clock Enabled.
+ * |[19] |UART3CKEN |UART3 Clock Enable Bit
+ * | | |0 = UART3 clock Disabled.
+ * | | |1 = UART3 clock Enabled.
+ * |[24] |CAN0CKEN |CAN0 Clock Enable Bit
+ * | | |0 = CAN0 clock Disabled.
+ * | | |1 = CAN0 clock Enabled.
+ * |[26] |OTGCKEN |USB OTG Clock Enable Bit
+ * | | |0 = USB OTG clock Disabled.
+ * | | |1 = USB OTG clock Enabled.
+ * |[27] |USBDCKEN |USB Device Clock Enable Bit
+ * | | |0 = USB Device clock Disabled.
+ * | | |1 = USB Device clock Enabled.
+ * |[28] |EADCCKEN |Enhanced Analog-Digital-Converter (EADC) Clock Enable Bit
+ * | | |0 = EADC clock Disabled.
+ * | | |1 = EADC clock Enabled.
+ * @var CLK_T::APBCLK1
+ * Offset: 0x0C APB Devices Clock Enable Control Register 1
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |SC0CKEN |SC0 Clock Enable Bit
+ * | | |0 = SC0 Clock Disabled.
+ * | | |1 = SC0 Clock Enabled.
+ * |[12] |DACCKEN |DAC Clock Enable Bit
+ * | | |0 = DAC Clock Disabled.
+ * | | |1 = DAC Clock Enabled.
+ * |[16] |PWM0CKEN |PWM0 Clock Enable Bit
+ * | | |0 = PWM0 Clock Disabled.
+ * | | |1 = PWM0 Clock Enabled.
+ * |[17] |PWM1CKEN |PWM1 Clock Enable Bit
+ * | | |0 = PWM1 Clock Disabled.
+ * | | |1 = PWM1 Clock Enabled.
+ * |[25] |TKCKEN |Touch Key Clock Enable Bit
+ * | | |0 = Touch Key Clock Disabled.
+ * | | |1 = Touch key Clock Enabled.
+ * @var CLK_T::CLKSEL0
+ * Offset: 0x10 Clock Source Select Control Register 0
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[2:0] |HCLKSEL |HCLK Clock Source Selection (Write Protect)
+ * | | |Before clock switching, the related clock sources (both pre-select and new-select) must be turned on.
+ * | | |The default value is reloaded from the value of CFOSC (CONFIG0[26:24]) in user configuration register of Flash controller by any reset.
+ * | | |Therefore the default value is either 000b or 111b.
+ * | | |000 = Clock source from external 4~24 MHz high-speed crystal clock.
+ * | | |001 = Clock source from external 32.768 kHz low-speed crystal clock.
+ * | | |010 = Clock source from PLL clock.
+ * | | |011 = Clock source from internal 10 kHz low-speed oscillator clock.
+ * | | |111= Clock source from internal 22.1184 MHz high-speed oscillator clock.
+ * | | |Other = Reserved.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[5:3] |STCLKSEL |Cortex-M4 SysTick Clock Source Selection (Write Protect)
+ * | | |If SYST_CTRL[2]=0, SysTick uses listed clock source below.
+ * | | |000 = Clock source from external 4~24 MHz high-speed crystal clock.
+ * | | |001 = Clock source from external 32.768 kHz low-speed crystal clock.
+ * | | |010 = Clock source from external 4~24 MHz high-speed crystal clock/2.
+ * | | |011 = Clock source from HCLK/2.
+ * | | |111 = Clock source from internal 22.1184 MHz high-speed oscillator clock/2.
+ * | | |Note: if SysTick clock source is not from HCLK (i.e.
+ * | | |SYST_CTRL[2] = 0), SysTick clock source must less than or equal to HCLK/2.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[6] |PCLK0SEL |PCLK0 Clock Source Selection (Write Protect)
+ * | | |0 = APB0 BUS clock source from HCLK.
+ * | | |1 = APB0 BUS clock source from HCLK/2.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[7] |PCLK1SEL |PCLK1 Clock Source Selection (Write Protect)
+ * | | |0 = APB1 BUS clock source from HCLK.
+ * | | |1 = APB1 BUS clock source from HCLK/2.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * @var CLK_T::CLKSEL1
+ * Offset: 0x14 Clock Source Select Control Register 1
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[1:0] |WDTSEL |Watchdog Timer Clock Source Selection (Write Protect)
+ * | | |00 = Reserved.
+ * | | |01 = Clock source from external 32.768 kHz low-speed crystal clock.
+ * | | |10 = Clock source from PCLK0/2048 clock.
+ * | | |11 = Clock source from internal 10 kHz low-speed oscillator clock.
+ * |[10:8] |TMR0SEL |TIMER0 Clock Source Selection
+ * | | |000 = Clock source from external 4~24 MHz high-speed crystal clock.
+ * | | |001 = Clock source from external 32.768 kHz low-speed crystal clock.
+ * | | |010 = Clock source from PCLK0.
+ * | | |011 = Clock source from external clock T0 pin
+ * | | |101 = Clock source from internal 10 kHz low-speed oscillator clock.
+ * | | |111 = Clock source from internal 22.1184 MHz high-speed oscillator clock.
+ * | | |Others = Reserved.
+ * |[14:12] |TMR1SEL |TIMER1 Clock Source Selection
+ * | | |000 = Clock source from external 4~24 MHz high-speed crystal clock.
+ * | | |001 = Clock source from external 32.768 kHz low-speed crystal clock.
+ * | | |010 = Clock source from PCLK0.
+ * | | |011 = Clock source from external clock T1 pin
+ * | | |101 = Clock source from internal 10 kHz low-speed oscillator clock.
+ * | | |111 = Clock source from internal 22.1184 MHz high-speed oscillator clock.
+ * | | |Others = Reserved.
+ * |[18:16] |TMR2SEL |TIMER2 Clock Source Selection
+ * | | |000 = Clock source from external 4~24 MHz high-speed crystal clock.
+ * | | |001 = Clock source from external 32.768 kHz low-speed crystal clock.
+ * | | |010 = Clock source from PCLK1.
+ * | | |011 = Clock source from external clock T2 pin
+ * | | |101 = Clock source from internal 10 kHz low-speed oscillator clock.
+ * | | |111 = Clock source from internal 22.1184 MHz high-speed oscillator clock.
+ * | | |Others = Reserved.
+ * |[22:20] |TMR3SEL |TIMER3 Clock Source Selection
+ * | | |000 = Clock source from external 4~24 MHz high-speed crystal clock.
+ * | | |001 = Clock source from external 32.768 kHz low-speed crystal clock.
+ * | | |010 = Clock source from PCLK1.
+ * | | |011 = Clock source from external clock T3 pin.
+ * | | |101 = Clock source from internal 10 kHz low-speed oscillator clock.
+ * | | |111 = Clock source from internal 22.1184 MHz high-speed oscillator clock.
+ * | | |Others = Reserved.
+ * |[25:24] |UARTSEL |UART Clock Source Selection
+ * | | |00 = Clock source from external 4~24 MHz high-speed crystal clock (HXT).
+ * | | |01 = Clock source from PLL clock.
+ * | | |10 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT).
+ * | | |11 = Clock source from internal 22.1184 MHz high-speed oscillator clock (HIRC).
+ * |[29:28] |CLKOSEL |Clock Divider Clock Source Selection
+ * | | |00 = Clock source from external 4~24 MHz high-speed crystal clock.
+ * | | |01 = Clock source from external 32.768 kHz low-speed crystal clock.
+ * | | |10 = Clock source from HCLK.
+ * | | |11 = Clock source from internal 22.1184 MHz high-speed oscillator clock.
+ * |[31:30] |WWDTSEL |Window Watchdog Timer Clock Source Selection
+ * | | |10 = Clock source from PCLK0/2048 clock.
+ * | | |11 = Clock source from internal 10 kHz low-speed oscillator clock.
+ * | | |Others = Reserved.
+ * @var CLK_T::CLKSEL2
+ * Offset: 0x18 Clock Source Select Control Register 2
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |PWM0SEL |PWM0 Clock Source Selection
+ * | | |The peripheral clock source of PWM0 is defined by PWM0SEL.
+ * | | |0 = Clock source from PLL clock.
+ * | | |1 = Clock source from PCLK0.
+ * |[1] |PWM1SEL |PWM1 Clock Source Selection
+ * | | |The peripheral clock source of PWM1 is defined by PWM1SEL.
+ * | | |0 = Clock source from PLL clock.
+ * | | |1 = Clock source from PCLK1.
+ * |[3:2] |SPI0SEL |SPI0 Clock Source Selection
+ * | | |00 = Clock source from external 4~24 MHz high speed crystal oscillator clock.
+ * | | |01 = Clock source from PLL clock.
+ * | | |10 = Clock source from PCLK0.
+ * | | |11 = Clock source from internal 22.1184 MHz high speed oscillator clock.
+ * |[5:4] |SPI1SEL |SPI1 Clock Source Selection
+ * | | |00 = Clock source from external 4~24 MHz high speed crystal oscillator clock.
+ * | | |01 = Clock source from PLL clock.
+ * | | |10 = Clock source from PCLK1.
+ * | | |11 = Clock source from internal 22.1184 MHz high speed oscillator clock.
+ * |[7:6] |SPI2SEL |SPI2 Clock Source Selection
+ * | | |00 = Clock source from external 4~24 MHz high speed crystal oscillator clock.
+ * | | |01 = Clock source from PLL clock.
+ * | | |10 = Clock source from PCLK0.
+ * | | |11 = Clock source from internal 22.1184 MHz high speed oscillator clock.
+ * @var CLK_T::CLKSEL3
+ * Offset: 0x1C Clock Source Select Control Register 3
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[1:0] |SC0SEL |SC0 Clock Source Selection
+ * | | |00 = Clock source from external 4~24 MHz high-speed crystal clock.
+ * | | |01 = Clock source from PLL clock.
+ * | | |10 = Clock source from PCLK0.
+ * | | |11 = Clock source from internal 22.1184 MHz high-speed oscillator clock.
+ * |[8] |RTCSEL |RTC Clock Source Selection
+ * | | |0 = Clock source from external 32.768 kHz low-speed oscillator.
+ * | | |1 = Clock source from internal 10 kHz low speed RC oscillator.
+ * @var CLK_T::CLKDIV0
+ * Offset: 0x20 Clock Divider Number Register 0
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[3:0] |HCLKDIV |HCLK Clock Divide Number From HCLK Clock Source
+ * | | |HCLK clock frequency = (HCLK clock source frequency) / (HCLKDIV + 1).
+ * |[7:4] |USBDIV |USB Clock Divide Number From PLL Clock
+ * | | |USB clock frequency = (PLL frequency) / (USBDIV + 1).
+ * |[11:8] |UARTDIV |UART Clock Divide Number From UART Clock Source
+ * | | |UART clock frequency = (UART clock source frequency) / (UARTDIV + 1).
+ * |[23:16] |EADCDIV |EADC Clock Divide Number From EADC Clock Source
+ * | | |EADC clock frequency = (EADC clock source frequency) / (EADCDIV + 1).
+ * @var CLK_T::CLKDIV1
+ * Offset: 0x24 Clock Divider Number Register 1
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:0] |SC0DIV |SC0 Clock Divide Number From SC0 Clock Source
+ * | | |SC0 clock frequency = (SC0 clock source frequency ) / (SC0DIV + 1).
+ * @var CLK_T::PLLCTL
+ * Offset: 0x40 PLL Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[8:0] |FBDIV |PLL Feedback Divider Control Pins (Write Protect)
+ * | | |Refer to the formulas below the table.
+ * |[13:9] |INDIV |PLL Input Divider Control Pins (Write Protect)
+ * | | |Refer to the formulas below the table.
+ * |[15:14] |OUTDIV |PLL Output Divider Control Pins (Write Protect)
+ * | | |Refer to the formulas below the table.
+ * |[16] |PD |Power-Down Mode (Write Protect)
+ * | | |If set the PDEN bit to 1 in CLK_PWRCTL register, the PLL will enter Power-down mode, too.
+ * | | |0 = PLL is in normal mode.
+ * | | |1 = PLL is in Power-down mode (default).
+ * |[17] |BP |PLL Bypass Control (Write Protect)
+ * | | |0 = PLL is in normal mode (default).
+ * | | |1 = PLL clock output is same as PLL input clock FIN.
+ * |[18] |OE |PLL OE (FOUT Enable) Pin Control (Write Protect)
+ * | | |0 = PLL FOUT Enabled.
+ * | | |1 = PLL FOUT is fixed low.
+ * |[19] |PLLSRC |PLL Source Clock Selection (Write Protect)
+ * | | |0 = PLL source clock from external 4~24 MHz high-speed crystal (HXT).
+ * | | |1 = PLL source clock from internal 22.1184 MHz high-speed oscillator (HIRC).
+ * |[23] |STBSEL |PLL Stable Counter Selection (Write Protect)
+ * | | |0 = PLL stable time is 6144 PLL source clock (suitable for source clock is equal to or less than 12MHz).
+ * | | |1 = PLL stable time is 12288 PLL source clock (suitable for source clock is larger than 12MHz).
+ * @var CLK_T::STATUS
+ * Offset: 0x50 Clock Status Monitor Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |HXTSTB |External 4~24 MHz High-Speed Crystal Clock Source Stable Flag (Read Only)
+ * | | |0 = External 4~24 MHz high-speed crystal clock is not stable or disabled.
+ * | | |1 = External 4~24 MHz high-speed crystal clock is stable and enabled.
+ * |[1] |LXTSTB |External 32.768 kHz Low-Speed Crystal Clock Source Stable Flag (Read Only)
+ * | | |0 = External 32.768 kHz low-speed crystal clock is not stable or disabled.
+ * | | |1 = External 32.768 kHz low-speed crystal clock is stabled and enabled.
+ * |[2] |PLLSTB |Internal PLL Clock Source Stable Flag (Read Only)
+ * | | |0 = Internal PLL clock is not stable or disabled.
+ * | | |1 = Internal PLL clock is stable and enabled.
+ * |[3] |LIRCSTB |Internal 10 KHz Low-Speed Oscillator Clock Source Stable Flag (Read Only)
+ * | | |0 = Internal 10 kHz low-speed oscillator clock is not stable or disabled.
+ * | | |1 = Internal 10 kHz low-speed oscillator clock is stable and enabled.
+ * |[4] |HIRCSTB |Internal 22.1184 MHz High-Speed Oscillator Clock Source Stable Flag (Read Only)
+ * | | |0 = Internal 22.1184 MHz high-speed oscillator clock is not stable or disabled.
+ * | | |1 = Internal 22.1184 MHz high-speed oscillator clock is stable and enabled.
+ * |[7] |CLKSFAIL |Clock Switching Fail Flag (Read Only)
+ * | | |This bit is updated when software switches system clock source.
+ * | | |If switch target clock is stable, this bit will be set to 0.
+ * | | |If switch target clock is not stable, this bit will be set to 1.
+ * | | |0 = Clock switching success.
+ * | | |1 = Clock switching failure.
+ * | | |Note: Write 1 to clear the bit to 0.
+ * @var CLK_T::CLKOCTL
+ * Offset: 0x60 Clock Output Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[3:0] |FREQSEL |Clock Output Frequency Selection
+ * | | |The formula of output frequency is
+ * | | |Fout = Fin/2(N+1).
+ * | | |Fin is the input clock frequency.
+ * | | |Fout is the frequency of divider output clock.
+ * | | |N is the 4-bit value of FREQSEL[3:0].
+ * |[4] |CLKOEN |Clock Output Enable Bit
+ * | | |0 =Clock Output function Disabled.
+ * | | |1 = Clock Output function Enabled.
+ * |[5] |DIV1EN |Clock Output Divide One Enable Bit
+ * | | |0 = Clock Output will output clock with source frequency divided by FREQSEL.
+ * | | |1 = Clock Output will output clock with source frequency.
+ * |[6] |CLK1HZEN |Clock Output 1Hz Enable Bit
+ * | | |0 = 1 Hz clock output for 32.768kHz frequency compensation Disabled.
+ * | | |1 = 1 Hz clock output for 332.768kHz frequency compensation Enabled.
+ * @var CLK_T::CLKDCTL
+ * Offset: 0x70 Clock Fail Detector Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[4] |HXTFDEN |HXT Clock Fail Detector Enable Bit
+ * | | |0 = HXT clock Fail detector Disabled.
+ * | | |1 = HXT clock Fail detector Enabled.
+ * |[5] |HXTFIEN |HXT Clock Fail Interrupt Enable Bit
+ * | | |0 = HXT clock Fail interrupt Disabled.
+ * | | |1 = HXT clock Fail interrupt Enabled.
+ * |[12] |LXTFDEN |LXT Clock Fail Detector Enable Bit
+ * | | |0 = LXT clock Fail detector Disabled.
+ * | | |1 = LXT clock Fail detector Enabled.
+ * |[13] |LXTFIEN |LXT Clock Fail Interrupt Enable Bit
+ * | | |0 = LXT clock Fail interrupt Disabled.
+ * | | |1 = LXT clock Fail interrupt Enabled.
+ * |[16] |HXTFQDEN |HXT Clock Frequency Monitor Enable Bit
+ * | | |0 = HXT clock frequency monitor Disabled.
+ * | | |1 = HXT clock frequency monitor Enabled.
+ * |[17] |HXTFQIEN |HXT Clock Frequency Monitor Interrupt Enable Bit
+ * | | |0 = HXT clock frequency monitor fail interrupt Disabled.
+ * | | |1 = HXT clock frequency monitor fail interrupt Enabled.
+ * @var CLK_T::CLKDSTS
+ * Offset: 0x74 Clock Fail Detector Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |HXTFIF |HXT Clock Fail Interrupt Flag
+ * | | |0 = HXT clock normal.
+ * | | |1 = HXT clock stop
+ * | | |Note: Write 1 to clear the bit to 0.
+ * |[1] |LXTFIF |LXT Clock Fail Interrupt Flag
+ * | | |0 = LXT clock normal.
+ * | | |1 = LXT stop
+ * | | |Note: Write 1 to clear the bit to 0.
+ * |[8] |HXTFQIF |HXT Clock Frequency Monitor Interrupt Flag
+ * | | |0 = HXT clock normal.
+ * | | |1 = HXT clock frequency abnormal
+ * | | |Note: Write 1 to clear the bit to 0.
+ * @var CLK_T::CDUPB
+ * Offset: 0x78 Clock Frequency Detector Upper Boundary Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[9:0] |UPERBD |HXT Clock Frequency Detector Upper Boundary
+ * | | |The bits define the high value of frequency monitor window.
+ * | | |When HXT frequency monitor value higher than this register, the HXT frequency detect fail interrupt flag will set to 1.
+ * @var CLK_T::CDLOWB
+ * Offset: 0x7C Clock Frequency Detector Low Boundary Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[9:0] |LOWERBD |HXT Clock Frequency Detector Low Boundary
+ * | | |The bits define the low value of frequency monitor window.
+ * | | |When HXT frequency monitor value lower than this register, the HXT frequency detect fail interrupt flag will set to 1.
+ */
+
+ __IO uint32_t PWRCTL; /* Offset: 0x00 System Power-down Control Register */
+ __IO uint32_t AHBCLK; /* Offset: 0x04 AHB Devices Clock Enable Control Register */
+ __IO uint32_t APBCLK0; /* Offset: 0x08 APB Devices Clock Enable Control Register 0 */
+ __IO uint32_t APBCLK1; /* Offset: 0x0C APB Devices Clock Enable Control Register 1 */
+ __IO uint32_t CLKSEL0; /* Offset: 0x10 Clock Source Select Control Register 0 */
+ __IO uint32_t CLKSEL1; /* Offset: 0x14 Clock Source Select Control Register 1 */
+ __IO uint32_t CLKSEL2; /* Offset: 0x18 Clock Source Select Control Register 2 */
+ __IO uint32_t CLKSEL3; /* Offset: 0x1C Clock Source Select Control Register 3 */
+ __IO uint32_t CLKDIV0; /* Offset: 0x20 Clock Divider Number Register 0 */
+ __IO uint32_t CLKDIV1; /* Offset: 0x24 Clock Divider Number Register 1 */
+ __I uint32_t RESERVE0[6];
+ __IO uint32_t PLLCTL; /* Offset: 0x40 PLL Control Register */
+ __I uint32_t RESERVE1[3];
+ __I uint32_t STATUS; /* Offset: 0x50 Clock Status Monitor Register */
+ __I uint32_t RESERVE2[3];
+ __IO uint32_t CLKOCTL; /* Offset: 0x60 Clock Output Control Register */
+ __I uint32_t RESERVE3[3];
+ __IO uint32_t CLKDCTL; /* Offset: 0x70 Clock Fail Detector Control Register */
+ __IO uint32_t CLKDSTS; /* Offset: 0x74 Clock Fail Detector Status Register */
+ __IO uint32_t CDUPB; /* Offset: 0x78 Clock Frequency Detector Upper Boundary Register */
+ __IO uint32_t CDLOWB; /* Offset: 0x7C Clock Frequency Detector Low Boundary Register */
+
+} CLK_T;
+
+
+
+/**
+ @addtogroup CLK_CONST CLK Bit Field Definition
+ Constant Definitions for CLK Controller
+@{ */
+
+#define CLK_PWRCTL_HXTEN_Pos (0) /*!< CLK_T::PWRCTL: HXTEN Position */
+#define CLK_PWRCTL_HXTEN_Msk (0x1ul << CLK_PWRCTL_HXTEN_Pos) /*!< CLK_T::PWRCTL: HXTEN Mask */
+
+#define CLK_PWRCTL_LXTEN_Pos (1) /*!< CLK_T::PWRCTL: LXTEN Position */
+#define CLK_PWRCTL_LXTEN_Msk (0x1ul << CLK_PWRCTL_LXTEN_Pos) /*!< CLK_T::PWRCTL: LXTEN Mask */
+
+#define CLK_PWRCTL_HIRCEN_Pos (2) /*!< CLK_T::PWRCTL: HIRCEN Position */
+#define CLK_PWRCTL_HIRCEN_Msk (0x1ul << CLK_PWRCTL_HIRCEN_Pos) /*!< CLK_T::PWRCTL: HIRCEN Mask */
+
+#define CLK_PWRCTL_LIRCEN_Pos (3) /*!< CLK_T::PWRCTL: LIRCEN Position */
+#define CLK_PWRCTL_LIRCEN_Msk (0x1ul << CLK_PWRCTL_LIRCEN_Pos) /*!< CLK_T::PWRCTL: LIRCEN Mask */
+
+#define CLK_PWRCTL_PDWKDLY_Pos (4) /*!< CLK_T::PWRCTL: PDWKDLY Position */
+#define CLK_PWRCTL_PDWKDLY_Msk (0x1ul << CLK_PWRCTL_PDWKDLY_Pos) /*!< CLK_T::PWRCTL: PDWKDLY Mask */
+
+#define CLK_PWRCTL_PDWKIEN_Pos (5) /*!< CLK_T::PWRCTL: PDWKIEN Position */
+#define CLK_PWRCTL_PDWKIEN_Msk (0x1ul << CLK_PWRCTL_PDWKIEN_Pos) /*!< CLK_T::PWRCTL: PDWKIEN Mask */
+
+#define CLK_PWRCTL_PDWKIF_Pos (6) /*!< CLK_T::PWRCTL: PDWKIF Position */
+#define CLK_PWRCTL_PDWKIF_Msk (0x1ul << CLK_PWRCTL_PDWKIF_Pos) /*!< CLK_T::PWRCTL: PDWKIF Mask */
+
+#define CLK_PWRCTL_PDEN_Pos (7) /*!< CLK_T::PWRCTL: PDEN Position */
+#define CLK_PWRCTL_PDEN_Msk (0x1ul << CLK_PWRCTL_PDEN_Pos) /*!< CLK_T::PWRCTL: PDEN Mask */
+
+#define CLK_PWRCTL_PDWTCPU_Pos (8) /*!< CLK_T::PWRCTL: PDWTCPU Position */
+#define CLK_PWRCTL_PDWTCPU_Msk (0x1ul << CLK_PWRCTL_PDWTCPU_Pos) /*!< CLK_T::PWRCTL: PDWTCPU Mask */
+
+#define CLK_PWRCTL_HXTGAIN_Pos (10) /*!< CLK_T::PWRCTL: HXTGAIN Position */
+#define CLK_PWRCTL_HXTGAIN_Msk (0x3ul << CLK_PWRCTL_HXTGAIN_Pos) /*!< CLK_T::PWRCTL: HXTGAIN Mask */
+
+#define CLK_PWRCTL_HXTSELTYP_Pos (12) /*!< CLK_T::PWRCTL: HXTSELTYP Position */
+#define CLK_PWRCTL_HXTSELTYP_Msk (0x1ul << CLK_PWRCTL_HXTSELTYP_Pos) /*!< CLK_T::PWRCTL: HXTSELTYP Mask */
+
+#define CLK_AHBCLK_PDMACKEN_Pos (1) /*!< CLK_T::AHBCLK: PDMACKEN Position */
+#define CLK_AHBCLK_PDMACKEN_Msk (0x1ul << CLK_AHBCLK_PDMACKEN_Pos) /*!< CLK_T::AHBCLK: PDMACKEN Mask */
+
+#define CLK_AHBCLK_ISPCKEN_Pos (2) /*!< CLK_T::AHBCLK: ISPCKEN Position */
+#define CLK_AHBCLK_ISPCKEN_Msk (0x1ul << CLK_AHBCLK_ISPCKEN_Pos) /*!< CLK_T::AHBCLK: ISPCKEN Mask */
+
+#define CLK_AHBCLK_EBICKEN_Pos (3) /*!< CLK_T::AHBCLK: EBICKEN Position */
+#define CLK_AHBCLK_EBICKEN_Msk (0x1ul << CLK_AHBCLK_EBICKEN_Pos) /*!< CLK_T::AHBCLK: EBICKEN Mask */
+
+#define CLK_AHBCLK_USBHCKEN_Pos (4) /*!< CLK_T::AHBCLK: USBHCKEN Position */
+#define CLK_AHBCLK_USBHCKEN_Msk (0x1ul << CLK_AHBCLK_USBHCKEN_Pos) /*!< CLK_T::AHBCLK: USBHCKEN Mask */
+
+#define CLK_AHBCLK_CRCCKEN_Pos (7) /*!< CLK_T::AHBCLK: CRCCKEN Position */
+#define CLK_AHBCLK_CRCCKEN_Msk (0x1ul << CLK_AHBCLK_CRCCKEN_Pos) /*!< CLK_T::AHBCLK: CRCCKEN Mask */
+
+#define CLK_AHBCLK_FMCIDLE_Pos (15) /*!< CLK_T::AHBCLK: FMCIDLE Position */
+#define CLK_AHBCLK_FMCIDLE_Msk (0x1ul << CLK_AHBCLK_FMCIDLE_Pos) /*!< CLK_T::AHBCLK: FMCIDLE Mask */
+
+#define CLK_APBCLK0_WDTCKEN_Pos (0) /*!< CLK_T::APBCLK0: WDTCKEN Position */
+#define CLK_APBCLK0_WDTCKEN_Msk (0x1ul << CLK_APBCLK0_WDTCKEN_Pos) /*!< CLK_T::APBCLK0: WDTCKEN Mask */
+
+#define CLK_APBCLK0_RTCCKEN_Pos (1) /*!< CLK_T::APBCLK0: RTCCKEN Position */
+#define CLK_APBCLK0_RTCCKEN_Msk (0x1ul << CLK_APBCLK0_RTCCKEN_Pos) /*!< CLK_T::APBCLK0: RTCCKEN Mask */
+
+#define CLK_APBCLK0_TMR0CKEN_Pos (2) /*!< CLK_T::APBCLK0: TMR0CKEN Position */
+#define CLK_APBCLK0_TMR0CKEN_Msk (0x1ul << CLK_APBCLK0_TMR0CKEN_Pos) /*!< CLK_T::APBCLK0: TMR0CKEN Mask */
+
+#define CLK_APBCLK0_TMR1CKEN_Pos (3) /*!< CLK_T::APBCLK0: TMR1CKEN Position */
+#define CLK_APBCLK0_TMR1CKEN_Msk (0x1ul << CLK_APBCLK0_TMR1CKEN_Pos) /*!< CLK_T::APBCLK0: TMR1CKEN Mask */
+
+#define CLK_APBCLK0_TMR2CKEN_Pos (4) /*!< CLK_T::APBCLK0: TMR2CKEN Position */
+#define CLK_APBCLK0_TMR2CKEN_Msk (0x1ul << CLK_APBCLK0_TMR2CKEN_Pos) /*!< CLK_T::APBCLK0: TMR2CKEN Mask */
+
+#define CLK_APBCLK0_TMR3CKEN_Pos (5) /*!< CLK_T::APBCLK0: TMR3CKEN Position */
+#define CLK_APBCLK0_TMR3CKEN_Msk (0x1ul << CLK_APBCLK0_TMR3CKEN_Pos) /*!< CLK_T::APBCLK0: TMR3CKEN Mask */
+
+#define CLK_APBCLK0_CLKOCKEN_Pos (6) /*!< CLK_T::APBCLK0: CLKOCKEN Position */
+#define CLK_APBCLK0_CLKOCKEN_Msk (0x1ul << CLK_APBCLK0_CLKOCKEN_Pos) /*!< CLK_T::APBCLK0: CLKOCKEN Mask */
+
+#define CLK_APBCLK0_ACMP01CKEN_Pos (7) /*!< CLK_T::APBCLK0: ACMP01CKEN Position */
+#define CLK_APBCLK0_ACMP01CKEN_Msk (0x1ul << CLK_APBCLK0_ACMP01CKEN_Pos) /*!< CLK_T::APBCLK0: ACMP01CKEN Mask */
+
+#define CLK_APBCLK0_I2C0CKEN_Pos (8) /*!< CLK_T::APBCLK0: I2C0CKEN Position */
+#define CLK_APBCLK0_I2C0CKEN_Msk (0x1ul << CLK_APBCLK0_I2C0CKEN_Pos) /*!< CLK_T::APBCLK0: I2C0CKEN Mask */
+
+#define CLK_APBCLK0_I2C1CKEN_Pos (9) /*!< CLK_T::APBCLK0: I2C1CKEN Position */
+#define CLK_APBCLK0_I2C1CKEN_Msk (0x1ul << CLK_APBCLK0_I2C1CKEN_Pos) /*!< CLK_T::APBCLK0: I2C1CKEN Mask */
+
+#define CLK_APBCLK0_SPI0CKEN_Pos (12) /*!< CLK_T::APBCLK0: SPI0CKEN Position */
+#define CLK_APBCLK0_SPI0CKEN_Msk (0x1ul << CLK_APBCLK0_SPI0CKEN_Pos) /*!< CLK_T::APBCLK0: SPI0CKEN Mask */
+
+#define CLK_APBCLK0_SPI1CKEN_Pos (13) /*!< CLK_T::APBCLK0: SPI1CKEN Position */
+#define CLK_APBCLK0_SPI1CKEN_Msk (0x1ul << CLK_APBCLK0_SPI1CKEN_Pos) /*!< CLK_T::APBCLK0: SPI1CKEN Mask */
+
+#define CLK_APBCLK0_SPI2CKEN_Pos (14) /*!< CLK_T::APBCLK0: SPI2CKEN Position */
+#define CLK_APBCLK0_SPI2CKEN_Msk (0x1ul << CLK_APBCLK0_SPI2CKEN_Pos) /*!< CLK_T::APBCLK0: SPI2CKEN Mask */
+
+#define CLK_APBCLK0_UART0CKEN_Pos (16) /*!< CLK_T::APBCLK0: UART0CKEN Position */
+#define CLK_APBCLK0_UART0CKEN_Msk (0x1ul << CLK_APBCLK0_UART0CKEN_Pos) /*!< CLK_T::APBCLK0: UART0CKEN Mask */
+
+#define CLK_APBCLK0_UART1CKEN_Pos (17) /*!< CLK_T::APBCLK0: UART1CKEN Position */
+#define CLK_APBCLK0_UART1CKEN_Msk (0x1ul << CLK_APBCLK0_UART1CKEN_Pos) /*!< CLK_T::APBCLK0: UART1CKEN Mask */
+
+#define CLK_APBCLK0_UART2CKEN_Pos (18) /*!< CLK_T::APBCLK0: UART2CKEN Position */
+#define CLK_APBCLK0_UART2CKEN_Msk (0x1ul << CLK_APBCLK0_UART2CKEN_Pos) /*!< CLK_T::APBCLK0: UART2CKEN Mask */
+
+#define CLK_APBCLK0_UART3CKEN_Pos (19) /*!< CLK_T::APBCLK0: UART3CKEN Position */
+#define CLK_APBCLK0_UART3CKEN_Msk (0x1ul << CLK_APBCLK0_UART3CKEN_Pos) /*!< CLK_T::APBCLK0: UART3CKEN Mask */
+
+#define CLK_APBCLK0_CAN0CKEN_Pos (24) /*!< CLK_T::APBCLK0: CAN0CKEN Position */
+#define CLK_APBCLK0_CAN0CKEN_Msk (0x1ul << CLK_APBCLK0_CAN0CKEN_Pos) /*!< CLK_T::APBCLK0: CAN0CKEN Mask */
+
+#define CLK_APBCLK0_OTGCKEN_Pos (26) /*!< CLK_T::APBCLK0: OTGCKEN Position */
+#define CLK_APBCLK0_OTGCKEN_Msk (0x1ul << CLK_APBCLK0_OTGCKEN_Pos) /*!< CLK_T::APBCLK0: OTGCKEN Mask */
+
+#define CLK_APBCLK0_USBDCKEN_Pos (27) /*!< CLK_T::APBCLK0: USBDCKEN Position */
+#define CLK_APBCLK0_USBDCKEN_Msk (0x1ul << CLK_APBCLK0_USBDCKEN_Pos) /*!< CLK_T::APBCLK0: USBDCKEN Mask */
+
+#define CLK_APBCLK0_EADCCKEN_Pos (28) /*!< CLK_T::APBCLK0: EADCCKEN Position */
+#define CLK_APBCLK0_EADCCKEN_Msk (0x1ul << CLK_APBCLK0_EADCCKEN_Pos) /*!< CLK_T::APBCLK0: EADCCKEN Mask */
+
+#define CLK_APBCLK1_SC0CKEN_Pos (0) /*!< CLK_T::APBCLK1: SC0CKEN Position */
+#define CLK_APBCLK1_SC0CKEN_Msk (0x1ul << CLK_APBCLK1_SC0CKEN_Pos) /*!< CLK_T::APBCLK1: SC0CKEN Mask */
+
+#define CLK_APBCLK1_DACCKEN_Pos (12) /*!< CLK_T::APBCLK1: DACCKEN Position */
+#define CLK_APBCLK1_DACCKEN_Msk (0x1ul << CLK_APBCLK1_DACCKEN_Pos) /*!< CLK_T::APBCLK1: DACCKEN Mask */
+
+#define CLK_APBCLK1_PWM0CKEN_Pos (16) /*!< CLK_T::APBCLK1: PWM0CKEN Position */
+#define CLK_APBCLK1_PWM0CKEN_Msk (0x1ul << CLK_APBCLK1_PWM0CKEN_Pos) /*!< CLK_T::APBCLK1: PWM0CKEN Mask */
+
+#define CLK_APBCLK1_PWM1CKEN_Pos (17) /*!< CLK_T::APBCLK1: PWM1CKEN Position */
+#define CLK_APBCLK1_PWM1CKEN_Msk (0x1ul << CLK_APBCLK1_PWM1CKEN_Pos) /*!< CLK_T::APBCLK1: PWM1CKEN Mask */
+
+#define CLK_APBCLK1_TKCKEN_Pos (25) /*!< CLK_T::APBCLK1: TKCKEN Position */
+#define CLK_APBCLK1_TKCKEN_Msk (0x1ul << CLK_APBCLK1_TKCKEN_Pos) /*!< CLK_T::APBCLK1: TKCKEN Mask */
+
+#define CLK_CLKSEL0_HCLKSEL_Pos (0) /*!< CLK_T::CLKSEL0: HCLKSEL Position */
+#define CLK_CLKSEL0_HCLKSEL_Msk (0x7ul << CLK_CLKSEL0_HCLKSEL_Pos) /*!< CLK_T::CLKSEL0: HCLKSEL Mask */
+
+#define CLK_CLKSEL0_STCLKSEL_Pos (3) /*!< CLK_T::CLKSEL0: STCLKSEL Position */
+#define CLK_CLKSEL0_STCLKSEL_Msk (0x7ul << CLK_CLKSEL0_STCLKSEL_Pos) /*!< CLK_T::CLKSEL0: STCLKSEL Mask */
+
+#define CLK_CLKSEL0_PCLK0SEL_Pos (6) /*!< CLK_T::CLKSEL0: PCLK0SEL Position */
+#define CLK_CLKSEL0_PCLK0SEL_Msk (0x1ul << CLK_CLKSEL0_PCLK0SEL_Pos) /*!< CLK_T::CLKSEL0: PCLK0SEL Mask */
+
+#define CLK_CLKSEL0_PCLK1SEL_Pos (7) /*!< CLK_T::CLKSEL0: PCLK1SEL Position */
+#define CLK_CLKSEL0_PCLK1SEL_Msk (0x1ul << CLK_CLKSEL0_PCLK1SEL_Pos) /*!< CLK_T::CLKSEL0: PCLK1SEL Mask */
+
+#define CLK_CLKSEL1_WDTSEL_Pos (0) /*!< CLK_T::CLKSEL1: WDTSEL Position */
+#define CLK_CLKSEL1_WDTSEL_Msk (0x3ul << CLK_CLKSEL1_WDTSEL_Pos) /*!< CLK_T::CLKSEL1: WDTSEL Mask */
+
+#define CLK_CLKSEL1_TMR0SEL_Pos (8) /*!< CLK_T::CLKSEL1: TMR0SEL Position */
+#define CLK_CLKSEL1_TMR0SEL_Msk (0x7ul << CLK_CLKSEL1_TMR0SEL_Pos) /*!< CLK_T::CLKSEL1: TMR0SEL Mask */
+
+#define CLK_CLKSEL1_TMR1SEL_Pos (12) /*!< CLK_T::CLKSEL1: TMR1SEL Position */
+#define CLK_CLKSEL1_TMR1SEL_Msk (0x7ul << CLK_CLKSEL1_TMR1SEL_Pos) /*!< CLK_T::CLKSEL1: TMR1SEL Mask */
+
+#define CLK_CLKSEL1_TMR2SEL_Pos (16) /*!< CLK_T::CLKSEL1: TMR2SEL Position */
+#define CLK_CLKSEL1_TMR2SEL_Msk (0x7ul << CLK_CLKSEL1_TMR2SEL_Pos) /*!< CLK_T::CLKSEL1: TMR2SEL Mask */
+
+#define CLK_CLKSEL1_TMR3SEL_Pos (20) /*!< CLK_T::CLKSEL1: TMR3SEL Position */
+#define CLK_CLKSEL1_TMR3SEL_Msk (0x7ul << CLK_CLKSEL1_TMR3SEL_Pos) /*!< CLK_T::CLKSEL1: TMR3SEL Mask */
+
+#define CLK_CLKSEL1_UARTSEL_Pos (24) /*!< CLK_T::CLKSEL1: UARTSEL Position */
+#define CLK_CLKSEL1_UARTSEL_Msk (0x3ul << CLK_CLKSEL1_UARTSEL_Pos) /*!< CLK_T::CLKSEL1: UARTSEL Mask */
+
+#define CLK_CLKSEL1_CLKOSEL_Pos (28) /*!< CLK_T::CLKSEL1: CLKOSEL Position */
+#define CLK_CLKSEL1_CLKOSEL_Msk (0x3ul << CLK_CLKSEL1_CLKOSEL_Pos) /*!< CLK_T::CLKSEL1: CLKOSEL Mask */
+
+#define CLK_CLKSEL1_WWDTSEL_Pos (30) /*!< CLK_T::CLKSEL1: WWDTSEL Position */
+#define CLK_CLKSEL1_WWDTSEL_Msk (0x3ul << CLK_CLKSEL1_WWDTSEL_Pos) /*!< CLK_T::CLKSEL1: WWDTSEL Mask */
+
+#define CLK_CLKSEL2_PWM0SEL_Pos (0) /*!< CLK_T::CLKSEL2: PWM0SEL Position */
+#define CLK_CLKSEL2_PWM0SEL_Msk (0x1ul << CLK_CLKSEL2_PWM0SEL_Pos) /*!< CLK_T::CLKSEL2: PWM0SEL Mask */
+
+#define CLK_CLKSEL2_PWM1SEL_Pos (1) /*!< CLK_T::CLKSEL2: PWM1SEL Position */
+#define CLK_CLKSEL2_PWM1SEL_Msk (0x1ul << CLK_CLKSEL2_PWM1SEL_Pos) /*!< CLK_T::CLKSEL2: PWM1SEL Mask */
+
+#define CLK_CLKSEL2_SPI0SEL_Pos (2) /*!< CLK_T::CLKSEL2: SPI0SEL Position */
+#define CLK_CLKSEL2_SPI0SEL_Msk (0x3ul << CLK_CLKSEL2_SPI0SEL_Pos) /*!< CLK_T::CLKSEL2: SPI0SEL Mask */
+
+#define CLK_CLKSEL2_SPI1SEL_Pos (4) /*!< CLK_T::CLKSEL2: SPI1SEL Position */
+#define CLK_CLKSEL2_SPI1SEL_Msk (0x3ul << CLK_CLKSEL2_SPI1SEL_Pos) /*!< CLK_T::CLKSEL2: SPI1SEL Mask */
+
+#define CLK_CLKSEL2_SPI2SEL_Pos (6) /*!< CLK_T::CLKSEL2: SPI2SEL Position */
+#define CLK_CLKSEL2_SPI2SEL_Msk (0x3ul << CLK_CLKSEL2_SPI2SEL_Pos) /*!< CLK_T::CLKSEL2: SPI2SEL Mask */
+
+#define CLK_CLKSEL3_SC0SEL_Pos (0) /*!< CLK_T::CLKSEL3: SC0SEL Position */
+#define CLK_CLKSEL3_SC0SEL_Msk (0x3ul << CLK_CLKSEL3_SC0SEL_Pos) /*!< CLK_T::CLKSEL3: SC0SEL Mask */
+
+#define CLK_CLKSEL3_RTCSEL_Pos (8) /*!< CLK_T::CLKSEL3: RTCSEL Position */
+#define CLK_CLKSEL3_RTCSEL_Msk (0x1ul << CLK_CLKSEL3_RTCSEL_Pos) /*!< CLK_T::CLKSEL3: RTCSEL Mask */
+
+#define CLK_CLKDIV0_HCLKDIV_Pos (0) /*!< CLK_T::CLKDIV0: HCLKDIV Position */
+#define CLK_CLKDIV0_HCLKDIV_Msk (0xful << CLK_CLKDIV0_HCLKDIV_Pos) /*!< CLK_T::CLKDIV0: HCLKDIV Mask */
+
+#define CLK_CLKDIV0_USBDIV_Pos (4) /*!< CLK_T::CLKDIV0: USBDIV Position */
+#define CLK_CLKDIV0_USBDIV_Msk (0xful << CLK_CLKDIV0_USBDIV_Pos) /*!< CLK_T::CLKDIV0: USBDIV Mask */
+
+#define CLK_CLKDIV0_UARTDIV_Pos (8) /*!< CLK_T::CLKDIV0: UARTDIV Position */
+#define CLK_CLKDIV0_UARTDIV_Msk (0xful << CLK_CLKDIV0_UARTDIV_Pos) /*!< CLK_T::CLKDIV0: UARTDIV Mask */
+
+#define CLK_CLKDIV0_EADCDIV_Pos (16) /*!< CLK_T::CLKDIV0: EADCDIV Position */
+#define CLK_CLKDIV0_EADCDIV_Msk (0xfful << CLK_CLKDIV0_EADCDIV_Pos) /*!< CLK_T::CLKDIV0: EADCDIV Mask */
+
+#define CLK_CLKDIV1_SC0DIV_Pos (0) /*!< CLK_T::CLKDIV1: SC0DIV Position */
+#define CLK_CLKDIV1_SC0DIV_Msk (0xfful << CLK_CLKDIV1_SC0DIV_Pos) /*!< CLK_T::CLKDIV1: SC0DIV Mask */
+
+#define CLK_PLLCTL_FBDIV_Pos (0) /*!< CLK_T::PLLCTL: FBDIV Position */
+#define CLK_PLLCTL_FBDIV_Msk (0x1fful << CLK_PLLCTL_FBDIV_Pos) /*!< CLK_T::PLLCTL: FBDIV Mask */
+
+#define CLK_PLLCTL_INDIV_Pos (9) /*!< CLK_T::PLLCTL: INDIV Position */
+#define CLK_PLLCTL_INDIV_Msk (0x1ful << CLK_PLLCTL_INDIV_Pos) /*!< CLK_T::PLLCTL: INDIV Mask */
+
+#define CLK_PLLCTL_OUTDIV_Pos (14) /*!< CLK_T::PLLCTL: OUTDIV Position */
+#define CLK_PLLCTL_OUTDIV_Msk (0x3ul << CLK_PLLCTL_OUTDIV_Pos) /*!< CLK_T::PLLCTL: OUTDIV Mask */
+
+#define CLK_PLLCTL_PD_Pos (16) /*!< CLK_T::PLLCTL: PD Position */
+#define CLK_PLLCTL_PD_Msk (0x1ul << CLK_PLLCTL_PD_Pos) /*!< CLK_T::PLLCTL: PD Mask */
+
+#define CLK_PLLCTL_BP_Pos (17) /*!< CLK_T::PLLCTL: BP Position */
+#define CLK_PLLCTL_BP_Msk (0x1ul << CLK_PLLCTL_BP_Pos) /*!< CLK_T::PLLCTL: BP Mask */
+
+#define CLK_PLLCTL_OE_Pos (18) /*!< CLK_T::PLLCTL: OE Position */
+#define CLK_PLLCTL_OE_Msk (0x1ul << CLK_PLLCTL_OE_Pos) /*!< CLK_T::PLLCTL: OE Mask */
+
+#define CLK_PLLCTL_PLLSRC_Pos (19) /*!< CLK_T::PLLCTL: PLLSRC Position */
+#define CLK_PLLCTL_PLLSRC_Msk (0x1ul << CLK_PLLCTL_PLLSRC_Pos) /*!< CLK_T::PLLCTL: PLLSRC Mask */
+
+#define CLK_PLLCTL_STBSEL_Pos (23) /*!< CLK_T::PLLCTL: STBSEL Position */
+#define CLK_PLLCTL_STBSEL_Msk (0x1ul << CLK_PLLCTL_STBSEL_Pos) /*!< CLK_T::PLLCTL: STBSEL Mask */
+
+#define CLK_STATUS_HXTSTB_Pos (0) /*!< CLK_T::STATUS: HXTSTB Position */
+#define CLK_STATUS_HXTSTB_Msk (0x1ul << CLK_STATUS_HXTSTB_Pos) /*!< CLK_T::STATUS: HXTSTB Mask */
+
+#define CLK_STATUS_LXTSTB_Pos (1) /*!< CLK_T::STATUS: LXTSTB Position */
+#define CLK_STATUS_LXTSTB_Msk (0x1ul << CLK_STATUS_LXTSTB_Pos) /*!< CLK_T::STATUS: LXTSTB Mask */
+
+#define CLK_STATUS_PLLSTB_Pos (2) /*!< CLK_T::STATUS: PLLSTB Position */
+#define CLK_STATUS_PLLSTB_Msk (0x1ul << CLK_STATUS_PLLSTB_Pos) /*!< CLK_T::STATUS: PLLSTB Mask */
+
+#define CLK_STATUS_LIRCSTB_Pos (3) /*!< CLK_T::STATUS: LIRCSTB Position */
+#define CLK_STATUS_LIRCSTB_Msk (0x1ul << CLK_STATUS_LIRCSTB_Pos) /*!< CLK_T::STATUS: LIRCSTB Mask */
+
+#define CLK_STATUS_HIRCSTB_Pos (4) /*!< CLK_T::STATUS: HIRCSTB Position */
+#define CLK_STATUS_HIRCSTB_Msk (0x1ul << CLK_STATUS_HIRCSTB_Pos) /*!< CLK_T::STATUS: HIRCSTB Mask */
+
+#define CLK_STATUS_CLKSFAIL_Pos (7) /*!< CLK_T::STATUS: CLKSFAIL Position */
+#define CLK_STATUS_CLKSFAIL_Msk (0x1ul << CLK_STATUS_CLKSFAIL_Pos) /*!< CLK_T::STATUS: CLKSFAIL Mask */
+
+#define CLK_CLKOCTL_FREQSEL_Pos (0) /*!< CLK_T::CLKOCTL: FREQSEL Position */
+#define CLK_CLKOCTL_FREQSEL_Msk (0xful << CLK_CLKOCTL_FREQSEL_Pos) /*!< CLK_T::CLKOCTL: FREQSEL Mask */
+
+#define CLK_CLKOCTL_CLKOEN_Pos (4) /*!< CLK_T::CLKOCTL: CLKOEN Position */
+#define CLK_CLKOCTL_CLKOEN_Msk (0x1ul << CLK_CLKOCTL_CLKOEN_Pos) /*!< CLK_T::CLKOCTL: CLKOEN Mask */
+
+#define CLK_CLKOCTL_DIV1EN_Pos (5) /*!< CLK_T::CLKOCTL: DIV1EN Position */
+#define CLK_CLKOCTL_DIV1EN_Msk (0x1ul << CLK_CLKOCTL_DIV1EN_Pos) /*!< CLK_T::CLKOCTL: DIV1EN Mask */
+
+#define CLK_CLKOCTL_CLK1HZEN_Pos (6) /*!< CLK_T::CLKOCTL: CLK1HZEN Position */
+#define CLK_CLKOCTL_CLK1HZEN_Msk (0x1ul << CLK_CLKOCTL_CLK1HZEN_Pos) /*!< CLK_T::CLKOCTL: CLK1HZEN Mask */
+
+#define CLK_CLKDCTL_HXTFDEN_Pos (4) /*!< CLK_T::CLKDCTL: HXTFDEN Position */
+#define CLK_CLKDCTL_HXTFDEN_Msk (0x1ul << CLK_CLKDCTL_HXTFDEN_Pos) /*!< CLK_T::CLKDCTL: HXTFDEN Mask */
+
+#define CLK_CLKDCTL_HXTFIEN_Pos (5) /*!< CLK_T::CLKDCTL: HXTFIEN Position */
+#define CLK_CLKDCTL_HXTFIEN_Msk (0x1ul << CLK_CLKDCTL_HXTFIEN_Pos) /*!< CLK_T::CLKDCTL: HXTFIEN Mask */
+
+#define CLK_CLKDCTL_LXTFDEN_Pos (12) /*!< CLK_T::CLKDCTL: LXTFDEN Position */
+#define CLK_CLKDCTL_LXTFDEN_Msk (0x1ul << CLK_CLKDCTL_LXTFDEN_Pos) /*!< CLK_T::CLKDCTL: LXTFDEN Mask */
+
+#define CLK_CLKDCTL_LXTFIEN_Pos (13) /*!< CLK_T::CLKDCTL: LXTFIEN Position */
+#define CLK_CLKDCTL_LXTFIEN_Msk (0x1ul << CLK_CLKDCTL_LXTFIEN_Pos) /*!< CLK_T::CLKDCTL: LXTFIEN Mask */
+
+#define CLK_CLKDCTL_HXTFQDEN_Pos (16) /*!< CLK_T::CLKDCTL: HXTFQDEN Position */
+#define CLK_CLKDCTL_HXTFQDEN_Msk (0x1ul << CLK_CLKDCTL_HXTFQDEN_Pos) /*!< CLK_T::CLKDCTL: HXTFQDEN Mask */
+
+#define CLK_CLKDCTL_HXTFQIEN_Pos (17) /*!< CLK_T::CLKDCTL: HXTFQIEN Position */
+#define CLK_CLKDCTL_HXTFQIEN_Msk (0x1ul << CLK_CLKDCTL_HXTFQIEN_Pos) /*!< CLK_T::CLKDCTL: HXTFQIEN Mask */
+
+#define CLK_CLKDSTS_HXTFIF_Pos (0) /*!< CLK_T::CLKDSTS: HXTFIF Position */
+#define CLK_CLKDSTS_HXTFIF_Msk (0x1ul << CLK_CLKDSTS_HXTFIF_Pos) /*!< CLK_T::CLKDSTS: HXTFIF Mask */
+
+#define CLK_CLKDSTS_LXTFIF_Pos (1) /*!< CLK_T::CLKDSTS: LXTFIF Position */
+#define CLK_CLKDSTS_LXTFIF_Msk (0x1ul << CLK_CLKDSTS_LXTFIF_Pos) /*!< CLK_T::CLKDSTS: LXTFIF Mask */
+
+#define CLK_CLKDSTS_HXTFQIF_Pos (8) /*!< CLK_T::CLKDSTS: HXTFQIF Position */
+#define CLK_CLKDSTS_HXTFQIF_Msk (0x1ul << CLK_CLKDSTS_HXTFQIF_Pos) /*!< CLK_T::CLKDSTS: HXTFQIF Mask */
+
+#define CLK_CDUPB_UPERBD_Pos (0) /*!< CLK_T::CDUPB: UPERBD Position */
+#define CLK_CDUPB_UPERBD_Msk (0x3fful << CLK_CDUPB_UPERBD_Pos) /*!< CLK_T::CDUPB: UPERBD Mask */
+
+#define CLK_CDLOWB_LOWERBD_Pos (0) /*!< CLK_T::CDLOWB: LOWERBD Position */
+#define CLK_CDLOWB_LOWERBD_Msk (0x3fful << CLK_CDLOWB_LOWERBD_Pos) /*!< CLK_T::CDLOWB: LOWERBD Mask */
+
+
+/**@}*/ /* CLK_CONST */
+/**@}*/ /* end of CLK register group */
+
+
+
+/*---------------------- Cyclic Redundancy Check Controller -------------------------*/
+/**
+ @addtogroup CRC Cyclic Redundancy Check Controller(CRC)
+ Memory Mapped Structure for CRC Controller
+@{ */
+
+
+typedef struct
+{
+
+
+
+
+/**
+ * @var CRC_T::CTL
+ * Offset: 0x00 CRC Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |CRCEN |CRC Channel Enable Bit
+ * | | |0 = No effect.
+ * | | |1 = CRC operation Enabled.
+ * |[1] |CRCRST |CRC Engine Reset
+ * | | |0 = No effect.
+ * | | |1 = Reset the internal CRC state machine and internal buffer.
+ * | | |The others contents of CRC_CTL register will not be cleared.
+ * | | |Note1: This bit will be cleared automatically.
+ * | | |Note2: Setting this bit will reload the initial seed value (CRC_SEED register).
+ * |[24] |DATREV |Write Data Bit Order Reverse
+ * | | |This bit is used to enable the bit order reverse function for write data value in CRC_DAT register.
+ * | | |0 = Bit order reversed for CRC write data in Disabled.
+ * | | |1 = Bit order reversed for CRC write data in Enabled (per byte).
+ * | | |Note: If the write data is 0xAABBCCDD, the bit order reverse for CRC write data in is 0x55DD33BB.
+ * |[25] |CHKSREV |Checksum Bit Order Reverse
+ * | | |This bit is used to enable the bit order reverse function for write data value in CRC_CHECKSUM register.
+ * | | |0 = Bit order reverse for CRC checksum Disabled.
+ * | | |1 = Bit order reverse for CRC checksum Enabled.
+ * | | |Note: If the checksum result is 0xDD7B0F2E, the bit order reverse for CRC checksum is 0x74F0DEBB.
+ * |[26] |DATFMT |Write Data 1's Complement
+ * | | |This bit is used to enable the 1's complement function for write data value in CRC_DAT register.
+ * | | |0 = 1's complement for CRC writes data in Disabled.
+ * | | |1 = 1's complement for CRC writes data in Enabled.
+ * |[27] |CHKSFMT |Checksum 1's Complement
+ * | | |This bit is used to enable the 1's complement function for checksum result in CRC_CHECKSUM register.
+ * | | |0 = 1's complement for CRC checksum Disabled.
+ * | | |1 = 1's complement for CRC checksum Enabled.
+ * |[29:28] |DATLEN |CPU Write Data Length
+ * | | |This field indicates the write data length.
+ * | | |00 = Data length is 8-bit mode.
+ * | | |01 = Data length is 16-bit mode.
+ * | | |1x = Data length is 32-bit mode.
+ * | | |Note: When the write data length is 8-bit mode, the valid data in CRC_DAT register is only DATA[7:0] bits; if the write data length is 16-bit mode, the valid data in CRC_DAT register is only DATA[15:0]
+ * |[31:30] |CRCMODE |CRC Polynomial Mode
+ * | | |This field indicates the CRC operation polynomial mode.
+ * | | |00 = CRC-CCITT Polynomial mode.
+ * | | |01 = CRC-8 Polynomial mode.
+ * | | |10 = CRC-16 Polynomial mode.
+ * | | |11 = CRC-32 Polynomial mode.
+ * @var CRC_T::DAT
+ * Offset: 0x04 CRC Write Data Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |DATA |CRC Write Data Bits
+ * | | |User can write data directly by CPU mode or use PDMA function to write data to this field to perform CRC operation.
+ * | | |Note: When the write data length is 8-bit mode, the valid data in CRC_DAT register is only DATA[7:0] bits; if the write data length is 16-bit mode, the valid data in CRC_DAT register is only DATA[15:0].
+ * @var CRC_T::SEED
+ * Offset: 0x08 CRC Seed Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |SEED |CRC Seed Value
+ * | | |This field indicates the CRC seed value.
+ * @var CRC_T::CHECKSUM
+ * Offset: 0x0C CRC Checksum Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |CHECKSUM |CRC Checksum Results
+ * | | |This field indicates the CRC checksum result.
+ */
+
+ __IO uint32_t CTL; /* Offset: 0x00 CRC Control Register */
+ __IO uint32_t DAT; /* Offset: 0x04 CRC Write Data Register */
+ __IO uint32_t SEED; /* Offset: 0x08 CRC Seed Register */
+ __I uint32_t CHECKSUM; /* Offset: 0x0C CRC Checksum Register */
+
+} CRC_T;
+
+
+
+/**
+ @addtogroup CRC_CONST CRC Bit Field Definition
+ Constant Definitions for CRC Controller
+@{ */
+
+#define CRC_CTL_CRCEN_Pos (0) /*!< CRC_T::CTL: CRCEN Position */
+#define CRC_CTL_CRCEN_Msk (0x1ul << CRC_CTL_CRCEN_Pos) /*!< CRC_T::CTL: CRCEN Mask */
+
+#define CRC_CTL_CRCRST_Pos (1) /*!< CRC_T::CTL: CRCRST Position */
+#define CRC_CTL_CRCRST_Msk (0x1ul << CRC_CTL_CRCRST_Pos) /*!< CRC_T::CTL: CRCRST Mask */
+
+#define CRC_CTL_DATREV_Pos (24) /*!< CRC_T::CTL: DATREV Position */
+#define CRC_CTL_DATREV_Msk (0x1ul << CRC_CTL_DATREV_Pos) /*!< CRC_T::CTL: DATREV Mask */
+
+#define CRC_CTL_CHKSREV_Pos (25) /*!< CRC_T::CTL: CHKSREV Position */
+#define CRC_CTL_CHKSREV_Msk (0x1ul << CRC_CTL_CHKSREV_Pos) /*!< CRC_T::CTL: CHKSREV Mask */
+
+#define CRC_CTL_DATFMT_Pos (26) /*!< CRC_T::CTL: DATFMT Position */
+#define CRC_CTL_DATFMT_Msk (0x1ul << CRC_CTL_DATFMT_Pos) /*!< CRC_T::CTL: DATFMT Mask */
+
+#define CRC_CTL_CHKSFMT_Pos (27) /*!< CRC_T::CTL: CHKSFMT Position */
+#define CRC_CTL_CHKSFMT_Msk (0x1ul << CRC_CTL_CHKSFMT_Pos) /*!< CRC_T::CTL: CHKSFMT Mask */
+
+#define CRC_CTL_DATLEN_Pos (28) /*!< CRC_T::CTL: DATLEN Position */
+#define CRC_CTL_DATLEN_Msk (0x3ul << CRC_CTL_DATLEN_Pos) /*!< CRC_T::CTL: DATLEN Mask */
+
+#define CRC_CTL_CRCMODE_Pos (30) /*!< CRC_T::CTL: CRCMODE Position */
+#define CRC_CTL_CRCMODE_Msk (0x3ul << CRC_CTL_CRCMODE_Pos) /*!< CRC_T::CTL: CRCMODE Mask */
+
+#define CRC_DAT_DATA_Pos (0) /*!< CRC_T::DAT: DATA Position */
+#define CRC_DAT_DATA_Msk (0xfffffffful << CRC_DAT_DATA_Pos) /*!< CRC_T::DAT: DATA Mask */
+
+#define CRC_SEED_SEED_Pos (0) /*!< CRC_T::SEED: SEED Position */
+#define CRC_SEED_SEED_Msk (0xfffffffful << CRC_SEED_SEED_Pos) /*!< CRC_T::SEED: SEED Mask */
+
+#define CRC_CHECKSUM_CHECKSUM_Pos (0) /*!< CRC_T::CHECKSUM: CHECKSUM Position */
+#define CRC_CHECKSUM_CHECKSUM_Msk (0xfffffffful << CRC_CHECKSUM_CHECKSUM_Pos) /*!< CRC_T::CHECKSUM: CHECKSUM Mask */
+
+/**@}*/ /* CRC_CONST */
+/**@}*/ /* end of CRC register group */
+
+
+/*---------------------- Digital to Analog Converter -------------------------*/
+/**
+ @addtogroup DAC Digital to Analog Converter(DAC)
+ Memory Mapped Structure for DAC Controller
+@{ */
+
+
+typedef struct
+{
+
+
+
+/**
+ * @var DAC_T::CTL
+ * Offset: 0x00 DAC Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |DACEN |DAC Enable Bit
+ * | | |0 = DAC is Disabled.
+ * | | |1 = DAC is Enabled.
+ * |[1] |DACIEN |DAC Interrupt Enable Bit
+ * | | |0 = Interrupt is Disabled.
+ * | | |1 = Interrupt is Enabled.
+ * |[2] |DMAEN |DMA Mode Enable Bit
+ * | | |0 = DMA mode Disabled.
+ * | | |1 = DMA mode Enabled.
+ * |[3] |DMAURIEN |DMA Under-Run Interrupt Enable Bit
+ * | | |0 = DMA under run interrupt Disabled.
+ * | | |1 = DMA under run interrupt Enabled.
+ * |[4] |TRGEN |Trigger Mode Enable Bit
+ * | | |0 = DAC event trigger mode Disabled.
+ * | | |1 = DAC event trigger mode Enabled.
+ * |[7:5] |TRGSEL |Trigger Source Selection
+ * | | |000 = Software trigger.
+ * | | |001 = External pin STDAC trigger.
+ * | | |010 = Timer 0 trigger.
+ * | | |011 = Timer 1 trigger.
+ * | | |100 = Timer 2 trigger.
+ * | | |101 = Timer 3 trigger.
+ * | | |110 = PWM0 trigger.
+ * | | |111 = PWM1 trigger.
+ * |[8] |BYPASS |Bypass Buffer Mode
+ * | | |0 = Output voltage buffer Enabled.
+ * | | |1 = Output voltage buffer Disabled.
+ * |[10] |LALIGN |DAC Data Left-Aligned Enabled Control
+ * | | |0 = Right alignment.
+ * | | |1 = Left alignment.
+ * |[13:12] |ETRGSEL |External Pin Trigger Selection
+ * | | |00 = Low level trigger.
+ * | | |01 = High level trigger.
+ * | | |10 = Falling edge trigger.
+ * | | |11 = Rising edge trigger.
+ * @var DAC_T::SWTRG
+ * Offset: 0x04 DAC Software Trigger Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |SWTRG |Software Trigger
+ * | | |0 = Software trigger Disabled.
+ * | | |1 = Software trigger Enabled.
+ * | | |User writes this bit to generate one shot pulse and it is cleared to 0 by hardware automatically; Reading this bit will always get 0.
+ * @var DAC_T::DAT
+ * Offset: 0x08 DAC Data Holding Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |DAC_DAT |DAC 12-Bit Holding Data
+ * | | |These bits are written by user software which specifies 12-bit conversion data for DAC output.
+ * | | |The unused bits (DAC_DAT[3:0] in left-alignment mode and DAC_DAT[15:12] in right alignment mode) are ignored by DAC controller hardware.
+ * | | |12 bit left alignment: user has to load data into DAC_DAT[15:4] bits.
+ * | | |12 bit right alignment: user has to load data into DAC_DAT[11:0] bits.
+ * @var DAC_T::DATOUT
+ * Offset: 0x0C DAC Data Output Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[11:0] |DATOUT |DAC 12-Bit Output Data
+ * | | |These bits are current digital data for DAC output conversion.
+ * | | |It is loaded from DAC_DAT register and user cannot write it directly.
+ * @var DAC_T::STATUS
+ * Offset: 0x10 DAC Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |FINISH |DAC Conversion Complete Finish Flag
+ * | | |0 = DAC is in conversion state.
+ * | | |1 = DAC conversion finish.
+ * | | |This bit set to 1 when conversion time counter counts to SETTLET.
+ * | | |It is cleared to 0 when DAC starts a new conversion.
+ * | | |User writes 1 to clear this bit to 0.
+ * |[1] |DMAUDR |DMA Under Run Interrupt Flag
+ * | | |0 = No DMA under-run error condition occurred.
+ * | | |1 = DMA under-run error condition occurred.
+ * | | |User writes 1 to clear this bit.
+ * |[8] |BUSY |DAC Busy Flag (Read Only)
+ * | | |0 = DAC is ready for next conversion.
+ * | | |1 = DAC is busy in conversion.
+ * | | |This is read only bit.
+ * @var DAC_T::TCTL
+ * Offset: 0x14 DAC Timing Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[9:0] |SETTLET |DAC Output Settling Time
+ * | | |User software needs to write appropriate value to these bits to meet DAC conversion settling time base on PCLK (APB clock) speed.
+ * | | |For example, DAC controller clock speed is 72MHz and DAC conversion setting time is 1 us, SETTLET value must be greater than 0x48.
+ */
+
+ __IO uint32_t CTL; /* Offset: 0x00 DAC Control Register */
+ __IO uint32_t SWTRG; /* Offset: 0x04 DAC Software Trigger Control Register */
+ __IO uint32_t DAT; /* Offset: 0x08 DAC Data Holding Register */
+ __I uint32_t DATOUT; /* Offset: 0x0C DAC Data Output Register */
+ __IO uint32_t STATUS; /* Offset: 0x10 DAC Status Register */
+ __IO uint32_t TCTL; /* Offset: 0x14 DAC Timing Control Register */
+
+} DAC_T;
+
+
+
+/**
+ @addtogroup DAC_CONST DAC Bit Field Definition
+ Constant Definitions for DAC Controller
+@{ */
+
+#define DAC_CTL_DACEN_Pos (0) /*!< DAC_T::CTL: DACEN Position */
+#define DAC_CTL_DACEN_Msk (0x1ul << DAC_CTL_DACEN_Pos) /*!< DAC_T::CTL: DACEN Mask */
+
+#define DAC_CTL_DACIEN_Pos (1) /*!< DAC_T::CTL: DACIEN Position */
+#define DAC_CTL_DACIEN_Msk (0x1ul << DAC_CTL_DACIEN_Pos) /*!< DAC_T::CTL: DACIEN Mask */
+
+#define DAC_CTL_DMAEN_Pos (2) /*!< DAC_T::CTL: DMAEN Position */
+#define DAC_CTL_DMAEN_Msk (0x1ul << DAC_CTL_DMAEN_Pos) /*!< DAC_T::CTL: DMAEN Mask */
+
+#define DAC_CTL_DMAURIEN_Pos (3) /*!< DAC_T::CTL: DMAURIEN Position */
+#define DAC_CTL_DMAURIEN_Msk (0x1ul << DAC_CTL_DMAURIEN_Pos) /*!< DAC_T::CTL: DMAURIEN Mask */
+
+#define DAC_CTL_TRGEN_Pos (4) /*!< DAC_T::CTL: TRGEN Position */
+#define DAC_CTL_TRGEN_Msk (0x1ul << DAC_CTL_TRGEN_Pos) /*!< DAC_T::CTL: TRGEN Mask */
+
+#define DAC_CTL_TRGSEL_Pos (5) /*!< DAC_T::CTL: TRGSEL Position */
+#define DAC_CTL_TRGSEL_Msk (0x7ul << DAC_CTL_TRGSEL_Pos) /*!< DAC_T::CTL: TRGSEL Mask */
+
+#define DAC_CTL_BYPASS_Pos (8) /*!< DAC_T::CTL: BYPASS Position */
+#define DAC_CTL_BYPASS_Msk (0x1ul << DAC_CTL_BYPASS_Pos) /*!< DAC_T::CTL: BYPASS Mask */
+
+#define DAC_CTL_LALIGN_Pos (10) /*!< DAC_T::CTL: LALIGN Position */
+#define DAC_CTL_LALIGN_Msk (0x1ul << DAC_CTL_LALIGN_Pos) /*!< DAC_T::CTL: LALIGN Mask */
+
+#define DAC_CTL_ETRGSEL_Pos (12) /*!< DAC_T::CTL: ETRGSEL Position */
+#define DAC_CTL_ETRGSEL_Msk (0x3ul << DAC_CTL_ETRGSEL_Pos) /*!< DAC_T::CTL: ETRGSEL Mask */
+
+#define DAC_SWTRG_SWTRG_Pos (0) /*!< DAC_T::SWTRG: SWTRG Position */
+#define DAC_SWTRG_SWTRG_Msk (0x1ul << DAC_SWTRG_SWTRG_Pos) /*!< DAC_T::SWTRG: SWTRG Mask */
+
+#define DAC_DAT_DAC_DAT_Pos (0) /*!< DAC_T::DAT: DAC_DAT Position */
+#define DAC_DAT_DAC_DAT_Msk (0xfffful << DAC_DAT_DAC_DAT_Pos) /*!< DAC_T::DAT: DAC_DAT Mask */
+
+#define DAC_DATOUT_DATOUT_Pos (0) /*!< DAC_T::DATOUT: DATOUT Position */
+#define DAC_DATOUT_DATOUT_Msk (0xffful << DAC_DATOUT_DATOUT_Pos) /*!< DAC_T::DATOUT: DATOUT Mask */
+
+#define DAC_STATUS_FINISH_Pos (0) /*!< DAC_T::STATUS: FINISH Position */
+#define DAC_STATUS_FINISH_Msk (0x1ul << DAC_STATUS_FINISH_Pos) /*!< DAC_T::STATUS: FINISH Mask */
+
+#define DAC_STATUS_DMAUDR_Pos (1) /*!< DAC_T::STATUS: DMAUDR Position */
+#define DAC_STATUS_DMAUDR_Msk (0x1ul << DAC_STATUS_DMAUDR_Pos) /*!< DAC_T::STATUS: DMAUDR Mask */
+
+#define DAC_STATUS_BUSY_Pos (8) /*!< DAC_T::STATUS: BUSY Position */
+#define DAC_STATUS_BUSY_Msk (0x1ul << DAC_STATUS_BUSY_Pos) /*!< DAC_T::STATUS: BUSY Mask */
+
+#define DAC_TCTL_SETTLET_Pos (0) /*!< DAC_T::TCTL: SETTLET Position */
+#define DAC_TCTL_SETTLET_Msk (0x3fful << DAC_TCTL_SETTLET_Pos) /*!< DAC_T::TCTL: SETTLET Mask */
+
+/**@}*/ /* DAC_CONST */
+/**@}*/ /* end of DAC register group */
+
+
+/*---------------------- External Bus Interface Controller -------------------------*/
+/**
+ @addtogroup EBI External Bus Interface Controller(EBI)
+ Memory Mapped Structure for EBI Controller
+@{ */
+
+
+typedef struct
+{
+
+
+
+
+/**
+ * @var EBI_T::CTL0
+ * Offset: 0x00 External Bus Interface Bank0 Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |EN |EBI Enable Bit
+ * | | |This bit is the functional enable bit for EBI.
+ * | | |0 = EBI function Disabled.
+ * | | |1 = EBI function Enabled.
+ * |[1] |DW16 |EBI Data Width 16-Bit Select
+ * | | |This bit defines if the EBI data width is 8-bit or 16-bit.
+ * | | |0 = EBI data width is 8-bit.
+ * | | |1 = EBI data width is 16-bit.
+ * |[2] |CSPOLINV |Chip Select Pin Polar Inverse
+ * | | |This bit defines the active level of EBI chip select pin (EBI_nCS).
+ * | | |0 = Chip select pin (EBI_nCS) is active low.
+ * | | |1 = Chip select pin (EBI_nCS) is active high.
+ * |[10:8] |MCLKDIV |External Output Clock Divider
+ * | | |The frequency of EBI output clock (MCLK) is controlled by MCLKDIV as follow:
+ * | | |000 = HCLK/1.
+ * | | |001 = HCLK/2.
+ * | | |010 = HCLK/4.
+ * | | |011 = HCLK/8.
+ * | | |100 = HCLK/16.
+ * | | |101 = HCLK/32.
+ * | | |110 = Reserved.
+ * | | |111 = Reserved.
+ * |[18:16] |TALE |Extend Time Of ALE
+ * | | |The EBI_ALE high pulse period (tALE) to latch the address can be controlled by TALE.
+ * | | |tALE = (TALE+1)*EBI_MCLK.
+ * | | |Note: This field only available in EBI_CTL0 register
+ * |[24] |WBUFEN |EBI Write Buffer Enable Bit
+ * | | |0 = EBI write buffer Disabled.
+ * | | |1 = EBI write buffer Enabled.
+ * | | |Note: This bit only available in EBI_CTL0 register
+ * @var EBI_T::TCTL0
+ * Offset: 0x04 External Bus Interface Bank0 Timing Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:3] |TACC |EBI Data Access Time
+ * | | |TACC define data access time (tACC).
+ * | | |tACC = (TACC +1) * EBI_MCLK.
+ * |[10:8] |TAHD |EBI Data Access Hold Time
+ * | | |TAHD define data access hold time (tAHD).
+ * | | |tAHD = (TAHD +1) * EBI_MCLK.
+ * |[15:12] |W2X |Idle Cycle After Write
+ * | | |This field defines the number of W2X idle cycle.
+ * | | |W2X idle cycle = (W2X * EBI_MCLK).
+ * | | |When write action is finish, W2X idle cycle is inserted and EBI_nCS return to idle state.
+ * |[22] |RAHDOFF |Access Hold Time Disable Control When Read
+ * | | |0 = The Data Access Hold Time (tAHD) during EBI reading is Enabled.
+ * | | |1 = The Data Access Hold Time (tAHD) during EBI reading is Disabled.
+ * |[23] |WAHDOFF |Access Hold Time Disable Control When Write
+ * | | |0 = The Data Access Hold Time (tAHD) during EBI writing is Enabled.
+ * | | |1 = The Data Access Hold Time (tAHD) during EBI writing is Disabled.
+ * |[27:24] |R2R |Idle Cycle Between Read-To-Read
+ * | | |This field defines the number of R2R idle cycle.
+ * | | |R2R idle cycle = (R2R * EBI_MCLK).
+ * | | |When read action is finish and next action is going to read, R2R idle cycle is inserted and EBI_nCS return to idle state.
+ * @var EBI_T::CTL1
+ * Offset: 0x10 External Bus Interface Bank1 Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |EN |EBI Enable Bit
+ * | | |This bit is the functional enable bit for EBI.
+ * | | |0 = EBI function Disabled.
+ * | | |1 = EBI function Enabled.
+ * |[1] |DW16 |EBI Data Width 16-Bit Select
+ * | | |This bit defines if the EBI data width is 8-bit or 16-bit.
+ * | | |0 = EBI data width is 8-bit.
+ * | | |1 = EBI data width is 16-bit.
+ * |[2] |CSPOLINV |Chip Select Pin Polar Inverse
+ * | | |This bit defines the active level of EBI chip select pin (EBI_nCS).
+ * | | |0 = Chip select pin (EBI_nCS) is active low.
+ * | | |1 = Chip select pin (EBI_nCS) is active high.
+ * |[10:8] |MCLKDIV |External Output Clock Divider
+ * | | |The frequency of EBI output clock (MCLK) is controlled by MCLKDIV as follow:
+ * | | |000 = HCLK/1.
+ * | | |001 = HCLK/2.
+ * | | |010 = HCLK/4.
+ * | | |011 = HCLK/8.
+ * | | |100 = HCLK/16.
+ * | | |101 = HCLK/32.
+ * | | |110 = Reserved.
+ * | | |111 = Reserved.
+ * |[18:16] |TALE |Extend Time Of ALE
+ * | | |The EBI_ALE high pulse period (tALE) to latch the address can be controlled by TALE.
+ * | | |tALE = (TALE+1)*EBI_MCLK.
+ * | | |Note: This field only available in EBI_CTL0 register
+ * |[24] |WBUFEN |EBI Write Buffer Enable Bit
+ * | | |0 = EBI write buffer Disabled.
+ * | | |1 = EBI write buffer Enabled.
+ * | | |Note: This bit only available in EBI_CTL0 register
+ * @var EBI_T::TCTL1
+ * Offset: 0x14 External Bus Interface Bank1 Timing Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:3] |TACC |EBI Data Access Time
+ * | | |TACC define data access time (tACC).
+ * | | |tACC = (TACC +1) * EBI_MCLK.
+ * |[10:8] |TAHD |EBI Data Access Hold Time
+ * | | |TAHD define data access hold time (tAHD).
+ * | | |tAHD = (TAHD +1) * EBI_MCLK.
+ * |[15:12] |W2X |Idle Cycle After Write
+ * | | |This field defines the number of W2X idle cycle.
+ * | | |W2X idle cycle = (W2X * EBI_MCLK).
+ * | | |When write action is finish, W2X idle cycle is inserted and EBI_nCS return to idle state.
+ * |[22] |RAHDOFF |Access Hold Time Disable Control When Read
+ * | | |0 = The Data Access Hold Time (tAHD) during EBI reading is Enabled.
+ * | | |1 = The Data Access Hold Time (tAHD) during EBI reading is Disabled.
+ * |[23] |WAHDOFF |Access Hold Time Disable Control When Write
+ * | | |0 = The Data Access Hold Time (tAHD) during EBI writing is Enabled.
+ * | | |1 = The Data Access Hold Time (tAHD) during EBI writing is Disabled.
+ * |[27:24] |R2R |Idle Cycle Between Read-To-Read
+ * | | |This field defines the number of R2R idle cycle.
+ * | | |R2R idle cycle = (R2R * EBI_MCLK).
+ * | | |When read action is finish and next action is going to read, R2R idle cycle is inserted and EBI_nCS return to idle state.
+ */
+
+ __IO uint32_t CTL0; /* Offset: 0x00 External Bus Interface Bank0 Control Register */
+ __IO uint32_t TCTL0; /* Offset: 0x04 External Bus Interface Bank0 Timing Control Register */
+ __I uint32_t RESERVE0[2];
+ __IO uint32_t CTL1; /* Offset: 0x10 External Bus Interface Bank1 Control Register */
+ __IO uint32_t TCTL1; /* Offset: 0x14 External Bus Interface Bank1 Timing Control Register */
+
+} EBI_T;
+
+
+
+/**
+ @addtogroup EBI_CONST EBI Bit Field Definition
+ Constant Definitions for EBI Controller
+@{ */
+
+#define EBI_CTL0_EN_Pos (0) /*!< EBI_T::CTL0: EN Position */
+#define EBI_CTL0_EN_Msk (0x1ul << EBI_CTL0_EN_Pos) /*!< EBI_T::CTL0: EN Mask */
+
+#define EBI_CTL0_DW16_Pos (1) /*!< EBI_T::CTL0: DW16 Position */
+#define EBI_CTL0_DW16_Msk (0x1ul << EBI_CTL0_DW16_Pos) /*!< EBI_T::CTL0: DW16 Mask */
+
+#define EBI_CTL0_CSPOLINV_Pos (2) /*!< EBI_T::CTL0: CSPOLINV Position */
+#define EBI_CTL0_CSPOLINV_Msk (0x1ul << EBI_CTL0_CSPOLINV_Pos) /*!< EBI_T::CTL0: CSPOLINV Mask */
+
+#define EBI_CTL0_MCLKDIV_Pos (8) /*!< EBI_T::CTL0: MCLKDIV Position */
+#define EBI_CTL0_MCLKDIV_Msk (0x7ul << EBI_CTL0_MCLKDIV_Pos) /*!< EBI_T::CTL0: MCLKDIV Mask */
+
+#define EBI_CTL0_TALE_Pos (16) /*!< EBI_T::CTL0: TALE Position */
+#define EBI_CTL0_TALE_Msk (0x7ul << EBI_CTL0_TALE_Pos) /*!< EBI_T::CTL0: TALE Mask */
+
+#define EBI_CTL0_WBUFEN_Pos (24) /*!< EBI_T::CTL0: WBUFEN Position */
+#define EBI_CTL0_WBUFEN_Msk (0x1ul << EBI_CTL0_WBUFEN_Pos) /*!< EBI_T::CTL0: WBUFEN Mask */
+
+#define EBI_TCTL0_TACC_Pos (3) /*!< EBI_T::TCTL0: TACC Position */
+#define EBI_TCTL0_TACC_Msk (0x1ful << EBI_TCTL0_TACC_Pos) /*!< EBI_T::TCTL0: TACC Mask */
+
+#define EBI_TCTL0_TAHD_Pos (8) /*!< EBI_T::TCTL0: TAHD Position */
+#define EBI_TCTL0_TAHD_Msk (0x7ul << EBI_TCTL0_TAHD_Pos) /*!< EBI_T::TCTL0: TAHD Mask */
+
+#define EBI_TCTL0_W2X_Pos (12) /*!< EBI_T::TCTL0: W2X Position */
+#define EBI_TCTL0_W2X_Msk (0xful << EBI_TCTL0_W2X_Pos) /*!< EBI_T::TCTL0: W2X Mask */
+
+#define EBI_TCTL0_RAHDOFF_Pos (22) /*!< EBI_T::TCTL0: RAHDOFF Position */
+#define EBI_TCTL0_RAHDOFF_Msk (0x1ul << EBI_TCTL0_RAHDOFF_Pos) /*!< EBI_T::TCTL0: RAHDOFF Mask */
+
+#define EBI_TCTL0_WAHDOFF_Pos (23) /*!< EBI_T::TCTL0: WAHDOFF Position */
+#define EBI_TCTL0_WAHDOFF_Msk (0x1ul << EBI_TCTL0_WAHDOFF_Pos) /*!< EBI_T::TCTL0: WAHDOFF Mask */
+
+#define EBI_TCTL0_R2R_Pos (24) /*!< EBI_T::TCTL0: R2R Position */
+#define EBI_TCTL0_R2R_Msk (0xful << EBI_TCTL0_R2R_Pos) /*!< EBI_T::TCTL0: R2R Mask */
+
+#define EBI_CTL1_EN_Pos (0) /*!< EBI_T::CTL1: EN Position */
+#define EBI_CTL1_EN_Msk (0x1ul << EBI_CTL1_EN_Pos) /*!< EBI_T::CTL1: EN Mask */
+
+#define EBI_CTL1_DW16_Pos (1) /*!< EBI_T::CTL1: DW16 Position */
+#define EBI_CTL1_DW16_Msk (0x1ul << EBI_CTL1_DW16_Pos) /*!< EBI_T::CTL1: DW16 Mask */
+
+#define EBI_CTL1_CSPOLINV_Pos (2) /*!< EBI_T::CTL1: CSPOLINV Position */
+#define EBI_CTL1_CSPOLINV_Msk (0x1ul << EBI_CTL1_CSPOLINV_Pos) /*!< EBI_T::CTL1: CSPOLINV Mask */
+
+#define EBI_CTL1_MCLKDIV_Pos (8) /*!< EBI_T::CTL1: MCLKDIV Position */
+#define EBI_CTL1_MCLKDIV_Msk (0x7ul << EBI_CTL1_MCLKDIV_Pos) /*!< EBI_T::CTL1: MCLKDIV Mask */
+
+#define EBI_CTL1_TALE_Pos (16) /*!< EBI_T::CTL1: TALE Position */
+#define EBI_CTL1_TALE_Msk (0x7ul << EBI_CTL1_TALE_Pos) /*!< EBI_T::CTL1: TALE Mask */
+
+#define EBI_CTL1_WBUFEN_Pos (24) /*!< EBI_T::CTL1: WBUFEN Position */
+#define EBI_CTL1_WBUFEN_Msk (0x1ul << EBI_CTL1_WBUFEN_Pos) /*!< EBI_T::CTL1: WBUFEN Mask */
+
+#define EBI_TCTL1_TACC_Pos (3) /*!< EBI_T::TCTL1: TACC Position */
+#define EBI_TCTL1_TACC_Msk (0x1ful << EBI_TCTL1_TACC_Pos) /*!< EBI_T::TCTL1: TACC Mask */
+
+#define EBI_TCTL1_TAHD_Pos (8) /*!< EBI_T::TCTL1: TAHD Position */
+#define EBI_TCTL1_TAHD_Msk (0x7ul << EBI_TCTL1_TAHD_Pos) /*!< EBI_T::TCTL1: TAHD Mask */
+
+#define EBI_TCTL1_W2X_Pos (12) /*!< EBI_T::TCTL1: W2X Position */
+#define EBI_TCTL1_W2X_Msk (0xful << EBI_TCTL1_W2X_Pos) /*!< EBI_T::TCTL1: W2X Mask */
+
+#define EBI_TCTL1_RAHDOFF_Pos (22) /*!< EBI_T::TCTL1: RAHDOFF Position */
+#define EBI_TCTL1_RAHDOFF_Msk (0x1ul << EBI_TCTL1_RAHDOFF_Pos) /*!< EBI_T::TCTL1: RAHDOFF Mask */
+
+#define EBI_TCTL1_WAHDOFF_Pos (23) /*!< EBI_T::TCTL1: WAHDOFF Position */
+#define EBI_TCTL1_WAHDOFF_Msk (0x1ul << EBI_TCTL1_WAHDOFF_Pos) /*!< EBI_T::TCTL1: WAHDOFF Mask */
+
+#define EBI_TCTL1_R2R_Pos (24) /*!< EBI_T::TCTL1: R2R Position */
+#define EBI_TCTL1_R2R_Msk (0xful << EBI_TCTL1_R2R_Pos) /*!< EBI_T::TCTL1: R2R Mask */
+
+/**@}*/ /* EBI_CONST */
+/**@}*/ /* end of EBI register group */
+
+
+/*---------------------- Flash Memory Controller -------------------------*/
+/**
+ @addtogroup FMC Flash Memory Controller(FMC)
+ Memory Mapped Structure for FMC Controller
+@{ */
+
+
+typedef struct
+{
+
+
+
+
+/**
+ * @var FMC_T::ISPCTL
+ * Offset: 0x00 ISP Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |ISPEN |ISP Enable Bit (Write Protect)
+ * | | |ISP function enable bit. Set this bit to enable ISP function.
+ * | | |0 = ISP function Disabled.
+ * | | |1 = ISP function Enabled.
+ * |[1] |BS |Boot Select (Write Protect)
+ * | | |When MBS in CONFIG0 is 1, set/clear this bit to select next booting from LDROM/APROM, respectively.
+ * | | |This bit also functions as chip booting status flag, which can be used to check where chip booted from.
+ * | | |This bit is initiated with the inverted value of CBS[1] (CONFIG0[7]) after any reset is happened except CPU reset (CPU is 1) or system reset (SYS) is happened.
+ * | | |0 = Booting from APROM when MBS (CONFIG0[5]) is 1.
+ * | | |1 = Booting from LDROM when MBS (CONFIG0[5]) is 1.
+ * |[3] |APUEN |APROM Update Enable Bit (Write Protect)
+ * | | |0 = APROM cannot be updated when the chip runs in APROM.
+ * | | |1 = APROM can be updated when the chip runs in APROM.
+ * |[4] |CFGUEN |CONFIG Update Enable Bit (Write Protect)
+ * | | |0 = CONFIG cannot be updated.
+ * | | |1 = CONFIG can be updated.
+ * |[5] |LDUEN |LDROM Update Enable Bit (Write Protect)
+ * | | |LDROM update enable bit.
+ * | | |0 = LDROM cannot be updated.
+ * | | |1 = LDROM can be updated.
+ * |[6] |ISPFF |ISP Fail Flag (Write Protect)
+ * | | |This bit is set by hardware when a triggered ISP meets any of the following conditions:
+ * | | |This bit needs to be cleared by writing 1 to it.
+ * | | |(1) APROM writes to itself if APUEN is set to 0.
+ * | | |(2) LDROM writes to itself if LDUEN is set to 0.
+ * | | |(3) CONFIG is erased/programmed if CFGUEN is set to 0.
+ * | | |(4) SPROM is erased/programmed if SPUEN is set to 0
+ * | | |(5) SPROM is programmed at SPROM secured mode.
+ * | | |(6) Page Erase command at LOCK mode with ICE connection
+ * | | |(7) Erase or Program command at brown-out detected
+ * | | |(8) Destination address is illegal, such as over an available range.
+ * | | |(9) Invalid ISP commands
+ * |[16] |BL |Boot Loader Booting (Write Protect)
+ * | | |This bit is initiated with the inverted value of MBS (CONFIG0[5]).
+ * | | |Any reset, except CPU reset (CPU is 1) or system reset (SYS), BL will be reloaded.
+ * | | |This bit is used to check chip boot from Boot Loader or not.
+ * | | |User should keep original value of this bit when updating FMC_ISPCTL register.
+ * | | |0 = Booting from APROM or LDROM.
+ * | | |1 = Booting from Boot Loader.
+ * @var FMC_T::ISPADDR
+ * Offset: 0x04 ISP Address Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |ISPADDR |ISP Address
+ * | | |The NuMicro M451 series is equipped with embedded flash.
+ * | | |ISPADDR[1:0] must be kept 00 for ISP 32-bit operation.
+ * | | |ISPADDR[2:0] must be kept 000 for ISP 64-bit operation.
+ * | | |For Checksum Calculation command, this field is the flash starting address for checksum calculation, 2 Kbytes alignment is necessary for checksum calculation.
+ * @var FMC_T::ISPDAT
+ * Offset: 0x08 ISP Data Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |ISPDAT |ISP Data
+ * | | |Write data to this register before ISP program operation.
+ * | | |Read data from this register after ISP read operation.
+ * | | |For Run Checksum Calculation command, ISPDAT is the memory size (byte) and 2 Kbytes alignment.
+ * | | |For ISP Read Checksum command, ISPDAT is the checksum result.
+ * | | |If ISPDAT = 0x0000_0000, it means that (1) the checksum calculation is in progress, (2) the memory range for checksum calculation is incorrect, or (3) all of data are 0.
+ * @var FMC_T::ISPCMD
+ * Offset: 0x0C ISP CMD Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[6:0] |CMD |ISP CMD
+ * | | |ISP command table is shown below:
+ * | | |0x00= FLASH Read.
+ * | | |0x04= Read Unique ID.
+ * | | |0x0B= Read Company ID.
+ * | | |0x0C= Read Device ID.
+ * | | |0x0D= Read Checksum.
+ * | | |0x21= FLASH 32-bit Program.
+ * | | |0x22= FLASH Page Erase.
+ * | | |0x27= FLASH Multi-Word Program.
+ * | | |0x2D= Run Checksum Calculation.
+ * | | |0x2E= Vector Remap.
+ * | | |0x61= FLASH 64-bit Program.
+ * | | |The other commands are invalid.
+ * @var FMC_T::ISPTRG
+ * Offset: 0x10 ISP Trigger Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |ISPGO |ISP Start Trigger (Write Protect)
+ * | | |Write 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished.
+ * | | |0 = ISP operation is finished.
+ * | | |1 = ISP is progressed.
+ * @var FMC_T::DFBA
+ * Offset: 0x14 Data Flash Base Address
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |DFBA |Data Flash Base Address
+ * | | |This register indicates Data Flash start address. It is a read only register.
+ * | | |The Data Flash is shared with APROM. the content of this register is loaded from CONFIG1
+ * | | |This register is valid when DFEN (CONFIG0[0]) =0 .
+ * @var FMC_T::FTCTL
+ * Offset: 0x18 Flash Access Time Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[6:4] |FOM |Frequency Optimization Mode (Write Protect)
+ * | | |The NuMicro M451 series support adjustable flash access timing to optimize the flash access cycles in different working frequency.
+ * | | |001 = Frequency <= 12MHz.
+ * | | |010 = Frequency <= 36MHz.
+ * | | |100 = Frequency <= 60MHz.
+ * | | |Others = Frequency <= 72MHz.
+ * @var FMC_T::ISPSTS
+ * Offset: 0x40 ISP Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |ISPBUSY |ISP Busy Flag (Read Only)
+ * | | |Write 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished.
+ * | | |This bit is the mirror of ISPGO(FMC_ISPTRG[0]).
+ * | | |0 = ISP operation is finished.
+ * | | |1 = ISP is progressed.
+ * |[2:1] |CBS |Boot Selection Of CONFIG (Read Only)
+ * | | |This bit is initiated with the CBS (CONFIG0[7:6]) after any reset is happened except CPU reset (CPU is 1) or system reset (SYS) is happened.
+ * | | |The following function is valid when MBS (FMC_ISPSTS[3])= 1.
+ * | | |00 = LDROM with IAP mode.
+ * | | |01 = LDROM without IAP mode.
+ * | | |10 = APROM with IAP mode.
+ * | | |11 = APROM without IAP mode.
+ * |[3] |MBS |Boot From Boot Loader Selection Flag (Read Only)
+ * | | |This bit is initiated with the MBS (CONFIG0[5]) after any reset is happened except CPU reset (CPU is 1) or system reset (SYS) is happened
+ * | | |0 = Booting from Boot Loader.
+ * | | |1 = Booting
+ * | | |from LDROM/APROM.(see CBS bit setting)
+ * |[5] |PGFF |Flash Program With Fast Verification Flag (Read Only)
+ * | | |This bit is set if data is mismatched at ISP programming verification.
+ * | | |This bit is clear by performing ISP flash erase or ISP read CID operation.
+ * | | |0 = Flash Program is success.
+ * | | |1 = Flash Program is fail. Program data is different with data in the flash memory
+ * |[6] |ISPFF |ISP Fail Flag (Write Protect)
+ * | | |This bit is the mirror of ISPFF (FMC_ISPCTL[6]), it needs to be cleared by writing 1 to FMC_ISPCTL[6] or FMC_ISPSTS[6].
+ * | | |This bit is set by hardware when a triggered ISP meets any of the following conditions:
+ * | | |(1) APROM writes to itself if APUEN is set to 0.
+ * | | |(2) LDROM writes to itself if LDUEN is set to 0.
+ * | | |(3) CONFIG is erased/programmed if CFGUEN is set to 0.
+ * | | |(4) SPROM is erased/programmed if SPUEN is set to 0
+ * | | |(5) SPROM is programmed at SPROM secured mode.
+ * | | |(6) Page Erase command at LOCK mode with ICE connection
+ * | | |(7) Erase or Program command at brown-out detected
+ * | | |(8) Destination address is illegal, such as over an available range.
+ * | | |(9) Invalid ISP commands
+ * |[23:9] |VECMAP |Vector Page Mapping Address (Read Only)
+ * | | |All access to 0x0000_0000~0x0000_01FF is remapped to the flash memory address {VECMAP[14:0], 9'h000} ~ {VECMAP[14:0], 9'h1FF}
+ * @var FMC_T::MPDAT0
+ * Offset: 0x80 ISP Data0 Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |ISPDAT0 |ISP Data 0
+ * | | |This register is the first 32-bit data for 32-bit/64-bit/multi-word programming, and it is also the mirror of FMC_ISPDAT, both registers keep the same data
+ * @var FMC_T::MPDAT1
+ * Offset: 0x84 ISP Data1 Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |ISPDAT1 |ISP Data 1
+ * | | |This register is the second 32-bit data for 64-bit/multi-word programming.
+ * @var FMC_T::MPDAT2
+ * Offset: 0x88 ISP Data2 Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |ISPDAT2 |ISP Data 2
+ * | | |This register is the third 32-bit data for multi-word programming.
+ * @var FMC_T::MPDAT3
+ * Offset: 0x8C ISP Data3 Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |ISPDAT3 |ISP Data 3
+ * | | |This register is the fourth 32-bit data for multi-word programming.
+ * @var FMC_T::MPSTS
+ * Offset: 0xC0 ISP Multi-Program Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |MPBUSY |ISP Multi-Word Program Busy Flag (Read Only)
+ * | | |Write 1 to start ISP Multi-Word program operation and this bit will be cleared to 0 by hardware automatically when ISP Multi-Word program operation is finished.
+ * | | |This bit is the mirror of ISPGO(FMC_ISPTRG[0]).
+ * | | |0 = ISP Multi-Word program operation is finished.
+ * | | |1 = ISP Multi-Word program operation
+ * | | |is progressed.
+ * |[1] |PPGO |ISP Multi-Program Status (Read Only)
+ * | | |0 = ISP multi-word program operation is not active.
+ * | | |1 = ISP multi-word program operation is in progress.
+ * |[2] |ISPFF |ISP Fail Flag (Read Only)
+ * | | |This bit is the mirror of ISPFF (FMC_ISPCTL[6]), it needs to be cleared by writing 1 to FMC_ISPCTL[6] or FMC_ISPSTS[6].
+ * | | |This bit is set by hardware when a triggered ISP meets any of the following conditions:
+ * | | |(1) APROM writes to itself if APUEN is set to 0.
+ * | | |(2) LDROM writes to itself if LDUEN is set to 0.
+ * | | |(3) CONFIG is erased/programmed if CFGUEN is set to 0.
+ * | | |(4) SPROM is erased/programmed if SPUEN is set to 0
+ * | | |(5) SPROM is programmed at SPROM secured mode.
+ * | | |(6) Page Erase command at LOCK mode with ICE connection
+ * | | |(7) Erase or Program command at brown-out detected
+ * | | |(8) Destination address is illegal, such as over an available range.
+ * | | |(9) Invalid ISP commands
+ * |[4] |D0 |ISP DATA 0 Flag (Read Only)
+ * | | |This bit is set when FMC_MPDAT0 is written and auto-clear to 0 when the FMC_MPDAT0 data is programmed to flash complete.
+ * | | |0 = FMC_MPDAT0 register is empty, or program to flash complete.
+ * | | |1 = FMC_MPDAT0 register has been written, and not program to flash complete.
+ * |[5] |D1 |ISP DATA 1 Flag (Read Only)
+ * | | |This bit is set when FMC_MPDAT1 is written and auto-clear to 0 when the FMC_MPDAT1 data is programmed to flash complete.
+ * | | |0 = FMC_MPDAT1 register is empty, or program to flash complete.
+ * | | |1 = FMC_MPDAT1 register has been written, and not program to flash complete.
+ * |[6] |D2 |ISP DATA 2 Flag (Read Only)
+ * | | |This bit is set when FMC_MPDAT2 is written and auto-clear to 0 when the FMC_MPDAT2 data is programmed to flash complete.
+ * | | |0 = FMC_MPDAT2 register is empty, or program to flash complete.
+ * | | |1 = FMC_MPDAT2 register has been written, and not program to flash complete.
+ * |[7] |D3 |ISP DATA 3 Flag (Read Only)
+ * | | |This bit is set when FMC_MPDAT3 is written and auto-clear to 0 when the FMC_MPDAT3 data is programmed to flash complete.
+ * | | |0 = FMC_MPDAT3 register is empty, or program to flash complete.
+ * | | |1 = FMC_MPDAT3 register has been written, and not program to flash complete.
+ * @var FMC_T::MPADDR
+ * Offset: 0xC4 ISP Multi-Program Address Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |MPADDR |ISP Multi-Word Program Address
+ * | | |MPADDR is the address of ISP multi-word program operation when ISPGO flag is 1.
+ * | | |MPADDR will keep the final ISP address when ISP multi-word program is complete.
+ */
+
+ __IO uint32_t ISPCTL; /* Offset: 0x00 ISP Control Register */
+ __IO uint32_t ISPADDR; /* Offset: 0x04 ISP Address Register */
+ __IO uint32_t ISPDAT; /* Offset: 0x08 ISP Data Register */
+ __IO uint32_t ISPCMD; /* Offset: 0x0C ISP CMD Register */
+ __IO uint32_t ISPTRG; /* Offset: 0x10 ISP Trigger Control Register */
+ __I uint32_t DFBA; /* Offset: 0x14 Data Flash Base Address */
+ __IO uint32_t FTCTL; /* Offset: 0x18 Flash Access Time Control Register */
+ __I uint32_t RESERVE0[9];
+ __I uint32_t ISPSTS; /* Offset: 0x40 ISP Status Register */
+ __I uint32_t RESERVE1[15];
+ __IO uint32_t MPDAT0; /* Offset: 0x80 ISP Data0 Register */
+ __IO uint32_t MPDAT1; /* Offset: 0x84 ISP Data1 Register */
+ __IO uint32_t MPDAT2; /* Offset: 0x88 ISP Data2 Register */
+ __IO uint32_t MPDAT3; /* Offset: 0x8C ISP Data3 Register */
+ __I uint32_t RESERVE2[12];
+ __I uint32_t MPSTS; /* Offset: 0xC0 ISP Multi-Program Status Register */
+ __I uint32_t MPADDR; /* Offset: 0xC4 ISP Multi-Program Address Register */
+
+} FMC_T;
+
+
+
+
+/**
+ @addtogroup FMC_CONST FMC Bit Field Definition
+ Constant Definitions for FMC Controller
+@{ */
+
+#define FMC_ISPCTL_ISPEN_Pos (0) /*!< FMC_T::ISPCTL: ISPEN Position */
+#define FMC_ISPCTL_ISPEN_Msk (0x1ul << FMC_ISPCTL_ISPEN_Pos) /*!< FMC_T::ISPCTL: ISPEN Mask */
+
+#define FMC_ISPCTL_BS_Pos (1) /*!< FMC_T::ISPCTL: BS Position */
+#define FMC_ISPCTL_BS_Msk (0x1ul << FMC_ISPCTL_BS_Pos) /*!< FMC_T::ISPCTL: BS Mask */
+
+#define FMC_ISPCTL_APUEN_Pos (3) /*!< FMC_T::ISPCTL: APUEN Position */
+#define FMC_ISPCTL_APUEN_Msk (0x1ul << FMC_ISPCTL_APUEN_Pos) /*!< FMC_T::ISPCTL: APUEN Mask */
+
+#define FMC_ISPCTL_CFGUEN_Pos (4) /*!< FMC_T::ISPCTL: CFGUEN Position */
+#define FMC_ISPCTL_CFGUEN_Msk (0x1ul << FMC_ISPCTL_CFGUEN_Pos) /*!< FMC_T::ISPCTL: CFGUEN Mask */
+
+#define FMC_ISPCTL_LDUEN_Pos (5) /*!< FMC_T::ISPCTL: LDUEN Position */
+#define FMC_ISPCTL_LDUEN_Msk (0x1ul << FMC_ISPCTL_LDUEN_Pos) /*!< FMC_T::ISPCTL: LDUEN Mask */
+
+#define FMC_ISPCTL_ISPFF_Pos (6) /*!< FMC_T::ISPCTL: ISPFF Position */
+#define FMC_ISPCTL_ISPFF_Msk (0x1ul << FMC_ISPCTL_ISPFF_Pos) /*!< FMC_T::ISPCTL: ISPFF Mask */
+
+#define FMC_ISPCTL_BL_Pos (16) /*!< FMC_T::ISPCTL: BL Position */
+#define FMC_ISPCTL_BL_Msk (0x1ul << FMC_ISPCTL_BL_Pos) /*!< FMC_T::ISPCTL: BL Mask */
+
+#define FMC_ISPADDR_ISPADDR_Pos (0) /*!< FMC_T::ISPADDR: ISPADDR Position */
+#define FMC_ISPADDR_ISPADDR_Msk (0xfffffffful << FMC_ISPADDR_ISPADDR_Pos) /*!< FMC_T::ISPADDR: ISPADDR Mask */
+
+#define FMC_ISPDAT_ISPDAT_Pos (0) /*!< FMC_T::ISPDAT: ISPDAT Position */
+#define FMC_ISPDAT_ISPDAT_Msk (0xfffffffful << FMC_ISPDAT_ISPDAT_Pos) /*!< FMC_T::ISPDAT: ISPDAT Mask */
+
+#define FMC_ISPCMD_CMD_Pos (0) /*!< FMC_T::ISPCMD: CMD Position */
+#define FMC_ISPCMD_CMD_Msk (0x7ful << FMC_ISPCMD_CMD_Pos) /*!< FMC_T::ISPCMD: CMD Mask */
+
+#define FMC_ISPTRG_ISPGO_Pos (0) /*!< FMC_T::ISPTRG: ISPGO Position */
+#define FMC_ISPTRG_ISPGO_Msk (0x1ul << FMC_ISPTRG_ISPGO_Pos) /*!< FMC_T::ISPTRG: ISPGO Mask */
+
+#define FMC_DFBA_DFBA_Pos (0) /*!< FMC_T::DFBA: DFBA Position */
+#define FMC_DFBA_DFBA_Msk (0xfffffffful << FMC_DFBA_DFBA_Pos) /*!< FMC_T::DFBA: DFBA Mask */
+
+#define FMC_FTCTL_FOM_Pos (4) /*!< FMC_T::FTCTL: FOM Position */
+#define FMC_FTCTL_FOM_Msk (0x7ul << FMC_FTCTL_FOM_Pos) /*!< FMC_T::FTCTL: FOM Mask */
+
+#define FMC_ISPSTS_ISPBUSY_Pos (0) /*!< FMC_T::ISPSTS: ISPBUSY Position */
+#define FMC_ISPSTS_ISPBUSY_Msk (0x1ul << FMC_ISPSTS_ISPBUSY_Pos) /*!< FMC_T::ISPSTS: ISPBUSY Mask */
+
+#define FMC_ISPSTS_CBS_Pos (1) /*!< FMC_T::ISPSTS: CBS Position */
+#define FMC_ISPSTS_CBS_Msk (0x3ul << FMC_ISPSTS_CBS_Pos) /*!< FMC_T::ISPSTS: CBS Mask */
+
+#define FMC_ISPSTS_MBS_Pos (3) /*!< FMC_T::ISPSTS: MBS Position */
+#define FMC_ISPSTS_MBS_Msk (0x1ul << FMC_ISPSTS_MBS_Pos) /*!< FMC_T::ISPSTS: MBS Mask */
+
+#define FMC_ISPSTS_PGFF_Pos (5) /*!< FMC_T::ISPSTS: PGFF Position */
+#define FMC_ISPSTS_PGFF_Msk (0x1ul << FMC_ISPSTS_PGFF_Pos) /*!< FMC_T::ISPSTS: PGFF Mask */
+
+#define FMC_ISPSTS_ISPFF_Pos (6) /*!< FMC_T::ISPSTS: ISPFF Position */
+#define FMC_ISPSTS_ISPFF_Msk (0x1ul << FMC_ISPSTS_ISPFF_Pos) /*!< FMC_T::ISPSTS: ISPFF Mask */
+
+#define FMC_ISPSTS_VECMAP_Pos (9) /*!< FMC_T::ISPSTS: VECMAP Position */
+#define FMC_ISPSTS_VECMAP_Msk (0x7ffful << FMC_ISPSTS_VECMAP_Pos) /*!< FMC_T::ISPSTS: VECMAP Mask */
+
+#define FMC_MPDAT0_ISPDAT0_Pos (0) /*!< FMC_T::MPDAT0: ISPDAT0 Position */
+#define FMC_MPDAT0_ISPDAT0_Msk (0xfffffffful << FMC_MPDAT0_ISPDAT0_Pos) /*!< FMC_T::MPDAT0: ISPDAT0 Mask */
+
+#define FMC_MPDAT1_ISPDAT1_Pos (0) /*!< FMC_T::MPDAT1: ISPDAT1 Position */
+#define FMC_MPDAT1_ISPDAT1_Msk (0xfffffffful << FMC_MPDAT1_ISPDAT1_Pos) /*!< FMC_T::MPDAT1: ISPDAT1 Mask */
+
+#define FMC_MPDAT2_ISPDAT2_Pos (0) /*!< FMC_T::MPDAT2: ISPDAT2 Position */
+#define FMC_MPDAT2_ISPDAT2_Msk (0xfffffffful << FMC_MPDAT2_ISPDAT2_Pos) /*!< FMC_T::MPDAT2: ISPDAT2 Mask */
+
+#define FMC_MPDAT3_ISPDAT3_Pos (0) /*!< FMC_T::MPDAT3: ISPDAT3 Position */
+#define FMC_MPDAT3_ISPDAT3_Msk (0xfffffffful << FMC_MPDAT3_ISPDAT3_Pos) /*!< FMC_T::MPDAT3: ISPDAT3 Mask */
+
+#define FMC_MPSTS_MPBUSY_Pos (0) /*!< FMC_T::MPSTS: MPBUSY Position */
+#define FMC_MPSTS_MPBUSY_Msk (0x1ul << FMC_MPSTS_MPBUSY_Pos) /*!< FMC_T::MPSTS: MPBUSY Mask */
+
+#define FMC_MPSTS_PPGO_Pos (1) /*!< FMC_T::MPSTS: PPGO Position */
+#define FMC_MPSTS_PPGO_Msk (0x1ul << FMC_MPSTS_PPGO_Pos) /*!< FMC_T::MPSTS: PPGO Mask */
+
+#define FMC_MPSTS_ISPFF_Pos (2) /*!< FMC_T::MPSTS: ISPFF Position */
+#define FMC_MPSTS_ISPFF_Msk (0x1ul << FMC_MPSTS_ISPFF_Pos) /*!< FMC_T::MPSTS: ISPFF Mask */
+
+#define FMC_MPSTS_D0_Pos (4) /*!< FMC_T::MPSTS: D0 Position */
+#define FMC_MPSTS_D0_Msk (0x1ul << FMC_MPSTS_D0_Pos) /*!< FMC_T::MPSTS: D0 Mask */
+
+#define FMC_MPSTS_D1_Pos (5) /*!< FMC_T::MPSTS: D1 Position */
+#define FMC_MPSTS_D1_Msk (0x1ul << FMC_MPSTS_D1_Pos) /*!< FMC_T::MPSTS: D1 Mask */
+
+#define FMC_MPSTS_D2_Pos (6) /*!< FMC_T::MPSTS: D2 Position */
+#define FMC_MPSTS_D2_Msk (0x1ul << FMC_MPSTS_D2_Pos) /*!< FMC_T::MPSTS: D2 Mask */
+
+#define FMC_MPSTS_D3_Pos (7) /*!< FMC_T::MPSTS: D3 Position */
+#define FMC_MPSTS_D3_Msk (0x1ul << FMC_MPSTS_D3_Pos) /*!< FMC_T::MPSTS: D3 Mask */
+
+#define FMC_MPADDR_MPADDR_Pos (0) /*!< FMC_T::MPADDR: MPADDR Position */
+#define FMC_MPADDR_MPADDR_Msk (0xfffffffful << FMC_MPADDR_MPADDR_Pos) /*!< FMC_T::MPADDR: MPADDR Mask */
+
+/**@}*/ /* FMC_CONST */
+/**@}*/ /* end of FMC register group */
+
+
+/*---------------------- General Purpose Input/Output Controller -------------------------*/
+/**
+ @addtogroup GPIO General Purpose Input/Output Controller(GPIO)
+ Memory Mapped Structure for GPIO Controller
+@{ */
+
+
+typedef struct
+{
+
+
+
+/**
+ * @var GPIO_T::MODE
+ * Offset: 0x00/0x40/0x80/0xC0/0x100/0x140 Port A-F I/O Mode Control
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[2n+1:2n]|MODEn |Port A-F I/O Pin[n] Mode Control
+ * | | |Determine each I/O mode of Px.n pins.
+ * | | |00 = Px.n is in Input mode.
+ * | | |01 = Px.n is in Push-pull Output mode.
+ * | | |10 = Px.n is in Open-drain Output mode.
+ * | | |11 = Px.n is in Quasi-bidirectional mode.
+ * | | |Note1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).
+ * | | |If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.
+ * | | |If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be
+ * | | |input mode after chip powered on.
+ * | | |Note2:
+ * | | |n=0~15 for port A/B/C/D.
+ * | | |n=0~14 for port E.
+ * | | |n=0~7 for port F.
+ * @var GPIO_T::DINOFF
+ * Offset: 0x04/0x44/0x84/0xC4/0x104/0x144 Port A-F Digital Input Path Disable Control
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[n+16] |DINOFFn |Port A-F Pin[n] Digital Input Path Disable Control
+ * | | |Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled.
+ * | | |If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
+ * | | |0 = Px.n digital input path Enabled.
+ * | | |1 = Px.n digital input path Disabled (digital input tied to low).
+ * | | |Note:
+ * | | |n=0~15 for port A/B/C/D.
+ * | | |n=0~14 for port E.
+ * | | |n=0~7 for port F.
+ * @var GPIO_T::DOUT
+ * Offset: 0x08/0x48/0x88/0xC8/0x108/0x148 Port A-F Data Output Value
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[n] |DOUTn |Port A-F Pin[n] Output Value
+ * | | |Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
+ * | | |0 = Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
+ * | | |1 = Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode.
+ * | | |Note:
+ * | | |n=0~15 for port A/B/C/D.
+ * | | |n=0~14 for port E.
+ * | | |n=0~7 for port F.
+ * @var GPIO_T::DATMSK
+ * Offset: 0x0C/0x4C/0x8C/0xCC/0x10C/0x14C Port A-F Data Output Write Mask
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[n] |DMASKn |Port A-F Pin[n] Data Output Write Mask
+ * | | |These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit.
+ * | | |When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected.
+ * | | |If the write signal is masked, writing data to the protect bit is ignored.
+ * | | |0 = Corresponding DOUT (Px_DOUT[n]) bit can be updated.
+ * | | |1 = Corresponding DOUT (Px_DOUT[n]) bit protected.
+ * | | |Note1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.
+ * | | |Note2:
+ * | | |n=0~15 for port A/B/C/D.
+ * | | |n=0~14 for port E.
+ * | | |n=0~7 for port F.
+ * @var GPIO_T::PIN
+ * Offset: 0x10/0x50/0x90/0xD0/0x110/0x150 Port A-F Pin Value
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[n] |PINn |Port A-F Pin[n] Pin Value
+ * | | |Each bit of the register reflects the actual status of the respective Px.n pin.
+ * | | |If the bit is 1, it indicates the corresponding pin status is high; else the pin status is low.
+ * | | |Note:
+ * | | |n=0~15 for port A/B/C/D.
+ * | | |n=0~14 for port E.
+ * | | |n=0~7 for port F.
+ * @var GPIO_T::DBEN
+ * Offset: 0x14/0x54/0x94/0xD4/0x114/0x154 Port A-F De-Bounce Enable Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[n] |DBENn |Port A-F Pin[n] Input Signal De-Bounce Enable Bit
+ * | | |The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit.
+ * | | |If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt.
+ * | | |The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
+ * | | |0 = Px.n de-bounce function Disabled.
+ * | | |1 = Px.n de-bounce function Enabled.
+ * | | |The de-bounce function is valid only for edge triggered interrupt.
+ * | | |If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
+ * | | |Note:
+ * | | |n=0~15 for port A/B/C/D.
+ * | | |n=0~14 for port E.
+ * | | |n=0~7 for port F.
+ * @var GPIO_T::INTTYPE
+ * Offset: 0x18/0x58/0x98/0xD8/0x118/0x158 Port A-F Interrupt Trigger Type Control
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[n] |TYPEn |Port A-F Pin[n] Edge Or Level Detection Interrupt Trigger Type Control
+ * | | |TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger.
+ * | | |If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce.
+ * | | |If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
+ * | | |0 = Edge trigger interrupt.
+ * | | |1 = Level trigger interrupt.
+ * | | |If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]).
+ * | | |If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur.
+ * | | |The de-bounce function is valid only for edge triggered interrupt.
+ * | | |If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
+ * | | |Note:
+ * | | |n=0~15 for port A/B/C/D.
+ * | | |n=0~14 for port E.
+ * | | |n=0~7 for port F.
+ * @var GPIO_T::INTEN
+ * Offset: 0x1C/0x5C/0x9C/0xDC/0x11C/0x15C Port A-F Interrupt Enable Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[n] |FLIENn |Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit
+ * | | |The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin.
+ * | | |Set bit to 1 also enable the pin wake-up function.
+ * | | |When setting the FLIEN (Px_INTEN[n]) bit to 1 :
+ * | | |If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.
+ * | | |If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
+ * | | |0 = Px.n level low or high to low interrupt Disabled.
+ * | | |1 = Px.n level low or high to low interrupt Enabled.
+ * | | |Note:
+ * | | |n=0~15 for port A/B/C/D.
+ * | | |n=0~14 for port E.
+ * | | |n=0~7 for port F.
+ * @var GPIO_T::INTSRC
+ * Offset: 0x20/0x60/0xA0/0xE0/0x120/0x160 Port A-F Interrupt Source Flag
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[n] |INTSRCn |Port A-F Pin[n] Interrupt Source Flag
+ * | | |Write Operation :
+ * | | |0 = No action.
+ * | | |1 = Clear the corresponding pending interrupt.
+ * | | |Read Operation :
+ * | | |0 = No interrupt at Px.n.
+ * | | |1 = Px.n generates an interrupt.
+ * | | |Note:
+ * | | |n=0~15 for port A/B/C/D.
+ * | | |n=0~14 for port E.
+ * | | |n=0~7 for port F.
+ * @var GPIO_T::SMTEN
+ * Offset: 0x24/0x64/0xA4/0xE4/0x124/0x164 Port A-F Input Schmitt Trigger Enable Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[n] |SMTENn |Port A-F Pin[n] Input Schmitt Trigger Enable Bit
+ * | | |0 = Px.n input Schmitt trigger function Disabled.
+ * | | |1 = Px.n input Schmitt trigger function Enabled.
+ * | | |Note:
+ * | | |n=0~15 for port A/B/C/D.
+ * | | |n=0~14 for port E.
+ * | | |n=0~7 for port F.
+ * @var GPIO_T::SLEWCTL
+ * Offset: 0x28/0x68/0xA8/0xE8/0x128/0x168 Port A-F High Slew Rate Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[n] |HSRENn |Port A-F Pin[n] High Slew Rate Control
+ * | | |0 = Px.n output with basic slew rate.
+ * | | |1 = Px.n output with higher slew rate.
+ * | | |Note:
+ * | | |n=0~15 for port A/B/C/D.
+ * | | |n=0~14 for port E.
+ * | | |n=0~7 for port F.
+ * @var GPIO_T::DRVCTL
+ * Offset: 0x2C Port E High Drive Strength Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[n] |HDRVENn |Port E Pin[n] Driving Strength Control
+ * | | |0 = Px.n output with basic driving strength.
+ * | | |1 = Px.n output with high driving strength.
+ * | | |Note:
+ * | | |n=8,9..13 for port E.
+ */
+
+ __IO uint32_t MODE; /* Offset: 0x00/0x40/0x80/0xC0/0x100/0x140 Port A-F I/O Mode Control */
+ __IO uint32_t DINOFF; /* Offset: 0x04/0x44/0x84/0xC4/0x104/0x144 Port A-F Digital Input Path Disable Control */
+ __IO uint32_t DOUT; /* Offset: 0x08/0x48/0x88/0xC8/0x108/0x148 Port A-F Data Output Value */
+ __IO uint32_t DATMSK; /* Offset: 0x0C/0x4C/0x8C/0xCC/0x10C/0x14C Port A-F Data Output Write Mask */
+ __I uint32_t PIN; /* Offset: 0x10/0x50/0x90/0xD0/0x110/0x150 Port A-F Pin Value */
+ __IO uint32_t DBEN; /* Offset: 0x14/0x54/0x94/0xD4/0x114/0x154 Port A-F De-Bounce Enable Control Register */
+ __IO uint32_t INTTYPE; /* Offset: 0x18/0x58/0x98/0xD8/0x118/0x158 Port A-F Interrupt Trigger Type Control */
+ __IO uint32_t INTEN; /* Offset: 0x1C/0x5C/0x9C/0xDC/0x11C/0x15C Port A-F Interrupt Enable Control Register */
+ __IO uint32_t INTSRC; /* Offset: 0x20/0x60/0xA0/0xE0/0x120/0x160 Port A-F Interrupt Source Flag */
+ __IO uint32_t SMTEN; /* Offset: 0x24/0x64/0xA4/0xE4/0x124/0x164 Port A-F Input Schmitt Trigger Enable Register */
+ __IO uint32_t SLEWCTL; /* Offset: 0x28/0x68/0xA8/0xE8/0x128/0x168 Port A-F High Slew Rate Control Register */
+ __IO uint32_t DRVCTL; /* Offset: 0x12C Port E High Drive Strength Control Register */
+
+} GPIO_T;
+
+
+
+
+typedef struct
+{
+
+
+
+/**
+ * @var GPIO_DBCTL_T::DBCTL
+ * Offset: 0x440 Interrupt De-bounce Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[3:0] |DBCLKSEL |De-Bounce Sampling Cycle Selection
+ * | | |0000 = Sample interrupt input once per 1 clocks.
+ * | | |0001 = Sample interrupt input once per 2 clocks.
+ * | | |0010 = Sample interrupt input once per 4 clocks.
+ * | | |0011 = Sample interrupt input once per 8 clocks.
+ * | | |0100 = Sample interrupt input once per 16 clocks.
+ * | | |0101 = Sample interrupt input once per 32 clocks.
+ * | | |0110 = Sample interrupt input once per 64 clocks.
+ * | | |0111 = Sample interrupt input once per 128 clocks.
+ * | | |1000 = Sample interrupt input once per 256 clocks.
+ * | | |1001 = Sample interrupt input once per 2*256 clocks.
+ * | | |1010 = Sample interrupt input once per 4*256 clocks.
+ * | | |1011 = Sample interrupt input once per 8*256 clocks.
+ * | | |1100 = Sample interrupt input once per 16*256 clocks.
+ * | | |1101 = Sample interrupt input once per 32*256 clocks.
+ * | | |1110 = Sample interrupt input once per 64*256 clocks.
+ * | | |1111 = Sample interrupt input once per 128*256 clocks.
+ * |[4] |DBCLKSRC |De-Bounce Counter Clock Source Selection
+ * | | |0 = De-bounce counter clock source is the HCLK.
+ * | | |1 = De-bounce counter clock source is the internal 10 kHz internal low speed oscillator.
+ * |[5] |ICLKON |Interrupt Clock On Mode
+ * | | |0 = Edge detection circuit is active only if I/O pin corresponding RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]) bit is set to 1.
+ * | | |1 = All I/O pins edge detection circuit is always active after reset.
+ * | | |Note: It is recommended to disable this bit to save system power if no special application concern.
+ */
+
+ __IO uint32_t DBCTL; /* Offset: 0x440 Interrupt De-bounce Control Register */
+
+} GPIO_DBCTL_T;
+
+
+
+
+/**
+ @addtogroup GPIO_CONST GPIO Bit Field Definition
+ Constant Definitions for GPIO Controller
+@{ */
+
+#define GPIO_MODE_MODE0_Pos (0) /*!< GPIO_T::MODE: MODE0 Position */
+#define GPIO_MODE_MODE0_Msk (0x3ul << GPIO_MODE_MODE0_Pos) /*!< GPIO_T::MODE: MODE0 Mask */
+
+#define GPIO_MODE_MODE1_Pos (2) /*!< GPIO_T::MODE: MODE1 Position */
+#define GPIO_MODE_MODE1_Msk (0x3ul << GPIO_MODE_MODE1_Pos) /*!< GPIO_T::MODE: MODE1 Mask */
+
+#define GPIO_MODE_MODE2_Pos (4) /*!< GPIO_T::MODE: MODE2 Position */
+#define GPIO_MODE_MODE2_Msk (0x3ul << GPIO_MODE_MODE2_Pos) /*!< GPIO_T::MODE: MODE2 Mask */
+
+#define GPIO_MODE_MODE3_Pos (6) /*!< GPIO_T::MODE: MODE3 Position */
+#define GPIO_MODE_MODE3_Msk (0x3ul << GPIO_MODE_MODE3_Pos) /*!< GPIO_T::MODE: MODE3 Mask */
+
+#define GPIO_MODE_MODE4_Pos (8) /*!< GPIO_T::MODE: MODE4 Position */
+#define GPIO_MODE_MODE4_Msk (0x3ul << GPIO_MODE_MODE4_Pos) /*!< GPIO_T::MODE: MODE4 Mask */
+
+#define GPIO_MODE_MODE5_Pos (10) /*!< GPIO_T::MODE: MODE5 Position */
+#define GPIO_MODE_MODE5_Msk (0x3ul << GPIO_MODE_MODE5_Pos) /*!< GPIO_T::MODE: MODE5 Mask */
+
+#define GPIO_MODE_MODE6_Pos (12) /*!< GPIO_T::MODE: MODE6 Position */
+#define GPIO_MODE_MODE6_Msk (0x3ul << GPIO_MODE_MODE6_Pos) /*!< GPIO_T::MODE: MODE6 Mask */
+
+#define GPIO_MODE_MODE7_Pos (14) /*!< GPIO_T::MODE: MODE7 Position */
+#define GPIO_MODE_MODE7_Msk (0x3ul << GPIO_MODE_MODE7_Pos) /*!< GPIO_T::MODE: MODE7 Mask */
+
+#define GPIO_MODE_MODE8_Pos (16) /*!< GPIO_T::MODE: MODE8 Position */
+#define GPIO_MODE_MODE8_Msk (0x3ul << GPIO_MODE_MODE8_Pos) /*!< GPIO_T::MODE: MODE8 Mask */
+
+#define GPIO_MODE_MODE9_Pos (18) /*!< GPIO_T::MODE: MODE9 Position */
+#define GPIO_MODE_MODE9_Msk (0x3ul << GPIO_MODE_MODE9_Pos) /*!< GPIO_T::MODE: MODE9 Mask */
+
+#define GPIO_MODE_MODE10_Pos (20) /*!< GPIO_T::MODE: MODE10 Position */
+#define GPIO_MODE_MODE10_Msk (0x3ul << GPIO_MODE_MODE10_Pos) /*!< GPIO_T::MODE: MODE10 Mask */
+
+#define GPIO_MODE_MODE11_Pos (22) /*!< GPIO_T::MODE: MODE11 Position */
+#define GPIO_MODE_MODE11_Msk (0x3ul << GPIO_MODE_MODE11_Pos) /*!< GPIO_T::MODE: MODE11 Mask */
+
+#define GPIO_MODE_MODE12_Pos (24) /*!< GPIO_T::MODE: MODE12 Position */
+#define GPIO_MODE_MODE12_Msk (0x3ul << GPIO_MODE_MODE12_Pos) /*!< GPIO_T::MODE: MODE12 Mask */
+
+#define GPIO_MODE_MODE13_Pos (26) /*!< GPIO_T::MODE: MODE13 Position */
+#define GPIO_MODE_MODE13_Msk (0x3ul << GPIO_MODE_MODE13_Pos) /*!< GPIO_T::MODE: MODE13 Mask */
+
+#define GPIO_MODE_MODE14_Pos (28) /*!< GPIO_T::MODE: MODE14 Position */
+#define GPIO_MODE_MODE14_Msk (0x3ul << GPIO_MODE_MODE14_Pos) /*!< GPIO_T::MODE: MODE14 Mask */
+
+#define GPIO_MODE_MODE15_Pos (30) /*!< GPIO_T::MODE: MODE15 Position */
+#define GPIO_MODE_MODE15_Msk (0x3ul << GPIO_MODE_MODE15_Pos) /*!< GPIO_T::MODE: MODE15 Mask */
+
+#define GPIO_DINOFF_DINOFF0_Pos (16) /*!< GPIO_T::DINOFF: DINOFF0 Position */
+#define GPIO_DINOFF_DINOFF0_Msk (0x1ul << GPIO_DINOFF_DINOFF0_Pos) /*!< GPIO_T::DINOFF: DINOFF0 Mask */
+
+#define GPIO_DINOFF_DINOFF1_Pos (17) /*!< GPIO_T::DINOFF: DINOFF1 Position */
+#define GPIO_DINOFF_DINOFF1_Msk (0x1ul << GPIO_DINOFF_DINOFF1_Pos) /*!< GPIO_T::DINOFF: DINOFF1 Mask */
+
+#define GPIO_DINOFF_DINOFF2_Pos (18) /*!< GPIO_T::DINOFF: DINOFF2 Position */
+#define GPIO_DINOFF_DINOFF2_Msk (0x1ul << GPIO_DINOFF_DINOFF2_Pos) /*!< GPIO_T::DINOFF: DINOFF2 Mask */
+
+#define GPIO_DINOFF_DINOFF3_Pos (19) /*!< GPIO_T::DINOFF: DINOFF3 Position */
+#define GPIO_DINOFF_DINOFF3_Msk (0x1ul << GPIO_DINOFF_DINOFF3_Pos) /*!< GPIO_T::DINOFF: DINOFF3 Mask */
+
+#define GPIO_DINOFF_DINOFF4_Pos (20) /*!< GPIO_T::DINOFF: DINOFF4 Position */
+#define GPIO_DINOFF_DINOFF4_Msk (0x1ul << GPIO_DINOFF_DINOFF4_Pos) /*!< GPIO_T::DINOFF: DINOFF4 Mask */
+
+#define GPIO_DINOFF_DINOFF5_Pos (21) /*!< GPIO_T::DINOFF: DINOFF5 Position */
+#define GPIO_DINOFF_DINOFF5_Msk (0x1ul << GPIO_DINOFF_DINOFF5_Pos) /*!< GPIO_T::DINOFF: DINOFF5 Mask */
+
+#define GPIO_DINOFF_DINOFF6_Pos (22) /*!< GPIO_T::DINOFF: DINOFF6 Position */
+#define GPIO_DINOFF_DINOFF6_Msk (0x1ul << GPIO_DINOFF_DINOFF6_Pos) /*!< GPIO_T::DINOFF: DINOFF6 Mask */
+
+#define GPIO_DINOFF_DINOFF7_Pos (23) /*!< GPIO_T::DINOFF: DINOFF7 Position */
+#define GPIO_DINOFF_DINOFF7_Msk (0x1ul << GPIO_DINOFF_DINOFF7_Pos) /*!< GPIO_T::DINOFF: DINOFF7 Mask */
+
+#define GPIO_DINOFF_DINOFF8_Pos (24) /*!< GPIO_T::DINOFF: DINOFF8 Position */
+#define GPIO_DINOFF_DINOFF8_Msk (0x1ul << GPIO_DINOFF_DINOFF8_Pos) /*!< GPIO_T::DINOFF: DINOFF8 Mask */
+
+#define GPIO_DINOFF_DINOFF9_Pos (25) /*!< GPIO_T::DINOFF: DINOFF9 Position */
+#define GPIO_DINOFF_DINOFF9_Msk (0x1ul << GPIO_DINOFF_DINOFF9_Pos) /*!< GPIO_T::DINOFF: DINOFF9 Mask */
+
+#define GPIO_DINOFF_DINOFF10_Pos (26) /*!< GPIO_T::DINOFF: DINOFF10 Position */
+#define GPIO_DINOFF_DINOFF10_Msk (0x1ul << GPIO_DINOFF_DINOFF10_Pos) /*!< GPIO_T::DINOFF: DINOFF10 Mask */
+
+#define GPIO_DINOFF_DINOFF11_Pos (27) /*!< GPIO_T::DINOFF: DINOFF11 Position */
+#define GPIO_DINOFF_DINOFF11_Msk (0x1ul << GPIO_DINOFF_DINOFF11_Pos) /*!< GPIO_T::DINOFF: DINOFF11 Mask */
+
+#define GPIO_DINOFF_DINOFF12_Pos (28) /*!< GPIO_T::DINOFF: DINOFF12 Position */
+#define GPIO_DINOFF_DINOFF12_Msk (0x1ul << GPIO_DINOFF_DINOFF12_Pos) /*!< GPIO_T::DINOFF: DINOFF12 Mask */
+
+#define GPIO_DINOFF_DINOFF13_Pos (29) /*!< GPIO_T::DINOFF: DINOFF13 Position */
+#define GPIO_DINOFF_DINOFF13_Msk (0x1ul << GPIO_DINOFF_DINOFF13_Pos) /*!< GPIO_T::DINOFF: DINOFF13 Mask */
+
+#define GPIO_DINOFF_DINOFF14_Pos (30) /*!< GPIO_T::DINOFF: DINOFF14 Position */
+#define GPIO_DINOFF_DINOFF14_Msk (0x1ul << GPIO_DINOFF_DINOFF14_Pos) /*!< GPIO_T::DINOFF: DINOFF14 Mask */
+
+#define GPIO_DINOFF_DINOFF15_Pos (31) /*!< GPIO_T::DINOFF: DINOFF15 Position */
+#define GPIO_DINOFF_DINOFF15_Msk (0x1ul << GPIO_DINOFF_DINOFF15_Pos) /*!< GPIO_T::DINOFF: DINOFF15 Mask */
+
+#define GPIO_DOUT_DOUT0_Pos (0) /*!< GPIO_T::DOUT: DOUT0 Position */
+#define GPIO_DOUT_DOUT0_Msk (0x1ul << GPIO_DOUT_DOUT0_Pos) /*!< GPIO_T::DOUT: DOUT0 Mask */
+
+#define GPIO_DOUT_DOUT1_Pos (1) /*!< GPIO_T::DOUT: DOUT1 Position */
+#define GPIO_DOUT_DOUT1_Msk (0x1ul << GPIO_DOUT_DOUT1_Pos) /*!< GPIO_T::DOUT: DOUT1 Mask */
+
+#define GPIO_DOUT_DOUT2_Pos (2) /*!< GPIO_T::DOUT: DOUT2 Position */
+#define GPIO_DOUT_DOUT2_Msk (0x1ul << GPIO_DOUT_DOUT2_Pos) /*!< GPIO_T::DOUT: DOUT2 Mask */
+
+#define GPIO_DOUT_DOUT3_Pos (3) /*!< GPIO_T::DOUT: DOUT3 Position */
+#define GPIO_DOUT_DOUT3_Msk (0x1ul << GPIO_DOUT_DOUT3_Pos) /*!< GPIO_T::DOUT: DOUT3 Mask */
+
+#define GPIO_DOUT_DOUT4_Pos (4) /*!< GPIO_T::DOUT: DOUT4 Position */
+#define GPIO_DOUT_DOUT4_Msk (0x1ul << GPIO_DOUT_DOUT4_Pos) /*!< GPIO_T::DOUT: DOUT4 Mask */
+
+#define GPIO_DOUT_DOUT5_Pos (5) /*!< GPIO_T::DOUT: DOUT5 Position */
+#define GPIO_DOUT_DOUT5_Msk (0x1ul << GPIO_DOUT_DOUT5_Pos) /*!< GPIO_T::DOUT: DOUT5 Mask */
+
+#define GPIO_DOUT_DOUT6_Pos (6) /*!< GPIO_T::DOUT: DOUT6 Position */
+#define GPIO_DOUT_DOUT6_Msk (0x1ul << GPIO_DOUT_DOUT6_Pos) /*!< GPIO_T::DOUT: DOUT6 Mask */
+
+#define GPIO_DOUT_DOUT7_Pos (7) /*!< GPIO_T::DOUT: DOUT7 Position */
+#define GPIO_DOUT_DOUT7_Msk (0x1ul << GPIO_DOUT_DOUT7_Pos) /*!< GPIO_T::DOUT: DOUT7 Mask */
+
+#define GPIO_DOUT_DOUT8_Pos (8) /*!< GPIO_T::DOUT: DOUT8 Position */
+#define GPIO_DOUT_DOUT8_Msk (0x1ul << GPIO_DOUT_DOUT8_Pos) /*!< GPIO_T::DOUT: DOUT8 Mask */
+
+#define GPIO_DOUT_DOUT9_Pos (9) /*!< GPIO_T::DOUT: DOUT9 Position */
+#define GPIO_DOUT_DOUT9_Msk (0x1ul << GPIO_DOUT_DOUT9_Pos) /*!< GPIO_T::DOUT: DOUT9 Mask */
+
+#define GPIO_DOUT_DOUT10_Pos (10) /*!< GPIO_T::DOUT: DOUT10 Position */
+#define GPIO_DOUT_DOUT10_Msk (0x1ul << GPIO_DOUT_DOUT10_Pos) /*!< GPIO_T::DOUT: DOUT10 Mask */
+
+#define GPIO_DOUT_DOUT11_Pos (11) /*!< GPIO_T::DOUT: DOUT11 Position */
+#define GPIO_DOUT_DOUT11_Msk (0x1ul << GPIO_DOUT_DOUT11_Pos) /*!< GPIO_T::DOUT: DOUT11 Mask */
+
+#define GPIO_DOUT_DOUT12_Pos (12) /*!< GPIO_T::DOUT: DOUT12 Position */
+#define GPIO_DOUT_DOUT12_Msk (0x1ul << GPIO_DOUT_DOUT12_Pos) /*!< GPIO_T::DOUT: DOUT12 Mask */
+
+#define GPIO_DOUT_DOUT13_Pos (13) /*!< GPIO_T::DOUT: DOUT13 Position */
+#define GPIO_DOUT_DOUT13_Msk (0x1ul << GPIO_DOUT_DOUT13_Pos) /*!< GPIO_T::DOUT: DOUT13 Mask */
+
+#define GPIO_DOUT_DOUT14_Pos (14) /*!< GPIO_T::DOUT: DOUT14 Position */
+#define GPIO_DOUT_DOUT14_Msk (0x1ul << GPIO_DOUT_DOUT14_Pos) /*!< GPIO_T::DOUT: DOUT14 Mask */
+
+#define GPIO_DOUT_DOUT15_Pos (15) /*!< GPIO_T::DOUT: DOUT15 Position */
+#define GPIO_DOUT_DOUT15_Msk (0x1ul << GPIO_DOUT_DOUT15_Pos) /*!< GPIO_T::DOUT: DOUT15 Mask */
+
+#define GPIO_DATMSK_DMASK0_Pos (0) /*!< GPIO_T::DATMSK: DMASK0 Position */
+#define GPIO_DATMSK_DMASK0_Msk (0x1ul << GPIO_DATMSK_DMASK0_Pos) /*!< GPIO_T::DATMSK: DMASK0 Mask */
+
+#define GPIO_DATMSK_DMASK1_Pos (1) /*!< GPIO_T::DATMSK: DMASK1 Position */
+#define GPIO_DATMSK_DMASK1_Msk (0x1ul << GPIO_DATMSK_DMASK1_Pos) /*!< GPIO_T::DATMSK: DMASK1 Mask */
+
+#define GPIO_DATMSK_DMASK2_Pos (2) /*!< GPIO_T::DATMSK: DMASK2 Position */
+#define GPIO_DATMSK_DMASK2_Msk (0x1ul << GPIO_DATMSK_DMASK2_Pos) /*!< GPIO_T::DATMSK: DMASK2 Mask */
+
+#define GPIO_DATMSK_DMASK3_Pos (3) /*!< GPIO_T::DATMSK: DMASK3 Position */
+#define GPIO_DATMSK_DMASK3_Msk (0x1ul << GPIO_DATMSK_DMASK3_Pos) /*!< GPIO_T::DATMSK: DMASK3 Mask */
+
+#define GPIO_DATMSK_DMASK4_Pos (4) /*!< GPIO_T::DATMSK: DMASK4 Position */
+#define GPIO_DATMSK_DMASK4_Msk (0x1ul << GPIO_DATMSK_DMASK4_Pos) /*!< GPIO_T::DATMSK: DMASK4 Mask */
+
+#define GPIO_DATMSK_DMASK5_Pos (5) /*!< GPIO_T::DATMSK: DMASK5 Position */
+#define GPIO_DATMSK_DMASK5_Msk (0x1ul << GPIO_DATMSK_DMASK5_Pos) /*!< GPIO_T::DATMSK: DMASK5 Mask */
+
+#define GPIO_DATMSK_DMASK6_Pos (6) /*!< GPIO_T::DATMSK: DMASK6 Position */
+#define GPIO_DATMSK_DMASK6_Msk (0x1ul << GPIO_DATMSK_DMASK6_Pos) /*!< GPIO_T::DATMSK: DMASK6 Mask */
+
+#define GPIO_DATMSK_DMASK7_Pos (7) /*!< GPIO_T::DATMSK: DMASK7 Position */
+#define GPIO_DATMSK_DMASK7_Msk (0x1ul << GPIO_DATMSK_DMASK7_Pos) /*!< GPIO_T::DATMSK: DMASK7 Mask */
+
+#define GPIO_DATMSK_DMASK8_Pos (8) /*!< GPIO_T::DATMSK: DMASK8 Position */
+#define GPIO_DATMSK_DMASK8_Msk (0x1ul << GPIO_DATMSK_DMASK8_Pos) /*!< GPIO_T::DATMSK: DMASK8 Mask */
+
+#define GPIO_DATMSK_DMASK9_Pos (9) /*!< GPIO_T::DATMSK: DMASK9 Position */
+#define GPIO_DATMSK_DMASK9_Msk (0x1ul << GPIO_DATMSK_DMASK9_Pos) /*!< GPIO_T::DATMSK: DMASK9 Mask */
+
+#define GPIO_DATMSK_DMASK10_Pos (10) /*!< GPIO_T::DATMSK: DMASK10 Position */
+#define GPIO_DATMSK_DMASK10_Msk (0x1ul << GPIO_DATMSK_DMASK10_Pos) /*!< GPIO_T::DATMSK: DMASK10 Mask */
+
+#define GPIO_DATMSK_DMASK11_Pos (11) /*!< GPIO_T::DATMSK: DMASK11 Position */
+#define GPIO_DATMSK_DMASK11_Msk (0x1ul << GPIO_DATMSK_DMASK11_Pos) /*!< GPIO_T::DATMSK: DMASK11 Mask */
+
+#define GPIO_DATMSK_DMASK12_Pos (12) /*!< GPIO_T::DATMSK: DMASK12 Position */
+#define GPIO_DATMSK_DMASK12_Msk (0x1ul << GPIO_DATMSK_DMASK12_Pos) /*!< GPIO_T::DATMSK: DMASK12 Mask */
+
+#define GPIO_DATMSK_DMASK13_Pos (13) /*!< GPIO_T::DATMSK: DMASK13 Position */
+#define GPIO_DATMSK_DMASK13_Msk (0x1ul << GPIO_DATMSK_DMASK13_Pos) /*!< GPIO_T::DATMSK: DMASK13 Mask */
+
+#define GPIO_DATMSK_DMASK14_Pos (14) /*!< GPIO_T::DATMSK: DMASK14 Position */
+#define GPIO_DATMSK_DMASK14_Msk (0x1ul << GPIO_DATMSK_DMASK14_Pos) /*!< GPIO_T::DATMSK: DMASK14 Mask */
+
+#define GPIO_DATMSK_DMASK15_Pos (15) /*!< GPIO_T::DATMSK: DMASK15 Position */
+#define GPIO_DATMSK_DMASK15_Msk (0x1ul << GPIO_DATMSK_DMASK15_Pos) /*!< GPIO_T::DATMSK: DMASK15 Mask */
+
+#define GPIO_PIN_PIN0_Pos (0) /*!< GPIO_T::PIN: PIN0 Position */
+#define GPIO_PIN_PIN0_Msk (0x1ul << GPIO_PIN_PIN0_Pos) /*!< GPIO_T::PIN: PIN0 Mask */
+
+#define GPIO_PIN_PIN1_Pos (1) /*!< GPIO_T::PIN: PIN1 Position */
+#define GPIO_PIN_PIN1_Msk (0x1ul << GPIO_PIN_PIN1_Pos) /*!< GPIO_T::PIN: PIN1 Mask */
+
+#define GPIO_PIN_PIN2_Pos (2) /*!< GPIO_T::PIN: PIN2 Position */
+#define GPIO_PIN_PIN2_Msk (0x1ul << GPIO_PIN_PIN2_Pos) /*!< GPIO_T::PIN: PIN2 Mask */
+
+#define GPIO_PIN_PIN3_Pos (3) /*!< GPIO_T::PIN: PIN3 Position */
+#define GPIO_PIN_PIN3_Msk (0x1ul << GPIO_PIN_PIN3_Pos) /*!< GPIO_T::PIN: PIN3 Mask */
+
+#define GPIO_PIN_PIN4_Pos (4) /*!< GPIO_T::PIN: PIN4 Position */
+#define GPIO_PIN_PIN4_Msk (0x1ul << GPIO_PIN_PIN4_Pos) /*!< GPIO_T::PIN: PIN4 Mask */
+
+#define GPIO_PIN_PIN5_Pos (5) /*!< GPIO_T::PIN: PIN5 Position */
+#define GPIO_PIN_PIN5_Msk (0x1ul << GPIO_PIN_PIN5_Pos) /*!< GPIO_T::PIN: PIN5 Mask */
+
+#define GPIO_PIN_PIN6_Pos (6) /*!< GPIO_T::PIN: PIN6 Position */
+#define GPIO_PIN_PIN6_Msk (0x1ul << GPIO_PIN_PIN6_Pos) /*!< GPIO_T::PIN: PIN6 Mask */
+
+#define GPIO_PIN_PIN7_Pos (7) /*!< GPIO_T::PIN: PIN7 Position */
+#define GPIO_PIN_PIN7_Msk (0x1ul << GPIO_PIN_PIN7_Pos) /*!< GPIO_T::PIN: PIN7 Mask */
+
+#define GPIO_PIN_PIN8_Pos (8) /*!< GPIO_T::PIN: PIN8 Position */
+#define GPIO_PIN_PIN8_Msk (0x1ul << GPIO_PIN_PIN8_Pos) /*!< GPIO_T::PIN: PIN8 Mask */
+
+#define GPIO_PIN_PIN9_Pos (9) /*!< GPIO_T::PIN: PIN9 Position */
+#define GPIO_PIN_PIN9_Msk (0x1ul << GPIO_PIN_PIN9_Pos) /*!< GPIO_T::PIN: PIN9 Mask */
+
+#define GPIO_PIN_PIN10_Pos (10) /*!< GPIO_T::PIN: PIN10 Position */
+#define GPIO_PIN_PIN10_Msk (0x1ul << GPIO_PIN_PIN10_Pos) /*!< GPIO_T::PIN: PIN10 Mask */
+
+#define GPIO_PIN_PIN11_Pos (11) /*!< GPIO_T::PIN: PIN11 Position */
+#define GPIO_PIN_PIN11_Msk (0x1ul << GPIO_PIN_PIN11_Pos) /*!< GPIO_T::PIN: PIN11 Mask */
+
+#define GPIO_PIN_PIN12_Pos (12) /*!< GPIO_T::PIN: PIN12 Position */
+#define GPIO_PIN_PIN12_Msk (0x1ul << GPIO_PIN_PIN12_Pos) /*!< GPIO_T::PIN: PIN12 Mask */
+
+#define GPIO_PIN_PIN13_Pos (13) /*!< GPIO_T::PIN: PIN13 Position */
+#define GPIO_PIN_PIN13_Msk (0x1ul << GPIO_PIN_PIN13_Pos) /*!< GPIO_T::PIN: PIN13 Mask */
+
+#define GPIO_PIN_PIN14_Pos (14) /*!< GPIO_T::PIN: PIN14 Position */
+#define GPIO_PIN_PIN14_Msk (0x1ul << GPIO_PIN_PIN14_Pos) /*!< GPIO_T::PIN: PIN14 Mask */
+
+#define GPIO_PIN_PIN15_Pos (15) /*!< GPIO_T::PIN: PIN15 Position */
+#define GPIO_PIN_PIN15_Msk (0x1ul << GPIO_PIN_PIN15_Pos) /*!< GPIO_T::PIN: PIN15 Mask */
+
+#define GPIO_DBEN_DBEN0_Pos (0) /*!< GPIO_T::DBEN: DBEN0 Position */
+#define GPIO_DBEN_DBEN0_Msk (0x1ul << GPIO_DBEN_DBEN0_Pos) /*!< GPIO_T::DBEN: DBEN0 Mask */
+
+#define GPIO_DBEN_DBEN1_Pos (1) /*!< GPIO_T::DBEN: DBEN1 Position */
+#define GPIO_DBEN_DBEN1_Msk (0x1ul << GPIO_DBEN_DBEN1_Pos) /*!< GPIO_T::DBEN: DBEN1 Mask */
+
+#define GPIO_DBEN_DBEN2_Pos (2) /*!< GPIO_T::DBEN: DBEN2 Position */
+#define GPIO_DBEN_DBEN2_Msk (0x1ul << GPIO_DBEN_DBEN2_Pos) /*!< GPIO_T::DBEN: DBEN2 Mask */
+
+#define GPIO_DBEN_DBEN3_Pos (3) /*!< GPIO_T::DBEN: DBEN3 Position */
+#define GPIO_DBEN_DBEN3_Msk (0x1ul << GPIO_DBEN_DBEN3_Pos) /*!< GPIO_T::DBEN: DBEN3 Mask */
+
+#define GPIO_DBEN_DBEN4_Pos (4) /*!< GPIO_T::DBEN: DBEN4 Position */
+#define GPIO_DBEN_DBEN4_Msk (0x1ul << GPIO_DBEN_DBEN4_Pos) /*!< GPIO_T::DBEN: DBEN4 Mask */
+
+#define GPIO_DBEN_DBEN5_Pos (5) /*!< GPIO_T::DBEN: DBEN5 Position */
+#define GPIO_DBEN_DBEN5_Msk (0x1ul << GPIO_DBEN_DBEN5_Pos) /*!< GPIO_T::DBEN: DBEN5 Mask */
+
+#define GPIO_DBEN_DBEN6_Pos (6) /*!< GPIO_T::DBEN: DBEN6 Position */
+#define GPIO_DBEN_DBEN6_Msk (0x1ul << GPIO_DBEN_DBEN6_Pos) /*!< GPIO_T::DBEN: DBEN6 Mask */
+
+#define GPIO_DBEN_DBEN7_Pos (7) /*!< GPIO_T::DBEN: DBEN7 Position */
+#define GPIO_DBEN_DBEN7_Msk (0x1ul << GPIO_DBEN_DBEN7_Pos) /*!< GPIO_T::DBEN: DBEN7 Mask */
+
+#define GPIO_DBEN_DBEN8_Pos (8) /*!< GPIO_T::DBEN: DBEN8 Position */
+#define GPIO_DBEN_DBEN8_Msk (0x1ul << GPIO_DBEN_DBEN8_Pos) /*!< GPIO_T::DBEN: DBEN8 Mask */
+
+#define GPIO_DBEN_DBEN9_Pos (9) /*!< GPIO_T::DBEN: DBEN9 Position */
+#define GPIO_DBEN_DBEN9_Msk (0x1ul << GPIO_DBEN_DBEN9_Pos) /*!< GPIO_T::DBEN: DBEN9 Mask */
+
+#define GPIO_DBEN_DBEN10_Pos (10) /*!< GPIO_T::DBEN: DBEN10 Position */
+#define GPIO_DBEN_DBEN10_Msk (0x1ul << GPIO_DBEN_DBEN10_Pos) /*!< GPIO_T::DBEN: DBEN10 Mask */
+
+#define GPIO_DBEN_DBEN11_Pos (11) /*!< GPIO_T::DBEN: DBEN11 Position */
+#define GPIO_DBEN_DBEN11_Msk (0x1ul << GPIO_DBEN_DBEN11_Pos) /*!< GPIO_T::DBEN: DBEN11 Mask */
+
+#define GPIO_DBEN_DBEN12_Pos (12) /*!< GPIO_T::DBEN: DBEN12 Position */
+#define GPIO_DBEN_DBEN12_Msk (0x1ul << GPIO_DBEN_DBEN12_Pos) /*!< GPIO_T::DBEN: DBEN12 Mask */
+
+#define GPIO_DBEN_DBEN13_Pos (13) /*!< GPIO_T::DBEN: DBEN13 Position */
+#define GPIO_DBEN_DBEN13_Msk (0x1ul << GPIO_DBEN_DBEN13_Pos) /*!< GPIO_T::DBEN: DBEN13 Mask */
+
+#define GPIO_DBEN_DBEN14_Pos (14) /*!< GPIO_T::DBEN: DBEN14 Position */
+#define GPIO_DBEN_DBEN14_Msk (0x1ul << GPIO_DBEN_DBEN14_Pos) /*!< GPIO_T::DBEN: DBEN14 Mask */
+
+#define GPIO_DBEN_DBEN15_Pos (15) /*!< GPIO_T::DBEN: DBEN15 Position */
+#define GPIO_DBEN_DBEN15_Msk (0x1ul << GPIO_DBEN_DBEN15_Pos) /*!< GPIO_T::DBEN: DBEN15 Mask */
+
+#define GPIO_INTTYPE_TYPE0_Pos (0) /*!< GPIO_T::INTTYPE: TYPE0 Position */
+#define GPIO_INTTYPE_TYPE0_Msk (0x1ul << GPIO_INTTYPE_TYPE0_Pos) /*!< GPIO_T::INTTYPE: TYPE0 Mask */
+
+#define GPIO_INTTYPE_TYPE1_Pos (1) /*!< GPIO_T::INTTYPE: TYPE1 Position */
+#define GPIO_INTTYPE_TYPE1_Msk (0x1ul << GPIO_INTTYPE_TYPE1_Pos) /*!< GPIO_T::INTTYPE: TYPE1 Mask */
+
+#define GPIO_INTTYPE_TYPE2_Pos (2) /*!< GPIO_T::INTTYPE: TYPE2 Position */
+#define GPIO_INTTYPE_TYPE2_Msk (0x1ul << GPIO_INTTYPE_TYPE2_Pos) /*!< GPIO_T::INTTYPE: TYPE2 Mask */
+
+#define GPIO_INTTYPE_TYPE3_Pos (3) /*!< GPIO_T::INTTYPE: TYPE3 Position */
+#define GPIO_INTTYPE_TYPE3_Msk (0x1ul << GPIO_INTTYPE_TYPE3_Pos) /*!< GPIO_T::INTTYPE: TYPE3 Mask */
+
+#define GPIO_INTTYPE_TYPE4_Pos (4) /*!< GPIO_T::INTTYPE: TYPE4 Position */
+#define GPIO_INTTYPE_TYPE4_Msk (0x1ul << GPIO_INTTYPE_TYPE4_Pos) /*!< GPIO_T::INTTYPE: TYPE4 Mask */
+
+#define GPIO_INTTYPE_TYPE5_Pos (5) /*!< GPIO_T::INTTYPE: TYPE5 Position */
+#define GPIO_INTTYPE_TYPE5_Msk (0x1ul << GPIO_INTTYPE_TYPE5_Pos) /*!< GPIO_T::INTTYPE: TYPE5 Mask */
+
+#define GPIO_INTTYPE_TYPE6_Pos (6) /*!< GPIO_T::INTTYPE: TYPE6 Position */
+#define GPIO_INTTYPE_TYPE6_Msk (0x1ul << GPIO_INTTYPE_TYPE6_Pos) /*!< GPIO_T::INTTYPE: TYPE6 Mask */
+
+#define GPIO_INTTYPE_TYPE7_Pos (7) /*!< GPIO_T::INTTYPE: TYPE7 Position */
+#define GPIO_INTTYPE_TYPE7_Msk (0x1ul << GPIO_INTTYPE_TYPE7_Pos) /*!< GPIO_T::INTTYPE: TYPE7 Mask */
+
+#define GPIO_INTTYPE_TYPE8_Pos (8) /*!< GPIO_T::INTTYPE: TYPE8 Position */
+#define GPIO_INTTYPE_TYPE8_Msk (0x1ul << GPIO_INTTYPE_TYPE8_Pos) /*!< GPIO_T::INTTYPE: TYPE8 Mask */
+
+#define GPIO_INTTYPE_TYPE9_Pos (9) /*!< GPIO_T::INTTYPE: TYPE9 Position */
+#define GPIO_INTTYPE_TYPE9_Msk (0x1ul << GPIO_INTTYPE_TYPE9_Pos) /*!< GPIO_T::INTTYPE: TYPE9 Mask */
+
+#define GPIO_INTTYPE_TYPE10_Pos (10) /*!< GPIO_T::INTTYPE: TYPE10 Position */
+#define GPIO_INTTYPE_TYPE10_Msk (0x1ul << GPIO_INTTYPE_TYPE10_Pos) /*!< GPIO_T::INTTYPE: TYPE10 Mask */
+
+#define GPIO_INTTYPE_TYPE11_Pos (11) /*!< GPIO_T::INTTYPE: TYPE11 Position */
+#define GPIO_INTTYPE_TYPE11_Msk (0x1ul << GPIO_INTTYPE_TYPE11_Pos) /*!< GPIO_T::INTTYPE: TYPE11 Mask */
+
+#define GPIO_INTTYPE_TYPE12_Pos (12) /*!< GPIO_T::INTTYPE: TYPE12 Position */
+#define GPIO_INTTYPE_TYPE12_Msk (0x1ul << GPIO_INTTYPE_TYPE12_Pos) /*!< GPIO_T::INTTYPE: TYPE12 Mask */
+
+#define GPIO_INTTYPE_TYPE13_Pos (13) /*!< GPIO_T::INTTYPE: TYPE13 Position */
+#define GPIO_INTTYPE_TYPE13_Msk (0x1ul << GPIO_INTTYPE_TYPE13_Pos) /*!< GPIO_T::INTTYPE: TYPE13 Mask */
+
+#define GPIO_INTTYPE_TYPE14_Pos (14) /*!< GPIO_T::INTTYPE: TYPE14 Position */
+#define GPIO_INTTYPE_TYPE14_Msk (0x1ul << GPIO_INTTYPE_TYPE14_Pos) /*!< GPIO_T::INTTYPE: TYPE14 Mask */
+
+#define GPIO_INTTYPE_TYPE15_Pos (15) /*!< GPIO_T::INTTYPE: TYPE15 Position */
+#define GPIO_INTTYPE_TYPE15_Msk (0x1ul << GPIO_INTTYPE_TYPE15_Pos) /*!< GPIO_T::INTTYPE: TYPE15 Mask */
+
+#define GPIO_INTEN_FLIEN0_Pos (0) /*!< GPIO_T::INTEN: FLIEN0 Position */
+#define GPIO_INTEN_FLIEN0_Msk (0x1ul << GPIO_INTEN_FLIEN0_Pos) /*!< GPIO_T::INTEN: FLIEN0 Mask */
+
+#define GPIO_INTEN_FLIEN1_Pos (1) /*!< GPIO_T::INTEN: FLIEN1 Position */
+#define GPIO_INTEN_FLIEN1_Msk (0x1ul << GPIO_INTEN_FLIEN1_Pos) /*!< GPIO_T::INTEN: FLIEN1 Mask */
+
+#define GPIO_INTEN_FLIEN2_Pos (2) /*!< GPIO_T::INTEN: FLIEN2 Position */
+#define GPIO_INTEN_FLIEN2_Msk (0x1ul << GPIO_INTEN_FLIEN2_Pos) /*!< GPIO_T::INTEN: FLIEN2 Mask */
+
+#define GPIO_INTEN_FLIEN3_Pos (3) /*!< GPIO_T::INTEN: FLIEN3 Position */
+#define GPIO_INTEN_FLIEN3_Msk (0x1ul << GPIO_INTEN_FLIEN3_Pos) /*!< GPIO_T::INTEN: FLIEN3 Mask */
+
+#define GPIO_INTEN_FLIEN4_Pos (4) /*!< GPIO_T::INTEN: FLIEN4 Position */
+#define GPIO_INTEN_FLIEN4_Msk (0x1ul << GPIO_INTEN_FLIEN4_Pos) /*!< GPIO_T::INTEN: FLIEN4 Mask */
+
+#define GPIO_INTEN_FLIEN5_Pos (5) /*!< GPIO_T::INTEN: FLIEN5 Position */
+#define GPIO_INTEN_FLIEN5_Msk (0x1ul << GPIO_INTEN_FLIEN5_Pos) /*!< GPIO_T::INTEN: FLIEN5 Mask */
+
+#define GPIO_INTEN_FLIEN6_Pos (6) /*!< GPIO_T::INTEN: FLIEN6 Position */
+#define GPIO_INTEN_FLIEN6_Msk (0x1ul << GPIO_INTEN_FLIEN6_Pos) /*!< GPIO_T::INTEN: FLIEN6 Mask */
+
+#define GPIO_INTEN_FLIEN7_Pos (7) /*!< GPIO_T::INTEN: FLIEN7 Position */
+#define GPIO_INTEN_FLIEN7_Msk (0x1ul << GPIO_INTEN_FLIEN7_Pos) /*!< GPIO_T::INTEN: FLIEN7 Mask */
+
+#define GPIO_INTEN_FLIEN8_Pos (8) /*!< GPIO_T::INTEN: FLIEN8 Position */
+#define GPIO_INTEN_FLIEN8_Msk (0x1ul << GPIO_INTEN_FLIEN8_Pos) /*!< GPIO_T::INTEN: FLIEN8 Mask */
+
+#define GPIO_INTEN_FLIEN9_Pos (9) /*!< GPIO_T::INTEN: FLIEN9 Position */
+#define GPIO_INTEN_FLIEN9_Msk (0x1ul << GPIO_INTEN_FLIEN9_Pos) /*!< GPIO_T::INTEN: FLIEN9 Mask */
+
+#define GPIO_INTEN_FLIEN10_Pos (10) /*!< GPIO_T::INTEN: FLIEN10 Position */
+#define GPIO_INTEN_FLIEN10_Msk (0x1ul << GPIO_INTEN_FLIEN10_Pos) /*!< GPIO_T::INTEN: FLIEN10 Mask */
+
+#define GPIO_INTEN_FLIEN11_Pos (11) /*!< GPIO_T::INTEN: FLIEN11 Position */
+#define GPIO_INTEN_FLIEN11_Msk (0x1ul << GPIO_INTEN_FLIEN11_Pos) /*!< GPIO_T::INTEN: FLIEN11 Mask */
+
+#define GPIO_INTEN_FLIEN12_Pos (12) /*!< GPIO_T::INTEN: FLIEN12 Position */
+#define GPIO_INTEN_FLIEN12_Msk (0x1ul << GPIO_INTEN_FLIEN12_Pos) /*!< GPIO_T::INTEN: FLIEN12 Mask */
+
+#define GPIO_INTEN_FLIEN13_Pos (13) /*!< GPIO_T::INTEN: FLIEN13 Position */
+#define GPIO_INTEN_FLIEN13_Msk (0x1ul << GPIO_INTEN_FLIEN13_Pos) /*!< GPIO_T::INTEN: FLIEN13 Mask */
+
+#define GPIO_INTEN_FLIEN14_Pos (14) /*!< GPIO_T::INTEN: FLIEN14 Position */
+#define GPIO_INTEN_FLIEN14_Msk (0x1ul << GPIO_INTEN_FLIEN14_Pos) /*!< GPIO_T::INTEN: FLIEN14 Mask */
+
+#define GPIO_INTEN_FLIEN15_Pos (15) /*!< GPIO_T::INTEN: FLIEN15 Position */
+#define GPIO_INTEN_FLIEN15_Msk (0x1ul << GPIO_INTEN_FLIEN15_Pos) /*!< GPIO_T::INTEN: FLIEN15 Mask */
+
+#define GPIO_INTEN_RHIEN0_Pos (16) /*!< GPIO_T::INTEN: RHIEN0 Position */
+#define GPIO_INTEN_RHIEN0_Msk (0x1ul << GPIO_INTEN_RHIEN0_Pos) /*!< GPIO_T::INTEN: RHIEN0 Mask */
+
+#define GPIO_INTEN_RHIEN1_Pos (17) /*!< GPIO_T::INTEN: RHIEN1 Position */
+#define GPIO_INTEN_RHIEN1_Msk (0x1ul << GPIO_INTEN_RHIEN1_Pos) /*!< GPIO_T::INTEN: RHIEN1 Mask */
+
+#define GPIO_INTEN_RHIEN2_Pos (18) /*!< GPIO_T::INTEN: RHIEN2 Position */
+#define GPIO_INTEN_RHIEN2_Msk (0x1ul << GPIO_INTEN_RHIEN2_Pos) /*!< GPIO_T::INTEN: RHIEN2 Mask */
+
+#define GPIO_INTEN_RHIEN3_Pos (19) /*!< GPIO_T::INTEN: RHIEN3 Position */
+#define GPIO_INTEN_RHIEN3_Msk (0x1ul << GPIO_INTEN_RHIEN3_Pos) /*!< GPIO_T::INTEN: RHIEN3 Mask */
+
+#define GPIO_INTEN_RHIEN4_Pos (20) /*!< GPIO_T::INTEN: RHIEN4 Position */
+#define GPIO_INTEN_RHIEN4_Msk (0x1ul << GPIO_INTEN_RHIEN4_Pos) /*!< GPIO_T::INTEN: RHIEN4 Mask */
+
+#define GPIO_INTEN_RHIEN5_Pos (21) /*!< GPIO_T::INTEN: RHIEN5 Position */
+#define GPIO_INTEN_RHIEN5_Msk (0x1ul << GPIO_INTEN_RHIEN5_Pos) /*!< GPIO_T::INTEN: RHIEN5 Mask */
+
+#define GPIO_INTEN_RHIEN6_Pos (22) /*!< GPIO_T::INTEN: RHIEN6 Position */
+#define GPIO_INTEN_RHIEN6_Msk (0x1ul << GPIO_INTEN_RHIEN6_Pos) /*!< GPIO_T::INTEN: RHIEN6 Mask */
+
+#define GPIO_INTEN_RHIEN7_Pos (23) /*!< GPIO_T::INTEN: RHIEN7 Position */
+#define GPIO_INTEN_RHIEN7_Msk (0x1ul << GPIO_INTEN_RHIEN7_Pos) /*!< GPIO_T::INTEN: RHIEN7 Mask */
+
+#define GPIO_INTEN_RHIEN8_Pos (24) /*!< GPIO_T::INTEN: RHIEN8 Position */
+#define GPIO_INTEN_RHIEN8_Msk (0x1ul << GPIO_INTEN_RHIEN8_Pos) /*!< GPIO_T::INTEN: RHIEN8 Mask */
+
+#define GPIO_INTEN_RHIEN9_Pos (25) /*!< GPIO_T::INTEN: RHIEN9 Position */
+#define GPIO_INTEN_RHIEN9_Msk (0x1ul << GPIO_INTEN_RHIEN9_Pos) /*!< GPIO_T::INTEN: RHIEN9 Mask */
+
+#define GPIO_INTEN_RHIEN10_Pos (26) /*!< GPIO_T::INTEN: RHIEN10 Position */
+#define GPIO_INTEN_RHIEN10_Msk (0x1ul << GPIO_INTEN_RHIEN10_Pos) /*!< GPIO_T::INTEN: RHIEN10 Mask */
+
+#define GPIO_INTEN_RHIEN11_Pos (27) /*!< GPIO_T::INTEN: RHIEN11 Position */
+#define GPIO_INTEN_RHIEN11_Msk (0x1ul << GPIO_INTEN_RHIEN11_Pos) /*!< GPIO_T::INTEN: RHIEN11 Mask */
+
+#define GPIO_INTEN_RHIEN12_Pos (28) /*!< GPIO_T::INTEN: RHIEN12 Position */
+#define GPIO_INTEN_RHIEN12_Msk (0x1ul << GPIO_INTEN_RHIEN12_Pos) /*!< GPIO_T::INTEN: RHIEN12 Mask */
+
+#define GPIO_INTEN_RHIEN13_Pos (29) /*!< GPIO_T::INTEN: RHIEN13 Position */
+#define GPIO_INTEN_RHIEN13_Msk (0x1ul << GPIO_INTEN_RHIEN13_Pos) /*!< GPIO_T::INTEN: RHIEN13 Mask */
+
+#define GPIO_INTEN_RHIEN14_Pos (30) /*!< GPIO_T::INTEN: RHIEN14 Position */
+#define GPIO_INTEN_RHIEN14_Msk (0x1ul << GPIO_INTEN_RHIEN14_Pos) /*!< GPIO_T::INTEN: RHIEN14 Mask */
+
+#define GPIO_INTEN_RHIEN15_Pos (31) /*!< GPIO_T::INTEN: RHIEN15 Position */
+#define GPIO_INTEN_RHIEN15_Msk (0x1ul << GPIO_INTEN_RHIEN15_Pos) /*!< GPIO_T::INTEN: RHIEN15 Mask */
+
+#define GPIO_INTSRC_INTSRC0_Pos (0) /*!< GPIO_T::INTSRC: INTSRC0 Position */
+#define GPIO_INTSRC_INTSRC0_Msk (0x1ul << GPIO_INTSRC_INTSRC0_Pos) /*!< GPIO_T::INTSRC: INTSRC0 Mask */
+
+#define GPIO_INTSRC_INTSRC1_Pos (1) /*!< GPIO_T::INTSRC: INTSRC1 Position */
+#define GPIO_INTSRC_INTSRC1_Msk (0x1ul << GPIO_INTSRC_INTSRC1_Pos) /*!< GPIO_T::INTSRC: INTSRC1 Mask */
+
+#define GPIO_INTSRC_INTSRC2_Pos (2) /*!< GPIO_T::INTSRC: INTSRC2 Position */
+#define GPIO_INTSRC_INTSRC2_Msk (0x1ul << GPIO_INTSRC_INTSRC2_Pos) /*!< GPIO_T::INTSRC: INTSRC2 Mask */
+
+#define GPIO_INTSRC_INTSRC3_Pos (3) /*!< GPIO_T::INTSRC: INTSRC3 Position */
+#define GPIO_INTSRC_INTSRC3_Msk (0x1ul << GPIO_INTSRC_INTSRC3_Pos) /*!< GPIO_T::INTSRC: INTSRC3 Mask */
+
+#define GPIO_INTSRC_INTSRC4_Pos (4) /*!< GPIO_T::INTSRC: INTSRC4 Position */
+#define GPIO_INTSRC_INTSRC4_Msk (0x1ul << GPIO_INTSRC_INTSRC4_Pos) /*!< GPIO_T::INTSRC: INTSRC4 Mask */
+
+#define GPIO_INTSRC_INTSRC5_Pos (5) /*!< GPIO_T::INTSRC: INTSRC5 Position */
+#define GPIO_INTSRC_INTSRC5_Msk (0x1ul << GPIO_INTSRC_INTSRC5_Pos) /*!< GPIO_T::INTSRC: INTSRC5 Mask */
+
+#define GPIO_INTSRC_INTSRC6_Pos (6) /*!< GPIO_T::INTSRC: INTSRC6 Position */
+#define GPIO_INTSRC_INTSRC6_Msk (0x1ul << GPIO_INTSRC_INTSRC6_Pos) /*!< GPIO_T::INTSRC: INTSRC6 Mask */
+
+#define GPIO_INTSRC_INTSRC7_Pos (7) /*!< GPIO_T::INTSRC: INTSRC7 Position */
+#define GPIO_INTSRC_INTSRC7_Msk (0x1ul << GPIO_INTSRC_INTSRC7_Pos) /*!< GPIO_T::INTSRC: INTSRC7 Mask */
+
+#define GPIO_INTSRC_INTSRC8_Pos (8) /*!< GPIO_T::INTSRC: INTSRC8 Position */
+#define GPIO_INTSRC_INTSRC8_Msk (0x1ul << GPIO_INTSRC_INTSRC8_Pos) /*!< GPIO_T::INTSRC: INTSRC8 Mask */
+
+#define GPIO_INTSRC_INTSRC9_Pos (9) /*!< GPIO_T::INTSRC: INTSRC9 Position */
+#define GPIO_INTSRC_INTSRC9_Msk (0x1ul << GPIO_INTSRC_INTSRC9_Pos) /*!< GPIO_T::INTSRC: INTSRC9 Mask */
+
+#define GPIO_INTSRC_INTSRC10_Pos (10) /*!< GPIO_T::INTSRC: INTSRC10 Position */
+#define GPIO_INTSRC_INTSRC10_Msk (0x1ul << GPIO_INTSRC_INTSRC10_Pos) /*!< GPIO_T::INTSRC: INTSRC10 Mask */
+
+#define GPIO_INTSRC_INTSRC11_Pos (11) /*!< GPIO_T::INTSRC: INTSRC11 Position */
+#define GPIO_INTSRC_INTSRC11_Msk (0x1ul << GPIO_INTSRC_INTSRC11_Pos) /*!< GPIO_T::INTSRC: INTSRC11 Mask */
+
+#define GPIO_INTSRC_INTSRC12_Pos (12) /*!< GPIO_T::INTSRC: INTSRC12 Position */
+#define GPIO_INTSRC_INTSRC12_Msk (0x1ul << GPIO_INTSRC_INTSRC12_Pos) /*!< GPIO_T::INTSRC: INTSRC12 Mask */
+
+#define GPIO_INTSRC_INTSRC13_Pos (13) /*!< GPIO_T::INTSRC: INTSRC13 Position */
+#define GPIO_INTSRC_INTSRC13_Msk (0x1ul << GPIO_INTSRC_INTSRC13_Pos) /*!< GPIO_T::INTSRC: INTSRC13 Mask */
+
+#define GPIO_INTSRC_INTSRC14_Pos (14) /*!< GPIO_T::INTSRC: INTSRC14 Position */
+#define GPIO_INTSRC_INTSRC14_Msk (0x1ul << GPIO_INTSRC_INTSRC14_Pos) /*!< GPIO_T::INTSRC: INTSRC14 Mask */
+
+#define GPIO_INTSRC_INTSRC15_Pos (15) /*!< GPIO_T::INTSRC: INTSRC15 Position */
+#define GPIO_INTSRC_INTSRC15_Msk (0x1ul << GPIO_INTSRC_INTSRC15_Pos) /*!< GPIO_T::INTSRC: INTSRC15 Mask */
+
+#define GPIO_SMTEN_SMTEN0_Pos (0) /*!< GPIO_T::SMTEN: SMTEN0 Position */
+#define GPIO_SMTEN_SMTEN0_Msk (0x1ul << GPIO_SMTEN_SMTEN0_Pos) /*!< GPIO_T::SMTEN: SMTEN0 Mask */
+
+#define GPIO_SMTEN_SMTEN1_Pos (1) /*!< GPIO_T::SMTEN: SMTEN1 Position */
+#define GPIO_SMTEN_SMTEN1_Msk (0x1ul << GPIO_SMTEN_SMTEN1_Pos) /*!< GPIO_T::SMTEN: SMTEN1 Mask */
+
+#define GPIO_SMTEN_SMTEN2_Pos (2) /*!< GPIO_T::SMTEN: SMTEN2 Position */
+#define GPIO_SMTEN_SMTEN2_Msk (0x1ul << GPIO_SMTEN_SMTEN2_Pos) /*!< GPIO_T::SMTEN: SMTEN2 Mask */
+
+#define GPIO_SMTEN_SMTEN3_Pos (3) /*!< GPIO_T::SMTEN: SMTEN3 Position */
+#define GPIO_SMTEN_SMTEN3_Msk (0x1ul << GPIO_SMTEN_SMTEN3_Pos) /*!< GPIO_T::SMTEN: SMTEN3 Mask */
+
+#define GPIO_SMTEN_SMTEN4_Pos (4) /*!< GPIO_T::SMTEN: SMTEN4 Position */
+#define GPIO_SMTEN_SMTEN4_Msk (0x1ul << GPIO_SMTEN_SMTEN4_Pos) /*!< GPIO_T::SMTEN: SMTEN4 Mask */
+
+#define GPIO_SMTEN_SMTEN5_Pos (5) /*!< GPIO_T::SMTEN: SMTEN5 Position */
+#define GPIO_SMTEN_SMTEN5_Msk (0x1ul << GPIO_SMTEN_SMTEN5_Pos) /*!< GPIO_T::SMTEN: SMTEN5 Mask */
+
+#define GPIO_SMTEN_SMTEN6_Pos (6) /*!< GPIO_T::SMTEN: SMTEN6 Position */
+#define GPIO_SMTEN_SMTEN6_Msk (0x1ul << GPIO_SMTEN_SMTEN6_Pos) /*!< GPIO_T::SMTEN: SMTEN6 Mask */
+
+#define GPIO_SMTEN_SMTEN7_Pos (7) /*!< GPIO_T::SMTEN: SMTEN7 Position */
+#define GPIO_SMTEN_SMTEN7_Msk (0x1ul << GPIO_SMTEN_SMTEN7_Pos) /*!< GPIO_T::SMTEN: SMTEN7 Mask */
+
+#define GPIO_SMTEN_SMTEN8_Pos (8) /*!< GPIO_T::SMTEN: SMTEN8 Position */
+#define GPIO_SMTEN_SMTEN8_Msk (0x1ul << GPIO_SMTEN_SMTEN8_Pos) /*!< GPIO_T::SMTEN: SMTEN8 Mask */
+
+#define GPIO_SMTEN_SMTEN9_Pos (9) /*!< GPIO_T::SMTEN: SMTEN9 Position */
+#define GPIO_SMTEN_SMTEN9_Msk (0x1ul << GPIO_SMTEN_SMTEN9_Pos) /*!< GPIO_T::SMTEN: SMTEN9 Mask */
+
+#define GPIO_SMTEN_SMTEN10_Pos (10) /*!< GPIO_T::SMTEN: SMTEN10 Position */
+#define GPIO_SMTEN_SMTEN10_Msk (0x1ul << GPIO_SMTEN_SMTEN10_Pos) /*!< GPIO_T::SMTEN: SMTEN10 Mask */
+
+#define GPIO_SMTEN_SMTEN11_Pos (11) /*!< GPIO_T::SMTEN: SMTEN11 Position */
+#define GPIO_SMTEN_SMTEN11_Msk (0x1ul << GPIO_SMTEN_SMTEN11_Pos) /*!< GPIO_T::SMTEN: SMTEN11 Mask */
+
+#define GPIO_SMTEN_SMTEN12_Pos (12) /*!< GPIO_T::SMTEN: SMTEN12 Position */
+#define GPIO_SMTEN_SMTEN12_Msk (0x1ul << GPIO_SMTEN_SMTEN12_Pos) /*!< GPIO_T::SMTEN: SMTEN12 Mask */
+
+#define GPIO_SMTEN_SMTEN13_Pos (13) /*!< GPIO_T::SMTEN: SMTEN13 Position */
+#define GPIO_SMTEN_SMTEN13_Msk (0x1ul << GPIO_SMTEN_SMTEN13_Pos) /*!< GPIO_T::SMTEN: SMTEN13 Mask */
+
+#define GPIO_SMTEN_SMTEN14_Pos (14) /*!< GPIO_T::SMTEN: SMTEN14 Position */
+#define GPIO_SMTEN_SMTEN14_Msk (0x1ul << GPIO_SMTEN_SMTEN14_Pos) /*!< GPIO_T::SMTEN: SMTEN14 Mask */
+
+#define GPIO_SMTEN_SMTEN15_Pos (15) /*!< GPIO_T::SMTEN: SMTEN15 Position */
+#define GPIO_SMTEN_SMTEN15_Msk (0x1ul << GPIO_SMTEN_SMTEN15_Pos) /*!< GPIO_T::SMTEN: SMTEN15 Mask */
+
+#define GPIO_SLEWCTL_HSREN0_Pos (0) /*!< GPIO_T::SLEWCTL: HSREN0 Position */
+#define GPIO_SLEWCTL_HSREN0_Msk (0x1ul << GPIO_SLEWCTL_HSREN0_Pos) /*!< GPIO_T::SLEWCTL: HSREN0 Mask */
+
+#define GPIO_SLEWCTL_HSREN1_Pos (1) /*!< GPIO_T::SLEWCTL: HSREN1 Position */
+#define GPIO_SLEWCTL_HSREN1_Msk (0x1ul << GPIO_SLEWCTL_HSREN1_Pos) /*!< GPIO_T::SLEWCTL: HSREN1 Mask */
+
+#define GPIO_SLEWCTL_HSREN2_Pos (2) /*!< GPIO_T::SLEWCTL: HSREN2 Position */
+#define GPIO_SLEWCTL_HSREN2_Msk (0x1ul << GPIO_SLEWCTL_HSREN2_Pos) /*!< GPIO_T::SLEWCTL: HSREN2 Mask */
+
+#define GPIO_SLEWCTL_HSREN3_Pos (3) /*!< GPIO_T::SLEWCTL: HSREN3 Position */
+#define GPIO_SLEWCTL_HSREN3_Msk (0x1ul << GPIO_SLEWCTL_HSREN3_Pos) /*!< GPIO_T::SLEWCTL: HSREN3 Mask */
+
+#define GPIO_SLEWCTL_HSREN4_Pos (4) /*!< GPIO_T::SLEWCTL: HSREN4 Position */
+#define GPIO_SLEWCTL_HSREN4_Msk (0x1ul << GPIO_SLEWCTL_HSREN4_Pos) /*!< GPIO_T::SLEWCTL: HSREN4 Mask */
+
+#define GPIO_SLEWCTL_HSREN5_Pos (5) /*!< GPIO_T::SLEWCTL: HSREN5 Position */
+#define GPIO_SLEWCTL_HSREN5_Msk (0x1ul << GPIO_SLEWCTL_HSREN5_Pos) /*!< GPIO_T::SLEWCTL: HSREN5 Mask */
+
+#define GPIO_SLEWCTL_HSREN6_Pos (6) /*!< GPIO_T::SLEWCTL: HSREN6 Position */
+#define GPIO_SLEWCTL_HSREN6_Msk (0x1ul << GPIO_SLEWCTL_HSREN6_Pos) /*!< GPIO_T::SLEWCTL: HSREN6 Mask */
+
+#define GPIO_SLEWCTL_HSREN7_Pos (7) /*!< GPIO_T::SLEWCTL: HSREN7 Position */
+#define GPIO_SLEWCTL_HSREN7_Msk (0x1ul << GPIO_SLEWCTL_HSREN7_Pos) /*!< GPIO_T::SLEWCTL: HSREN7 Mask */
+
+#define GPIO_SLEWCTL_HSREN8_Pos (8) /*!< GPIO_T::SLEWCTL: HSREN8 Position */
+#define GPIO_SLEWCTL_HSREN8_Msk (0x1ul << GPIO_SLEWCTL_HSREN8_Pos) /*!< GPIO_T::SLEWCTL: HSREN8 Mask */
+
+#define GPIO_SLEWCTL_HSREN9_Pos (9) /*!< GPIO_T::SLEWCTL: HSREN9 Position */
+#define GPIO_SLEWCTL_HSREN9_Msk (0x1ul << GPIO_SLEWCTL_HSREN9_Pos) /*!< GPIO_T::SLEWCTL: HSREN9 Mask */
+
+#define GPIO_SLEWCTL_HSREN10_Pos (10) /*!< GPIO_T::SLEWCTL: HSREN10 Position */
+#define GPIO_SLEWCTL_HSREN10_Msk (0x1ul << GPIO_SLEWCTL_HSREN10_Pos) /*!< GPIO_T::SLEWCTL: HSREN10 Mask */
+
+#define GPIO_SLEWCTL_HSREN11_Pos (11) /*!< GPIO_T::SLEWCTL: HSREN11 Position */
+#define GPIO_SLEWCTL_HSREN11_Msk (0x1ul << GPIO_SLEWCTL_HSREN11_Pos) /*!< GPIO_T::SLEWCTL: HSREN11 Mask */
+
+#define GPIO_SLEWCTL_HSREN12_Pos (12) /*!< GPIO_T::SLEWCTL: HSREN12 Position */
+#define GPIO_SLEWCTL_HSREN12_Msk (0x1ul << GPIO_SLEWCTL_HSREN12_Pos) /*!< GPIO_T::SLEWCTL: HSREN12 Mask */
+
+#define GPIO_SLEWCTL_HSREN13_Pos (13) /*!< GPIO_T::SLEWCTL: HSREN13 Position */
+#define GPIO_SLEWCTL_HSREN13_Msk (0x1ul << GPIO_SLEWCTL_HSREN13_Pos) /*!< GPIO_T::SLEWCTL: HSREN13 Mask */
+
+#define GPIO_SLEWCTL_HSREN14_Pos (14) /*!< GPIO_T::SLEWCTL: HSREN14 Position */
+#define GPIO_SLEWCTL_HSREN14_Msk (0x1ul << GPIO_SLEWCTL_HSREN14_Pos) /*!< GPIO_T::SLEWCTL: HSREN14 Mask */
+
+#define GPIO_SLEWCTL_HSREN15_Pos (15) /*!< GPIO_T::SLEWCTL: HSREN15 Position */
+#define GPIO_SLEWCTL_HSREN15_Msk (0x1ul << GPIO_SLEWCTL_HSREN15_Pos) /*!< GPIO_T::SLEWCTL: HSREN15 Mask */
+
+#define GPIO_DRVCTL_HDRVEN8_Pos (8) /*!< GPIO_T::DRVCTL: HDRVEN8 Position */
+#define GPIO_DRVCTL_HDRVEN8_Msk (0x1ul << GPIO_DRVCTL_HDRVEN8_Pos) /*!< GPIO_T::DRVCTL: HDRVEN8 Mask */
+
+#define GPIO_DRVCTL_HDRVEN9_Pos (9) /*!< GPIO_T::DRVCTL: HDRVEN9 Position */
+#define GPIO_DRVCTL_HDRVEN9_Msk (0x1ul << GPIO_DRVCTL_HDRVEN9_Pos) /*!< GPIO_T::DRVCTL: HDRVEN9 Mask */
+
+#define GPIO_DRVCTL_HDRVEN10_Pos (10) /*!< GPIO_T::DRVCTL: HDRVEN10 Position */
+#define GPIO_DRVCTL_HDRVEN10_Msk (0x1ul << GPIO_DRVCTL_HDRVEN10_Pos) /*!< GPIO_T::DRVCTL: HDRVEN10 Mask */
+
+#define GPIO_DRVCTL_HDRVEN11_Pos (11) /*!< GPIO_T::DRVCTL: HDRVEN11 Position */
+#define GPIO_DRVCTL_HDRVEN11_Msk (0x1ul << GPIO_DRVCTL_HDRVEN11_Pos) /*!< GPIO_T::DRVCTL: HDRVEN11 Mask */
+
+#define GPIO_DRVCTL_HDRVEN12_Pos (12) /*!< GPIO_T::DRVCTL: HDRVEN12 Position */
+#define GPIO_DRVCTL_HDRVEN12_Msk (0x1ul << GPIO_DRVCTL_HDRVEN12_Pos) /*!< GPIO_T::DRVCTL: HDRVEN12 Mask */
+
+#define GPIO_DRVCTL_HDRVEN13_Pos (13) /*!< GPIO_T::DRVCTL: HDRVEN13 Position */
+#define GPIO_DRVCTL_HDRVEN13_Msk (0x1ul << GPIO_DRVCTL_HDRVEN13_Pos) /*!< GPIO_T::DRVCTL: HDRVEN13 Mask */
+
+#define GPIO_DBCTL_DBCLKSEL_Pos (0) /*!< GPIO_T::DBCTL: DBCLKSEL Position */
+#define GPIO_DBCTL_DBCLKSEL_Msk (0xFul << GPIO_DBCTL_DBCLKSEL_Pos) /*!< GPIO_T::DBCTL: DBCLKSEL Mask */
+
+#define GPIO_DBCTL_DBCLKSRC_Pos (4) /*!< GPIO_T::DBCTL: DBCLKSRC Position */
+#define GPIO_DBCTL_DBCLKSRC_Msk (1ul << GPIO_DBCTL_DBCLKSRC_Pos) /*!< GPIO_T::DBCTL: DBCLKSRC Mask */
+
+#define GPIO_DBCTL_ICLKON_Pos (5) /*!< GPIO_T::DBCTL: ICLKON Position */
+#define GPIO_DBCTL_ICLKON_Msk (1ul << GPIO_DBCTL_ICLKON_Pos) /*!< GPIO_T::DBCTL: ICLKON Mask */
+
+
+/**@}*/ /* GPIO_CONST */
+/**@}*/ /* end of GPIO register group */
+
+
+/*---------------------- Inter-IC Bus Controller -------------------------*/
+/**
+ @addtogroup I2C Inter-IC Bus Controller(I2C)
+ Memory Mapped Structure for I2C Controller
+@{ */
+
+
+typedef struct
+{
+
+
+
+
+/**
+ * @var I2C_T::CTL
+ * Offset: 0x00 I2C Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[2] |AA |Assert Acknowledge Control
+ * | | |When AA =1 prior to address or data is received,
+ * | | |an acknowledged (low level to SDA) will be returned during the acknowledge clock pulse on the SCL line when
+ * | | |1. A slave is acknowledging the address sent from master.
+ * | | |2. The receiver devices are acknowledging the data sent by transmitter.
+ * | | |When AA=0 prior to address or data received,
+ * | | |a Not acknowledged (high level to SDA) will be returned during the acknowledge clock pulse on the SCL line.
+ * |[3] |SI |I2C Interrupt Flag
+ * | | |When a new I2C state is present in the I2C_STATUS register, the SI flag is set by hardware.
+ * | | |If bit INTEN (I2C_CTL [7]) is set, the I2C interrupt is requested.
+ * | | |SI must be cleared by software.
+ * | | |Clear SI by writing 1 to this bit.
+ * | | |For ACKMEN is set in slave read mode, the SI flag is set in 8th clock period for user to confirm the acknowledge bit and 9th clock period for user to read the data in the data buffer.
+ * |[4] |STO |I2C STOP Control
+ * | | |In Master mode, setting STO to transmit a STOP condition to bus then I2C controller will check the bus condition if a STOP condition is detected.
+ * | | |This bit will be cleared by hardware automatically.
+ * |[5] |STA |I2C START Control
+ * | | |Setting STA to logic 1 to enter Master mode, the I2C hardware sends a START or repeat START condition to bus when the bus is free.
+ * |[6] |I2CEN |I2C Controller Enable Bit
+ * | | |Set to enable I2C serial function controller.
+ * | | |When I2CEN=1 the I2C serial function enable.
+ * | | |The multi-function pin function must set to SDA, and SCL of I2C function first.
+ * | | |0 = Disabled.
+ * | | |1 = Enabled.
+ * |[7] |INTEN |Enable Interrupt
+ * | | |0 = I2C interrupt Disabled.
+ * | | |1 = I2C interrupt Enabled.
+ * @var I2C_T::ADDR0
+ * Offset: 0x04 I2C Slave Address Register0
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |GC |General Call Function
+ * | | |0 = General Call Function Disabled.
+ * | | |1 = General Call Function Enabled.
+ * |[7:1] |ADDR |I2C Address
+ * | | |The content of this register is irrelevant when I2C is in Master mode.
+ * | | |In the slave mode, the seven most significant bits must be loaded with the chip's own address.
+ * | | |The I2C hardware will react if either of the address is matched.
+ * @var I2C_T::DAT
+ * Offset: 0x08 I2C Data Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:0] |DAT |I2C Data
+ * | | |Bit [7:0] is located with the 8-bit transferred/received data of I2C serial port.
+ * @var I2C_T::STATUS
+ * Offset: 0x0C I2C Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:0] |STATUS |I2C Status
+ * | | |The three least significant bits are always 0.
+ * | | |The five most significant bits contain the status code.
+ * | | |There are 28 possible status codes.
+ * | | |When the content of I2C_STATUS is F8H, no serial interrupt is requested.
+ * | | |Others I2C_STATUS values correspond to defined I2C states.
+ * | | |When each of these states is entered, a status interrupt is requested (SI = 1).
+ * | | |A valid status code is present in I2C_STATUS one cycle after SI is set by hardware and is still present one cycle after SI has been reset by software.
+ * | | |In addition, states 00H stands for a Bus Error.
+ * | | |A Bus Error occurs when a START or STOP condition is present at an illegal position in the formation frame.
+ * | | |Example of illegal position are during the serial transfer of an address byte, a data byte or an acknowledge bit.
+ * | | |Note:
+ * | | |1.
+ * | | |If the BUSEN and ACKMEN are enabled in slave received mode, there is SI interrupt in the 8th clock.
+ * | | |The user can read the I2C_STATUS = 0xf0 for the function condition has done.
+ * | | |2.
+ * | | |If the BUSEN and PECEN are enabled, the status of PECERR, I2C_BUSSTS[3], is used to substitute for I2C_STATUS to check the ACK status in the last frame when the byte count done interrupt has active and the PEC frame has been transformed.
+ * @var I2C_T::CLKDIV
+ * Offset: 0x10 I2C Clock Divided Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:0] |DIVIDER |I2C Clock Divided
+ * | | |Indicates the I2C clock rate: Data Baud Rate of I2C = (system clock) / (4x (I2C_CLKDIV+1)).
+ * | | |Note: The minimum value of I2C_CLKDIV is 4.
+ * @var I2C_T::TOCTL
+ * Offset: 0x14 I2C Time-out Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |TOIF |Time-Out Flag
+ * | | |This bit is set by hardware when I2C time-out happened and it can interrupt CPU if I2C interrupt enable bit (INTEN) is set to 1.
+ * | | |Note: Software can write 1 to clear this bit.
+ * |[1] |TOCDIV4 |Time-Out Counter Input Clock Divided By 4
+ * | | |When Enabled, The time-out period is extend 4 times.
+ * | | |0 = Disabled.
+ * | | |1 = Enabled.
+ * |[2] |TOCEN |Time-Out Counter Enable Bit
+ * | | |When Enabled, the 14-bit time-out counter will start counting when SI is clear.
+ * | | |Setting flag SI to '1' will reset counter and re-start up counting after SI is cleared.
+ * | | |0 = Disabled.
+ * | | |1 = Enabled.
+ * @var I2C_T::ADDR1
+ * Offset: 0x18 I2C Slave Address Register1
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |GC |General Call Function
+ * | | |0 = General Call Function Disabled.
+ * | | |1 = General Call Function Enabled.
+ * |[7:1] |ADDR |I2C Address
+ * | | |The content of this register is irrelevant when I2C is in Master mode.
+ * | | |In the slave mode, the seven most significant bits must be loaded with the chip's own address.
+ * | | |The I2C hardware will react if either of the address is matched.
+ * @var I2C_T::ADDR2
+ * Offset: 0x1C I2C Slave Address Register2
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |GC |General Call Function
+ * | | |0 = General Call Function Disabled.
+ * | | |1 = General Call Function Enabled.
+ * |[7:1] |ADDR |I2C Address
+ * | | |The content of this register is irrelevant when I2C is in Master mode.
+ * | | |In the slave mode, the seven most significant bits must be loaded with the chip's own address.
+ * | | |The I2C hardware will react if either of the address is matched.
+ * @var I2C_T::ADDR3
+ * Offset: 0x20 I2C Slave Address Register3
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |GC |General Call Function
+ * | | |0 = General Call Function Disabled.
+ * | | |1 = General Call Function Enabled.
+ * |[7:1] |ADDR |I2C Address
+ * | | |The content of this register is irrelevant when I2C is in Master mode.
+ * | | |In the slave mode, the seven most significant bits must be loaded with the chip's own address.
+ * | | |The I2C hardware will react if either of the address is matched.
+ * @var I2C_T::ADDRMSK0
+ * Offset: 0x24 I2C Slave Address Mask Register0
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:1] |ADDRMSK |I2C Address Mask
+ * | | |0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.).
+ * | | |1 = Mask Enabled (the received corresponding address bit is don't care.).
+ * | | |I2C bus controllers support multiple address recognition with four address mask register.
+ * | | |When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care.
+ * | | |If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.
+ * @var I2C_T::ADDRMSK1
+ * Offset: 0x28 I2C Slave Address Mask Register1
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:1] |ADDRMSK |I2C Address Mask
+ * | | |0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.).
+ * | | |1 = Mask Enabled (the received corresponding address bit is don't care.).
+ * | | |I2C bus controllers support multiple address recognition with four address mask register.
+ * | | |When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care.
+ * | | |If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.
+ * @var I2C_T::ADDRMSK2
+ * Offset: 0x2C I2C Slave Address Mask Register2
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:1] |ADDRMSK |I2C Address Mask
+ * | | |0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.).
+ * | | |1 = Mask Enabled (the received corresponding address bit is don't care.).
+ * | | |I2C bus controllers support multiple address recognition with four address mask register.
+ * | | |When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care.
+ * | | |If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.
+ * @var I2C_T::ADDRMSK3
+ * Offset: 0x30 I2C Slave Address Mask Register3
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:1] |ADDRMSK |I2C Address Mask
+ * | | |0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.).
+ * | | |1 = Mask Enabled (the received corresponding address bit is don't care.).
+ * | | |I2C bus controllers support multiple address recognition with four address mask register.
+ * | | |When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care.
+ * | | |If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.
+ * @var I2C_T::WKCTL
+ * Offset: 0x3C I2C Wake-up Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |WKEN |I2C Wake-Up Enable Bit
+ * | | |0 = I2C wake-up function Disabled.
+ * | | |1= I2C wake-up function Enabled.
+ * @var I2C_T::WKSTS
+ * Offset: 0x40 I2C Wake-up Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |WKIF |I2C Wake-Up Flag
+ * | | |When chip is woken up from Power-down mode by I2C, this bit is set to 1.
+ * | | |Software can write 1 to clear this bit.
+ * @var I2C_T::BUSCTL
+ * Offset: 0x44 I2C Bus Management Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |ACKMEN |Acknowledge Control By Manual
+ * | | |In order to allow ACK control in slave reception including the command and data, slave byte control mode must be enabled by setting the ACKMEN bit.
+ * | | |0 = Slave byte control Disabled.
+ * | | |1 = Slave byte control Enabled.
+ * | | |The 9th bit can response the ACK or NACK according the received data by user.
+ * | | |When the byte is received, stretching the SCLK signal low between the 8th and 9th SCLK pulse.
+ * | | |Note: If the BMDEN =1 and this bit is enabled, the information of I2C_STATUS will be fixed as 0xF0 in slave receive condition.
+ * |[1] |PECEN |Packet Error Checking Calculation Enable Bit
+ * | | |0 = Packet Error Checking Calculation Disabled.
+ * | | |1 = Packet Error Checking Calculation Enabled.
+ * |[2] |BMDEN |Bus Management Device Default Address Enable Bit
+ * | | |0 = Device default address Disable.
+ * | | |When the address 0'b1100001x coming and the both of BMDEN and ACKMEN are enabled, the device responses NACKed.
+ * | | |1 = Device default address Enabled.
+ * | | |When the address 0'b1100001x coming and the both of BMDEN and ACKMEN are enabled, the device responses ACKed.
+ * |[3] |BMHEN |Bus Management Host Enable Bit
+ * | | |0 = Host function Disabled.
+ * | | |1 = Host function Enabled and the SUSCON will be used as CONTROL function.
+ * |[4] |ALERTEN |Bus Management Alert Enable Bit
+ * | | |Device Mode (BMHEN =0).
+ * | | |0 = Release the BM_ALERT pin high and Alert Response Header disabled: 0001100x followed by NACK if both of BMDEN and ACKMEN are enabled.
+ * | | |1 = Drive BM_ALERT pin low and Alert Response Address Header enables: 0001100x followed by ACK if both of BMDEN and ACKMEN are enabled.
+ * | | |Host Mode (BMHEN =1).
+ * | | |0 = BM_ALERT pin not supported.
+ * | | |1 = BM_ALERT pin supported.
+ * |[5] |SCTLOSTS |Suspend/Control Data Output Status
+ * | | |0 = The output of SUSCON pin is low.
+ * | | |1 = The output of SUSCON pin is high.
+ * |[6] |SCTLOEN |Suspend Or Control Pin Output Enable Bit
+ * | | |0 = The SUSCON pin in input.
+ * | | |1 = The output enable is active on the SUSCON pin.
+ * |[7] |BUSEN |BUS Enable Bit
+ * | | |0 = The system management function is Disabled.
+ * | | |1 = The system management function is Enable.
+ * | | |Note: When the bit is enabled, the internal 14-bit counter is used to calculate the time out event of clock low condition.
+ * |[8] |PECTXEN |Packet Error Checking Byte Transmission/Reception
+ * | | |This bit is set by software, and cleared by hardware when the PEC is transferred, or when a STOP condition or an Address Matched is received
+ * | | |0 = No PEC transfer.
+ * | | |1 = PEC transmission/reception is requested.
+ * | | |Note: 1.This bit has no effect in slave mode when ACKMEN =0.
+ * |[9] |TIDLE |Timer Check In Idle State
+ * | | |The BUSTOUT is used to calculate the time-out of clock low in bus active and the idle period in bus Idle.
+ * | | |This bit is used to define which condition is enabled.
+ * | | |0 = The BUSTOUT is used to calculate the clock low period in bus active.
+ * | | |1 = The BUSTOUT is used to calculate the IDLE period in bus Idle.
+ * | | |Note: The BUSY (I2C_BUSSTS[0]) indicate the current bus state.
+ * |[10] |PECCLR |PEC Clear At Repeat Start
+ * | | |The calculation of PEC starts when PECEN is set to 1 and it is clear when the STA or STO bit is detected.
+ * | | |This PECCLR bit is used to enable the condition of REPEAT START can clear the PEC calculation.
+ * | | |0 = The PEC calculation is cleared by "Repeat Start" function is Disabled.
+ * | | |1 = The PEC calculation is cleared by "Repeat Start" function is Enabled.
+ * |[11] |ACKM9SI |Acknowledge Manual Enable Extra SI Interrupt
+ * | | |0 = There is no SI interrupt in the 9th clock cycle when the BUSEN =1 and ACKMEN =1.
+ * | | |1 = There is SI interrupt in the 9th clock cycle when the BUSEN =1 and ACKMEN =1.
+ * @var I2C_T::BUSTCTL
+ * Offset: 0x48 I2C Bus Management Timer Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |BUSTOEN |Bus Time Out Enable Bit
+ * | | |0 = Indicates the bus clock low time-out detection is Disabled.
+ * | | |1 = Indicates the bus clock low time-out detection is Enabled
+ * | | |bus clock is low for more than Time-out (in BIDLE=0) or high more than Time-out(in BIDLE =1),
+ * |[1] |CLKTOEN |Cumulative Clock Low Time Out Enable Bit
+ * | | |0 = Indicates the cumulative clock low time-out detection is Disabled.
+ * | | |1 = Indicates the cumulative clock low time-out detection is Enabled.
+ * | | |For Master, it calculates the period from START to ACK
+ * | | |For Slave, it calculates the period from START to STOP
+ * |[2] |BUSTOIEN |Time-Out Interrupt Enable Bit
+ * | | |BUSY =1.
+ * | | |0 = Indicates the SCLK low time-out interrupt is Disabled.
+ * | | |1 = Indicates the SCLK low time-out interrupt is Enabled.
+ * | | |BUSY =0.
+ * | | |0 = Indicates the bus IDLE time-out interrupt is Disabled.
+ * | | |1 = Indicates the bus IDLE time-out interrupt is Enabled.
+ * |[3] |CLKTOIEN |Extended Clock Time Out Interrupt Enable Bit
+ * | | |0 = Indicates the time extended interrupt is Disabled.
+ * | | |1 = Indicates the time extended interrupt is Enabled.
+ * |[4] |TORSTEN |Time Out Reset Enable Bit
+ * | | |0 = Indicates the I2C state machine reset is Disable.
+ * | | |1 = Indicates the I2C state machine reset is Enable. (The clock and data bus will be released to high)
+ * |[5] |PECIEN |Packet Error Checking Byte Count Done Interrupt Enable Bit
+ * | | |0 = Indicates the byte count done interrupt is Disabled.
+ * | | |1 = Indicates the byte count done interrupt is Enabled.
+ * | | |Note: This bit is used in PECEN =1.
+ * @var I2C_T::BUSSTS
+ * Offset: 0x4C I2C Bus Management Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |BUSY |Bus Busy
+ * | | |Indicates that a communication is in progress on the bus.
+ * | | |It is set by hardware when a START condition is detected.
+ * | | |It is cleared by hardware when a STOP condition is detected.
+ * | | |0 = The bus is IDLE (both SCLK and SDA High).
+ * | | |1 = The bus is busy.
+ * |[1] |BCDONE |Byte Count Transmission/Receive Done
+ * | | |0 = Indicates the transmission/ receive is not finished when the PECEN is set.
+ * | | |1 = Indicates the transmission/ receive is finished when the PECEN is set.
+ * | | |Note: Software can write 1 to clear this bit.
+ * |[2] |PECERR |PEC Error In Reception
+ * | | |0 = Indicates the PEC value equal the received PEC data packet.
+ * | | |1 = Indicates the PEC value doesn't match the receive PEC data packet.
+ * | | |Note: Software can write 1 to clear this bit.
+ * |[3] |ALERT |SMBus Alert Status
+ * | | |Device Mode (BMHEN =0).
+ * | | |0 = Indicates SMALERT pin state is low.
+ * | | |1 = Indicates SMALERT pin state is high
+ * | | |Host Mode (BMHEN =1).
+ * | | |0 = No SMBALERT event.
+ * | | |1 = Indicates there is SMBALERT event (falling edge) is detected in SMALERT pin when the BMHEN = 1 (SMBus host configuration) and the ALERTEN = 1.
+ * | | |Note: 1.
+ * | | |The SMALERT pin is an open-drain pin, the pull-high resistor is must in the system.
+ * | | |2.
+ * | | |Software can write 1 to clear this bit.
+ * |[4] |SCTLDIN |Bus Suspend Or Control Signal Input Status
+ * | | |0 = The input status of SUSCON pin is 0.
+ * | | |1 = The input status of SUSCON pin is 1.
+ * |[5] |BUSTO |Bus Time-out Status
+ * | | |0 = Indicates that there is no any time-out or external clock time-out.
+ * | | |1 = Indicates that a time-out or external clock time-out occurred.
+ * | | |In bus busy, the bit indicates the total clock low time-out event occurred otherwise, it indicates the bus idle time-out event occurred.
+ * | | |Note: Software can write 1 to clear this bit.
+ * |[6] |CLKTO |Clock Low Cumulate Time-out Status
+ * | | |0 = Indicates that the cumulative clock low is no any time-out.
+ * | | |1 = Indicates that the cumulative clock low time-out occurred.
+ * | | |Note: Software can write 1 to clear this bit.
+ * @var I2C_T::PKTSIZE
+ * Offset: 0x50 I2C Packet Error Checking Byte Number Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:0] |PLDSIZE |Transfer Byte Number
+ * | | |The transmission or receive byte number in one transaction when the PECEN is set.
+ * | | |The maximum transaction or receive byte is 255 Bytes.
+ * @var I2C_T::PKTCRC
+ * Offset: 0x54 I2C Packet Error Checking Byte Value Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:0] |PECCRC |Packet Error Checking Byte Value
+ * | | |This byte indicates the packet error checking content after transmission or receive byte count by using the C(x) = X8 + X2 + X + 1.
+ * | | |I t is read only.
+ * @var I2C_T::BUSTOUT
+ * Offset: 0x58 I2C Bus Management Timer Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:0] |BUSTO |Bus Management Time-out Value
+ * | | |Indicate the bus time-out value in bus is IDLE or SCLK low.
+ * | | |Note: If the user wants to revise the value of BUSTOUT, the TORSTEN (I2C_BUSTCTL[4]) bit shall be set to 1 and clear to 0 first in the BUSEN(I2C_BUSCTL[7]) is set.
+ * @var I2C_T::CLKTOUT
+ * Offset: 0x5C I2C Bus Management Clock Low Timer Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:0] |CLKTO |Bus Clock Low Timer
+ * | | |The field is used to configure the cumulative clock extension time-out.
+ * | | |Note: If the user wants to revise the value of CLKLTOUT, the TORSTEN bit shall be set to 1 and d clear to 0 first in the BUSEN is set.
+ */
+
+ __IO uint32_t CTL; /* Offset: 0x00 I2C Control Register */
+ __IO uint32_t ADDR0; /* Offset: 0x04 I2C Slave Address Register0 */
+ __IO uint32_t DAT; /* Offset: 0x08 I2C Data Register */
+ __I uint32_t STATUS; /* Offset: 0x0C I2C Status Register */
+ __IO uint32_t CLKDIV; /* Offset: 0x10 I2C Clock Divided Register */
+ __IO uint32_t TOCTL; /* Offset: 0x14 I2C Time-out Control Register */
+ __IO uint32_t ADDR1; /* Offset: 0x18 I2C Slave Address Register1 */
+ __IO uint32_t ADDR2; /* Offset: 0x1C I2C Slave Address Register2 */
+ __IO uint32_t ADDR3; /* Offset: 0x20 I2C Slave Address Register3 */
+ __IO uint32_t ADDRMSK0; /* Offset: 0x24 I2C Slave Address Mask Register0 */
+ __IO uint32_t ADDRMSK1; /* Offset: 0x28 I2C Slave Address Mask Register1 */
+ __IO uint32_t ADDRMSK2; /* Offset: 0x2C I2C Slave Address Mask Register2 */
+ __IO uint32_t ADDRMSK3; /* Offset: 0x30 I2C Slave Address Mask Register3 */
+ __I uint32_t RESERVE0[2];
+ __IO uint32_t WKCTL; /* Offset: 0x3C I2C Wake-up Control Register */
+ __IO uint32_t WKSTS; /* Offset: 0x40 I2C Wake-up Status Register */
+ __IO uint32_t BUSCTL; /* Offset: 0x44 I2C Bus Management Control Register */
+ __IO uint32_t BUSTCTL; /* Offset: 0x48 I2C Bus Management Timer Control Register */
+ __IO uint32_t BUSSTS; /* Offset: 0x4C I2C Bus Management Status Register */
+ __IO uint32_t PKTSIZE; /* Offset: 0x50 I2C Packet Error Checking Byte Number Register */
+ __I uint32_t PKTCRC; /* Offset: 0x54 I2C Packet Error Checking Byte Value Register */
+ __IO uint32_t BUSTOUT; /* Offset: 0x58 I2C Bus Management Timer Register */
+ __IO uint32_t CLKTOUT; /* Offset: 0x5C I2C Bus Management Clock Low Timer Register */
+
+} I2C_T;
+
+
+
+/**
+ @addtogroup I2C_CONST I2C Bit Field Definition
+ Constant Definitions for I2C Controller
+@{ */
+
+#define I2C_CTL_AA_Pos (2) /*!< I2C_T::CTL: AA Position */
+#define I2C_CTL_AA_Msk (0x1ul << I2C_CTL_AA_Pos) /*!< I2C_T::CTL: AA Mask */
+
+#define I2C_CTL_SI_Pos (3) /*!< I2C_T::CTL: SI Position */
+#define I2C_CTL_SI_Msk (0x1ul << I2C_CTL_SI_Pos) /*!< I2C_T::CTL: SI Mask */
+
+#define I2C_CTL_STO_Pos (4) /*!< I2C_T::CTL: STO Position */
+#define I2C_CTL_STO_Msk (0x1ul << I2C_CTL_STO_Pos) /*!< I2C_T::CTL: STO Mask */
+
+#define I2C_CTL_STA_Pos (5) /*!< I2C_T::CTL: STA Position */
+#define I2C_CTL_STA_Msk (0x1ul << I2C_CTL_STA_Pos) /*!< I2C_T::CTL: STA Mask */
+
+#define I2C_CTL_I2CEN_Pos (6) /*!< I2C_T::CTL: I2CEN Position */
+#define I2C_CTL_I2CEN_Msk (0x1ul << I2C_CTL_I2CEN_Pos) /*!< I2C_T::CTL: I2CEN Mask */
+
+#define I2C_CTL_INTEN_Pos (7) /*!< I2C_T::CTL: INTEN Position */
+#define I2C_CTL_INTEN_Msk (0x1ul << I2C_CTL_INTEN_Pos) /*!< I2C_T::CTL: INTEN Mask */
+
+#define I2C_ADDR0_GC_Pos (0) /*!< I2C_T::ADDR0: GC Position */
+#define I2C_ADDR0_GC_Msk (0x1ul << I2C_ADDR0_GC_Pos) /*!< I2C_T::ADDR0: GC Mask */
+
+#define I2C_ADDR0_ADDR_Pos (1) /*!< I2C_T::ADDR0: ADDR Position */
+#define I2C_ADDR0_ADDR_Msk (0x7ful << I2C_ADDR0_ADDR_Pos) /*!< I2C_T::ADDR0: ADDR Mask */
+
+#define I2C_DAT_DAT_Pos (0) /*!< I2C_T::DAT: DAT Position */
+#define I2C_DAT_DAT_Msk (0xfful << I2C_DAT_DAT_Pos) /*!< I2C_T::DAT: DAT Mask */
+
+#define I2C_STATUS_STATUS_Pos (0) /*!< I2C_T::STATUS: STATUS Position */
+#define I2C_STATUS_STATUS_Msk (0xfful << I2C_STATUS_STATUS_Pos) /*!< I2C_T::STATUS: STATUS Mask */
+
+#define I2C_CLKDIV_DIVIDER_Pos (0) /*!< I2C_T::CLKDIV: DIVIDER Position */
+#define I2C_CLKDIV_DIVIDER_Msk (0xfful << I2C_CLKDIV_DIVIDER_Pos) /*!< I2C_T::CLKDIV: DIVIDER Mask */
+
+#define I2C_TOCTL_TOIF_Pos (0) /*!< I2C_T::TOCTL: TOIF Position */
+#define I2C_TOCTL_TOIF_Msk (0x1ul << I2C_TOCTL_TOIF_Pos) /*!< I2C_T::TOCTL: TOIF Mask */
+
+#define I2C_TOCTL_TOCDIV4_Pos (1) /*!< I2C_T::TOCTL: TOCDIV4 Position */
+#define I2C_TOCTL_TOCDIV4_Msk (0x1ul << I2C_TOCTL_TOCDIV4_Pos) /*!< I2C_T::TOCTL: TOCDIV4 Mask */
+
+#define I2C_TOCTL_TOCEN_Pos (2) /*!< I2C_T::TOCTL: TOCEN Position */
+#define I2C_TOCTL_TOCEN_Msk (0x1ul << I2C_TOCTL_TOCEN_Pos) /*!< I2C_T::TOCTL: TOCEN Mask */
+
+#define I2C_ADDR1_GC_Pos (0) /*!< I2C_T::ADDR1: GC Position */
+#define I2C_ADDR1_GC_Msk (0x1ul << I2C_ADDR1_GC_Pos) /*!< I2C_T::ADDR1: GC Mask */
+
+#define I2C_ADDR1_ADDR_Pos (1) /*!< I2C_T::ADDR1: ADDR Position */
+#define I2C_ADDR1_ADDR_Msk (0x7ful << I2C_ADDR1_ADDR_Pos) /*!< I2C_T::ADDR1: ADDR Mask */
+
+#define I2C_ADDR2_GC_Pos (0) /*!< I2C_T::ADDR2: GC Position */
+#define I2C_ADDR2_GC_Msk (0x1ul << I2C_ADDR2_GC_Pos) /*!< I2C_T::ADDR2: GC Mask */
+
+#define I2C_ADDR2_ADDR_Pos (1) /*!< I2C_T::ADDR2: ADDR Position */
+#define I2C_ADDR2_ADDR_Msk (0x7ful << I2C_ADDR2_ADDR_Pos) /*!< I2C_T::ADDR2: ADDR Mask */
+
+#define I2C_ADDR3_GC_Pos (0) /*!< I2C_T::ADDR3: GC Position */
+#define I2C_ADDR3_GC_Msk (0x1ul << I2C_ADDR3_GC_Pos) /*!< I2C_T::ADDR3: GC Mask */
+
+#define I2C_ADDR3_ADDR_Pos (1) /*!< I2C_T::ADDR3: ADDR Position */
+#define I2C_ADDR3_ADDR_Msk (0x7ful << I2C_ADDR3_ADDR_Pos) /*!< I2C_T::ADDR3: ADDR Mask */
+
+#define I2C_ADDRMSK0_ADDRMSK_Pos (1) /*!< I2C_T::ADDRMSK0: ADDRMSK Position */
+#define I2C_ADDRMSK0_ADDRMSK_Msk (0x7ful << I2C_ADDRMSK0_ADDRMSK_Pos) /*!< I2C_T::ADDRMSK0: ADDRMSK Mask */
+
+#define I2C_ADDRMSK1_ADDRMSK_Pos (1) /*!< I2C_T::ADDRMSK1: ADDRMSK Position */
+#define I2C_ADDRMSK1_ADDRMSK_Msk (0x7ful << I2C_ADDRMSK1_ADDRMSK_Pos) /*!< I2C_T::ADDRMSK1: ADDRMSK Mask */
+
+#define I2C_ADDRMSK2_ADDRMSK_Pos (1) /*!< I2C_T::ADDRMSK2: ADDRMSK Position */
+#define I2C_ADDRMSK2_ADDRMSK_Msk (0x7ful << I2C_ADDRMSK2_ADDRMSK_Pos) /*!< I2C_T::ADDRMSK2: ADDRMSK Mask */
+
+#define I2C_ADDRMSK3_ADDRMSK_Pos (1) /*!< I2C_T::ADDRMSK3: ADDRMSK Position */
+#define I2C_ADDRMSK3_ADDRMSK_Msk (0x7ful << I2C_ADDRMSK3_ADDRMSK_Pos) /*!< I2C_T::ADDRMSK3: ADDRMSK Mask */
+
+#define I2C_WKCTL_WKEN_Pos (0) /*!< I2C_T::WKCTL: WKEN Position */
+#define I2C_WKCTL_WKEN_Msk (0x1ul << I2C_WKCTL_WKEN_Pos) /*!< I2C_T::WKCTL: WKEN Mask */
+
+#define I2C_WKSTS_WKIF_Pos (0) /*!< I2C_T::WKSTS: WKIF Position */
+#define I2C_WKSTS_WKIF_Msk (0x1ul << I2C_WKSTS_WKIF_Pos) /*!< I2C_T::WKSTS: WKIF Mask */
+
+#define I2C_BUSCTL_ACKMEN_Pos (0) /*!< I2C_T::BUSCTL: ACKMEN Position */
+#define I2C_BUSCTL_ACKMEN_Msk (0x1ul << I2C_BUSCTL_ACKMEN_Pos) /*!< I2C_T::BUSCTL: ACKMEN Mask */
+
+#define I2C_BUSCTL_PECEN_Pos (1) /*!< I2C_T::BUSCTL: PECEN Position */
+#define I2C_BUSCTL_PECEN_Msk (0x1ul << I2C_BUSCTL_PECEN_Pos) /*!< I2C_T::BUSCTL: PECEN Mask */
+
+#define I2C_BUSCTL_BMDEN_Pos (2) /*!< I2C_T::BUSCTL: BMDEN Position */
+#define I2C_BUSCTL_BMDEN_Msk (0x1ul << I2C_BUSCTL_BMDEN_Pos) /*!< I2C_T::BUSCTL: BMDEN Mask */
+
+#define I2C_BUSCTL_BMHEN_Pos (3) /*!< I2C_T::BUSCTL: BMHEN Position */
+#define I2C_BUSCTL_BMHEN_Msk (0x1ul << I2C_BUSCTL_BMHEN_Pos) /*!< I2C_T::BUSCTL: BMHEN Mask */
+
+#define I2C_BUSCTL_ALERTEN_Pos (4) /*!< I2C_T::BUSCTL: ALERTEN Position */
+#define I2C_BUSCTL_ALERTEN_Msk (0x1ul << I2C_BUSCTL_ALERTEN_Pos) /*!< I2C_T::BUSCTL: ALERTEN Mask */
+
+#define I2C_BUSCTL_SCTLOSTS_Pos (5) /*!< I2C_T::BUSCTL: SCTLOSTS Position */
+#define I2C_BUSCTL_SCTLOSTS_Msk (0x1ul << I2C_BUSCTL_SCTLOSTS_Pos) /*!< I2C_T::BUSCTL: SCTLOSTS Mask */
+
+#define I2C_BUSCTL_SCTLOEN_Pos (6) /*!< I2C_T::BUSCTL: SCTLOEN Position */
+#define I2C_BUSCTL_SCTLOEN_Msk (0x1ul << I2C_BUSCTL_SCTLOEN_Pos) /*!< I2C_T::BUSCTL: SCTLOEN Mask */
+
+#define I2C_BUSCTL_BUSEN_Pos (7) /*!< I2C_T::BUSCTL: BUSEN Position */
+#define I2C_BUSCTL_BUSEN_Msk (0x1ul << I2C_BUSCTL_BUSEN_Pos) /*!< I2C_T::BUSCTL: BUSEN Mask */
+
+#define I2C_BUSCTL_PECTXEN_Pos (8) /*!< I2C_T::BUSCTL: PECTXEN Position */
+#define I2C_BUSCTL_PECTXEN_Msk (0x1ul << I2C_BUSCTL_PECTXEN_Pos) /*!< I2C_T::BUSCTL: PECTXEN Mask */
+
+#define I2C_BUSCTL_TIDLE_Pos (9) /*!< I2C_T::BUSCTL: TIDLE Position */
+#define I2C_BUSCTL_TIDLE_Msk (0x1ul << I2C_BUSCTL_TIDLE_Pos) /*!< I2C_T::BUSCTL: TIDLE Mask */
+
+#define I2C_BUSCTL_PECCLR_Pos (10) /*!< I2C_T::BUSCTL: PECCLR Position */
+#define I2C_BUSCTL_PECCLR_Msk (0x1ul << I2C_BUSCTL_PECCLR_Pos) /*!< I2C_T::BUSCTL: PECCLR Mask */
+
+#define I2C_BUSCTL_ACKM9SI_Pos (11) /*!< I2C_T::BUSCTL: ACKM9SI Position */
+#define I2C_BUSCTL_ACKM9SI_Msk (0x1ul << I2C_BUSCTL_ACKM9SI_Pos) /*!< I2C_T::BUSCTL: ACKM9SI Mask */
+
+#define I2C_BUSTCTL_BUSTOEN_Pos (0) /*!< I2C_T::BUSTCTL: BUSTOEN Position */
+#define I2C_BUSTCTL_BUSTOEN_Msk (0x1ul << I2C_BUSTCTL_BUSTOEN_Pos) /*!< I2C_T::BUSTCTL: BUSTOEN Mask */
+
+#define I2C_BUSTCTL_CLKTOEN_Pos (1) /*!< I2C_T::BUSTCTL: CLKTOEN Position */
+#define I2C_BUSTCTL_CLKTOEN_Msk (0x1ul << I2C_BUSTCTL_CLKTOEN_Pos) /*!< I2C_T::BUSTCTL: CLKTOEN Mask */
+
+#define I2C_BUSTCTL_BUSTOIEN_Pos (2) /*!< I2C_T::BUSTCTL: BUSTOIEN Position */
+#define I2C_BUSTCTL_BUSTOIEN_Msk (0x1ul << I2C_BUSTCTL_BUSTOIEN_Pos) /*!< I2C_T::BUSTCTL: BUSTOIEN Mask */
+
+#define I2C_BUSTCTL_CLKTOIEN_Pos (3) /*!< I2C_T::BUSTCTL: CLKTOIEN Position */
+#define I2C_BUSTCTL_CLKTOIEN_Msk (0x1ul << I2C_BUSTCTL_CLKTOIEN_Pos) /*!< I2C_T::BUSTCTL: CLKTOIEN Mask */
+
+#define I2C_BUSTCTL_TORSTEN_Pos (4) /*!< I2C_T::BUSTCTL: TORSTEN Position */
+#define I2C_BUSTCTL_TORSTEN_Msk (0x1ul << I2C_BUSTCTL_TORSTEN_Pos) /*!< I2C_T::BUSTCTL: TORSTEN Mask */
+
+#define I2C_BUSTCTL_PECIEN_Pos (5) /*!< I2C_T::BUSTCTL: PECIEN Position */
+#define I2C_BUSTCTL_PECIEN_Msk (0x1ul << I2C_BUSTCTL_PECIEN_Pos) /*!< I2C_T::BUSTCTL: PECIEN Mask */
+
+#define I2C_BUSSTS_BUSY_Pos (0) /*!< I2C_T::BUSSTS: BUSY Position */
+#define I2C_BUSSTS_BUSY_Msk (0x1ul << I2C_BUSSTS_BUSY_Pos) /*!< I2C_T::BUSSTS: BUSY Mask */
+
+#define I2C_BUSSTS_BCDONE_Pos (1) /*!< I2C_T::BUSSTS: BCDONE Position */
+#define I2C_BUSSTS_BCDONE_Msk (0x1ul << I2C_BUSSTS_BCDONE_Pos) /*!< I2C_T::BUSSTS: BCDONE Mask */
+
+#define I2C_BUSSTS_PECERR_Pos (2) /*!< I2C_T::BUSSTS: PECERR Position */
+#define I2C_BUSSTS_PECERR_Msk (0x1ul << I2C_BUSSTS_PECERR_Pos) /*!< I2C_T::BUSSTS: PECERR Mask */
+
+#define I2C_BUSSTS_ALERT_Pos (3) /*!< I2C_T::BUSSTS: ALERT Position */
+#define I2C_BUSSTS_ALERT_Msk (0x1ul << I2C_BUSSTS_ALERT_Pos) /*!< I2C_T::BUSSTS: ALERT Mask */
+
+#define I2C_BUSSTS_SCTLDIN_Pos (4) /*!< I2C_T::BUSSTS: SCTLDIN Position */
+#define I2C_BUSSTS_SCTLDIN_Msk (0x1ul << I2C_BUSSTS_SCTLDIN_Pos) /*!< I2C_T::BUSSTS: SCTLDIN Mask */
+
+#define I2C_BUSSTS_BUSTO_Pos (5) /*!< I2C_T::BUSSTS: BUSTO Position */
+#define I2C_BUSSTS_BUSTO_Msk (0x1ul << I2C_BUSSTS_BUSTO_Pos) /*!< I2C_T::BUSSTS: BUSTO Mask */
+
+#define I2C_BUSSTS_CLKTO_Pos (6) /*!< I2C_T::BUSSTS: CLKTO Position */
+#define I2C_BUSSTS_CLKTO_Msk (0x1ul << I2C_BUSSTS_CLKTO_Pos) /*!< I2C_T::BUSSTS: CLKTO Mask */
+
+#define I2C_PKTSIZE_PLDSIZE_Pos (0) /*!< I2C_T::PKTSIZE: PLDSIZE Position */
+#define I2C_PKTSIZE_PLDSIZE_Msk (0xfful << I2C_PKTSIZE_PLDSIZE_Pos) /*!< I2C_T::PKTSIZE: PLDSIZE Mask */
+
+#define I2C_PKTCRC_PECCRC_Pos (0) /*!< I2C_T::PKTCRC: PECCRC Position */
+#define I2C_PKTCRC_PECCRC_Msk (0xfful << I2C_PKTCRC_PECCRC_Pos) /*!< I2C_T::PKTCRC: PECCRC Mask */
+
+#define I2C_BUSTOUT_BUSTO_Pos (0) /*!< I2C_T::BUSTOUT: BUSTO Position */
+#define I2C_BUSTOUT_BUSTO_Msk (0xfful << I2C_BUSTOUT_BUSTO_Pos) /*!< I2C_T::BUSTOUT: BUSTO Mask */
+
+#define I2C_CLKTOUT_CLKTO_Pos (0) /*!< I2C_T::CLKTOUT: CLKTO Position */
+#define I2C_CLKTOUT_CLKTO_Msk (0xfful << I2C_CLKTOUT_CLKTO_Pos) /*!< I2C_T::CLKTOUT: CLKTO Mask */
+
+
+/**@}*/ /* I2C_CONST */
+/**@}*/ /* end of I2C register group */
+
+/*---------------------- USB On-The-Go Controller -------------------------*/
+/**
+ @addtogroup OTG USB On-The-Go Controller(OTG)
+ Memory Mapped Structure for OTG Controller
+@{ */
+
+
+typedef struct
+{
+
+
+/**
+ * @var OTG_T::CTL
+ * Offset: 0x00 OTG Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |VBUSDROP |Drop VBUS Control
+ * | | |If user application running on this OTG A-device wants to conserve power, set this bit to drop VBUS.
+ * | | |BUSREQ (OTG_CTL[1]) will be also cleared no matter A-device or B-device.
+ * | | |0 = Not drop the VBUS.
+ * | | |1 = Drop the VBUS.
+ * |[1] |BUSREQ |OTG Bus Request
+ * | | |If OTG A-device wants to do data transfers via USB bus, setting this bit will drive VBUS high to detect USB device connection.
+ * | | |If user won't use the bus any more, clearing this bit will drop VBUS to save power.
+ * | | |This bit will be cleared when A-device goes to A_wait_vfall state. A_wait_vfall state is defined in OTG specification.
+ * | | |This bit will be also cleared if VBUSDROP (OTG_CTL[0]) bit is set or IDSTS (OTG_STATUS[1]) changed.
+ * | | |If user of an OTG-B Device wants to request VBUS, setting this bit will run SRP protocol.
+ * | | |This bit will be cleared if SRP failure (OTG A-device does not provide VBUS after B-device issues ARP in specified interval, defined in OTG specification).
+ * | | |This bit will be also cleared if VBUSDROP (OTG_CTL[0]) bit is set IDSTS (OTG_STATUS[1]) changed.
+ * | | |0 = Not launch VBUS in OTG A-device or not request SRP in OTG B-device.
+ * | | |1 = Launch VBUS in OTG A-device or request SRP in OTG B-device.
+ * |[2] |HNPREQEN |OTG HNP Request Enable Bit
+ * | | |When USB frame as A-device, set this bit when A-device allows to process Host Negotiation Protocol.
+ * | | |This bit will be cleared when OTG state changes from a_suspend to a_peripheral or goes back to a_idle state.
+ * | | |When USB frame is as B-device, set this bit after the OTG A-device successfully sends a SetFeature (b_hnp_enable) command to the OTG B-device to start role change.
+ * | | |This bit will be cleared when OTG state changes from b_peripheral to b_wait_acon or goes back to b_idle state.
+ * | | |0 = HNP request Disabled.
+ * | | |1 = HNP request Enabled (A-device can change role from Host to Peripheral or B-device can change role from Peripheral to Host).
+ * | | |Note: Refer to OTG specification to get a_suspend, a_peripheral, a_idle and b_idle state.
+ * |[4] |OTGEN |OTG Function Enable Bit
+ * | | |User needs to set this bit to enable OTG function while USB frame configured as OTG device.
+ * | | |When USB frame not configured as OTG device, this bit is must be low.
+ * | | |0 = OTG function Disabled.
+ * | | |1 = OTG function Enabled.
+ * |[5] |WKEN |OTG ID Pin Wake-Up Enable Bit
+ * | | |0 = OTG ID pin status change wake-up function Disabled.
+ * | | |1 = OTG ID pin status change wake-up function Enabled.
+ * @var OTG_T::PHYCTL
+ * Offset: 0x04 OTG PHY Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |OTGPHYEN |OTG PHY Enable
+ * | | |When USB frame is configured as OTG-device, user needs to set this bit before using OTG function.
+ * | | |If device is not configured as OTG-device, this bit is "don't care".
+ * | | |0 = OTG PHY Disabled.
+ * | | |1 = OTG PHY Enabled.
+ * |[1] |IDDETEN |ID Detection Enable Bit
+ * | | |0 = Detect ID pin status Disabled.
+ * | | |1 = Detect ID pin status Enabled.
+ * |[4] |VBENPOL |Off-Chip USB VBUS Power Switch Enable Polarity
+ * | | |The OTG controller will enable off-chip USB VBUS power switch to provide VBUS power when need.
+ * | | |A USB_VBUS_EN pin is used to control the off-chip USB VBUS power switch.
+ * | | |The polarity of enabling off-chip USB VBUS power switch (high active or low active) depends on the selected component.
+ * | | |Set this bit as following according to the polarity of off-chip USB VBUS power switch.
+ * | | |0 = The off-chip USB VBUS power switch enable is active high.
+ * | | |1 = The off-chip USB VBUS power switch enable is active low.
+ * |[5] |VBSTSPOL |Off-Chip USB VBUS Power Switch Status Polarity
+ * | | |The polarity of off-chip USB VBUS power switch valid signal depends on the selected component.
+ * | | |A USB_VBUS_ST pin is used to monitor the valid signal of the off-chip USB VBUS power switch.
+ * | | |Set this bit as following according to the polarity of off-chip USB VBUS power switch.
+ * | | |0 = The polarity of off-chip USB VBUS power switch valid status is high.
+ * | | |1 = The polarity of off-chip USB VBUS power switch valid status is low.
+ * @var OTG_T::INTEN
+ * Offset: 0x08 OTG Interrupt Enable Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |ROLECHGIEN|Role (Host Or Peripheral) Changed Interrupt Enable Bit
+ * | | |0 = Interrupt Disabled.
+ * | | |1 = Interrupt Enabled.
+ * |[1] |VBEIEN |VBUS Error Interrupt Enable Bit
+ * | | |0 = Interrupt Disabled.
+ * | | |1 = Interrupt Enabled.
+ * | | |Note: VBUS error means going to a_vbus_err state. Please refer to A-device state diagram in OTG spec.
+ * |[2] |SRPFIEN |SRP Fail Interrupt Enable Bit
+ * | | |0 = Interrupt Disabled.
+ * | | |1 = Interrupt Enabled.
+ * |[3] |HNPFIEN |HNP Fail Interrupt Enable Bit
+ * | | |0 = Interrupt Disabled.
+ * | | |1 = Interrupt Enabled.
+ * |[4] |GOIDLEIEN |OTG Device Goes to IDLE State Interrupt Enable Bit
+ * | | |0 = Interrupt Disabled.
+ * | | |1 = Interrupt Enabled.
+ * | | |Note: Going to idle state means going to a_idle or b_idle state.
+ * | | |Please refer to A-device state diagram and B-device state diagram in OTG spec.
+ * |[5] |IDCHGIEN |IDSTS Changed Interrupt Enable Bit
+ * | | |If this bit is set to 1 and IDSTS (OTG_STATUS[1]) status is changed from high to low or from low to high, a interrupt will be asserted.
+ * | | |0 = Interrupt Disabled.
+ * | | |1 = Interrupt Enabled.
+ * |[6] |PDEVIEN |Act As Peripheral Interrupt Enable Bit
+ * | | |If this bit is set to 1 and the device is changed as a peripheral, a interrupt will be asserted.
+ * | | |0 = This device as a peripheral interrupt Disabled.
+ * | | |1 = This device as a peripheral interrupt Enabled.
+ * |[7] |HOSTIEN |Act As Host Interrupt Enable Bit
+ * | | |If this bit is set to 1 and the device is changed as a host, a interrupt will be asserted.
+ * | | |0 = This device as a host interrupt Disabled.
+ * | | |1 = This device as a host interrupt Enabled.
+ * |[8] |BVLDCHGIEN|B-Device Session Valid Status Changed Interrupt Enable Bit
+ * | | |If this bit is set to 1 and BVLD (OTG_STATUS[3]) status is changed from high to low or from low to high, a interrupt will be asserted.
+ * | | |0 = Interrupt Disabled.
+ * | | |1 = Interrupt Enabled.
+ * |[9] |AVLDCHGIEN|A-Device Session Valid Status Changed Interrupt Enable Bit
+ * | | |If this bit is set to 1 and AVLD (OTG_STATUS[4]) status is changed from high to low or from low to high, a interrupt will be asserted.
+ * | | |0 = Interrupt Disabled.
+ * | | |1 = Interrupt Enabled.
+ * |[10] |VBCHGIEN |VBUSVLD Status Changed
+ * | | |Interrupt Enable Bit
+ * | | |If this bit is set to 1 and VBUSVLD (OTG_STATUS[5]) status is changed from high to low or from low to high, a interrupt will be asserted.
+ * | | |0 = Interrupt Disabled.
+ * | | |1 = Interrupt Enabled.
+ * |[11] |SECHGIEN |SESSEND Status Changed Interrupt Enable Bit
+ * | | |If this bit is set to 1 and SESSEND (OTG_STATUS[2]) status is changed from high to low or from low to high, a interrupt will be asserted.
+ * | | |0 = Interrupt Disabled.
+ * | | |1 = Interrupt Enabled.
+ * |[13] |SRPDETIEN |SRP Detected Interrupt Enable Bit
+ * | | |0 = Interrupt Disabled.
+ * | | |1 = Interrupt Enabled.
+ * @var OTG_T::INTSTS
+ * Offset: 0x0C OTG Interrupt Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |ROLECHGIF |OTG Role Change Interrupt Status
+ * | | |This flag is set when the role of an OTG device changed from a host to a peripheral, or changed from a peripheral to a host while USB_ID pin status does not change.
+ * | | |0 = OTG device role not changed.
+ * | | |1 = OTG device role changed.
+ * | | |Note: Write 1 to clear this flag.
+ * |[1] |VBEIF |VBUS Error Interrupt Status
+ * | | |This bit will be set when voltage on VBUS cannot reach a minimum valid threshold 4.4V within a maximum time of 100ms after OTG A-device starting to drive VBUS high.
+ * | | |0 = OTG A-device drives VBUS over threshold voltage before this interval expires.
+ * | | |1 = OTG A-device cannot drive VBUS over threshold voltage before this interval expires.
+ * | | |Note: Write 1 to clear this flag and recover from the VBUS error state.
+ * |[2] |SRPFIF |SRP Fail Interrupt Status
+ * | | |After initiating SRP, an OTG B-device will wait for the OTG A-device to drive VBUS high at least TB_SRP_FAIL minimum, defined in OTG specification.
+ * | | |This flag is set when the OTG B-device does not get VBUS high after this interval.
+ * | | |0 = OTG B-device gets VBUS high before this interval.
+ * | | |1 = OTG B-device does not get VBUS high before this interval.
+ * | | |Note: Write 1 to clear this flag.
+ * |[3] |HNPFIF |HNP Fail Interrupt Status
+ * | | |When A-device has granted B-device to be host and USB bus is in SE0 (both USB_D+ and USB_D- low) state, this bit will be set when A-device does not connect after specified interval expires.
+ * | | |0 = A-device connects to B-device before specified interval expires.
+ * | | |1 = A-device does not connect to B-device before specified interval expires.
+ * | | |Note: Write 1 to clear this flag.
+ * |[4] |GOIDLEIF |OTG Device Goes to IDLE Interrupt Status
+ * | | |Flag is set if the OTG device transfers from non-idle state to idle state.
+ * | | |The OTG device will be neither a host nor a peripheral.
+ * | | |0 = OTG device does not go back to idle state (a_idle or b_idle).
+ * | | |1 = OTG device goes back to idle state (a_idle or b_idle).
+ * | | |Note 1: Going to idle state means going to a_idle or b_idle state. Please refer to OTG specification for the details of a_idle state and b_idle state.
+ * | | |Note 2: Write 1 to clear this flag.
+ * |[5] |IDCHGIF |ID State Change Interrupt Status
+ * | | |0 = IDSTS (OTG_STATUS[1]) not toggled.
+ * | | |1 = IDSTS (OTG_STATUS[1]) from high to low or from low to high.
+ * | | |Note: Write 1 to clear this flag.
+ * |[6] |PDEVIF |Act As Peripheral Interrupt Status
+ * | | |0 = This device does not act as a peripheral.
+ * | | |1 = This device acts as a peripheral.
+ * | | |Note: Write 1 to clear this flag.
+ * |[7] |HOSTIF |Act As Host Interrupt Status
+ * | | |0 = This device does not act as a host.
+ * | | |1 = This device acts as a host.
+ * | | |Note: Write 1 to clear this flag.
+ * |[8] |BVLDCHGIF |B-Device Session Valid State Change Interrupt Status
+ * | | |0 = BVLD (OTG_STATUS[3]) is not toggled.
+ * | | |1 = BVLD (OTG_STATUS[3]) from high to low or low to high.
+ * | | |Note: Write 1 to clear this status.
+ * |[9] |AVLDCHGIF |A-Device Session Valid State Change Interrupt Status
+ * | | |0 = AVLD (OTG_STATUS[4]) not toggled.
+ * | | |1 = AVLD (OTG_STATUS[4]) from high to low or low to high.
+ * | | |Note: Write 1 to clear this status.
+ * |[10] |VBCHGIF |VBUSVLD State Change Interrupt Status
+ * | | |0 = VBUSVLD (OTG_STATUS[5]) not toggled.
+ * | | |1 = VBUSVLD (OTG_STATUS[5]) from high to low or from low to high.
+ * | | |Note: Write 1 to clear this status.
+ * |[11] |SECHGIF |SESSEND State Change Interrupt Status
+ * | | |0 = SESSEND (OTG_STATUS[2]) not toggled.
+ * | | |1 = SESSEND (OTG_STATUS[2]) from high to low or from low to high.
+ * | | |Note: Write 1 to clear this flag.
+ * |[13] |SRPDETIF |SRP Detected Interrupt Status
+ * | | |0 = SRP not detected.
+ * | | |1 = SRP detected.
+ * | | |Note: Write 1 to clear this status.
+ * @var OTG_T::STATUS
+ * Offset: 0x10 OTG Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |OVERCUR |Over Current Condition
+ * | | |The voltage on VBUS cannot reach a minimum VBUS valid threshold, 4.4V minimum, within a maximum time of 100ms after OTG A-device drives VBUS high.
+ * | | |0 = OTG A-device drives VBUS successfully.
+ * | | |1 = OTG A-device cannot drives VBUS high in this interval.
+ * |[1] |IDSTS |USB_ID Pin State Of Mini-B/Micro-Plug
+ * | | |0 = Mini-A/Micro-A plug is attached.
+ * | | |1 = Mini-B/Micro-B plug is attached.
+ * |[2] |SESSEND |Session End Status
+ * | | |When VBUS voltage is lower than 0.4V, this bit will be set to 1.
+ * | | |Session end means no meaningful power on VBUS.
+ * | | |0 = Session is not end.
+ * | | |1 = Session is end.
+ * |[3] |BVLD |B-Device Session Valid Status
+ * | | |0 = B-device session is not valid.
+ * | | |1 = B-device session is valid.
+ * |[4] |AVLD |A-Device Session Valid Status
+ * | | |0 = A-device session is not valid.
+ * | | |1 = A-device session is valid.
+ * |[5] |VBUSVLD |VBUS Valid Status
+ * | | |When VBUS is larger than 4.7V, this bit will be set to 1.
+ * | | |0 = VBUS is not valid.
+ * | | |1 = VBUS is valid.
+ */
+
+ __IO uint32_t CTL; /* Offset: 0x00 OTG Control Register */
+ __IO uint32_t PHYCTL; /* Offset: 0x04 OTG PHY Control Register */
+ __IO uint32_t INTEN; /* Offset: 0x08 OTG Interrupt Enable Register */
+ __IO uint32_t INTSTS; /* Offset: 0x0C OTG Interrupt Status Register */
+ __I uint32_t STATUS; /* Offset: 0x10 OTG Status Register */
+
+} OTG_T;
+
+
+
+/**
+ @addtogroup OTG_CONST OTG Bit Field Definition
+ Constant Definitions for OTG Controller
+@{ */
+
+#define OTG_CTL_VBUSDROP_Pos (0) /*!< OTG_T::CTL: VBUSDROP Position */
+#define OTG_CTL_VBUSDROP_Msk (0x1ul << OTG_CTL_VBUSDROP_Pos) /*!< OTG_T::CTL: VBUSDROP Mask */
+
+#define OTG_CTL_BUSREQ_Pos (1) /*!< OTG_T::CTL: BUSREQ Position */
+#define OTG_CTL_BUSREQ_Msk (0x1ul << OTG_CTL_BUSREQ_Pos) /*!< OTG_T::CTL: BUSREQ Mask */
+
+#define OTG_CTL_HNPREQEN_Pos (2) /*!< OTG_T::CTL: HNPREQEN Position */
+#define OTG_CTL_HNPREQEN_Msk (0x1ul << OTG_CTL_HNPREQEN_Pos) /*!< OTG_T::CTL: HNPREQEN Mask */
+
+#define OTG_CTL_OTGEN_Pos (4) /*!< OTG_T::CTL: OTGEN Position */
+#define OTG_CTL_OTGEN_Msk (0x1ul << OTG_CTL_OTGEN_Pos) /*!< OTG_T::CTL: OTGEN Mask */
+
+#define OTG_CTL_WKEN_Pos (5) /*!< OTG_T::CTL: WKEN Position */
+#define OTG_CTL_WKEN_Msk (0x1ul << OTG_CTL_WKEN_Pos) /*!< OTG_T::CTL: WKEN Mask */
+
+#define OTG_PHYCTL_OTGPHYEN_Pos (0) /*!< OTG_T::PHYCTL: OTGPHYEN Position */
+#define OTG_PHYCTL_OTGPHYEN_Msk (0x1ul << OTG_PHYCTL_OTGPHYEN_Pos) /*!< OTG_T::PHYCTL: OTGPHYEN Mask */
+
+#define OTG_PHYCTL_IDDETEN_Pos (1) /*!< OTG_T::PHYCTL: IDDETEN Position */
+#define OTG_PHYCTL_IDDETEN_Msk (0x1ul << OTG_PHYCTL_IDDETEN_Pos) /*!< OTG_T::PHYCTL: IDDETEN Mask */
+
+#define OTG_PHYCTL_VBENPOL_Pos (4) /*!< OTG_T::PHYCTL: VBENPOL Position */
+#define OTG_PHYCTL_VBENPOL_Msk (0x1ul << OTG_PHYCTL_VBENPOL_Pos) /*!< OTG_T::PHYCTL: VBENPOL Mask */
+
+#define OTG_PHYCTL_VBSTSPOL_Pos (5) /*!< OTG_T::PHYCTL: VBSTSPOL Position */
+#define OTG_PHYCTL_VBSTSPOL_Msk (0x1ul << OTG_PHYCTL_VBSTSPOL_Pos) /*!< OTG_T::PHYCTL: VBSTSPOL Mask */
+
+#define OTG_INTEN_ROLECHGIEN_Pos (0) /*!< OTG_T::INTEN: ROLECHGIEN Position */
+#define OTG_INTEN_ROLECHGIEN_Msk (0x1ul << OTG_INTEN_ROLECHGIEN_Pos) /*!< OTG_T::INTEN: ROLECHGIEN Mask */
+
+#define OTG_INTEN_VBEIEN_Pos (1) /*!< OTG_T::INTEN: VBEIEN Position */
+#define OTG_INTEN_VBEIEN_Msk (0x1ul << OTG_INTEN_VBEIEN_Pos) /*!< OTG_T::INTEN: VBEIEN Mask */
+
+#define OTG_INTEN_SRPFIEN_Pos (2) /*!< OTG_T::INTEN: SRPFIEN Position */
+#define OTG_INTEN_SRPFIEN_Msk (0x1ul << OTG_INTEN_SRPFIEN_Pos) /*!< OTG_T::INTEN: SRPFIEN Mask */
+
+#define OTG_INTEN_HNPFIEN_Pos (3) /*!< OTG_T::INTEN: HNPFIEN Position */
+#define OTG_INTEN_HNPFIEN_Msk (0x1ul << OTG_INTEN_HNPFIEN_Pos) /*!< OTG_T::INTEN: HNPFIEN Mask */
+
+#define OTG_INTEN_GOIDLEIEN_Pos (4) /*!< OTG_T::INTEN: GOIDLEIEN Position */
+#define OTG_INTEN_GOIDLEIEN_Msk (0x1ul << OTG_INTEN_GOIDLEIEN_Pos) /*!< OTG_T::INTEN: GOIDLEIEN Mask */
+
+#define OTG_INTEN_IDCHGIEN_Pos (5) /*!< OTG_T::INTEN: IDCHGIEN Position */
+#define OTG_INTEN_IDCHGIEN_Msk (0x1ul << OTG_INTEN_IDCHGIEN_Pos) /*!< OTG_T::INTEN: IDCHGIEN Mask */
+
+#define OTG_INTEN_PDEVIEN_Pos (6) /*!< OTG_T::INTEN: PDEVIEN Position */
+#define OTG_INTEN_PDEVIEN_Msk (0x1ul << OTG_INTEN_PDEVIEN_Pos) /*!< OTG_T::INTEN: PDEVIEN Mask */
+
+#define OTG_INTEN_HOSTIEN_Pos (7) /*!< OTG_T::INTEN: HOSTIEN Position */
+#define OTG_INTEN_HOSTIEN_Msk (0x1ul << OTG_INTEN_HOSTIEN_Pos) /*!< OTG_T::INTEN: HOSTIEN Mask */
+
+#define OTG_INTEN_BVLDCHGIEN_Pos (8) /*!< OTG_T::INTEN: BVLDCHGIEN Position */
+#define OTG_INTEN_BVLDCHGIEN_Msk (0x1ul << OTG_INTEN_BVLDCHGIEN_Pos) /*!< OTG_T::INTEN: BVLDCHGIEN Mask */
+
+#define OTG_INTEN_AVLDCHGIEN_Pos (9) /*!< OTG_T::INTEN: AVLDCHGIEN Position */
+#define OTG_INTEN_AVLDCHGIEN_Msk (0x1ul << OTG_INTEN_AVLDCHGIEN_Pos) /*!< OTG_T::INTEN: AVLDCHGIEN Mask */
+
+#define OTG_INTEN_VBCHGIEN_Pos (10) /*!< OTG_T::INTEN: VBCHGIEN Position */
+#define OTG_INTEN_VBCHGIEN_Msk (0x1ul << OTG_INTEN_VBCHGIEN_Pos) /*!< OTG_T::INTEN: VBCHGIEN Mask */
+
+#define OTG_INTEN_SECHGIEN_Pos (11) /*!< OTG_T::INTEN: SECHGIEN Position */
+#define OTG_INTEN_SECHGIEN_Msk (0x1ul << OTG_INTEN_SECHGIEN_Pos) /*!< OTG_T::INTEN: SECHGIEN Mask */
+
+#define OTG_INTEN_SRPDETIEN_Pos (13) /*!< OTG_T::INTEN: SRPDETIEN Position */
+#define OTG_INTEN_SRPDETIEN_Msk (0x1ul << OTG_INTEN_SRPDETIEN_Pos) /*!< OTG_T::INTEN: SRPDETIEN Mask */
+
+#define OTG_INTSTS_ROLECHGIF_Pos (0) /*!< OTG_T::INTSTS: ROLECHGIF Position */
+#define OTG_INTSTS_ROLECHGIF_Msk (0x1ul << OTG_INTSTS_ROLECHGIF_Pos) /*!< OTG_T::INTSTS: ROLECHGIF Mask */
+
+#define OTG_INTSTS_VBEIF_Pos (1) /*!< OTG_T::INTSTS: VBEIF Position */
+#define OTG_INTSTS_VBEIF_Msk (0x1ul << OTG_INTSTS_VBEIF_Pos) /*!< OTG_T::INTSTS: VBEIF Mask */
+
+#define OTG_INTSTS_SRPFIF_Pos (2) /*!< OTG_T::INTSTS: SRPFIF Position */
+#define OTG_INTSTS_SRPFIF_Msk (0x1ul << OTG_INTSTS_SRPFIF_Pos) /*!< OTG_T::INTSTS: SRPFIF Mask */
+
+#define OTG_INTSTS_HNPFIF_Pos (3) /*!< OTG_T::INTSTS: HNPFIF Position */
+#define OTG_INTSTS_HNPFIF_Msk (0x1ul << OTG_INTSTS_HNPFIF_Pos) /*!< OTG_T::INTSTS: HNPFIF Mask */
+
+#define OTG_INTSTS_GOIDLEIF_Pos (4) /*!< OTG_T::INTSTS: GOIDLEIF Position */
+#define OTG_INTSTS_GOIDLEIF_Msk (0x1ul << OTG_INTSTS_GOIDLEIF_Pos) /*!< OTG_T::INTSTS: GOIDLEIF Mask */
+
+#define OTG_INTSTS_IDCHGIF_Pos (5) /*!< OTG_T::INTSTS: IDCHGIF Position */
+#define OTG_INTSTS_IDCHGIF_Msk (0x1ul << OTG_INTSTS_IDCHGIF_Pos) /*!< OTG_T::INTSTS: IDCHGIF Mask */
+
+#define OTG_INTSTS_PDEVIF_Pos (6) /*!< OTG_T::INTSTS: PDEVIF Position */
+#define OTG_INTSTS_PDEVIF_Msk (0x1ul << OTG_INTSTS_PDEVIF_Pos) /*!< OTG_T::INTSTS: PDEVIF Mask */
+
+#define OTG_INTSTS_HOSTIF_Pos (7) /*!< OTG_T::INTSTS: HOSTIF Position */
+#define OTG_INTSTS_HOSTIF_Msk (0x1ul << OTG_INTSTS_HOSTIF_Pos) /*!< OTG_T::INTSTS: HOSTIF Mask */
+
+#define OTG_INTSTS_BVLDCHGIF_Pos (8) /*!< OTG_T::INTSTS: BVLDCHGIF Position */
+#define OTG_INTSTS_BVLDCHGIF_Msk (0x1ul << OTG_INTSTS_BVLDCHGIF_Pos) /*!< OTG_T::INTSTS: BVLDCHGIF Mask */
+
+#define OTG_INTSTS_AVLDCHGIF_Pos (9) /*!< OTG_T::INTSTS: AVLDCHGIF Position */
+#define OTG_INTSTS_AVLDCHGIF_Msk (0x1ul << OTG_INTSTS_AVLDCHGIF_Pos) /*!< OTG_T::INTSTS: AVLDCHGIF Mask */
+
+#define OTG_INTSTS_VBCHGIF_Pos (10) /*!< OTG_T::INTSTS: VBCHGIF Position */
+#define OTG_INTSTS_VBCHGIF_Msk (0x1ul << OTG_INTSTS_VBCHGIF_Pos) /*!< OTG_T::INTSTS: VBCHGIF Mask */
+
+#define OTG_INTSTS_SECHGIF_Pos (11) /*!< OTG_T::INTSTS: SECHGIF Position */
+#define OTG_INTSTS_SECHGIF_Msk (0x1ul << OTG_INTSTS_SECHGIF_Pos) /*!< OTG_T::INTSTS: SECHGIF Mask */
+
+#define OTG_INTSTS_SRPDETIF_Pos (13) /*!< OTG_T::INTSTS: SRPDETIF Position */
+#define OTG_INTSTS_SRPDETIF_Msk (0x1ul << OTG_INTSTS_SRPDETIF_Pos) /*!< OTG_T::INTSTS: SRPDETIF Mask */
+
+#define OTG_STATUS_OVERCUR_Pos (0) /*!< OTG_T::STATUS: OVERCUR Position */
+#define OTG_STATUS_OVERCUR_Msk (0x1ul << OTG_STATUS_OVERCUR_Pos) /*!< OTG_T::STATUS: OVERCUR Mask */
+
+#define OTG_STATUS_IDSTS_Pos (1) /*!< OTG_T::STATUS: IDSTS Position */
+#define OTG_STATUS_IDSTS_Msk (0x1ul << OTG_STATUS_IDSTS_Pos) /*!< OTG_T::STATUS: IDSTS Mask */
+
+#define OTG_STATUS_SESSEND_Pos (2) /*!< OTG_T::STATUS: SESSEND Position */
+#define OTG_STATUS_SESSEND_Msk (0x1ul << OTG_STATUS_SESSEND_Pos) /*!< OTG_T::STATUS: SESSEND Mask */
+
+#define OTG_STATUS_BVLD_Pos (3) /*!< OTG_T::STATUS: BVLD Position */
+#define OTG_STATUS_BVLD_Msk (0x1ul << OTG_STATUS_BVLD_Pos) /*!< OTG_T::STATUS: BVLD Mask */
+
+#define OTG_STATUS_AVLD_Pos (4) /*!< OTG_T::STATUS: AVLD Position */
+#define OTG_STATUS_AVLD_Msk (0x1ul << OTG_STATUS_AVLD_Pos) /*!< OTG_T::STATUS: AVLD Mask */
+
+#define OTG_STATUS_VBUSVLD_Pos (5) /*!< OTG_T::STATUS: VBUSVLD Position */
+#define OTG_STATUS_VBUSVLD_Msk (0x1ul << OTG_STATUS_VBUSVLD_Pos) /*!< OTG_T::STATUS: VBUSVLD Mask */
+
+/**@}*/ /* OTG_CONST */
+/**@}*/ /* end of OTG register group */
+
+
+/*---------------------- Peripheral Direct Memory Access Controller -------------------------*/
+/**
+ @addtogroup PDMA Peripheral Direct Memory Access Controller(PDMA)
+ Memory Mapped Structure for PDMA Controller
+@{ */
+
+
+typedef struct
+{
+
+
+/**
+ * @var DSCT_T::CTL
+ * Offset: 0x00/0x10/0x20/0x30/0x40/0x50/0x60/0x70/0x80/0x90/0xA0/0xB0 Descriptor Table Control Register of PDMA Channel 0~11
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[1:0] |OPMODE |PDMA Operation Mode Selection
+ * | | |0 = Idle state: Channel is stopped or this table is complete, when PDMA finish channel table task, OPMODE will be cleared to idle state automatically.
+ * | | |1 = Basic mode: The descriptor table only has one task.
+ * | | |When this task is finished, the PDMA_INTSTS[x] will be asserted.
+ * | | |2 = Scatter-Gather mode: When operating in this mode, user must give the next descriptor table address in PDMA_DSCT_NEXT register; PDMA controller will ignore this task, then load the next task to execute.
+ * | | |3 = Reserved.
+ * | | |Note: Before filling transfer task in the Descriptor Table, user must check if the descriptor table is complete.
+ * |[2] |TXTYPE |Transfer Type
+ * | | |0 = Burst transfer type.
+ * | | |1 = Single transfer type.
+ * |[6:4] |BURSIZE |Burst Size
+ * | | |This field is used for peripheral to determine the burst size or used for determine the re-arbitration size.
+ * | | |000 = 128 Transfers.
+ * | | |001 = 64 Transfers.
+ * | | |010 = 32 Transfers.
+ * | | |011 = 16 Transfers.
+ * | | |100 = 8 Transfers.
+ * | | |101 = 4 Transfers.
+ * | | |110 = 2 Transfers.
+ * | | |111 = 1 Transfers.
+ * | | |Note: This field is only useful in burst transfer type.
+ * |[7] |TBINTDIS |Table Interrupt Disable
+ * | | |This field can be used to decide whether to enable table interrupt or not.
+ * | | |If the TBINTDIS bit is enabled when PDMA controller finishes transfer task, it will not generates interrupt.
+ * | | |0 = Table interrupt Enabled.
+ * | | |1 = Table interrupt Disabled.
+ * | | |Note: If this bit set to '1', the TEMPTYF will not be set.
+ * |[9:8] |SAINC |Source Address Increment
+ * | | |This field is used to set the source address increment size.
+ * | | |11 = No increment (fixed address).
+ * | | |Others = Increment and size is depended on TXWIDTH selection.
+ * |[11:10] |DAINC |Destination Address Increment
+ * | | |This field is used to set the destination address increment size.
+ * | | |11 = No increment (fixed address).
+ * | | |Others = Increment and size is depended on TXWIDTH selection.
+ * |[13:12] |TXWIDTH |Transfer Width Selection
+ * | | |This field is used for transfer width.
+ * | | |00 = One byte (8 bit) is transferred for every operation.
+ * | | |01= One half-word (16 bit) is transferred for every operation.
+ * | | |10 = One word (32-bit) is transferred for every operation.
+ * | | |11 = Reserved.
+ * | | |Note: The PDMA transfer source address (PDMA_DSCT_SA) and PDMA transfer destination address (PDMA_DSCT_DA) should be alignment under the TXWIDTH selection
+ * |[29:16] |TXCNT |Transfer Count
+ * | | |The TXCNT represents the required number of PDMA transfer, the real transfer count is (TXCNT + 1); The maximum transfer count is 16384 , every transfer may be byte, half-word or word that is dependent on TXWIDTH field.
+ * | | |Note: When PDMA finish each transfer data, this field will be decrease immediately.
+ * @var DSCT_T::SA
+ * Offset: 0x04/0x14/0x24/0x34/0x44/0x54/0x64/0x74/0x84/0x94/0xA4/0xB4 Source Address Register of PDMA Channel 0~11
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |SA |PDMA Transfer Source Address Register
+ * | | |This field indicates a 32-bit source address of PDMA controller.
+ * @var DSCT_T::DA
+ * Offset: 0x08/0x18/0x28/0x38/0x48/0x58/0x68/0x78/0x88/0x98/0xA8/0xB8 Destination Address Register of PDMA Channel 0~11
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |DA |PDMA Transfer Destination Address Register
+ * | | |This field indicates a 32-bit destination address of PDMA controller.
+ * @var DSCT_T::NEXT
+ * Offset: 0x0C/0x1C/0x2C/0x3C/0x4C/0x5C/0x6C/0x7C/0x8C/0x9C/0xAC/0xBC First Scatter-Gather Descriptor Table Offset Address of PDMA Channel 0~11
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:2] |NEXT |PDMA Next Descriptor Table Offset Address Register
+ * | | |This field indicates the offset of next descriptor table address in system memory.
+ * | | |The system memory based address is 0x2000_0000 (PDMA_SCATBA), if the next descriptor table is 0x2000_0100, then this field must fill in 0x0100.
+ * | | |Note1: The next descriptor table address must be word boundary.
+ * | | |Note2: Before filled transfer task in the descriptor table, user must check if the descriptor table is complete.
+ */
+
+ __IO uint32_t CTL; /* Offset: 0x00/0x10/0x20/0x30/0x40/0x50/0x60/0x70/0x80/0x90/0xA0/0xB0 Descriptor Table Control Register of PDMA Channel 0~11 */
+ __IO uint32_t SA; /* Offset: 0x04/0x14/0x24/0x34/0x44/0x54/0x64/0x74/0x84/0x94/0xA4/0xB4 Source Address Register of PDMA Channel 0~11 */
+ __IO uint32_t DA; /* Offset: 0x08/0x18/0x28/0x38/0x48/0x58/0x68/0x78/0x88/0x98/0xA8/0xB8 Destination Address Register of PDMA Channel 0~11 */
+ __IO uint32_t NEXT; /* Offset: 0x0C/0x1C/0x2C/0x3C/0x4C/0x5C/0x6C/0x7C/0x8C/0x9C/0xAC/0xBC First Scatter-Gather Descriptor Table Offset Address of PDMA Channel 0~11 */
+
+} DSCT_T;
+
+
+
+
+typedef struct
+{
+
+
+/**
+ * @var PDMA_T::DSCT
+ * Offset: 0x0000 ~ 0x00BC DMA Embedded Description Table 0~11
+ * ---------------------------------------------------------------------------------------------------
+ * @var PDMA_T::CURSCAT
+ * Offset: 0xC0 ~ 0xEC Current Scatter-Gather Descriptor Table Address of PDMA Channel 0~11
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |CURADDR |PDMA Current Description Address Register (Read Only)
+ * | | |This field indicates a 32-bit current external description address of PDMA controller.
+ * | | |Note: This field is read only and only used for Scatter-Gather mode to indicate the current external description address.
+ * @var PDMA_T::CHCTL
+ * Offset: 0x400 PDMA Channel Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[11:0] |CHENn |PDMA Channel Enable Bit
+ * | | |Set this bit to 1 to enable PDMAn operation.
+ * | | |If each channel is not set as enabled, each channel cannot be active.
+ * | | |0 = PDMA channel [n] Disabled.
+ * | | |1 = PDMA channel [n] Enabled.
+ * | | |Note1: If software stops each PDMA transfer by setting PDMA_STOP register, this bit will be cleared automatically after finishing current transfer.
+ * | | |Note2: Software reset (writing 0xFFFF_FFFF to PDMA_STOP register) will also clear this bit.
+ * @var PDMA_T::STOP
+ * Offset: 0x404 PDMA Transfer Stop Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[11:0] |STOPn |PDMA Transfer Stop Control Register (Write Only)
+ * | | |User can stop the PDMA transfer by STOPn bit field or by software reset (writing '0xFFFF_FFFF' to PDMA_STOP register).
+ * | | |By bit field:
+ * | | |0 = No effect.
+ * | | |1 = Stop PDMA transfer[n].
+ * | | |When software set PDMA_STOP bit, the operation will finish the on-going transfer channel and then clear the channel enable bit (PDMA_CHCTL [CHEN]) and request active flag.
+ * | | |By write 0xFFFF_FFFF to PDMA_STOP:
+ * | | |Setting all PDMA_STOP bit to "1" will generate software reset to reset internal state machine (the DSCT will not be reset).
+ * | | |When software reset, the operation will be stopped imminently that include the on-going transfer and the channel enable bit (PDMA_CHCTL [CHEN]) and request active flag will be cleared to '0'.
+ * | | |Note: User can poll channel enable bit to know if the on-going transfer is finished.
+ * @var PDMA_T::SWREQ
+ * Offset: 0x408 PDMA Software Request Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[11:0] |SWREQn |PDMA Software Request Register (Write Only)
+ * | | |Set this bit to 1 to generate a software request to PDMA [n].
+ * | | |0 = No effect.
+ * | | |1 = Generate a software request.
+ * | | |Note1: User can read PDMA_TRGSTS register to know which channel is on active.
+ * | | |Active flag may be triggered by software request or peripheral request.
+ * | | |Note2: If user does not enable each PDMA channel, the software request will be ignored.
+ * @var PDMA_T::TRGSTS
+ * Offset: 0x40C PDMA Channel Request Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[11:0] |REQSTSn |PDMA Channel Request Status (Read Only)
+ * | | |This flag indicates whether channel[n] have a request or not, no matter request from software or peripheral.
+ * | | |When PDMA controller finishes channel transfer, this bit will be cleared automatically.
+ * | | |0 = PDMA Channel n has no request.
+ * | | |1 = PDMA Channel n has a request.
+ * | | |Note1: If software stops each PDMA transfer by setting PDMA_STOP register, this bit will be cleared automatically after finishing current transfer.
+ * | | |Note2: Software reset (writing 0xFFFF_FFFF to PDMA_STOP register) will also clear this bit.
+ * @var PDMA_T::PRISET
+ * Offset: 0x410 PDMA Fixed Priority Setting Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[11:0] |FPRISETn |PDMA Fixed Priority Setting Register
+ * | | |Set this bit to 1 to enable fixed priority level.
+ * | | |Write Operation:
+ * | | |0 = No effect.
+ * | | |1 = Set PDMA channel [n] to fixed priority channel.
+ * | | |Read Operation:
+ * | | |0 = Corresponding PDMA channel is round-robin priority.
+ * | | |1 = Corresponding PDMA channel is fixed priority.
+ * | | |Note: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register.
+ * @var PDMA_T::PRICLR
+ * Offset: 0x414 PDMA Fixed Priority Clear Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[11:0] |FPRICLRn |PDMA Fixed Priority Clear Register (Write Only)
+ * | | |Set this bit to 1 to clear fixed priority level.
+ * | | |0 = No effect.
+ * | | |1 = Clear PDMA channel [n] fixed priority setting.
+ * | | |Note: User can read PDMA_PRISET register to know the channel priority.
+ * @var PDMA_T::INTEN
+ * Offset: 0x418 PDMA Interrupt Enable Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[11:0] |INTENn |PDMA Interrupt Enable Register
+ * | | |This field is used for enabling PDMA channel[n] interrupt.
+ * | | |0 = PDMA channel n interrupt Disabled.
+ * | | |1 = PDMA channel n interrupt Enabled.
+ * |[31:12] |Reserved |should be keep 0.
+ * @var PDMA_T::INTSTS
+ * Offset: 0x41C PDMA Interrupt Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |ABTIF |PDMA Read/Write Target Abort Interrupt Flag (Read-Only)
+ * | | |This bit indicates that PDMA has target abort error; Software can read PDMA_ABTSTS register to find which channel has target abort error.
+ * | | |0 = No AHB bus ERROR response received.
+ * | | |1 = AHB bus ERROR response received.
+ * |[1] |TDIF |Transfer Done Interrupt Flag (Read Only)
+ * | | |This bit indicates that PDMA controller has finished transmission; User can read PDMA_TDSTS register to indicate which channel finished transfer.
+ * | | |0 = Not finished yet.
+ * | | |1 = PDMA channel has finished transmission.
+ * |[2] |TEIF |Table Empty Interrupt Flag (Read Only)
+ * | | |This bit indicates that PDMA controller has finished each table transmission and the operation is Stop mode.
+ * | | |User can read TEIF register to indicate which channel finished transfer.
+ * | | |0 = PDMA channel transfer is not finished.
+ * | | |1 = PDMA channel transfer is finished and the operation is in idle state.
+ * |[8:15] |REQTOFn |Request Time-out Flag For Each Channel [N](M45xD/M45xC Only)
+ * | | |This flag indicates that PDMA controller has waited peripheral request for a period defined by PDMA_TOCn, user can write 1 to clear these bits.
+ * | | |0 = No request time-out.
+ * | | |1 = Peripheral request time-out.
+ * @var PDMA_T::ABTSTS
+ * Offset: 0x420 PDMA Channel Read/Write Target Abort Flag Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[11:0] |ABTIFn |PDMA Read/Write Target Abort Interrupt Status Flag
+ * | | |This bit indicates which PDMA controller has target abort error; User can write 1 to clear these bits.
+ * | | |0 = No AHB bus ERROR response received when channel n transfer.
+ * | | |1 = AHB bus ERROR response received when channel n transfer.
+ * @var PDMA_T::TDSTS
+ * Offset: 0x424 PDMA Channel Transfer Done Flag Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[11:0] |TDIFn |Transfer Done Flag Register
+ * | | |This bit indicates whether PDMA controller channel transfer has been finished or not, user can write 1 to clear these bits.
+ * | | |0 = PDMA channel transfer has not finished.
+ * | | |1 = PDMA channel has finished transmission.
+ * @var PDMA_T::SCATSTS
+ * Offset: 0x428 PDMA Scatter-Gather Table Empty Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[11:0] |TEMPTYFn |Scatter-Gather Table Empty Flag Register
+ * | | |This bit indicates which PDMA channel n Scatter Gather table is empty when SWREQn set to high or channel has finished transmission and the operation mode is Stop mode.
+ * | | |User can write 1 to clear these bits.
+ * | | |0 = PDMA channel scatter-gather table is not empty.
+ * | | |1 = PDMA channel scatter-gather table is empty and PDMA SWREQ has be set.
+ * @var PDMA_T::TACTSTS
+ * Offset: 0x42C PDMA Transfer Active Flag Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[11:0] |TXACTFn |Transfer On Active Flag Register (Read Only)
+ * | | |This bit indicates which PDMA channel is in active.
+ * | | |0 = PDMA channel is not finished.
+ * | | |1 = PDMA channel is active.
+ * @var PDMA_T::TOUTEN
+ * Offset: 0x434 PDMA Time-out Enable register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:0] |TOUTENn |PDMA Time-Out Enable Bits
+ * | | |0 = PDMA Channel n time-out function Disable.
+ * | | |1 = PDMA Channel n time-out function Enable.
+ * @var PDMA_T::TOUTIEN
+ * Offset: 0x438 PDMA Time-out Interrupt Enable register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:0] |TOUTIENn |PDMA Time-Out Interrupt Enable Bits
+ * | | |0 = PDMA Channel n time-out interrupt Disable.
+ * | | |1 = PDMA Channel n time-out interrupt Enable.
+ * @var PDMA_T::SCATBA
+ * Offset: 0x43C PDMA Scatter-Gather Descriptor Table Base Address Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:16] |SCATBA |PDMA Scatter-Gather Descriptor Table Address Register
+ * | | |In Scatter-Gather mode, this is the base address for calculating the next link - list address.
+ * | | |The next link address equation is.
+ * | | |Next Link Address = PDMA_SCATBA + PDMA_DSCT_NEXT.
+ * | | |Note: Only useful in Scatter-Gather mode.
+ * @var PDMA_T::TOC0_1
+ * Offset: 0x440 PDMA Time-out Counter Ch1 and Ch0 Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:16] |TOC1 |Time-Out Counter For Channel 1
+ * | | |This controls the period of time-out function for channel 1. The calculation unit is based on 10 kHz clock.
+ * |[15:0] |TOC0 |Time-Out Counter For Channel 0
+ * | | |This controls the period of time-out function for channel 0. The calculation unit is based on 10 kHz clock.
+ * @var PDMA_T::TOC2_3
+ * Offset: 0x444 PDMA Time-out Counter Ch3 and Ch2 Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:16] |TOC3 |Time-Out Counter For Channel 3
+ * | | |This controls the period of time-out function for channel 3. The calculation unit is based on 10 kHz clock.
+ * |[15:0] |TOC2 |Time-Out Counter For Channel 2
+ * | | |This controls the period of time-out function for channel 2. The calculation unit is based on 10 kHz clock.
+ * @var PDMA_T::TOC4_5
+ * Offset: 0x448 PDMA Time-out Counter Ch5 and Ch4 Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:16] |TOC5 |Time-Out Counter For Channel 5
+ * | | |This controls the period of time-out function for channel 5. The calculation unit is based on 10 kHz clock.
+ * |[15:0] |TOC4 |Time-Out Counter For Channel 4
+ * | | |This controls the period of time-out function for channel 4. The calculation unit is based on 10 kHz clock.
+ * @var PDMA_T::TOC6_7
+ * Offset: 0x44C PDMA Time-out Counter Ch7 and Ch6 Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:16] |TOC7 |Time-Out Counter For Channel 7
+ * | | |This controls the period of time-out function for channel 7. The calculation unit is based on 10 kHz clock.
+ * |[15:0] |TOC6 |Time-Out Counter For Channel 6
+ * | | |This controls the period of time-out function for channel 6. The calculation unit is based on 10 kHz clock.
+ * @var PDMA_T::REQSEL0_3
+ * Offset: 0x480 PDMA Request Source Select Register 0
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[4:0] |REQSRC0 |Channel 0 Request Source Selection
+ * | | |This filed defines which peripheral is connected to PDMA channel 0.
+ * | | |User can configure the peripheral by setting REQSRC0.
+ * | | |1 = Channel connects to SPI0_TX.
+ * | | |2 = Channel connects to SPI1_TX.
+ * | | |3 = Channel connects to SPI2_TX.
+ * | | |4 = Channel connects to UART0_TX.
+ * | | |5 = Channel connects to UART1_TX.
+ * | | |6 = Channel connects to UART2_TX.
+ * | | |7 = Channel connects to UART3_TX.
+ * | | |8 = Channel connects to DAC_TX.
+ * | | |9 = Channel connects to ADC_RX.
+ * | | |11 = Channel connects to PWM0_P1_RX.
+ * | | |12 = Channel connects to PWM0_P2_RX.
+ * | | |13 = Channel connects to PWM0_P3_RX.
+ * | | |14 = Channel connects to PWM1_P1_RX.
+ * | | |15 = Channel connects to PWM1_P2_RX.
+ * | | |16 = Channel connects to PWM1_P3_RX.
+ * | | |17 = Channel connects to SPI0_RX.
+ * | | |18 = Channel connects to SPI1_RX.
+ * | | |19 = Channel connects to SPI2_RX.
+ * | | |20 = Channel connects to UART0_RX.
+ * | | |21 = Channel connects to UART1_RX.
+ * | | |22 = Channel connects to UART2_RX.
+ * | | |23 = Channel connects to UART3_RX.
+ * | | |31 = Disable PDMA.
+ * | | |Others = Reserved.
+ * | | |Note 1: A peripheral can't assign to two channels at the same time.
+ * | | |Note 2: This field is useless when transfer between memory and memory.
+ * |[12:8] |REQSRC1 |Channel 1 Request Source Selection
+ * | | |This filed defines which peripheral is connected to PDMA channel 1.
+ * | | |User can configure the peripheral setting by REQSRC1.
+ * | | |Note: The channel configuration is the same as REQSRC0 field.
+ * | | |Please refer to the explanation of REQSRC0.
+ * |[20:16] |REQSRC2 |Channel 2 Request Source Selection
+ * | | |This filed defines which peripheral is connected to PDMA channel 2.
+ * | | |User can configure the peripheral setting by REQSRC2.
+ * | | |Note: The channel configuration is the same as REQSRC0 field.
+ * | | |Please refer to the explanation of REQSRC0.
+ * |[28:24] |REQSRC3 |Channel 3 Request Source Selection
+ * | | |This filed defines which peripheral is connected to PDMA channel 3.
+ * | | |User can configure the peripheral setting by REQSRC3.
+ * | | |Note: The channel configuration is the same as REQSRC0 field.
+ * | | |Please refer to the explanation of REQSRC0.
+ * @var PDMA_T::REQSEL4_7
+ * Offset: 0x484 PDMA Request Source Select Register 1
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[4:0] |REQSRC4 |Channel 4 Request Source Selection
+ * | | |This filed defines which peripheral is connected to PDMA channel 4.
+ * | | |User can configure the peripheral setting by REQSRC4.
+ * | | |Note: The channel configuration is the same as REQSRC0 field.
+ * | | |Please refer to the explanation of REQSRC0.
+ * |[12:8] |REQSRC5 |Channel 5 Request Source Selection
+ * | | |This filed defines which peripheral is connected to PDMA channel 5.
+ * | | |User can configure the peripheral setting by REQSRC5.
+ * | | |Note: The channel configuration is the same as REQSRC0 field.
+ * | | |Please refer to the explanation of REQSRC0.
+ * |[20:16] |REQSRC6 |Channel 6 Request Source Selection
+ * | | |This filed defines which peripheral is connected to PDMA channel 6.
+ * | | |User can configure the peripheral setting by REQSRC6.
+ * | | |Note: The channel configuration is the same as REQSRC0 field.
+ * | | |Please refer to the explanation of REQSRC0.
+ * |[28:24] |REQSRC7 |Channel 7 Request Source Selection
+ * | | |This filed defines which peripheral is connected to PDMA channel 7.
+ * | | |User can configure the peripheral setting by REQSRC7.
+ * | | |Note: The channel configuration is the same as REQSRC0 field.
+ * | | |Please refer to the explanation of REQSRC0.
+ * @var PDMA_T::REQSEL8_11
+ * Offset: 0x488 PDMA Request Source Select Register 2
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[4:0] |REQSRC8 |Channel 8 Request Source Selection
+ * | | |This filed defines which peripheral is connected to PDMA channel 8.
+ * | | |User can configure the peripheral setting by REQSRC8.
+ * | | |Note: The channel configuration is the same as REQSRC0 field.
+ * | | |Please refer to the explanation of REQSRC0.
+ * |[12:8] |REQSRC9 |Channel 9 Request Source Selection
+ * | | |This filed defines which peripheral is connected to PDMA channel 9.
+ * | | |User can configure the peripheral setting by REQSRC9.
+ * | | |Note: The channel configuration is the same as REQSRC0 field.
+ * | | |Please refer to the explanation of REQSRC0.
+ * |[20:16] |REQSRC10 |Channel 10 Request Source Selection
+ * | | |This filed defines which peripheral is connected to PDMA channel 10.
+ * | | |User can configure the peripheral setting by REQSRC10.
+ * | | |Note: The channel configuration is the same as REQSRC0 field.
+ * | | |Please refer to the explanation of REQSRC0.
+ * |[28:24] |REQSRC11 |Channel 11 Request Source Selection
+ * | | |This filed defines which peripheral is connected to PDMA channel 11.
+ * | | |User can configure the peripheral setting by REQSRC11.
+ * | | |Note: The channel configuration is the same as REQSRC0 field.
+ * | | |Please refer to the explanation of REQSRC0.
+ */
+
+ DSCT_T DSCT[12]; /* Offset: 0x0000 ~ 0x00BC DMA Embedded Description Table 0~11 */
+ __I uint32_t CURSCAT[12];
+ __I uint32_t RESERVE0[196]; /* Offset: 0xC0 ~ 0xEC Current Scatter-Gather Descriptor Table Address of PDMA Channel 0~11 */
+ __IO uint32_t CHCTL; /* Offset: 0x400 PDMA Channel Control Register */
+ __O uint32_t STOP; /* Offset: 0x404 PDMA Transfer Stop Control Register */
+ __O uint32_t SWREQ; /* Offset: 0x408 PDMA Software Request Register */
+ __I uint32_t TRGSTS; /* Offset: 0x40C PDMA Channel Request Status Register */
+ __IO uint32_t PRISET; /* Offset: 0x410 PDMA Fixed Priority Setting Register */
+ __O uint32_t PRICLR; /* Offset: 0x414 PDMA Fixed Priority Clear Register */
+ __IO uint32_t INTEN; /* Offset: 0x418 PDMA Interrupt Enable Register */
+ __IO uint32_t INTSTS; /* Offset: 0x41C PDMA Interrupt Status Register */
+ __IO uint32_t ABTSTS; /* Offset: 0x420 PDMA Channel Read/Write Target Abort Flag Register */
+ __IO uint32_t TDSTS; /* Offset: 0x424 PDMA Channel Transfer Done Flag Register */
+ __IO uint32_t SCATSTS; /* Offset: 0x428 PDMA Scatter-Gather Table Empty Status Register */
+ __I uint32_t TACTSTS;
+ __I uint32_t RESERVE1[1]; /* Offset: 0x42C PDMA Transfer Active Flag Register */
+ __IO uint32_t TOUTEN; /* Offset: 0x434 PDMA Time-out Enable register */
+ __IO uint32_t TOUTIEN; /* Offset: 0x438 PDMA Time-out Interrupt Enable register */
+ __IO uint32_t SCATBA; /* Offset: 0x43C PDMA Scatter-Gather Descriptor Table Base Address Register */
+ __IO uint32_t TOC0_1; /* Offset: 0x440 PDMA Time-out Counter Ch1 and Ch0 Register */
+ __IO uint32_t TOC2_3; /* Offset: 0x444 PDMA Time-out Counter Ch3 and Ch2 Register */
+ __IO uint32_t TOC4_5; /* Offset: 0x448 PDMA Time-out Counter Ch5 and Ch4 Register */
+ __IO uint32_t TOC6_7;
+ __I uint32_t RESERVE2[12]; /* Offset: 0x44C PDMA Time-out Counter Ch7 and Ch6 Register */
+ __IO uint32_t REQSEL0_3; /* Offset: 0x480 PDMA Request Source Select Register 0 */
+ __IO uint32_t REQSEL4_7; /* Offset: 0x484 PDMA Request Source Select Register 1 */
+ __IO uint32_t REQSEL8_11; /* Offset: 0x484 PDMA Request Source Select Register 2 */
+
+} PDMA_T;
+
+
+
+/**
+ @addtogroup PDMA_CONST PDMA Bit Field Definition
+ Constant Definitions for PDMA Controller
+@{ */
+
+#define PDMA_DSCT_CTL_OPMODE_Pos (0) /*!< DSCT_T::CTL: OPMODE Position */
+#define PDMA_DSCT_CTL_OPMODE_Msk (0x3ul << PDMA_DSCT_CTL_OPMODE_Pos) /*!< DSCT_T::CTL: OPMODE Mask */
+
+#define PDMA_DSCT_CTL_TXTYPE_Pos (2) /*!< DSCT_T::CTL: TXTYPE Position */
+#define PDMA_DSCT_CTL_TXTYPE_Msk (1ul << PDMA_DSCT_CTL_TXTYPE_Pos) /*!< DSCT_T::CTL: TXTYPE Mask */
+
+#define PDMA_DSCT_CTL_BURSIZE_Pos (4) /*!< DSCT_T::CTL: BURSIZE Position */
+#define PDMA_DSCT_CTL_BURSIZE_Msk (0x7ul << PDMA_DSCT_CTL_BURSIZE_Pos) /*!< DSCT_T::CTL: BURSIZE Mask */
+
+#define PDMA_DSCT_CTL_TBINTDIS_Pos (7) /*!< DSCT_T::CTL: TBINTDIS Position */
+#define PDMA_DSCT_CTL_TBINTDIS_Msk (1ul << PDMA_DSCT_CTL_TBINTDIS_Pos) /*!< DSCT_T::CTL: TBINTDIS Mask */
+
+#define PDMA_DSCT_CTL_SAINC_Pos (8) /*!< DSCT_T::CTL: SAINC Position */
+#define PDMA_DSCT_CTL_SAINC_Msk (0x3ul << PDMA_DSCT_CTL_SAINC_Pos) /*!< DSCT_T::CTL: SAINC Mask */
+
+#define PDMA_DSCT_CTL_DAINC_Pos (10) /*!< DSCT_T::CTL: DAINC Position */
+#define PDMA_DSCT_CTL_DAINC_Msk (0x3ul << PDMA_DSCT_CTL_DAINC_Pos) /*!< DSCT_T::CTL: DAINC Mask */
+
+#define PDMA_DSCT_CTL_TXWIDTH_Pos (12) /*!< DSCT_T::CTL: TXWIDTH Position */
+#define PDMA_DSCT_CTL_TXWIDTH_Msk (0x3ul << PDMA_DSCT_CTL_TXWIDTH_Pos) /*!< DSCT_T::CTL: TXWIDTH Mask */
+
+#define PDMA_DSCT_CTL_TXCNT_Pos (16) /*!< DSCT_T::CTL: TXCNT Position */
+#define PDMA_DSCT_CTL_TXCNT_Msk (0x3FFFul << PDMA_DSCT_CTL_TXCNT_Pos) /*!< DSCT_T::CTL: TXCNT Mask */
+
+#define PDMA_DSCT_SA_SA_Pos (0) /*!< DSCT_T::SA: SA Position */
+#define PDMA_DSCT_SA_SA_Msk (0xFFFFFFFFul << PDMA_DSCT_SA_SA_Pos) /*!< DSCT_T::SA: SA Mask */
+
+#define PDMA_DSCT_DA_DA_Pos (0) /*!< DSCT_T::DA: DA Position */
+#define PDMA_DSCT_DA_DA_Msk (0xFFFFFFFFul << PDMA_DSCT_DA_DA_Pos) /*!< DSCT_T::DA: DA Mask */
+
+#define PDMA_DSCT_NEXT_NEXT_Pos (0) /*!< DSCT_T::NEXT: NEXT Position */
+#define PDMA_DSCT_NEXT_NEXT_Msk (0xFFFFul << PDMA_DSCT_NEXT_NEXT_Pos) /*!< DSCT_T::NEXT: NEXT Mask */
+
+#define PDMA_CURSCAT_CURADDR_Pos (0) /*!< PDMA_T::CURSCAT: CURADDR Position */
+#define PDMA_CURSCAT_CURADDR_Msk (0xfffffffful << PDMA_CURSCAT_CURADDR_Pos) /*!< PDMA_T::CURSCAT: CURADDR Mask */
+
+#define PDMA_CHCTL_CHENn_Pos (0) /*!< PDMA_T::CHCTL: CHENn Position */
+#define PDMA_CHCTL_CHENn_Msk (0xffful << PDMA_CHCTL_CHENn_Pos) /*!< PDMA_T::CHCTL: CHENn Mask */
+
+#define PDMA_STOP_STOPn_Pos (0) /*!< PDMA_T::STOP: STOPn Position */
+#define PDMA_STOP_STOPn_Msk (0xffful << PDMA_STOP_STOPn_Pos) /*!< PDMA_T::STOP: STOPn Mask */
+
+#define PDMA_SWREQ_SWREQn_Pos (0) /*!< PDMA_T::SWREQ: SWREQn Position */
+#define PDMA_SWREQ_SWREQn_Msk (0xffful << PDMA_SWREQ_SWREQn_Pos) /*!< PDMA_T::SWREQ: SWREQn Mask */
+
+#define PDMA_TRGSTS_REQSTSn_Pos (0) /*!< PDMA_T::TRGSTS: REQSTSn Position */
+#define PDMA_TRGSTS_REQSTSn_Msk (0xffful << PDMA_TRGSTS_REQSTSn_Pos) /*!< PDMA_T::TRGSTS: REQSTSn Mask */
+
+#define PDMA_PRISET_FPRISETn_Pos (0) /*!< PDMA_T::PRISET: FPRISETn Position */
+#define PDMA_PRISET_FPRISETn_Msk (0xffful << PDMA_PRISET_FPRISETn_Pos) /*!< PDMA_T::PRISET: FPRISETn Mask */
+
+#define PDMA_PRICLR_FPRICLRn_Pos (0) /*!< PDMA_T::PRICLR: FPRICLRn Position */
+#define PDMA_PRICLR_FPRICLRn_Msk (0xffful << PDMA_PRICLR_FPRICLRn_Pos) /*!< PDMA_T::PRICLR: FPRICLRn Mask */
+
+#define PDMA_INTEN_INTENn_Pos (0) /*!< PDMA_T::INTEN: INTENn Position */
+#define PDMA_INTEN_INTENn_Msk (0xffful << PDMA_INTEN_INTENn_Pos) /*!< PDMA_T::INTEN: INTENn Mask */
+
+#define PDMA_INTSTS_ABTIF_Pos (0) /*!< PDMA_T::INTSTS: ABTIF Position */
+#define PDMA_INTSTS_ABTIF_Msk (0x1ul << PDMA_INTSTS_ABTIF_Pos) /*!< PDMA_T::INTSTS: ABTIF Mask */
+
+#define PDMA_INTSTS_TDIF_Pos (1) /*!< PDMA_T::INTSTS: TDIF Position */
+#define PDMA_INTSTS_TDIF_Msk (0x1ul << PDMA_INTSTS_TDIF_Pos) /*!< PDMA_T::INTSTS: TDIF Mask */
+
+#define PDMA_INTSTS_TEIF_Pos (2) /*!< PDMA_T::INTSTS: TEIF Position */
+#define PDMA_INTSTS_TEIF_Msk (0x1ul << PDMA_INTSTS_TEIF_Pos) /*!< PDMA_T::INTSTS: TEIF Mask */
+
+#define PDMA_INTSTS_REQTOFn_Pos (8) /*!< PDMA_T::INTSTS: REQTOFn Position */
+#define PDMA_INTSTS_REQTOFn_Msk (0xfful << PDMA_INTSTS_REQTOFn_Pos) /*!< PDMA_T::INTSTS: REQTOFn Mask */
+
+#define PDMA_ABTSTS_ABTIFn_Pos (0) /*!< PDMA_T::ABTSTS: ABTIFn Position */
+#define PDMA_ABTSTS_ABTIFn_Msk (0xffful << PDMA_ABTSTS_ABTIFn_Pos) /*!< PDMA_T::ABTSTS: ABTIFn Mask */
+
+#define PDMA_TDSTS_TDIFn_Pos (0) /*!< PDMA_T::TDSTS: TDIFn Position */
+#define PDMA_TDSTS_TDIFn_Msk (0xffful << PDMA_TDSTS_TDIFn_Pos) /*!< PDMA_T::TDSTS: TDIFn Mask */
+
+#define PDMA_SCATSTS_TEMPTYFn_Pos (0) /*!< PDMA_T::SCATSTS: TEMPTYFn Position */
+#define PDMA_SCATSTS_TEMPTYFn_Msk (0xffful << PDMA_SCATSTS_TEMPTYFn_Pos) /*!< PDMA_T::SCATSTS: TEMPTYFn Mask */
+
+#define PDMA_TACTSTS_TXACTFn_Pos (0) /*!< PDMA_T::TACTSTS: TXACTFn Position */
+#define PDMA_TACTSTS_TXACTFn_Msk (0xffful << PDMA_TACTSTS_TXACTFn_Pos) /*!< PDMA_T::TACTSTS: TXACTFn Mask */
+
+#define PDMA_TOUTEN_TOUTENn_Pos (0) /*!< PDMA_T::TOUTEN: TOUTENn Position */
+#define PDMA_TOUTEN_TOUTENn_Msk (0xfful << PDMA_TOUTEN_TOUTENn_Pos) /*!< PDMA_T::TOUTEN: TOUTENn Mask */
+
+#define PDMA_TOUTIEN_TOUTIENn_Pos (0) /*!< PDMA_T::TOUTIEN: TOUTIENn Position */
+#define PDMA_TOUTIEN_TOUTIENn_Msk (0xfful << PDMA_TOUTIEN_TOUTIENn_Pos) /*!< PDMA_T::TOUTIEN: TOUTIENn Mask */
+
+#define PDMA_SCATBA_SCATBA_Pos (16) /*!< PDMA_T::SCATBA: SCATBA Position */
+#define PDMA_SCATBA_SCATBA_Msk (0xfffful << PDMA_SCATBA_SCATBA_Pos) /*!< PDMA_T::SCATBA: SCATBA Mask */
+
+#define PDMA_TOC0_1_TOC0_Pos (0) /*!< PDMA_T::TOC0_1: TOC0 Position */
+#define PDMA_TOC0_1_TOC0_Msk (0xfffful << PDMA_TOC0_1_TOC0_Pos) /*!< PDMA_T::TOC0_1: TOC0 Mask */
+
+#define PDMA_TOC0_1_TOC1_Pos (16) /*!< PDMA_T::TOC0_1: TOC1 Position */
+#define PDMA_TOC0_1_TOC1_Msk (0xfffful << PDMA_TOC0_1_TOC1_Pos) /*!< PDMA_T::TOC0_1: TOC1 Mask */
+
+#define PDMA_TOC2_3_TOC2_Pos (0) /*!< PDMA_T::TOC2_3: TOC2 Position */
+#define PDMA_TOC2_3_TOC2_Msk (0xfffful << PDMA_TOC2_3_TOC2_Pos) /*!< PDMA_T::TOC2_3: TOC2 Mask */
+
+#define PDMA_TOC2_3_TOC3_Pos (16) /*!< PDMA_T::TOC2_3: TOC3 Position */
+#define PDMA_TOC2_3_TOC3_Msk (0xfffful << PDMA_TOC2_3_TOC3_Pos) /*!< PDMA_T::TOC2_3: TOC3 Mask */
+
+#define PDMA_TOC4_5_TOC4_Pos (0) /*!< PDMA_T::TOC4_5: TOC4 Position */
+#define PDMA_TOC4_5_TOC4_Msk (0xfffful << PDMA_TOC4_5_TOC4_Pos) /*!< PDMA_T::TOC4_5: TOC4 Mask */
+
+#define PDMA_TOC4_5_TOC5_Pos (16) /*!< PDMA_T::TOC4_5: TOC5 Position */
+#define PDMA_TOC4_5_TOC5_Msk (0xfffful << PDMA_TOC4_5_TOC5_Pos) /*!< PDMA_T::TOC4_5: TOC5 Mask */
+
+#define PDMA_TOC6_7_TOC6_Pos (0) /*!< PDMA_T::TOC6_7: TOC6 Position */
+#define PDMA_TOC6_7_TOC6_Msk (0xfffful << PDMA_TOC6_7_TOC6_Pos) /*!< PDMA_T::TOC6_7: TOC6 Mask */
+
+#define PDMA_TOC6_7_TOC7_Pos (16) /*!< PDMA_T::TOC6_7: TOC7 Position */
+#define PDMA_TOC6_7_TOC7_Msk (0xfffful << PDMA_TOC6_7_TOC7_Pos) /*!< PDMA_T::TOC6_7: TOC7 Mask */
+
+#define PDMA_REQSEL0_3_REQSRC0_Pos (0) /*!< PDMA_T::REQSEL0_3: REQSRC0 Position */
+#define PDMA_REQSEL0_3_REQSRC0_Msk (0x1ful << PDMA_REQSEL0_3_REQSRC0_Pos) /*!< PDMA_T::REQSEL0_3: REQSRC0 Mask */
+
+#define PDMA_REQSEL0_3_REQSRC1_Pos (8) /*!< PDMA_T::REQSEL0_3: REQSRC1 Position */
+#define PDMA_REQSEL0_3_REQSRC1_Msk (0x1ful << PDMA_REQSEL0_3_REQSRC1_Pos) /*!< PDMA_T::REQSEL0_3: REQSRC1 Mask */
+
+#define PDMA_REQSEL0_3_REQSRC2_Pos (16) /*!< PDMA_T::REQSEL0_3: REQSRC2 Position */
+#define PDMA_REQSEL0_3_REQSRC2_Msk (0x1ful << PDMA_REQSEL0_3_REQSRC2_Pos) /*!< PDMA_T::REQSEL0_3: REQSRC2 Mask */
+
+#define PDMA_REQSEL0_3_REQSRC3_Pos (24) /*!< PDMA_T::REQSEL0_3: REQSRC3 Position */
+#define PDMA_REQSEL0_3_REQSRC3_Msk (0x1ful << PDMA_REQSEL0_3_REQSRC3_Pos) /*!< PDMA_T::REQSEL0_3: REQSRC3 Mask */
+
+#define PDMA_REQSEL4_7_REQSRC4_Pos (0) /*!< PDMA_T::REQSEL4_7: REQSRC4 Position */
+#define PDMA_REQSEL4_7_REQSRC4_Msk (0x1ful << PDMA_REQSEL4_7_REQSRC4_Pos) /*!< PDMA_T::REQSEL4_7: REQSRC4 Mask */
+
+#define PDMA_REQSEL4_7_REQSRC5_Pos (8) /*!< PDMA_T::REQSEL4_7: REQSRC5 Position */
+#define PDMA_REQSEL4_7_REQSRC5_Msk (0x1ful << PDMA_REQSEL4_7_REQSRC5_Pos) /*!< PDMA_T::REQSEL4_7: REQSRC5 Mask */
+
+#define PDMA_REQSEL4_7_REQSRC6_Pos (16) /*!< PDMA_T::REQSEL4_7: REQSRC6 Position */
+#define PDMA_REQSEL4_7_REQSRC6_Msk (0x1ful << PDMA_REQSEL4_7_REQSRC6_Pos) /*!< PDMA_T::REQSEL4_7: REQSRC6 Mask */
+
+#define PDMA_REQSEL4_7_REQSRC7_Pos (24) /*!< PDMA_T::REQSEL4_7: REQSRC7 Position */
+#define PDMA_REQSEL4_7_REQSRC7_Msk (0x1ful << PDMA_REQSEL4_7_REQSRC7_Pos) /*!< PDMA_T::REQSEL4_7: REQSRC7 Mask */
+
+#define PDMA_REQSEL8_11_REQSRC8_Pos (0) /*!< PDMA_T::REQSEL8_11: REQSRC8 Position */
+#define PDMA_REQSEL8_11_REQSRC8_Msk (0x1ful << PDMA_REQSEL8_11_REQSRC8_Pos) /*!< PDMA_T::REQSEL8_11: REQSRC8 Mask */
+
+#define PDMA_REQSEL8_11_REQSRC9_Pos (8) /*!< PDMA_T::REQSEL8_11: REQSRC9 Position */
+#define PDMA_REQSEL8_11_REQSRC9_Msk (0x1ful << PDMA_REQSEL8_11_REQSRC9_Pos) /*!< PDMA_T::REQSEL8_11: REQSRC9 Mask */
+
+#define PDMA_REQSEL8_11_REQSRC10_Pos (16) /*!< PDMA_T::REQSEL8_11: REQSRC10 Position */
+#define PDMA_REQSEL8_11_REQSRC10_Msk (0x1ful << PDMA_REQSEL8_11_REQSRC10_Pos) /*!< PDMA_T::REQSEL8_11: REQSRC10 Mask */
+
+#define PDMA_REQSEL8_11_REQSRC11_Pos (24) /*!< PDMA_T::REQSEL8_11: REQSRC11 Position */
+#define PDMA_REQSEL8_11_REQSRC11_Msk (0x1ful << PDMA_REQSEL8_11_REQSRC11_Pos) /*!< PDMA_T::REQSEL8_11: REQSRC11 Mask */
+
+/**@}*/ /* PDMA_CONST */
+/**@}*/ /* end of PDMA register group */
+
+
+/*---------------------- Pulse Width Modulation Controller -------------------------*/
+/**
+ @addtogroup PWM Pulse Width Modulation Controller(PWM)
+ Memory Mapped Structure for PWM Controller
+@{ */
+
+
+typedef struct
+{
+
+
+/**
+ * @var PWM_T::CTL0
+ * Offset: 0x00 PWM Control Register 0
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[5:0] |CTRLDn |Center Re-Load
+ * | | |Each bit n controls the corresponding PWM channel n.
+ * | | |In up-down counter type, PERIOD will load to PBUF at the end point of each period.
+ * | | |CMPDAT will load to CMPBUF at the center point of a period.
+ * |[13:8] |WINLDENn |Window Load Enable
+ * | | |Each bit n controls the corresponding PWM channel n.
+ * | | |0 = PERIOD will load to PBUF at the end point of each period.
+ * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit.
+ * | | |1 = PERIOD will load to PBUF at the end point of each period.
+ * | | |CMPDAT will load to CMPBUF at the end point of each period when valid reload window is set.
+ * | | |The valid reload window is set by software write 1 to PWM_LOAD register and cleared by hardware after load success.
+ * |[21:16] |IMMLDENn |Immediately Load Enable
+ * | | |Each bit n controls the corresponding PWM channel n.
+ * | | |0 = PERIOD will load to PBUF at the end point of each period.
+ * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit.
+ * | | |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT.
+ * | | |Note: If IMMLDENn is enabled, WINLDENn and CTRLDn will be invalid.
+ * |[24] |GROUPEN |Group Function Enable
+ * | | |0 = The output waveform of each PWM channel are independent.
+ * | | |1 = Unify the PWM_CH2 and PWM_CH4 to output the same waveform as PWM_CH0 and unify the PWM_CH3 and PWM_CH5 to output the same waveform as PWM_CH1.
+ * |[30] |DBGHALT |ICE Debug Mode Counter Halt (Write Protect)
+ * | | |If counter halt is enabled, PWM all counters will keep current value until exit ICE debug mode.
+ * | | |0 = ICE debug mode counter halt disable.
+ * | | |1 = ICE debug mode counter halt enable.
+ * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
+ * |[31] |DBGTRIOFF |ICE Debug Mode Acknowledge Disable (Write Protect)
+ * | | |0 = ICE debug mode acknowledgement effects PWM output.
+ * | | |PWM pin will be forced as tri-state while ICE debug mode acknowledged.
+ * | | |1 = ICE debug mode acknowledgement disabled.
+ * | | |PWM pin will keep output no matter ICE debug mode acknowledged or not.
+ * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
+ * @var PWM_T::CTL1
+ * Offset: 0x04 PWM Control Register 1
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[11:0] |CNTTYPEn |PWM Counter Behavior Type
+ * | | |Each bit n controls corresponding PWM channel n.
+ * | | |00 = Up counter type (supports in capture mode).
+ * | | |01 = Down count type (supports in capture mode).
+ * | | |10 = Up-down counter type.
+ * | | |11 = Reserved.
+ * |[21:16] |CNTMODEn |PWM Counter Mode
+ * | | |Each bit n controls the corresponding PWM channel n.
+ * | | |0 = Auto-reload mode.
+ * | | |1 = One-shot mode.
+ * |[26:24] |OUTMODEn |PWM Output Mode
+ * | | |Each bit n controls the
+ * | | |output mode of
+ * | | |corresponding PWM channel n.
+ * | | |0 = PWM independent mode.
+ * | | |1 = PWM complementary mode.
+ * | | |Note: When operating in group function, these bits must all set to the same mode.
+ * @var PWM_T::SYNC
+ * Offset: 0x08 PWM Synchronization Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[2:0] |PHSENn |SYNC Phase Enable
+ * | | |Each bit n controls corresponding PWM channel n.
+ * | | |0 = PWM counter disable to load PHS value.
+ * | | |1 = PWM counter enable to load PHS value.
+ * |[13:8] |SINSRCn |PWM_SYNC_IN Source Selection
+ * | | |Each bit n controls corresponding PWM channel n.
+ * | | |00 = Synchronize source from SYNC_IN or SWSYNC.
+ * | | |01 = Counter equal to 0.
+ * | | |10 = Counter equal to PWM_CMPDATm, m denotes 1, 3, 5.
+ * | | |11 = SYNC_OUT will not be generated.
+ * |[16] |SNFLTEN |PWM_SYNC_IN Noise Filter Enable
+ * | | |0 = Noise filter of input pin PWM_SYNC_IN is Disabled.
+ * | | |1 = Noise filter of input pin PWM_SYNC_IN is Enabled.
+ * |[19:17] |SFLTCSEL |SYNC Edge Detector Filter Clock Selection
+ * | | |000 = Filter clock = HCLK.
+ * | | |001 = Filter clock = HCLK/2.
+ * | | |010 = Filter clock = HCLK/4.
+ * | | |011 = Filter clock = HCLK/8.
+ * | | |100 = Filter clock = HCLK/16.
+ * | | |101 = Filter clock = HCLK/32.
+ * | | |110 = Filter clock = HCLK/64.
+ * | | |111 = Filter clock = HCLK/128.
+ * |[22:20] |SFLTCNT |SYNC Edge Detector Filter Count
+ * | | |The register bits control the counter number of edge detector.
+ * |[23] |SINPINV |SYNC Input Pin Inverse
+ * | | |0 = The state of pin SYNC is passed to the negative edge detector.
+ * | | |1 = The inverted state of pin SYNC is passed to the negative edge detector.
+ * |[26:24] |PHSDIRn |PWM Phase Direction Control
+ * | | |Each bit n controls corresponding PWM channel n.
+ * | | |0 = Control PWM counter count decrement after synchronizing.
+ * | | |1 = Control PWM counter count increment after synchronizing.
+ * @var PWM_T::SWSYNC
+ * Offset: 0x0C PWM Software Control Synchronization Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[2:0] |SWSYNCn |Software SYNC Function
+ * | | |Each bit n controls corresponding PWM channel n.
+ * | | |When SINSRCn (PWM_SYNC[13:8]) is selected to 0, SYNC_OUT source is come from SYNC_IN or this bit.
+ * @var PWM_T::CLKSRC
+ * Offset: 0x10 PWM Clock Source Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[2:0] |ECLKSRC0 |PWM_CH01 External Clock Source Select
+ * | | |000 = PWMx_CLK, x denotes 0 or 1.
+ * | | |001 = TIMER0 overflow.
+ * | | |010 = TIMER1 overflow.
+ * | | |011 = TIMER2 overflow.
+ * | | |100 = TIMER3 overflow.
+ * | | |Others = Reserved.
+ * |[10:8] |ECLKSRC2 |PWM_CH23 External Clock Source Select
+ * | | |000 = PWMx_CLK, x denotes 0 or 1.
+ * | | |001 = TIMER0 overflow.
+ * | | |010 = TIMER1 overflow.
+ * | | |011 = TIMER2 overflow.
+ * | | |100 = TIMER3 overflow.
+ * | | |Others = Reserved.
+ * |[18:16] |ECLKSRC4 |PWM_CH45 External Clock Source Select
+ * | | |000 = PWMx_CLK, x denotes 0 or 1.
+ * | | |001 = TIMER0 overflow.
+ * | | |010 = TIMER1 overflow.
+ * | | |011 = TIMER2 overflow.
+ * | | |100 = TIMER3 overflow.
+ * | | |Others = Reserved.
+ * @var PWM_T::CLKPSC0_1
+ * Offset: 0x14 PWM Clock Pre-scale Register 0
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[11:0] |CLKPSC |PWM Counter Clock Pre-Scale
+ * | | |The clock of PWM counter is decided by clock prescaler.
+ * | | |Each PWM pair share one PWM counter clock prescaler.
+ * | | |The clock of PWM counter is divided by (CLKPSC+ 1).
+ * @var PWM_T::CLKPSC2_3
+ * Offset: 0x18 PWM Clock Pre-scale Register 2
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[11:0] |CLKPSC |PWM Counter Clock Pre-Scale
+ * | | |The clock of PWM counter is decided by clock prescaler.
+ * | | |Each PWM pair share one PWM counter clock prescaler.
+ * | | |The clock of PWM counter is divided by (CLKPSC+ 1).
+ * @var PWM_T::CLKPSC4_5
+ * Offset: 0x1C PWM Clock Pre-scale Register 4
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[11:0] |CLKPSC |PWM Counter Clock Pre-Scale
+ * | | |The clock of PWM counter is decided by clock prescaler.
+ * | | |Each PWM pair share one PWM counter clock prescaler.
+ * | | |The clock of PWM counter is divided by (CLKPSC+ 1).
+ * @var PWM_T::CNTEN
+ * Offset: 0x20 PWM Counter Enable Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[5:0] |CNTENn |PWM Counter Enable
+ * | | |Each bit n controls the corresponding PWM channel n.
+ * | | |0 = PWM Counter and clock prescaler Stop Running.
+ * | | |1 = PWM Counter and clock prescaler Start Running.
+ * @var PWM_T::CNTCLR
+ * Offset: 0x24 PWM Clear Counter Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[5:0] |CNTCLRn |Clear PWM Counter Control Bit
+ * | | |It is automatically cleared by hardware. Each bit n controls the corresponding PWM channel n.
+ * | | |0 = No effect.
+ * | | |1 = Clear 16-bit PWM counter to 0000H.
+ * @var PWM_T::LOAD
+ * Offset: 0x28 PWM Load Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[5:0] |LOADn |Re-Load PWM Comparator Register (CMPDAT) Control Bit
+ * | | |This bit is software write, hardware clear when current PWM period end.
+ * | | |Each bit n controls the corresponding PWM channel n.
+ * | | |Write Operation:
+ * | | |0 = No effect.
+ * | | |1 = Set load window of window loading mode.
+ * | | |Read Operation:
+ * | | |0 = No load window is set.
+ * | | |1 = Load window is set.
+ * | | |Note: This bit only use in window loading mode, WINLDENn(PWM_CTL0[13:8]) = 1.
+ * @var PWM_T::PERIOD
+ * Offset: 0x30~0x44 PWM Period Register 0~5
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |PERIOD |PWM Period Register
+ * | | |Up-Count mode: In this mode, PWM counter counts from 0 to PERIOD, and restarts from 0.
+ * | | |Down-Count mode: In this mode, PWM counter counts from PERIOD to 0, and restarts from PERIOD.
+ * | | |PWM period time = (PERIOD+1) * PWM_CLK period.
+ * | | |Up-Down-Count mode: In this mode, PWM counter counts from 0 to PERIOD, then decrements to 0 and repeats again.
+ * | | |PWM period time = 2 * PERIOD * PWM_CLK period.
+ * @var PWM_T::CMPDAT
+ * Offset: 0x50~0x64 PWM Comparator Register 0~5
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |CMP |PWM Comparator Register
+ * | | |CMP use to compare with CNTR to generate PWM waveform, interrupt and trigger EADC/DAC.
+ * | | |In independent mode, CMPDAT0~5 denote as 6 independent PWM_CH0~5 compared point.
+ * | | |In complementary mode, CMPDAT0, 2, 4 denote as first compared point, and CMPDAT1, 3, 5 denote as second compared point for the corresponding 3 complementary pairs PWM_CH0 and PWM_CH1, PWM_CH2 and PWM_CH3, PWM_CH4 and PWM_CH5.
+ * @var PWM_T::DTCTL0_1
+ * Offset: 0x70 PWM Dead-Time Control Register 0
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[11:0] |DTCNT |Dead-Time Counter (Write Protect)
+ * | | |The dead-time can be calculated from the following formula:
+ * | | |Dead-time = (DTCNT[11:0]+1) * PWM_CLK period.
+ * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
+ * |[16] |DTEN |Enable Dead-Time Insertion For PWM Pair (PWM_CH0, PWM_CH1) (PWM_CH2, PWM_CH3) (PWM_CH4, PWM_CH5) (Write Protect)
+ * | | |Dead-time insertion is only active when this pair of complementary PWM is enabled.
+ * | | |If dead- time insertion is inactive, the outputs of pin pair are complementary without any delay.
+ * | | |0 = Dead-time insertion Disabled on the pin pair.
+ * | | |1 = Dead-time insertion Enabled on the pin pair.
+ * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
+ * |[24] |DTCKSEL |Dead-Time Clock Select (Write Protect) (M45xD/M45xC Only)
+ * | | |0 = Dead-time clock source from PWM_CLK.
+ * | | |1 = Dead-time clock source from prescaler output.
+ * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
+ * @var PWM_T::DTCTL2_3
+ * Offset: 0x74 PWM Dead-Time Control Register 2
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[11:0] |DTCNT |Dead-Time Counter (Write Protect)
+ * | | |The dead-time can be calculated from the following formula:
+ * | | |Dead-time = (DTCNT[11:0]+1) * PWM_CLK period.
+ * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
+ * |[16] |DTEN |Enable Dead-Time Insertion For PWM Pair (PWM_CH0, PWM_CH1) (PWM_CH2, PWM_CH3) (PWM_CH4, PWM_CH5) (Write Protect)
+ * | | |Dead-time insertion is only active when this pair of complementary PWM is enabled.
+ * | | |If dead- time insertion is inactive, the outputs of pin pair are complementary without any delay.
+ * | | |0 = Dead-time insertion Disabled on the pin pair.
+ * | | |1 = Dead-time insertion Enabled on the pin pair.
+ * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
+ * |[24] |DTCKSEL |Dead-Time Clock Select (Write Protect) (M45xD/M45xC Only)
+ * | | |0 = Dead-time clock source from PWM_CLK.
+ * | | |1 = Dead-time clock source from prescaler output.
+ * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
+ * @var PWM_T::DTCTL4_5
+ * Offset: 0x78 PWM Dead-Time Control Register 4
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[11:0] |DTCNT |Dead-Time Counter (Write Protect)
+ * | | |The dead-time can be calculated from the following formula:
+ * | | |Dead-time = (DTCNT[11:0]+1) * PWM_CLK period.
+ * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
+ * |[16] |DTEN |Enable Dead-Time Insertion For PWM Pair (PWM_CH0, PWM_CH1) (PWM_CH2, PWM_CH3) (PWM_CH4, PWM_CH5) (Write Protect)
+ * | | |Dead-time insertion is only active when this pair of complementary PWM is enabled.
+ * | | |If dead- time insertion is inactive, the outputs of pin pair are complementary without any delay.
+ * | | |0 = Dead-time insertion Disabled on the pin pair.
+ * | | |1 = Dead-time insertion Enabled on the pin pair.
+ * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
+ * |[24] |DTCKSEL |Dead-Time Clock Select (Write Protect) (M45xD/M45xC Only)
+ * | | |0 = Dead-time clock source from PWM_CLK.
+ * | | |1 = Dead-time clock source from prescaler output.
+ * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
+ * @var PWM_T::PHS0_1
+ * Offset: 0x80 PWM Counter Phase Register 0
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |PHS |PWM Synchronous Start Phase Bits
+ * | | |PHS determines the PWM synchronous start phase value. These bits only use in synchronous function.
+ * @var PWM_T::PHS2_3
+ * Offset: 0x84 PWM Counter Phase Register 2
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |PHS |PWM Synchronous Start Phase Bits
+ * | | |PHS determines the PWM synchronous start phase value. These bits only use in synchronous function.
+ * @var PWM_T::PHS4_5
+ * Offset: 0x88 PWM Counter Phase Register 4
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |PHS |PWM Synchronous Start Phase Bits
+ * | | |PHS determines the PWM synchronous start phase value. These bits only use in synchronous function.
+ * @var PWM_T::CNT
+ * Offset: 0x90~0xA4 PWM Counter Register 0~5
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |CNT |PWM Data Register (Read Only)
+ * | | |User can monitor CNTR to know the current value in 16-bit period counter.
+ * |[16] |DIRF |PWM Direction Indicator Flag (Read Only)
+ * | | |0 = Counter is Down count.
+ * | | |1 = Counter is UP count.
+ * @var PWM_T::WGCTL0
+ * Offset: 0xB0 PWM Generation Register 0
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[11:0] |ZPCTLn |PWM Zero Point Control
+ * | | |Each bit n controls the corresponding PWM channel n.
+ * | | |00 = Do nothing.
+ * | | |01 = PWM zero point output Low.
+ * | | |10 = PWM zero point output High.
+ * | | |11 = PWM zero point output Toggle.
+ * | | |PWM can control output level when PWM counter count to zero.
+ * |[27:16] |PRDPCTLn |PWM Period (Center) Point Control
+ * | | |Each bit n controls the corresponding PWM channel n.
+ * | | |00 = Do nothing.
+ * | | |01 = PWM period (center) point output Low.
+ * | | |10 = PWM period (center) point output High.
+ * | | |11 = PWM period (center) point output Toggle.
+ * | | |PWM can control output level when PWM counter count to (PERIODn+1).
+ * | | |Note: This bit is center point control when PWM counter operating in up-down counter type.
+ * @var PWM_T::WGCTL1
+ * Offset: 0xB4 PWM Generation Register 1
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[11:0] |CMPUCTLn |PWM Compare Up Point Control
+ * | | |Each bit n controls the corresponding PWM channel n.
+ * | | |00 = Do nothing.
+ * | | |01 = PWM compare up point output Low.
+ * | | |10 = PWM compare up point output High.
+ * | | |11 = PWM compare up point output Toggle.
+ * | | |PWM can control output level when PWM counter up count to CMPDAT.
+ * | | |Note: In complementary mode, CMPUCTL1, 3, 5 use as another CMPUCTL for channel 0, 2, 4.
+ * |[27:16] |CMPDCTLn |PWM Compare Down Point Control
+ * | | |Each bit n controls the corresponding PWM channel n.
+ * | | |00 = Do nothing.
+ * | | |01 = PWM compare down point output Low.
+ * | | |10 = PWM compare down point output High.
+ * | | |11 = PWM compare down point output Toggle.
+ * | | |PWM can control output level when PWM counter down count to CMPDAT.
+ * | | |Note: In complementary mode, CMPDCTL1, 3, 5 use as another CMPDCTL for channel 0, 2, 4.
+ * @var PWM_T::MSKEN
+ * Offset: 0xB8 PWM Mask Enable Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[5:0] |MSKENn |PWM Mask Enable
+ * | | |Each bit n controls the corresponding PWM channel n.
+ * | | |The PWM output signal will be masked when this bit is enabled.
+ * | | |The corresponding PWM channel n will output MSKDATn (PWM_MSK[5:0]) data.
+ * | | |0 = PWM output signal is non-masked.
+ * | | |1 = PWM output signal is masked and output MSKDATn data.
+ * @var PWM_T::MSK
+ * Offset: 0xBC PWM Mask Data Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[5:0] |MSKDATn |PWM Mask Data Bit
+ * | | |This data bit control the state of PWMn output pin, if corresponding mask function is enabled.
+ * | | |Each bit n controls the corresponding PWM channel n.
+ * | | |0 = Output logic low to PWMn.
+ * | | |1 = Output logic high to PWMn.
+ * @var PWM_T::BNF
+ * Offset: 0xC0 PWM Brake Noise Filter Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |BRK0NFEN |PWM Brake 0 Noise Filter Enable
+ * | | |0 = Noise filter of PWM Brake 0 Disabled.
+ * | | |1 = Noise filter of PWM Brake 0 Enabled.
+ * |[3:1] |BRK0NFSEL |Brake 0 Edge Detector Filter Clock Selection
+ * | | |000 = Filter clock = HCLK.
+ * | | |001 = Filter clock = HCLK/2.
+ * | | |010 = Filter clock = HCLK/4.
+ * | | |011 = Filter clock = HCLK/8.
+ * | | |100 = Filter clock = HCLK/16.
+ * | | |101 = Filter clock = HCLK/32.
+ * | | |110 = Filter clock = HCLK/64.
+ * | | |111 = Filter clock = HCLK/128.
+ * |[6:4] |BRK0FCNT |Brake 0 Edge Detector Filter Count
+ * | | |The register bits control the Brake0 filter counter to count from 0 to BRK1FCNT.
+ * |[7] |BRK0PINV |Brake 0 Pin Inverse
+ * | | |0 = The state of pin PWMx_BRAKE0 is passed to the negative edge detector.
+ * | | |1 = The inverted state of pin PWMx_BRAKE10 is passed to the negative edge detector.
+ * |[8] |BRK1NFEN |PWM Brake 1 Noise Filter Enable
+ * | | |0 = Noise filter of PWM Brake 1 Disabled.
+ * | | |1 = Noise filter of PWM Brake 1 Enabled.
+ * |[11:9] |BRK1NFSEL |Brake 1 Edge Detector Filter Clock Selection
+ * | | |000 = Filter clock = HCLK.
+ * | | |001 = Filter clock = HCLK/2.
+ * | | |010 = Filter clock = HCLK/4.
+ * | | |011 = Filter clock = HCLK/8.
+ * | | |100 = Filter clock = HCLK/16.
+ * | | |101 = Filter clock = HCLK/32.
+ * | | |110 = Filter clock = HCLK/64.
+ * | | |111 = Filter clock = HCLK/128.
+ * |[14:12] |BRK1FCNT |Brake 1 Edge Detector Filter Count
+ * | | |The register bits control the Brake1 filter counter to count from 0 to BRK1FCNT.
+ * |[15] |BRK1PINV |Brake 1 Pin Inverse
+ * | | |0 = The state of pin PWMx_BRAKE1 is passed to the negative edge detector.
+ * | | |1 = The inverted state of pin PWMx_BRAKE1 is passed to the negative edge detector.
+ * |[16] |BK0SRC |Brake 0 Pin Source Select (M45xD/M45xC Only)
+ * | | |For PWM0 setting:
+ * | | |0 = Brake 0 pin source come from PWM0_BRAKE0.
+ * | | |1 = Brake 0 pin source come from PWM1_BRAKE0.
+ * | | |For PWM1 setting:
+ * | | |0 = Brake 0 pin source come from PWM1_BRAKE0.
+ * | | |1 = Brake 0 pin source come from PWM0_BRAKE0.
+ * |[24] |BK1SRC |Brake 1 Pin Source Select (M45xD/M45xC Only)
+ * | | |For PWM0 setting:
+ * | | |0 = Brake 1 pin source come from PWM0_BRAKE1.
+ * | | |1 = Brake 1 pin source come from PWM1_BRAKE1.
+ * | | |For PWM1 setting:
+ * | | |0 = Brake 1 pin source come from PWM1_BRAKE1.
+ * | | |1 = Brake 1 pin source come from PWM0_BRAKE1.
+ * @var PWM_T::FAILBRK
+ * Offset: 0xC4 PWM System Fail Brake Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |CSSBRKEN |Clock Security System Detection Trigger PWM Brake Function 0 Enable
+ * | | |0 = Brake Function triggered by CSS detection Disabled.
+ * | | |1 = Brake Function triggered by CSS detection Enabled.
+ * |[1] |BODBRKEN |Brown-Out Detection Trigger PWM Brake Function 0 Enable
+ * | | |0 = Brake Function triggered by BOD Disabled.
+ * | | |1 = Brake Function triggered by BOD Enabled.
+ * |[2] |RAMBRKEN |SRAM Parity Error Detection Trigger PWM Brake Function 0 Enable
+ * | | |0 = Brake Function triggered by SRAM parity error detection Disabled.
+ * | | |1 = Brake Function triggered by SRAM parity error detection Enabled.
+ * |[3] |CORBRKEN |Core Lockup Detection Trigger PWM Brake Function 0 Enable
+ * | | |0 = Brake Function triggered by Core lockup detection Disabled.
+ * | | |1 = Brake Function triggered by Core lockup detection Enabled.
+ * @var PWM_T::BRKCTL0_1
+ * Offset: 0xC8 PWM Brake Edge Detect Control Register 0
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |CPO0EBEN |Enable ACMP0_O Digital Output As Edge-Detect Brake Source (Write Protect)
+ * | | |0 = ACMP0_O as edge-detect brake source Disabled.
+ * | | |1 = ACMP0_O as edge-detect brake source Enabled.
+ * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
+ * |[1] |CPO1EBEN |Enable ACMP1_O Digital Output As Edge-Detect Brake Source (Write Protect)
+ * | | |0 = ACMP1_O as edge-detect brake source Disabled.
+ * | | |1 = ACMP1_O as edge-detect brake source Enabled.
+ * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
+ * |[4] |BRKP0EEN |Enable PWMx_BRAKE0 Pin As Edge-Detect Brake Source (Write Protect)
+ * | | |0 = BKP0 pin as edge-detect brake source Disabled.
+ * | | |1 = BKP0 pin as edge-detect brake source Enabled.
+ * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
+ * |[5] |BRKP1EEN |Enable PWMx_BRAKE1 Pin As Edge-Detect Brake Source (Write Protect)
+ * | | |0 = BKP1 pin as edge-detect brake source Disabled.
+ * | | |1 = BKP1 pin as edge-detect brake source Enabled.
+ * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
+ * |[7] |SYSEBEN |Enable System Fail As Edge-Detect Brake Source (Write Protect)
+ * | | |0 = System Fail condition as edge-detect brake source Disabled.
+ * | | |1 = System Fail condition as edge-detect brake source Enabled.
+ * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
+ * |[8] |CPO0LBEN |Enable ACMP0_O Digital Output As Level-Detect Brake Source (Write Protect)
+ * | | |0 = ACMP0_O as level-detect brake source Disabled.
+ * | | |1 = ACMP0_O as level-detect brake source Enabled.
+ * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
+ * |[9] |CPO1LBEN |Enable ACMP1_O Digital Output As Level-Detect Brake Source (Write Protect)
+ * | | |0 = ACMP1_O as level-detect brake source Disabled.
+ * | | |1 = ACMP1_O as level-detect brake source Enabled.
+ * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
+ * |[12] |BRKP0LEN |Enable BKP0 Pin As Level-Detect Brake Source (Write Protect)
+ * | | |0 = PWMx_BRAKE0 pin as level-detect brake source Disabled.
+ * | | |1 = PWMx_BRAKE0 pin as level-detect brake source Enabled.
+ * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
+ * |[13] |BRKP1LEN |Enable BKP1 Pin As Level-Detect Brake Source (Write Protect)
+ * | | |0 = PWMx_BRAKE1 pin as level-detect brake source Disabled.
+ * | | |1 = PWMx_BRAKE1 pin as level-detect brake source Enabled.
+ * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
+ * |[15] |SYSLBEN |Enable System Fail As Level-Detect Brake Source (Write Protect)
+ * | | |0 = System Fail condition as level-detect brake source Disabled.
+ * | | |1 = System Fail condition as level-detect brake source Enabled.
+ * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
+ * |[17:16] |BRKAEVEN |PWM Brake Action Select For Even Channel (Write Protect)
+ * | | |00 = PWM even channel level-detect brake function not affect channel output.
+ * | | |01 = PWM even channel output tri-state when level-detect brake happened.
+ * | | |10 = PWM even channel output low level when level-detect brake happened.
+ * | | |11 = PWM even channel output high level when level-detect brake happened.
+ * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
+ * |[19:18] |BRKAODD |PWM Brake Action Select For Odd Channel (Write Protect)
+ * | | |00 = PWM odd channel level-detect brake function not affect channel output.
+ * | | |01 = PWM odd channel output tri-state when level-detect brake happened.
+ * | | |10 = PWM odd channel output low level when level-detect brake happened.
+ * | | |11 = PWM odd channel output high level when level-detect brake happened.
+ * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
+ * @var PWM_T::BRKCTL2_3
+ * Offset: 0xCC PWM Brake Edge Detect Control Register 2
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |CPO0EBEN |Enable ACMP0_O Digital Output As Edge-Detect Brake Source (Write Protect)
+ * | | |0 = ACMP0_O as edge-detect brake source Disabled.
+ * | | |1 = ACMP0_O as edge-detect brake source Enabled.
+ * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
+ * |[1] |CPO1EBEN |Enable ACMP1_O Digital Output As Edge-Detect Brake Source (Write Protect)
+ * | | |0 = ACMP1_O as edge-detect brake source Disabled.
+ * | | |1 = ACMP1_O as edge-detect brake source Enabled.
+ * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
+ * |[4] |BRKP0EEN |Enable PWMx_BRAKE0 Pin As Edge-Detect Brake Source (Write Protect)
+ * | | |0 = BKP0 pin as edge-detect brake source Disabled.
+ * | | |1 = BKP0 pin as edge-detect brake source Enabled.
+ * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
+ * |[5] |BRKP1EEN |Enable PWMx_BRAKE1 Pin As Edge-Detect Brake Source (Write Protect)
+ * | | |0 = BKP1 pin as edge-detect brake source Disabled.
+ * | | |1 = BKP1 pin as edge-detect brake source Enabled.
+ * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
+ * |[7] |SYSEBEN |Enable System Fail As Edge-Detect Brake Source (Write Protect)
+ * | | |0 = System Fail condition as edge-detect brake source Disabled.
+ * | | |1 = System Fail condition as edge-detect brake source Enabled.
+ * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
+ * |[8] |CPO0LBEN |Enable ACMP0_O Digital Output As Level-Detect Brake Source (Write Protect)
+ * | | |0 = ACMP0_O as level-detect brake source Disabled.
+ * | | |1 = ACMP0_O as level-detect brake source Enabled.
+ * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
+ * |[9] |CPO1LBEN |Enable ACMP1_O Digital Output As Level-Detect Brake Source (Write Protect)
+ * | | |0 = ACMP1_O as level-detect brake source Disabled.
+ * | | |1 = ACMP1_O as level-detect brake source Enabled.
+ * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
+ * |[12] |BRKP0LEN |Enable BKP0 Pin As Level-Detect Brake Source (Write Protect)
+ * | | |0 = PWMx_BRAKE0 pin as level-detect brake source Disabled.
+ * | | |1 = PWMx_BRAKE0 pin as level-detect brake source Enabled.
+ * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
+ * |[13] |BRKP1LEN |Enable BKP1 Pin As Level-Detect Brake Source (Write Protect)
+ * | | |0 = PWMx_BRAKE1 pin as level-detect brake source Disabled.
+ * | | |1 = PWMx_BRAKE1 pin as level-detect brake source Enabled.
+ * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
+ * |[15] |SYSLBEN |Enable System Fail As Level-Detect Brake Source (Write Protect)
+ * | | |0 = System Fail condition as level-detect brake source Disabled.
+ * | | |1 = System Fail condition as level-detect brake source Enabled.
+ * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
+ * |[17:16] |BRKAEVEN |PWM Brake Action Select For Even Channel (Write Protect)
+ * | | |00 = PWM even channel level-detect brake function not affect channel output.
+ * | | |01 = PWM even channel output tri-state when level-detect brake happened.
+ * | | |10 = PWM even channel output low level when level-detect brake happened.
+ * | | |11 = PWM even channel output high level when level-detect brake happened.
+ * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
+ * |[19:18] |BRKAODD |PWM Brake Action Select For Odd Channel (Write Protect)
+ * | | |00 = PWM odd channel level-detect brake function not affect channel output.
+ * | | |01 = PWM odd channel output tri-state when level-detect brake happened.
+ * | | |10 = PWM odd channel output low level when level-detect brake happened.
+ * | | |11 = PWM odd channel output high level when level-detect brake happened.
+ * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
+ * @var PWM_T::BRKCTL4_5
+ * Offset: 0xD0 PWM Brake Edge Detect Control Register 4
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |CPO0EBEN |Enable ACMP0_O Digital Output As Edge-Detect Brake Source (Write Protect)
+ * | | |0 = ACMP0_O as edge-detect brake source Disabled.
+ * | | |1 = ACMP0_O as edge-detect brake source Enabled.
+ * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
+ * |[1] |CPO1EBEN |Enable ACMP1_O Digital Output As Edge-Detect Brake Source (Write Protect)
+ * | | |0 = ACMP1_O as edge-detect brake source Disabled.
+ * | | |1 = ACMP1_O as edge-detect brake source Enabled.
+ * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
+ * |[4] |BRKP0EEN |Enable PWMx_BRAKE0 Pin As Edge-Detect Brake Source (Write Protect)
+ * | | |0 = BKP0 pin as edge-detect brake source Disabled.
+ * | | |1 = BKP0 pin as edge-detect brake source Enabled.
+ * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
+ * |[5] |BRKP1EEN |Enable PWMx_BRAKE1 Pin As Edge-Detect Brake Source (Write Protect)
+ * | | |0 = BKP1 pin as edge-detect brake source Disabled.
+ * | | |1 = BKP1 pin as edge-detect brake source Enabled.
+ * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
+ * |[7] |SYSEBEN |Enable System Fail As Edge-Detect Brake Source (Write Protect)
+ * | | |0 = System Fail condition as edge-detect brake source Disabled.
+ * | | |1 = System Fail condition as edge-detect brake source Enabled.
+ * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
+ * |[8] |CPO0LBEN |Enable ACMP0_O Digital Output As Level-Detect Brake Source (Write Protect)
+ * | | |0 = ACMP0_O as level-detect brake source Disabled.
+ * | | |1 = ACMP0_O as level-detect brake source Enabled.
+ * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
+ * |[9] |CPO1LBEN |Enable ACMP1_O Digital Output As Level-Detect Brake Source (Write Protect)
+ * | | |0 = ACMP1_O as level-detect brake source Disabled.
+ * | | |1 = ACMP1_O as level-detect brake source Enabled.
+ * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
+ * |[12] |BRKP0LEN |Enable BKP0 Pin As Level-Detect Brake Source (Write Protect)
+ * | | |0 = PWMx_BRAKE0 pin as level-detect brake source Disabled.
+ * | | |1 = PWMx_BRAKE0 pin as level-detect brake source Enabled.
+ * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
+ * |[13] |BRKP1LEN |Enable BKP1 Pin As Level-Detect Brake Source (Write Protect)
+ * | | |0 = PWMx_BRAKE1 pin as level-detect brake source Disabled.
+ * | | |1 = PWMx_BRAKE1 pin as level-detect brake source Enabled.
+ * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
+ * |[15] |SYSLBEN |Enable System Fail As Level-Detect Brake Source (Write Protect)
+ * | | |0 = System Fail condition as level-detect brake source Disabled.
+ * | | |1 = System Fail condition as level-detect brake source Enabled.
+ * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
+ * |[17:16] |BRKAEVEN |PWM Brake Action Select For Even Channel (Write Protect)
+ * | | |00 = PWM even channel level-detect brake function not affect channel output.
+ * | | |01 = PWM even channel output tri-state when level-detect brake happened.
+ * | | |10 = PWM even channel output low level when level-detect brake happened.
+ * | | |11 = PWM even channel output high level when level-detect brake happened.
+ * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
+ * |[19:18] |BRKAODD |PWM Brake Action Select For Odd Channel (Write Protect)
+ * | | |00 = PWM odd channel level-detect brake function not affect channel output.
+ * | | |01 = PWM odd channel output tri-state when level-detect brake happened.
+ * | | |10 = PWM odd channel output low level when level-detect brake happened.
+ * | | |11 = PWM odd channel output high level when level-detect brake happened.
+ * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
+ * @var PWM_T::POLCTL
+ * Offset: 0xD4 PWM Pin Polar Inverse Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[5:0] |PINVn |PWM PIN Polar Inverse Control
+ * | | |The register controls polarity state of PWM output.
+ * | | |Each bit n controls the corresponding PWM channel n.
+ * | | |0 = PWM output polar inverse Disabled.
+ * | | |1 = PWM output polar inverse Enabled.
+ * @var PWM_T::POEN
+ * Offset: 0xD8 PWM Output Enable Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[5:0] |POENn |PWM Pin Output Enable
+ * | | |Each bit n controls the corresponding PWM channel n.
+ * | | |0 = PWM pin at tri-state.
+ * | | |1 = PWM pin in output mode.
+ * @var PWM_T::SWBRK
+ * Offset: 0xDC PWM Software Brake Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[2:0] |BRKETRGn |PWM Edge Brake Software Trigger (Write Only) (Write Protect) (M45xD/M45xC Only)
+ * | | |Each bit n controls the corresponding PWM pair n.
+ * | | |Write 1 to this bit will trigger edge brake, and set BRKEIFn to 1 in PWM_INTSTS1 register.
+ * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
+ * |[10:8] |BRKLTRGn |PWM Level Brake Software Trigger (Write Only) (Write Protect)
+ * | | |Each bit n controls the corresponding PWM pair n.
+ * | | |Write 1 to this bit will trigger level brake, and set BRKLIFn to 1 in PWM_INTSTS1 register.
+ * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
+ * @var PWM_T::INTEN0
+ * Offset: 0xE0 PWM Interrupt Enable Register 0
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[5:0] |ZIENn |PWM Zero Point Interrupt Enable
+ * | | |Each bit n controls the corresponding PWM channel n.
+ * | | |0 = Zero point interrupt Disabled.
+ * | | |1 = Zero point interrupt Enabled.
+ * | | |Note: Odd channels will read always 0 at complementary mode.
+ * |[7] |IFAIEN0_1 |PWM_CH0/1 Interrupt Flag Accumulator Interrupt Enable
+ * | | |0 = Interrupt Flag accumulator interrupt Disabled.
+ * | | |1 = Interrupt Flag accumulator interrupt Enabled.
+ * |[13:8] |PIENn |PWM Period Point Interrupt Enable
+ * | | |Each bit n controls the corresponding PWM channel n.
+ * | | |0 = Period point interrupt Disabled.
+ * | | |1 = Period point interrupt Enabled.
+ * | | |Note1: When up-down counter type period point means center point.
+ * | | |Note2: Odd channels will read always 0 at complementary mode.
+ * |[15] |IFAIEN2_3 |PWM_CH2/3 Interrupt Flag Accumulator Interrupt Enable
+ * | | |0 = Interrupt Flag accumulator interrupt Disabled.
+ * | | |1 = Interrupt Flag accumulator interrupt Enabled.
+ * |[21:16] |CMPUIENn |PWM Compare Up Count Interrupt Enable
+ * | | |Each bit n controls the corresponding PWM channel n.
+ * | | |0 = Compare up count interrupt Disabled.
+ * | | |1 = Compare up count interrupt Enabled.
+ * | | |Note: In complementary mode, CMPUIEN1, 3, 5 use as another CMPUIEN for channel 0, 2, 4.
+ * |[23] |IFAIEN4_5 |PWM_CH4/5 Interrupt Flag Accumulator Interrupt Enable
+ * | | |0 = Interrupt Flag accumulator interrupt Disabled.
+ * | | |1 = Interrupt Flag accumulator interrupt Enabled.
+ * |[29:24] |CMPDIENn |PWM Compare Down Count Interrupt Enable
+ * | | |Each bit n controls the corresponding PWM channel n.
+ * | | |0 = Compare down count interrupt Disabled.
+ * | | |1 = Compare down count interrupt Enabled.
+ * | | |Note: In complementary mode, CMPDIEN1, 3, 5 use as another CMPDIEN for channel 0, 2, 4.
+ * @var PWM_T::INTEN1
+ * Offset: 0xE4 PWM Interrupt Enable Register 1
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |BRKEIEN0_1|PWM Edge-Detect Brake Interrupt Enable For Channel0/1 (Write Protect)
+ * | | |0 = Edge-detect Brake interrupt for channel0/1 Disabled.
+ * | | |1 = Edge-detect Brake interrupt for channel0/1 Enabled.
+ * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
+ * |[1] |BRKEIEN2_3|PWM Edge-Detect Brake Interrupt Enable For Channel2/3 (Write Protect)
+ * | | |0 = Edge-detect Brake interrupt for channel2/3 Disabled.
+ * | | |1 = Edge-detect Brake interrupt for channel2/3 Enabled.
+ * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
+ * |[2] |BRKEIEN4_5|PWM Edge-Detect Brake Interrupt Enable For Channel4/5 (Write Protect)
+ * | | |0 = Edge-detect Brake interrupt for channel4/5 Disabled.
+ * | | |1 = Edge-detect Brake interrupt for channel4/5 Enabled.
+ * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
+ * |[8] |BRKLIEN0_1|PWM Level-Detect Brake Interrupt Enable For Channel0/1 (Write Protect)
+ * | | |0 = Level-detect Brake interrupt for channel0/1 Disabled.
+ * | | |1 = Level-detect Brake interrupt for channel0/1 Enabled.
+ * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
+ * |[9] |BRKLIEN2_3|PWM Level-Detect Brake Interrupt Enable For Channel2/3 (Write Protect)
+ * | | |0 = Level-detect Brake interrupt for channel2/3 Disabled.
+ * | | |1 = Level-detect Brake interrupt for channel2/3 Enabled.
+ * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
+ * |[10] |BRKLIEN4_5|PWM Level-Detect Brake Interrupt Enable For Channel4/5 (Write Protect)
+ * | | |0 = Level-detect Brake interrupt for channel4/5 Disabled.
+ * | | |1 = Level-detect Brake interrupt for channel4/5 Enabled.
+ * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
+ * @var PWM_T::INTSTS0
+ * Offset: 0xE8 PWM Interrupt Flag Register 0
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[5:0] |ZIFn |PWM Zero Point Interrupt Flag
+ * | | |Each bit n controls the corresponding PWM channel n.
+ * | | |This bit is set by hardware when PWM counter reaches zero, software can write 1 to clear this bit to zero.
+ * |[7] |IFAIF0_1 |PWM_CH0/1 Interrupt Flag Accumulator Interrupt Flag
+ * | | |Flag is set by hardware when condition match IFSEL0_1 in PWM_IFA register, software can clear this bit by writing 1 to it.
+ * |[13:8] |PIFn |PWM Period Point Interrupt Flag
+ * | | |This bit is set by hardware when PWM counter reaches PWM_PERIODn, software can write 1 to clear this bit to zero.
+ * | | |Each bit n controls the corresponding PWM channel n.
+ * |[15] |IFAIF2_3 |PWM_CH2/3 Interrupt Flag Accumulator Interrupt Flag
+ * | | |Flag is set by hardware when condition match IFSEL2_3 in PWM_IFA register, software can clear this bit by writing 1 to it.
+ * |[21:16] |CMPUIFn |PWM Compare Up Count Interrupt Flag
+ * | | |Flag is set by hardware when PWM counter up count and reaches PWM_CMPDATn, software can clear this bit by writing 1 to it.
+ * | | |Each bit n controls the corresponding PWM channel n.
+ * | | |Note1: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection.
+ * | | |Note2: In complementary mode, CMPUIF1, 3, 5 use as another CMPUIF for channel 0, 2, 4.
+ * |[23] |IFAIF4_5 |PWM_CH4/5 Interrupt Flag Accumulator Interrupt Flag
+ * | | |Flag is set by hardware when condition match IFSEL4_5 in PWM_IFA register, software can clear this bit by writing 1 to it.
+ * |[29:24] |CMPDIFn |PWM Compare Down Count Interrupt Flag
+ * | | |Each bit n controls the corresponding PWM channel n.
+ * | | |Flag is set by hardware when PWM counter down count and reaches PWM_CMPDATn, software can clear this bit by writing 1 to it.
+ * | | |Note1: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection.
+ * | | |Note2: In complementary mode, CMPDIF1, 3, 5 use as another CMPDIF for channel 0, 2, 4.
+ * @var PWM_T::INTSTS1
+ * Offset: 0xEC PWM Interrupt Flag Register 1
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |BRKEIF0 |PWM Channel0 Edge-Detect Brake Interrupt Flag (Write Protect)
+ * | | |0 = PWM channel0 edge-detect brake event do not happened.
+ * | | |1 = When PWM channel0 edge-detect brake event happened, this bit is set to 1, writing 1 to clear.
+ * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
+ * |[1] |BRKEIF1 |PWM Channel1 Edge-Detect Brake Interrupt Flag (Write Protect)
+ * | | |0 = PWM channel1 edge-detect brake event do not happened.
+ * | | |1 = When PWM channel1 edge-detect brake event happened, this bit is set to 1, writing 1 to clear.
+ * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
+ * |[2] |BRKEIF2 |PWM Channel2 Edge-Detect Brake Interrupt Flag (Write Protect)
+ * | | |0 = PWM channel2 edge-detect brake event do not happened.
+ * | | |1 = When PWM channel2 edge-detect brake event happened, this bit is set to 1, writing 1 to clear.
+ * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
+ * |[3] |BRKEIF3 |PWM Channel3 Edge-Detect Brake Interrupt Flag (Write Protect)
+ * | | |0 = PWM channel3 edge-detect brake event do not happened.
+ * | | |1 = When PWM channel3 edge-detect brake event happened, this bit is set to 1, writing 1 to clear.
+ * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
+ * |[4] |BRKEIF4 |PWM Channel4 Edge-Detect Brake Interrupt Flag (Write Protect)
+ * | | |0 = PWM channel4 edge-detect brake event do not happened.
+ * | | |1 = When PWM channel4 edge-detect brake event happened, this bit is set to 1, writing 1 to clear.
+ * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
+ * |[5] |BRKEIF5 |PWM Channel5 Edge-Detect Brake Interrupt Flag (Write Protect)
+ * | | |0 = PWM channel5 edge-detect brake event do not happened.
+ * | | |1 = When PWM channel5 edge-detect brake event happened, this bit is set to 1, writing 1 to clear.
+ * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
+ * |[8] |BRKLIF0 |PWM Channel0 Level-Detect Brake Interrupt Flag (Write Protect)
+ * | | |0 = PWM channel0 level-detect brake event do not happened.
+ * | | |1 = When PWM channel0 level-detect brake event happened, this bit is set to 1, writing 1 to clear.
+ * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
+ * |[9] |BRKLIF1 |PWM Channel1 Level-Detect Brake Interrupt Flag (Write Protect)
+ * | | |0 = PWM channel1 level-detect brake event do not happened.
+ * | | |1 = When PWM channel1 level-detect brake event happened, this bit is set to 1, writing 1 to clear.
+ * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
+ * |[10] |BRKLIF2 |PWM Channel2 Level-Detect Brake Interrupt Flag (Write Protect)
+ * | | |0 = PWM channel2 level-detect brake event do not happened.
+ * | | |1 = When PWM channel2 level-detect brake event happened, this bit is set to 1, writing 1 to clear.
+ * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
+ * |[11] |BRKLIF3 |PWM Channel3 Level-Detect Brake Interrupt Flag (Write Protect)
+ * | | |0 = PWM channel3 level-detect brake event do not happened.
+ * | | |1 = When PWM channel3 level-detect brake event happened, this bit is set to 1, writing 1 to clear.
+ * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
+ * |[12] |BRKLIF4 |PWM Channel4 Level-Detect Brake Interrupt Flag (Write Protect)
+ * | | |0 = PWM channel4 level-detect brake event do not happened.
+ * | | |1 = When PWM channel4 level-detect brake event happened, this bit is set to 1, writing 1 to clear.
+ * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
+ * |[13] |BRKLIF5 |PWM Channel5 Level-Detect Brake Interrupt Flag (Write Protect)
+ * | | |0 = PWM channel5 level-detect brake event do not happened.
+ * | | |1 = When PWM channel5 level-detect brake event happened, this bit is set to 1, writing 1 to clear.
+ * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
+ * |[16] |BRKESTS0 |PWM Channel0 Edge-Detect Brake Status
+ * | | |0 = PWM channel0 edge-detect brake state is released.
+ * | | |1 = When PWM channel0 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel0 at brake state, writing 1 to clear.
+ * |[17] |BRKESTS1 |PWM Channel1 Edge-Detect Brake Status
+ * | | |0 = PWM channel1 edge-detect brake state is released.
+ * | | |1 = When PWM channel1 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel1 at brake state, writing 1 to clear.
+ * |[18] |BRKESTS2 |PWM Channel2 Edge-Detect Brake Status
+ * | | |0 = PWM channel2 edge-detect brake state is released.
+ * | | |1 = When PWM channel2 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel2 at brake state, writing 1 to clear.
+ * |[19] |BRKESTS3 |PWM Channel3 Edge-Detect Brake Status
+ * | | |0 = PWM channel3 edge-detect brake state is released.
+ * | | |1 = When PWM channel3 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel3 at brake state, writing 1 to clear.
+ * |[20] |BRKESTS4 |PWM Channel4 Edge-Detect Brake Status
+ * | | |0 = PWM channel4 edge-detect brake state is released.
+ * | | |1 = When PWM channel4 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel4 at brake state, writing 1 to clear.
+ * |[21] |BRKESTS5 |PWM Channel5 Edge-Detect Brake Status
+ * | | |0 = PWM channel5 edge-detect brake state is released.
+ * | | |1 = When PWM channel5 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel5 at brake state, writing 1 to clear.
+ * |[24] |BRKLSTS0 |PWM Channel0 Level-Detect Brake Status (Read Only)
+ * | | |0 = PWM channel0 level-detect brake state is released.
+ * | | |1 = When PWM channel0 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel0 at brake state.
+ * | | |Note: This bit is read only and auto cleared by hardware.
+ * | | |When enabled brake source return to high level, PWM will release brake state until current PWM period finished.
+ * | | |The PWM waveform will start output from next full PWM period.
+ * |[25] |BRKLSTS1 |PWM Channel1 Level-Detect Brake Status (Read Only)
+ * | | |0 = PWM channel1 level-detect brake state is released.
+ * | | |1 = When PWM channel1 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel1 at brake state.
+ * | | |Note: This bit is read only and auto cleared by hardware.
+ * | | |When enabled brake source return to high level, PWM will release brake state until current PWM period finished.
+ * | | |The PWM waveform will start output from next full PWM period.
+ * |[26] |BRKLSTS2 |PWM Channel2 Level-Detect Brake Status (Read Only)
+ * | | |0 = PWM channel2 level-detect brake state is released.
+ * | | |1 = When PWM channel2 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel2 at brake state.
+ * | | |Note: This bit is read only and auto cleared by hardware.
+ * | | |When enabled brake source return to high level, PWM will release brake state until current PWM period finished.
+ * | | |The PWM waveform will start output from next full PWM period.
+ * |[27] |BRKLSTS3 |PWM Channel3 Level-Detect Brake Status (Read Only)
+ * | | |0 = PWM channel3 level-detect brake state is released.
+ * | | |1 = When PWM channel3 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel3 at brake state.
+ * | | |Note: This bit is read only and auto cleared by hardware.
+ * | | |When enabled brake source return to high level, PWM will release brake state until current PWM period finished.
+ * | | |The PWM waveform will start output from next full PWM period.
+ * |[28] |BRKLSTS4 |PWM Channel4 Level-Detect Brake Status (Read Only)
+ * | | |0 = PWM channel4 level-detect brake state is released.
+ * | | |1 = When PWM channel4 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel4 at brake state.
+ * | | |Note: This bit is read only and auto cleared by hardware.
+ * | | |When enabled brake source return to high level, PWM will release brake state until current PWM period finished.
+ * | | |The PWM waveform will start output from next full PWM period.
+ * |[29] |BRKLSTS5 |PWM Channel5 Level-Detect Brake Status (Read Only)
+ * | | |0 = PWM channel5 level-detect brake state is released.
+ * | | |1 = When PWM channel5 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel5 at brake state.
+ * | | |Note: This bit is read only and auto cleared by hardware.
+ * | | |When enabled brake source return to high level, PWM will release brake state until current PWM period finished.
+ * | | |The PWM waveform will start output from next full PWM period.
+ * @var PWM_T::IFA
+ * Offset: 0xF0 PWM Interrupt Flag Accumulator Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[3:0] |IFCNT0_1 |PWM_CH0 And PWM_CH1 Interrupt Flag Counter
+ * | | |The register sets the count number which defines how many times of PWM_CH0 and PWM_CH1 period occurs to set bit IFAIF0_1 to request the PWM period interrupt.
+ * | | |PWM flag will be set in every IFCNT0_1 [3:0] times of PWM period.
+ * |[6:4] |IFSEL0_1 |PWM_CH0 And PWM_CH1 Interrupt Flag Accumulator Source Select
+ * | | |000 = CNT equal to Zero in channel 0.
+ * | | |001 = CNT equal to PERIOD in channel 0.
+ * | | |010 = CNT equal to CMPU in channel 0.
+ * | | |011 = CNT equal to CMPD in channel 0.
+ * | | |100 = CNT equal to Zero in channel 1.
+ * | | |101 = CNT equal to PERIOD in channel 1.
+ * | | |110 = CNT equal to CMPU in channel 1.
+ * | | |111 = CNT equal to CMPD in channel 1.
+ * |[7] |IFAEN0_1 |PWM_CH0 And PWM_CH1 Interrupt Flag Accumulator Enable
+ * | | |0 = PWM_CH0 and PWM_CH1 interrupt flag accumulator disable.
+ * | | |1 = PWM_CH0 and PWM_CH1 interrupt flag accumulator enable.
+ * |[11:8] |IFCNT2_3 |PWM_CH2 And PWM_CH3 Interrupt Flag Counter
+ * | | |The register sets the count number which defines how many times of PWM_CH2 and PWM_CH3 period occurs to set bit IFAIF2_3 to request the PWM period interrupt.
+ * | | |PWM flag will be set in every IFCNT2_3[3:0] times of PWM period.
+ * |[14:12] |IFSEL2_3 |PWM_CH2 And PWM_CH3 Interrupt Flag Accumulator Source Select
+ * | | |000 = CNT equal to Zero in channel 2.
+ * | | |001 = CNT equal to PERIOD in channel 2.
+ * | | |010 = CNT equal to CMPU in channel 2.
+ * | | |011 = CNT equal to CMPD in channel 2.
+ * | | |100 = CNT equal to Zero in channel 3.
+ * | | |101 = CNT equal to PERIOD in channel 3.
+ * | | |110 = CNT equal to CMPU in channel 3.
+ * | | |111 = CNT equal to CMPD in channel 3.
+ * |[15] |IFAEN2_3 |PWM_CH2 And PWM_CH3 Interrupt Flag Accumulator Enable
+ * | | |0 = PWM_CH2 and PWM_CH3 interrupt flag accumulator disable.
+ * | | |1 = PWM_CH2 and PWM_CH3 interrupt flag accumulator enable.
+ * |[19:16] |IFCNT4_5 |PWM_CH4 And PWM_CH5 Interrupt Flag Counter
+ * | | |The register sets the count number which defines how many times of PWM_CH4 and PWM_CH5 period occurs to set bit IFAIF4_5 to request the PWM period interrupt.
+ * | | |PWM flag will be set in every IFCNT4_5[3:0] times of PWM period.
+ * |[22:20] |IFSEL4_5 |PWM_CH4 And PWM_CH5 Interrupt Flag Accumulator Source Select
+ * | | |000 = CNT equal to Zero in channel 4.
+ * | | |001 = CNT equal to PERIOD in channel 4.
+ * | | |010 = CNT equal to CMPU in channel 4.
+ * | | |011 = CNT equal to CMPD in channel 4.
+ * | | |100 = CNT equal to Zero in channel 5.
+ * | | |101 = CNT equal to PERIOD in channel 5.
+ * | | |110 = CNT equal to CMPU in channel 5.
+ * | | |111 = CNT equal to CMPD in channel 5.
+ * |[23] |IFAEN4_5 |PWM_CH4 And PWM_CH5 Interrupt Flag Accumulator Enable
+ * | | |0 = PWM_CH4 and PWM_CH5 interrupt flag accumulator disable.
+ * | | |1 = PWM_CH4 and PWM_CH5 interrupt flag accumulator enable.
+ * @var PWM_T::DACTRGEN
+ * Offset: 0xF4 PWM Trigger DAC Enable Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[5:0] |ZTEn |PWM Zero Point Trigger DAC Enable
+ * | | |0 = PWM period point trigger DAC function Disabled.
+ * | | |1 = PWM period point trigger DAC function Enabled.
+ * | | |PWM can trigger EADC/DAC/DMA to start action when PWM counter down count to zero if this bit is set to 1.
+ * | | |Each bit n controls the corresponding PWM channel n.
+ * |[13:8] |PTEn |PWM Period Point Trigger DAC Enable
+ * | | |0 = PWM period point trigger DAC function Disabled.
+ * | | |1 = PWM period point trigger DAC function Enabled.
+ * | | |PWM can trigger DAC to start action when PWM counter up count to (PERIODn+1) if this bit is set to 1.
+ * | | |Each bit n controls the corresponding PWM channel n.
+ * |[21:16] |CUTRGEn |PWM Compare Up Count Point Trigger DAC Enable
+ * | | |0 = PWM Compare Up point trigger DAC function Disabled.
+ * | | |1 = PWM Compare Up point trigger DAC function Enabled.
+ * | | |PWM can trigger DAC to start action when PWM counter up count to CMPDAT if this bit is set to 1.
+ * | | |Each bit n controls the corresponding PWM channel n.
+ * | | |Note1: This bit should keep at 0 when PWM counter operating in down counter type.
+ * | | |Note2: In complementary mode, CUTRGE1, 3, 5 use as another CUTRGE for channel 0, 2, 4.
+ * |[29:24] |CDTRGEn |PWM Compare Down Count Point Trigger DAC Enable
+ * | | |0 = PWM Compare Down count point trigger DAC function Disabled.
+ * | | |1 = PWM Compare Down count point trigger DAC function Enabled.
+ * | | |PWM can trigger DAC to start action when PWM counter down count to CMPDAT if this bit is set to 1.
+ * | | |Each bit n controls the corresponding PWM channel n.
+ * | | |Note1: This bit should keep at 0 when PWM counter operating in up counter type.
+ * | | |Note2: In complementary mode, CDTRGE1, 3, 5 use as another CDTRGE for channel 0, 2, 4.
+ * @var PWM_T::EADCTS0
+ * Offset: 0xF8 PWM Trigger EADC Source Select Register 0
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[3:0] |TRGSEL0 |PWM_CH0 Trigger EADC Source Select
+ * | | |0000 = PWM_CH0 zero point.
+ * | | |0001 = PWM_CH0 period point.
+ * | | |0010 = PWM_CH0 zero or period point.
+ * | | |0011 = PWM_CH0 up-count CMPDAT point.
+ * | | |0100 = PWM_CH0 down-count CMPDAT point.
+ * | | |0101 = PWM_CH1 zero point.
+ * | | |0110 = PWM_CH1 period point.
+ * | | |0111 = PWM_CH1 zero or period point.
+ * | | |1000 = PWM_CH1 up-count CMPDAT point.
+ * | | |1001 = PWM_CH1 down-count CMPDAT point.
+ * | | |1010 = PWM_CH0 up-count free CMPDAT point.
+ * | | |1011 = PWM_CH0 down-count free CMPDAT point.
+ * | | |1100 = PWM_CH2 up-count free CMPDAT point.
+ * | | |1101 = PWM_CH2 down-count free CMPDAT point.
+ * | | |1110 = PWM_CH4 up-count free CMPDAT point.
+ * | | |1111 = PWM_CH4 down-count free CMPDAT point.
+ * |[7] |TRGEN0 |PWM_CH0 Trigger EADC enable bit
+ * |[11:8] |TRGSEL1 |PWM_CH1 Trigger EADC Source Select
+ * | | |0000 = PWM_CH0 zero point.
+ * | | |0001 = PWM_CH0 period point.
+ * | | |0010 = PWM_CH0 zero or period point.
+ * | | |0011 = PWM_CH0 up-count CMPDAT point.
+ * | | |0100 = PWM_CH0 down-count CMPDAT point.
+ * | | |0101 = PWM_CH1 zero point.
+ * | | |0110 = PWM_CH1 period point.
+ * | | |0111 = PWM_CH1 zero or period point.
+ * | | |1000 = PWM_CH1 up-count CMPDAT point.
+ * | | |1001 = PWM_CH1 down-count CMPDAT point.
+ * | | |1010 = PWM_CH0 up-count free CMPDAT point.
+ * | | |1011 = PWM_CH0 down-count free CMPDAT point.
+ * | | |1100 = PWM_CH2 up-count free CMPDAT point.
+ * | | |1101 = PWM_CH2 down-count free CMPDAT point.
+ * | | |1110 = PWM_CH4 up-count free CMPDAT point.
+ * | | |1111 = PWM_CH4 down-count free CMPDAT point.
+ * |[15] |TRGEN1 |PWM_CH1 Trigger EADC enable bit
+ * |[19:16] |TRGSEL2 |PWM_CH2 Trigger EADC Source Select
+ * | | |0000 = PWM_CH2 zero point.
+ * | | |0001 = PWM_CH2 period point.
+ * | | |0010 = PWM_CH2 zero or period point.
+ * | | |0011 = PWM_CH2 up-count CMPDAT point.
+ * | | |0100 = PWM_CH2 down-count CMPDAT point.
+ * | | |0101 = PWM_CH3 zero point.
+ * | | |0110 = PWM_CH3 period point.
+ * | | |0111 = PWM_CH3 zero or period point.
+ * | | |1000 = PWM_CH3 up-count CMPDAT point.
+ * | | |1001 = PWM_CH3 down-count CMPDAT point.
+ * | | |1010 = PWM_CH0 up-count free CMPDAT point.
+ * | | |1011 = PWM_CH0 down-count free CMPDAT point.
+ * | | |1100 = PWM_CH2 up-count free CMPDAT point.
+ * | | |1101 = PWM_CH2 down-count free CMPDAT point.
+ * | | |1110 = PWM_CH4 up-count free CMPDAT point.
+ * | | |1111 = PWM_CH4 down-count free CMPDAT point.
+ * |[23] |TRGEN2 |PWM_CH2 Trigger EADC enable bit
+ * |[27:24] |TRGSEL3 |PWM_CH3 Trigger EADC Source Select
+ * | | |0000 = PWM_CH2 zero point.
+ * | | |0001 = PWM_CH2 period point.
+ * | | |0010 = PWM_CH2 zero or period point.
+ * | | |0011 = PWM_CH2 up-count CMPDAT point.
+ * | | |0100 = PWM_CH2 down-count CMPDAT point.
+ * | | |0101 = PWM_CH3 zero point.
+ * | | |0110 = PWM_CH3 period point.
+ * | | |0111 = PWM_CH3 zero or period point.
+ * | | |1000 = PWM_CH3 up-count CMPDAT point.
+ * | | |1001 = PWM_CH3 down-count CMPDAT point.
+ * | | |1010 = PWM_CH0 up-count free CMPDAT point.
+ * | | |1011 = PWM_CH0 down-count free CMPDAT point.
+ * | | |1100 = PWM_CH2 up-count free CMPDAT point.
+ * | | |1101 = PWM_CH2 down-count free CMPDAT point.
+ * | | |1110 = PWM_CH4 up-count free CMPDAT point.
+ * | | |1111 = PWM_CH4 down-count free CMPDAT point.
+ * |[31] |TRGEN3 |PWM_CH3 Trigger EADC enable bit
+ * @var PWM_T::EADCTS1
+ * Offset: 0xFC PWM Trigger EADC Source Select Register 1
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[3:0] |TRGSEL4 |PWM_CH4 Trigger EADC Source Select
+ * | | |0000 = PWM_CH4 zero point.
+ * | | |0001 = PWM_CH4 period point.
+ * | | |0010 = PWM_CH4 zero or period point.
+ * | | |0011 = PWM_CH4 up-count CMPDAT point.
+ * | | |0100 = PWM_CH4 down-count CMPDAT point.
+ * | | |0101 = PWM_CH5 zero point.
+ * | | |0110 = PWM_CH5 period point.
+ * | | |0111 = PWM_CH5 zero or period point.
+ * | | |1000 = PWM_CH5 up-count CMPDAT point.
+ * | | |1001 = PWM_CH5 down-count CMPDAT point.
+ * | | |1010 = PWM_CH0 up-count free CMPDAT point.
+ * | | |1011 = PWM_CH0 down-count free CMPDAT point.
+ * | | |1100 = PWM_CH2 up-count free CMPDAT point.
+ * | | |1101 = PWM_CH2 down-count free CMPDAT point.
+ * | | |1110 = PWM_CH4 up-count free CMPDAT point.
+ * | | |1111 = PWM_CH4 down-count free CMPDAT point.
+ * |[7] |TRGEN4 |PWM_CH4 Trigger EADC enable bit
+ * |[11:8] |TRGSEL5 |PWM_CH5 Trigger EADC Source Select
+ * | | |0000 = PWM_CH4 zero point.
+ * | | |0001 = PWM_CH4 period point.
+ * | | |0010 = PWM_CH4 zero or period point.
+ * | | |0011 = PWM_CH4 up-count CMPDAT point.
+ * | | |0100 = PWM_CH4 down-count CMPDAT point.
+ * | | |0101 = PWM_CH5 zero point.
+ * | | |0110 = PWM_CH5 period point.
+ * | | |0111 = PWM_CH5 zero or period point.
+ * | | |1000 = PWM_CH5 up-count CMPDAT point.
+ * | | |1001 = PWM_CH5 down-count CMPDAT point.
+ * | | |1010 = PWM_CH0 up-count free CMPDAT point.
+ * | | |1011 = PWM_CH0 down-count free CMPDAT point.
+ * | | |1100 = PWM_CH2 up-count free CMPDAT point.
+ * | | |1101 = PWM_CH2 down-count free CMPDAT point.
+ * | | |1110 = PWM_CH4 up-count free CMPDAT point.
+ * | | |1111 = PWM_CH4 down-count free CMPDAT point.
+ * |[15] |TRGEN5 |PWM_CH5 Trigger EADC enable bit
+ * @var PWM_T::FTCMPDAT0_1
+ * Offset: 0x100 PWM Free Trigger Compare Register 0
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |FTCMP |PWM Free Trigger Compare Register
+ * | | |FTCMP use to compare with even CNTR to trigger EADC.
+ * | | |FTCMPDAT0, 2, 4 corresponding complementary pairs PWM_CH0and PWM_CH1, PWM_CH2 and PWM_CH3, PWM_CH4 and PWM_CH5.
+ * @var PWM_T::FTCMPDAT2_3
+ * Offset: 0x104 PWM Free Trigger Compare Register 2
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |FTCMP |PWM Free Trigger Compare Register
+ * | | |FTCMP use to compare with even CNTR to trigger EADC.
+ * | | |FTCMPDAT0, 2, 4 corresponding complementary pairs PWM_CH0and PWM_CH1, PWM_CH2 and PWM_CH3, PWM_CH4 and PWM_CH5.
+ * @var PWM_T::FTCMPDAT4_5
+ * Offset: 0x108 PWM Free Trigger Compare Register 4
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |FTCMP |PWM Free Trigger Compare Register
+ * | | |FTCMP use to compare with even CNTR to trigger EADC.
+ * | | |FTCMPDAT0, 2, 4 corresponding complementary pairs PWM_CH0and PWM_CH1, PWM_CH2 and PWM_CH3, PWM_CH4 and PWM_CH5.
+ * @var PWM_T::SSCTL
+ * Offset: 0x110 PWM Synchronous Start Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[5:0] |SSENn |PWM Synchronous Start Function Enable
+ * | | |When synchronous start function is enabled, the PWM counter enable register (PWM_CNTEN) can be enabled by writing PWM synchronous start trigger bit (CNTSEN).
+ * | | |Each bit n controls the corresponding PWM channel n.
+ * | | |0 = PWM synchronous start function Disabled.
+ * | | |1 = PWM synchronous start function Enabled.
+ * @var PWM_T::SSTRG
+ * Offset: 0x114 PWM Synchronous Start Trigger Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |CNTSEN |PWM Counter Synchronous Start Enable (Write Only)
+ * | | |PMW counter synchronous enable function is used to make selected PWM channels (include PWM0_CHx and PWM1_CHx) start counting at the same time.
+ * | | |Writing this bit to 1 will also set the counter enable bit (CNTENn, n denotes channel 0 to 5) if correlated PWM channel counter synchronous start function is enabled.
+ * | | |Note: This bit only present in PWM0_BA.
+ * @var PWM_T::STATUS
+ * Offset: 0x120 PWM Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[5:0] |CNTMAXFn |Time-Base Counter Equal To 0xFFFF Latched Flag
+ * | | |Each bit n controls the corresponding PWM channel n.
+ * | | |0 = indicates the time-base counter never reached its maximum value 0xFFFF.
+ * | | |1 = indicates the time-base counter reached its maximum value, software can write 1 to clear this bit.
+ * |[10:8] |SYNCINFn |Input Synchronization Latched Flag
+ * | | |Each bit n controls the corresponding PWM channel n.
+ * | | |0 = Indicates no SYNC_IN event has occurred.
+ * | | |1 = Indicates an SYNC_IN event has occurred, software can write 1 to clear this bit.
+ * |[21:16] |ADCTRGFn |EADC Start Of Conversion Flag
+ * | | |Each bit n controls the corresponding PWM channel n.
+ * | | |0 = Indicates no EADC start of conversion trigger event has occurred.
+ * | | |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit.
+ * |[24] |DACTRGF |DAC Start Of Conversion Flag
+ * | | |0 = Indicates no DAC start of conversion trigger event has occurred.
+ * | | |1 = Indicates an DAC start of conversion trigger event has occurred, software can write 1 to clear this bit
+ * @var PWM_T::CAPINEN
+ * Offset: 0x200 PWM Capture Input Enable Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[5:0] |CAPINENn |Capture Input Enable
+ * | | |Each bit n controls the corresponding PWM channel n.
+ * | | |0 = PWM Channel capture input path Disabled.
+ * | | |The input of PWM channel capture function is always regarded as 0.
+ * | | |1 = PWM Channel capture input path Enabled.
+ * | | |The input of PWM channel capture function comes from correlative multifunction pin.
+ * @var PWM_T::CAPCTL
+ * Offset: 0x204 PWM Capture Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[5:0] |CAPENn |Capture Function Enable
+ * | | |Each bit n controls the corresponding PWM channel n.
+ * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated.
+ * | | |1 = Capture function Enabled.
+ * | | |Capture latched the PWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch).
+ * |[13:8] |CAPINVn |Capture Inverter Enable
+ * | | |Each bit n controls the corresponding PWM channel n.
+ * | | |0 = Capture source inverter Disabled.
+ * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO.
+ * |[21:16] |RCRLDENn |Rising Capture Reload Enable
+ * | | |Each bit n controls the corresponding PWM channel n.
+ * | | |0 = Rising capture reload counter Disabled.
+ * | | |1 = Rising capture reload counter Enabled.
+ * |[29:24] |FCRLDENn |Falling Capture Reload Enable
+ * | | |Each bit n controls the corresponding PWM channel n.
+ * | | |0 = Falling capture reload counter Disabled.
+ * | | |1 = Falling capture reload counter Enabled.
+ * @var PWM_T::CAPSTS
+ * Offset: 0x208 PWM Capture Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[5:0] |CRLIFOVn |Capture Rising Latch Interrupt Flag Overrun Status (Read Only)
+ * | | |This flag indicates if rising latch happened when the corresponding CRLIF is 1.
+ * | | |Each bit n controls the corresponding PWM channel n.
+ * | | |Note: This bit will be cleared automatically when user clear corresponding CRLIF.
+ * |[13:8] |CFLIFOVn |Capture Falling Latch Interrupt Flag Overrun Status (Read Only)
+ * | | |This flag indicates if falling latch happened when the corresponding CFLIF is 1.
+ * | | |Each bit n controls the corresponding PWM channel n.
+ * | | |Note: This bit will be cleared automatically when user clear corresponding CFLIF.
+ * @var PWM_T::RCAPDAT0
+ * Offset: 0x20C PWM Rising Capture Data Register 0
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |RCAPDAT |PWM Rising Capture Data Register (Read Only)
+ * | | |When rising capture condition happened, the PWM counter value will be saved in this register.
+ * @var PWM_T::FCAPDAT0
+ * Offset: 0x210 PWM Falling Capture Data Register 0
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |FCAPDAT |PWM Falling Capture Data Register (Read Only)
+ * | | |When falling capture condition happened, the PWM counter value will be saved in this register.
+ * @var PWM_T::RCAPDAT1
+ * Offset: 0x214 PWM Rising Capture Data Register 1
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |RCAPDAT |PWM Rising Capture Data Register (Read Only)
+ * | | |When rising capture condition happened, the PWM counter value will be saved in this register.
+ * @var PWM_T::FCAPDAT1
+ * Offset: 0x218 PWM Falling Capture Data Register 1
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |FCAPDAT |PWM Falling Capture Data Register (Read Only)
+ * | | |When falling capture condition happened, the PWM counter value will be saved in this register.
+ * @var PWM_T::RCAPDAT2
+ * Offset: 0x21C PWM Rising Capture Data Register 2
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |RCAPDAT |PWM Rising Capture Data Register (Read Only)
+ * | | |When rising capture condition happened, the PWM counter value will be saved in this register.
+ * @var PWM_T::FCAPDAT2
+ * Offset: 0x220 PWM Falling Capture Data Register 2
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |FCAPDAT |PWM Falling Capture Data Register (Read Only)
+ * | | |When falling capture condition happened, the PWM counter value will be saved in this register.
+ * @var PWM_T::RCAPDAT3
+ * Offset: 0x224 PWM Rising Capture Data Register 3
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |RCAPDAT |PWM Rising Capture Data Register (Read Only)
+ * | | |When rising capture condition happened, the PWM counter value will be saved in this register.
+ * @var PWM_T::FCAPDAT3
+ * Offset: 0x228 PWM Falling Capture Data Register 3
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |FCAPDAT |PWM Falling Capture Data Register (Read Only)
+ * | | |When falling capture condition happened, the PWM counter value will be saved in this register.
+ * @var PWM_T::RCAPDAT4
+ * Offset: 0x22C PWM Rising Capture Data Register 4
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |RCAPDAT |PWM Rising Capture Data Register (Read Only)
+ * | | |When rising capture condition happened, the PWM counter value will be saved in this register.
+ * @var PWM_T::FCAPDAT4
+ * Offset: 0x230 PWM Falling Capture Data Register 4
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |FCAPDAT |PWM Falling Capture Data Register (Read Only)
+ * | | |When falling capture condition happened, the PWM counter value will be saved in this register.
+ * @var PWM_T::RCAPDAT5
+ * Offset: 0x234 PWM Rising Capture Data Register 5
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |RCAPDAT |PWM Rising Capture Data Register (Read Only)
+ * | | |When rising capture condition happened, the PWM counter value will be saved in this register.
+ * @var PWM_T::FCAPDAT5
+ * Offset: 0x238 PWM Falling Capture Data Register 5
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |FCAPDAT |PWM Falling Capture Data Register (Read Only)
+ * | | |When falling capture condition happened, the PWM counter value will be saved in this register.
+ * @var PWM_T::PDMACTL
+ * Offset: 0x23C PWM PDMA Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |CHEN0_1 |Channel 0/1 PDMA Enable
+ * | | |0 = Channel 0/1 PDMA function Disabled.
+ * | | |1 = Channel 0/1 PDMA function Enabled for the channel 0/1 captured data and transfer to memory.
+ * |[2:1] |CAPMOD0_1 |Select PWM_RCAPDAT0/1 Or PWM_FCAPDAT0/1 To Do PDMA Transfer
+ * | | |00 = Reserved.
+ * | | |01 = PWM_RCAPDAT0/1.
+ * | | |10 = PWM_FCAPDAT0/1.
+ * | | |11 = Both PWM_RCAPDAT0/1 and PWM_FCAPDAT0/1.
+ * |[3] |CAPORD0_1 |Capture Channel 0/1 Rising/Falling Order
+ * | | |Set this bit to determine whether the PWM_RCAPDAT0/1 or PWM_FCAPDAT0/1 is the first captured data transferred to memory through PDMA when CAPMOD0_1 = 11.
+ * | | |0 = PWM_FCAPDAT0/1 is the first captured data to memory.
+ * | | |1 = PWM_RCAPDAT0/1 is the first captured data to memory.
+ * |[4] |CHSEL0_1 |Select Channel 0/1 To Do PDMA Transfer
+ * | | |0 = Channel0.
+ * | | |1 = Channel1.
+ * |[8] |CHEN2_3 |Channel 2/3 PDMA Enable
+ * | | |0 = Channel 2/3 PDMA function Disabled.
+ * | | |1 = Channel 2/3 PDMA function Enabled for the channel 2/3 captured data and transfer to memory.
+ * |[10:9] |CAPMOD2_3 |Select PWM_RCAPDAT2/3 Or PWM_FCAODAT2/3 To Do PDMA Transfer
+ * | | |00 = Reserved.
+ * | | |01 = PWM_RCAPDAT2/3.
+ * | | |10 = PWM_FCAPDAT2/3.
+ * | | |11 = Both PWM_RCAPDAT2/3 and PWM_FCAPDAT2/3.
+ * |[11] |CAPORD2_3 |Capture Channel 2/3 Rising/Falling Order
+ * | | |Set this bit to determine whether the PWM_RCAPDAT2/3 or PWM_FCAPDAT2/3 is the first captured data transferred to memory through PDMA when CAPMOD2_3 = 11.
+ * | | |0 = PWM_FCAPDAT2/3 is the first captured data to memory.
+ * | | |1 = PWM_RCAPDAT2/3 is the first captured data to memory.
+ * |[12] |CHSEL2_3 |Select Channel 2/3 To Do PDMA Transfer
+ * | | |0 = Channel2.
+ * | | |1 = Channel3.
+ * |[16] |CHEN4_5 |Channel 4/5 PDMA Enable
+ * | | |0 = Channel 4/5 PDMA function Disabled.
+ * | | |1 = Channel 4/5 PDMA function Enabled for the channel 4/5 captured data and transfer to memory.
+ * |[18:17] |CAPMOD4_5 |Select PWM_RCAPDAT4/5 Or PWM_FCAPDAT4/5 To Do PDMA Transfer
+ * | | |00 = Reserved.
+ * | | |01 = PWM_RCAPDAT4/5.
+ * | | |10 = PWM_FCAPDAT4/5.
+ * | | |11 = Both PWM_RCAPDAT4/5 and PWM_FCAPDAT4/5.
+ * |[19] |CAPORD4_5 |Capture Channel 4/5 Rising/Falling Order
+ * | | |Set this bit to determine whether the PWM_RCAPDAT4/5 or PWM_FCAPDAT4/5 is the first captured data transferred to memory through PDMA when CAPMOD4_5 = 11.
+ * | | |0 = PWM_FCAPDAT4/5 is the first captured data to memory.
+ * | | |1 = PWM_RCAPDAT4/5 is the first captured data to memory.
+ * |[20] |CHSEL4_5 |Select Channel 4/5 To Do PDMA Transfer
+ * | | |0 = Channel4.
+ * | | |1 = Channel5.
+ * @var PWM_T::PDMACAP0_1
+ * Offset: 0x240 PWM Capture Channel 01 PDMA Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |CAPBUF |PWM Capture PDMA Register
+ * | | |(Read Only)
+ * | | |This register is use as a buffer to transfer PWM capture rising or falling data to memory by PDMA.
+ * @var PWM_T::PDMACAP2_3
+ * Offset: 0x244 PWM Capture Channel 23 PDMA Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |CAPBUF |PWM Capture PDMA Register
+ * | | |(Read Only)
+ * | | |This register is use as a buffer to transfer PWM capture rising or falling data to memory by PDMA.
+ * @var PWM_T::PDMACAP4_5
+ * Offset: 0x248 PWM Capture Channel 45 PDMA Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |CAPBUF |PWM Capture PDMA Register
+ * | | |(Read Only)
+ * | | |This register is use as a buffer to transfer PWM capture rising or falling data to memory by PDMA.
+ * @var PWM_T::CAPIEN
+ * Offset: 0x250 PWM Capture Interrupt Enable Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[5:0] |CAPRIENn |PWM Capture Rising Latch Interrupt Enable
+ * | | |Each bit n controls the corresponding PWM channel n.
+ * | | |0 = Capture rising edge latch interrupt Disabled.
+ * | | |1 = Capture rising edge latch interrupt Enabled.
+ * | | |Note: When Capture with PDMA operating, CINTENR corresponding channel CAPRIEN must be disabled.
+ * |[13:8] |CAPFIENn |PWM Capture Falling Latch Interrupt Enable
+ * | | |Each bit n controls the corresponding PWM channel n.
+ * | | |0 = Capture falling edge latch interrupt Disabled.
+ * | | |1 = Capture falling edge latch interrupt Enabled.
+ * | | |Note: When Capture with PDMA operating, CINTENR corresponding channel CAPFIEN must be disabled.
+ * @var PWM_T::CAPIF
+ * Offset: 0x254 PWM Capture Interrupt Flag Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[5:0] |CRLIFn |PWM Capture Rising Latch Interrupt Flag
+ * | | |This bit is writing 1 to clear. Each bit n controls the corresponding PWM channel n.
+ * | | |0 = No capture rising latch condition happened.
+ * | | |1 = Capture rising latch condition happened, this flag will be set to high.
+ * | | |Note: When Capture with PDMA operating, CIFR corresponding channel CRLIF will cleared by hardware after PDMA transfer data.
+ * |[13:8] |CFLIFn |PWM Capture Falling Latch Interrupt Flag
+ * | | |This bit is writing 1 to clear. Each bit n controls the corresponding PWM channel n.
+ * | | |0 = No capture falling latch condition happened.
+ * | | |1 = Capture falling latch condition happened, this flag will be set to high.
+ * | | |Note: When Capture with PDMA operating, CIFR corresponding channel CFLIF will cleared by hardware after PDMA transfer data.
+ * @var PWM_T::PBUF
+ * Offset: 0x304~0x318 PWM PERIOD0~5 Buffer
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |PBUF |PWM Period Register Buffer
+ * | | |(Read Only)
+ * | | |Used as PERIOD active register.
+ * @var PWM_T::CMPBUF
+ * Offset: 0x31C~0x330 PWM CMPDAT0~5 Buffer
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |CMPBUF |PWM Comparator Register Buffer
+ * | | |(Read Only)
+ * | | |Used as CMP active register.
+ * @var PWM_T::FTCBUF0_1
+ * Offset: 0x340 PWM FTCMPDAT0_1 Buffer
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |FTCMPBUF |PWM FTCMPDAT Buffer (Read Only)
+ * | | |Used as FTCMPDAT active register.
+ * @var PWM_T::FTCBUF2_3
+ * Offset: 0x344 PWM FTCMPDAT2_3 Buffer
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |FTCMPBUF |PWM FTCMPDAT Buffer (Read Only)
+ * | | |Used as FTCMPDAT active register.
+ * @var PWM_T::FTCBUF4_5
+ * Offset: 0x348 PWM FTCMPDAT4_5 Buffer
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |FTCMPBUF |PWM FTCMPDAT Buffer (Read Only)
+ * | | |Used as FTCMPDAT active register.
+ * @var PWM_T::FTCI
+ * Offset: 0x34C PWM FTCMPDAT Indicator Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[2:0] |FTCMUn |PWM FTCMPDAT Up Indicator
+ * | | |Indicator will be set to high when FTCMPDATn equal to PERIODn and DIRF=1, software can write 1 to clear this bit.
+ * | | |Each bit n controls the corresponding PWM channel n.
+ * |[10:8] |FTCMDn |PWM FTCMPDAT Down Indicator
+ * | | |Indicator will be set to high when FTCMPDATn equal to PERIODn and DIRF=0, software can write 1 to clear this bit.
+ * | | |Each bit n controls the corresponding PWM channel n.
+ */
+
+ __IO uint32_t CTL0; /* Offset: 0x00 PWM Control Register 0 */
+ __IO uint32_t CTL1; /* Offset: 0x04 PWM Control Register 1 */
+ __IO uint32_t SYNC; /* Offset: 0x08 PWM Synchronization Register */
+ __IO uint32_t SWSYNC; /* Offset: 0x0C PWM Software Control Synchronization Register */
+ __IO uint32_t CLKSRC; /* Offset: 0x10 PWM Clock Source Register */
+ __IO uint32_t CLKPSC0_1; /* Offset: 0x14 PWM Clock Pre-scale Register 0 */
+ __IO uint32_t CLKPSC2_3; /* Offset: 0x18 PWM Clock Pre-scale Register 2 */
+ __IO uint32_t CLKPSC4_5; /* Offset: 0x1C PWM Clock Pre-scale Register 4 */
+ __IO uint32_t CNTEN; /* Offset: 0x20 PWM Counter Enable Register */
+ __IO uint32_t CNTCLR; /* Offset: 0x24 PWM Clear Counter Register */
+ __IO uint32_t LOAD; /* Offset: 0x28 PWM Load Register */
+ __I uint32_t RESERVE0[1];
+ __IO uint32_t PERIOD[6]; /* Offset: 0x30~0x44 PWM Period Register 0~5 */
+ __I uint32_t RESERVE1[2];
+ __IO uint32_t CMPDAT[6]; /* Offset: 0x50~0x64 PWM Comparator Register 0~5 */
+ __I uint32_t RESERVE2[2];
+ __IO uint32_t DTCTL0_1; /* Offset: 0x70 PWM Dead-Time Control Register 0 */
+ __IO uint32_t DTCTL2_3; /* Offset: 0x74 PWM Dead-Time Control Register 2 */
+ __IO uint32_t DTCTL4_5; /* Offset: 0x78 PWM Dead-Time Control Register 4 */
+ __I uint32_t RESERVE3[1];
+ __IO uint32_t PHS0_1; /* Offset: 0x80 PWM Counter Phase Register 0 */
+ __IO uint32_t PHS2_3; /* Offset: 0x84 PWM Counter Phase Register 2 */
+ __IO uint32_t PHS4_5; /* Offset: 0x88 PWM Counter Phase Register 4 */
+ __I uint32_t RESERVE4[1];
+ __I uint32_t CNT[6]; /* Offset: 0x90~0xA4 PWM Counter Register 0~5 */
+ __I uint32_t RESERVE5[2];
+ __IO uint32_t WGCTL0; /* Offset: 0xB0 PWM Generation Register 0 */
+ __IO uint32_t WGCTL1; /* Offset: 0xB4 PWM Generation Register 1 */
+ __IO uint32_t MSKEN; /* Offset: 0xB8 PWM Mask Enable Register */
+ __IO uint32_t MSK; /* Offset: 0xBC PWM Mask Data Register */
+ __IO uint32_t BNF; /* Offset: 0xC0 PWM Brake Noise Filter Register */
+ __IO uint32_t FAILBRK; /* Offset: 0xC4 PWM System Fail Brake Control Register */
+ __IO uint32_t BRKCTL0_1; /* Offset: 0xC8 PWM Brake Edge Detect Control Register 0 */
+ __IO uint32_t BRKCTL2_3; /* Offset: 0xCC PWM Brake Edge Detect Control Register 2 */
+ __IO uint32_t BRKCTL4_5; /* Offset: 0xD0 PWM Brake Edge Detect Control Register 4 */
+ __IO uint32_t POLCTL; /* Offset: 0xD4 PWM Pin Polar Inverse Register */
+ __IO uint32_t POEN; /* Offset: 0xD8 PWM Output Enable Register */
+ __O uint32_t SWBRK; /* Offset: 0xDC PWM Software Brake Control Register */
+ __IO uint32_t INTEN0; /* Offset: 0xE0 PWM Interrupt Enable Register 0 */
+ __IO uint32_t INTEN1; /* Offset: 0xE4 PWM Interrupt Enable Register 1 */
+ __IO uint32_t INTSTS0; /* Offset: 0xE8 PWM Interrupt Flag Register 0 */
+ __IO uint32_t INTSTS1; /* Offset: 0xEC PWM Interrupt Flag Register 1 */
+ __IO uint32_t IFA; /* Offset: 0xF0 PWM Interrupt Flag Accumulator Register */
+ __IO uint32_t DACTRGEN; /* Offset: 0xF4 PWM Trigger DAC Enable Register */
+ __IO uint32_t EADCTS0; /* Offset: 0xF8 PWM Trigger EADC Source Select Register 0 */
+ __IO uint32_t EADCTS1; /* Offset: 0xFC PWM Trigger EADC Source Select Register 1 */
+ __IO uint32_t FTCMPDAT0_1; /* Offset: 0x100 PWM Free Trigger Compare Register 0 */
+ __IO uint32_t FTCMPDAT2_3; /* Offset: 0x104 PWM Free Trigger Compare Register 2 */
+ __IO uint32_t FTCMPDAT4_5; /* Offset: 0x108 PWM Free Trigger Compare Register 4 */
+ __I uint32_t RESERVE6[1];
+ __IO uint32_t SSCTL; /* Offset: 0x110 PWM Synchronous Start Control Register */
+ __O uint32_t SSTRG; /* Offset: 0x114 PWM Synchronous Start Trigger Register */
+ __I uint32_t RESERVE7[2];
+ __IO uint32_t STATUS; /* Offset: 0x120 PWM Status Register */
+ __I uint32_t RESERVE8[55];
+ __IO uint32_t CAPINEN; /* Offset: 0x200 PWM Capture Input Enable Register */
+ __IO uint32_t CAPCTL; /* Offset: 0x204 PWM Capture Control Register */
+ __I uint32_t CAPSTS; /* Offset: 0x208 PWM Capture Status Register */
+ __I uint32_t RCAPDAT0; /* Offset: 0x20C PWM Rising Capture Data Register 0 */
+ __I uint32_t FCAPDAT0; /* Offset: 0x210 PWM Falling Capture Data Register 0 */
+ __I uint32_t RCAPDAT1; /* Offset: 0x214 PWM Rising Capture Data Register 1 */
+ __I uint32_t FCAPDAT1; /* Offset: 0x218 PWM Falling Capture Data Register 1 */
+ __I uint32_t RCAPDAT2; /* Offset: 0x21C PWM Rising Capture Data Register 2 */
+ __I uint32_t FCAPDAT2; /* Offset: 0x220 PWM Falling Capture Data Register 2 */
+ __I uint32_t RCAPDAT3; /* Offset: 0x224 PWM Rising Capture Data Register 3 */
+ __I uint32_t FCAPDAT3; /* Offset: 0x228 PWM Falling Capture Data Register 3 */
+ __I uint32_t RCAPDAT4; /* Offset: 0x22C PWM Rising Capture Data Register 4 */
+ __I uint32_t FCAPDAT4; /* Offset: 0x230 PWM Falling Capture Data Register 4 */
+ __I uint32_t RCAPDAT5; /* Offset: 0x234 PWM Rising Capture Data Register 5 */
+ __I uint32_t FCAPDAT5; /* Offset: 0x238 PWM Falling Capture Data Register 5 */
+ __IO uint32_t PDMACTL; /* Offset: 0x23C PWM PDMA Control Register */
+ __I uint32_t PDMACAP0_1; /* Offset: 0x240 PWM Capture Channel 01 PDMA Register */
+ __I uint32_t PDMACAP2_3; /* Offset: 0x244 PWM Capture Channel 23 PDMA Register */
+ __I uint32_t PDMACAP4_5; /* Offset: 0x248 PWM Capture Channel 45 PDMA Register */
+ __I uint32_t RESERVE9[1];
+ __IO uint32_t CAPIEN; /* Offset: 0x250 PWM Capture Interrupt Enable Register */
+ __IO uint32_t CAPIF; /* Offset: 0x254 PWM Capture Interrupt Flag Register */
+ __I uint32_t RESERVE10[43];
+ __I uint32_t PBUF[6]; /* Offset: 0x304~0x318 PWM PERIOD0~5 Buffer */
+ __I uint32_t CMPBUF[6]; /* Offset: 0x31C~0x330 PWM CMPDAT0~5 Buffer */
+ __I uint32_t RESERVE11[3];
+ __I uint32_t FTCBUF0_1; /* Offset: 0x340 PWM FTCMPDAT0_1 Buffer */
+ __I uint32_t FTCBUF2_3; /* Offset: 0x344 PWM FTCMPDAT2_3 Buffer */
+ __I uint32_t FTCBUF4_5; /* Offset: 0x348 PWM FTCMPDAT4_5 Buffer */
+ __IO uint32_t FTCI; /* Offset: 0x34C PWM FTCMPDAT Indicator Register */
+
+} PWM_T;
+
+
+
+/**
+ @addtogroup PWM_CONST PWM Bit Field Definition
+ Constant Definitions for PWM Controller
+@{ */
+
+#define PWM_CTL0_CTRLDn_Pos (0) /*!< PWM_T::CTL0: CTRLDn Position */
+#define PWM_CTL0_CTRLDn_Msk (0x3ful << PWM_CTL0_CTRLDn_Pos) /*!< PWM_T::CTL0: CTRLDn Mask */
+
+#define PWM_CTL0_CTRLD0_Pos (0) /*!< PWM_T::CTL0: CTRLD0 Position */
+#define PWM_CTL0_CTRLD0_Msk (0x1ul << PWM_CTL0_CTRLD0_Pos) /*!< PWM_T::CTL0: CTRLD0 Mask */
+
+#define PWM_CTL0_CTRLD1_Pos (1) /*!< PWM_T::CTL0: CTRLD1 Position */
+#define PWM_CTL0_CTRLD1_Msk (0x1ul << PWM_CTL0_CTRLD1_Pos) /*!< PWM_T::CTL0: CTRLD1 Mask */
+
+#define PWM_CTL0_CTRLD2_Pos (2) /*!< PWM_T::CTL0: CTRLD2 Position */
+#define PWM_CTL0_CTRLD2_Msk (0x1ul << PWM_CTL0_CTRLD2_Pos) /*!< PWM_T::CTL0: CTRLD2 Mask */
+
+#define PWM_CTL0_CTRLD3_Pos (3) /*!< PWM_T::CTL0: CTRLD3 Position */
+#define PWM_CTL0_CTRLD3_Msk (0x1ul << PWM_CTL0_CTRLD3_Pos) /*!< PWM_T::CTL0: CTRLD3 Mask */
+
+#define PWM_CTL0_CTRLD4_Pos (4) /*!< PWM_T::CTL0: CTRLD4 Position */
+#define PWM_CTL0_CTRLD4_Msk (0x1ul << PWM_CTL0_CTRLD4_Pos) /*!< PWM_T::CTL0: CTRLD4 Mask */
+
+#define PWM_CTL0_CTRLD5_Pos (5) /*!< PWM_T::CTL0: CTRLD5 Position */
+#define PWM_CTL0_CTRLD5_Msk (0x1ul << PWM_CTL0_CTRLD5_Pos) /*!< PWM_T::CTL0: CTRLD5 Mask */
+
+#define PWM_CTL0_WINLDENn_Pos (8) /*!< PWM_T::CTL0: WINLDENn Position */
+#define PWM_CTL0_WINLDENn_Msk (0x3ful << PWM_CTL0_WINLDENn_Pos) /*!< PWM_T::CTL0: WINLDENn Mask */
+
+#define PWM_CTL0_WINLDEN0_Pos (8) /*!< PWM_T::CTL0: WINLDEN0 Position */
+#define PWM_CTL0_WINLDEN0_Msk (0x1ul << PWM_CTL0_WINLDEN0_Pos) /*!< PWM_T::CTL0: WINLDEN0 Mask */
+
+#define PWM_CTL0_WINLDEN1_Pos (9) /*!< PWM_T::CTL0: WINLDEN1 Position */
+#define PWM_CTL0_WINLDEN1_Msk (0x1ul << PWM_CTL0_WINLDEN1_Pos) /*!< PWM_T::CTL0: WINLDEN1 Mask */
+
+#define PWM_CTL0_WINLDEN2_Pos (10) /*!< PWM_T::CTL0: WINLDEN2 Position */
+#define PWM_CTL0_WINLDEN2_Msk (0x1ul << PWM_CTL0_WINLDEN2_Pos) /*!< PWM_T::CTL0: WINLDEN2 Mask */
+
+#define PWM_CTL0_WINLDEN3_Pos (11) /*!< PWM_T::CTL0: WINLDEN3 Position */
+#define PWM_CTL0_WINLDEN3_Msk (0x1ul << PWM_CTL0_WINLDEN3_Pos) /*!< PWM_T::CTL0: WINLDEN3 Mask */
+
+#define PWM_CTL0_WINLDEN4_Pos (12) /*!< PWM_T::CTL0: WINLDEN4 Position */
+#define PWM_CTL0_WINLDEN4_Msk (0x1ul << PWM_CTL0_WINLDEN4_Pos) /*!< PWM_T::CTL0: WINLDEN4 Mask */
+
+#define PWM_CTL0_WINLDEN5_Pos (13) /*!< PWM_T::CTL0: WINLDEN5 Position */
+#define PWM_CTL0_WINLDEN5_Msk (0x1ul << PWM_CTL0_WINLDEN5_Pos) /*!< PWM_T::CTL0: WINLDEN5 Mask */
+
+#define PWM_CTL0_IMMLDENn_Pos (16) /*!< PWM_T::CTL0: IMMLDENn Position */
+#define PWM_CTL0_IMMLDENn_Msk (0x3ful << PWM_CTL0_IMMLDENn_Pos) /*!< PWM_T::CTL0: IMMLDENn Mask */
+
+#define PWM_CTL0_IMMLDEN0_Pos (16) /*!< PWM_T::CTL0: IMMLDEN0 Position */
+#define PWM_CTL0_IMMLDEN0_Msk (0x1ul << PWM_CTL0_IMMLDEN0_Pos) /*!< PWM_T::CTL0: IMMLDEN0 Mask */
+
+#define PWM_CTL0_IMMLDEN1_Pos (17) /*!< PWM_T::CTL0: IMMLDEN1 Position */
+#define PWM_CTL0_IMMLDEN1_Msk (0x1ul << PWM_CTL0_IMMLDEN1_Pos) /*!< PWM_T::CTL0: IMMLDEN1 Mask */
+
+#define PWM_CTL0_IMMLDEN2_Pos (18) /*!< PWM_T::CTL0: IMMLDEN2 Position */
+#define PWM_CTL0_IMMLDEN2_Msk (0x1ul << PWM_CTL0_IMMLDEN2_Pos) /*!< PWM_T::CTL0: IMMLDEN2 Mask */
+
+#define PWM_CTL0_IMMLDEN3_Pos (19) /*!< PWM_T::CTL0: IMMLDEN3 Position */
+#define PWM_CTL0_IMMLDEN3_Msk (0x1ul << PWM_CTL0_IMMLDEN3_Pos) /*!< PWM_T::CTL0: IMMLDEN3 Mask */
+
+#define PWM_CTL0_IMMLDEN4_Pos (20) /*!< PWM_T::CTL0: IMMLDEN4 Position */
+#define PWM_CTL0_IMMLDEN4_Msk (0x1ul << PWM_CTL0_IMMLDEN4_Pos) /*!< PWM_T::CTL0: IMMLDEN4 Mask */
+
+#define PWM_CTL0_IMMLDEN5_Pos (21) /*!< PWM_T::CTL0: IMMLDEN5 Position */
+#define PWM_CTL0_IMMLDEN5_Msk (0x1ul << PWM_CTL0_IMMLDEN5_Pos) /*!< PWM_T::CTL0: IMMLDEN5 Mask */
+
+#define PWM_CTL0_GROUPEN_Pos (24) /*!< PWM_T::CTL0: GROUPEN Position */
+#define PWM_CTL0_GROUPEN_Msk (0x1ul << PWM_CTL0_GROUPEN_Pos) /*!< PWM_T::CTL0: GROUPEN Mask */
+
+#define PWM_CTL0_DBGHALT_Pos (30) /*!< PWM_T::CTL0: DBGHALT Position */
+#define PWM_CTL0_DBGHALT_Msk (0x1ul << PWM_CTL0_DBGHALT_Pos) /*!< PWM_T::CTL0: DBGHALT Mask */
+
+#define PWM_CTL0_DBGTRIOFF_Pos (31) /*!< PWM_T::CTL0: DBGTRIOFF Position */
+#define PWM_CTL0_DBGTRIOFF_Msk (0x1ul << PWM_CTL0_DBGTRIOFF_Pos) /*!< PWM_T::CTL0: DBGTRIOFF Mask */
+
+#define PWM_CTL1_CNTTYPEn_Pos (0) /*!< PWM_T::CTL1: CNTTYPEn Position */
+#define PWM_CTL1_CNTTYPEn_Msk (0xffful << PWM_CTL1_CNTTYPEn_Pos) /*!< PWM_T::CTL1: CNTTYPEn Mask */
+
+#define PWM_CTL1_CNTTYPE0_Pos (0) /*!< PWM_T::CTL1: CNTTYPE0 Position */
+#define PWM_CTL1_CNTTYPE0_Msk (0x3ul << PWM_CTL1_CNTTYPE0_Pos) /*!< PWM_T::CTL1: CNTTYPE0 Mask */
+
+#define PWM_CTL1_CNTTYPE1_Pos (2) /*!< PWM_T::CTL1: CNTTYPE1 Position */
+#define PWM_CTL1_CNTTYPE1_Msk (0x3ul << PWM_CTL1_CNTTYPE1_Pos) /*!< PWM_T::CTL1: CNTTYPE1 Mask */
+
+#define PWM_CTL1_CNTTYPE2_Pos (4) /*!< PWM_T::CTL1: CNTTYPE2 Position */
+#define PWM_CTL1_CNTTYPE2_Msk (0x3ul << PWM_CTL1_CNTTYPE2_Pos) /*!< PWM_T::CTL1: CNTTYPE2 Mask */
+
+#define PWM_CTL1_CNTTYPE3_Pos (6) /*!< PWM_T::CTL1: CNTTYPE3 Position */
+#define PWM_CTL1_CNTTYPE3_Msk (0x3ul << PWM_CTL1_CNTTYPE3_Pos) /*!< PWM_T::CTL1: CNTTYPE3 Mask */
+
+#define PWM_CTL1_CNTTYPE4_Pos (8) /*!< PWM_T::CTL1: CNTTYPE4 Position */
+#define PWM_CTL1_CNTTYPE4_Msk (0x3ul << PWM_CTL1_CNTTYPE4_Pos) /*!< PWM_T::CTL1: CNTTYPE4 Mask */
+
+#define PWM_CTL1_CNTTYPE5_Pos (10) /*!< PWM_T::CTL1: CNTTYPE5 Position */
+#define PWM_CTL1_CNTTYPE5_Msk (0x3ul << PWM_CTL1_CNTTYPE5_Pos) /*!< PWM_T::CTL1: CNTTYPE5 Mask */
+
+#define PWM_CTL1_CNTMODEn_Pos (16) /*!< PWM_T::CTL1: CNTMODEn Position */
+#define PWM_CTL1_CNTMODEn_Msk (0x3ful << PWM_CTL1_CNTMODEn_Pos) /*!< PWM_T::CTL1: CNTMODEn Mask */
+
+#define PWM_CTL1_CNTMODE0_Pos (16) /*!< PWM_T::CTL1: CNTMODE0 Position */
+#define PWM_CTL1_CNTMODE0_Msk (0x1ul << PWM_CTL1_CNTMODE0_Pos) /*!< PWM_T::CTL1: CNTMODE0 Mask */
+
+#define PWM_CTL1_CNTMODE1_Pos (17) /*!< PWM_T::CTL1: CNTMODE1 Position */
+#define PWM_CTL1_CNTMODE1_Msk (0x1ul << PWM_CTL1_CNTMODE1_Pos) /*!< PWM_T::CTL1: CNTMODE1 Mask */
+
+#define PWM_CTL1_CNTMODE2_Pos (18) /*!< PWM_T::CTL1: CNTMODE2 Position */
+#define PWM_CTL1_CNTMODE2_Msk (0x1ul << PWM_CTL1_CNTMODE2_Pos) /*!< PWM_T::CTL1: CNTMODE2 Mask */
+
+#define PWM_CTL1_CNTMODE3_Pos (19) /*!< PWM_T::CTL1: CNTMODE3 Position */
+#define PWM_CTL1_CNTMODE3_Msk (0x1ul << PWM_CTL1_CNTMODE3_Pos) /*!< PWM_T::CTL1: CNTMODE3 Mask */
+
+#define PWM_CTL1_CNTMODE4_Pos (20) /*!< PWM_T::CTL1: CNTMODE4 Position */
+#define PWM_CTL1_CNTMODE4_Msk (0x1ul << PWM_CTL1_CNTMODE4_Pos) /*!< PWM_T::CTL1: CNTMODE4 Mask */
+
+#define PWM_CTL1_CNTMODE5_Pos (21) /*!< PWM_T::CTL1: CNTMODE5 Position */
+#define PWM_CTL1_CNTMODE5_Msk (0x1ul << PWM_CTL1_CNTMODE5_Pos) /*!< PWM_T::CTL1: CNTMODE5 Mask */
+
+#define PWM_CTL1_OUTMODEn_Pos (24) /*!< PWM_T::CTL1: OUTMODEn Position */
+#define PWM_CTL1_OUTMODEn_Msk (0x7ul << PWM_CTL1_OUTMODEn_Pos) /*!< PWM_T::CTL1: OUTMODEn Mask */
+
+#define PWM_CTL1_OUTMODE0_Pos (24) /*!< PWM_T::CTL1: OUTMODE0 Position */
+#define PWM_CTL1_OUTMODE0_Msk (0x1ul << PWM_CTL1_OUTMODE0_Pos) /*!< PWM_T::CTL1: OUTMODE0 Mask */
+
+#define PWM_CTL1_OUTMODE2_Pos (25) /*!< PWM_T::CTL1: OUTMODE2 Position */
+#define PWM_CTL1_OUTMODE2_Msk (0x1ul << PWM_CTL1_OUTMODE2_Pos) /*!< PWM_T::CTL1: OUTMODE2 Mask */
+
+#define PWM_CTL1_OUTMODE4_Pos (26) /*!< PWM_T::CTL1: OUTMODE4 Position */
+#define PWM_CTL1_OUTMODE4_Msk (0x1ul << PWM_CTL1_OUTMODE4_Pos) /*!< PWM_T::CTL1: OUTMODE4 Mask */
+
+#define PWM_SYNC_PHSENn_Pos (0) /*!< PWM_T::SYNC: PHSENn Position */
+#define PWM_SYNC_PHSENn_Msk (0x7ul << PWM_SYNC_PHSENn_Pos) /*!< PWM_T::SYNC: PHSENn Mask */
+
+#define PWM_SYNC_PHSEN0_Pos (0) /*!< PWM_T::SYNC: PHSEN0 Position */
+#define PWM_SYNC_PHSEN0_Msk (0x1ul << PWM_SYNC_PHSEN0_Pos) /*!< PWM_T::SYNC: PHSEN0 Mask */
+
+#define PWM_SYNC_PHSEN2_Pos (1) /*!< PWM_T::SYNC: PHSEN2 Position */
+#define PWM_SYNC_PHSEN2_Msk (0x1ul << PWM_SYNC_PHSEN2_Pos) /*!< PWM_T::SYNC: PHSEN2 Mask */
+
+#define PWM_SYNC_PHSEN4_Pos (2) /*!< PWM_T::SYNC: PHSEN4 Position */
+#define PWM_SYNC_PHSEN4_Msk (0x1ul << PWM_SYNC_PHSEN4_Pos) /*!< PWM_T::SYNC: PHSEN4 Mask */
+
+#define PWM_SYNC_SINSRCn_Pos (8) /*!< PWM_T::SYNC: SINSRCn Position */
+#define PWM_SYNC_SINSRCn_Msk (0x3ful << PWM_SYNC_SINSRCn_Pos) /*!< PWM_T::SYNC: SINSRCn Mask */
+
+#define PWM_SYNC_SINSRC0_Pos (8) /*!< PWM_T::SYNC: SINSRC0 Position */
+#define PWM_SYNC_SINSRC0_Msk (0x3ul << PWM_SYNC_SINSRC0_Pos) /*!< PWM_T::SYNC: SINSRC0 Mask */
+
+#define PWM_SYNC_SINSRC2_Pos (10) /*!< PWM_T::SYNC: SINSRC2 Position */
+#define PWM_SYNC_SINSRC2_Msk (0x3ul << PWM_SYNC_SINSRC2_Pos) /*!< PWM_T::SYNC: SINSRC2 Mask */
+
+#define PWM_SYNC_SINSRC4_Pos (12) /*!< PWM_T::SYNC: SINSRC4 Position */
+#define PWM_SYNC_SINSRC4_Msk (0x3ul << PWM_SYNC_SINSRC4_Pos) /*!< PWM_T::SYNC: SINSRC4 Mask */
+
+#define PWM_SYNC_SNFLTEN_Pos (16) /*!< PWM_T::SYNC: SNFLTEN Position */
+#define PWM_SYNC_SNFLTEN_Msk (0x1ul << PWM_SYNC_SNFLTEN_Pos) /*!< PWM_T::SYNC: SNFLTEN Mask */
+
+#define PWM_SYNC_SFLTCSEL_Pos (17) /*!< PWM_T::SYNC: SFLTCSEL Position */
+#define PWM_SYNC_SFLTCSEL_Msk (0x7ul << PWM_SYNC_SFLTCSEL_Pos) /*!< PWM_T::SYNC: SFLTCSEL Mask */
+
+#define PWM_SYNC_SFLTCNT_Pos (20) /*!< PWM_T::SYNC: SFLTCNT Position */
+#define PWM_SYNC_SFLTCNT_Msk (0x7ul << PWM_SYNC_SFLTCNT_Pos) /*!< PWM_T::SYNC: SFLTCNT Mask */
+
+#define PWM_SYNC_SINPINV_Pos (23) /*!< PWM_T::SYNC: SINPINV Position */
+#define PWM_SYNC_SINPINV_Msk (0x1ul << PWM_SYNC_SINPINV_Pos) /*!< PWM_T::SYNC: SINPINV Mask */
+
+#define PWM_SYNC_PHSDIRn_Pos (24) /*!< PWM_T::SYNC: PHSDIRn Position */
+#define PWM_SYNC_PHSDIRn_Msk (0x7ul << PWM_SYNC_PHSDIRn_Pos) /*!< PWM_T::SYNC: PHSDIRn Mask */
+
+#define PWM_SYNC_PHSDIR0_Pos (24) /*!< PWM_T::SYNC: PHSDIR0 Position */
+#define PWM_SYNC_PHSDIR0_Msk (0x1ul << PWM_SYNC_PHSDIR0_Pos) /*!< PWM_T::SYNC: PHSDIR0 Mask */
+
+#define PWM_SYNC_PHSDIR2_Pos (25) /*!< PWM_T::SYNC: PHSDIR2 Position */
+#define PWM_SYNC_PHSDIR2_Msk (0x1ul << PWM_SYNC_PHSDIR2_Pos) /*!< PWM_T::SYNC: PHSDIR2 Mask */
+
+#define PWM_SYNC_PHSDIR4_Pos (26) /*!< PWM_T::SYNC: PHSDIR4 Position */
+#define PWM_SYNC_PHSDIR4_Msk (0x1ul << PWM_SYNC_PHSDIR4_Pos) /*!< PWM_T::SYNC: PHSDIR4 Mask */
+
+#define PWM_SWSYNC_SWSYNCn_Pos (0) /*!< PWM_T::SWSYNC: SWSYNCn Position */
+#define PWM_SWSYNC_SWSYNCn_Msk (0x7ul << PWM_SWSYNC_SWSYNCn_Pos) /*!< PWM_T::SWSYNC: SWSYNCn Mask */
+
+#define PWM_SWSYNC_SWSYNC0_Pos (0) /*!< PWM_T::SWSYNC: SWSYNC0 Position */
+#define PWM_SWSYNC_SWSYNC0_Msk (0x1ul << PWM_SWSYNC_SWSYNC0_Pos) /*!< PWM_T::SWSYNC: SWSYNC0 Mask */
+
+#define PWM_SWSYNC_SWSYNC2_Pos (1) /*!< PWM_T::SWSYNC: SWSYNC2 Position */
+#define PWM_SWSYNC_SWSYNC2_Msk (0x1ul << PWM_SWSYNC_SWSYNC2_Pos) /*!< PWM_T::SWSYNC: SWSYNC2 Mask */
+
+#define PWM_SWSYNC_SWSYNC4_Pos (2) /*!< PWM_T::SWSYNC: SWSYNC4 Position */
+#define PWM_SWSYNC_SWSYNC4_Msk (0x1ul << PWM_SWSYNC_SWSYNC4_Pos) /*!< PWM_T::SWSYNC: SWSYNC4 Mask */
+
+#define PWM_CLKSRC_ECLKSRC0_Pos (0) /*!< PWM_T::CLKSRC: ECLKSRC0 Position */
+#define PWM_CLKSRC_ECLKSRC0_Msk (0x7ul << PWM_CLKSRC_ECLKSRC0_Pos) /*!< PWM_T::CLKSRC: ECLKSRC0 Mask */
+
+#define PWM_CLKSRC_ECLKSRC2_Pos (8) /*!< PWM_T::CLKSRC: ECLKSRC2 Position */
+#define PWM_CLKSRC_ECLKSRC2_Msk (0x7ul << PWM_CLKSRC_ECLKSRC2_Pos) /*!< PWM_T::CLKSRC: ECLKSRC2 Mask */
+
+#define PWM_CLKSRC_ECLKSRC4_Pos (16) /*!< PWM_T::CLKSRC: ECLKSRC4 Position */
+#define PWM_CLKSRC_ECLKSRC4_Msk (0x7ul << PWM_CLKSRC_ECLKSRC4_Pos) /*!< PWM_T::CLKSRC: ECLKSRC4 Mask */
+
+#define PWM_CLKPSC0_1_CLKPSC_Pos (0) /*!< PWM_T::CLKPSC0_1: CLKPSC Position */
+#define PWM_CLKPSC0_1_CLKPSC_Msk (0xffful << PWM_CLKPSC0_1_CLKPSC_Pos) /*!< PWM_T::CLKPSC0_1: CLKPSC Mask */
+
+#define PWM_CLKPSC2_3_CLKPSC_Pos (0) /*!< PWM_T::CLKPSC2_3: CLKPSC Position */
+#define PWM_CLKPSC2_3_CLKPSC_Msk (0xffful << PWM_CLKPSC2_3_CLKPSC_Pos) /*!< PWM_T::CLKPSC2_3: CLKPSC Mask */
+
+#define PWM_CLKPSC4_5_CLKPSC_Pos (0) /*!< PWM_T::CLKPSC4_5: CLKPSC Position */
+#define PWM_CLKPSC4_5_CLKPSC_Msk (0xffful << PWM_CLKPSC4_5_CLKPSC_Pos) /*!< PWM_T::CLKPSC4_5: CLKPSC Mask */
+
+#define PWM_CNTEN_CNTENn_Pos (0) /*!< PWM_T::CNTEN: CNTENn Position */
+#define PWM_CNTEN_CNTENn_Msk (0x3ful << PWM_CNTEN_CNTENn_Pos) /*!< PWM_T::CNTEN: CNTENn Mask */
+
+#define PWM_CNTEN_CNTEN0_Pos (0) /*!< PWM_T::CNTEN: CNTEN0 Position */
+#define PWM_CNTEN_CNTEN0_Msk (0x1ul << PWM_CNTEN_CNTEN0_Pos) /*!< PWM_T::CNTEN: CNTEN0 Mask */
+
+#define PWM_CNTEN_CNTEN1_Pos (1) /*!< PWM_T::CNTEN: CNTEN1 Position */
+#define PWM_CNTEN_CNTEN1_Msk (0x1ul << PWM_CNTEN_CNTEN1_Pos) /*!< PWM_T::CNTEN: CNTEN1 Mask */
+
+#define PWM_CNTEN_CNTEN2_Pos (2) /*!< PWM_T::CNTEN: CNTEN2 Position */
+#define PWM_CNTEN_CNTEN2_Msk (0x1ul << PWM_CNTEN_CNTEN2_Pos) /*!< PWM_T::CNTEN: CNTEN2 Mask */
+
+#define PWM_CNTEN_CNTEN3_Pos (3) /*!< PWM_T::CNTEN: CNTEN3 Position */
+#define PWM_CNTEN_CNTEN3_Msk (0x1ul << PWM_CNTEN_CNTEN3_Pos) /*!< PWM_T::CNTEN: CNTEN3 Mask */
+
+#define PWM_CNTEN_CNTEN4_Pos (4) /*!< PWM_T::CNTEN: CNTEN4 Position */
+#define PWM_CNTEN_CNTEN4_Msk (0x1ul << PWM_CNTEN_CNTEN4_Pos) /*!< PWM_T::CNTEN: CNTEN4 Mask */
+
+#define PWM_CNTEN_CNTEN5_Pos (5) /*!< PWM_T::CNTEN: CNTEN5 Position */
+#define PWM_CNTEN_CNTEN5_Msk (0x1ul << PWM_CNTEN_CNTEN5_Pos) /*!< PWM_T::CNTEN: CNTEN5 Mask */
+
+#define PWM_CNTCLR_CNTCLRn_Pos (0) /*!< PWM_T::CNTCLR: CNTCLRn Position */
+#define PWM_CNTCLR_CNTCLRn_Msk (0x3ful << PWM_CNTCLR_CNTCLRn_Pos) /*!< PWM_T::CNTCLR: CNTCLRn Mask */
+
+#define PWM_CNTCLR_CNTCLR0_Pos (0) /*!< PWM_T::CNTCLR: CNTCLR0 Position */
+#define PWM_CNTCLR_CNTCLR0_Msk (0x1ul << PWM_CNTCLR_CNTCLR0_Pos) /*!< PWM_T::CNTCLR: CNTCLR0 Mask */
+
+#define PWM_CNTCLR_CNTCLR1_Pos (1) /*!< PWM_T::CNTCLR: CNTCLR1 Position */
+#define PWM_CNTCLR_CNTCLR1_Msk (0x1ul << PWM_CNTCLR_CNTCLR1_Pos) /*!< PWM_T::CNTCLR: CNTCLR1 Mask */
+
+#define PWM_CNTCLR_CNTCLR2_Pos (2) /*!< PWM_T::CNTCLR: CNTCLR2 Position */
+#define PWM_CNTCLR_CNTCLR2_Msk (0x1ul << PWM_CNTCLR_CNTCLR2_Pos) /*!< PWM_T::CNTCLR: CNTCLR2 Mask */
+
+#define PWM_CNTCLR_CNTCLR3_Pos (3) /*!< PWM_T::CNTCLR: CNTCLR3 Position */
+#define PWM_CNTCLR_CNTCLR3_Msk (0x1ul << PWM_CNTCLR_CNTCLR3_Pos) /*!< PWM_T::CNTCLR: CNTCLR3 Mask */
+
+#define PWM_CNTCLR_CNTCLR4_Pos (4) /*!< PWM_T::CNTCLR: CNTCLR4 Position */
+#define PWM_CNTCLR_CNTCLR4_Msk (0x1ul << PWM_CNTCLR_CNTCLR4_Pos) /*!< PWM_T::CNTCLR: CNTCLR4 Mask */
+
+#define PWM_CNTCLR_CNTCLR5_Pos (5) /*!< PWM_T::CNTCLR: CNTCLR5 Position */
+#define PWM_CNTCLR_CNTCLR5_Msk (0x1ul << PWM_CNTCLR_CNTCLR5_Pos) /*!< PWM_T::CNTCLR: CNTCLR5 Mask */
+
+#define PWM_LOAD_LOADn_Pos (0) /*!< PWM_T::LOAD: LOADn Position */
+#define PWM_LOAD_LOADn_Msk (0x3ful << PWM_LOAD_LOADn_Pos) /*!< PWM_T::LOAD: LOADn Mask */
+
+#define PWM_LOAD_LOAD0_Pos (0) /*!< PWM_T::LOAD: LOAD0 Position */
+#define PWM_LOAD_LOAD0_Msk (0x1ul << PWM_LOAD_LOAD0_Pos) /*!< PWM_T::LOAD: LOAD0 Mask */
+
+#define PWM_LOAD_LOAD1_Pos (1) /*!< PWM_T::LOAD: LOAD1 Position */
+#define PWM_LOAD_LOAD1_Msk (0x1ul << PWM_LOAD_LOAD1_Pos) /*!< PWM_T::LOAD: LOAD1 Mask */
+
+#define PWM_LOAD_LOAD2_Pos (2) /*!< PWM_T::LOAD: LOAD2 Position */
+#define PWM_LOAD_LOAD2_Msk (0x1ul << PWM_LOAD_LOAD2_Pos) /*!< PWM_T::LOAD: LOAD2 Mask */
+
+#define PWM_LOAD_LOAD3_Pos (3) /*!< PWM_T::LOAD: LOAD3 Position */
+#define PWM_LOAD_LOAD3_Msk (0x1ul << PWM_LOAD_LOAD3_Pos) /*!< PWM_T::LOAD: LOAD3 Mask */
+
+#define PWM_LOAD_LOAD4_Pos (4) /*!< PWM_T::LOAD: LOAD4 Position */
+#define PWM_LOAD_LOAD4_Msk (0x1ul << PWM_LOAD_LOAD4_Pos) /*!< PWM_T::LOAD: LOAD4 Mask */
+
+#define PWM_LOAD_LOAD5_Pos (5) /*!< PWM_T::LOAD: LOAD5 Position */
+#define PWM_LOAD_LOAD5_Msk (0x1ul << PWM_LOAD_LOAD5_Pos) /*!< PWM_T::LOAD: LOAD5 Mask */
+
+#define PWM_PERIOD_PERIOD_Pos (0) /*!< PWM_T::PERIOD: PERIOD Position */
+#define PWM_PERIOD_PERIOD_Msk (0xfffful << PWM_PERIOD_PERIOD_Pos) /*!< PWM_T::PERIOD: PERIOD Mask */
+
+#define PWM_CMPDAT_CMP_Pos (0) /*!< PWM_T::CMPDAT: CMP Position */
+#define PWM_CMPDAT_CMP_Msk (0xfffful << PWM_CMPDAT_CMP_Pos) /*!< PWM_T::CMPDAT: CMP Mask */
+
+#define PWM_DTCTL0_1_DTCNT_Pos (0) /*!< PWM_T::DTCTL0_1: DTCNT Position */
+#define PWM_DTCTL0_1_DTCNT_Msk (0xffful << PWM_DTCTL0_1_DTCNT_Pos) /*!< PWM_T::DTCTL0_1: DTCNT Mask */
+
+#define PWM_DTCTL0_1_DTEN_Pos (16) /*!< PWM_T::DTCTL0_1: DTEN Position */
+#define PWM_DTCTL0_1_DTEN_Msk (0x1ul << PWM_DTCTL0_1_DTEN_Pos) /*!< PWM_T::DTCTL0_1: DTEN Mask */
+
+#define PWM_DTCTL0_1_DTCKSEL_Pos (24) /*!< PWM_T::DTCTL0_1: DTCKSEL Position */
+#define PWM_DTCTL0_1_DTCKSEL_Msk (0x1ul << PWM_DTCTL0_1_DTCKSEL_Pos) /*!< PWM_T::DTCTL0_1: DTCKSEL Mask */
+
+#define PWM_DTCTL2_3_DTCNT_Pos (0) /*!< PWM_T::DTCTL2_3: DTCNT Position */
+#define PWM_DTCTL2_3_DTCNT_Msk (0xffful << PWM_DTCTL2_3_DTCNT_Pos) /*!< PWM_T::DTCTL2_3: DTCNT Mask */
+
+#define PWM_DTCTL2_3_DTEN_Pos (16) /*!< PWM_T::DTCTL2_3: DTEN Position */
+#define PWM_DTCTL2_3_DTEN_Msk (0x1ul << PWM_DTCTL2_3_DTEN_Pos) /*!< PWM_T::DTCTL2_3: DTEN Mask */
+
+#define PWM_DTCTL2_3_DTCKSEL_Pos (24) /*!< PWM_T::DTCTL2_3: DTCKSEL Position */
+#define PWM_DTCTL2_3_DTCKSEL_Msk (0x1ul << PWM_DTCTL2_3_DTCKSEL_Pos) /*!< PWM_T::DTCTL2_3: DTCKSEL Mask */
+
+#define PWM_DTCTL4_5_DTCNT_Pos (0) /*!< PWM_T::DTCTL4_5: DTCNT Position */
+#define PWM_DTCTL4_5_DTCNT_Msk (0xffful << PWM_DTCTL4_5_DTCNT_Pos) /*!< PWM_T::DTCTL4_5: DTCNT Mask */
+
+#define PWM_DTCTL4_5_DTEN_Pos (16) /*!< PWM_T::DTCTL4_5: DTEN Position */
+#define PWM_DTCTL4_5_DTEN_Msk (0x1ul << PWM_DTCTL4_5_DTEN_Pos) /*!< PWM_T::DTCTL4_5: DTEN Mask */
+
+#define PWM_DTCTL4_5_DTCKSEL_Pos (24) /*!< PWM_T::DTCTL4_5: DTCKSEL Position */
+#define PWM_DTCTL4_5_DTCKSEL_Msk (0x1ul << PWM_DTCTL4_5_DTCKSEL_Pos) /*!< PWM_T::DTCTL4_5: DTCKSEL Mask */
+
+#define PWM_PHS0_1_PHS_Pos (0) /*!< PWM_T::PHS0_1: PHS Position */
+#define PWM_PHS0_1_PHS_Msk (0xfffful << PWM_PHS0_1_PHS_Pos) /*!< PWM_T::PHS0_1: PHS Mask */
+
+#define PWM_PHS2_3_PHS_Pos (0) /*!< PWM_T::PHS2_3: PHS Position */
+#define PWM_PHS2_3_PHS_Msk (0xfffful << PWM_PHS2_3_PHS_Pos) /*!< PWM_T::PHS2_3: PHS Mask */
+
+#define PWM_PHS4_5_PHS_Pos (0) /*!< PWM_T::PHS4_5: PHS Position */
+#define PWM_PHS4_5_PHS_Msk (0xfffful << PWM_PHS4_5_PHS_Pos) /*!< PWM_T::PHS4_5: PHS Mask */
+
+#define PWM_CNT_CNT_Pos (0) /*!< PWM_T::CNT: CNT Position */
+#define PWM_CNT_CNT_Msk (0xfffful << PWM_CNT_CNT_Pos) /*!< PWM_T::CNT: CNT Mask */
+
+#define PWM_CNT_DIRF_Pos (16) /*!< PWM_T::CNT: DIRF Position */
+#define PWM_CNT_DIRF_Msk (0x1ul << PWM_CNT_DIRF_Pos) /*!< PWM_T::CNT: DIRF Mask */
+
+#define PWM_WGCTL0_ZPCTLn_Pos (0) /*!< PWM_T::WGCTL0: ZPCTLn Position */
+#define PWM_WGCTL0_ZPCTLn_Msk (0xffful << PWM_WGCTL0_ZPCTLn_Pos) /*!< PWM_T::WGCTL0: ZPCTLn Mask */
+
+#define PWM_WGCTL0_ZPCTL0_Pos (0) /*!< PWM_T::WGCTL0: ZPCTL0 Position */
+#define PWM_WGCTL0_ZPCTL0_Msk (0x3ul << PWM_WGCTL0_ZPCTL0_Pos) /*!< PWM_T::WGCTL0: ZPCTL0 Mask */
+
+#define PWM_WGCTL0_ZPCTL1_Pos (2) /*!< PWM_T::WGCTL0: ZPCTL1 Position */
+#define PWM_WGCTL0_ZPCTL1_Msk (0x3ul << PWM_WGCTL0_ZPCTL1_Pos) /*!< PWM_T::WGCTL0: ZPCTL1 Mask */
+
+#define PWM_WGCTL0_ZPCTL2_Pos (4) /*!< PWM_T::WGCTL0: ZPCTL2 Position */
+#define PWM_WGCTL0_ZPCTL2_Msk (0x3ul << PWM_WGCTL0_ZPCTL2_Pos) /*!< PWM_T::WGCTL0: ZPCTL2 Mask */
+
+#define PWM_WGCTL0_ZPCTL3_Pos (6) /*!< PWM_T::WGCTL0: ZPCTL3 Position */
+#define PWM_WGCTL0_ZPCTL3_Msk (0x3ul << PWM_WGCTL0_ZPCTL3_Pos) /*!< PWM_T::WGCTL0: ZPCTL3 Mask */
+
+#define PWM_WGCTL0_ZPCTL4_Pos (8) /*!< PWM_T::WGCTL0: ZPCTL4 Position */
+#define PWM_WGCTL0_ZPCTL4_Msk (0x3ul << PWM_WGCTL0_ZPCTL4_Pos) /*!< PWM_T::WGCTL0: ZPCTL4 Mask */
+
+#define PWM_WGCTL0_ZPCTL5_Pos (10) /*!< PWM_T::WGCTL0: ZPCTL5 Position */
+#define PWM_WGCTL0_ZPCTL5_Msk (0x3ul << PWM_WGCTL0_ZPCTL5_Pos) /*!< PWM_T::WGCTL0: ZPCTL5 Mask */
+
+#define PWM_WGCTL0_PRDPCTLn_Pos (16) /*!< PWM_T::WGCTL0: PRDPCTLn Position */
+#define PWM_WGCTL0_PRDPCTLn_Msk (0xffful << PWM_WGCTL0_PRDPCTLn_Pos) /*!< PWM_T::WGCTL0: PRDPCTLn Mask */
+
+#define PWM_WGCTL0_PRDPCTL0_Pos (16) /*!< PWM_T::WGCTL0: PRDPCTL0 Position */
+#define PWM_WGCTL0_PRDPCTL0_Msk (0x3ul << PWM_WGCTL0_PRDPCTL0_Pos) /*!< PWM_T::WGCTL0: PRDPCTL0 Mask */
+
+#define PWM_WGCTL0_PRDPCTL1_Pos (18) /*!< PWM_T::WGCTL0: PRDPCTL1 Position */
+#define PWM_WGCTL0_PRDPCTL1_Msk (0x3ul << PWM_WGCTL0_PRDPCTL1_Pos) /*!< PWM_T::WGCTL0: PRDPCTL1 Mask */
+
+#define PWM_WGCTL0_PRDPCTL2_Pos (20) /*!< PWM_T::WGCTL0: PRDPCTL2 Position */
+#define PWM_WGCTL0_PRDPCTL2_Msk (0x3ul << PWM_WGCTL0_PRDPCTL2_Pos) /*!< PWM_T::WGCTL0: PRDPCTL2 Mask */
+
+#define PWM_WGCTL0_PRDPCTL3_Pos (22) /*!< PWM_T::WGCTL0: PRDPCTL3 Position */
+#define PWM_WGCTL0_PRDPCTL3_Msk (0x3ul << PWM_WGCTL0_PRDPCTL3_Pos) /*!< PWM_T::WGCTL0: PRDPCTL3 Mask */
+
+#define PWM_WGCTL0_PRDPCTL4_Pos (24) /*!< PWM_T::WGCTL0: PRDPCTL4 Position */
+#define PWM_WGCTL0_PRDPCTL4_Msk (0x3ul << PWM_WGCTL0_PRDPCTL4_Pos) /*!< PWM_T::WGCTL0: PRDPCTL4 Mask */
+
+#define PWM_WGCTL0_PRDPCTL5_Pos (26) /*!< PWM_T::WGCTL0: PRDPCTL5 Position */
+#define PWM_WGCTL0_PRDPCTL5_Msk (0x3ul << PWM_WGCTL0_PRDPCTL5_Pos) /*!< PWM_T::WGCTL0: PRDPCTL5 Mask */
+
+#define PWM_WGCTL1_CMPUCTLn_Pos (0) /*!< PWM_T::WGCTL1: CMPUCTLn Position */
+#define PWM_WGCTL1_CMPUCTLn_Msk (0xffful << PWM_WGCTL1_CMPUCTLn_Pos) /*!< PWM_T::WGCTL1: CMPUCTLn Mask */
+
+#define PWM_WGCTL1_CMPUCTL0_Pos (0) /*!< PWM_T::WGCTL1: CMPUCTL0 Position */
+#define PWM_WGCTL1_CMPUCTL0_Msk (0x3ul << PWM_WGCTL1_CMPUCTL0_Pos) /*!< PWM_T::WGCTL1: CMPUCTL0 Mask */
+
+#define PWM_WGCTL1_CMPUCTL1_Pos (2) /*!< PWM_T::WGCTL1: CMPUCTL1 Position */
+#define PWM_WGCTL1_CMPUCTL1_Msk (0x3ul << PWM_WGCTL1_CMPUCTL1_Pos) /*!< PWM_T::WGCTL1: CMPUCTL1 Mask */
+
+#define PWM_WGCTL1_CMPUCTL2_Pos (4) /*!< PWM_T::WGCTL1: CMPUCTL2 Position */
+#define PWM_WGCTL1_CMPUCTL2_Msk (0x3ul << PWM_WGCTL1_CMPUCTL2_Pos) /*!< PWM_T::WGCTL1: CMPUCTL2 Mask */
+
+#define PWM_WGCTL1_CMPUCTL3_Pos (6) /*!< PWM_T::WGCTL1: CMPUCTL3 Position */
+#define PWM_WGCTL1_CMPUCTL3_Msk (0x3ul << PWM_WGCTL1_CMPUCTL3_Pos) /*!< PWM_T::WGCTL1: CMPUCTL3 Mask */
+
+#define PWM_WGCTL1_CMPUCTL4_Pos (8) /*!< PWM_T::WGCTL1: CMPUCTL4 Position */
+#define PWM_WGCTL1_CMPUCTL4_Msk (0x3ul << PWM_WGCTL1_CMPUCTL4_Pos) /*!< PWM_T::WGCTL1: CMPUCTL4 Mask */
+
+#define PWM_WGCTL1_CMPUCTL5_Pos (10) /*!< PWM_T::WGCTL1: CMPUCTL5 Position */
+#define PWM_WGCTL1_CMPUCTL5_Msk (0x3ul << PWM_WGCTL1_CMPUCTL5_Pos) /*!< PWM_T::WGCTL1: CMPUCTL5 Mask */
+
+#define PWM_WGCTL1_CMPDCTLn_Pos (16) /*!< PWM_T::WGCTL1: CMPDCTLn Position */
+#define PWM_WGCTL1_CMPDCTLn_Msk (0xffful << PWM_WGCTL1_CMPDCTLn_Pos) /*!< PWM_T::WGCTL1: CMPDCTLn Mask */
+
+#define PWM_WGCTL1_CMPDCTL0_Pos (16) /*!< PWM_T::WGCTL1: CMPDCTL0 Position */
+#define PWM_WGCTL1_CMPDCTL0_Msk (0x3ul << PWM_WGCTL1_CMPDCTL0_Pos) /*!< PWM_T::WGCTL1: CMPDCTL0 Mask */
+
+#define PWM_WGCTL1_CMPDCTL1_Pos (18) /*!< PWM_T::WGCTL1: CMPDCTL1 Position */
+#define PWM_WGCTL1_CMPDCTL1_Msk (0x3ul << PWM_WGCTL1_CMPDCTL1_Pos) /*!< PWM_T::WGCTL1: CMPDCTL1 Mask */
+
+#define PWM_WGCTL1_CMPDCTL2_Pos (20) /*!< PWM_T::WGCTL1: CMPDCTL2 Position */
+#define PWM_WGCTL1_CMPDCTL2_Msk (0x3ul << PWM_WGCTL1_CMPDCTL2_Pos) /*!< PWM_T::WGCTL1: CMPDCTL2 Mask */
+
+#define PWM_WGCTL1_CMPDCTL3_Pos (22) /*!< PWM_T::WGCTL1: CMPDCTL3 Position */
+#define PWM_WGCTL1_CMPDCTL3_Msk (0x3ul << PWM_WGCTL1_CMPDCTL3_Pos) /*!< PWM_T::WGCTL1: CMPDCTL3 Mask */
+
+#define PWM_WGCTL1_CMPDCTL4_Pos (24) /*!< PWM_T::WGCTL1: CMPDCTL4 Position */
+#define PWM_WGCTL1_CMPDCTL4_Msk (0x3ul << PWM_WGCTL1_CMPDCTL4_Pos) /*!< PWM_T::WGCTL1: CMPDCTL4 Mask */
+
+#define PWM_WGCTL1_CMPDCTL5_Pos (26) /*!< PWM_T::WGCTL1: CMPDCTL5 Position */
+#define PWM_WGCTL1_CMPDCTL5_Msk (0x3ul << PWM_WGCTL1_CMPDCTL5_Pos) /*!< PWM_T::WGCTL1: CMPDCTL5 Mask */
+
+#define PWM_MSKEN_MSKENn_Pos (0) /*!< PWM_T::MSKEN: MSKENn Position */
+#define PWM_MSKEN_MSKENn_Msk (0x3ful << PWM_MSKEN_MSKENn_Pos) /*!< PWM_T::MSKEN: MSKENn Mask */
+
+#define PWM_MSKEN_MSKEN0_Pos (0) /*!< PWM_T::MSKEN: MSKEN0 Position */
+#define PWM_MSKEN_MSKEN0_Msk (0x1ul << PWM_MSKEN_MSKEN0_Pos) /*!< PWM_T::MSKEN: MSKEN0 Mask */
+
+#define PWM_MSKEN_MSKEN1_Pos (1) /*!< PWM_T::MSKEN: MSKEN1 Position */
+#define PWM_MSKEN_MSKEN1_Msk (0x1ul << PWM_MSKEN_MSKEN1_Pos) /*!< PWM_T::MSKEN: MSKEN1 Mask */
+
+#define PWM_MSKEN_MSKEN2_Pos (2) /*!< PWM_T::MSKEN: MSKEN2 Position */
+#define PWM_MSKEN_MSKEN2_Msk (0x1ul << PWM_MSKEN_MSKEN2_Pos) /*!< PWM_T::MSKEN: MSKEN2 Mask */
+
+#define PWM_MSKEN_MSKEN3_Pos (3) /*!< PWM_T::MSKEN: MSKEN3 Position */
+#define PWM_MSKEN_MSKEN3_Msk (0x1ul << PWM_MSKEN_MSKEN3_Pos) /*!< PWM_T::MSKEN: MSKEN3 Mask */
+
+#define PWM_MSKEN_MSKEN4_Pos (4) /*!< PWM_T::MSKEN: MSKEN4 Position */
+#define PWM_MSKEN_MSKEN4_Msk (0x1ul << PWM_MSKEN_MSKEN4_Pos) /*!< PWM_T::MSKEN: MSKEN4 Mask */
+
+#define PWM_MSKEN_MSKEN5_Pos (5) /*!< PWM_T::MSKEN: MSKEN5 Position */
+#define PWM_MSKEN_MSKEN5_Msk (0x1ul << PWM_MSKEN_MSKEN5_Pos) /*!< PWM_T::MSKEN: MSKEN5 Mask */
+
+#define PWM_MSK_MSKDATn_Pos (0) /*!< PWM_T::MSK: MSKDATn Position */
+#define PWM_MSK_MSKDATn_Msk (0x3ful << PWM_MSK_MSKDATn_Pos) /*!< PWM_T::MSK: MSKDATn Mask */
+
+#define PWM_MSK_MSKDAT0_Pos (0) /*!< PWM_T::MSK: MSKDAT0 Position */
+#define PWM_MSK_MSKDAT0_Msk (0x1ul << PWM_MSK_MSKDAT0_Pos) /*!< PWM_T::MSK: MSKDAT0 Mask */
+
+#define PWM_MSK_MSKDAT1_Pos (1) /*!< PWM_T::MSK: MSKDAT1 Position */
+#define PWM_MSK_MSKDAT1_Msk (0x1ul << PWM_MSK_MSKDAT1_Pos) /*!< PWM_T::MSK: MSKDAT1 Mask */
+
+#define PWM_MSK_MSKDAT2_Pos (2) /*!< PWM_T::MSK: MSKDAT2 Position */
+#define PWM_MSK_MSKDAT2_Msk (0x1ul << PWM_MSK_MSKDAT2_Pos) /*!< PWM_T::MSK: MSKDAT2 Mask */
+
+#define PWM_MSK_MSKDAT3_Pos (3) /*!< PWM_T::MSK: MSKDAT3 Position */
+#define PWM_MSK_MSKDAT3_Msk (0x1ul << PWM_MSK_MSKDAT3_Pos) /*!< PWM_T::MSK: MSKDAT3 Mask */
+
+#define PWM_MSK_MSKDAT4_Pos (4) /*!< PWM_T::MSK: MSKDAT4 Position */
+#define PWM_MSK_MSKDAT4_Msk (0x1ul << PWM_MSK_MSKDAT4_Pos) /*!< PWM_T::MSK: MSKDAT4 Mask */
+
+#define PWM_MSK_MSKDAT5_Pos (5) /*!< PWM_T::MSK: MSKDAT5 Position */
+#define PWM_MSK_MSKDAT5_Msk (0x1ul << PWM_MSK_MSKDAT5_Pos) /*!< PWM_T::MSK: MSKDAT5 Mask */
+
+#define PWM_BNF_BRK0NFEN_Pos (0) /*!< PWM_T::BNF: BRK0NFEN Position */
+#define PWM_BNF_BRK0NFEN_Msk (0x1ul << PWM_BNF_BRK0NFEN_Pos) /*!< PWM_T::BNF: BRK0NFEN Mask */
+
+#define PWM_BNF_BRK0NFSEL_Pos (1) /*!< PWM_T::BNF: BRK0NFSEL Position */
+#define PWM_BNF_BRK0NFSEL_Msk (0x7ul << PWM_BNF_BRK0NFSEL_Pos) /*!< PWM_T::BNF: BRK0NFSEL Mask */
+
+#define PWM_BNF_BRK0FCNT_Pos (4) /*!< PWM_T::BNF: BRK0FCNT Position */
+#define PWM_BNF_BRK0FCNT_Msk (0x7ul << PWM_BNF_BRK0FCNT_Pos) /*!< PWM_T::BNF: BRK0FCNT Mask */
+
+#define PWM_BNF_BRK0PINV_Pos (7) /*!< PWM_T::BNF: BRK0PINV Position */
+#define PWM_BNF_BRK0PINV_Msk (0x1ul << PWM_BNF_BRK0PINV_Pos) /*!< PWM_T::BNF: BRK0PINV Mask */
+
+#define PWM_BNF_BRK1NFEN_Pos (8) /*!< PWM_T::BNF: BRK1NFEN Position */
+#define PWM_BNF_BRK1NFEN_Msk (0x1ul << PWM_BNF_BRK1NFEN_Pos) /*!< PWM_T::BNF: BRK1NFEN Mask */
+
+#define PWM_BNF_BRK1NFSEL_Pos (9) /*!< PWM_T::BNF: BRK1NFSEL Position */
+#define PWM_BNF_BRK1NFSEL_Msk (0x7ul << PWM_BNF_BRK1NFSEL_Pos) /*!< PWM_T::BNF: BRK1NFSEL Mask */
+
+#define PWM_BNF_BRK1FCNT_Pos (12) /*!< PWM_T::BNF: BRK1FCNT Position */
+#define PWM_BNF_BRK1FCNT_Msk (0x7ul << PWM_BNF_BRK1FCNT_Pos) /*!< PWM_T::BNF: BRK1FCNT Mask */
+
+#define PWM_BNF_BRK1PINV_Pos (15) /*!< PWM_T::BNF: BRK1PINV Position */
+#define PWM_BNF_BRK1PINV_Msk (0x1ul << PWM_BNF_BRK1PINV_Pos) /*!< PWM_T::BNF: BRK1PINV Mask */
+
+#define PWM_BNF_BK0SRC_Pos (16) /*!< PWM_T::BNF: BK0SRC Position */
+#define PWM_BNF_BK0SRC_Msk (0x1ul << PWM_BNF_BK0SRC_Pos) /*!< PWM_T::BNF: BK0SRC Mask */
+
+#define PWM_BNF_BK1SRC_Pos (24) /*!< PWM_T::BNF: BK1SRC Position */
+#define PWM_BNF_BK1SRC_Msk (0x1ul << PWM_BNF_BK1SRC_Pos) /*!< PWM_T::BNF: BK1SRC Mask */
+
+#define PWM_FAILBRK_CSSBRKEN_Pos (0) /*!< PWM_T::FAILBRK: CSSBRKEN Position */
+#define PWM_FAILBRK_CSSBRKEN_Msk (0x1ul << PWM_FAILBRK_CSSBRKEN_Pos) /*!< PWM_T::FAILBRK: CSSBRKEN Mask */
+
+#define PWM_FAILBRK_BODBRKEN_Pos (1) /*!< PWM_T::FAILBRK: BODBRKEN Position */
+#define PWM_FAILBRK_BODBRKEN_Msk (0x1ul << PWM_FAILBRK_BODBRKEN_Pos) /*!< PWM_T::FAILBRK: BODBRKEN Mask */
+
+#define PWM_FAILBRK_RAMBRKEN_Pos (2) /*!< PWM_T::FAILBRK: RAMBRKEN Position */
+#define PWM_FAILBRK_RAMBRKEN_Msk (0x1ul << PWM_FAILBRK_RAMBRKEN_Pos) /*!< PWM_T::FAILBRK: RAMBRKEN Mask */
+
+#define PWM_FAILBRK_CORBRKEN_Pos (3) /*!< PWM_T::FAILBRK: CORBRKEN Position */
+#define PWM_FAILBRK_CORBRKEN_Msk (0x1ul << PWM_FAILBRK_CORBRKEN_Pos) /*!< PWM_T::FAILBRK: CORBRKEN Mask */
+
+#define PWM_BRKCTL0_1_CPO0EBEN_Pos (0) /*!< PWM_T::BRKCTL0_1: CPO0EBEN Position */
+#define PWM_BRKCTL0_1_CPO0EBEN_Msk (0x1ul << PWM_BRKCTL0_1_CPO0EBEN_Pos) /*!< PWM_T::BRKCTL0_1: CPO0EBEN Mask */
+
+#define PWM_BRKCTL0_1_CPO1EBEN_Pos (1) /*!< PWM_T::BRKCTL0_1: CPO1EBEN Position */
+#define PWM_BRKCTL0_1_CPO1EBEN_Msk (0x1ul << PWM_BRKCTL0_1_CPO1EBEN_Pos) /*!< PWM_T::BRKCTL0_1: CPO1EBEN Mask */
+
+#define PWM_BRKCTL0_1_BRKP0EEN_Pos (4) /*!< PWM_T::BRKCTL0_1: BRKP0EEN Position */
+#define PWM_BRKCTL0_1_BRKP0EEN_Msk (0x1ul << PWM_BRKCTL0_1_BRKP0EEN_Pos) /*!< PWM_T::BRKCTL0_1: BRKP0EEN Mask */
+
+#define PWM_BRKCTL0_1_BRKP1EEN_Pos (5) /*!< PWM_T::BRKCTL0_1: BRKP1EEN Position */
+#define PWM_BRKCTL0_1_BRKP1EEN_Msk (0x1ul << PWM_BRKCTL0_1_BRKP1EEN_Pos) /*!< PWM_T::BRKCTL0_1: BRKP1EEN Mask */
+
+#define PWM_BRKCTL0_1_SYSEBEN_Pos (7) /*!< PWM_T::BRKCTL0_1: SYSEBEN Position */
+#define PWM_BRKCTL0_1_SYSEBEN_Msk (0x1ul << PWM_BRKCTL0_1_SYSEBEN_Pos) /*!< PWM_T::BRKCTL0_1: SYSEBEN Mask */
+
+#define PWM_BRKCTL0_1_CPO0LBEN_Pos (8) /*!< PWM_T::BRKCTL0_1: CPO0LBEN Position */
+#define PWM_BRKCTL0_1_CPO0LBEN_Msk (0x1ul << PWM_BRKCTL0_1_CPO0LBEN_Pos) /*!< PWM_T::BRKCTL0_1: CPO0LBEN Mask */
+
+#define PWM_BRKCTL0_1_CPO1LBEN_Pos (9) /*!< PWM_T::BRKCTL0_1: CPO1LBEN Position */
+#define PWM_BRKCTL0_1_CPO1LBEN_Msk (0x1ul << PWM_BRKCTL0_1_CPO1LBEN_Pos) /*!< PWM_T::BRKCTL0_1: CPO1LBEN Mask */
+
+#define PWM_BRKCTL0_1_BRKP0LEN_Pos (12) /*!< PWM_T::BRKCTL0_1: BRKP0LEN Position */
+#define PWM_BRKCTL0_1_BRKP0LEN_Msk (0x1ul << PWM_BRKCTL0_1_BRKP0LEN_Pos) /*!< PWM_T::BRKCTL0_1: BRKP0LEN Mask */
+
+#define PWM_BRKCTL0_1_BRKP1LEN_Pos (13) /*!< PWM_T::BRKCTL0_1: BRKP1LEN Position */
+#define PWM_BRKCTL0_1_BRKP1LEN_Msk (0x1ul << PWM_BRKCTL0_1_BRKP1LEN_Pos) /*!< PWM_T::BRKCTL0_1: BRKP1LEN Mask */
+
+#define PWM_BRKCTL0_1_SYSLBEN_Pos (15) /*!< PWM_T::BRKCTL0_1: SYSLBEN Position */
+#define PWM_BRKCTL0_1_SYSLBEN_Msk (0x1ul << PWM_BRKCTL0_1_SYSLBEN_Pos) /*!< PWM_T::BRKCTL0_1: SYSLBEN Mask */
+
+#define PWM_BRKCTL0_1_BRKAEVEN_Pos (16) /*!< PWM_T::BRKCTL0_1: BRKAEVEN Position */
+#define PWM_BRKCTL0_1_BRKAEVEN_Msk (0x3ul << PWM_BRKCTL0_1_BRKAEVEN_Pos) /*!< PWM_T::BRKCTL0_1: BRKAEVEN Mask */
+
+#define PWM_BRKCTL0_1_BRKAODD_Pos (18) /*!< PWM_T::BRKCTL0_1: BRKAODD Position */
+#define PWM_BRKCTL0_1_BRKAODD_Msk (0x3ul << PWM_BRKCTL0_1_BRKAODD_Pos) /*!< PWM_T::BRKCTL0_1: BRKAODD Mask */
+
+#define PWM_BRKCTL2_3_CPO0EBEN_Pos (0) /*!< PWM_T::BRKCTL2_3: CPO0EBEN Position */
+#define PWM_BRKCTL2_3_CPO0EBEN_Msk (0x1ul << PWM_BRKCTL2_3_CPO0EBEN_Pos) /*!< PWM_T::BRKCTL2_3: CPO0EBEN Mask */
+
+#define PWM_BRKCTL2_3_CPO1EBEN_Pos (1) /*!< PWM_T::BRKCTL2_3: CPO1EBEN Position */
+#define PWM_BRKCTL2_3_CPO1EBEN_Msk (0x1ul << PWM_BRKCTL2_3_CPO1EBEN_Pos) /*!< PWM_T::BRKCTL2_3: CPO1EBEN Mask */
+
+#define PWM_BRKCTL2_3_BRKP0EEN_Pos (4) /*!< PWM_T::BRKCTL2_3: BRKP0EEN Position */
+#define PWM_BRKCTL2_3_BRKP0EEN_Msk (0x1ul << PWM_BRKCTL2_3_BRKP0EEN_Pos) /*!< PWM_T::BRKCTL2_3: BRKP0EEN Mask */
+
+#define PWM_BRKCTL2_3_BRKP1EEN_Pos (5) /*!< PWM_T::BRKCTL2_3: BRKP1EEN Position */
+#define PWM_BRKCTL2_3_BRKP1EEN_Msk (0x1ul << PWM_BRKCTL2_3_BRKP1EEN_Pos) /*!< PWM_T::BRKCTL2_3: BRKP1EEN Mask */
+
+#define PWM_BRKCTL2_3_SYSEBEN_Pos (7) /*!< PWM_T::BRKCTL2_3: SYSEBEN Position */
+#define PWM_BRKCTL2_3_SYSEBEN_Msk (0x1ul << PWM_BRKCTL2_3_SYSEBEN_Pos) /*!< PWM_T::BRKCTL2_3: SYSEBEN Mask */
+
+#define PWM_BRKCTL2_3_CPO0LBEN_Pos (8) /*!< PWM_T::BRKCTL2_3: CPO0LBEN Position */
+#define PWM_BRKCTL2_3_CPO0LBEN_Msk (0x1ul << PWM_BRKCTL2_3_CPO0LBEN_Pos) /*!< PWM_T::BRKCTL2_3: CPO0LBEN Mask */
+
+#define PWM_BRKCTL2_3_CPO1LBEN_Pos (9) /*!< PWM_T::BRKCTL2_3: CPO1LBEN Position */
+#define PWM_BRKCTL2_3_CPO1LBEN_Msk (0x1ul << PWM_BRKCTL2_3_CPO1LBEN_Pos) /*!< PWM_T::BRKCTL2_3: CPO1LBEN Mask */
+
+#define PWM_BRKCTL2_3_BRKP0LEN_Pos (12) /*!< PWM_T::BRKCTL2_3: BRKP0LEN Position */
+#define PWM_BRKCTL2_3_BRKP0LEN_Msk (0x1ul << PWM_BRKCTL2_3_BRKP0LEN_Pos) /*!< PWM_T::BRKCTL2_3: BRKP0LEN Mask */
+
+#define PWM_BRKCTL2_3_BRKP1LEN_Pos (13) /*!< PWM_T::BRKCTL2_3: BRKP1LEN Position */
+#define PWM_BRKCTL2_3_BRKP1LEN_Msk (0x1ul << PWM_BRKCTL2_3_BRKP1LEN_Pos) /*!< PWM_T::BRKCTL2_3: BRKP1LEN Mask */
+
+#define PWM_BRKCTL2_3_SYSLBEN_Pos (15) /*!< PWM_T::BRKCTL2_3: SYSLBEN Position */
+#define PWM_BRKCTL2_3_SYSLBEN_Msk (0x1ul << PWM_BRKCTL2_3_SYSLBEN_Pos) /*!< PWM_T::BRKCTL2_3: SYSLBEN Mask */
+
+#define PWM_BRKCTL2_3_BRKAEVEN_Pos (16) /*!< PWM_T::BRKCTL2_3: BRKAEVEN Position */
+#define PWM_BRKCTL2_3_BRKAEVEN_Msk (0x3ul << PWM_BRKCTL2_3_BRKAEVEN_Pos) /*!< PWM_T::BRKCTL2_3: BRKAEVEN Mask */
+
+#define PWM_BRKCTL2_3_BRKAODD_Pos (18) /*!< PWM_T::BRKCTL2_3: BRKAODD Position */
+#define PWM_BRKCTL2_3_BRKAODD_Msk (0x3ul << PWM_BRKCTL2_3_BRKAODD_Pos) /*!< PWM_T::BRKCTL2_3: BRKAODD Mask */
+
+#define PWM_BRKCTL4_5_CPO0EBEN_Pos (0) /*!< PWM_T::BRKCTL4_5: CPO0EBEN Position */
+#define PWM_BRKCTL4_5_CPO0EBEN_Msk (0x1ul << PWM_BRKCTL4_5_CPO0EBEN_Pos) /*!< PWM_T::BRKCTL4_5: CPO0EBEN Mask */
+
+#define PWM_BRKCTL4_5_CPO1EBEN_Pos (1) /*!< PWM_T::BRKCTL4_5: CPO1EBEN Position */
+#define PWM_BRKCTL4_5_CPO1EBEN_Msk (0x1ul << PWM_BRKCTL4_5_CPO1EBEN_Pos) /*!< PWM_T::BRKCTL4_5: CPO1EBEN Mask */
+
+#define PWM_BRKCTL4_5_BRKP0EEN_Pos (4) /*!< PWM_T::BRKCTL4_5: BRKP0EEN Position */
+#define PWM_BRKCTL4_5_BRKP0EEN_Msk (0x1ul << PWM_BRKCTL4_5_BRKP0EEN_Pos) /*!< PWM_T::BRKCTL4_5: BRKP0EEN Mask */
+
+#define PWM_BRKCTL4_5_BRKP1EEN_Pos (5) /*!< PWM_T::BRKCTL4_5: BRKP1EEN Position */
+#define PWM_BRKCTL4_5_BRKP1EEN_Msk (0x1ul << PWM_BRKCTL4_5_BRKP1EEN_Pos) /*!< PWM_T::BRKCTL4_5: BRKP1EEN Mask */
+
+#define PWM_BRKCTL4_5_SYSEBEN_Pos (7) /*!< PWM_T::BRKCTL4_5: SYSEBEN Position */
+#define PWM_BRKCTL4_5_SYSEBEN_Msk (0x1ul << PWM_BRKCTL4_5_SYSEBEN_Pos) /*!< PWM_T::BRKCTL4_5: SYSEBEN Mask */
+
+#define PWM_BRKCTL4_5_CPO0LBEN_Pos (8) /*!< PWM_T::BRKCTL4_5: CPO0LBEN Position */
+#define PWM_BRKCTL4_5_CPO0LBEN_Msk (0x1ul << PWM_BRKCTL4_5_CPO0LBEN_Pos) /*!< PWM_T::BRKCTL4_5: CPO0LBEN Mask */
+
+#define PWM_BRKCTL4_5_CPO1LBEN_Pos (9) /*!< PWM_T::BRKCTL4_5: CPO1LBEN Position */
+#define PWM_BRKCTL4_5_CPO1LBEN_Msk (0x1ul << PWM_BRKCTL4_5_CPO1LBEN_Pos) /*!< PWM_T::BRKCTL4_5: CPO1LBEN Mask */
+
+#define PWM_BRKCTL4_5_BRKP0LEN_Pos (12) /*!< PWM_T::BRKCTL4_5: BRKP0LEN Position */
+#define PWM_BRKCTL4_5_BRKP0LEN_Msk (0x1ul << PWM_BRKCTL4_5_BRKP0LEN_Pos) /*!< PWM_T::BRKCTL4_5: BRKP0LEN Mask */
+
+#define PWM_BRKCTL4_5_BRKP1LEN_Pos (13) /*!< PWM_T::BRKCTL4_5: BRKP1LEN Position */
+#define PWM_BRKCTL4_5_BRKP1LEN_Msk (0x1ul << PWM_BRKCTL4_5_BRKP1LEN_Pos) /*!< PWM_T::BRKCTL4_5: BRKP1LEN Mask */
+
+#define PWM_BRKCTL4_5_SYSLBEN_Pos (15) /*!< PWM_T::BRKCTL4_5: SYSLBEN Position */
+#define PWM_BRKCTL4_5_SYSLBEN_Msk (0x1ul << PWM_BRKCTL4_5_SYSLBEN_Pos) /*!< PWM_T::BRKCTL4_5: SYSLBEN Mask */
+
+#define PWM_BRKCTL4_5_BRKAEVEN_Pos (16) /*!< PWM_T::BRKCTL4_5: BRKAEVEN Position */
+#define PWM_BRKCTL4_5_BRKAEVEN_Msk (0x3ul << PWM_BRKCTL4_5_BRKAEVEN_Pos) /*!< PWM_T::BRKCTL4_5: BRKAEVEN Mask */
+
+#define PWM_BRKCTL4_5_BRKAODD_Pos (18) /*!< PWM_T::BRKCTL4_5: BRKAODD Position */
+#define PWM_BRKCTL4_5_BRKAODD_Msk (0x3ul << PWM_BRKCTL4_5_BRKAODD_Pos) /*!< PWM_T::BRKCTL4_5: BRKAODD Mask */
+
+#define PWM_POLCTL_PINVn_Pos (0) /*!< PWM_T::POLCTL: PINVn Position */
+#define PWM_POLCTL_PINVn_Msk (0x3ful << PWM_POLCTL_PINVn_Pos) /*!< PWM_T::POLCTL: PINVn Mask */
+
+#define PWM_POLCTL_PINV0_Pos (0) /*!< PWM_T::POLCTL: PINV0 Position */
+#define PWM_POLCTL_PINV0_Msk (0x1ul << PWM_POLCTL_PINV0_Pos) /*!< PWM_T::POLCTL: PINV0 Mask */
+
+#define PWM_POLCTL_PINV1_Pos (1) /*!< PWM_T::POLCTL: PINV1 Position */
+#define PWM_POLCTL_PINV1_Msk (0x1ul << PWM_POLCTL_PINV1_Pos) /*!< PWM_T::POLCTL: PINV1 Mask */
+
+#define PWM_POLCTL_PINV2_Pos (2) /*!< PWM_T::POLCTL: PINV2 Position */
+#define PWM_POLCTL_PINV2_Msk (0x1ul << PWM_POLCTL_PINV2_Pos) /*!< PWM_T::POLCTL: PINV2 Mask */
+
+#define PWM_POLCTL_PINV3_Pos (3) /*!< PWM_T::POLCTL: PINV3 Position */
+#define PWM_POLCTL_PINV3_Msk (0x1ul << PWM_POLCTL_PINV3_Pos) /*!< PWM_T::POLCTL: PINV3 Mask */
+
+#define PWM_POLCTL_PINV4_Pos (4) /*!< PWM_T::POLCTL: PINV4 Position */
+#define PWM_POLCTL_PINV4_Msk (0x1ul << PWM_POLCTL_PINV4_Pos) /*!< PWM_T::POLCTL: PINV4 Mask */
+
+#define PWM_POLCTL_PINV5_Pos (5) /*!< PWM_T::POLCTL: PINV5 Position */
+#define PWM_POLCTL_PINV5_Msk (0x1ul << PWM_POLCTL_PINV5_Pos) /*!< PWM_T::POLCTL: PINV5 Mask */
+
+#define PWM_POEN_POENn_Pos (0) /*!< PWM_T::POEN: POENn Position */
+#define PWM_POEN_POENn_Msk (0x3ful << PWM_POEN_POENn_Pos) /*!< PWM_T::POEN: POENn Mask */
+
+#define PWM_POEN_POEN0_Pos (0) /*!< PWM_T::POEN: POEN0 Position */
+#define PWM_POEN_POEN0_Msk (0x1ul << PWM_POEN_POEN0_Pos) /*!< PWM_T::POEN: POEN0 Mask */
+
+#define PWM_POEN_POEN1_Pos (1) /*!< PWM_T::POEN: POEN1 Position */
+#define PWM_POEN_POEN1_Msk (0x1ul << PWM_POEN_POEN1_Pos) /*!< PWM_T::POEN: POEN1 Mask */
+
+#define PWM_POEN_POEN2_Pos (2) /*!< PWM_T::POEN: POEN2 Position */
+#define PWM_POEN_POEN2_Msk (0x1ul << PWM_POEN_POEN2_Pos) /*!< PWM_T::POEN: POEN2 Mask */
+
+#define PWM_POEN_POEN3_Pos (3) /*!< PWM_T::POEN: POEN3 Position */
+#define PWM_POEN_POEN3_Msk (0x1ul << PWM_POEN_POEN3_Pos) /*!< PWM_T::POEN: POEN3 Mask */
+
+#define PWM_POEN_POEN4_Pos (4) /*!< PWM_T::POEN: POEN4 Position */
+#define PWM_POEN_POEN4_Msk (0x1ul << PWM_POEN_POEN4_Pos) /*!< PWM_T::POEN: POEN4 Mask */
+
+#define PWM_POEN_POEN5_Pos (5) /*!< PWM_T::POEN: POEN5 Position */
+#define PWM_POEN_POEN5_Msk (0x1ul << PWM_POEN_POEN5_Pos) /*!< PWM_T::POEN: POEN5 Mask */
+
+#define PWM_SWBRK_BRKETRGn_Pos (0) /*!< PWM_T::SWBRK: BRKETRGn Position */
+#define PWM_SWBRK_BRKETRGn_Msk (0x7ul << PWM_SWBRK_BRKETRGn_Pos) /*!< PWM_T::SWBRK: BRKETRGn Mask */
+
+#define PWM_SWBRK_BRKETRG0_Pos (0) /*!< PWM_T::SWBRK: BRKETRG0 Position */
+#define PWM_SWBRK_BRKETRG0_Msk (0x1ul << PWM_SWBRK_BRKETRG0_Pos) /*!< PWM_T::SWBRK: BRKETRG0 Mask */
+
+#define PWM_SWBRK_BRKETRG2_Pos (1) /*!< PWM_T::SWBRK: BRKETRG2 Position */
+#define PWM_SWBRK_BRKETRG2_Msk (0x1ul << PWM_SWBRK_BRKETRG2_Pos) /*!< PWM_T::SWBRK: BRKETRG2 Mask */
+
+#define PWM_SWBRK_BRKETRG4_Pos (2) /*!< PWM_T::SWBRK: BRKETRG4 Position */
+#define PWM_SWBRK_BRKETRG4_Msk (0x1ul << PWM_SWBRK_BRKETRG4_Pos) /*!< PWM_T::SWBRK: BRKETRG4 Mask */
+
+#define PWM_SWBRK_BRKLTRGn_Pos (8) /*!< PWM_T::SWBRK: BRKLTRGn Position */
+#define PWM_SWBRK_BRKLTRGn_Msk (0x7ul << PWM_SWBRK_BRKLTRGn_Pos) /*!< PWM_T::SWBRK: BRKLTRGn Mask */
+
+#define PWM_SWBRK_BRKLTRG0_Pos (8) /*!< PWM_T::SWBRK: BRKLTRG0 Position */
+#define PWM_SWBRK_BRKLTRG0_Msk (0x1ul << PWM_SWBRK_BRKLTRG0_Pos) /*!< PWM_T::SWBRK: BRKLTRG0 Mask */
+
+#define PWM_SWBRK_BRKLTRG2_Pos (9) /*!< PWM_T::SWBRK: BRKLTRG2 Position */
+#define PWM_SWBRK_BRKLTRG2_Msk (0x1ul << PWM_SWBRK_BRKLTRG2_Pos) /*!< PWM_T::SWBRK: BRKLTRG2 Mask */
+
+#define PWM_SWBRK_BRKLTRG4_Pos (10) /*!< PWM_T::SWBRK: BRKLTRG4 Position */
+#define PWM_SWBRK_BRKLTRG4_Msk (0x1ul << PWM_SWBRK_BRKLTRG4_Pos) /*!< PWM_T::SWBRK: BRKLTRG4 Mask */
+
+#define PWM_INTEN0_ZIENn_Pos (0) /*!< PWM_T::INTEN0: ZIENn Position */
+#define PWM_INTEN0_ZIENn_Msk (0x3ful << PWM_INTEN0_ZIENn_Pos) /*!< PWM_T::INTEN0: ZIENn Mask */
+
+#define PWM_INTEN0_ZIEN0_Pos (0) /*!< PWM_T::INTEN0: ZIEN0 Position */
+#define PWM_INTEN0_ZIEN0_Msk (0x1ul << PWM_INTEN0_ZIEN0_Pos) /*!< PWM_T::INTEN0: ZIEN0 Mask */
+
+#define PWM_INTEN0_ZIEN1_Pos (1) /*!< PWM_T::INTEN0: ZIEN1 Position */
+#define PWM_INTEN0_ZIEN1_Msk (0x1ul << PWM_INTEN0_ZIEN1_Pos) /*!< PWM_T::INTEN0: ZIEN1 Mask */
+
+#define PWM_INTEN0_ZIEN2_Pos (2) /*!< PWM_T::INTEN0: ZIEN2 Position */
+#define PWM_INTEN0_ZIEN2_Msk (0x1ul << PWM_INTEN0_ZIEN2_Pos) /*!< PWM_T::INTEN0: ZIEN2 Mask */
+
+#define PWM_INTEN0_ZIEN3_Pos (3) /*!< PWM_T::INTEN0: ZIEN3 Position */
+#define PWM_INTEN0_ZIEN3_Msk (0x1ul << PWM_INTEN0_ZIEN3_Pos) /*!< PWM_T::INTEN0: ZIEN3 Mask */
+
+#define PWM_INTEN0_ZIEN4_Pos (4) /*!< PWM_T::INTEN0: ZIEN4 Position */
+#define PWM_INTEN0_ZIEN4_Msk (0x1ul << PWM_INTEN0_ZIEN4_Pos) /*!< PWM_T::INTEN0: ZIEN4 Mask */
+
+#define PWM_INTEN0_ZIEN5_Pos (5) /*!< PWM_T::INTEN0: ZIEN5 Position */
+#define PWM_INTEN0_ZIEN5_Msk (0x1ul << PWM_INTEN0_ZIEN5_Pos) /*!< PWM_T::INTEN0: ZIEN5 Mask */
+
+#define PWM_INTEN0_IFAIEN0_1_Pos (7) /*!< PWM_T::INTEN0: IFAIEN0_1 Position */
+#define PWM_INTEN0_IFAIEN0_1_Msk (0x1ul << PWM_INTEN0_IFAIEN0_1_Pos) /*!< PWM_T::INTEN0: IFAIEN0_1 Mask */
+
+#define PWM_INTEN0_PIENn_Pos (8) /*!< PWM_T::INTEN0: PIENn Position */
+#define PWM_INTEN0_PIENn_Msk (0x3ful << PWM_INTEN0_PIENn_Pos) /*!< PWM_T::INTEN0: PIENn Mask */
+
+#define PWM_INTEN0_PIEN0_Pos (8) /*!< PWM_T::INTEN0: PIEN0 Position */
+#define PWM_INTEN0_PIEN0_Msk (0x1ul << PWM_INTEN0_PIEN0_Pos) /*!< PWM_T::INTEN0: PIEN0 Mask */
+
+#define PWM_INTEN0_PIEN1_Pos (9) /*!< PWM_T::INTEN0: PIEN1 Position */
+#define PWM_INTEN0_PIEN1_Msk (0x1ul << PWM_INTEN0_PIEN1_Pos) /*!< PWM_T::INTEN0: PIEN1 Mask */
+
+#define PWM_INTEN0_PIEN2_Pos (10) /*!< PWM_T::INTEN0: PIEN2 Position */
+#define PWM_INTEN0_PIEN2_Msk (0x1ul << PWM_INTEN0_PIEN2_Pos) /*!< PWM_T::INTEN0: PIEN2 Mask */
+
+#define PWM_INTEN0_PIEN3_Pos (11) /*!< PWM_T::INTEN0: PIEN3 Position */
+#define PWM_INTEN0_PIEN3_Msk (0x1ul << PWM_INTEN0_PIEN3_Pos) /*!< PWM_T::INTEN0: PIEN3 Mask */
+
+#define PWM_INTEN0_PIEN4_Pos (12) /*!< PWM_T::INTEN0: PIEN4 Position */
+#define PWM_INTEN0_PIEN4_Msk (0x1ul << PWM_INTEN0_PIEN4_Pos) /*!< PWM_T::INTEN0: PIEN4 Mask */
+
+#define PWM_INTEN0_PIEN5_Pos (13) /*!< PWM_T::INTEN0: PIEN5 Position */
+#define PWM_INTEN0_PIEN5_Msk (0x1ul << PWM_INTEN0_PIEN5_Pos) /*!< PWM_T::INTEN0: PIEN5 Mask */
+
+#define PWM_INTEN0_IFAIEN2_3_Pos (15) /*!< PWM_T::INTEN0: IFAIEN2_3 Position */
+#define PWM_INTEN0_IFAIEN2_3_Msk (0x1ul << PWM_INTEN0_IFAIEN2_3_Pos) /*!< PWM_T::INTEN0: IFAIEN2_3 Mask */
+
+#define PWM_INTEN0_CMPUIENn_Pos (16) /*!< PWM_T::INTEN0: CMPUIENn Position */
+#define PWM_INTEN0_CMPUIENn_Msk (0x3ful << PWM_INTEN0_CMPUIENn_Pos) /*!< PWM_T::INTEN0: CMPUIENn Mask */
+
+#define PWM_INTEN0_CMPUIEN0_Pos (16) /*!< PWM_T::INTEN0: CMPUIEN0 Position */
+#define PWM_INTEN0_CMPUIEN0_Msk (0x1ul << PWM_INTEN0_CMPUIEN0_Pos) /*!< PWM_T::INTEN0: CMPUIEN0 Mask */
+
+#define PWM_INTEN0_CMPUIEN1_Pos (17) /*!< PWM_T::INTEN0: CMPUIEN1 Position */
+#define PWM_INTEN0_CMPUIEN1_Msk (0x1ul << PWM_INTEN0_CMPUIEN1_Pos) /*!< PWM_T::INTEN0: CMPUIEN1 Mask */
+
+#define PWM_INTEN0_CMPUIEN2_Pos (18) /*!< PWM_T::INTEN0: CMPUIEN2 Position */
+#define PWM_INTEN0_CMPUIEN2_Msk (0x1ul << PWM_INTEN0_CMPUIEN2_Pos) /*!< PWM_T::INTEN0: CMPUIEN2 Mask */
+
+#define PWM_INTEN0_CMPUIEN3_Pos (19) /*!< PWM_T::INTEN0: CMPUIEN3 Position */
+#define PWM_INTEN0_CMPUIEN3_Msk (0x1ul << PWM_INTEN0_CMPUIEN3_Pos) /*!< PWM_T::INTEN0: CMPUIEN3 Mask */
+
+#define PWM_INTEN0_CMPUIEN4_Pos (20) /*!< PWM_T::INTEN0: CMPUIEN4 Position */
+#define PWM_INTEN0_CMPUIEN4_Msk (0x1ul << PWM_INTEN0_CMPUIEN4_Pos) /*!< PWM_T::INTEN0: CMPUIEN4 Mask */
+
+#define PWM_INTEN0_CMPUIEN5_Pos (21) /*!< PWM_T::INTEN0: CMPUIEN5 Position */
+#define PWM_INTEN0_CMPUIEN5_Msk (0x1ul << PWM_INTEN0_CMPUIEN5_Pos) /*!< PWM_T::INTEN0: CMPUIEN5 Mask */
+
+#define PWM_INTEN0_IFAIEN4_5_Pos (23) /*!< PWM_T::INTEN0: IFAIEN4_5 Position */
+#define PWM_INTEN0_IFAIEN4_5_Msk (0x1ul << PWM_INTEN0_IFAIEN4_5_Pos) /*!< PWM_T::INTEN0: IFAIEN4_5 Mask */
+
+#define PWM_INTEN0_CMPDIENn_Pos (24) /*!< PWM_T::INTEN0: CMPDIENn Position */
+#define PWM_INTEN0_CMPDIENn_Msk (0x3ful << PWM_INTEN0_CMPDIENn_Pos) /*!< PWM_T::INTEN0: CMPDIENn Mask */
+
+#define PWM_INTEN0_CMPDIEN0_Pos (24) /*!< PWM_T::INTEN0: CMPDIEN0 Position */
+#define PWM_INTEN0_CMPDIEN0_Msk (0x1ul << PWM_INTEN0_CMPDIEN0_Pos) /*!< PWM_T::INTEN0: CMPDIEN0 Mask */
+
+#define PWM_INTEN0_CMPDIEN1_Pos (25) /*!< PWM_T::INTEN0: CMPDIEN1 Position */
+#define PWM_INTEN0_CMPDIEN1_Msk (0x1ul << PWM_INTEN0_CMPDIEN1_Pos) /*!< PWM_T::INTEN0: CMPDIEN1 Mask */
+
+#define PWM_INTEN0_CMPDIEN2_Pos (26) /*!< PWM_T::INTEN0: CMPDIEN2 Position */
+#define PWM_INTEN0_CMPDIEN2_Msk (0x1ul << PWM_INTEN0_CMPDIEN2_Pos) /*!< PWM_T::INTEN0: CMPDIEN2 Mask */
+
+#define PWM_INTEN0_CMPDIEN3_Pos (27) /*!< PWM_T::INTEN0: CMPDIEN3 Position */
+#define PWM_INTEN0_CMPDIEN3_Msk (0x1ul << PWM_INTEN0_CMPDIEN3_Pos) /*!< PWM_T::INTEN0: CMPDIEN3 Mask */
+
+#define PWM_INTEN0_CMPDIEN4_Pos (28) /*!< PWM_T::INTEN0: CMPDIEN4 Position */
+#define PWM_INTEN0_CMPDIEN4_Msk (0x1ul << PWM_INTEN0_CMPDIEN4_Pos) /*!< PWM_T::INTEN0: CMPDIEN4 Mask */
+
+#define PWM_INTEN0_CMPDIEN5_Pos (29) /*!< PWM_T::INTEN0: CMPDIEN5 Position */
+#define PWM_INTEN0_CMPDIEN5_Msk (0x1ul << PWM_INTEN0_CMPDIEN5_Pos) /*!< PWM_T::INTEN0: CMPDIEN5 Mask */
+
+#define PWM_INTEN1_BRKEIEN0_1_Pos (0) /*!< PWM_T::INTEN1: BRKEIEN0_1 Position */
+#define PWM_INTEN1_BRKEIEN0_1_Msk (0x1ul << PWM_INTEN1_BRKEIEN0_1_Pos) /*!< PWM_T::INTEN1: BRKEIEN0_1 Mask */
+
+#define PWM_INTEN1_BRKEIEN2_3_Pos (1) /*!< PWM_T::INTEN1: BRKEIEN2_3 Position */
+#define PWM_INTEN1_BRKEIEN2_3_Msk (0x1ul << PWM_INTEN1_BRKEIEN2_3_Pos) /*!< PWM_T::INTEN1: BRKEIEN2_3 Mask */
+
+#define PWM_INTEN1_BRKEIEN4_5_Pos (2) /*!< PWM_T::INTEN1: BRKEIEN4_5 Position */
+#define PWM_INTEN1_BRKEIEN4_5_Msk (0x1ul << PWM_INTEN1_BRKEIEN4_5_Pos) /*!< PWM_T::INTEN1: BRKEIEN4_5 Mask */
+
+#define PWM_INTEN1_BRKLIEN0_1_Pos (8) /*!< PWM_T::INTEN1: BRKLIEN0_1 Position */
+#define PWM_INTEN1_BRKLIEN0_1_Msk (0x1ul << PWM_INTEN1_BRKLIEN0_1_Pos) /*!< PWM_T::INTEN1: BRKLIEN0_1 Mask */
+
+#define PWM_INTEN1_BRKLIEN2_3_Pos (9) /*!< PWM_T::INTEN1: BRKLIEN2_3 Position */
+#define PWM_INTEN1_BRKLIEN2_3_Msk (0x1ul << PWM_INTEN1_BRKLIEN2_3_Pos) /*!< PWM_T::INTEN1: BRKLIEN2_3 Mask */
+
+#define PWM_INTEN1_BRKLIEN4_5_Pos (10) /*!< PWM_T::INTEN1: BRKLIEN4_5 Position */
+#define PWM_INTEN1_BRKLIEN4_5_Msk (0x1ul << PWM_INTEN1_BRKLIEN4_5_Pos) /*!< PWM_T::INTEN1: BRKLIEN4_5 Mask */
+
+#define PWM_INTSTS0_ZIFn_Pos (0) /*!< PWM_T::INTSTS0: ZIFn Position */
+#define PWM_INTSTS0_ZIFn_Msk (0x3ful << PWM_INTSTS0_ZIFn_Pos) /*!< PWM_T::INTSTS0: ZIFn Mask */
+
+#define PWM_INTSTS0_ZIF0_Pos (0) /*!< PWM_T::INTSTS0: ZIF0 Position */
+#define PWM_INTSTS0_ZIF0_Msk (0x1ul << PWM_INTSTS0_ZIF0_Pos) /*!< PWM_T::INTSTS0: ZIF0 Mask */
+
+#define PWM_INTSTS0_ZIF1_Pos (1) /*!< PWM_T::INTSTS0: ZIF1 Position */
+#define PWM_INTSTS0_ZIF1_Msk (0x1ul << PWM_INTSTS0_ZIF1_Pos) /*!< PWM_T::INTSTS0: ZIF1 Mask */
+
+#define PWM_INTSTS0_ZIF2_Pos (2) /*!< PWM_T::INTSTS0: ZIF2 Position */
+#define PWM_INTSTS0_ZIF2_Msk (0x1ul << PWM_INTSTS0_ZIF2_Pos) /*!< PWM_T::INTSTS0: ZIF2 Mask */
+
+#define PWM_INTSTS0_ZIF3_Pos (3) /*!< PWM_T::INTSTS0: ZIF3 Position */
+#define PWM_INTSTS0_ZIF3_Msk (0x1ul << PWM_INTSTS0_ZIF3_Pos) /*!< PWM_T::INTSTS0: ZIF3 Mask */
+
+#define PWM_INTSTS0_ZIF4_Pos (4) /*!< PWM_T::INTSTS0: ZIF4 Position */
+#define PWM_INTSTS0_ZIF4_Msk (0x1ul << PWM_INTSTS0_ZIF4_Pos) /*!< PWM_T::INTSTS0: ZIF4 Mask */
+
+#define PWM_INTSTS0_ZIF5_Pos (5) /*!< PWM_T::INTSTS0: ZIF5 Position */
+#define PWM_INTSTS0_ZIF5_Msk (0x1ul << PWM_INTSTS0_ZIF5_Pos) /*!< PWM_T::INTSTS0: ZIF5 Mask */
+
+#define PWM_INTSTS0_IFAIF0_1_Pos (7) /*!< PWM_T::INTSTS0: IFAIF0_1 Position */
+#define PWM_INTSTS0_IFAIF0_1_Msk (0x1ul << PWM_INTSTS0_IFAIF0_1_Pos) /*!< PWM_T::INTSTS0: IFAIF0_1 Mask */
+
+#define PWM_INTSTS0_PIFn_Pos (8) /*!< PWM_T::INTSTS0: PIFn Position */
+#define PWM_INTSTS0_PIFn_Msk (0x3ful << PWM_INTSTS0_PIFn_Pos) /*!< PWM_T::INTSTS0: PIFn Mask */
+
+#define PWM_INTSTS0_PIF0_Pos (8) /*!< PWM_T::INTSTS0: PIF0 Position */
+#define PWM_INTSTS0_PIF0_Msk (0x1ul << PWM_INTSTS0_PIF0_Pos) /*!< PWM_T::INTSTS0: PIF0 Mask */
+
+#define PWM_INTSTS0_PIF1_Pos (9) /*!< PWM_T::INTSTS0: PIF1 Position */
+#define PWM_INTSTS0_PIF1_Msk (0x1ul << PWM_INTSTS0_PIF1_Pos) /*!< PWM_T::INTSTS0: PIF1 Mask */
+
+#define PWM_INTSTS0_PIF2_Pos (10) /*!< PWM_T::INTSTS0: PIF2 Position */
+#define PWM_INTSTS0_PIF2_Msk (0x1ul << PWM_INTSTS0_PIF2_Pos) /*!< PWM_T::INTSTS0: PIF2 Mask */
+
+#define PWM_INTSTS0_PIF3_Pos (11) /*!< PWM_T::INTSTS0: PIF3 Position */
+#define PWM_INTSTS0_PIF3_Msk (0x1ul << PWM_INTSTS0_PIF3_Pos) /*!< PWM_T::INTSTS0: PIF3 Mask */
+
+#define PWM_INTSTS0_PIF4_Pos (12) /*!< PWM_T::INTSTS0: PIF4 Position */
+#define PWM_INTSTS0_PIF4_Msk (0x1ul << PWM_INTSTS0_PIF4_Pos) /*!< PWM_T::INTSTS0: PIF4 Mask */
+
+#define PWM_INTSTS0_PIF5_Pos (13) /*!< PWM_T::INTSTS0: PIF5 Position */
+#define PWM_INTSTS0_PIF5_Msk (0x1ul << PWM_INTSTS0_PIF5_Pos) /*!< PWM_T::INTSTS0: PIF5 Mask */
+
+#define PWM_INTSTS0_IFAIF2_3_Pos (15) /*!< PWM_T::INTSTS0: IFAIF2_3 Position */
+#define PWM_INTSTS0_IFAIF2_3_Msk (0x1ul << PWM_INTSTS0_IFAIF2_3_Pos) /*!< PWM_T::INTSTS0: IFAIF2_3 Mask */
+
+#define PWM_INTSTS0_CMPUIFn_Pos (16) /*!< PWM_T::INTSTS0: CMPUIFn Position */
+#define PWM_INTSTS0_CMPUIFn_Msk (0x3ful << PWM_INTSTS0_CMPUIFn_Pos) /*!< PWM_T::INTSTS0: CMPUIFn Mask */
+
+#define PWM_INTSTS0_CMPUIF0_Pos (16) /*!< PWM_T::INTSTS0: CMPUIF0 Position */
+#define PWM_INTSTS0_CMPUIF0_Msk (0x1ul << PWM_INTSTS0_CMPUIF0_Pos) /*!< PWM_T::INTSTS0: CMPUIF0 Mask */
+
+#define PWM_INTSTS0_CMPUIF1_Pos (17) /*!< PWM_T::INTSTS0: CMPUIF1 Position */
+#define PWM_INTSTS0_CMPUIF1_Msk (0x1ul << PWM_INTSTS0_CMPUIF1_Pos) /*!< PWM_T::INTSTS0: CMPUIF1 Mask */
+
+#define PWM_INTSTS0_CMPUIF2_Pos (18) /*!< PWM_T::INTSTS0: CMPUIF2 Position */
+#define PWM_INTSTS0_CMPUIF2_Msk (0x1ul << PWM_INTSTS0_CMPUIF2_Pos) /*!< PWM_T::INTSTS0: CMPUIF2 Mask */
+
+#define PWM_INTSTS0_CMPUIF3_Pos (19) /*!< PWM_T::INTSTS0: CMPUIF3 Position */
+#define PWM_INTSTS0_CMPUIF3_Msk (0x1ul << PWM_INTSTS0_CMPUIF3_Pos) /*!< PWM_T::INTSTS0: CMPUIF3 Mask */
+
+#define PWM_INTSTS0_CMPUIF4_Pos (20) /*!< PWM_T::INTSTS0: CMPUIF4 Position */
+#define PWM_INTSTS0_CMPUIF4_Msk (0x1ul << PWM_INTSTS0_CMPUIF4_Pos) /*!< PWM_T::INTSTS0: CMPUIF4 Mask */
+
+#define PWM_INTSTS0_CMPUIF5_Pos (21) /*!< PWM_T::INTSTS0: CMPUIF5 Position */
+#define PWM_INTSTS0_CMPUIF5_Msk (0x1ul << PWM_INTSTS0_CMPUIF5_Pos) /*!< PWM_T::INTSTS0: CMPUIF5 Mask */
+
+#define PWM_INTSTS0_IFAIF4_5_Pos (23) /*!< PWM_T::INTSTS0: IFAIF4_5 Position */
+#define PWM_INTSTS0_IFAIF4_5_Msk (0x1ul << PWM_INTSTS0_IFAIF4_5_Pos) /*!< PWM_T::INTSTS0: IFAIF4_5 Mask */
+
+#define PWM_INTSTS0_CMPDIFn_Pos (24) /*!< PWM_T::INTSTS0: CMPDIFn Position */
+#define PWM_INTSTS0_CMPDIFn_Msk (0x3ful << PWM_INTSTS0_CMPDIFn_Pos) /*!< PWM_T::INTSTS0: CMPDIFn Mask */
+
+#define PWM_INTSTS0_CMPDIF0_Pos (24) /*!< PWM_T::INTSTS0: CMPDIF0 Position */
+#define PWM_INTSTS0_CMPDIF0_Msk (0x1ul << PWM_INTSTS0_CMPDIF0_Pos) /*!< PWM_T::INTSTS0: CMPDIF0 Mask */
+
+#define PWM_INTSTS0_CMPDIF1_Pos (25) /*!< PWM_T::INTSTS0: CMPDIF1 Position */
+#define PWM_INTSTS0_CMPDIF1_Msk (0x1ul << PWM_INTSTS0_CMPDIF1_Pos) /*!< PWM_T::INTSTS0: CMPDIF1 Mask */
+
+#define PWM_INTSTS0_CMPDIF2_Pos (26) /*!< PWM_T::INTSTS0: CMPDIF2 Position */
+#define PWM_INTSTS0_CMPDIF2_Msk (0x1ul << PWM_INTSTS0_CMPDIF2_Pos) /*!< PWM_T::INTSTS0: CMPDIF2 Mask */
+
+#define PWM_INTSTS0_CMPDIF3_Pos (27) /*!< PWM_T::INTSTS0: CMPDIF3 Position */
+#define PWM_INTSTS0_CMPDIF3_Msk (0x1ul << PWM_INTSTS0_CMPDIF3_Pos) /*!< PWM_T::INTSTS0: CMPDIF3 Mask */
+
+#define PWM_INTSTS0_CMPDIF4_Pos (28) /*!< PWM_T::INTSTS0: CMPDIF4 Position */
+#define PWM_INTSTS0_CMPDIF4_Msk (0x1ul << PWM_INTSTS0_CMPDIF4_Pos) /*!< PWM_T::INTSTS0: CMPDIF4 Mask */
+
+#define PWM_INTSTS0_CMPDIF5_Pos (29) /*!< PWM_T::INTSTS0: CMPDIF5 Position */
+#define PWM_INTSTS0_CMPDIF5_Msk (0x1ul << PWM_INTSTS0_CMPDIF5_Pos) /*!< PWM_T::INTSTS0: CMPDIF5 Mask */
+
+#define PWM_INTSTS1_BRKEIFn_Pos (0) /*!< PWM_T::INTSTS1: BRKEIFn Position */
+#define PWM_INTSTS1_BRKEIFn_Msk (0x3ful << PWM_INTSTS1_BRKEIFn_Pos) /*!< PWM_T::INTSTS1: BRKEIFn Mask */
+
+#define PWM_INTSTS1_BRKEIF0_Pos (0) /*!< PWM_T::INTSTS1: BRKEIF0 Position */
+#define PWM_INTSTS1_BRKEIF0_Msk (0x1ul << PWM_INTSTS1_BRKEIF0_Pos) /*!< PWM_T::INTSTS1: BRKEIF0 Mask */
+
+#define PWM_INTSTS1_BRKEIF1_Pos (1) /*!< PWM_T::INTSTS1: BRKEIF1 Position */
+#define PWM_INTSTS1_BRKEIF1_Msk (0x1ul << PWM_INTSTS1_BRKEIF1_Pos) /*!< PWM_T::INTSTS1: BRKEIF1 Mask */
+
+#define PWM_INTSTS1_BRKEIF2_Pos (2) /*!< PWM_T::INTSTS1: BRKEIF2 Position */
+#define PWM_INTSTS1_BRKEIF2_Msk (0x1ul << PWM_INTSTS1_BRKEIF2_Pos) /*!< PWM_T::INTSTS1: BRKEIF2 Mask */
+
+#define PWM_INTSTS1_BRKEIF3_Pos (3) /*!< PWM_T::INTSTS1: BRKEIF3 Position */
+#define PWM_INTSTS1_BRKEIF3_Msk (0x1ul << PWM_INTSTS1_BRKEIF3_Pos) /*!< PWM_T::INTSTS1: BRKEIF3 Mask */
+
+#define PWM_INTSTS1_BRKEIF4_Pos (4) /*!< PWM_T::INTSTS1: BRKEIF4 Position */
+#define PWM_INTSTS1_BRKEIF4_Msk (0x1ul << PWM_INTSTS1_BRKEIF4_Pos) /*!< PWM_T::INTSTS1: BRKEIF4 Mask */
+
+#define PWM_INTSTS1_BRKEIF5_Pos (5) /*!< PWM_T::INTSTS1: BRKEIF5 Position */
+#define PWM_INTSTS1_BRKEIF5_Msk (0x1ul << PWM_INTSTS1_BRKEIF5_Pos) /*!< PWM_T::INTSTS1: BRKEIF5 Mask */
+
+#define PWM_INTSTS1_BRKLIFn_Pos (8) /*!< PWM_T::INTSTS1: BRKLIFn Position */
+#define PWM_INTSTS1_BRKLIFn_Msk (0x3ful << PWM_INTSTS1_BRKLIFn_Pos) /*!< PWM_T::INTSTS1: BRKLIFn Mask */
+
+#define PWM_INTSTS1_BRKLIF0_Pos (8) /*!< PWM_T::INTSTS1: BRKLIF0 Position */
+#define PWM_INTSTS1_BRKLIF0_Msk (0x1ul << PWM_INTSTS1_BRKLIF0_Pos) /*!< PWM_T::INTSTS1: BRKLIF0 Mask */
+
+#define PWM_INTSTS1_BRKLIF1_Pos (9) /*!< PWM_T::INTSTS1: BRKLIF1 Position */
+#define PWM_INTSTS1_BRKLIF1_Msk (0x1ul << PWM_INTSTS1_BRKLIF1_Pos) /*!< PWM_T::INTSTS1: BRKLIF1 Mask */
+
+#define PWM_INTSTS1_BRKLIF2_Pos (10) /*!< PWM_T::INTSTS1: BRKLIF2 Position */
+#define PWM_INTSTS1_BRKLIF2_Msk (0x1ul << PWM_INTSTS1_BRKLIF2_Pos) /*!< PWM_T::INTSTS1: BRKLIF2 Mask */
+
+#define PWM_INTSTS1_BRKLIF3_Pos (11) /*!< PWM_T::INTSTS1: BRKLIF3 Position */
+#define PWM_INTSTS1_BRKLIF3_Msk (0x1ul << PWM_INTSTS1_BRKLIF3_Pos) /*!< PWM_T::INTSTS1: BRKLIF3 Mask */
+
+#define PWM_INTSTS1_BRKLIF4_Pos (12) /*!< PWM_T::INTSTS1: BRKLIF4 Position */
+#define PWM_INTSTS1_BRKLIF4_Msk (0x1ul << PWM_INTSTS1_BRKLIF4_Pos) /*!< PWM_T::INTSTS1: BRKLIF4 Mask */
+
+#define PWM_INTSTS1_BRKLIF5_Pos (13) /*!< PWM_T::INTSTS1: BRKLIF5 Position */
+#define PWM_INTSTS1_BRKLIF5_Msk (0x1ul << PWM_INTSTS1_BRKLIF5_Pos) /*!< PWM_T::INTSTS1: BRKLIF5 Mask */
+
+#define PWM_INTSTS1_BRKESTS0_Pos (16) /*!< PWM_T::INTSTS1: BRKESTS0 Position */
+#define PWM_INTSTS1_BRKESTS0_Msk (0x1ul << PWM_INTSTS1_BRKESTS0_Pos) /*!< PWM_T::INTSTS1: BRKESTS0 Mask */
+
+#define PWM_INTSTS1_BRKESTS1_Pos (17) /*!< PWM_T::INTSTS1: BRKESTS1 Position */
+#define PWM_INTSTS1_BRKESTS1_Msk (0x1ul << PWM_INTSTS1_BRKESTS1_Pos) /*!< PWM_T::INTSTS1: BRKESTS1 Mask */
+
+#define PWM_INTSTS1_BRKESTS2_Pos (18) /*!< PWM_T::INTSTS1: BRKESTS2 Position */
+#define PWM_INTSTS1_BRKESTS2_Msk (0x1ul << PWM_INTSTS1_BRKESTS2_Pos) /*!< PWM_T::INTSTS1: BRKESTS2 Mask */
+
+#define PWM_INTSTS1_BRKESTS3_Pos (19) /*!< PWM_T::INTSTS1: BRKESTS3 Position */
+#define PWM_INTSTS1_BRKESTS3_Msk (0x1ul << PWM_INTSTS1_BRKESTS3_Pos) /*!< PWM_T::INTSTS1: BRKESTS3 Mask */
+
+#define PWM_INTSTS1_BRKESTS4_Pos (20) /*!< PWM_T::INTSTS1: BRKESTS4 Position */
+#define PWM_INTSTS1_BRKESTS4_Msk (0x1ul << PWM_INTSTS1_BRKESTS4_Pos) /*!< PWM_T::INTSTS1: BRKESTS4 Mask */
+
+#define PWM_INTSTS1_BRKESTS5_Pos (21) /*!< PWM_T::INTSTS1: BRKESTS5 Position */
+#define PWM_INTSTS1_BRKESTS5_Msk (0x1ul << PWM_INTSTS1_BRKESTS5_Pos) /*!< PWM_T::INTSTS1: BRKESTS5 Mask */
+
+#define PWM_INTSTS1_BRKLSTS0_Pos (24) /*!< PWM_T::INTSTS1: BRKLSTS0 Position */
+#define PWM_INTSTS1_BRKLSTS0_Msk (0x1ul << PWM_INTSTS1_BRKLSTS0_Pos) /*!< PWM_T::INTSTS1: BRKLSTS0 Mask */
+
+#define PWM_INTSTS1_BRKLSTS1_Pos (25) /*!< PWM_T::INTSTS1: BRKLSTS1 Position */
+#define PWM_INTSTS1_BRKLSTS1_Msk (0x1ul << PWM_INTSTS1_BRKLSTS1_Pos) /*!< PWM_T::INTSTS1: BRKLSTS1 Mask */
+
+#define PWM_INTSTS1_BRKLSTS2_Pos (26) /*!< PWM_T::INTSTS1: BRKLSTS2 Position */
+#define PWM_INTSTS1_BRKLSTS2_Msk (0x1ul << PWM_INTSTS1_BRKLSTS2_Pos) /*!< PWM_T::INTSTS1: BRKLSTS2 Mask */
+
+#define PWM_INTSTS1_BRKLSTS3_Pos (27) /*!< PWM_T::INTSTS1: BRKLSTS3 Position */
+#define PWM_INTSTS1_BRKLSTS3_Msk (0x1ul << PWM_INTSTS1_BRKLSTS3_Pos) /*!< PWM_T::INTSTS1: BRKLSTS3 Mask */
+
+#define PWM_INTSTS1_BRKLSTS4_Pos (28) /*!< PWM_T::INTSTS1: BRKLSTS4 Position */
+#define PWM_INTSTS1_BRKLSTS4_Msk (0x1ul << PWM_INTSTS1_BRKLSTS4_Pos) /*!< PWM_T::INTSTS1: BRKLSTS4 Mask */
+
+#define PWM_INTSTS1_BRKLSTS5_Pos (29) /*!< PWM_T::INTSTS1: BRKLSTS5 Position */
+#define PWM_INTSTS1_BRKLSTS5_Msk (0x1ul << PWM_INTSTS1_BRKLSTS5_Pos) /*!< PWM_T::INTSTS1: BRKLSTS5 Mask */
+
+#define PWM_IFA_IFCNT0_1_Pos (0) /*!< PWM_T::IFA: IFCNT0_1 Position */
+#define PWM_IFA_IFCNT0_1_Msk (0xful << PWM_IFA_IFCNT0_1_Pos) /*!< PWM_T::IFA: IFCNT0_1 Mask */
+
+#define PWM_IFA_IFSEL0_1_Pos (4) /*!< PWM_T::IFA: IFSEL0_1 Position */
+#define PWM_IFA_IFSEL0_1_Msk (0x7ul << PWM_IFA_IFSEL0_1_Pos) /*!< PWM_T::IFA: IFSEL0_1 Mask */
+
+#define PWM_IFA_IFAEN0_1_Pos (7) /*!< PWM_T::IFA: IFAEN0_1 Position */
+#define PWM_IFA_IFAEN0_1_Msk (0x1ul << PWM_IFA_IFAEN0_1_Pos) /*!< PWM_T::IFA: IFAEN0_1 Mask */
+
+#define PWM_IFA_IFCNT2_3_Pos (8) /*!< PWM_T::IFA: IFCNT2_3 Position */
+#define PWM_IFA_IFCNT2_3_Msk (0xful << PWM_IFA_IFCNT2_3_Pos) /*!< PWM_T::IFA: IFCNT2_3 Mask */
+
+#define PWM_IFA_IFSEL2_3_Pos (12) /*!< PWM_T::IFA: IFSEL2_3 Position */
+#define PWM_IFA_IFSEL2_3_Msk (0x7ul << PWM_IFA_IFSEL2_3_Pos) /*!< PWM_T::IFA: IFSEL2_3 Mask */
+
+#define PWM_IFA_IFAEN2_3_Pos (15) /*!< PWM_T::IFA: IFAEN2_3 Position */
+#define PWM_IFA_IFAEN2_3_Msk (0x1ul << PWM_IFA_IFAEN2_3_Pos) /*!< PWM_T::IFA: IFAEN2_3 Mask */
+
+#define PWM_IFA_IFCNT4_5_Pos (16) /*!< PWM_T::IFA: IFCNT4_5 Position */
+#define PWM_IFA_IFCNT4_5_Msk (0xful << PWM_IFA_IFCNT4_5_Pos) /*!< PWM_T::IFA: IFCNT4_5 Mask */
+
+#define PWM_IFA_IFSEL4_5_Pos (20) /*!< PWM_T::IFA: IFSEL4_5 Position */
+#define PWM_IFA_IFSEL4_5_Msk (0x7ul << PWM_IFA_IFSEL4_5_Pos) /*!< PWM_T::IFA: IFSEL4_5 Mask */
+
+#define PWM_IFA_IFAEN4_5_Pos (23) /*!< PWM_T::IFA: IFAEN4_5 Position */
+#define PWM_IFA_IFAEN4_5_Msk (0x1ul << PWM_IFA_IFAEN4_5_Pos) /*!< PWM_T::IFA: IFAEN4_5 Mask */
+
+#define PWM_DACTRGEN_ZTEn_Pos (0) /*!< PWM_T::DACTRGEN: ZTEn Position */
+#define PWM_DACTRGEN_ZTEn_Msk (0x3ful << PWM_DACTRGEN_ZTEn_Pos) /*!< PWM_T::DACTRGEN: ZTEn Mask */
+
+#define PWM_DACTRGEN_ZTE0_Pos (0) /*!< PWM_T::DACTRGEN: ZTE0 Position */
+#define PWM_DACTRGEN_ZTE0_Msk (0x1ul << PWM_DACTRGEN_ZTE0_Pos) /*!< PWM_T::DACTRGEN: ZTE0 Mask */
+
+#define PWM_DACTRGEN_ZTE1_Pos (1) /*!< PWM_T::DACTRGEN: ZTE1 Position */
+#define PWM_DACTRGEN_ZTE1_Msk (0x1ul << PWM_DACTRGEN_ZTE1_Pos) /*!< PWM_T::DACTRGEN: ZTE1 Mask */
+
+#define PWM_DACTRGEN_ZTE2_Pos (2) /*!< PWM_T::DACTRGEN: ZTE2 Position */
+#define PWM_DACTRGEN_ZTE2_Msk (0x1ul << PWM_DACTRGEN_ZTE2_Pos) /*!< PWM_T::DACTRGEN: ZTE2 Mask */
+
+#define PWM_DACTRGEN_ZTE3_Pos (3) /*!< PWM_T::DACTRGEN: ZTE3 Position */
+#define PWM_DACTRGEN_ZTE3_Msk (0x1ul << PWM_DACTRGEN_ZTE3_Pos) /*!< PWM_T::DACTRGEN: ZTE3 Mask */
+
+#define PWM_DACTRGEN_ZTE4_Pos (4) /*!< PWM_T::DACTRGEN: ZTE4 Position */
+#define PWM_DACTRGEN_ZTE4_Msk (0x1ul << PWM_DACTRGEN_ZTE4_Pos) /*!< PWM_T::DACTRGEN: ZTE4 Mask */
+
+#define PWM_DACTRGEN_ZTE5_Pos (5) /*!< PWM_T::DACTRGEN: ZTE5 Position */
+#define PWM_DACTRGEN_ZTE5_Msk (0x1ul << PWM_DACTRGEN_ZTE5_Pos) /*!< PWM_T::DACTRGEN: ZTE5 Mask */
+
+#define PWM_DACTRGEN_PTEn_Pos (8) /*!< PWM_T::DACTRGEN: PTEn Position */
+#define PWM_DACTRGEN_PTEn_Msk (0x3ful << PWM_DACTRGEN_PTEn_Pos) /*!< PWM_T::DACTRGEN: PTEn Mask */
+
+#define PWM_DACTRGEN_PTE0_Pos (8) /*!< PWM_T::DACTRGEN: PTE0 Position */
+#define PWM_DACTRGEN_PTE0_Msk (0x1ul << PWM_DACTRGEN_PTE0_Pos) /*!< PWM_T::DACTRGEN: PTE0 Mask */
+
+#define PWM_DACTRGEN_PTE1_Pos (9) /*!< PWM_T::DACTRGEN: PTE1 Position */
+#define PWM_DACTRGEN_PTE1_Msk (0x1ul << PWM_DACTRGEN_PTE1_Pos) /*!< PWM_T::DACTRGEN: PTE1 Mask */
+
+#define PWM_DACTRGEN_PTE2_Pos (10) /*!< PWM_T::DACTRGEN: PTE2 Position */
+#define PWM_DACTRGEN_PTE2_Msk (0x1ul << PWM_DACTRGEN_PTE2_Pos) /*!< PWM_T::DACTRGEN: PTE2 Mask */
+
+#define PWM_DACTRGEN_PTE3_Pos (11) /*!< PWM_T::DACTRGEN: PTE3 Position */
+#define PWM_DACTRGEN_PTE3_Msk (0x1ul << PWM_DACTRGEN_PTE3_Pos) /*!< PWM_T::DACTRGEN: PTE3 Mask */
+
+#define PWM_DACTRGEN_PTE4_Pos (12) /*!< PWM_T::DACTRGEN: PTE4 Position */
+#define PWM_DACTRGEN_PTE4_Msk (0x1ul << PWM_DACTRGEN_PTE4_Pos) /*!< PWM_T::DACTRGEN: PTE4 Mask */
+
+#define PWM_DACTRGEN_PTE5_Pos (13) /*!< PWM_T::DACTRGEN: PTE5 Position */
+#define PWM_DACTRGEN_PTE5_Msk (0x1ul << PWM_DACTRGEN_PTE5_Pos) /*!< PWM_T::DACTRGEN: PTE5 Mask */
+
+#define PWM_DACTRGEN_CUTRGEn_Pos (16) /*!< PWM_T::DACTRGEN: CUTRGEn Position */
+#define PWM_DACTRGEN_CUTRGEn_Msk (0x3ful << PWM_DACTRGEN_CUTRGEn_Pos) /*!< PWM_T::DACTRGEN: CUTRGEn Mask */
+
+#define PWM_DACTRGEN_CUTRGE0_Pos (16) /*!< PWM_T::DACTRGEN: CUTRGE0 Position */
+#define PWM_DACTRGEN_CUTRGE0_Msk (0x1ul << PWM_DACTRGEN_CUTRGE0_Pos) /*!< PWM_T::DACTRGEN: CUTRGE0 Mask */
+
+#define PWM_DACTRGEN_CUTRGE1_Pos (17) /*!< PWM_T::DACTRGEN: CUTRGE1 Position */
+#define PWM_DACTRGEN_CUTRGE1_Msk (0x1ul << PWM_DACTRGEN_CUTRGE1_Pos) /*!< PWM_T::DACTRGEN: CUTRGE1 Mask */
+
+#define PWM_DACTRGEN_CUTRGE2_Pos (18) /*!< PWM_T::DACTRGEN: CUTRGE2 Position */
+#define PWM_DACTRGEN_CUTRGE2_Msk (0x1ul << PWM_DACTRGEN_CUTRGE2_Pos) /*!< PWM_T::DACTRGEN: CUTRGE2 Mask */
+
+#define PWM_DACTRGEN_CUTRGE3_Pos (19) /*!< PWM_T::DACTRGEN: CUTRGE3 Position */
+#define PWM_DACTRGEN_CUTRGE3_Msk (0x1ul << PWM_DACTRGEN_CUTRGE3_Pos) /*!< PWM_T::DACTRGEN: CUTRGE3 Mask */
+
+#define PWM_DACTRGEN_CUTRGE4_Pos (20) /*!< PWM_T::DACTRGEN: CUTRGE4 Position */
+#define PWM_DACTRGEN_CUTRGE4_Msk (0x1ul << PWM_DACTRGEN_CUTRGE4_Pos) /*!< PWM_T::DACTRGEN: CUTRGE4 Mask */
+
+#define PWM_DACTRGEN_CUTRGE5_Pos (21) /*!< PWM_T::DACTRGEN: CUTRGE5 Position */
+#define PWM_DACTRGEN_CUTRGE5_Msk (0x1ul << PWM_DACTRGEN_CUTRGE5_Pos) /*!< PWM_T::DACTRGEN: CUTRGE5 Mask */
+
+#define PWM_DACTRGEN_CDTRGEn_Pos (24) /*!< PWM_T::DACTRGEN: CDTRGEn Position */
+#define PWM_DACTRGEN_CDTRGEn_Msk (0x3ful << PWM_DACTRGEN_CDTRGEn_Pos) /*!< PWM_T::DACTRGEN: CDTRGEn Mask */
+
+#define PWM_DACTRGEN_CDTRGE0_Pos (24) /*!< PWM_T::DACTRGEN: CDTRGE0 Position */
+#define PWM_DACTRGEN_CDTRGE0_Msk (0x1ul << PWM_DACTRGEN_CDTRGE0_Pos) /*!< PWM_T::DACTRGEN: CDTRGE0 Mask */
+
+#define PWM_DACTRGEN_CDTRGE1_Pos (25) /*!< PWM_T::DACTRGEN: CDTRGE1 Position */
+#define PWM_DACTRGEN_CDTRGE1_Msk (0x1ul << PWM_DACTRGEN_CDTRGE1_Pos) /*!< PWM_T::DACTRGEN: CDTRGE1 Mask */
+
+#define PWM_DACTRGEN_CDTRGE2_Pos (26) /*!< PWM_T::DACTRGEN: CDTRGE2 Position */
+#define PWM_DACTRGEN_CDTRGE2_Msk (0x1ul << PWM_DACTRGEN_CDTRGE2_Pos) /*!< PWM_T::DACTRGEN: CDTRGE2 Mask */
+
+#define PWM_DACTRGEN_CDTRGE3_Pos (27) /*!< PWM_T::DACTRGEN: CDTRGE3 Position */
+#define PWM_DACTRGEN_CDTRGE3_Msk (0x1ul << PWM_DACTRGEN_CDTRGE3_Pos) /*!< PWM_T::DACTRGEN: CDTRGE3 Mask */
+
+#define PWM_DACTRGEN_CDTRGE4_Pos (28) /*!< PWM_T::DACTRGEN: CDTRGE4 Position */
+#define PWM_DACTRGEN_CDTRGE4_Msk (0x1ul << PWM_DACTRGEN_CDTRGE4_Pos) /*!< PWM_T::DACTRGEN: CDTRGE4 Mask */
+
+#define PWM_DACTRGEN_CDTRGE5_Pos (29) /*!< PWM_T::DACTRGEN: CDTRGE5 Position */
+#define PWM_DACTRGEN_CDTRGE5_Msk (0x1ul << PWM_DACTRGEN_CDTRGE5_Pos) /*!< PWM_T::DACTRGEN: CDTRGE5 Mask */
+
+#define PWM_EADCTS0_TRGSEL0_Pos (0) /*!< PWM_T::EADCTS0: TRGSEL0 Position */
+#define PWM_EADCTS0_TRGSEL0_Msk (0xful << PWM_EADCTS0_TRGSEL0_Pos) /*!< PWM_T::EADCTS0: TRGSEL0 Mask */
+
+#define PWM_EADCTS0_TRGEN0_Pos (7) /*!< PWM_T::EADCTS0: TRGEN0 Position */
+#define PWM_EADCTS0_TRGEN0_Msk (0x1ul << PWM_EADCTS0_TRGEN0_Pos) /*!< PWM_T::EADCTS0: TRGEN0 Mask */
+
+#define PWM_EADCTS0_TRGSEL1_Pos (8) /*!< PWM_T::EADCTS0: TRGSEL1 Position */
+#define PWM_EADCTS0_TRGSEL1_Msk (0xful << PWM_EADCTS0_TRGSEL1_Pos) /*!< PWM_T::EADCTS0: TRGSEL1 Mask */
+
+#define PWM_EADCTS0_TRGEN1_Pos (15) /*!< PWM_T::EADCTS0: TRGEN1 Position */
+#define PWM_EADCTS0_TRGEN1_Msk (0x1ul << PWM_EADCTS0_TRGEN1_Pos) /*!< PWM_T::EADCTS0: TRGEN1 Mask */
+
+#define PWM_EADCTS0_TRGSEL2_Pos (16) /*!< PWM_T::EADCTS0: TRGSEL2 Position */
+#define PWM_EADCTS0_TRGSEL2_Msk (0xful << PWM_EADCTS0_TRGSEL2_Pos) /*!< PWM_T::EADCTS0: TRGSEL2 Mask */
+
+#define PWM_EADCTS0_TRGEN2_Pos (23) /*!< PWM_T::EADCTS0: TRGEN2 Position */
+#define PWM_EADCTS0_TRGEN2_Msk (0x1ul << PWM_EADCTS0_TRGEN2_Pos) /*!< PWM_T::EADCTS0: TRGEN2 Mask */
+
+#define PWM_EADCTS0_TRGSEL3_Pos (24) /*!< PWM_T::EADCTS0: TRGSEL3 Position */
+#define PWM_EADCTS0_TRGSEL3_Msk (0xful << PWM_EADCTS0_TRGSEL3_Pos) /*!< PWM_T::EADCTS0: TRGSEL3 Mask */
+
+#define PWM_EADCTS0_TRGEN3_Pos (31) /*!< PWM_T::EADCTS0: TRGEN3 Position */
+#define PWM_EADCTS0_TRGEN3_Msk (0x1ul << PWM_EADCTS0_TRGEN3_Pos) /*!< PWM_T::EADCTS0: TRGEN3 Mask */
+
+#define PWM_EADCTS1_TRGSEL4_Pos (0) /*!< PWM_T::EADCTS1: TRGSEL4 Position */
+#define PWM_EADCTS1_TRGSEL4_Msk (0xful << PWM_EADCTS1_TRGSEL4_Pos) /*!< PWM_T::EADCTS1: TRGSEL4 Mask */
+
+#define PWM_EADCTS1_TRGEN4_Pos (7) /*!< PWM_T::EADCTS1: TRGEN4 Position */
+#define PWM_EADCTS1_TRGEN4_Msk (0x1ul << PWM_EADCTS1_TRGEN4_Pos) /*!< PWM_T::EADCTS1: TRGEN4 Mask */
+
+#define PWM_EADCTS1_TRGSEL5_Pos (8) /*!< PWM_T::EADCTS1: TRGSEL5 Position */
+#define PWM_EADCTS1_TRGSEL5_Msk (0xful << PWM_EADCTS1_TRGSEL5_Pos) /*!< PWM_T::EADCTS1: TRGSEL5 Mask */
+
+#define PWM_EADCTS1_TRGEN5_Pos (15) /*!< PWM_T::EADCTS1: TRGEN5 Position */
+#define PWM_EADCTS1_TRGEN5_Msk (0x1ul << PWM_EADCTS1_TRGEN5_Pos) /*!< PWM_T::EADCTS1: TRGEN5 Mask */
+
+#define PWM_FTCMPDAT0_1_FTCMP_Pos (0) /*!< PWM_T::FTCMPDAT0_1: FTCMP Position */
+#define PWM_FTCMPDAT0_1_FTCMP_Msk (0xfffful << PWM_FTCMPDAT0_1_FTCMP_Pos) /*!< PWM_T::FTCMPDAT0_1: FTCMP Mask */
+
+#define PWM_FTCMPDAT2_3_FTCMP_Pos (0) /*!< PWM_T::FTCMPDAT2_3: FTCMP Position */
+#define PWM_FTCMPDAT2_3_FTCMP_Msk (0xfffful << PWM_FTCMPDAT2_3_FTCMP_Pos) /*!< PWM_T::FTCMPDAT2_3: FTCMP Mask */
+
+#define PWM_FTCMPDAT4_5_FTCMP_Pos (0) /*!< PWM_T::FTCMPDAT4_5: FTCMP Position */
+#define PWM_FTCMPDAT4_5_FTCMP_Msk (0xfffful << PWM_FTCMPDAT4_5_FTCMP_Pos) /*!< PWM_T::FTCMPDAT4_5: FTCMP Mask */
+
+#define PWM_SSCTL_SSENn_Pos (0) /*!< PWM_T::SSCTL: SSENn Position */
+#define PWM_SSCTL_SSENn_Msk (0x3ful << PWM_SSCTL_SSENn_Pos) /*!< PWM_T::SSCTL: SSENn Mask */
+
+#define PWM_SSCTL_SSEN0_Pos (0) /*!< PWM_T::SSCTL: SSEN0 Position */
+#define PWM_SSCTL_SSEN0_Msk (0x1ul << PWM_SSCTL_SSEN0_Pos) /*!< PWM_T::SSCTL: SSEN0 Mask */
+
+#define PWM_SSCTL_SSEN1_Pos (1) /*!< PWM_T::SSCTL: SSEN1 Position */
+#define PWM_SSCTL_SSEN1_Msk (0x1ul << PWM_SSCTL_SSEN1_Pos) /*!< PWM_T::SSCTL: SSEN1 Mask */
+
+#define PWM_SSCTL_SSEN2_Pos (2) /*!< PWM_T::SSCTL: SSEN2 Position */
+#define PWM_SSCTL_SSEN2_Msk (0x1ul << PWM_SSCTL_SSEN2_Pos) /*!< PWM_T::SSCTL: SSEN2 Mask */
+
+#define PWM_SSCTL_SSEN3_Pos (3) /*!< PWM_T::SSCTL: SSEN3 Position */
+#define PWM_SSCTL_SSEN3_Msk (0x1ul << PWM_SSCTL_SSEN3_Pos) /*!< PWM_T::SSCTL: SSEN3 Mask */
+
+#define PWM_SSCTL_SSEN4_Pos (4) /*!< PWM_T::SSCTL: SSEN4 Position */
+#define PWM_SSCTL_SSEN4_Msk (0x1ul << PWM_SSCTL_SSEN4_Pos) /*!< PWM_T::SSCTL: SSEN4 Mask */
+
+#define PWM_SSCTL_SSEN5_Pos (5) /*!< PWM_T::SSCTL: SSEN5 Position */
+#define PWM_SSCTL_SSEN5_Msk (0x1ul << PWM_SSCTL_SSEN5_Pos) /*!< PWM_T::SSCTL: SSEN5 Mask */
+
+#define PWM_SSTRG_CNTSEN_Pos (0) /*!< PWM_T::SSTRG: CNTSEN Position */
+#define PWM_SSTRG_CNTSEN_Msk (0x1ul << PWM_SSTRG_CNTSEN_Pos) /*!< PWM_T::SSTRG: CNTSEN Mask */
+
+#define PWM_STATUS_CNTMAXFn_Pos (0) /*!< PWM_T::STATUS: CNTMAXFn Position */
+#define PWM_STATUS_CNTMAXFn_Msk (0x3ful << PWM_STATUS_CNTMAXFn_Pos) /*!< PWM_T::STATUS: CNTMAXFn Mask */
+
+#define PWM_STATUS_CNTMAXF0_Pos (0) /*!< PWM_T::STATUS: CNTMAXF0 Position */
+#define PWM_STATUS_CNTMAXF0_Msk (0x1ul << PWM_STATUS_CNTMAXF0_Pos) /*!< PWM_T::STATUS: CNTMAXF0 Mask */
+
+#define PWM_STATUS_CNTMAXF1_Pos (1) /*!< PWM_T::STATUS: CNTMAXF1 Position */
+#define PWM_STATUS_CNTMAXF1_Msk (0x1ul << PWM_STATUS_CNTMAXF1_Pos) /*!< PWM_T::STATUS: CNTMAXF1 Mask */
+
+#define PWM_STATUS_CNTMAXF2_Pos (2) /*!< PWM_T::STATUS: CNTMAXF2 Position */
+#define PWM_STATUS_CNTMAXF2_Msk (0x1ul << PWM_STATUS_CNTMAXF2_Pos) /*!< PWM_T::STATUS: CNTMAXF2 Mask */
+
+#define PWM_STATUS_CNTMAXF3_Pos (3) /*!< PWM_T::STATUS: CNTMAXF3 Position */
+#define PWM_STATUS_CNTMAXF3_Msk (0x1ul << PWM_STATUS_CNTMAXF3_Pos) /*!< PWM_T::STATUS: CNTMAXF3 Mask */
+
+#define PWM_STATUS_CNTMAXF4_Pos (4) /*!< PWM_T::STATUS: CNTMAXF4 Position */
+#define PWM_STATUS_CNTMAXF4_Msk (0x1ul << PWM_STATUS_CNTMAXF4_Pos) /*!< PWM_T::STATUS: CNTMAXF4 Mask */
+
+#define PWM_STATUS_CNTMAXF5_Pos (5) /*!< PWM_T::STATUS: CNTMAXF5 Position */
+#define PWM_STATUS_CNTMAXF5_Msk (0x1ul << PWM_STATUS_CNTMAXF5_Pos) /*!< PWM_T::STATUS: CNTMAXF5 Mask */
+
+#define PWM_STATUS_SYNCINFn_Pos (8) /*!< PWM_T::STATUS: SYNCINFn Position */
+#define PWM_STATUS_SYNCINFn_Msk (0x7ul << PWM_STATUS_SYNCINFn_Pos) /*!< PWM_T::STATUS: SYNCINFn Mask */
+
+#define PWM_STATUS_SYNCINF0_Pos (8) /*!< PWM_T::STATUS: SYNCINF0 Position */
+#define PWM_STATUS_SYNCINF0_Msk (0x1ul << PWM_STATUS_SYNCINF0_Pos) /*!< PWM_T::STATUS: SYNCINF0 Mask */
+
+#define PWM_STATUS_SYNCINF2_Pos (9) /*!< PWM_T::STATUS: SYNCINF2 Position */
+#define PWM_STATUS_SYNCINF2_Msk (0x1ul << PWM_STATUS_SYNCINF2_Pos) /*!< PWM_T::STATUS: SYNCINF2 Mask */
+
+#define PWM_STATUS_SYNCINF4_Pos (10) /*!< PWM_T::STATUS: SYNCINF4 Position */
+#define PWM_STATUS_SYNCINF4_Msk (0x1ul << PWM_STATUS_SYNCINF4_Pos) /*!< PWM_T::STATUS: SYNCINF4 Mask */
+
+#define PWM_STATUS_ADCTRGFn_Pos (16) /*!< PWM_T::STATUS: ADCTRGFn Position */
+#define PWM_STATUS_ADCTRGFn_Msk (0x3ful << PWM_STATUS_ADCTRGFn_Pos) /*!< PWM_T::STATUS: ADCTRGFn Mask */
+
+#define PWM_STATUS_ADCTRGF0_Pos (16) /*!< PWM_T::STATUS: ADCTRGF0 Position */
+#define PWM_STATUS_ADCTRGF0_Msk (0x1ul << PWM_STATUS_ADCTRGF0_Pos) /*!< PWM_T::STATUS: ADCTRGF0 Mask */
+
+#define PWM_STATUS_ADCTRGF1_Pos (17) /*!< PWM_T::STATUS: ADCTRGF1 Position */
+#define PWM_STATUS_ADCTRGF1_Msk (0x1ul << PWM_STATUS_ADCTRGF1_Pos) /*!< PWM_T::STATUS: ADCTRGF1 Mask */
+
+#define PWM_STATUS_ADCTRGF2_Pos (18) /*!< PWM_T::STATUS: ADCTRGF2 Position */
+#define PWM_STATUS_ADCTRGF2_Msk (0x1ul << PWM_STATUS_ADCTRGF2_Pos) /*!< PWM_T::STATUS: ADCTRGF2 Mask */
+
+#define PWM_STATUS_ADCTRGF3_Pos (19) /*!< PWM_T::STATUS: ADCTRGF3 Position */
+#define PWM_STATUS_ADCTRGF3_Msk (0x1ul << PWM_STATUS_ADCTRGF3_Pos) /*!< PWM_T::STATUS: ADCTRGF3 Mask */
+
+#define PWM_STATUS_ADCTRGF4_Pos (20) /*!< PWM_T::STATUS: ADCTRGF4 Position */
+#define PWM_STATUS_ADCTRGF4_Msk (0x1ul << PWM_STATUS_ADCTRGF4_Pos) /*!< PWM_T::STATUS: ADCTRGF4 Mask */
+
+#define PWM_STATUS_ADCTRGF5_Pos (21) /*!< PWM_T::STATUS: ADCTRGF5 Position */
+#define PWM_STATUS_ADCTRGF5_Msk (0x1ul << PWM_STATUS_ADCTRGF5_Pos) /*!< PWM_T::STATUS: ADCTRGF5 Mask */
+
+#define PWM_STATUS_DACTRGF_Pos (24) /*!< PWM_T::STATUS: DACTRGF Position */
+#define PWM_STATUS_DACTRGF_Msk (0x1ul << PWM_STATUS_DACTRGF_Pos) /*!< PWM_T::STATUS: DACTRGF Mask */
+
+#define PWM_CAPINEN_CAPINENn_Pos (0) /*!< PWM_T::CAPINEN: CAPINENn Position */
+#define PWM_CAPINEN_CAPINENn_Msk (0x3ful << PWM_CAPINEN_CAPINENn_Pos) /*!< PWM_T::CAPINEN: CAPINENn Mask */
+
+#define PWM_CAPINEN_CAPINEN0_Pos (0) /*!< PWM_T::CAPINEN: CAPINEN0 Position */
+#define PWM_CAPINEN_CAPINEN0_Msk (0x1ul << PWM_CAPINEN_CAPINEN0_Pos) /*!< PWM_T::CAPINEN: CAPINEN0 Mask */
+
+#define PWM_CAPINEN_CAPINEN1_Pos (1) /*!< PWM_T::CAPINEN: CAPINEN1 Position */
+#define PWM_CAPINEN_CAPINEN1_Msk (0x1ul << PWM_CAPINEN_CAPINEN1_Pos) /*!< PWM_T::CAPINEN: CAPINEN1 Mask */
+
+#define PWM_CAPINEN_CAPINEN2_Pos (2) /*!< PWM_T::CAPINEN: CAPINEN2 Position */
+#define PWM_CAPINEN_CAPINEN2_Msk (0x1ul << PWM_CAPINEN_CAPINEN2_Pos) /*!< PWM_T::CAPINEN: CAPINEN2 Mask */
+
+#define PWM_CAPINEN_CAPINEN3_Pos (3) /*!< PWM_T::CAPINEN: CAPINEN3 Position */
+#define PWM_CAPINEN_CAPINEN3_Msk (0x1ul << PWM_CAPINEN_CAPINEN3_Pos) /*!< PWM_T::CAPINEN: CAPINEN3 Mask */
+
+#define PWM_CAPINEN_CAPINEN4_Pos (4) /*!< PWM_T::CAPINEN: CAPINEN4 Position */
+#define PWM_CAPINEN_CAPINEN4_Msk (0x1ul << PWM_CAPINEN_CAPINEN4_Pos) /*!< PWM_T::CAPINEN: CAPINEN4 Mask */
+
+#define PWM_CAPINEN_CAPINEN5_Pos (5) /*!< PWM_T::CAPINEN: CAPINEN5 Position */
+#define PWM_CAPINEN_CAPINEN5_Msk (0x1ul << PWM_CAPINEN_CAPINEN5_Pos) /*!< PWM_T::CAPINEN: CAPINEN5 Mask */
+
+#define PWM_CAPCTL_CAPENn_Pos (0) /*!< PWM_T::CAPCTL: CAPENn Position */
+#define PWM_CAPCTL_CAPENn_Msk (0x3ful << PWM_CAPCTL_CAPENn_Pos) /*!< PWM_T::CAPCTL: CAPENn Mask */
+
+#define PWM_CAPCTL_CAPEN0_Pos (0) /*!< PWM_T::CAPCTL: CAPEN0 Position */
+#define PWM_CAPCTL_CAPEN0_Msk (0x1ul << PWM_CAPCTL_CAPEN0_Pos) /*!< PWM_T::CAPCTL: CAPEN0 Mask */
+
+#define PWM_CAPCTL_CAPEN1_Pos (1) /*!< PWM_T::CAPCTL: CAPEN1 Position */
+#define PWM_CAPCTL_CAPEN1_Msk (0x1ul << PWM_CAPCTL_CAPEN1_Pos) /*!< PWM_T::CAPCTL: CAPEN1 Mask */
+
+#define PWM_CAPCTL_CAPEN2_Pos (2) /*!< PWM_T::CAPCTL: CAPEN2 Position */
+#define PWM_CAPCTL_CAPEN2_Msk (0x1ul << PWM_CAPCTL_CAPEN2_Pos) /*!< PWM_T::CAPCTL: CAPEN2 Mask */
+
+#define PWM_CAPCTL_CAPEN3_Pos (3) /*!< PWM_T::CAPCTL: CAPEN3 Position */
+#define PWM_CAPCTL_CAPEN3_Msk (0x1ul << PWM_CAPCTL_CAPEN3_Pos) /*!< PWM_T::CAPCTL: CAPEN3 Mask */
+
+#define PWM_CAPCTL_CAPEN4_Pos (4) /*!< PWM_T::CAPCTL: CAPEN4 Position */
+#define PWM_CAPCTL_CAPEN4_Msk (0x1ul << PWM_CAPCTL_CAPEN4_Pos) /*!< PWM_T::CAPCTL: CAPEN4 Mask */
+
+#define PWM_CAPCTL_CAPEN5_Pos (5) /*!< PWM_T::CAPCTL: CAPEN5 Position */
+#define PWM_CAPCTL_CAPEN5_Msk (0x1ul << PWM_CAPCTL_CAPEN5_Pos) /*!< PWM_T::CAPCTL: CAPEN5 Mask */
+
+#define PWM_CAPCTL_CAPINVn_Pos (8) /*!< PWM_T::CAPCTL: CAPINVn Position */
+#define PWM_CAPCTL_CAPINVn_Msk (0x3ful << PWM_CAPCTL_CAPINVn_Pos) /*!< PWM_T::CAPCTL: CAPINVn Mask */
+
+#define PWM_CAPCTL_CAPINV0_Pos (8) /*!< PWM_T::CAPCTL: CAPINV0 Position */
+#define PWM_CAPCTL_CAPINV0_Msk (0x1ul << PWM_CAPCTL_CAPINV0_Pos) /*!< PWM_T::CAPCTL: CAPINV0 Mask */
+
+#define PWM_CAPCTL_CAPINV1_Pos (9) /*!< PWM_T::CAPCTL: CAPINV1 Position */
+#define PWM_CAPCTL_CAPINV1_Msk (0x1ul << PWM_CAPCTL_CAPINV1_Pos) /*!< PWM_T::CAPCTL: CAPINV1 Mask */
+
+#define PWM_CAPCTL_CAPINV2_Pos (10) /*!< PWM_T::CAPCTL: CAPINV2 Position */
+#define PWM_CAPCTL_CAPINV2_Msk (0x1ul << PWM_CAPCTL_CAPINV2_Pos) /*!< PWM_T::CAPCTL: CAPINV2 Mask */
+
+#define PWM_CAPCTL_CAPINV3_Pos (11) /*!< PWM_T::CAPCTL: CAPINV3 Position */
+#define PWM_CAPCTL_CAPINV3_Msk (0x1ul << PWM_CAPCTL_CAPINV3_Pos) /*!< PWM_T::CAPCTL: CAPINV3 Mask */
+
+#define PWM_CAPCTL_CAPINV4_Pos (12) /*!< PWM_T::CAPCTL: CAPINV4 Position */
+#define PWM_CAPCTL_CAPINV4_Msk (0x1ul << PWM_CAPCTL_CAPINV4_Pos) /*!< PWM_T::CAPCTL: CAPINV4 Mask */
+
+#define PWM_CAPCTL_CAPINV5_Pos (13) /*!< PWM_T::CAPCTL: CAPINV5 Position */
+#define PWM_CAPCTL_CAPINV5_Msk (0x1ul << PWM_CAPCTL_CAPINV5_Pos) /*!< PWM_T::CAPCTL: CAPINV5 Mask */
+
+#define PWM_CAPCTL_RCRLDENn_Pos (16) /*!< PWM_T::CAPCTL: RCRLDENn Position */
+#define PWM_CAPCTL_RCRLDENn_Msk (0x3ful << PWM_CAPCTL_RCRLDENn_Pos) /*!< PWM_T::CAPCTL: RCRLDENn Mask */
+
+#define PWM_CAPCTL_RCRLDEN0_Pos (16) /*!< PWM_T::CAPCTL: RCRLDEN0 Position */
+#define PWM_CAPCTL_RCRLDEN0_Msk (0x1ul << PWM_CAPCTL_RCRLDEN0_Pos) /*!< PWM_T::CAPCTL: RCRLDEN0 Mask */
+
+#define PWM_CAPCTL_RCRLDEN1_Pos (17) /*!< PWM_T::CAPCTL: RCRLDEN1 Position */
+#define PWM_CAPCTL_RCRLDEN1_Msk (0x1ul << PWM_CAPCTL_RCRLDEN1_Pos) /*!< PWM_T::CAPCTL: RCRLDEN1 Mask */
+
+#define PWM_CAPCTL_RCRLDEN2_Pos (18) /*!< PWM_T::CAPCTL: RCRLDEN2 Position */
+#define PWM_CAPCTL_RCRLDEN2_Msk (0x1ul << PWM_CAPCTL_RCRLDEN2_Pos) /*!< PWM_T::CAPCTL: RCRLDEN2 Mask */
+
+#define PWM_CAPCTL_RCRLDEN3_Pos (19) /*!< PWM_T::CAPCTL: RCRLDEN3 Position */
+#define PWM_CAPCTL_RCRLDEN3_Msk (0x1ul << PWM_CAPCTL_RCRLDEN3_Pos) /*!< PWM_T::CAPCTL: RCRLDEN3 Mask */
+
+#define PWM_CAPCTL_RCRLDEN4_Pos (20) /*!< PWM_T::CAPCTL: RCRLDEN4 Position */
+#define PWM_CAPCTL_RCRLDEN4_Msk (0x1ul << PWM_CAPCTL_RCRLDEN4_Pos) /*!< PWM_T::CAPCTL: RCRLDEN4 Mask */
+
+#define PWM_CAPCTL_RCRLDEN5_Pos (21) /*!< PWM_T::CAPCTL: RCRLDEN5 Position */
+#define PWM_CAPCTL_RCRLDEN5_Msk (0x1ul << PWM_CAPCTL_RCRLDEN5_Pos) /*!< PWM_T::CAPCTL: RCRLDEN5 Mask */
+
+#define PWM_CAPCTL_FCRLDENn_Pos (24) /*!< PWM_T::CAPCTL: FCRLDENn Position */
+#define PWM_CAPCTL_FCRLDENn_Msk (0x3ful << PWM_CAPCTL_FCRLDENn_Pos) /*!< PWM_T::CAPCTL: FCRLDENn Mask */
+
+#define PWM_CAPCTL_FCRLDEN0_Pos (24) /*!< PWM_T::CAPCTL: FCRLDEN0 Position */
+#define PWM_CAPCTL_FCRLDEN0_Msk (0x1ul << PWM_CAPCTL_FCRLDEN0_Pos) /*!< PWM_T::CAPCTL: FCRLDEN0 Mask */
+
+#define PWM_CAPCTL_FCRLDEN1_Pos (25) /*!< PWM_T::CAPCTL: FCRLDEN1 Position */
+#define PWM_CAPCTL_FCRLDEN1_Msk (0x1ul << PWM_CAPCTL_FCRLDEN1_Pos) /*!< PWM_T::CAPCTL: FCRLDEN1 Mask */
+
+#define PWM_CAPCTL_FCRLDEN2_Pos (26) /*!< PWM_T::CAPCTL: FCRLDEN2 Position */
+#define PWM_CAPCTL_FCRLDEN2_Msk (0x1ul << PWM_CAPCTL_FCRLDEN2_Pos) /*!< PWM_T::CAPCTL: FCRLDEN2 Mask */
+
+#define PWM_CAPCTL_FCRLDEN3_Pos (27) /*!< PWM_T::CAPCTL: FCRLDEN3 Position */
+#define PWM_CAPCTL_FCRLDEN3_Msk (0x1ul << PWM_CAPCTL_FCRLDEN3_Pos) /*!< PWM_T::CAPCTL: FCRLDEN3 Mask */
+
+#define PWM_CAPCTL_FCRLDEN4_Pos (28) /*!< PWM_T::CAPCTL: FCRLDEN4 Position */
+#define PWM_CAPCTL_FCRLDEN4_Msk (0x1ul << PWM_CAPCTL_FCRLDEN4_Pos) /*!< PWM_T::CAPCTL: FCRLDEN4 Mask */
+
+#define PWM_CAPCTL_FCRLDEN5_Pos (29) /*!< PWM_T::CAPCTL: FCRLDEN5 Position */
+#define PWM_CAPCTL_FCRLDEN5_Msk (0x1ul << PWM_CAPCTL_FCRLDEN5_Pos) /*!< PWM_T::CAPCTL: FCRLDEN5 Mask */
+
+#define PWM_CAPSTS_CRLIFOVn_Pos (0) /*!< PWM_T::CAPSTS: CRLIFOVn Position */
+#define PWM_CAPSTS_CRLIFOVn_Msk (0x3ful << PWM_CAPSTS_CRLIFOVn_Pos) /*!< PWM_T::CAPSTS: CRLIFOVn Mask */
+
+#define PWM_CAPSTS_CRLIFOV0_Pos (0) /*!< PWM_T::CAPSTS: CRLIFOV0 Position */
+#define PWM_CAPSTS_CRLIFOV0_Msk (0x1ul << PWM_CAPSTS_CRLIFOV0_Pos) /*!< PWM_T::CAPSTS: CRLIFOV0 Mask */
+
+#define PWM_CAPSTS_CRLIFOV1_Pos (1) /*!< PWM_T::CAPSTS: CRLIFOV1 Position */
+#define PWM_CAPSTS_CRLIFOV1_Msk (0x1ul << PWM_CAPSTS_CRLIFOV1_Pos) /*!< PWM_T::CAPSTS: CRLIFOV1 Mask */
+
+#define PWM_CAPSTS_CRLIFOV2_Pos (2) /*!< PWM_T::CAPSTS: CRLIFOV2 Position */
+#define PWM_CAPSTS_CRLIFOV2_Msk (0x1ul << PWM_CAPSTS_CRLIFOV2_Pos) /*!< PWM_T::CAPSTS: CRLIFOV2 Mask */
+
+#define PWM_CAPSTS_CRLIFOV3_Pos (3) /*!< PWM_T::CAPSTS: CRLIFOV3 Position */
+#define PWM_CAPSTS_CRLIFOV3_Msk (0x1ul << PWM_CAPSTS_CRLIFOV3_Pos) /*!< PWM_T::CAPSTS: CRLIFOV3 Mask */
+
+#define PWM_CAPSTS_CRLIFOV4_Pos (4) /*!< PWM_T::CAPSTS: CRLIFOV4 Position */
+#define PWM_CAPSTS_CRLIFOV4_Msk (0x1ul << PWM_CAPSTS_CRLIFOV4_Pos) /*!< PWM_T::CAPSTS: CRLIFOV4 Mask */
+
+#define PWM_CAPSTS_CRLIFOV5_Pos (5) /*!< PWM_T::CAPSTS: CRLIFOV5 Position */
+#define PWM_CAPSTS_CRLIFOV5_Msk (0x1ul << PWM_CAPSTS_CRLIFOV5_Pos) /*!< PWM_T::CAPSTS: CRLIFOV5 Mask */
+
+#define PWM_CAPSTS_CFLIFOVn_Pos (8) /*!< PWM_T::CAPSTS: CFLIFOVn Position */
+#define PWM_CAPSTS_CFLIFOVn_Msk (0x3ful << PWM_CAPSTS_CFLIFOVn_Pos) /*!< PWM_T::CAPSTS: CFLIFOVn Mask */
+
+#define PWM_CAPSTS_CFLIFOV0_Pos (8) /*!< PWM_T::CAPSTS: CFLIFOV0 Position */
+#define PWM_CAPSTS_CFLIFOV0_Msk (0x1ul << PWM_CAPSTS_CFLIFOV0_Pos) /*!< PWM_T::CAPSTS: CFLIFOV0 Mask */
+
+#define PWM_CAPSTS_CFLIFOV1_Pos (9) /*!< PWM_T::CAPSTS: CFLIFOV1 Position */
+#define PWM_CAPSTS_CFLIFOV1_Msk (0x1ul << PWM_CAPSTS_CFLIFOV1_Pos) /*!< PWM_T::CAPSTS: CFLIFOV1 Mask */
+
+#define PWM_CAPSTS_CFLIFOV2_Pos (10) /*!< PWM_T::CAPSTS: CFLIFOV2 Position */
+#define PWM_CAPSTS_CFLIFOV2_Msk (0x1ul << PWM_CAPSTS_CFLIFOV2_Pos) /*!< PWM_T::CAPSTS: CFLIFOV2 Mask */
+
+#define PWM_CAPSTS_CFLIFOV3_Pos (11) /*!< PWM_T::CAPSTS: CFLIFOV3 Position */
+#define PWM_CAPSTS_CFLIFOV3_Msk (0x1ul << PWM_CAPSTS_CFLIFOV3_Pos) /*!< PWM_T::CAPSTS: CFLIFOV3 Mask */
+
+#define PWM_CAPSTS_CFLIFOV4_Pos (12) /*!< PWM_T::CAPSTS: CFLIFOV4 Position */
+#define PWM_CAPSTS_CFLIFOV4_Msk (0x1ul << PWM_CAPSTS_CFLIFOV4_Pos) /*!< PWM_T::CAPSTS: CFLIFOV4 Mask */
+
+#define PWM_CAPSTS_CFLIFOV5_Pos (13) /*!< PWM_T::CAPSTS: CFLIFOV5 Position */
+#define PWM_CAPSTS_CFLIFOV5_Msk (0x1ul << PWM_CAPSTS_CFLIFOV5_Pos) /*!< PWM_T::CAPSTS: CFLIFOV5 Mask */
+
+#define PWM_RCAPDAT0_RCAPDAT_Pos (0) /*!< PWM_T::RCAPDAT0: RCAPDAT Position */
+#define PWM_RCAPDAT0_RCAPDAT_Msk (0xfffful << PWM_RCAPDAT0_RCAPDAT_Pos) /*!< PWM_T::RCAPDAT0: RCAPDAT Mask */
+
+#define PWM_FCAPDAT0_FCAPDAT_Pos (0) /*!< PWM_T::FCAPDAT0: FCAPDAT Position */
+#define PWM_FCAPDAT0_FCAPDAT_Msk (0xfffful << PWM_FCAPDAT0_FCAPDAT_Pos) /*!< PWM_T::FCAPDAT0: FCAPDAT Mask */
+
+#define PWM_RCAPDAT1_RCAPDAT_Pos (0) /*!< PWM_T::RCAPDAT1: RCAPDAT Position */
+#define PWM_RCAPDAT1_RCAPDAT_Msk (0xfffful << PWM_RCAPDAT1_RCAPDAT_Pos) /*!< PWM_T::RCAPDAT1: RCAPDAT Mask */
+
+#define PWM_FCAPDAT1_FCAPDAT_Pos (0) /*!< PWM_T::FCAPDAT1: FCAPDAT Position */
+#define PWM_FCAPDAT1_FCAPDAT_Msk (0xfffful << PWM_FCAPDAT1_FCAPDAT_Pos) /*!< PWM_T::FCAPDAT1: FCAPDAT Mask */
+
+#define PWM_RCAPDAT2_RCAPDAT_Pos (0) /*!< PWM_T::RCAPDAT2: RCAPDAT Position */
+#define PWM_RCAPDAT2_RCAPDAT_Msk (0xfffful << PWM_RCAPDAT2_RCAPDAT_Pos) /*!< PWM_T::RCAPDAT2: RCAPDAT Mask */
+
+#define PWM_FCAPDAT2_FCAPDAT_Pos (0) /*!< PWM_T::FCAPDAT2: FCAPDAT Position */
+#define PWM_FCAPDAT2_FCAPDAT_Msk (0xfffful << PWM_FCAPDAT2_FCAPDAT_Pos) /*!< PWM_T::FCAPDAT2: FCAPDAT Mask */
+
+#define PWM_RCAPDAT3_RCAPDAT_Pos (0) /*!< PWM_T::RCAPDAT3: RCAPDAT Position */
+#define PWM_RCAPDAT3_RCAPDAT_Msk (0xfffful << PWM_RCAPDAT3_RCAPDAT_Pos) /*!< PWM_T::RCAPDAT3: RCAPDAT Mask */
+
+#define PWM_FCAPDAT3_FCAPDAT_Pos (0) /*!< PWM_T::FCAPDAT3: FCAPDAT Position */
+#define PWM_FCAPDAT3_FCAPDAT_Msk (0xfffful << PWM_FCAPDAT3_FCAPDAT_Pos) /*!< PWM_T::FCAPDAT3: FCAPDAT Mask */
+
+#define PWM_RCAPDAT4_RCAPDAT_Pos (0) /*!< PWM_T::RCAPDAT4: RCAPDAT Position */
+#define PWM_RCAPDAT4_RCAPDAT_Msk (0xfffful << PWM_RCAPDAT4_RCAPDAT_Pos) /*!< PWM_T::RCAPDAT4: RCAPDAT Mask */
+
+#define PWM_FCAPDAT4_FCAPDAT_Pos (0) /*!< PWM_T::FCAPDAT4: FCAPDAT Position */
+#define PWM_FCAPDAT4_FCAPDAT_Msk (0xfffful << PWM_FCAPDAT4_FCAPDAT_Pos) /*!< PWM_T::FCAPDAT4: FCAPDAT Mask */
+
+#define PWM_RCAPDAT5_RCAPDAT_Pos (0) /*!< PWM_T::RCAPDAT5: RCAPDAT Position */
+#define PWM_RCAPDAT5_RCAPDAT_Msk (0xfffful << PWM_RCAPDAT5_RCAPDAT_Pos) /*!< PWM_T::RCAPDAT5: RCAPDAT Mask */
+
+#define PWM_FCAPDAT5_FCAPDAT_Pos (0) /*!< PWM_T::FCAPDAT5: FCAPDAT Position */
+#define PWM_FCAPDAT5_FCAPDAT_Msk (0xfffful << PWM_FCAPDAT5_FCAPDAT_Pos) /*!< PWM_T::FCAPDAT5: FCAPDAT Mask */
+
+#define PWM_PDMACTL_CHEN0_1_Pos (0) /*!< PWM_T::PDMACTL: CHEN0_1 Position */
+#define PWM_PDMACTL_CHEN0_1_Msk (0x1ul << PWM_PDMACTL_CHEN0_1_Pos) /*!< PWM_T::PDMACTL: CHEN0_1 Mask */
+
+#define PWM_PDMACTL_CAPMOD0_1_Pos (1) /*!< PWM_T::PDMACTL: CAPMOD0_1 Position */
+#define PWM_PDMACTL_CAPMOD0_1_Msk (0x3ul << PWM_PDMACTL_CAPMOD0_1_Pos) /*!< PWM_T::PDMACTL: CAPMOD0_1 Mask */
+
+#define PWM_PDMACTL_CAPORD0_1_Pos (3) /*!< PWM_T::PDMACTL: CAPORD0_1 Position */
+#define PWM_PDMACTL_CAPORD0_1_Msk (0x1ul << PWM_PDMACTL_CAPORD0_1_Pos) /*!< PWM_T::PDMACTL: CAPORD0_1 Mask */
+
+#define PWM_PDMACTL_CHSEL0_1_Pos (4) /*!< PWM_T::PDMACTL: CHSEL0_1 Position */
+#define PWM_PDMACTL_CHSEL0_1_Msk (0x1ul << PWM_PDMACTL_CHSEL0_1_Pos) /*!< PWM_T::PDMACTL: CHSEL0_1 Mask */
+
+#define PWM_PDMACTL_CHEN2_3_Pos (8) /*!< PWM_T::PDMACTL: CHEN2_3 Position */
+#define PWM_PDMACTL_CHEN2_3_Msk (0x1ul << PWM_PDMACTL_CHEN2_3_Pos) /*!< PWM_T::PDMACTL: CHEN2_3 Mask */
+
+#define PWM_PDMACTL_CAPMOD2_3_Pos (9) /*!< PWM_T::PDMACTL: CAPMOD2_3 Position */
+#define PWM_PDMACTL_CAPMOD2_3_Msk (0x3ul << PWM_PDMACTL_CAPMOD2_3_Pos) /*!< PWM_T::PDMACTL: CAPMOD2_3 Mask */
+
+#define PWM_PDMACTL_CAPORD2_3_Pos (11) /*!< PWM_T::PDMACTL: CAPORD2_3 Position */
+#define PWM_PDMACTL_CAPORD2_3_Msk (0x1ul << PWM_PDMACTL_CAPORD2_3_Pos) /*!< PWM_T::PDMACTL: CAPORD2_3 Mask */
+
+#define PWM_PDMACTL_CHSEL2_3_Pos (12) /*!< PWM_T::PDMACTL: CHSEL2_3 Position */
+#define PWM_PDMACTL_CHSEL2_3_Msk (0x1ul << PWM_PDMACTL_CHSEL2_3_Pos) /*!< PWM_T::PDMACTL: CHSEL2_3 Mask */
+
+#define PWM_PDMACTL_CHEN4_5_Pos (16) /*!< PWM_T::PDMACTL: CHEN4_5 Position */
+#define PWM_PDMACTL_CHEN4_5_Msk (0x1ul << PWM_PDMACTL_CHEN4_5_Pos) /*!< PWM_T::PDMACTL: CHEN4_5 Mask */
+
+#define PWM_PDMACTL_CAPMOD4_5_Pos (17) /*!< PWM_T::PDMACTL: CAPMOD4_5 Position */
+#define PWM_PDMACTL_CAPMOD4_5_Msk (0x3ul << PWM_PDMACTL_CAPMOD4_5_Pos) /*!< PWM_T::PDMACTL: CAPMOD4_5 Mask */
+
+#define PWM_PDMACTL_CAPORD4_5_Pos (19) /*!< PWM_T::PDMACTL: CAPORD4_5 Position */
+#define PWM_PDMACTL_CAPORD4_5_Msk (0x1ul << PWM_PDMACTL_CAPORD4_5_Pos) /*!< PWM_T::PDMACTL: CAPORD4_5 Mask */
+
+#define PWM_PDMACTL_CHSEL4_5_Pos (20) /*!< PWM_T::PDMACTL: CHSEL4_5 Position */
+#define PWM_PDMACTL_CHSEL4_5_Msk (0x1ul << PWM_PDMACTL_CHSEL4_5_Pos) /*!< PWM_T::PDMACTL: CHSEL4_5 Mask */
+
+#define PWM_PDMACAP0_1_CAPBUF_Pos (0) /*!< PWM_T::PDMACAP0_1: CAPBUF Position */
+#define PWM_PDMACAP0_1_CAPBUF_Msk (0xfffful << PWM_PDMACAP0_1_CAPBUF_Pos) /*!< PWM_T::PDMACAP0_1: CAPBUF Mask */
+
+#define PWM_PDMACAP2_3_CAPBUF_Pos (0) /*!< PWM_T::PDMACAP2_3: CAPBUF Position */
+#define PWM_PDMACAP2_3_CAPBUF_Msk (0xfffful << PWM_PDMACAP2_3_CAPBUF_Pos) /*!< PWM_T::PDMACAP2_3: CAPBUF Mask */
+
+#define PWM_PDMACAP4_5_CAPBUF_Pos (0) /*!< PWM_T::PDMACAP4_5: CAPBUF Position */
+#define PWM_PDMACAP4_5_CAPBUF_Msk (0xfffful << PWM_PDMACAP4_5_CAPBUF_Pos) /*!< PWM_T::PDMACAP4_5: CAPBUF Mask */
+
+#define PWM_CAPIEN_CAPRIENn_Pos (0) /*!< PWM_T::CAPIEN: CAPRIENn Position */
+#define PWM_CAPIEN_CAPRIENn_Msk (0x3ful << PWM_CAPIEN_CAPRIENn_Pos) /*!< PWM_T::CAPIEN: CAPRIENn Mask */
+
+#define PWM_CAPIEN_CAPRIEN0_Pos (0) /*!< PWM_T::CAPIEN: CAPRIEN0 Position */
+#define PWM_CAPIEN_CAPRIEN0_Msk (0x1ul << PWM_CAPIEN_CAPRIEN0_Pos) /*!< PWM_T::CAPIEN: CAPRIEN0 Mask */
+
+#define PWM_CAPIEN_CAPRIEN1_Pos (1) /*!< PWM_T::CAPIEN: CAPRIEN1 Position */
+#define PWM_CAPIEN_CAPRIEN1_Msk (0x1ul << PWM_CAPIEN_CAPRIEN1_Pos) /*!< PWM_T::CAPIEN: CAPRIEN1 Mask */
+
+#define PWM_CAPIEN_CAPRIEN2_Pos (2) /*!< PWM_T::CAPIEN: CAPRIEN2 Position */
+#define PWM_CAPIEN_CAPRIEN2_Msk (0x1ul << PWM_CAPIEN_CAPRIEN2_Pos) /*!< PWM_T::CAPIEN: CAPRIEN2 Mask */
+
+#define PWM_CAPIEN_CAPRIEN3_Pos (3) /*!< PWM_T::CAPIEN: CAPRIEN3 Position */
+#define PWM_CAPIEN_CAPRIEN3_Msk (0x1ul << PWM_CAPIEN_CAPRIEN3_Pos) /*!< PWM_T::CAPIEN: CAPRIEN3 Mask */
+
+#define PWM_CAPIEN_CAPRIEN4_Pos (4) /*!< PWM_T::CAPIEN: CAPRIEN4 Position */
+#define PWM_CAPIEN_CAPRIEN4_Msk (0x1ul << PWM_CAPIEN_CAPRIEN4_Pos) /*!< PWM_T::CAPIEN: CAPRIEN4 Mask */
+
+#define PWM_CAPIEN_CAPRIEN5_Pos (5) /*!< PWM_T::CAPIEN: CAPRIEN5 Position */
+#define PWM_CAPIEN_CAPRIEN5_Msk (0x1ul << PWM_CAPIEN_CAPRIEN5_Pos) /*!< PWM_T::CAPIEN: CAPRIEN5 Mask */
+
+#define PWM_CAPIEN_CAPFIENn_Pos (8) /*!< PWM_T::CAPIEN: CAPFIENn Position */
+#define PWM_CAPIEN_CAPFIENn_Msk (0x3ful << PWM_CAPIEN_CAPFIENn_Pos) /*!< PWM_T::CAPIEN: CAPFIENn Mask */
+
+#define PWM_CAPIEN_CAPFIEN0_Pos (8) /*!< PWM_T::CAPIEN: CAPFIEN0 Position */
+#define PWM_CAPIEN_CAPFIEN0_Msk (0x1ul << PWM_CAPIEN_CAPFIEN0_Pos) /*!< PWM_T::CAPIEN: CAPFIEN0 Mask */
+
+#define PWM_CAPIEN_CAPFIEN1_Pos (9) /*!< PWM_T::CAPIEN: CAPFIEN1 Position */
+#define PWM_CAPIEN_CAPFIEN1_Msk (0x1ul << PWM_CAPIEN_CAPFIEN1_Pos) /*!< PWM_T::CAPIEN: CAPFIEN1 Mask */
+
+#define PWM_CAPIEN_CAPFIEN2_Pos (10) /*!< PWM_T::CAPIEN: CAPFIEN2 Position */
+#define PWM_CAPIEN_CAPFIEN2_Msk (0x1ul << PWM_CAPIEN_CAPFIEN2_Pos) /*!< PWM_T::CAPIEN: CAPFIEN2 Mask */
+
+#define PWM_CAPIEN_CAPFIEN3_Pos (11) /*!< PWM_T::CAPIEN: CAPFIEN3 Position */
+#define PWM_CAPIEN_CAPFIEN3_Msk (0x1ul << PWM_CAPIEN_CAPFIEN3_Pos) /*!< PWM_T::CAPIEN: CAPFIEN3 Mask */
+
+#define PWM_CAPIEN_CAPFIEN4_Pos (12) /*!< PWM_T::CAPIEN: CAPFIEN4 Position */
+#define PWM_CAPIEN_CAPFIEN4_Msk (0x1ul << PWM_CAPIEN_CAPFIEN4_Pos) /*!< PWM_T::CAPIEN: CAPFIEN4 Mask */
+
+#define PWM_CAPIEN_CAPFIEN5_Pos (13) /*!< PWM_T::CAPIEN: CAPFIEN5 Position */
+#define PWM_CAPIEN_CAPFIEN5_Msk (0x1ul << PWM_CAPIEN_CAPFIEN5_Pos) /*!< PWM_T::CAPIEN: CAPFIEN5 Mask */
+
+#define PWM_CAPIF_CRLIFn_Pos (0) /*!< PWM_T::CAPIF: CRLIFn Position */
+#define PWM_CAPIF_CRLIFn_Msk (0x3ful << PWM_CAPIF_CRLIFn_Pos) /*!< PWM_T::CAPIF: CRLIFn Mask */
+
+#define PWM_CAPIF_CRLIF0_Pos (0) /*!< PWM_T::CAPIF: CRLIF0 Position */
+#define PWM_CAPIF_CRLIF0_Msk (0x1ul << PWM_CAPIF_CRLIF0_Pos) /*!< PWM_T::CAPIF: CRLIF0 Mask */
+
+#define PWM_CAPIF_CRLIF1_Pos (1) /*!< PWM_T::CAPIF: CRLIF1 Position */
+#define PWM_CAPIF_CRLIF1_Msk (0x1ul << PWM_CAPIF_CRLIF1_Pos) /*!< PWM_T::CAPIF: CRLIF1 Mask */
+
+#define PWM_CAPIF_CRLIF2_Pos (2) /*!< PWM_T::CAPIF: CRLIF2 Position */
+#define PWM_CAPIF_CRLIF2_Msk (0x1ul << PWM_CAPIF_CRLIF2_Pos) /*!< PWM_T::CAPIF: CRLIF2 Mask */
+
+#define PWM_CAPIF_CRLIF3_Pos (3) /*!< PWM_T::CAPIF: CRLIF3 Position */
+#define PWM_CAPIF_CRLIF3_Msk (0x1ul << PWM_CAPIF_CRLIF3_Pos) /*!< PWM_T::CAPIF: CRLIF3 Mask */
+
+#define PWM_CAPIF_CRLIF4_Pos (4) /*!< PWM_T::CAPIF: CRLIF4 Position */
+#define PWM_CAPIF_CRLIF4_Msk (0x1ul << PWM_CAPIF_CRLIF4_Pos) /*!< PWM_T::CAPIF: CRLIF4 Mask */
+
+#define PWM_CAPIF_CRLIF5_Pos (5) /*!< PWM_T::CAPIF: CRLIF5 Position */
+#define PWM_CAPIF_CRLIF5_Msk (0x1ul << PWM_CAPIF_CRLIF5_Pos) /*!< PWM_T::CAPIF: CRLIF5 Mask */
+
+#define PWM_CAPIF_CFLIFn_Pos (8) /*!< PWM_T::CAPIF: CFLIFn Position */
+#define PWM_CAPIF_CFLIFn_Msk (0x3ful << PWM_CAPIF_CFLIFn_Pos) /*!< PWM_T::CAPIF: CFLIFn Mask */
+
+#define PWM_CAPIF_CFLIF0_Pos (8) /*!< PWM_T::CAPIF: CFLIF0 Position */
+#define PWM_CAPIF_CFLIF0_Msk (0x1ul << PWM_CAPIF_CFLIF0_Pos) /*!< PWM_T::CAPIF: CFLIF0 Mask */
+
+#define PWM_CAPIF_CFLIF1_Pos (9) /*!< PWM_T::CAPIF: CFLIF1 Position */
+#define PWM_CAPIF_CFLIF1_Msk (0x1ul << PWM_CAPIF_CFLIF1_Pos) /*!< PWM_T::CAPIF: CFLIF1 Mask */
+
+#define PWM_CAPIF_CFLIF2_Pos (10) /*!< PWM_T::CAPIF: CFLIF2 Position */
+#define PWM_CAPIF_CFLIF2_Msk (0x1ul << PWM_CAPIF_CFLIF2_Pos) /*!< PWM_T::CAPIF: CFLIF2 Mask */
+
+#define PWM_CAPIF_CFLIF3_Pos (11) /*!< PWM_T::CAPIF: CFLIF3 Position */
+#define PWM_CAPIF_CFLIF3_Msk (0x1ul << PWM_CAPIF_CFLIF3_Pos) /*!< PWM_T::CAPIF: CFLIF3 Mask */
+
+#define PWM_CAPIF_CFLIF4_Pos (12) /*!< PWM_T::CAPIF: CFLIF4 Position */
+#define PWM_CAPIF_CFLIF4_Msk (0x1ul << PWM_CAPIF_CFLIF4_Pos) /*!< PWM_T::CAPIF: CFLIF4 Mask */
+
+#define PWM_CAPIF_CFLIF5_Pos (13) /*!< PWM_T::CAPIF: CFLIF5 Position */
+#define PWM_CAPIF_CFLIF5_Msk (0x1ul << PWM_CAPIF_CFLIF5_Pos) /*!< PWM_T::CAPIF: CFLIF5 Mask */
+
+#define PWM_PBUF_PBUF_Pos (0) /*!< PWM_T::PBUF: PBUF Position */
+#define PWM_PBUF_PBUF_Msk (0xfffful << PWM_PBUF_PBUF_Pos) /*!< PWM_T::PBUF: PBUF Mask */
+
+#define PWM_CMPBUF_CMPBUF_Pos (0) /*!< PWM_T::CMPBUF: CMPBUF Position */
+#define PWM_CMPBUF_CMPBUF_Msk (0xfffful << PWM_CMPBUF_CMPBUF_Pos) /*!< PWM_T::CMPBUF: CMPBUF Mask */
+
+#define PWM_FTCBUF0_1_FTCMPBUF_Pos (0) /*!< PWM_T::FTCBUF0_1: FTCMPBUF Position */
+#define PWM_FTCBUF0_1_FTCMPBUF_Msk (0xfffful << PWM_FTCBUF0_1_FTCMPBUF_Pos) /*!< PWM_T::FTCBUF0_1: FTCMPBUF Mask */
+
+#define PWM_FTCBUF2_3_FTCMPBUF_Pos (0) /*!< PWM_T::FTCBUF2_3: FTCMPBUF Position */
+#define PWM_FTCBUF2_3_FTCMPBUF_Msk (0xfffful << PWM_FTCBUF2_3_FTCMPBUF_Pos) /*!< PWM_T::FTCBUF2_3: FTCMPBUF Mask */
+
+#define PWM_FTCBUF4_5_FTCMPBUF_Pos (0) /*!< PWM_T::FTCBUF4_5: FTCMPBUF Position */
+#define PWM_FTCBUF4_5_FTCMPBUF_Msk (0xfffful << PWM_FTCBUF4_5_FTCMPBUF_Pos) /*!< PWM_T::FTCBUF4_5: FTCMPBUF Mask */
+
+#define PWM_FTCI_FTCMUn_Pos (0) /*!< PWM_T::FTCI: FTCMUn Position */
+#define PWM_FTCI_FTCMUn_Msk (0x7ul << PWM_FTCI_FTCMUn_Pos) /*!< PWM_T::FTCI: FTCMUn Mask */
+
+#define PWM_FTCI_FTCMU0_Pos (0) /*!< PWM_T::FTCI: FTCMU0 Position */
+#define PWM_FTCI_FTCMU0_Msk (0x1ul << PWM_FTCI_FTCMU0_Pos) /*!< PWM_T::FTCI: FTCMU0 Mask */
+
+#define PWM_FTCI_FTCMU2_Pos (1) /*!< PWM_T::FTCI: FTCMU2 Position */
+#define PWM_FTCI_FTCMU2_Msk (0x1ul << PWM_FTCI_FTCMU2_Pos) /*!< PWM_T::FTCI: FTCMU2 Mask */
+
+#define PWM_FTCI_FTCMU4_Pos (2) /*!< PWM_T::FTCI: FTCMU4 Position */
+#define PWM_FTCI_FTCMU4_Msk (0x1ul << PWM_FTCI_FTCMU4_Pos) /*!< PWM_T::FTCI: FTCMU4 Mask */
+
+#define PWM_FTCI_FTCMDn_Pos (8) /*!< PWM_T::FTCI: FTCMDn Position */
+#define PWM_FTCI_FTCMDn_Msk (0x7ul << PWM_FTCI_FTCMDn_Pos) /*!< PWM_T::FTCI: FTCMDn Mask */
+
+#define PWM_FTCI_FTCMD0_Pos (8) /*!< PWM_T::FTCI: FTCMD0 Position */
+#define PWM_FTCI_FTCMD0_Msk (0x1ul << PWM_FTCI_FTCMD0_Pos) /*!< PWM_T::FTCI: FTCMD0 Mask */
+
+#define PWM_FTCI_FTCMD2_Pos (9) /*!< PWM_T::FTCI: FTCMD2 Position */
+#define PWM_FTCI_FTCMD2_Msk (0x1ul << PWM_FTCI_FTCMD2_Pos) /*!< PWM_T::FTCI: FTCMD2 Mask */
+
+#define PWM_FTCI_FTCMD4_Pos (10) /*!< PWM_T::FTCI: FTCMD4 Position */
+#define PWM_FTCI_FTCMD4_Msk (0x1ul << PWM_FTCI_FTCMD4_Pos) /*!< PWM_T::FTCI: FTCMD4 Mask */
+
+/**@}*/ /* PWM_CONST */
+/**@}*/ /* end of PWM register group */
+
+
+/*---------------------- Real Time Clock Controller -------------------------*/
+/**
+ @addtogroup RTC Real Time Clock Controller(RTC)
+ Memory Mapped Structure for RTC Controller
+@{ */
+
+
+typedef struct
+{
+
+
+
+
+/**
+ * @var RTC_T::INIT
+ * Offset: 0x00 RTC Initiation Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |INIT[0]/ACTIVE|RTC Active Status (Read Only)
+ * | | |0 = RTC is at reset state.
+ * | | |1 = RTC is at normal active state.
+ * |[31:1] |INIT[31:1]|RTC Initiation
+ * | | |When RTC block is powered on, RTC is at reset state.
+ * | | |User has to write a number (0x a5eb1357) to INIT to make RTC leaving reset state.
+ * | | |Once the INIT is written as 0xa5eb1357, the RTC will be in un-reset state permanently.
+ * | | |The INIT is a write-only field and read value will be always 0.
+ * @var RTC_T::RWEN
+ * Offset: 0x04 RTC Access Enable Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |RWEN |RTC Register Access Enable Password (Write Only)
+ * | | |Writing 0xA965 to this register will enable RTC access and keep 1024 RTC clock.
+ * |[16] |RWENF |RTC Register Access Enable Flag (Read Only)
+ * | | |0 = RTC register read/write Disabled.
+ * | | |1 = RTC register read/write Enabled.
+ * | | |This bit will be set after RTC_RWEN[15:0] register is load a 0xA965, and be cleared automatically after 1024 RTC clock.
+ * @var RTC_T::FREQADJ
+ * Offset: 0x08 RTC Frequency Compensation Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[5:0] |FRACTION |Fraction Part
+ * | | |Formula = (fraction part of detected value) x 60.
+ * | | |Note: Digit in RTC_FREQADJ must be expressed as hexadecimal number.
+ * |[11:8] |INTEGER |Integer Part
+ * @var RTC_T::TIME
+ * Offset: 0x0C Time Loading Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[3:0] |SEC |1-Sec Time Digit (0~9)
+ * |[6:4] |TENSEC |10-Sec Time Digit (0~5)
+ * |[11:8] |MIN |1-Min Time Digit (0~9)
+ * |[14:12] |TENMIN |10-Min Time Digit (0~5)
+ * |[19:16] |HR |1-Hour Time Digit (0~9)
+ * |[21:20] |TENHR |10-Hour Time Digit (0~2)
+ * @var RTC_T::CAL
+ * Offset: 0x10 RTC Calendar Loading Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[3:0] |DAY |1-Day Calendar Digit (0~9)
+ * |[5:4] |TENDAY |10-Day Calendar Digit (0~3)
+ * |[11:8] |MON |1-Month Calendar Digit (0~9)
+ * |[12] |TENMON |10-Month Calendar Digit (0~1)
+ * |[19:16] |YEAR |1-Year Calendar Digit (0~9)
+ * |[23:20] |TENYEAR |10-Year Calendar Digit (0~9)
+ * @var RTC_T::CLKFMT
+ * Offset: 0x14 Time Scale Selection Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |24HEN |24-Hour / 12-Hour Time Scale Selection
+ * | | |Indicates that RTC_TIME and RTC_TALM are in 24-hour time scale or 12-hour time scale
+ * | | |0 = 12-hour time scale with AM and PM indication selected.
+ * | | |1 = 24-hour time scale selected.
+ * @var RTC_T::WEEKDAY
+ * Offset: 0x18 Day of the Week Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[2:0] |WEEKDAY |Day Of The Week Register
+ * | | |000 = Sunday.
+ * | | |001 = Monday.
+ * | | |010 = Tuesday.
+ * | | |011 = Wednesday.
+ * | | |100 = Thursday.
+ * | | |101 = Friday.
+ * | | |110 = Saturday.
+ * | | |111 = Reserved.
+ * @var RTC_T::TALM
+ * Offset: 0x1C Time Alarm Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[3:0] |SEC |1-Sec Time Digit of Alarm Setting (0~9)
+ * |[6:4] |TENSEC |10-Sec Time Digit of Alarm Setting (0~5)
+ * |[11:8] |MIN |1-Min Time Digit of Alarm Setting (0~9)
+ * |[14:12] |TENMIN |10-Min Time Digit of Alarm Setting (0~5)
+ * |[19:16] |HR |1-Hour Time Digit of Alarm Setting (0~9)
+ * |[21:20] |TENHR |10-Hour Time Digit of Alarm Setting (0~2)
+ * @var RTC_T::CALM
+ * Offset: 0x20 Calendar Alarm Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[3:0] |DAY |1-Day Calendar Digit of Alarm Setting (0~9)
+ * |[5:4] |TENDAY |10-Day Calendar Digit of Alarm Setting (0~3)
+ * |[11:8] |MON |1-Month Calendar Digit of Alarm Setting (0~9)
+ * |[12] |TENMON |10-Month Calendar Digit of Alarm Setting (0~1)
+ * |[19:16] |YEAR |1-Year Calendar Digit of Alarm Setting (0~9)
+ * |[23:20] |TENYEAR |10-Year Calendar Digit of Alarm Setting (0~9)
+ * @var RTC_T::LEAPYEAR
+ * Offset: 0x24 RTC Leap Year Indicator Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |LEAPYEAR |Leap Year Indication Register (Read Only)
+ * | | |0 = This year is not a leap year.
+ * | | |1 = This year is leap year.
+ * @var RTC_T::INTEN
+ * Offset: 0x28 RTC Interrupt Enable Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |ALMIEN |Alarm Interrupt Enable Bit
+ * | | |0 = RTC Alarm interrupt Disabled.
+ * | | |1 = RTC Alarm interrupt Enabled.
+ * |[1] |TICKIEN |Time Tick Interrupt Enable Bit
+ * | | |0 = RTC Time Tick interrupt Disabled.
+ * | | |1 = RTC Time Tick interrupt Enabled.
+ * |[2] |SNPDIEN |Snoop Detection Interrupt Enable Bit
+ * | | |0 = Snoop detected interrupt Disabled.
+ * | | |1 = Snoop detected interrupt Enabled.
+ * @var RTC_T::INTSTS
+ * Offset: 0x2C RTC Interrupt Indicator Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |ALMIF |RTC Alarm Interrupt Flag
+ * | | |When RTC time counters RTC_TIME and RTC_CAL match the alarm setting time registers RTC_TALM and RTC_CALM, this bit will be set to 1 and an interrupt will be generated if RTC Alarm Interrupt enabled ALMIEN (RTC_INTEN[0]) is set to 1.
+ * | | |Chip will be waken up if RTC Alarm Interrupt is enabled when chip is at Power-down mode.
+ * | | |0 = Alarm condition is not matched.
+ * | | |1 = Alarm condition is matched.
+ * | | |Note: Write 1 to clear this bit.
+ * |[1] |TICKIF |RTC Time Tick Interrupt Flag
+ * | | |When RTC time tick happened, this bit will be set to 1 and an interrupt will be generated if RTC Tick Interrupt enabled TICKIEN (RTC_INTEN[1]) is set to 1.
+ * | | |Chip will also be waken up if RTC Tick Interrupt is enabled and this bit is set to 1 when chip is running at Power-down mode.
+ * | | |0 = Tick condition does not occur.
+ * | | |1 = Tick condition occur.
+ * | | |Note: Write 1 to clear to clear this bit.
+ * |[2] |SNPDIF |Snoop Detect Interrupt Flag
+ * | | |When tamper pin transition event is detected, this bit is set to 1 and an interrupt is generated if Snoop Detection Interrupt enabled SNPDIEN (RTC_INTEN[2]) is set to1.
+ * | | |Chip will be waken up from Power-down mode if spare register snooper detect interrupt is enabled.
+ * | | |0 = No snoop event is detected.
+ * | | |1 = Snoop event is detected.
+ * | | |Note: Write 1 to clear this bit.
+ * @var RTC_T::TICK
+ * Offset: 0x30 RTC Time Tick Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[2:0] |TICK |Time Tick Register
+ * | | |These bits are used to select RTC time tick period for Periodic Time Tick Interrupt request.
+ * | | |000 = Time tick is 1 second.
+ * | | |001 = Time tick is 1/2 second.
+ * | | |010 = Time tick is 1/4 second.
+ * | | |011 = Time tick is 1/8 second.
+ * | | |100 = Time tick is 1/16 second.
+ * | | |101 = Time tick is 1/32 second.
+ * | | |110 = Time tick is 1/64 second.
+ * | | |111 = Time tick is 1/28 second.
+ * | | |Note: This register can be read back after the RTC register access enable bit RWENF (RTC_RWEN[16]) is active.
+ * @var RTC_T::TAMSK
+ * Offset: 0x34 Time Alarm Mask Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |MSEC |Mask 1-Sec Time Digit of Alarm Setting (0~9)
+ * |[1] |MTENSEC |Mask 10-Sec Time Digit of Alarm Setting (0~5)
+ * |[2] |MMIN |Mask 1-Min Time Digit of Alarm Setting (0~9)
+ * |[3] |MTENMIN |Mask 10-Min Time Digit of Alarm Setting (0~5)
+ * |[4] |MHR |Mask 1-Hour Time Digit of Alarm Setting (0~9)
+ * |[5] |MTENHR |Mask 10-Hour Time Digit of Alarm Setting (0~2)
+ * @var RTC_T::CAMSK
+ * Offset: 0x38 Calendar Alarm Mask Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |MDAY |Mask 1-Day Calendar Digit of Alarm Setting (0~9)
+ * |[1] |MTENDAY |Mask 10-Day Calendar Digit of Alarm Setting (0~3)
+ * |[2] |MMON |Mask 1-Month Calendar Digit of Alarm Setting (0~9)
+ * |[3] |MTENMON |Mask 10-Month Calendar Digit of Alarm Setting (0~1)
+ * |[4] |MYEAR |Mask 1-Year Calendar Digit of Alarm Setting (0~9)
+ * |[5] |MTENYEAR |Mask 10-Year Calendar Digit of Alarm Setting (0~9)
+ * @var RTC_T::SPRCTL
+ * Offset: 0x3C RTC Spare Functional Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |SNPDEN |Snoop Detection Enable Bit
+ * | | |0 = TAMPER pin detection is Disabled.
+ * | | |1 = TAMPER pin detection is Enabled.
+ * |[1] |SNPTYPE0 |Snoop Detection Level
+ * | | |This bit controls TAMPER detect event is high level/rising edge or low level/falling edge.
+ * | | |0 = Low level/Falling edge detection.
+ * | | |1 = High level/Rising edge detection.
+ * |[2] |SPRRWEN |Spare Register Enable Bit
+ * | | |0 = Spare register is Disabled.
+ * | | |1 = Spare register is Enabled.
+ * | | |Note: When spare register is disabled, RTC_SPR0 ~ RTC_SPR19 cannot be accessed.
+ * |[3] |SNPTYPE1 |Snoop Detection Mode
+ * | | |This bit controls TAMPER pin is edge or level detection
+ * | | |0 = Level detection.
+ * | | |1 = Edge detection.
+ * |[5] |SPRCSTS |SPR Clear Flag
+ * | | |This bit indicates if the RTC_SPR0 ~RTC_SPR19 content is cleared when specify snoop event is detected.
+ * | | |0 = Spare register content is not cleared.
+ * | | |1 = Spare register content is cleared.
+ * | | |Writes 1 to clear this bit.
+ * |[7] |SPRRWRDY |SPR Register Ready
+ * | | |This bit indicates if the registers RTC_SPRCTL, RTC_SPR0 ~ RTC_SPR19 are ready to be accessed.
+ * | | |After user writing registers RTC_SPRCTL, RTC_SPR0 ~ RTC_SPR19, read this bit to check if these registers are updated done is necessary.
+ * | | |0 = RTC_SPRCTL, RTC_SPR0 ~ RTC_SPR19 updating is in progress.
+ * | | |1 = RTC_SPRCTL, RTC_SPR0 ~ RTC_SPR19 are updated done and ready to be accessed.
+ * | | |Note: This bit is read only and any write to it won't take any effect.
+ * @var RTC_T::SPR
+ * Offset: 0x40 ~ 0x8C RTC Spare Register 0 ~ 19
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |SPARE |Spare Register
+ * | | |This field is used to store back-up information defined by user.
+ * | | |This field will be cleared by hardware automatically once a snooper pin event is detected.
+ * | | |Before storing back-up information in to RTC_SPRx register, user should write 0xA965 to RTC_RWEN[15:0] to make sure register read/write enable bit REWNF (RTC_RWEN[16]) is enabled.
+ * @var RTC_T::LXTCTL
+ * Offset: 0x100 RTC 32.768 kHz Oscillator Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |LXTEN |Backup Domain 32K Oscillator Enable Bit
+ * | | |0 = Oscillator is Disabled.
+ * | | |1 = Oscillator is Enabled.
+ * | | |This bit controls 32 kHz oscillator on/off.
+ * | | |User can set either LXTEN in RTC domain or system manager control register CLK_PWRCTL[1] (LXTEN) to enable 32 kHz oscillator.
+ * | | |If this bit is set 1, X32 kHz oscillator keep running after system power is turned off, if this bit is clear to 0, oscillator is turned off when system power is turned off.
+ * |[3:1] |GAIN |Oscillator Gain Option
+ * | | |User can select oscillator gain according to crystal external loading and operating temperature range.
+ * | | |The larger gain value corresponding to stronger driving capability and higher power consumption.
+ * | | |000 = L0 mode.
+ * | | |001 = L1 mode.
+ * | | |010 = L2 mode.
+ * | | |011 = L3 mode.
+ * | | |100 = L4 mode.
+ * | | |101 = L5 mode.
+ * | | |110 = L6 mode.
+ * | | |111 = L7 mode (Default).
+ * @var RTC_T::LXTOCTL
+ * Offset: 0x104 X32KO Pin Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[1:0] |OPMODE |GPF0 Operation Mode
+ * | | |00 = X32KO (PF.0) is input only mode, without pull-up resistor.
+ * | | |01 = X32KO (PF.0) is output push pull mode.
+ * | | |10 = X32KO (PF.0) is open drain mode.
+ * | | |11 = X32KO (PF.0) is input only mode with internal pull up.
+ * |[2] |DOUT |IO Output Data
+ * | | |0 = X32KO (PF.0) output low.
+ * | | |1 = X32KO (PF.0) output high.
+ * |[3] |CTLSEL |IO Pin State Backup Selection
+ * | | |When low speed 32 kHz oscillator is disabled, X32KO (PF.0) pin can be used as GPIO function.
+ * | | |User can program CTLSEL bit to decide X32KO (PF.0) I/O function is controlled by system power domain GPIO module or VBAT power domain RTC_LXTOCTL control register.
+ * | | |0 = X32KO (PF.0) pin I/O function is controlled by GPIO module.
+ * | | |It becomes floating when system power is turned off.
+ * | | |1 = X32KO (PF.0) pin I/O function is controlled by VBAT power domain, X32KO (PF.0) pin function and I/O status are controlled by OPMODE[1:0] and DOUT after CTLSEL it set to 1.
+ * | | |I/O pin keeps the previous state after system power is turned off.
+ * @var RTC_T::LXTICTL
+ * Offset: 0x108 X32KI Pin Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[1:0] |OPMODE |IO Operation Mode
+ * | | |00 = X32KI (PF.1) is input only mode, without pull-up resistor.
+ * | | |01 = X32KI (PF.1) is output push pull mode.
+ * | | |10 = X32KI (PF.1) is open drain mode.
+ * | | |11 = X32KI (PF.1) is input only mode with internal pull up.
+ * |[2] |DOUT |IO Output Data
+ * | | |0 = X32KI (PF.1) output low.
+ * | | |1 = X32KI (PF.1) output high.
+ * |[3] |CTLSEL |IO Pin State Backup Selection
+ * | | |When low speed 32 kHz oscillator is disabled, X32KI (PF.1) pin can be used as GPIO function.
+ * | | |User can program CTLSEL bit to decide X32KI (PF.1) I/O function is controlled by system power domain GPIO module or VBAT power domain RTC_LXTICTL control register.
+ * | | |0 = X32KI (PF.1) pin I/O function is controlled by GPIO module.
+ * | | |It becomes floating state when system power is turned off.
+ * | | |1 = X32KI (PF.1) pin I/O function is controlled by VBAT power domain, X32KI (PF.1) pin function and I/O status are controlled by OPMODE[1:0] and DOUT after CTLSEL it set to 1.
+ * | | |I/O pin keeps the previous state after system power is turned off.
+ * @var RTC_T::TAMPCTL
+ * Offset: 0x10C TAMPER Pin Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[1:0] |OPMODE |IO Operation Mode
+ * | | |00 = TAMPER (PF.2) is input only mode, without pull-up resistor.
+ * | | |01 = TAMPER (PF.2) is output push pull mode.
+ * | | |10 = TAMPER (PF.2) is open drain mode.
+ * | | |11 = TAMPER (PF.2) is input only mode with internal pull up.
+ * |[2] |DOUT |IO Output Data
+ * | | |0 = TAMPER (PF.2) output low.
+ * | | |1 = TAMPER (PF.2) output high.
+ * |[3] |CTLSEL |IO Pin State Backup Selection
+ * | | |When tamper function is disabled, TAMPER pin can be used as GPIO function.
+ * | | |User can program CTLSEL bit to decide PF.2 I/O function is controlled by system power domain GPIO module or VBAT power domain RTC_TAMPCTL control register.
+ * | | |0 =TAMPER (PF.2) I/O function is controlled by GPIO module.
+ * | | |It becomes floating state when system power is turned off.
+ * | | |1 =TAMPER (PF.2) I/O function is controlled by VBAT power domain.
+ * | | |PF.2 function and I/O status are controlled by OPMODE[1:0] and DOUT after CTLSEL it set to 1.
+ * | | |I/O pin state keeps previous state after system power is turned off.
+ */
+
+ __IO uint32_t INIT; /* Offset: 0x00 RTC Initiation Register */
+ __O uint32_t RWEN; /* Offset: 0x04 RTC Access Enable Register */
+ __IO uint32_t FREQADJ; /* Offset: 0x08 RTC Frequency Compensation Register */
+ __IO uint32_t TIME; /* Offset: 0x0C Time Loading Register */
+ __IO uint32_t CAL; /* Offset: 0x10 RTC Calendar Loading Register */
+ __IO uint32_t CLKFMT; /* Offset: 0x14 Time Scale Selection Register */
+ __IO uint32_t WEEKDAY; /* Offset: 0x18 Day of the Week Register */
+ __IO uint32_t TALM; /* Offset: 0x1C Time Alarm Register */
+ __IO uint32_t CALM; /* Offset: 0x20 Calendar Alarm Register */
+ __I uint32_t LEAPYEAR; /* Offset: 0x24 RTC Leap Year Indicator Register */
+ __IO uint32_t INTEN; /* Offset: 0x28 RTC Interrupt Enable Register */
+ __IO uint32_t INTSTS; /* Offset: 0x2C RTC Interrupt Indicator Register */
+ __IO uint32_t TICK; /* Offset: 0x30 RTC Time Tick Register */
+ __IO uint32_t TAMSK; /* Offset: 0x34 Time Alarm Mask Register */
+ __IO uint32_t CAMSK; /* Offset: 0x38 Calendar Alarm Mask Register */
+ __IO uint32_t SPRCTL; /* Offset: 0x3C RTC Spare Functional Control Register */
+ __IO uint32_t SPR[20]; /* Offset: 0x40 ~ 0x8C RTC Spare Register 0 ~ 19 */
+ __I uint32_t RESERVE0[28];
+ __IO uint32_t LXTCTL; /* Offset: 0x100 RTC 32.768 kHz Oscillator Control Register */
+ __IO uint32_t LXTOCTL; /* Offset: 0x104 X32KO Pin Control Register */
+ __IO uint32_t LXTICTL; /* Offset: 0x108 X32KI Pin Control Register */
+ __IO uint32_t TAMPCTL; /* Offset: 0x10C TAMPER Pin Control Register */
+
+} RTC_T;
+
+
+
+/**
+ @addtogroup RTC_CONST RTC Bit Field Definition
+ Constant Definitions for RTC Controller
+@{ */
+
+#define RTC_INIT_ACTIVE_Pos (0) /*!< RTC_T::INIT: ACTIVE Position */
+#define RTC_INIT_ACTIVE_Msk (0x1ul << RTC_INIT_ACTIVE_Pos) /*!< RTC_T::INIT: ACTIVE Mask */
+
+#define RTC_INIT_INIT_Pos (0) /*!< RTC_T::INIT: INIT Position */
+#define RTC_INIT_INIT_Msk (0xfffffffful << RTC_INIT_INIT_Pos) /*!< RTC_T::INIT: INIT Mask */
+
+#define RTC_RWEN_RWEN_Pos (0) /*!< RTC_T::RWEN: RWEN Position */
+#define RTC_RWEN_RWEN_Msk (0xfffful << RTC_RWEN_RWEN_Pos) /*!< RTC_T::RWEN: RWEN Mask */
+
+#define RTC_RWEN_RWENF_Pos (16) /*!< RTC_T::RWEN: RWENF Position */
+#define RTC_RWEN_RWENF_Msk (0x1ul << RTC_RWEN_RWENF_Pos) /*!< RTC_T::RWEN: RWENF Mask */
+
+#define RTC_FREQADJ_FRACTION_Pos (0) /*!< RTC_T::FREQADJ: FRACTION Position */
+#define RTC_FREQADJ_FRACTION_Msk (0x3ful << RTC_FREQADJ_FRACTION_Pos) /*!< RTC_T::FREQADJ: FRACTION Mask */
+
+#define RTC_FREQADJ_INTEGER_Pos (8) /*!< RTC_T::FREQADJ: INTEGER Position */
+#define RTC_FREQADJ_INTEGER_Msk (0xful << RTC_FREQADJ_INTEGER_Pos) /*!< RTC_T::FREQADJ: INTEGER Mask */
+
+#define RTC_TIME_SEC_Pos (0) /*!< RTC_T::TIME: SEC Position */
+#define RTC_TIME_SEC_Msk (0xful << RTC_TIME_SEC_Pos) /*!< RTC_T::TIME: SEC Mask */
+
+#define RTC_TIME_TENSEC_Pos (4) /*!< RTC_T::TIME: TENSEC Position */
+#define RTC_TIME_TENSEC_Msk (0x7ul << RTC_TIME_TENSEC_Pos) /*!< RTC_T::TIME: TENSEC Mask */
+
+#define RTC_TIME_MIN_Pos (8) /*!< RTC_T::TIME: MIN Position */
+#define RTC_TIME_MIN_Msk (0xful << RTC_TIME_MIN_Pos) /*!< RTC_T::TIME: MIN Mask */
+
+#define RTC_TIME_TENMIN_Pos (12) /*!< RTC_T::TIME: TENMIN Position */
+#define RTC_TIME_TENMIN_Msk (0x7ul << RTC_TIME_TENMIN_Pos) /*!< RTC_T::TIME: TENMIN Mask */
+
+#define RTC_TIME_HR_Pos (16) /*!< RTC_T::TIME: HR Position */
+#define RTC_TIME_HR_Msk (0xful << RTC_TIME_HR_Pos) /*!< RTC_T::TIME: HR Mask */
+
+#define RTC_TIME_TENHR_Pos (20) /*!< RTC_T::TIME: TENHR Position */
+#define RTC_TIME_TENHR_Msk (0x3ul << RTC_TIME_TENHR_Pos) /*!< RTC_T::TIME: TENHR Mask */
+
+#define RTC_CAL_DAY_Pos (0) /*!< RTC_T::CAL: DAY Position */
+#define RTC_CAL_DAY_Msk (0xful << RTC_CAL_DAY_Pos) /*!< RTC_T::CAL: DAY Mask */
+
+#define RTC_CAL_TENDAY_Pos (4) /*!< RTC_T::CAL: TENDAY Position */
+#define RTC_CAL_TENDAY_Msk (0x3ul << RTC_CAL_TENDAY_Pos) /*!< RTC_T::CAL: TENDAY Mask */
+
+#define RTC_CAL_MON_Pos (8) /*!< RTC_T::CAL: MON Position */
+#define RTC_CAL_MON_Msk (0xful << RTC_CAL_MON_Pos) /*!< RTC_T::CAL: MON Mask */
+
+#define RTC_CAL_TENMON_Pos (12) /*!< RTC_T::CAL: TENMON Position */
+#define RTC_CAL_TENMON_Msk (0x1ul << RTC_CAL_TENMON_Pos) /*!< RTC_T::CAL: TENMON Mask */
+
+#define RTC_CAL_YEAR_Pos (16) /*!< RTC_T::CAL: YEAR Position */
+#define RTC_CAL_YEAR_Msk (0xful << RTC_CAL_YEAR_Pos) /*!< RTC_T::CAL: YEAR Mask */
+
+#define RTC_CAL_TENYEAR_Pos (20) /*!< RTC_T::CAL: TENYEAR Position */
+#define RTC_CAL_TENYEAR_Msk (0xful << RTC_CAL_TENYEAR_Pos) /*!< RTC_T::CAL: TENYEAR Mask */
+
+#define RTC_CLKFMT_24HEN_Pos (0) /*!< RTC_T::CLKFMT: 24HEN Position */
+#define RTC_CLKFMT_24HEN_Msk (0x1ul << RTC_CLKFMT_24HEN_Pos) /*!< RTC_T::CLKFMT: 24HEN Mask */
+
+#define RTC_WEEKDAY_WEEKDAY_Pos (0) /*!< RTC_T::WEEKDAY: WEEKDAY Position */
+#define RTC_WEEKDAY_WEEKDAY_Msk (0x7ul << RTC_WEEKDAY_WEEKDAY_Pos) /*!< RTC_T::WEEKDAY: WEEKDAY Mask */
+
+#define RTC_TALM_SEC_Pos (0) /*!< RTC_T::TALM: SEC Position */
+#define RTC_TALM_SEC_Msk (0xful << RTC_TALM_SEC_Pos) /*!< RTC_T::TALM: SEC Mask */
+
+#define RTC_TALM_TENSEC_Pos (4) /*!< RTC_T::TALM: TENSEC Position */
+#define RTC_TALM_TENSEC_Msk (0x7ul << RTC_TALM_TENSEC_Pos) /*!< RTC_T::TALM: TENSEC Mask */
+
+#define RTC_TALM_MIN_Pos (8) /*!< RTC_T::TALM: MIN Position */
+#define RTC_TALM_MIN_Msk (0xful << RTC_TALM_MIN_Pos) /*!< RTC_T::TALM: MIN Mask */
+
+#define RTC_TALM_TENMIN_Pos (12) /*!< RTC_T::TALM: TENMIN Position */
+#define RTC_TALM_TENMIN_Msk (0x7ul << RTC_TALM_TENMIN_Pos) /*!< RTC_T::TALM: TENMIN Mask */
+
+#define RTC_TALM_HR_Pos (16) /*!< RTC_T::TALM: HR Position */
+#define RTC_TALM_HR_Msk (0xful << RTC_TALM_HR_Pos) /*!< RTC_T::TALM: HR Mask */
+
+#define RTC_TALM_TENHR_Pos (20) /*!< RTC_T::TALM: TENHR Position */
+#define RTC_TALM_TENHR_Msk (0x3ul << RTC_TALM_TENHR_Pos) /*!< RTC_T::TALM: TENHR Mask */
+
+#define RTC_CALM_DAY_Pos (0) /*!< RTC_T::CALM: DAY Position */
+#define RTC_CALM_DAY_Msk (0xful << RTC_CALM_DAY_Pos) /*!< RTC_T::CALM: DAY Mask */
+
+#define RTC_CALM_TENDAY_Pos (4) /*!< RTC_T::CALM: TENDAY Position */
+#define RTC_CALM_TENDAY_Msk (0x3ul << RTC_CALM_TENDAY_Pos) /*!< RTC_T::CALM: TENDAY Mask */
+
+#define RTC_CALM_MON_Pos (8) /*!< RTC_T::CALM: MON Position */
+#define RTC_CALM_MON_Msk (0xful << RTC_CALM_MON_Pos) /*!< RTC_T::CALM: MON Mask */
+
+#define RTC_CALM_TENMON_Pos (12) /*!< RTC_T::CALM: TENMON Position */
+#define RTC_CALM_TENMON_Msk (0x1ul << RTC_CALM_TENMON_Pos) /*!< RTC_T::CALM: TENMON Mask */
+
+#define RTC_CALM_YEAR_Pos (16) /*!< RTC_T::CALM: YEAR Position */
+#define RTC_CALM_YEAR_Msk (0xful << RTC_CALM_YEAR_Pos) /*!< RTC_T::CALM: YEAR Mask */
+
+#define RTC_CALM_TENYEAR_Pos (20) /*!< RTC_T::CALM: TENYEAR Position */
+#define RTC_CALM_TENYEAR_Msk (0xful << RTC_CALM_TENYEAR_Pos) /*!< RTC_T::CALM: TENYEAR Mask */
+
+#define RTC_LEAPYEAR_LEAPYEAR_Pos (0) /*!< RTC_T::LEAPYEAR: LEAPYEAR Position */
+#define RTC_LEAPYEAR_LEAPYEAR_Msk (0x1ul << RTC_LEAPYEAR_LEAPYEAR_Pos) /*!< RTC_T::LEAPYEAR: LEAPYEAR Mask */
+
+#define RTC_INTEN_ALMIEN_Pos (0) /*!< RTC_T::INTEN: ALMIEN Position */
+#define RTC_INTEN_ALMIEN_Msk (0x1ul << RTC_INTEN_ALMIEN_Pos) /*!< RTC_T::INTEN: ALMIEN Mask */
+
+#define RTC_INTEN_TICKIEN_Pos (1) /*!< RTC_T::INTEN: TICKIEN Position */
+#define RTC_INTEN_TICKIEN_Msk (0x1ul << RTC_INTEN_TICKIEN_Pos) /*!< RTC_T::INTEN: TICKIEN Mask */
+
+#define RTC_INTEN_SNPDIEN_Pos (2) /*!< RTC_T::INTEN: SNPDIEN Position */
+#define RTC_INTEN_SNPDIEN_Msk (0x1ul << RTC_INTEN_SNPDIEN_Pos) /*!< RTC_T::INTEN: SNPDIEN Mask */
+
+#define RTC_INTSTS_ALMIF_Pos (0) /*!< RTC_T::INTSTS: ALMIF Position */
+#define RTC_INTSTS_ALMIF_Msk (0x1ul << RTC_INTSTS_ALMIF_Pos) /*!< RTC_T::INTSTS: ALMIF Mask */
+
+#define RTC_INTSTS_TICKIF_Pos (1) /*!< RTC_T::INTSTS: TICKIF Position */
+#define RTC_INTSTS_TICKIF_Msk (0x1ul << RTC_INTSTS_TICKIF_Pos) /*!< RTC_T::INTSTS: TICKIF Mask */
+
+#define RTC_INTSTS_SNPDIF_Pos (2) /*!< RTC_T::INTSTS: SNPDIF Position */
+#define RTC_INTSTS_SNPDIF_Msk (0x1ul << RTC_INTSTS_SNPDIF_Pos) /*!< RTC_T::INTSTS: SNPDIF Mask */
+
+#define RTC_TICK_TICK_Pos (0) /*!< RTC_T::TICK: TICK Position */
+#define RTC_TICK_TICK_Msk (0x7ul << RTC_TICK_TICK_Pos) /*!< RTC_T::TICK: TICK Mask */
+
+#define RTC_TAMSK_MSEC_Pos (0) /*!< RTC_T::TAMSK: MSEC Position */
+#define RTC_TAMSK_MSEC_Msk (0x1ul << RTC_TAMSK_MSEC_Pos) /*!< RTC_T::TAMSK: MSEC Mask */
+
+#define RTC_TAMSK_MTENSEC_Pos (1) /*!< RTC_T::TAMSK: MTENSEC Position */
+#define RTC_TAMSK_MTENSEC_Msk (0x1ul << RTC_TAMSK_MTENSEC_Pos) /*!< RTC_T::TAMSK: MTENSEC Mask */
+
+#define RTC_TAMSK_MMIN_Pos (2) /*!< RTC_T::TAMSK: MMIN Position */
+#define RTC_TAMSK_MMIN_Msk (0x1ul << RTC_TAMSK_MMIN_Pos) /*!< RTC_T::TAMSK: MMIN Mask */
+
+#define RTC_TAMSK_MTENMIN_Pos (3) /*!< RTC_T::TAMSK: MTENMIN Position */
+#define RTC_TAMSK_MTENMIN_Msk (0x1ul << RTC_TAMSK_MTENMIN_Pos) /*!< RTC_T::TAMSK: MTENMIN Mask */
+
+#define RTC_TAMSK_MHR_Pos (4) /*!< RTC_T::TAMSK: MHR Position */
+#define RTC_TAMSK_MHR_Msk (0x1ul << RTC_TAMSK_MHR_Pos) /*!< RTC_T::TAMSK: MHR Mask */
+
+#define RTC_TAMSK_MTENHR_Pos (5) /*!< RTC_T::TAMSK: MTENHR Position */
+#define RTC_TAMSK_MTENHR_Msk (0x1ul << RTC_TAMSK_MTENHR_Pos) /*!< RTC_T::TAMSK: MTENHR Mask */
+
+#define RTC_CAMSK_MDAY_Pos (0) /*!< RTC_T::CAMSK: MDAY Position */
+#define RTC_CAMSK_MDAY_Msk (0x1ul << RTC_CAMSK_MDAY_Pos) /*!< RTC_T::CAMSK: MDAY Mask */
+
+#define RTC_CAMSK_MTENDAY_Pos (1) /*!< RTC_T::CAMSK: MTENDAY Position */
+#define RTC_CAMSK_MTENDAY_Msk (0x1ul << RTC_CAMSK_MTENDAY_Pos) /*!< RTC_T::CAMSK: MTENDAY Mask */
+
+#define RTC_CAMSK_MMON_Pos (2) /*!< RTC_T::CAMSK: MMON Position */
+#define RTC_CAMSK_MMON_Msk (0x1ul << RTC_CAMSK_MMON_Pos) /*!< RTC_T::CAMSK: MMON Mask */
+
+#define RTC_CAMSK_MTENMON_Pos (3) /*!< RTC_T::CAMSK: MTENMON Position */
+#define RTC_CAMSK_MTENMON_Msk (0x1ul << RTC_CAMSK_MTENMON_Pos) /*!< RTC_T::CAMSK: MTENMON Mask */
+
+#define RTC_CAMSK_MYEAR_Pos (4) /*!< RTC_T::CAMSK: MYEAR Position */
+#define RTC_CAMSK_MYEAR_Msk (0x1ul << RTC_CAMSK_MYEAR_Pos) /*!< RTC_T::CAMSK: MYEAR Mask */
+
+#define RTC_CAMSK_MTENYEAR_Pos (5) /*!< RTC_T::CAMSK: MTENYEAR Position */
+#define RTC_CAMSK_MTENYEAR_Msk (0x1ul << RTC_CAMSK_MTENYEAR_Pos) /*!< RTC_T::CAMSK: MTENYEAR Mask */
+
+#define RTC_SPRCTL_SNPDEN_Pos (0) /*!< RTC_T::SPRCTL: SNPDEN Position */
+#define RTC_SPRCTL_SNPDEN_Msk (0x1ul << RTC_SPRCTL_SNPDEN_Pos) /*!< RTC_T::SPRCTL: SNPDEN Mask */
+
+#define RTC_SPRCTL_SNPTYPE0_Pos (1) /*!< RTC_T::SPRCTL: SNPTYPE0 Position */
+#define RTC_SPRCTL_SNPTYPE0_Msk (0x1ul << RTC_SPRCTL_SNPTYPE0_Pos) /*!< RTC_T::SPRCTL: SNPTYPE0 Mask */
+
+#define RTC_SPRCTL_SPRRWEN_Pos (2) /*!< RTC_T::SPRCTL: SPRRWEN Position */
+#define RTC_SPRCTL_SPRRWEN_Msk (0x1ul << RTC_SPRCTL_SPRRWEN_Pos) /*!< RTC_T::SPRCTL: SPRRWEN Mask */
+
+#define RTC_SPRCTL_SNPTYPE1_Pos (3) /*!< RTC_T::SPRCTL: SNPTYPE1 Position */
+#define RTC_SPRCTL_SNPTYPE1_Msk (0x1ul << RTC_SPRCTL_SNPTYPE1_Pos) /*!< RTC_T::SPRCTL: SNPTYPE1 Mask */
+
+#define RTC_SPRCTL_SPRCSTS_Pos (5) /*!< RTC_T::SPRCTL: SPRCSTS Position */
+#define RTC_SPRCTL_SPRCSTS_Msk (0x1ul << RTC_SPRCTL_SPRCSTS_Pos) /*!< RTC_T::SPRCTL: SPRCSTS Mask */
+
+#define RTC_SPRCTL_SPRRWRDY_Pos (7) /*!< RTC_T::SPRCTL: SPRRWRDY Position */
+#define RTC_SPRCTL_SPRRWRDY_Msk (0x1ul << RTC_SPRCTL_SPRRWRDY_Pos) /*!< RTC_T::SPRCTL: SPRRWRDY Mask */
+
+#define RTC_SPR_SPARE_Pos (0) /*!< RTC_T::SPR: SPARE Position */
+#define RTC_SPR_SPARE_Msk (0xfffffffful << RTC_SPR_SPARE_Pos) /*!< RTC_T::SPR: SPARE Mask */
+
+#define RTC_LXTCTL_LXTEN_Pos (0) /*!< RTC_T::LXTCTL: LXTEN Position */
+#define RTC_LXTCTL_LXTEN_Msk (0x1ul << RTC_LXTCTL_LXTEN_Pos) /*!< RTC_T::LXTCTL: LXTEN Mask */
+
+#define RTC_LXTCTL_GAIN_Pos (1) /*!< RTC_T::LXTCTL: GAIN Position */
+#define RTC_LXTCTL_GAIN_Msk (0x7ul << RTC_LXTCTL_GAIN_Pos) /*!< RTC_T::LXTCTL: GAIN Mask */
+
+#define RTC_LXTOCTL_OPMODE_Pos (0) /*!< RTC_T::LXTOCTL: OPMODE Position */
+#define RTC_LXTOCTL_OPMODE_Msk (0x3ul << RTC_LXTOCTL_OPMODE_Pos) /*!< RTC_T::LXTOCTL: OPMODE Mask */
+
+#define RTC_LXTOCTL_DOUT_Pos (2) /*!< RTC_T::LXTOCTL: DOUT Position */
+#define RTC_LXTOCTL_DOUT_Msk (0x1ul << RTC_LXTOCTL_DOUT_Pos) /*!< RTC_T::LXTOCTL: DOUT Mask */
+
+#define RTC_LXTOCTL_CTLSEL_Pos (3) /*!< RTC_T::LXTOCTL: CTLSEL Position */
+#define RTC_LXTOCTL_CTLSEL_Msk (0x1ul << RTC_LXTOCTL_CTLSEL_Pos) /*!< RTC_T::LXTOCTL: CTLSEL Mask */
+
+#define RTC_LXTICTL_OPMODE_Pos (0) /*!< RTC_T::LXTICTL: OPMODE Position */
+#define RTC_LXTICTL_OPMODE_Msk (0x3ul << RTC_LXTICTL_OPMODE_Pos) /*!< RTC_T::LXTICTL: OPMODE Mask */
+
+#define RTC_LXTICTL_DOUT_Pos (2) /*!< RTC_T::LXTICTL: DOUT Position */
+#define RTC_LXTICTL_DOUT_Msk (0x1ul << RTC_LXTICTL_DOUT_Pos) /*!< RTC_T::LXTICTL: DOUT Mask */
+
+#define RTC_LXTICTL_CTLSEL_Pos (3) /*!< RTC_T::LXTICTL: CTLSEL Position */
+#define RTC_LXTICTL_CTLSEL_Msk (0x1ul << RTC_LXTICTL_CTLSEL_Pos) /*!< RTC_T::LXTICTL: CTLSEL Mask */
+
+#define RTC_TAMPCTL_OPMODE_Pos (0) /*!< RTC_T::TAMPCTL: OPMODE Position */
+#define RTC_TAMPCTL_OPMODE_Msk (0x3ul << RTC_TAMPCTL_OPMODE_Pos) /*!< RTC_T::TAMPCTL: OPMODE Mask */
+
+#define RTC_TAMPCTL_DOUT_Pos (2) /*!< RTC_T::TAMPCTL: DOUT Position */
+#define RTC_TAMPCTL_DOUT_Msk (0x1ul << RTC_TAMPCTL_DOUT_Pos) /*!< RTC_T::TAMPCTL: DOUT Mask */
+
+#define RTC_TAMPCTL_CTLSEL_Pos (3) /*!< RTC_T::TAMPCTL: CTLSEL Position */
+#define RTC_TAMPCTL_CTLSEL_Msk (0x1ul << RTC_TAMPCTL_CTLSEL_Pos) /*!< RTC_T::TAMPCTL: CTLSEL Mask */
+
+/**@}*/ /* RTC_CONST */
+/**@}*/ /* end of RTC register group */
+
+
+/*---------------------- Smart Card Host Interface Controller -------------------------*/
+/**
+ @addtogroup SC Smart Card Host Interface Controller(SC)
+ Memory Mapped Structure for SC Controller
+@{ */
+
+
+typedef struct
+{
+
+
+/**
+ * @var SC_T::DAT
+ * Offset: 0x00 SC Receiving/Transmit Holding Buffer Register.
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:0] |DAT |Receiving/ Transmit Holding Buffer
+ * | | |Write Operation:
+ * | | |By writing data to DAT, the SC will send out an 8-bit data.
+ * | | |Note: If SCEN(SC_CTL[0]) is not enabled, DAT cannot be programmed.
+ * | | |Read Operation:
+ * | | |By reading DAT, the SC will return an 8-bit received data.
+ * @var SC_T::CTL
+ * Offset: 0x04 SC Control Register.
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |SCEN |SC Engine Enable Bit
+ * | | |Set this bit to 1 to enable SC operation.
+ * | | |If this bit is cleared, SC will force all transition to IDLE state.
+ * |[1] |RXOFF |RX Transition Disable Control
+ * | | |0 = The receiver Enabled.
+ * | | |1 = The receiver Disabled.
+ * | | |Note:
+ * | | |If AUTOCEN (SC_CTL[3])is enabled, these fields must be ignored.
+ * |[2] |TXOFF |TX Transition Disable Control
+ * | | |0 = The transceiver Enabled.
+ * | | |1 = The transceiver Disabled.
+ * |[3] |AUTOCEN |Auto Convention Enable Bit
+ * | | |0 = Auto-convention Disabled.
+ * | | |1 = Auto-convention Enabled.
+ * | | |When hardware receives TS in answer to reset state and the TS is direct convention, CONSEL(SC_CTL[5:4]) will be set to 00 automatically, otherwise if the TS is inverse convention, and CONSEL (SC_CTL[5:4]) will be set to 11.
+ * | | |If software enables auto convention function, the setting step must be done before Answer to Reset state and the first data must be 0x3B or 0x3F.
+ * | | |After hardware received first data and stored it at buffer,
+ * | | |hardware will decided the convention and change the CONSEL (SC_CTL[5:4]) bits automatically.
+ * | | |If the first data is not 0x3B or 0x3F, hardware will generate an interrupt if ACERRIEN (SC_INTEN[10]) = 1 to CPU.
+ * |[5:4] |CONSEL |Convention Selection
+ * | | |00 = Direct convention.
+ * | | |01 = Reserved.
+ * | | |10 = Reserved.
+ * | | |11 = Inverse convention.
+ * | | |Note:
+ * | | |If AUTOCEN(SC_CTL[3]) enabled, this fields are ignored.
+ * |[7:6] |RXTRGLV |Rx Buffer Trigger Level
+ * | | |When the number of bytes in the receiving buffer equals the RXTRGLV, the RDAIF will be set (if SC_INTEN [RDAIEN] is enabled, an interrupt will be generated).
+ * | | |00 = INTR_RDA Trigger Level with 01 Bytes.
+ * | | |01 = INTR_RDA Trigger Level with 02 Bytes.
+ * | | |10 = INTR_RDA Trigger Level with 03 Bytes.
+ * | | |11 = Reserved.
+ * |[12:8] |BGT |Block Guard Time (BGT)
+ * | | |Block guard time means the minimum bit length between the leading edges of two consecutive characters between different transfer directions.
+ * | | |This field indicates the counter for the bit length of block guard time.
+ * | | |According to ISO7816-3, in T = 0 mode, software must fill 15 (real block guard time = 16.5) to this field; in T = 1 mode, software must fill 21 (real block guard time = 22.5) to it.
+ * | | |Note:
+ * | | |The real block guard time is BGT + 1.
+ * |[14:13] |TMRSEL |Timer Selection
+ * | | |00 = All internal timer function Disabled.
+ * | | |01 = Internal 24 bit timer Enabled.
+ * | | |Software can configure it by setting SC_TMRCTL0 [23:0].
+ * | | |SC_TMRCTL1 and SC_TMRCTL2 will be ignored in this mode.
+ * | | |10 = internal 24 bit timer and 8 bit internal timer Enabled.
+ * | | |Software can configure the 24 bit timer by setting SC_TMRCTL0 [23:0] and configure the 8 bit timer by setting SC_TMRCTL1[7:0].
+ * | | |SC_TMRCTL2 will be ignored in this mode.
+ * | | |11 = Internal 24 bit timer and two 8 bit timers Enabled.
+ * | | |Software can configure them by setting SC_TMRCTL0 [23:0], SC_TMRCTL1 [7:0] and SC_TMRCTL2 [7:0].
+ * |[15] |NSB |Stop Bit Length
+ * | | |This field indicates the length of stop bit.
+ * | | |0 = The stop bit length is 2 ETU.
+ * | | |1= The stop bit length is 1 ETU.
+ * | | |Note:
+ * | | |The default stop bit length is 2. SMC and UART adopts NSB to program the stop bit length
+ * |[18:16] |RXRTY |RX Error Retry Count Number
+ * | | |This field indicates the maximum number of receiver retries that are allowed when parity error has occurred
+ * | | |Note1: The real retry number is RXRTY + 1, so 8 is the maximum retry number.
+ * | | |Note2: This field cannot be changed when RXRTYEN enabled.
+ * | | |The change flow is to disable RXRTYEN first and then fill in new retry value.
+ * |[19] |RXRTYEN |RX Error Retry Enable Bit
+ * | | |This bit enables receiver retry function when parity error has occurred.
+ * | | |0 = RX error retry function Disabled.
+ * | | |1 = RX error retry function Enabled.
+ * | | |Note:
+ * | | |Software must fill in the RXRTY value before enabling this bit.
+ * |[22:20] |TXRTY |TX Error Retry Count Number
+ * | | |This field indicates the maximum number of transmitter retries that are allowed when parity error has occurred.
+ * | | |Note1: The real retry number is TXRTY + 1, so 8 is the maximum retry number.
+ * | | |Note2: This field cannot be changed when TXRTYEN enabled.
+ * | | |The change flow is to disable TXRTYEN first and then fill in new retry value.
+ * |[23] |TXRTYEN |TX Error Retry Enable Bit
+ * | | |This bit enables transmitter retry function when parity error has occurred.
+ * | | |0 = TX error retry function Disabled.
+ * | | |1 = TX error retry function Enabled.
+ * |[25:24] |CDDBSEL |Card Detect De-Bounce Selection
+ * | | |This field indicates the card detect de-bounce selection.
+ * | | |00 = De-bounce sample card insert once per 384 (128 * 3) peripheral clocks and de-bounce sample card removal once per 128 peripheral clocks.
+ * | | |01 = De-bounce sample card insert once per 192 (64 * 3) peripheral clocks and de-bounce sample card removal once per 64 peripheral clocks.
+ * | | |10 = De-bounce sample card insert once per 96 (32 * 3) peripheral clocks and de-bounce sample card removal once per 32 peripheral clocks.
+ * | | |11 = De-bounce sample card insert once per 48 (16 * 3) peripheral clocks and de-bounce sample card removal once per 16 peripheral clocks.
+ * |[26] |CDLV |Card Detect Level
+ * | | |0 = When hardware detects the card detect pin (SC_CD) from high to low, it indicates a card is detected.
+ * | | |1 = When hardware detects the card detect pin from low to high, it indicates a card is detected.
+ * | | |Note: Software must select card detect level before Smart Card engine enabled.
+ * |[30] |SYNC |SYNC Flag Indicator
+ * | | |Due to synchronization, software should check this bit before writing a new value to RXRTY and TXRTY.
+ * | | |0 = Synchronizing is completion, user can write new data to RXRTY and TXRTY.
+ * | | |1 = Last value is synchronizing.
+ * | | |Note: This bit is read only.
+ * |[31] |ICEDEBUG |ICE Debug Mode Acknowledge Disable Control
+ * | | |0 = ICE debug mode acknowledgement affects SC counting.
+ * | | |SC internal counter will be held while CPU is held by ICE.
+ * | | |1 = ICE debug mode acknowledgement Disabled.
+ * | | |SC internal counter will keep going no matter CPU is held by ICE or not.
+ * @var SC_T::ALTCTL
+ * Offset: 0x08 SC Alternate Control Register.
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |TXRST |TX Software Reset
+ * | | |When TXRST is set, all the bytes in the transmit buffer and TX internal state machine will be cleared.
+ * | | |0 = No effect.
+ * | | |1 = Reset the TX internal state machine and pointers.
+ * | | |Note:
+ * | | |This bit will be auto cleared after reset is complete.
+ * |[1] |RXRST |Rx Software Reset
+ * | | |When RXRST is set, all the bytes in the receiver buffer and Rx internal state machine will be cleared.
+ * | | |0 = No effect.
+ * | | |1 = Reset the Rx internal state machine and pointers.
+ * | | |Note:
+ * | | |This bit will be auto cleared after reset is complete.
+ * |[2] |DACTEN |Deactivation Sequence Generator Enable Bit
+ * | | |This bit enables SC controller to initiate the card by deactivation sequence
+ * | | |0 = No effect.
+ * | | |1 = Deactivation sequence generator Enabled.
+ * | | |Note1:
+ * | | |When the deactivation sequence completed, this bit will be cleared automatically and the INITIF(SC_INTSTS[8]) will be set to 1.
+ * | | |Note2:
+ * | | |This field will be cleared by TXRST (SC_ALTCTL[0]) and RXRST(SC_ALTCTL[1]).
+ * | | |So don't fill this bit, TXRST, and RXRST at the same time.
+ * | | |Note3:
+ * | | |If SCEN (SC_CTL[0]) is not enabled, this filed cannot be programmed.
+ * |[3] |ACTEN |Activation Sequence Generator Enable Bit
+ * | | |This bit enables SC controller to initiate the card by activation sequence
+ * | | |0 = No effect.
+ * | | |1 = Activation sequence generator Enabled.
+ * | | |Note1:
+ * | | |When the activation sequence completed, this bit will be cleared automatically and the INITIF(SC_INTSTS[8]) will be set to 1.
+ * | | |Note2:
+ * | | |This field will be cleared by TXRST(SC_ALTCTL[0]) and RXRST(SC_ALTCTL[1]), so don't fill this bit, TXRST(SC_ALTCTL[0]), and RXRST(SC_ALTCTL[1]) at the same time.
+ * | | |Note3:
+ * | | |If SCEN(SC_CTL[0]) is not enabled, this filed cannot be programmed.
+ * |[4] |WARSTEN |Warm Reset Sequence Generator Enable Bit
+ * | | |This bit enables SC controller to initiate the card by warm reset sequence
+ * | | |0 = No effect.
+ * | | |1 = Warm reset sequence generator Enabled.
+ * | | |Note1:
+ * | | |When the warm reset sequence completed, this bit will be cleared automatically and the INITIF(SC_INTSTS[8]) will be set to 1.
+ * | | |Note2:
+ * | | |This field will be cleared by TXRST(SC_ALTCTL[0]) and RXRST(SC_ALTCTL[1]), so don't fill this bit, TXRST, and RXRST at the same time.
+ * | | |Note3:
+ * | | |If SCEN(SC_CTL[0]) is not enabled, this filed cannot be programmed.
+ * |[5] |CNTEN0 |Internal Timer0 Start Enable Bit
+ * | | |This bit enables Timer 0 to start counting.
+ * | | |Software can fill 0 to stop it and set 1 to reload and count.
+ * | | |0 = Stops counting.
+ * | | |1 = Start counting.
+ * | | |Note1:
+ * | | |This field is used for internal 24 bit timer when TMRSEL (SC_CTL[14:13]) = 01.
+ * | | |Note2:
+ * | | |If the operation mode is not in auto-reload mode (SC_TMRCTL0[26] = 0), this bit will be auto-cleared by hardware.
+ * | | |Note3:
+ * | | |This field will be cleared by TXRST(SC_ALTCTL[0]) and RXRST(SC_ALTCTL[1]).
+ * | | |So don't fill this bit, TXRST and RXRST at the same time.
+ * | | |Note4: If SCEN(SC_CTL[0]) is not enabled, this filed cannot be programmed.
+ * |[6] |CNTEN1 |Internal Timer1 Start Enable Bit
+ * | | |This bit enables Timer 1 to start counting.
+ * | | |Software can fill 0 to stop it and set 1 to reload and count.
+ * | | |0 = Stops counting.
+ * | | |1 = Start counting.
+ * | | |Note1:
+ * | | |This field is used for internal 8 bit timer when TMRSEL(SC_CTL[14:13]) = 10 or TMRSEL(SC_CTL[14:13]) = 11.
+ * | | |Don't filled CNTEN1 when TMRSEL(SC_CTL[14:13]) = 00 or TMRSEL(SC_CTL[14:13]) = 01.
+ * | | |Note2:
+ * | | |If the operation mode is not in auto-reload mode (SC_TMRCTL1[26] = 0), this bit will be auto-cleared by hardware.
+ * | | |Note3:
+ * | | |This field will be cleared by TXRST(SC_ALTCTL[0]) and RXRST(SC_ALTCTL[1]), so don't fill this bit, TXRST(SC_ALTCTL[0]), and RXRST(SC_ALTCTL[1]) at the same time.
+ * | | |Note4:
+ * | | |If SCEN(SC_CTL[0]) is not enabled, this filed cannot be programmed.
+ * |[7] |CNTEN2 |Internal Timer2 Start Enable Bit
+ * | | |This bit enables Timer 2 to start counting.
+ * | | |Software can fill 0 to stop it and set 1 to reload and count.
+ * | | |0 = Stops counting.
+ * | | |1 = Start counting.
+ * | | |Note1:
+ * | | |This field is used for internal 8 bit timer when TMRSEL(SC_CTL[14:13]) = 11.
+ * | | |Don't filled CNTEN2 when TMRSEL(SC_CTL[14:13]) = 00 or TMRSEL(SC_CTL[14:13]) = 01 or TMRSEL(SC_CTL[14:13]) = 10.
+ * | | |Note2:
+ * | | |If the operation mode is not in auto-reload mode (SC_TMRCTL2[26] = 0), this bit will be auto-cleared by hardware.
+ * | | |Note3:
+ * | | |This field will be cleared by TXRST(SC_ALTCTL[0]) and RXRST(SC_ALTCTL[1]).
+ * | | |So don't fill this bit, TXRST(SC_ALTCTL[0]), and RXRST(SC_ALTCTL[1]) at the same time.
+ * | | |Note4:
+ * | | |If SCEN(SC_CTL[0]) is not enabled, this filed cannot be programmed.
+ * |[9:8] |INITSEL |Initial Timing Selection
+ * | | |This fields indicates the timing of hardware initial state (activation or warm-reset or deactivation).
+ * | | |Unit: SC clock
+ * | | |Activation: refer to SC Activation Sequence in Figure 6.17-4
+ * | | |Warm-reset: refer to Warm-Reset Sequence in Figure 6.17-5
+ * | | |Deactivation: refer to Deactivation Sequence in Figure 6.17-6
+ * |[12] |RXBGTEN |Receiver Block Guard Time Function Enable Bit
+ * | | |0 = Receiver block guard time function Disabled.
+ * | | |1 = Receiver block guard time function Enabled.
+ * |[13] |ACTSTS0 |Internal Timer0 Active State (Read Only)
+ * | | |This bit indicates the timer counter status of timer0.
+ * | | |0 = Timer0 is not active.
+ * | | |1 = Timer0 is active.
+ * |[14] |ACTSTS1 |Internal Timer1 Active State (Read Only)
+ * | | |This bit indicates the timer counter status of timer1.
+ * | | |0 = Timer1 is not active.
+ * | | |1 = Timer1 is active.
+ * |[15] |ACTSTS2 |Internal Timer2 Active State (Read Only)
+ * | | |This bit indicates the timer counter status of timer2.
+ * | | |0 = Timer2 is not active.
+ * | | |1 = Timer2 is active.
+ * @var SC_T::EGT
+ * Offset: 0x0C SC Extend Guard Time Register.
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:0] |EGT |Extended Guard Time
+ * | | |This field indicates the extended guard timer value.
+ * | | |Note:
+ * | | |The counter is ETU base and the real extended guard time is EGT.
+ * @var SC_T::RXTOUT
+ * Offset: 0x10 SC Receive buffer Time-out Register.
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[8:0] |RFTM |SC Receiver FIFO Time-out (ETU Base)
+ * | | |The time-out counter resets and starts counting whenever the RX buffer received a new data word.
+ * | | |Once the counter decrease to 1 and no new data is received or CPU does not read data by reading SC_DAT buffer, a receiver time-out interrupt INT_RTMR will be generated(if RXTOIF(SC_INTEN[9]) = 1 ).
+ * | | |Note1: The counter unit is ETU based and the interval of time-out is RFTM + 0.5.
+ * | | |Note2:
+ * | | |Filling all 0 to this field indicates to disable this function.
+ * @var SC_T::ETUCTL
+ * Offset: 0x14 SC ETU Control Register.
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[11:0] |ETURDIV |ETU Rate Divider
+ * | | |The field indicates the clock rate divider.
+ * | | |The real ETU is ETURDIV + 1.
+ * | | |Note:
+ * | | |Software can configure this field, but this field must be greater than 0x004.
+ * |[15] |CMPEN |Compensation Mode Enable Bit
+ * | | |This bit enables clock compensation function.
+ * | | |When this bit enabled, hardware will alternate between n clock cycles and n-1 clock cycles, where n is the value to be written into the ETURDIV .
+ * | | |0 = Compensation function Disabled.
+ * | | |1 = Compensation function Enabled.
+ * @var SC_T::INTEN
+ * Offset: 0x18 SC Interrupt Enable Control Register.
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |RDAIEN |Receive Data Reach Interrupt Enable Bit
+ * | | |This field is used for received data reaching trigger level RXTRGLV (SC_CTL[7:6]) interrupt enable.
+ * | | |0 = Receive data reach trigger level interrupt Disabled.
+ * | | |1 = Receive data reach trigger level interrupt Enabled.
+ * |[1] |TBEIEN |Transmit Buffer Empty Interrupt Enable Bit
+ * | | |This field is used for transmit buffer empty interrupt enable.
+ * | | |0 = Transmit buffer empty interrupt Disabled.
+ * | | |1 = Transmit buffer empty interrupt Enabled.
+ * |[2] |TERRIEN |Transfer Error Interrupt Enable Bit
+ * | | |This field is used for transfer error interrupt enable.
+ * | | |The transfer error states is at SC_STATUS register which includes receiver break error BEF(SC_STATUS[6]), frame error FEF(SC_STATUS[5]), parity error PEF(SC_STATUS[4]), receiver buffer overflow error RXOV(SC_STATUS[0]), transmit buffer overflow error TXOV(SC_STATUS[8]), receiver retry over limit error RXOVERR(SC_STATUS[22]) and transmitter retry over limit error TXOVERR (SC_STATUS[30]).
+ * | | |0 = Transfer error interrupt Disabled.
+ * | | |1 = Transfer error interrupt Enabled.
+ * |[3] |TMR0IEN |Timer0 Interrupt Enable Bit
+ * | | |This field is used to enable TMR0 interrupt enable.
+ * | | |0 = Timer0 interrupt Disabled.
+ * | | |1 = Timer0 interrupt Enabled.
+ * |[4] |TMR1IEN |Timer1 Interrupt Enable Bit
+ * | | |This field is used to enable the TMR1 interrupt.
+ * | | |0 = Timer1 interrupt Disabled.
+ * | | |1 = Timer1 interrupt Enabled.
+ * |[5] |TMR2IEN |Timer2 Interrupt Enable Bit
+ * | | |This field is used for TMR2 interrupt enable.
+ * | | |0 = Timer2 interrupt Disabled.
+ * | | |1 = Timer2 interrupt Enabled.
+ * |[6] |BGTIEN |Block Guard Time Interrupt Enable Bit
+ * | | |This field is used for block guard time interrupt enable.
+ * | | |0 = Block guard time Disabled.
+ * | | |1 = Block guard time Enabled.
+ * |[7] |CDIEN |Card Detect Interrupt Enable Bit
+ * | | |This field is used for card detect interrupt enable. The card detect status is CINSERT(SC_STATUS[12])
+ * | | |0 = Card detect interrupt Disabled.
+ * | | |1 = Card detect interrupt Enabled.
+ * |[8] |INITIEN |Initial End Interrupt Enable Bit
+ * | | |This field is used for activation (ACTEN(SC_ALTCTL[3] = 1)), deactivation ((DACTEN SC_ALTCTL[2]) = 1) and warm reset (WARSTEN (SC_ALTCTL [4])) sequence interrupt enable.
+ * | | |0 = Initial end interrupt Disabled.
+ * | | |1 = Initial end interrupt Enabled.
+ * |[9] |RXTOIF |Receiver Buffer Time-Out Interrupt Enable Bit
+ * | | |This field is used for receiver buffer time-out interrupt enable.
+ * | | |0 = Receiver buffer time-out interrupt Disabled.
+ * | | |1 = Receiver buffer time-out interrupt Enabled.
+ * |[10] |ACERRIEN |Auto Convention Error Interrupt Enable Bit
+ * | | |This field is used for auto-convention error interrupt enable.
+ * | | |0 = Auto-convention error interrupt Disabled.
+ * | | |1 = Auto-convention error interrupt Enabled.
+ * @var SC_T::INTSTS
+ * Offset: 0x1C SC Interrupt Status Register.
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |RDAIF |Receive Data Reach Interrupt Status Flag (Read Only)
+ * | | |This field is used for received data reaching trigger level RXTRGLV (SC_CTL[7:6]) interrupt status flag.
+ * | | |Note: This field is the status flag of received data reaching RXTRGLV (SC_CTL[7:6]).
+ * | | |If software reads data from SC_DAT and receiver buffer data byte number is less than RXTRGLV (SC_CTL[7:6]), this bit will be cleared automatically.
+ * |[1] |TBEIF |Transmit Buffer Empty Interrupt Status Flag (Read Only)
+ * | | |This field is used for transmit buffer empty interrupt status flag.
+ * | | |Note: This field is the status flag of transmit buffer empty state.
+ * | | |If software wants to clear this bit, software must write data to DAT(SC_DAT[7:0]) buffer and then this bit will be cleared automatically.
+ * |[2] |TERRIF |Transfer Error Interrupt Status Flag (Read Only)
+ * | | |This field is used for transfer error interrupt status flag.
+ * | | |The transfer error states is at SC_STATUS register which includes receiver break error BEF(SC_STATUS[6]), frame error FEF(SC_STATUS[5]), parity error PEF(SC_STATUS[4]) and receiver buffer overflow error RXOV(SC_STATUS[0]), transmit buffer overflow error TXOV(SC_STATUS[8]), receiver retry over limit error RXOVERR(SC_STATUS[22]) and transmitter retry over limit error TXOVERR(SC_STATUS[30]).
+ * | | |Note: This field is the status flag of
+ * | | |BEF(SC_STATUS[6]), FEF(SC_STATUS[5]), PEF(SC_STATUS[4]), RXOV(SC_STATUS[0]), TXOV(SC_STATUS[8]), RXOVERR(SC_STATUS[22]) or TXOVERR(SC_STATUS[30]).
+ * | | |So, if software wants to clear this bit, software must write 1 to each field.
+ * |[3] |TMR0IF |Timer0 Interrupt Status Flag (Read Only)
+ * | | |This field is used for TMR0 interrupt status flag.
+ * | | |Note: This bit is read only, but it can be cleared by writing 1 to it.
+ * |[4] |TMR1IF |Timer1 Interrupt Status Flag (Read Only)
+ * | | |This field is used for TMR1 interrupt status flag.
+ * | | |Note: This bit is read only, but it can be cleared by writing 1 to it.
+ * |[5] |TMR2IF |Timer2 Interrupt Status Flag (Read Only)
+ * | | |This field is used for TMR2 interrupt status flag.
+ * | | |Note: This bit is read only, but it can be cleared by writing 1 to it.
+ * |[6] |BGTIF |Block Guard Time Interrupt Status Flag (Read Only)
+ * | | |This field is used for block guard time interrupt status flag.
+ * | | |Note1: This bit is valid when RXBGTEN (SC_ALTCTL[12]) is enabled.
+ * | | |Note2: This bit is read only, but it can be cleared by writing "1" to it.
+ * |[7] |CDIF |Card Detect Interrupt Status Flag (Read Only)
+ * | | |This field is used for card detect interrupt status flag.
+ * | | |The card detect status is CINSERT (SC_STATUS[12]) and CREMOVE(SC_STATUS[11]).
+ * | | |Note:
+ * | | |This field is the status flag of CINSERT(SC_STATUS[12]) or CREMOVE(SC_STATUS[11])].
+ * | | |So if software wants to clear this bit, software must write 1 to this field.
+ * |[8] |INITIF |Initial End Interrupt Status Flag (Read Only)
+ * | | |This field is used for activation (ACTEN(SC_ALTCTL[3])), deactivation (DACTEN (SC_ALTCTL[2])) and warm reset (WARSTEN (SC_ALTCTL[4])) sequence interrupt status flag.
+ * | | |Note: This bit is read only, but it can be cleared by writing 1 to it.
+ * |[9] |RBTOIF |Receiver Buffer Time-Out Interrupt Status Flag (Read Only)
+ * | | |This field is used for receiver buffer time-out interrupt status flag.
+ * | | |Note: This field is the status flag of receiver buffer time-out state.
+ * | | |If software wants to clear this bit, software must read all receiver buffer remaining data by reading SC_DAT buffer,.
+ * |[10] |ACERRIF |Auto Convention Error Interrupt Status Flag (Read Only)
+ * | | |This field indicates auto convention sequence error.
+ * | | |If the received TS at ATR state is neither 0x3B nor 0x3F, this bit will be set.
+ * | | |Note: This bit is read only, but it can be cleared by writing 1 to it.
+ * @var SC_T::STATUS
+ * Offset: 0x20 SC Status Register.
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |RXOV |RX Overflow Error Status Flag (Read Only)
+ * | | |This bit is set when RX buffer overflow.
+ * | | |If the number of received bytes is greater than Rx Buffer size (4 bytes), this bit will be set.
+ * | | |Note: This bit is read only, but it can be cleared by writing 1 to it.
+ * |[1] |RXEMPTY |Receiver Buffer Empty Status Flag(Read Only)
+ * | | |This bit indicates RX buffer empty or not.
+ * | | |When the last byte of Rx buffer has been read by CPU, hardware sets this bit high.
+ * | | |It will be cleared when SC receives any new data.
+ * |[2] |RXFULL |Receiver Buffer Full Status Flag (Read Only)
+ * | | |This bit indicates RX buffer full or not.
+ * | | |This bit is set when RX pointer is equal to 4, otherwise it is cleared by hardware.
+ * |[4] |PEF |Receiver Parity Error Status Flag (Read Only)
+ * | | |This bit is set to logic 1 whenever the received character does not have a valid
+ * | | |"parity bit".
+ * | | |Note1:
+ * | | |This bit is read only, but it can be cleared by writing 1 to it.
+ * | | |Note2:
+ * | | |If CPU sets receiver retries function by setting RXRTYEN(SC_CTL[19]) , hardware will not set this flag.
+ * |[5] |FEF |Receiver Frame Error Status Flag (Read Only)
+ * | | |This bit is set to logic 1 whenever the received character does not have a valid "stop bit" (that is, the stop bit following the last data bit or parity bit is detected as logic 0).
+ * | | |Note1:
+ * | | |This bit is read only, but it can be cleared by writing 1 to it.
+ * | | |Note2:
+ * | | |If CPU sets receiver retries function by setting RXRTYEN(SC_CTL[19]) , hardware will not set this flag.
+ * |[6] |BEF |Receiver Break Error Status Flag (Read Only)
+ * | | |This bit is set to logic 1 whenever the received data input (RX) held in the "spacing state" (logic 0) is longer than a full word transmission time (that is, the total time of "start bit" + data bits + parity + stop bits).
+ * | | |.
+ * | | |Note1:
+ * | | |This bit is read only, but it can be cleared by writing 1 to it.
+ * | | |Note2:
+ * | | |If CPU sets receiver retries function by setting RXRTYEN(SC_CTL[19]) , hardware will not set this flag.
+ * |[8] |TXOV |TX Overflow Error Interrupt Status Flag (Read Only)
+ * | | |If TX buffer is full, an additional write to DAT(SC_DAT[7:0]) will cause this bit be set to "1" by hardware.
+ * | | |Note: This bit is read only, but it can be cleared by writing 1 to it.
+ * |[9] |TXEMPTY |Transmit Buffer Empty Status Flag (Read Only)
+ * | | |This bit indicates TX buffer empty or not.
+ * | | |When the last byte of TX buffer has been transferred to Transmitter Shift Register, hardware sets this bit high.
+ * | | |It will be cleared when writing data into DAT(SC_DAT[7:0]) (TX buffer not empty).
+ * |[10] |TXFULL |Transmit Buffer Full Status Flag (Read Only)
+ * | | |This bit indicates TX buffer full or not.This bit is set when TX pointer is equal to 4, otherwise is cleared by hardware.
+ * |[11] |CREMOVE |Card Detect Removal Status Of SC_CD Pin (Read Only)
+ * | | |This bit is set whenever card has been removal.
+ * | | |0 = No effect.
+ * | | |1 = Card removed.
+ * | | |Note1: This bit is read only, but it can be cleared by writing "1" to it.
+ * | | |Note2: Card detect engine will start after SCEN (SC_CTL[0])set.
+ * |[12] |CINSERT |Card Detect Insert Status Of SC_CD Pin (Read Only)
+ * | | |This bit is set whenever card has been inserted.
+ * | | |0 = No effect.
+ * | | |1 = Card insert.
+ * | | |Note1: This bit is read only, but it can be cleared by writing "1" to it.
+ * | | |Note2: The
+ * | | |card detect engine will start after SCEN (SC_CTL[0]) set.
+ * |[13] |CDPINSTS |Card Detect Status Of SC_CD Pin Status (Read Only)
+ * | | |This bit is the pin status flag of SC_CD
+ * | | |0 = The SC_CD pin state at low.
+ * | | |1 = The SC_CD pin state at high.
+ * |[17:16] |RXPOINT |Receiver Buffer Pointer Status Flag (Read Only)
+ * | | |This field indicates the RX buffer pointer status flag.
+ * | | |When SC receives one byte from external device, RXPOINT(SC_STATUS[17:16]) increases one.
+ * | | |When one byte of RX buffer is read by CPU, RXPOINT(SC_STATUS[17:16]) decreases one.
+ * |[21] |RXRERR |Receiver Retry Error (Read Only)
+ * | | |This bit is set by hardware when RX has any error and retries transfer.
+ * | | |Note1: This bit is read only, but it can be cleared by writing 1 to it.
+ * | | |Note2 This bit is a flag and cannot generate any interrupt to CPU.
+ * | | |Note3: If CPU enables receiver retry function by setting RXRTYEN (SC_CTL[19]) , the PEF(SC_STATUS[4]) flag will be ignored (hardware will not set PEF(SC_STATUS[4])).
+ * |[22] |RXOVERR |Receiver Over Retry Error (Read Only)
+ * | | |This bit is set by hardware when RX transfer error retry over retry number limit.
+ * | | |Note1: This bit is read only, but it can be cleared by writing 1 to it.
+ * | | |Note2: If CPU enables receiver retries function by setting RXRTYEN (SC_CTL[19]), the PEF(SC_STATUS[4]) flag will be ignored (hardware will not set PEF(SC_STATUS[4])).
+ * |[23] |RXACT |Receiver In Active Status Flag (Read Only)
+ * | | |This bit is set by hardware when RX transfer is in active.
+ * | | |This bit is cleared automatically when RX transfer is finished.
+ * |[25:24] |TXPOINT |Transmit Buffer Pointer Status Flag (Read Only)
+ * | | |This field indicates the TX buffer pointer status flag.
+ * | | |When CPU writes data into SC_DAT, TXPOINT increases one.
+ * | | |When one byte of TX Buffer is transferred to transmitter shift register, TXPOINT decreases one.
+ * |[29] |TXRERR |Transmitter Retry Error (Read Only)
+ * | | |This bit is set by hardware when transmitter re-transmits.
+ * | | |Note1: This bit is read only, but it can be cleared by writing 1 to it.
+ * | | |Note2 This bit is a flag and cannot generate any interrupt to CPU.
+ * |[30] |TXOVERR |Transmitter Over Retry Error (Read Only)
+ * | | |This bit is set by hardware when transmitter re-transmits over retry number limitation.
+ * | | |Note: This bit is read only, but it can be cleared by writing 1 to it.
+ * |[31] |TXACT |Transmit In Active Status Flag (Read Only)
+ * | | |0 = This bit is cleared automatically when TX transfer is finished or the last byte transmission has completed.
+ * | | |1 = This bit is set by hardware when TX transfer is in active and the STOP bit of the last byte has been transmitted.
+ * @var SC_T::PINCTL
+ * Offset: 0x24 SC Pin Control State Register.
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |PWREN |SC_PWREN Pin Signal
+ * | | |Software can set PWREN (SC_PINCTL[0]) and PWRINV (SC_PINCTL[11])to decide SC_PWR pin is in high or low level.
+ * | | |Write this field to drive SC_PWR pin
+ * | | |Refer PWRINV (SC_PINCTL[11]) description for programming SC_PWR pin voltage level.
+ * | | |Read this field to get SC_PWR pin status.
+ * | | |0 = SC_PWR pin status is low.
+ * | | |1 = SC_PWR pin status is high.
+ * | | |Note: When operating at activation, warm reset or deactivation mode, this bit will be changed automatically.
+ * | | |So don't fill this field when operating in these modes.
+ * |[1] |SCRST |SC_RST Pin Signal
+ * | | |This bit is the pin status of SC_RST but user can drive SC_RST pin to high or low by setting this bit.
+ * | | |Write this field to drive SC_RST pin.
+ * | | |0 = Drive SC_RST pin to low.
+ * | | |1 = Drive SC_RST pin to high.
+ * | | |Read this field to get SC_RST pin status.
+ * | | |0 = SC_RST pin status is low.
+ * | | |1 = SC_RST pin status is high.
+ * | | |Note: When operating at activation, warm reset or deactivation mode, this bit will be changed automatically.
+ * | | |So don't fill this field when operating in these modes.
+ * |[5] |CSTOPLV |SC Clock Stop Level
+ * | | |This field indicates the clock polarity control in clock stop mode.
+ * | | |0 = SC_CLK stopped in low level.
+ * | | |1 = SC_CLK stopped in high level.
+ * |[6] |CLKKEEP |SC Clock Enable Bit
+ * | | |0 = SC clock generation Disabled.
+ * | | |1 = SC clock always keeps free running.
+ * | | |Note: When operating in activation, warm reset or deactivation mode, this bit will be changed automatically.
+ * | | |So don't fill this field when operating in these modes.
+ * |[9] |SCDOUT |SC Data Output Pin
+ * | | |This bit is the pin status of SCDATOUT but user can drive SCDATOUT pin to high or low by setting this bit.
+ * | | |0 = Drive SCDATOUT pin to low.
+ * | | |1 = Drive SCDATOUT pin to high.
+ * | | |Note: When SC is at activation, warm reset or deactivation mode, this bit will be changed automatically.
+ * | | |So don't fill this field when SC is in these modes.
+ * |[11] |PWRINV |SC_POW Pin Inverse
+ * | | |This bit is used for inverse the SC_POW pin.
+ * | | |There are four kinds of combination for SC_POW pin setting by PWRINV(SC_PINCTL[11]) and PWREN(SC_PINCTL[0]).
+ * | | |PWRINV (SC_PINCTL[11]) is bit 1 and PWREN(SC_PINCTL[0]) is bit 0 for SC_POW_Pin as high or low voltage selection.
+ * | | |00 = SC_POW_ Pin is 0.
+ * | | |01 = SC_POW _Pin is 1.
+ * | | |10 = SC_POW _Pin is 1.
+ * | | |11 = SC_POW_ Pin is 0.
+ * | | |Note: Software must select PWRINV (SC_PINCTL[11]) before Smart Card is enabled by SCEN (SC_CTL[0]).
+ * |[12] |SCDOSTS |SC Data Pin Output Status
+ * | | |This bit is the pin status of SCDATOUT
+ * | | |0 = SCDATOUT pin to low.
+ * | | |1 = SCDATOUT pin to high.
+ * | | |Note: When SC is operated at activation, warm reset or deactivation mode, this bit will be changed automatically.
+ * | | |This bit is not allowed to program when SC is operated at these modes.
+ * |[16] |DATSTS |This bit is the pin status of SC_DAT
+ * | | |0 = The SC_DAT pin is low.
+ * | | |1 = The SC_DAT pin is high.
+ * |[17] |PWRSTS |SC_PWR Pin Signal
+ * | | |This bit is the pin status of SC_PWR
+ * | | |0 = SC_PWR pin to low.
+ * | | |1 = SC_PWR pin to high.
+ * | | |Note: When SC is operated at activation, warm reset or deactivation mode, this bit will be changed automatically.
+ * | | |This bit is not allowed to program when SC is operated at these modes.
+ * |[18] |RSTSTS |SCRST Pin Signals
+ * | | |This bit is the pin status of SC_RST
+ * | | |0 = SC_RST pin is low.
+ * | | |1 = SC_RST pin is high.
+ * | | |Note: When SC is operated at activation, warm reset or deactivation mode, this bit will be changed automatically.
+ * | | |This bit is not allowed to program when SC is operated at these modes.
+ * |[30] |SYNC |SYNC Flag Indicator
+ * | | |Due to synchronization, software should check this bit when writing a new value to SC_PINCTL register.
+ * | | |0 = Synchronizing is completion, user can write new data to SC_PINCTL register.
+ * | | |1 = Last value is synchronizing.
+ * | | |Note: This bit is read only.
+ * |[31] |LOOPBK |Loop Back Test
+ * | | |0 = loop back test Disabled.
+ * | | |1 = Enabling loop back test and the internal SCDATOUT will connect to internal SC_DATA_I.
+ * @var SC_T::TMRCTL0
+ * Offset: 0x28 SC Internal Timer Control Register 0.
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[23:0] |CNT |Timer 0 Counter Value (ETU Base)
+ * | | |This field indicates the internal timer operation values.
+ * |[27:24] |OPMODE |Timer 0 Operation Mode Selection
+ * | | |This field indicates the internal 24-bit timer operation selection.
+ * | | |Refer to 6.17.5.4 for programming Timer0
+ * @var SC_T::TMRCTL1
+ * Offset: 0x2C SC Internal Timer Control Register 1.
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:0] |CNT |Timer 1 Counter Value (ETU Base)
+ * | | |This field indicates the internal timer operation values.
+ * |[27:24] |OPMODE |Timer 1 Operation Mode Selection
+ * | | |This field indicates the internal 8-bit timer operation selection.
+ * | | |Refer to 6.17.5.4 for programming Timer1
+ * @var SC_T::TMRCTL2
+ * Offset: 0x30 SC Internal Timer Control Register 2.
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:0] |CNT |Timer 2 Counter Value (ETU Base)
+ * | | |This field indicates the internal timer operation values.
+ * |[27:24] |OPMODE |Timer 2 Operation Mode Selection
+ * | | |This field indicates the internal 8-bit timer operation selection
+ * | | |Refer to 6.17.5.4 for programming Timer2
+ * @var SC_T::UARTCTL
+ * Offset: 0x34 SC UART Mode Control Register.
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |UARTEN |UART Mode Enable Bit
+ * | | |0 = Smart Card mode.
+ * | | |1 = UART mode.
+ * | | |Note1: When operating in UART mode, user must set CONSEL (SC_CTL[5:4]) = 00 and AUTOCEN(SC_CTL[3]) = 0.
+ * | | |Note2: When operating in Smart Card mode, user must set UARTEN(SC_UARTCTL [0]) = 00.
+ * | | |Note3: When UART is enabled, hardware will generate a reset to reset FIFO and internal state machine.
+ * |[5:4] |WLS10 |Word Length Selection
+ * | | |00 = Word length is 8 bits.
+ * | | |01 = Word length is 7 bits.
+ * | | |10 = Word length is 6 bits.
+ * | | |11 = Word length is 5 bits.
+ * | | |Note: In smart card mode, this WLS must be '00'
+ * |[6] |PBOFF |Parity Bit Disable Control
+ * | | |0 = Parity bit is generated or checked between the "last data word bit" and "stop bit" of the serial data.
+ * | | |1 = Parity bit is not generated (transmitting data) or checked (receiving data) during transfer.
+ * | | |Note: In smart card mode, this field must be '0' (default setting is with parity bit)
+ * |[7] |OPE |Odd Parity Enable Bit
+ * | | |0 = Even number of logic 1's are transmitted or check the data word and parity bits in receiving mode.
+ * | | |1 = Odd number of logic 1's are transmitted or check the data word and parity bits in receiving mode.
+ * | | |Note: This bit has effect only when PBOFF bit is '0'.
+ * @var SC_T::TMRDAT0
+ * Offset: 0x38 SC Timer Current Data Register A.
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[23:0] |CNT0 |Timer0 Current Data Value (Read Only)
+ * | | |This field indicates the current count values of timer0.
+ * @var SC_T::TMRDAT1_2
+ * Offset: 0x3C SC Timer Current Data Register B.
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:0] |CNT1 |Timer1 Current Data Value (Read Only)
+ * | | |This field indicates the current count values of timer1.
+ * |[15:8] |CNT2 |Timer2 Current Data Value (Read Only)
+ * | | |This field indicates the current count values of timer2.
+ */
+
+ __IO uint32_t DAT; /* Offset: 0x00 SC Receiving/Transmit Holding Buffer Register. */
+ __IO uint32_t CTL; /* Offset: 0x04 SC Control Register. */
+ __IO uint32_t ALTCTL; /* Offset: 0x08 SC Alternate Control Register. */
+ __IO uint32_t EGT; /* Offset: 0x0C SC Extend Guard Time Register. */
+ __IO uint32_t RXTOUT; /* Offset: 0x10 SC Receive buffer Time-out Register. */
+ __IO uint32_t ETUCTL; /* Offset: 0x14 SC ETU Control Register. */
+ __IO uint32_t INTEN; /* Offset: 0x18 SC Interrupt Enable Control Register. */
+ __IO uint32_t INTSTS; /* Offset: 0x1C SC Interrupt Status Register. */
+ __IO uint32_t STATUS; /* Offset: 0x20 SC Status Register. */
+ __IO uint32_t PINCTL; /* Offset: 0x24 SC Pin Control State Register. */
+ __IO uint32_t TMRCTL0; /* Offset: 0x28 SC Internal Timer Control Register 0. */
+ __IO uint32_t TMRCTL1; /* Offset: 0x2C SC Internal Timer Control Register 1. */
+ __IO uint32_t TMRCTL2; /* Offset: 0x30 SC Internal Timer Control Register 2. */
+ __IO uint32_t UARTCTL; /* Offset: 0x34 SC UART Mode Control Register. */
+ __I uint32_t TMRDAT0; /* Offset: 0x38 SC Timer Current Data Register A. */
+ __I uint32_t TMRDAT1_2; /* Offset: 0x3C SC Timer Current Data Register B. */
+
+} SC_T;
+
+
+
+/**
+ @addtogroup SC_CONST SC Bit Field Definition
+ Constant Definitions for SC Controller
+@{ */
+
+#define SC_DAT_DAT_Pos (0) /*!< SC_T::DAT: DAT Position */
+#define SC_DAT_DAT_Msk (0xfful << SC_DAT_DAT_Pos) /*!< SC_T::DAT: DAT Mask */
+
+#define SC_CTL_SCEN_Pos (0) /*!< SC_T::CTL: SCEN Position */
+#define SC_CTL_SCEN_Msk (0x1ul << SC_CTL_SCEN_Pos) /*!< SC_T::CTL: SCEN Mask */
+
+#define SC_CTL_RXOFF_Pos (1) /*!< SC_T::CTL: RXOFF Position */
+#define SC_CTL_RXOFF_Msk (0x1ul << SC_CTL_RXOFF_Pos) /*!< SC_T::CTL: RXOFF Mask */
+
+#define SC_CTL_TXOFF_Pos (2) /*!< SC_T::CTL: TXOFF Position */
+#define SC_CTL_TXOFF_Msk (0x1ul << SC_CTL_TXOFF_Pos) /*!< SC_T::CTL: TXOFF Mask */
+
+#define SC_CTL_AUTOCEN_Pos (3) /*!< SC_T::CTL: AUTOCEN Position */
+#define SC_CTL_AUTOCEN_Msk (0x1ul << SC_CTL_AUTOCEN_Pos) /*!< SC_T::CTL: AUTOCEN Mask */
+
+#define SC_CTL_CONSEL_Pos (4) /*!< SC_T::CTL: CONSEL Position */
+#define SC_CTL_CONSEL_Msk (0x3ul << SC_CTL_CONSEL_Pos) /*!< SC_T::CTL: CONSEL Mask */
+
+#define SC_CTL_RXTRGLV_Pos (6) /*!< SC_T::CTL: RXTRGLV Position */
+#define SC_CTL_RXTRGLV_Msk (0x3ul << SC_CTL_RXTRGLV_Pos) /*!< SC_T::CTL: RXTRGLV Mask */
+
+#define SC_CTL_BGT_Pos (8) /*!< SC_T::CTL: BGT Position */
+#define SC_CTL_BGT_Msk (0x1ful << SC_CTL_BGT_Pos) /*!< SC_T::CTL: BGT Mask */
+
+#define SC_CTL_TMRSEL_Pos (13) /*!< SC_T::CTL: TMRSEL Position */
+#define SC_CTL_TMRSEL_Msk (0x3ul << SC_CTL_TMRSEL_Pos) /*!< SC_T::CTL: TMRSEL Mask */
+
+#define SC_CTL_NSB_Pos (15) /*!< SC_T::CTL: NSB Position */
+#define SC_CTL_NSB_Msk (0x1ul << SC_CTL_NSB_Pos) /*!< SC_T::CTL: NSB Mask */
+
+#define SC_CTL_RXRTY_Pos (16) /*!< SC_T::CTL: RXRTY Position */
+#define SC_CTL_RXRTY_Msk (0x7ul << SC_CTL_RXRTY_Pos) /*!< SC_T::CTL: RXRTY Mask */
+
+#define SC_CTL_RXRTYEN_Pos (19) /*!< SC_T::CTL: RXRTYEN Position */
+#define SC_CTL_RXRTYEN_Msk (0x1ul << SC_CTL_RXRTYEN_Pos) /*!< SC_T::CTL: RXRTYEN Mask */
+
+#define SC_CTL_TXRTY_Pos (20) /*!< SC_T::CTL: TXRTY Position */
+#define SC_CTL_TXRTY_Msk (0x7ul << SC_CTL_TXRTY_Pos) /*!< SC_T::CTL: TXRTY Mask */
+
+#define SC_CTL_TXRTYEN_Pos (23) /*!< SC_T::CTL: TXRTYEN Position */
+#define SC_CTL_TXRTYEN_Msk (0x1ul << SC_CTL_TXRTYEN_Pos) /*!< SC_T::CTL: TXRTYEN Mask */
+
+#define SC_CTL_CDDBSEL_Pos (24) /*!< SC_T::CTL: CDDBSEL Position */
+#define SC_CTL_CDDBSEL_Msk (0x3ul << SC_CTL_CDDBSEL_Pos) /*!< SC_T::CTL: CDDBSEL Mask */
+
+#define SC_CTL_CDLV_Pos (26) /*!< SC_T::CTL: CDLV Position */
+#define SC_CTL_CDLV_Msk (0x1ul << SC_CTL_CDLV_Pos) /*!< SC_T::CTL: CDLV Mask */
+
+#define SC_CTL_SYNC_Pos (30) /*!< SC_T::CTL: SYNC Position */
+#define SC_CTL_SYNC_Msk (0x1ul << SC_CTL_SYNC_Pos) /*!< SC_T::CTL: SYNC Mask */
+
+#define SC_CTL_ICEDEBUG_Pos (31) /*!< SC_T::CTL: ICEDEBUG Position */
+#define SC_CTL_ICEDEBUG_Msk (0x1ul << SC_CTL_ICEDEBUG_Pos) /*!< SC_T::CTL: ICEDEBUG Mask */
+
+#define SC_ALTCTL_TXRST_Pos (0) /*!< SC_T::ALTCTL: TXRST Position */
+#define SC_ALTCTL_TXRST_Msk (0x1ul << SC_ALTCTL_TXRST_Pos) /*!< SC_T::ALTCTL: TXRST Mask */
+
+#define SC_ALTCTL_RXRST_Pos (1) /*!< SC_T::ALTCTL: RXRST Position */
+#define SC_ALTCTL_RXRST_Msk (0x1ul << SC_ALTCTL_RXRST_Pos) /*!< SC_T::ALTCTL: RXRST Mask */
+
+#define SC_ALTCTL_DACTEN_Pos (2) /*!< SC_T::ALTCTL: DACTEN Position */
+#define SC_ALTCTL_DACTEN_Msk (0x1ul << SC_ALTCTL_DACTEN_Pos) /*!< SC_T::ALTCTL: DACTEN Mask */
+
+#define SC_ALTCTL_ACTEN_Pos (3) /*!< SC_T::ALTCTL: ACTEN Position */
+#define SC_ALTCTL_ACTEN_Msk (0x1ul << SC_ALTCTL_ACTEN_Pos) /*!< SC_T::ALTCTL: ACTEN Mask */
+
+#define SC_ALTCTL_WARSTEN_Pos (4) /*!< SC_T::ALTCTL: WARSTEN Position */
+#define SC_ALTCTL_WARSTEN_Msk (0x1ul << SC_ALTCTL_WARSTEN_Pos) /*!< SC_T::ALTCTL: WARSTEN Mask */
+
+#define SC_ALTCTL_CNTEN0_Pos (5) /*!< SC_T::ALTCTL: CNTEN0 Position */
+#define SC_ALTCTL_CNTEN0_Msk (0x1ul << SC_ALTCTL_CNTEN0_Pos) /*!< SC_T::ALTCTL: CNTEN0 Mask */
+
+#define SC_ALTCTL_CNTEN1_Pos (6) /*!< SC_T::ALTCTL: CNTEN1 Position */
+#define SC_ALTCTL_CNTEN1_Msk (0x1ul << SC_ALTCTL_CNTEN1_Pos) /*!< SC_T::ALTCTL: CNTEN1 Mask */
+
+#define SC_ALTCTL_CNTEN2_Pos (7) /*!< SC_T::ALTCTL: CNTEN2 Position */
+#define SC_ALTCTL_CNTEN2_Msk (0x1ul << SC_ALTCTL_CNTEN2_Pos) /*!< SC_T::ALTCTL: CNTEN2 Mask */
+
+#define SC_ALTCTL_INITSEL_Pos (8) /*!< SC_T::ALTCTL: INITSEL Position */
+#define SC_ALTCTL_INITSEL_Msk (0x3ul << SC_ALTCTL_INITSEL_Pos) /*!< SC_T::ALTCTL: INITSEL Mask */
+
+#define SC_ALTCTL_ADACEN_Pos (11) /*!< SC_T::ALTCTL: ADACEN Position */
+#define SC_ALTCTL_ADACEN_Msk (0x1ul << SC_ALTCTL_ADACEN_Pos) /*!< SC_T::ALTCTL: ADACEN Mask */
+
+#define SC_ALTCTL_RXBGTEN_Pos (12) /*!< SC_T::ALTCTL: RXBGTEN Position */
+#define SC_ALTCTL_RXBGTEN_Msk (0x1ul << SC_ALTCTL_RXBGTEN_Pos) /*!< SC_T::ALTCTL: RXBGTEN Mask */
+
+#define SC_ALTCTL_ACTSTS0_Pos (13) /*!< SC_T::ALTCTL: ACTSTS0 Position */
+#define SC_ALTCTL_ACTSTS0_Msk (0x1ul << SC_ALTCTL_ACTSTS0_Pos) /*!< SC_T::ALTCTL: ACTSTS0 Mask */
+
+#define SC_ALTCTL_ACTSTS1_Pos (14) /*!< SC_T::ALTCTL: ACTSTS1 Position */
+#define SC_ALTCTL_ACTSTS1_Msk (0x1ul << SC_ALTCTL_ACTSTS1_Pos) /*!< SC_T::ALTCTL: ACTSTS1 Mask */
+
+#define SC_ALTCTL_ACTSTS2_Pos (15) /*!< SC_T::ALTCTL: ACTSTS2 Position */
+#define SC_ALTCTL_ACTSTS2_Msk (0x1ul << SC_ALTCTL_ACTSTS2_Pos) /*!< SC_T::ALTCTL: ACTSTS2 Mask */
+
+#define SC_ALTCTL_OUTSEL_Pos (16) /*!< SC_T::ALTCTL: OUTSEL Position */
+#define SC_ALTCTL_OUTSEL_Msk (0x1ul << SC_ALTCTL_OUTSEL_Pos) /*!< SC_T::ALTCTL: OUTSEL Mask */
+
+#define SC_EGT_EGT_Pos (0) /*!< SC_T::EGT: EGT Position */
+#define SC_EGT_EGT_Msk (0xfful << SC_EGT_EGT_Pos) /*!< SC_T::EGT: EGT Mask */
+
+#define SC_RXTOUT_RFTM_Pos (0) /*!< SC_T::RXTOUT: RFTM Position */
+#define SC_RXTOUT_RFTM_Msk (0x1fful << SC_RXTOUT_RFTM_Pos) /*!< SC_T::RXTOUT: RFTM Mask */
+
+#define SC_ETUCTL_ETURDIV_Pos (0) /*!< SC_T::ETUCTL: ETURDIV_ Position */
+#define SC_ETUCTL_ETURDIV_Msk (0xffful << SC_ETUCTL_ETURDIV_Pos) /*!< SC_T::ETUCTL: ETURDIV_ Mask */
+
+#define SC_ETUCTL_CMPEN_Pos (15) /*!< SC_T::ETUCTL: CMPEN_ Position */
+#define SC_ETUCTL_CMPEN_Msk (0x1ul << SC_ETUCTL_CMPEN_Pos) /*!< SC_T::ETUCTL: CMPEN_ Mask */
+
+#define SC_INTEN_RDAIEN_Pos (0) /*!< SC_T::INTEN: RDAIEN Position */
+#define SC_INTEN_RDAIEN_Msk (0x1ul << SC_INTEN_RDAIEN_Pos) /*!< SC_T::INTEN: RDAIEN Mask */
+
+#define SC_INTEN_TBEIEN_Pos (1) /*!< SC_T::INTEN: TBEIEN Position */
+#define SC_INTEN_TBEIEN_Msk (0x1ul << SC_INTEN_TBEIEN_Pos) /*!< SC_T::INTEN: TBEIEN Mask */
+
+#define SC_INTEN_TERRIEN_Pos (2) /*!< SC_T::INTEN: TERRIEN Position */
+#define SC_INTEN_TERRIEN_Msk (0x1ul << SC_INTEN_TERRIEN_Pos) /*!< SC_T::INTEN: TERRIEN Mask */
+
+#define SC_INTEN_TMR0IEN_Pos (3) /*!< SC_T::INTEN: TMR0IEN_Position */
+#define SC_INTEN_TMR0IEN_Msk (0x1ul << SC_INTEN_TMR0IEN_Pos) /*!< SC_T::INTEN: TMR0IEN Mask */
+
+#define SC_INTEN_TMR1IEN_Pos (4) /*!< SC_T::INTEN: TMR1IEN Position */
+#define SC_INTEN_TMR1IEN_Msk (0x1ul << SC_INTEN_TMR1IEN_Pos) /*!< SC_T::INTEN: TMR1IEN Mask */
+
+#define SC_INTEN_TMR2IEN_Pos (5) /*!< SC_T::INTEN: TMR2IEN Position */
+#define SC_INTEN_TMR2IEN_Msk (0x1ul << SC_INTEN_TMR2IEN_Pos) /*!< SC_T::INTEN: TMR2IEN Mask */
+
+#define SC_INTEN_BGTIEN_Pos (6) /*!< SC_T::INTEN: BGTIEN Position */
+#define SC_INTEN_BGTIEN_Msk (0x1ul << SC_INTEN_BGTIEN_Pos) /*!< SC_T::INTEN: BGTIEN Mask */
+
+#define SC_INTEN_CDIEN_Pos (7) /*!< SC_T::INTEN: CDIEN Position */
+#define SC_INTEN_CDIEN_Msk (0x1ul << SC_INTEN_CDIEN_Pos) /*!< SC_T::INTEN: CDIEN Mask */
+
+#define SC_INTEN_INITIEN_Pos (8) /*!< SC_T::INTEN: INITIEN Position */
+#define SC_INTEN_INITIEN_Msk (0x1ul << SC_INTEN_INITIEN_Pos) /*!< SC_T::INTEN: INITIEN Mask */
+
+#define SC_INTEN_RXTOIF_Pos (9) /*!< SC_T::INTEN: RXTOIF Position */
+#define SC_INTEN_RXTOIF_Msk (0x1ul << SC_INTEN_RXTOIF_Pos) /*!< SC_T::INTEN: RXTOIF Mask */
+
+#define SC_INTEN_ACERRIEN_Pos (10) /*!< SC_T::INTEN: ACERRIEN Position */
+#define SC_INTEN_ACERRIEN_Msk (0x1ul << SC_INTEN_ACERRIEN_Pos) /*!< SC_T::INTEN: ACERRIEN Mask */
+
+#define SC_INTSTS_RDAIF_Pos (0) /*!< SC_T::INTSTS: RDAIF Position */
+#define SC_INTSTS_RDAIF_Msk (0x1ul << SC_INTSTS_RDAIF_Pos) /*!< SC_T::INTSTS: RDAIF Mask */
+
+#define SC_INTSTS_TBEIF_Pos (1) /*!< SC_T::INTSTS: TBEIF Position */
+#define SC_INTSTS_TBEIF_Msk (0x1ul << SC_INTSTS_TBEIF_Pos) /*!< SC_T::INTSTS: TBEIF Mask */
+
+#define SC_INTSTS_TERRIF_Pos (2) /*!< SC_T::INTSTS: TERRIF Position */
+#define SC_INTSTS_TERRIF_Msk (0x1ul << SC_INTSTS_TERRIF_Pos) /*!< SC_T::INTSTS: TERRIF Mask */
+
+#define SC_INTSTS_TMR0IF_Pos (3) /*!< SC_T::INTSTS: TMR0IF Position */
+#define SC_INTSTS_TMR0IF_Msk (0x1ul << SC_INTSTS_TMR0IF_Pos) /*!< SC_T::INTSTS: TMR0IF Mask */
+
+#define SC_INTSTS_TMR1IF_Pos (4) /*!< SC_T::INTSTS: TMR1IF Position */
+#define SC_INTSTS_TMR1IF_Msk (0x1ul << SC_INTSTS_TMR1IF_Pos) /*!< SC_T::INTSTS: TMR1IF Mask */
+
+#define SC_INTSTS_TMR2IF_Pos (5) /*!< SC_T::INTSTS: TMR2IF Position */
+#define SC_INTSTS_TMR2IF_Msk (0x1ul << SC_INTSTS_TMR2IF_Pos) /*!< SC_T::INTSTS: TMR2IF Mask */
+
+#define SC_INTSTS_BGTIF_Pos (6) /*!< SC_T::INTSTS: BGTIF Position */
+#define SC_INTSTS_BGTIF_Msk (0x1ul << SC_INTSTS_BGTIF_Pos) /*!< SC_T::INTSTS: BGTIF Mask */
+
+#define SC_INTSTS_CDIF_Pos (7) /*!< SC_T::INTSTS: CDIF Position */
+#define SC_INTSTS_CDIF_Msk (0x1ul << SC_INTSTS_CDIF_Pos) /*!< SC_T::INTSTS: CDIF Mask */
+
+#define SC_INTSTS_INITIF_Pos (8) /*!< SC_T::INTSTS: INITIF Position */
+#define SC_INTSTS_INITIF_Msk (0x1ul << SC_INTSTS_INITIF_Pos) /*!< SC_T::INTSTS: INITIF Mask */
+
+#define SC_INTSTS_RBTOIF_Pos (9) /*!< SC_T::INTSTS: RBTOIF Position */
+#define SC_INTSTS_RBTOIF_Msk (0x1ul << SC_INTSTS_RBTOIF_Pos) /*!< SC_T::INTSTS: RBTOIF Mask */
+
+#define SC_INTSTS_ACERRIF_Pos (10) /*!< SC_T::INTSTS: ACERRIF Position */
+#define SC_INTSTS_ACERRIF_Msk (0x1ul << SC_INTSTS_ACERRIF_Pos) /*!< SC_T::INTSTS: ACERRIF Mask */
+
+#define SC_STATUS_RXOV_Pos (0) /*!< SC_T::STATUS: RXO Position */
+#define SC_STATUS_RXOV_Msk (0x1ul << SC_STATUS_RXOV_Pos) /*!< SC_T::STATUS: RXO Mask */
+
+#define SC_STATUS_RXEMPTY_Pos (1) /*!< SC_T::STATUS: RXEMPTY Position */
+#define SC_STATUS_RXEMPTY_Msk (0x1ul << SC_STATUS_RXEMPTY_Pos) /*!< SC_T::STATUS: RXEMPTY Mask */
+
+#define SC_STATUS_RXFULL_Pos (2) /*!< SC_T::STATUS: RXFULL Position */
+#define SC_STATUS_RXFULL_Msk (0x1ul << SC_STATUS_RXFULL_Pos) /*!< SC_T::STATUS: RXFULL Mask */
+
+#define SC_STATUS_PEF_Pos (4) /*!< SC_T::STATUS: PEF Position */
+#define SC_STATUS_PEF_Msk (0x1ul << SC_STATUS_PEF_Pos) /*!< SC_T::STATUS: PEF Mask */
+
+#define SC_STATUS_FEF_Pos (5) /*!< SC_T::STATUS: FEF Position */
+#define SC_STATUS_FEF_Msk (0x1ul << SC_STATUS_FEF_Pos) /*!< SC_T::STATUS: FEF Mask */
+
+#define SC_STATUS_BEF_Pos (6) /*!< SC_T::STATUS: BEF Position */
+#define SC_STATUS_BEF_Msk (0x1ul << SC_STATUS_BEF_Pos) /*!< SC_T::STATUS: BEF Mask */
+
+#define SC_STATUS_TXOV_Pos (8) /*!< SC_T::STATUS: TXOV Position */
+#define SC_STATUS_TXOV_Msk (0x1ul << SC_STATUS_TXOV_Pos) /*!< SC_T::STATUS: TXOV Mask */
+
+#define SC_STATUS_TXEMPTY_Pos (9) /*!< SC_T::STATUS: TXEMPTY Position */
+#define SC_STATUS_TXEMPTY_Msk (0x1ul << SC_STATUS_TXEMPTY_Pos) /*!< SC_T::STATUS: TXEMPTY Mask */
+
+#define SC_STATUS_TXFULL_Pos (10) /*!< SC_T::STATUS: TXFULL Position */
+#define SC_STATUS_TXFULL_Msk (0x1ul << SC_STATUS_TXFULL_Pos) /*!< SC_T::STATUS: TXFULL Mask */
+
+#define SC_STATUS_CREMOVE_Pos (11) /*!< SC_T::STATUS: CREMOVE Position */
+#define SC_STATUS_CREMOVE_Msk (0x1ul << SC_STATUS_CREMOVE_Pos) /*!< SC_T::STATUS: CREMOVE Mask */
+
+#define SC_STATUS_CINSERT_Pos (12) /*!< SC_T::STATUS: CINSERT Position */
+#define SC_STATUS_CINSERT_Msk (0x1ul << SC_STATUS_CINSERT_Pos) /*!< SC_T::STATUS: CINSERT Mask */
+
+#define SC_STATUS_CDPINSTS_Pos (13) /*!< SC_T::STATUS: CDPINSTS Position */
+#define SC_STATUS_CDPINSTS_Msk (0x1ul << SC_STATUS_CDPINSTS_Pos) /*!< SC_T::STATUS: CDPINSTS Mask */
+
+#define SC_STATUS_RXPOINT_Pos (16) /*!< SC_T::STATUS: RXPOINT Position */
+#define SC_STATUS_RXPOINT_Msk (0x3ul << SC_STATUS_RXPOINT_Pos) /*!< SC_T::STATUS: RXPOINT Mask */
+
+#define SC_STATUS_RXRERR_Pos (21) /*!< SC_T::STATUS: RXRERR Position */
+#define SC_STATUS_RXRERR_Msk (0x1ul << SC_STATUS_RXRERR_Pos) /*!< SC_T::STATUS: RXRERR Mask */
+
+#define SC_STATUS_RXOVERR_Pos (22) /*!< SC_T::STATUS: RXOVERR Position */
+#define SC_STATUS_RXOVERR_Msk (0x1ul << SC_STATUS_RXOVERR_Pos) /*!< SC_T::STATUS: RXOVERR Mask */
+
+#define SC_STATUS_RXACT_Pos (23) /*!< SC_T::STATUS: RXACT Position */
+#define SC_STATUS_RXACT_Msk (0x1ul << SC_STATUS_RXACT_Pos) /*!< SC_T::STATUS: RXACT Msk */
+
+#define SC_STATUS_TXPOINT_Pos (24) /*!< SC_T::STATUS: TXPOINT Position */
+#define SC_STATUS_TXPOINT_Msk (0x3ul << SC_STATUS_TXPOINT_Pos) /*!< SC_T::STATUS: TXPOINT Msk */
+
+#define SC_STATUS_TXRERR_Pos (29) /*!< SC_T::STATUS: TXRERR Position */
+#define SC_STATUS_TXRERR_Msk (0x1ul << SC_STATUS_TXRERR_Pos) /*!< SC_T::STATUS: TXRERR Msk */
+
+#define SC_STATUS_TXOVERR_Pos (30) /*!< SC_T::STATUS: TXOVERR_ Position */
+#define SC_STATUS_TXOVERR_Msk (0x1ul << SC_STATUS_TXOVERR_Pos) /*!< SC_T::STATUS: TXOVERR_ Msk */
+
+#define SC_STATUS_TXACT_Pos (31) /*!< SC_T::STATUS: TXACT Position */
+#define SC_STATUS_TXACT_Msk (0x1ul << SC_STATUS_TXACT_Pos) /*!< SC_T::STATUS: TXACT Msk */
+
+#define SC_PINCTL_PWREN_Pos (0) /*!< SC_T::PINCTL: PWREN Position */
+#define SC_PINCTL_PWREN_Msk (0x1ul << SC_PINCTL_PWREN_Pos) /*!< SC_T::PINCTL: PWREN Msk */
+
+#define SC_PINCTL_SCRST_Pos (1) /*!< SC_T::PINCTL: SCRST Position */
+#define SC_PINCTL_SCRST_Msk (0x1ul << SC_PINCTL_SCRST_Pos) /*!< SC_T::PINCTL: SCRST Msk */
+
+#define SC_PINCTL_CSTOPLV_Pos (5) /*!< SC_T::PINCTL: CSTOPLV Position */
+#define SC_PINCTL_CSTOPLV_Msk (0x1ul << SC_PINCTL_CSTOPLV_Pos) /*!< SC_T::PINCTL: CSTOPLV Msk */
+
+#define SC_PINCTL_CLKKEEP_Pos (6) /*!< SC_T::PINCTL: CLKKEEP Position */
+#define SC_PINCTL_CLKKEEP_Msk (0x1ul << SC_PINCTL_CLKKEEP_Pos) /*!< SC_T::PINCTL: CLKKEEP Msk */
+
+#define SC_PINCTL_SCDOUT_Pos (9) /*!< SC_T::PINCTL: SCDOUT Position */
+#define SC_PINCTL_SCDOUT_Msk (0x1ul << SC_PINCTL_SCDOUT_Pos) /*!< SC_T::PINCTL: SCDOUT Msk */
+
+#define SC_PINCTL_PWRINV_Pos (11) /*!< SC_T::PINCTL: PWRINV Position */
+#define SC_PINCTL_PWRINV_Msk (0x1ul << SC_PINCTL_PWRINV_Pos) /*!< SC_T::PINCTL: PWRINV Msk */
+
+#define SC_PINCTL_SCDOSTS_Pos (12) /*!< SC_T::PINCTL: SCDOSTS Position */
+#define SC_PINCTL_SCDOSTS_Msk (0x1ul << SC_PINCTL_SCDOSTS_Pos) /*!< SC_T::PINCTL: SCDOSTS Msk */
+
+#define SC_PINCTL_DATSTS_Pos (16) /*!< SC_T::PINCTL: DATSTS Position */
+#define SC_PINCTL_DATSTS_Msk (0x1ul << SC_PINCTL_DATSTS_Pos) /*!< SC_T::PINCTL: DATSTS Msk */
+
+#define SC_PINCTL_PWRSTS_Pos (17) /*!< SC_T::PINCTL: PWRSTS Position */
+#define SC_PINCTL_PWRSTS_Msk (0x1ul << SC_PINCTL_PWRSTS_Pos) /*!< SC_T::PINCTL: PWRSTS Msk */
+
+#define SC_PINCTL_RSTSTS_Pos (18) /*!< SC_T::PINCTL: RSTSTS Position */
+#define SC_PINCTL_RSTSTS_Msk (0x1ul << SC_PINCTL_RSTSTS_Pos) /*!< SC_T::PINCTL: RSTSTS Msk */
+
+#define SC_PINCTL_SYNC_Pos (30) /*!< SC_T::PINCTL: SYNC Position */
+#define SC_PINCTL_SYNC_Msk (0x1ul << SC_PINCTL_SYNC_Pos) /*!< SC_T::PINCTL: SYNC Msk */
+
+#define SC_PINCTL_LOOPBK_Pos (31) /*!< SC_T::PINCTL: LOOPBK Position */
+#define SC_PINCTL_LOOPBK_Msk (0x1ul << SC_PINCTL_LOOPBK_Pos) /*!< SC_T::PINCTL: LOOPBK Msk */
+
+#define SC_TMRCTL0_CNT_Pos (0) /*!< SC_T::TMRCTL0: CNT Position */
+#define SC_TMRCTL0_CNT_Msk (0xfffffful << SC_TMRCTL0_CNT_Pos) /*!< SC_T::TMRCTL0: CNT Msk */
+
+#define SC_TMRCTL0_OPMODE_Pos (24) /*!< SC_T::TMRCTL0: OPMODE Position */
+#define SC_TMRCTL0_OPMODE_Msk (0xful << SC_TMRCTL0_OPMODE_Pos) /*!< SC_T::TMRCTL0: OPMODE Msk */
+
+#define SC_TMRCTL1_CNT_Pos (0) /*!< SC_T::TMRCTL1: CNT Position */
+#define SC_TMRCTL1_CNT_Msk (0xfful << SC_TMRCTL1_CNT_Pos) /*!< SC_T::TMRCTL1: CNT Msk */
+
+#define SC_TMRCTL1_OPMODE_Pos (24) /*!< SC_T::TMRCTL1: OPMODE Position */
+#define SC_TMRCTL1_OPMODE_Msk (0xful << SC_TMRCTL1_OPMODE_Pos) /*!< SC_T::TMRCTL1: OPMODE Msk */
+
+#define SC_TMRCTL2_CNT_Pos (0) /*!< SC_T::TMRCTL2: CNT Position */
+#define SC_TMRCTL2_CNT_Msk (0xfful << SC_TMRCTL2_CNT_Pos) /*!< SC_T::TMRCTL2: CNT Msk */
+
+#define SC_TMRCTL2_OPMODE_Pos (24) /*!< SC_T::TMRCTL2: OPMODE Position */
+#define SC_TMRCTL2_OPMODE_Msk (0xful << SC_TMRCTL2_OPMODE_Pos) /*!< SC_T::TMRCTL2: OPMODE Msk */
+
+#define SC_UARTCTL_UARTEN_Pos (0) /*!< SC_T::UARTCTL: UARTEN Position */
+#define SC_UARTCTL_UARTEN_Msk (0x1ul << SC_UARTCTL_UARTEN_Pos) /*!< SC_T::UARTCTL: UARTEN Msk */
+
+#define SC_UARTCTL_WLS_Pos (4) /*!< SC_T::UARTCTL: WLS Position */
+#define SC_UARTCTL_WLS_Msk (0x3ul << SC_UARTCTL_WLS10_Pos) /*!< SC_T::UARTCTL: WLS Msk */
+
+#define SC_UARTCTL_PBOFF_Pos (6) /*!< SC_T::UARTCTL: PBOFF Position */
+#define SC_UARTCTL_PBOFF_Msk (0x1ul << SC_UARTCTL_PBOFF_Pos) /*!< SC_T::UARTCTL: PBOFF Msk */
+
+#define SC_UARTCTL_OPE_Pos (7) /*!< SC_T::UARTCTL: OPE Position */
+#define SC_UARTCTL_OPE_Msk (0x1ul << SC_UARTCTL_OPE_Pos) /*!< SC_T::UARTCTL: OPE Msk */
+
+#define SC_TMRDAT0_CNT0_Pos (0) /*!< SC_T::TMRDAT0: CNT0 Position */
+#define SC_TMRDAT0_CNT0_Msk (0xfffffful << SC_TMRDAT0_CNT0_Pos) /*!< SC_T::TMRDAT0: CNT0 Msk */
+
+#define SC_TMRDAT1_2_CNT1_Pos (0) /*!< SC_T::TMRDAT1_2: CNT1 Position */
+#define SC_TMRDAT1_2_CNT1_Msk (0xfful << SC_TMRDAT1_2_CNT1_Pos) /*!< SC_T::TMRDAT1_2: CNT1 Msk */
+
+#define SC_TMRDAT1_2_CNT2_Pos (8) /*!< SC_T::TMRDAT1_2: CNT2 Position */
+#define SC_TMRDAT1_2_CNT2_Msk (0xfful << SC_TMRDAT1_2_CNT2_Pos) /*!< SC_T::TMRDAT1_2: CNT2 Msk */
+
+/**@}*/ /* SC_CONST */
+/**@}*/ /* end of SC register group */
+
+
+/*---------------------- Serial Peripheral Interface Controller -------------------------*/
+/**
+ @addtogroup SPI Serial Peripheral Interface Controller(SPI)
+ Memory Mapped Structure for SPI Controller
+@{ */
+
+
+typedef struct
+{
+
+
+/**
+ * @var SPI_T::CTL
+ * Offset: 0x00 Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |SPIEN |SPI Transfer Control Enable Bit
+ * | | |In Master mode, the transfer will start when there is data in the FIFO buffer after this is set to 1.
+ * | | |In Slave mode, this device is ready to receive data when this bit is set to 1.
+ * | | |0 = Transfer control Disabled.
+ * | | |1 = Transfer control Enabled.
+ * | | |Note: Before changing the configurations of SPI_CTL, SPI_CLKDIV, SPI_SSCTL and SPI_FIFOCTL registers, user shall clear the SPIEN (SPI_CTL[0]) and confirm the SPIENSTS (SPI_STATUS[15]) is 0.
+ * |[1] |RXNEG |Receive On Negative Edge
+ * | | |0 = Received data input signal is latched on the rising edge of SPI bus clock.
+ * | | |1 = Received data input signal is latched on the falling edge of SPI bus clock.
+ * |[2] |TXNEG |Transmit On Negative Edge
+ * | | |0 = Transmitted data output signal is changed on the rising edge of SPI bus clock.
+ * | | |1 = Transmitted data output signal is changed on the falling edge of SP bus clock.
+ * |[3] |CLKPOL |Clock Polarity
+ * | | |0 = SPI bus clock is idle low.
+ * | | |1 = SPI bus clock is idle high.
+ * |[7:4] |SUSPITV |Suspend Interval (Master Only)
+ * | | |The four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer.
+ * | | |The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word.
+ * | | |The default value is 0x3.
+ * | | |The period of the suspend interval is obtained according to the following equation.
+ * | | |(SUSPITV[3:0] + 0.5) * period of SPICLK clock cycle
+ * | | |Example:
+ * | | |SUSPITV = 0x0 ... 0.5 SPICLK clock cycle.
+ * | | |SUSPITV = 0x1 ... 1.5 SPICLK clock cycle.
+ * | | |...
+ * | | |SUSPITV = 0xE ... 14.5 SPICLK clock cycle.
+ * | | |SUSPITV = 0xF ... 15.5 SPICLK clock cycle.
+ * |[12:8] |DWIDTH |Data Width
+ * | | |This field specifies how many bits can be transmitted / received in one transaction.
+ * | | |The minimum bit length is 8 bits and can up to 32 bits.
+ * | | |DWIDTH = 0x08 ... 8 bits.
+ * | | |DWIDTH = 0x09 ... 9 bits.
+ * | | |...
+ * | | |DWIDTH = 0x1F ... 31 bits.
+ * | | |DWIDTH = 0x00 ... 32 bits.
+ * |[13] |LSB |Send LSB First
+ * | | |0 = The MSB, which bit of transmit/receive register depends on the setting of DWIDTH, is transmitted/received first.
+ * | | |1 = The LSB, bit 0 of the SPI TX register, is sent first to the SPI data output pin, and the first bit received from the SPI data input pin will be put in the LSB position of the RX register (bit 0 of SPI_RX).
+ * |[16] |TWOBIT |2-Bit Transfer Mode Enable Bit (Only Supported in SPI0)
+ * | | |0 = 2-Bit Transfer mode Disabled.
+ * | | |1 = 2-Bit Transfer mode Enabled.
+ * | | |Note: When 2-Bit Transfer mode is enabled, the first serial transmitted bit data is from the first FIFO buffer data, and the 2nd
+ * | | |serial transmitted bit data is from the second FIFO buffer data.
+ * | | |As the same as transmitted function, the first received bit data is stored into the first FIFO buffer and the 2nd received bit data is stored into the second FIFO buffer at the same time.
+ * |[17] |UNITIEN |Unit Transfer Interrupt Enable Bit
+ * | | |0 = SPI unit transfer interrupt Disabled.
+ * | | |1 = SPI unit transfer interrupt Enabled.
+ * |[18] |SLAVE |Slave Mode Control
+ * | | |0 = Master mode.
+ * | | |1 = Slave mode.
+ * |[19] |REORDER |Byte Reorder Function Enable Bit
+ * | | |0 = Byte Reorder function Disabled.
+ * | | |1 = Byte Reorder function Enabled. A byte suspend interval will be inserted among each byte.
+ * | | |The period of the byte suspend interval depends on the setting of SUSPITV.
+ * | | |Note:
+ * | | |1. Byte Reorder function is only available if DWIDTH is defined as 16, 24, and 32 bits.
+ * | | |2. Byte Reorder function is not supported when the Quad or Dual I/O mode is enabled.
+ * |[20] |QDIODIR |Quad Or Dual I/O Mode Direction Control (Only Supported in SPI0)
+ * | | |0 = Quad or Dual Input mode.
+ * | | |1 = Quad or Dual Output mode.
+ * |[21] |DUALIOEN |Dual I/O Mode Enable Bit (Only Supported in SPI0)
+ * | | |0 = Dual I/O mode Disabled.
+ * | | |1 = Dual I/O mode Enabled.
+ * |[22] |QUADIOEN |Quad I/O Mode Enable Bit (Only Supported in SPI0)
+ * | | |0 = Quad I/O mode Disabled.
+ * | | |1 = Quad I/O mode Enabled.
+ * @var SPI_T::CLKDIV
+ * Offset: 0x04 Clock Divider Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:0] |DIVIDER |Clock Divider
+ * | | |The value in this field is the frequency divider for generating the peripheral clock, fspi_eclk, and the SPI bus clock of SPI master.
+ * | | |The frequency is obtained according to the following equation.
+ * | | | fspi_eclk = fspi_clock_src / (DIVIDER + 1)
+ * | | |where fspi_clock_src is the peripheral clock source, which is defined in the clock control register CLK_CLKSEL2.
+ * @var SPI_T::SSCTL
+ * Offset: 0x08 Slave Select Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |SS |Slave Selection Control (Master Only)
+ * | | |If AUTOSS bit is cleared to 0,
+ * | | |0 = set the SPIn_SS line to inactive state.
+ * | | |1 = set the SPIn_SS line to active state
+ * | | |If the AUTOSS bit is set to 1,
+ * | | |0 = Keep the SPIn_SS line at inactive state.
+ * | | |1 = SPIn_SS line will be automatically driven to active state for the duration of data transfer, and will be driven to inactive state for the rest of the time.
+ * | | |The active state of SPIn_SS is specified in SSACTPOL (SPI_SSCTL[2]).
+ * |[2] |SSACTPOL |Slave Selection Active Polarity
+ * | | |This bit defines the active polarity of slave selection signal (SPIn_SS).
+ * | | |0 = The slave selection signal SPIn_SS is active low.
+ * | | |1 = The slave selection signal SPIn_SS is active high.
+ * |[3] |AUTOSS |Automatic Slave Selection Function Enable Bit (Master Only)
+ * | | |0 = Automatic slave selection function Disabled.
+ * | | |Slave selection signal will be asserted/de-asserted according to SS (SPI_SSCTL[0]).
+ * | | |1 = Automatic slave selection function Enabled.
+ * |[4] |SLV3WIRE |Slave 3-Wire Mode Enable Bit
+ * | | |Slave 3-wire mode is only available in SPI0.
+ * | | |In Slave 3-wire mode, the SPI controller can work with 3-wire interface including SPI0_CLK, SPI0_MISO, and SPI0_MOSI.
+ * | | |0 = 4-wire bi-direction interface.
+ * | | |1 = 3-wire bi-direction interface.
+ * |[5] |SLVTOIEN |Slave Mode Time-Out Interrupt Enable Bit (Only Supported in SPI0)
+ * | | |0 = Slave mode time-out interrupt Disabled.
+ * | | |1 = Slave mode time-out interrupt Enabled.
+ * |[6] |SLVTORST |Slave Mode Time-Out Reset Control (Only Supported in SPI0)
+ * | | |0 = When Slave mode time-out event occurs, the TX and RX control circuit will not be reset.
+ * | | |1 = When Slave mode time-out event occurs, the TX and RX control circuit will be reset by hardware.
+ * |[8] |SLVBEIEN |Slave Mode Bit Count Error Interrupt Enable Bit
+ * | | |0 = Slave mode bit count error interrupt Disabled.
+ * | | |1 = Slave mode bit count error interrupt Enabled.
+ * |[9] |SLVURIEN |Slave Mode TX Under Run Interrupt Enable Bit
+ * | | |0 = Slave mode TX under run interrupt Disabled.
+ * | | |1 = Slave mode TX under run interrupt Enabled.
+ * |[12] |SSACTIEN |Slave Select Active Interrupt Enable Bit
+ * | | |0 = Slave select active interrupt Disabled.
+ * | | |1 = Slave select active interrupt Enabled.
+ * |[13] |SSINAIEN |Slave Select Inactive Interrupt Enable Bit
+ * | | |0 = Slave select inactive interrupt Disabled.
+ * | | |1 = Slave select inactive interrupt Enabled.
+ * |[31:16] |SLVTOCNT |Slave Mode Time-Out Period (Only Supported in SPI0)
+ * | | |In Slave mode, these bits indicate the time-out period when there is bus clock input during slave select active.
+ * | | |The clock source of the time-out counter is Slave peripheral clock.
+ * | | |If the value is 0, it indicates the slave mode time-out function is disabled.
+ * @var SPI_T::PDMACTL
+ * Offset: 0x0C SPI PDMA Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |TXPDMAEN |Transmit PDMA Enable Bit
+ * | | |0 = Transmit PDMA function Disabled.
+ * | | |1 = Transmit PDMA function Enabled.
+ * | | |Note: In SPI master mode with full duplex transfer, if both TX and RX PDMA functions are enabled, RX PDMA function cannot be enabled prior to TX PDMA function.
+ * | | |User can enable TX PDMA function firstly or enable both functions simultaneously.
+ * |[1] |RXPDMAEN |Receive PDMA Enable Bit
+ * | | |0 = Receiver PDMA function Disabled.
+ * | | |1 = Receiver PDMA function Enabled.
+ * |[2] |PDMARST |PDMA Reset
+ * | | |0 = No effect.
+ * | | |1 = Reset the PDMA control logic of the SPI controller. This bit will be automatically cleared to 0.
+ * @var SPI_T::FIFOCTL
+ * Offset: 0x10 SPI FIFO Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |RXRST |Receive Reset
+ * | | |0 = No effect.
+ * | | |1 = Reset receive FIFO pointer and receive circuit. The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1.
+ * | | |This bit will be cleared to 0 by hardware about 3 system clock cycles + 3 peripheral clock cycles after it is set to 1.
+ * | | |User can read TXRXRST (SPI_STATUS[23]) to check if reset is accomplished or not.
+ * | | |Note: If there is slave receive time-out event, the RXRST will be set 1 when the SLVTORST (SPI_SSCTL[6]) is enabled.
+ * |[1] |TXRST |Transmit Reset
+ * | | |0 = No effect.
+ * | | |1 = Reset transmit FIFO pointer and transmit circuit. The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1.
+ * | | |This bit will be cleared to 0 by hardware about 3 system clock cycles + 3 peripheral clock cycles after it is set to 1.
+ * | | |User can read TXRXRST (SPI_STATUS[23]) to check if reset is accomplished or not.
+ * | | |Note: If there is slave receive time-out event, the TXRST will be set to 1 when the SLVTORST (SPI_SSCTL[6]) is enabled.
+ * |[2] |RXTHIEN |Receive FIFO Threshold Interrupt Enable Bit
+ * | | |0 = RX FIFO threshold interrupt Disabled.
+ * | | |1 = RX FIFO threshold interrupt Enabled.
+ * |[3] |TXTHIEN |Transmit FIFO Threshold Interrupt Enable Bit
+ * | | |0 = TX FIFO threshold interrupt Disabled.
+ * | | |1 = TX FIFO threshold interrupt Enabled.
+ * |[4] |RXTOIEN |Slave Receive Time-Out Interrupt Enable Bit
+ * | | |0 = Receive time-out interrupt Disabled.
+ * | | |1 = Receive time-out interrupt Enabled.
+ * |[5] |RXOVIEN |Receive FIFO Overrun Interrupt Enable Bit
+ * | | |0 = Receive FIFO overrun interrupt Disabled.
+ * | | |1 = Receive FIFO overrun interrupt Enabled.
+ * |[6] |TXUFPOL |TX Underflow Data Polarity
+ * | | |0 = The SPI data out is keep 0 if there is TX underflow event in Slave mode.
+ * | | |1 = The SPI data out is keep 1 if there is TX underflow event in Slave mode.
+ * | | |Note: The TX underflow event occurs if there is not any data in TX FIFO when the slave selection signal is active.
+ * |[7] |TXUFIEN |TX Underflow Interrupt Enable Bit
+ * | | |In Slave mode, when TX underflow event occurs, this interrupt flag will be set to 1.
+ * | | |0 = Slave TX underflow interrupt Disabled.
+ * | | |1 = Slave TX underflow interrupt Enabled.
+ * |[8] |RXFBCLR |Receive FIFO Buffer Clear
+ * | | |0 = No effect.
+ * | | |1 = Clear receive FIFO pointer. The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1.
+ * | | |This bit will be cleared to 0 by hardware about 1 system clock after it is set to 1.
+ * | | |Note: The RX shift register will not be cleared.
+ * |[9] |TXFBCLR |Transmit FIFO Buffer Clear
+ * | | |0 = No effect.
+ * | | |1 = Clear transmit FIFO pointer. The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1.
+ * | | |This bit will be cleared to 0 by hardware about 1 system clock after it is set to 1.
+ * | | |Note: The TX shift register will not be cleared.
+ * |[26:24] |RXTH |Receive FIFO Threshold
+ * | | |If the valid data count of the receive FIFO buffer is larger than the RXTH setting, the RXTHIF bit will be set to 1, else the RXTHIF bit will be cleared to 0.
+ * | | |In SPI0, RXTH is a 3-bit wide configuration; in SPI1 and SPI2, 2-bit wide only (SPI_FIFOCTL[25:24]).
+ * |[30:28] |TXTH |Transmit FIFO Threshold
+ * | | |If the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting, the TXTHIF bit will be set to 1, else the TXTHIF bit will be cleared to 0.
+ * | | |In SPI0, TXTH is a 3-bit wide configuration; in SPI1 and SPI2, 2-bit wide only (SPI_FIFOCTL[29:28]).
+ * @var SPI_T::STATUS
+ * Offset: 0x14 SPI Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |BUSY |Busy Status (Read Only)
+ * | | |0 = SPI controller is in idle state.
+ * | | |1 = SPI controller is in busy state.
+ * | | |The following listing are the bus busy conditions:
+ * | | |a. SPI_CTL[0] = 1 and the TXEMPTY = 0.
+ * | | |b. For SPI Master mode, the TXEMPTY = 1 but the current transaction is not finished yet.
+ * | | |c. For SPI Slave mode, the SPI_CTL[0] = 1 and there is serial clock input into the SPI core logic when slave select is active.
+ * | | |d. For SPI Slave mode, the SPI_CTL[0] = 1 and the transmit buffer or transmit shift register is not empty even if the slave select is inactive.
+ * |[1] |UNITIF |Unit Transfer Interrupt Flag
+ * | | |0 = No transaction has been finished since this bit was cleared to 0.
+ * | | |1 = SPI controller has finished one unit transfer.
+ * | | |Note: This bit will be cleared by writing 1 to it.
+ * |[2] |SSACTIF |Slave Select Active Interrupt Flag
+ * | | |0 = Slave select active interrupt was cleared or not occurred.
+ * | | |1 = Slave select active interrupt event occurred.
+ * | | |Note: Only available in Slave mode. This bit will be cleared by writing 1 to it.
+ * |[3] |SSINAIF |Slave Select Inactive Interrupt Flag
+ * | | |0 = Slave select inactive interrupt was cleared or not occurred.
+ * | | |1 = Slave select inactive interrupt event occurred.
+ * | | |Note: Only available in Slave mode. This bit will be cleared by writing 1 to it.
+ * |[4] |SSLINE |Slave Select Line Bus Status (Read Only)
+ * | | |0 = The slave select line status is 0.
+ * | | |1 = The slave select line status is 1.
+ * | | |Note: This bit is only available in Slave mode.
+ * | | |If SSACTPOL (SPI_SSCTL[2]) is set 0, and the SSLINE is 1, the SPI slave select is in inactive status.
+ * |[5] |SLVTOIF |Slave Time-Out Interrupt Flag (Only Supported in SPI0)
+ * | | |When the Slave Select is active and the value of SLVTOCNT is not 0, as the bus clock is detected, the slave time-out counter in SPI controller logic will be started.
+ * | | |When the value of time-out counter is greater than or equal to the value of SLVTOCNT (SPI_SSCTL[31:16]) before one transaction is done, the slave time-out interrupt event will be asserted.
+ * | | |0 = Slave time-out is not active.
+ * | | |1 = Slave time-out is active.
+ * | | |Note: This bit will be cleared by writing 1 to it.
+ * |[6] |SLVBEIF |Slave Mode Bit Count Error Interrupt Flag
+ * | | |In Slave mode, when the slave select line goes to inactive state, if bit counter is mismatch with DWIDTH, this interrupt flag will be set to 1.
+ * | | |0 = No Slave mode bit count error event.
+ * | | |1 = Slave mode bit count error event occurs.
+ * | | |Note: If the slave select active but there is no any bus clock input, the SLVBCEIF also active when the slave select goes to inactive state.
+ * | | |This bit will be cleared by writing 1 to it.
+ * |[7] |SLVURIF |Slave Mode TX Under Run Interrupt Flag
+ * | | |In Slave mode, if TX underflow event occurs and the slave select line goes to inactive state, this interrupt flag will be set to 1.
+ * | | |0 = No Slave TX under run event.
+ * | | |1 = Slave TX under run occurs.
+ * | | |Note: This bit will be cleared by writing 1 to it.
+ * |[8] |RXEMPTY |Receive FIFO Buffer Empty Indicator (Read Only)
+ * | | |0 = Receive FIFO buffer is not empty.
+ * | | |1 = Receive FIFO buffer is empty.
+ * |[9] |RXFULL |Receive FIFO Buffer Full Indicator (Read Only)
+ * | | |0 = Receive FIFO buffer is not full.
+ * | | |1 = Receive FIFO buffer is full.
+ * |[10] |RXTHIF |Receive FIFO Threshold Interrupt Flag (Read Only)
+ * | | |0 = The valid data count within the RX FIFO buffer is smaller than or equal to the setting value of RXTH.
+ * | | |1 = The valid data count within the receive FIFO buffer is larger than the setting value of RXTH.
+ * |[11] |RXOVIF |Receive FIFO Overrun Interrupt Flag
+ * | | |When the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1.
+ * | | |0 = No FIFO is over run.
+ * | | |1 = Receive FIFO over run.
+ * | | |Note: This bit will be cleared by writing 1 to it.
+ * |[12] |RXTOIF |Receive Time-Out Interrupt Flag
+ * | | |0 = No receive FIFO time-out event.
+ * | | |1 = Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 SPI clock period in Master mode or over 576 peripheral clock period in Slave mode.
+ * | | |When the received FIFO buffer is read by software, the time-out status will be cleared automatically.
+ * | | |Note: This bit will be cleared by writing 1 to it.
+ * |[15] |SPIENSTS |SPI Enable Status (Read Only)
+ * | | |0 = The SPI controller is disabled.
+ * | | |1 = The SPI controller is enabled.
+ * | | |Note: The SPI peripheral clock is asynchronous with the system clock.
+ * | | |In order to make sure the SPI control logic is disabled, this bit indicates the real status of SPI controller.
+ * |[16] |TXEMPTY |Transmit FIFO Buffer Empty Indicator (Read Only)
+ * | | |0 = Transmit FIFO buffer is not empty.
+ * | | |1 = Transmit FIFO buffer is empty.
+ * |[17] |TXFULL |Transmit FIFO Buffer Full Indicator (Read Only)
+ * | | |0 = Transmit FIFO buffer is not full.
+ * | | |1 = Transmit FIFO buffer is full.
+ * |[18] |TXTHIF |Transmit FIFO Threshold Interrupt Flag (Read Only)
+ * | | |0 = The valid data count within the transmit FIFO buffer is larger than the setting value of TXTH.
+ * | | |1 = The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TXTH.
+ * |[19] |TXUFIF |TX Underflow Interrupt Flag
+ * | | |When the TX underflow event occurs, this bit will be set to 1, the state of data output pin depends on the setting of TXUFPOL.
+ * | | |0 = No effect.
+ * | | |1 = No data in Transmit FIFO and TX shift register when the slave selection signal is active.
+ * | | |Note 1: This bit will be cleared by writing 1 to it.
+ * | | |Note 2: If reset slave's transmission circuit when slave selection signal is active, this flag will be set to 1 after 2 peripheral clock cycles + 3 system clock cycles since the reset operation is done.
+ * |[23] |TXRXRST |TX or RX Reset Status (Read Only)
+ * | | |0 = The reset function of TXRST or RXRST is done.
+ * | | |1 = Doing the reset function of TXRST or RXRST.
+ * | | |Note: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles.
+ * | | |User can check the status of this bit to monitor the reset function is doing or done.
+ * |[27:24] |RXCNT |Receive FIFO Data Count (Read Only)
+ * | | |This bit field indicates the valid data count of receive FIFO buffer.
+ * |[31:28] |TXCNT |Transmit FIFO Data Count (Read Only)
+ * | | |This bit field indicates the valid data count of transmit FIFO buffer.
+ * @var SPI_T::TX
+ * Offset: 0x20 Data Transmit Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |TX |Data Transmit Register
+ * | | |The data transmit registers pass through the transmitted data into the 8-/4-level transmit FIFO buffer.
+ * | | |The number of valid bits depends on the setting of DWIDTH (SPI_CTL[12:8]).
+ * | | |For example, if DWIDTH is set to 0x08, the bits TX[7:0] will be transmitted.
+ * | | |If DWIDTH is set to 0x00, the SPI controller will perform a 32-bit transfer.
+ * | | |Note: In Master mode, SPI controller will start to transfer after 5 peripheral clock cycles after user writes to this register.
+ * @var SPI_T::RX
+ * Offset: 0x30 Data Receive Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |RX |Data Receive Register
+ * | | |There are 8-/4-level FIFO buffers in this controller.
+ * | | |The data receive register holds the data received from SPI data input pin.
+ * | | |If the RXEMPTY (SPI_STATUS[8]) is not set to 1, the receive FIFO buffers can be accessed through software by reading this register.
+ * | | |This is a read only register.
+ * @var SPI_T::I2SCTL
+ * Offset: 0x60 I2S Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |I2SEN |I2S Controller Enable Bit
+ * | | |0 = Disabled.
+ * | | |1 = Enabled.
+ * | | |Note: If enable this bit, I2Sn_BCLK will start to output in master mode.
+ * |[1] |TXEN |Transmit Enable Bit
+ * | | |0 = Data transmit Disabled.
+ * | | |1 = Data transmit Enabled.
+ * |[2] |RXEN |Receive Enable Bit
+ * | | |0 = Data receiving Disabled.
+ * | | |1 = Data receiving Enabled.
+ * |[3] |MUTE |Transmit Mute Enable Bit
+ * | | |0 = Transmit data is shifted from buffer.
+ * | | |1= Transmit channel zero.
+ * |[5:4] |WDWIDTH |Word Width
+ * | | |00 = data is 8-bit.
+ * | | |01 = data is 16-bit.
+ * | | |10 = data is 24-bit.
+ * | | |11 = data is 32-bit.
+ * |[6] |MONO |Monaural Data
+ * | | |0 = Data is stereo format.
+ * | | |1 = Data is monaural format.
+ * |[7] |ORDER |Stereo Data Order In FIFO
+ * | | |0 = Left channel data at high byte.
+ * | | |1 = Left channel data at low byte.
+ * |[8] |SLAVE |Slave Mode
+ * | | |I2S can operate as master or slave.
+ * | | |For Master mode, I2Sn_BCLK and I2Sn_LRCLK pins are output mode and send bit clock from NuMicro M451 series to Audio CODEC chip.
+ * | | |In Slave mode, I2Sn_BCLK and I2Sn_LRCLK pins are input mode and I2Sn_BCLK and I2Sn_LRCLK signals are received from outer Audio CODEC chip.
+ * | | |0 = Master mode.
+ * | | |1 = Slave mode.
+ * |[15] |MCLKEN |Master Clock Enable Bit
+ * | | |If MCLKEN is set to 1, I2S controller will generate master clock on I2Sn_MCLK pin for external audio devices.
+ * | | |0 = Master clock Disabled.
+ * | | |1 = Master clock Enabled.
+ * |[16] |RZCEN |Right Channel Zero Cross Detection Enable Bit
+ * | | |If this bit is set to 1, when right channel data sign bit change or next shift data bits are all 0 then RZCIF flag in SPI_I2SSTS register is set to 1.
+ * | | |This function is only available in transmit operation.
+ * | | |0 = Right channel zero cross detection Disabled.
+ * | | |1 = Right channel zero cross detection Enabled.
+ * |[17] |LZCEN |Left Channel Zero Cross Detection Enable Bit
+ * | | |If this bit is set to 1, when left channel data sign bit changes or next shift data bits are all 0 then LZCIF flag in SPI_I2SSTS register is set to 1.
+ * | | |This function is only available in transmit operation.
+ * | | |0 = Left channel zero cross detection Disabled.
+ * | | |1 = Left channel zero cross detection Enabled.
+ * |[23] |RXLCH |Receive Left Channel Enable Bit
+ * | | |When monaural format is selected (MONO = 1), I2S controller will receive right channel data if RXLCH is set to 0, and receive left channel data if RXLCH is set to 1.
+ * | | |0 = Receive right channel data in Mono mode.
+ * | | |1 = Receive left channel data in Mono mode.
+ * |[24] |RZCIEN |Right Channel Zero-Cross Interrupt Enable Bit
+ * | | |Interrupt occurs if this bit is set to 1 and right channel zero-cross event occurs.
+ * | | |0 = Interrupt Disabled.
+ * | | |1 = Interrupt Enabled.
+ * |[25] |LZCIEN |Left Channel Zero-Cross Interrupt Enable Bit
+ * | | |Interrupt occurs if this bit is set to 1 and left channel zero-cross event occurs.
+ * | | |0 = Interrupt Disabled.
+ * | | |1 = Interrupt Enabled.
+ * |[29:28] |FORMAT |Data Format Selection
+ * | | |00 = I2S data format.
+ * | | |01 = MSB justified data format.
+ * | | |10 = PCM mode A.
+ * | | |11 = PCM mode B.
+ * @var SPI_T::I2SCLK
+ * Offset: 0x64 I2S Clock Divider Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[5:0] |MCLKDIV |Master Clock Divider
+ * | | |If MCLKEN is set to 1, I2S controller will generate master clock for external audio devices.
+ * | | |The master clock rate, F_MCLK, is determined by the following expressions.
+ * | | |If MCLKDIV >= 1, F_MCLK = F_I2SCLK/(2x(MCLKDIV)).
+ * | | |If MCLKDIV = 0, F_MCLK = F_I2SCLK.
+ * | | |F_I2SCLK is the frequency of I2S peripheral clock.
+ * | | |In general, the master clock rate is 256 times sampling clock rate.
+ * |[16:8] |BCLKDIV |Bit Clock Divider
+ * | | |The I2S controller will generate bit clock in Master mode.
+ * | | |The bit clock rate, F_BCLK, is determined by the following expression.
+ * | | |F_BCLK = F_I2SCLK /(2x(BCLKDIV + 1)) , where F_I2SCLK is the frequency of I2S peripheral clock.
+ * @var SPI_T::I2SSTS
+ * Offset: 0x68 I2S Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[4] |RIGHT |Right Channel (Read Only)
+ * | | |This bit indicates the current transmit data is belong to which channel.
+ * | | |0 = Left channel.
+ * | | |1 = Right channel.
+ * |[8] |RXEMPTY |Receive FIFO Buffer Empty Indicator (Read Only)
+ * | | |0 = Receive FIFO buffer is not empty.
+ * | | |1 = Receive FIFO buffer is empty.
+ * |[9] |RXFULL |Receive FIFO Buffer Full Indicator (Read Only)
+ * | | |0 = Receive FIFO buffer is not full.
+ * | | |1 = Receive FIFO buffer is full.
+ * |[10] |RXTHIF |Receive FIFO Threshold Interrupt Flag (Read Only)
+ * | | |0 = The valid data count within the Rx FIFO buffer is smaller than or equal to the setting value of RXTH.
+ * | | |1 = The valid data count within the receive FIFO buffer is larger than the setting value of RXTH.
+ * | | |Note: If RXTHIEN = 1 and RXTHIF = 1, the SPI/I2S controller will generate a SPI interrupt request.
+ * |[11] |RXOVIF |Receive FIFO Overrun Interrupt Flag
+ * | | |When the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1.
+ * | | |Note: This bit will be cleared by writing 1 to it.
+ * |[12] |RXTOIF |Receive Time-Out Interrupt Flag
+ * | | |0 = No receive FIFO time-out event.
+ * | | |1 = Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 SPI clock period in Master mode or over 576 peripheral clock period in Slave mode.
+ * | | |When the received FIFO buffer is read by software, the time-out status will be cleared automatically.
+ * | | |Note: This bit will be cleared by writing 1 to it.
+ * |[15] |I2SENSTS |I2S Enable Status (Read Only)
+ * | | |0 = The SPI/I2S control logic is disabled.
+ * | | |1 = The SPI/I2S control logic is enabled.
+ * | | |Note: The SPI peripheral clock is asynchronous with the system clock.
+ * | | |In order to make sure the SPI/I2S controller logic is disabled, this bit indicates the real status of SPI/I2S controller logic for user.
+ * |[16] |TXEMPTY |Transmit FIFO Buffer Empty Indicator (Read Only)
+ * | | |0 = Transmit FIFO buffer is not empty.
+ * | | |1 = Transmit FIFO buffer is empty.
+ * |[17] |TXFULL |Transmit FIFO Buffer Full Indicator (Read Only)
+ * | | |0 = Transmit FIFO buffer is not full.
+ * | | |1 = Transmit FIFO buffer is full.
+ * |[18] |TXTHIF |Transmit FIFO Threshold Interrupt Flag (Read Only)
+ * | | |0 = The valid data count within the transmit FIFO buffer is larger than the setting value of TXTH.
+ * | | |1 = The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TXTH.
+ * | | |Note: If TXTHIEN = 1 and TXTHIF = 1, the SPI controller will generate a SPI interrupt request.
+ * |[19] |TXUFIF |Transmit FIFO Underflow Interrupt Flag
+ * | | |When the transmit FIFO buffer is empty and there is no datum written into the FIFO buffer, if there is more bus clock input,
+ * | | | the output data depends on the setting of TXUFPOL and this bit will be set to 1.
+ * | | |Note: This bit will be cleared by writing 1 to it.
+ * |[20] |RZCIF |Right Channel Zero Cross Interrupt Flag
+ * | | |0 = No zero cross event occurred on right channel.
+ * | | |1 = Zero cross event occurred on right channel.
+ * |[21] |LZCIF |Left Channel Zero Cross Interrupt Flag
+ * | | |0 = No zero cross event occurred on left channel.
+ * | | |1 = Zero cross event occurred on left channel.
+ * |[23] |TXRXRST |TX or RX Reset Status (Read Only)
+ * | | |0 = The reset function of TXRST or RXRST is done.
+ * | | |1 = Doing the reset function of TXRST or RXRST.
+ * | | |Note: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 3 peripheral clock cycles.
+ * | | |User can check the status of this bit to monitor the reset function is doing or done.
+ * |[26:24] |RXCNT |Receive FIFO Data Count (Read Only)
+ * | | |This bit field indicates the valid data count of receive FIFO buffer.
+ * |[30:28] |TXCNT |Transmit FIFO Data Count (Read Only)
+ * | | |This bit field indicates the valid data count of transmit FIFO buffer.
+ */
+
+ __IO uint32_t CTL; /* Offset: 0x00 Control Register */
+ __IO uint32_t CLKDIV; /* Offset: 0x04 Clock Divider Register */
+ __IO uint32_t SSCTL; /* Offset: 0x08 Slave Select Control Register */
+ __IO uint32_t PDMACTL; /* Offset: 0x0C SPI PDMA Control Register */
+ __IO uint32_t FIFOCTL; /* Offset: 0x10 SPI FIFO Control Register */
+ __IO uint32_t STATUS; /* Offset: 0x14 SPI Status Register */
+ __I uint32_t RESERVE0[2];
+ __O uint32_t TX; /* Offset: 0x20 Data Transmit Register */
+ __I uint32_t RESERVE1[3];
+ __I uint32_t RX; /* Offset: 0x30 Data Receive Register */
+ __I uint32_t RESERVE2[11];
+ __IO uint32_t I2SCTL; /* Offset: 0x60 I2S Control Register */
+ __IO uint32_t I2SCLK; /* Offset: 0x64 I2S Clock Divider Control Register */
+ __IO uint32_t I2SSTS; /* Offset: 0x68 I2S Status Register */
+
+} SPI_T;
+
+
+
+/**
+ @addtogroup SPI_CONST SPI Bit Field Definition
+ Constant Definitions for SPI Controller
+@{ */
+
+#define SPI_CTL_SPIEN_Pos (0) /*!< SPI_T::CTL: SPIEN Position */
+#define SPI_CTL_SPIEN_Msk (0x1ul << SPI_CTL_SPIEN_Pos) /*!< SPI_T::CTL: SPIEN Mask */
+
+#define SPI_CTL_RXNEG_Pos (1) /*!< SPI_T::CTL: RXNEG Position */
+#define SPI_CTL_RXNEG_Msk (0x1ul << SPI_CTL_RXNEG_Pos) /*!< SPI_T::CTL: RXNEG Mask */
+
+#define SPI_CTL_TXNEG_Pos (2) /*!< SPI_T::CTL: TXNEG Position */
+#define SPI_CTL_TXNEG_Msk (0x1ul << SPI_CTL_TXNEG_Pos) /*!< SPI_T::CTL: TXNEG Mask */
+
+#define SPI_CTL_CLKPOL_Pos (3) /*!< SPI_T::CTL: CLKPOL Position */
+#define SPI_CTL_CLKPOL_Msk (0x1ul << SPI_CTL_CLKPOL_Pos) /*!< SPI_T::CTL: CLKPOL Mask */
+
+#define SPI_CTL_SUSPITV_Pos (4) /*!< SPI_T::CTL: SUSPITV Position */
+#define SPI_CTL_SUSPITV_Msk (0xful << SPI_CTL_SUSPITV_Pos) /*!< SPI_T::CTL: SUSPITV Mask */
+
+#define SPI_CTL_DWIDTH_Pos (8) /*!< SPI_T::CTL: DWIDTH Position */
+#define SPI_CTL_DWIDTH_Msk (0x1ful << SPI_CTL_DWIDTH_Pos) /*!< SPI_T::CTL: DWIDTH Mask */
+
+#define SPI_CTL_LSB_Pos (13) /*!< SPI_T::CTL: LSB Position */
+#define SPI_CTL_LSB_Msk (0x1ul << SPI_CTL_LSB_Pos) /*!< SPI_T::CTL: LSB Mask */
+
+#define SPI_CTL_TWOBIT_Pos (16) /*!< SPI_T::CTL: TWOBIT Position */
+#define SPI_CTL_TWOBIT_Msk (0x1ul << SPI_CTL_TWOBIT_Pos) /*!< SPI_T::CTL: TWOBIT Mask */
+
+#define SPI_CTL_UNITIEN_Pos (17) /*!< SPI_T::CTL: UNITIEN Position */
+#define SPI_CTL_UNITIEN_Msk (0x1ul << SPI_CTL_UNITIEN_Pos) /*!< SPI_T::CTL: UNITIEN Mask */
+
+#define SPI_CTL_SLAVE_Pos (18) /*!< SPI_T::CTL: SLAVE Position */
+#define SPI_CTL_SLAVE_Msk (0x1ul << SPI_CTL_SLAVE_Pos) /*!< SPI_T::CTL: SLAVE Mask */
+
+#define SPI_CTL_REORDER_Pos (19) /*!< SPI_T::CTL: REORDER Position */
+#define SPI_CTL_REORDER_Msk (0x1ul << SPI_CTL_REORDER_Pos) /*!< SPI_T::CTL: REORDER Mask */
+
+#define SPI_CTL_QDIODIR_Pos (20) /*!< SPI_T::CTL: QDIODIR Position */
+#define SPI_CTL_QDIODIR_Msk (0x1ul << SPI_CTL_QDIODIR_Pos) /*!< SPI_T::CTL: QDIODIR Mask */
+
+#define SPI_CTL_DUALIOEN_Pos (21) /*!< SPI_T::CTL: DUALIOEN Position */
+#define SPI_CTL_DUALIOEN_Msk (0x1ul << SPI_CTL_DUALIOEN_Pos) /*!< SPI_T::CTL: DUALIOEN Mask */
+
+#define SPI_CTL_QUADIOEN_Pos (22) /*!< SPI_T::CTL: QUADIOEN Position */
+#define SPI_CTL_QUADIOEN_Msk (0x1ul << SPI_CTL_QUADIOEN_Pos) /*!< SPI_T::CTL: QUADIOEN Mask */
+
+#define SPI_CLKDIV_DIVIDER_Pos (0) /*!< SPI_T::CLKDIV: DIVIDER Position */
+#define SPI_CLKDIV_DIVIDER_Msk (0xfful << SPI_CLKDIV_DIVIDER_Pos) /*!< SPI_T::CLKDIV: DIVIDER Mask */
+
+#define SPI_SSCTL_SS_Pos (0) /*!< SPI_T::SSCTL: SS Position */
+#define SPI_SSCTL_SS_Msk (0x1ul << SPI_SSCTL_SS_Pos) /*!< SPI_T::SSCTL: SS Mask */
+
+#define SPI_SSCTL_SSACTPOL_Pos (2) /*!< SPI_T::SSCTL: SSACTPOL Position */
+#define SPI_SSCTL_SSACTPOL_Msk (0x1ul << SPI_SSCTL_SSACTPOL_Pos) /*!< SPI_T::SSCTL: SSACTPOL Mask */
+
+#define SPI_SSCTL_AUTOSS_Pos (3) /*!< SPI_T::SSCTL: AUTOSS Position */
+#define SPI_SSCTL_AUTOSS_Msk (0x1ul << SPI_SSCTL_AUTOSS_Pos) /*!< SPI_T::SSCTL: AUTOSS Mask */
+
+#define SPI_SSCTL_SLV3WIRE_Pos (4) /*!< SPI_T::SSCTL: SLV3WIRE Position */
+#define SPI_SSCTL_SLV3WIRE_Msk (0x1ul << SPI_SSCTL_SLV3WIRE_Pos) /*!< SPI_T::SSCTL: SLV3WIRE Mask */
+
+#define SPI_SSCTL_SLVTOIEN_Pos (5) /*!< SPI_T::SSCTL: SLVTOIEN Position */
+#define SPI_SSCTL_SLVTOIEN_Msk (0x1ul << SPI_SSCTL_SLVTOIEN_Pos) /*!< SPI_T::SSCTL: SLVTOIEN Mask */
+
+#define SPI_SSCTL_SLVTORST_Pos (6) /*!< SPI_T::SSCTL: SLVTORST Position */
+#define SPI_SSCTL_SLVTORST_Msk (0x1ul << SPI_SSCTL_SLVTORST_Pos) /*!< SPI_T::SSCTL: SLVTORST Mask */
+
+#define SPI_SSCTL_SLVBEIEN_Pos (8) /*!< SPI_T::SSCTL: SLVBEIEN Position */
+#define SPI_SSCTL_SLVBEIEN_Msk (0x1ul << SPI_SSCTL_SLVBEIEN_Pos) /*!< SPI_T::SSCTL: SLVBEIEN Mask */
+
+#define SPI_SSCTL_SLVURIEN_Pos (9) /*!< SPI_T::SSCTL: SLVURIEN Position */
+#define SPI_SSCTL_SLVURIEN_Msk (0x1ul << SPI_SSCTL_SLVURIEN_Pos) /*!< SPI_T::SSCTL: SLVURIEN Mask */
+
+#define SPI_SSCTL_SSACTIEN_Pos (12) /*!< SPI_T::SSCTL: SSACTIEN Position */
+#define SPI_SSCTL_SSACTIEN_Msk (0x1ul << SPI_SSCTL_SSACTIEN_Pos) /*!< SPI_T::SSCTL: SSACTIEN Mask */
+
+#define SPI_SSCTL_SSINAIEN_Pos (13) /*!< SPI_T::SSCTL: SSINAIEN Position */
+#define SPI_SSCTL_SSINAIEN_Msk (0x1ul << SPI_SSCTL_SSINAIEN_Pos) /*!< SPI_T::SSCTL: SSINAIEN Mask */
+
+#define SPI_SSCTL_SLVTOCNT_Pos (16) /*!< SPI_T::SSCTL: SLVTOCNT Position */
+#define SPI_SSCTL_SLVTOCNT_Msk (0xfffful << SPI_SSCTL_SLVTOCNT_Pos) /*!< SPI_T::SSCTL: SLVTOCNT Mask */
+
+#define SPI_PDMACTL_TXPDMAEN_Pos (0) /*!< SPI_T::PDMACTL: TXPDMAEN Position */
+#define SPI_PDMACTL_TXPDMAEN_Msk (0x1ul << SPI_PDMACTL_TXPDMAEN_Pos) /*!< SPI_T::PDMACTL: TXPDMAEN Mask */
+
+#define SPI_PDMACTL_RXPDMAEN_Pos (1) /*!< SPI_T::PDMACTL: RXPDMAEN Position */
+#define SPI_PDMACTL_RXPDMAEN_Msk (0x1ul << SPI_PDMACTL_RXPDMAEN_Pos) /*!< SPI_T::PDMACTL: RXPDMAEN Mask */
+
+#define SPI_PDMACTL_PDMARST_Pos (2) /*!< SPI_T::PDMACTL: PDMARST Position */
+#define SPI_PDMACTL_PDMARST_Msk (0x1ul << SPI_PDMACTL_PDMARST_Pos) /*!< SPI_T::PDMACTL: PDMARST Mask */
+
+#define SPI_FIFOCTL_RXRST_Pos (0) /*!< SPI_T::FIFOCTL: RXRST Position */
+#define SPI_FIFOCTL_RXRST_Msk (0x1ul << SPI_FIFOCTL_RXRST_Pos) /*!< SPI_T::FIFOCTL: RXRST Mask */
+
+#define SPI_FIFOCTL_TXRST_Pos (1) /*!< SPI_T::FIFOCTL: TXRST Position */
+#define SPI_FIFOCTL_TXRST_Msk (0x1ul << SPI_FIFOCTL_TXRST_Pos) /*!< SPI_T::FIFOCTL: TXRST Mask */
+
+#define SPI_FIFOCTL_RXTHIEN_Pos (2) /*!< SPI_T::FIFOCTL: RXTHIEN Position */
+#define SPI_FIFOCTL_RXTHIEN_Msk (0x1ul << SPI_FIFOCTL_RXTHIEN_Pos) /*!< SPI_T::FIFOCTL: RXTHIEN Mask */
+
+#define SPI_FIFOCTL_TXTHIEN_Pos (3) /*!< SPI_T::FIFOCTL: TXTHIEN Position */
+#define SPI_FIFOCTL_TXTHIEN_Msk (0x1ul << SPI_FIFOCTL_TXTHIEN_Pos) /*!< SPI_T::FIFOCTL: TXTHIEN Mask */
+
+#define SPI_FIFOCTL_RXTOIEN_Pos (4) /*!< SPI_T::FIFOCTL: RXTOIEN Position */
+#define SPI_FIFOCTL_RXTOIEN_Msk (0x1ul << SPI_FIFOCTL_RXTOIEN_Pos) /*!< SPI_T::FIFOCTL: RXTOIEN Mask */
+
+#define SPI_FIFOCTL_RXOVIEN_Pos (5) /*!< SPI_T::FIFOCTL: RXOVIEN Position */
+#define SPI_FIFOCTL_RXOVIEN_Msk (0x1ul << SPI_FIFOCTL_RXOVIEN_Pos) /*!< SPI_T::FIFOCTL: RXOVIEN Mask */
+
+#define SPI_FIFOCTL_TXUFPOL_Pos (6) /*!< SPI_T::FIFOCTL: TXUFPOL Position */
+#define SPI_FIFOCTL_TXUFPOL_Msk (0x1ul << SPI_FIFOCTL_TXUFPOL_Pos) /*!< SPI_T::FIFOCTL: TXUFPOL Mask */
+
+#define SPI_FIFOCTL_TXUFIEN_Pos (7) /*!< SPI_T::FIFOCTL: TXUFIEN Position */
+#define SPI_FIFOCTL_TXUFIEN_Msk (0x1ul << SPI_FIFOCTL_TXUFIEN_Pos) /*!< SPI_T::FIFOCTL: TXUFIEN Mask */
+
+#define SPI_FIFOCTL_RXFBCLR_Pos (8) /*!< SPI_T::FIFOCTL: RXFBCLR Position */
+#define SPI_FIFOCTL_RXFBCLR_Msk (0x1ul << SPI_FIFOCTL_RXFBCLR_Pos) /*!< SPI_T::FIFOCTL: RXFBCLR Mask */
+
+#define SPI_FIFOCTL_TXFBCLR_Pos (9) /*!< SPI_T::FIFOCTL: TXFBCLR Position */
+#define SPI_FIFOCTL_TXFBCLR_Msk (0x1ul << SPI_FIFOCTL_TXFBCLR_Pos) /*!< SPI_T::FIFOCTL: TXFBCLR Mask */
+
+#define SPI_FIFOCTL_RXTH_Pos (24) /*!< SPI_T::FIFOCTL: RXTH Position */
+#define SPI_FIFOCTL_RXTH_Msk (0x7ul << SPI_FIFOCTL_RXTH_Pos) /*!< SPI_T::FIFOCTL: RXTH Mask */
+
+#define SPI_FIFOCTL_TXTH_Pos (28) /*!< SPI_T::FIFOCTL: TXTH Position */
+#define SPI_FIFOCTL_TXTH_Msk (0x7ul << SPI_FIFOCTL_TXTH_Pos) /*!< SPI_T::FIFOCTL: TXTH Mask */
+
+#define SPI_STATUS_BUSY_Pos (0) /*!< SPI_T::STATUS: BUSY Position */
+#define SPI_STATUS_BUSY_Msk (0x1ul << SPI_STATUS_BUSY_Pos) /*!< SPI_T::STATUS: BUSY Mask */
+
+#define SPI_STATUS_UNITIF_Pos (1) /*!< SPI_T::STATUS: UNITIF Position */
+#define SPI_STATUS_UNITIF_Msk (0x1ul << SPI_STATUS_UNITIF_Pos) /*!< SPI_T::STATUS: UNITIF Mask */
+
+#define SPI_STATUS_SSACTIF_Pos (2) /*!< SPI_T::STATUS: SSACTIF Position */
+#define SPI_STATUS_SSACTIF_Msk (0x1ul << SPI_STATUS_SSACTIF_Pos) /*!< SPI_T::STATUS: SSACTIF Mask */
+
+#define SPI_STATUS_SSINAIF_Pos (3) /*!< SPI_T::STATUS: SSINAIF Position */
+#define SPI_STATUS_SSINAIF_Msk (0x1ul << SPI_STATUS_SSINAIF_Pos) /*!< SPI_T::STATUS: SSINAIF Mask */
+
+#define SPI_STATUS_SSLINE_Pos (4) /*!< SPI_T::STATUS: SSLINE Position */
+#define SPI_STATUS_SSLINE_Msk (0x1ul << SPI_STATUS_SSLINE_Pos) /*!< SPI_T::STATUS: SSLINE Mask */
+
+#define SPI_STATUS_SLVTOIF_Pos (5) /*!< SPI_T::STATUS: SLVTOIF Position */
+#define SPI_STATUS_SLVTOIF_Msk (0x1ul << SPI_STATUS_SLVTOIF_Pos) /*!< SPI_T::STATUS: SLVTOIF Mask */
+
+#define SPI_STATUS_SLVBEIF_Pos (6) /*!< SPI_T::STATUS: SLVBEIF Position */
+#define SPI_STATUS_SLVBEIF_Msk (0x1ul << SPI_STATUS_SLVBEIF_Pos) /*!< SPI_T::STATUS: SLVBEIF Mask */
+
+#define SPI_STATUS_SLVURIF_Pos (7) /*!< SPI_T::STATUS: SLVURIF Position */
+#define SPI_STATUS_SLVURIF_Msk (0x1ul << SPI_STATUS_SLVURIF_Pos) /*!< SPI_T::STATUS: SLVURIF Mask */
+
+#define SPI_STATUS_RXEMPTY_Pos (8) /*!< SPI_T::STATUS: RXEMPTY Position */
+#define SPI_STATUS_RXEMPTY_Msk (0x1ul << SPI_STATUS_RXEMPTY_Pos) /*!< SPI_T::STATUS: RXEMPTY Mask */
+
+#define SPI_STATUS_RXFULL_Pos (9) /*!< SPI_T::STATUS: RXFULL Position */
+#define SPI_STATUS_RXFULL_Msk (0x1ul << SPI_STATUS_RXFULL_Pos) /*!< SPI_T::STATUS: RXFULL Mask */
+
+#define SPI_STATUS_RXTHIF_Pos (10) /*!< SPI_T::STATUS: RXTHIF Position */
+#define SPI_STATUS_RXTHIF_Msk (0x1ul << SPI_STATUS_RXTHIF_Pos) /*!< SPI_T::STATUS: RXTHIF Mask */
+
+#define SPI_STATUS_RXOVIF_Pos (11) /*!< SPI_T::STATUS: RXOVIF Position */
+#define SPI_STATUS_RXOVIF_Msk (0x1ul << SPI_STATUS_RXOVIF_Pos) /*!< SPI_T::STATUS: RXOVIF Mask */
+
+#define SPI_STATUS_RXTOIF_Pos (12) /*!< SPI_T::STATUS: RXTOIF Position */
+#define SPI_STATUS_RXTOIF_Msk (0x1ul << SPI_STATUS_RXTOIF_Pos) /*!< SPI_T::STATUS: RXTOIF Mask */
+
+#define SPI_STATUS_SPIENSTS_Pos (15) /*!< SPI_T::STATUS: SPIENSTS Position */
+#define SPI_STATUS_SPIENSTS_Msk (0x1ul << SPI_STATUS_SPIENSTS_Pos) /*!< SPI_T::STATUS: SPIENSTS Mask */
+
+#define SPI_STATUS_TXEMPTY_Pos (16) /*!< SPI_T::STATUS: TXEMPTY Position */
+#define SPI_STATUS_TXEMPTY_Msk (0x1ul << SPI_STATUS_TXEMPTY_Pos) /*!< SPI_T::STATUS: TXEMPTY Mask */
+
+#define SPI_STATUS_TXFULL_Pos (17) /*!< SPI_T::STATUS: TXFULL Position */
+#define SPI_STATUS_TXFULL_Msk (0x1ul << SPI_STATUS_TXFULL_Pos) /*!< SPI_T::STATUS: TXFULL Mask */
+
+#define SPI_STATUS_TXTHIF_Pos (18) /*!< SPI_T::STATUS: TXTHIF Position */
+#define SPI_STATUS_TXTHIF_Msk (0x1ul << SPI_STATUS_TXTHIF_Pos) /*!< SPI_T::STATUS: TXTHIF Mask */
+
+#define SPI_STATUS_TXUFIF_Pos (19) /*!< SPI_T::STATUS: TXUFIF Position */
+#define SPI_STATUS_TXUFIF_Msk (0x1ul << SPI_STATUS_TXUFIF_Pos) /*!< SPI_T::STATUS: TXUFIF Mask */
+
+#define SPI_STATUS_TXRXRST_Pos (23) /*!< SPI_T::STATUS: TXRXRST Position */
+#define SPI_STATUS_TXRXRST_Msk (0x1ul << SPI_STATUS_TXRXRST_Pos) /*!< SPI_T::STATUS: TXRXRST Mask */
+
+#define SPI_STATUS_RXCNT_Pos (24) /*!< SPI_T::STATUS: RXCNT Position */
+#define SPI_STATUS_RXCNT_Msk (0xful << SPI_STATUS_RXCNT_Pos) /*!< SPI_T::STATUS: RXCNT Mask */
+
+#define SPI_STATUS_TXCNT_Pos (28) /*!< SPI_T::STATUS: TXCNT Position */
+#define SPI_STATUS_TXCNT_Msk (0xful << SPI_STATUS_TXCNT_Pos) /*!< SPI_T::STATUS: TXCNT Mask */
+
+#define SPI_TX_TX_Pos (0) /*!< SPI_T::TX: TX Position */
+#define SPI_TX_TX_Msk (0xfffffffful << SPI_TX_TX_Pos) /*!< SPI_T::TX: TX Mask */
+
+#define SPI_RX_RX_Pos (0) /*!< SPI_T::RX: RX Position */
+#define SPI_RX_RX_Msk (0xfffffffful << SPI_RX_RX_Pos) /*!< SPI_T::RX: RX Mask */
+
+#define SPI_I2SCTL_I2SEN_Pos (0) /*!< SPI_T::I2SCTL: I2SEN Position */
+#define SPI_I2SCTL_I2SEN_Msk (0x1ul << SPI_I2SCTL_I2SEN_Pos) /*!< SPI_T::I2SCTL: I2SEN Mask */
+
+#define SPI_I2SCTL_TXEN_Pos (1) /*!< SPI_T::I2SCTL: TXEN Position */
+#define SPI_I2SCTL_TXEN_Msk (0x1ul << SPI_I2SCTL_TXEN_Pos) /*!< SPI_T::I2SCTL: TXEN Mask */
+
+#define SPI_I2SCTL_RXEN_Pos (2) /*!< SPI_T::I2SCTL: RXEN Position */
+#define SPI_I2SCTL_RXEN_Msk (0x1ul << SPI_I2SCTL_RXEN_Pos) /*!< SPI_T::I2SCTL: RXEN Mask */
+
+#define SPI_I2SCTL_MUTE_Pos (3) /*!< SPI_T::I2SCTL: MUTE Position */
+#define SPI_I2SCTL_MUTE_Msk (0x1ul << SPI_I2SCTL_MUTE_Pos) /*!< SPI_T::I2SCTL: MUTE Mask */
+
+#define SPI_I2SCTL_WDWIDTH_Pos (4) /*!< SPI_T::I2SCTL: WDWIDTH Position */
+#define SPI_I2SCTL_WDWIDTH_Msk (0x3ul << SPI_I2SCTL_WDWIDTH_Pos) /*!< SPI_T::I2SCTL: WDWIDTH Mask */
+
+#define SPI_I2SCTL_MONO_Pos (6) /*!< SPI_T::I2SCTL: MONO Position */
+#define SPI_I2SCTL_MONO_Msk (0x1ul << SPI_I2SCTL_MONO_Pos) /*!< SPI_T::I2SCTL: MONO Mask */
+
+#define SPI_I2SCTL_ORDER_Pos (7) /*!< SPI_T::I2SCTL: ORDER Position */
+#define SPI_I2SCTL_ORDER_Msk (0x1ul << SPI_I2SCTL_ORDER_Pos) /*!< SPI_T::I2SCTL: ORDER Mask */
+
+#define SPI_I2SCTL_SLAVE_Pos (8) /*!< SPI_T::I2SCTL: SLAVE Position */
+#define SPI_I2SCTL_SLAVE_Msk (0x1ul << SPI_I2SCTL_SLAVE_Pos) /*!< SPI_T::I2SCTL: SLAVE Mask */
+
+#define SPI_I2SCTL_MCLKEN_Pos (15) /*!< SPI_T::I2SCTL: MCLKEN Position */
+#define SPI_I2SCTL_MCLKEN_Msk (0x1ul << SPI_I2SCTL_MCLKEN_Pos) /*!< SPI_T::I2SCTL: MCLKEN Mask */
+
+#define SPI_I2SCTL_RZCEN_Pos (16) /*!< SPI_T::I2SCTL: RZCEN Position */
+#define SPI_I2SCTL_RZCEN_Msk (0x1ul << SPI_I2SCTL_RZCEN_Pos) /*!< SPI_T::I2SCTL: RZCEN Mask */
+
+#define SPI_I2SCTL_LZCEN_Pos (17) /*!< SPI_T::I2SCTL: LZCEN Position */
+#define SPI_I2SCTL_LZCEN_Msk (0x1ul << SPI_I2SCTL_LZCEN_Pos) /*!< SPI_T::I2SCTL: LZCEN Mask */
+
+#define SPI_I2SCTL_RXLCH_Pos (23) /*!< SPI_T::I2SCTL: RXLCH Position */
+#define SPI_I2SCTL_RXLCH_Msk (0x1ul << SPI_I2SCTL_RXLCH_Pos) /*!< SPI_T::I2SCTL: RXLCH Mask */
+
+#define SPI_I2SCTL_RZCIEN_Pos (24) /*!< SPI_T::I2SCTL: RZCIEN Position */
+#define SPI_I2SCTL_RZCIEN_Msk (0x1ul << SPI_I2SCTL_RZCIEN_Pos) /*!< SPI_T::I2SCTL: RZCIEN Mask */
+
+#define SPI_I2SCTL_LZCIEN_Pos (25) /*!< SPI_T::I2SCTL: LZCIEN Position */
+#define SPI_I2SCTL_LZCIEN_Msk (0x1ul << SPI_I2SCTL_LZCIEN_Pos) /*!< SPI_T::I2SCTL: LZCIEN Mask */
+
+#define SPI_I2SCTL_FORMAT_Pos (28) /*!< SPI_T::I2SCTL: FORMAT Position */
+#define SPI_I2SCTL_FORMAT_Msk (0x3ul << SPI_I2SCTL_FORMAT_Pos) /*!< SPI_T::I2SCTL: FORMAT Mask */
+
+#define SPI_I2SCLK_MCLKDIV_Pos (0) /*!< SPI_T::I2SCLK: MCLKDIV Position */
+#define SPI_I2SCLK_MCLKDIV_Msk (0x3ful << SPI_I2SCLK_MCLKDIV_Pos) /*!< SPI_T::I2SCLK: MCLKDIV Mask */
+
+#define SPI_I2SCLK_BCLKDIV_Pos (8) /*!< SPI_T::I2SCLK: BCLKDIV Position */
+#define SPI_I2SCLK_BCLKDIV_Msk (0x1fful << SPI_I2SCLK_BCLKDIV_Pos) /*!< SPI_T::I2SCLK: BCLKDIV Mask */
+
+#define SPI_I2SSTS_RIGHT_Pos (4) /*!< SPI_T::I2SSTS: RIGHT Position */
+#define SPI_I2SSTS_RIGHT_Msk (0x1ul << SPI_I2SSTS_RIGHT_Pos) /*!< SPI_T::I2SSTS: RIGHT Mask */
+
+#define SPI_I2SSTS_RXEMPTY_Pos (8) /*!< SPI_T::I2SSTS: RXEMPTY Position */
+#define SPI_I2SSTS_RXEMPTY_Msk (0x1ul << SPI_I2SSTS_RXEMPTY_Pos) /*!< SPI_T::I2SSTS: RXEMPTY Mask */
+
+#define SPI_I2SSTS_RXFULL_Pos (9) /*!< SPI_T::I2SSTS: RXFULL Position */
+#define SPI_I2SSTS_RXFULL_Msk (0x1ul << SPI_I2SSTS_RXFULL_Pos) /*!< SPI_T::I2SSTS: RXFULL Mask */
+
+#define SPI_I2SSTS_RXTHIF_Pos (10) /*!< SPI_T::I2SSTS: RXTHIF Position */
+#define SPI_I2SSTS_RXTHIF_Msk (0x1ul << SPI_I2SSTS_RXTHIF_Pos) /*!< SPI_T::I2SSTS: RXTHIF Mask */
+
+#define SPI_I2SSTS_RXOVIF_Pos (11) /*!< SPI_T::I2SSTS: RXOVIF Position */
+#define SPI_I2SSTS_RXOVIF_Msk (0x1ul << SPI_I2SSTS_RXOVIF_Pos) /*!< SPI_T::I2SSTS: RXOVIF Mask */
+
+#define SPI_I2SSTS_RXTOIF_Pos (12) /*!< SPI_T::I2SSTS: RXTOIF Position */
+#define SPI_I2SSTS_RXTOIF_Msk (0x1ul << SPI_I2SSTS_RXTOIF_Pos) /*!< SPI_T::I2SSTS: RXTOIF Mask */
+
+#define SPI_I2SSTS_I2SENSTS_Pos (15) /*!< SPI_T::I2SSTS: I2SENSTS Position */
+#define SPI_I2SSTS_I2SENSTS_Msk (0x1ul << SPI_I2SSTS_I2SENSTS_Pos) /*!< SPI_T::I2SSTS: I2SENSTS Mask */
+
+#define SPI_I2SSTS_TXEMPTY_Pos (16) /*!< SPI_T::I2SSTS: TXEMPTY Position */
+#define SPI_I2SSTS_TXEMPTY_Msk (0x1ul << SPI_I2SSTS_TXEMPTY_Pos) /*!< SPI_T::I2SSTS: TXEMPTY Mask */
+
+#define SPI_I2SSTS_TXFULL_Pos (17) /*!< SPI_T::I2SSTS: TXFULL Position */
+#define SPI_I2SSTS_TXFULL_Msk (0x1ul << SPI_I2SSTS_TXFULL_Pos) /*!< SPI_T::I2SSTS: TXFULL Mask */
+
+#define SPI_I2SSTS_TXTHIF_Pos (18) /*!< SPI_T::I2SSTS: TXTHIF Position */
+#define SPI_I2SSTS_TXTHIF_Msk (0x1ul << SPI_I2SSTS_TXTHIF_Pos) /*!< SPI_T::I2SSTS: TXTHIF Mask */
+
+#define SPI_I2SSTS_TXUFIF_Pos (19) /*!< SPI_T::I2SSTS: TXUFIF Position */
+#define SPI_I2SSTS_TXUFIF_Msk (0x1ul << SPI_I2SSTS_TXUFIF_Pos) /*!< SPI_T::I2SSTS: TXUFIF Mask */
+
+#define SPI_I2SSTS_RZCIF_Pos (20) /*!< SPI_T::I2SSTS: RZCIF Position */
+#define SPI_I2SSTS_RZCIF_Msk (0x1ul << SPI_I2SSTS_RZCIF_Pos) /*!< SPI_T::I2SSTS: RZCIF Mask */
+
+#define SPI_I2SSTS_LZCIF_Pos (21) /*!< SPI_T::I2SSTS: LZCIF Position */
+#define SPI_I2SSTS_LZCIF_Msk (0x1ul << SPI_I2SSTS_LZCIF_Pos) /*!< SPI_T::I2SSTS: LZCIF Mask */
+
+#define SPI_I2SSTS_TXRXRST_Pos (23) /*!< SPI_T::I2SSTS: TXRXRST Position */
+#define SPI_I2SSTS_TXRXRST_Msk (0x1ul << SPI_I2SSTS_TXRXRST_Pos) /*!< SPI_T::I2SSTS: TXRXRST Mask */
+
+#define SPI_I2SSTS_RXCNT_Pos (24) /*!< SPI_T::I2SSTS: RXCNT Position */
+#define SPI_I2SSTS_RXCNT_Msk (0x7ul << SPI_I2SSTS_RXCNT_Pos) /*!< SPI_T::I2SSTS: RXCNT Mask */
+
+#define SPI_I2SSTS_TXCNT_Pos (28) /*!< SPI_T::I2SSTS: TXCNT Position */
+#define SPI_I2SSTS_TXCNT_Msk (0x7ul << SPI_I2SSTS_TXCNT_Pos) /*!< SPI_T::I2SSTS: TXCNT Mask */
+
+/**@}*/ /* SPI_CONST */
+/**@}*/ /* end of SPI register group */
+
+
+/*---------------------- System Manger Controller -------------------------*/
+/**
+ @addtogroup SYS System Manger Controller(SYS)
+ Memory Mapped Structure for SYS Controller
+@{ */
+
+
+typedef struct
+{
+
+/**
+ * @var SYS_T::PDID
+ * Offset: 0x00 Part Device Identification Number Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |PDID |Part Device Identification Number (Read Only)
+ * | | |This register reflects device part number code.
+ * | | |Software can read this register to identify which device is used.
+ * @var SYS_T::RSTSTS
+ * Offset: 0x04 System Reset Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |PORF |POR Reset Flag
+ * | | |The POR reset flag is set by the "Reset Signal" from the Power-On Reset (POR) Controller or bit CHIPRST (SYS_IPRST0[0]) to indicate the previous reset source.
+ * | | |0 = No reset from POR or CHIPRST.
+ * | | |1 = Power-On Reset (POR) or CHIPRST had issued the reset signal to reset the system.
+ * | | |Note: Write 1 to clear this bit to 0.
+ * |[1] |PINRF |nRESET Pin Reset Flag
+ * | | |The nRESET pin reset flag is set by the "Reset Signal" from the nRESET Pin to indicate the previous reset source.
+ * | | |0 = No reset from nRESET pin.
+ * | | |1 = Pin nRESET had issued the reset signal to reset the system.
+ * | | |Note: Write 1 to clear this bit to 0.
+ * |[2] |WDTRF |WDT Reset Flag
+ * | | |The WDT reset flag is set by the "Reset Signal" from the Watchdog Timer or Window Watchdog Timer to indicate the previous reset source.
+ * | | |0 = No reset from watchdog timer or window watchdog timer.
+ * | | |1 = The watchdog timer or window watchdog timer had issued the reset signal to reset the system.
+ * | | |Note1:
+ * | | |Write 1 to clear this bit to 0.
+ * | | |Note2: Watchdog Timer register RSTF(WDT_CTL[2]) bit is set if the system has been reset by WDT time-out reset.
+ * | | |Window Watchdog Timer register WWDTRF(WWDT_STATUS[1]) bit is set if the system has been reset by WWDT time-out reset.
+ * |[3] |LVRF |LVR Reset Flag
+ * | | |The LVR reset flag is set by the "Reset Signal" from the Low-Voltage-Reset Controller to indicate the previous reset source.
+ * | | |0 = No reset from LVR.
+ * | | |1 = LVR controller had issued the reset signal to reset the system.
+ * | | |Note: Write 1 to clear this bit to 0.
+ * |[4] |BODRF |BOD Reset Flag
+ * | | |The BOD reset flag is set by the "Reset Signal" from the Brown-Out-Detector to indicate the previous reset source.
+ * | | |0 = No reset from BOD.
+ * | | |1 = The BOD had issued the reset signal to reset the system.
+ * | | |Note: Write 1 to clear this bit to 0.
+ * |[5] |SYSRF |System Reset Flag
+ * | | |The system reset flag is set by the "Reset Signal" from the Cortex-M4 Core to indicate the previous reset source.
+ * | | |0 = No reset from Cortex-M4.
+ * | | |1 = The Cortex-M4 had issued the reset signal to reset the system by writing 1 to the bit SYSRESETREQ(AIRCR[2], Application Interrupt and Reset Control Register, address = 0xE000ED0C) in system control registers of Cortex-M4 core.
+ * | | |Note: Write 1 to clear this bit to 0.
+ * |[7] |CPURF |CPU Reset Flag
+ * | | |The CPU reset flag is set by hardware if software writes CPURST (SYS_IPRST0[1]) 1 to reset Cortex-M4 Core and Flash Memory Controller (FMC).
+ * | | |0 = No reset from CPU.
+ * | | |1 = The Cortex-M4 Core and FMC are reset by software setting CPURST to 1.
+ * | | |Note: Write 1 to clear this bit to 0.
+ * |[8] |CPULKRF |CPU Lockup Reset Flag
+ * | | |The CPU reset flag is set by hardware if Cortex-M4 lockup happened.
+ * | | |0 = No reset from CPU lockup happened.
+ * | | |1 = The Cortex-M4 lockup happened and chip is reset.
+ * | | |Note: Write 1 to clear this bit to 0.
+ * @var SYS_T::IPRST0
+ * Offset: 0x08 Peripheral Reset Control Register 0
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |CHIPRST |Chip One-Shot Reset (Write Protect)
+ * | | |Setting this bit will reset the whole chip, including Processor core and all peripherals, and this bit will automatically return to 0 after the 2 clock cycles.
+ * | | |The CHIPRST is same as the POR reset, all the chip controllers is reset and the chip setting from flash are also reload.
+ * | | |About the difference between CHIPRST and SYSRESETREQ, please refer to section 5.2.2
+ * | | |0 = Chip normal operation.
+ * | | |1 = Chip one shot reset.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[1] |CPURST |Processor Core One-Shot Reset (Write Protect)
+ * | | |Setting this bit will only reset the processor core and Flash Memory Controller(FMC), and this bit will automatically return to 0 after the 2 clock cycles.
+ * | | |0 = Processor core normal operation.
+ * | | |1 = Processor core one-shot reset.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[2] |PDMARST |PDMA Controller Reset (Write Protect)
+ * | | |Setting this bit to 1 will generate a reset signal to the PDMA.
+ * | | |User needs to set this bit to 0 to release from reset state.
+ * | | |0 = PDMA controller normal operation.
+ * | | |1 = PDMA controller reset.
+ * |[3] |EBIRST |EBI Controller Reset (Write Protect)
+ * | | |Set this bit to 1 will generate a reset signal to the EBI.
+ * | | |User needs to set this bit to 0 to release from the reset state.
+ * | | |0 = EBI controller normal operation.
+ * | | |1 = EBI controller reset.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[4] |USBHRST |USBH Controller Reset (Write Protect)
+ * | | |Set this bit to 1 will generate a reset signal to the USB host controller.
+ * | | |User needs to set this bit to 0 to release from the reset state.
+ * | | |0 = USBH controller normal operation.
+ * | | |1 = USBH controller reset.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[7] |CRCRST |CRC Calculation Unit Reset (Write Protect)
+ * | | |Set this bit to 1 will generate a reset signal to the CRC calculation module.
+ * | | |User needs to set this bit to 0 to release from the reset state.
+ * | | |0 = CRC Calculation unit normal operation.
+ * | | |1 = CRC Calculation unit reset.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * @var SYS_T::IPRST1
+ * Offset: 0x0C Peripheral Reset Control Register 1
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[1] |GPIORST |GPIO Controller Reset
+ * | | |0 = GPIO controller normal operation.
+ * | | |1 = GPIO controller reset.
+ * |[2] |TMR0RST |Timer0 Controller Reset
+ * | | |0 = Timer0 controller normal operation.
+ * | | |1 = Timer0 controller reset.
+ * |[3] |TMR1RST |Timer1 Controller Reset
+ * | | |0 = Timer1 controller normal operation.
+ * | | |1 = Timer1 controller reset.
+ * |[4] |TMR2RST |Timer2 Controller Reset
+ * | | |0 = Timer2 controller normal operation.
+ * | | |1 = Timer2 controller reset.
+ * |[5] |TMR3RST |Timer3 Controller Reset
+ * | | |0 = Timer3 controller normal operation.
+ * | | |1 = Timer3 controller reset.
+ * |[7] |ACMP01RST |Analog Comparator 0/1 Controller Reset
+ * | | |0 = Analog Comparator 0/1 controller normal operation.
+ * | | |1 = Analog Comparator 0/1 controller reset.
+ * |[8] |I2C0RST |I2C0 Controller Reset
+ * | | |0 = I2C0 controller normal operation.
+ * | | |1 = I2C0 controller reset.
+ * |[9] |I2C1RST |I2C1 Controller Reset
+ * | | |0 = I2C1 controller normal operation.
+ * | | |1 = I2C1 controller reset.
+ * |[12] |SPI0RST |SPI0 Controller Reset
+ * | | |0 = SPI0 controller normal operation.
+ * | | |1 = SPI0 controller reset.
+ * |[13] |SPI1RST |SPI1 Controller Reset
+ * | | |0 = SPI1 controller normal operation.
+ * | | |1 = SPI1 controller reset.
+ * |[14] |SPI2RST |SPI2 Controller Reset
+ * | | |0 = SPI2 controller normal operation.
+ * | | |1 = SPI2 controller reset.
+ * |[16] |UART0RST |UART0 Controller Reset
+ * | | |0 = UART0 controller normal operation.
+ * | | |1 = UART0 controller reset.
+ * |[17] |UART1RST |UART1 Controller Reset
+ * | | |0 = UART1 controller normal operation.
+ * | | |1 = UART1 controller reset.
+ * |[18] |UART2RST |UART2 Controller Reset
+ * | | |0 = UART2 controller normal operation.
+ * | | |1 = UART2 controller reset.
+ * |[19] |UART3RST |UART3 Controller Reset
+ * | | |0 = UART3 controller normal operation.
+ * | | |1 = UART3 controller reset.
+ * |[24] |CAN0RST |CAN0 Controller Reset
+ * | | |0 = CAN0 controller normal operation.
+ * | | |1 = CAN0 controller reset.
+ * |[26] |OTGRST |OTG Controller Reset
+ * | | |0 = OTG controller normal operation.
+ * | | |1 = OTG controller reset.
+ * |[27] |USBDRST |USB Device Controller Reset
+ * | | |0 = USB device controller normal operation.
+ * | | |1 = USB device controller reset.
+ * |[28] |EADCRST |EADC Controller Reset
+ * | | |0 = EADC controller normal operation.
+ * | | |1 = EADC controller reset.
+ * @var SYS_T::IPRST2
+ * Offset: 0x10 Peripheral Reset Control Register 2
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |SC0RST |SC0 Controller Reset
+ * | | |0 = SC0 controller normal operation.
+ * | | |1 = SC0 controller reset.
+ * |[12] |DACRST |DAC Controller Reset
+ * | | |0 = DAC controller normal operation.
+ * | | |1 = DAC controller reset.
+ * |[16] |PWM0RST |PWM0 Controller Reset
+ * | | |0 = PWM0 controller normal operation.
+ * | | |1 = PWM0 controller reset.
+ * |[17] |PWM1RST |PWM1 Controller Reset
+ * | | |0 = PWM1 controller normal operation.
+ * | | |1 = PWM1 controller reset.
+ * |[25] |TKRST |Touch Key Controller Reset
+ * | | |0 = Touch Key controller normal operation.
+ * | | |1 = Touch Key controller reset.
+ * @var SYS_T::BODCTL
+ * Offset: 0x18 Brown-Out Detector Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |BODEN |Brown-Out Detector Enable Bit (Write Protect)
+ * | | |The default value is set by flash controller user configuration register CBODEN (CONFIG0 [23]).
+ * | | |0 = Brown-out Detector function Disabled.
+ * | | |1 = Brown-out Detector function Enabled.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[2:1] |BODVL |Brown-Out Detector Threshold Voltage Selection (Write Protect)
+ * | | |The default value is set by flash controller user configuration register CBOV (CONFIG0 [22:21]).
+ * | | |00 = Brown-Out Detector Threshold Voltage is 2.2V
+ * | | |01 = Brown-Out Detector Threshold Voltage is 2.7V
+ * | | |10 = Brown-Out Detector Threshold Voltage is 3.7V
+ * | | |11 = Brown-Out Detector Threshold Voltage is 4.5V
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[3] |BODRSTEN |Brown-Out Reset Enable Bit (Write Protect)
+ * | | |The default value is set by flash controller user configuration register CBORST(CONFIG0[20]) bit .
+ * | | |0 = Brown-out "INTERRUPT" function Enabled.
+ * | | |1 = Brown-out "RESET" function Enabled.
+ * | | |Note1:
+ * | | |While the Brown-out Detector function is enabled (BODEN high) and BOD reset function is enabled (BODRSTEN high), BOD will assert a signal to reset chip when the detected voltage is lower than the threshold (BODOUT high).
+ * | | |While the BOD function is enabled (BODEN high) and BOD interrupt function is enabled (BODRSTEN low), BOD will assert an interrupt if BODOUT is high.
+ * | | |BOD interrupt will keep till to the BODEN set to 0.
+ * | | |BOD interrupt can be blocked by disabling the NVIC BOD interrupt or disabling BOD function (set BODEN low).
+ * | | |Note2: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[4] |BODIF |Brown-Out Detector Interrupt Flag
+ * | | |0 = Brown-out Detector does not detect any voltage draft at VDD down through or up through the voltage of BODVL setting.
+ * | | |1 = When Brown-out Detector detects the VDD is dropped down through the voltage of BODVL setting or the VDD is raised up through the voltage of BODVL setting, this bit is set to 1 and the brown-out interrupt is requested if brown-out interrupt is enabled.
+ * | | |Note: Write 1 to clear this bit to 0.
+ * |[5] |BODLPM |Brown-Out Detector Low Power Mode (Write Protect)
+ * | | |0 = BOD operate in normal mode (default).
+ * | | |1 = BOD Low Power mode Enabled.
+ * | | |Note1: The BOD consumes about 100uA in normal mode, the low power mode can reduce the current to about 1/10 but slow the BOD response.
+ * | | |Note2: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[6] |BODOUT |Brown-Out Detector Output Status
+ * | | |0 = Brown-out Detector output status is 0.
+ * | | |It means the detected voltage is higher than BODVL setting or BODEN is 0.
+ * | | |1 = Brown-out Detector output status is 1.
+ * | | |It means the detected voltage is lower than BODVL setting.
+ * | | |If the BODEN is 0, BOD function disabled , this bit always responds 0000.
+ * |[7] |LVREN |Low Voltage Reset Enable Bit (Write Protect)
+ * | | |The LVR function resets the chip when the input power voltage is lower than LVR circuit setting.
+ * | | |LVR function is enabled by default.
+ * | | |0 = Low Voltage Reset function Disabled.
+ * | | |1 = Low Voltage Reset function Enabled
+ * | | |Note1: After enabling the bit, the LVR function will be active with 100us delay for LVR output stable (default).
+ * | | |Note2: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[10:8] |BODDGSEL |Brown-Out Detector Output De-Glitch Time Select (Write Protect)
+ * | | |000 = BOD output is sampled by RC10K clock.
+ * | | |001 = 4 system clock (HCLK).
+ * | | |010 = 8 system clock (HCLK).
+ * | | |011 = 16 system clock (HCLK).
+ * | | |100 = 32 system clock (HCLK).
+ * | | |101 = 64 system clock (HCLK).
+ * | | |110 = 128 system clock (HCLK).
+ * | | |111 = 256 system clock (HCLK).
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[14:12] |LVRDGSEL |LVR Output De-Glitch Time Select (Write Protect)
+ * | | |000 = Without de-glitch function.
+ * | | |001 = 4 system clock (HCLK).
+ * | | |010 = 8 system clock (HCLK).
+ * | | |011 = 16 system clock (HCLK).
+ * | | |100 = 32 system clock (HCLK).
+ * | | |101 = 64 system clock (HCLK).
+ * | | |110 = 128 system clock (HCLK).
+ * | | |111 = 256 system clock (HCLK).
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * @var SYS_T::IVSCTL
+ * Offset: 0x1C Internal Voltage Source Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |VTEMPEN |Temperature Sensor Enable Bit
+ * | | |This bit is used to enable/disable temperature sensor function.
+ * | | |0 = Temperature sensor function Disabled (default).
+ * | | |1 = Temperature sensor function Enabled.
+ * | | |Note: After this bit is set to 1, the value of temperature sensor output can be obtained from ADC conversion result.
+ * | | |Please refer to ADC function chapter for details.
+ * |[1] |VBATUGEN |VBAT Unity Gain Buffer Enable Bit
+ * | | |This bit is used to enable/disable VBAT unity gain buffer function.
+ * | | |0 = VBAT unity gain buffer function Disabled (default).
+ * | | |1 = VBAT unity gain buffer function Enabled.
+ * | | |Note: After this bit is set to 1, the value of VBAT unity gain buffer output voltage can be obtained from ADC conversion result
+ * @var SYS_T::PORCTL
+ * Offset: 0x24 Power-On-Reset Controller Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |POROFF |Power-On-Reset Enable Bit (Write Protect)
+ * | | |When powered on, the POR circuit generates a reset signal to reset the whole chip function, but noise on the power may cause the POR active again.
+ * | | |User can disable internal POR circuit to avoid unpredictable noise to cause chip reset by writing 0x5AA5 to this field.
+ * | | |The POR function will be active again when this field is set to another value or chip is reset by other reset source, including:
+ * | | |nRESET, Watchdog, LVR reset, BOD reset, ICE reset command and the software-chip reset function
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * @var SYS_T::VREFCTL
+ * Offset: 0x28 VREF Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[4:0] |VREFCTL |VREF Control Bits (Write Protect)
+ * | | |00011 = VREF is internal 2.65V.
+ * | | |00111 = VREF is internal 2.048V.
+ * | | |01011 = VREF is internal 3.072V.
+ * | | |01111 = VREF is internal 4.096V.
+ * | | |Others = Reserved.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * @var SYS_T::USBPHY
+ * Offset: 0x2C USB PHY Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[1:0] |USBROLE |USB Role Option (Write Protect)
+ * | | |These two bits are used to select the role of USB.
+ * | | |00 = Standard USB Device mode.
+ * | | |01 = Standard USB Host mode.
+ * | | |10 = ID dependent mode.
+ * | | |11 = On-The-Go device mode.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[8] |LDO33EN |USB LDO33 Enable Bit (Write Protect)
+ * | | |0 = USB LDO33 Disabled.
+ * | | |1 = USB LDO33 Enabled.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * @var SYS_T::GPA_MFPL
+ * Offset: 0x30 GPIOA Low Byte Multiple Function Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[3:0] |PA0MFP |PA.0 Multi-function Pin Selection
+ * |[7:4] |PA1MFP |PA.1 Multi-function Pin Selection
+ * |[11:8] |PA2MFP |PA.2 Multi-function Pin Selection
+ * |[15:12] |PA3MFP |PA.3 Multi-function Pin Selection
+ * |[19:16] |PA4MFP |PA.4 Multi-function Pin Selection
+ * |[23:20] |PA5MFP |PA.5 Multi-function Pin Selection
+ * |[27:24] |PA6MFP |PA.6 Multi-function Pin Selection
+ * |[31:28] |PA7MFP |PA.7 Multi-function Pin Selection
+ * @var SYS_T::GPA_MFPH
+ * Offset: 0x34 GPIOA High Byte Multiple Function Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[3:0] |PA8MFP |PA.8 Multi-function Pin Selection
+ * |[7:4] |PA9MFP |PA.9 Multi-function Pin Selection
+ * |[11:8] |PA10MFP |PA.10 Multi-function Pin Selection
+ * |[15:12] |PA11MFP |PA.11 Multi-function Pin Selection
+ * |[19:16] |PA12MFP |PA.12 Multi-function Pin Selection
+ * |[23:20] |PA13MFP |PA.13 Multi-function Pin Selection
+ * |[27:24] |PA14MFP |PA.14 Multi-function Pin Selection
+ * |[31:28] |PA15MFP |PA.15 Multi-function Pin Selection
+ * @var SYS_T::GPB_MFPL
+ * Offset: 0x38 GPIOB Low Byte Multiple Function Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[3:0] |PB0MFP |PB.0 Multi-function Pin Selection
+ * |[7:4] |PB1MFP |PB.1 Multi-function Pin Selection
+ * |[11:8] |PB2MFP |PB.2 Multi-function Pin Selection
+ * |[15:12] |PB3MFP |PB.3 Multi-function Pin Selection
+ * |[19:16] |PB4MFP |PB.4 Multi-function Pin Selection
+ * |[23:20] |PB5MFP |PB.5 Multi-function Pin Selection
+ * |[27:24] |PB6MFP |PB.6 Multi-function Pin Selection
+ * |[31:28] |PB7MFP |PB.7 Multi-function Pin Selection
+ * @var SYS_T::GPB_MFPH
+ * Offset: 0x3C GPIOB High Byte Multiple Function Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[3:0] |PB8MFP |PB.8 Multi-function Pin Selection
+ * |[7:4] |PB9MFP |PB.9 Multi-function Pin Selection
+ * |[11:8] |PB10MFP |PB.10 Multi-function Pin Selection
+ * |[15:12] |PB11MFP |PB.11 Multi-function Pin Selection
+ * |[19:16] |PB12MFP |PB.12 Multi-function Pin Selection
+ * |[23:20] |PB13MFP |PB.13 Multi-function Pin Selection
+ * |[27:24] |PB14MFP |PB.14 Multi-function Pin Selection
+ * |[31:28] |PB15MFP |PB.15 Multi-function Pin Selection
+ * @var SYS_T::GPC_MFPL
+ * Offset: 0x40 GPIOC Low Byte Multiple Function Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[3:0] |PC0MFP |PC.0 Multi-function Pin Selection
+ * |[7:4] |PC1MFP |PC.1 Multi-function Pin Selection
+ * |[11:8] |PC2MFP |PC.2 Multi-function Pin Selection
+ * |[15:12] |PC3MFP |PC.3 Multi-function Pin Selection
+ * |[19:16] |PC4MFP |PC.4 Multi-function Pin Selection
+ * |[23:20] |PC5MFP |PC.5 Multi-function Pin Selection
+ * |[27:24] |PC6MFP |PC.6 Multi-function Pin Selection
+ * |[31:28] |PC7MFP |PC.7 Multi-function Pin Selection
+ * @var SYS_T::GPC_MFPH
+ * Offset: 0x44 GPIOC High Byte Multiple Function Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[3:0] |PC8MFP |PC.8 Multi-function Pin Selection
+ * |[7:4] |PC9MFP |PC.9 Multi-function Pin Selection
+ * |[11:8] |PC10MFP |PC.10 Multi-function Pin Selection
+ * |[15:12] |PC11MFP |PC.11 Multi-function Pin Selection
+ * |[19:16] |PC12MFP |PC.12 Multi-function Pin Selection
+ * |[23:20] |PC13MFP |PC.13 Multi-function Pin Selection
+ * |[27:24] |PC14MFP |PC.14 Multi-function Pin Selection
+ * |[31:28] |PC15MFP |PC.15 Multi-function Pin Selection
+ * @var SYS_T::GPD_MFPL
+ * Offset: 0x48 GPIOD Low Byte Multiple Function Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[3:0] |PD0MFP |PD.0 Multi-function Pin Selection
+ * |[7:4] |PD1MFP |PD.1 Multi-function Pin Selection
+ * |[11:8] |PD2MFP |PD.2 Multi-function Pin Selection
+ * |[15:12] |PD3MFP |PD.3 Multi-function Pin Selection
+ * |[19:16] |PD4MFP |PD.4 Multi-function Pin Selection
+ * |[23:20] |PD5MFP |PD.5 Multi-function Pin Selection
+ * |[27:24] |PD6MFP |PD.6 Multi-function Pin Selection
+ * |[31:28] |PD7MFP |PD.7 Multi-function Pin Selection
+ * @var SYS_T::GPD_MFPH
+ * Offset: 0x4C GPIOD High Byte Multiple Function Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[3:0] |PD8MFP |PD.8 Multi-function Pin Selection
+ * |[7:4] |PD9MFP |PD.9 Multi-function Pin Selection
+ * |[11:8] |PD10MFP |PD.10 Multi-function Pin Selection
+ * |[15:12] |PD11MFP |PD.11 Multi-function Pin Selection
+ * |[19:16] |PD12MFP |PD.12 Multi-function Pin Selection
+ * |[23:20] |PD13MFP |PD.13 Multi-function Pin Selection
+ * |[27:24] |PD14MFP |PD.14 Multi-function Pin Selection
+ * |[31:28] |PD15MFP |PD.15 Multi-function Pin Selection
+ * @var SYS_T::GPE_MFPL
+ * Offset: 0x50 GPIOE Low Byte Multiple Function Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[3:0] |PE0MFP |PE.0 Multi-function Pin Selection
+ * |[7:4] |PE1MFP |PE.1 Multi-function Pin Selection
+ * |[11:8] |PE2MFP |PE.2 Multi-function Pin Selection
+ * |[15:12] |PE3MFP |PE.3 Multi-function Pin Selection
+ * |[19:16] |PE4MFP |PE.4 Multi-function Pin Selection
+ * |[23:20] |PE5MFP |PE.5 Multi-function Pin Selection
+ * |[27:24] |PE6MFP |PE.6 Multi-function Pin Selection
+ * |[31:28] |PE7MFP |PE.7 Multi-function Pin Selection
+ * @var SYS_T::GPE_MFPH
+ * Offset: 0x54 GPIOE High Byte Multiple Function Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[3:0] |PE8MFP |PE.8 Multi-function Pin Selection
+ * |[7:4] |PE9MFP |PE.9 Multi-function Pin Selection
+ * |[11:8] |PE10MFP |PE.10 Multi-function Pin Selection
+ * |[15:12] |PE11MFP |PE.11 Multi-function Pin Selection
+ * |[19:16] |PE12MFP |PE.12 Multi-function Pin Selection
+ * |[23:20] |PE13MFP |PE.13 Multi-function Pin Selection
+ * |[27:24] |PE14_MFP |PE.14 Multi-function Pin Selection
+ * @var SYS_T::GPF_MFPL
+ * Offset: 0x58 GPIOF Low Byte Multiple Function Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[3:0] |PF0MFP |PF.0 Multi-function Pin Selection
+ * |[7:4] |PF1MFP |PF.1 Multi-function Pin Selection
+ * |[11:8] |PF2MFP |PF.2 Multi-function Pin Selection
+ * |[15:12] |PF3MFP |PF.3 Multi-function Pin Selection
+ * |[19:16] |PF4MFP |PF.4 Multi-function Pin Selection
+ * |[23:20] |PF5MFP |PF.5 Multi-function Pin Selection
+ * |[27:24] |PF6MFP |PF.6 Multi-function Pin Selection
+ * |[31:28] |PF7MFP |PF.7 Multi-function Pin Selection
+ * @var SYS_T::SRAM_INTCTL
+ * Offset: 0xC0 System SRAM Interrupt Enable Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |PERRIEN |SRAM Parity Check Error Interrupt Enable Bit
+ * | | |0 = SRAM parity check error interrupt Disabled.
+ * | | |1 = SRAM parity check error interrupt Enabled.
+ * @var SYS_T::SRAM_STATUS
+ * Offset: 0xC4 System SRAM Parity Error Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |PERRIF |SRAM Parity Check Error Flag
+ * | | |0 = No System SRAM parity error.
+ * | | |1 = System SRAM parity error occur.
+ * @var SYS_T::SRAM_ERRADDR
+ * Offset: 0xC8 System SRAM Parity Check Error Address Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |ERRADDR |System SRAM Parity Error Address
+ * | | |This register shows system SRAM parity error byte address.
+ * @var SYS_T::SRAM_BISTCTL
+ * Offset: 0xD0 System SRAM BIST Test Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |SRBIST0 |1st
+ * | | |SRAM BIST Enable Bit
+ * | | |This bit enables BIST test for SRAM located in address 0x2000_0000 ~0x2000_3FFF
+ * | | |0 = system SRAM BIST Disabled.
+ * | | |1 = system SRAM BIST Enabled.
+ * |[1] |SRBIST1 |2nd
+ * | | |SRAM BIST Enable Bit
+ * | | |This bit enables BIST test for SRAM located in address 0x2000_4000 ~0x2000_7FFF
+ * | | |0 = system SRAM BIST Disabled.
+ * | | |1 = system SRAM BIST Enabled.
+ * |[2] |CRBIST |CACHE BIST Enable Bit
+ * | | |This bit enables BIST test for CACHE RAM
+ * | | |0 = system CACHE BIST Disabled.
+ * | | |1 = system CACHE BIST Enabled.
+ * |[3] |CANBIST |CAN BIST Enable Bit
+ * | | |This bit enables BIST test for CAN RAM
+ * | | |0 = system CAN BIST Disabled.
+ * | | |1 = system CAN BIST Enabled.
+ * |[4] |USBBIST |USB BIST Enable Bit
+ * | | |This bit enables BIST test for USB RAM
+ * | | |0 = system USB BIST Disabled.
+ * | | |1 = system USB BIST Enabled.
+ * @var SYS_T::SRAM_BISTSTS
+ * Offset: 0xD4 System SRAM BIST Test Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |SRBISTEF0 |1st System SRAM BIST Fail Flag
+ * | | |0 = 1st system SRAM BIST test pass.
+ * | | |1 = 1st system SRAM BIST test fail.
+ * |[1] |SRBISTEF1 |2nd System SRAM BIST Fail Flag
+ * | | |0 = 2nd system SRAM BIST test pass.
+ * | | |1 = 2nd system SRAM BIST test fail.
+ * |[2] |CRBISTEF |CACHE SRAM BIST Fail Flag
+ * | | |0 = System CACHE RAM BIST test pass.
+ * | | |1 = System CACHE RAM BIST test fail.
+ * |[3] |CANBEF |CAN SRAM BIST Fail Flag
+ * | | |0 = CAN SRAM BIST test pass.
+ * | | |1 = CAN SRAM BIST test fail.
+ * |[4] |USBBEF |USB SRAM BIST Fail Flag
+ * | | |0 = USB SRAM BIST test pass.
+ * | | |1 = USB SRAM BIST test fail.
+ * |[16] |SRBEND0 |1st SRAM BIST Test Finish
+ * | | |0 = 1st system SRAM BIST active.
+ * | | |1 = 1st system SRAM BIST finish.
+ * |[17] |SRBEND1 |2nd SRAM BIST Test Finish
+ * | | |0 = 2nd system SRAM BIST is active.
+ * | | |1 = 2nd system SRAM BIST finish.
+ * |[18] |CRBEND |CACHE SRAM BIST Test Finish
+ * | | |0 = System CACHE RAM BIST is active.
+ * | | |1 = System CACHE RAM BIST test finish.
+ * |[19] |CANBEND |CAN SRAM BIST Test Finish
+ * | | |0 = CAN SRAM BIST is active.
+ * | | |1 = CAN SRAM BIST test finish.
+ * |[20] |USBBEND |USB SRAM BIST Test Finish
+ * | | |0 = USB SRAM BIST is active.
+ * | | |1 = USB SRAM BIST test finish.
+ * @var SYS_T::IRCTCTL
+ * Offset: 0xF0 IRC Trim Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[1:0] |FREQSEL |Trim Frequency Selection
+ * | | |This field indicates the target frequency of internal 22.1184 MHz high-speed oscillator auto trim.
+ * | | |During auto trim operation, if clock error detected with CESTOPEN is set to 1 or trim retry limitation count reached, this field will be cleared to 00 automatically.
+ * | | |00 = Disable HIRC auto trim function.
+ * | | |01 = Enable HIRC auto trim function and trim HIRC to 22.1184 MHz.
+ * | | |10 = Enable HIRC auto trim function and trim HIRC to 24 MHz.
+ * | | |11 = Reserved.
+ * |[5:4] |LOOPSEL |Trim Calculation Loop Selection
+ * | | |This field defines that trim value calculation is based on how many 32.768 kHz clock.
+ * | | |00 = Trim value calculation is based on average difference in 4 32.768 kHz clock.
+ * | | |01 = Trim value calculation is based on average difference in 8 32.768 kHz clock.
+ * | | |10 = Trim value calculation is based on average difference in 16 32.768 kHz clock.
+ * | | |11 = Trim value calculation is based on average difference in 32 32.768 kHz clock.
+ * | | |Note: For example, if LOOPSEL is set as 00, auto trim circuit will calculate trim value based on the average frequency difference in 4 32.768 kHz clock.
+ * |[7:6] |RETRYCNT |Trim Value Update Limitation Count
+ * | | |This field defines that how many times the auto trim circuit will try to update the HIRC trim value before the frequency of HIRC locked.
+ * | | |Once the HIRC locked, the internal trim value update counter will be reset.
+ * | | |If the trim value update counter reached this limitation value and frequency of HIRC still doesn't lock, the auto trim operation will be disabled and FREQSEL will be cleared to 00.
+ * | | |00 = Trim retry count limitation is 64 loops.
+ * | | |01 = Trim retry count limitation is 128 loops.
+ * | | |10 = Trim retry count limitation is 256 loops.
+ * | | |11 = Trim retry count limitation is 512 loops.
+ * |[8] |CESTOPEN |Clock Error Stop Enable Bit
+ * | | |0 = The trim operation is keep going if clock is inaccuracy.
+ * | | |1 = The trim operation is stopped if clock is inaccuracy.
+ * @var SYS_T::IRCTIEN
+ * Offset: 0xF4 IRC Trim Interrupt Enable Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[1] |TFAILIEN |Trim Failure Interrupt Enable Bit
+ * | | |This bit controls if an interrupt will be triggered while HIRC trim value update limitation count reached and HIRC frequency still not locked on target frequency set by FREQSEL(SYS_IRCTCTL[1:0]).
+ * | | |If this bit is high and TFAILIF(SYS_IRCTSTS[1]) is set during auto trim operation, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached.
+ * | | |0 = Disable TFAILIF(SYS_IRCTSTS[1]) status to trigger an interrupt to CPU.
+ * | | |1 = Enable TFAILIF(SYS_IRCTSTS[1]) status to trigger an interrupt to CPU.
+ * |[2] |CLKEIEN |Clock Error Interrupt Enable Bit
+ * | | |This bit controls if CPU would get an interrupt while clock is inaccuracy during auto trim operation.
+ * | | |If this bit is set to1, and CLKERRIF(SYS_IRCTSTS[2]) is set during auto trim operation, an interrupt will be triggered to notify the clock frequency is inaccuracy.
+ * | | |0 = Disable CLKERRIF(SYS_IRCTSTS[2]) status to trigger an interrupt to CPU.
+ * | | |1 = Enable CLKERRIF(SYS_IRCTSTS[2]) status to trigger an interrupt to CPU.
+ * @var SYS_T::IRCTISTS
+ * Offset: 0xF8 IRC Trim Interrupt Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |FREQLOCK |HIRC Frequency Lock Status
+ * | | |This bit indicates the internal 22.1184 MHz high-speed oscillator frequency is locked.
+ * | | |This is a status bit and doesn't trigger any interrupt.
+ * |[1] |TFAILIF |Trim Failure Interrupt Status
+ * | | |This bit indicates that internal 22.1184 MHz high-speed oscillator trim value update limitation count reached and the internal 22.1184 MHz high-speed oscillator clock frequency still doesn't be locked.
+ * | | |Once this bit is set, the auto trim operation stopped and FREQSEL(SYS_iRCTCTL[1:0]) will be cleared to 00 by hardware automatically.
+ * | | |If this bit is set and TFAILIEN(SYS_IRCTIEN[1]) is high, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached.
+ * | | |Write 1 to clear this to 0.
+ * | | |0 = Trim value update limitation count does not reach.
+ * | | |1 = Trim value update limitation count reached and internal 22.1184 MHz high-speed oscillator frequency still not locked.
+ * |[2] |CLKERRIF |Clock Error Interrupt Status
+ * | | |When the frequency of external 32.768 kHz low-speed crystal or internal 22.1184 MHz high-speed oscillator is shift larger to unreasonable value, this bit will be set and to be an indicate that clock frequency is inaccuracy
+ * | | |Once this bit is set to 1, the auto trim operation stopped and FREQSEL(SYS_IRCTCL[1:0]) will be cleared to 00 by hardware automatically if CESTOPEN(SYS_IRCTCTL[8]) is set to 1.
+ * | | |If this bit is set and CLKEIEN(SYS_IRCTIEN[2]) is high, an interrupt will be triggered to notify the clock frequency is inaccuracy.
+ * | | |Write 1 to clear this to 0.
+ * | | |0 = Clock frequency is accuracy.
+ * | | |1 = Clock frequency is inaccuracy.
+ * @var SYS_T::REGLCTL
+ * Offset: 0x100 Register Lock Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:0] |REGLCTL |Register Lock Control Code
+ * | | |Write operation:
+ * | | |Some registers have write-protection function.
+ * | | |Writing these registers have to disable the protected function by writing the sequence value "59h", "16h", "88h" to this field.
+ * | | |After this sequence is completed, the REGLCTL bit will be set to 1 and write-protection registers can be normal write.
+ * | | |Read operation:
+ * | | |0 = Write-protection Enabled for writing protected registers.
+ * | | |Any write to the protected register is ignored.
+ * | | |1 = Write-protection Disabled for writing protected registers.
+ * | | |The Protected registers are:
+ * | | |SYS_IPRST0: address 0x4000_0008
+ * | | |SYS_BODCTL: address 0x4000_0018
+ * | | |SYS_PORCTL: address 0x4000_0024
+ * | | |SYS_VREFCTL: address 0x4000_0028
+ * | | |SYS_USBPHY: address 0x4000_002C
+ * | | |CLK_PWRCTL: address 0x4000_0200 (bit[6] is not protected for power wake-up interrupt clear)
+ * | | |SYS_SRAM_BISTCTL: address 0x4000_00D0
+ * | | |CLK_APBCLK0 [0]: address 0x4000_0208 (bit[0] is watchdog clock enable)
+ * | | |CLK_CLKSEL0: address 0x4000_0210 (for HCLK and CPU STCLK clock source select)
+ * | | |CLK_CLKSEL1 [1:0]: address 0x4000_0214 (for watchdog clock source select)
+ * | | |CLK_CLKSEL1 [31:30]: address 0x4000_0214 (for window watchdog clock source select)
+ * | | |CLK_CLKDSTS: address 0x4000_0274
+ * | | |NMIEN: address 0x4000_0300
+ * | | |FMC_ISPCTL: address 0x4000_C000 (Flash ISP Control register)
+ * | | |FMC_ISPTRG: address 0x4000_C010 (ISP Trigger Control register)
+ * | | |FMC_ISPSTS: address 0x4000_C040
+ * | | |WDT_CTL: address 0x4004_0000
+ * | | |FMC_FTCTL: address 0x4000_5018
+ * | | |FMC_ICPCMD: address 0x4000_501C
+ * | | |CLK_PLLCTL: address 0x40000240
+ * | | |PWM_CTL0: address 0x4005_8000
+ * | | |PWM_CTL0: address 0x4005_9000
+ * | | |PWM_DTCTL0_1: address 0x4005_8070
+ * | | |PWM_DTCTL0_1: address 0x4005_9070
+ * | | |PWM_DTCTL2_3: address 0x4005_8074
+ * | | |PWM_DTCTL2_3: address 0x4005_9074
+ * | | |PWM_DTCTL4_5: address 0x4005_8078
+ * | | |PWM_DTCTL4_5: address 0x4005_9078
+ * | | |PWM_BRKCTL0_1: address 0x4005_80C8
+ * | | |PWM_BRKCTL0_1: address 0x4005_90C8
+ * | | |PWM_BRKCTL2_3: address0x4005_80CC
+ * | | |PWM_BRKCTL2_3: address0x4005_90CC
+ * | | |PWM_BRKCTL4_5: address0x4005_80D0
+ * | | |PWM_BRKCTL4_5: address0x4005_90D0
+ * | | |PWM_INTEN1: address0x4005_80E4
+ * | | |PWM_INTEN1: address0x4005_90E4
+ * | | |PWM_INTSTS1: address0x4005_80EC
+ * | | |PWM_INTSTS1: address0x4005_90EC
+ */
+
+ __I uint32_t PDID; /* Offset: 0x00 Part Device Identification Number Register */
+ __IO uint32_t RSTSTS; /* Offset: 0x04 System Reset Status Register */
+ __IO uint32_t IPRST0; /* Offset: 0x08 Peripheral Reset Control Register 0 */
+ __IO uint32_t IPRST1; /* Offset: 0x0C Peripheral Reset Control Register 1 */
+ __IO uint32_t IPRST2; /* Offset: 0x10 Peripheral Reset Control Register 2 */
+ __I uint32_t RESERVE0[1];
+ __IO uint32_t BODCTL; /* Offset: 0x18 Brown-Out Detector Control Register */
+ __IO uint32_t IVSCTL; /* Offset: 0x1C Internal Voltage Source Control Register */
+ __I uint32_t RESERVE1[1];
+ __IO uint32_t PORCTL; /* Offset: 0x24 Power-On-Reset Controller Register */
+ __IO uint32_t VREFCTL; /* Offset: 0x28 VREF Control Register */
+ __IO uint32_t USBPHY; /* Offset: 0x2C USB PHY Control Register */
+ __IO uint32_t GPA_MFPL; /* Offset: 0x30 GPIOA Low Byte Multiple Function Control Register */
+ __IO uint32_t GPA_MFPH; /* Offset: 0x34 GPIOA High Byte Multiple Function Control Register */
+ __IO uint32_t GPB_MFPL; /* Offset: 0x38 GPIOB Low Byte Multiple Function Control Register */
+ __IO uint32_t GPB_MFPH; /* Offset: 0x3C GPIOB High Byte Multiple Function Control Register */
+ __IO uint32_t GPC_MFPL; /* Offset: 0x40 GPIOC Low Byte Multiple Function Control Register */
+ __IO uint32_t GPC_MFPH; /* Offset: 0x44 GPIOC High Byte Multiple Function Control Register */
+ __IO uint32_t GPD_MFPL; /* Offset: 0x48 GPIOD Low Byte Multiple Function Control Register */
+ __IO uint32_t GPD_MFPH; /* Offset: 0x4C GPIOD High Byte Multiple Function Control Register */
+ __IO uint32_t GPE_MFPL; /* Offset: 0x50 GPIOE Low Byte Multiple Function Control Register */
+ __IO uint32_t GPE_MFPH; /* Offset: 0x54 GPIOE High Byte Multiple Function Control Register */
+ __IO uint32_t GPF_MFPL; /* Offset: 0x58 GPIOF Low Byte Multiple Function Control Register */
+ __I uint32_t RESERVE2[25];
+ __IO uint32_t SRAM_INTCTL; /* Offset: 0xC0 System SRAM Interrupt Enable Control Register */
+ __I uint32_t SRAM_STATUS; /* Offset: 0xC4 System SRAM Parity Error Status Register */
+ __I uint32_t SRAM_ERRADDR; /* Offset: 0xC8 System SRAM Parity Check Error Address Register */
+ __I uint32_t RESERVE3[1];
+ __IO uint32_t SRAM_BISTCTL; /* Offset: 0xD0 System SRAM BIST Test Control Register */
+ __I uint32_t SRAM_BISTSTS; /* Offset: 0xD4 System SRAM BIST Test Status Register */
+ __I uint32_t RESERVE4[6];
+ __IO uint32_t IRCTCTL; /* Offset: 0xF0 IRC Trim Control Register */
+ __IO uint32_t IRCTIEN; /* Offset: 0xF4 IRC Trim Interrupt Enable Register */
+ __IO uint32_t IRCTISTS; /* Offset: 0xF8 IRC Trim Interrupt Status Register */
+ __I uint32_t RESERVE5[1];
+ __IO uint32_t REGLCTL; /* Offset: 0x100 Register Lock Control Register */
+
+} SYS_T;
+
+
+
+/**
+ @addtogroup SYS_CONST SYS Bit Field Definition
+ Constant Definitions for SYS Controller
+@{ */
+
+#define SYS_PDID_PDID_Pos (0) /*!< SYS_T::PDID: PDID Position */
+#define SYS_PDID_PDID_Msk (0xfffffffful << SYS_PDID_PDID_Pos) /*!< SYS_T::PDID: PDID Mask */
+
+#define SYS_RSTSTS_PORF_Pos (0) /*!< SYS_T::RSTSTS: PORF Position */
+#define SYS_RSTSTS_PORF_Msk (0x1ul << SYS_RSTSTS_PORF_Pos) /*!< SYS_T::RSTSTS: PORF Mask */
+
+#define SYS_RSTSTS_PINRF_Pos (1) /*!< SYS_T::RSTSTS: PINRF Position */
+#define SYS_RSTSTS_PINRF_Msk (0x1ul << SYS_RSTSTS_PINRF_Pos) /*!< SYS_T::RSTSTS: PINRF Mask */
+
+#define SYS_RSTSTS_WDTRF_Pos (2) /*!< SYS_T::RSTSTS: WDTRF Position */
+#define SYS_RSTSTS_WDTRF_Msk (0x1ul << SYS_RSTSTS_WDTRF_Pos) /*!< SYS_T::RSTSTS: WDTRF Mask */
+
+#define SYS_RSTSTS_LVRF_Pos (3) /*!< SYS_T::RSTSTS: LVRF Position */
+#define SYS_RSTSTS_LVRF_Msk (0x1ul << SYS_RSTSTS_LVRF_Pos) /*!< SYS_T::RSTSTS: LVRF Mask */
+
+#define SYS_RSTSTS_BODRF_Pos (4) /*!< SYS_T::RSTSTS: BODRF Position */
+#define SYS_RSTSTS_BODRF_Msk (0x1ul << SYS_RSTSTS_BODRF_Pos) /*!< SYS_T::RSTSTS: BODRF Mask */
+
+#define SYS_RSTSTS_SYSRF_Pos (5) /*!< SYS_T::RSTSTS: SYSRF Position */
+#define SYS_RSTSTS_SYSRF_Msk (0x1ul << SYS_RSTSTS_SYSRF_Pos) /*!< SYS_T::RSTSTS: SYSRF Mask */
+
+#define SYS_RSTSTS_CPURF_Pos (7) /*!< SYS_T::RSTSTS: CPURF Position */
+#define SYS_RSTSTS_CPURF_Msk (0x1ul << SYS_RSTSTS_CPURF_Pos) /*!< SYS_T::RSTSTS: CPURF Mask */
+
+#define SYS_RSTSTS_CPULKRF_Pos (8) /*!< SYS_T::RSTSTS: CPULKRF Position */
+#define SYS_RSTSTS_CPULKRF_Msk (0x1ul << SYS_RSTSTS_CPULKRF_Pos) /*!< SYS_T::RSTSTS: CPULKRF Mask */
+
+#define SYS_IPRST0_CHIPRST_Pos (0) /*!< SYS_T::IPRST0: CHIPRST Position */
+#define SYS_IPRST0_CHIPRST_Msk (0x1ul << SYS_IPRST0_CHIPRST_Pos) /*!< SYS_T::IPRST0: CHIPRST Mask */
+
+#define SYS_IPRST0_CPURST_Pos (1) /*!< SYS_T::IPRST0: CPURST Position */
+#define SYS_IPRST0_CPURST_Msk (0x1ul << SYS_IPRST0_CPURST_Pos) /*!< SYS_T::IPRST0: CPURST Mask */
+
+#define SYS_IPRST0_PDMARST_Pos (2) /*!< SYS_T::IPRST0: PDMARST Position */
+#define SYS_IPRST0_PDMARST_Msk (0x1ul << SYS_IPRST0_PDMARST_Pos) /*!< SYS_T::IPRST0: PDMARST Mask */
+
+#define SYS_IPRST0_EBIRST_Pos (3) /*!< SYS_T::IPRST0: EBIRST Position */
+#define SYS_IPRST0_EBIRST_Msk (0x1ul << SYS_IPRST0_EBIRST_Pos) /*!< SYS_T::IPRST0: EBIRST Mask */
+
+#define SYS_IPRST0_USBHRST_Pos (4) /*!< SYS_T::IPRST0: USBHRST Position */
+#define SYS_IPRST0_USBHRST_Msk (0x1ul << SYS_IPRST0_USBHRST_Pos) /*!< SYS_T::IPRST0: USBHRST Mask */
+
+#define SYS_IPRST0_CRCRST_Pos (7) /*!< SYS_T::IPRST0: CRCRST Position */
+#define SYS_IPRST0_CRCRST_Msk (0x1ul << SYS_IPRST0_CRCRST_Pos) /*!< SYS_T::IPRST0: CRCRST Mask */
+
+#define SYS_IPRST1_GPIORST_Pos (1) /*!< SYS_T::IPRST1: GPIORST Position */
+#define SYS_IPRST1_GPIORST_Msk (0x1ul << SYS_IPRST1_GPIORST_Pos) /*!< SYS_T::IPRST1: GPIORST Mask */
+
+#define SYS_IPRST1_TMR0RST_Pos (2) /*!< SYS_T::IPRST1: TMR0RST Position */
+#define SYS_IPRST1_TMR0RST_Msk (0x1ul << SYS_IPRST1_TMR0RST_Pos) /*!< SYS_T::IPRST1: TMR0RST Mask */
+
+#define SYS_IPRST1_TMR1RST_Pos (3) /*!< SYS_T::IPRST1: TMR1RST Position */
+#define SYS_IPRST1_TMR1RST_Msk (0x1ul << SYS_IPRST1_TMR1RST_Pos) /*!< SYS_T::IPRST1: TMR1RST Mask */
+
+#define SYS_IPRST1_TMR2RST_Pos (4) /*!< SYS_T::IPRST1: TMR2RST Position */
+#define SYS_IPRST1_TMR2RST_Msk (0x1ul << SYS_IPRST1_TMR2RST_Pos) /*!< SYS_T::IPRST1: TMR2RST Mask */
+
+#define SYS_IPRST1_TMR3RST_Pos (5) /*!< SYS_T::IPRST1: TMR3RST Position */
+#define SYS_IPRST1_TMR3RST_Msk (0x1ul << SYS_IPRST1_TMR3RST_Pos) /*!< SYS_T::IPRST1: TMR3RST Mask */
+
+#define SYS_IPRST1_ACMP01RST_Pos (7) /*!< SYS_T::IPRST1: ACMP01RST Position */
+#define SYS_IPRST1_ACMP01RST_Msk (0x1ul << SYS_IPRST1_ACMP01RST_Pos) /*!< SYS_T::IPRST1: ACMP01RST Mask */
+
+#define SYS_IPRST1_I2C0RST_Pos (8) /*!< SYS_T::IPRST1: I2C0RST Position */
+#define SYS_IPRST1_I2C0RST_Msk (0x1ul << SYS_IPRST1_I2C0RST_Pos) /*!< SYS_T::IPRST1: I2C0RST Mask */
+
+#define SYS_IPRST1_I2C1RST_Pos (9) /*!< SYS_T::IPRST1: I2C1RST Position */
+#define SYS_IPRST1_I2C1RST_Msk (0x1ul << SYS_IPRST1_I2C1RST_Pos) /*!< SYS_T::IPRST1: I2C1RST Mask */
+
+#define SYS_IPRST1_SPI0RST_Pos (12) /*!< SYS_T::IPRST1: SPI0RST Position */
+#define SYS_IPRST1_SPI0RST_Msk (0x1ul << SYS_IPRST1_SPI0RST_Pos) /*!< SYS_T::IPRST1: SPI0RST Mask */
+
+#define SYS_IPRST1_SPI1RST_Pos (13) /*!< SYS_T::IPRST1: SPI1RST Position */
+#define SYS_IPRST1_SPI1RST_Msk (0x1ul << SYS_IPRST1_SPI1RST_Pos) /*!< SYS_T::IPRST1: SPI1RST Mask */
+
+#define SYS_IPRST1_SPI2RST_Pos (14) /*!< SYS_T::IPRST1: SPI2RST Position */
+#define SYS_IPRST1_SPI2RST_Msk (0x1ul << SYS_IPRST1_SPI2RST_Pos) /*!< SYS_T::IPRST1: SPI2RST Mask */
+
+#define SYS_IPRST1_UART0RST_Pos (16) /*!< SYS_T::IPRST1: UART0RST Position */
+#define SYS_IPRST1_UART0RST_Msk (0x1ul << SYS_IPRST1_UART0RST_Pos) /*!< SYS_T::IPRST1: UART0RST Mask */
+
+#define SYS_IPRST1_UART1RST_Pos (17) /*!< SYS_T::IPRST1: UART1RST Position */
+#define SYS_IPRST1_UART1RST_Msk (0x1ul << SYS_IPRST1_UART1RST_Pos) /*!< SYS_T::IPRST1: UART1RST Mask */
+
+#define SYS_IPRST1_UART2RST_Pos (18) /*!< SYS_T::IPRST1: UART2RST Position */
+#define SYS_IPRST1_UART2RST_Msk (0x1ul << SYS_IPRST1_UART2RST_Pos) /*!< SYS_T::IPRST1: UART2RST Mask */
+
+#define SYS_IPRST1_UART3RST_Pos (19) /*!< SYS_T::IPRST1: UART3RST Position */
+#define SYS_IPRST1_UART3RST_Msk (0x1ul << SYS_IPRST1_UART3RST_Pos) /*!< SYS_T::IPRST1: UART3RST Mask */
+
+#define SYS_IPRST1_CAN0RST_Pos (24) /*!< SYS_T::IPRST1: CAN0RST Position */
+#define SYS_IPRST1_CAN0RST_Msk (0x1ul << SYS_IPRST1_CAN0RST_Pos) /*!< SYS_T::IPRST1: CAN0RST Mask */
+
+#define SYS_IPRST1_OTGRST_Pos (26) /*!< SYS_T::IPRST1: OTGRST Position */
+#define SYS_IPRST1_OTGRST_Msk (0x1ul << SYS_IPRST1_OTGRST_Pos) /*!< SYS_T::IPRST1: OTGRST Mask */
+
+#define SYS_IPRST1_USBDRST_Pos (27) /*!< SYS_T::IPRST1: USBDRST Position */
+#define SYS_IPRST1_USBDRST_Msk (0x1ul << SYS_IPRST1_USBDRST_Pos) /*!< SYS_T::IPRST1: USBDRST Mask */
+
+#define SYS_IPRST1_EADCRST_Pos (28) /*!< SYS_T::IPRST1: EADCRST Position */
+#define SYS_IPRST1_EADCRST_Msk (0x1ul << SYS_IPRST1_EADCRST_Pos) /*!< SYS_T::IPRST1: EADCRST Mask */
+
+#define SYS_IPRST2_SC0RST_Pos (0) /*!< SYS_T::IPRST2: SC0RST Position */
+#define SYS_IPRST2_SC0RST_Msk (0x1ul << SYS_IPRST2_SC0RST_Pos) /*!< SYS_T::IPRST2: SC0RST Mask */
+
+#define SYS_IPRST2_DACRST_Pos (12) /*!< SYS_T::IPRST2: DACRST Position */
+#define SYS_IPRST2_DACRST_Msk (0x1ul << SYS_IPRST2_DACRST_Pos) /*!< SYS_T::IPRST2: DACRST Mask */
+
+#define SYS_IPRST2_PWM0RST_Pos (16) /*!< SYS_T::IPRST2: PWM0RST Position */
+#define SYS_IPRST2_PWM0RST_Msk (0x1ul << SYS_IPRST2_PWM0RST_Pos) /*!< SYS_T::IPRST2: PWM0RST Mask */
+
+#define SYS_IPRST2_PWM1RST_Pos (17) /*!< SYS_T::IPRST2: PWM1RST Position */
+#define SYS_IPRST2_PWM1RST_Msk (0x1ul << SYS_IPRST2_PWM1RST_Pos) /*!< SYS_T::IPRST2: PWM1RST Mask */
+
+#define SYS_IPRST2_TKRST_Pos (25) /*!< SYS_T::IPRST2: TKRST Position */
+#define SYS_IPRST2_TKRST_Msk (0x1ul << SYS_IPRST2_TKRST_Pos) /*!< SYS_T::IPRST2: TKRST Mask */
+
+#define SYS_BODCTL_BODEN_Pos (0) /*!< SYS_T::BODCTL: BODEN Position */
+#define SYS_BODCTL_BODEN_Msk (0x1ul << SYS_BODCTL_BODEN_Pos) /*!< SYS_T::BODCTL: BODEN Mask */
+
+#define SYS_BODCTL_BODVL_Pos (1) /*!< SYS_T::BODCTL: BODVL Position */
+#define SYS_BODCTL_BODVL_Msk (0x3ul << SYS_BODCTL_BODVL_Pos) /*!< SYS_T::BODCTL: BODVL Mask */
+
+#define SYS_BODCTL_BODRSTEN_Pos (3) /*!< SYS_T::BODCTL: BODRSTEN Position */
+#define SYS_BODCTL_BODRSTEN_Msk (0x1ul << SYS_BODCTL_BODRSTEN_Pos) /*!< SYS_T::BODCTL: BODRSTEN Mask */
+
+#define SYS_BODCTL_BODIF_Pos (4) /*!< SYS_T::BODCTL: BODIF Position */
+#define SYS_BODCTL_BODIF_Msk (0x1ul << SYS_BODCTL_BODIF_Pos) /*!< SYS_T::BODCTL: BODIF Mask */
+
+#define SYS_BODCTL_BODLPM_Pos (5) /*!< SYS_T::BODCTL: BODLPM Position */
+#define SYS_BODCTL_BODLPM_Msk (0x1ul << SYS_BODCTL_BODLPM_Pos) /*!< SYS_T::BODCTL: BODLPM Mask */
+
+#define SYS_BODCTL_BODOUT_Pos (6) /*!< SYS_T::BODCTL: BODOUT Position */
+#define SYS_BODCTL_BODOUT_Msk (0x1ul << SYS_BODCTL_BODOUT_Pos) /*!< SYS_T::BODCTL: BODOUT Mask */
+
+#define SYS_BODCTL_LVREN_Pos (7) /*!< SYS_T::BODCTL: LVREN Position */
+#define SYS_BODCTL_LVREN_Msk (0x1ul << SYS_BODCTL_LVREN_Pos) /*!< SYS_T::BODCTL: LVREN Mask */
+
+#define SYS_BODCTL_BODDGSEL_Pos (8) /*!< SYS_T::BODCTL: BODDGSEL Position */
+#define SYS_BODCTL_BODDGSEL_Msk (0x7ul << SYS_BODCTL_BODDGSEL_Pos) /*!< SYS_T::BODCTL: BODDGSEL Mask */
+
+#define SYS_BODCTL_LVRDGSEL_Pos (12) /*!< SYS_T::BODCTL: LVRDGSEL Position */
+#define SYS_BODCTL_LVRDGSEL_Msk (0x7ul << SYS_BODCTL_LVRDGSEL_Pos) /*!< SYS_T::BODCTL: LVRDGSEL Mask */
+
+#define SYS_IVSCTL_VTEMPEN_Pos (0) /*!< SYS_T::IVSCTL: VTEMPEN Position */
+#define SYS_IVSCTL_VTEMPEN_Msk (0x1ul << SYS_IVSCTL_VTEMPEN_Pos) /*!< SYS_T::IVSCTL: VTEMPEN Mask */
+
+#define SYS_IVSCTL_VBATUGEN_Pos (1) /*!< SYS_T::IVSCTL: VBATUGEN Position */
+#define SYS_IVSCTL_VBATUGEN_Msk (0x1ul << SYS_IVSCTL_VBATUGEN_Pos) /*!< SYS_T::IVSCTL: VBATUGEN Mask */
+
+#define SYS_PORCTL_POROFF_Pos (0) /*!< SYS_T::PORCTL: POROFF Position */
+#define SYS_PORCTL_POROFF_Msk (0xfffful << SYS_PORCTL_POROFF_Pos) /*!< SYS_T::PORCTL: POROFF Mask */
+
+#define SYS_VREFCTL_VREFCTL_Pos (0) /*!< SYS_T::VREFCTL: VREFCTL Position */
+#define SYS_VREFCTL_VREFCTL_Msk (0x1ful << SYS_VREFCTL_VREFCTL_Pos) /*!< SYS_T::VREFCTL: VREFCTL Mask */
+
+#define SYS_USBPHY_USBROLE_Pos (0) /*!< SYS_T::USBPHY: USBROLE Position */
+#define SYS_USBPHY_USBROLE_Msk (0x3ul << SYS_USBPHY_USBROLE_Pos) /*!< SYS_T::USBPHY: USBROLE Mask */
+
+#define SYS_USBPHY_LDO33EN_Pos (8) /*!< SYS_T::USBPHY: LDO33EN Position */
+#define SYS_USBPHY_LDO33EN_Msk (0x1ul << SYS_USBPHY_LDO33EN_Pos) /*!< SYS_T::USBPHY: LDO33EN Mask */
+
+#define SYS_GPA_MFPL_PA0MFP_Pos (0) /*!< SYS_T::GPA_MFPL: PA0MFP Position */
+#define SYS_GPA_MFPL_PA0MFP_Msk (0xful << SYS_GPA_MFPL_PA0MFP_Pos) /*!< SYS_T::GPA_MFPL: PA0MFP Mask */
+
+#define SYS_GPA_MFPL_PA1MFP_Pos (4) /*!< SYS_T::GPA_MFPL: PA1MFP Position */
+#define SYS_GPA_MFPL_PA1MFP_Msk (0xful << SYS_GPA_MFPL_PA1MFP_Pos) /*!< SYS_T::GPA_MFPL: PA1MFP Mask */
+
+#define SYS_GPA_MFPL_PA2MFP_Pos (8) /*!< SYS_T::GPA_MFPL: PA2MFP Position */
+#define SYS_GPA_MFPL_PA2MFP_Msk (0xful << SYS_GPA_MFPL_PA2MFP_Pos) /*!< SYS_T::GPA_MFPL: PA2MFP Mask */
+
+#define SYS_GPA_MFPL_PA3MFP_Pos (12) /*!< SYS_T::GPA_MFPL: PA3MFP Position */
+#define SYS_GPA_MFPL_PA3MFP_Msk (0xful << SYS_GPA_MFPL_PA3MFP_Pos) /*!< SYS_T::GPA_MFPL: PA3MFP Mask */
+
+#define SYS_GPA_MFPL_PA4MFP_Pos (16) /*!< SYS_T::GPA_MFPL: PA4MFP Position */
+#define SYS_GPA_MFPL_PA4MFP_Msk (0xful << SYS_GPA_MFPL_PA4MFP_Pos) /*!< SYS_T::GPA_MFPL: PA4MFP Mask */
+
+#define SYS_GPA_MFPL_PA5MFP_Pos (20) /*!< SYS_T::GPA_MFPL: PA5MFP Position */
+#define SYS_GPA_MFPL_PA5MFP_Msk (0xful << SYS_GPA_MFPL_PA5MFP_Pos) /*!< SYS_T::GPA_MFPL: PA5MFP Mask */
+
+#define SYS_GPA_MFPL_PA6MFP_Pos (24) /*!< SYS_T::GPA_MFPL: PA6MFP Position */
+#define SYS_GPA_MFPL_PA6MFP_Msk (0xful << SYS_GPA_MFPL_PA6MFP_Pos) /*!< SYS_T::GPA_MFPL: PA6MFP Mask */
+
+#define SYS_GPA_MFPL_PA7MFP_Pos (28) /*!< SYS_T::GPA_MFPL: PA7MFP Position */
+#define SYS_GPA_MFPL_PA7MFP_Msk (0xful << SYS_GPA_MFPL_PA7MFP_Pos) /*!< SYS_T::GPA_MFPL: PA7MFP Mask */
+
+#define SYS_GPA_MFPH_PA8MFP_Pos (0) /*!< SYS_T::GPA_MFPH: PA8MFP Position */
+#define SYS_GPA_MFPH_PA8MFP_Msk (0xful << SYS_GPA_MFPH_PA8MFP_Pos) /*!< SYS_T::GPA_MFPH: PA8MFP Mask */
+
+#define SYS_GPA_MFPH_PA9MFP_Pos (4) /*!< SYS_T::GPA_MFPH: PA9MFP Position */
+#define SYS_GPA_MFPH_PA9MFP_Msk (0xful << SYS_GPA_MFPH_PA9MFP_Pos) /*!< SYS_T::GPA_MFPH: PA9MFP Mask */
+
+#define SYS_GPA_MFPH_PA10MFP_Pos (8) /*!< SYS_T::GPA_MFPH: PA10MFP Position */
+#define SYS_GPA_MFPH_PA10MFP_Msk (0xful << SYS_GPA_MFPH_PA10MFP_Pos) /*!< SYS_T::GPA_MFPH: PA10MFP Mask */
+
+#define SYS_GPA_MFPH_PA11MFP_Pos (12) /*!< SYS_T::GPA_MFPH: PA11MFP Position */
+#define SYS_GPA_MFPH_PA11MFP_Msk (0xful << SYS_GPA_MFPH_PA11MFP_Pos) /*!< SYS_T::GPA_MFPH: PA11MFP Mask */
+
+#define SYS_GPA_MFPH_PA12MFP_Pos (16) /*!< SYS_T::GPA_MFPH: PA12MFP Position */
+#define SYS_GPA_MFPH_PA12MFP_Msk (0xful << SYS_GPA_MFPH_PA12MFP_Pos) /*!< SYS_T::GPA_MFPH: PA12MFP Mask */
+
+#define SYS_GPA_MFPH_PA13MFP_Pos (20) /*!< SYS_T::GPA_MFPH: PA13MFP Position */
+#define SYS_GPA_MFPH_PA13MFP_Msk (0xful << SYS_GPA_MFPH_PA13MFP_Pos) /*!< SYS_T::GPA_MFPH: PA13MFP Mask */
+
+#define SYS_GPA_MFPH_PA14MFP_Pos (24) /*!< SYS_T::GPA_MFPH: PA14MFP Position */
+#define SYS_GPA_MFPH_PA14MFP_Msk (0xful << SYS_GPA_MFPH_PA14MFP_Pos) /*!< SYS_T::GPA_MFPH: PA14MFP Mask */
+
+#define SYS_GPA_MFPH_PA15MFP_Pos (28) /*!< SYS_T::GPA_MFPH: PA15MFP Position */
+#define SYS_GPA_MFPH_PA15MFP_Msk (0xful << SYS_GPA_MFPH_PA15MFP_Pos) /*!< SYS_T::GPA_MFPH: PA15MFP Mask */
+
+#define SYS_GPB_MFPL_PB0MFP_Pos (0) /*!< SYS_T::GPB_MFPL: PB0MFP Position */
+#define SYS_GPB_MFPL_PB0MFP_Msk (0xful << SYS_GPB_MFPL_PB0MFP_Pos) /*!< SYS_T::GPB_MFPL: PB0MFP Mask */
+
+#define SYS_GPB_MFPL_PB1MFP_Pos (4) /*!< SYS_T::GPB_MFPL: PB1MFP Position */
+#define SYS_GPB_MFPL_PB1MFP_Msk (0xful << SYS_GPB_MFPL_PB1MFP_Pos) /*!< SYS_T::GPB_MFPL: PB1MFP Mask */
+
+#define SYS_GPB_MFPL_PB2MFP_Pos (8) /*!< SYS_T::GPB_MFPL: PB2MFP Position */
+#define SYS_GPB_MFPL_PB2MFP_Msk (0xful << SYS_GPB_MFPL_PB2MFP_Pos) /*!< SYS_T::GPB_MFPL: PB2MFP Mask */
+
+#define SYS_GPB_MFPL_PB3MFP_Pos (12) /*!< SYS_T::GPB_MFPL: PB3MFP Position */
+#define SYS_GPB_MFPL_PB3MFP_Msk (0xful << SYS_GPB_MFPL_PB3MFP_Pos) /*!< SYS_T::GPB_MFPL: PB3MFP Mask */
+
+#define SYS_GPB_MFPL_PB4MFP_Pos (16) /*!< SYS_T::GPB_MFPL: PB4MFP Position */
+#define SYS_GPB_MFPL_PB4MFP_Msk (0xful << SYS_GPB_MFPL_PB4MFP_Pos) /*!< SYS_T::GPB_MFPL: PB4MFP Mask */
+
+#define SYS_GPB_MFPL_PB5MFP_Pos (20) /*!< SYS_T::GPB_MFPL: PB5MFP Position */
+#define SYS_GPB_MFPL_PB5MFP_Msk (0xful << SYS_GPB_MFPL_PB5MFP_Pos) /*!< SYS_T::GPB_MFPL: PB5MFP Mask */
+
+#define SYS_GPB_MFPL_PB6MFP_Pos (24) /*!< SYS_T::GPB_MFPL: PB6MFP Position */
+#define SYS_GPB_MFPL_PB6MFP_Msk (0xful << SYS_GPB_MFPL_PB6MFP_Pos) /*!< SYS_T::GPB_MFPL: PB6MFP Mask */
+
+#define SYS_GPB_MFPL_PB7MFP_Pos (28) /*!< SYS_T::GPB_MFPL: PB7MFP Position */
+#define SYS_GPB_MFPL_PB7MFP_Msk (0xful << SYS_GPB_MFPL_PB7MFP_Pos) /*!< SYS_T::GPB_MFPL: PB7MFP Mask */
+
+#define SYS_GPB_MFPH_PB8MFP_Pos (0) /*!< SYS_T::GPB_MFPH: PB8MFP Position */
+#define SYS_GPB_MFPH_PB8MFP_Msk (0xful << SYS_GPB_MFPH_PB8MFP_Pos) /*!< SYS_T::GPB_MFPH: PB8MFP Mask */
+
+#define SYS_GPB_MFPH_PB9MFP_Pos (4) /*!< SYS_T::GPB_MFPH: PB9MFP Position */
+#define SYS_GPB_MFPH_PB9MFP_Msk (0xful << SYS_GPB_MFPH_PB9MFP_Pos) /*!< SYS_T::GPB_MFPH: PB9MFP Mask */
+
+#define SYS_GPB_MFPH_PB10MFP_Pos (8) /*!< SYS_T::GPB_MFPH: PB10MFP Position */
+#define SYS_GPB_MFPH_PB10MFP_Msk (0xful << SYS_GPB_MFPH_PB10MFP_Pos) /*!< SYS_T::GPB_MFPH: PB10MFP Mask */
+
+#define SYS_GPB_MFPH_PB11MFP_Pos (12) /*!< SYS_T::GPB_MFPH: PB11MFP Position */
+#define SYS_GPB_MFPH_PB11MFP_Msk (0xful << SYS_GPB_MFPH_PB11MFP_Pos) /*!< SYS_T::GPB_MFPH: PB11MFP Mask */
+
+#define SYS_GPB_MFPH_PB12MFP_Pos (16) /*!< SYS_T::GPB_MFPH: PB12MFP Position */
+#define SYS_GPB_MFPH_PB12MFP_Msk (0xful << SYS_GPB_MFPH_PB12MFP_Pos) /*!< SYS_T::GPB_MFPH: PB12MFP Mask */
+
+#define SYS_GPB_MFPH_PB13MFP_Pos (20) /*!< SYS_T::GPB_MFPH: PB13MFP Position */
+#define SYS_GPB_MFPH_PB13MFP_Msk (0xful << SYS_GPB_MFPH_PB13MFP_Pos) /*!< SYS_T::GPB_MFPH: PB13MFP Mask */
+
+#define SYS_GPB_MFPH_PB14MFP_Pos (24) /*!< SYS_T::GPB_MFPH: PB14MFP Position */
+#define SYS_GPB_MFPH_PB14MFP_Msk (0xful << SYS_GPB_MFPH_PB14MFP_Pos) /*!< SYS_T::GPB_MFPH: PB14MFP Mask */
+
+#define SYS_GPB_MFPH_PB15MFP_Pos (28) /*!< SYS_T::GPB_MFPH: PB15MFP Position */
+#define SYS_GPB_MFPH_PB15MFP_Msk (0xful << SYS_GPB_MFPH_PB15MFP_Pos) /*!< SYS_T::GPB_MFPH: PB15MFP Mask */
+
+#define SYS_GPC_MFPL_PC0MFP_Pos (0) /*!< SYS_T::GPC_MFPL: PC0MFP Position */
+#define SYS_GPC_MFPL_PC0MFP_Msk (0xful << SYS_GPC_MFPL_PC0MFP_Pos) /*!< SYS_T::GPC_MFPL: PC0MFP Mask */
+
+#define SYS_GPC_MFPL_PC1MFP_Pos (4) /*!< SYS_T::GPC_MFPL: PC1MFP Position */
+#define SYS_GPC_MFPL_PC1MFP_Msk (0xful << SYS_GPC_MFPL_PC1MFP_Pos) /*!< SYS_T::GPC_MFPL: PC1MFP Mask */
+
+#define SYS_GPC_MFPL_PC2MFP_Pos (8) /*!< SYS_T::GPC_MFPL: PC2MFP Position */
+#define SYS_GPC_MFPL_PC2MFP_Msk (0xful << SYS_GPC_MFPL_PC2MFP_Pos) /*!< SYS_T::GPC_MFPL: PC2MFP Mask */
+
+#define SYS_GPC_MFPL_PC3MFP_Pos (12) /*!< SYS_T::GPC_MFPL: PC3MFP Position */
+#define SYS_GPC_MFPL_PC3MFP_Msk (0xful << SYS_GPC_MFPL_PC3MFP_Pos) /*!< SYS_T::GPC_MFPL: PC3MFP Mask */
+
+#define SYS_GPC_MFPL_PC4MFP_Pos (16) /*!< SYS_T::GPC_MFPL: PC4MFP Position */
+#define SYS_GPC_MFPL_PC4MFP_Msk (0xful << SYS_GPC_MFPL_PC4MFP_Pos) /*!< SYS_T::GPC_MFPL: PC4MFP Mask */
+
+#define SYS_GPC_MFPL_PC5MFP_Pos (20) /*!< SYS_T::GPC_MFPL: PC5MFP Position */
+#define SYS_GPC_MFPL_PC5MFP_Msk (0xful << SYS_GPC_MFPL_PC5MFP_Pos) /*!< SYS_T::GPC_MFPL: PC5MFP Mask */
+
+#define SYS_GPC_MFPL_PC6MFP_Pos (24) /*!< SYS_T::GPC_MFPL: PC6MFP Position */
+#define SYS_GPC_MFPL_PC6MFP_Msk (0xful << SYS_GPC_MFPL_PC6MFP_Pos) /*!< SYS_T::GPC_MFPL: PC6MFP Mask */
+
+#define SYS_GPC_MFPL_PC7MFP_Pos (28) /*!< SYS_T::GPC_MFPL: PC7MFP Position */
+#define SYS_GPC_MFPL_PC7MFP_Msk (0xful << SYS_GPC_MFPL_PC7MFP_Pos) /*!< SYS_T::GPC_MFPL: PC7MFP Mask */
+
+#define SYS_GPC_MFPH_PC8MFP_Pos (0) /*!< SYS_T::GPC_MFPH: PC8MFP Position */
+#define SYS_GPC_MFPH_PC8MFP_Msk (0xful << SYS_GPC_MFPH_PC8MFP_Pos) /*!< SYS_T::GPC_MFPH: PC8MFP Mask */
+
+#define SYS_GPC_MFPH_PC9MFP_Pos (4) /*!< SYS_T::GPC_MFPH: PC9MFP Position */
+#define SYS_GPC_MFPH_PC9MFP_Msk (0xful << SYS_GPC_MFPH_PC9MFP_Pos) /*!< SYS_T::GPC_MFPH: PC9MFP Mask */
+
+#define SYS_GPC_MFPH_PC10MFP_Pos (8) /*!< SYS_T::GPC_MFPH: PC10MFP Position */
+#define SYS_GPC_MFPH_PC10MFP_Msk (0xful << SYS_GPC_MFPH_PC10MFP_Pos) /*!< SYS_T::GPC_MFPH: PC10MFP Mask */
+
+#define SYS_GPC_MFPH_PC11MFP_Pos (12) /*!< SYS_T::GPC_MFPH: PC11MFP Position */
+#define SYS_GPC_MFPH_PC11MFP_Msk (0xful << SYS_GPC_MFPH_PC11MFP_Pos) /*!< SYS_T::GPC_MFPH: PC11MFP Mask */
+
+#define SYS_GPC_MFPH_PC12MFP_Pos (16) /*!< SYS_T::GPC_MFPH: PC12MFP Position */
+#define SYS_GPC_MFPH_PC12MFP_Msk (0xful << SYS_GPC_MFPH_PC12MFP_Pos) /*!< SYS_T::GPC_MFPH: PC12MFP Mask */
+
+#define SYS_GPC_MFPH_PC13MFP_Pos (20) /*!< SYS_T::GPC_MFPH: PC13MFP Position */
+#define SYS_GPC_MFPH_PC13MFP_Msk (0xful << SYS_GPC_MFPH_PC13MFP_Pos) /*!< SYS_T::GPC_MFPH: PC13MFP Mask */
+
+#define SYS_GPC_MFPH_PC14MFP_Pos (24) /*!< SYS_T::GPC_MFPH: PC14MFP Position */
+#define SYS_GPC_MFPH_PC14MFP_Msk (0xful << SYS_GPC_MFPH_PC14MFP_Pos) /*!< SYS_T::GPC_MFPH: PC14MFP Mask */
+
+#define SYS_GPC_MFPH_PC15MFP_Pos (28) /*!< SYS_T::GPC_MFPH: PC15MFP Position */
+#define SYS_GPC_MFPH_PC15MFP_Msk (0xful << SYS_GPC_MFPH_PC15MFP_Pos) /*!< SYS_T::GPC_MFPH: PC15MFP Mask */
+
+#define SYS_GPD_MFPL_PD0MFP_Pos (0) /*!< SYS_T::GPD_MFPL: PD0MFP Position */
+#define SYS_GPD_MFPL_PD0MFP_Msk (0xful << SYS_GPD_MFPL_PD0MFP_Pos) /*!< SYS_T::GPD_MFPL: PD0MFP Mask */
+
+#define SYS_GPD_MFPL_PD1MFP_Pos (4) /*!< SYS_T::GPD_MFPL: PD1MFP Position */
+#define SYS_GPD_MFPL_PD1MFP_Msk (0xful << SYS_GPD_MFPL_PD1MFP_Pos) /*!< SYS_T::GPD_MFPL: PD1MFP Mask */
+
+#define SYS_GPD_MFPL_PD2MFP_Pos (8) /*!< SYS_T::GPD_MFPL: PD2MFP Position */
+#define SYS_GPD_MFPL_PD2MFP_Msk (0xful << SYS_GPD_MFPL_PD2MFP_Pos) /*!< SYS_T::GPD_MFPL: PD2MFP Mask */
+
+#define SYS_GPD_MFPL_PD3MFP_Pos (12) /*!< SYS_T::GPD_MFPL: PD3MFP Position */
+#define SYS_GPD_MFPL_PD3MFP_Msk (0xful << SYS_GPD_MFPL_PD3MFP_Pos) /*!< SYS_T::GPD_MFPL: PD3MFP Mask */
+
+#define SYS_GPD_MFPL_PD4MFP_Pos (16) /*!< SYS_T::GPD_MFPL: PD4MFP Position */
+#define SYS_GPD_MFPL_PD4MFP_Msk (0xful << SYS_GPD_MFPL_PD4MFP_Pos) /*!< SYS_T::GPD_MFPL: PD4MFP Mask */
+
+#define SYS_GPD_MFPL_PD5MFP_Pos (20) /*!< SYS_T::GPD_MFPL: PD5MFP Position */
+#define SYS_GPD_MFPL_PD5MFP_Msk (0xful << SYS_GPD_MFPL_PD5MFP_Pos) /*!< SYS_T::GPD_MFPL: PD5MFP Mask */
+
+#define SYS_GPD_MFPL_PD6MFP_Pos (24) /*!< SYS_T::GPD_MFPL: PD6MFP Position */
+#define SYS_GPD_MFPL_PD6MFP_Msk (0xful << SYS_GPD_MFPL_PD6MFP_Pos) /*!< SYS_T::GPD_MFPL: PD6MFP Mask */
+
+#define SYS_GPD_MFPL_PD7MFP_Pos (28) /*!< SYS_T::GPD_MFPL: PD7MFP Position */
+#define SYS_GPD_MFPL_PD7MFP_Msk (0xful << SYS_GPD_MFPL_PD7MFP_Pos) /*!< SYS_T::GPD_MFPL: PD7MFP Mask */
+
+#define SYS_GPD_MFPH_PD8MFP_Pos (0) /*!< SYS_T::GPD_MFPH: PD8MFP Position */
+#define SYS_GPD_MFPH_PD8MFP_Msk (0xful << SYS_GPD_MFPH_PD8MFP_Pos) /*!< SYS_T::GPD_MFPH: PD8MFP Mask */
+
+#define SYS_GPD_MFPH_PD9MFP_Pos (4) /*!< SYS_T::GPD_MFPH: PD9MFP Position */
+#define SYS_GPD_MFPH_PD9MFP_Msk (0xful << SYS_GPD_MFPH_PD9MFP_Pos) /*!< SYS_T::GPD_MFPH: PD9MFP Mask */
+
+#define SYS_GPD_MFPH_PD10MFP_Pos (8) /*!< SYS_T::GPD_MFPH: PD10MFP Position */
+#define SYS_GPD_MFPH_PD10MFP_Msk (0xful << SYS_GPD_MFPH_PD10MFP_Pos) /*!< SYS_T::GPD_MFPH: PD10MFP Mask */
+
+#define SYS_GPD_MFPH_PD11MFP_Pos (12) /*!< SYS_T::GPD_MFPH: PD11MFP Position */
+#define SYS_GPD_MFPH_PD11MFP_Msk (0xful << SYS_GPD_MFPH_PD11MFP_Pos) /*!< SYS_T::GPD_MFPH: PD11MFP Mask */
+
+#define SYS_GPD_MFPH_PD12MFP_Pos (16) /*!< SYS_T::GPD_MFPH: PD12MFP Position */
+#define SYS_GPD_MFPH_PD12MFP_Msk (0xful << SYS_GPD_MFPH_PD12MFP_Pos) /*!< SYS_T::GPD_MFPH: PD12MFP Mask */
+
+#define SYS_GPD_MFPH_PD13MFP_Pos (20) /*!< SYS_T::GPD_MFPH: PD13MFP Position */
+#define SYS_GPD_MFPH_PD13MFP_Msk (0xful << SYS_GPD_MFPH_PD13MFP_Pos) /*!< SYS_T::GPD_MFPH: PD13MFP Mask */
+
+#define SYS_GPD_MFPH_PD14MFP_Pos (24) /*!< SYS_T::GPD_MFPH: PD14MFP Position */
+#define SYS_GPD_MFPH_PD14MFP_Msk (0xful << SYS_GPD_MFPH_PD14MFP_Pos) /*!< SYS_T::GPD_MFPH: PD14MFP Mask */
+
+#define SYS_GPD_MFPH_PD15MFP_Pos (28) /*!< SYS_T::GPD_MFPH: PD15MFP Position */
+#define SYS_GPD_MFPH_PD15MFP_Msk (0xful << SYS_GPD_MFPH_PD15MFP_Pos) /*!< SYS_T::GPD_MFPH: PD15MFP Mask */
+
+#define SYS_GPE_MFPL_PE0MFP_Pos (0) /*!< SYS_T::GPE_MFPL: PE0MFP Position */
+#define SYS_GPE_MFPL_PE0MFP_Msk (0xful << SYS_GPE_MFPL_PE0MFP_Pos) /*!< SYS_T::GPE_MFPL: PE0MFP Mask */
+
+#define SYS_GPE_MFPL_PE1MFP_Pos (4) /*!< SYS_T::GPE_MFPL: PE1MFP Position */
+#define SYS_GPE_MFPL_PE1MFP_Msk (0xful << SYS_GPE_MFPL_PE1MFP_Pos) /*!< SYS_T::GPE_MFPL: PE1MFP Mask */
+
+#define SYS_GPE_MFPL_PE2MFP_Pos (8) /*!< SYS_T::GPE_MFPL: PE2MFP Position */
+#define SYS_GPE_MFPL_PE2MFP_Msk (0xful << SYS_GPE_MFPL_PE2MFP_Pos) /*!< SYS_T::GPE_MFPL: PE2MFP Mask */
+
+#define SYS_GPE_MFPL_PE3MFP_Pos (12) /*!< SYS_T::GPE_MFPL: PE3MFP Position */
+#define SYS_GPE_MFPL_PE3MFP_Msk (0xful << SYS_GPE_MFPL_PE3MFP_Pos) /*!< SYS_T::GPE_MFPL: PE3MFP Mask */
+
+#define SYS_GPE_MFPL_PE4MFP_Pos (16) /*!< SYS_T::GPE_MFPL: PE4MFP Position */
+#define SYS_GPE_MFPL_PE4MFP_Msk (0xful << SYS_GPE_MFPL_PE4MFP_Pos) /*!< SYS_T::GPE_MFPL: PE4MFP Mask */
+
+#define SYS_GPE_MFPL_PE5MFP_Pos (20) /*!< SYS_T::GPE_MFPL: PE5MFP Position */
+#define SYS_GPE_MFPL_PE5MFP_Msk (0xful << SYS_GPE_MFPL_PE5MFP_Pos) /*!< SYS_T::GPE_MFPL: PE5MFP Mask */
+
+#define SYS_GPE_MFPL_PE6MFP_Pos (24) /*!< SYS_T::GPE_MFPL: PE6MFP Position */
+#define SYS_GPE_MFPL_PE6MFP_Msk (0xful << SYS_GPE_MFPL_PE6MFP_Pos) /*!< SYS_T::GPE_MFPL: PE6MFP Mask */
+
+#define SYS_GPE_MFPL_PE7MFP_Pos (28) /*!< SYS_T::GPE_MFPL: PE7MFP Position */
+#define SYS_GPE_MFPL_PE7MFP_Msk (0xful << SYS_GPE_MFPL_PE7MFP_Pos) /*!< SYS_T::GPE_MFPL: PE7MFP Mask */
+
+#define SYS_GPE_MFPH_PE8MFP_Pos (0) /*!< SYS_T::GPE_MFPH: PE8MFP Position */
+#define SYS_GPE_MFPH_PE8MFP_Msk (0xful << SYS_GPE_MFPH_PE8MFP_Pos) /*!< SYS_T::GPE_MFPH: PE8MFP Mask */
+
+#define SYS_GPE_MFPH_PE9MFP_Pos (4) /*!< SYS_T::GPE_MFPH: PE9MFP Position */
+#define SYS_GPE_MFPH_PE9MFP_Msk (0xful << SYS_GPE_MFPH_PE9MFP_Pos) /*!< SYS_T::GPE_MFPH: PE9MFP Mask */
+
+#define SYS_GPE_MFPH_PE10MFP_Pos (8) /*!< SYS_T::GPE_MFPH: PE10MFP Position */
+#define SYS_GPE_MFPH_PE10MFP_Msk (0xful << SYS_GPE_MFPH_PE10MFP_Pos) /*!< SYS_T::GPE_MFPH: PE10MFP Mask */
+
+#define SYS_GPE_MFPH_PE11MFP_Pos (12) /*!< SYS_T::GPE_MFPH: PE11MFP Position */
+#define SYS_GPE_MFPH_PE11MFP_Msk (0xful << SYS_GPE_MFPH_PE11MFP_Pos) /*!< SYS_T::GPE_MFPH: PE11MFP Mask */
+
+#define SYS_GPE_MFPH_PE12MFP_Pos (16) /*!< SYS_T::GPE_MFPH: PE12MFP Position */
+#define SYS_GPE_MFPH_PE12MFP_Msk (0xful << SYS_GPE_MFPH_PE12MFP_Pos) /*!< SYS_T::GPE_MFPH: PE12MFP Mask */
+
+#define SYS_GPE_MFPH_PE13MFP_Pos (20) /*!< SYS_T::GPE_MFPH: PE13MFP Position */
+#define SYS_GPE_MFPH_PE13MFP_Msk (0xful << SYS_GPE_MFPH_PE13MFP_Pos) /*!< SYS_T::GPE_MFPH: PE13MFP Mask */
+
+#define SYS_GPE_MFPH_PE14MFP_Pos (24) /*!< SYS_T::GPE_MFPH: PE14MFP Position */
+#define SYS_GPE_MFPH_PE14MFP_Msk (0xful << SYS_GPE_MFPH_PE14MFP_Pos) /*!< SYS_T::GPE_MFPH: PE14MFP Mask */
+
+#define SYS_GPF_MFPL_PF0MFP_Pos (0) /*!< SYS_T::GPF_MFPL: PF0MFP Position */
+#define SYS_GPF_MFPL_PF0MFP_Msk (0xful << SYS_GPF_MFPL_PF0MFP_Pos) /*!< SYS_T::GPF_MFPL: PF0MFP Mask */
+
+#define SYS_GPF_MFPL_PF1MFP_Pos (4) /*!< SYS_T::GPF_MFPL: PF1MFP Position */
+#define SYS_GPF_MFPL_PF1MFP_Msk (0xful << SYS_GPF_MFPL_PF1MFP_Pos) /*!< SYS_T::GPF_MFPL: PF1MFP Mask */
+
+#define SYS_GPF_MFPL_PF2MFP_Pos (8) /*!< SYS_T::GPF_MFPL: PF2MFP Position */
+#define SYS_GPF_MFPL_PF2MFP_Msk (0xful << SYS_GPF_MFPL_PF2MFP_Pos) /*!< SYS_T::GPF_MFPL: PF2MFP Mask */
+
+#define SYS_GPF_MFPL_PF3MFP_Pos (12) /*!< SYS_T::GPF_MFPL: PF3MFP Position */
+#define SYS_GPF_MFPL_PF3MFP_Msk (0xful << SYS_GPF_MFPL_PF3MFP_Pos) /*!< SYS_T::GPF_MFPL: PF3MFP Mask */
+
+#define SYS_GPF_MFPL_PF4MFP_Pos (16) /*!< SYS_T::GPF_MFPL: PF4MFP Position */
+#define SYS_GPF_MFPL_PF4MFP_Msk (0xful << SYS_GPF_MFPL_PF4MFP_Pos) /*!< SYS_T::GPF_MFPL: PF4MFP Mask */
+
+#define SYS_GPF_MFPL_PF5MFP_Pos (20) /*!< SYS_T::GPF_MFPL: PF5MFP Position */
+#define SYS_GPF_MFPL_PF5MFP_Msk (0xful << SYS_GPF_MFPL_PF5MFP_Pos) /*!< SYS_T::GPF_MFPL: PF5MFP Mask */
+
+#define SYS_GPF_MFPL_PF6MFP_Pos (24) /*!< SYS_T::GPF_MFPL: PF6MFP Position */
+#define SYS_GPF_MFPL_PF6MFP_Msk (0xful << SYS_GPF_MFPL_PF6MFP_Pos) /*!< SYS_T::GPF_MFPL: PF6MFP Mask */
+
+#define SYS_GPF_MFPL_PF7MFP_Pos (28) /*!< SYS_T::GPF_MFPL: PF7MFP Position */
+#define SYS_GPF_MFPL_PF7MFP_Msk (0xful << SYS_GPF_MFPL_PF7MFP_Pos) /*!< SYS_T::GPF_MFPL: PF7MFP Mask */
+
+#define SYS_SRAM_INTCTL_PERRIEN_Pos (0) /*!< SYS_T::SRAM_INTCTL: PERRIEN Position */
+#define SYS_SRAM_INTCTL_PERRIEN_Msk (0x1ul << SYS_SRAM_INTCTL_PERRIEN_Pos) /*!< SYS_T::SRAM_INTCTL: PERRIEN Mask */
+
+#define SYS_SRAM_STATUS_PERRIF_Pos (0) /*!< SYS_T::SRAM_STATUS: PERRIF Position */
+#define SYS_SRAM_STATUS_PERRIF_Msk (0x1ul << SYS_SRAM_STATUS_PERRIF_Pos) /*!< SYS_T::SRAM_STATUS: PERRIF Mask */
+
+#define SYS_SRAM_ERRADDR_ERRADDR_Pos (0) /*!< SYS_T::SRAM_ERRADDR: ERRADDR Position */
+#define SYS_SRAM_ERRADDR_ERRADDR_Msk (0xfffffffful << SYS_SRAM_ERRADDR_ERRADDR_Pos) /*!< SYS_T::SRAM_ERRADDR: ERRADDR Mask */
+
+#define SYS_SRAM_BISTCTL_SRBIST0_Pos (0) /*!< SYS_T::SRAM_BISTCTL: SRBIST0 Position */
+#define SYS_SRAM_BISTCTL_SRBIST0_Msk (0x1ul << SYS_SRAM_BISTCTL_SRBIST0_Pos) /*!< SYS_T::SRAM_BISTCTL: SRBIST0 Mask */
+
+#define SYS_SRAM_BISTCTL_SRBIST1_Pos (1) /*!< SYS_T::SRAM_BISTCTL: SRBIST1 Position */
+#define SYS_SRAM_BISTCTL_SRBIST1_Msk (0x1ul << SYS_SRAM_BISTCTL_SRBIST1_Pos) /*!< SYS_T::SRAM_BISTCTL: SRBIST1 Mask */
+
+#define SYS_SRAM_BISTCTL_CRBIST_Pos (2) /*!< SYS_T::SRAM_BISTCTL: CRBIST Position */
+#define SYS_SRAM_BISTCTL_CRBIST_Msk (0x1ul << SYS_SRAM_BISTCTL_CRBIST_Pos) /*!< SYS_T::SRAM_BISTCTL: CRBIST Mask */
+
+#define SYS_SRAM_BISTCTL_CANBIST_Pos (3) /*!< SYS_T::SRAM_BISTCTL: CANBIST Position */
+#define SYS_SRAM_BISTCTL_CANBIST_Msk (0x1ul << SYS_SRAM_BISTCTL_CANBIST_Pos) /*!< SYS_T::SRAM_BISTCTL: CANBIST Mask */
+
+#define SYS_SRAM_BISTCTL_USBBIST_Pos (4) /*!< SYS_T::SRAM_BISTCTL: USBBIST Position */
+#define SYS_SRAM_BISTCTL_USBBIST_Msk (0x1ul << SYS_SRAM_BISTCTL_USBBIST_Pos) /*!< SYS_T::SRAM_BISTCTL: USBBIST Mask */
+
+#define SYS_SRAM_BISTSTS_SRBISTEF0_Pos (0) /*!< SYS_T::SRAM_BISTSTS: SRBISTEF0 Position */
+#define SYS_SRAM_BISTSTS_SRBISTEF0_Msk (0x1ul << SYS_SRAM_BISTSTS_SRBISTEF0_Pos) /*!< SYS_T::SRAM_BISTSTS: SRBISTEF0 Mask */
+
+#define SYS_SRAM_BISTSTS_SRBISTEF1_Pos (1) /*!< SYS_T::SRAM_BISTSTS: SRBISTEF1 Position */
+#define SYS_SRAM_BISTSTS_SRBISTEF1_Msk (0x1ul << SYS_SRAM_BISTSTS_SRBISTEF1_Pos) /*!< SYS_T::SRAM_BISTSTS: SRBISTEF1 Mask */
+
+#define SYS_SRAM_BISTSTS_CRBISTEF_Pos (2) /*!< SYS_T::SRAM_BISTSTS: CRBISTEF Position */
+#define SYS_SRAM_BISTSTS_CRBISTEF_Msk (0x1ul << SYS_SRAM_BISTSTS_CRBISTEF_Pos) /*!< SYS_T::SRAM_BISTSTS: CRBISTEF Mask */
+
+#define SYS_SRAM_BISTSTS_CANBEF_Pos (3) /*!< SYS_T::SRAM_BISTSTS: CANBEF Position */
+#define SYS_SRAM_BISTSTS_CANBEF_Msk (0x1ul << SYS_SRAM_BISTSTS_CANBEF_Pos) /*!< SYS_T::SRAM_BISTSTS: CANBEF Mask */
+
+#define SYS_SRAM_BISTSTS_USBBEF_Pos (4) /*!< SYS_T::SRAM_BISTSTS: USBBEF Position */
+#define SYS_SRAM_BISTSTS_USBBEF_Msk (0x1ul << SYS_SRAM_BISTSTS_USBBEF_Pos) /*!< SYS_T::SRAM_BISTSTS: USBBEF Mask */
+
+#define SYS_SRAM_BISTSTS_SRBEND0_Pos (16) /*!< SYS_T::SRAM_BISTSTS: SRBEND0 Position */
+#define SYS_SRAM_BISTSTS_SRBEND0_Msk (0x1ul << SYS_SRAM_BISTSTS_SRBEND0_Pos) /*!< SYS_T::SRAM_BISTSTS: SRBEND0 Mask */
+
+#define SYS_SRAM_BISTSTS_SRBEND1_Pos (17) /*!< SYS_T::SRAM_BISTSTS: SRBEND1 Position */
+#define SYS_SRAM_BISTSTS_SRBEND1_Msk (0x1ul << SYS_SRAM_BISTSTS_SRBEND1_Pos) /*!< SYS_T::SRAM_BISTSTS: SRBEND1 Mask */
+
+#define SYS_SRAM_BISTSTS_CRBEND_Pos (18) /*!< SYS_T::SRAM_BISTSTS: CRBEND Position */
+#define SYS_SRAM_BISTSTS_CRBEND_Msk (0x1ul << SYS_SRAM_BISTSTS_CRBEND_Pos) /*!< SYS_T::SRAM_BISTSTS: CRBEND Mask */
+
+#define SYS_SRAM_BISTSTS_CANBEND_Pos (19) /*!< SYS_T::SRAM_BISTSTS: CANBEND Position */
+#define SYS_SRAM_BISTSTS_CANBEND_Msk (0x1ul << SYS_SRAM_BISTSTS_CANBEND_Pos) /*!< SYS_T::SRAM_BISTSTS: CANBEND Mask */
+
+#define SYS_SRAM_BISTSTS_USBBEND_Pos (20) /*!< SYS_T::SRAM_BISTSTS: USBBEND Position */
+#define SYS_SRAM_BISTSTS_USBBEND_Msk (0x1ul << SYS_SRAM_BISTSTS_USBBEND_Pos) /*!< SYS_T::SRAM_BISTSTS: USBBEND Mask */
+
+#define SYS_IRCTCTL_FREQSEL_Pos (0) /*!< SYS_T::IRCTCTL: FREQSEL Position */
+#define SYS_IRCTCTL_FREQSEL_Msk (0x3ul << SYS_IRCTCTL_FREQSEL_Pos) /*!< SYS_T::IRCTCTL: FREQSEL Mask */
+
+#define SYS_IRCTCTL_LOOPSEL_Pos (4) /*!< SYS_T::IRCTCTL: LOOPSEL Position */
+#define SYS_IRCTCTL_LOOPSEL_Msk (0x3ul << SYS_IRCTCTL_LOOPSEL_Pos) /*!< SYS_T::IRCTCTL: LOOPSEL Mask */
+
+#define SYS_IRCTCTL_RETRYCNT_Pos (6) /*!< SYS_T::IRCTCTL: RETRYCNT Position */
+#define SYS_IRCTCTL_RETRYCNT_Msk (0x3ul << SYS_IRCTCTL_RETRYCNT_Pos) /*!< SYS_T::IRCTCTL: RETRYCNT Mask */
+
+#define SYS_IRCTCTL_CESTOPEN_Pos (8) /*!< SYS_T::IRCTCTL: CESTOPEN Position */
+#define SYS_IRCTCTL_CESTOPEN_Msk (0x1ul << SYS_IRCTCTL_CESTOPEN_Pos) /*!< SYS_T::IRCTCTL: CESTOPEN Mask */
+
+#define SYS_IRCTIEN_TFAILIEN_Pos (1) /*!< SYS_T::IRCTIEN: TFAILIEN Position */
+#define SYS_IRCTIEN_TFAILIEN_Msk (0x1ul << SYS_IRCTIEN_TFAILIEN_Pos) /*!< SYS_T::IRCTIEN: TFAILIEN Mask */
+
+#define SYS_IRCTIEN_CLKEIEN_Pos (2) /*!< SYS_T::IRCTIEN: CLKEIEN Position */
+#define SYS_IRCTIEN_CLKEIEN_Msk (0x1ul << SYS_IRCTIEN_CLKEIEN_Pos) /*!< SYS_T::IRCTIEN: CLKEIEN Mask */
+
+#define SYS_IRCTISTS_FREQLOCK_Pos (0) /*!< SYS_T::IRCTISTS: FREQLOCK Position */
+#define SYS_IRCTISTS_FREQLOCK_Msk (0x1ul << SYS_IRCTISTS_FREQLOCK_Pos) /*!< SYS_T::IRCTISTS: FREQLOCK Mask */
+
+#define SYS_IRCTISTS_TFAILIF_Pos (1) /*!< SYS_T::IRCTISTS: TFAILIF Position */
+#define SYS_IRCTISTS_TFAILIF_Msk (0x1ul << SYS_IRCTISTS_TFAILIF_Pos) /*!< SYS_T::IRCTISTS: TFAILIF Mask */
+
+#define SYS_IRCTISTS_CLKERRIF_Pos (2) /*!< SYS_T::IRCTISTS: CLKERRIF Position */
+#define SYS_IRCTISTS_CLKERRIF_Msk (0x1ul << SYS_IRCTISTS_CLKERRIF_Pos) /*!< SYS_T::IRCTISTS: CLKERRIF Mask */
+
+#define SYS_REGLCTL_REGLCTL_Pos (0) /*!< SYS_T::REGLCTL: REGLCTL Position */
+#define SYS_REGLCTL_REGLCTL_Msk (0xfful << SYS_REGLCTL_REGLCTL_Pos) /*!< SYS_T::REGLCTL: REGLCTL Mask */
+
+/**@}*/ /* SYS_CONST */
+
+
+typedef struct
+{
+
+/**
+ * @var SYS_INT_T::NMIEN
+ * Offset: 0x00 NMI Source Interrupt Enable Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |BODOUT |BOD NMI Source Enable (Write Protect)
+ * | | |0 = BOD NMI source Disabled.
+ * | | |1 = BOD NMI source Enabled.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[1] |IRC_INT |IRC TRIM NMI Source Enable (Write Protect)
+ * | | |0 = IRC TRIM NMI source Disabled.
+ * | | |1 = IRC TRIM NMI source Enabled.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[2] |PWRWU_INT |Power-Down Mode Wake-Up NMI Source Enable (Write Protect)
+ * | | |0 = Power-down mode wake-up NMI source Disabled.
+ * | | |1 = Power-down mode wake-up NMI source Enabled.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[3] |SRAM_PERR |SRAM ParityCheck Error NMI Source Enable (Write Protect)
+ * | | |0 = SRAM parity check error NMI source Disabled.
+ * | | |1 = SRAM parity check error NMI source Enabled.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[4] |CLKFAIL |Clock Fail Detected NMI Source Enable (Write Protect)
+ * | | |0 = Clock fail detected interrupt NMI source Disabled.
+ * | | |1 = Clock fail detected interrupt NMI source Enabled.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[6] |RTC_INT |RTC NMI Source Enable (Write Protect)
+ * | | |0 = RTC NMI source Disabled.
+ * | | |1 = RTC NMI source Enabled.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[7] |TAMPER_INT|TAMPER_INT NMI Source Enable (Write Protect)
+ * | | |0 = Backup register tamper detected interrupt.NMI source Disabled.
+ * | | |1 = Backup register tamper detected interrupt.NMI source Enabled.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[8] |EINT0 |External Interrupt From PA.0, PD.2 Or PE.4 Pin NMI Source Enable (Write Protect)
+ * | | |0 = External interrupt from PA.0, PD.2 or PE.4 pin NMI source Disabled.
+ * | | |1 = External interrupt from PA.0, PD.2 or PE.4 pin NMI source Enabled.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[9] |EINT1 |External Interrupt From PB.0, PD.3 Or PE.5 Pin NMI Source Enable (Write Protect)
+ * | | |0 = External interrupt from PB.0, PD.3 or PE.5 pin NMI source Disabled.
+ * | | |1 = External interrupt from PB.0, PD.3 or PE.5 pin NMI source Enabled.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[10] |EINT2 |External Interrupt From PC.0 Pin NMI Source Enable (Write Protect)
+ * | | |0 = External interrupt from PC.0 pin NMI source Disabled.
+ * | | |1 = External interrupt from PC.0 pin NMI source Enabled.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[11] |EINT3 |External Interrupt From PD.0 Pin NMI Source Enable (Write Protect)
+ * | | |0 = External interrupt from PD.0 pin NMI source Disabled.
+ * | | |1 = External interrupt from PD.0 pin NMI source Enabled.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[12] |EINT4 |External Interrupt From PE.0 Pin NMI Source Enable (Write Protect)
+ * | | |0 = External interrupt from PE.0 pin NMI source Disabled.
+ * | | |1 = External interrupt from PE.0 pin NMI source Enabled.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[13] |EINT5 |External Interrupt From PF.0 Pin NMI Source Enable (Write Protect)
+ * | | |0 = External interrupt from PF.0 pin NMI source Disabled.
+ * | | |1 = External interrupt from PF.0 pin NMI source Enabled.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[14] |UART0_INT |UART0 NMI Source Enable (Write Protect)
+ * | | |0 = UART0 NMI source Disabled.
+ * | | |1 = UART0 NMI source Enabled.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[15] |UART1_INT |UART1 NMI Source Enable (Write Protect)
+ * | | |0 = UART1 NMI source Disabled.
+ * | | |1 = UART1 NMI source Enabled.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * @var SYS_INT_T::NMISTS
+ * Offset: 0x04 NMI source interrupt Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |BODOUT |BOD Interrupt Flag (Read Only)
+ * | | |0 = BOD interrupt is deasserted.
+ * | | |1 = BOD interrupt is asserted.
+ * |[1] |IRC_INT |IRC TRIM Interrupt Flag (Read Only)
+ * | | |0 = HIRC TRIM interrupt is deasserted.
+ * | | |1 = HIRC TRIM interrupt is asserted.
+ * |[2] |PWRWU_INT |Power-Down Mode Wake-Up Interrupt Flag (Read Only)
+ * | | |0 = Power-down mode wake-up interrupt is deasserted.
+ * | | |1 = Power-down mode wake-up interrupt is asserted.
+ * |[3] |SRAM_PERR |SRAM ParityCheck Error Interrupt Flag (Read Only)
+ * | | |0 = SRAM parity check error interrupt is deasserted.
+ * | | |1 = SRAM parity check error interrupt is asserted.
+ * |[4] |CLKFAIL |Clock Fail Detected Interrupt Flag (Read Only)
+ * | | |0 = Clock fail detected interrupt is deasserted.
+ * | | |1 = Clock fail detected interrupt is asserted.
+ * |[6] |RTC_INT |RTC Interrupt Flag (Read Only)
+ * | | |0 = RTC interrupt is deasserted.
+ * | | |1 = RTC interrupt is asserted.
+ * |[7] |TAMPER_INT|TAMPER_INT Interrupt Flag (Read Only)
+ * | | |0 = Backup register tamper detected interrupt is deasserted.
+ * | | |1 = Backup register tamper detected interrupt is asserted.
+ * |[8] |EINT0 |External Interrupt From PA.0, PD.2 Or PE.4 Pin Interrupt Flag (Read Only)
+ * | | |0 = External Interrupt from PA.0, PD.2 or PE.4 interrupt is deasserted.
+ * | | |1 = External Interrupt from PA.0, PD.2 or PE.4 interrupt is asserted.
+ * |[9] |EINT1 |External Interrupt From PB.0, PD.3 Or PE.5 Pin Interrupt Flag (Read Only)
+ * | | |0 = External Interrupt from PB.0, PD.3 or PE.5 interrupt is deasserted.
+ * | | |1 = External Interrupt from PB.0, PD.3 or PE.5 interrupt is asserted.
+ * |[10] |EINT2 |External Interrupt From PC.0 Pin Interrupt Flag (Read Only)
+ * | | |0 = External Interrupt from PC.0 interrupt is deasserted.
+ * | | |1 = External Interrupt from PC.0 interrupt is asserted.
+ * |[11] |EINT3 |External Interrupt From PD.0 Pin Interrupt Flag (Read Only)
+ * | | |0 = External Interrupt from PD.0 interrupt is deasserted.
+ * | | |1 = External Interrupt from PD.0 interrupt is asserted.
+ * |[12] |EINT4 |External Interrupt From PE.0 Pin Interrupt Flag (Read Only)
+ * | | |0 = External Interrupt from PE.0 interrupt is deasserted.
+ * | | |1 = External Interrupt from PE.0 interrupt is asserted.
+ * |[13] |EINT5 |External Interrupt From PF.0 Pin Interrupt Flag (Read Only)
+ * | | |0 = External Interrupt from PF.0 interrupt is deasserted.
+ * | | |1 = External Interrupt from PF.0 interrupt is asserted.
+ * |[14] |UART0_INT |UART0 Interrupt Flag (Read Only)
+ * | | |0 = UART1 interrupt is deasserted.
+ * | | |1 = UART1 interrupt is asserted.
+ * |[15] |UART1_INT |UART1 Interrupt Flag (Read Only)
+ * | | |0 = UART1 interrupt is deasserted.
+ * | | |1 = UART1 interrupt is asserted.
+ */
+
+ __IO uint32_t NMIEN; /* Offset: 0x00 NMI Source Interrupt Enable Register */
+ __I uint32_t NMISTS; /* Offset: 0x04 NMI source interrupt Status Register */
+
+} SYS_INT_T;
+
+
+
+/**
+ @addtogroup INT_CONST INT Bit Field Definition
+ Constant Definitions for SYS Controller
+@{ */
+
+#define SYS_NMIEN_BODOUT_Pos (0) /*!< SYS_INT_T::NMIEN: BODOUT Position */
+#define SYS_NMIEN_BODOUT_Msk (0x1ul << SYS_NMIEN_BODOUT_Pos ) /*!< SYS_INT_T::NMIEN: BODOUT Mask */
+
+#define SYS_NMIEN_IRC_INT_Pos (1) /*!< SYS_INT_T::NMIEN: IRC_INT Position */
+#define SYS_NMIEN_IRC_INT_Msk (0x1ul << SYS_NMIEN_IRC_INT_Pos ) /*!< SYS_INT_T::NMIEN: IRC_INT Mask */
+
+#define SYS_NMIEN_PWRWU_INT_Pos (2) /*!< SYS_INT_T::NMIEN: PWRWU_INT Position */
+#define SYS_NMIEN_PWRWU_INT_Msk (0x1ul << SYS_NMIEN_PWRWU_INT_Pos ) /*!< SYS_INT_T::NMIEN: PWRWU_INT Mask */
+
+#define SYS_NMIEN_SRAM_PERR_Pos (3) /*!< SYS_INT_T::NMIEN: SRAM_PERR Position */
+#define SYS_NMIEN_SRAM_PERR_Msk (0x1ul << SYS_NMIEN_SRAM_PERR_Pos ) /*!< SYS_INT_T::NMIEN: SRAM_PERR Mask */
+
+#define SYS_NMIEN_CLKFAIL_Pos (4) /*!< SYS_INT_T::NMIEN: CLKFAIL Position */
+#define SYS_NMIEN_CLKFAIL_Msk (0x1ul << SYS_NMIEN_CLKFAIL_Pos ) /*!< SYS_INT_T::NMIEN: CLKFAIL Mask */
+
+#define SYS_NMIEN_RTC_INT_Pos (6) /*!< SYS_INT_T::NMIEN: RTC_INT Position */
+#define SYS_NMIEN_RTC_INT_Msk (0x1ul << SYS_NMIEN_RTC_INT_Pos ) /*!< SYS_INT_T::NMIEN: RTC_INT Mask */
+
+#define SYS_NMIEN_TAMPER_INT_Pos (7) /*!< SYS_INT_T::NMIEN: TAMPER_INT Position */
+#define SYS_NMIEN_TAMPER_INT_Msk (0x1ul << SYS_NMIEN_TAMPER_INT_Pos ) /*!< SYS_INT_T::NMIEN: TAMPER_INT Mask */
+
+#define SYS_NMIEN_EINT0_Pos (8) /*!< SYS_INT_T::NMIEN: EINT0 Position */
+#define SYS_NMIEN_EINT0_Msk (0x1ul << SYS_NMIEN_EINT0_Pos ) /*!< SYS_INT_T::NMIEN: EINT0 Mask */
+
+#define SYS_NMIEN_EINT1_Pos (9) /*!< SYS_INT_T::NMIEN: EINT1 Position */
+#define SYS_NMIEN_EINT1_Msk (0x1ul << SYS_NMIEN_EINT1_Pos ) /*!< SYS_INT_T::NMIEN: EINT1 Mask */
+
+#define SYS_NMIEN_EINT2_Pos (10) /*!< SYS_INT_T::NMIEN: EINT2 Position */
+#define SYS_NMIEN_EINT2_Msk (0x1ul << SYS_NMIEN_EINT2_Pos ) /*!< SYS_INT_T::NMIEN: EINT2 Mask */
+
+#define SYS_NMIEN_EINT3_Pos (11) /*!< SYS_INT_T::NMIEN: EINT3 Position */
+#define SYS_NMIEN_EINT3_Msk (0x1ul << SYS_NMIEN_EINT3_Pos ) /*!< SYS_INT_T::NMIEN: EINT3 Mask */
+
+#define SYS_NMIEN_EINT4_Pos (12) /*!< SYS_INT_T::NMIEN: EINT4 Position */
+#define SYS_NMIEN_EINT4_Msk (0x1ul << SYS_NMIEN_EINT4_Pos ) /*!< SYS_INT_T::NMIEN: EINT4 Mask */
+
+#define SYS_NMIEN_EINT5_Pos (13) /*!< SYS_INT_T::NMIEN: EINT5 Position */
+#define SYS_NMIEN_EINT5_Msk (0x1ul << SYS_NMIEN_EINT5_Pos ) /*!< SYS_INT_T::NMIEN: EINT5 Mask */
+
+#define SYS_NMIEN_UART0_INT_Pos (14) /*!< SYS_INT_T::NMIEN: UART0_INT Position */
+#define SYS_NMIEN_UART0_INT_Msk (0x1ul << SYS_NMIEN_UART0_INT_Pos ) /*!< SYS_INT_T::NMIEN: UART0_INT Mask */
+
+#define SYS_NMIEN_UART1_INT_Pos (15) /*!< SYS_INT_T::NMIEN: UART1_INT Position */
+#define SYS_NMIEN_UART1_INT_Msk (0x1ul << SYS_NMIEN_UART1_INT_Pos ) /*!< SYS_INT_T::NMIEN: UART1_INT Mask */
+
+#define SYS_NMISTS_BODOUT_Pos (0) /*!< SYS_INT_T::NMISTS: BODOUT Position */
+#define SYS_NMISTS_BODOUT_Msk (0x1ul << SYS_NMISTS_BODOUT_Pos ) /*!< SYS_INT_T::NMISTS: BODOUT Mask */
+
+#define SYS_NMISTS_IRC_INT_Pos (1) /*!< SYS_INT_T::NMISTS: IRC_INT Position */
+#define SYS_NMISTS_IRC_INT_Msk (0x1ul << SYS_NMISTS_IRC_INT_Pos ) /*!< SYS_INT_T::NMISTS: IRC_INT Mask */
+
+#define SYS_NMISTS_PWRWU_INT_Pos (2) /*!< SYS_INT_T::NMISTS: PWRWU_INT Position */
+#define SYS_NMISTS_PWRWU_INT_Msk (0x1ul << SYS_NMISTS_PWRWU_INT_Pos ) /*!< SYS_INT_T::NMISTS: PWRWU_INT Mask */
+
+#define SYS_NMISTS_SRAM_PERR_Pos (3) /*!< SYS_INT_T::NMISTS: SRAM_PERR Position */
+#define SYS_NMISTS_SRAM_PERR_Msk (0x1ul << SYS_NMISTS_SRAM_PERR_Pos ) /*!< SYS_INT_T::NMISTS: SRAM_PERR Mask */
+
+#define SYS_NMISTS_CLKFAIL_Pos (4) /*!< SYS_INT_T::NMISTS: CLKFAIL Position */
+#define SYS_NMISTS_CLKFAIL_Msk (0x1ul << SYS_NMISTS_CLKFAIL_Pos ) /*!< SYS_INT_T::NMISTS: CLKFAIL Mask */
+
+#define SYS_NMISTS_RTC_INT_Pos (6) /*!< SYS_INT_T::NMISTS: RTC_INT Position */
+#define SYS_NMISTS_RTC_INT_Msk (0x1ul << SYS_NMISTS_RTC_INT_Pos ) /*!< SYS_INT_T::NMISTS: RTC_INT Mask */
+
+#define SYS_NMISTS_TAMPER_INT_Pos (7) /*!< SYS_INT_T::NMISTS: TAMPER_INT Position */
+#define SYS_NMISTS_TAMPER_INT_Msk (0x1ul << SYS_NMISTS_TAMPER_INT_Pos ) /*!< SYS_INT_T::NMISTS: TAMPER_INT Mask */
+
+#define SYS_NMISTS_EINT0_Pos (8) /*!< SYS_INT_T::NMISTS: EINT0 Position */
+#define SYS_NMISTS_EINT0_Msk (0x1ul << SYS_NMISTS_EINT0_Pos ) /*!< SYS_INT_T::NMISTS: EINT0 Mask */
+
+#define SYS_NMISTS_EINT1_Pos (9) /*!< SYS_INT_T::NMISTS: EINT1 Position */
+#define SYS_NMISTS_EINT1_Msk (0x1ul << SYS_NMISTS_EINT1_Pos ) /*!< SYS_INT_T::NMISTS: EINT1 Mask */
+
+#define SYS_NMISTS_EINT2_Pos (10) /*!< SYS_INT_T::NMISTS: EINT2 Position */
+#define SYS_NMISTS_EINT2_Msk (0x1ul << SYS_NMISTS_EINT2_Pos ) /*!< SYS_INT_T::NMISTS: EINT2 Mask */
+
+#define SYS_NMISTS_EINT3_Pos (11) /*!< SYS_INT_T::NMISTS: EINT3 Position */
+#define SYS_NMISTS_EINT3_Msk (0x1ul << SYS_NMISTS_EINT3_Pos ) /*!< SYS_INT_T::NMISTS: EINT3 Mask */
+
+#define SYS_NMISTS_EINT4_Pos (12) /*!< SYS_INT_T::NMISTS: EINT4 Position */
+#define SYS_NMISTS_EINT4_Msk (0x1ul << SYS_NMISTS_EINT4_Pos ) /*!< SYS_INT_T::NMISTS: EINT4 Mask */
+
+#define SYS_NMISTS_EINT5_Pos (13) /*!< SYS_INT_T::NMISTS: EINT5 Position */
+#define SYS_NMISTS_EINT5_Msk (0x1ul << SYS_NMISTS_EINT5_Pos ) /*!< SYS_INT_T::NMISTS: EINT5 Mask */
+
+#define SYS_NMISTS_UART0_INT_Pos (14) /*!< SYS_INT_T::NMISTS: UART0_INT Position */
+#define SYS_NMISTS_UART0_INT_Msk (0x1ul << SYS_NMISTS_UART0_INT_Pos ) /*!< SYS_INT_T::NMISTS: UART0_INT Mask */
+
+#define SYS_NMISTS_UART1_INT_Pos (15) /*!< SYS_INT_T::NMISTS: UART1_INT Position */
+#define SYS_NMISTS_UART1_INT_Msk (0x1ul << SYS_NMISTS_UART1_INT_Pos ) /*!< SYS_INT_T::NMISTS: UART1_INT Mask */
+
+/**@}*/ /* INT_CONST */
+/**@}*/ /* end of SYS register group */
+
+
+/*---------------------- Touch Key Controller -------------------------*/
+/**
+ @addtogroup TK Touch Key Controller(TK)
+ Memory Mapped Structure for TK Controller
+@{ */
+
+
+typedef struct
+{
+
+
+/**
+ * @var TK_T::CTL
+ * Offset: 0x00 Touch Key Scan Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |TKSEN0 |TK0 Scan Enable Bit
+ * | | |This bit is ignored if TKREN0 (TK_REFCTL[0]) is "1" except SCANALL (TK_REFCTL[23]) is "1".
+ * | | |0 = TKDAT0 (TK_DAT0[7:0]) is invalid.
+ * | | |1 = TK0 is always enable for Touch Key scan. TKDAT0 (TK_DAT0[7:0]) is valid.
+ * |[1] |TKSEN1 |TK1 Scan Enable Bit
+ * | | |This bit is ignored if TKREN1 (TK_REFCTL[1]) is "1".
+ * | | |0 = TKDAT1 (TK_DAT0[15:8]) is invalid.
+ * | | |1 = TK1 is always enable for Touch Key scan. TKDAT1 (TK_DAT0[15:8]) is valid.
+ * |[2] |TKSEN2 |TK2 Scan Enable Bit
+ * | | |This bit is ignored if TKREN2 (TK_REFCTL[2]) is "1".
+ * | | |0 = TKDAT2 (TK_DAT0[23:16]) is invalid.
+ * | | |1 = TK2 is always enable for Touch Key scan. TKDAT2 (TK_DAT0[23:16]) is valid.
+ * |[3] |TKSEN3 |TK3 Scan Enable Bit
+ * | | |0 = TKDAT3 (TK_DAT0[31:24]) is invalid.
+ * | | |1 = TK3 is always enable for Touch Key scan. TKDAT3 (TK_DAT0[31:24]) is valid.
+ * | | |This bit is ignored if TKREN3 (TK_REFCTL[3]) is "1".
+ * |[4] |TKSEN4 |TK4 Scan Enable Bit
+ * | | |This bit is ignored if TKREN4 (TK_REFCTL[4]) is "1".
+ * | | |0 = TKDAT4 (TK_DAT1[7:0]) is invalid.
+ * | | |1 = TK4 is always enable for Touch Key scan. TKDAT4 (TK_DAT1[7:0]) is valid.
+ * |[5] |TKSEN5 |TK5 Scan Enable Bit
+ * | | |This bit is ignored if TKREN5 (TK_REFCTL[5]) is "1".
+ * | | |0 = TKDAT5 (TK_DAT1[15:8]) is invalid.
+ * | | |1 = TK5 is always enable for Touch Key scan. TKDAT5 (TK_DAT1[15:8]) is valid.
+ * |[6] |TKSEN6 |TK6 Scan Enable Bit
+ * | | |This bit is ignored if TKREN6 (TK_REFCTL[6]) is "1".
+ * | | |0 = TKDAT6 (TK_DAT1[23:16]) is invalid.
+ * | | |1 = TK6 is always enable for Touch Key scan. TKDAT6 (TK_DAT1[23:16]) is valid.
+ * |[7] |TKSEN7 |TK7 Scan Enable
+ * | | |This bit is ignored if TKREN7 (TK_REFCTL[7]) is "1".
+ * | | |0 = TKDAT7 (TK_DAT1[31:24]) is invalid.
+ * | | |1 = TK7 is always enable for Touch Key scan. TKDAT7 (TK_DAT1[31:24]) is valid.
+ * |[8] |TKSEN8 |TK8 Scan Enable Bit
+ * | | |This bit is ignored if TKREN8 (TK_REFCTL[8]) is "1".
+ * | | |0 = TKDAT8 (TK_DAT2[7:0]) is invalid.
+ * | | |1 = TK8 is always enable for Touch Key scan. TKDAT8 (TK_DAT2[7:0]) is valid.
+ * |[9] |TKSEN9 |TK9 Scan Enable Bit
+ * | | |This bit is ignored if TKREN9 (TK_REFCTL[9]) is "1".
+ * | | |0 = TKDAT9 (TK_DAT2[15:8]) is invalid.
+ * | | |1 = TK9 is always enable for Touch Key scan. TKDAT9 (TK_DAT2[15:8]) is valid.
+ * |[10] |TKSEN10 |TK10 Scan Enable Bit
+ * | | |This bit is ignored if TKREN10 (TK_REFCTL[10]) is "1".
+ * | | |0 = TKDAT10 (TK_DAT2[23:16]) is invalid.
+ * | | |1 = TK10 is always enable for Touch Key scan. TKDAT10 (TK_DAT2[23:16]) is valid.
+ * |[11] |TKSEN11 |TK11 Scan Enable
+ * | | |This bit is ignored if TKREN11 (TK_REFCTL[11]) is "1".
+ * | | |0 = TKDAT11 (TK_DAT2[31:24]) is invalid.
+ * | | |1 = TK11 is always enable for Touch Key scan. TKDAT11 (TK_DAT2[31:24]) is valid.
+ * |[12] |TKSEN12 |TK12 Scan Enable Bit
+ * | | |This bit is ignored if TKREN12 (TK_REFCTL[12]) is "1".
+ * | | |0 = TKDAT12 (TK_DAT3[7:0]) is invalid.
+ * | | |1 = TK12 is always enable for Touch Key scan. TKDAT12 (TK_DAT3[7:0]) is valid.
+ * |[13] |TKSEN13 |TK13 Scan Enable Bit
+ * | | |This bit is ignored if TKREN13 (TK_REFCTL[13]) is "1".
+ * | | |0 = TKDAT13 (TK_DAT3[15:8]) is invalid.
+ * | | |1 = TK13 is always enable for key scan. TKDAT13 (TK_DAT3[15:8]) is valid.
+ * |[14] |TKSEN14 |TK14 Scan Enable Bit
+ * | | |This bit is ignored if TKREN14 (TK_REFCTL[14]) is "1".
+ * | | |0 = TKDAT14 (TK_DAT3[23:16]) is invalid.
+ * | | |1 = TK14 is always enabled for key scan. TKDAT14 (TK_DAT3[23:16]) is valid.
+ * |[15] |TKSEN15 |TK15 Scan Enable Bit
+ * | | |This bit is ignored if TKREN15 (TK_REFCTL[15]) is "1".
+ * | | |0 = TKDAT15 (TK_DAT3[31:24]) is invalid.
+ * | | |1 = TK15 is always enabled for key scan. TKDAT15 (TK_DAT3[31:24]) is valid.
+ * |[16] |TKSEN16 |TK16 Scan Enable Bit
+ * | | |This bit is ignored if TKREN16 (TK_REFCTL[16]) is "1".
+ * | | |0 = TKDAT16 (TK_DAT4[7:0]) is invalid.
+ * | | |1 = TK16 is always enabled for key scan. TKDAT16 (TK_DAT4[7:0]) is valid.
+ * |[22:20] |AVCCHSEL |AVCCH Voltage Select
+ * | | |000 = 1/16 VDD.
+ * | | |001 = 1/8 VDD.
+ * | | |010 = 3/16 VDD.
+ * | | |011 = 1/4 VDD.
+ * | | |100 = 5/16 VDD.
+ * | | |101 = 3/8 VDD.
+ * | | |110 = 7/16 VDD.
+ * | | |111 = 1/2 VDD.
+ * |[24] |SCAN |Scan
+ * | | |Write an '1' to this bit will immediately initiate key scan on all channels which are enabled.
+ * | | |This bit will be self-cleared after key scan started.
+ * |[25] |TMRTRGEN |Timer Trigger Enable Bit
+ * | | |0 = Disable timer to trigger key scan.
+ * | | |1 = Enable timer triggers key scan periodically. Key scan will be initiated by Timer0 periodically.
+ * |[31] |TKEN |Touch Key Scan Enable Bit
+ * | | |0 = Disable Touch Key Function.
+ * | | |1 = Enable Touch Key Function.
+ * @var TK_T::REFCTL
+ * Offset: 0x04 Touch Key Reference Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |TKREN0 |TK0 Reference Enable Bit
+ * | | |0 = TK0 is not reference.
+ * | | |1 = TK0 is set as reference, and TKDAT0 (TK_DAT0[7:0]) is invalid except SCANALL (TK_REFCTL[23]) is "1".
+ * |[1] |TKREN1 |TK1 Reference Enable Bit
+ * | | |0 = TK1 is not reference.
+ * | | |1 = TK1 is set as reference, and TKDAT1 (TK_DAT0[15:8]) is invalid.
+ * |[2] |TKREN2 |TK2 Reference Enable Bit
+ * | | |0 = TK2 is not reference.
+ * | | |1 = TK2 is set as reference, and TKDAT2 (TK_DAT0[23:16]) is invalid.
+ * |[3] |TKREN3 |TK3 Reference Enable Bit
+ * | | |0 = TK3 is not reference.
+ * | | |1 = TK3 is set as reference, and TKDAT3 (TK_DAT0[31:24]) is invalid.
+ * |[4] |TKREN4 |TK4 Reference Enable Bit
+ * | | |0 = TK4 is not reference.
+ * | | |1 = TK4 is set as reference, and TKDAT4 (TK_DAT1[7:0]) is invalid.
+ * |[5] |TKREN5 |TK5 Reference Enable Bit
+ * | | |0 = TK5 is not reference.
+ * | | |1 = TK5 is set as reference, and TKDAT5 (TK_DAT1[15:8]) is invalid.
+ * |[6] |TKREN6 |TK6 Reference Enable Bit
+ * | | |0 = TK6 is not reference.
+ * | | |1 = TK6 is set as reference, and TKDAT6 (TK_DAT1[23:16]) is invalid.
+ * |[7] |TKREN7 |TK7 Reference Enable Bit
+ * | | |0 = TK7 is not reference.
+ * | | |1 = TK7 is set as reference, and TKDAT7 (TK_DAT1[31:24]) is invalid.
+ * |[8] |TKREN8 |TK8 Reference Enable Bit
+ * | | |0 = TK8 is not reference.
+ * | | |1 = TK8 is set as reference, and TKDAT8 (TK_DAT2[7:0]) is invalid.
+ * |[9] |TKREN9 |TK9 Reference Enable Bit
+ * | | |0 = TK9 is not reference.
+ * | | |1 = TK9 is set as reference, and TKDAT9 (TK_DAT2[15:8]) is invalid.
+ * |[10] |TKREN10 |TK10 Reference Enable Bit
+ * | | |0 = TK10 is not reference.
+ * | | |1 = TK10 is set as reference, and TKDAT10 (TK_DAT2[23:16]) is invalid.
+ * |[11] |TKREN11 |TK11 Reference Enable Bit
+ * | | |0 = TK11 is not reference.
+ * | | |1 = TK11 is set as reference, and TKDAT11 (TK_DAT2[31:24]) is invalid.
+ * |[12] |TKREN12 |TK12 Reference Enable Bit
+ * | | |0 = TK12 is not reference.
+ * | | |1 = TK12 is set as reference, and TKDAT12 (TK_DAT3[7:0]) is invalid.
+ * |[13] |TKREN13 |TK13 Reference Enable Bit
+ * | | |0 = TK13 is not reference.
+ * | | |1 = TK13 is set as reference, and TKDAT13 (TK_DAT3[15:8]) is invalid.
+ * |[14] |TKREN14 |TK14 Reference Enable Bit
+ * | | |0 = TK14 is not reference.
+ * | | |1 = TK14 is set as reference, and TKDAT14 (TK_DAT3[23:16]) is invalid.
+ * |[15] |TKREN15 |TK15 Reference Enable Bit
+ * | | |0 = TK15 is not reference.
+ * | | |1 = TK15 is set as reference, and TKDAT15 (TK_DAT3[31:24]) is invalid.
+ * |[16] |TKREN16 |TK16 Reference Enable Bit
+ * | | |0 = TK16 is not reference.
+ * | | |1 = TK16 is set as reference, and TKDAT16 (TK_DAT4[7:0]) is invalid.
+ * | | |Note: This bit is forced to "1" automatically if none is set as reference.
+ * |[23] |SCANALL |All Key Scan Enable Bit
+ * | | |This function is used for low power key scanning operation.
+ * | | |TKDAT0 (TK_DAT0[7:0]) is the only one valid data when key scan is complete.
+ * | | |0 = Disable All Keys Scan function.
+ * | | |1 = Enable All Keys Scan function.
+ * |[25:24] |SENTCTL |Touch Key Sensing Time Control
+ * | | |00 = 128 x SENPTCTL.
+ * | | |01 = 255 x SENPTCTL.
+ * | | |10 = 511 x SENPTCTL.
+ * | | |11 = 1023 x SENPTCTL.
+ * |[29:28] |SENPTCTL |Touch Key Sensing Pulse Width Time Control
+ * | | |00 = 1us.
+ * | | |01 = 2us.
+ * | | |10 = 4us.
+ * | | |11 = 8us.
+ * @var TK_T::CCBDAT0
+ * Offset: 0x08 Touch Key Complement Capacitor Bank Data Register 0
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:0] |CCBDAT0 |TK0 Complement CB Data
+ * | | |This is register is used for TK0 sensitivity adjustment.
+ * |[15:8] |CCBDAT1 |TK1 Complement CB Data
+ * | | |This is register is used for TK1 sensitivity adjustment.
+ * |[23:16] |CCBDAT2 |TK2 Complement CB Data
+ * | | |This is register is used for TK2 sensitivity adjustment.
+ * |[31:24] |CCBDAT3 |TK3 Complement CB Data
+ * | | |This is register is used for TK3 sensitivity adjustment.
+ * @var TK_T::CCBDAT1
+ * Offset: 0x0C Touch Key Complement Capacitor Bank Data Register 1
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:0] |CCBDAT4 |TK4 Complement CB Data
+ * | | |This is register is used for TK4 sensitivity adjustment.
+ * |[15:8] |CCBDAT5 |TK5 Complement CB Data
+ * | | |This is register is used for TK5 sensitivity adjustment.
+ * |[23:16] |CCBDAT6 |TK6 Complement CB Data
+ * | | |This is register is used for TK6 sensitivity adjustment.
+ * |[31:24] |CCBDAT7 |TK7 Complement CB Data
+ * | | |This is register is used for TK7 sensitivity adjustment.
+ * @var TK_T::CCBDAT2
+ * Offset: 0x10 Touch Key Complement Capacitor Bank Data Register 2
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:0] |CCBDAT8 |TK8 Complement CB Data
+ * | | |This is register is used for TK8 sensitivity adjustment.
+ * |[15:8] |CCBDAT9 |TK9 Complement CB Data
+ * | | |This is register is used for TK9 sensitivity adjustment.
+ * |[23:16] |CCBDAT10 |TK10 Complement CB Data
+ * | | |This is register is used for TK10 sensitivity adjustment.
+ * |[31:24] |CCBDAT11 |TK11 Complement CB Data
+ * | | |This is register is used for TK11 sensitivity adjustment.
+ * @var TK_T::CCBDAT3
+ * Offset: 0x14 Touch Key Complement Capacitor Bank Data Register 3
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:0] |CCBDAT12 |TK12 Complement CB Data
+ * | | |This is register is used for TK12 sensitivity adjustment.
+ * |[15:8] |CCBDAT13 |TK13 Complement CB Data
+ * | | |This is register is used for TK13 sensitivity adjustment.
+ * |[23:16] |CCBDAT14 |TK14 Complement CB Data
+ * | | |This is register is used for TK14 sensitivity adjustment.
+ * |[31:24] |CCBDAT15 |TK15 Complement CB Data
+ * | | |This is register is used for TK15 sensitivity adjustment.
+ * @var TK_T::CCBDAT4
+ * Offset: 0x18 Touch Key Complement Capacitor Bank Data Register 4
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:0] |CCBDAT16 |TK16 Complement CB Data
+ * | | |This is register is used for TK16 sensitivity adjustment.
+ * |[31:24] |REFCBDAT |Reference CB Data
+ * @var TK_T::IDLESEL
+ * Offset: 0x1C Touch Key Idle State Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |IDLSn |TKn Idle State Control
+ * | | |This register is ignored if both TKSENn (TK_CTL[n]) and POLENn (TK_POLCTL[n+8]) are "0" or TKRENn (TK_REFCTL[n]) is "1".
+ * | | |00 = TKn connected to GND.
+ * | | |01 = TKn connected to AVCCH.
+ * | | |10 = TKn connected to VDD.
+ * | | |11 = TKn connected to VDD.
+ * | | |n = 0 to 15.
+ * @var TK_T::POLSEL
+ * Offset: 0x20 Touch Key Polarity Select Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |POLSELn |TKn Polarity Select
+ * | | |This register is ignored if POLENn (TK_POLCTL[n+8]) is "0", or either TKSENn (TK_CTL[n]) or TKRENn (TK_REFCTL[n]) is "1".
+ * | | |00 = TKn connected to Gnd.
+ * | | |01 = TKn connected to AVCCH.
+ * | | |10 = TKn connected to VDD.
+ * | | |11 = TKn connected to VDD.
+ * @var TK_T::POLCTL
+ * Offset: 0x24 Touch Key Polarity Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[1:0] |IDLS16 |TK16 Idle State Control
+ * | | |This register is ignored if both TKSEN16 (TK_CTL[16]) and POLEN16 (TK_POLCTL[24]) are "0" or TKREN16 (TK_REFCTL[16]) is "1".
+ * | | |00 = TK16 connected to Gnd.
+ * | | |01 = TK16 connected to AVCCH.
+ * | | |10 = TK16 connected to VDD.
+ * | | |11 = TK16 connected to VDD.
+ * |[3:2] |POLSEL16 |TK16 Polarity Control
+ * | | |This register is ignored if POLEN16 (TK_POLCTL[24]) is "0", or either TKSEN16 (TK_CTL[16]) or TKREN16 (TK_REFCTL[16]) is "1".
+ * | | |00 = TK16 connected to Gnd.
+ * | | |01 = TK16 connected to AVCCH.
+ * | | |10 = TK16 connected to VDD.
+ * | | |11 = TK16 connected to VDD.
+ * |[5:4] |CBPOLSEL |Capacitor Bank Polarity Select
+ * | | |00 = Gnd.
+ * | | |01 = AVCCH.
+ * | | |10 = VDD.
+ * | | |11 = VDD.
+ * |[8] |POLEN0 |TK0 Polarity Function Enable Control
+ * | | |0 = Disabled.
+ * | | |1 = Enabled.
+ * |[9] |POLEN1 |TK1 Polarity Function Enable Control
+ * | | |0 = Disabled.
+ * | | |1 = Enabled.
+ * |[10] |POLEN2 |TK2 Polarity Function Enable Control
+ * | | |0 = Disabled.
+ * | | |1 = Enabled.
+ * |[11] |POLEN3 |TK3 Polarity Function Enable Control
+ * | | |0 = Disabled.
+ * | | |1 = Enabled.
+ * |[12] |POLEN4 |TK4 Polarity Function Enable Control
+ * | | |0 = Disabled.
+ * | | |1 = Enabled.
+ * |[13] |POLEN5 |TK5 Polarity Function Enable Control
+ * | | |0 = Disabled.
+ * | | |1 = Enabled.
+ * |[14] |POLEN6 |TK6 Polarity Function Enable Control
+ * | | |0 = Disabled.
+ * | | |1 = Enabled.
+ * |[15] |POLEN7 |TK7 Polarity Function Enable Control
+ * | | |0 = Disabled.
+ * | | |1 = Enabled.
+ * |[16] |POLEN8 |TK8 Polarity Function Enable Control
+ * | | |0 = Disabled.
+ * | | |1 = Enabled.
+ * |[17] |POLEN9 |TK9 Polarity Function Enable Control
+ * | | |0 = Disabled.
+ * | | |1 = Enabled.
+ * |[18] |POLEN10 |TK10 Polarity Function Enable Control
+ * | | |0 = Disabled.
+ * | | |1 = Enabled.
+ * |[19] |POLEN11 |TK11 Polarity Function Enable Control
+ * | | |0 = Disabled.
+ * | | |1 = Enabled.
+ * |[20] |POLEN12 |TK12 Polarity Function Enable Control
+ * | | |0 = Disabled.
+ * | | |1 = Enabled.
+ * |[21] |POLEN13 |TK13 Polarity Function Enable Control
+ * | | |0 = Disabled.
+ * | | |1 = Enabled.
+ * |[22] |POLEN14 |TK14 Polarity Function Enable Control
+ * | | |0 = Disabled.
+ * | | |1 = Enabled.
+ * |[23] |POLEN15 |TK15 Polarity Function Enable Control
+ * | | |0 = Disabled.
+ * | | |1 = Enabled.
+ * |[24] |POLEN16 |TK16 Polarity Function Enable Control
+ * | | |0 = Disabled.
+ * | | |1 = Enabled.
+ * |[31] |SPOTINIT |Touch Key Sensing Initial Potential Control
+ * | | |0 = Key pad is connected to Gnd before sensing.
+ * | | |1 = Key pad is connected to AVCCH before sensing.
+ * @var TK_T::STATUS
+ * Offset: 0x28 Touch Key Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |BUSY |Touch Key Busy (Read Only)
+ * | | |0 = Key scan is complete or stopped.
+ * | | |1 = Key scan is proceeding.
+ * |[1] |SCIF |Touch Key Scan Complete Interrupt Flag
+ * | | |This bit will be cleared by writing a "1" to this bit.
+ * | | |0 = Key scan is proceeding and data is not ready for read.
+ * | | |1 = Key scan is complete and data is ready for read in TKDATx registers.
+ * | | |Note1: The Touch Key interrupt asserts if SCINTEN bit of TK_INTEN register is set.
+ * | | |Note2: The Touch Key interrupt also asserts if SCTHIEN bit of TK_INTEN register is set and any channel data value is greater/less than its threshold setting
+ * |[8] |TKIF0 |TK0 Interrupt Flag
+ * | | |This bit will be cleared by writing a "1" to this bit.
+ * | | |0 = No threshold control event with TK0.
+ * | | |1 = Threshold control event occurs with TK0.
+ * |[9] |TKIF1 |TK1 Interrupt Flag
+ * | | |This bit will be cleared by writing a "1" to this bit.
+ * | | |0 = No threshold control event with TK1.
+ * | | |1 = Threshold control event occurs with TK1.
+ * |[10] |TKIF2 |TK2 Interrupt Flag
+ * | | |This bit will be cleared by writing a "1" to this bit.
+ * | | |0 = No threshold control event with TK2.
+ * | | |1 = Threshold control event occurs with TK2.
+ * |[11] |TKIF3 |TK3 Interrupt Flag
+ * | | |This bit will be cleared by writing a "1" to this bit.
+ * | | |0 = No threshold control event with TK3.
+ * | | |1 = Threshold control event occurs with TK3.
+ * |[12] |TKIF4 |TK4 Interrupt Flag
+ * | | |This bit will be cleared by writing a "1" to this bit.
+ * | | |0 = No threshold control event with TK4.
+ * | | |1 = Threshold control event occurs with TK4.
+ * |[13] |TKIF5 |TK5 Interrupt Flag
+ * | | |This bit will be cleared by writing a "1" to this bit.
+ * | | |0 = No threshold control event with TK5.
+ * | | |1 = Threshold control event occurs with TK5.
+ * |[14] |TKIF6 |TK6 Interrupt Flag
+ * | | |This bit will be cleared by writing a "1" to this bit.
+ * | | |0 = No threshold control event with TK6.
+ * | | |1 = Threshold control event occurs with TK6.
+ * |[15] |TKIF7 |TK7 Interrupt Flag
+ * | | |This bit will be cleared by writing a "1" to this bit.
+ * | | |0 = No threshold control event with TK7.
+ * | | |1 = Threshold control event occurs with TK7.
+ * |[16] |TKIF8 |TK8 Interrupt Flag
+ * | | |This bit will be cleared by writing a "1" to this bit.
+ * | | |0 = No threshold control event with TK8.
+ * | | |1 = Threshold control event occurs with TK8.
+ * |[17] |TKIF9 |TK9 Interrupt Flag
+ * | | |This bit will be cleared by writing a "1" to this bit.
+ * | | |0 = No threshold control event with TK9.
+ * | | |1 = Threshold control event occurs with TK9.
+ * |[18] |TKIF10 |TK10 Interrupt Flag
+ * | | |This bit will be cleared by writing a "1" to this bit.
+ * | | |0 = No threshold control event with TK10.
+ * | | |1 = Threshold control event occurs with TK10.
+ * |[19] |TKIF11 |TK11 Interrupt Flag
+ * | | |This bit will be cleared by writing a "1" to this bit.
+ * | | |0 = No threshold control event with TK11.
+ * | | |1 = Threshold control event occurs with TK11.
+ * |[20] |TKIF12 |TK12 Interrupt Flag
+ * | | |This bit will be cleared by writing a "1" to this bit.
+ * | | |0 = No threshold control event with TK12.
+ * | | |1 = Threshold control event occurs with TK12.
+ * |[21] |TKIF13 |TK13 Interrupt Flag
+ * | | |This bit will be cleared by writing a "1" to this bit.
+ * | | |0 = No threshold control event with TK13.
+ * | | |1 = Threshold control event occurs with TK13.
+ * |[22] |TKIF14 |TK14 Interrupt Flag
+ * | | |This bit will be cleared by writing a "1" to this bit.
+ * | | |0 = No threshold control event with TK14.
+ * | | |1 = Threshold control event occurs with TK14.
+ * |[23] |TKIF15 |TK15 Interrupt Flag
+ * | | |This bit will be cleared by writing a "1" to this bit.
+ * | | |0 = No threshold control event with TK15.
+ * | | |1 = Threshold control event occurs with TK15.
+ * |[24] |TKIF16 |TK16 Interrupt Flag
+ * | | |This bit will be cleared by writing a "1" to this bit.
+ * | | |0 = No threshold control event with TK16.
+ * | | |1 = Threshold control event occurs with TK16.
+ * @var TK_T::DAT0
+ * Offset: 0x2C Touch Key Data Register 0
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:0] |TKDAT0 |TK0 Sensing Result Data (Read Only)
+ * | | |This data is invalid if TKSEN0 (TK_CTL[0]) is "0" or TKREN0 (TK_REFCTL[0]) is "1" except SCANALL (TK_REFCTL[23]) is "1".
+ * |[15:8] |TKDAT1 |TK1 Sensing Result Data (Read Only)
+ * | | |This data is invalid if TKSEN1 (TK_CTL[1]) is "0" or TKREN1 (TK_REFCTL[1]) is "1".
+ * |[23:16] |TKDAT2 |TK2 Sensing Result Data (Read Only)
+ * | | |This data is invalid if TKSEN2 (TK_CTL[2]) is "0" or TKREN2 (TK_REFCTL[2]) is "1".
+ * |[31:24] |TKDAT3 |TK3 Sensing Result Data (Read Only)
+ * | | |This data is invalid if TKSEN3 (TK_CTL[3]) is "0" or TKREN3 (TK_REFCTL[3]) is "1".
+ * @var TK_T::DAT1
+ * Offset: 0x30 Touch Key Data Register 1
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:0] |TKDAT4 |TK0 Sensing Result Data (Read Only)
+ * | | |This data is invalid if TKSEN4 (TK_CTL[4]) is "0" or TKREN4 (TK_REFCTL[4]) is "1".
+ * |[15:8] |TKDAT5 |TK5 Sensing Result Data (Read Only)
+ * | | |This data is invalid if TKSEN5 (TK_CTL[5]) is "0" or TKREN5 (TK_REFCTL[5]) is "1".
+ * |[23:16] |TKDAT6 |TK6 Sensing Result Data (Read Only)
+ * | | |This data is invalid if TKSEN6 (TK_CTL[6]) is "0" or TKREN6 (TK_REFCTL[6]) is "1".
+ * |[31:24] |TKDAT7 |TK7 Sensing Result Data (Read Only)
+ * | | |This data is invalid if TKSEN7 (TK_CTL[7]) is "0" or TKREN7 (TK_REFCTL[7]) is "1".
+ * @var TK_T::DAT2
+ * Offset: 0x34 Touch Key Data Register 2
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:0] |TKDAT8 |TK8 Sensing Result Data (Read Only)
+ * | | |This data is invalid if TKSEN8 (TK_CTL[8]) is "0" or TKREN8 (TK_REFCTL[8]) is "1".
+ * |[15:8] |TKDAT9 |TK9 Sensing Result Data (Read Only)
+ * | | |This data is invalid if TKSEN9 (TK_CTL[9]) is "0" or TKREN9 (TK_REFCTL[9]) is "1".
+ * |[23:16] |TKDAT10 |TK10 Sensing Result Data (Read Only)
+ * | | |This data is invalid if TKSEN10 (TK_CTL[10]) is "0" or TKREN10 (TK_REFCTL[10]) is "1".
+ * |[31:24] |TKDAT11 |TK11 Sensing Result Data (Read Only)
+ * | | |This data is invalid if TKSEN11 (TK_CTL[11]) is "0" or TKREN11 (TK_REFCTL[11]) is "1".
+ * @var TK_T::DAT3
+ * Offset: 0x38 Touch Key Data Register 3
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:0] |TKDAT12 |TK12 Sensing Result Data (Read Only)
+ * | | |This data is invalid if TKSEN12 (TK_CTL[12]) is "0" or TKREN12 (TK_REFCTL[12]) is "1".
+ * |[15:8] |TKDAT13 |TK13 Sensing Result Data (Read Only)
+ * | | |This data is invalid if TKSEN13 (TK_CTL[13]) is "0" or TKREN13 (TK_REFCTL[13]) is "1".
+ * |[23:16] |TKDAT14 |TK14 Sensing Result Data (Read Only)
+ * | | |This data is invalid if TKSEN14 (TK_CTL[14]) is "0" or TKREN14 (TK_REFCTL[14]) is "1".
+ * |[31:24] |TKDAT15 |TK15 Sensing Result Data (Read Only)
+ * | | |This data is invalid if TKSEN15 (TK_CTL[15]) is "0" or TKREN15 (TK_REFCTL[15]) is "1".
+ * @var TK_T::DAT4
+ * Offset: 0x3C Touch Key Data Register 4
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:0] |TKDAT16 |TK16 Sensing Result Data (Read Only)
+ * | | |This data is invalid if TKSEN16 (TK_CTL[16]) is "0" or TKREN16 (TK_REFCTL[16]) is "1".
+ * @var TK_T::INTEN
+ * Offset: 0x40 Touch Key Interrupt Enable Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |SCTHIEN |Touch Key Scan Complete With High/Low Threshold Control Interrupt Enable Bit
+ * | | |0 = Key scan complete with threshold control interrupt is disable.
+ * | | |1 = Key scan complete with threshold control interrupt is enable.
+ * |[1] |SCINTEN |Touch Key Scan Complete Interrupt Enable
+ * | | |Bit
+ * | | |0 = Key scan complete without threshold control interrupt is disable.
+ * | | |1 = Key scan complete without threshold control interrupt is enable.
+ * |[31] |THIMOD |Touch Key Threshold Interrupt Mode Select
+ * | | |0 = Edge trigger mode.
+ * | | |1 = Level trigger mode.
+ * @var TK_T::TH0_1
+ * Offset: 0x44 Touch Key TK0/TK1 Threshold Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:0] |LTH0 |Low Threshold Of TK0
+ * | | |Low level for TK0 threshold control.
+ * |[15:8] |HTH0 |High Threshold Of TK0
+ * | | |High level for TK0 threshold control.
+ * |[23:16] |LTH1 |Low Threshold Of TK1
+ * | | |Low level for TK1 threshold control.
+ * |[31:24] |HTH1 |High Threshold Of TK1
+ * | | |High level for TK1 threshold control.
+ * @var TK_T::TH2_3
+ * Offset: 0x48 Touch Key TK2/TK3 Threshold Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:0] |LTH2 |Low Threshold Of TK2
+ * | | |Low level for TK2 threshold control.
+ * |[15:8] |HTH2 |High Threshold Of TK2
+ * | | |High level for TK2 threshold control.
+ * |[23:16] |LTH3 |Low Threshold Of TK3
+ * | | |Low level for TK3 threshold control.
+ * |[31:24] |HTH3 |High Threshold Of TK3
+ * | | |High level for TK3 threshold control.
+ * @var TK_T::TH4_5
+ * Offset: 0x4C Touch Key TK4/TK5 Threshold Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:0] |LTH4 |Low Threshold Of TK4
+ * | | |Low level for TK4 threshold control.
+ * |[15:8] |HTH4 |High Threshold Of TK4
+ * | | |High level for TK4 threshold control.
+ * |[23:16] |LTH5 |Low Threshold Of TK5
+ * | | |Low level for TK5 threshold control.
+ * |[31:24] |HTH5 |High Threshold Of TK5
+ * | | |High level for TK5 threshold control.
+ * @var TK_T::TH6_7
+ * Offset: 0x50 Touch Key TK6/TK7 Threshold Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:0] |LTH6 |Low Threshold Of TK6
+ * | | |Low level for TK6 threshold control.
+ * |[15:8] |HTH6 |High Threshold Of TK6
+ * | | |High level for TK6 threshold control.
+ * |[23:16] |LTH7 |Low Threshold Of TK7
+ * | | |Low level for TK7 threshold control.
+ * |[31:24] |HTH7 |High Threshold Of TK7
+ * | | |High level for TK7 threshold control.
+ * @var TK_T::TH8_9
+ * Offset: 0x54 Touch Key TK8/TK9 Threshold Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:0] |LTH8 |Low Threshold Of TK8
+ * | | |Low level for TK8 threshold control.
+ * |[15:8] |HTH8 |High Threshold Of TK8
+ * | | |High level for TK8 threshold control.
+ * |[23:16] |LTH9 |Low Threshold Of TK9
+ * | | |Low level for TK9 threshold control.
+ * |[31:24] |HTH9 |High Threshold Of TK9
+ * | | |High level for TK9 threshold control.
+ * @var TK_T::TH10_11
+ * Offset: 0x58 Touch Key TK10/TK11 Threshold Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:0] |LTH10 |Low Threshold Of TK10
+ * | | |Low level for TK10 threshold control.
+ * |[15:8] |HTH10 |High Threshold Of TK10
+ * | | |High level for TK10 threshold control.
+ * |[23:16] |LTH11 |Low Threshold Of TK11
+ * | | |Low level for TK11 threshold control.
+ * |[31:24] |HTH11 |High Threshold Of TK11
+ * | | |High level for TK11 threshold control.
+ * @var TK_T::TH12_13
+ * Offset: 0x5C Touch Key TK12/TK13 Threshold Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:0] |LTH12 |Low Threshold Of TK12
+ * | | |Low level for TK12 threshold control.
+ * |[15:8] |HTH12 |High Threshold Of TK12
+ * | | |High level for TK12 threshold control.
+ * |[23:16] |LTH13 |Low Threshold Of TK13
+ * | | |Low level for TK13 threshold control.
+ * |[31:24] |HTH13 |High Threshold Of TK13
+ * | | |High level for TK13 threshold control.
+ * @var TK_T::TH14_15
+ * Offset: 0x60 Touch Key TK14/TK15 Threshold Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:0] |LTH14 |Low Threshold Of TK14
+ * | | |Low level for TK14 threshold control.
+ * |[15:8] |HTH14 |High Threshold Of TK14
+ * | | |High level for TK14 threshold control.
+ * |[23:16] |LTH15 |Low Threshold Of TK15
+ * | | |Low level for TK15 threshold control.
+ * |[31:24] |HTH15 |High Threshold Of TK15
+ * | | |High level for TK15 threshold control.
+ * @var TK_T::TH16
+ * Offset: 0x64 Touch Key TK16 Threshold Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:0] |LTH16 |Low Threshold Of TK16
+ * | | |Low level for TK16 threshold control.
+ * |[15:8] |HTH16 |High Threshold Of TK16
+ * | | |High level for TK16 threshold control.
+ */
+
+ __IO uint32_t CTL; /* Offset: 0x00 Touch Key Scan Control Register */
+ __IO uint32_t REFCTL; /* Offset: 0x04 Touch Key Reference Control Register */
+ __IO uint32_t CCBDAT0; /* Offset: 0x08 Touch Key Complement Capacitor Bank Data Register 0 */
+ __IO uint32_t CCBDAT1; /* Offset: 0x0C Touch Key Complement Capacitor Bank Data Register 1 */
+ __IO uint32_t CCBDAT2; /* Offset: 0x10 Touch Key Complement Capacitor Bank Data Register 2 */
+ __IO uint32_t CCBDAT3; /* Offset: 0x14 Touch Key Complement Capacitor Bank Data Register 3 */
+ __IO uint32_t CCBDAT4; /* Offset: 0x18 Touch Key Complement Capacitor Bank Data Register 4 */
+ __IO uint32_t IDLESEL; /* Offset: 0x1C Touch Key Idle State Control Register */
+ __IO uint32_t POLSEL; /* Offset: 0x20 Touch Key Polarity Select Register */
+ __IO uint32_t POLCTL; /* Offset: 0x24 Touch Key Polarity Control Register */
+ __IO uint32_t STATUS; /* Offset: 0x28 Touch Key Status Register */
+ __I uint32_t DAT0; /* Offset: 0x2C Touch Key Data Register 0 */
+ __I uint32_t DAT1; /* Offset: 0x30 Touch Key Data Register 1 */
+ __I uint32_t DAT2; /* Offset: 0x34 Touch Key Data Register 2 */
+ __I uint32_t DAT3; /* Offset: 0x38 Touch Key Data Register 3 */
+ __I uint32_t DAT4; /* Offset: 0x3C Touch Key Data Register 4 */
+ __IO uint32_t INTEN; /* Offset: 0x40 Touch Key Interrupt Enable Register */
+ __IO uint32_t TH0_1; /* Offset: 0x44 Touch Key TK0/TK1 Threshold Control Register */
+ __IO uint32_t TH2_3; /* Offset: 0x48 Touch Key TK2/TK3 Threshold Control Register */
+ __IO uint32_t TH4_5; /* Offset: 0x4C Touch Key TK4/TK5 Threshold Control Register */
+ __IO uint32_t TH6_7; /* Offset: 0x50 Touch Key TK6/TK7 Threshold Control Register */
+ __IO uint32_t TH8_9; /* Offset: 0x54 Touch Key TK8/TK9 Threshold Control Register */
+ __IO uint32_t TH10_11; /* Offset: 0x58 Touch Key TK10/TK11 Threshold Control Register */
+ __IO uint32_t TH12_13; /* Offset: 0x5C Touch Key TK12/TK13 Threshold Control Register */
+ __IO uint32_t TH14_15; /* Offset: 0x60 Touch Key TK14/TK15 Threshold Control Register */
+ __IO uint32_t TH16; /* Offset: 0x64 Touch Key TK16 Threshold Control Register */
+
+} TK_T;
+
+
+
+/**
+ @addtogroup TK_CONST TK Bit Field Definition
+ Constant Definitions for TK Controller
+@{ */
+
+
+#define TK_CTL_TKSEN0_Pos (0) /*!< TK_T::CTL: TKSEN0 Position */
+#define TK_CTL_TKSEN0_Msk (0x1ul << TK_CTL_TKSEN0_Pos) /*!< TK_T::CTL: TKSEN0 Mask */
+
+#define TK_CTL_TKSEN1_Pos (1) /*!< TK_T::CTL: TKSEN1 Position */
+#define TK_CTL_TKSEN1_Msk (0x1ul << TK_CTL_TKSEN1_Pos) /*!< TK_T::CTL: TKSEN1 Mask */
+
+#define TK_CTL_TKSEN2_Pos (2) /*!< TK_T::CTL: TKSEN2 Position */
+#define TK_CTL_TKSEN2_Msk (0x1ul << TK_CTL_TKSEN2_Pos) /*!< TK_T::CTL: TKSEN2 Mask */
+
+#define TK_CTL_TKSEN3_Pos (3) /*!< TK_T::CTL: TKSEN3 Position */
+#define TK_CTL_TKSEN3_Msk (0x1ul << TK_CTL_TKSEN3_Pos) /*!< TK_T::CTL: TKSEN3 Mask */
+
+#define TK_CTL_TKSEN4_Pos (4) /*!< TK_T::CTL: TKSEN4 Position */
+#define TK_CTL_TKSEN4_Msk (0x1ul << TK_CTL_TKSEN4_Pos) /*!< TK_T::CTL: TKSEN4 Mask */
+
+#define TK_CTL_TKSEN5_Pos (5) /*!< TK_T::CTL: TKSEN5 Position */
+#define TK_CTL_TKSEN5_Msk (0x1ul << TK_CTL_TKSEN5_Pos) /*!< TK_T::CTL: TKSEN5 Mask */
+
+#define TK_CTL_TKSEN6_Pos (6) /*!< TK_T::CTL: TKSEN6 Position */
+#define TK_CTL_TKSEN6_Msk (0x1ul << TK_CTL_TKSEN6_Pos) /*!< TK_T::CTL: TKSEN6 Mask */
+
+#define TK_CTL_TKSEN7_Pos (7) /*!< TK_T::CTL: TKSEN7 Position */
+#define TK_CTL_TKSEN7_Msk (0x1ul << TK_CTL_TKSEN7_Pos) /*!< TK_T::CTL: TKSEN7 Mask */
+
+#define TK_CTL_TKSEN8_Pos (8) /*!< TK_T::CTL: TKSEN8 Position */
+#define TK_CTL_TKSEN8_Msk (0x1ul << TK_CTL_TKSEN8_Pos) /*!< TK_T::CTL: TKSEN8 Mask */
+
+#define TK_CTL_TKSEN9_Pos (9) /*!< TK_T::CTL: TKSEN9 Position */
+#define TK_CTL_TKSEN9_Msk (0x1ul << TK_CTL_TKSEN9_Pos) /*!< TK_T::CTL: TKSEN9 Mask */
+
+#define TK_CTL_TKSEN10_Pos (10) /*!< TK_T::CTL: TKSEN10 Position */
+#define TK_CTL_TKSEN10_Msk (0x1ul << TK_CTL_TKSEN10_Pos) /*!< TK_T::CTL: TKSEN10 Mask */
+
+#define TK_CTL_TKSEN11_Pos (11) /*!< TK_T::CTL: TKSEN11 Position */
+#define TK_CTL_TKSEN11_Msk (0x1ul << TK_CTL_TKSEN11_Pos) /*!< TK_T::CTL: TKSEN11 Mask */
+
+#define TK_CTL_TKSEN12_Pos (12) /*!< TK_T::CTL: TKSEN12 Position */
+#define TK_CTL_TKSEN12_Msk (0x1ul << TK_CTL_TKSEN12_Pos) /*!< TK_T::CTL: TKSEN12 Mask */
+
+#define TK_CTL_TKSEN13_Pos (13) /*!< TK_T::CTL: TKSEN13 Position */
+#define TK_CTL_TKSEN13_Msk (0x1ul << TK_CTL_TKSEN13_Pos) /*!< TK_T::CTL: TKSEN13 Mask */
+
+#define TK_CTL_TKSEN14_Pos (14) /*!< TK_T::CTL: TKSEN14 Position */
+#define TK_CTL_TKSEN14_Msk (0x1ul << TK_CTL_TKSEN14_Pos) /*!< TK_T::CTL: TKSEN14 Mask */
+
+#define TK_CTL_TKSEN15_Pos (15) /*!< TK_T::CTL: TKSEN15 Position */
+#define TK_CTL_TKSEN15_Msk (0x1ul << TK_CTL_TKSEN15_Pos) /*!< TK_T::CTL: TKSEN15 Mask */
+
+#define TK_CTL_TKSEN16_Pos (16) /*!< TK_T::CTL: TKSEN16 Position */
+#define TK_CTL_TKSEN16_Msk (0x1ul << TK_CTL_TKSEN16_Pos) /*!< TK_T::CTL: TKSEN16 Mask */
+
+#define TK_CTL_AVCCHSEL_Pos (20) /*!< TK_T::CTL: AVCCHSEL Position */
+#define TK_CTL_AVCCHSEL_Msk (0x7ul << TK_CTL_AVCCHSEL_Pos) /*!< TK_T::CTL: AVCCHSEL Mask */
+
+#define TK_CTL_SCAN_Pos (24) /*!< TK_T::CTL: SCAN Position */
+#define TK_CTL_SCAN_Msk (0x1ul << TK_CTL_SCAN_Pos) /*!< TK_T::CTL: SCAN Mask */
+
+#define TK_CTL_TMRTRGEN_Pos (25) /*!< TK_T::CTL: TMRTRGEN Position */
+#define TK_CTL_TMRTRGEN_Msk (0x1ul << TK_CTL_TMRTRGEN_Pos) /*!< TK_T::CTL: TMRTRGEN Mask */
+
+#define TK_CTL_TKEN_Pos (31) /*!< TK_T::CTL: TKEN Position */
+#define TK_CTL_TKEN_Msk (0x1ul << TK_CTL_TKEN_Pos) /*!< TK_T::CTL: TKEN Mask */
+
+#define TK_REFCTL_TKREN0_Pos (0) /*!< TK_T::REFCTL: TKREN0 Position */
+#define TK_REFCTL_TKREN0_Msk (0x1ul << TK_REFCTL_TKREN0_Pos) /*!< TK_T::REFCTL: TKREN0 Mask */
+
+#define TK_REFCTL_TKREN1_Pos (1) /*!< TK_T::REFCTL: TKREN1 Position */
+#define TK_REFCTL_TKREN1_Msk (0x1ul << TK_REFCTL_TKREN1_Pos) /*!< TK_T::REFCTL: TKREN1 Mask */
+
+#define TK_REFCTL_TKREN2_Pos (2) /*!< TK_T::REFCTL: TKREN2 Position */
+#define TK_REFCTL_TKREN2_Msk (0x1ul << TK_REFCTL_TKREN2_Pos) /*!< TK_T::REFCTL: TKREN2 Mask */
+
+#define TK_REFCTL_TKREN3_Pos (3) /*!< TK_T::REFCTL: TKREN3 Position */
+#define TK_REFCTL_TKREN3_Msk (0x1ul << TK_REFCTL_TKREN3_Pos) /*!< TK_T::REFCTL: TKREN3 Mask */
+
+#define TK_REFCTL_TKREN4_Pos (4) /*!< TK_T::REFCTL: TKREN4 Position */
+#define TK_REFCTL_TKREN4_Msk (0x1ul << TK_REFCTL_TKREN4_Pos) /*!< TK_T::REFCTL: TKREN4 Mask */
+
+#define TK_REFCTL_TKREN5_Pos (5) /*!< TK_T::REFCTL: TKREN5 Position */
+#define TK_REFCTL_TKREN5_Msk (0x1ul << TK_REFCTL_TKREN5_Pos) /*!< TK_T::REFCTL: TKREN5 Mask */
+
+#define TK_REFCTL_TKREN6_Pos (6) /*!< TK_T::REFCTL: TKREN6 Position */
+#define TK_REFCTL_TKREN6_Msk (0x1ul << TK_REFCTL_TKREN6_Pos) /*!< TK_T::REFCTL: TKREN6 Mask */
+
+#define TK_REFCTL_TKREN7_Pos (7) /*!< TK_T::REFCTL: TKREN7 Position */
+#define TK_REFCTL_TKREN7_Msk (0x1ul << TK_REFCTL_TKREN7_Pos) /*!< TK_T::REFCTL: TKREN7 Mask */
+
+#define TK_REFCTL_TKREN8_Pos (8) /*!< TK_T::REFCTL: TKREN8 Position */
+#define TK_REFCTL_TKREN8_Msk (0x1ul << TK_REFCTL_TKREN8_Pos) /*!< TK_T::REFCTL: TKREN8 Mask */
+
+#define TK_REFCTL_TKREN9_Pos (9) /*!< TK_T::REFCTL: TKREN9 Position */
+#define TK_REFCTL_TKREN9_Msk (0x1ul << TK_REFCTL_TKREN9_Pos) /*!< TK_T::REFCTL: TKREN9 Mask */
+
+#define TK_REFCTL_TKREN10_Pos (10) /*!< TK_T::REFCTL: TKREN10 Position */
+#define TK_REFCTL_TKREN10_Msk (0x1ul << TK_REFCTL_TKREN10_Pos) /*!< TK_T::REFCTL: TKREN10 Mask */
+
+#define TK_REFCTL_TKREN11_Pos (11) /*!< TK_T::REFCTL: TKREN11 Position */
+#define TK_REFCTL_TKREN11_Msk (0x1ul << TK_REFCTL_TKREN11_Pos) /*!< TK_T::REFCTL: TKREN11 Mask */
+
+#define TK_REFCTL_TKREN12_Pos (12) /*!< TK_T::REFCTL: TKREN12 Position */
+#define TK_REFCTL_TKREN12_Msk (0x1ul << TK_REFCTL_TKREN12_Pos) /*!< TK_T::REFCTL: TKREN12 Mask */
+
+#define TK_REFCTL_TKREN13_Pos (13) /*!< TK_T::REFCTL: TKREN13 Position */
+#define TK_REFCTL_TKREN13_Msk (0x1ul << TK_REFCTL_TKREN13_Pos) /*!< TK_T::REFCTL: TKREN13 Mask */
+
+#define TK_REFCTL_TKREN14_Pos (14) /*!< TK_T::REFCTL: TKREN14 Position */
+#define TK_REFCTL_TKREN14_Msk (0x1ul << TK_REFCTL_TKREN14_Pos) /*!< TK_T::REFCTL: TKREN14 Mask */
+
+#define TK_REFCTL_TKREN15_Pos (15) /*!< TK_T::REFCTL: TKREN15 Position */
+#define TK_REFCTL_TKREN15_Msk (0x1ul << TK_REFCTL_TKREN15_Pos) /*!< TK_T::REFCTL: TKREN15 Mask */
+
+#define TK_REFCTL_TKREN16_Pos (16) /*!< TK_T::REFCTL: TKREN16 Position */
+#define TK_REFCTL_TKREN16_Msk (0x1ul << TK_REFCTL_TKREN16_Pos) /*!< TK_T::REFCTL: TKREN16 Mask */
+
+#define TK_REFCTL_SCANALL_Pos (23) /*!< TK_T::REFCTL: SCANALL Position */
+#define TK_REFCTL_SCANALL_Msk (0x1ul << TK_REFCTL_SCANALL_Pos) /*!< TK_T::REFCTL: SCANALL Mask */
+
+#define TK_REFCTL_SENTCTL_Pos (24) /*!< TK_T::REFCTL: SENTCTL Position */
+#define TK_REFCTL_SENTCTL_Msk (0x3ul << TK_REFCTL_SENTCTL_Pos) /*!< TK_T::REFCTL: SENTCTL Mask */
+
+#define TK_REFCTL_SENPTCTL_Pos (28) /*!< TK_T::REFCTL: SENPTCTL Position */
+#define TK_REFCTL_SENPTCTL_Msk (0x3ul << TK_REFCTL_SENPTCTL_Pos) /*!< TK_T::REFCTL: SENPTCTL Mask */
+
+#define TK_CCBDAT0_CCBDAT0_Pos (0) /*!< TK_T::CCBDAT0: CCBDAT0 Position */
+#define TK_CCBDAT0_CCBDAT0_Msk (0xfful << TK_CCBDAT0_CCBDAT0_Pos) /*!< TK_T::CCBDAT0: CCBDAT0 Mask */
+
+#define TK_CCBDAT0_CCBDAT1_Pos (8) /*!< TK_T::CCBDAT0: CCBDAT1 Position */
+#define TK_CCBDAT0_CCBDAT1_Msk (0xfful << TK_CCBDAT0_CCBDAT1_Pos) /*!< TK_T::CCBDAT0: CCBDAT1 Mask */
+
+#define TK_CCBDAT0_CCBDAT2_Pos (16) /*!< TK_T::CCBDAT0: CCBDAT2 Position */
+#define TK_CCBDAT0_CCBDAT2_Msk (0xfful << TK_CCBDAT0_CCBDAT2_Pos) /*!< TK_T::CCBDAT0: CCBDAT2 Mask */
+
+#define TK_CCBDAT0_CCBDAT3_Pos (24) /*!< TK_T::CCBDAT0: CCBDAT3 Position */
+#define TK_CCBDAT0_CCBDAT3_Msk (0xfful << TK_CCBDAT0_CCBDAT3_Pos) /*!< TK_T::CCBDAT0: CCBDAT3 Mask */
+
+#define TK_CCBDAT1_CCBDAT4_Pos (0) /*!< TK_T::CCBDAT1: CCBDAT4 Position */
+#define TK_CCBDAT1_CCBDAT4_Msk (0xfful << TK_CCBDAT1_CCBDAT4_Pos) /*!< TK_T::CCBDAT1: CCBDAT4 Mask */
+
+#define TK_CCBDAT1_CCBDAT5_Pos (8) /*!< TK_T::CCBDAT1: CCBDAT5 Position */
+#define TK_CCBDAT1_CCBDAT5_Msk (0xfful << TK_CCBDAT1_CCBDAT5_Pos) /*!< TK_T::CCBDAT1: CCBDAT5 Mask */
+
+#define TK_CCBDAT1_CCBDAT6_Pos (16) /*!< TK_T::CCBDAT1: CCBDAT6 Position */
+#define TK_CCBDAT1_CCBDAT6_Msk (0xfful << TK_CCBDAT1_CCBDAT6_Pos) /*!< TK_T::CCBDAT1: CCBDAT6 Mask */
+
+#define TK_CCBDAT1_CCBDAT7_Pos (24) /*!< TK_T::CCBDAT1: CCBDAT7 Position */
+#define TK_CCBDAT1_CCBDAT7_Msk (0xfful << TK_CCBDAT1_CCBDAT7_Pos) /*!< TK_T::CCBDAT1: CCBDAT7 Mask */
+
+#define TK_CCBDAT2_CCBDAT8_Pos (0) /*!< TK_T::CCBDAT2: CCBDAT8 Position */
+#define TK_CCBDAT2_CCBDAT8_Msk (0xfful << TK_CCBDAT2_CCBDAT8_Pos) /*!< TK_T::CCBDAT2: CCBDAT8 Mask */
+
+#define TK_CCBDAT2_CCBDAT9_Pos (8) /*!< TK_T::CCBDAT2: CCBDAT9 Position */
+#define TK_CCBDAT2_CCBDAT9_Msk (0xfful << TK_CCBDAT2_CCBDAT9_Pos) /*!< TK_T::CCBDAT2: CCBDAT9 Mask */
+
+#define TK_CCBDAT2_CCBDAT10_Pos (16) /*!< TK_T::CCBDAT2: CCBDAT10 Position */
+#define TK_CCBDAT2_CCBDAT10_Msk (0xfful << TK_CCBDAT2_CCBDAT10_Pos) /*!< TK_T::CCBDAT2: CCBDAT10 Mask */
+
+#define TK_CCBDAT2_CCBDAT11_Pos (24) /*!< TK_T::CCBDAT2: CCBDAT11 Position */
+#define TK_CCBDAT2_CCBDAT11_Msk (0xfful << TK_CCBDAT2_CCBDAT11_Pos) /*!< TK_T::CCBDAT2: CCBDAT11 Mask */
+
+#define TK_CCBDAT3_CCBDAT12_Pos (0) /*!< TK_T::CCBDAT3: CCBDAT12 Position */
+#define TK_CCBDAT3_CCBDAT12_Msk (0xfful << TK_CCBDAT3_CCBDAT12_Pos) /*!< TK_T::CCBDAT3: CCBDAT12 Mask */
+
+#define TK_CCBDAT3_CCBDAT13_Pos (8) /*!< TK_T::CCBDAT3: CCBDAT13 Position */
+#define TK_CCBDAT3_CCBDAT13_Msk (0xfful << TK_CCBDAT3_CCBDAT13_Pos) /*!< TK_T::CCBDAT3: CCBDAT13 Mask */
+
+#define TK_CCBDAT3_CCBDAT14_Pos (16) /*!< TK_T::CCBDAT3: CCBDAT14 Position */
+#define TK_CCBDAT3_CCBDAT14_Msk (0xfful << TK_CCBDAT3_CCBDAT14_Pos) /*!< TK_T::CCBDAT3: CCBDAT14 Mask */
+
+#define TK_CCBDAT3_CCBDAT15_Pos (24) /*!< TK_T::CCBDAT3: CCBDAT15 Position */
+#define TK_CCBDAT3_CCBDAT15_Msk (0xfful << TK_CCBDAT3_CCBDAT15_Pos) /*!< TK_T::CCBDAT3: CCBDAT15 Mask */
+
+#define TK_CCBDAT4_CCBDAT16_Pos (0) /*!< TK_T::CCBDAT4: CCBDAT16 Position */
+#define TK_CCBDAT4_CCBDAT16_Msk (0xfful << TK_CCBDAT4_CCBDAT16_Pos) /*!< TK_T::CCBDAT4: CCBDAT16 Mask */
+
+#define TK_CCBDAT4_REFCBDAT_Pos (24) /*!< TK_T::CCBDAT4: REFCBDAT Position */
+#define TK_CCBDAT4_REFCBDAT_Msk (0xfful << TK_CCBDAT4_REFCBDAT_Pos) /*!< TK_T::CCBDAT4: REFCBDAT Mask */
+
+#define TK_IDLESEL_IDLS_Pos (0) /*!< TK_T::IDLESEL: IDLS Position */
+#define TK_IDLESEL_IDLS_Msk (0xfffffffful << TK_IDLESEL_IDLS_Pos) /*!< TK_T::IDLESEL: IDLS Mask */
+
+#define TK_IDLESEL_IDLSn_Pos (0) /*!< TK_T::IDLESEL: IDLSn Position */
+#define TK_IDLESEL_IDLSn_Msk (0x3ul << TK_IDLESEL_IDLSn_Pos) /*!< TK_T::IDLESEL: IDLSn Mask */
+
+#define TK_POLSEL_POLSEL_Pos (0) /*!< TK_T::POLSEL: POLSEL Position */
+#define TK_POLSEL_POLSEL_Msk (0xfffffffful << TK_POLSEL_POLSEL_Pos) /*!< TK_T::POLSEL: POLSEL Mask */
+
+#define TK_POLSEL_POLSELn_Pos (0) /*!< TK_T::POLSEL: POLSELn Position */
+#define TK_POLSEL_POLSELn_Msk (0x3ul << TK_POLSEL_POLSELn_Pos) /*!< TK_T::POLSEL: POLSELn Mask */
+
+#define TK_POLCTL_IDLS16_Pos (0) /*!< TK_T::POLCTL: IDLS16 Position */
+#define TK_POLCTL_IDLS16_Msk (0x3ul << TK_POLCTL_IDLS16_Pos) /*!< TK_T::POLCTL: IDLS16 Mask */
+
+#define TK_POLCTL_POLSEL16_Pos (2) /*!< TK_T::POLCTL: POLSEL16 Position */
+#define TK_POLCTL_POLSEL16_Msk (0x3ul << TK_POLCTL_POLSEL16_Pos) /*!< TK_T::POLCTL: POLSEL16 Mask */
+
+#define TK_POLCTL_CBPOLSEL_Pos (4) /*!< TK_T::POLCTL: CBPOLSEL Position */
+#define TK_POLCTL_CBPOLSEL_Msk (0x3ul << TK_POLCTL_CBPOLSEL_Pos) /*!< TK_T::POLCTL: CBPOLSEL Mask */
+
+#define TK_POLCTL_POLEN0_Pos (8) /*!< TK_T::POLCTL: POLEN0 Position */
+#define TK_POLCTL_POLEN0_Msk (0x1ul << TK_POLCTL_POLEN0_Pos) /*!< TK_T::POLCTL: POLEN0 Mask */
+
+#define TK_POLCTL_POLEN1_Pos (9) /*!< TK_T::POLCTL: POLEN1 Position */
+#define TK_POLCTL_POLEN1_Msk (0x1ul << TK_POLCTL_POLEN1_Pos) /*!< TK_T::POLCTL: POLEN1 Mask */
+
+#define TK_POLCTL_POLEN2_Pos (10) /*!< TK_T::POLCTL: POLEN2 Position */
+#define TK_POLCTL_POLEN2_Msk (0x1ul << TK_POLCTL_POLEN2_Pos) /*!< TK_T::POLCTL: POLEN2 Mask */
+
+#define TK_POLCTL_POLEN3_Pos (11) /*!< TK_T::POLCTL: POLEN3 Position */
+#define TK_POLCTL_POLEN3_Msk (0x1ul << TK_POLCTL_POLEN3_Pos) /*!< TK_T::POLCTL: POLEN3 Mask */
+
+#define TK_POLCTL_POLEN4_Pos (12) /*!< TK_T::POLCTL: POLEN4 Position */
+#define TK_POLCTL_POLEN4_Msk (0x1ul << TK_POLCTL_POLEN4_Pos) /*!< TK_T::POLCTL: POLEN4 Mask */
+
+#define TK_POLCTL_POLEN5_Pos (13) /*!< TK_T::POLCTL: POLEN5 Position */
+#define TK_POLCTL_POLEN5_Msk (0x1ul << TK_POLCTL_POLEN5_Pos) /*!< TK_T::POLCTL: POLEN5 Mask */
+
+#define TK_POLCTL_POLEN6_Pos (14) /*!< TK_T::POLCTL: POLEN6 Position */
+#define TK_POLCTL_POLEN6_Msk (0x1ul << TK_POLCTL_POLEN6_Pos) /*!< TK_T::POLCTL: POLEN6 Mask */
+
+#define TK_POLCTL_POLEN7_Pos (15) /*!< TK_T::POLCTL: POLEN7 Position */
+#define TK_POLCTL_POLEN7_Msk (0x1ul << TK_POLCTL_POLEN7_Pos) /*!< TK_T::POLCTL: POLEN7 Mask */
+
+#define TK_POLCTL_POLEN8_Pos (16) /*!< TK_T::POLCTL: POLEN8 Position */
+#define TK_POLCTL_POLEN8_Msk (0x1ul << TK_POLCTL_POLEN8_Pos) /*!< TK_T::POLCTL: POLEN8 Mask */
+
+#define TK_POLCTL_POLEN9_Pos (17) /*!< TK_T::POLCTL: POLEN9 Position */
+#define TK_POLCTL_POLEN9_Msk (0x1ul << TK_POLCTL_POLEN9_Pos) /*!< TK_T::POLCTL: POLEN9 Mask */
+
+#define TK_POLCTL_POLEN10_Pos (18) /*!< TK_T::POLCTL: POLEN10 Position */
+#define TK_POLCTL_POLEN10_Msk (0x1ul << TK_POLCTL_POLEN10_Pos) /*!< TK_T::POLCTL: POLEN10 Mask */
+
+#define TK_POLCTL_POLEN11_Pos (19) /*!< TK_T::POLCTL: POLEN11 Position */
+#define TK_POLCTL_POLEN11_Msk (0x1ul << TK_POLCTL_POLEN11_Pos) /*!< TK_T::POLCTL: POLEN11 Mask */
+
+#define TK_POLCTL_POLEN12_Pos (20) /*!< TK_T::POLCTL: POLEN12 Position */
+#define TK_POLCTL_POLEN12_Msk (0x1ul << TK_POLCTL_POLEN12_Pos) /*!< TK_T::POLCTL: POLEN12 Mask */
+
+#define TK_POLCTL_POLEN13_Pos (21) /*!< TK_T::POLCTL: POLEN13 Position */
+#define TK_POLCTL_POLEN13_Msk (0x1ul << TK_POLCTL_POLEN13_Pos) /*!< TK_T::POLCTL: POLEN13 Mask */
+
+#define TK_POLCTL_POLEN14_Pos (22) /*!< TK_T::POLCTL: POLEN14 Position */
+#define TK_POLCTL_POLEN14_Msk (0x1ul << TK_POLCTL_POLEN14_Pos) /*!< TK_T::POLCTL: POLEN14 Mask */
+
+#define TK_POLCTL_POLEN15_Pos (23) /*!< TK_T::POLCTL: POLEN15 Position */
+#define TK_POLCTL_POLEN15_Msk (0x1ul << TK_POLCTL_POLEN15_Pos) /*!< TK_T::POLCTL: POLEN15 Mask */
+
+#define TK_POLCTL_POLEN16_Pos (24) /*!< TK_T::POLCTL: POLEN16 Position */
+#define TK_POLCTL_POLEN16_Msk (0x1ul << TK_POLCTL_POLEN16_Pos) /*!< TK_T::POLCTL: POLEN16 Mask */
+
+#define TK_POLCTL_SPOTINIT_Pos (31) /*!< TK_T::POLCTL: SPOTINIT Position */
+#define TK_POLCTL_SPOTINIT_Msk (0x1ul << TK_POLCTL_SPOTINIT_Pos) /*!< TK_T::POLCTL: SPOTINIT Mask */
+
+#define TK_STATUS_BUSY_Pos (0) /*!< TK_T::STATUS: BUSY Position */
+#define TK_STATUS_BUSY_Msk (0x1ul << TK_STATUS_BUSY_Pos) /*!< TK_T::STATUS: BUSY Mask */
+
+#define TK_STATUS_SCIF_Pos (1) /*!< TK_T::STATUS: SCIF Position */
+#define TK_STATUS_SCIF_Msk (0x1ul << TK_STATUS_SCIF_Pos) /*!< TK_T::STATUS: SCIF Mask */
+
+#define TK_STATUS_TKIF0_Pos (8) /*!< TK_T::STATUS: TKIF0 Position */
+#define TK_STATUS_TKIF0_Msk (0x1ul << TK_STATUS_TKIF0_Pos) /*!< TK_T::STATUS: TKIF0 Mask */
+
+#define TK_STATUS_TKIF1_Pos (9) /*!< TK_T::STATUS: TKIF1 Position */
+#define TK_STATUS_TKIF1_Msk (0x1ul << TK_STATUS_TKIF1_Pos) /*!< TK_T::STATUS: TKIF1 Mask */
+
+#define TK_STATUS_TKIF2_Pos (10) /*!< TK_T::STATUS: TKIF2 Position */
+#define TK_STATUS_TKIF2_Msk (0x1ul << TK_STATUS_TKIF2_Pos) /*!< TK_T::STATUS: TKIF2 Mask */
+
+#define TK_STATUS_TKIF3_Pos (11) /*!< TK_T::STATUS: TKIF3 Position */
+#define TK_STATUS_TKIF3_Msk (0x1ul << TK_STATUS_TKIF3_Pos) /*!< TK_T::STATUS: TKIF3 Mask */
+
+#define TK_STATUS_TKIF4_Pos (12) /*!< TK_T::STATUS: TKIF4 Position */
+#define TK_STATUS_TKIF4_Msk (0x1ul << TK_STATUS_TKIF4_Pos) /*!< TK_T::STATUS: TKIF4 Mask */
+
+#define TK_STATUS_TKIF5_Pos (13) /*!< TK_T::STATUS: TKIF5 Position */
+#define TK_STATUS_TKIF5_Msk (0x1ul << TK_STATUS_TKIF5_Pos) /*!< TK_T::STATUS: TKIF5 Mask */
+
+#define TK_STATUS_TKIF6_Pos (14) /*!< TK_T::STATUS: TKIF6 Position */
+#define TK_STATUS_TKIF6_Msk (0x1ul << TK_STATUS_TKIF6_Pos) /*!< TK_T::STATUS: TKIF6 Mask */
+
+#define TK_STATUS_TKIF7_Pos (15) /*!< TK_T::STATUS: TKIF7 Position */
+#define TK_STATUS_TKIF7_Msk (0x1ul << TK_STATUS_TKIF7_Pos) /*!< TK_T::STATUS: TKIF7 Mask */
+
+#define TK_STATUS_TKIF8_Pos (16) /*!< TK_T::STATUS: TKIF8 Position */
+#define TK_STATUS_TKIF8_Msk (0x1ul << TK_STATUS_TKIF8_Pos) /*!< TK_T::STATUS: TKIF8 Mask */
+
+#define TK_STATUS_TKIF9_Pos (17) /*!< TK_T::STATUS: TKIF9 Position */
+#define TK_STATUS_TKIF9_Msk (0x1ul << TK_STATUS_TKIF9_Pos) /*!< TK_T::STATUS: TKIF9 Mask */
+
+#define TK_STATUS_TKIF10_Pos (18) /*!< TK_T::STATUS: TKIF10 Position */
+#define TK_STATUS_TKIF10_Msk (0x1ul << TK_STATUS_TKIF10_Pos) /*!< TK_T::STATUS: TKIF10 Mask */
+
+#define TK_STATUS_TKIF11_Pos (19) /*!< TK_T::STATUS: TKIF11 Position */
+#define TK_STATUS_TKIF11_Msk (0x1ul << TK_STATUS_TKIF11_Pos) /*!< TK_T::STATUS: TKIF11 Mask */
+
+#define TK_STATUS_TKIF12_Pos (20) /*!< TK_T::STATUS: TKIF12 Position */
+#define TK_STATUS_TKIF12_Msk (0x1ul << TK_STATUS_TKIF12_Pos) /*!< TK_T::STATUS: TKIF12 Mask */
+
+#define TK_STATUS_TKIF13_Pos (21) /*!< TK_T::STATUS: TKIF13 Position */
+#define TK_STATUS_TKIF13_Msk (0x1ul << TK_STATUS_TKIF13_Pos) /*!< TK_T::STATUS: TKIF13 Mask */
+
+#define TK_STATUS_TKIF14_Pos (22) /*!< TK_T::STATUS: TKIF14 Position */
+#define TK_STATUS_TKIF14_Msk (0x1ul << TK_STATUS_TKIF14_Pos) /*!< TK_T::STATUS: TKIF14 Mask */
+
+#define TK_STATUS_TKIF15_Pos (23) /*!< TK_T::STATUS: TKIF15 Position */
+#define TK_STATUS_TKIF15_Msk (0x1ul << TK_STATUS_TKIF15_Pos) /*!< TK_T::STATUS: TKIF15 Mask */
+
+#define TK_STATUS_TKIF16_Pos (24) /*!< TK_T::STATUS: TKIF16 Position */
+#define TK_STATUS_TKIF16_Msk (0x1ul << TK_STATUS_TKIF16_Pos) /*!< TK_T::STATUS: TKIF16 Mask */
+
+#define TK_DAT0_TKDAT0_Pos (0) /*!< TK_T::DAT0: TKDAT0 Position */
+#define TK_DAT0_TKDAT0_Msk (0xfful << TK_DAT0_TKDAT0_Pos) /*!< TK_T::DAT0: TKDAT0 Mask */
+
+#define TK_DAT0_TKDAT1_Pos (8) /*!< TK_T::DAT0: TKDAT1 Position */
+#define TK_DAT0_TKDAT1_Msk (0xfful << TK_DAT0_TKDAT1_Pos) /*!< TK_T::DAT0: TKDAT1 Mask */
+
+#define TK_DAT0_TKDAT2_Pos (16) /*!< TK_T::DAT0: TKDAT2 Position */
+#define TK_DAT0_TKDAT2_Msk (0xfful << TK_DAT0_TKDAT2_Pos) /*!< TK_T::DAT0: TKDAT2 Mask */
+
+#define TK_DAT0_TKDAT3_Pos (24) /*!< TK_T::DAT0: TKDAT3 Position */
+#define TK_DAT0_TKDAT3_Msk (0xfful << TK_DAT0_TKDAT3_Pos) /*!< TK_T::DAT0: TKDAT3 Mask */
+
+#define TK_DAT1_TKDAT4_Pos (0) /*!< TK_T::DAT1: TKDAT4 Position */
+#define TK_DAT1_TKDAT4_Msk (0xfful << TK_DAT1_TKDAT4_Pos) /*!< TK_T::DAT1: TKDAT4 Mask */
+
+#define TK_DAT1_TKDAT5_Pos (8) /*!< TK_T::DAT1: TKDAT5 Position */
+#define TK_DAT1_TKDAT5_Msk (0xfful << TK_DAT1_TKDAT5_Pos) /*!< TK_T::DAT1: TKDAT5 Mask */
+
+#define TK_DAT1_TKDAT6_Pos (16) /*!< TK_T::DAT1: TKDAT6 Position */
+#define TK_DAT1_TKDAT6_Msk (0xfful << TK_DAT1_TKDAT6_Pos) /*!< TK_T::DAT1: TKDAT6 Mask */
+
+#define TK_DAT1_TKDAT7_Pos (24) /*!< TK_T::DAT1: TKDAT7 Position */
+#define TK_DAT1_TKDAT7_Msk (0xfful << TK_DAT1_TKDAT7_Pos) /*!< TK_T::DAT1: TKDAT7 Mask */
+
+#define TK_DAT2_TKDAT8_Pos (0) /*!< TK_T::DAT2: TKDAT8 Position */
+#define TK_DAT2_TKDAT8_Msk (0xfful << TK_DAT2_TKDAT8_Pos) /*!< TK_T::DAT2: TKDAT8 Mask */
+
+#define TK_DAT2_TKDAT9_Pos (8) /*!< TK_T::DAT2: TKDAT9 Position */
+#define TK_DAT2_TKDAT9_Msk (0xfful << TK_DAT2_TKDAT9_Pos) /*!< TK_T::DAT2: TKDAT9 Mask */
+
+#define TK_DAT2_TKDAT10_Pos (16) /*!< TK_T::DAT2: TKDAT10 Position */
+#define TK_DAT2_TKDAT10_Msk (0xfful << TK_DAT2_TKDAT10_Pos) /*!< TK_T::DAT2: TKDAT10 Mask */
+
+#define TK_DAT2_TKDAT11_Pos (24) /*!< TK_T::DAT2: TKDAT11 Position */
+#define TK_DAT2_TKDAT11_Msk (0xfful << TK_DAT2_TKDAT11_Pos) /*!< TK_T::DAT2: TKDAT11 Mask */
+
+#define TK_DAT3_TKDAT12_Pos (0) /*!< TK_T::DAT3: TKDAT12 Position */
+#define TK_DAT3_TKDAT12_Msk (0xfful << TK_DAT3_TKDAT12_Pos) /*!< TK_T::DAT3: TKDAT12 Mask */
+
+#define TK_DAT3_TKDAT13_Pos (8) /*!< TK_T::DAT3: TKDAT13 Position */
+#define TK_DAT3_TKDAT13_Msk (0xfful << TK_DAT3_TKDAT13_Pos) /*!< TK_T::DAT3: TKDAT13 Mask */
+
+#define TK_DAT3_TKDAT14_Pos (16) /*!< TK_T::DAT3: TKDAT14 Position */
+#define TK_DAT3_TKDAT14_Msk (0xfful << TK_DAT3_TKDAT14_Pos) /*!< TK_T::DAT3: TKDAT14 Mask */
+
+#define TK_DAT3_TKDAT15_Pos (24) /*!< TK_T::DAT3: TKDAT15 Position */
+#define TK_DAT3_TKDAT15_Msk (0xfful << TK_DAT3_TKDAT15_Pos) /*!< TK_T::DAT3: TKDAT15 Mask */
+
+#define TK_DAT4_TKDAT16_Pos (0) /*!< TK_T::DAT4: TKDAT16 Position */
+#define TK_DAT4_TKDAT16_Msk (0xfful << TK_DAT4_TKDAT16_Pos) /*!< TK_T::DAT4: TKDAT16 Mask */
+
+#define TK_INTEN_SCTHIEN_Pos (0) /*!< TK_T::INTEN: SCTHIEN Position */
+#define TK_INTEN_SCTHIEN_Msk (0x1ul << TK_INTEN_SCTHIEN_Pos) /*!< TK_T::INTEN: SCTHIEN Mask */
+
+#define TK_INTEN_SCINTEN_Pos (1) /*!< TK_T::INTEN: SCINTEN Position */
+#define TK_INTEN_SCINTEN_Msk (0x1ul << TK_INTEN_SCINTEN_Pos) /*!< TK_T::INTEN: SCINTEN Mask */
+
+#define TK_INTEN_THIMOD_Pos (31) /*!< TK_T::INTEN: THIMOD Position */
+#define TK_INTEN_THIMOD_Msk (0x1ul << TK_INTEN_THIMOD_Pos) /*!< TK_T::INTEN: THIMOD Mask */
+
+#define TK_TH0_1_LTH0_Pos (0) /*!< TK_T::TH0_1: LTH0 Position */
+#define TK_TH0_1_LTH0_Msk (0xfful << TK_TH0_1_LTH0_Pos) /*!< TK_T::TH0_1: LTH0 Mask */
+
+#define TK_TH0_1_HTH0_Pos (8) /*!< TK_T::TH0_1: HTH0 Position */
+#define TK_TH0_1_HTH0_Msk (0xfful << TK_TH0_1_HTH0_Pos) /*!< TK_T::TH0_1: HTH0 Mask */
+
+#define TK_TH0_1_LTH1_Pos (16) /*!< TK_T::TH0_1: LTH1 Position */
+#define TK_TH0_1_LTH1_Msk (0xfful << TK_TH0_1_LTH1_Pos) /*!< TK_T::TH0_1: LTH1 Mask */
+
+#define TK_TH0_1_HTH1_Pos (24) /*!< TK_T::TH0_1: HTH1 Position */
+#define TK_TH0_1_HTH1_Msk (0xfful << TK_TH0_1_HTH1_Pos) /*!< TK_T::TH0_1: HTH1 Mask */
+
+#define TK_TH2_3_LTH2_Pos (0) /*!< TK_T::TH2_3: LTH2 Position */
+#define TK_TH2_3_LTH2_Msk (0xfful << TK_TH2_3_LTH2_Pos) /*!< TK_T::TH2_3: LTH2 Mask */
+
+#define TK_TH2_3_HTH2_Pos (8) /*!< TK_T::TH2_3: HTH2 Position */
+#define TK_TH2_3_HTH2_Msk (0xfful << TK_TH2_3_HTH2_Pos) /*!< TK_T::TH2_3: HTH2 Mask */
+
+#define TK_TH2_3_LTH3_Pos (16) /*!< TK_T::TH2_3: LTH3 Position */
+#define TK_TH2_3_LTH3_Msk (0xfful << TK_TH2_3_LTH3_Pos) /*!< TK_T::TH2_3: LTH3 Mask */
+
+#define TK_TH2_3_HTH3_Pos (24) /*!< TK_T::TH2_3: HTH3 Position */
+#define TK_TH2_3_HTH3_Msk (0xfful << TK_TH2_3_HTH3_Pos) /*!< TK_T::TH2_3: HTH3 Mask */
+
+#define TK_TH4_5_LTH4_Pos (0) /*!< TK_T::TH4_5: LTH4 Position */
+#define TK_TH4_5_LTH4_Msk (0xfful << TK_TH4_5_LTH4_Pos) /*!< TK_T::TH4_5: LTH4 Mask */
+
+#define TK_TH4_5_HTH4_Pos (8) /*!< TK_T::TH4_5: HTH4 Position */
+#define TK_TH4_5_HTH4_Msk (0xfful << TK_TH4_5_HTH4_Pos) /*!< TK_T::TH4_5: HTH4 Mask */
+
+#define TK_TH4_5_LTH5_Pos (16) /*!< TK_T::TH4_5: LTH5 Position */
+#define TK_TH4_5_LTH5_Msk (0xfful << TK_TH4_5_LTH5_Pos) /*!< TK_T::TH4_5: LTH5 Mask */
+
+#define TK_TH4_5_HTH5_Pos (24) /*!< TK_T::TH4_5: HTH5 Position */
+#define TK_TH4_5_HTH5_Msk (0xfful << TK_TH4_5_HTH5_Pos) /*!< TK_T::TH4_5: HTH5 Mask */
+
+#define TK_TH6_7_LTH6_Pos (0) /*!< TK_T::TH6_7: LTH6 Position */
+#define TK_TH6_7_LTH6_Msk (0xfful << TK_TH6_7_LTH6_Pos) /*!< TK_T::TH6_7: LTH6 Mask */
+
+#define TK_TH6_7_HTH6_Pos (8) /*!< TK_T::TH6_7: HTH6 Position */
+#define TK_TH6_7_HTH6_Msk (0xfful << TK_TH6_7_HTH6_Pos) /*!< TK_T::TH6_7: HTH6 Mask */
+
+#define TK_TH6_7_LTH7_Pos (16) /*!< TK_T::TH6_7: LTH7 Position */
+#define TK_TH6_7_LTH7_Msk (0xfful << TK_TH6_7_LTH7_Pos) /*!< TK_T::TH6_7: LTH7 Mask */
+
+#define TK_TH6_7_HTH7_Pos (24) /*!< TK_T::TH6_7: HTH7 Position */
+#define TK_TH6_7_HTH7_Msk (0xfful << TK_TH6_7_HTH7_Pos) /*!< TK_T::TH6_7: HTH7 Mask */
+
+#define TK_TH8_9_LTH8_Pos (0) /*!< TK_T::TH8_9: LTH8 Position */
+#define TK_TH8_9_LTH8_Msk (0xfful << TK_TH8_9_LTH8_Pos) /*!< TK_T::TH8_9: LTH8 Mask */
+
+#define TK_TH8_9_HTH8_Pos (8) /*!< TK_T::TH8_9: HTH8 Position */
+#define TK_TH8_9_HTH8_Msk (0xfful << TK_TH8_9_HTH8_Pos) /*!< TK_T::TH8_9: HTH8 Mask */
+
+#define TK_TH8_9_LTH9_Pos (16) /*!< TK_T::TH8_9: LTH9 Position */
+#define TK_TH8_9_LTH9_Msk (0xfful << TK_TH8_9_LTH9_Pos) /*!< TK_T::TH8_9: LTH9 Mask */
+
+#define TK_TH8_9_HTH9_Pos (24) /*!< TK_T::TH8_9: HTH9 Position */
+#define TK_TH8_9_HTH9_Msk (0xfful << TK_TH8_9_HTH9_Pos) /*!< TK_T::TH8_9: HTH9 Mask */
+
+#define TK_TH10_11_LTH10_Pos (0) /*!< TK_T::TH10_11: LTH10 Position */
+#define TK_TH10_11_LTH10_Msk (0xfful << TK_TH10_11_LTH10_Pos) /*!< TK_T::TH10_11: LTH10 Mask */
+
+#define TK_TH10_11_HTH10_Pos (8) /*!< TK_T::TH10_11: HTH10 Position */
+#define TK_TH10_11_HTH10_Msk (0xfful << TK_TH10_11_HTH10_Pos) /*!< TK_T::TH10_11: HTH10 Mask */
+
+#define TK_TH10_11_LTH11_Pos (16) /*!< TK_T::TH10_11: LTH11 Position */
+#define TK_TH10_11_LTH11_Msk (0xfful << TK_TH10_11_LTH11_Pos) /*!< TK_T::TH10_11: LTH11 Mask */
+
+#define TK_TH10_11_HTH11_Pos (24) /*!< TK_T::TH10_11: HTH11 Position */
+#define TK_TH10_11_HTH11_Msk (0xfful << TK_TH10_11_HTH11_Pos) /*!< TK_T::TH10_11: HTH11 Mask */
+
+#define TK_TH12_13_LTH12_Pos (0) /*!< TK_T::TH12_13: LTH12 Position */
+#define TK_TH12_13_LTH12_Msk (0xfful << TK_TH12_13_LTH12_Pos) /*!< TK_T::TH12_13: LTH12 Mask */
+
+#define TK_TH12_13_HTH12_Pos (8) /*!< TK_T::TH12_13: HTH12 Position */
+#define TK_TH12_13_HTH12_Msk (0xfful << TK_TH12_13_HTH12_Pos) /*!< TK_T::TH12_13: HTH12 Mask */
+
+#define TK_TH12_13_LTH13_Pos (16) /*!< TK_T::TH12_13: LTH13 Position */
+#define TK_TH12_13_LTH13_Msk (0xfful << TK_TH12_13_LTH13_Pos) /*!< TK_T::TH12_13: LTH13 Mask */
+
+#define TK_TH12_13_HTH13_Pos (24) /*!< TK_T::TH12_13: HTH13 Position */
+#define TK_TH12_13_HTH13_Msk (0xfful << TK_TH12_13_HTH13_Pos) /*!< TK_T::TH12_13: HTH13 Mask */
+
+#define TK_TH14_15_LTH14_Pos (0) /*!< TK_T::TH14_15: LTH14 Position */
+#define TK_TH14_15_LTH14_Msk (0xfful << TK_TH14_15_LTH14_Pos) /*!< TK_T::TH14_15: LTH14 Mask */
+
+#define TK_TH14_15_HTH14_Pos (8) /*!< TK_T::TH14_15: HTH14 Position */
+#define TK_TH14_15_HTH14_Msk (0xfful << TK_TH14_15_HTH14_Pos) /*!< TK_T::TH14_15: HTH14 Mask */
+
+#define TK_TH14_15_LTH15_Pos (16) /*!< TK_T::TH14_15: LTH15 Position */
+#define TK_TH14_15_LTH15_Msk (0xfful << TK_TH14_15_LTH15_Pos) /*!< TK_T::TH14_15: LTH15 Mask */
+
+#define TK_TH14_15_HTH15_Pos (24) /*!< TK_T::TH14_15: HTH15 Position */
+#define TK_TH14_15_HTH15_Msk (0xfful << TK_TH14_15_HTH15_Pos) /*!< TK_T::TH14_15: HTH15 Mask */
+
+#define TK_TH16_LTH16_Pos (0) /*!< TK_T::TH16: LTH16 Position */
+#define TK_TH16_LTH16_Msk (0xfful << TK_TH16_LTH16_Pos) /*!< TK_T::TH16: LTH16 Mask */
+
+#define TK_TH16_HTH16_Pos (8) /*!< TK_T::TH16: HTH16 Position */
+#define TK_TH16_HTH16_Msk (0xfful << TK_TH16_HTH16_Pos) /*!< TK_T::TH16: HTH16 Mask */
+
+/**@}*/ /* TK_CONST */
+/**@}*/ /* end of TK register group */
+
+
+/*---------------------- Timer Controller -------------------------*/
+/**
+ @addtogroup TMR Timer Controller(TMR)
+ Memory Mapped Structure for TMR Controller
+@{ */
+
+
+typedef struct
+{
+
+
+
+
+/**
+ * @var TIMER_T::CTL
+ * Offset: 0x00 Timer Control and Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:0] |PSC |Prescale Counter
+ * | | |Timer input clock or event source is divided by (PSC+1) before it is fed to the timer up counter.
+ * | | |If this field is 0 (PSC = 0), then there is no scaling.
+ * |[17] |WKTKEN |Wake-Up Touch-Key Scan Enable Bit
+ * | | |If this bit is set to 1, timer time-out interrupt in Power-down mode can be triggered Touch-Key start scan.
+ * | | |0 = Timer time-out interrupt signal trigger Touch-Key start scan Disabled.
+ * | | |1 = Timer time-out interrupt signal trigger Touch-Key start scan Enabled.
+ * | | |Note: This bit is only available in TIMER0_CTL.
+ * |[18] |TRGSSEL |Trigger Source Select Bit
+ * | | |This bit is used to select trigger source is form Timer time-out interrupt signal or capture interrupt signal.
+ * | | |0 = Timer time-out interrupt signal is used to trigger PWM, EADC and DAC.
+ * | | |1 = Capture interrupt signal is used to trigger PWM, EADC and DAC.
+ * |[19] |TRGPWM |Trigger PWM Enable Bit
+ * | | |If this bit is set to 1, timer time-out interrupt or capture interrupt can be triggered PWM.
+ * | | |0 = Timer interrupt trigger PWM Disabled.
+ * | | |1 = Timer interrupt trigger PWM Enabled.
+ * | | |Note: If TRGSSEL (TIMERx_CTL[18]) = 0, time-out interrupt signal will trigger PWM.
+ * | | |If TRGSSEL (TIMERx_CTL[18]) = 1, capture interrupt signal will trigger PWM.
+ * |[20] |TRGDAC |Trigger DAC Enable Bit
+ * | | |If this bit is set to 1, timer time-out interrupt or capture interrupt can be triggered DAC.
+ * | | |0 = Timer interrupt trigger DAC Disabled.
+ * | | |1 = Timer interrupt trigger DAC Enabled.
+ * | | |Note: If TRGSSEL (TIMERx_CTL[18]) = 0, time-out interrupt signal will trigger DAC.
+ * | | |If TRGSSEL (TIMERx_CTL[18]) = 1, capture interrupt signal will trigger DAC.
+ * |[21] |TRGEADC |Trigger EADC Enable Bit
+ * | | |If this bit is set to 1, timer time-out interrupt or capture interrupt can be triggered EADC.
+ * | | |0 = Timer interrupt trigger EADC Disabled.
+ * | | |1 = Timer interrupt trigger EADC Enabled.
+ * | | |Note: If TRGSSEL (TIMERx_CTL[18]) = 0, time-out interrupt signal will trigger EADC.
+ * | | |If TRGSSEL (TIMERx_CTL[18]) = 1, capture interrupt signal will trigger EADC.
+ * |[22] |TGLPINSEL |Toggle-Output Pin Select
+ * | | |0 = Toggle mode output to Tx_OUT (Timer Event Counter Pin).
+ * | | |1 = Toggle mode output to Tx_EXT(Timer External Capture Pin).
+ * |[23] |WKEN |Wake-Up Function Enable Bit
+ * | | |If this bit is set to 1, while timer interrupt flag TIF (TIMERx_INTSTS[0]) is 1 and INTEN (TIMERx_CTL[29]) is enabled, the timer interrupt signal will generate a wake-up trigger event to CPU.
+ * | | |0 = Wake-up function Disabled if timer interrupt signal generated.
+ * | | |1 = Wake-up function Enabled if timer interrupt signal generated.
+ * |[24] |EXTCNTEN |Event Counter Mode Enable Bit
+ * | | |This bit is for external counting pin function enabled.
+ * | | |0 = Event counter mode Disabled.
+ * | | |1 = Event counter mode Enabled.
+ * | | |Note: When timer is used as an event counter, this bit should be set to 1 and select HCLK as timer clock source.
+ * |[25] |ACTSTS |Timer Active Status Bit (Read Only)
+ * | | |This bit indicates the 24-bit up counter status.
+ * | | |0 = 24-bit up counter is not active.
+ * | | |1 = 24-bit up counter is active.
+ * |[26] |RSTCNT |Timer Counter Reset Bit
+ * | | |Setting this bit will reset the 24-bit up counter value CNT (TIMERx_CNT[23:0]) and also force CNTEN (TIMERx_CTL[30]) to 0 if ACTSTS (TIMERx_CTL[25]) is 1.
+ * | | |0 = No effect.
+ * | | |1 = Reset internal 8-bit prescale counter, 24-bit up counter value and CNTEN bit.
+ * |[28:27] |OPMODE |Timer Counting Mode Select
+ * | | |00 = The Timer controller is operated in One-shot mode.
+ * | | |01 = The Timer controller is operated in Periodic mode.
+ * | | |10 = The Timer controller is operated in Toggle-output mode.
+ * | | |11 = The Timer controller is operated in Continuous Counting mode.
+ * |[29] |INTEN |Timer Interrupt Enable Bit
+ * | | |0 = Timer Interrupt Disabled.
+ * | | |1 = Timer Interrupt Enabled.
+ * | | |Note: If this bit is enabled, when the timer interrupt flag TIF is set to 1, the timer interrupt signal is generated and inform to CPU.
+ * |[30] |CNTEN |Timer Counting Enable Bit
+ * | | |0 = Stops/Suspends counting.
+ * | | |1 = Starts counting.
+ * | | |Note1: In stop status, and then set CNTEN to 1 will enable the 24-bit up counter to keep counting from the last stop counting value.
+ * | | |Note2: This bit is auto-cleared by hardware in one-shot mode (TIMER_CTL[28:27] = 00) when the timer interrupt flag TIF (TIMERx_INTSTS[0]) is generated.
+ * |[31] |ICEDEBUG |ICE Debug Mode Acknowledge Disable
+ * | | |0 = ICE debug mode acknowledgement effects TIMER counting.
+ * | | |TIMER counter will be held while CPU is held by ICE.
+ * | | |1 = ICE debug mode acknowledgement Disabled.
+ * | | |TIMER counter will keep going no matter CPU is held by ICE or not.
+ * @var TIMER_T::CMP
+ * Offset: 0x04 Timer Compare Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[23:0] |CMPDAT |Timer Compared Value
+ * | | |CMPDAT is a 24-bit compared value register.
+ * | | |When the internal 24-bit up counter value is equal to CMPDAT value, the TIF (TIMERx_INTSTS[0] Timer Interrupt Flag) will set to 1.
+ * | | |Time-out period = (Period of timer clock input) * (8-bit PSC + 1) * (24-bit CMPDAT).
+ * | | |Note1: Never write 0x0 or 0x1 in CMPDAT field, or the core will run into unknown state.
+ * | | |Note2: When timer is operating at continuous counting mode, the 24-bit up counter will keep counting continuously even if user writes a new value into CMPDAT field.
+ * | | |But if timer is operating at other modes, the 24-bit up counter will restart counting from 0 and using newest CMPDAT value to be the timer compared value while user writes a new value into CMPDAT field.
+ * @var TIMER_T::INTSTS
+ * Offset: 0x08 Timer Interrupt Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |TIF |Timer Interrupt Flag
+ * | | |This bit indicates the interrupt flag status of Timer while 24-bit timer up counter CNT (TIMERx_CNT[23:0]) value reaches to CMPDAT (TIMERx_CMP[23:0]) value.
+ * | | |0 = No effect.
+ * | | |1 = CNT value matches the CMPDAT value.
+ * | | |Note: This bit is cleared by writing 1 to it.
+ * |[1] |TWKF |Timer Wake-Up Flag
+ * | | |This bit indicates the interrupt wake-up flag status of timer.
+ * | | |0 = Timer does not cause CPU wake-up.
+ * | | |1 = CPU wake-up from Idle or Power-down mode if timer time-out interrupt signal generated.
+ * | | |Note: This bit is cleared by writing 1 to it.
+ * @var TIMER_T::CNT
+ * Offset: 0x0C Timer Data Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[23:0] |CNT |Timer Data Register
+ * | | |This field can be reflected the internal 24-bit timer counter value or external event input counter value from Tx_CNT (x=0~3) pin.
+ * | | |If EXTCNTEN (TIMERx_CTL[24] ) is 0, user can read CNT value for getting current 24- bit counter value .
+ * | | |If EXTCNTEN (TIMERx_CTL[24] ) is 1, user can read CNT value for getting current 24- bit event input counter value.
+ * @var TIMER_T::CAP
+ * Offset: 0x10 Timer Capture Data Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[23:0] |CAPDAT |Timer Capture Data Register
+ * | | |When CAPEN (TIMERx_EXTCTL[3]) bit is set, CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0, and a transition on Tx_EXT pin matched the CAPEDGE (TIMERx_EXTCTL[2:1]) setting, CAPIF (TIMERx_EINTSTS[0]) will set to 1 and the current timer counter value CNT (TIMERx_CNT[23:0]) will be auto-loaded into this CAPDAT field.
+ * @var TIMER_T::EXTCTL
+ * Offset: 0x14 Timer External Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |CNTPHASE |Timer External Count Phase
+ * | | |This bit indicates the detection phase of external counting pin Tx_CNT (x= 0~3).
+ * | | |0 = A Falling edge of external counting pin will be counted.
+ * | | |1 = A Rising edge of external counting pin will be counted.
+ * |[2:1] |CAPEDGE |Timer External Capture Pin Edge Detect
+ * | | |00 = A Falling edge on Tx_EXT (x= 0~3) pin will be detected.
+ * | | |01 = A Rising edge on Tx_EXT (x= 0~3) pin will be detected.
+ * | | |10 = Either Rising or Falling edge on Tx_EXT (x= 0~3) pin will be detected.
+ * | | |11 = Reserved.
+ * |[3] |CAPEN |Timer External Capture Pin Enable
+ * | | |This bit enables the Tx_EXT pin.
+ * | | |0 =Tx_EXT (x= 0~3) pin Disabled.
+ * | | |1 =Tx_EXT (x= 0~3) pin Enabled.
+ * |[4] |CAPFUNCS |Capture Function Selection
+ * | | |0 = External Capture Mode Enabled.
+ * | | |1 = External Reset Mode Enabled.
+ * | | |Note1: When CAPFUNCS is 0, transition on Tx_EXT (x= 0~3) pin is using to save the 24-bit timer counter value.
+ * | | |Note2: When CAPFUNCS is 1, transition on Tx_EXT (x= 0~3) pin is using to reset the 24-bit timer counter value.
+ * |[5] |CAPIEN |Timer External Capture Interrupt Enable
+ * | | |0 = Tx_EXT (x= 0~3) pin detection Interrupt Disabled.
+ * | | |1 = Tx_EXT (x= 0~3) pin detection Interrupt Enabled.
+ * | | |Note: CAPIEN is used to enable timer external interrupt.
+ * | | |If CAPIEN enabled, timer will rise an interrupt when CAPIF (TIMERx_EINTSTS[0]) is 1.
+ * | | |For example, while CAPIEN = 1, CAPEN = 1, and CAPEDGE = 00, a 1 to 0 transition on the Tx_EXT pin will cause the CAPIF to be set then the interrupt signal is generated and sent to NVIC to inform CPU.
+ * |[6] |CAPDBEN |Timer External Capture Pin De-Bounce Enable
+ * | | |0 = Tx_EXT (x= 0~3) pin de-bounce Disabled.
+ * | | |1 = Tx_EXT (x= 0~3) pin de-bounce Enabled.
+ * | | |Note: If this bit is enabled, the edge detection of Tx_EXT pin is detected with de-bounce circuit.
+ * |[7] |CNTDBEN |Timer Counter Pin De-Bounce Enable
+ * | | |0 = Tx_CNT (x= 0~3) pin de-bounce Disabled.
+ * | | |1 = Tx_CNT (x= 0~3) pin de-bounce Enabled.
+ * | | |Note: If this bit is enabled, the edge detection of Tx_CNT pin is detected with de-bounce circuit.
+ * @var TIMER_T::EINTSTS
+ * Offset: 0x18 Timer External Interrupt Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |CAPIF |Timer External Capture Interrupt Flag
+ * | | |This bit indicates the timer external capture interrupt flag status.
+ * | | |0 = Tx_EXT (x= 0~3) pin interrupt did not occur.
+ * | | |1 = Tx_EXT (x= 0~3) pin interrupt occurred.
+ * | | |Note1: This bit is cleared by writing 1 to it.
+ * | | |Note2: When CAPEN (TIMERx_EXTCTL[3]) bit is set, CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0, and a transition on Tx_EXT (x= 0~3) pin matched the CAPEDGE (TIMERx_EXTCTL[2:1]) setting, this bit will set to 1 by hardware.
+ * | | |Note3: There is a new incoming capture event detected before CPU clearing the CAPIF status.
+ * | | |If the above condition occurred, the Timer will keep register TIMERx_CAP unchanged and drop the new capture value.
+ */
+
+ __IO uint32_t CTL; /* Offset: 0x00 Timer Control and Status Register */
+ __IO uint32_t CMP; /* Offset: 0x04 Timer Compare Register */
+ __IO uint32_t INTSTS; /* Offset: 0x08 Timer Interrupt Status Register */
+ __I uint32_t CNT; /* Offset: 0x0C Timer Data Register */
+ __I uint32_t CAP; /* Offset: 0x10 Timer Capture Data Register */
+ __IO uint32_t EXTCTL; /* Offset: 0x14 Timer External Control Register */
+ __IO uint32_t EINTSTS; /* Offset: 0x18 Timer External Interrupt Status Register */
+
+} TIMER_T;
+
+
+
+/**
+ @addtogroup TMR_CONST TMR Bit Field Definition
+ Constant Definitions for TMR Controller
+@{ */
+
+#define TIMER_CTL_PSC_Pos (0) /*!< TIMER_T::CTL: PSC Position */
+#define TIMER_CTL_PSC_Msk (0xfful << TIMER_CTL_PSC_Pos) /*!< TIMER_T::CTL: PSC Mask */
+
+#define TIMER_CTL_WKTKEN_Pos (17) /*!< TIMER_T::CTL: WKTKEN Position */
+#define TIMER_CTL_WKTKEN_Msk (0x1ul << TIMER_CTL_WKTKEN_Pos) /*!< TIMER_T::CTL: WKTKEN Mask */
+
+#define TIMER_CTL_TRGSSEL_Pos (18) /*!< TIMER_T::CTL: TRGSSEL Position */
+#define TIMER_CTL_TRGSSEL_Msk (0x1ul << TIMER_CTL_TRGSSEL_Pos) /*!< TIMER_T::CTL: TRGSSEL Mask */
+
+#define TIMER_CTL_TRGPWM_Pos (19) /*!< TIMER_T::CTL: TRGPWM Position */
+#define TIMER_CTL_TRGPWM_Msk (0x1ul << TIMER_CTL_TRGPWM_Pos) /*!< TIMER_T::CTL: TRGPWM Mask */
+
+#define TIMER_CTL_TRGDAC_Pos (20) /*!< TIMER_T::CTL: TRGDAC Position */
+#define TIMER_CTL_TRGDAC_Msk (0x1ul << TIMER_CTL_TRGDAC_Pos) /*!< TIMER_T::CTL: TRGDAC Mask */
+
+#define TIMER_CTL_TRGEADC_Pos (21) /*!< TIMER_T::CTL: TRGEADC Position */
+#define TIMER_CTL_TRGEADC_Msk (0x1ul << TIMER_CTL_TRGEADC_Pos) /*!< TIMER_T::CTL: TRGEADC Mask */
+
+#define TIMER_CTL_TGLPINSEL_Pos (22) /*!< TIMER_T::CTL: TGLPINSEL Position */
+#define TIMER_CTL_TGLPINSEL_Msk (0x1ul << TIMER_CTL_TGLPINSEL_Pos) /*!< TIMER_T::CTL: TGLPINSEL Mask */
+
+#define TIMER_CTL_WKEN_Pos (23) /*!< TIMER_T::CTL: WKEN Position */
+#define TIMER_CTL_WKEN_Msk (0x1ul << TIMER_CTL_WKEN_Pos) /*!< TIMER_T::CTL: WKEN Mask */
+
+#define TIMER_CTL_EXTCNTEN_Pos (24) /*!< TIMER_T::CTL: EXTCNTEN Position */
+#define TIMER_CTL_EXTCNTEN_Msk (0x1ul << TIMER_CTL_EXTCNTEN_Pos) /*!< TIMER_T::CTL: EXTCNTEN Mask */
+
+#define TIMER_CTL_ACTSTS_Pos (25) /*!< TIMER_T::CTL: ACTSTS Position */
+#define TIMER_CTL_ACTSTS_Msk (0x1ul << TIMER_CTL_ACTSTS_Pos) /*!< TIMER_T::CTL: ACTSTS Mask */
+
+#define TIMER_CTL_RSTCNT_Pos (26) /*!< TIMER_T::CTL: RSTCNT Position */
+#define TIMER_CTL_RSTCNT_Msk (0x1ul << TIMER_CTL_RSTCNT_Pos) /*!< TIMER_T::CTL: RSTCNT Mask */
+
+#define TIMER_CTL_OPMODE_Pos (27) /*!< TIMER_T::CTL: OPMODE Position */
+#define TIMER_CTL_OPMODE_Msk (0x3ul << TIMER_CTL_OPMODE_Pos) /*!< TIMER_T::CTL: OPMODE Mask */
+
+#define TIMER_CTL_INTEN_Pos (29) /*!< TIMER_T::CTL: INTEN Position */
+#define TIMER_CTL_INTEN_Msk (0x1ul << TIMER_CTL_INTEN_Pos) /*!< TIMER_T::CTL: INTEN Mask */
+
+#define TIMER_CTL_CNTEN_Pos (30) /*!< TIMER_T::CTL: CNTEN Position */
+#define TIMER_CTL_CNTEN_Msk (0x1ul << TIMER_CTL_CNTEN_Pos) /*!< TIMER_T::CTL: CNTEN Mask */
+
+#define TIMER_CTL_ICEDEBUG_Pos (31) /*!< TIMER_T::CTL: ICEDEBUG Position */
+#define TIMER_CTL_ICEDEBUG_Msk (0x1ul << TIMER_CTL_ICEDEBUG_Pos) /*!< TIMER_T::CTL: ICEDEBUG Mask */
+
+#define TIMER_CMP_CMPDAT_Pos (0) /*!< TIMER_T::CMP: CMPDAT Position */
+#define TIMER_CMP_CMPDAT_Msk (0xfffffful << TIMER_CMP_CMPDAT_Pos) /*!< TIMER_T::CMP: CMPDAT Mask */
+
+#define TIMER_INTSTS_TIF_Pos (0) /*!< TIMER_T::INTSTS: TIF Position */
+#define TIMER_INTSTS_TIF_Msk (0x1ul << TIMER_INTSTS_TIF_Pos) /*!< TIMER_T::INTSTS: TIF Mask */
+
+#define TIMER_INTSTS_TWKF_Pos (1) /*!< TIMER_T::INTSTS: TWKF Position */
+#define TIMER_INTSTS_TWKF_Msk (0x1ul << TIMER_INTSTS_TWKF_Pos) /*!< TIMER_T::INTSTS: TWKF Mask */
+
+#define TIMER_CNT_CNT_Pos (0) /*!< TIMER_T::CNT: CNT Position */
+#define TIMER_CNT_CNT_Msk (0xfffffful << TIMER_CNT_CNT_Pos) /*!< TIMER_T::CNT: CNT Mask */
+
+#define TIMER_CAP_CAPDAT_Pos (0) /*!< TIMER_T::CAP: CAPDAT Position */
+#define TIMER_CAP_CAPDAT_Msk (0xfffffful << TIMER_CAP_CAPDAT_Pos) /*!< TIMER_T::CAP: CAPDAT Mask */
+
+#define TIMER_EXTCTL_CNTPHASE_Pos (0) /*!< TIMER_T::EXTCTL: CNTPHASE Position */
+#define TIMER_EXTCTL_CNTPHASE_Msk (0x1ul << TIMER_EXTCTL_CNTPHASE_Pos) /*!< TIMER_T::EXTCTL: CNTPHASE Mask */
+
+#define TIMER_EXTCTL_CAPEDGE_Pos (1) /*!< TIMER_T::EXTCTL: CAPEDGE Position */
+#define TIMER_EXTCTL_CAPEDGE_Msk (0x3ul << TIMER_EXTCTL_CAPEDGE_Pos) /*!< TIMER_T::EXTCTL: CAPEDGE Mask */
+
+#define TIMER_EXTCTL_CAPEN_Pos (3) /*!< TIMER_T::EXTCTL: CAPEN Position */
+#define TIMER_EXTCTL_CAPEN_Msk (0x1ul << TIMER_EXTCTL_CAPEN_Pos) /*!< TIMER_T::EXTCTL: CAPEN Mask */
+
+#define TIMER_EXTCTL_CAPFUNCS_Pos (4) /*!< TIMER_T::EXTCTL: CAPFUNCS Position */
+#define TIMER_EXTCTL_CAPFUNCS_Msk (0x1ul << TIMER_EXTCTL_CAPFUNCS_Pos) /*!< TIMER_T::EXTCTL: CAPFUNCS Mask */
+
+#define TIMER_EXTCTL_CAPIEN_Pos (5) /*!< TIMER_T::EXTCTL: CAPIEN Position */
+#define TIMER_EXTCTL_CAPIEN_Msk (0x1ul << TIMER_EXTCTL_CAPIEN_Pos) /*!< TIMER_T::EXTCTL: CAPIEN Mask */
+
+#define TIMER_EXTCTL_CAPDBEN_Pos (6) /*!< TIMER_T::EXTCTL: CAPDBEN Position */
+#define TIMER_EXTCTL_CAPDBEN_Msk (0x1ul << TIMER_EXTCTL_CAPDBEN_Pos) /*!< TIMER_T::EXTCTL: CAPDBEN Mask */
+
+#define TIMER_EXTCTL_CNTDBEN_Pos (7) /*!< TIMER_T::EXTCTL: CNTDBEN Position */
+#define TIMER_EXTCTL_CNTDBEN_Msk (0x1ul << TIMER_EXTCTL_CNTDBEN_Pos) /*!< TIMER_T::EXTCTL: CNTDBEN Mask */
+
+#define TIMER_EINTSTS_CAPIF_Pos (0) /*!< TIMER_T::EINTSTS: CAPIF Position */
+#define TIMER_EINTSTS_CAPIF_Msk (0x1ul << TIMER_EINTSTS_CAPIF_Pos) /*!< TIMER_T::EINTSTS: CAPIF Mask */
+
+/**@}*/ /* TIMER_CONST */
+/**@}*/ /* end of TIMER register group */
+
+
+/*---------------------- Universal Asynchronous Receiver/Transmitter Controller -------------------------*/
+/**
+ @addtogroup UART Universal Asynchronous Receiver/Transmitter Controller(UART)
+ Memory Mapped Structure for UART Controller
+@{ */
+
+
+typedef struct
+{
+
+
+
+
+/**
+ * @var UART_T::DAT
+ * Offset: 0x00 UART Receive/Transmit Buffer Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:0] |DAT |Receiving/Transmit Buffer
+ * | | |Write Operation:
+ * | | |By writing one byte to this register, the data byte will be stored in transmitter FIFO.
+ * | | |The UART Controller will send out the data stored in transmitter FIFO top location through the UART_TXD.
+ * | | |Read Operation:
+ * | | |By reading this register, the UART will return an 8-bit data received from receiving FIFO.
+ * @var UART_T::INTEN
+ * Offset: 0x04 UART Interrupt Enable Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |RDAIEN |Receive Data Available Interrupt Enable Bit
+ * | | |0 = Receive data available interrupt Disabled.
+ * | | |1 = Receive data available interrupt Enabled.
+ * |[1] |THREIEN |Transmit Holding Register Empty Interrupt Enable Bit
+ * | | |0 = Transmit holding register empty interrupt Disabled.
+ * | | |1 = Transmit holding register empty interrupt Enabled.
+ * |[2] |RLSIEN |Receive Line Status Interrupt Enable Bit
+ * | | |0 = Receive Line Status interrupt Disabled.
+ * | | |1 = Receive Line Status interrupt Enabled.
+ * |[3] |MODEMIEN |Modem Status Interrupt Enable Bit
+ * | | |0 = Modem status interrupt Disabled.
+ * | | |1 = Modem status interrupt Enabled.
+ * |[4] |RXTOIEN |RX Time-Out Interrupt Enable Bit
+ * | | |0 = RX time-out interrupt Disabled.
+ * | | |1 = RX time-out interrupt Enabled.
+ * |[5] |BUFERRIEN |Buffer Error Interrupt Enable Bit
+ * | | |0 = Buffer error interrupt Disabled.
+ * | | |1 = Buffer error interrupt Enabled.
+ * |[8] |LINIEN |LIN Bus Interrupt Enable Bit (Not Available In UART2/UART3)
+ * | | |0 = LIN bus interrupt Disabled.
+ * | | |1 = LIN bus interrupt Enabled.
+ * | | |Note: This bit is used for LIN function mode.
+ * |[9] |WKCTSIEN |nCTS Wake-Up Interrupt Enable Bit
+ * | | |0 = nCTS wake-up system function Disabled.
+ * | | |1 = Wake-up system function Enabled, when the system is in Power-down mode, an external nCTS change will wake-up system from Power-down mode.
+ * |[10] |WKDATIEN |Incoming Data Wake-Up Interrupt Enable Bit
+ * | | |0 = Incoming data wake-up system function Disabled.
+ * | | |1 = Incoming data wake-up system function Enabled, when the system is in Power-down mode, incoming data will wake-up system from Power-down mode.
+ * | | |Note: Hardware will clear this bit when the incoming data wake-up operation finishes and "system clock" work stable
+ * |[11] |TOCNTEN |Time-Out Counter Enable Bit
+ * | | |0 = Time-out counter Disabled.
+ * | | |1 = Time-out counter Enabled.
+ * |[12] |ATORTSEN |nRTS Auto-Flow Control Enable Bit
+ * | | |0 = nRTS auto-flow control Disabled.
+ * | | |1 = nRTS auto-flow control Enabled.
+ * | | |Note: When nRTS auto-flow is enabled, if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO[19:16]), the UART will de-assert nRTS signal.
+ * |[13] |ATOCTSEN |nCTS Auto-Flow Control Enable Bit
+ * | | |0 = nCTS auto-flow control Disabled.
+ * | | |1 = nCTS auto-flow control Enabled.
+ * | | |Note: When nCTS auto-flow is enabled, the UART will send data to external device if nCTS input assert (UART will not send data to device until nCTS is asserted).
+ * |[14] |TXPDMAEN |TX DMA Enable Bit
+ * | | |This bit can enable or disable TX DMA service.
+ * | | |0 = TX DMA Disabled.
+ * | | |1 = TX DMA Enabled.
+ * |[15] |RXPDMAEN |RX DMA Enable Bit
+ * | | |This bit can enable or disable RX DMA service.
+ * | | |0 = RX DMA Disabled.
+ * | | |1 = RX DMA Enabled.
+ * |[18] |ABRIEN |Auto-Baud Rate Interrupt Enable Bit
+ * | | |0 = Auto-baud rate interrupt Disabled.
+ * | | |1 = Auto-baud rate interrupt Enabled.
+ * @var UART_T::FIFO
+ * Offset: 0x08 UART FIFO Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[1] |RXRST |RX Field Software Reset
+ * | | |When RXRST (UART_FIFO[1]) is set, all the byte in the receiver FIFO and RX internal state machine are cleared.
+ * | | |0 = No effect.
+ * | | |1 = Reset the RX internal state machine and pointers.
+ * | | |Note: This bit will automatically clear at least 3 UART peripheral clock cycles.
+ * |[2] |TXRST |TX Field Software Reset
+ * | | |When TXRST (UART_FIFO[2]) is set, all the byte in the transmit FIFO and TX internal state machine are cleared.
+ * | | |0 = No effect.
+ * | | |1 = Reset the TX internal state machine and pointers.
+ * | | |Note: This bit will automatically clear at least 3 UART peripheral clock cycles.
+ * |[7:4] |RFITL |RX FIFO Interrupt Trigger Level
+ * | | |When the number of bytes in the receive FIFO equals the RFITL, the RDAIF will be set (if RDAIEN (UART_INTEN [0]) enabled, and an interrupt will be generated).
+ * | | |0000 = RX FIFO Interrupt Trigger Level is 1 byte.
+ * | | |0001 = RX FIFO Interrupt Trigger Level is 4 bytes.
+ * | | |0010 = RX FIFO Interrupt Trigger Level is 8 bytes.
+ * | | |0011 = RX FIFO Interrupt Trigger Level is 14 bytes.
+ * | | |Others = Reserved.
+ * |[8] |RXOFF |Receiver Disable
+ * | | |The receiver is disabled or not (set 1 to disable receiver)
+ * | | |0 = Receiver Enabled.
+ * | | |1 = Receiver Disabled.
+ * | | |Note: This bit is used for RS-485 Normal Multi-drop mode.
+ * | | |It should be programmed before RS485NMM (UART_ALTCTL [8]) is programmed.
+ * |[19:16] |RTSTRGLV |nRTS Trigger Level For Auto-Flow Control Use
+ * | | |0000 = nRTS Trigger Level is 1 bytes.
+ * | | |0001 = nRTS Trigger Level is 4bytes.
+ * | | |0010 = nRTS Trigger Level is 8 bytes.
+ * | | |0011 = nRTS Trigger Level is 14 bytes.
+ * | | |Others = Reserved.
+ * | | |Note: This field is used for auto nRTS flow control.
+ * @var UART_T::LINE
+ * Offset: 0x0C UART Line Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[1:0] |WLS |Word Length Selection
+ * | | |This field sets UART word length.
+ * | | |00 = 5 bits.
+ * | | |01 = 6 bits.
+ * | | |10 = 7 bits.
+ * | | |11 = 8 bits.
+ * |[2] |NSB |Number Of "STOP Bit"
+ * | | |0 = One "STOP bit" is generated in the transmitted data.
+ * | | |1 = When select 5-bit word length, 1.5 "STOP bit" is generated in the transmitted data.
+ * | | |When select 6-, 7- and 8-bit word length, 2 "STOP bit" is generated in the transmitted data.
+ * |[3] |PBE |Parity Bit Enable Bit
+ * | | |0 = No parity bit generated Disabled.
+ * | | |1 = Parity bit generated Enabled.
+ * | | |Note : Parity bit is generated on each outgoing character and is checked on each incoming data.
+ * |[4] |EPE |Even Parity Enable Bit
+ * | | |0 = Odd number of logic 1's is transmitted and checked in each word.
+ * | | |1 = Even number of logic 1's is transmitted and checked in each word.
+ * | | |Note:This bit has effect only when PBE (UART_LINE[3]) is set.
+ * |[5] |SPE |Stick Parity Enable Bit
+ * | | |0 = Stick parity Disabled.
+ * | | |1 = Stick parity Enabled.
+ * | | |Note: If PBE (UART_LINE[3]) and EPE (UART_LINE[4]) are logic 1, the parity bit is transmitted and checked as logic 0.
+ * | | |If PBE (UART_LINE[3]) is 1 and EPE (UART_LINE[4]) is 0 then the parity bit is transmitted and checked as 1.
+ * |[6] |BCB |Break Control Bit
+ * | | |0 = Break Control Disabled.
+ * | | |1 = Break Control Enabled.
+ * | | |Note: When this bit is set to logic 1, the serial data output (TX) is forced to the Spacing State (logic 0).
+ * | | |This bit acts only on TX line and has no effect on the transmitter logic.
+ * @var UART_T::MODEM
+ * Offset: 0x10 UART Modem Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[1] |RTS |nRTS (Request-To-Send) Signal Control
+ * | | |This bit is direct control internal nRTS signal active or not, and then drive the nRTS pin output with RTSACTLV bit configuration.
+ * | | |0 = nRTS signal is active.
+ * | | |1 = nRTS signal is inactive.
+ * | | |Note1: This nRTS signal control bit is not effective when nRTS auto-flow control is enabled in UART function mode.
+ * | | |Note2: This nRTS signal control bit is not effective when RS-485 auto direction mode (AUD) is enabled in RS-485 function mode.
+ * |[9] |RTSACTLV |nRTS Pin Active Level
+ * | | |This bit defines the active level state of nRTS pin output.
+ * | | |0 =n RTS pin output is high level active.
+ * | | |1 = nRTS pin output is low level active. (Default)
+ * | | |Note1: Refer to Figure 6.21-10 and Figure 6.21-11 for UART function mode.
+ * | | |Note2: Refer to Figure 6.21-21 and Figure 6.21-22 for RS-485 function mode.
+ * |[13] |RTSSTS |nRTS Pin Status (Read Only)
+ * | | |This bit mirror from nRTS pin output of voltage logic status.
+ * | | |0 = nRTS pin output is low level voltage logic state.
+ * | | |1 = nRTS pin output is high level voltage logic state.
+ * @var UART_T::MODEMSTS
+ * Offset: 0x14 UART Modem Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |CTSDETF |Detect nCTS State Change Flag (Read Only)
+ * | | |This bit is set whenever nCTS input has change state, and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN [3]) is set to 1.
+ * | | |0 = nCTS input has not change state.
+ * | | |1 = nCTS input has change state.
+ * | | |Note: This bit is read only, but can be cleared by writing "1" to it.
+ * |[4] |CTSSTS |nCTS Pin Status (Read Only)
+ * | | |This bit mirror from nCTS pin input of voltage logic status.
+ * | | |0 = nCTS pin input is low level voltage logic state.
+ * | | |1 = nCTS pin input is high level voltage logic state.
+ * | | |Note: This bit echoes when UART Controller peripheral clock is enabled, and nCTS multi-function port is selected.
+ * |[8] |CTSACTLV |nCTS Pin Active Level
+ * | | |This bit defines the active level state of nCTS pin input.
+ * | | |0 = nCTS pin input is high level active.
+ * | | |1 = nCTS pin input is low level active. (Default)
+ * @var UART_T::FIFOSTS
+ * Offset: 0x18 UART FIFO Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |RXOVIF |RX Overflow Error Interrupt Flag (Read Only)
+ * | | |This bit is set when RX FIFO overflow.
+ * | | |If the number of bytes of received data is greater than RX_FIFO (UART_DAT) size, 16 bytes this bit will be set.
+ * | | |0 = RX FIFO is not overflow.
+ * | | |1 = RX FIFO is overflow.
+ * | | |Note: This bit is read only, but can be cleared by writing "1" to it.
+ * |[1] |ABRDIF |Auto-Baud Rate Detect Interrupt (Read Only)
+ * | | |0 = Auto-baud rate detect function is not finished.
+ * | | |1 = Auto-baud rate detect function is finished.
+ * | | |This bit is set to logic "1" when auto-baud rate detect function is finished.
+ * | | |Note: This bit is read only, but can be cleared by writing "1" to it.
+ * |[2] |ABRDTOIF |Auto-Baud Rate Time-Out Interrupt (Read Only)
+ * | | |0 = Auto-baud rate counter is underflow.
+ * | | |1 = Auto-baud rate counter is overflow.
+ * | | |Note1: This bit is set to logic "1" in Auto-baud Rate Detect mode and the baud rate counter is overflow.
+ * | | |Note2: This bit is read only, but can be cleared by writing "1" to it.
+ * |[3] |ADDRDETF |RS-485 Address Byte Detect Flag (Read Only)
+ * | | |0 = Receiver detects a data that is not an address bit (bit 9 ='0').
+ * | | |1 = Receiver detects a data that is an address bit (bit 9 ='1').
+ * | | |Note1: This field is used for RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1 to enable Address detection mode .
+ * | | |Note2: This bit is read only, but can be cleared by writing '1' to it.
+ * |[4] |PEF |Parity Error Flag (Read Only)
+ * | | |This bit is set to logic 1 whenever the received character does not have a valid "parity bit".
+ * | | |0 = No parity error is generated.
+ * | | |1 = Parity error is generated.
+ * | | |Note: This bit is read only, but can be cleared by writing '1' to it.
+ * |[5] |FEF |Framing Error Flag (Read Only)
+ * | | |This bit is set to logic 1 whenever the received character does not have a valid "stop bit" (that is, the stop bit following the last data bit or parity bit is detected as logic 0).
+ * | | |0 = No framing error is generated.
+ * | | |1 = Framing error is generated.
+ * | | |Note: This bit is read only, but can be cleared by writing '1' to it.
+ * |[6] |BIF |Break Interrupt Flag (Read Only)
+ * | | |This bit is set to logic 1 whenever the received data input (RX) is held in the "spacing state" (logic 0) for longer than a full word transmission time (that is, the total time of "start bit" + data bits + parity + stop bits).
+ * | | |0 = No Break interrupt is generated.
+ * | | |1 = Break interrupt is generated.
+ * | | |Note: This bit is read only, but can be cleared by writing '1' to it.
+ * |[13:8] |RXPTR |RX FIFO Pointer (Read Only)
+ * | | |This field indicates the RX FIFO Buffer Pointer.
+ * | | |When UART receives one byte from external device, RXPTR increases one.
+ * | | |When one byte of RX FIFO is read by CPU, RXPTR decreases one.
+ * | | |The Maximum value shown in RXPTR is 15.
+ * | | |When the using level of RX FIFO Buffer equal to 16, the RXFULL bit is set to 1 and RXPTR will show 0.
+ * | | |As one byte of RX FIFO is read by CPU, the RXFULL bit is cleared to 0 and RXPTR will show 15.
+ * |[14] |RXEMPTY |Receiver FIFO Empty (Read Only)
+ * | | |This bit initiate RX FIFO empty or not.
+ * | | |0 = RX FIFO is not empty.
+ * | | |1 = RX FIFO is empty.
+ * | | |Note: When the last byte of RX FIFO has been read by CPU, hardware sets this bit high.
+ * | | |It will be cleared when UART receives any new data.
+ * |[15] |RXFULL |Receiver FIFO Full (Read Only)
+ * | | |This bit initiates RX FIFO full or not.
+ * | | |0 = RX FIFO is not full.
+ * | | |1 = RX FIFO is full.
+ * | | |Note: This bit is set when the number of usage in RX FIFO Buffer is equal to 16, otherwise is cleared by hardware.
+ * |[21:16] |TXPTR |TX FIFO Pointer (Read Only)
+ * | | |This field indicates the TX FIFO Buffer Pointer.
+ * | | |When CPU writes one byte into UART_DAT, TXPTR increases one.
+ * | | |When one byte of TX FIFO is transferred to Transmitter Shift Register, TXPTR decreases one.
+ * | | |The Maximum value shown in TXPTR is 15.
+ * | | |When the using level of TX FIFO Buffer equal to 16, the TXFULL bit is set to 1 and TXPTR will show 0.
+ * | | |As one byte of TX FIFO is transferred to Transmitter Shift Register, the TXFULL bit is cleared to 0 and TXPTR will show 15.
+ * |[22] |TXEMPTY |Transmitter FIFO Empty (Read Only)
+ * | | |This bit indicates TX FIFO empty or not.
+ * | | |0 = TX FIFO is not empty.
+ * | | |1 = TX FIFO is empty.
+ * | | |Note: When the last byte of TX FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high.
+ * | | |It will be cleared when writing data into DAT (TX FIFO not empty).
+ * |[23] |TXFULL |Transmitter FIFO Full (Read Only)
+ * | | |This bit indicates TX FIFO full or not.
+ * | | |0 = TX FIFO is not full.
+ * | | |1 = TX FIFO is full.
+ * | | |Note: This bit is set when the number of usage in TX FIFO Buffer is equal to 16, otherwise is cleared by hardware.
+ * |[24] |TXOVIF |TX Overflow Error Interrupt Flag (Read Only)
+ * | | |If TX FIFO (UART_DAT) is full, an additional write to UART_DAT will cause this bit to logic 1.
+ * | | |0 = TX FIFO is not overflow.
+ * | | |1 = TX FIFO is overflow.
+ * | | |Note: This bit is read only, but can be cleared by writing "1" to it.
+ * |[28] |TXEMPTYF |Transmitter Empty Flag (Read Only)
+ * | | |This bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted.
+ * | | |0 = TX FIFO is not empty.
+ * | | |1 = TX FIFO is empty.
+ * | | |Note: This bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed.
+ * @var UART_T::INTSTS
+ * Offset: 0x1C UART Interrupt Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |RDAIF |Receive Data Available Interrupt Flag (Read Only)
+ * | | |When the number of bytes in the RX FIFO equals the RFITL then the RDAIF(UART_INTSTS[0]) will be set.
+ * | | |If RDAIEN (UART_INTEN [0]) is enabled, the RDA interrupt will be generated.
+ * | | |0 = No RDA interrupt flag is generated.
+ * | | |1 = RDA interrupt flag is generated.
+ * | | |Note: This bit is read only and it will be cleared when the number of unread bytes of RX FIFO drops below the threshold level (RFITL(UART_FIFO[7:4])).
+ * |[1] |THREIF |Transmit Holding Register Empty Interrupt Flag (Read Only)
+ * | | |This bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register.
+ * | | |If THREIEN (UART_INTEN[1]) is enabled, the THRE interrupt will be generated.
+ * | | |0 = No THRE interrupt flag is generated.
+ * | | |1 = THRE interrupt flag is generated.
+ * | | |Note: This bit is read only and it will be cleared when writing data into UART_DAT (TX FIFO not empty).
+ * |[2] |RLSIF |Receive Line Interrupt Flag (Read Only)
+ * | | |This bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF(UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]), is set).
+ * | | |If RLSIEN (UART_INTEN [2]) is enabled, the RLS interrupt will be generated.
+ * | | |0 = No RLS interrupt flag is generated.
+ * | | |1 = RLS interrupt flag is generated.
+ * | | |Note1: In RS-485 function mode, this field is set include receiver detect and received address byte character (bit9 = '1') bit.
+ * | | |At the same time, the bit of ADDRDETF (UART_FIFOSTS[3]) is also set.
+ * | | |Note2: This bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) are cleared.
+ * | | |Note3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]) , FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) and ADDRDETF (UART_FIFOSTS[3]) are cleared.
+ * |[3] |MODEMIF |MODEM Interrupt Flag (Read Only) Channel This bit is set when the nCTS pin has state change (CTSDETF (UART_MODEMSTS[0]) = 1). If MODEMIEN (UART_INTEN [3]) is enabled, the Modem interrupt will be generated.
+ * | | |0 = No Modem interrupt flag is generated.
+ * | | |1 = Modem interrupt flag is generated.
+ * | | |Note: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF(UART_MODEMSTS[0]).
+ * |[4] |RXTOIF |Time-Out Interrupt Flag (Read Only)
+ * | | |This bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC.
+ * | | |If TOUTIEN (UART_INTEN [4]) is enabled, the Tout interrupt will be generated.
+ * | | |0 = No Time-out interrupt flag is generated.
+ * | | |1 = Time-out interrupt flag is generated.
+ * | | |Note: This bit is read only and user can read UART_DAT (RX is in active) to clear it.
+ * |[5] |BUFERRIF |Buffer Error Interrupt Flag (Read Only)
+ * | | |This bit is set when the TX FIFO or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set).
+ * | | |When BERRIF (UART_INTSTS[5])is set, the transfer is not correct.
+ * | | |If BFERRIEN (UART_INTEN [8]) is enabled, the buffer error interrupt will be generated.
+ * | | |0 = No buffer error interrupt flag is generated.
+ * | | |1 = Buffer error interrupt flag is generated.
+ * | | |Note: This bit is read only.
+ * | | |This bit is cleared if both of RXOVIF(UART_FIFOSTS[0]) and TXOVIF(UART_FIFOSTS[24]) are cleared to 0 by writing 1 to RXOVIF(UART_FIFOSTS[0]) and TXOVIF(UART_FIFOSTS[24]).
+ * |[6] |WKIF |UART Wake-up Interrupt Flag (Read Only)
+ * | | |This bit is set when DATWKIF (UART_INTSTS[17]) or CTSWKIF(UART_INTSTS[16]) is set to 1.
+ * | | |0 = No DATWKIF and CTSWKIF are generated.
+ * | | |1 = DATWKIF or CTSWKIF.
+ * | | |Note: This bit is read only.
+ * | | |This bit is cleared if both of DATWKIF (UART_INTSTS[17]) and CTSWKIF(UART_INTSTS[16]) are cleared to 0 by writing 1 to DATWKIF (UART_INTSTS[17]) and CTSWKIF (UART_INTSTS[17]).
+ * |[7] |LINIF |LIN Bus Interrupt Flag (Read Only) (Not Available in UART2/UART3 Channel)
+ * | | |This bit is set when LIN slave header detect (SLVHDETF (UART_LINSTS[0] =1)), LIN break detect (BRKDETF(UART_LINSTS[9])=1), bit error detect (BITEF(UART_LINSTS[9])=1), LIN slave ID parity error (SLVIDPEF(UART_LINSTS[2]) = 1) or LIN slave header error detect (SLVHEF (UART_LINSTS[1])).
+ * | | |If LIN_ IEN (UART_INTEN [8]) is enabled the LIN interrupt will be generated.
+ * | | |0 = None of SLVHDETF, BRKDETF, BITEF, SLVIDPEF and SLVHEF is generated.
+ * | | |1 = At least one of SLVHDETF, BRKDETF, BITEF, SLVIDPEF and SLVHEF is generated.
+ * | | |Note: This bit is read only.
+ * | | |This bit is cleared when SLVHDETF(UART_LINSTS[0]), BRKDETF(UART_LINSTS[8]), BITEF(UART_LINSTS[9]), SLVIDPEF (UART_LINSTS[2]), SLVHEF(UART_LINSTS[1]) and SLVSYNCF(UART_LINSTS[3]) all are cleared.
+ * |[8] |RDAINT |Receive Data Available Interrupt Indicator (Read Only)
+ * | | |This bit is set if RDAIEN (UART_INTEN[0]) and RDAIF (UART_INTSTS[0]) are both set to 1.
+ * | | |0 = No RDA interrupt is generated.
+ * | | |1 = RDA interrupt is generated.
+ * |[9] |THREINT |Transmit Holding Register Empty Interrupt Indicator (Read Only)
+ * | | |This bit is set if THREIEN (UART_INTEN[1])and THREIF(UART_INTSTS[1]) are both set to 1.
+ * | | |0 = No DATE interrupt is generated.
+ * | | |1 = DATE interrupt is generated.
+ * |[10] |RLSINT |Receive Line Status Interrupt Indicator (Read Only)
+ * | | |This bit is set if RLSIEN (UART_INTEN[2]) and RLSIF(UART_INTSTS[2]) are both set to 1.
+ * | | |0 = No RLS interrupt is generated.
+ * | | |1 = RLS interrupt is generated.
+ * |[11] |MODEMINT |MODEM Status Interrupt Indicator (Read Only)
+ * | | |This bit is set if MODEMIEN(UART_INTEN[3]) and MODEMIF(UART_INTSTS[4]) are both set to 1
+ * | | |0 = No Modem interrupt is generated.
+ * | | |1 = Modem interrupt is generated.
+ * |[12] |RXTOINT |Time-Out Interrupt Indicator (Read Only)
+ * | | |This bit is set if TOUTIEN(UART_INTEN[4]) and RXTOIF(UART_INTSTS[4]) are both set to 1.
+ * | | |0 = No Tout interrupt is generated.
+ * | | |1 = Tout interrupt is generated.
+ * |[13] |BUFERRINT |Buffer Error Interrupt Indicator (Read Only)
+ * | | |This bit is set if BFERRIEN(UART_INTEN[5]) and BERRIF(UART_INTSTS[5]) are both set to 1.
+ * | | |0 = No buffer error interrupt is generated.
+ * | | |1 = Buffer error interrupt is generated.
+ * |[15] |LININT |LIN Bus Interrupt Indicator (Read Only)(Not Available in UART2/UART3 Channel)
+ * | | |This bit is set if LINIEN (UART_INTEN[8]) and LIN IF(UART_INTSTS[7]) are both set to 1.
+ * | | |0 = No LIN Bus interrupt is generated.
+ * | | |1 = The LIN Bus interrupt is generated.
+ * |[16] |CTSWKIF |nCTS Wake-Up Interrupt Flag (Read Only)
+ * | | |0 = Chip stays in power-down state.
+ * | | |1 = Chip wake-up from power-down state by nCTS wake-up.
+ * | | |Note1: If WKCTSIEN (UART_INTEN[9])is enabled, the wake-up interrupt is generated.
+ * | | |Note2: This bit is read only, but can be cleared by writing '1' to it.
+ * |[17] |DATWKIF |Data Wake-Up Interrupt Flag (Read Only)
+ * | | |This bit is set if chip wake-up from power-down state by data wake-up.
+ * | | |0 = Chip stays in power-down state.
+ * | | |1 = Chip wake-up from power-down state by data wake-up.
+ * | | |Note1: If WKDATIEN (UART_INTEN[10]) is enabled, the wake-up interrupt is generated.
+ * | | |Note2: This bit is read only, but can be cleared by writing '1' to it.
+ * |[18] |HWRLSIF |In DMA Mode, Receive Line Status Flag (Read Only)
+ * | | |This bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF (UART_FIFOSTS[6]), FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]) is set).
+ * | | |If RLSIEN (UART_INTEN [2]) is enabled, the RLS interrupt will be generated.
+ * | | |0 = No RLS interrupt flag is generated.
+ * | | |1 = RLS interrupt flag is generated.
+ * | | |Note1: In RS-485 function mode, this field include receiver detect any address byte received address byte character (bit9 = '1') bit.
+ * | | |Note2: In UART function mode, this bit is read only and reset to 0 when all bits of BIF(UART_FIFOSTS[6]) , FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) are cleared.
+ * | | |Note3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF(UART_FIFOSTS[6]) , FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) and ADDRDETF (UART_FIFOSTS[3]) are cleared
+ * |[19] |HWMODIF |In DMA Mode, MODEM Interrupt Flag (Read Only)
+ * | | |This bit is set when the nCTS pin has state change (CTSDETF (UART_CTSDETF[0] =1)).
+ * | | |If MODEMIEN (UART_INTEN [3]) is enabled, the Modem interrupt will be generated.
+ * | | |0 = No Modem interrupt flag is generated.
+ * | | |1 = Modem interrupt flag is generated.
+ * | | |Note: This bit is read only and reset to 0 when the bit UART_CTSDETF (US_MSR[0]) is cleared by writing 1 on CTSDETF (UART_CTSDETF [0]).
+ * |[20] |HWTOIF |In DMA Mode, Time-Out Interrupt Flag (Read Only)
+ * | | |This bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]).
+ * | | |If TOUTIEN (UART_INTEN [4]) is enabled, the Tout interrupt will be generated.
+ * | | |0 = No Time-out interrupt flag is generated.
+ * | | |1 = Time-out interrupt flag is generated.
+ * | | |Note: This bit is read only and user can read UART_DAT (RX is in active) to clear it.
+ * |[21] |HWBUFEIF |In DMA Mode, Buffer Error Interrupt Flag (Read Only)
+ * | | |This bit is set when the TX or RX FIFO overflows (TXOVIF (UART_FIFOSTS [24]) or RXOVIF (UART_FIFOSTS[0]) is set).
+ * | | |When BERRIF (UART_INTSTS[5]) is set, the transfer maybe is not correct.
+ * | | |If BFERRIEN (UART_INTEN [5]) is enabled, the buffer error interrupt will be generated.
+ * | | |0 = No buffer error interrupt flag is generated.
+ * | | |1 = Buffer error interrupt flag is generated.
+ * | | |Note: This bit is cleared when both TXOVIF (UART_FIFOSTS[24]]) and RXOVIF (UART_FIFOSTS[0]) are cleared.
+ * |[26] |HWRLSINT |In DMA Mode, Receive Line Status Interrupt Indicator (Read Only)
+ * | | |This bit is set if RLSIEN (UART_INTEN[2])and HWRLSIF(UART_INTSTS[18]) are both set to 1.
+ * | | |0 = No RLS interrupt is generated in DMA mode.
+ * | | |1 = RLS interrupt is generated in DMA mode.
+ * |[27] |HWMODINT |In DMA Mode, MODEM Status Interrupt Indicator (Read Only)
+ * | | |This bit is set if MODEMIEN(UART_INTEN[3]) and HWMODIF(UART_INTSTS[3]) are both set to 1.
+ * | | |0 = No Modem interrupt is generated in DMA mode.
+ * | | |1 = Modem interrupt is generated in DMA mode.
+ * |[28] |HWTOINT |In DMA Mode, Time-Out Interrupt Indicator (Read Only)
+ * | | |This bit is set if TOUTIEN (UART_INTEN[4])and HWTOIF(UART_INTSTS[20]) are both set to 1.
+ * | | |0 = No Tout interrupt is generated in DMA mode.
+ * | | |1 = Tout interrupt is generated in DMA mode.
+ * |[29] |HWBUFEINT |In DMA Mode, Buffer Error Interrupt Indicator (Read Only)
+ * | | |This bit is set if BFERRIEN (UART_INTEN[5]) and HWBEIF (UART_INTSTS[5])are both set to 1.
+ * | | |0 = No buffer error interrupt is generated in DMA mode.
+ * | | |1 = Buffer error interrupt is generated in DMA mode.
+ * @var UART_T::TOUT
+ * Offset: 0x20 UART Time-out Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:0] |TOIC |Time-Out Interrupt Comparator
+ * | | |The time-out counter resets and starts counting (the counting clock = baud rate) whenever the RX FIFO receives a new data word.
+ * | | |Once the content of time-out counter is equal to that of time-out interrupt comparator (TOIC (UART_TOUT[7:0])), a receiver time-out interrupt (RXTOINT(UART_INTSTS[12])) is generated if RXTOIEN (UART_INTEN [4]) enabled.
+ * | | |A new incoming data word or RX FIFO empty will clear RXTOINT(UART_INTSTS[12]).
+ * | | |In order to avoid receiver time-out interrupt generation immediately during one character is being received, TOIC value should be set between 40 and 255.
+ * | | |So, for example, if TOIC is set with 40, the time-out interrupt is generated after four characters are not received when 1 stop bit and no parity check is set for UART transfer.
+ * |[15:8] |DLY |TX Delay Time Value
+ * | | |This field is used to programming the transfer delay time between the last stop bit and next start bit.
+ * | | |The unit is bit time.
+ * @var UART_T::BAUD
+ * Offset: 0x24 UART Baud Rate Divisor Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |BRD |Baud Rate Divider
+ * | | |The field indicates the baud rate divider.
+ * | | |This filed is used in baud rate calculation.
+ * | | |The detail description is shown in Table 6.21-2.
+ * |[27:24] |EDIVM1 |Extra Divider For BAUD Rate Mode 1
+ * | | |This field is used for baud rate calculation in mode 1 and has no effect for baud rate calculation in mode 0 and mode 2.
+ * | | |The detail description is shown in Table 6.21-2.
+ * |[28] |BAUDM0 |BAUD Rate Mode Selection Bit 0
+ * | | |This bit is baud rate mode selection bit 0.
+ * | | |UART provides three baud rate calculation modes.
+ * | | |This bit combines with BAUDM1 (UART_BAUD[29]) to select baud rate calculation mode.
+ * | | |The detail description is shown in Table 6.21-2.
+ * |[29] |BAUDM1 |BAUD Rate Mode Selection Bit 1
+ * | | |This bit is baud rate mode selection bit 1.
+ * | | |UART provides three baud rate calculation modes.
+ * | | |This bit combines with BAUDM0 (UART_BAUD[28]) to select baud rate calculation mode.
+ * | | |The detail description is shown in Table 6.21-2.
+ * | | |Note: In IrDA mode must be operated in mode 0.
+ * @var UART_T::IRDA
+ * Offset: 0x28 UART IrDA Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[1] |TXEN |IrDA Receiver/Transmitter Selection Enable Bit
+ * | | |0 = IrDA Transmitter Disabled and Receiver Enabled. (Default)
+ * | | |1 = IrDA Transmitter Enabled and Receiver Disabled.
+ * | | |Note: In IrDA function mode (FUNCSEL(UART_FUNCSEL[1:0])=10), the first received data is unreliable and it should be skipped if IrDA receiver is enabled (TXEN(UART_IRDA[1])=0) at the first time.
+ * |[5] |TXINV |IrDA Inverse Transmitting Output Signal
+ * | | |0 = None inverse transmitting signal. (Default)
+ * | | |1 = Inverse transmitting output signal.
+ * |[6] |RXINV |IrDA Inverse Receive Input Signal
+ * | | |0 = None inverse receiving input signal.
+ * | | |1 = Inverse receiving input signal. (Default)
+ * @var UART_T::ALTCTL
+ * Offset: 0x2C UART Alternate Control/Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[3:0] |BRKFL |UART LIN Break Field Length (Only Available In UART0/UART1 Channel)
+ * | | |This field indicates a 4-bit LIN TX break field count.
+ * | | |Note1: This break field length is BRKFL + 1
+ * | | |Note2: According to LIN spec, the reset value is 0xC (break field length = 13).
+ * |[6] |LINRXEN |LIN RX Enable Bit (Only Available In UART0/UART1 Channel)
+ * | | |0 = LIN RX mode Disabled.
+ * | | |1 = LIN RX mode Enabled.
+ * |[7] |LINTXEN |LIN TX Break Mode Enable Bit (Only Available In UART0/UART1 Channel)
+ * | | |0 = LIN TX Break mode Disabled.
+ * | | |1 = LIN TX Break mode Enabled.
+ * | | |Note: When TX break field transfer operation finished, this bit will be cleared automatically.
+ * |[8] |RS485NMM |RS-485 Normal Multi-Drop Operation Mode (NMM)
+ * | | |0 = RS-485 Normal Multi-drop Operation mode (NMM) Disabled.
+ * | | |1 = RS-485 Normal Multi-drop Operation mode (NMM) Enabled.
+ * | | |Note: It cannot be active with RS-485_AAD operation mode.
+ * |[9] |RS485AAD |RS-485 Auto Address Detection Operation Mode (AAD)
+ * | | |0 = RS-485 Auto Address Detection Operation mode (AAD) Disabled.
+ * | | |1 = RS-485 Auto Address Detection Operation mode (AAD) Enabled.
+ * | | |Note: It cannot be active with RS-485_NMM operation mode.
+ * |[10] |RS485AUD |RS-485 Auto Direction Function (AUD)
+ * | | |0 = RS-485 Auto Direction Operation function (AUD) Disabled.
+ * | | |1 = RS-485 Auto Direction Operation function (AUD) Enabled.
+ * | | |Note: It can be active with RS-485_AAD or RS-485_NMM operation mode.
+ * |[15] |ADDRDEN |RS-485 Address Detection Enable Bit
+ * | | |This bit is used to enable RS-485 Address Detection mode.
+ * | | |0 = Address detection mode Disabled.
+ * | | |1 = Address detection mode Enabled.
+ * | | |Note: This bit is used for RS-485 any operation mode.
+ * |[17] |ABRIF |Auto-Baud Rate Interrupt Flag (Read Only)
+ * | | |This bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN(UART_INTEN [18]) is set then the auto-baud rate interrupt will be generated.
+ * | | |Note: This bit is read only, but it can be cleared by writing "1" to ABRDTOIF (UART_FIFOSTS[2]) and ABRDIF(UART_FIFOSTS[1])
+ * |[18] |ABRDEN |Auto-Baud Rate Detect Enable Bit
+ * | | |0 = Auto-baud rate detect function Disabled.
+ * | | |1 = Auto-baud rate detect function Enabled.
+ * | | |This bit is cleared automatically after auto-baud detection is finished.
+ * |[20:19] |ABRDBITS |Auto-Baud Rate Detect Bit Length
+ * | | |00 = 1-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x01.
+ * | | |01 = 2-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x02.
+ * | | |10 = 4-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x08.
+ * | | |11 = 8-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x80.
+ * | | |Note : The calculation of bit number includes the START bit.
+ * |[31:24] |ADDRMV |Address Match Value
+ * | | |This field contains the RS-485 address match values.
+ * | | |Note: This field is used for RS-485 auto address detection mode.
+ * @var UART_T::FUNCSEL
+ * Offset: 0x30 UART Function Select Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[1:0] |FUNCSEL |Function Select
+ * | | |00 = UART function.
+ * | | |01 = LIN function (Only Available in UART0/UART1 Channel).
+ * | | |10 = IrDA function.
+ * | | |11 = RS-485 function.
+ * | | |Note: In IrDA function mode (FUNCSEL(UART_FUNCSEL[1:0])=10), the first received data is unreliable and it should be skipped if IrDA receiver is enabled (TXEN(UART_IRDA[1])=0) at the first time.
+ * @var UART_T::LINCTL
+ * Offset: 0x34 UART LIN Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |SLVEN |LIN Slave Mode Enable Bit
+ * | | |0 = LIN slave mode Disabled.
+ * | | |1 = LIN slave mode Enabled.
+ * |[1] |SLVHDEN |LIN Slave Header Detection Enable Bit
+ * | | |0 = LIN slave header detection Disabled.
+ * | | |1 = LIN slave header detection Enabled.
+ * | | |Note1: This bit only valid when in LIN slave mode (SLVEN (UART_LINCTL[0]) = 1).
+ * | | |Note2: In LIN function mode, when detect header field (break + sync + frame ID), SLVHDETF (UART_LINSTS [0]) flag will be asserted.
+ * | | |If the LINIEN (UART_INTEN[8]) = 1, an interrupt will be generated.
+ * |[2] |SLVAREN |LIN Slave Automatic Resynchronization Mode Enable Bit
+ * | | |0 = LIN automatic resynchronization Disabled.
+ * | | |1 = LIN automatic resynchronization Enabled.
+ * | | |Note1: This bit only valid when in LIN slave mode (SLVEN (UART_LINCTL[0]) = 1).
+ * | | |Note2: When operation in Automatic Resynchronization mode, the baud rate setting must be mode2 (BAUDM1 (UART_BAUD [29]) and BAUDM0 (UART_BAUD [28]) must be 1).
+ * | | |Note3: The control and interactions of this field are explained in 6.21.5.9(Slave mode with automatic resynchronization).
+ * |[3] |SLVDUEN |LIN Slave Divider Update Method Enable Bit
+ * | | |0 = UART_BAUD updated is written by software (if no automatic resynchronization update occurs at the same time).
+ * | | |1 = UART_BAUD is updated at the next received character.
+ * | | |User must set the bit before checksum reception.
+ * | | |Note1: This bit only valid when in LIN slave mode (SLVEN (UART_LINCTL[0]) = 1).
+ * | | |Note2: This bit used for LIN Slave Automatic Resynchronization mode.
+ * | | |(for Non-Automatic Resynchronization mode, this bit should be kept cleared).
+ * | | |Note3: The control and interactions of this field are explained in 6.21.5.9 (Slave mode with automatic resynchronization).
+ * |[4] |MUTE |LIN Mute Mode Enable Bit
+ * | | |0 = LIN mute mode Disabled.
+ * | | |1 = LIN mute mode Enabled.
+ * | | |Note: The exit from mute mode condition and each control and interactions of this field are explained in 6.21.5.9 (LIN slave mode).
+ * |[8] |SENDH |LIN TX Send Header Enable Bit
+ * | | |The LIN TX header can be "break field" or "break and sync field" or "break, sync and frame ID field", it is depend on setting HSEL (UART_LINCTL[23:22]).
+ * | | |0 = Send LIN TX header Disabled.
+ * | | |1 = Send LIN TX header Enabled.
+ * | | |Note1: These registers are shadow registers of SENDH (UART_ALTCTL [7]); user can read/write it by setting SENDH (UART_ALTCTL [7]) or SENDH (UART_LINCTL [8]).
+ * | | |Note2: When transmitter header field (it may be "break" or "break + sync" or "break + sync + frame ID" selected by HSEL (UART_LINCTL[23:22]) field) transfer operation finished, this bit will be cleared automatically.
+ * |[9] |IDPEN |LIN ID Parity Enable Bit
+ * | | |0 = LIN frame ID parity Disabled.
+ * | | |1 = LIN frame ID parity Enabled.
+ * | | |Note1: This bit can be used for LIN master to sending header field (SENDH (UART_LINCTL[8]) = 1 and HSEL (UART_LINCTL[23:22]) = 10) or be used for enable LIN slave received frame ID parity checked.
+ * | | |Note2: This bit is only use when the operation header transmitter is in HSEL (UART_LINCTL[23:22]) = 10
+ * |[10] |BRKDETEN |LIN Break Detection Enable Bit
+ * | | |When detect consecutive dominant greater than 11 bits, and are followed by a delimiter character, the BRKDETF (UART_LINSTS[8]) flag is set in UART_LINSTS register at the end of break field.
+ * | | |If the LINIEN (UART_INTEN [8])=1, an interrupt will be generated.
+ * | | |0 = LIN break detection Disabled .
+ * | | |1 = LIN break detection Enabled.
+ * |[11] |RXOFF |LIN Receiver Disable Bit
+ * | | |If the receiver is enabled (RXOFF (UART_LINCTL[11] ) = 0),
+ * | | |all received byte data will be accepted and stored in the RX-FIFO,
+ * | | |and if the receiver is disabled (RXOFF (UART_LINCTL[11]) = 1), all received byte data will be ignore.
+ * | | |0 = LIN receiver Enabled.
+ * | | |1 = LIN receiver Disabled.
+ * | | |Note: This bit is only valid when operating in LIN function mode (FUNCSEL (UART_FUNCSEL[1:0]) = 01).
+ * |[12] |BITERREN |Bit Error Detect Enable Bit
+ * | | |0 = Bit error detection function Disabled.
+ * | | |1 = Bit error detection Enabled.
+ * | | |Note: In LIN function mode, when occur bit error, the BITEF (UART_LINSTS[9]) flag will be asserted.
+ * | | |If the LINIEN (UART_INTEN[8]) = 1, an interrupt will be generated.
+ * |[19:16] |BRKFL |LIN Break Field Length
+ * | | |This field indicates a 4-bit LIN TX break field count.
+ * | | |Note1: These registers are shadow registers of BRKFL, User can read/write it by setting BRKFL (UART_ALTCTL[3:0]) or BRKFL (UART_LINCTL[19:16]).
+ * | | |Note2: This break field length is BRKFL + 1.
+ * | | |Note3: According to LIN spec, the reset value is 12 (break field length = 13).
+ * |[21:20] |BSL |LIN Break/Sync Delimiter Length
+ * | | |00 = The LIN break/sync delimiter length is 1-bit time.
+ * | | |01 = The LIN break/sync delimiter length is 2-bit time.
+ * | | |10 = The LIN break/sync delimiter length is 3-bit time.
+ * | | |11 = The LIN break/sync delimiter length is 4-bit time.
+ * | | |Note: This bit used for LIN master to sending header field.
+ * |[23:22] |HSEL |LIN Header Select
+ * | | |00 = The LIN header includes "break field".
+ * | | |01 = The LIN header includes "break field" and "sync field".
+ * | | |10 = The LIN header includes "break field", "sync field" and "frame ID field".
+ * | | |11 = Reserved.
+ * | | |Note: This bit is used to master mode for LIN to send header field (SENDH (UART_LINCTL [8]) = 1) or used to slave to indicates exit from mute mode condition (MUTE (UART_LINCTL[4]) = 1).
+ * |[31:24] |PID |LIN PID Bits
+ * | | |This field contains the LIN frame ID value when in LIN function mode, the frame ID parity can be generated by software or hardware depends on IDPEN (UART_LINCTL[9]) = 1.
+ * | | |If the parity generated by hardware, user fill ID0~ID5, (PID [29:24] )hardware will calculate P0 (PID[30]) and P1 (PID[31]), otherwise user must filled frame ID and parity in this field.
+ * | | |Note1: User can fill any 8-bit value to this field and the bit 24 indicates ID0 (LSB first).
+ * | | |Note2: This field can be used for LIN master mode or slave mode.
+ * @var UART_T::LINSTS
+ * Offset: 0x38 UART LIN Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |SLVHDETF |LIN Slave Header Detection Flag (Read Only)
+ * | | |This bit is set by hardware when a LIN header is detected in LIN slave mode and be cleared by writing 1 to it.
+ * | | |0 = LIN header not detected.
+ * | | |1 = LIN header detected (break + sync + frame ID).
+ * | | |Note1: This bit is read only, but it can be cleared by writing 1 to it.
+ * | | |Note2: This bit is only valid when in LIN slave mode (SLVEN (UART_LINCTL [0]) = 1) and enable LIN slave header detection function (SLVHDEN (UART_LINCTL [1])).
+ * | | |Note3: When enable ID parity check IDPEN (UART_LINCTL [9]), if hardware detect complete header ("break + sync + frame ID"), the SLVHDETF will be set whether the frame ID correct or not.
+ * |[1] |SLVHEF |LIN Slave Header Error Flag (Read Only)
+ * | | |This bit is set by hardware when a LIN header error is detected in LIN slave mode and be cleared by writing 1 to it.
+ * | | |The header errors include "break delimiter is too short (less than 0.5 bit time)", "frame error in sync field or Identifier field", "sync field data is not 0x55 in Non-Automatic Resynchronization mode", "sync field deviation error with Automatic Resynchronization mode", "sync field measure time-out with Automatic Resynchronization mode" and "LIN header reception time-out".
+ * | | |0 = LIN header error not detected.
+ * | | |1 = LIN header error detected.
+ * | | |Note1: This bit is read only, but it can be cleared by writing 1 to it.
+ * | | |Note2: This bit is only valid when UART is operated in LIN slave mode (SLVEN (UART_LINCTL [0]) = 1) and enables LIN slave header detection function (SLVHDEN (UART_LINCTL [1])).
+ * |[2] |SLVIDPEF |LIN Slave ID Parity Error Flag
+ * | | |This bit is set by hardware when receipted frame ID parity is not correct.
+ * | | |0 = No active.
+ * | | |1 = Receipted frame ID parity is not correct.
+ * | | |Note1: This bit is read only, but it can be cleared by writing 1 to it.
+ * | | |Note2: This bit is only valid when in LIN slave mode (SLVEN (UART_LINCTL [0])= 1) and enable LIN frame ID parity check function IDPEN (UART_LINCTL [9]).
+ * |[3] |SLVSYNCF |LIN Slave Sync Field (Read Only)
+ * | | |This bit indicates that the LIN sync field is being analyzed in Automatic Resynchronization mode.
+ * | | |When the receiver header have some error been detect, user must reset the internal circuit to re-search new frame header by writing 1 to this bit.
+ * | | |0 = The current character is not at LIN sync state.
+ * | | |1 = The current character is at LIN sync state.
+ * | | |Note1: This bit is only valid when in LIN Slave mode (SLVEN(UART_LINCTL[0]) = 1).
+ * | | |Note2: This bit is read only, but it can be cleared by writing 1 to it.
+ * | | |Note3: When writing 1 to it, hardware will reload the initial baud rate and re-search a new frame header.
+ * |[8] |BRKDETF |LIN Break Detection Flag (Read Only)
+ * | | |This bit is set by hardware when a break is detected and be cleared by writing 1 to it through software.
+ * | | |0 = LIN break not detected.
+ * | | |1 = LIN break detected.
+ * | | |Note1: This bit is read only, but it can be cleared by writing 1 to it.
+ * | | |Note2: This bit is only valid when LIN break detection function is enabled (BRKDETEN (UART_LINCTL[10]) =1).
+ * |[9] |BITEF |Bit Error Detect Status Flag (Read Only)
+ * | | |At TX transfer state, hardware will monitoring the bus state, if the input pin (SIN) state not equals to the output pin (SOUT) state, BITEF (UART_LINSTS[9]) will be set.
+ * | | |When occur bit error, if the LINIEN (UART_INTEN[8]) = 1, an interrupt will be generated.
+ * | | |Note1: This bit is read only, but it can be cleared by writing 1 to it.
+ * | | |Note2: This bit is only valid when enable bit error detection function (BITERREN (UART_LINCTL [12]) = 1).
+ */
+
+ __IO uint32_t DAT; /* Offset: 0x00 UART Receive/Transmit Buffer Register */
+ __IO uint32_t INTEN; /* Offset: 0x04 UART Interrupt Enable Register */
+ __IO uint32_t FIFO; /* Offset: 0x08 UART FIFO Control Register */
+ __IO uint32_t LINE; /* Offset: 0x0C UART Line Control Register */
+ __IO uint32_t MODEM; /* Offset: 0x10 UART Modem Control Register */
+ __IO uint32_t MODEMSTS; /* Offset: 0x14 UART Modem Status Register */
+ __IO uint32_t FIFOSTS; /* Offset: 0x18 UART FIFO Status Register */
+ __IO uint32_t INTSTS; /* Offset: 0x1C UART Interrupt Status Register */
+ __IO uint32_t TOUT; /* Offset: 0x20 UART Time-out Register */
+ __IO uint32_t BAUD; /* Offset: 0x24 UART Baud Rate Divisor Register */
+ __IO uint32_t IRDA; /* Offset: 0x28 UART IrDA Control Register */
+ __IO uint32_t ALTCTL; /* Offset: 0x2C UART Alternate Control/Status Register */
+ __IO uint32_t FUNCSEL; /* Offset: 0x30 UART Function Select Register */
+ __IO uint32_t LINCTL; /* Offset: 0x34 UART LIN Control Register */
+ __IO uint32_t LINSTS; /* Offset: 0x38 UART LIN Status Register */
+
+} UART_T;
+
+
+
+/**
+ @addtogroup UART_CONST UART Bit Field Definition
+ Constant Definitions for UART Controller
+@{ */
+
+#define UART_DAT_DAT_Pos (0) /*!< UART_T::DAT: DAT Position */
+#define UART_DAT_DAT_Msk (0xfful << UART_DAT_DAT_Pos) /*!< UART_T::DAT: DAT Mask */
+
+#define UART_INTEN_RDAIEN_Pos (0) /*!< UART_T::INTEN: RDAIEN Position */
+#define UART_INTEN_RDAIEN_Msk (0x1ul << UART_INTEN_RDAIEN_Pos) /*!< UART_T::INTEN: RDAIEN Mask */
+
+#define UART_INTEN_THREIEN_Pos (1) /*!< UART_T::INTEN: THREIEN Position */
+#define UART_INTEN_THREIEN_Msk (0x1ul << UART_INTEN_THREIEN_Pos) /*!< UART_T::INTEN: THREIEN Mask */
+
+#define UART_INTEN_RLSIEN_Pos (2) /*!< UART_T::INTEN: RLSIEN Position */
+#define UART_INTEN_RLSIEN_Msk (0x1ul << UART_INTEN_RLSIEN_Pos) /*!< UART_T::INTEN: RLSIEN Mask */
+
+#define UART_INTEN_MODEMIEN_Pos (3) /*!< UART_T::INTEN: MODEMIEN Position */
+#define UART_INTEN_MODEMIEN_Msk (0x1ul << UART_INTEN_MODEMIEN_Pos) /*!< UART_T::INTEN: MODEMIEN Mask */
+
+#define UART_INTEN_RXTOIEN_Pos (4) /*!< UART_T::INTEN: RXTOIEN Position */
+#define UART_INTEN_RXTOIEN_Msk (0x1ul << UART_INTEN_RXTOIEN_Pos) /*!< UART_T::INTEN: RXTOIEN Mask */
+
+#define UART_INTEN_BUFERRIEN_Pos (5) /*!< UART_T::INTEN: BUFERRIEN Position */
+#define UART_INTEN_BUFERRIEN_Msk (0x1ul << UART_INTEN_BUFERRIEN_Pos) /*!< UART_T::INTEN: BUFERRIEN Mask */
+
+#define UART_INTEN_LINIEN_Pos (8) /*!< UART_T::INTEN: LINIEN Position */
+#define UART_INTEN_LINIEN_Msk (0x1ul << UART_INTEN_LINIEN_Pos) /*!< UART_T::INTEN: LINIEN Mask */
+
+#define UART_INTEN_WKCTSIEN_Pos (9) /*!< UART_T::INTEN: WKCTSIEN Position */
+#define UART_INTEN_WKCTSIEN_Msk (0x1ul << UART_INTEN_WKCTSIEN_Pos) /*!< UART_T::INTEN: WKCTSIEN Mask */
+
+#define UART_INTEN_WKDATIEN_Pos (10) /*!< UART_T::INTEN: WKDATIEN Position */
+#define UART_INTEN_WKDATIEN_Msk (0x1ul << UART_INTEN_WKDATIEN_Pos) /*!< UART_T::INTEN: WKDATIEN Mask */
+
+#define UART_INTEN_TOCNTEN_Pos (11) /*!< UART_T::INTEN: TOCNTEN Position */
+#define UART_INTEN_TOCNTEN_Msk (0x1ul << UART_INTEN_TOCNTEN_Pos) /*!< UART_T::INTEN: TOCNTEN Mask */
+
+#define UART_INTEN_ATORTSEN_Pos (12) /*!< UART_T::INTEN: ATORTSEN Position */
+#define UART_INTEN_ATORTSEN_Msk (0x1ul << UART_INTEN_ATORTSEN_Pos) /*!< UART_T::INTEN: ATORTSEN Mask */
+
+#define UART_INTEN_ATOCTSEN_Pos (13) /*!< UART_T::INTEN: ATOCTSEN Position */
+#define UART_INTEN_ATOCTSEN_Msk (0x1ul << UART_INTEN_ATOCTSEN_Pos) /*!< UART_T::INTEN: ATOCTSEN Mask */
+
+#define UART_INTEN_TXPDMAEN_Pos (14) /*!< UART_T::INTEN: TXPDMAEN Position */
+#define UART_INTEN_TXPDMAEN_Msk (0x1ul << UART_INTEN_TXPDMAEN_Pos) /*!< UART_T::INTEN: TXPDMAEN Mask */
+
+#define UART_INTEN_RXPDMAEN_Pos (15) /*!< UART_T::INTEN: RXPDMAEN Position */
+#define UART_INTEN_RXPDMAEN_Msk (0x1ul << UART_INTEN_RXPDMAEN_Pos) /*!< UART_T::INTEN: RXPDMAEN Mask */
+
+#define UART_INTEN_ABRIEN_Pos (18) /*!< UART_T::INTEN: ABRIEN Position */
+#define UART_INTEN_ABRIEN_Msk (0x1ul << UART_INTEN_ABRIEN_Pos) /*!< UART_T::INTEN: ABRIEN Mask */
+
+#define UART_FIFO_RXRST_Pos (1) /*!< UART_T::FIFO: RXRST Position */
+#define UART_FIFO_RXRST_Msk (0x1ul << UART_FIFO_RXRST_Pos) /*!< UART_T::FIFO: RXRST Mask */
+
+#define UART_FIFO_TXRST_Pos (2) /*!< UART_T::FIFO: TXRST Position */
+#define UART_FIFO_TXRST_Msk (0x1ul << UART_FIFO_TXRST_Pos) /*!< UART_T::FIFO: TXRST Mask */
+
+#define UART_FIFO_RFITL_Pos (4) /*!< UART_T::FIFO: RFITL Position */
+#define UART_FIFO_RFITL_Msk (0xful << UART_FIFO_RFITL_Pos) /*!< UART_T::FIFO: RFITL Mask */
+
+#define UART_FIFO_RXOFF_Pos (8) /*!< UART_T::FIFO: RXOFF Position */
+#define UART_FIFO_RXOFF_Msk (0x1ul << UART_FIFO_RXOFF_Pos) /*!< UART_T::FIFO: RXOFF Mask */
+
+#define UART_FIFO_RTSTRGLV_Pos (16) /*!< UART_T::FIFO: RTSTRGLV Position */
+#define UART_FIFO_RTSTRGLV_Msk (0xful << UART_FIFO_RTSTRGLV_Pos) /*!< UART_T::FIFO: RTSTRGLV Mask */
+
+#define UART_LINE_WLS_Pos (0) /*!< UART_T::LINE: WLS Position */
+#define UART_LINE_WLS_Msk (0x3ul << UART_LINE_WLS_Pos) /*!< UART_T::LINE: WLS Mask */
+
+#define UART_LINE_NSB_Pos (2) /*!< UART_T::LINE: NSB Position */
+#define UART_LINE_NSB_Msk (0x1ul << UART_LINE_NSB_Pos) /*!< UART_T::LINE: NSB Mask */
+
+#define UART_LINE_PBE_Pos (3) /*!< UART_T::LINE: PBE Position */
+#define UART_LINE_PBE_Msk (0x1ul << UART_LINE_PBE_Pos) /*!< UART_T::LINE: PBE Mask */
+
+#define UART_LINE_EPE_Pos (4) /*!< UART_T::LINE: EPE Position */
+#define UART_LINE_EPE_Msk (0x1ul << UART_LINE_EPE_Pos) /*!< UART_T::LINE: EPE Mask */
+
+#define UART_LINE_SPE_Pos (5) /*!< UART_T::LINE: SPE Position */
+#define UART_LINE_SPE_Msk (0x1ul << UART_LINE_SPE_Pos) /*!< UART_T::LINE: SPE Mask */
+
+#define UART_LINE_BCB_Pos (6) /*!< UART_T::LINE: BCB Position */
+#define UART_LINE_BCB_Msk (0x1ul << UART_LINE_BCB_Pos) /*!< UART_T::LINE: BCB Mask */
+
+#define UART_MODEM_RTS_Pos (1) /*!< UART_T::MODEM: RTS Position */
+#define UART_MODEM_RTS_Msk (0x1ul << UART_MODEM_RTS_Pos) /*!< UART_T::MODEM: RTS Mask */
+
+#define UART_MODEM_RTSACTLV_Pos (9) /*!< UART_T::MODEM: RTSACTLV Position */
+#define UART_MODEM_RTSACTLV_Msk (0x1ul << UART_MODEM_RTSACTLV_Pos) /*!< UART_T::MODEM: RTSACTLV Mask */
+
+#define UART_MODEM_RTSSTS_Pos (13) /*!< UART_T::MODEM: RTSSTS Position */
+#define UART_MODEM_RTSSTS_Msk (0x1ul << UART_MODEM_RTSSTS_Pos) /*!< UART_T::MODEM: RTSSTS Mask */
+
+#define UART_MODEMSTS_CTSDETF_Pos (0) /*!< UART_T::MODEMSTS: CTSDETF Position */
+#define UART_MODEMSTS_CTSDETF_Msk (0x1ul << UART_MODEMSTS_CTSDETF_Pos) /*!< UART_T::MODEMSTS: CTSDETF Mask */
+
+#define UART_MODEMSTS_CTSSTS_Pos (4) /*!< UART_T::MODEMSTS: CTSSTS Position */
+#define UART_MODEMSTS_CTSSTS_Msk (0x1ul << UART_MODEMSTS_CTSSTS_Pos) /*!< UART_T::MODEMSTS: CTSSTS Mask */
+
+#define UART_MODEMSTS_CTSACTLV_Pos (8) /*!< UART_T::MODEMSTS: CTSACTLV Position */
+#define UART_MODEMSTS_CTSACTLV_Msk (0x1ul << UART_MODEMSTS_CTSACTLV_Pos) /*!< UART_T::MODEMSTS: CTSACTLV Mask */
+
+#define UART_FIFOSTS_RXOVIF_Pos (0) /*!< UART_T::FIFOSTS: RXOVIF Position */
+#define UART_FIFOSTS_RXOVIF_Msk (0x1ul << UART_FIFOSTS_RXOVIF_Pos) /*!< UART_T::FIFOSTS: RXOVIF Mask */
+
+#define UART_FIFOSTS_ABRDIF_Pos (1) /*!< UART_T::FIFOSTS: ABRDIF Position */
+#define UART_FIFOSTS_ABRDIF_Msk (0x1ul << UART_FIFOSTS_ABRDIF_Pos) /*!< UART_T::FIFOSTS: ABRDIF Mask */
+
+#define UART_FIFOSTS_ABRDTOIF_Pos (2) /*!< UART_T::FIFOSTS: ABRDTOIF Position */
+#define UART_FIFOSTS_ABRDTOIF_Msk (0x1ul << UART_FIFOSTS_ABRDTOIF_Pos) /*!< UART_T::FIFOSTS: ABRDTOIF Mask */
+
+#define UART_FIFOSTS_ADDRDETF_Pos (3) /*!< UART_T::FIFOSTS: ADDRDETF Position */
+#define UART_FIFOSTS_ADDRDETF_Msk (0x1ul << UART_FIFOSTS_ADDRDETF_Pos) /*!< UART_T::FIFOSTS: ADDRDETF Mask */
+
+#define UART_FIFOSTS_PEF_Pos (4) /*!< UART_T::FIFOSTS: PEF Position */
+#define UART_FIFOSTS_PEF_Msk (0x1ul << UART_FIFOSTS_PEF_Pos) /*!< UART_T::FIFOSTS: PEF Mask */
+
+#define UART_FIFOSTS_FEF_Pos (5) /*!< UART_T::FIFOSTS: FEF Position */
+#define UART_FIFOSTS_FEF_Msk (0x1ul << UART_FIFOSTS_FEF_Pos) /*!< UART_T::FIFOSTS: FEF Mask */
+
+#define UART_FIFOSTS_BIF_Pos (6) /*!< UART_T::FIFOSTS: BIF Position */
+#define UART_FIFOSTS_BIF_Msk (0x1ul << UART_FIFOSTS_BIF_Pos) /*!< UART_T::FIFOSTS: BIF Mask */
+
+#define UART_FIFOSTS_RXPTR_Pos (8) /*!< UART_T::FIFOSTS: RXPTR Position */
+#define UART_FIFOSTS_RXPTR_Msk (0x3ful << UART_FIFOSTS_RXPTR_Pos) /*!< UART_T::FIFOSTS: RXPTR Mask */
+
+#define UART_FIFOSTS_RXEMPTY_Pos (14) /*!< UART_T::FIFOSTS: RXEMPTY Position */
+#define UART_FIFOSTS_RXEMPTY_Msk (0x1ul << UART_FIFOSTS_RXEMPTY_Pos) /*!< UART_T::FIFOSTS: RXEMPTY Mask */
+
+#define UART_FIFOSTS_RXFULL_Pos (15) /*!< UART_T::FIFOSTS: RXFULL Position */
+#define UART_FIFOSTS_RXFULL_Msk (0x1ul << UART_FIFOSTS_RXFULL_Pos) /*!< UART_T::FIFOSTS: RXFULL Mask */
+
+#define UART_FIFOSTS_TXPTR_Pos (16) /*!< UART_T::FIFOSTS: TXPTR Position */
+#define UART_FIFOSTS_TXPTR_Msk (0x3ful << UART_FIFOSTS_TXPTR_Pos) /*!< UART_T::FIFOSTS: TXPTR Mask */
+
+#define UART_FIFOSTS_TXEMPTY_Pos (22) /*!< UART_T::FIFOSTS: TXEMPTY Position */
+#define UART_FIFOSTS_TXEMPTY_Msk (0x1ul << UART_FIFOSTS_TXEMPTY_Pos) /*!< UART_T::FIFOSTS: TXEMPTY Mask */
+
+#define UART_FIFOSTS_TXFULL_Pos (23) /*!< UART_T::FIFOSTS: TXFULL Position */
+#define UART_FIFOSTS_TXFULL_Msk (0x1ul << UART_FIFOSTS_TXFULL_Pos) /*!< UART_T::FIFOSTS: TXFULL Mask */
+
+#define UART_FIFOSTS_TXOVIF_Pos (24) /*!< UART_T::FIFOSTS: TXOVIF Position */
+#define UART_FIFOSTS_TXOVIF_Msk (0x1ul << UART_FIFOSTS_TXOVIF_Pos) /*!< UART_T::FIFOSTS: TXOVIF Mask */
+
+#define UART_FIFOSTS_TXEMPTYF_Pos (28) /*!< UART_T::FIFOSTS: TXEMPTYF Position */
+#define UART_FIFOSTS_TXEMPTYF_Msk (0x1ul << UART_FIFOSTS_TXEMPTYF_Pos) /*!< UART_T::FIFOSTS: TXEMPTYF Mask */
+
+#define UART_INTSTS_RDAIF_Pos (0) /*!< UART_T::INTSTS: RDAIF Position */
+#define UART_INTSTS_RDAIF_Msk (0x1ul << UART_INTSTS_RDAIF_Pos) /*!< UART_T::INTSTS: RDAIF Mask */
+
+#define UART_INTSTS_THREIF_Pos (1) /*!< UART_T::INTSTS: THREIF Position */
+#define UART_INTSTS_THREIF_Msk (0x1ul << UART_INTSTS_THREIF_Pos) /*!< UART_T::INTSTS: THREIF Mask */
+
+#define UART_INTSTS_RLSIF_Pos (2) /*!< UART_T::INTSTS: RLSIF Position */
+#define UART_INTSTS_RLSIF_Msk (0x1ul << UART_INTSTS_RLSIF_Pos) /*!< UART_T::INTSTS: RLSIF Mask */
+
+#define UART_INTSTS_MODEMIF_Pos (3) /*!< UART_T::INTSTS: MODEMIF Position */
+#define UART_INTSTS_MODEMIF_Msk (0x1ul << UART_INTSTS_MODEMIF_Pos) /*!< UART_T::INTSTS: MODEMIF Mask */
+
+#define UART_INTSTS_RXTOIF_Pos (4) /*!< UART_T::INTSTS: RXTOIF Position */
+#define UART_INTSTS_RXTOIF_Msk (0x1ul << UART_INTSTS_RXTOIF_Pos) /*!< UART_T::INTSTS: RXTOIF Mask */
+
+#define UART_INTSTS_BUFERRIF_Pos (5) /*!< UART_T::INTSTS: BUFERRIF Position */
+#define UART_INTSTS_BUFERRIF_Msk (0x1ul << UART_INTSTS_BUFERRIF_Pos) /*!< UART_T::INTSTS: BUFERRIF Mask */
+
+#define UART_INTSTS_WKIF_Pos (6) /*!< UART_T::INTSTS: WKIF Position */
+#define UART_INTSTS_WKIF_Msk (0x1ul << UART_INTSTS_WKIF_Pos) /*!< UART_T::INTSTS: WKIF Mask */
+
+#define UART_INTSTS_LINIF_Pos (7) /*!< UART_T::INTSTS: LINIF Position */
+#define UART_INTSTS_LINIF_Msk (0x1ul << UART_INTSTS_LINIF_Pos) /*!< UART_T::INTSTS: LINIF Mask */
+
+#define UART_INTSTS_RDAINT_Pos (8) /*!< UART_T::INTSTS: RDAINT Position */
+#define UART_INTSTS_RDAINT_Msk (0x1ul << UART_INTSTS_RDAINT_Pos) /*!< UART_T::INTSTS: RDAINT Mask */
+
+#define UART_INTSTS_THREINT_Pos (9) /*!< UART_T::INTSTS: THREINT Position */
+#define UART_INTSTS_THREINT_Msk (0x1ul << UART_INTSTS_THREINT_Pos) /*!< UART_T::INTSTS: THREINT Mask */
+
+#define UART_INTSTS_RLSINT_Pos (10) /*!< UART_T::INTSTS: RLSINT Position */
+#define UART_INTSTS_RLSINT_Msk (0x1ul << UART_INTSTS_RLSINT_Pos) /*!< UART_T::INTSTS: RLSINT Mask */
+
+#define UART_INTSTS_MODEMINT_Pos (11) /*!< UART_T::INTSTS: MODEMINT Position */
+#define UART_INTSTS_MODEMINT_Msk (0x1ul << UART_INTSTS_MODEMINT_Pos) /*!< UART_T::INTSTS: MODEMINT Mask */
+
+#define UART_INTSTS_RXTOINT_Pos (12) /*!< UART_T::INTSTS: RXTOINT Position */
+#define UART_INTSTS_RXTOINT_Msk (0x1ul << UART_INTSTS_RXTOINT_Pos) /*!< UART_T::INTSTS: RXTOINT Mask */
+
+#define UART_INTSTS_BUFERRINT_Pos (13) /*!< UART_T::INTSTS: BUFERRINT Position */
+#define UART_INTSTS_BUFERRINT_Msk (0x1ul << UART_INTSTS_BUFERRINT_Pos) /*!< UART_T::INTSTS: BUFERRINT Mask */
+
+#define UART_INTSTS_LININT_Pos (15) /*!< UART_T::INTSTS: LININT Position */
+#define UART_INTSTS_LININT_Msk (0x1ul << UART_INTSTS_LININT_Pos) /*!< UART_T::INTSTS: LININT Mask */
+
+#define UART_INTSTS_CTSWKIF_Pos (16) /*!< UART_T::INTSTS: CTSWKIF Position */
+#define UART_INTSTS_CTSWKIF_Msk (0x1ul << UART_INTSTS_CTSWKIF_Pos) /*!< UART_T::INTSTS: CTSWKIF Mask */
+
+#define UART_INTSTS_DATWKIF_Pos (17) /*!< UART_T::INTSTS: DATWKIF Position */
+#define UART_INTSTS_DATWKIF_Msk (0x1ul << UART_INTSTS_DATWKIF_Pos) /*!< UART_T::INTSTS: DATWKIF Mask */
+
+#define UART_INTSTS_HWRLSIF_Pos (18) /*!< UART_T::INTSTS: HWRLSIF Position */
+#define UART_INTSTS_HWRLSIF_Msk (0x1ul << UART_INTSTS_HWRLSIF_Pos) /*!< UART_T::INTSTS: HWRLSIF Mask */
+
+#define UART_INTSTS_HWMODIF_Pos (19) /*!< UART_T::INTSTS: HWMODIF Position */
+#define UART_INTSTS_HWMODIF_Msk (0x1ul << UART_INTSTS_HWMODIF_Pos) /*!< UART_T::INTSTS: HWMODIF Mask */
+
+#define UART_INTSTS_HWTOIF_Pos (20) /*!< UART_T::INTSTS: HWTOIF Position */
+#define UART_INTSTS_HWTOIF_Msk (0x1ul << UART_INTSTS_HWTOIF_Pos) /*!< UART_T::INTSTS: HWTOIF Mask */
+
+#define UART_INTSTS_HWBUFEIF_Pos (21) /*!< UART_T::INTSTS: HWBUFEIF Position */
+#define UART_INTSTS_HWBUFEIF_Msk (0x1ul << UART_INTSTS_HWBUFEIF_Pos) /*!< UART_T::INTSTS: HWBUFEIF Mask */
+
+#define UART_INTSTS_HWRLSINT_Pos (26) /*!< UART_T::INTSTS: HWRLSINT Position */
+#define UART_INTSTS_HWRLSINT_Msk (0x1ul << UART_INTSTS_HWRLSINT_Pos) /*!< UART_T::INTSTS: HWRLSINT Mask */
+
+#define UART_INTSTS_HWMODINT_Pos (27) /*!< UART_T::INTSTS: HWMODINT Position */
+#define UART_INTSTS_HWMODINT_Msk (0x1ul << UART_INTSTS_HWMODINT_Pos) /*!< UART_T::INTSTS: HWMODINT Mask */
+
+#define UART_INTSTS_HWTOINT_Pos (28) /*!< UART_T::INTSTS: HWTOINT Position */
+#define UART_INTSTS_HWTOINT_Msk (0x1ul << UART_INTSTS_HWTOINT_Pos) /*!< UART_T::INTSTS: HWTOINT Mask */
+
+#define UART_INTSTS_HWBUFEINT_Pos (29) /*!< UART_T::INTSTS: HWBUFEINT Position */
+#define UART_INTSTS_HWBUFEINT_Msk (0x1ul << UART_INTSTS_HWBUFEINT_Pos) /*!< UART_T::INTSTS: HWBUFEINT Mask */
+
+#define UART_TOUT_TOIC_Pos (0) /*!< UART_T::TOUT: TOIC Position */
+#define UART_TOUT_TOIC_Msk (0xfful << UART_TOUT_TOIC_Pos) /*!< UART_T::TOUT: TOIC Mask */
+
+#define UART_TOUT_DLY_Pos (8) /*!< UART_T::TOUT: DLY Position */
+#define UART_TOUT_DLY_Msk (0xfful << UART_TOUT_DLY_Pos) /*!< UART_T::TOUT: DLY Mask */
+
+#define UART_BAUD_BRD_Pos (0) /*!< UART_T::BAUD: BRD Position */
+#define UART_BAUD_BRD_Msk (0xfffful << UART_BAUD_BRD_Pos) /*!< UART_T::BAUD: BRD Mask */
+
+#define UART_BAUD_EDIVM1_Pos (24) /*!< UART_T::BAUD: EDIVM1 Position */
+#define UART_BAUD_EDIVM1_Msk (0xful << UART_BAUD_EDIVM1_Pos) /*!< UART_T::BAUD: EDIVM1 Mask */
+
+#define UART_BAUD_BAUDM0_Pos (28) /*!< UART_T::BAUD: BAUDM0 Position */
+#define UART_BAUD_BAUDM0_Msk (0x1ul << UART_BAUD_BAUDM0_Pos) /*!< UART_T::BAUD: BAUDM0 Mask */
+
+#define UART_BAUD_BAUDM1_Pos (29) /*!< UART_T::BAUD: BAUDM1 Position */
+#define UART_BAUD_BAUDM1_Msk (0x1ul << UART_BAUD_BAUDM1_Pos) /*!< UART_T::BAUD: BAUDM1 Mask */
+
+#define UART_IRDA_TXEN_Pos (1) /*!< UART_T::IRDA: TXEN Position */
+#define UART_IRDA_TXEN_Msk (0x1ul << UART_IRDA_TXEN_Pos) /*!< UART_T::IRDA: TXEN Mask */
+
+#define UART_IRDA_TXINV_Pos (5) /*!< UART_T::IRDA: TXINV Position */
+#define UART_IRDA_TXINV_Msk (0x1ul << UART_IRDA_TXINV_Pos) /*!< UART_T::IRDA: TXINV Mask */
+
+#define UART_IRDA_RXINV_Pos (6) /*!< UART_T::IRDA: RXINV Position */
+#define UART_IRDA_RXINV_Msk (0x1ul << UART_IRDA_RXINV_Pos) /*!< UART_T::IRDA: RXINV Mask */
+
+#define UART_ALTCTL_BRKFL_Pos (0) /*!< UART_T::ALTCTL: BRKFL Position */
+#define UART_ALTCTL_BRKFL_Msk (0xful << UART_ALTCTL_BRKFL_Pos) /*!< UART_T::ALTCTL: BRKFL Mask */
+
+#define UART_ALTCTL_LINRXEN_Pos (6) /*!< UART_T::ALTCTL: LINRXEN Position */
+#define UART_ALTCTL_LINRXEN_Msk (0x1ul << UART_ALTCTL_LINRXEN_Pos) /*!< UART_T::ALTCTL: LINRXEN Mask */
+
+#define UART_ALTCTL_LINTXEN_Pos (7) /*!< UART_T::ALTCTL: LINTXEN Position */
+#define UART_ALTCTL_LINTXEN_Msk (0x1ul << UART_ALTCTL_LINTXEN_Pos) /*!< UART_T::ALTCTL: LINTXEN Mask */
+
+#define UART_ALTCTL_RS485NMM_Pos (8) /*!< UART_T::ALTCTL: RS485NMM Position */
+#define UART_ALTCTL_RS485NMM_Msk (0x1ul << UART_ALTCTL_RS485NMM_Pos) /*!< UART_T::ALTCTL: RS485NMM Mask */
+
+#define UART_ALTCTL_RS485AAD_Pos (9) /*!< UART_T::ALTCTL: RS485AAD Position */
+#define UART_ALTCTL_RS485AAD_Msk (0x1ul << UART_ALTCTL_RS485AAD_Pos) /*!< UART_T::ALTCTL: RS485AAD Mask */
+
+#define UART_ALTCTL_RS485AUD_Pos (10) /*!< UART_T::ALTCTL: RS485AUD Position */
+#define UART_ALTCTL_RS485AUD_Msk (0x1ul << UART_ALTCTL_RS485AUD_Pos) /*!< UART_T::ALTCTL: RS485AUD Mask */
+
+#define UART_ALTCTL_ADDRDEN_Pos (15) /*!< UART_T::ALTCTL: ADDRDEN Position */
+#define UART_ALTCTL_ADDRDEN_Msk (0x1ul << UART_ALTCTL_ADDRDEN_Pos) /*!< UART_T::ALTCTL: ADDRDEN Mask */
+
+#define UART_ALTCTL_ABRIF_Pos (17) /*!< UART_T::ALTCTL: ABRIF Position */
+#define UART_ALTCTL_ABRIF_Msk (0x1ul << UART_ALTCTL_ABRIF_Pos) /*!< UART_T::ALTCTL: ABRIF Mask */
+
+#define UART_ALTCTL_ABRDEN_Pos (18) /*!< UART_T::ALTCTL: ABRDEN Position */
+#define UART_ALTCTL_ABRDEN_Msk (0x1ul << UART_ALTCTL_ABRDEN_Pos) /*!< UART_T::ALTCTL: ABRDEN Mask */
+
+#define UART_ALTCTL_ABRDBITS_Pos (19) /*!< UART_T::ALTCTL: ABRDBITS Position */
+#define UART_ALTCTL_ABRDBITS_Msk (0x3ul << UART_ALTCTL_ABRDBITS_Pos) /*!< UART_T::ALTCTL: ABRDBITS Mask */
+
+#define UART_ALTCTL_ADDRMV_Pos (24) /*!< UART_T::ALTCTL: ADDRMV Position */
+#define UART_ALTCTL_ADDRMV_Msk (0xfful << UART_ALTCTL_ADDRMV_Pos) /*!< UART_T::ALTCTL: ADDRMV Mask */
+
+#define UART_FUNCSEL_FUNCSEL_Pos (0) /*!< UART_T::FUNCSEL: FUNCSEL Position */
+#define UART_FUNCSEL_FUNCSEL_Msk (0x3ul << UART_FUNCSEL_FUNCSEL_Pos) /*!< UART_T::FUNCSEL: FUNCSEL Mask */
+
+#define UART_LINCTL_SLVEN_Pos (0) /*!< UART_T::LINCTL: SLVEN Position */
+#define UART_LINCTL_SLVEN_Msk (0x1ul << UART_LINCTL_SLVEN_Pos) /*!< UART_T::LINCTL: SLVEN Mask */
+
+#define UART_LINCTL_SLVHDEN_Pos (1) /*!< UART_T::LINCTL: SLVHDEN Position */
+#define UART_LINCTL_SLVHDEN_Msk (0x1ul << UART_LINCTL_SLVHDEN_Pos) /*!< UART_T::LINCTL: SLVHDEN Mask */
+
+#define UART_LINCTL_SLVAREN_Pos (2) /*!< UART_T::LINCTL: SLVAREN Position */
+#define UART_LINCTL_SLVAREN_Msk (0x1ul << UART_LINCTL_SLVAREN_Pos) /*!< UART_T::LINCTL: SLVAREN Mask */
+
+#define UART_LINCTL_SLVDUEN_Pos (3) /*!< UART_T::LINCTL: SLVDUEN Position */
+#define UART_LINCTL_SLVDUEN_Msk (0x1ul << UART_LINCTL_SLVDUEN_Pos) /*!< UART_T::LINCTL: SLVDUEN Mask */
+
+#define UART_LINCTL_MUTE_Pos (4) /*!< UART_T::LINCTL: MUTE Position */
+#define UART_LINCTL_MUTE_Msk (0x1ul << UART_LINCTL_MUTE_Pos) /*!< UART_T::LINCTL: MUTE Mask */
+
+#define UART_LINCTL_SENDH_Pos (8) /*!< UART_T::LINCTL: SENDH Position */
+#define UART_LINCTL_SENDH_Msk (0x1ul << UART_LINCTL_SENDH_Pos) /*!< UART_T::LINCTL: SENDH Mask */
+
+#define UART_LINCTL_IDPEN_Pos (9) /*!< UART_T::LINCTL: IDPEN Position */
+#define UART_LINCTL_IDPEN_Msk (0x1ul << UART_LINCTL_IDPEN_Pos) /*!< UART_T::LINCTL: IDPEN Mask */
+
+#define UART_LINCTL_BRKDETEN_Pos (10) /*!< UART_T::LINCTL: BRKDETEN Position */
+#define UART_LINCTL_BRKDETEN_Msk (0x1ul << UART_LINCTL_BRKDETEN_Pos) /*!< UART_T::LINCTL: BRKDETEN Mask */
+
+#define UART_LINCTL_RXOFF_Pos (11) /*!< UART_T::LINCTL: RXOFF Position */
+#define UART_LINCTL_RXOFF_Msk (0x1ul << UART_LINCTL_RXOFF_Pos) /*!< UART_T::LINCTL: RXOFF Mask */
+
+#define UART_LINCTL_BITERREN_Pos (12) /*!< UART_T::LINCTL: BITERREN Position */
+#define UART_LINCTL_BITERREN_Msk (0x1ul << UART_LINCTL_BITERREN_Pos) /*!< UART_T::LINCTL: BITERREN Mask */
+
+#define UART_LINCTL_BRKFL_Pos (16) /*!< UART_T::LINCTL: BRKFL Position */
+#define UART_LINCTL_BRKFL_Msk (0xful << UART_LINCTL_BRKFL_Pos) /*!< UART_T::LINCTL: BRKFL Mask */
+
+#define UART_LINCTL_BSL_Pos (20) /*!< UART_T::LINCTL: BSL Position */
+#define UART_LINCTL_BSL_Msk (0x3ul << UART_LINCTL_BSL_Pos) /*!< UART_T::LINCTL: BSL Mask */
+
+#define UART_LINCTL_HSEL_Pos (22) /*!< UART_T::LINCTL: HSEL Position */
+#define UART_LINCTL_HSEL_Msk (0x3ul << UART_LINCTL_HSEL_Pos) /*!< UART_T::LINCTL: HSEL Mask */
+
+#define UART_LINCTL_PID_Pos (24) /*!< UART_T::LINCTL: PID Position */
+#define UART_LINCTL_PID_Msk (0xfful << UART_LINCTL_PID_Pos) /*!< UART_T::LINCTL: PID Mask */
+
+#define UART_LINSTS_SLVHDETF_Pos (0) /*!< UART_T::LINSTS: SLVHDETF Position */
+#define UART_LINSTS_SLVHDETF_Msk (0x1ul << UART_LINSTS_SLVHDETF_Pos) /*!< UART_T::LINSTS: SLVHDETF Mask */
+
+#define UART_LINSTS_SLVHEF_Pos (1) /*!< UART_T::LINSTS: SLVHEF Position */
+#define UART_LINSTS_SLVHEF_Msk (0x1ul << UART_LINSTS_SLVHEF_Pos) /*!< UART_T::LINSTS: SLVHEF Mask */
+
+#define UART_LINSTS_SLVIDPEF_Pos (2) /*!< UART_T::LINSTS: SLVIDPEF Position */
+#define UART_LINSTS_SLVIDPEF_Msk (0x1ul << UART_LINSTS_SLVIDPEF_Pos) /*!< UART_T::LINSTS: SLVIDPEF Mask */
+
+#define UART_LINSTS_SLVSYNCF_Pos (3) /*!< UART_T::LINSTS: SLVSYNCF Position */
+#define UART_LINSTS_SLVSYNCF_Msk (0x1ul << UART_LINSTS_SLVSYNCF_Pos) /*!< UART_T::LINSTS: SLVSYNCF Mask */
+
+#define UART_LINSTS_BRKDETF_Pos (8) /*!< UART_T::LINSTS: BRKDETF Position */
+#define UART_LINSTS_BRKDETF_Msk (0x1ul << UART_LINSTS_BRKDETF_Pos) /*!< UART_T::LINSTS: BRKDETF Mask */
+
+#define UART_LINSTS_BITEF_Pos (9) /*!< UART_T::LINSTS: BITEF Position */
+#define UART_LINSTS_BITEF_Msk (0x1ul << UART_LINSTS_BITEF_Pos) /*!< UART_T::LINSTS: BITEF Mask */
+
+
+/**@}*/ /* UART_CONST */
+/**@}*/ /* end of UART register group */
+
+
+/*---------------------- Universal Serial Bus Controller -------------------------*/
+/**
+ @addtogroup USB Universal Serial Bus Controller(USB)
+ Memory Mapped Structure for USB Controller
+@{ */
+
+/**
+ * @brief USBD endpoints register
+ */
+
+typedef struct
+{
+
+
+/**
+ * @var USBD_EP_T::BUFSEG
+ * Offset: 0x500/0x510/0x520/0x530/0x540/0x550/0x560/0x570 Endpoint 0~7 Buffer Segmentation Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[8:3] |BUFSEG |Endpoint Buffer Segmentation
+ * | | |It is used to indicate the offset address for each endpoint with the USB SRAM starting address The effective starting address of the endpoint is
+ * | | |USB_SRAM address + { BUFSEG[8:3], 3'b000}
+ * | | |Where the USB_SRAM address = USBD_BA+0x100h.
+ * | | |Refer to the section 5.4.4.7 for the endpoint SRAM structure and its description.
+ * @var USBD_EP_T::MXPLD
+ * Offset: 0x504/0x514/0x524/0x534/0x544/0x554/0x564/0x574 Endpoint 0~7 Maximal Payload Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[8:0] |MXPLD |Maximal Payload
+ * | | |Define the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token).
+ * | | |It also used to indicate that the endpoint is ready to be transmitted in IN token or received in OUT token.
+ * | | |(1) When the register is written by CPU,
+ * | | |For IN token, the value of MXPLD is used to define the data length to be transmitted and indicate the data buffer is ready.
+ * | | |For OUT token, it means that the controller is ready to receive data from the host and the value of MXPLD is the maximal data length comes from host.
+ * | | |(2) When the register is read by CPU,
+ * | | |For IN token, the value of MXPLD is indicated by the data length be transmitted to host
+ * | | |For OUT token, the value of MXPLD is indicated the actual data length receiving from host.
+ * | | |Note: Once MXPLD is written, the data packets will be transmitted/received immediately after IN/OUT token arrived.
+ * @var USBD_EP_T::CFG
+ * Offset: 0x508/0x518/0x528/0x538/0x548/0x558/0x568/0x578 Endpoint 0~7 Configuration Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[3:0] |EPNUM |Endpoint Number
+ * | | |These bits are used to define the endpoint number of the current endpoint.
+ * |[4] |ISOCH |Isochronous Endpoint
+ * | | |This bit is used to set the endpoint as Isochronous endpoint, no handshake.
+ * | | |0 = No Isochronous endpoint.
+ * | | |1 = Isochronous endpoint.
+ * |[6:5] |STATE |Endpoint STATE
+ * | | |00 = Endpoint is Disabled.
+ * | | |01 = Out endpoint.
+ * | | |10 = IN endpoint.
+ * | | |11 = Undefined.
+ * |[7] |DSQSYNC |Data Sequence Synchronization
+ * | | |0 = DATA0 PID.
+ * | | |1 = DATA1 PID.
+ * | | |Note: It is used to specify the DATA0 or DATA1 PID in the following IN token transaction.
+ * | | |Hardware will toggle automatically in IN token base on the bit.
+ * |[9] |CSTALL |Clear STALL Response
+ * | | |0 = Disable the device to clear the STALL handshake in setup stage.
+ * | | |1 = Clear the device to response STALL handshake in setup stage.
+ * @var USBD_EP_T::CFGP
+ * Offset: 0x50C/0x51C/0x52C/0x53C/0x54C/0x55C/0x56C/0x57C Endpoint 0~7 Set Stall and Clear In/Out Ready Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |CLRRDY |Clear Ready
+ * | | |When the USB_MXPLD register is set by user, it means that the endpoint is ready to transmit or receive data.
+ * | | |If the user wants to turn off this transaction before the transaction start, users can set this bit to 1 to turn it off and it will be cleared to 0 automatically.
+ * | | |For IN token, write 1 to clear the IN token had ready to transmit the data to USB.
+ * | | |For OUT token, write 1 to clear the OUT token had ready to receive the data from USB.
+ * | | |This bit is write 1 only and is always 0 when it is read back.
+ * |[1] |SSTALL |Set STALL
+ * | | |0 = Disable the device to response STALL.
+ * | | |1 = Set the device to respond STALL automatically.
+ */
+
+ __IO uint32_t BUFSEG; /* Offset: 0x500/0x510/0x520/0x530/0x540/0x550/0x560/0x570 Endpoint 0~7 Buffer Segmentation Register */
+ __IO uint32_t MXPLD; /* Offset: 0x504/0x514/0x524/0x534/0x544/0x554/0x564/0x574 Endpoint 0~7 Maximal Payload Register */
+ __IO uint32_t CFG; /* Offset: 0x508/0x518/0x528/0x538/0x548/0x558/0x568/0x578 Endpoint 0~7 Configuration Register */
+ __IO uint32_t CFGP; /* Offset: 0x50C/0x51C/0x52C/0x53C/0x54C/0x55C/0x56C/0x57C Endpoint 0~7 Set Stall and Clear In/Out Ready Control Register */
+
+} USBD_EP_T;
+
+
+
+
+
+typedef struct
+{
+
+
+/**
+ * @var USBD_T::INTEN
+ * Offset: 0x00 USB Interrupt Enable Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |BUSIEN |Bus Event Interrupt Enable
+ * | | |0 = BUS event interrupt Disabled.
+ * | | |1 = BUS event interrupt Enabled.
+ * |[1] |USBIEN |USB Event Interrupt Enable
+ * | | |0 = USB event interrupt Disabled.
+ * | | |1 = USB event interrupt Enabled.
+ * |[2] |VBDETIEN |VBUS Detection Interrupt Enable
+ * | | |0 = Floating detection Interrupt Disabled.
+ * | | |1 = Floating detection Interrupt Enabled.
+ * |[3] |NEVWKIEN |USB No-Event-Wake-Up Interrupt Enable
+ * | | |0 = No-Event-Wake-up Interrupt Disabled.
+ * | | |1 = No-Event-Wake-up Interrupt Enabled.
+ * |[8] |WKEN |Wake-Up Function Enable
+ * | | |0 = USB wake-up function Disabled.
+ * | | |1 = USB wake-up function Enabled.
+ * |[15] |INNAKEN |Active NAK Function And Its Status In IN Token
+ * | | |0 = When device responds NAK after receiving IN token, IN NAK status will not be
+ * | | | updated to USBD_EPSTS register, so that the USB interrupt event will not be asserted.
+ * | | |1 = IN NAK status will be updated to USBD_EPSTS register and the USB interrupt event
+ * | | | will be asserted, when the device responds NAK after receiving IN token.
+ * @var USBD_T::INTSTS
+ * Offset: 0x04 USB Interrupt Event Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |BUSIF |BUS Interrupt Status
+ * | | |The BUS event means that there is one of the suspense or the resume function in the bus.
+ * | | |0 = No BUS event occurred.
+ * | | |1 = Bus event occurred; check USB_ATTR[3:0] to know which kind of bus event was occurred, cleared by write 1 to USB_INTSTS[0].
+ * |[1] |USBIF |USB Event Interrupt Status
+ * | | |The USB event includes the SETUP Token, IN Token, OUT ACK, ISO IN, or ISO OUT events in the bus.
+ * | | |0 = No USB event occurred.
+ * | | |1 = USB event occurred, check EPSTS0~7 to know which kind of USB event occurred.
+ * | | |Cleared by write 1 to USB_INTSTS[1] or EPEVT0~7 and SETUP (USB_INTSTS[31]).
+ * |[2] |VBDETIF |VBUS Detection Interrupt Status
+ * | | |0 = There is not attached/detached event in the USB.
+ * | | |1 = There is attached/detached event in the USB bus and it is cleared by write 1 to USB_INTSTS[2].
+ * |[3] |NEVWKIF |USB No-Event-Wake-Up Interrupt Status
+ * | | |0 = No Wake-up event occurred.
+ * | | |1 = Wake-up event occurred, cleared by write 1 to USB_INTSTS[3].
+ * |[16] |EPEVT0 |Endpoint 0's USB Event Status
+ * | | |0 = No event occurred on endpoint 0.
+ * | | |1 = USB event occurred on Endpoint 0, check USB_EPSTS[10:8] to know which kind of USB event was occurred, cleared by write 1 to USB_INTSTS[16] or USB_INTSTS[1].
+ * |[17] |EPEVT1 |Endpoint 1's USB Event Status
+ * | | |0 = No event occurred on endpoint 1.
+ * | | |1 = USB event occurred on Endpoint 1, check USB_EPSTS[13:11] to know which kind of USB event was occurred, cleared by write 1 to USB_INTSTS[17] or USB_INTSTS[1].
+ * |[18] |EPEVT2 |Endpoint 2's USB Event Status
+ * | | |0 = No event occurred on endpoint 2.
+ * | | |1 = USB event occurred on Endpoint 2, check USB_EPSTS[16:14] to know which kind of USB event was occurred, cleared by write 1 to USB_INTSTS[18] or USB_INTSTS[1].
+ * |[19] |EPEVT3 |Endpoint 3's USB Event Status
+ * | | |0 = No event occurred on endpoint 3.
+ * | | |1 = USB event occurred on Endpoint 3, check USB_EPSTS[19:17] to know which kind of USB event was occurred, cleared by write 1 to USB_INTSTS[19] or USB_INTSTS[1].
+ * |[20] |EPEVT4 |Endpoint 4's USB Event Status
+ * | | |0 = No event occurred on endpoint 4.
+ * | | |1 = USB event occurred on Endpoint 4, check USB_EPSTS[22:20] to know which kind of USB event was occurred, cleared by write 1 to USB_INTSTS[20] or USB_INTSTS[1].
+ * |[21] |EPEVT5 |Endpoint 5's USB Event Status
+ * | | |0 = No event occurred on endpoint 5.
+ * | | |1 = USB event occurred on Endpoint 5, check USB_EPSTS[25:23] to know which kind of USB event was occurred, cleared by write 1 to USB_INTSTS[21] or USB_INTSTS[1].
+ * |[22] |EPEVT6 |Endpoint 6's USB Event Status
+ * | | |0 = No event occurred on endpoint 6.
+ * | | |1 = USB event occurred on Endpoint 6, check USB_EPSTS[28:26] to know which kind of USB event was occurred, cleared by write 1 to USB_INTSTS[22] or USB_INTSTS[1].
+ * |[23] |EPEVT7 |Endpoint 7's USB Event Status
+ * | | |0 = No event occurred on endpoint 7.
+ * | | |1 = USB event occurred on Endpoint 7, check USB_EPSTS[31:29] to know which kind of USB event was occurred, cleared by write 1 to USB_INTSTS[23] or USB_INTSTS[1].
+ * |[31] |SETUP |Setup Event Status
+ * | | |0 = No Setup event.
+ * | | |1 = SETUP event occurred, cleared by write 1 to USB_INTSTS[31].
+ * @var USBD_T::FADDR
+ * Offset: 0x08 USB Device Function Address Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[6:0] |FADDR |USB Device Function Address
+ * @var USBD_T::EPSTS
+ * Offset: 0x0C USB Endpoint Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7] |OV |Overrun
+ * | | |It indicates that the received data is over the maximum payload number or not.
+ * | | |0 = No overrun.
+ * | | |1 = Out Data is more than the Max Payload in MXPLD register or the Setup Data is more than 8 Bytes.
+ * |[10:8] |EPSTS0 |Endpoint 0 Bus Status
+ * | | |These bits are used to indicate the current status of this endpoint
+ * | | |000 = In ACK.
+ * | | |001 = In NAK.
+ * | | |010 = Out Packet Data0 ACK.
+ * | | |110 = Out Packet Data1 ACK.
+ * | | |011 = Setup ACK.
+ * | | |111 = Isochronous transfer end.
+ * |[13:11] |EPSTS1 |Endpoint 1 Bus Status
+ * | | |These bits are used to indicate the current status of this endpoint
+ * | | |000 = In ACK.
+ * | | |001 = In NAK.
+ * | | |010 = Out Packet Data0 ACK.
+ * | | |110 = Out Packet Data1 ACK.
+ * | | |011 = Setup ACK.
+ * | | |111 = Isochronous transfer end.
+ * |[16:14] |EPSTS2 |Endpoint 2 Bus Status
+ * | | |These bits are used to indicate the current status of this endpoint
+ * | | |000 = In ACK.
+ * | | |001 = In NAK.
+ * | | |010 = Out Packet Data0 ACK.
+ * | | |110 = Out Packet Data1 ACK.
+ * | | |011 = Setup ACK.
+ * | | |111 = Isochronous transfer end.
+ * |[19:17] |EPSTS3 |Endpoint 3 Bus Status
+ * | | |These bits are used to indicate the current status of this endpoint
+ * | | |000 = In ACK.
+ * | | |001 = In NAK.
+ * | | |010 = Out Packet Data0 ACK.
+ * | | |110 = Out Packet Data1 ACK.
+ * | | |011 = Setup ACK.
+ * | | |111 = Isochronous transfer end.
+ * |[22:20] |EPSTS4 |Endpoint 4 Bus Status
+ * | | |These bits are used to indicate the current status of this endpoint
+ * | | |000 = In ACK.
+ * | | |001 = In NAK.
+ * | | |010 = Out Packet Data0 ACK.
+ * | | |110 = Out Packet Data1 ACK.
+ * | | |011 = Setup ACK.
+ * | | |111 = Isochronous transfer end.
+ * |[25:23] |EPSTS5 |Endpoint 5 Bus Status
+ * | | |These bits are used to indicate the current status of this endpoint
+ * | | |000 = In ACK.
+ * | | |001 = In NAK.
+ * | | |010 = Out Packet Data0 ACK.
+ * | | |110 = Out Packet Data1 ACK.
+ * | | |011 = Setup ACK.
+ * | | |111 = Isochronous transfer end.
+ * |[28:26] |EPSTS6 |Endpoint 6 Bus Status
+ * | | |These bits are used to indicate the current status of this endpoint
+ * | | |000 = In ACK.
+ * | | |001 = In NAK.
+ * | | |010 = Out Packet Data0 ACK.
+ * | | |110 = Out Packet Data1 ACK.
+ * | | |011 = Setup ACK.
+ * | | |111 = Isochronous transfer end.
+ * |[31:29] |EPSTS7 |Endpoint 7 Bus Status
+ * | | |These bits are used to indicate the current status of this endpoint
+ * | | |000 = In ACK.
+ * | | |001 = In NAK.
+ * | | |010 = Out Packet Data0 ACK.
+ * | | |110 = Out Packet Data1 ACK.
+ * | | |011 = Setup ACK.
+ * | | |111 = Isochronous transfer end.
+ * @var USBD_T::ATTR
+ * Offset: 0x10 USB Bus Status and Attribution Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |USBRST |USB Reset Status
+ * | | |0 = Bus no reset.
+ * | | |1 = Bus reset when SE0 (single-ended 0) is presented more than 2.5us.
+ * | | |Note: This bit is read only.
+ * |[1] |SUSPEND |Suspend Status
+ * | | |0 = Bus no suspend.
+ * | | |1 = Bus idle more than 3ms, either cable is plugged off or host is sleeping.
+ * | | |Note: This bit is read only.
+ * |[2] |RESUME |Resume Status
+ * | | |0 = No bus resume.
+ * | | |1 = Resume from suspend.
+ * | | |Note: This bit is read only.
+ * |[3] |TOUT |Time-Out Status
+ * | | |0 = No time-out.
+ * | | |1 = No Bus response more than 18 bits time.
+ * | | |Note: This bit is read only.
+ * |[4] |PHYEN |PHY Transceiver Function Enable
+ * | | |0 = PHY transceiver function Disabled.
+ * | | |1 = PHY transceiver function Enabled.
+ * |[5] |RWAKEUP |Remote Wake-Up
+ * | | |0 = Release the USB bus from K state.
+ * | | |1 = Force USB bus to K (USB_D+ low, USB_D- high) state, used for remote wake-up.
+ * |[7] |USBEN |USB Controller Enable
+ * | | |0 = USB Controller Disabled.
+ * | | |1 = USB Controller Enabled.
+ * |[8] |DPPUEN |Pull-Up Resistor On USB_D+ Enable
+ * | | |0 = Pull-up resistor in USB_D+ pin Disabled.
+ * | | |1 = Pull-up resistor in USB_D+ pin Enabled.
+ * |[9] |PWRDN |Power Down PHY Transceiver, Low Active (M45xD/M45xC Only)
+ * | | |0 = Power down related circuits of PHY transceiver.
+ * | | |1 = Turn on related circuits of PHY transceiver.
+ * |[10] |BYTEM |CPU Access USB SRAM Size Mode Selection
+ * | | |0 = Word mode: The size of the transfer from CPU to USB SRAM can be Word only.
+ * | | |1 = Byte mode: The size of the transfer from CPU to USB SRAM can be Byte only.
+ * @var USBD_T::VBUSDET
+ * Offset: 0x14 USB Device VBUS Detection Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |FLDET |Device VBUS Detected
+ * | | |0 = Controller is not attached into the USB host.
+ * | | |1 =Controller is attached into the BUS.
+ * @var USBD_T::STBUFSEG
+ * Offset: 0x18 Setup Token Buffer Segmentation Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[8:3] |STBUFSEG |Setup Token Buffer Segmentation
+ * | | |It is used to indicate the offset address for the SETUP token with the USB Device SRAM starting address The effective starting address is
+ * | | |USB_SRAM address + {STBUFSEG[8:3], 3'b000}
+ * | | |Where the USB_SRAM address = USBD_BA+0x100h.
+ * | | |Note: It is used for SETUP token only.
+ * @var USBD_T::SE0
+ * Offset: 0x90 USB Drive SE0 Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |DRVSE0 |Drive Single Ended Zero In USB Bus
+ * | | |The Single Ended Zero (SE0) is when both lines (USB_D+ and USB_D-) are being pulled low.
+ * | | |0 = None.
+ * | | |1 = Force USB PHY transceiver to drive SE0.
+ * @var USBD_T::EP
+ * Offset: 0x500 ~ 0x57C USB End Point 0 ~ 7 Configuration Register
+ * ---------------------------------------------------------------------------------------------------
+ */
+
+ __IO uint32_t INTEN; /* Offset: 0x00 USB Interrupt Enable Register */
+ __IO uint32_t INTSTS; /* Offset: 0x04 USB Interrupt Event Status Register */
+ __IO uint32_t FADDR; /* Offset: 0x08 USB Device Function Address Register */
+ __I uint32_t EPSTS; /* Offset: 0x0C USB Endpoint Status Register */
+ __IO uint32_t ATTR; /* Offset: 0x10 USB Bus Status and Attribution Register */
+ __I uint32_t VBUSDET; /* Offset: 0x14 USB Device VBUS Detection Register */
+ __IO uint32_t STBUFSEG; /* Offset: 0x18 Setup Token Buffer Segmentation Register */
+ __I uint32_t RESERVE0[29];
+ __IO uint32_t SE0; /* Offset: 0x90 USB Drive SE0 Control Register */
+ __I uint32_t RESERVE1[283];
+ USBD_EP_T EP[8]; /* Offset: 0x500 ~ 0x57C USB End Point 0 ~ 7 Configuration Register */
+
+} USBD_T;
+
+
+
+/**
+ @addtogroup USB_CONST USB Bit Field Definition
+ Constant Definitions for USB Controller
+@{ */
+
+#define USBD_INTEN_BUSIEN_Pos (0) /*!< USBD_T::INTEN: BUSIEN Position */
+#define USBD_INTEN_BUSIEN_Msk (0x1ul << USBD_INTEN_BUSIEN_Pos) /*!< USBD_T::INTEN: BUSIEN Mask */
+
+#define USBD_INTEN_USBIEN_Pos (1) /*!< USBD_T::INTEN: USBIEN Position */
+#define USBD_INTEN_USBIEN_Msk (0x1ul << USBD_INTEN_USBIEN_Pos) /*!< USBD_T::INTEN: USBIEN Mask */
+
+#define USBD_INTEN_VBDETIEN_Pos (2) /*!< USBD_T::INTEN: VBDETIEN Position */
+#define USBD_INTEN_VBDETIEN_Msk (0x1ul << USBD_INTEN_VBDETIEN_Pos) /*!< USBD_T::INTEN: VBDETIEN Mask */
+
+#define USBD_INTEN_NEVWKIEN_Pos (3) /*!< USBD_T::INTEN: NEVWKIEN Position */
+#define USBD_INTEN_NEVWKIEN_Msk (0x1ul << USBD_INTEN_NEVWKIEN_Pos) /*!< USBD_T::INTEN: NEVWKIEN Mask */
+
+#define USBD_INTEN_WKEN_Pos (8) /*!< USBD_T::INTEN: WKEN Position */
+#define USBD_INTEN_WKEN_Msk (0x1ul << USBD_INTEN_WKEN_Pos) /*!< USBD_T::INTEN: WKEN Mask */
+
+#define USBD_INTEN_INNAKEN_Pos (15) /*!< USBD_T::INTEN: INNAKEN Position */
+#define USBD_INTEN_INNAKEN_Msk (0x1ul << USBD_INTEN_INNAKEN_Pos) /*!< USBD_T::INTEN: INNAKEN Mask */
+
+#define USBD_INTSTS_BUSIF_Pos (0) /*!< USBD_T::INTSTS: BUSIF Position */
+#define USBD_INTSTS_BUSIF_Msk (0x1ul << USBD_INTSTS_BUSIF_Pos) /*!< USBD_T::INTSTS: BUSIF Mask */
+
+#define USBD_INTSTS_USBIF_Pos (1) /*!< USBD_T::INTSTS: USBIF Position */
+#define USBD_INTSTS_USBIF_Msk (0x1ul << USBD_INTSTS_USBIF_Pos) /*!< USBD_T::INTSTS: USBIF Mask */
+
+#define USBD_INTSTS_VBDETIF_Pos (2) /*!< USBD_T::INTSTS: VBDETIF Position */
+#define USBD_INTSTS_VBDETIF_Msk (0x1ul << USBD_INTSTS_VBDETIF_Pos) /*!< USBD_T::INTSTS: VBDETIF Mask */
+
+#define USBD_INTSTS_NEVWKIF_Pos (3) /*!< USBD_T::INTSTS: NEVWKIF Position */
+#define USBD_INTSTS_NEVWKIF_Msk (0x1ul << USBD_INTSTS_NEVWKIF_Pos) /*!< USBD_T::INTSTS: NEVWKIF Mask */
+
+#define USBD_INTSTS_EPEVT0_Pos (16) /*!< USBD_T::INTSTS: EPEVT0 Position */
+#define USBD_INTSTS_EPEVT0_Msk (0x1ul << USBD_INTSTS_EPEVT0_Pos) /*!< USBD_T::INTSTS: EPEVT0 Mask */
+
+#define USBD_INTSTS_EPEVT1_Pos (17) /*!< USBD_T::INTSTS: EPEVT1 Position */
+#define USBD_INTSTS_EPEVT1_Msk (0x1ul << USBD_INTSTS_EPEVT1_Pos) /*!< USBD_T::INTSTS: EPEVT1 Mask */
+
+#define USBD_INTSTS_EPEVT2_Pos (18) /*!< USBD_T::INTSTS: EPEVT2 Position */
+#define USBD_INTSTS_EPEVT2_Msk (0x1ul << USBD_INTSTS_EPEVT2_Pos) /*!< USBD_T::INTSTS: EPEVT2 Mask */
+
+#define USBD_INTSTS_EPEVT3_Pos (19) /*!< USBD_T::INTSTS: EPEVT3 Position */
+#define USBD_INTSTS_EPEVT3_Msk (0x1ul << USBD_INTSTS_EPEVT3_Pos) /*!< USBD_T::INTSTS: EPEVT3 Mask */
+
+#define USBD_INTSTS_EPEVT4_Pos (20) /*!< USBD_T::INTSTS: EPEVT4 Position */
+#define USBD_INTSTS_EPEVT4_Msk (0x1ul << USBD_INTSTS_EPEVT4_Pos) /*!< USBD_T::INTSTS: EPEVT4 Mask */
+
+#define USBD_INTSTS_EPEVT5_Pos (21) /*!< USBD_T::INTSTS: EPEVT5 Position */
+#define USBD_INTSTS_EPEVT5_Msk (0x1ul << USBD_INTSTS_EPEVT5_Pos) /*!< USBD_T::INTSTS: EPEVT5 Mask */
+
+#define USBD_INTSTS_EPEVT6_Pos (22) /*!< USBD_T::INTSTS: EPEVT6 Position */
+#define USBD_INTSTS_EPEVT6_Msk (0x1ul << USBD_INTSTS_EPEVT6_Pos) /*!< USBD_T::INTSTS: EPEVT6 Mask */
+
+#define USBD_INTSTS_EPEVT7_Pos (23) /*!< USBD_T::INTSTS: EPEVT7 Position */
+#define USBD_INTSTS_EPEVT7_Msk (0x1ul << USBD_INTSTS_EPEVT7_Pos) /*!< USBD_T::INTSTS: EPEVT7 Mask */
+
+#define USBD_INTSTS_SETUP_Pos (31) /*!< USBD_T::INTSTS: SETUP Position */
+#define USBD_INTSTS_SETUP_Msk (0x1ul << USBD_INTSTS_SETUP_Pos) /*!< USBD_T::INTSTS: SETUP Mask */
+
+#define USBD_FADDR_FADDR_Pos (0) /*!< USBD_T::FADDR: FADDR Position */
+#define USBD_FADDR_FADDR_Msk (0x7ful << USBD_FADDR_FADDR_Pos) /*!< USBD_T::FADDR: FADDR Mask */
+
+#define USBD_EPSTS_OV_Pos (7) /*!< USBD_T::EPSTS: OV Position */
+#define USBD_EPSTS_OV_Msk (0x1ul << USBD_EPSTS_OV_Pos) /*!< USBD_T::EPSTS: OV Mask */
+
+#define USBD_EPSTS_EPSTS0_Pos (8) /*!< USBD_T::EPSTS: EPSTS0 Position */
+#define USBD_EPSTS_EPSTS0_Msk (0x7ul << USBD_EPSTS_EPSTS0_Pos) /*!< USBD_T::EPSTS: EPSTS0 Mask */
+
+#define USBD_EPSTS_EPSTS1_Pos (11) /*!< USBD_T::EPSTS: EPSTS1 Position */
+#define USBD_EPSTS_EPSTS1_Msk (0x7ul << USBD_EPSTS_EPSTS1_Pos) /*!< USBD_T::EPSTS: EPSTS1 Mask */
+
+#define USBD_EPSTS_EPSTS2_Pos (14) /*!< USBD_T::EPSTS: EPSTS2 Position */
+#define USBD_EPSTS_EPSTS2_Msk (0x7ul << USBD_EPSTS_EPSTS2_Pos) /*!< USBD_T::EPSTS: EPSTS2 Mask */
+
+#define USBD_EPSTS_EPSTS3_Pos (17) /*!< USBD_T::EPSTS: EPSTS3 Position */
+#define USBD_EPSTS_EPSTS3_Msk (0x7ul << USBD_EPSTS_EPSTS3_Pos) /*!< USBD_T::EPSTS: EPSTS3 Mask */
+
+#define USBD_EPSTS_EPSTS4_Pos (20) /*!< USBD_T::EPSTS: EPSTS4 Position */
+#define USBD_EPSTS_EPSTS4_Msk (0x7ul << USBD_EPSTS_EPSTS4_Pos) /*!< USBD_T::EPSTS: EPSTS4 Mask */
+
+#define USBD_EPSTS_EPSTS5_Pos (23) /*!< USBD_T::EPSTS: EPSTS5 Position */
+#define USBD_EPSTS_EPSTS5_Msk (0x7ul << USBD_EPSTS_EPSTS5_Pos) /*!< USBD_T::EPSTS: EPSTS5 Mask */
+
+#define USBD_EPSTS_EPSTS6_Pos (26) /*!< USBD_T::EPSTS: EPSTS6 Position */
+#define USBD_EPSTS_EPSTS6_Msk (0x7ul << USBD_EPSTS_EPSTS6_Pos) /*!< USBD_T::EPSTS: EPSTS6 Mask */
+
+#define USBD_EPSTS_EPSTS7_Pos (29) /*!< USBD_T::EPSTS: EPSTS7 Position */
+#define USBD_EPSTS_EPSTS7_Msk (0x7ul << USBD_EPSTS_EPSTS7_Pos) /*!< USBD_T::EPSTS: EPSTS7 Mask */
+
+#define USBD_ATTR_USBRST_Pos (0) /*!< USBD_T::ATTR: USBRST Position */
+#define USBD_ATTR_USBRST_Msk (0x1ul << USBD_ATTR_USBRST_Pos) /*!< USBD_T::ATTR: USBRST Mask */
+
+#define USBD_ATTR_SUSPEND_Pos (1) /*!< USBD_T::ATTR: SUSPEND Position */
+#define USBD_ATTR_SUSPEND_Msk (0x1ul << USBD_ATTR_SUSPEND_Pos) /*!< USBD_T::ATTR: SUSPEND Mask */
+
+#define USBD_ATTR_RESUME_Pos (2) /*!< USBD_T::ATTR: RESUME Position */
+#define USBD_ATTR_RESUME_Msk (0x1ul << USBD_ATTR_RESUME_Pos) /*!< USBD_T::ATTR: RESUME Mask */
+
+#define USBD_ATTR_TOUT_Pos (3) /*!< USBD_T::ATTR: TOUT Position */
+#define USBD_ATTR_TOUT_Msk (0x1ul << USBD_ATTR_TOUT_Pos) /*!< USBD_T::ATTR: TOUT Mask */
+
+#define USBD_ATTR_PHYEN_Pos (4) /*!< USBD_T::ATTR: PHYEN Position */
+#define USBD_ATTR_PHYEN_Msk (0x1ul << USBD_ATTR_PHYEN_Pos) /*!< USBD_T::ATTR: PHYEN Mask */
+
+#define USBD_ATTR_RWAKEUP_Pos (5) /*!< USBD_T::ATTR: RWAKEUP Position */
+#define USBD_ATTR_RWAKEUP_Msk (0x1ul << USBD_ATTR_RWAKEUP_Pos) /*!< USBD_T::ATTR: RWAKEUP Mask */
+
+#define USBD_ATTR_USBEN_Pos (7) /*!< USBD_T::ATTR: USBEN Position */
+#define USBD_ATTR_USBEN_Msk (0x1ul << USBD_ATTR_USBEN_Pos) /*!< USBD_T::ATTR: USBEN Mask */
+
+#define USBD_ATTR_DPPUEN_Pos (8) /*!< USBD_T::ATTR: DPPUEN Position */
+#define USBD_ATTR_DPPUEN_Msk (0x1ul << USBD_ATTR_DPPUEN_Pos) /*!< USBD_T::ATTR: DPPUEN Mask */
+
+#define USBD_ATTR_PWRDN_Pos (9) /*!< USBD_T::ATTR: PWRDN Position */
+#define USBD_ATTR_PWRDN_Msk (0x1ul << USBD_ATTR_PWRDN_Pos) /*!< USBD_T::ATTR: PWRDN Mask */
+
+#define USBD_ATTR_BYTEM_Pos (10) /*!< USBD_T::ATTR: BYTEM Position */
+#define USBD_ATTR_BYTEM_Msk (0x1ul << USBD_ATTR_BYTEM_Pos) /*!< USBD_T::ATTR: BYTEM Mask */
+
+#define USBD_VBUSDET_VBUSDET_Pos (0) /*!< USBD_T::VBUSDET: VBUSDET Position */
+#define USBD_VBUSDET_VBUSDET_Msk (0x1ul << USBD_VBUSDET_VBUSDET_Pos) /*!< USBD_T::VBUSDET: VBUSDET Mask */
+
+#define USBD_STBUFSEG_STBUFSEG_Pos (3) /*!< USBD_T::STBUFSEG: STBUFSEG Position */
+#define USBD_STBUFSEG_STBUFSEG_Msk (0x3ful << USBD_STBUFSEG_STBUFSEG_Pos) /*!< USBD_T::STBUFSEG: STBUFSEG Mask */
+
+#define USBD_SE0_SE0_Pos (0) /*!< USBD_T::SE0: SE0 Position */
+#define USBD_SE0_SE0_Msk (0x1ul << USBD_SE0_SE0_Pos) /*!< USBD_T::SE0: SE0 Mask */
+
+#define USBD_BUFSEG_BUFSEG_Pos (3) /*!< USBD_EP_T::BUFSEG: BUFSEG Position */
+#define USBD_BUFSEG_BUFSEG_Msk (0x3ful << USBD_BUFSEG_BUFSEG_Pos) /*!< USBD_EP_T::BUFSEG: BUFSEG Mask */
+
+#define USBD_MXPLD_MXPLD_Pos (0) /*!< USBD_EP_T::MXPLD: MXPLD Position */
+#define USBD_MXPLD_MXPLD_Msk (0x1fful << USBD_MXPLD_MXPLD_Pos) /*!< USBD_EP_T::MXPLD: MXPLD Mask */
+
+#define USBD_CFG_EPNUM_Pos (0) /*!< USBD_EP_T::CFG: EPNUM Position */
+#define USBD_CFG_EPNUM_Msk (0xful << USBD_CFG_EPNUM_Pos) /*!< USBD_EP_T::CFG: EPNUM Mask */
+
+#define USBD_CFG_ISOCH_Pos (4) /*!< USBD_EP_T::CFG: ISOCH Position */
+#define USBD_CFG_ISOCH_Msk (0x1ul << USBD_CFG_ISOCH_Pos) /*!< USBD_EP_T::CFG: ISOCH Mask */
+
+#define USBD_CFG_STATE_Pos (5) /*!< USBD_EP_T::CFG: STATE Position */
+#define USBD_CFG_STATE_Msk (0x3ul << USBD_CFG_STATE_Pos) /*!< USBD_EP_T::CFG: STATE Mask */
+
+#define USBD_CFG_DSQSYNC_Pos (7) /*!< USBD_EP_T::CFG: DSQSYNC Position */
+#define USBD_CFG_DSQSYNC_Msk (0x1ul << USBD_CFG_DSQSYNC_Pos) /*!< USBD_EP_T::CFG: DSQSYNC Mask */
+
+#define USBD_CFG_CSTALL_Pos (9) /*!< USBD_EP_T::CFG: CSTALL Position */
+#define USBD_CFG_CSTALL_Msk (0x1ul << USBD_CFG_CSTALL_Pos) /*!< USBD_EP_T::CFG: CSTALL Mask */
+
+#define USBD_CFGP_CLRRDY_Pos (0) /*!< USBD_EP_T::CFGP: CLRRDY Position */
+#define USBD_CFGP_CLRRDY_Msk (0x1ul << USBD_CFGP_CLRRDY_Pos) /*!< USBD_EP_T::CFGP: CLRRDY Mask */
+
+#define USBD_CFGP_SSTALL_Pos (1) /*!< USBD_EP_T::CFGP: SSTALL Position */
+#define USBD_CFGP_SSTALL_Msk (0x1ul << USBD_CFGP_SSTALL_Pos) /*!< USBD_EP_T::CFGP: SSTALL Mask */
+
+/**@}*/ /* USB_CONST */
+/**@}*/ /* end of USB register group */
+
+
+/*---------------------- USB Host Controller -------------------------*/
+/**
+ @addtogroup USBH USB Host Controller(USBH)
+ Memory Mapped Structure for USBH Controller
+@{ */
+
+
+typedef struct
+{
+
+
+
+
+/**
+ * @var USBH_T::HcRevision
+ * Offset: 0x00 Host Controller Revision Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:0] |REV |Revision Number
+ * | | |Indicates the Open HCI Specification revision number implemented by the Hardware.
+ * | | |Host Controller supports 1.1 specification.
+ * | | |(X.Y = XYh).
+ * @var USBH_T::HcControl
+ * Offset: 0x04 Host Controller Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[1:0] |CBSR |Control Bulk Service Ratio
+ * | | |This specifies the service ratio between Control and Bulk EDs.
+ * | | |Before processing any of the non-periodic lists, HC must compare the ratio specified with its internal count on how many nonempty Control EDs have been processed, in determining whether to continue serving another Control ED or switching to Bulk EDs.
+ * | | |The internal count will be retained when crossing the frame boundary.
+ * | | |In case of reset, HCD is responsible for restoring this.
+ * | | |Value.
+ * | | |00 = Number of Control EDs over Bulk EDs served is 1:1.
+ * | | |01 = Number of Control EDs over Bulk EDs served is 2:1.
+ * | | |10 = Number of Control EDs over Bulk EDs served is 3:1.
+ * | | |11 = Number of Control EDs over Bulk EDs served is 4:1.
+ * |[2] |PLE |Periodic List Enable Bit
+ * | | |When set, this bit enables processing of the Periodic (interrupt and Isochronous) list.
+ * | | |The Host Controller checks this bit prior to attempting any periodic transfers in a frame.
+ * | | |0 = Disable the processing of the Periodic (Interrupt and Isochronous) list after next SOF (Start-Of-Frame).
+ * | | |1 = Enable the processing of the Periodic (Interrupt and Isochronous) list in the next frame.
+ * | | |Note: To enable the processing of the Isochronous list, user has to set both PLE and IE (HcControl[3]) high.
+ * |[3] |IE |Isochronous List Enable Bit
+ * | | |Both ISOEn and PLE (HcControl[2]) high enables Host Controller to process the Isochronous list.
+ * | | |Either ISOEn or PLE (HcControl[2]) is low disables Host Controller to process the Isochronous list.
+ * | | |0 = Disable the processing of the Isochronous list after next SOF (Start-Of-Frame).
+ * | | |1 = Enable the processing of the Isochronous list in the next frame if the PLE (HcControl[2]) is high, too.
+ * |[4] |CLE |Control List Enable Bit
+ * | | |0 = Disable processing of the Control list after next SOF (Start-Of-Frame).
+ * | | |1 = Enable processing of the Control list in the next frame.
+ * |[5] |BLE |Bulk List Enable Bit
+ * | | |0 = Disable processing of the Bulk list after next SOF (Start-Of-Frame).
+ * | | |1 = Enable processing of the Bulk list in the next frame.
+ * |[7:6] |HCFS |Host Controller Functional State
+ * | | |This field sets the Host Controller state.
+ * | | |The Controller may force a state change from USBSUSPEND to USBRESUME after detecting resume signaling from a downstream port.
+ * | | |States are:
+ * | | |00 = USBSUSPEND.
+ * | | |01 = USBRESUME.
+ * | | |10 = USBOPERATIONAL.
+ * | | |11 = USBRESET.
+ * @var USBH_T::HcCommandStatus
+ * Offset: 0x08 Host Controller CMD Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |HCR |Host Controller Reset
+ * | | |This bit is set to initiate the software reset of Host Controller.
+ * | | |This bit is cleared by the Host Controller, upon completed of the reset operation.
+ * | | |This bit, when set, didn't reset the Root Hub and no subsequent reset signaling be asserted to its downstream ports.
+ * | | |0 = Host Controller is not in software reset state.
+ * | | |1 = Host Controller is in software reset state.
+ * |[1] |CLF |Control List Filled
+ * | | |Set high to indicate there is an active TD on the Control List.
+ * | | |It may be set by either software or the Host Controller and cleared by the Host Controller each time it begins processing the head of the Control List.
+ * | | |0 = No active TD found or Host Controller begins to process the head of the Control list.
+ * | | |1 = An active TD added or found on the Control list.
+ * |[2] |BLF |Bulk List Filled
+ * | | |Set high to indicate there is an active TD on the Bulk list.
+ * | | |This bit may be set by either software or the Host Controller and cleared by the Host Controller each time it begins processing the head of the Bulk list.
+ * | | |0 = No active TD found or Host Controller begins to process the head of the Bulk list.
+ * | | |1 = An active TD added or found on the Bulk list.
+ * |[17:16] |SOC |Schedule Overrun Count
+ * | | |These bits are incremented on each scheduling overrun error.
+ * | | |It is initialized to 00b and wraps around at 11b.
+ * | | |This will be incremented when a scheduling overrun is detected even if SO (HcIntSts[0]) has already been set.
+ * @var USBH_T::HcInterruptStatus
+ * Offset: 0x0C Host Controller Interrupt Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |SO |Scheduling Overrun
+ * | | |Set when the List Processor determines a Schedule Overrun has occurred.
+ * | | |0 = Schedule Overrun didn't occur.
+ * | | |1 = Schedule Overrun has occurred.
+ * |[1] |WDH |Write Back Done Head
+ * | | |Set after the Host Controller has written HcDoneHead to HccaDoneHead.
+ * | | |Further updates of the HccaDoneHead will not occur until this bit has been cleared.
+ * | | |0 =.Host Controller didn't update HccaDoneHead.
+ * | | |1 =.Host Controller has written HcDoneHead to HccaDoneHead.
+ * |[2] |SF |Start Of Frame
+ * | | |Set when the Frame Management functional block signals a 'Start of Frame' event.
+ * | | |Host Control generates a SOF token at the same time.
+ * | | |0 =.Not the start of a frame.
+ * | | |1 =.Indicate the start of a frame and Host Controller generates a SOF token.
+ * |[3] |RD |Resume Detected
+ * | | |Set when Host Controller detects resume signaling on a downstream port.
+ * | | |0 = No resume signaling detected on a downstream port.
+ * | | |1 = Resume signaling detected on a downstream port.
+ * |[5] |FNO |Frame Number Overflow
+ * | | |This bit is set when bit 15 of Frame Number changes from 1 to 0 or from 0 to 1.
+ * | | |0 = The bit 15 of Frame Number didn't change.
+ * | | |1 = The bit 15 of Frame Number changes from 1 to 0 or from 0 to 1.
+ * |[6] |RHSC |Root Hub Status Change
+ * | | |This bit is set when the content of HcRhSts or the content of HcRhPrt1 register has changed.
+ * | | |0 = The content of HcRhSts and the content of HcRhPrt1 register didn't change.
+ * | | |1 = The content of HcRhSts or the content of HcRhPrt1 register has changed.
+ * @var USBH_T::HcInterruptEnable
+ * Offset: 0x10 Host Controller Interrupt Enable Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |SO |Scheduling Overrun Enable Bit
+ * | | |Write Operation:
+ * | | |0 = No effect.
+ * | | |1 = Enable interrupt generation due to SO (HcIntSts[0]).
+ * | | |Read Operation:
+ * | | |0 = Interrupt generation due to SO (HcIntSts[0]) disabled.
+ * | | |1 = Interrupt generation due to SO (HcIntSts[0]) enabled.
+ * |[1] |WDH |Write Back Done Head Enable Bit
+ * | | |Write Operation:
+ * | | |0 = No effect.
+ * | | |1 = Enable interrupt generation due to WDH (HcIntSts[1]).
+ * | | |Read Operation:
+ * | | |0 = Interrupt generation due to WDH (HcIntSts[1]) disabled.
+ * | | |1 = Interrupt generation due to WDH (HcIntSts[1]) enabled.
+ * |[2] |SF |Start Of Frame Enable Bit
+ * | | |Write Operation:
+ * | | |0 = No effect.
+ * | | |1 = Enable interrupt generation due to SF (HcIntSts[2]).
+ * | | |Read Operation:
+ * | | |0 = Interrupt generation due to SF (HcIntSts[2]) disabled.
+ * | | |1 = Interrupt generation due to SF (HcIntSts[2]) enabled.
+ * |[3] |RD |Resume Detected Enable Bit
+ * | | |Write Operation:
+ * | | |0 = No effect.
+ * | | |1 = Enable interrupt generation due to RD (HcIntSts[3]).
+ * | | |Read Operation:
+ * | | |0 = Interrupt generation due to RD (HcIntSts[3]) disabled.
+ * | | |1 = Interrupt generation due to RD (HcIntSts[3]) enabled.
+ * |[5] |FNO |Frame Number Overflow Enable Bit
+ * | | |Write Operation:
+ * | | |0 = No effect.
+ * | | |1 = Enable interrupt generation due to FNO (HcIntSts[5]).
+ * | | |Read Operation:
+ * | | |0 = Interrupt generation due to FNO (HcIntSts[5]) disabled.
+ * | | |1 = Interrupt generation due to FNO (HcIntSts[5]) enabled.
+ * |[6] |RHSC |Root Hub Status Change Enable Bit
+ * | | |Write Operation:
+ * | | |0 = No effect.
+ * | | |1 = Enable interrupt generation due to RHSC (HcIntSts[6]).
+ * | | |Read Operation:
+ * | | |0 = Interrupt generation due to RHSC (HcIntSts[6]) disabled.
+ * | | |1 = Interrupt generation due to RHSC (HcIntSts[6]) enabled.
+ * |[31] |MIE |Master Interrupt Enable Bit
+ * | | |This bit is a global interrupt enable.
+ * | | |A write of '1' allows interrupts to be enabled via the specific enable bits listed above.
+ * | | |Write Operation:
+ * | | |0 = No effect.
+ * | | |1 = Enable interrupt generation due to RHSC (HcIntSts[6]), FNO (HcIntSts[5]), RD (HcIntSts[3]), SF (HcIntSts[2]), WDH (HcIntSts[1]) or SO (HcIntSts[0]) if the corresponding bit in HcIntEn is high.
+ * | | |Read Operation:
+ * | | |0 = Interrupt generation due to RHSC (HcIntSts[6]), FNO (HcIntSts[5]), RD (HcIntSts[3]), SF (HcIntSts[2]), WDH (HcIntSts[1]) or SO (HcIntSts[0]) disabled even if the corresponding bit in HcIntEn is high.
+ * | | |1 = Interrupt generation due to RHSC (HcIntSts[6]), FNO (HcIntSts[5]), RD (HcIntSts[3]), SF (HcIntSts[2]), WDH (HcIntSts[1]) or SO (HcIntSts[0]) enabled if the corresponding bit in HcIntEn is high.
+ * @var USBH_T::HcInterruptDisable
+ * Offset: 0x14 Host Controller Interrupt Disable Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |SO |Scheduling Overrun Disable Bit
+ * | | |Write Operation:
+ * | | |0 = No effect.
+ * | | |1 = Disable interrupt generation due to SO (HcIntSts[0]).
+ * | | |Read Operation:
+ * | | |0 = Interrupt generation due to SO (HcIntSts[0]) disabled.
+ * | | |1 = Interrupt generation due to SO (HcIntSts[0]) enabled.
+ * |[1] |WDH |Write Back Done Head Disable Bit
+ * | | |Write Operation:
+ * | | |0 = No effect.
+ * | | |1 = Disable interrupt generation due to WDH (HcIntSts[1]).
+ * | | |Read Operation:
+ * | | |0 = Interrupt generation due to WDH (HcIntSts[1]) disabled.
+ * | | |1 = Interrupt generation due to WDH (HcIntSts[1]) enabled.
+ * |[2] |SF |Start Of Frame Disable Bit
+ * | | |Write Operation:
+ * | | |0 = No effect.
+ * | | |1 = Disable interrupt generation due to SF (HcIntSts[2]).
+ * | | |Read Operation:
+ * | | |0 = Interrupt generation due to SF (HcIntSts[2]) disabled.
+ * | | |1 = Interrupt generation due to SF (HcIntSts[2]) enabled.
+ * |[3] |RD |Resume Detected Disable Bit
+ * | | |Write Operation:
+ * | | |0 = No effect.
+ * | | |1 = Disable interrupt generation due to RD (HcIntSts[3]).
+ * | | |Read Operation:
+ * | | |0 = Interrupt generation due to RD (HcIntSts[3]) disabled.
+ * | | |1 = Interrupt generation due to RD (HcIntSts[3]) enabled.
+ * |[5] |FNO |Frame Number Overflow Disable Bit
+ * | | |Write Operation:
+ * | | |0 = No effect.
+ * | | |1 = Disable interrupt generation due to FNO (HcIntSts[5]).
+ * | | |Read Operation:
+ * | | |0 = Interrupt generation due to FNO (HcIntSts[5]) disabled.
+ * | | |1 = Interrupt generation due to FNO (HcIntSts[5]) enabled.
+ * |[6] |RHSC |Root Hub Status Change Disable Bit
+ * | | |Write Operation:
+ * | | |0 = No effect.
+ * | | |1 = Disable interrupt generation due to RHSC (HcIntSts[6]).
+ * | | |Read Operation:
+ * | | |0 = Interrupt generation due to RHSC (HcIntSts[6]) disabled.
+ * | | |1 = Interrupt generation due to RHSC (HcIntSts[6]) enabled.
+ * |[31] |MIE |Master Interrupt Disable Bit
+ * | | |Global interrupt disable. Writing '1' to disable all interrupts.
+ * | | |Write Operation:
+ * | | |0 = No effect.
+ * | | |1 = Disable interrupt generation due to RHSC (HcIntSts[6]), FNO (HcIntSts[5]), RD (HcIntSts[3]), SF (HcIntSts[2]), WDH (HcIntSts[1]) or SO (HcIntSts[0]) if the corresponding bit in HcIntEn is high.
+ * | | |Read Operation:
+ * | | |0 = Interrupt generation due to RHSC (HcIntSts[6]), FNO (HcIntSts[5]), RD (HcIntSts[3]), SF (HcIntSts[2]), WDH (HcIntSts[1]) or SO (HcIntSts[0]) disabled even if the corresponding bit in HcIntEn is high.
+ * | | |1 = Interrupt generation due to RHSC (HcIntSts[6]), FNO (HcIntSts[5]), RD (HcIntSts[3]), SF (HcIntSts[2]), WDH (HcIntSts[1]) or SO (HcIntSts[0]) enabled if the corresponding bit in HcIntEn is high.
+ * @var USBH_T::HcHCCA
+ * Offset: 0x18 Host Controller Communication Area Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:8] |HCCA |Host Controller Communication Area
+ * | | |Pointer to indicate base address of the Host Controller Communication Area (HCCA).
+ * @var USBH_T::HcPeriodCurrentED
+ * Offset: 0x1C Host Controller Period Current ED Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:4] |PCED |Periodic Current ED
+ * | | |Pointer to indicate physical address of the current Isochronous or Interrupt Endpoint Descriptor.
+ * @var USBH_T::HcControlHeadED
+ * Offset: 0x20 Host Controller Control Head ED Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:4] |CHED |Control Head ED
+ * | | |Pointer to indicate physical address of the first Endpoint Descriptor of the Control list.
+ * @var USBH_T::HcControlCurrentED
+ * Offset: 0x24 Host Controller Control Current ED Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:4] |CCED |Control Current Head ED
+ * | | |Pointer to indicate the physical address of the current Endpoint Descriptor of the Control list.
+ * @var USBH_T::HcBulkHeadED
+ * Offset: 0x28 Host Controller Bulk Head ED Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:4] |BHED |Bulk Head ED
+ * | | |Pointer to indicate the physical address of the first Endpoint Descriptor of the Bulk list.
+ * @var USBH_T::HcBulkCurrentED
+ * Offset: 0x2C Host Controller Bulk Current ED Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:4] |BCED |Bulk Current Head ED
+ * | | |Pointer to indicate the physical address of the current endpoint of the Bulk list.
+ * @var USBH_T::HcDoneHead
+ * Offset: 0x30 Host Controller Done Head Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:4] |DH |Done Head
+ * | | |Pointer to indicate the physical address of the last completed Transfer Descriptor that was added to the Done queue.
+ * @var USBH_T::HcFmInterval
+ * Offset: 0x34 Host Controller Frame Interval Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[13:0] |FI |Frame Interval
+ * | | |This field specifies the length of a frame as (bit times - 1).
+ * | | |For 12,000 bit times in a frame, a value of 11,999 is stored here.
+ * |[30:16] |FSMPS |FS Largest Data Packet
+ * | | |This field specifies a value that is loaded into the Largest Data Packet Counter at the beginning of each frame.
+ * |[31] |FIT |Frame Interval Toggle
+ * | | |This bit is toggled by Host Controller Driver when it loads a new value into FI (HcFmIntv[13:0]).
+ * | | |0 = Host Controller Driver didn't load new value into FI (HcFmIntv[13:0]).
+ * | | |1 = Host Controller Driver loads a new value into FI (HcFmIntv[13:0]).
+ * @var USBH_T::HcFmRemaining
+ * Offset: 0x38 Host Controller Frame Remaining Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[13:0] |FR |Frame Remaining
+ * | | |When the Host Controller is in the USBOPERATIONAL state, this 14-bit field decrements each 12 MHz clock period.
+ * | | |When the count reaches 0, (end of frame) the counter reloads with Frame Interval.
+ * | | |In addition, the counter loads when the Host Controller transitions into USBOPERATIONAL.
+ * |[31] |FRT |Frame Remaining Toggle
+ * | | |This bit is loaded from the FIT (HcFmIntv[31]) whenever FR (HcFmRem[13:0]) reaches 0.
+ * @var USBH_T::HcFmNumber
+ * Offset: 0x3C Host Controller Frame Number Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[15:0] |FN |Frame Number
+ * | | |This 16-bit incrementing counter field is incremented coincident with the re-load of FR (HcFmRem[13:0]).
+ * | | |The count rolls over from 'FFFFh' to '0h.'.
+ * @var USBH_T::HcPeriodicStart
+ * Offset: 0x40 Host Controller Periodic Start Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[13:0] |PS |Periodic Start
+ * | | |This field contains a value used by the List Processor to determine where in a frame the Periodic List processing must begin.
+ * @var USBH_T::HcLSThreshold
+ * Offset: 0x44 Host Controller Low-speed Threshold Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[11:0] |LST |Low-Speed Threshold
+ * | | |This field contains a value which is compared to the FR (HcFmRem[13:0]) field prior to initiating a Low-speed transaction.
+ * | | |The transaction is started only if FR (HcFmRem[13:0]) >= this field.
+ * | | |The value is calculated by Host Controller Driver with the consideration of transmission and setup overhead.
+ * @var USBH_T::HcRhDescriptorA
+ * Offset: 0x48 Host Controller Root Hub Descriptor A Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[7:0] |NDP |Number Downstream Ports
+ * | | |USB host control supports two downstream ports and only one port is available in this series of chip.
+ * |[8] |PSM |Power Switching Mode
+ * | | |This bit is used to specify how the power switching of the Root Hub ports is controlled.
+ * | | |0 = Global Switching.
+ * | | |1 = Individual Switching.
+ * |[11] |OCPM |Over Current Protection Mode
+ * | | |This bit describes how the over current status for the Root Hub ports reported.
+ * | | |This bit is only valid when NOCP (HcRhDeA[12]) is cleared.
+ * | | |0 = Global Over current.
+ * | | |1 = Individual Over current.
+ * |[12] |NOCP |No Over Current Protection
+ * | | |This bit describes how the over current status for the Root Hub ports reported.
+ * | | |0 = Over current status is reported.
+ * | | |1 = Over current status is not reported.
+ * @var USBH_T::HcRhDescriptorB
+ * Offset: 0x4C Host Controller Root Hub Descriptor B Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:16] |PPCM |Port Power Control Mask
+ * | | |Global power switching.
+ * | | |This field is only valid if PowerSwitchingMode is set (individual port switching).
+ * | | |When set, the port only responds to individual port power switching commands (Set/ClearPortPower).
+ * | | |When cleared, the port only responds to global power switching commands (Set/ClearGlobalPower).
+ * | | |0 = Port power controlled by global power switching.
+ * | | |1 = Port power controlled by port power switching.
+ * | | |Note: PPCM[15:2] and PPCM[0] are reserved.
+ * @var USBH_T::HcRhStatus
+ * Offset: 0x50 Host Controller Root Hub Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |LPS |Clear Global Power
+ * | | |In global power mode (PSM (HcRhDeA[8]) = 0), this bit is written to one to clear all ports' power.
+ * | | |This bit always read as zero.
+ * | | |Write Operation:
+ * | | |0 = No effect.
+ * | | |1 = Clear global power.
+ * |[1] |OCI |Over Current Indicator
+ * | | |This bit reflects the state of the over current status pin.
+ * | | |This field is only valid if NOCP (HcRhDesA[12]) and OCPM (HcRhDesA[11]) are cleared.
+ * | | |0 = No over current condition.
+ * | | |1 = Over current condition.
+ * |[15] |DRWE |Device Remote Wakeup Enable Bit
+ * | | |This bit controls if port's Connect Status Change as a remote wake-up event.
+ * | | |Write Operation:
+ * | | |0 = No effect.
+ * | | |1 = Enable Connect Status Change as a remote wake-up event.
+ * | | |Read Operation:
+ * | | |0 = Connect Status Change as a remote wake-up event disabled.
+ * | | |1 = Connect Status Change as a remote wake-up event enabled.
+ * |[16] |LPSC |Set Global Power
+ * | | |In global power mode (PSM (HcRhDeA[8]) = 0), this bit is written to one to enable power to all ports.
+ * | | |This bit always read as zero.
+ * | | |Write Operation:
+ * | | |0 = No effect.
+ * | | |1 = Set global power.
+ * |[17] |OCIC |Over Current Indicator Change
+ * | | |This bit is set by hardware when a change has occurred in OCI (HcRhSts[1]).
+ * | | |Write 1 to clear this bit to zero.
+ * | | |0 = OCI (HcRhSts[1]) didn't change.
+ * | | |1 = OCI (HcRhSts[1]) change.
+ * |[31] |CRWE |Clear Remote Wake-up Enable Bit
+ * | | |This bit is use to clear DRWE (HcRhSts[15]).
+ * | | |This bit always read as zero.
+ * | | |Write Operation:
+ * | | |0 = No effect.
+ * | | |1 = Clear DRWE (HcRhSts[15]).
+ * @var USBH_T::HcRhPortStatus
+ * Offset: 0x54 Host Controller Root Hub Port Status [1]
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |CCS |CurrentConnectStatus (Read) Or ClearPortEnable Bit (Write)
+ * | | |Write Operation:
+ * | | |0 = No effect.
+ * | | |1 = Clear port enable.
+ * | | |Read Operation:
+ * | | |0 = No device connected.
+ * | | |1 = Device connected.
+ * |[1] |PES |Port Enable Status
+ * | | |Write Operation:
+ * | | |0 = No effect.
+ * | | |1 = Set port enable.
+ * | | |Read Operation:
+ * | | |0 = Port Disabled.
+ * | | |1 = Port Enabled.
+ * |[2] |PSS |Port Suspend Status
+ * | | |This bit indicates the port is suspended
+ * | | |Write Operation:
+ * | | |0 = No effect.
+ * | | |1 = Set port suspend.
+ * | | |Read Operation:
+ * | | |0 = Port is not suspended.
+ * | | |1 = Port is selectively suspended.
+ * |[3] |POCI |Port Over Current Indicator (Read) Or Clear Port Suspend (Write)
+ * | | |This bit reflects the state of the over current status pin dedicated to this port.
+ * | | |This field is only valid if NOCP (HcRhDeA[12]) is cleared and OCPM (HcRhDeA[11]) is set.
+ * | | |This bit is also used to initiate the selective result sequence for the port.
+ * | | |Write Operation:
+ * | | |0 = No effect.
+ * | | |1 = Clear port suspend.
+ * | | |Read Operation:
+ * | | |0 = No over current condition.
+ * | | |1 = Over current condition.
+ * |[4] |PRS |Port Reset Status
+ * | | |This bit reflects the reset state of the port.
+ * | | |Write Operation:
+ * | | |0 = No effect.
+ * | | |1 = Set port reset.
+ * | | |Read Operation
+ * | | |0 = Port reset signal is not active.
+ * | | |1 = Port reset signal is active.
+ * |[8] |PPS |Port Power Status
+ * | | |This bit reflects the power state of the port regardless of the power switching mode.
+ * | | |Write Operation:
+ * | | |0 = No effect.
+ * | | |1 = Port Power Enabled.
+ * | | |Read Operation:
+ * | | |0 = Port power is Disabled.
+ * | | |1 = Port power is Enabled.
+ * |[9] |LSDA |Low Speed Device Attached (Read) Or Clear Port Power (Write)
+ * | | |This bit defines the speed (and bud idle) of the attached device.
+ * | | |It is only valid when CCS (HcRhPrt1[0]) is set.
+ * | | |This bit is also used to clear port power.
+ * | | |Write Operation:
+ * | | |0 = No effect.
+ * | | |1 = Clear PPS (HcRhPrt1[8]).
+ * | | |Read Operation:
+ * | | |0 = Full Speed device.
+ * | | |1 = Low-speed device.
+ * |[16] |CSC |Connect Status Change
+ * | | |This bit indicates connect or disconnect event has been detected (CCS
+ * | | |(HcRhPrt1[0]) changed).
+ * | | |Write 1 to clear this bit to zero.
+ * | | |0 = No connect/disconnect event (CCS (HcRhPrt1[0]) didn't change).
+ * | | |1 = Hardware detection of connect/disconnect event (CCS
+ * | | |(HcRhPrt1[0]) changed).
+ * |[17] |PESC |Port Enable Status Change
+ * | | |This bit indicates that the port has been disabled (PES (HcRhPrt1[1]) cleared) due to a hardware event.
+ * | | |Write 1 to clear this bit to zero.
+ * | | |0 = PES (HcRhPrt1[1]) didn't change.
+ * | | |1 = PES (HcRhPrt1[1]) changed.
+ * |[18] |PSSC |Port Suspend Status Change
+ * | | |This bit indicates the completion of the selective resume sequence for the port.
+ * | | |Write 1 to clear this bit to zero.
+ * | | |0 = Port resume is not completed.
+ * | | |1 = Port resume completed.
+ * |[19] |OCIC |Port Over Current Indicator Change
+ * | | |This bit is set when POCI (HcRhPrt1[3]) changes.
+ * | | |Write 1 to clear this bit to zero.
+ * | | |0 = POCI (HcRhPrt1[3]) didn't change.
+ * | | |1 = POCI (HcRhPrt1[3]) changes.
+ * |[20] |PRSC |Port Reset Status Change
+ * | | |This bit indicates that the port reset signal has completed.
+ * | | |Write 1 to clear this bit to zero.
+ * | | |0 = Port reset is not complete.
+ * | | |1 = Port reset is complete.
+ * @var USBH_T::HcPhyControl
+ * Offset: 0x200 USB Host Controller PHY Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[27] |STBYEN |USB Transceiver Standby Enable Bit
+ * | | |This bit controls if USB transceiver could enter the standby mode to reduce power consumption.
+ * | | |0 = The USB transceiver would never enter the standby mode.
+ * | | |1 = The USB transceiver will enter standby mode while port is in power off state (port power is inactive).
+ * @var USBH_T::HcMiscControl
+ * Offset: 0x204 USB Host Controller Miscellaneous Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[1] |ABORT |AHB Bus ERROR Response
+ * | | |This bit indicates there is an ERROR response received in AHB bus.
+ * | | |0 = No ERROR response received.
+ * | | |1 = ERROR response received.
+ * |[3] |OCAL |Over Current Active Low
+ * | | |This bit controls the polarity of over current flag from external power IC.
+ * | | |0 = Over current flag is high active.
+ * | | |1 = Over current flag is low active.
+ * |[16] |DPRT1 |Disable Port 1
+ * | | |This bit controls if the connection between USB host controller and transceiver of port 1 is disabled.
+ * | | |If the connection is disabled, the USB host controller will not recognize any event of USB bus.
+ * | | |Set this bit high, the transceiver of port 1 will also be forced into the standby mode no matter what USB host controller operation is.
+ * | | |0 = The connection between USB host controller and transceiver of port 1 is enabled.
+ * | | |1 = The connection between USB host controller and transceiver of port 1 is disabled and the transceiver of port 1 will also be forced into the standby mode.
+ */
+
+ __I uint32_t HcRevision; /* Offset: 0x00 Host Controller Revision Register */
+ __IO uint32_t HcControl; /* Offset: 0x04 Host Controller Control Register */
+ __IO uint32_t HcCommandStatus; /* Offset: 0x08 Host Controller CMD Status Register */
+ __IO uint32_t HcInterruptStatus; /* Offset: 0x0C Host Controller Interrupt Status Register */
+ __IO uint32_t HcInterruptEnable; /* Offset: 0x10 Host Controller Interrupt Enable Register */
+ __IO uint32_t HcInterruptDisable; /* Offset: 0x14 Host Controller Interrupt Disable Register */
+ __IO uint32_t HcHCCA; /* Offset: 0x18 Host Controller Communication Area Register */
+ __IO uint32_t HcPeriodCurrentED; /* Offset: 0x1C Host Controller Period Current ED Register */
+ __IO uint32_t HcControlHeadED; /* Offset: 0x20 Host Controller Control Head ED Register */
+ __IO uint32_t HcControlCurrentED; /* Offset: 0x24 Host Controller Control Current ED Register */
+ __IO uint32_t HcBulkHeadED; /* Offset: 0x28 Host Controller Bulk Head ED Register */
+ __IO uint32_t HcBulkCurrentED; /* Offset: 0x2C Host Controller Bulk Current ED Register */
+ __IO uint32_t HcDoneHead; /* Offset: 0x30 Host Controller Done Head Register */
+ __IO uint32_t HcFmInterval; /* Offset: 0x34 Host Controller Frame Interval Register */
+ __I uint32_t HcFmRemaining; /* Offset: 0x38 Host Controller Frame Remaining Register */
+ __I uint32_t HcFmNumber; /* Offset: 0x3C Host Controller Frame Number Register */
+ __IO uint32_t HcPeriodicStart; /* Offset: 0x40 Host Controller Periodic Start Register */
+ __IO uint32_t HcLSThreshold; /* Offset: 0x44 Host Controller Low-speed Threshold Register */
+ __IO uint32_t HcRhDescriptorA; /* Offset: 0x48 Host Controller Root Hub Descriptor A Register */
+ __IO uint32_t HcRhDescriptorB; /* Offset: 0x4C Host Controller Root Hub Descriptor B Register */
+ __IO uint32_t HcRhStatus; /* Offset: 0x50 Host Controller Root Hub Status Register */
+ __IO uint32_t HcRhPortStatus[2]; /* Offset: 0x54 Host Controller Root Hub Port Status [1] */
+ __I uint32_t RESERVE0[105];
+ __IO uint32_t HcPhyControl; /* Offset: 0x200 USB Host Controller PHY Control Register */
+ __IO uint32_t HcMiscControl; /* Offset: 0x204 USB Host Controller Miscellaneous Control Register */
+
+} USBH_T;
+
+
+
+
+/**
+ @addtogroup USBH_CONST USBH Bit Field Definition
+ Constant Definitions for USBH Controller
+@{ */
+
+#define USBH_HcRevision_REV_Pos (0) /*!< USBH_T::HcRevision: REV Position */
+#define USBH_HcRevision_REV_Msk (0xfful << USBH_HcRevision_REV_Pos) /*!< USBH_T::HcRevision: REV Mask */
+
+#define USBH_HcControl_CBSR_Pos (0) /*!< USBH_T::HcControl: CBSR Position */
+#define USBH_HcControl_CBSR_Msk (0x3ul << USBH_HcControl_CBSR_Pos) /*!< USBH_T::HcControl: CBSR Mask */
+
+#define USBH_HcControl_PLE_Pos (2) /*!< USBH_T::HcControl: CBSR Position */
+#define USBH_HcControl_PLE_Msk (0x1ul << USBH_HcControl_PLE_Pos) /*!< USBH_T::HcControl: CBSR Mask */
+
+#define USBH_HcControl_IE_Pos (3) /*!< USBH_T::HcControl: IE Position */
+#define USBH_HcControl_IE_Msk (0x1ul << USBH_HcControl_IE_Pos) /*!< USBH_T::HcControl: IE Mask */
+
+#define USBH_HcControl_CLE_Pos (4) /*!< USBH_T::HcControl: CLE Position */
+#define USBH_HcControl_CLE_Msk (0x1ul << USBH_HcControl_CLE_Pos) /*!< USBH_T::HcControl: CLE Mask */
+
+#define USBH_HcControl_BLE_Pos (5) /*!< USBH_T::HcControl: BLE Position */
+#define USBH_HcControl_BLE_Msk (0x1ul << USBH_HcControl_BLE_Pos) /*!< USBH_T::HcControl: BLE Mask */
+
+#define USBH_HcControl_HCFS_Pos (6) /*!< USBH_T::HcControl: HCFS Position */
+#define USBH_HcControl_HCFS_Msk (0x3ul << USBH_HcControl_HCFS_Pos) /*!< USBH_T::HcControl: HCFS Mask */
+
+#define USBH_HcCommandStatus_HCR_Pos (0) /*!< USBH_T::HcCommandStatus: HCR Position */
+#define USBH_HcCommandStatus_HCR_Msk (0x1ul << USBH_HcCommandStatus_HCR_Pos) /*!< USBH_T::HcCommandStatus: HCR Mask */
+
+#define USBH_HcCommandStatus_CLF_Pos (1) /*!< USBH_T::HcCommandStatus: CLF Position */
+#define USBH_HcCommandStatus_CLF_Msk (0x1ul << USBH_HcCommandStatus_CLF_Pos) /*!< USBH_T::HcCommandStatus: CLF Mask */
+
+#define USBH_HcCommandStatus_BLF_Pos (2) /*!< USBH_T::HcCommandStatus: BLF Position */
+#define USBH_HcCommandStatus_BLF_Msk (0x1ul << USBH_HcCommandStatus_BLF_Pos) /*!< USBH_T::HcCommandStatus: BLF Mask */
+
+#define USBH_HcCommandStatus_SOC_Pos (16) /*!< USBH_T::HcCommandStatus: SOC Position */
+#define USBH_HcCommandStatus_SOC_Msk (0x3ul << USBH_HcCommandStatus_SOC_Pos) /*!< USBH_T::HcCommandStatus: SOC Mask */
+
+#define USBH_HcInterruptStatus_SO_Pos (0) /*!< USBH_T::HcInterruptStatus: SO Position */
+#define USBH_HcInterruptStatus_SO_Msk (0x1ul << USBH_HcInterruptStatus_SO_Pos) /*!< USBH_T::HcInterruptStatus: SO Mask */
+
+#define USBH_HcInterruptStatus_WDH_Pos (1) /*!< USBH_T::HcInterruptStatus: WDH Position */
+#define USBH_HcInterruptStatus_WDH_Msk (0x1ul << USBH_HcInterruptStatus_WDH_Pos) /*!< USBH_T::HcInterruptStatus: WDH Mask */
+
+#define USBH_HcInterruptStatus_SF_Pos (2) /*!< USBH_T::HcInterruptStatus: SF Position */
+#define USBH_HcInterruptStatus_SF_Msk (0x1ul << USBH_HcInterruptStatus_SF_Pos) /*!< USBH_T::HcInterruptStatus: SF Mask */
+
+#define USBH_HcInterruptStatus_RD_Pos (3) /*!< USBH_T::HcInterruptStatus: RD Position */
+#define USBH_HcInterruptStatus_RD_Msk (0x1ul << USBH_HcInterruptStatus_RD_Pos) /*!< USBH_T::HcInterruptStatus: RD Mask */
+
+#define USBH_HcInterruptStatus_FNO_Pos (5) /*!< USBH_T::HcInterruptStatus: FNO Position */
+#define USBH_HcInterruptStatus_FNO_Msk (0x1ul << USBH_HcInterruptStatus_FNO_Pos) /*!< USBH_T::HcInterruptStatus: FNO Mask */
+
+#define USBH_HcInterruptStatus_RHSC_Pos (6) /*!< USBH_T::HcInterruptStatus: RHSC Position */
+#define USBH_HcInterruptStatus_RHSC_Msk (0x1ul << USBH_HcInterruptStatus_RHSC_Pos) /*!< USBH_T::HcInterruptStatus: RHSC Mask */
+
+#define USBH_HcInterruptEnable_SO_Pos (0) /*!< USBH_T::HcInterruptEnable: SO Position */
+#define USBH_HcInterruptEnable_SO_Msk (0x1ul << USBH_HcInterruptEnable_SO_Pos) /*!< USBH_T::HcInterruptEnable: SO Mask */
+
+#define USBH_HcInterruptEnable_WDH_Pos (1) /*!< USBH_T::HcInterruptEnable: WDH Position */
+#define USBH_HcInterruptEnable_WDH_Msk (0x1ul << USBH_HcInterruptEnable_WDH_Pos) /*!< USBH_T::HcInterruptEnable: WDH Mask */
+
+#define USBH_HcInterruptEnable_SF_Pos (2) /*!< USBH_T::HcInterruptEnable: SF Position */
+#define USBH_HcInterruptEnable_SF_Msk (0x1ul << USBH_HcInterruptEnable_SF_Pos) /*!< USBH_T::HcInterruptEnable: SF Mask */
+
+#define USBH_HcInterruptEnable_RD_Pos (3) /*!< USBH_T::HcInterruptEnable: RD Position */
+#define USBH_HcInterruptEnable_RD_Msk (0x1ul << USBH_HcInterruptEnable_RD_Pos) /*!< USBH_T::HcInterruptEnable: RD Mask */
+
+#define USBH_HcInterruptEnable_FNO_Pos (5) /*!< USBH_T::HcInterruptEnable: FNO Position */
+#define USBH_HcInterruptEnable_FNO_Msk (0x1ul << USBH_HcInterruptEnable_FNO_Pos) /*!< USBH_T::HcInterruptEnable: FNO Mask */
+
+#define USBH_HcInterruptEnable_RHSC_Pos (6) /*!< USBH_T::HcInterruptEnable: RHSC Position */
+#define USBH_HcInterruptEnable_RHSC_Msk (0x1ul << USBH_HcInterruptEnable_RHSC_Pos) /*!< USBH_T::HcInterruptEnable: RHSC Mask */
+
+#define USBH_HcInterruptEnable_MIE_Pos (31) /*!< USBH_T::HcInterruptEnable: MIE Position */
+#define USBH_HcInterruptEnable_MIE_Msk (0x1ul << USBH_HcInterruptEnable_MIE_Pos) /*!< USBH_T::HcInterruptEnable: MIE Mask */
+
+#define USBH_HcInterruptDisable_SO_Pos (0) /*!< USBH_T::HcInterruptDisable: SO Position */
+#define USBH_HcInterruptDisable_SO_Msk (0x1ul << USBH_HcInterruptDisable_SO_Pos) /*!< USBH_T::HcInterruptDisable: SO Mask */
+
+#define USBH_HcInterruptDisable_WDH_Pos (1) /*!< USBH_T::HcInterruptDisable: WDH Position */
+#define USBH_HcInterruptDisable_WDH_Msk (0x1ul << USBH_HcInterruptDisable_WDH_Pos) /*!< USBH_T::HcInterruptDisable: WDH Mask */
+
+#define USBH_HcInterruptDisable_SF_Pos (2) /*!< USBH_T::HcInterruptDisable: SF Position */
+#define USBH_HcInterruptDisable_SF_Msk (0x1ul << USBH_HcInterruptDisable_SF_Pos) /*!< USBH_T::HcInterruptDisable: SF Mask */
+
+#define USBH_HcInterruptDisable_RD_Pos (3) /*!< USBH_T::HcInterruptDisable: RD Position */
+#define USBH_HcInterruptDisable_RD_Msk (0x1ul << USBH_HcInterruptDisable_RD_Pos) /*!< USBH_T::HcInterruptDisable: RD Mask */
+
+#define USBH_HcInterruptDisable_FNO_Pos (5) /*!< USBH_T::HcInterruptDisable: FNO Position */
+#define USBH_HcInterruptDisable_FNO_Msk (0x1ul << USBH_HcInterruptDisable_FNO_Pos) /*!< USBH_T::HcInterruptDisable: FNO Mask */
+
+#define USBH_HcInterruptDisable_RHSC_Pos (6) /*!< USBH_T::HcInterruptDisable: RHSC Position */
+#define USBH_HcInterruptDisable_RHSC_Msk (0x1ul << USBH_HcInterruptDisable_RHSC_Pos) /*!< USBH_T::HcInterruptDisable: RHSC Mask */
+
+#define USBH_HcInterruptDisable_MIE_Pos (31) /*!< USBH_T::HcInterruptDisable: MIE Position */
+#define USBH_HcInterruptDisable_MIE_Msk (0x1ul << USBH_HcInterruptDisable_MIE_Pos) /*!< USBH_T::HcInterruptDisable: MIE Mask */
+
+#define USBH_HcHCCA_HCCA_Pos (8) /*!< USBH_T::HcHCCA: HCCA Position */
+#define USBH_HcHCCA_HCCA_Msk (0xfffffful << USBH_HcHCCA_HCCA_Pos) /*!< USBH_T::HcHCCA: HCCA Mask */
+
+#define USBH_HcPeriodCurrentED_PCED_Pos (4) /*!< USBH_T::HcPeriodCurrentED: PCED Position */
+#define USBH_HcPeriodCurrentED_PCED_Msk (0xffffffful << USBH_HcPeriodCurrentED_PCED_Pos) /*!< USBH_T::HcPeriodCurrentED: PCED Mask */
+
+#define USBH_HcControlHeadED_CHED_Pos (4) /*!< USBH_T::HcControlHeadED: CHED Position */
+#define USBH_HcControlHeadED_CHED_Msk (0xffffffful << USBH_HcControlHeadED_CHED_Pos) /*!< USBH_T::HcControlHeadED: CHED Mask */
+
+#define USBH_HcControlCurrentED_CCED_Pos (4) /*!< USBH_T::HcControlCurrentED: CCED Position */
+#define USBH_HcControlCurrentED_CCED_Msk (0xffffffful << USBH_HcControlCurrentED_CCED_Pos) /*!< USBH_T::HcControlCurrentED: CCED Mask */
+
+#define USBH_HcBulkHeadED_BHED_Pos (4) /*!< USBH_T::HcBulkHeadED: BHED Position */
+#define USBH_HcBulkHeadED_BHED_Msk (0xffffffful << USBH_HcBulkHeadED_BHED_Pos) /*!< USBH_T::HcBulkHeadED: BHED Mask */
+
+#define USBH_HcBulkCurrentED_BCED_Pos (4) /*!< USBH_T::HcBulkCurrentED: BCED Position */
+#define USBH_HcBulkCurrentED_BCED_Msk (0xffffffful << USBH_HcBulkCurrentED_BCED_Pos) /*!< USBH_T::HcBulkCurrentED: BCED Mask */
+
+#define USBH_HcDoneHead_DH_Pos (4) /*!< USBH_T::HcDoneHead: DH Position */
+#define USBH_HcDoneHead_DH_Msk (0xffffffful << USBH_HcDoneHead_DH_Pos) /*!< USBH_T::HcDoneHead: DH Mask */
+
+#define USBH_HcFmInterval_FI_Pos (0) /*!< USBH_T::HcFmInterval: FI Position */
+#define USBH_HcFmInterval_FI_Msk (0x3ffful << USBH_HcFmInterval_FI_Pos) /*!< USBH_T::HcFmInterval: FI Mask */
+
+#define USBH_HcFmInterval_FSMPS_Pos (16) /*!< USBH_T::HcFmInterval: FSMPS Position */
+#define USBH_HcFmInterval_FSMPS_Msk (0x7ffful << USBH_HcFmInterval_FSMPS_Pos) /*!< USBH_T::HcFmInterval: FSMPS Mask */
+
+#define USBH_HcFmInterval_FIT_Pos (31) /*!< USBH_T::HcFmInterval: FIT Position */
+#define USBH_HcFmInterval_FIT_Msk (0x1ul << USBH_HcFmInterval_FIT_Pos) /*!< USBH_T::HcFmInterval: FIT Mask */
+
+#define USBH_HcFmRemaining_FR_Pos (0) /*!< USBH_T::HcFmRemaining: FR Position */
+#define USBH_HcFmRemaining_FR_Msk (0x3ffful << USBH_HcFmRemaining_FR_Pos) /*!< USBH_T::HcFmRemaining: FR Mask */
+
+#define USBH_HcFmRemaining_FRT_Pos (31) /*!< USBH_T::HcFmRemaining: FRT Position */
+#define USBH_HcFmRemaining_FRT_Msk (0x1ul << USBH_HcFmRemaining_FRT_Pos) /*!< USBH_T::HcFmRemaining: FRT Mask */
+
+#define USBH_HcFmNumber_FN_Pos (0) /*!< USBH_T::HcFmNumber: FN Position */
+#define USBH_HcFmNumber_FN_Msk (0xfffful << USBH_HcFmNumber_FN_Pos) /*!< USBH_T::HcFmNumber: FN Mask */
+
+#define USBH_HcPeriodicStart_PS_Pos (0) /*!< USBH_T::HcPeriodicStart: PS Position */
+#define USBH_HcPeriodicStart_PS_Msk (0x3ffful << USBH_HcPeriodicStart_PS_Pos) /*!< USBH_T::HcPeriodicStart: PS Mask */
+
+#define USBH_HcLSThreshold_LST_Pos (0) /*!< USBH_T::HcLSThreshold: LST Position */
+#define USBH_HcLSThreshold_LST_Msk (0xffful << USBH_HcLSThreshold_LST_Pos) /*!< USBH_T::HcLSThreshold: LST Mask */
+
+#define USBH_HcRhDescriptorA_NDP_Pos (0) /*!< USBH_T::HcRhDescriptorA: NDP Position */
+#define USBH_HcRhDescriptorA_NDP_Msk (0xfful << USBH_HcRhDescriptorA_NDP_Pos) /*!< USBH_T::HcRhDescriptorA: NDP Mask */
+
+#define USBH_HcRhDescriptorA_PSM_Pos (8) /*!< USBH_T::HcRhDescriptorA: PSM Position */
+#define USBH_HcRhDescriptorA_PSM_Msk (0x1ul << USBH_HcRhDescriptorA_PSM_Pos) /*!< USBH_T::HcRhDescriptorA: PSM Mask */
+
+#define USBH_HcRhDescriptorA_OCPM_Pos (11) /*!< USBH_T::HcRhDescriptorA: OCPM Position */
+#define USBH_HcRhDescriptorA_OCPM_Msk (0x1ul << USBH_HcRhDescriptorA_OCPM_Pos) /*!< USBH_T::HcRhDescriptorA: OCPM Mask */
+
+#define USBH_HcRhDescriptorA_NOCP_Pos (12) /*!< USBH_T::HcRhDescriptorA: NOCP Position */
+#define USBH_HcRhDescriptorA_NOCP_Msk (0x1ul << USBH_HcRhDescriptorA_NOCP_Pos) /*!< USBH_T::HcRhDescriptorA: NOCP Mask */
+
+#define USBH_HcRhDescriptorB_PPCM_Pos (16) /*!< USBH_T::HcRhDescriptorB: PPCM Position */
+#define USBH_HcRhDescriptorB_PPCM_Msk (0xfffful << USBH_HcRhDescriptorB_PPCM_Pos) /*!< USBH_T::HcRhDescriptorB: PPCM Mask */
+
+#define USBH_HcRhStatus_LPS_Pos (0) /*!< USBH_T::HcRhStatus: LPS Position */
+#define USBH_HcRhStatus_LPS_Msk (0x1ul << USBH_HcRhStatus_LPS_Pos) /*!< USBH_T::HcRhStatus: LPS Mask */
+
+#define USBH_HcRhStatus_OCI_Pos (1) /*!< USBH_T::HcRhStatus: OCI Position */
+#define USBH_HcRhStatus_OCI_Msk (0x1ul << USBH_HcRhStatus_OCI_Pos) /*!< USBH_T::HcRhStatus: OCI Mask */
+
+#define USBH_HcRhStatus_DRWE_Pos (15) /*!< USBH_T::HcRhStatus: DRWE Position */
+#define USBH_HcRhStatus_DRWE_Msk (0x1ul << USBH_HcRhStatus_DRWE_Pos) /*!< USBH_T::HcRhStatus: DRWE Mask */
+
+#define USBH_HcRhStatus_LPSC_Pos (16) /*!< USBH_T::HcRhStatus: LPSC Position */
+#define USBH_HcRhStatus_LPSC_Msk (0x1ul << USBH_HcRhStatus_LPSC_Pos) /*!< USBH_T::HcRhStatus: LPSC Mask */
+
+#define USBH_HcRhStatus_OCIC_Pos (17) /*!< USBH_T::HcRhStatus: OCIC Position */
+#define USBH_HcRhStatus_OCIC_Msk (0x1ul << USBH_HcRhStatus_OCIC_Pos) /*!< USBH_T::HcRhStatus: OCIC Mask */
+
+#define USBH_HcRhStatus_CRWE_Pos (31) /*!< USBH_T::HcRhStatus: CRWE Position */
+#define USBH_HcRhStatus_CRWE_Msk (0x1ul << USBH_HcRhStatus_CRWE_Pos) /*!< USBH_T::HcRhStatus: CRWE Mask */
+
+#define USBH_HcRhPortStatus_CCS_Pos (0) /*!< USBH_T::HcRhPortStatus: CCS Position */
+#define USBH_HcRhPortStatus_CCS_Msk (0x1ul << USBH_HcRhPortStatus_CCS_Pos) /*!< USBH_T::HcRhPortStatus: CCS Mask */
+
+#define USBH_HcRhPortStatus_PES_Pos (1) /*!< USBH_T::HcRhPortStatus: PES Position */
+#define USBH_HcRhPortStatus_PES_Msk (0x1ul << USBH_HcRhPortStatus_PES_Pos) /*!< USBH_T::HcRhPortStatus: PES Mask */
+
+#define USBH_HcRhPortStatus_PSS_Pos (2) /*!< USBH_T::HcRhPortStatus: PSS Position */
+#define USBH_HcRhPortStatus_PSS_Msk (0x1ul << USBH_HcRhPortStatus_PSS_Pos) /*!< USBH_T::HcRhPortStatus: PSS Mask */
+
+#define USBH_HcRhPortStatus_POCI_Pos (3) /*!< USBH_T::HcRhPortStatus: POCI Position */
+#define USBH_HcRhPortStatus_POCI_Msk (0x1ul << USBH_HcRhPortStatus_POCI_Pos) /*!< USBH_T::HcRhPortStatus: POCI Mask */
+
+#define USBH_HcRhPortStatus_PRS_Pos (4) /*!< USBH_T::HcRhPortStatus: PRS Position */
+#define USBH_HcRhPortStatus_PRS_Msk (0x1ul << USBH_HcRhPortStatus_PRS_Pos) /*!< USBH_T::HcRhPortStatus: PRS Mask */
+
+#define USBH_HcRhPortStatus_PPS_Pos (8) /*!< USBH_T::HcRhPortStatus: PPS Position */
+#define USBH_HcRhPortStatus_PPS_Msk (0x1ul << USBH_HcRhPortStatus_PPS_Pos) /*!< USBH_T::HcRhPortStatus: PPS Mask */
+
+#define USBH_HcRhPortStatus_LSDA_Pos (9) /*!< USBH_T::HcRhPortStatus: LSDA Position */
+#define USBH_HcRhPortStatus_LSDA_Msk (0x1ul << USBH_HcRhPortStatus_LSDA_Pos) /*!< USBH_T::HcRhPortStatus: LSDA Mask */
+
+#define USBH_HcRhPortStatus_CSC_Pos (16) /*!< USBH_T::HcRhPortStatus: CSC Position */
+#define USBH_HcRhPortStatus_CSC_Msk (0x1ul << USBH_HcRhPortStatus_CSC_Pos) /*!< USBH_T::HcRhPortStatus: CSC Mask */
+
+#define USBH_HcRhPortStatus_PESC_Pos (17) /*!< USBH_T::HcRhPortStatus: PESC Position */
+#define USBH_HcRhPortStatus_PESC_Msk (0x1ul << USBH_HcRhPortStatus_PESC_Pos) /*!< USBH_T::HcRhPortStatus: PESC Mask */
+
+#define USBH_HcRhPortStatus_PSSC_Pos (18) /*!< USBH_T::HcRhPortStatus: PSSC Position */
+#define USBH_HcRhPortStatus_PSSC_Msk (0x1ul << USBH_HcRhPortStatus_PSSC_Pos) /*!< USBH_T::HcRhPortStatus: PSSC Mask */
+
+#define USBH_HcRhPortStatus_OCIC_Pos (19) /*!< USBH_T::HcRhPortStatus: OCIC Position */
+#define USBH_HcRhPortStatus_OCIC_Msk (0x1ul << USBH_HcRhPortStatus_OCIC_Pos) /*!< USBH_T::HcRhPortStatus: OCIC Mask */
+
+#define USBH_HcRhPortStatus_PRSC_Pos (20) /*!< USBH_T::HcRhPortStatus: PRSC Position */
+#define USBH_HcRhPortStatus_PRSC_Msk (0x1ul << USBH_HcRhPortStatus_PRSC_Pos) /*!< USBH_T::HcRhPortStatus: PRSC Mask */
+
+#define USBH_HcPhyControl_STBYEN_Pos (27) /*!< USBH_T::HcPhyControl: STBYEN Position */
+#define USBH_HcPhyControl_STBYEN_Msk (0x1ul << USBH_HcPhyControl_STBYEN_Pos) /*!< USBH_T::HcPhyControl: STBYEN Mask */
+
+#define USBH_HcMiscControl_ABORT_Pos (1) /*!< USBH_T::HcMiscControl: ABORT Position */
+#define USBH_HcMiscControl_ABORT_Msk (0x1ul << USBH_HcMiscControl_ABORT_Pos) /*!< USBH_T::HcMiscControl: ABORT Mask */
+
+#define USBH_HcMiscControl_OCAL_Pos (3) /*!< USBH_T::HcMiscControl: OCAL Position */
+#define USBH_HcMiscControl_OCAL_Msk (0x1ul << USBH_HcMiscControl_OCAL_Pos) /*!< USBH_T::HcMiscControl: OCAL Mask */
+
+#define USBH_HcMiscControl_DPRT1_Pos (16) /*!< USBH_T::HcMiscControl: DPRT1 Position */
+#define USBH_HcMiscControl_DPRT1_Msk (0x1ul << USBH_HcMiscControl_DPRT1_Pos) /*!< USBH_T::HcMiscControl: DPRT1 Mask */
+
+/**@}*/ /* USBH_CONST */
+/**@}*/ /* end of USBH register group */
+
+
+/*---------------------- Watch Dog Timer Controller -------------------------*/
+/**
+ @addtogroup WDT Watch Dog Timer Controller(WDT)
+ Memory Mapped Structure for WDT Controller
+@{ */
+
+
+typedef struct
+{
+
+
+
+
+/**
+ * @var WDT_T::CTL
+ * Offset: 0x00 WDT Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |RSTCNT |Reset WDT Up Counter (Write Protect)
+ * | | |0 = No effect.
+ * | | |1 = Reset the internal 18-bit WDT up counter value.
+ * | | |Note1: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * | | |Note2: This bit will be automatically cleared by hardware.
+ * |[1] |RSTEN |WDT Time-Out Reset Enable Control (Write Protect)
+ * | | |Setting this bit will enable the WDT time-out reset function If the WDT up counter value has not been cleared after the specific WDT reset delay period expires.
+ * | | |0 = WDT time-out reset function Disabled.
+ * | | |1 = WDT time-out reset function Enabled.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[2] |RSTF |WDT Time-Out Reset Flag
+ * | | |This bit indicates the system has been reset by WDT time-out reset or not.
+ * | | |0 = WDT time-out reset did not occur.
+ * | | |1 = WDT time-out reset occurred.
+ * | | |Note: This bit is cleared by writing 1 to it.
+ * |[3] |IF |WDT Time-Out Interrupt Flag
+ * | | |This bit will set to 1 while WDT up counter value reaches the selected WDT time-out interval
+ * | | |0 = WDT time-out interrupt did not occur.
+ * | | |1 = WDT time-out interrupt occurred.
+ * | | |Note: This bit is cleared by writing 1 to it.
+ * |[4] |WKEN |WDT Time-Out Wake-Up Function Control (Write Protect)
+ * | | |If this bit is set to 1, while WDT time-out interrupt flag IF (WDT_CTL[3]) is generated to 1 and interrupt enable bit INTEN (WDT_CTL[6]) is enabled, the WDT time-out interrupt signal will generate a wake-up trigger event to chip.
+ * | | |0 = Wake-up trigger event Disabled if WDT time-out interrupt signal generated.
+ * | | |1 = Wake-up trigger event Enabled if WDT time-out interrupt signal generated.
+ * | | |Note1: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * | | |Note2: Chip can be woken-up by WDT time-out interrupt signal generated only if WDT clock source is selected to 10 kHz oscillator.
+ * |[5] |WKF |WDT Time-Out Wake-Up Flag
+ * | | |This bit indicates the interrupt wake-up flag status of WDT
+ * | | |0 = WDT does not cause chip wake-up.
+ * | | |1 = Chip wake-up from Idle or Power-down mode if WDT time-out interrupt signal generated.
+ * | | |Note1: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * | | |Note2: This bit is cleared by writing 1 to it.
+ * |[6] |INTEN |WDT Time-Out Interrupt Enable Control (Write Protect)
+ * | | |If this bit is enabled, the WDT time-out interrupt signal is generated and inform to CPU.
+ * | | |0 = WDT time-out interrupt Disabled.
+ * | | |1 = WDT time-out interrupt Enabled.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[7] |WDTEN |WDT Enable Control (Write Protect)
+ * | | |0 = WDT Disabled (This action will reset the internal up counter value).
+ * | | |1 = WDT Enabled.
+ * | | |Note1: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * | | |Note2: If CWDTEN[2:0] (combined by Config0[31] and Config0[4:3]) bits is not configure to 111, this bit is forced as 1 and user cannot change this bit to 0.
+ * |[10:8] |TOUTSEL |WDT Time-Out Interval Selection (Write Protect)
+ * | | |These three bits select the time-out interval period for the WDT.
+ * | | |000 = (2^4)*TWDT.
+ * | | |001 = (2^6)*TWDT.
+ * | | |010 = (2^8)*TWDT.
+ * | | |011 = (2^10)*TWDT.
+ * | | |100 = (2^12)*TWDT.
+ * | | |101 = (2^14)*TWDT.
+ * | | |110 = (2^16)*TWDT.
+ * | | |111 = (2^18)*TWDT.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * |[31] |ICEDEBUG |ICE Debug Mode Acknowledge Disable Control (Write Protect)
+ * | | |0 = ICE debug mode acknowledgement affects WDT counting.
+ * | | |WDT up counter will be held while CPU is held by ICE.
+ * | | |1 = ICE debug mode acknowledgement Disabled.
+ * | | |WDT up counter will keep going no matter CPU is held by ICE or not.
+ * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * @var WDT_T::ALTCTL
+ * Offset: 0x04 WDT Alternative Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[1:0] |RSTDSEL |WDT Reset Delay Selection (Write Protect)
+ * | | |When WDT time-out happened, user has a time named WDT Reset Delay Period to clear WDT counter by setting RSTCNT (WDT_CTL[0]) to prevent WDT time-out reset happened.
+ * | | |User can select a suitable setting of RSTDSEL for different WDT Reset Delay Period.
+ * | | |00 = WDT Reset Delay Period is 1026 * WDT_CLK.
+ * | | |01 = WDT Reset Delay Period is 130 * WDT_CLK.
+ * | | |10 = WDT Reset Delay Period is 18 * WDT_CLK.
+ * | | |11 = WDT Reset Delay Period is 3 * WDT_CLK.
+ * | | |Note1: This bit is write protected. Refer to the SYS_REGLCTL register.
+ * | | |Note2: This register will be reset to 0 if WDT time-out reset happened.
+ */
+
+ __IO uint32_t CTL; /* Offset: 0x00 WDT Control Register */
+ __IO uint32_t ALTCTL; /* Offset: 0x04 WDT Alternative Control Register */
+
+} WDT_T;
+
+
+
+/**
+ @addtogroup WDT_CONST WDT Bit Field Definition
+ Constant Definitions for WDT Controller
+@{ */
+
+#define WDT_CTL_RSTCNT_Pos (0) /*!< WDT_T::CTL: RSTCNT Position */
+#define WDT_CTL_RSTCNT_Msk (0x1ul << WDT_CTL_RSTCNT_Pos) /*!< WDT_T::CTL: RSTCNT Mask */
+
+#define WDT_CTL_RSTEN_Pos (1) /*!< WDT_T::CTL: RSTEN Position */
+#define WDT_CTL_RSTEN_Msk (0x1ul << WDT_CTL_RSTEN_Pos) /*!< WDT_T::CTL: RSTEN Mask */
+
+#define WDT_CTL_RSTF_Pos (2) /*!< WDT_T::CTL: RSTF Position */
+#define WDT_CTL_RSTF_Msk (0x1ul << WDT_CTL_RSTF_Pos) /*!< WDT_T::CTL: RSTF Mask */
+
+#define WDT_CTL_IF_Pos (3) /*!< WDT_T::CTL: IF Position */
+#define WDT_CTL_IF_Msk (0x1ul << WDT_CTL_IF_Pos) /*!< WDT_T::CTL: IF Mask */
+
+#define WDT_CTL_WKEN_Pos (4) /*!< WDT_T::CTL: WKEN Position */
+#define WDT_CTL_WKEN_Msk (0x1ul << WDT_CTL_WKEN_Pos) /*!< WDT_T::CTL: WKEN Mask */
+
+#define WDT_CTL_WKF_Pos (5) /*!< WDT_T::CTL: WKF Position */
+#define WDT_CTL_WKF_Msk (0x1ul << WDT_CTL_WKF_Pos) /*!< WDT_T::CTL: WKF Mask */
+
+#define WDT_CTL_INTEN_Pos (6) /*!< WDT_T::CTL: INTEN Position */
+#define WDT_CTL_INTEN_Msk (0x1ul << WDT_CTL_INTEN_Pos) /*!< WDT_T::CTL: INTEN Mask */
+
+#define WDT_CTL_WDTEN_Pos (7) /*!< WDT_T::CTL: WDTEN Position */
+#define WDT_CTL_WDTEN_Msk (0x1ul << WDT_CTL_WDTEN_Pos) /*!< WDT_T::CTL: WDTEN Mask */
+
+#define WDT_CTL_TOUTSEL_Pos (8) /*!< WDT_T::CTL: TOUTSEL Position */
+#define WDT_CTL_TOUTSEL_Msk (0x7ul << WDT_CTL_TOUTSEL_Pos) /*!< WDT_T::CTL: TOUTSEL Mask */
+
+#define WDT_CTL_ICEDEBUG_Pos (31) /*!< WDT_T::CTL: ICEDEBUG Position */
+#define WDT_CTL_ICEDEBUG_Msk (0x1ul << WDT_CTL_ICEDEBUG_Pos) /*!< WDT_T::CTL: ICEDEBUG Mask */
+
+#define WDT_ALTCTL_RSTDSEL_Pos (0) /*!< WDT_T::ALTCTL: RSTDSEL Position */
+#define WDT_ALTCTL_RSTDSEL_Msk (0x3ul << WDT_ALTCTL_RSTDSEL_Pos) /*!< WDT_T::ALTCTL: RSTDSEL Mask */
+
+/**@}*/ /* WDT_CONST */
+/**@}*/ /* end of WDT register group */
+
+
+/*---------------------- Window Watchdog Timer -------------------------*/
+/**
+ @addtogroup WWDT Window Watchdog Timer(WWDT)
+ Memory Mapped Structure for WWDT Controller
+@{ */
+
+
+typedef struct
+{
+
+
+
+
+/**
+ * @var WWDT_T::RLDCNT
+ * Offset: 0x00 WWDT Reload Counter Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[31:0] |WWDT_RLDCNT|WWDT Reload Counter Register
+ * | | |Writing 0x00005AA5 to this register will reload the WWDT counter value to 0x3F.
+ * | | |Note: User can only write WWDT_RLDCNT register to reload WWDT counter value when current WWDT counter value between 0 and CMPDAT (WWDT_CTL[21:16]).
+ * | | |If user writes WWDT_RLDCNT when current WWDT counter value is larger than CMPDAT , WWDT reset signal will generate immediately.
+ * @var WWDT_T::CTL
+ * Offset: 0x04 WWDT Control Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |WWDTEN |WWDT Enable Control Bit
+ * | | |Set this bit to enable WWDT counter counting.
+ * | | |0 = WWDT counter is stopped.
+ * | | |1 = WWDT counter is starting counting.
+ * |[1] |INTEN |WWDT Interrupt Enable Control Bit
+ * | | |If this bit is enabled, the WWDT counter compare match interrupt signal is generated and inform to CPU.
+ * | | |0 = WWDT counter compare match interrupt Disabled.
+ * | | |1 = WWDT counter compare match interrupt Enabled.
+ * |[11:8] |PSCSEL |WWDT Counter Prescale Period Selection
+ * | | |0000 = Pre-scale is 1; Max time-out period is 1 * 64 * TWWDT.
+ * | | |0001 = Pre-scale is 2; Max time-out period is 2 * 64 * TWWDT.
+ * | | |0010 = Pre-scale is 4; Max time-out period is 4 * 64 * TWWDT.
+ * | | |0011 = Pre-scale is 8; Max time-out period is 8 * 64 * TWWDT.
+ * | | |0100 = Pre-scale is 16; Max time-out period is 16 * 64 * TWWDT.
+ * | | |0101 = Pre-scale is 32; Max time-out period is 32 * 64 * TWWDT.
+ * | | |0110 = Pre-scale is 64; Max time-out period is 64 * 64 * TWWDT.
+ * | | |0111 = Pre-scale is 128; Max time-out period is 128 * 64 * TWWDT.
+ * | | |1000 = Pre-scale is 192; Max time-out period is 192 * 64 * TWWDT.
+ * | | |1001 = Pre-scale is 256; Max time-out period is 256 * 64 * TWWDT.
+ * | | |1010 = Pre-scale is 384; Max time-out period is 384 * 64 * TWWDT.
+ * | | |1011 = Pre-scale is 512; Max time-out period is 512 * 64 * TWWDT.
+ * | | |1100 = Pre-scale is 768; Max time-out period is 768 * 64 * TWWDT.
+ * | | |1101 = Pre-scale is 1024; Max time-out period is 1024 * 64 * TWWDT.
+ * | | |1110 = Pre-scale is 1536; Max time-out period is 1536 * 64 * TWWDT.
+ * | | |1111 = Pre-scale is 2048; Max time-out period is 2048 * 64 * TWWDT.
+ * |[21:16] |CMPDAT |WWDT Window Compare Register
+ * | | |Set this register to adjust the valid reload window.
+ * | | |Note: User can only write WWDT_RLDCNT register to reload WWDT counter value when current WWDT counter value between 0 and CMPDAT.
+ * | | |If user writes WWDT_RLDCNT register when current WWDT counter value larger than CMPDAT, WWDT reset signal will generate immediately.
+ * |[31] |ICEDEBUG |ICE Debug Mode Acknowledge Disable Control
+ * | | |0 = ICE debug mode acknowledgement effects WWDT counting.
+ * | | |WWDT down counter will be held while CPU is held by ICE.
+ * | | |1 = ICE debug mode acknowledgement Disabled.
+ * | | |WWDT down counter will keep going no matter CPU is held by ICE or not.
+ * @var WWDT_T::STATUS
+ * Offset: 0x08 WWDT Status Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[0] |WWDTIF |WWDT Compare Match Interrupt Flag
+ * | | |This bit indicates the interrupt flag status of WWDT while WWDT counter value matches CMPDAT (WWDT_CTL[21:16]).
+ * | | |0 = No effect.
+ * | | |1 = WWDT counter value matches CMPDAT.
+ * | | |Note: This bit is cleared by writing 1 to it.
+ * |[1] |WWDTRF |WWDT Timer-Out Reset Flag
+ * | | |This bit indicates the system has been reset by WWDT time-out reset or not.
+ * | | |0 = WWDT time-out reset did not occur.
+ * | | |1 = WWDT time-out reset occurred.
+ * | | |Note: This bit is cleared by writing 1 to it.
+ * @var WWDT_T::CNT
+ * Offset: 0x0C WWDT Counter Value Register
+ * ---------------------------------------------------------------------------------------------------
+ * |Bits |Field |Descriptions
+ * | :----: | :----: | :---- |
+ * |[5:0] |CNTDAT |WWDT Counter Value
+ * | | |CNTDAT will be updated continuously to monitor 6-bit WWDT down counter value.
+ */
+
+ __O uint32_t RLDCNT; /* Offset: 0x00 WWDT Reload Counter Register */
+ __IO uint32_t CTL; /* Offset: 0x04 WWDT Control Register */
+ __IO uint32_t STATUS; /* Offset: 0x08 WWDT Status Register */
+ __I uint32_t CNT; /* Offset: 0x0C WWDT Counter Value Register */
+
+} WWDT_T;
+
+
+
+/**
+ @addtogroup WWDT_CONST WWDT Bit Field Definition
+ Constant Definitions for WWDT Controller
+@{ */
+
+#define WWDT_RLDCNT_WWDT_RLDCNT_Pos (0) /*!< WWDT_T::RLDCNT: WWDT_RLDCNT Position */
+#define WWDT_RLDCNT_WWDT_RLDCNT_Msk (0xfffffffful << WWDT_RLDCNT_WWDT_RLDCNT_Pos) /*!< WWDT_T::RLDCNT: WWDT_RLDCNT Mask */
+
+#define WWDT_CTL_WWDTEN_Pos (0) /*!< WWDT_T::CTL: WWDTEN Position */
+#define WWDT_CTL_WWDTEN_Msk (0x1ul << WWDT_CTL_WWDTEN_Pos) /*!< WWDT_T::CTL: WWDTEN Mask */
+
+#define WWDT_CTL_INTEN_Pos (1) /*!< WWDT_T::CTL: INTEN Position */
+#define WWDT_CTL_INTEN_Msk (0x1ul << WWDT_CTL_INTEN_Pos) /*!< WWDT_T::CTL: INTEN Mask */
+
+#define WWDT_CTL_PSCSEL_Pos (8) /*!< WWDT_T::CTL: PSCSEL Position */
+#define WWDT_CTL_PSCSEL_Msk (0xful << WWDT_CTL_PSCSEL_Pos) /*!< WWDT_T::CTL: PSCSEL Mask */
+
+#define WWDT_CTL_CMPDAT_Pos (16) /*!< WWDT_T::CTL: CMPDAT Position */
+#define WWDT_CTL_CMPDAT_Msk (0x3ful << WWDT_CTL_CMPDAT_Pos) /*!< WWDT_T::CTL: CMPDAT Mask */
+
+#define WWDT_CTL_ICEDEBUG_Pos (31) /*!< WWDT_T::CTL: ICEDEBUG Position */
+#define WWDT_CTL_ICEDEBUG_Msk (0x1ul << WWDT_CTL_ICEDEBUG_Pos) /*!< WWDT_T::CTL: ICEDEBUG Mask */
+
+#define WWDT_STATUS_WWDTIF_Pos (0) /*!< WWDT_T::STATUS: WWDTIF Position */
+#define WWDT_STATUS_WWDTIF_Msk (0x1ul << WWDT_STATUS_WWDTIF_Pos) /*!< WWDT_T::STATUS: WWDTIF Mask */
+
+#define WWDT_STATUS_WWDTRF_Pos (1) /*!< WWDT_T::STATUS: WWDTRF Position */
+#define WWDT_STATUS_WWDTRF_Msk (0x1ul << WWDT_STATUS_WWDTRF_Pos) /*!< WWDT_T::STATUS: WWDTRF Mask */
+
+#define WWDT_CNT_CNTDAT_Pos (0) /*!< WWDT_T::CNT: CNTDAT Position */
+#define WWDT_CNT_CNTDAT_Msk (0x3ful << WWDT_CNT_CNTDAT_Pos) /*!< WWDT_T::CNT: CNTDAT Mask */
+
+/**@}*/ /* WWDT_CONST */
+/**@}*/ /* end of WWDT register group */
+
+
+/**@}*/ /* end of REGISTER group */
+
+
+/******************************************************************************/
+/* Peripheral memory map */
+/******************************************************************************/
+/** @addtogroup MemoryMap Memory Mapping
+ @{
+*/
+
+/* Peripheral and SRAM base address */
+#define SRAM_BASE (0x20000000UL) /*!< (SRAM ) Base Address */
+#define PERIPH_BASE (0x40000000UL) /*!< (Peripheral) Base Address */
+
+
+/* Peripheral memory map */
+#define AHBPERIPH_BASE PERIPH_BASE
+#define APBPERIPH_BASE (PERIPH_BASE + 0x00040000)
+
+/*!< AHB peripherals */
+#define GCR_BASE (AHBPERIPH_BASE + 0x00000)
+#define CLK_BASE (AHBPERIPH_BASE + 0x00200)
+#define INT_BASE (AHBPERIPH_BASE + 0x00300)
+#define GPIO_BASE (AHBPERIPH_BASE + 0x04000)
+#define GPIOA_BASE (AHBPERIPH_BASE + 0x04000)
+#define GPIOB_BASE (AHBPERIPH_BASE + 0x04040)
+#define GPIOC_BASE (AHBPERIPH_BASE + 0x04080)
+#define GPIOD_BASE (AHBPERIPH_BASE + 0x040C0)
+#define GPIOE_BASE (AHBPERIPH_BASE + 0x04100)
+#define GPIOF_BASE (AHBPERIPH_BASE + 0x04140)
+#define GPIO_DBCTL_BASE (AHBPERIPH_BASE + 0x04440)
+#define GPIO_PIN_DATA_BASE (AHBPERIPH_BASE + 0x04800)
+#define PDMA_BASE (AHBPERIPH_BASE + 0x08000)
+#define USBH_BASE (AHBPERIPH_BASE + 0x09000)
+#define FMC_BASE (AHBPERIPH_BASE + 0x0C000)
+#define EBI_BASE (AHBPERIPH_BASE + 0x10000)
+#define CRC_BASE (AHBPERIPH_BASE + 0x31000)
+
+/*!< APB0 peripherals */
+#define WDT_BASE (APBPERIPH_BASE + 0x00000)
+#define WWDT_BASE (APBPERIPH_BASE + 0x00100)
+#define TMR01_BASE (APBPERIPH_BASE + 0x10000)
+#define PWM0_BASE (APBPERIPH_BASE + 0x18000)
+#define SPI0_BASE (APBPERIPH_BASE + 0x20000)
+#define SPI2_BASE (APBPERIPH_BASE + 0x22000)
+#define UART0_BASE (APBPERIPH_BASE + 0x30000)
+#define UART2_BASE (APBPERIPH_BASE + 0x32000)
+#define I2C0_BASE (APBPERIPH_BASE + 0x40000)
+#define SC0_BASE (APBPERIPH_BASE + 0x50000)
+#define CAN0_BASE (APBPERIPH_BASE + 0x60000)
+#define USBD_BASE (APBPERIPH_BASE + 0x80000)
+#define TK_BASE (APBPERIPH_BASE + 0xA2000)
+
+/*!< APB1 peripherals */
+#define RTC_BASE (APBPERIPH_BASE + 0x01000)
+#define EADC0_BASE (APBPERIPH_BASE + 0x03000)
+#define ACMP01_BASE (APBPERIPH_BASE + 0x05000)
+#define DAC_BASE (APBPERIPH_BASE + 0x07000)
+#define OTG_BASE (APBPERIPH_BASE + 0x0D000)
+#define TMR23_BASE (APBPERIPH_BASE + 0x11000)
+#define PWM1_BASE (APBPERIPH_BASE + 0x19000)
+#define SPI1_BASE (APBPERIPH_BASE + 0x21000)
+#define UART1_BASE (APBPERIPH_BASE + 0x31000)
+#define UART3_BASE (APBPERIPH_BASE + 0x33000)
+#define I2C1_BASE (APBPERIPH_BASE + 0x41000)
+/*@}*/ /* end of group MemoryMap */
+
+
+/******************************************************************************/
+/* Peripheral declaration */
+/******************************************************************************/
+/** @addtogroup PeripheralDecl Peripheral Declaration
+ @{
+*/
+
+
+#define SYS ((SYS_T *) GCR_BASE)
+#define SYSINT ((SYS_INT_T *) INT_BASE)
+#define CLK ((CLK_T *) CLK_BASE)
+#define PA ((GPIO_T *) GPIOA_BASE)
+#define PB ((GPIO_T *) GPIOB_BASE)
+#define PC ((GPIO_T *) GPIOC_BASE)
+#define PD ((GPIO_T *) GPIOD_BASE)
+#define PE ((GPIO_T *) GPIOE_BASE)
+#define PF ((GPIO_T *) GPIOF_BASE)
+#define GPIO ((GPIO_DBCTL_T *) GPIO_DBCTL_BASE)
+#define PDMA ((PDMA_T *) PDMA_BASE)
+#define USBH ((USBH_T *) USBH_BASE)
+#define FMC ((FMC_T *) FMC_BASE)
+#define EBI ((EBI_T *) EBI_BASE)
+#define CRC ((CRC_T *) CRC_BASE)
+
+#define WDT ((WDT_T *) WDT_BASE)
+#define WWDT ((WWDT_T *) WWDT_BASE)
+#define RTC ((RTC_T *) RTC_BASE)
+#define EADC ((EADC_T *) EADC0_BASE)
+#define ACMP01 ((ACMP_T *) ACMP01_BASE)
+
+#define USBD ((USBD_T *) USBD_BASE)
+#define OTG ((OTG_T *) OTG_BASE)
+#define TIMER0 ((TIMER_T *) TMR01_BASE)
+#define TIMER1 ((TIMER_T *) (TMR01_BASE + 0x20))
+#define TIMER2 ((TIMER_T *) TMR23_BASE)
+#define TIMER3 ((TIMER_T *) (TMR23_BASE+ 0x20))
+#define PWM0 ((PWM_T *) PWM0_BASE)
+#define PWM1 ((PWM_T *) PWM1_BASE)
+#define DAC ((DAC_T *) DAC_BASE)
+#define SPI0 ((SPI_T *) SPI0_BASE)
+#define SPI1 ((SPI_T *) SPI1_BASE)
+#define SPI2 ((SPI_T *) SPI2_BASE)
+#define UART0 ((UART_T *) UART0_BASE)
+#define UART1 ((UART_T *) UART1_BASE)
+#define UART2 ((UART_T *) UART2_BASE)
+#define UART3 ((UART_T *) UART3_BASE)
+#define I2C0 ((I2C_T *) I2C0_BASE)
+#define I2C1 ((I2C_T *) I2C1_BASE)
+#define SC0 ((SC_T *) SC0_BASE)
+#define CAN0 ((CAN_T *) CAN0_BASE)
+#define TK ((TK_T *) TK_BASE)
+
+/* One Bit Mask Definitions */
+#define BIT0 0x00000001
+#define BIT1 0x00000002
+#define BIT2 0x00000004
+#define BIT3 0x00000008
+#define BIT4 0x00000010
+#define BIT5 0x00000020
+#define BIT6 0x00000040
+#define BIT7 0x00000080
+#define BIT8 0x00000100
+#define BIT9 0x00000200
+#define BIT10 0x00000400
+#define BIT11 0x00000800
+#define BIT12 0x00001000
+#define BIT13 0x00002000
+#define BIT14 0x00004000
+#define BIT15 0x00008000
+#define BIT16 0x00010000
+#define BIT17 0x00020000
+#define BIT18 0x00040000
+#define BIT19 0x00080000
+#define BIT20 0x00100000
+#define BIT21 0x00200000
+#define BIT22 0x00400000
+#define BIT23 0x00800000
+#define BIT24 0x01000000
+#define BIT25 0x02000000
+#define BIT26 0x04000000
+#define BIT27 0x08000000
+#define BIT28 0x10000000
+#define BIT29 0x20000000
+#define BIT30 0x40000000
+#define BIT31 0x80000000
+
+/* Byte Mask Definitions */
+#define BYTE0_Msk (0x000000FF)
+#define BYTE1_Msk (0x0000FF00)
+#define BYTE2_Msk (0x00FF0000)
+#define BYTE3_Msk (0xFF000000)
+
+#define _GET_BYTE0(u32Param) (((u32Param) & BYTE0_Msk) ) /*!< Extract Byte 0 (Bit 0~ 7) from parameter u32Param */
+#define _GET_BYTE1(u32Param) (((u32Param) & BYTE1_Msk) >> 8) /*!< Extract Byte 1 (Bit 8~15) from parameter u32Param */
+#define _GET_BYTE2(u32Param) (((u32Param) & BYTE2_Msk) >> 16) /*!< Extract Byte 2 (Bit 16~23) from parameter u32Param */
+#define _GET_BYTE3(u32Param) (((u32Param) & BYTE3_Msk) >> 24) /*!< Extract Byte 3 (Bit 24~31) from parameter u32Param */
+
+#ifndef TRUE
+# define TRUE 1
+#endif
+#ifndef FALSE
+# define FALSE 0
+#endif
+
+#ifndef NULL
+#define NULL 0
+#endif
+
+#include "sys.h"
+#include "clk.h"
+#include "gpio.h"
+#include "i2c.h"
+#include "crc.h"
+#include "ebi.h"
+#include "rtc.h"
+#include "timer.h"
+#include "wdt.h"
+#include "wwdt.h"
+#include "spi.h"
+#include "sc.h"
+#include "scuart.h"
+#include "acmp.h"
+#include "eadc.h"
+#include "dac.h"
+#include "can.h"
+#include "usbd.h"
+#include "fmc.h"
+#include "uart.h"
+#include "pwm.h"
+#include "pdma.h"
+#include "tk.h"
+#include "otg.h"
+
+typedef volatile unsigned char vu8;
+typedef volatile unsigned long vu32;
+typedef volatile unsigned short vu16;
+#define M8(adr) (*((vu8 *) (adr)))
+#define M16(adr) (*((vu16 *) (adr)))
+#define M32(adr) (*((vu32 *) (adr)))
+
+#define outpw(port,value) (*((volatile unsigned int *)(port))=(value))
+#define inpw(port) (*((volatile unsigned int *)(port)))
+#define outpb(port,value) (*((volatile unsigned char *)(port))=(value))
+#define inpb(port) (*((volatile unsigned char *)(port)))
+#define outps(port,value) (*((volatile unsigned short *)(port))=(value))
+#define inps(port) (*((volatile unsigned short *)(port)))
+
+#define outp32(port,value) (*((volatile unsigned int *)(port))=(value))
+#define inp32(port) (*((volatile unsigned int *)(port)))
+#define outp8(port,value) (*((volatile unsigned char *)(port))=(value))
+#define inp8(port) (*((volatile unsigned char *)(port)))
+#define outp16(port,value) (*((volatile unsigned short *)(port))=(value))
+#define inp16(port) (*((volatile unsigned short *)(port)))
+
+/*@}*/ /* end of group PeripheralDecl */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __M451SERIES_H__ */
+
+/*** (C) COPYRIGHT 2014~2015 Nuvoton Technology Corp. ***/
+
+
+
diff --git a/bsp/nuvoton_m451/Libraries/Device/Nuvoton/M451Series/Include/system_M451Series.h b/bsp/nuvoton_m451/Libraries/Device/Nuvoton/M451Series/Include/system_M451Series.h
new file mode 100644
index 0000000000000000000000000000000000000000..edb80e509a3214337d4f7c7b5d78efa972734c83
--- /dev/null
+++ b/bsp/nuvoton_m451/Libraries/Device/Nuvoton/M451Series/Include/system_M451Series.h
@@ -0,0 +1,75 @@
+/******************************************************************************
+ * @file system_M451Series.h
+ * @version V0.10
+ * $Revision: 7 $
+ * $Date: 15/09/02 10:02a $
+ * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File for M451 Series MCU
+ *
+ * @note
+ * Copyright (C) 2013~2015 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+
+#ifndef __SYSTEM_M451SERIES_H__
+#define __SYSTEM_M451SERIES_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Macro Definition */
+/*---------------------------------------------------------------------------------------------------------*/
+#ifndef DEBUG_PORT
+# define DEBUG_PORT UART0 /*!< Select Debug Port which is used for retarget.c to output debug message to UART */
+#endif
+
+
+/*----------------------------------------------------------------------------
+ Define clocks
+ *----------------------------------------------------------------------------*/
+
+#define __HSI (12000000UL) /*!< PLL default output is 72MHz */
+#define __HXT (12000000UL) /*!< External Crystal Clock Frequency */
+#define __LXT (32768UL) /*!< External Crystal Clock Frequency 32.768KHz */
+#define __HIRC (22118400UL) /*!< Internal 22M RC Oscillator Frequency */
+#define __LIRC (10000UL) /*!< Internal 10K RC Oscillator Frequency */
+#define __SYS_OSC_CLK ( ___HSI) /* Main oscillator frequency */
+
+
+#define __SYSTEM_CLOCK (1*__HXT)
+
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
+extern uint32_t CyclesPerUs; /*!< Cycles per micro second */
+extern uint32_t PllClock; /*!< PLL Output Clock Frequency */
+
+
+/**
+ * Initialize the system
+ *
+ * @param None
+ * @return None
+ *
+ * @brief Setup the microcontroller system.
+ * Initialize the System and update the SystemCoreClock variable.
+ */
+extern void SystemInit(void);
+
+/**
+ * Update SystemCoreClock variable
+ *
+ * @param None
+ * @return None
+ *
+ * @brief Updates the SystemCoreClock with current core Clock
+ * retrieved from cpu registers.
+ */
+extern void SystemCoreClockUpdate(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __SYSTEM_M451SERIES_H__ */
+/*** (C) COPYRIGHT 2013~2015 Nuvoton Technology Corp. ***/
diff --git a/bsp/nuvoton_m451/Libraries/Device/Nuvoton/M451Series/Source/ARM/startup_M451Series.s b/bsp/nuvoton_m451/Libraries/Device/Nuvoton/M451Series/Source/ARM/startup_M451Series.s
new file mode 100644
index 0000000000000000000000000000000000000000..c083f20bf8b86e3c75552b240908793c7982edec
--- /dev/null
+++ b/bsp/nuvoton_m451/Libraries/Device/Nuvoton/M451Series/Source/ARM/startup_M451Series.s
@@ -0,0 +1,376 @@
+;/******************************************************************************
+; * @file startup_M451Series.s
+; * @version V0.10
+; * $Revision: 5 $
+; * $Date: 14/12/24 10:20a $
+; * @brief CMSIS Cortex-M4 Core Device Startup File for M451 Series MCU
+; *
+; * @note
+; * Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved.
+;*****************************************************************************/
+;/*
+;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+;*/
+
+
+; Stack Configuration
+; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;
+
+ ; User may overwrite stack size setting by pre-defined symbol
+ IF :LNOT: :DEF: Stack_Size
+Stack_Size EQU 0x00000400
+ ENDIF
+
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem SPACE Stack_Size
+__initial_sp
+
+
+; Heap Configuration
+; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;
+
+ IF :LNOT: :DEF: Heap_Size
+Heap_Size EQU 0x00000000
+ ENDIF
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem SPACE Heap_Size
+__heap_limit
+
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD BOD_IRQHandler ; 0: Brown Out detection
+ DCD IRC_IRQHandler ; 1: Internal RC
+ DCD PWRWU_IRQHandler ; 2: Power down wake up
+ DCD RAMPE_IRQHandler ; 3: RAM parity error
+ DCD CLKFAIL_IRQHandler ; 4: Clock detection fail
+ DCD Default_Handler ; 5: Reserved
+ DCD RTC_IRQHandler ; 6: Real Time Clock
+ DCD TAMPER_IRQHandler ; 7: Tamper detection
+ DCD WDT_IRQHandler ; 8: Watchdog timer
+ DCD WWDT_IRQHandler ; 9: Window watchdog timer
+ DCD EINT0_IRQHandler ; 10: External Input 0
+ DCD EINT1_IRQHandler ; 11: External Input 1
+ DCD EINT2_IRQHandler ; 12: External Input 2
+ DCD EINT3_IRQHandler ; 13: External Input 3
+ DCD EINT4_IRQHandler ; 14: External Input 4
+ DCD EINT5_IRQHandler ; 15: External Input 5
+ DCD GPA_IRQHandler ; 16: GPIO Port A
+ DCD GPB_IRQHandler ; 17: GPIO Port B
+ DCD GPC_IRQHandler ; 18: GPIO Port C
+ DCD GPD_IRQHandler ; 19: GPIO Port D
+ DCD GPE_IRQHandler ; 20: GPIO Port E
+ DCD GPF_IRQHandler ; 21: GPIO Port F
+ DCD SPI0_IRQHandler ; 22: SPI0
+ DCD SPI1_IRQHandler ; 23: SPI1
+ DCD BRAKE0_IRQHandler ; 24:
+ DCD PWM0P0_IRQHandler ; 25:
+ DCD PWM0P1_IRQHandler ; 26:
+ DCD PWM0P2_IRQHandler ; 27:
+ DCD BRAKE1_IRQHandler ; 28:
+ DCD PWM1P0_IRQHandler ; 29:
+ DCD PWM1P1_IRQHandler ; 30:
+ DCD PWM1P2_IRQHandler ; 31:
+ DCD TMR0_IRQHandler ; 32: Timer 0
+ DCD TMR1_IRQHandler ; 33: Timer 1
+ DCD TMR2_IRQHandler ; 34: Timer 2
+ DCD TMR3_IRQHandler ; 35: Timer 3
+ DCD UART0_IRQHandler ; 36: UART0
+ DCD UART1_IRQHandler ; 37: UART1
+ DCD I2C0_IRQHandler ; 38: I2C0
+ DCD I2C1_IRQHandler ; 39: I2C1
+ DCD PDMA_IRQHandler ; 40: Peripheral DMA
+ DCD DAC_IRQHandler ; 41: DAC
+ DCD ADC00_IRQHandler ; 42: ADC0 interrupt source 0
+ DCD ADC01_IRQHandler ; 43: ADC0 interrupt source 1
+ DCD ACMP01_IRQHandler ; 44: ACMP0 and ACMP1
+ DCD Default_Handler ; 45: Reserved
+ DCD ADC02_IRQHandler ; 46: ADC0 interrupt source 2
+ DCD ADC03_IRQHandler ; 47: ADC0 interrupt source 3
+ DCD UART2_IRQHandler ; 48: UART2
+ DCD UART3_IRQHandler ; 49: UART3
+ DCD Default_Handler ; 50: Reserved
+ DCD SPI2_IRQHandler ; 51: SPI2
+ DCD Default_Handler ; 52: Reserved
+ DCD USBD_IRQHandler ; 53: USB device
+ DCD USBH_IRQHandler ; 54: USB host
+ DCD USBOTG_IRQHandler ; 55: USB OTG
+ DCD CAN0_IRQHandler ; 56: CAN0
+ DCD Default_Handler ; 57: Reserved
+ DCD SC0_IRQHandler ; 58:
+ DCD Default_Handler ; 59: Reserved.
+ DCD Default_Handler ; 60:
+ DCD Default_Handler ; 61:
+ DCD Default_Handler ; 62:
+ DCD TK_IRQHandler ; 63:
+
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+ AREA |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+
+ LDR R0, =0x40000100
+ ; Unlock Register
+ LDR R1, =0x59
+ STR R1, [R0]
+ LDR R1, =0x16
+ STR R1, [R0]
+ LDR R1, =0x88
+ STR R1, [R0]
+
+ ; Init POR
+ LDR R2, =0x40000024
+ LDR R1, =0x00005AA5
+ STR R1, [R2]
+
+ ; Select INV Type
+ LDR R2, =0x40000200
+ LDR R1, [R2]
+ BIC R1, R1, #0x1000
+ STR R1, [R2]
+
+ ; Lock register
+ MOVS R1, #0
+ STR R1, [R0]
+
+
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+MemManage_Handler\
+ PROC
+ EXPORT MemManage_Handler [WEAK]
+ B .
+ ENDP
+BusFault_Handler\
+ PROC
+ EXPORT BusFault_Handler [WEAK]
+ B .
+ ENDP
+UsageFault_Handler\
+ PROC
+ EXPORT UsageFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+DebugMon_Handler\
+ PROC
+ EXPORT DebugMon_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler\
+ PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler\
+ PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+
+ EXPORT BOD_IRQHandler [WEAK]
+ EXPORT IRC_IRQHandler [WEAK]
+ EXPORT PWRWU_IRQHandler [WEAK]
+ EXPORT RAMPE_IRQHandler [WEAK]
+ EXPORT CLKFAIL_IRQHandler [WEAK]
+ EXPORT RTC_IRQHandler [WEAK]
+ EXPORT TAMPER_IRQHandler [WEAK]
+ EXPORT WDT_IRQHandler [WEAK]
+ EXPORT WWDT_IRQHandler [WEAK]
+ EXPORT EINT0_IRQHandler [WEAK]
+ EXPORT EINT1_IRQHandler [WEAK]
+ EXPORT EINT2_IRQHandler [WEAK]
+ EXPORT EINT3_IRQHandler [WEAK]
+ EXPORT EINT4_IRQHandler [WEAK]
+ EXPORT EINT5_IRQHandler [WEAK]
+ EXPORT GPA_IRQHandler [WEAK]
+ EXPORT GPB_IRQHandler [WEAK]
+ EXPORT GPC_IRQHandler [WEAK]
+ EXPORT GPD_IRQHandler [WEAK]
+ EXPORT GPE_IRQHandler [WEAK]
+ EXPORT GPF_IRQHandler [WEAK]
+ EXPORT SPI0_IRQHandler [WEAK]
+ EXPORT SPI1_IRQHandler [WEAK]
+ EXPORT BRAKE0_IRQHandler [WEAK]
+ EXPORT PWM0P0_IRQHandler [WEAK]
+ EXPORT PWM0P1_IRQHandler [WEAK]
+ EXPORT PWM0P2_IRQHandler [WEAK]
+ EXPORT BRAKE1_IRQHandler [WEAK]
+ EXPORT PWM1P0_IRQHandler [WEAK]
+ EXPORT PWM1P1_IRQHandler [WEAK]
+ EXPORT PWM1P2_IRQHandler [WEAK]
+ EXPORT TMR0_IRQHandler [WEAK]
+ EXPORT TMR1_IRQHandler [WEAK]
+ EXPORT TMR2_IRQHandler [WEAK]
+ EXPORT TMR3_IRQHandler [WEAK]
+ EXPORT UART0_IRQHandler [WEAK]
+ EXPORT UART1_IRQHandler [WEAK]
+ EXPORT I2C0_IRQHandler [WEAK]
+ EXPORT I2C1_IRQHandler [WEAK]
+ EXPORT PDMA_IRQHandler [WEAK]
+ EXPORT DAC_IRQHandler [WEAK]
+ EXPORT ADC00_IRQHandler [WEAK]
+ EXPORT ADC01_IRQHandler [WEAK]
+ EXPORT ACMP01_IRQHandler [WEAK]
+ EXPORT ADC02_IRQHandler [WEAK]
+ EXPORT ADC03_IRQHandler [WEAK]
+ EXPORT UART2_IRQHandler [WEAK]
+ EXPORT UART3_IRQHandler [WEAK]
+ EXPORT SPI2_IRQHandler [WEAK]
+ EXPORT USBD_IRQHandler [WEAK]
+ EXPORT USBH_IRQHandler [WEAK]
+ EXPORT USBOTG_IRQHandler [WEAK]
+ EXPORT CAN0_IRQHandler [WEAK]
+ EXPORT SC0_IRQHandler [WEAK]
+ EXPORT TK_IRQHandler [WEAK]
+
+BOD_IRQHandler
+IRC_IRQHandler
+PWRWU_IRQHandler
+RAMPE_IRQHandler
+CLKFAIL_IRQHandler
+RTC_IRQHandler
+TAMPER_IRQHandler
+WDT_IRQHandler
+WWDT_IRQHandler
+EINT0_IRQHandler
+EINT1_IRQHandler
+EINT2_IRQHandler
+EINT3_IRQHandler
+EINT4_IRQHandler
+EINT5_IRQHandler
+GPA_IRQHandler
+GPB_IRQHandler
+GPC_IRQHandler
+GPD_IRQHandler
+GPE_IRQHandler
+GPF_IRQHandler
+SPI0_IRQHandler
+SPI1_IRQHandler
+BRAKE0_IRQHandler
+PWM0P0_IRQHandler
+PWM0P1_IRQHandler
+PWM0P2_IRQHandler
+BRAKE1_IRQHandler
+PWM1P0_IRQHandler
+PWM1P1_IRQHandler
+PWM1P2_IRQHandler
+TMR0_IRQHandler
+TMR1_IRQHandler
+TMR2_IRQHandler
+TMR3_IRQHandler
+UART0_IRQHandler
+UART1_IRQHandler
+I2C0_IRQHandler
+I2C1_IRQHandler
+PDMA_IRQHandler
+DAC_IRQHandler
+ADC00_IRQHandler
+ADC01_IRQHandler
+ACMP01_IRQHandler
+ADC02_IRQHandler
+ADC03_IRQHandler
+UART2_IRQHandler
+UART3_IRQHandler
+SPI2_IRQHandler
+USBD_IRQHandler
+USBH_IRQHandler
+USBOTG_IRQHandler
+CAN0_IRQHandler
+SC0_IRQHandler
+TK_IRQHandler
+ B .
+ ENDP
+
+
+ ALIGN
+
+
+; User Initial Stack & Heap
+
+ IF :DEF:__MICROLIB
+
+ EXPORT __initial_sp
+ EXPORT __heap_base
+ EXPORT __heap_limit
+
+ ELSE
+
+ IMPORT __use_two_region_memory
+ EXPORT __user_initial_stackheap
+
+__user_initial_stackheap PROC
+ LDR R0, = Heap_Mem
+ LDR R1, =(Stack_Mem + Stack_Size)
+ LDR R2, = (Heap_Mem + Heap_Size)
+ LDR R3, = Stack_Mem
+ BX LR
+ ENDP
+
+ ALIGN
+
+ ENDIF
+
+
+ END
+;/*** (C) COPYRIGHT 2014 Nuvoton Technology Corp. ***/
diff --git a/bsp/nuvoton_m451/Libraries/Device/Nuvoton/M451Series/Source/GCC/startup_M451Series.s b/bsp/nuvoton_m451/Libraries/Device/Nuvoton/M451Series/Source/GCC/startup_M451Series.s
new file mode 100644
index 0000000000000000000000000000000000000000..d1db011e7ef5dbec50ab3fd95362cea0ed3917ee
--- /dev/null
+++ b/bsp/nuvoton_m451/Libraries/Device/Nuvoton/M451Series/Source/GCC/startup_M451Series.s
@@ -0,0 +1,447 @@
+/**
+ ******************************************************************************
+ * @file startup_M451Series.s
+ * @author RT-Thread Develop Team
+ * @version V1.0.0
+ * @date 2016-12-07
+ * @brief M451Series Devices vector table for GCC toolchain.
+ * This module performs:
+ * - Set the initial SP
+ * - Set the initial PC == Reset_Handler,
+ * - Set the vector table entries with the exceptions ISR address
+ * - Branches to main in the C library (which eventually
+ * calls main()).
+ * After Reset the Cortex-M4 processor is in Thread mode,
+ * priority is Privileged, and the Stack is set to Main.
+ * It's ported from startup_M051Series.s
+ ******************************************************************************
+*/
+
+ .syntax unified
+ .cpu cortex-m4
+ .fpu softvfp
+ .thumb
+
+.global g_pfnVectors
+.global Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word _sidata
+/* start address for the .data section. defined in linker script */
+.word _sdata
+/* end address for the .data section. defined in linker script */
+.word _edata
+/* start address for the .bss section. defined in linker script */
+.word _sbss
+/* end address for the .bss section. defined in linker script */
+.word _ebss
+
+/**
+ * @brief This is the code that gets called when the processor first
+ * starts execution following a reset event. Only the absolutely
+ * necessary set is performed, after which the application
+ * supplied main() routine is called.
+ * @param None
+ * @retval : None
+*/
+
+ .section .text.Reset_Handler
+ .weak Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+
+ /* Unlock Register */
+ ldr r0, =0x40000100
+ ldr r1, =0x59
+ str r1, [R0]
+ ldr r1, =0x16
+ str r1, [R0]
+ ldr r1, =0x88
+ str r1, [r0]
+
+ /* Init POR */
+ ldr r2, =0x40000024
+ ldr r1, =0x00005AA5
+ str r1, [r2]
+
+ /* Select INV Type*/
+ ldr r2, =0x40000200
+ ldr r1, [r2]
+ bic r1, r1, #0x1000
+ str r1, [r2]
+
+ /* Lock register */
+ movs r1, #0
+ str r1, [r0]
+
+ /* Copy the data segment initializers from flash to SRAM */
+ movs r1, #0
+ b LoopCopyDataInit
+
+CopyDataInit:
+ ldr r3, =_sidata
+ ldr r3, [r3, r1]
+ str r3, [r0, r1]
+ adds r1, r1, #4
+
+LoopCopyDataInit:
+ ldr r0, =_sdata
+ ldr r3, =_edata
+ adds r2, r0, r1
+ cmp r2, r3
+ bcc CopyDataInit
+ ldr r2, =_sbss
+ b LoopFillZerobss
+/* Zero fill the bss segment. */
+FillZerobss:
+ movs r3, #0
+/* Here I changed*/
+ str r3, [r2], #4
+
+LoopFillZerobss:
+ ldr r3, = _ebss
+ cmp r2, r3
+ bcc FillZerobss
+ /* Call the clock system intitialization function.*/
+ bl SystemInit
+ /* Call the application's entry point.*/
+ bl main
+ bx lr
+.size Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief This is the code that gets called when the processor receives an
+ * unexpected interrupt. This simply enters an infinite loop, preserving
+ * the system state for examination by a debugger.
+ *
+ * @param None
+ * @retval None
+*/
+ .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+ b Infinite_Loop
+ .size Default_Handler, .-Default_Handler
+/*******************************************************************************
+*
+* The minimal vector table for a Cortex M0. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*******************************************************************************/
+ .section .isr_vector,"a",%progbits
+ .type g_pfnVectors, %object
+ .size g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+ .word _estack
+ .word Reset_Handler
+ .word NMI_Handler
+ .word HardFault_Handler
+ .word MemManage_Handler
+ .word BusFault_Handler
+ .word UsageFault_Handler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word SVC_Handler
+ .word DebugMon_Handler
+ .word 0
+ .word PendSV_Handler
+ .word SysTick_Handler
+ /* External Interrupts */
+ .word BOD_IRQHandler /* 0: Brown Out detection */
+ .word IRC_IRQHandler /* 1: Internal RC */
+ .word PWRWU_IRQHandler /* 2: Power down wake up */
+ .word RAMPE_IRQHandler /* 3: RAM parity error */
+ .word CLKFAIL_IRQHandler /* 4: Clock detection fail */
+ .word Default_Handler /* 5: Reserved */
+ .word RTC_IRQHandler /* 6: Real Time Clock */
+ .word TAMPER_IRQHandler /* 7: Tamper detection */
+ .word WDT_IRQHandler /* 8: Watchdog timer */
+ .word WWDT_IRQHandler /* 9: Window watchdog timer */
+ .word EINT0_IRQHandler /* 10: External Input 0 */
+ .word EINT1_IRQHandler /* 11: External Input 1 */
+ .word EINT2_IRQHandler /* 12: External Input 2 */
+ .word EINT3_IRQHandler /* 13: External Input 3 */
+ .word EINT4_IRQHandler /* 14: External Input 4 */
+ .word EINT5_IRQHandler /* 15: External Input 5 */
+ .word GPA_IRQHandler /* 16: GPIO Port A */
+ .word GPB_IRQHandler /* 17: GPIO Port B */
+ .word GPC_IRQHandler /* 18: GPIO Port C */
+ .word GPD_IRQHandler /* 19: GPIO Port D */
+ .word GPE_IRQHandler /* 20: GPIO Port E */
+ .word GPF_IRQHandler /* 21: GPIO Port F */
+ .word SPI0_IRQHandler /* 22: SPI0 */
+ .word SPI1_IRQHandler /* 23: SPI1 */
+ .word BRAKE0_IRQHandler /* 24: */
+ .word PWM0P0_IRQHandler /* 25: */
+ .word PWM0P1_IRQHandler /* 26: */
+ .word PWM0P2_IRQHandler /* 27: */
+ .word BRAKE1_IRQHandler /* 28: */
+ .word PWM1P0_IRQHandler /* 29: */
+ .word PWM1P1_IRQHandler /* 30: */
+ .word PWM1P2_IRQHandler /* 31: */
+ .word TMR0_IRQHandler /* 32: Timer 0 */
+ .word TMR1_IRQHandler /* 33: Timer 1 */
+ .word TMR2_IRQHandler /* 34: Timer 2 */
+ .word TMR3_IRQHandler /* 35: Timer 3 */
+ .word UART0_IRQHandler /* 36: UART0 */
+ .word UART1_IRQHandler /* 37: UART1 */
+ .word I2C0_IRQHandler /* 38: I2C0 */
+ .word I2C1_IRQHandler /* 39: I2C1 */
+ .word PDMA_IRQHandler /* 40: Peripheral DMA */
+ .word DAC_IRQHandler /* 41: DAC */
+ .word ADC00_IRQHandler /* 42: ADC0 interrupt source 0 */
+ .word ADC01_IRQHandler /* 43: ADC0 interrupt source 1 */
+ .word ACMP01_IRQHandler /* 44: ACMP0 and ACMP1 */
+ .word Default_Handler /* 45: Reserved */
+ .word ADC02_IRQHandler /* 46: ADC0 interrupt source 2 */
+ .word ADC03_IRQHandler /* 47: ADC0 interrupt source 3 */
+ .word UART2_IRQHandler /* 48: UART2 */
+ .word UART3_IRQHandler /* 49: UART3 */
+ .word Default_Handler /* 50: Reserved */
+ .word SPI2_IRQHandler /* 51: SPI2 */
+ .word Default_Handler /* 52: Reserved */
+ .word USBD_IRQHandler /* 53: USB device */
+ .word USBH_IRQHandler /* 54: USB host */
+ .word USBOTG_IRQHandler /* 55: USB OTG */
+ .word CAN0_IRQHandler /* 56: CAN0 */
+ .word Default_Handler /* 57: Reserved */
+ .word SC0_IRQHandler /* 58: */
+ .word Default_Handler /* 59: Reserved. */
+ .word Default_Handler /* 60: */
+ .word Default_Handler /* 61: */
+ .word Default_Handler /* 62: */
+ .word TK_IRQHandler /* 63: */
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+
+ .weak NMI_Handler
+ .thumb_set NMI_Handler,Default_Handler
+
+ .weak HardFault_Handler
+ .thumb_set HardFault_Handler,Default_Handler
+
+ .weak MemManage_Handler
+ .thumb_set MemManage_Handler,Default_Handler
+
+ .weak BusFault_Handler
+ .thumb_set BusFault_Handler,Default_Handler
+
+ .weak UsageFault_Handler
+ .thumb_set UsageFault_Handler,Default_Handler
+
+ .weak SVC_Handler
+ .thumb_set SVC_Handler,Default_Handler
+
+ .weak DebugMon_Handler
+ .thumb_set DebugMon_Handler,Default_Handler
+
+ .weak PendSV_Handler
+ .thumb_set PendSV_Handler,Default_Handler
+
+ .weak SysTick_Handler
+ .thumb_set SysTick_Handler,Default_Handler
+
+ .weak BOD_IRQHandler
+ .thumb_set BOD_IRQHandler, Default_Handler
+
+ .weak IRC_IRQHandler
+ .thumb_set IRC_IRQHandler, Default_Handler
+
+ .weak PWRWU_IRQHandler
+ .thumb_set PWRWU_IRQHandler, Default_Handler
+
+ .weak RAMPE_IRQHandler
+ .thumb_set RAMPE_IRQHandler, Default_Handler
+
+ .weak CLKFAIL_IRQHandler
+ .thumb_set CLKFAIL_IRQHandler, Default_Handler
+
+ .weak Default_Handler
+ .thumb_set Default_Handler, Default_Handler
+
+ .weak RTC_IRQHandler
+ .thumb_set RTC_IRQHandler, Default_Handler
+
+ .weak TAMPER_IRQHandler
+ .thumb_set TAMPER_IRQHandler, Default_Handler
+
+ .weak WDT_IRQHandler
+ .thumb_set WDT_IRQHandler, Default_Handler
+
+ .weak WWDT_IRQHandler
+ .thumb_set WWDT_IRQHandler, Default_Handler
+
+ .weak EINT0_IRQHandler
+ .thumb_set EINT0_IRQHandler, Default_Handler
+
+ .weak EINT1_IRQHandler
+ .thumb_set EINT1_IRQHandler, Default_Handler
+
+ .weak EINT2_IRQHandler
+ .thumb_set EINT2_IRQHandler, Default_Handler
+
+ .weak EINT3_IRQHandler
+ .thumb_set EINT3_IRQHandler, Default_Handler
+
+ .weak EINT4_IRQHandler
+ .thumb_set EINT4_IRQHandler, Default_Handler
+
+ .weak EINT5_IRQHandler
+ .thumb_set EINT5_IRQHandler, Default_Handler
+
+ .weak GPA_IRQHandler
+ .thumb_set GPA_IRQHandler, Default_Handler
+
+ .weak GPB_IRQHandler
+ .thumb_set GPB_IRQHandler, Default_Handler
+
+ .weak GPC_IRQHandler
+ .thumb_set GPC_IRQHandler, Default_Handler
+
+ .weak GPD_IRQHandler
+ .thumb_set GPD_IRQHandler, Default_Handler
+
+ .weak GPE_IRQHandler
+ .thumb_set GPE_IRQHandler, Default_Handler
+
+ .weak GPF_IRQHandler
+ .thumb_set GPF_IRQHandler, Default_Handler
+
+ .weak SPI0_IRQHandler
+ .thumb_set SPI0_IRQHandler, Default_Handler
+
+ .weak SPI1_IRQHandler
+ .thumb_set SPI1_IRQHandler, Default_Handler
+
+ .weak BRAKE0_IRQHandler
+ .thumb_set BRAKE0_IRQHandler, Default_Handler
+
+ .weak PWM0P0_IRQHandler
+ .thumb_set PWM0P0_IRQHandler, Default_Handler
+
+ .weak PWM0P1_IRQHandler
+ .thumb_set PWM0P1_IRQHandler, Default_Handler
+
+ .weak PWM0P2_IRQHandler
+ .thumb_set PWM0P2_IRQHandler, Default_Handler
+
+ .weak BRAKE1_IRQHandler
+ .thumb_set BRAKE1_IRQHandler, Default_Handler
+
+ .weak PWM1P0_IRQHandler
+ .thumb_set PWM1P0_IRQHandler, Default_Handler
+
+ .weak PWM1P1_IRQHandler
+ .thumb_set PWM1P1_IRQHandler, Default_Handler
+
+ .weak PWM1P2_IRQHandler
+ .thumb_set PWM1P2_IRQHandler, Default_Handler
+
+ .weak TMR0_IRQHandler
+ .thumb_set TMR0_IRQHandler, Default_Handler
+
+ .weak TMR1_IRQHandler
+ .thumb_set TMR1_IRQHandler, Default_Handler
+
+ .weak TMR2_IRQHandler
+ .thumb_set TMR2_IRQHandler, Default_Handler
+
+ .weak TMR3_IRQHandler
+ .thumb_set TMR3_IRQHandler, Default_Handler
+
+ .weak UART0_IRQHandler
+ .thumb_set UART0_IRQHandler, Default_Handler
+
+ .weak UART1_IRQHandler
+ .thumb_set UART1_IRQHandler, Default_Handler
+
+ .weak I2C0_IRQHandler
+ .thumb_set I2C0_IRQHandler, Default_Handler
+
+ .weak I2C1_IRQHandler
+ .thumb_set I2C1_IRQHandler, Default_Handler
+
+ .weak PDMA_IRQHandler
+ .thumb_set PDMA_IRQHandler, Default_Handler
+
+ .weak DAC_IRQHandler
+ .thumb_set DAC_IRQHandler, Default_Handler
+
+ .weak ADC00_IRQHandler
+ .thumb_set ADC00_IRQHandler, Default_Handler
+
+ .weak ADC01_IRQHandler
+ .thumb_set ADC01_IRQHandler, Default_Handler
+
+ .weak ACMP01_IRQHandler
+ .thumb_set ACMP01_IRQHandler, Default_Handler
+
+ .weak Default_Handler
+ .thumb_set Default_Handler, Default_Handler
+
+ .weak ADC02_IRQHandler
+ .thumb_set ADC02_IRQHandler, Default_Handler
+
+ .weak ADC03_IRQHandler
+ .thumb_set ADC03_IRQHandler, Default_Handler
+
+ .weak UART2_IRQHandler
+ .thumb_set UART2_IRQHandler, Default_Handler
+
+ .weak UART3_IRQHandler
+ .thumb_set UART3_IRQHandler, Default_Handler
+
+ .weak Default_Handler
+ .thumb_set Default_Handler, Default_Handler
+
+ .weak SPI2_IRQHandler
+ .thumb_set SPI2_IRQHandler, Default_Handler
+
+ .weak Default_Handler
+ .thumb_set Default_Handler, Default_Handler
+
+ .weak USBD_IRQHandler
+ .thumb_set USBD_IRQHandler, Default_Handler
+
+ .weak USBH_IRQHandler
+ .thumb_set USBH_IRQHandler, Default_Handler
+
+ .weak USBOTG_IRQHandler
+ .thumb_set USBOTG_IRQHandler, Default_Handler
+
+ .weak CAN0_IRQHandler
+ .thumb_set CAN0_IRQHandler, Default_Handler
+
+ .weak Default_Handler
+ .thumb_set Default_Handler, Default_Handler
+
+ .weak SC0_IRQHandler
+ .thumb_set SC0_IRQHandler, Default_Handler
+
+ .weak Default_Handler
+ .thumb_set Default_Handler, Default_Handler
+
+ .weak Default_Handler
+ .thumb_set Default_Handler, Default_Handler
+
+ .weak Default_Handler
+ .thumb_set Default_Handler, Default_Handler
+
+ .weak Default_Handler
+ .thumb_set Default_Handler, Default_Handler
+
+ .weak TK_IRQHandler
+ .thumb_set TK_IRQHandler, Default_Handler
+/************************ END OF FILE ***********************/
+
diff --git a/bsp/nuvoton_m451/Libraries/Device/Nuvoton/M451Series/Source/IAR/startup_M451Series.s b/bsp/nuvoton_m451/Libraries/Device/Nuvoton/M451Series/Source/IAR/startup_M451Series.s
new file mode 100644
index 0000000000000000000000000000000000000000..83892d9b9e86ba82c2fc46fe1a757c85e0cad817
--- /dev/null
+++ b/bsp/nuvoton_m451/Libraries/Device/Nuvoton/M451Series/Source/IAR/startup_M451Series.s
@@ -0,0 +1,351 @@
+;/******************************************************************************
+; * @file startup_NUC400Series.s
+; * @version V0.10
+; * $Revision: 3 $
+; * $Date: 14/12/24 10:20a $
+; * @brief CMSIS Cortex-M4 Core Device Startup File for NUC451 Series MCU
+; *
+; * @note
+; * Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved.
+;*****************************************************************************/
+
+ MODULE ?cstartup
+
+ ;; Forward declaration of sections.
+ SECTION CSTACK:DATA:NOROOT(3)
+
+ SECTION .intvec:CODE:NOROOT(2)
+
+ EXTERN __iar_program_start
+ EXTERN SystemInit
+ PUBLIC __vector_table
+ PUBLIC __vector_table_0x1c
+ PUBLIC __Vectors
+ PUBLIC __Vectors_End
+ PUBLIC __Vectors_Size
+
+ DATA
+
+__vector_table
+ DCD sfe(CSTACK)
+ DCD Reset_Handler
+
+ DCD NMI_Handler
+ DCD HardFault_Handler
+ DCD MemManage_Handler
+ DCD BusFault_Handler
+ DCD UsageFault_Handler
+__vector_table_0x1c
+ DCD 0
+ DCD 0
+ DCD 0
+ DCD 0
+ DCD SVC_Handler
+ DCD DebugMon_Handler
+ DCD 0
+ DCD PendSV_Handler
+ DCD SysTick_Handler
+
+ ; External Interrupts
+ DCD BOD_IRQHandler ; 0: Brown Out detection
+ DCD IRC_IRQHandler ; 1: Internal RC
+ DCD PWRWU_IRQHandler ; 2: Power Down Wake Up
+ DCD Default_Handler ; 3: Reserved.
+ DCD CLKFAIL_IRQHandler ; 4: Reserved.
+ DCD Default_Handler ; 5: Reserved.
+ DCD RTC_IRQHandler ; 6: Real Time Clock
+ DCD TAMPER_IRQHandler ; 7: Tamper detection
+ DCD WDT_IRQHandler ; 8: Watchdog timer
+ DCD WWDT_IRQHandler ; 9: Window watchdog timer
+ DCD EINT0_IRQHandler ; 10: External Input 0
+ DCD EINT1_IRQHandler ; 11: External Input 1
+ DCD EINT2_IRQHandler ; 12: External Input 2
+ DCD EINT3_IRQHandler ; 13: External Input 3
+ DCD EINT4_IRQHandler ; 14: External Input 4
+ DCD EINT5_IRQHandler ; 15: External Input 5
+ DCD GPA_IRQHandler ; 16: GPIO Port A
+ DCD GPB_IRQHandler ; 17: GPIO Port B
+ DCD GPC_IRQHandler ; 18: GPIO Port C
+ DCD GPD_IRQHandler ; 19: GPIO Port D
+ DCD GPE_IRQHandler ; 20: GPIO Port E
+ DCD GPF_IRQHandler ; 21: GPIO Port F
+ DCD SPI0_IRQHandler ; 22: SPI0
+ DCD SPI1_IRQHandler ; 23: SPI1
+ DCD BRAKE0_IRQHandler ; 24:
+ DCD PWM0P0_IRQHandler ; 25:
+ DCD PWM0P1_IRQHandler ; 26:
+ DCD PWM0P2_IRQHandler ; 27:
+ DCD BRAKE1_IRQHandler ; 28:
+ DCD PWM1P0_IRQHandler ; 29:
+ DCD PWM1P1_IRQHandler ; 30:
+ DCD PWM1P2_IRQHandler ; 31:
+ DCD TMR0_IRQHandler ; 32: Timer 0
+ DCD TMR1_IRQHandler ; 33: Timer 1
+ DCD TMR2_IRQHandler ; 34: Timer 2
+ DCD TMR3_IRQHandler ; 35: Timer 3
+ DCD UART0_IRQHandler ; 36: UART0
+ DCD UART1_IRQHandler ; 37: UART1
+ DCD I2C0_IRQHandler ; 38: I2C0
+ DCD I2C1_IRQHandler ; 39: I2C1
+ DCD PDMA_IRQHandler ; 40: Peripheral DMA
+ DCD DAC_IRQHandler ; 41: DAC
+ DCD ADC00_IRQHandler ; 42: ADC0 interrupt source 0
+ DCD ADC01_IRQHandler ; 43: ADC0 interrupt source 1
+ DCD ACMP01_IRQHandler ; 44: ACMP0 and ACMP1
+ DCD Default_Handler ; 45: Reserved
+ DCD ADC02_IRQHandler ; 46: ADC0 interrupt source 2
+ DCD ADC03_IRQHandler ; 47: ADC0 interrupt source 3
+ DCD UART2_IRQHandler ; 48: UART2
+ DCD UART3_IRQHandler ; 49: UART3
+ DCD Default_Handler ; 50: Reserved
+ DCD SPI2_IRQHandler ; 51: SPI2
+ DCD Default_Handler ; 52: Reserved
+ DCD USBD_IRQHandler ; 53: USB device
+ DCD USBH_IRQHandler ; 54: USB host
+ DCD USBOTG_IRQHandler ; 55: USB OTG
+ DCD CAN0_IRQHandler ; 56: CAN0
+ DCD Default_Handler ; 57: Reserved
+ DCD SC0_IRQHandler ; 58:
+ DCD Default_Handler ; 59: Reserved.
+ DCD Default_Handler ; 60:
+ DCD Default_Handler ; 61:
+ DCD Default_Handler ; 62:
+ DCD TK_IRQHandler ; 63:
+__Vectors_End
+
+__Vectors EQU __vector_table
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+ THUMB
+
+ PUBWEAK Reset_Handler
+ SECTION .text:CODE:REORDER:NOROOT(2)
+Reset_Handler
+ LDR R0, =0x40000100
+ ; Unlock Register
+ LDR R1, =0x59
+ STR R1, [R0]
+ LDR R1, =0x16
+ STR R1, [R0]
+ LDR R1, =0x88
+ STR R1, [R0]
+
+ ; Init POR
+ LDR R2, =0x40000024
+ LDR R1, =0x00005AA5
+ STR R1, [R2]
+
+ ; Select INV Type
+ LDR R2, =0x40000200
+ LDR R1, [R2]
+ BIC R1, R1, #0x1000
+ STR R1, [R2]
+
+ ; Lock register
+ MOVS R1, #0
+ STR R1, [R0]
+
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__iar_program_start
+ BX R0
+
+ PUBWEAK NMI_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+NMI_Handler
+ B NMI_Handler
+
+ PUBWEAK HardFault_Handler
+
+#ifdef DEBUG_ENABLE_SEMIHOST
+ SECTION .text:CODE:REORDER:NOROOT(2)
+HardFault_Handler
+
+
+ MOV R0, LR
+ LSLS R0,R0, #29 ; Check bit 2
+ BMI SP_is_PSP ; previous stack is PSP
+ MRS R0, MSP ; previous stack is MSP, read MSP
+ B SP_Read_Ready
+SP_is_PSP
+ MRS R0, PSP ; Read PSP
+SP_Read_Ready
+ LDR R1, [R13, #24] ; Get previous PC
+ LDRH R3, [R1] ; Get instruction
+ LDR R2, =0xBEAB ; The sepcial BKPT instruction
+ CMP R3, R2 ; Test if the instruction at previous PC is BKPT
+ BNE HardFault_Handler_Ret ; Not BKPT
+
+ ADDS R1, #4 ; Skip BKPT and next line
+ STR R1, [R13, #24] ; Save previous PC
+
+ BX LR
+HardFault_Handler_Ret
+
+#else
+
+ SECTION .text:CODE:REORDER:NOROOT(1)
+HardFault_Handler
+
+#endif
+
+ B HardFault_Handler
+
+ PUBWEAK MemManage_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+MemManage_Handler
+ B MemManage_Handler
+
+ PUBWEAK BusFault_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+BusFault_Handler
+ B BusFault_Handler
+
+ PUBWEAK UsageFault_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+UsageFault_Handler
+ B UsageFault_Handler
+
+ PUBWEAK SVC_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+SVC_Handler
+ B SVC_Handler
+
+ PUBWEAK DebugMon_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+DebugMon_Handler
+ B DebugMon_Handler
+
+ PUBWEAK PendSV_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+PendSV_Handler
+ B PendSV_Handler
+
+ PUBWEAK SysTick_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+SysTick_Handler
+ B SysTick_Handler
+
+ PUBWEAK BOD_IRQHandler
+ PUBWEAK IRC_IRQHandler
+ PUBWEAK PWRWU_IRQHandler
+ PUBWEAK RAMPE_IRQHandler
+ PUBWEAK CLKFAIL_IRQHandler
+ PUBWEAK RTC_IRQHandler
+ PUBWEAK TAMPER_IRQHandler
+ PUBWEAK WDT_IRQHandler
+ PUBWEAK WWDT_IRQHandler
+ PUBWEAK EINT0_IRQHandler
+ PUBWEAK EINT1_IRQHandler
+ PUBWEAK EINT2_IRQHandler
+ PUBWEAK EINT3_IRQHandler
+ PUBWEAK EINT4_IRQHandler
+ PUBWEAK EINT5_IRQHandler
+ PUBWEAK GPA_IRQHandler
+ PUBWEAK GPB_IRQHandler
+ PUBWEAK GPC_IRQHandler
+ PUBWEAK GPD_IRQHandler
+ PUBWEAK GPE_IRQHandler
+ PUBWEAK GPF_IRQHandler
+ PUBWEAK SPI0_IRQHandler
+ PUBWEAK SPI1_IRQHandler
+ PUBWEAK BRAKE0_IRQHandler
+ PUBWEAK PWM0P0_IRQHandler
+ PUBWEAK PWM0P1_IRQHandler
+ PUBWEAK PWM0P2_IRQHandler
+ PUBWEAK BRAKE1_IRQHandler
+ PUBWEAK PWM1P0_IRQHandler
+ PUBWEAK PWM1P1_IRQHandler
+ PUBWEAK PWM1P2_IRQHandler
+ PUBWEAK TMR0_IRQHandler
+ PUBWEAK TMR1_IRQHandler
+ PUBWEAK TMR2_IRQHandler
+ PUBWEAK TMR3_IRQHandler
+ PUBWEAK UART0_IRQHandler
+ PUBWEAK UART1_IRQHandler
+ PUBWEAK I2C0_IRQHandler
+ PUBWEAK I2C1_IRQHandler
+ PUBWEAK PDMA_IRQHandler
+ PUBWEAK DAC_IRQHandler
+ PUBWEAK ADC00_IRQHandler
+ PUBWEAK ADC01_IRQHandler
+ PUBWEAK ACMP01_IRQHandler
+ PUBWEAK ADC02_IRQHandler
+ PUBWEAK ADC03_IRQHandler
+ PUBWEAK UART2_IRQHandler
+ PUBWEAK UART3_IRQHandler
+ PUBWEAK SPI2_IRQHandler
+ PUBWEAK USBD_IRQHandler
+ PUBWEAK USBH_IRQHandler
+ PUBWEAK USBOTG_IRQHandler
+ PUBWEAK CAN0_IRQHandler
+ PUBWEAK SC0_IRQHandler
+ PUBWEAK TK_IRQHandler
+
+ SECTION .text:CODE:REORDER:NOROOT(1)
+
+BOD_IRQHandler
+IRC_IRQHandler
+PWRWU_IRQHandler
+RAMPE_IRQHandler
+CLKFAIL_IRQHandler
+RTC_IRQHandler
+TAMPER_IRQHandler
+WDT_IRQHandler
+WWDT_IRQHandler
+EINT0_IRQHandler
+EINT1_IRQHandler
+EINT2_IRQHandler
+EINT3_IRQHandler
+EINT4_IRQHandler
+EINT5_IRQHandler
+GPA_IRQHandler
+GPB_IRQHandler
+GPC_IRQHandler
+GPD_IRQHandler
+GPE_IRQHandler
+GPF_IRQHandler
+SPI0_IRQHandler
+SPI1_IRQHandler
+BRAKE0_IRQHandler
+PWM0P0_IRQHandler
+PWM0P1_IRQHandler
+PWM0P2_IRQHandler
+BRAKE1_IRQHandler
+PWM1P0_IRQHandler
+PWM1P1_IRQHandler
+PWM1P2_IRQHandler
+TMR0_IRQHandler
+TMR1_IRQHandler
+TMR2_IRQHandler
+TMR3_IRQHandler
+UART0_IRQHandler
+UART1_IRQHandler
+I2C0_IRQHandler
+I2C1_IRQHandler
+PDMA_IRQHandler
+DAC_IRQHandler
+ADC00_IRQHandler
+ADC01_IRQHandler
+ACMP01_IRQHandler
+ADC02_IRQHandler
+ADC03_IRQHandler
+UART2_IRQHandler
+UART3_IRQHandler
+SPI2_IRQHandler
+USBD_IRQHandler
+USBH_IRQHandler
+USBOTG_IRQHandler
+CAN0_IRQHandler
+SC0_IRQHandler
+TK_IRQHandler
+Default_Handler
+ B .
+
+ END
+;/*** (C) COPYRIGHT 2014 Nuvoton Technology Corp. ***/
diff --git a/bsp/nuvoton_m451/Libraries/Device/Nuvoton/M451Series/Source/system_M451Series.c b/bsp/nuvoton_m451/Libraries/Device/Nuvoton/M451Series/Source/system_M451Series.c
new file mode 100644
index 0000000000000000000000000000000000000000..daf91b90c7ba031afdef2abd71e5ebe79d96490f
--- /dev/null
+++ b/bsp/nuvoton_m451/Libraries/Device/Nuvoton/M451Series/Source/system_M451Series.c
@@ -0,0 +1,109 @@
+/******************************************************************************
+ * @file system_M451Series.c
+ * @version V0.10
+ * $Revision: 11 $
+ * $Date: 15/09/02 10:02a $
+ * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Source File for M451 Series MCU
+ *
+ * @note
+ * Copyright (C) 2013~2015 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+
+#include "M451Series.h"
+
+
+/*----------------------------------------------------------------------------
+ DEFINES
+ *----------------------------------------------------------------------------*/
+
+
+/*----------------------------------------------------------------------------
+ Clock Variable definitions
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/
+uint32_t CyclesPerUs = (__HSI / 1000000); /* Cycles per micro second */
+uint32_t PllClock = __HSI; /*!< PLL Output Clock Frequency */
+uint32_t gau32ClkSrcTbl[] = {__HXT, __LXT, 0, __LIRC, 0, 0, 0, __HIRC};
+
+/*----------------------------------------------------------------------------
+ Clock functions
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate(void) /* Get Core Clock Frequency */
+{
+#if 1
+ uint32_t u32Freq, u32ClkSrc;
+ uint32_t u32HclkDiv;
+
+ /* Update PLL Clock */
+ PllClock = CLK_GetPLLClockFreq();
+
+ u32ClkSrc = CLK->CLKSEL0 & CLK_CLKSEL0_HCLKSEL_Msk;
+
+ if(u32ClkSrc == CLK_CLKSEL0_HCLKSEL_PLL)
+ {
+ /* Use PLL clock */
+ u32Freq = PllClock;
+ }
+ else
+ {
+ /* Use the clock sources directly */
+ u32Freq = gau32ClkSrcTbl[u32ClkSrc];
+ }
+
+ u32HclkDiv = (CLK->CLKDIV0 & CLK_CLKDIV0_HCLKDIV_Msk) + 1;
+
+ /* Update System Core Clock */
+ SystemCoreClock = u32Freq / u32HclkDiv;
+
+
+ //if(SystemCoreClock == 0)
+ // __BKPT(0);
+
+ CyclesPerUs = (SystemCoreClock + 500000) / 1000000;
+#endif
+}
+
+/**
+ * Initialize the system
+ *
+ * @param None
+ * @return None
+ *
+ * @brief Setup the microcontroller system.
+ * Initialize the System.
+ */
+void SystemInit(void)
+{
+ /* ToDo: add code to initialize the system
+ do not use global variables because this function is called before
+ reaching pre-main. RW section maybe overwritten afterwards. */
+
+ SYS_UnlockReg();
+ /* One-time POR18 */
+ if((SYS->PDID >> 12) == 0x945)
+ {
+ M32(GCR_BASE+0x14) |= BIT7;
+ }
+ /* Force to use INV type with HXT */
+ CLK->PWRCTL &= ~CLK_PWRCTL_HXTSELTYP_Msk;
+ SYS_LockReg();
+
+
+#ifdef EBI_INIT
+ extern void SYS_Init();
+ extern void EBI_Init();
+
+ SYS_UnlockReg();
+ SYS_Init();
+ EBI_Init();
+ SYS_LockReg();
+#endif
+
+ /* FPU settings ------------------------------------------------------------*/
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ SCB->CPACR |= ((3UL << 10 * 2) | /* set CP10 Full Access */
+ (3UL << 11 * 2)); /* set CP11 Full Access */
+#endif
+
+}
+/*** (C) COPYRIGHT 2013~2015 Nuvoton Technology Corp. ***/
diff --git a/bsp/nuvoton_m451/Libraries/Device/SConscript b/bsp/nuvoton_m451/Libraries/Device/SConscript
new file mode 100644
index 0000000000000000000000000000000000000000..17ffd896597de438ffe71a2a4ba4305fe6432283
--- /dev/null
+++ b/bsp/nuvoton_m451/Libraries/Device/SConscript
@@ -0,0 +1,25 @@
+# RT-Thread building script for component
+
+Import('rtconfig')
+import os
+from building import *
+
+CPPDEFINES = []
+cwd = GetCurrentDir()
+src = Split('''
+Nuvoton/M451Series/Source/system_M451Series.c
+''')
+CPPPATH = [cwd + '/Nuvoton/M451Series/Include']
+CPPPATH += [os.path.dirname(cwd) + '/CMSIS/Include']
+
+#add for startup script
+if rtconfig.CROSS_TOOL == 'iar':
+ src = src + ['Nuvoton/M451Series/Source/IAR/startup_M451Series.s']
+elif rtconfig.CROSS_TOOL == 'keil':
+ src = src + ['Nuvoton/M451Series/Source/ARM/startup_M451Series.s']
+elif rtconfig.CROSS_TOOL == 'gcc':
+ src = src + ['Nuvoton/M451Series/Source/GCC/startup_M451Series.s']
+
+group = DefineGroup('CMSIS', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES)
+
+Return('group')
diff --git a/bsp/nuvoton_m451/Libraries/SConscript b/bsp/nuvoton_m451/Libraries/SConscript
new file mode 100644
index 0000000000000000000000000000000000000000..4c815c49b835a3a5ea61f337dc17154dd316d7d1
--- /dev/null
+++ b/bsp/nuvoton_m451/Libraries/SConscript
@@ -0,0 +1,15 @@
+# RT-Thread building script for bridge
+
+import os
+from building import *
+
+cwd = GetCurrentDir()
+objs = []
+list = os.listdir(cwd)
+
+for d in list:
+ path = os.path.join(cwd, d)
+ if os.path.isfile(os.path.join(path, 'SConscript')):
+ objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
+Return('objs')
diff --git a/bsp/nuvoton_m451/Libraries/StdDriver/SConscript b/bsp/nuvoton_m451/Libraries/StdDriver/SConscript
new file mode 100644
index 0000000000000000000000000000000000000000..40411fdf005c3579fd9b42069e3a9c51558fef26
--- /dev/null
+++ b/bsp/nuvoton_m451/Libraries/StdDriver/SConscript
@@ -0,0 +1,23 @@
+import os
+import rtconfig
+Import('RTT_ROOT')
+from building import *
+
+CPPDEFINES = []
+# get current directory
+cwd = GetCurrentDir()
+
+# The set of source files associated with this SConscript file.
+
+src = Glob('src/*.c')
+# Remove retarget.c As there is a HardFaultHandler in it
+for src_f in src:
+ if 'retarget.c' in src_f.path:
+ src.remove(src_f)
+
+path = [cwd + '/inc']
+
+group = DefineGroup('StdDriver', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)
+
+Return('group')
+
diff --git a/bsp/nuvoton_m451/Libraries/StdDriver/inc/acmp.h b/bsp/nuvoton_m451/Libraries/StdDriver/inc/acmp.h
new file mode 100644
index 0000000000000000000000000000000000000000..67857f42d1ae66dd2fb0d49dd36e164879743147
--- /dev/null
+++ b/bsp/nuvoton_m451/Libraries/StdDriver/inc/acmp.h
@@ -0,0 +1,333 @@
+/**************************************************************************//**
+ * @file ACMP.h
+ * @version V0.10
+ * $Revision: 10 $
+ * $Date: 15/08/11 10:26a $
+ * @brief M451 Series ACMP Driver Header File
+ *
+ * @note
+ * Copyright (C) 2014~2015 Nuvoton Technology Corp. All rights reserved.
+ *
+ ******************************************************************************/
+#ifndef __ACMP_H__
+#define __ACMP_H__
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Include related headers */
+/*---------------------------------------------------------------------------------------------------------*/
+#include "M451Series.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup Standard_Driver Standard Driver
+ @{
+*/
+
+/** @addtogroup ACMP_Driver ACMP Driver
+ @{
+*/
+
+
+/** @addtogroup ACMP_EXPORTED_CONSTANTS ACMP Exported Constants
+ @{
+*/
+
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* ACMP_CTL constant definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define ACMP_CTL_FILTSEL_OFF (0UL << 13) /*!< ACMP_CTL setting for filter function disabled. */
+#define ACMP_CTL_FILTSEL_1PCLK (1UL << 13) /*!< ACMP_CTL setting for 1 PCLK filter count. */
+#define ACMP_CTL_FILTSEL_2PCLK (2UL << 13) /*!< ACMP_CTL setting for 2 PCLK filter count. */
+#define ACMP_CTL_FILTSEL_4PCLK (3UL << 13) /*!< ACMP_CTL setting for 4 PCLK filter count. */
+#define ACMP_CTL_FILTSEL_8PCLK (4UL << 13) /*!< ACMP_CTL setting for 8 PCLK filter count. */
+#define ACMP_CTL_FILTSEL_16PCLK (5UL << 13) /*!< ACMP_CTL setting for 16 PCLK filter count. */
+#define ACMP_CTL_FILTSEL_32PCLK (6UL << 13) /*!< ACMP_CTL setting for 32 PCLK filter count. */
+#define ACMP_CTL_FILTSEL_64PCLK (7UL << 13) /*!< ACMP_CTL setting for 64 PCLK filter count. */
+#define ACMP_CTL_INTPOL_RF (0UL << 8) /*!< ACMP_CTL setting for selecting rising edge and falling edge as interrupt condition. */
+#define ACMP_CTL_INTPOL_R (1UL << 8) /*!< ACMP_CTL setting for selecting rising edge as interrupt condition. */
+#define ACMP_CTL_INTPOL_F (2UL << 8) /*!< ACMP_CTL setting for selecting falling edge as interrupt condition. */
+#define ACMP_CTL_POSSEL_P0 (0UL << 6) /*!< ACMP_CTL setting for selecting ACMPx_P0 pin as the source of ACMP V+. */
+#define ACMP_CTL_POSSEL_P1 (1UL << 6) /*!< ACMP_CTL setting for selecting ACMPx_P1 pin as the source of ACMP V+. */
+#define ACMP_CTL_POSSEL_P2 (2UL << 6) /*!< ACMP_CTL setting for selecting ACMPx_P2 pin as the source of ACMP V+. */
+#define ACMP_CTL_POSSEL_P3 (3UL << 6) /*!< ACMP_CTL setting for selecting ACMPx_P3 pin as the source of ACMP V+. */
+#define ACMP_CTL_NEGSEL_PIN (0UL << 4) /*!< ACMP_CTL setting for selecting the voltage of ACMP negative input pin as the source of ACMP V-. */
+#define ACMP_CTL_NEGSEL_CRV (1UL << 4) /*!< ACMP_CTL setting for selecting internal comparator reference voltage as the source of ACMP V-. */
+#define ACMP_CTL_NEGSEL_VBG (2UL << 4) /*!< ACMP_CTL setting for selecting internal Band-gap voltage as the source of ACMP V-. */
+#define ACMP_CTL_NEGSEL_DAC (3UL << 4) /*!< ACMP_CTL setting for selecting DAC output voltage as the source of ACMP V-. */
+#define ACMP_CTL_HYSTERESIS_ENABLE (1UL << 2) /*!< ACMP_CTL setting for enabling the hysteresis function. */
+#define ACMP_CTL_HYSTERESIS_DISABLE (0UL << 2) /*!< ACMP_CTL setting for disabling the hysteresis function. */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* ACMP_VREF constant definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define ACMP_VREF_CRVSSEL_VDDA (0UL << 6) /*!< ACMP_VREF setting for selecting analog supply voltage VDDA as the CRV source voltage */
+#define ACMP_VREF_CRVSSEL_INTVREF (1UL << 6) /*!< ACMP_VREF setting for selecting internal reference voltage as the CRV source voltage */
+
+
+/*@}*/ /* end of group ACMP_EXPORTED_CONSTANTS */
+
+
+/** @addtogroup ACMP_EXPORTED_FUNCTIONS ACMP Exported Functions
+ @{
+*/
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Define Macros and functions */
+/*---------------------------------------------------------------------------------------------------------*/
+
+
+/**
+ * @brief This macro is used to enable output inverse function
+ * @param[in] acmp The pointer of the specified ACMP module
+ * @param[in] u32ChNum The ACMP number
+ * @return None
+ * @details This macro will set ACMPOINV bit of ACMP_CTL register to enable output inverse function.
+ */
+#define ACMP_ENABLE_OUTPUT_INVERSE(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)%2] |= ACMP_CTL_ACMPOINV_Msk)
+
+/**
+ * @brief This macro is used to disable output inverse function
+ * @param[in] acmp The pointer of the specified ACMP module
+ * @param[in] u32ChNum The ACMP number
+ * @return None
+ * @details This macro will clear ACMPOINV bit of ACMP_CTL register to disable output inverse function.
+ */
+#define ACMP_DISABLE_OUTPUT_INVERSE(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)%2] &= ~ACMP_CTL_ACMPOINV_Msk)
+
+/**
+ * @brief This macro is used to select ACMP negative input source
+ * @param[in] acmp The pointer of the specified ACMP module
+ * @param[in] u32ChNum The ACMP number
+ * @param[in] u32Src is comparator negative input selection. Including:
+ * - \ref ACMP_CTL_NEGSEL_PIN
+ * - \ref ACMP_CTL_NEGSEL_CRV
+ * - \ref ACMP_CTL_NEGSEL_VBG
+ * - \ref ACMP_CTL_NEGSEL_DAC
+ * @return None
+ * @details This macro will set NEGSEL (ACMP_CTL[5:4]) to determine the source of negative input.
+ */
+#define ACMP_SET_NEG_SRC(acmp, u32ChNum, u32Src) ((acmp)->CTL[(u32ChNum)%2] = ((acmp)->CTL[(u32ChNum)%2] & ~ACMP_CTL_NEGSEL_Msk) | (u32Src))
+
+/**
+ * @brief This macro is used to enable hysteresis function
+ * @param[in] acmp The pointer of the specified ACMP module
+ * @param[in] u32ChNum The ACMP number
+ * @return None
+ * @details This macro will set HYSEN bit of ACMP_CTL register to enable hysteresis function.
+ */
+#define ACMP_ENABLE_HYSTERESIS(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)%2] |= ACMP_CTL_HYSEN_Msk)
+
+/**
+ * @brief This macro is used to disable hysteresis function
+ * @param[in] acmp The pointer of the specified ACMP module
+ * @param[in] u32ChNum The ACMP number
+ * @return None
+ * @details This macro will clear HYSEN bit of ACMP_CTL register to disable hysteresis function.
+ */
+#define ACMP_DISABLE_HYSTERESIS(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)%2] &= ~ACMP_CTL_HYSEN_Msk)
+
+/**
+ * @brief This macro is used to enable interrupt
+ * @param[in] acmp The pointer of the specified ACMP module
+ * @param[in] u32ChNum The ACMP number
+ * @return None
+ * @details This macro will set ACMPIE bit of ACMP_CTL register to enable interrupt function.
+ * If wake-up function is enabled, the wake-up interrupt will be enabled as well.
+ */
+#define ACMP_ENABLE_INT(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)%2] |= ACMP_CTL_ACMPIE_Msk)
+
+/**
+ * @brief This macro is used to disable interrupt
+ * @param[in] acmp The pointer of the specified ACMP module
+ * @param[in] u32ChNum The ACMP number
+ * @return None
+ * @details This macro will clear ACMPIE bit of ACMP_CTL register to disable interrupt function.
+ */
+#define ACMP_DISABLE_INT(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)%2] &= ~ACMP_CTL_ACMPIE_Msk)
+
+/**
+ * @brief This macro is used to enable ACMP
+ * @param[in] acmp The pointer of the specified ACMP module
+ * @param[in] u32ChNum The ACMP number
+ * @return None
+ * @details This macro will set ACMPEN bit of ACMP_CTL register to enable analog comparator.
+ */
+#define ACMP_ENABLE(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)%2] |= ACMP_CTL_ACMPEN_Msk)
+
+/**
+ * @brief This macro is used to disable ACMP
+ * @param[in] acmp The pointer of the specified ACMP module
+ * @param[in] u32ChNum The ACMP number
+ * @return None
+ * @details This macro will clear ACMPEN bit of ACMP_CTL register to disable analog comparator.
+ */
+#define ACMP_DISABLE(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)%2] &= ~ACMP_CTL_ACMPEN_Msk)
+
+/**
+ * @brief This macro is used to get ACMP output value
+ * @param[in] acmp The pointer of the specified ACMP module
+ * @param[in] u32ChNum The ACMP number
+ * @return ACMP output value
+ * @details This macro will return the ACMP output value.
+ */
+#define ACMP_GET_OUTPUT(acmp, u32ChNum) (((acmp)->STATUS & (ACMP_STATUS_ACMPO0_Msk<<((u32ChNum)%2)))?1:0)
+
+/**
+ * @brief This macro is used to get ACMP interrupt flag
+ * @param[in] acmp The pointer of the specified ACMP module
+ * @param[in] u32ChNum The ACMP number
+ * @return ACMP interrupt occurred (1) or not (0)
+ * @details This macro will return the ACMP interrupt flag.
+ */
+#define ACMP_GET_INT_FLAG(acmp, u32ChNum) (((acmp)->STATUS & (ACMP_STATUS_ACMPIF0_Msk<<((u32ChNum)%2)))?1:0)
+
+/**
+ * @brief This macro is used to clear ACMP interrupt flag
+ * @param[in] acmp The pointer of the specified ACMP module
+ * @param[in] u32ChNum The ACMP number
+ * @return None
+ * @details This macro will write 1 to ACMPIFn bit of ACMP_STATUS register to clear interrupt flag.
+ */
+#define ACMP_CLR_INT_FLAG(acmp, u32ChNum) ((acmp)->STATUS = (ACMP_STATUS_ACMPIF0_Msk<<((u32ChNum)%2)))
+
+/**
+ * @brief This macro is used to clear ACMP wake-up interrupt flag
+ * @param[in] acmp The pointer of the specified ACMP module
+ * @param[in] u32ChNum The ACMP number
+ * @return None
+ * @details This macro will write 1 to WKIFn bit of ACMP_STATUS register to clear interrupt flag.
+ */
+#define ACMP_CLR_WAKEUP_INT_FLAG(acmp, u32ChNum) ((acmp)->STATUS = (ACMP_STATUS_WKIF0_Msk<<((u32ChNum)%2)))
+
+/**
+ * @brief This macro is used to enable ACMP wake-up function
+ * @param[in] acmp The pointer of the specified ACMP module
+ * @param[in] u32ChNum The ACMP number
+ * @return None
+ * @details This macro will set WKEN (ACMP_CTL[16]) to enable ACMP wake-up function.
+ */
+#define ACMP_ENABLE_WAKEUP(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)%2] |= ACMP_CTL_WKEN_Msk)
+
+/**
+ * @brief This macro is used to disable ACMP wake-up function
+ * @param[in] acmp The pointer of the specified ACMP module
+ * @param[in] u32ChNum The ACMP number
+ * @return None
+ * @details This macro will clear WKEN (ACMP_CTL[16]) to disable ACMP wake-up function.
+ */
+#define ACMP_DISABLE_WAKEUP(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)%2] &= ~ACMP_CTL_WKEN_Msk)
+
+/**
+ * @brief This macro is used to select ACMP positive input pin
+ * @param[in] acmp The pointer of the specified ACMP module
+ * @param[in] u32ChNum The ACMP number
+ * @param[in] u32Pin Comparator positive pin selection. Including:
+ * - \ref ACMP_CTL_POSSEL_P0
+ * - \ref ACMP_CTL_POSSEL_P1
+ * - \ref ACMP_CTL_POSSEL_P2
+ * - \ref ACMP_CTL_POSSEL_P3
+ * @return None
+ * @details This macro will set POSSEL (ACMP_CTL[7:6]) to determine the comparator positive input pin.
+ */
+#define ACMP_SELECT_P(acmp, u32ChNum, u32Pin) ((acmp)->CTL[(u32ChNum)%2] = ((acmp)->CTL[(u32ChNum)%2] & ~ACMP_CTL_POSSEL_Msk) | (u32Pin))
+
+/**
+ * @brief This macro is used to enable ACMP filter function
+ * @param[in] acmp The pointer of the specified ACMP module
+ * @param[in] u32ChNum The ACMP number
+ * @return None
+ * @details This macro will set OUTSEL (ACMP_CTL[12]) to enable output filter function.
+ */
+#define ACMP_ENABLE_FILTER(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)%2] |= ACMP_CTL_OUTSEL_Msk)
+
+/**
+ * @brief This macro is used to disable ACMP filter function
+ * @param[in] acmp The pointer of the specified ACMP module
+ * @param[in] u32ChNum The ACMP number
+ * @return None
+ * @details This macro will clear OUTSEL (ACMP_CTL[12]) to disable output filter function.
+ */
+#define ACMP_DISABLE_FILTER(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)%2] &= ~ACMP_CTL_OUTSEL_Msk)
+
+/**
+ * @brief This macro is used to set ACMP filter function
+ * @param[in] acmp The pointer of the specified ACMP module
+ * @param[in] u32ChNum The ACMP number
+ * @param[in] u32Cnt is comparator filter count setting.
+ * - \ref ACMP_CTL_FILTSEL_OFF
+ * - \ref ACMP_CTL_FILTSEL_1PCLK
+ * - \ref ACMP_CTL_FILTSEL_2PCLK
+ * - \ref ACMP_CTL_FILTSEL_4PCLK
+ * - \ref ACMP_CTL_FILTSEL_8PCLK
+ * - \ref ACMP_CTL_FILTSEL_16PCLK
+ * - \ref ACMP_CTL_FILTSEL_32PCLK
+ * - \ref ACMP_CTL_FILTSEL_64PCLK
+ * @return None
+ * @details When ACMP output filter function is enabled, the output sampling count is determined by FILTSEL (ACMP_CTL[15:13]).
+ */
+#define ACMP_SET_FILTER(acmp, u32ChNum, u32Cnt) ((acmp)->CTL[(u32ChNum)%2] = ((acmp)->CTL[(u32ChNum)%2] & ~ACMP_CTL_FILTSEL_Msk) | (u32Cnt))
+
+/**
+ * @brief This macro is used to select comparator reference voltage
+ * @param[in] acmp The pointer of the specified ACMP module
+ * @param[in] u32Level The comparator reference voltage setting.
+ * The formula is:
+ * comparator reference voltage = CRV source voltage x (1/6 + u32Level/24)
+ * The range of u32Level is 0 ~ 15.
+ * @return None
+ * @details When CRV is selected as ACMP negative input source, the CRV level is determined by CRVCTL (ACMP_VREF[3:0]).
+ */
+#define ACMP_CRV_SEL(acmp, u32Level) ((acmp)->VREF = ((acmp)->VREF & ~ACMP_VREF_CRVCTL_Msk) | ((u32Level)<VREF = ((acmp)->VREF & ~ACMP_VREF_CRVSSEL_Msk) | (u32Src))
+
+/**
+ * @brief This macro is used to select ACMP interrupt condition
+ * @param[in] acmp The pointer of the specified ACMP module
+ * @param[in] u32ChNum The ACMP number
+ * @param[in] u32Cond Comparator interrupt condition selection. Including:
+ * - \ref ACMP_CTL_INTPOL_RF
+ * - \ref ACMP_CTL_INTPOL_R
+ * - \ref ACMP_CTL_INTPOL_F
+ * @return None
+ * @details The ACMP output interrupt condition can be rising edge, falling edge or any edge.
+ */
+#define ACMP_SELECT_INT_COND(acmp, u32ChNum, u32Cond) ((acmp)->CTL[(u32ChNum)%2] = ((acmp)->CTL[(u32ChNum)%2] & ~ACMP_CTL_INTPOL_Msk) | (u32Cond))
+
+
+
+/* Function prototype declaration */
+void ACMP_Open(ACMP_T *, uint32_t u32ChNum, uint32_t u32NegSrc, uint32_t u32HysteresisEn);
+void ACMP_Close(ACMP_T *, uint32_t u32ChNum);
+
+
+
+/*@}*/ /* end of group ACMP_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group ACMP_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif //__ACMP_H__
+
+/*** (C) COPYRIGHT 2014~2015 Nuvoton Technology Corp. ***/
diff --git a/bsp/nuvoton_m451/Libraries/StdDriver/inc/can.h b/bsp/nuvoton_m451/Libraries/StdDriver/inc/can.h
new file mode 100644
index 0000000000000000000000000000000000000000..7f661c3bb046217dc77104084f78a2397fb66ddb
--- /dev/null
+++ b/bsp/nuvoton_m451/Libraries/StdDriver/inc/can.h
@@ -0,0 +1,175 @@
+/**************************************************************************//**
+ * @file can.h
+ * @version V2.00
+ * $Revision: 9 $
+ * $Date: 15/08/11 10:26a $
+ * @brief M451 Series CAN Driver Header File
+ *
+ * @note
+ * Copyright (C) 2014~2015 Nuvoton Technology Corp. All rights reserved.
+ *
+ ******************************************************************************/
+#ifndef __CAN_H__
+#define __CAN_H__
+
+#include "M451Series.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup Standard_Driver Standard Driver
+ @{
+*/
+
+/** @addtogroup CAN_Driver CAN Driver
+ @{
+*/
+
+/** @addtogroup CAN_EXPORTED_CONSTANTS CAN Exported Constants
+ @{
+*/
+/*---------------------------------------------------------------------------------------------------------*/
+/* CAN Test Mode Constant Definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define CAN_NORMAL_MODE 0
+#define CAN_BASIC_MODE 1
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Message ID Type Constant Definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define CAN_STD_ID 0
+#define CAN_EXT_ID 1
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Message Frame Type Constant Definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define CAN_REMOTE_FRAME 0
+#define CAN_DATA_FRAME 1
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* CAN message structure */
+/*---------------------------------------------------------------------------------------------------------*/
+typedef struct
+{
+ uint32_t IdType;
+ uint32_t FrameType;
+ uint32_t Id;
+ uint8_t DLC;
+ uint8_t Data[8];
+} STR_CANMSG_T;
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* CAN mask message structure */
+/*---------------------------------------------------------------------------------------------------------*/
+typedef struct
+{
+ uint8_t u8Xtd;
+ uint8_t u8Dir;
+ uint32_t u32Id;
+ uint8_t u8IdType;
+} STR_CANMASK_T;
+
+#define MSG(id) (id)
+
+
+/*@}*/ /* end of group CAN_EXPORTED_CONSTANTS */
+
+
+/** @addtogroup CAN_EXPORTED_FUNCTIONS CAN Exported Functions
+ @{
+*/
+
+/**
+ * @brief Get interrupt status.
+ *
+ * @param[in] can The base address of can module.
+ *
+ * @return CAN module status register value.
+ *
+ * @details Status Interrupt is generated by bits BOff (CAN_STATUS[7]), EWarn (CAN_STATUS[6]),
+ * EPass (CAN_STATUS[5]), RxOk (CAN_STATUS[4]), TxOk (CAN_STATUS[3]), and LEC (CAN_STATUS[2:0]).
+ */
+#define CAN_GET_INT_STATUS(can) ((can)->STATUS)
+
+/**
+ * @brief Get specified interrupt pending status.
+ *
+ * @param[in] can The base address of can module.
+ *
+ * @return The source of the interrupt.
+ *
+ * @details If several interrupts are pending, the CAN Interrupt Register will point to the pending interrupt
+ * with the highest priority, disregarding their chronological order.
+ */
+#define CAN_GET_INT_PENDING_STATUS(can) ((can)->IIDR)
+
+/**
+ * @brief Disable wake-up function.
+ *
+ * @param[in] can The base address of can module.
+ *
+ * @return None
+ *
+ * @details The macro is used to disable wake-up function.
+ */
+#define CAN_DISABLE_WAKEUP(can) ((can)->WU_EN = 0)
+
+/**
+ * @brief Enable wake-up function.
+ *
+ * @param[in] can The base address of can module.
+ *
+ * @return None
+ *
+ * @details User can wake-up system when there is a falling edge in the CAN_Rx pin.
+ */
+#define CAN_ENABLE_WAKEUP(can) ((can)->WU_EN = CAN_WUEN_WAKUP_EN_Msk)
+
+/**
+ * @brief Get specified Message Object new data into bit value.
+ *
+ * @param[in] can The base address of can module.
+ * @param[in] u32MsgNum Specified Message Object number, valid value are from 0 to 31.
+ *
+ * @return Specified Message Object new data into bit value.
+ *
+ * @details The NewDat bit (CAN_IFn_MCON[15]) of a specific Message Object can be set/reset by the software through the IFn Message Interface Registers
+ * or by the Message Handler after reception of a Data Frame or after a successful transmission.
+ */
+#define CAN_GET_NEW_DATA_IN_BIT(can, u32MsgNum) ((u32MsgNum) < 16 ? (can)->NDAT1 & (1 << (u32MsgNum)) : (can)->NDAT2 & (1 << ((u32MsgNum)-16)))
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Define CAN functions prototype */
+/*---------------------------------------------------------------------------------------------------------*/
+uint32_t CAN_SetBaudRate(CAN_T *tCAN, uint32_t u32BaudRate);
+uint32_t CAN_Open(CAN_T *tCAN, uint32_t u32BaudRate, uint32_t u32Mode);
+void CAN_Close(CAN_T *tCAN);
+void CAN_CLR_INT_PENDING_BIT(CAN_T *tCAN, uint8_t u32MsgNum);
+void CAN_EnableInt(CAN_T *tCAN, uint32_t u32Mask);
+void CAN_DisableInt(CAN_T *tCAN, uint32_t u32Mask);
+int32_t CAN_Transmit(CAN_T *tCAN, uint32_t u32MsgNum , STR_CANMSG_T* pCanMsg);
+int32_t CAN_Receive(CAN_T *tCAN, uint32_t u32MsgNum , STR_CANMSG_T* pCanMsg);
+int32_t CAN_SetMultiRxMsg(CAN_T *tCAN, uint32_t u32MsgNum , uint32_t u32MsgCount, uint32_t u32IDType, uint32_t u32ID);
+int32_t CAN_SetRxMsg(CAN_T *tCAN, uint32_t u32MsgNum , uint32_t u32IDType, uint32_t u32ID);
+int32_t CAN_SetRxMsgAndMsk(CAN_T *tCAN, uint32_t u32MsgNum , uint32_t u32IDType, uint32_t u32ID, uint32_t u32IDMask);
+int32_t CAN_SetTxMsg(CAN_T *tCAN, uint32_t u32MsgNum , STR_CANMSG_T* pCanMsg);
+int32_t CAN_TriggerTxMsg(CAN_T *tCAN, uint32_t u32MsgNum);
+
+
+/*@}*/ /* end of group CAN_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group CAN_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif //__CAN_H__
+
+/*** (C) COPYRIGHT 2014~2015 Nuvoton Technology Corp. ***/
diff --git a/bsp/nuvoton_m451/Libraries/StdDriver/inc/clk.h b/bsp/nuvoton_m451/Libraries/StdDriver/inc/clk.h
new file mode 100644
index 0000000000000000000000000000000000000000..7b4da2ba5e7fff8e4d19f7e7ec58d798f8dcb292
--- /dev/null
+++ b/bsp/nuvoton_m451/Libraries/StdDriver/inc/clk.h
@@ -0,0 +1,447 @@
+/******************************************************************************
+ * @file CLK.h
+ * @version V3.0
+ * $Revision 1 $
+ * $Date: 15/08/11 10:26a $
+ * @brief M451 Series CLK Header File
+ *
+ * @note
+ * Copyright (C) 2013~2015 Nuvoton Technology Corp. All rights reserved.
+ ******************************************************************************/
+#ifndef __CLK_H__
+#define __CLK_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/** @addtogroup Standard_Driver Standard Driver
+ @{
+*/
+
+/** @addtogroup CLK_Driver CLK Driver
+ @{
+*/
+
+/** @addtogroup CLK_EXPORTED_CONSTANTS CLK Exported Constants
+ @{
+*/
+
+
+#define FREQ_25MHZ 25000000
+#define FREQ_50MHZ 50000000
+#define FREQ_72MHZ 72000000
+#define FREQ_125MHZ 125000000
+#define FREQ_200MHZ 200000000
+#define FREQ_250MHZ 250000000
+#define FREQ_500MHZ 500000000
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* CLKSEL0 constant definitions. (Write-protection) */
+/*---------------------------------------------------------------------------------------------------------*/
+#define CLK_CLKSEL0_HCLKSEL_HXT (0x00UL< 250MHz is preferred.) */
+#define CLK_PLLCTL_NR(x) (((x)-2)<<9) /*!< x must be constant and 2 <= x <= 33. 1.6MHz < FIN/NR < 16MHz */
+
+#define CLK_PLLCTL_NO_1 0x0000UL /*!< For output divider is 1 */
+#define CLK_PLLCTL_NO_2 0x4000UL /*!< For output divider is 2 */
+#define CLK_PLLCTL_NO_4 0xC000UL /*!< For output divider is 4 */
+
+#define CLK_PLLCTL_72MHz_HXT (CLK_PLLCTL_PLLSRC_HXT | CLK_PLLCTL_NR(2) | CLK_PLLCTL_NF( 48) | CLK_PLLCTL_NO_4) /*!< Predefined PLLCTL setting for 72MHz PLL output with HXT(12MHz X'tal) */
+#define CLK_PLLCTL_144MHz_HXT (CLK_PLLCTL_PLLSRC_HXT | CLK_PLLCTL_NR(2) | CLK_PLLCTL_NF( 48) | CLK_PLLCTL_NO_2) /*!< Predefined PLLCTL setting for 144MHz PLL output with HXT(12MHz X'tal) */
+#define CLK_PLLCTL_72MHz_HIRC (CLK_PLLCTL_PLLSRC_HIRC | CLK_PLLCTL_NR(4) | CLK_PLLCTL_NF( 52) | CLK_PLLCTL_NO_4) /*!< Predefined PLLCTL setting for 71.8848MHz PLL output with HIRC(22.1184MHz IRC) */
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* MODULE constant definitions. */
+/*---------------------------------------------------------------------------------------------------------*/
+
+/* APBCLK(31:30)|CLKSEL(29:28)|CLKSEL_Msk(27:25) |CLKSEL_Pos(24:20)|CLKDIV(19:18)|CLKDIV_Msk(17:10)|CLKDIV_Pos(9:5)|IP_EN_Pos(4:0) */
+
+#define MODULE_APBCLK(x) (((x) >>30) & 0x3) /*!< Calculate AHBCLK/APBCLK offset on MODULE index, 0x0:AHBCLK, 0x1:APBCLK0, 0x2:APBCLK1 */
+#define MODULE_CLKSEL(x) (((x) >>28) & 0x3) /*!< Calculate CLKSEL offset on MODULE index, 0x0:CLKSEL0, 0x1:CLKSEL1, 0x2:CLKSEL2, 0x3:CLKSEL3 */
+#define MODULE_CLKSEL_Msk(x) (((x) >>25) & 0x7) /*!< Calculate CLKSEL mask offset on MODULE index */
+#define MODULE_CLKSEL_Pos(x) (((x) >>20) & 0x1f) /*!< Calculate CLKSEL position offset on MODULE index */
+#define MODULE_CLKDIV(x) (((x) >>18) & 0x3) /*!< Calculate APBCLK CLKDIV on MODULE index, 0x0:CLKDIV, 0x1:CLKDIV1 */
+#define MODULE_CLKDIV_Msk(x) (((x) >>10) & 0xff) /*!< Calculate CLKDIV mask offset on MODULE index */
+#define MODULE_CLKDIV_Pos(x) (((x) >>5 ) & 0x1f) /*!< Calculate CLKDIV position offset on MODULE index */
+#define MODULE_IP_EN_Pos(x) (((x) >>0 ) & 0x1f) /*!< Calculate APBCLK offset on MODULE index */
+#define MODULE_NoMsk 0x0 /*!< Not mask on MODULE index */
+#define NA MODULE_NoMsk /*!< Not Available */
+
+#define MODULE_APBCLK_ENC(x) (((x) & 0x03) << 30) /*!< MODULE index, 0x0:AHBCLK, 0x1:APBCLK0, 0x2:APBCLK1 */
+#define MODULE_CLKSEL_ENC(x) (((x) & 0x03) << 28) /*!< CLKSEL offset on MODULE index, 0x0:CLKSEL0, 0x1:CLKSEL1, 0x2:CLKSEL2, 0x3:CLKSEL3 */
+#define MODULE_CLKSEL_Msk_ENC(x) (((x) & 0x07) << 25) /*!< CLKSEL mask offset on MODULE index */
+#define MODULE_CLKSEL_Pos_ENC(x) (((x) & 0x1f) << 20) /*!< CLKSEL position offset on MODULE index */
+#define MODULE_CLKDIV_ENC(x) (((x) & 0x03) << 18) /*!< APBCLK CLKDIV on MODULE index, 0x0:CLKDIV, 0x1:CLKDIV1 */
+#define MODULE_CLKDIV_Msk_ENC(x) (((x) & 0xff) << 10) /*!< CLKDIV mask offset on MODULE index */
+#define MODULE_CLKDIV_Pos_ENC(x) (((x) & 0x1f) << 5) /*!< CLKDIV position offset on MODULE index */
+#define MODULE_IP_EN_Pos_ENC(x) (((x) & 0x1f) << 0) /*!< AHBCLK/APBCLK offset on MODULE index */
+
+
+//AHBCLK
+#define PDMA_MODULE (MODULE_APBCLK_ENC( 0)|MODULE_IP_EN_Pos_ENC(CLK_AHBCLK_PDMACKEN_Pos) |\
+ MODULE_CLKSEL_ENC(NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
+ MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< PDMA Module */
+
+#define ISP_MODULE (MODULE_APBCLK_ENC( 0)|MODULE_IP_EN_Pos_ENC(CLK_AHBCLK_ISPCKEN_Pos) |\
+ MODULE_CLKSEL_ENC(NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
+ MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< ISP Module */
+
+#define EBI_MODULE (MODULE_APBCLK_ENC( 0)|MODULE_IP_EN_Pos_ENC(CLK_AHBCLK_EBICKEN_Pos) |\
+ MODULE_CLKSEL_ENC(NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
+ MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< EBI Module */
+
+#define USBH_MODULE (MODULE_APBCLK_ENC( 0)|MODULE_IP_EN_Pos_ENC(CLK_AHBCLK_USBHCKEN_Pos) |\
+ MODULE_CLKSEL_ENC(NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
+ MODULE_CLKDIV_ENC( 0)|MODULE_CLKDIV_Msk_ENC(0x0F)|MODULE_CLKDIV_Pos_ENC(4)) /*!< USBH Module */
+
+#define CRC_MODULE (MODULE_APBCLK_ENC( 0)|MODULE_IP_EN_Pos_ENC(CLK_AHBCLK_CRCCKEN_Pos) |\
+ MODULE_CLKSEL_ENC(NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
+ MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< CRC Module */
+
+
+//APBCLK0
+#define WDT_MODULE (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK0_WDTCKEN_Pos) |\
+ MODULE_CLKSEL_ENC( 1)|MODULE_CLKSEL_Msk_ENC( 3)|MODULE_CLKSEL_Pos_ENC( 0)|\
+ MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< WDT Module */
+
+#define WWDT_MODULE (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK0_WDTCKEN_Pos) |\
+ MODULE_CLKSEL_ENC( 1)|MODULE_CLKSEL_Msk_ENC( 3)|MODULE_CLKSEL_Pos_ENC(30)|\
+ MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< WWDT Module */
+
+#define RTC_MODULE (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK0_RTCCKEN_Pos) |\
+ MODULE_CLKSEL_ENC( 3)|MODULE_CLKSEL_Msk_ENC( 1)|MODULE_CLKSEL_Pos_ENC( 8)|\
+ MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< RTC Module */
+
+#define TMR0_MODULE (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK0_TMR0CKEN_Pos) |\
+ MODULE_CLKSEL_ENC( 1)|MODULE_CLKSEL_Msk_ENC( 7)|MODULE_CLKSEL_Pos_ENC( 8)|\
+ MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< TMR0 Module */
+
+#define TMR1_MODULE (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK0_TMR1CKEN_Pos) |\
+ MODULE_CLKSEL_ENC( 1)|MODULE_CLKSEL_Msk_ENC( 7)|MODULE_CLKSEL_Pos_ENC(12)|\
+ MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< TMR1 Module */
+
+#define TMR2_MODULE (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK0_TMR2CKEN_Pos) |\
+ MODULE_CLKSEL_ENC( 1)|MODULE_CLKSEL_Msk_ENC( 7)|MODULE_CLKSEL_Pos_ENC(16)|\
+ MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< TMR2 Module */
+
+#define TMR3_MODULE (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK0_TMR3CKEN_Pos) |\
+ MODULE_CLKSEL_ENC( 1)|MODULE_CLKSEL_Msk_ENC( 7)|MODULE_CLKSEL_Pos_ENC(20)|\
+ MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< TMR3 Module */
+
+#define CLKO_MODULE (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK0_CLKOCKEN_Pos) |\
+ MODULE_CLKSEL_ENC( 1)|MODULE_CLKSEL_Msk_ENC( 3)|MODULE_CLKSEL_Pos_ENC(28)|\
+ MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< CLKO Module */
+
+#define ACMP01_MODULE (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK0_ACMP01CKEN_Pos) |\
+ MODULE_CLKSEL_ENC(NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
+ MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< ACMP01 Module */
+
+#define I2C0_MODULE (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK0_I2C0CKEN_Pos) |\
+ MODULE_CLKSEL_ENC(NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
+ MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< I2C0 Module */
+
+#define I2C1_MODULE (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK0_I2C1CKEN_Pos) |\
+ MODULE_CLKSEL_ENC(NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
+ MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< I2C1 Module */
+
+#define SPI0_MODULE (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK0_SPI0CKEN_Pos) |\
+ MODULE_CLKSEL_ENC( 2)|MODULE_CLKSEL_Msk_ENC( 3)|MODULE_CLKSEL_Pos_ENC( 2)|\
+ MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< SPI0 Module */
+
+#define SPI1_MODULE (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK0_SPI1CKEN_Pos) |\
+ MODULE_CLKSEL_ENC( 2)|MODULE_CLKSEL_Msk_ENC( 3)|MODULE_CLKSEL_Pos_ENC( 4)|\
+ MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< SPI1 Module */
+
+#define SPI2_MODULE (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK0_SPI2CKEN_Pos) |\
+ MODULE_CLKSEL_ENC( 2)|MODULE_CLKSEL_Msk_ENC( 3)|MODULE_CLKSEL_Pos_ENC( 6)|\
+ MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< SPI2 Module */
+
+#define UART0_MODULE (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK0_UART0CKEN_Pos)|\
+ MODULE_CLKSEL_ENC( 1)|MODULE_CLKSEL_Msk_ENC( 3)|MODULE_CLKSEL_Pos_ENC(24)|\
+ MODULE_CLKDIV_ENC( 0)|MODULE_CLKDIV_Msk_ENC(0x0F)|MODULE_CLKDIV_Pos_ENC( 8)) /*!< UART0 Module */
+
+#define UART1_MODULE (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK0_UART1CKEN_Pos)|\
+ MODULE_CLKSEL_ENC( 1)|MODULE_CLKSEL_Msk_ENC( 3)|MODULE_CLKSEL_Pos_ENC(24)|\
+ MODULE_CLKDIV_ENC( 0)|MODULE_CLKDIV_Msk_ENC(0x0F)|MODULE_CLKDIV_Pos_ENC( 8)) /*!< UART1 Module */
+
+#define UART2_MODULE (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK0_UART2CKEN_Pos)|\
+ MODULE_CLKSEL_ENC( 1)|MODULE_CLKSEL_Msk_ENC( 3)|MODULE_CLKSEL_Pos_ENC(24)|\
+ MODULE_CLKDIV_ENC( 0)|MODULE_CLKDIV_Msk_ENC(0x0F)|MODULE_CLKDIV_Pos_ENC( 8)) /*!< UART2 Module */
+
+#define UART3_MODULE (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK0_UART3CKEN_Pos)|\
+ MODULE_CLKSEL_ENC( 1)|MODULE_CLKSEL_Msk_ENC( 3)|MODULE_CLKSEL_Pos_ENC(24)|\
+ MODULE_CLKDIV_ENC( 0)|MODULE_CLKDIV_Msk_ENC(0x0F)|MODULE_CLKDIV_Pos_ENC( 8)) /*!< UART3 Module */
+
+#define CAN0_MODULE (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK0_CAN0CKEN_Pos) |\
+ MODULE_CLKSEL_ENC(NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
+ MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< CAN0 Module */
+
+#define OTG_MODULE (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK0_OTGCKEN_Pos) |\
+ MODULE_CLKSEL_ENC(NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
+ MODULE_CLKDIV_ENC( 0)|MODULE_CLKDIV_Msk_ENC(0x0F)|MODULE_CLKDIV_Pos_ENC(4)) /*!< OTG Module */
+
+#define USBD_MODULE (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK0_USBDCKEN_Pos) |\
+ MODULE_CLKSEL_ENC(NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
+ MODULE_CLKDIV_ENC( 0)|MODULE_CLKDIV_Msk_ENC(0x0F)|MODULE_CLKDIV_Pos_ENC(4)) /*!< USBD Module */
+
+#define EADC_MODULE (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK0_EADCCKEN_Pos) |\
+ MODULE_CLKSEL_ENC(NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
+ MODULE_CLKDIV_ENC( 0)|MODULE_CLKDIV_Msk_ENC(0xFF)|MODULE_CLKDIV_Pos_ENC(16)) /*!< EADC Module */
+
+
+//APBCLK1
+#define SC0_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK1_SC0CKEN_Pos) |\
+ MODULE_CLKSEL_ENC( 3)|MODULE_CLKSEL_Msk_ENC( 3)|MODULE_CLKSEL_Pos_ENC( 0)|\
+ MODULE_CLKDIV_ENC( 1)|MODULE_CLKDIV_Msk_ENC(0xFF)|MODULE_CLKDIV_Pos_ENC( 0)) /*!< SC0 Module */
+
+#define DAC_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK1_DACCKEN_Pos) |\
+ MODULE_CLKSEL_ENC(NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
+ MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< DAC Module */
+
+#define PWM0_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK1_PWM0CKEN_Pos)|\
+ MODULE_CLKSEL_ENC( 2)|MODULE_CLKSEL_Msk_ENC( 1)|MODULE_CLKSEL_Pos_ENC( 0)|\
+ MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< PWM0 Module */
+
+#define PWM1_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK1_PWM1CKEN_Pos)|\
+ MODULE_CLKSEL_ENC( 2)|MODULE_CLKSEL_Msk_ENC( 1)|MODULE_CLKSEL_Pos_ENC( 1)|\
+ MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< PWM1 Module */
+
+#define TK_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK1_TKCKEN_Pos)|\
+ MODULE_CLKSEL_ENC(NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
+ MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< TK Module */
+
+
+/*@}*/ /* end of group CLK_EXPORTED_CONSTANTS */
+
+
+/** @addtogroup CLK_EXPORTED_FUNCTIONS CLK Exported Functions
+ @{
+*/
+
+
+/**
+ * @brief Get PLL clock frequency
+ * @param None
+ * @return PLL frequency
+ * @details This function get PLL frequency. The frequency unit is Hz.
+ */
+__STATIC_INLINE uint32_t CLK_GetPLLClockFreq(void)
+{
+ uint32_t u32PllFreq = 0, u32PllReg;
+ uint32_t u32FIN, u32NF, u32NR, u32NO;
+ uint8_t au8NoTbl[4] = {1, 2, 2, 4};
+
+ u32PllReg = CLK->PLLCTL;
+
+ if(u32PllReg & (CLK_PLLCTL_PD_Msk | CLK_PLLCTL_OE_Msk))
+ return 0; /* PLL is in power down mode or fix low */
+
+ if(u32PllReg & CLK_PLLCTL_PLLSRC_HIRC)
+ u32FIN = __HIRC; /* PLL source clock from HIRC */
+ else
+ u32FIN = __HXT; /* PLL source clock from HXT */
+
+ if(u32PllReg & CLK_PLLCTL_BP_Msk)
+ return u32FIN; /* PLL is in bypass mode */
+
+ /* PLL is output enabled in normal work mode */
+ u32NO = au8NoTbl[((u32PllReg & CLK_PLLCTL_OUTDIV_Msk) >> CLK_PLLCTL_OUTDIV_Pos)];
+ u32NF = ((u32PllReg & CLK_PLLCTL_FBDIV_Msk) >> CLK_PLLCTL_FBDIV_Pos) + 2;
+ u32NR = ((u32PllReg & CLK_PLLCTL_INDIV_Msk) >> CLK_PLLCTL_INDIV_Pos) + 2;
+
+ /* u32FIN is shifted 2 bits to avoid overflow */
+ u32PllFreq = (((u32FIN >> 2) * u32NF) / (u32NR * u32NO) << 2);
+
+ return u32PllFreq;
+}
+
+/**
+ * @brief This function execute delay function.
+ * @param us Delay time. The Max value is 2^24 / CPU Clock(MHz). Ex:
+ * 72MHz => 233016us, 50MHz => 335544us,
+ 48MHz => 349525us, 28MHz => 699050us ...
+ * @return None
+ * @details Use the SysTick to generate the delay time and the unit is in us.
+ * The SysTick clock source is from HCLK, i.e the same as system core clock.
+ */
+__STATIC_INLINE void CLK_SysTickDelay(uint32_t us)
+{
+ SysTick->LOAD = us * CyclesPerUs;
+ SysTick->VAL = (0x00);
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk;
+
+ /* Waiting for down-count to zero */
+ while((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == 0);
+
+ /* Disable SysTick counter */
+ SysTick->CTRL = 0;
+}
+
+
+void CLK_DisableCKO(void);
+void CLK_EnableCKO(uint32_t u32ClkSrc, uint32_t u32ClkDiv, uint32_t u32ClkDivBy1En);
+void CLK_PowerDown(void);
+void CLK_Idle(void);
+uint32_t CLK_GetHXTFreq(void);
+uint32_t CLK_GetLXTFreq(void);
+uint32_t CLK_GetHCLKFreq(void);
+uint32_t CLK_GetPCLK0Freq(void);
+uint32_t CLK_GetPCLK1Freq(void);
+uint32_t CLK_GetCPUFreq(void);
+uint32_t CLK_SetCoreClock(uint32_t u32Hclk);
+void CLK_SetHCLK(uint32_t u32ClkSrc, uint32_t u32ClkDiv);
+void CLK_SetModuleClock(uint32_t u32ModuleIdx, uint32_t u32ClkSrc, uint32_t u32ClkDiv);
+void CLK_SetSysTickClockSrc(uint32_t u32ClkSrc);
+void CLK_EnableXtalRC(uint32_t u32ClkMask);
+void CLK_DisableXtalRC(uint32_t u32ClkMask);
+void CLK_EnableModuleClock(uint32_t u32ModuleIdx);
+void CLK_DisableModuleClock(uint32_t u32ModuleIdx);
+uint32_t CLK_EnablePLL(uint32_t u32PllClkSrc, uint32_t u32PllFreq);
+void CLK_DisablePLL(void);
+uint32_t CLK_WaitClockReady(uint32_t u32ClkMask);
+void CLK_EnableSysTick(uint32_t u32ClkSrc, uint32_t u32Count);
+void CLK_DisableSysTick(void);
+
+
+
+/*@}*/ /* end of group CLK_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group CLK_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif //__CLK_H__
diff --git a/bsp/nuvoton_m451/Libraries/StdDriver/inc/crc.h b/bsp/nuvoton_m451/Libraries/StdDriver/inc/crc.h
new file mode 100644
index 0000000000000000000000000000000000000000..4c8c3332625d6918fbcd0d34775dc0dfdaed4fae
--- /dev/null
+++ b/bsp/nuvoton_m451/Libraries/StdDriver/inc/crc.h
@@ -0,0 +1,112 @@
+/**************************************************************************//**
+ * @file crc.h
+ * @version V3.00
+ * $Revision: 6 $
+ * $Date: 15/08/11 10:26a $
+ * @brief M451 series CRC driver header file
+ *
+ * @note
+ * Copyright (C) 2013~2015 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __CRC_H__
+#define __CRC_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup Standard_Driver Standard Driver
+ @{
+*/
+
+/** @addtogroup CRC_Driver CRC Driver
+ @{
+*/
+
+/** @addtogroup CRC_EXPORTED_CONSTANTS CRC Exported Constants
+ @{
+*/
+/*---------------------------------------------------------------------------------------------------------*/
+/* CRC Polynomial Mode Constant Definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define CRC_CCITT 0x00000000UL /*!SEED = (u32Seed); CRC->CTL |= CRC_CTL_CRCRST_Msk; }
+
+/**
+ * @brief Get CRC Seed Value
+ *
+ * @param None
+ *
+ * @return CRC seed value
+ *
+ * @details This macro gets the current CRC seed value.
+ */
+#define CRC_GET_SEED() (CRC->SEED)
+
+/**
+ * @brief CRC Write Data
+ *
+ * @param[in] u32Data Write data
+ *
+ * @return None
+ *
+ * @details User can write data directly to CRC Write Data Register(CRC_DAT) by this macro to perform CRC operation.
+ */
+#define CRC_WRITE_DATA(u32Data) (CRC->DAT = (u32Data))
+
+void CRC_Open(uint32_t u32Mode, uint32_t u32Attribute, uint32_t u32Seed, uint32_t u32DataLen);
+uint32_t CRC_GetChecksum(void);
+
+/*@}*/ /* end of group CRC_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group CRC_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif //__CRC_H__
+
+/*** (C) COPYRIGHT 2013~2015 Nuvoton Technology Corp. ***/
diff --git a/bsp/nuvoton_m451/Libraries/StdDriver/inc/dac.h b/bsp/nuvoton_m451/Libraries/StdDriver/inc/dac.h
new file mode 100644
index 0000000000000000000000000000000000000000..c0914a3a7445984c490778b77f30272078d4e386
--- /dev/null
+++ b/bsp/nuvoton_m451/Libraries/StdDriver/inc/dac.h
@@ -0,0 +1,245 @@
+/******************************************************************************
+ * @file dac.h
+ * @version V0.10
+ * $Revision: 12 $
+ * $Date: 15/08/11 10:26a $
+ * @brief M451 series DAC driver header file
+ *
+ * @note
+ * Copyright (C) 2013~2015 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#ifndef __DAC_H__
+#define __DAC_H__
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Include related headers */
+/*---------------------------------------------------------------------------------------------------------*/
+#include "M451Series.h"
+
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup Standard_Driver Standard Driver
+ @{
+*/
+
+/** @addtogroup DAC_Driver DAC Driver
+ @{
+*/
+
+
+/** @addtogroup DAC_EXPORTED_CONSTANTS DAC Exported Constants
+ @{
+*/
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* DAC_CTL Constant Definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define DAC_CTL_LALIGN_RIGHT_ALIGN (0UL<SWTRG = DAC_SWTRG_SWTRG_Msk)
+
+/**
+ * @brief Enable DAC data left-aligned.
+ * @param[in] dac Base address of DAC module.
+ * @return None
+ * @details User has to load data into DAC_DAT[15:4] bits. DAC_DAT[31:16] and DAC_DAT[3:0] are ignored in DAC conversion.
+ */
+#define DAC_ENABLE_LEFT_ALIGN(dac) ((dac)->CTL |= DAC_CTL_LALIGN_Msk)
+
+/**
+ * @brief Enable DAC data right-aligned.
+ * @param[in] dac Base address of DAC module.
+ * @return None
+ * @details User has to load data into DAC_DAT[11:0] bits, DAC_DAT[31:12] are ignored in DAC conversion.
+ */
+#define DAC_ENABLE_RIGHT_ALIGN(dac) ((dac)->CTL &= ~DAC_CTL_LALIGN_Msk)
+
+/**
+ * @brief Enable output voltage buffer.
+ * @param[in] dac Base address of DAC module.
+ * @return None
+ * @details The DAC integrates a voltage output buffer that can be used to reduce output impedance and
+ * drive external loads directly without having to add an external operational amplifier.
+ */
+#define DAC_ENABLE_BYPASS_BUFFER(dac) ((dac)->CTL |= DAC_CTL_BYPASS_Msk)
+
+/**
+ * @brief Disable output voltage buffer.
+ * @param[in] dac Base address of DAC module.
+ * @return None
+ * @details This macro is used to disable output voltage buffer.
+ */
+#define DAC_DISABLE_BYPASS_BUFFER(dac) ((dac)->CTL &= ~DAC_CTL_BYPASS_Msk)
+
+/**
+ * @brief Enable the interrupt.
+ * @param[in] dac Base address of DAC module.
+ * @param[in] u32Ch Not used in M451 Series DAC.
+ * @return None
+ * @details This macro is used to enable DAC interrupt.
+ */
+#define DAC_ENABLE_INT(dac, u32Ch) ((dac)->CTL |= DAC_CTL_DACIEN_Msk)
+
+/**
+ * @brief Disable the interrupt.
+ * @param[in] dac Base address of DAC module.
+ * @param[in] u32Ch Not used in M451 Series DAC.
+ * @return None
+ * @details This macro is used to disable DAC interrupt.
+ */
+#define DAC_DISABLE_INT(dac, u32Ch) ((dac)->CTL &= ~DAC_CTL_DACIEN_Msk)
+
+/**
+ * @brief Enable DMA under-run interrupt.
+ * @param[in] dac Base address of DAC module.
+ * @return None
+ * @details This macro is used to enable DMA under-run interrupt.
+ */
+#define DAC_ENABLE_DMAUDR_INT(dac) ((dac)->CTL |= DAC_CTL_DMAURIEN_Msk)
+
+/**
+ * @brief Disable DMA under-run interrupt.
+ * @param[in] dac Base address of DAC module.
+ * @return None
+ * @details This macro is used to disable DMA under-run interrupt.
+ */
+#define DAC_DISABLE_DMAUDR_INT(dac) ((dac)->CTL &= ~DAC_CTL_DMAURIEN_Msk)
+
+/**
+ * @brief Enable PDMA mode.
+ * @param[in] dac Base address of DAC module.
+ * @return None
+ * @details DAC DMA request is generated when a hardware trigger event occurs while DMAEN (DAC_CTL[2]) is set.
+ */
+#define DAC_ENABLE_PDMA(dac) ((dac)->CTL |= DAC_CTL_DMAEN_Msk)
+
+/**
+ * @brief Disable PDMA mode.
+ * @param[in] dac Base address of DAC module.
+ * @return None
+ * @details This macro is used to disable DMA mode.
+ */
+#define DAC_DISABLE_PDMA(dac) ((dac)->CTL &= ~DAC_CTL_DMAEN_Msk)
+
+/**
+ * @brief Write data for conversion.
+ * @param[in] dac Base address of DAC module.
+ * @param[in] u32Ch Not used in M451 Series DAC.
+ * @param[in] u32Data Decides the data for conversion, valid range are between 0~0xFFF.
+ * @return None
+ * @details 12 bit left alignment: user has to load data into DAC_DAT[15:4] bits.
+ * 12 bit right alignment: user has to load data into DAC_DAT[11:0] bits.
+ */
+#define DAC_WRITE_DATA(dac, u32Ch, u32Data) ((dac)->DAT = (u32Data))
+
+/**
+ * @brief Read DAC 12-bit holding data.
+ * @param[in] dac Base address of DAC module.
+ * @param[in] u32Ch Not used in M451 Series DAC.
+ * @return Return DAC 12-bit holding data.
+ * @details This macro is used to read DAC_DAT register.
+ */
+#define DAC_READ_DATA(dac, u32Ch) ((dac)->DAT)
+
+/**
+ * @brief Get the busy state of DAC.
+ * @param[in] dac Base address of DAC module.
+ * @param[in] u32Ch Not used in M451 Series DAC.
+ * @retval 0 Idle state.
+ * @retval 1 Busy state.
+ * @details This macro is used to read BUSY bit (DAC_STATUS[8]) to get busy state.
+ */
+#define DAC_IS_BUSY(dac, u32Ch) (((dac)->STATUS & DAC_STATUS_BUSY_Msk) >> DAC_STATUS_BUSY_Pos)
+
+/**
+ * @brief Get the interrupt flag.
+ * @param[in] dac Base address of DAC module.
+ * @param[in] u32Ch Not used in M451 Series DAC.
+ * @retval 0 DAC is in conversion state.
+ * @retval 1 DAC conversion finish.
+ * @details This macro is used to read FINISH bit (DAC_STATUS[0]) to get DAC conversion complete finish flag.
+ */
+#define DAC_GET_INT_FLAG(dac, u32Ch) ((dac)->STATUS & DAC_STATUS_FINISH_Msk)
+
+/**
+ * @brief Get the DMA under-run flag.
+ * @param[in] dac Base address of DAC module.
+ * @retval 0 No DMA under-run error condition occurred.
+ * @retval 1 DMA under-run error condition occurred.
+ * @details This macro is used to read DMAUDR bit (DAC_STATUS[1]) to get DMA under-run state.
+ */
+#define DAC_GET_DMAUDR_FLAG(dac) (((dac)->STATUS & DAC_STATUS_DMAUDR_Msk) >> DAC_STATUS_DMAUDR_Pos)
+
+/**
+ * @brief This macro clear the interrupt status bit.
+ * @param[in] dac Base address of DAC module.
+ * @param[in] u32Ch Not used in M451 Series DAC.
+ * @return None
+ * @details User writes FINISH bit (DAC_STATUS[0]) to clear DAC conversion complete finish flag.
+ */
+#define DAC_CLR_INT_FLAG(dac, u32Ch) ((dac)->STATUS = DAC_STATUS_FINISH_Msk)
+
+/**
+ * @brief This macro clear the DMA under-run flag.
+ * @param[in] dac Base address of DAC module.
+ * @return None
+ * @details User writes DMAUDR bit (DAC_STATUS[1]) to clear DMA under-run flag.
+ */
+#define DAC_CLR_DMAUDR_FLAG(dac) ((dac)->STATUS = DAC_STATUS_DMAUDR_Msk)
+
+void DAC_Open(DAC_T *dac, uint32_t u32Ch, uint32_t u32TrgSrc);
+void DAC_Close(DAC_T *dac, uint32_t u32Ch);
+float DAC_SetDelayTime(DAC_T *dac, uint32_t u16Delay);
+
+/*@}*/ /* end of group DAC_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group DAC_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif //__DAC_H__
+
+/*** (C) COPYRIGHT 2013~2015 Nuvoton Technology Corp. ***/
diff --git a/bsp/nuvoton_m451/Libraries/StdDriver/inc/eadc.h b/bsp/nuvoton_m451/Libraries/StdDriver/inc/eadc.h
new file mode 100644
index 0000000000000000000000000000000000000000..9751d5781d4c623d0b39dfd4fc4a792fa740aca0
--- /dev/null
+++ b/bsp/nuvoton_m451/Libraries/StdDriver/inc/eadc.h
@@ -0,0 +1,569 @@
+/******************************************************************************
+ * @file eadc.h
+ * @version V0.10
+ * $Revision: 18 $
+ * $Date: 15/08/11 10:26a $
+ * @brief M451 series EADC driver header file
+ *
+ * @note
+ * Copyright (C) 2013~2015 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#ifndef __EADC_H__
+#define __EADC_H__
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Include related headers */
+/*---------------------------------------------------------------------------------------------------------*/
+#include "M451Series.h"
+
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup Standard_Driver Standard Driver
+ @{
+*/
+
+/** @addtogroup EADC_Driver EADC Driver
+ @{
+*/
+
+/** @addtogroup EADC_EXPORTED_CONSTANTS EADC Exported Constants
+ @{
+*/
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* EADC_CTL Constant Definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define EADC_CTL_DIFFEN_SINGLE_END (0UL<CTL |= EADC_CTL_ADRST_Msk)
+
+/**
+ * @brief Enable PDMA transfer.
+ * @param[in] eadc The pointer of the specified EADC module.
+ * @return None
+ * @details When A/D conversion is completed, the converted data is loaded into EADC_DATn (n: 0 ~ 18) register,
+ * user can enable this bit to generate a PDMA data transfer request.
+ * @note When set PDMAEN bit (EADC_CTL[11]), user must set ADINTENn (EADC_CTL[5:2], n=0~3) = 0 to disable interrupt.
+ */
+#define EADC_ENABLE_PDMA(eadc) ((eadc)->CTL |= EADC_CTL_PDMAEN_Msk)
+
+/**
+ * @brief Disable PDMA transfer.
+ * @param[in] eadc The pointer of the specified EADC module.
+ * @return None
+ * @details This macro is used to disable PDMA transfer.
+ */
+#define EADC_DISABLE_PDMA(eadc) ((eadc)->CTL &= (~EADC_CTL_PDMAEN_Msk))
+
+/**
+ * @brief Enable double buffer mode.
+ * @param[in] eadc The pointer of the specified EADC module.
+ * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 3.
+ * @return None
+ * @details The ADC controller supports a double buffer mode in sample module 0~3.
+ * If user enable DBMEN (EADC_SCTLn[23], n=0~3), the double buffer mode will enable.
+ */
+#define EADC_ENABLE_DOUBLE_BUFFER(eadc, u32ModuleNum) ((eadc)->SCTL[(u32ModuleNum)] |= EADC_SCTL_DBMEN_Msk)
+
+/**
+ * @brief Disable double buffer mode.
+ * @param[in] eadc The pointer of the specified EADC module.
+ * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 3.
+ * @return None
+ * @details Sample has one sample result register.
+ */
+#define EADC_DISABLE_DOUBLE_BUFFER(eadc, u32ModuleNum) ((eadc)->SCTL[(u32ModuleNum)] &= ~EADC_SCTL_DBMEN_Msk)
+
+/**
+ * @brief Set ADIFn at A/D end of conversion.
+ * @param[in] eadc The pointer of the specified EADC module.
+ * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 15.
+ * @return None
+ * @details The A/D converter generates ADIFn (EADC_STATUS2[3:0], n=0~3) at the start of conversion.
+ */
+#define EADC_ENABLE_INT_POSITION(eadc, u32ModuleNum) ((eadc)->SCTL[(u32ModuleNum)] |= EADC_SCTL_INTPOS_Msk)
+
+/**
+ * @brief Set ADIFn at A/D start of conversion.
+ * @param[in] eadc The pointer of the specified EADC module.
+ * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 15.
+ * @return None
+ * @details The A/D converter generates ADIFn (EADC_STATUS2[3:0], n=0~3) at the end of conversion.
+ */
+#define EADC_DISABLE_INT_POSITION(eadc, u32ModuleNum) ((eadc)->SCTL[(u32ModuleNum)] &= ~EADC_SCTL_INTPOS_Msk)
+
+/**
+ * @brief Enable the interrupt.
+ * @param[in] eadc The pointer of the specified EADC module.
+ * @param[in] u32Mask Decides the combination of interrupt status bits. Each bit corresponds to a interrupt status.
+ * This parameter decides which interrupts will be enabled. Bit 0 is ADCIEN0, bit 1 is ADCIEN1..., bit 3 is ADCIEN3.
+ * @return None
+ * @details The A/D converter generates a conversion end ADIFn (EADC_STATUS2[n]) upon the end of specific sample module A/D conversion.
+ * If ADCIENn bit (EADC_CTL[n+2]) is set then conversion end interrupt request ADINTn is generated (n=0~3).
+ */
+#define EADC_ENABLE_INT(eadc, u32Mask) ((eadc)->CTL |= ((u32Mask) << EADC_CTL_ADCIEN0_Pos))
+
+/**
+ * @brief Disable the interrupt.
+ * @param[in] eadc The pointer of the specified EADC module.
+ * @param[in] u32Mask Decides the combination of interrupt status bits. Each bit corresponds to a interrupt status.
+ * This parameter decides which interrupts will be disabled. Bit 0 is ADCIEN0, bit 1 is ADCIEN1..., bit 3 is ADCIEN3.
+ * @return None
+ * @details Specific sample module A/D ADINT0 interrupt function Disabled.
+ */
+#define EADC_DISABLE_INT(eadc, u32Mask) ((eadc)->CTL &= ~((u32Mask) << EADC_CTL_ADCIEN0_Pos))
+
+/**
+ * @brief Enable the sample module interrupt.
+ * @param[in] eadc The pointer of the specified EADC module.
+ * @param[in] u32IntSel Decides which interrupt source will be used, valid value are from 0 to 3.
+ * @param[in] u32ModuleMask the combination of sample module interrupt status bits. Each bit corresponds to a sample module interrupt status.
+ * This parameter decides which sample module interrupts will be enabled, valid range are between 1~0x7FFFF.
+ * @return None
+ * @details There are 4 ADC interrupts ADINT0~3, and each of these interrupts has its own interrupt vector address.
+ */
+#define EADC_ENABLE_SAMPLE_MODULE_INT(eadc, u32IntSel, u32ModuleMask) ((eadc)->INTSRC[(u32IntSel)] |= (u32ModuleMask))
+
+/**
+ * @brief Disable the sample module interrupt.
+ * @param[in] eadc The pointer of the specified EADC module.
+ * @param[in] u32IntSel Decides which interrupt source will be used, valid value are from 0 to 3.
+ * @param[in] u32ModuleMask the combination of sample module interrupt status bits. Each bit corresponds to a sample module interrupt status.
+ * This parameter decides which sample module interrupts will be disabled, valid range are between 1~0x7FFFF.
+ * @return None
+ * @details There are 4 ADC interrupts ADINT0~3, and each of these interrupts has its own interrupt vector address.
+ */
+#define EADC_DISABLE_SAMPLE_MODULE_INT(eadc, u32IntSel, u32ModuleMask) ((eadc)->INTSRC[(u32IntSel)] &= ~(u32ModuleMask))
+
+/**
+ * @brief Set the input mode output format.
+ * @param[in] eadc The pointer of the specified EADC module.
+ * @param[in] u32Format Decides the output format. Valid values are:
+ * - \ref EADC_CTL_DMOF_STRAIGHT_BINARY :Select the straight binary format as the output format of the conversion result.
+ * - \ref EADC_CTL_DMOF_TWOS_COMPLEMENT :Select the 2's complement format as the output format of the conversion result.
+ * @return None
+ * @details The macro is used to set A/D input mode output format.
+ */
+#define EADC_SET_DMOF(eadc, u32Format) ((eadc)->CTL = ((eadc)->CTL & ~EADC_CTL_DMOF_Msk) | (u32Format))
+
+/**
+ * @brief Start the A/D conversion.
+ * @param[in] eadc The pointer of the specified EADC module.
+ * @param[in] u32ModuleMask The combination of sample module. Each bit corresponds to a sample module.
+ * This parameter decides which sample module will be conversion, valid range are between 1~0x7FFFF.
+ * Bit 0 is sample module 0, bit 1 is sample module 1..., bit 18 is sample module 18.
+ * @return None
+ * @details After write EADC_SWTRG register to start ADC conversion, the EADC_PENDSTS register will show which SAMPLE will conversion.
+ */
+#define EADC_START_CONV(eadc, u32ModuleMask) ((eadc)->SWTRG = (u32ModuleMask))
+
+/**
+ * @brief Cancel the conversion for sample module.
+ * @param[in] eadc The pointer of the specified EADC module.
+ * @param[in] u32ModuleMask The combination of sample module. Each bit corresponds to a sample module.
+ * This parameter decides which sample module will stop the conversion, valid range are between 1~0x7FFFF.
+ * Bit 0 is sample module 0, bit 1 is sample module 1..., bit 18 is sample module18.
+ * @return None
+ * @details If user want to disable the conversion of the sample module, user can write EADC_PENDSTS register to clear it.
+ */
+#define EADC_STOP_CONV(eadc, u32ModuleMask) ((eadc)->PENDSTS = (u32ModuleMask))
+
+/**
+ * @brief Get the conversion pending flag.
+ * @param[in] eadc The pointer of the specified EADC module.
+ * @return Return the conversion pending sample module.
+ * @details This STPFn(EADC_PENDSTS[18:0]) bit remains 1 during pending state, when the respective ADC conversion is end,
+ * the STPFn (n=0~18) bit is automatically cleared to 0.
+ */
+#define EADC_GET_PENDING_CONV(eadc) ((eadc)->PENDSTS)
+
+/**
+ * @brief Get the conversion data of the user-specified sample module.
+ * @param[in] eadc The pointer of the specified EADC module.
+ * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 18.
+ * @return Return the conversion data of the user-specified sample module.
+ * @details This macro is used to read RESULT bit (EADC_DATn[15:0], n=0~18) field to get conversion data.
+ */
+#define EADC_GET_CONV_DATA(eadc, u32ModuleNum) ((eadc)->DAT[(u32ModuleNum)] & EADC_DAT_RESULT_Msk)
+
+/**
+ * @brief Get the data overrun flag of the user-specified sample module.
+ * @param[in] eadc The pointer of the specified EADC module.
+ * @param[in] u32ModuleMask The combination of data overrun status bits. Each bit corresponds to a data overrun status, valid range are between 1~0x7FFFF.
+ * @return Return the data overrun flag of the user-specified sample module.
+ * @details This macro is used to read OV bit (EADC_STATUS0[31:16], EADC_STATUS1[18:16]) field to get data overrun status.
+ */
+#define EADC_GET_DATA_OVERRUN_FLAG(eadc, u32ModuleMask) ((((eadc)->STATUS0 >> EADC_STATUS0_OV_Pos) | ((eadc)->STATUS1 & EADC_STATUS1_OV_Msk)) & (u32ModuleMask))
+
+/**
+ * @brief Get the data valid flag of the user-specified sample module.
+ * @param[in] eadc The pointer of the specified EADC module.
+ * @param[in] u32ModuleMask The combination of data valid status bits. Each bit corresponds to a data valid status, valid range are between 1~0x7FFFF.
+ * @return Return the data valid flag of the user-specified sample module.
+ * @details This macro is used to read VALID bit (EADC_STATUS0[15:0], EADC_STATUS1[1:0]) field to get data overrun status.
+ */
+#define EADC_GET_DATA_VALID_FLAG(eadc, u32ModuleMask) ((((eadc)->STATUS0 & EADC_STATUS0_VALID_Msk) | (((eadc)->STATUS1 & EADC_STATUS1_VALID_Msk) << 16)) & (u32ModuleMask))
+
+/**
+ * @brief Get the double data of the user-specified sample module.
+ * @param[in] eadc The pointer of the specified EADC module.
+ * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 18.
+ * @return Return the double data of the user-specified sample module.
+ * @details This macro is used to read RESULT bit (EADC_DDATn[15:0], n=0~3) field to get conversion data.
+ */
+#define EADC_GET_DOUBLE_DATA(eadc, u32ModuleNum) ((eadc)->DDAT[(u32ModuleNum)] & EADC_DDAT_RESULT_Msk)
+
+/**
+ * @brief Get the user-specified interrupt flags.
+ * @param[in] eadc The pointer of the specified EADC module.
+ * @param[in] u32Mask The combination of interrupt status bits. Each bit corresponds to a interrupt status.
+ * Bit 0 is ADIF0, bit 1 is ADIF1..., bit 3 is ADIF3.
+ * Bit 4 is ADCMPF0, bit 5 is ADCMPF1..., bit 7 is ADCMPF3.
+ * @return Return the user-specified interrupt flags.
+ * @details This macro is used to get the user-specified interrupt flags.
+ */
+#define EADC_GET_INT_FLAG(eadc, u32Mask) ((eadc)->STATUS2 & (u32Mask))
+
+/**
+ * @brief Get the user-specified sample module overrun flags.
+ * @param[in] eadc The pointer of the specified EADC module.
+ * @param[in] u32ModuleMask The combination of sample module overrun status bits. Each bit corresponds to a sample module overrun status, valid range are between 1~0x7FFFF.
+ * @return Return the user-specified sample module overrun flags.
+ * @details This macro is used to get the user-specified sample module overrun flags.
+ */
+#define EADC_GET_SAMPLE_MODULE_OV_FLAG(eadc, u32ModuleMask) ((eadc)->OVSTS & (u32ModuleMask))
+
+/**
+ * @brief Clear the selected interrupt status bits.
+ * @param[in] eadc The pointer of the specified EADC module.
+ * @param[in] u32Mask The combination of compare interrupt status bits. Each bit corresponds to a compare interrupt status.
+ * Bit 0 is ADIF0, bit 1 is ADIF1..., bit 3 is ADIF3.
+ * Bit 4 is ADCMPF0, bit 5 is ADCMPF1..., bit 7 is ADCMPF3.
+ * @return None
+ * @details This macro is used to clear clear the selected interrupt status bits.
+ */
+#define EADC_CLR_INT_FLAG(eadc, u32Mask) ((eadc)->STATUS2 = (u32Mask))
+
+/**
+ * @brief Clear the selected sample module overrun status bits.
+ * @param[in] eadc The pointer of the specified EADC module.
+ * @param[in] u32ModuleMask The combination of sample module overrun status bits. Each bit corresponds to a sample module overrun status.
+ * Bit 0 is SPOVF0, bit 1 is SPOVF1..., bit 18 is SPOVF18.
+ * @return None
+ * @details This macro is used to clear the selected sample module overrun status bits.
+ */
+#define EADC_CLR_SAMPLE_MODULE_OV_FLAG(eadc, u32ModuleMask) ((eadc)->OVSTS = (u32ModuleMask))
+
+/**
+ * @brief Check all sample module A/D result data register overrun flags.
+ * @param[in] eadc The pointer of the specified EADC module.
+ * @retval 0 None of sample module data register overrun flag is set to 1.
+ * @retval 1 Any one of sample module data register overrun flag is set to 1.
+ * @details The AOV bit (EADC_STATUS2[27]) will keep 1 when any one of sample module data register overrun flag OVn (EADC_DATn[16]) is set to 1.
+ */
+#define EADC_IS_DATA_OV(eadc) (((eadc)->STATUS2 & EADC_STATUS2_AOV_Msk) >> EADC_STATUS2_AOV_Pos)
+
+/**
+ * @brief Check all sample module A/D result data register valid flags.
+ * @param[in] eadc The pointer of the specified EADC module.
+ * @retval 0 None of sample module data register valid flag is set to 1.
+ * @retval 1 Any one of sample module data register valid flag is set to 1.
+ * @details The AVALID bit (EADC_STATUS2[26]) will keep 1 when any one of sample module data register valid flag VALIDn (EADC_DATn[17]) is set to 1.
+ */
+#define EADC_IS_DATA_VALID(eadc) (((eadc)->STATUS2 & EADC_STATUS2_AVALID_Msk) >> EADC_STATUS2_AVALID_Pos)
+
+/**
+ * @brief Check all A/D sample module start of conversion overrun flags.
+ * @param[in] eadc The pointer of the specified EADC module.
+ * @retval 0 None of sample module event overrun flag is set to 1.
+ * @retval 1 Any one of sample module event overrun flag is set to 1.
+ * @details The STOVF bit (EADC_STATUS2[25]) will keep 1 when any one of sample module event overrun flag SPOVFn (EADC_OVSTS[n]) is set to 1.
+ */
+#define EADC_IS_SAMPLE_MODULE_OV(eadc) (((eadc)->STATUS2 & EADC_STATUS2_STOVF_Msk) >> EADC_STATUS2_STOVF_Pos)
+
+/**
+ * @brief Check all A/D interrupt flag overrun bits.
+ * @param[in] eadc The pointer of the specified EADC module.
+ * @retval 0 None of ADINT interrupt flag is overwritten to 1.
+ * @retval 1 Any one of ADINT interrupt flag is overwritten to 1.
+ * @details The ADOVIF bit (EADC_STATUS2[24]) will keep 1 when any one of ADINT interrupt flag ADOVIFn (EADC_STATUS2[11:8]) is overwritten to 1.
+ */
+#define EADC_IS_INT_FLAG_OV(eadc) (((eadc)->STATUS2 & EADC_STATUS2_ADOVIF_Msk) >> EADC_STATUS2_ADOVIF_Pos)
+
+/**
+ * @brief Get the busy state of EADC.
+ * @param[in] eadc The pointer of the specified EADC module.
+ * @retval 0 Idle state.
+ * @retval 1 Busy state.
+ * @details This macro is used to read BUSY bit (EADC_STATUS2[23]) to get busy state.
+ */
+#define EADC_IS_BUSY(eadc) (((eadc)->STATUS2 & EADC_STATUS2_BUSY_Msk) >> EADC_STATUS2_BUSY_Pos)
+
+/**
+ * @brief Configure the comparator 0 and enable it.
+ * @param[in] eadc The pointer of the specified EADC module.
+ * @param[in] u32ModuleNum specifies the compare sample module, valid value are from 0 to 18.
+ * @param[in] u32Condition specifies the compare condition. Valid values are:
+ * - \ref EADC_CMP_CMPCOND_LESS_THAN :The compare condition is "less than the compare value"
+ * - \ref EADC_CMP_CMPCOND_GREATER_OR_EQUAL :The compare condition is "greater than or equal to the compare value
+ * @param[in] u16CMPData specifies the compare value, valid range are between 0~0xFFF.
+ * @param[in] u32MatchCount specifies the match count setting, valid range are between 0~0xF.
+ * @return None
+ * @details For example, ADC_ENABLE_CMP0(EADC, 5, ADC_ADCMPR_CMPCOND_GREATER_OR_EQUAL, 0x800, 10, EADC_CMP_CMPWEN_DISABLE, EADC_CMP_ADCMPIE_ENABLE);
+ * Means EADC will assert comparator 0 flag if sample module 5 conversion result is greater or
+ * equal to 0x800 for 10 times continuously, and a compare interrupt request is generated.
+ */
+#define EADC_ENABLE_CMP0(eadc,\
+ u32ModuleNum,\
+ u32Condition,\
+ u16CMPData,\
+ u32MatchCount) ((eadc)->CMP[0] |=(((u32ModuleNum) << EADC_CMP_CMPSPL_Pos)|\
+ (u32Condition) |\
+ ((u16CMPData) << EADC_CMP_CMPDAT_Pos)| \
+ (((u32MatchCount) - 1) << EADC_CMP_CMPMCNT_Pos)|\
+ EADC_CMP_ADCMPEN_Msk))
+
+/**
+ * @brief Configure the comparator 1 and enable it.
+ * @param[in] eadc The pointer of the specified EADC module.
+ * @param[in] u32ModuleNum specifies the compare sample module, valid value are from 0 to 18.
+ * @param[in] u32Condition specifies the compare condition. Valid values are:
+ * - \ref EADC_CMP_CMPCOND_LESS_THAN :The compare condition is "less than the compare value"
+ * - \ref EADC_CMP_CMPCOND_GREATER_OR_EQUAL :The compare condition is "greater than or equal to the compare value
+ * @param[in] u16CMPData specifies the compare value, valid range are between 0~0xFFF.
+ * @param[in] u32MatchCount specifies the match count setting, valid range are between 0~0xF.
+ * @return None
+ * @details For example, ADC_ENABLE_CMP1(EADC, 5, ADC_ADCMPR_CMPCOND_GREATER_OR_EQUAL, 0x800, 10, EADC_CMP_ADCMPIE_ENABLE);
+ * Means EADC will assert comparator 1 flag if sample module 5 conversion result is greater or
+ * equal to 0x800 for 10 times continuously, and a compare interrupt request is generated.
+ */
+#define EADC_ENABLE_CMP1(eadc,\
+ u32ModuleNum,\
+ u32Condition,\
+ u16CMPData,\
+ u32MatchCount) ((eadc)->CMP[1] |=(((u32ModuleNum) << EADC_CMP_CMPSPL_Pos)|\
+ (u32Condition) |\
+ ((u16CMPData) << EADC_CMP_CMPDAT_Pos)| \
+ (((u32MatchCount) - 1) << EADC_CMP_CMPMCNT_Pos)|\
+ EADC_CMP_ADCMPEN_Msk))
+
+/**
+ * @brief Configure the comparator 2 and enable it.
+ * @param[in] eadc The pointer of the specified EADC module.
+ * @param[in] u32ModuleNum specifies the compare sample module, valid value are from 0 to 18.
+ * @param[in] u32Condition specifies the compare condition. Valid values are:
+ * - \ref EADC_CMP_CMPCOND_LESS_THAN :The compare condition is "less than the compare value"
+ * - \ref EADC_CMP_CMPCOND_GREATER_OR_EQUAL :The compare condition is "greater than or equal to the compare value
+ * @param[in] u16CMPData specifies the compare value, valid range are between 0~0xFFF.
+ * @param[in] u32MatchCount specifies the match count setting, valid range are between 0~0xF.
+ * @return None
+ * @details For example, ADC_ENABLE_CMP2(EADC, 5, ADC_ADCMPR_CMPCOND_GREATER_OR_EQUAL, 0x800, 10, EADC_CMP_CMPWEN_DISABLE, EADC_CMP_ADCMPIE_ENABLE);
+ * Means EADC will assert comparator 2 flag if sample module 5 conversion result is greater or
+ * equal to 0x800 for 10 times continuously, and a compare interrupt request is generated.
+ */
+#define EADC_ENABLE_CMP2(eadc,\
+ u32ModuleNum,\
+ u32Condition,\
+ u16CMPData,\
+ u32MatchCount) ((eadc)->CMP[2] |=(((u32ModuleNum) << EADC_CMP_CMPSPL_Pos)|\
+ (u32Condition) |\
+ ((u16CMPData) << EADC_CMP_CMPDAT_Pos)| \
+ (((u32MatchCount) - 1) << EADC_CMP_CMPMCNT_Pos)|\
+ EADC_CMP_ADCMPEN_Msk))
+
+/**
+ * @brief Configure the comparator 3 and enable it.
+ * @param[in] eadc The pointer of the specified EADC module.
+ * @param[in] u32ModuleNum specifies the compare sample module, valid value are from 0 to 18.
+ * @param[in] u32Condition specifies the compare condition. Valid values are:
+ * - \ref EADC_CMP_CMPCOND_LESS_THAN :The compare condition is "less than the compare value"
+ * - \ref EADC_CMP_CMPCOND_GREATER_OR_EQUAL :The compare condition is "greater than or equal to the compare value
+ * @param[in] u16CMPData specifies the compare value, valid range are between 0~0xFFF.
+ * @param[in] u32MatchCount specifies the match count setting, valid range are between 1~0xF.
+ * @return None
+ * @details For example, ADC_ENABLE_CMP3(EADC, 5, ADC_ADCMPR_CMPCOND_GREATER_OR_EQUAL, 0x800, 10, EADC_CMP_ADCMPIE_ENABLE);
+ * Means EADC will assert comparator 3 flag if sample module 5 conversion result is greater or
+ * equal to 0x800 for 10 times continuously, and a compare interrupt request is generated.
+ */
+#define EADC_ENABLE_CMP3(eadc,\
+ u32ModuleNum,\
+ u32Condition,\
+ u16CMPData,\
+ u32MatchCount) ((eadc)->CMP[3] |=(((u32ModuleNum) << EADC_CMP_CMPSPL_Pos)|\
+ (u32Condition) |\
+ ((u16CMPData) << EADC_CMP_CMPDAT_Pos)| \
+ (((u32MatchCount) - 1) << EADC_CMP_CMPMCNT_Pos)|\
+ EADC_CMP_ADCMPEN_Msk))
+
+/**
+ * @brief Enable the compare window mode.
+ * @param[in] eadc The pointer of the specified EADC module.
+ * @param[in] u32CMP Specifies the compare register, valid value are 0 and 2.
+ * @return None
+ * @details ADCMPF0 (EADC_STATUS2[4]) will be set when both EADC_CMP0 and EADC_CMP1 compared condition matched.
+ */
+#define EADC_ENABLE_CMP_WINDOW_MODE(eadc, u32CMP) ((eadc)->CMP[(u32CMP)] |= EADC_CMP_CMPWEN_Msk)
+
+/**
+ * @brief Disable the compare window mode.
+ * @param[in] eadc The pointer of the specified EADC module.
+ * @param[in] u32CMP Specifies the compare register, valid value are 0 and 2.
+ * @return None
+ * @details ADCMPF2 (EADC_STATUS2[6]) will be set when both EADC_CMP2 and EADC_CMP3 compared condition matched.
+ */
+#define EADC_DISABLE_CMP_WINDOW_MODE(eadc, u32CMP) ((eadc)->CMP[(u32CMP)] &= ~EADC_CMP_CMPWEN_Msk)
+
+/**
+ * @brief Enable the compare interrupt.
+ * @param[in] eadc The pointer of the specified EADC module.
+ * @param[in] u32CMP Specifies the compare register, valid value are from 0 to 3.
+ * @return None
+ * @details If the compare function is enabled and the compare condition matches the setting of CMPCOND (EADC_CMPn[2], n=0~3)
+ * and CMPMCNT (EADC_CMPn[11:8], n=0~3), ADCMPFn (EADC_STATUS2[7:4], n=0~3) will be asserted, in the meanwhile,
+ * if ADCMPIE is set to 1, a compare interrupt request is generated.
+ */
+#define EADC_ENABLE_CMP_INT(eadc, u32CMP) ((eadc)->CMP[(u32CMP)] |= EADC_CMP_ADCMPIE_Msk)
+
+/**
+ * @brief Disable the compare interrupt.
+ * @param[in] eadc The pointer of the specified EADC module.
+ * @param[in] u32CMP Specifies the compare register, valid value are from 0 to 3.
+ * @return None
+ * @details This macro is used to disable the compare interrupt.
+ */
+#define EADC_DISABLE_CMP_INT(eadc, u32CMP) ((eadc)->CMP[(u32CMP)] &= ~EADC_CMP_ADCMPIE_Msk)
+
+/**
+ * @brief Disable comparator 0.
+ * @param[in] eadc The pointer of the specified EADC module.
+ * @return None
+ * @details This macro is used to disable comparator 0.
+ */
+#define EADC_DISABLE_CMP0(eadc) ((eadc)->CMP[0] = 0)
+
+/**
+ * @brief Disable comparator 1.
+ * @param[in] eadc The pointer of the specified EADC module.
+ * @return None
+ * @details This macro is used to disable comparator 1.
+ */
+#define EADC_DISABLE_CMP1(eadc) ((eadc)->CMP[1] = 0)
+
+/**
+ * @brief Disable comparator 2.
+ * @param[in] eadc The pointer of the specified EADC module.
+ * @return None
+ * @details This macro is used to disable comparator 2.
+ */
+#define EADC_DISABLE_CMP2(eadc) ((eadc)->CMP[2] = 0)
+
+/**
+ * @brief Disable comparator 3.
+ * @param[in] eadc The pointer of the specified EADC module.
+ * @return None
+ * @details This macro is used to disable comparator 3.
+ */
+#define EADC_DISABLE_CMP3(eadc) ((eadc)->CMP[3] = 0)
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Define EADC functions prototype */
+/*---------------------------------------------------------------------------------------------------------*/
+void EADC_Open(EADC_T *eadc, uint32_t u32InputMode);
+void EADC_Close(EADC_T *eadc);
+void EADC_ConfigSampleModule(EADC_T *eadc, uint32_t u32ModuleNum, uint32_t u32TriggerSource, uint32_t u32Channel);
+void EADC_SetTriggerDelayTime(EADC_T *eadc, uint32_t u32ModuleNum, uint32_t u32TriggerDelayTime, uint32_t u32DelayClockDivider);
+void EADC_SetInternalSampleTime(EADC_T *eadc, uint32_t u32SampleTime);
+void EADC_SetExtendSampleTime(EADC_T *eadc, uint32_t u32ModuleNum, uint32_t u32ExtendSampleTime);
+
+/*@}*/ /* end of group EADC_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group EADC_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif //__EADC_H__
+
+/*** (C) COPYRIGHT 2013~2015 Nuvoton Technology Corp. ***/
diff --git a/bsp/nuvoton_m451/Libraries/StdDriver/inc/ebi.h b/bsp/nuvoton_m451/Libraries/StdDriver/inc/ebi.h
new file mode 100644
index 0000000000000000000000000000000000000000..36af7ff5169435d6c5775bd9e6ce9d986544d690
--- /dev/null
+++ b/bsp/nuvoton_m451/Libraries/StdDriver/inc/ebi.h
@@ -0,0 +1,235 @@
+/**************************************************************************//**
+ * @file ebi.h
+ * @version V3.00
+ * $Revision: 8 $
+ * $Date: 15/08/11 10:26a $
+ * @brief M451 series EBI driver header file
+ *
+ * @note
+ * Copyright (C) 2013~2015 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __EBI_H__
+#define __EBI_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup Standard_Driver Standard Driver
+ @{
+*/
+
+/** @addtogroup EBI_Driver EBI Driver
+ @{
+*/
+
+/** @addtogroup EBI_EXPORTED_CONSTANTS EBI Exported Constants
+ @{
+*/
+/*---------------------------------------------------------------------------------------------------------*/
+/* Miscellaneous Constant Definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define EBI_BANK0_BASE_ADDR 0x60000000UL /*!< EBI bank0 base address */
+#define EBI_BANK1_BASE_ADDR 0x60100000UL /*!< EBI bank1 base address */
+#define EBI_MAX_SIZE 0x00100000UL /*!< Maximum EBI size for each bank is 1 MB */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Constants for EBI bank number */
+/*---------------------------------------------------------------------------------------------------------*/
+#define EBI_BANK0 0 /*!< EBI bank 0 */
+#define EBI_BANK1 1 /*!< EBI bank 1 */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Constants for EBI data bus width */
+/*---------------------------------------------------------------------------------------------------------*/
+#define EBI_BUSWIDTH_8BIT 8 /*!< EBI bus width is 8-bit */
+#define EBI_BUSWIDTH_16BIT 16 /*!< EBI bus width is 16-bit */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Constants for EBI CS Active Level */
+/*---------------------------------------------------------------------------------------------------------*/
+#define EBI_CS_ACTIVE_LOW 0 /*!< EBI CS active level is low */
+#define EBI_CS_ACTIVE_HIGH 1 /*!< EBI CS active level is high */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Constants for EBI MCLK divider and Timing */
+/*---------------------------------------------------------------------------------------------------------*/
+#define EBI_MCLKDIV_1 0x0UL /*!< EBI output clock(MCLK) is HCLK/1 */
+#define EBI_MCLKDIV_2 0x1UL /*!< EBI output clock(MCLK) is HCLK/2 */
+#define EBI_MCLKDIV_4 0x2UL /*!< EBI output clock(MCLK) is HCLK/4 */
+#define EBI_MCLKDIV_8 0x3UL /*!< EBI output clock(MCLK) is HCLK/8 */
+#define EBI_MCLKDIV_16 0x4UL /*!< EBI output clock(MCLK) is HCLK/16 */
+#define EBI_MCLKDIV_32 0x5UL /*!< EBI output clock(MCLK) is HCLK/32 */
+
+#define EBI_TIMING_FASTEST 0x0UL /*!< EBI timing is the fastest */
+#define EBI_TIMING_VERYFAST 0x1UL /*!< EBI timing is very fast */
+#define EBI_TIMING_FAST 0x2UL /*!< EBI timing is fast */
+#define EBI_TIMING_NORMAL 0x3UL /*!< EBI timing is normal */
+#define EBI_TIMING_SLOW 0x4UL /*!< EBI timing is slow */
+#define EBI_TIMING_VERYSLOW 0x5UL /*!< EBI timing is very slow */
+#define EBI_TIMING_SLOWEST 0x6UL /*!< EBI timing is the slowest */
+
+/*@}*/ /* end of group EBI_EXPORTED_CONSTANTS */
+
+
+/** @addtogroup EBI_EXPORTED_FUNCTIONS EBI Exported Functions
+ @{
+*/
+
+/**
+ * @brief Read 8-bit data on EBI bank0
+ *
+ * @param[in] u32Addr The data address on EBI bank0.
+ *
+ * @return 8-bit Data
+ *
+ * @details This macro is used to read 8-bit data from specify address on EBI bank0.
+ */
+#define EBI0_READ_DATA8(u32Addr) (*((volatile unsigned char *)(EBI_BANK0_BASE_ADDR+(u32Addr))))
+
+/**
+ * @brief Write 8-bit data to EBI bank0
+ *
+ * @param[in] u32Addr The data address on EBI bank0.
+ * @param[in] u32Data Specify data to be written.
+ *
+ * @return None
+ *
+ * @details This macro is used to write 8-bit data to specify address on EBI bank0.
+ */
+#define EBI0_WRITE_DATA8(u32Addr, u32Data) (*((volatile unsigned char *)(EBI_BANK0_BASE_ADDR+(u32Addr))) = (u32Data))
+
+/**
+ * @brief Read 16-bit data on EBI bank0
+ *
+ * @param[in] u32Addr The data address on EBI bank0.
+ *
+ * @return 16-bit Data
+ *
+ * @details This macro is used to read 16-bit data from specify address on EBI bank0.
+ */
+#define EBI0_READ_DATA16(u32Addr) (*((volatile unsigned short *)(EBI_BANK0_BASE_ADDR+(u32Addr))))
+
+/**
+ * @brief Write 16-bit data to EBI bank0
+ *
+ * @param[in] u32Addr The data address on EBI bank0.
+ * @param[in] u32Data Specify data to be written.
+ *
+ * @return None
+ *
+ * @details This macro is used to write 16-bit data to specify address on EBI bank0.
+ */
+#define EBI0_WRITE_DATA16(u32Addr, u32Data) (*((volatile unsigned short *)(EBI_BANK0_BASE_ADDR+(u32Addr))) = (u32Data))
+
+/**
+ * @brief Read 32-bit data on EBI bank0
+ *
+ * @param[in] u32Addr The data address on EBI bank0.
+ *
+ * @return 32-bit Data
+ *
+ * @details This macro is used to read 32-bit data from specify address on EBI bank0.
+ */
+#define EBI0_READ_DATA32(u32Addr) (*((volatile unsigned int *)(EBI_BANK0_BASE_ADDR+(u32Addr))))
+
+/**
+ * @brief Write 32-bit data to EBI bank0
+ *
+ * @param[in] u32Addr The data address on EBI bank0.
+ * @param[in] u32Data Specify data to be written.
+ *
+ * @return None
+ *
+ * @details This macro is used to write 32-bit data to specify address on EBI bank0.
+ */
+#define EBI0_WRITE_DATA32(u32Addr, u32Data) (*((volatile unsigned int *)(EBI_BANK0_BASE_ADDR+(u32Addr))) = (u32Data))
+
+/**
+ * @brief Read 8-bit data on EBI bank1
+ *
+ * @param[in] u32Addr The data address on EBI bank1.
+ *
+ * @return 8-bit Data
+ *
+ * @details This macro is used to read 8-bit data from specify address on EBI bank1.
+ */
+#define EBI1_READ_DATA8(u32Addr) (*((volatile unsigned char *)(EBI_BANK1_BASE_ADDR+(u32Addr))))
+
+/**
+ * @brief Write 8-bit data to EBI bank1
+ *
+ * @param[in] u32Addr The data address on EBI bank1.
+ * @param[in] u32Data Specify data to be written.
+ *
+ * @return None
+ *
+ * @details This macro is used to write 8-bit data to specify address on EBI bank1.
+ */
+#define EBI1_WRITE_DATA8(u32Addr, u32Data) (*((volatile unsigned char *)(EBI_BANK1_BASE_ADDR+(u32Addr))) = (u32Data))
+
+/**
+ * @brief Read 16-bit data on EBI bank1
+ *
+ * @param[in] u32Addr The data address on EBI bank1.
+ *
+ * @return 16-bit Data
+ *
+ * @details This macro is used to read 16-bit data from specify address on EBI bank1.
+ */
+#define EBI1_READ_DATA16(u32Addr) (*((volatile unsigned short *)(EBI_BANK1_BASE_ADDR+(u32Addr))))
+
+/**
+ * @brief Write 16-bit data to EBI bank1
+ *
+ * @param[in] u32Addr The data address on EBI bank1.
+ * @param[in] u32Data Specify data to be written.
+ *
+ * @return None
+ *
+ * @details This macro is used to write 16-bit data to specify address on EBI bank1.
+ */
+#define EBI1_WRITE_DATA16(u32Addr, u32Data) (*((volatile unsigned short *)(EBI_BANK1_BASE_ADDR+(u32Addr))) = (u32Data))
+
+/**
+ * @brief Read 32-bit data on EBI bank1
+ *
+ * @param[in] u32Addr The data address on EBI bank1.
+ *
+ * @return 32-bit Data
+ *
+ * @details This macro is used to read 32-bit data from specify address on EBI bank1.
+ */
+#define EBI1_READ_DATA32(u32Addr) (*((volatile unsigned int *)(EBI_BANK1_BASE_ADDR+(u32Addr))))
+
+/**
+ * @brief Write 32-bit data to EBI bank1
+ *
+ * @param[in] u32Addr The data address on EBI bank1.
+ * @param[in] u32Data Specify data to be written.
+ *
+ * @return None
+ *
+ * @details This macro is used to write 32-bit data to specify address on EBI bank1.
+ */
+#define EBI1_WRITE_DATA32(u32Addr, u32Data) (*((volatile unsigned int *)(EBI_BANK1_BASE_ADDR+(u32Addr))) = (u32Data))
+
+void EBI_Open(uint32_t u32Bank, uint32_t u32DataWidth, uint32_t u32TimingClass, uint32_t u32BusMode, uint32_t u32CSActiveLevel);
+void EBI_Close(uint32_t u32Bank);
+void EBI_SetBusTiming(uint32_t u32Bank, uint32_t u32TimingConfig, uint32_t u32MclkDiv);
+
+/*@}*/ /* end of group EBI_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group EBI_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif //__EBI_H__
+
+/*** (C) COPYRIGHT 2013~2015 Nuvoton Technology Corp. ***/
diff --git a/bsp/nuvoton_m451/Libraries/StdDriver/inc/fmc.h b/bsp/nuvoton_m451/Libraries/StdDriver/inc/fmc.h
new file mode 100644
index 0000000000000000000000000000000000000000..994c0b311ed899ff5c603e3fc14534f19d41fb3b
--- /dev/null
+++ b/bsp/nuvoton_m451/Libraries/StdDriver/inc/fmc.h
@@ -0,0 +1,605 @@
+/**************************************************************************//**
+ * @file FMC.h
+ * @version V2.1
+ * $Revision: 19 $
+ * $Date: 15/08/11 10:26a $
+ * @brief M451 Series Flash Memory Controller Driver Header File
+ *
+ * @note
+ * Copyright (C) 2011~2015 Nuvoton Technology Corp. All rights reserved.
+ *
+ ******************************************************************************/
+#ifndef __FMC_H__
+#define __FMC_H__
+
+#include "M451Series.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup Standard_Driver Standard Driver
+ @{
+*/
+
+/** @addtogroup FMC_Driver FMC Driver
+ @{
+*/
+
+/** @addtogroup FMC_EXPORTED_CONSTANTS FMC Exported Constants
+ @{
+*/
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Global constant definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define ISBEN 0
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Define Base Address */
+/*---------------------------------------------------------------------------------------------------------*/
+#define FMC_APROM_BASE 0x00000000UL /*!< APROM Base Address */
+#define FMC_LDROM_BASE 0x00100000UL /*!< LDROM Base Address */
+#define FMC_SPROM_BASE 0x00200000UL /*!< SPROM Base Address */
+#define FMC_CONFIG_BASE 0x00300000UL /*!< CONFIG Base Address */
+
+#define FMC_CONFIG0_ADDR (FMC_CONFIG_BASE) /*!< CONFIG 0 Address */
+#define FMC_CONFIG1_ADDR (FMC_CONFIG_BASE + 4) /*!< CONFIG 1 Address */
+
+
+#define FMC_FLASH_PAGE_SIZE 0x800 /*!< Flash Page Size (2048 Bytes) */
+#define FMC_LDROM_SIZE 0x1000 /*!< LDROM Size (4 kBytes) */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* ISPCTL constant definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define FMC_ISPCTL_BS_LDROM 0x2 /*!< ISPCTL setting to select to boot from LDROM */
+#define FMC_ISPCTL_BS_APROM 0x0 /*!< ISPCTL setting to select to boot from APROM */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* ISPCMD constant definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define FMC_ISPCMD_READ 0x00 /*!< ISP Command: Read Flash */
+#define FMC_ISPCMD_PROGRAM 0x21 /*!< ISP Command: 32-bit Program Flash */
+#define FMC_ISPCMD_WRITE_8 0x61 /*!< ISP Command: 64-bit program Flash */
+#define FMC_ISPCMD_PAGE_ERASE 0x22 /*!< ISP Command: Page Erase Flash */
+#define FMC_ISPCMD_READ_CID 0x0B /*!< ISP Command: Read Company ID */
+#define FMC_ISPCMD_READ_UID 0x04 /*!< ISP Command: Read Unique ID */
+#define FMC_ISPCMD_READ_DID 0x0C /*!< ISP Command: Read Device ID */
+#define FMC_ISPCMD_VECMAP 0x2E /*!< ISP Command: Set vector mapping */
+#define FMC_ISPCMD_CHECKSUM 0x0D /*!< ISP Command: Read Checksum */
+#define FMC_ISPCMD_CAL_CHECKSUM 0x2D /*!< ISP Command: Run Check Calculation */
+#define FMC_ISPCMD_MULTI_PROG 0x27 /*!< ISP Command: Flash Multi-Word Program */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* FTCTL constant definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define FMC_FTCTL_OPTIMIZE_DISABLE 0x00 /*!< Frequency Optimize Mode disable */
+#define FMC_FTCTL_OPTIMIZE_12MHZ 0x01 /*!< Frequency Optimize Mode <= 12Mhz */
+#define FMC_FTCTL_OPTIMIZE_36MHZ 0x02 /*!< Frequency Optimize Mode <= 36Mhz */
+#define FMC_FTCTL_OPTIMIZE_60MHZ 0x04 /*!< Frequency Optimize Mode <= 60Mhz */
+#define FMC_FTCTL_OPTIMIZE_72MHZ 0x05 /*!< Frequency Optimize Mode <= 72Mhz */
+
+/*@}*/ /* end of group FMC_EXPORTED_CONSTANTS */
+
+/** @addtogroup FMC_EXPORTED_FUNCTIONS FMC Exported Functions
+ @{
+*/
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* FMC Macro Definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+/**
+ * @brief Enable ISP Function
+ *
+ * @param None
+ *
+ * @return None
+ *
+ * @details This function will set ISPEN bit of ISPCTL control register to enable ISP function.
+ *
+ */
+#define FMC_ENABLE_ISP() (FMC->ISPCTL |= FMC_ISPCTL_ISPEN_Msk) /*!< Enable ISP Function */
+
+/**
+ * @brief Disable ISP Function
+ *
+ * @param None
+ *
+ * @return None
+ *
+ * @details This function will clear ISPEN bit of ISPCTL control register to disable ISP function.
+ *
+ */
+#define FMC_DISABLE_ISP() (FMC->ISPCTL &= ~FMC_ISPCTL_ISPEN_Msk) /*!< Disable ISP Function */
+
+/**
+ * @brief Enable LDROM Update Function
+ *
+ * @param None
+ *
+ * @return None
+ *
+ * @details This function will set LDUEN bit of ISPCTL control register to enable LDROM update function.
+ * User needs to set LDUEN bit before they can update LDROM.
+ *
+ */
+#define FMC_ENABLE_LD_UPDATE() (FMC->ISPCTL |= FMC_ISPCTL_LDUEN_Msk) /*!< Enable LDROM Update Function */
+
+/**
+ * @brief Disable LDROM Update Function
+ *
+ * @param None
+ *
+ * @return None
+ *
+ * @details This function will set ISPEN bit of ISPCTL control register to disable LDROM update function.
+ *
+ */
+#define FMC_DISABLE_LD_UPDATE() (FMC->ISPCTL &= ~FMC_ISPCTL_LDUEN_Msk) /*!< Disable LDROM Update Function */
+
+/**
+ * @brief Enable User Configuration Update Function
+ *
+ * @param None
+ *
+ * @return None
+ *
+ * @details This function will set CFGUEN bit of ISPCTL control register to enable User Configuration update function.
+ * User needs to set CFGUEN bit before they can update User Configuration area.
+ *
+ */
+#define FMC_ENABLE_CFG_UPDATE() (FMC->ISPCTL |= FMC_ISPCTL_CFGUEN_Msk) /*!< Enable CONFIG Update Function */
+
+/**
+ * @brief Disable User Configuration Update Function
+ *
+ * @param None
+ *
+ * @return None
+ *
+ * @details This function will clear CFGUEN bit of ISPCTL control register to disable User Configuration update function.
+ *
+ */
+#define FMC_DISABLE_CFG_UPDATE() (FMC->ISPCTL &= ~FMC_ISPCTL_CFGUEN_Msk) /*!< Disable CONFIG Update Function */
+
+
+/**
+ * @brief Enable APROM Update Function
+ *
+ * @param None
+ *
+ * @return None
+ *
+ * @details This function will set APUEN bit of ISPCTL control register to enable APROM update function.
+ * User needs to set APUEN bit before they can update APROM in APROM boot mode.
+ *
+ */
+#define FMC_ENABLE_AP_UPDATE() (FMC->ISPCTL |= FMC_ISPCTL_APUEN_Msk) /*!< Enable APROM Update Function */
+
+/**
+ * @brief Disable APROM Update Function
+ *
+ * @param None
+ *
+ * @return None
+ *
+ * @details This function will clear APUEN bit of ISPCTL control register to disable APROM update function.
+ *
+ */
+#define FMC_DISABLE_AP_UPDATE() (FMC->ISPCTL &= ~FMC_ISPCTL_APUEN_Msk) /*!< Disable APROM Update Function */
+
+/**
+ * @brief Next Booting Selection function
+ *
+ * @param[in] x Booting from APROM(0)/LDROM(1)
+ *
+ * @return None
+ *
+ * @details This function will set MCU next booting from LDROM/APROM.
+ *
+ * @note When use this macro, the Boot Loader booting selection MBS(CONFIG0[5]) must be set.
+ *
+ */
+#define FMC_SELECT_NEXT_BOOT(x) (FMC->ISPCTL = (FMC->ISPCTL & ~FMC_ISPCTL_BS_Msk) | ((x) << FMC_ISPCTL_BS_Pos)) /*!< Select Next Booting, x = 0 or 1 */
+
+/**
+ * @brief Get MCU Booting Status
+ *
+ * @param None
+ *
+ * @return None
+ *
+ * @details This function will get status of chip next booting from LDROM/APROM.
+ *
+ */
+#define FMC_GET_BOOT_STATUS() ((FMC->ISPCTL & FMC_ISPCTL_BS_Msk)?1:0) /*!< Get MCU Booting Status */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* inline functions */
+/*---------------------------------------------------------------------------------------------------------*/
+/**
+ * @brief Program 32-bit data into specified address of flash
+ *
+ * @param[in] u32Addr Flash address include APROM, LDROM, Data Flash, and CONFIG
+ * @param[in] u32Data 32-bit Data to program
+ *
+ * @return None
+ *
+ * @details To program word data into Flash include APROM, LDROM, Data Flash, and CONFIG.
+ * The corresponding functions in CONFIG are listed in FMC section of Technical Reference Manual.
+ *
+ */
+static __INLINE void FMC_Write(uint32_t u32Addr, uint32_t u32Data)
+{
+ FMC->ISPCMD = FMC_ISPCMD_PROGRAM;
+ FMC->ISPADDR = u32Addr;
+ FMC->ISPDAT = u32Data;
+ FMC->ISPTRG = 0x1;
+#if ISBEN
+ __ISB();
+#endif
+ while(FMC->ISPTRG);
+}
+
+/**
+ * @brief Program 64-bit data into specified address of flash
+ *
+ * @param[in] u32Addr Flash address include APROM, LDROM, Data Flash, and CONFIG
+ * @param[in] u32Data0 32-bit Data to program
+ * @param[in] u32Data1 32-bit Data to program
+ *
+ * @return None
+ *
+ * @details To program two words data into Flash include APROM, LDROM, Data Flash, and CONFIG.
+ * The corresponding functions in CONFIG are listed in FMC section of Technical Reference Manual.
+ *
+ */
+static __INLINE void FMC_Write8(uint32_t u32Addr, uint32_t u32Data0, uint32_t u32Data1)
+{
+ FMC->ISPCMD = FMC_ISPCMD_WRITE_8;
+ FMC->ISPADDR = u32Addr;
+ FMC->MPDAT0 = u32Data0;
+ FMC->MPDAT1 = u32Data1;
+ FMC->ISPTRG = 0x1;
+#if ISBEN
+ __ISB();
+#endif
+ while(FMC->ISPTRG);
+}
+
+
+/**
+ * @brief Read 32-bit Data from specified address of flash
+ *
+ * @param[in] u32Addr Flash address include APROM, LDROM, Data Flash, and CONFIG
+ *
+ * @return The data of specified address
+ *
+ * @details To read word data from Flash include APROM, LDROM, Data Flash, and CONFIG.
+ *
+ */
+static __INLINE uint32_t FMC_Read(uint32_t u32Addr)
+{
+ FMC->ISPCMD = FMC_ISPCMD_READ;
+ FMC->ISPADDR = u32Addr;
+ FMC->ISPDAT = 0;
+ FMC->ISPTRG = 0x1;
+#if ISBEN
+ __ISB();
+#endif
+ while(FMC->ISPTRG);
+
+ return FMC->ISPDAT;
+}
+
+/**
+ * @brief Flash page erase
+ *
+ * @param[in] u32Addr Flash address including APROM, LDROM, Data Flash, and CONFIG
+ *
+ * @details To do flash page erase. The target address could be APROM, LDROM, Data Flash, or CONFIG.
+ * The page size is 2048 bytes.
+ *
+ * @retval 0 Success
+ * @retval -1 Erase failed
+ *
+ */
+static __INLINE int32_t FMC_Erase(uint32_t u32Addr)
+{
+ FMC->ISPCMD = FMC_ISPCMD_PAGE_ERASE;
+ FMC->ISPADDR = u32Addr;
+ FMC->ISPTRG = 0x1;
+#if ISBEN
+ __ISB();
+#endif
+ while(FMC->ISPTRG);
+
+ /* Check ISPFF flag to know whether erase OK or fail. */
+ if(FMC->ISPCTL & FMC_ISPCTL_ISPFF_Msk)
+ {
+ FMC->ISPCTL |= FMC_ISPCTL_ISPFF_Msk;
+ return -1;
+ }
+ return 0;
+}
+
+/**
+ * @brief Read Unique ID
+ *
+ * @param[in] u8Index UID index. 0 = UID[31:0], 1 = UID[63:32], 2 = UID[95:64]
+ *
+ * @return The 32-bit unique ID data of specified UID index.
+ *
+ * @details To read out 96-bit Unique ID.
+ *
+ */
+static __INLINE uint32_t FMC_ReadUID(uint8_t u8Index)
+{
+ FMC->ISPCMD = FMC_ISPCMD_READ_UID;
+ FMC->ISPADDR = (u8Index << 2);
+ FMC->ISPDAT = 0;
+ FMC->ISPTRG = 0x1;
+#if ISBEN
+ __ISB();
+#endif
+ while(FMC->ISPTRG);
+
+ return FMC->ISPDAT;
+}
+
+/**
+ * @brief Read company ID
+ *
+ * @param None
+ *
+ * @return The company ID (32-bit)
+ *
+ * @details The company ID of Nuvoton is fixed to be 0xDA
+ *
+ */
+static __INLINE uint32_t FMC_ReadCID(void)
+{
+ FMC->ISPCMD = FMC_ISPCMD_READ_CID; /* Set ISP Command Code */
+ FMC->ISPADDR = 0x0; /* Must keep 0x0 when read CID */
+ FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; /* Trigger to start ISP procedure */
+#if ISBEN
+ __ISB();
+#endif /* To make sure ISP/CPU be Synchronized */
+ while(FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) ; /* Waiting for ISP Done */
+
+ return FMC->ISPDAT;
+}
+
+/**
+ * @brief Read product ID
+ *
+ * @param None
+ *
+ * @return The product ID (32-bit)
+ *
+ * @details This function is used to read product ID.
+ *
+ */
+static __INLINE uint32_t FMC_ReadPID(void)
+{
+ FMC->ISPCMD = FMC_ISPCMD_READ_DID; /* Set ISP Command Code */
+ FMC->ISPADDR = 0x04; /* Must keep 0x4 when read PID */
+ FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; /* Trigger to start ISP procedure */
+#if ISBEN
+ __ISB();
+#endif /* To make sure ISP/CPU be Synchronized */
+ while(FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk); /* Waiting for ISP Done */
+
+ return FMC->ISPDAT;
+}
+
+/**
+ * @brief To read UCID
+ *
+ * @param[in] u32Index Index of the UCID to read. u32Index must be 0, 1, 2, or 3.
+ *
+ * @return The UCID of specified index
+ *
+ * @details This function is used to read unique chip ID (UCID).
+ *
+ */
+static __INLINE uint32_t FMC_ReadUCID(uint32_t u32Index)
+{
+ FMC->ISPCMD = FMC_ISPCMD_READ_UID; /* Set ISP Command Code */
+ FMC->ISPADDR = (0x04 * u32Index) + 0x10; /* The UCID is at offset 0x10 with word alignment. */
+ FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; /* Trigger to start ISP procedure */
+#if ISBEN
+ __ISB();
+#endif /* To make sure ISP/CPU be Synchronized */
+ while(FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk); /* Waiting for ISP Done */
+
+ return FMC->ISPDAT;
+}
+
+/**
+ * @brief Set vector mapping address
+ *
+ * @param[in] u32PageAddr The page address to remap to address 0x0. The address must be page alignment.
+ *
+ * @return To set VECMAP to remap specified page address to 0x0.
+ *
+ * @details This function is used to set VECMAP to map specified page to vector page (0x0).
+ *
+ * @note
+ * VECMAP only valid when new IAP function is enabled. (CBS = 10'b or 00'b)
+ *
+ */
+static __INLINE void FMC_SetVectorPageAddr(uint32_t u32PageAddr)
+{
+ FMC->ISPCMD = FMC_ISPCMD_VECMAP; /* Set ISP Command Code */
+ FMC->ISPADDR = u32PageAddr; /* The address of specified page which will be map to address 0x0. It must be page alignment. */
+ FMC->ISPTRG = 0x1; /* Trigger to start ISP procedure */
+#if ISBEN
+ __ISB();
+#endif /* To make sure ISP/CPU be Synchronized */
+ while(FMC->ISPTRG); /* Waiting for ISP Done */
+}
+
+/**
+ * @brief Get current vector mapping address.
+ *
+ * @param None
+ *
+ * @return The current vector mapping address.
+ *
+ * @details To get VECMAP value which is the page address for remapping to vector page (0x0).
+ *
+ * @note
+ * VECMAP only valid when new IAP function is enabled. (CBS = 10'b or 00'b)
+ *
+ */
+static __INLINE uint32_t FMC_GetVECMAP(void)
+{
+ return (FMC->ISPSTS & FMC_ISPSTS_VECMAP_Msk);
+}
+
+/**
+ * @brief Get Flash Checksum
+ *
+ * @param[in] u32Addr Specific flash start address
+ * @param[in] i32Size Specific a size of Flash area
+ *
+ * @return A checksum value of a flash block.
+ *
+ * @details To get VECMAP value which is the page address for remapping to vector page (0x0).
+ *
+ */
+static __INLINE uint32_t FMC_GetCheckSum(uint32_t u32Addr, int32_t i32Size)
+{
+ FMC->ISPCMD = FMC_ISPCMD_CAL_CHECKSUM;
+ FMC->ISPADDR = u32Addr;
+ FMC->ISPDAT = i32Size;
+ FMC->ISPTRG = 0x1;
+#if ISBEN
+ __ISB();
+#endif
+ while(FMC->ISPTRG);
+
+ FMC->ISPCMD = FMC_ISPCMD_CHECKSUM;
+ FMC->ISPTRG = 0x1;
+ while(FMC->ISPTRG);
+
+ return FMC->ISPDAT;
+}
+
+/**
+ * @brief Program Multi-Word data into specified address of flash
+ *
+ * @param[in] u32Addr Flash address include APROM, LDROM, Data Flash, and CONFIG
+ * @param[in] pu32Buf A data pointer is point to a data buffer start address;
+ *
+ * @return None
+ *
+ * @details To program multi-words data into Flash include APROM, LDROM, Data Flash, and CONFIG.
+ * The corresponding functions in CONFIG are listed in FMC section of Technical Reference Manual.
+ *
+ */
+static __INLINE void FMC_Write256(uint32_t u32Addr, uint32_t *pu32Buf)
+{
+ int32_t i, idx;
+ volatile uint32_t *pu32IspData;
+ //int32_t i32Err;
+
+ //i32Err = 0;
+ idx = 0;
+ FMC->ISPCMD = FMC_ISPCMD_MULTI_PROG;
+ FMC->ISPADDR = u32Addr;
+
+retrigger:
+
+ //if(i32Err)
+ // printf("idx=%d ISPADDR = 0x%08x\n",idx, FMC->ISPADDR);
+
+ FMC->MPDAT0 = pu32Buf[idx + 0];
+ FMC->MPDAT1 = pu32Buf[idx + 1];
+ FMC->MPDAT2 = pu32Buf[idx + 2];
+ FMC->MPDAT3 = pu32Buf[idx + 3];
+
+
+
+ FMC->ISPTRG = 0x1;
+
+ pu32IspData = &FMC->MPDAT0;
+ idx += 4;
+
+ for(i = idx; i < 256 / 4; i += 4) // Max data length is 256 bytes (256/4 words)
+ {
+
+ __set_PRIMASK(1); // Mask interrupt to avoid status check coherence error
+ do
+ {
+ if((FMC->MPSTS & FMC_MPSTS_MPBUSY_Msk) == 0)
+ {
+ __set_PRIMASK(0);
+ //printf("%d %x\n", i, FMC->MPADDR);
+ FMC->ISPADDR = FMC->MPADDR & (~0xful);
+ idx = (FMC->ISPADDR - u32Addr) / 4;
+ //i32Err = -1;
+ goto retrigger;
+ }
+ }
+ while(FMC->MPSTS & (3 << FMC_MPSTS_D0_Pos));
+
+ // Update new data for D0
+ pu32IspData[0] = pu32Buf[i ];
+ pu32IspData[1] = pu32Buf[i + 1];
+
+ do
+ {
+ if((FMC->MPSTS & FMC_MPSTS_MPBUSY_Msk) == 0)
+ {
+ __set_PRIMASK(0);
+ //printf("%d %x\n", i, FMC->MPADDR);
+ FMC->ISPADDR = FMC->MPADDR & (~0xful);
+ idx = (FMC->ISPADDR - u32Addr) / 4;
+ //i32Err = -1;
+ goto retrigger;
+ }
+ }
+ while(FMC->MPSTS & (3 << FMC_MPSTS_D2_Pos));
+
+ // Update new data for D2
+ pu32IspData[2] = pu32Buf[i + 2];
+ pu32IspData[3] = pu32Buf[i + 3];
+ __set_PRIMASK(0);
+ }
+
+ while(FMC->ISPSTS & FMC_ISPSTS_ISPBUSY_Msk);
+}
+
+void FMC_Open(void);
+void FMC_Close(void);
+void FMC_EnableAPUpdate(void);
+void FMC_DisableAPUpdate(void);
+void FMC_EnableConfigUpdate(void);
+void FMC_DisableConfigUpdate(void);
+void FMC_EnableLDUpdate(void);
+void FMC_DisableLDUpdate(void);
+int32_t FMC_ReadConfig(uint32_t *u32Config, uint32_t u32Count);
+int32_t FMC_WriteConfig(uint32_t *u32Config, uint32_t u32Count);
+void FMC_SetBootSource(int32_t i32BootSrc);
+int32_t FMC_GetBootSource(void);
+uint32_t FMC_ReadDataFlashBaseAddr(void);
+void FMC_EnableFreqOptimizeMode(uint32_t u32Mode);
+void FMC_DisableFreqOptimizeMode(void);
+/*@}*/ /* end of group FMC_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group FMC_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif
+
diff --git a/bsp/nuvoton_m451/Libraries/StdDriver/inc/gpio.h b/bsp/nuvoton_m451/Libraries/StdDriver/inc/gpio.h
new file mode 100644
index 0000000000000000000000000000000000000000..37ca98f2754c4b57c3b3b1dcbe3ebfbaa1216be5
--- /dev/null
+++ b/bsp/nuvoton_m451/Libraries/StdDriver/inc/gpio.h
@@ -0,0 +1,439 @@
+/**************************************************************************//**
+ * @file GPIO.h
+ * @version V3.00
+ * $Revision: 21 $
+ * $Date: 15/08/11 10:26a $
+ * @brief M451 series GPIO driver header file
+ *
+ * @note
+ * Copyright (C) 2011~2015 Nuvoton Technology Corp. All rights reserved.
+ *
+ ******************************************************************************/
+#ifndef __GPIO_H__
+#define __GPIO_H__
+
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/** @addtogroup Standard_Driver Standard Driver
+ @{
+*/
+
+/** @addtogroup GPIO_Driver GPIO Driver
+ @{
+*/
+
+/** @addtogroup GPIO_EXPORTED_CONSTANTS GPIO Exported Constants
+ @{
+*/
+
+
+#define GPIO_PIN_MAX 16 /*!< Specify Maximum Pins of Each GPIO Port */
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* GPIO_MODE Constant Definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define GPIO_MODE_INPUT 0x0UL /*!< Input Mode */
+#define GPIO_MODE_OUTPUT 0x1UL /*!< Output Mode */
+#define GPIO_MODE_OPEN_DRAIN 0x2UL /*!< Open-Drain Mode */
+#define GPIO_MODE_QUASI 0x3UL /*!< Quasi-bidirectional Mode */
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* GPIO Interrupt Type Constant Definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define GPIO_INT_RISING 0x00010000UL /*!< Interrupt enable by Input Rising Edge */
+#define GPIO_INT_FALLING 0x00000001UL /*!< Interrupt enable by Input Falling Edge */
+#define GPIO_INT_BOTH_EDGE 0x00010001UL /*!< Interrupt enable by both Rising Edge and Falling Edge */
+#define GPIO_INT_HIGH 0x01010000UL /*!< Interrupt enable by Level-High */
+#define GPIO_INT_LOW 0x01000001UL /*!< Interrupt enable by Level-Level */
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* GPIO_INTTYPE Constant Definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define GPIO_INTTYPE_EDGE 0UL /*!< GPIO_INTTYPE Setting for Edge Trigger Mode */
+#define GPIO_INTTYPE_LEVEL 1UL /*!< GPIO_INTTYPE Setting for Edge Level Mode */
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* GPIO_DBCTL Constant Definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define GPIO_DBCTL_ICLK_ON 0x00000020UL /*!< GPIO_DBCTL setting for all IO pins edge detection circuit is always active after reset */
+#define GPIO_DBCTL_ICLK_OFF 0x00000000UL /*!< GPIO_DBCTL setting for edge detection circuit is active only if IO pin corresponding GPIOx_IEN bit is set to 1 */
+
+#define GPIO_DBCTL_DBCLKSRC_LIRC 0x00000010UL /*!< GPIO_DBCTL setting for de-bounce counter clock source is the internal 10 kHz */
+#define GPIO_DBCTL_DBCLKSRC_HCLK 0x00000000UL /*!< GPIO_DBCTL setting for de-bounce counter clock source is the HCLK */
+
+#define GPIO_DBCTL_DBCLKSEL_1 0x00000000UL /*!< GPIO_DBCTL setting for sampling cycle = 1 clocks */
+#define GPIO_DBCTL_DBCLKSEL_2 0x00000001UL /*!< GPIO_DBCTL setting for sampling cycle = 2 clocks */
+#define GPIO_DBCTL_DBCLKSEL_4 0x00000002UL /*!< GPIO_DBCTL setting for sampling cycle = 4 clocks */
+#define GPIO_DBCTL_DBCLKSEL_8 0x00000003UL /*!< GPIO_DBCTL setting for sampling cycle = 8 clocks */
+#define GPIO_DBCTL_DBCLKSEL_16 0x00000004UL /*!< GPIO_DBCTL setting for sampling cycle = 16 clocks */
+#define GPIO_DBCTL_DBCLKSEL_32 0x00000005UL /*!< GPIO_DBCTL setting for sampling cycle = 32 clocks */
+#define GPIO_DBCTL_DBCLKSEL_64 0x00000006UL /*!< GPIO_DBCTL setting for sampling cycle = 64 clocks */
+#define GPIO_DBCTL_DBCLKSEL_128 0x00000007UL /*!< GPIO_DBCTL setting for sampling cycle = 128 clocks */
+#define GPIO_DBCTL_DBCLKSEL_256 0x00000008UL /*!< GPIO_DBCTL setting for sampling cycle = 256 clocks */
+#define GPIO_DBCTL_DBCLKSEL_512 0x00000009UL /*!< GPIO_DBCTL setting for sampling cycle = 512 clocks */
+#define GPIO_DBCTL_DBCLKSEL_1024 0x0000000AUL /*!< GPIO_DBCTL setting for sampling cycle = 1024 clocks */
+#define GPIO_DBCTL_DBCLKSEL_2048 0x0000000BUL /*!< GPIO_DBCTL setting for sampling cycle = 2048 clocks */
+#define GPIO_DBCTL_DBCLKSEL_4096 0x0000000CUL /*!< GPIO_DBCTL setting for sampling cycle = 4096 clocks */
+#define GPIO_DBCTL_DBCLKSEL_8192 0x0000000DUL /*!< GPIO_DBCTL setting for sampling cycle = 8192 clocks */
+#define GPIO_DBCTL_DBCLKSEL_16384 0x0000000EUL /*!< GPIO_DBCTL setting for sampling cycle = 16384 clocks */
+#define GPIO_DBCTL_DBCLKSEL_32768 0x0000000FUL /*!< GPIO_DBCTL setting for sampling cycle = 32768 clocks */
+
+
+/* Define GPIO Pin Data Input/Output. It could be used to control each I/O pin by pin address mapping.
+ Example 1:
+
+ PA0 = 1;
+
+ It is used to set GPIO PA.0 to high;
+
+ Example 2:
+
+ if (PA0)
+ PA0 = 0;
+
+ If GPIO PA.0 pin status is high, then set GPIO PA.0 data output to low.
+ */
+#define GPIO_PIN_DATA(port, pin) (*((volatile uint32_t *)((GPIO_PIN_DATA_BASE+(0x40*(port))) + ((pin)<<2))))
+#define PA0 GPIO_PIN_DATA(0, 0 ) /*!< Specify PA.0 Pin Data Input/Output */
+#define PA1 GPIO_PIN_DATA(0, 1 ) /*!< Specify PA.1 Pin Data Input/Output */
+#define PA2 GPIO_PIN_DATA(0, 2 ) /*!< Specify PA.2 Pin Data Input/Output */
+#define PA3 GPIO_PIN_DATA(0, 3 ) /*!< Specify PA.3 Pin Data Input/Output */
+#define PA4 GPIO_PIN_DATA(0, 4 ) /*!< Specify PA.4 Pin Data Input/Output */
+#define PA5 GPIO_PIN_DATA(0, 5 ) /*!< Specify PA.5 Pin Data Input/Output */
+#define PA6 GPIO_PIN_DATA(0, 6 ) /*!< Specify PA.6 Pin Data Input/Output */
+#define PA7 GPIO_PIN_DATA(0, 7 ) /*!< Specify PA.7 Pin Data Input/Output */
+#define PA8 GPIO_PIN_DATA(0, 8 ) /*!< Specify PA.8 Pin Data Input/Output */
+#define PA9 GPIO_PIN_DATA(0, 9 ) /*!< Specify PA.9 Pin Data Input/Output */
+#define PA10 GPIO_PIN_DATA(0, 10) /*!< Specify PA.10 Pin Data Input/Output */
+#define PA11 GPIO_PIN_DATA(0, 11) /*!< Specify PA.11 Pin Data Input/Output */
+#define PA12 GPIO_PIN_DATA(0, 12) /*!< Specify PA.12 Pin Data Input/Output */
+#define PA13 GPIO_PIN_DATA(0, 13) /*!< Specify PA.13 Pin Data Input/Output */
+#define PA14 GPIO_PIN_DATA(0, 14) /*!< Specify PA.14 Pin Data Input/Output */
+#define PA15 GPIO_PIN_DATA(0, 15) /*!< Specify PA.15 Pin Data Input/Output */
+#define PB0 GPIO_PIN_DATA(1, 0 ) /*!< Specify PB.0 Pin Data Input/Output */
+#define PB1 GPIO_PIN_DATA(1, 1 ) /*!< Specify PB.1 Pin Data Input/Output */
+#define PB2 GPIO_PIN_DATA(1, 2 ) /*!< Specify PB.2 Pin Data Input/Output */
+#define PB3 GPIO_PIN_DATA(1, 3 ) /*!< Specify PB.3 Pin Data Input/Output */
+#define PB4 GPIO_PIN_DATA(1, 4 ) /*!< Specify PB.4 Pin Data Input/Output */
+#define PB5 GPIO_PIN_DATA(1, 5 ) /*!< Specify PB.5 Pin Data Input/Output */
+#define PB6 GPIO_PIN_DATA(1, 6 ) /*!< Specify PB.6 Pin Data Input/Output */
+#define PB7 GPIO_PIN_DATA(1, 7 ) /*!< Specify PB.7 Pin Data Input/Output */
+#define PB8 GPIO_PIN_DATA(1, 8 ) /*!< Specify PB.8 Pin Data Input/Output */
+#define PB9 GPIO_PIN_DATA(1, 9 ) /*!< Specify PB.9 Pin Data Input/Output */
+#define PB10 GPIO_PIN_DATA(1, 10) /*!< Specify PB.10 Pin Data Input/Output */
+#define PB11 GPIO_PIN_DATA(1, 11) /*!< Specify PB.11 Pin Data Input/Output */
+#define PB12 GPIO_PIN_DATA(1, 12) /*!< Specify PB.12 Pin Data Input/Output */
+#define PB13 GPIO_PIN_DATA(1, 13) /*!< Specify PB.13 Pin Data Input/Output */
+#define PB14 GPIO_PIN_DATA(1, 14) /*!< Specify PB.14 Pin Data Input/Output */
+#define PB15 GPIO_PIN_DATA(1, 15) /*!< Specify PB.15 Pin Data Input/Output */
+#define PC0 GPIO_PIN_DATA(2, 0 ) /*!< Specify PC.0 Pin Data Input/Output */
+#define PC1 GPIO_PIN_DATA(2, 1 ) /*!< Specify PC.1 Pin Data Input/Output */
+#define PC2 GPIO_PIN_DATA(2, 2 ) /*!< Specify PC.2 Pin Data Input/Output */
+#define PC3 GPIO_PIN_DATA(2, 3 ) /*!< Specify PC.3 Pin Data Input/Output */
+#define PC4 GPIO_PIN_DATA(2, 4 ) /*!< Specify PC.4 Pin Data Input/Output */
+#define PC5 GPIO_PIN_DATA(2, 5 ) /*!< Specify PC.5 Pin Data Input/Output */
+#define PC6 GPIO_PIN_DATA(2, 6 ) /*!< Specify PC.6 Pin Data Input/Output */
+#define PC7 GPIO_PIN_DATA(2, 7 ) /*!< Specify PC.7 Pin Data Input/Output */
+#define PC8 GPIO_PIN_DATA(2, 8 ) /*!< Specify PC.8 Pin Data Input/Output */
+#define PC9 GPIO_PIN_DATA(2, 9 ) /*!< Specify PC.9 Pin Data Input/Output */
+#define PC10 GPIO_PIN_DATA(2, 10) /*!< Specify PC.10 Pin Data Input/Output */
+#define PC11 GPIO_PIN_DATA(2, 11) /*!< Specify PC.11 Pin Data Input/Output */
+#define PC12 GPIO_PIN_DATA(2, 12) /*!< Specify PC.12 Pin Data Input/Output */
+#define PC13 GPIO_PIN_DATA(2, 13) /*!< Specify PC.13 Pin Data Input/Output */
+#define PC14 GPIO_PIN_DATA(2, 14) /*!< Specify PC.14 Pin Data Input/Output */
+#define PC15 GPIO_PIN_DATA(2, 15) /*!< Specify PC.15 Pin Data Input/Output */
+#define PD0 GPIO_PIN_DATA(3, 0 ) /*!< Specify PD.0 Pin Data Input/Output */
+#define PD1 GPIO_PIN_DATA(3, 1 ) /*!< Specify PD.1 Pin Data Input/Output */
+#define PD2 GPIO_PIN_DATA(3, 2 ) /*!< Specify PD.2 Pin Data Input/Output */
+#define PD3 GPIO_PIN_DATA(3, 3 ) /*!< Specify PD.3 Pin Data Input/Output */
+#define PD4 GPIO_PIN_DATA(3, 4 ) /*!< Specify PD.4 Pin Data Input/Output */
+#define PD5 GPIO_PIN_DATA(3, 5 ) /*!< Specify PD.5 Pin Data Input/Output */
+#define PD6 GPIO_PIN_DATA(3, 6 ) /*!< Specify PD.6 Pin Data Input/Output */
+#define PD7 GPIO_PIN_DATA(3, 7 ) /*!< Specify PD.7 Pin Data Input/Output */
+#define PD8 GPIO_PIN_DATA(3, 8 ) /*!< Specify PD.8 Pin Data Input/Output */
+#define PD9 GPIO_PIN_DATA(3, 9 ) /*!< Specify PD.9 Pin Data Input/Output */
+#define PD10 GPIO_PIN_DATA(3, 10) /*!< Specify PD.10 Pin Data Input/Output */
+#define PD11 GPIO_PIN_DATA(3, 11) /*!< Specify PD.11 Pin Data Input/Output */
+#define PD12 GPIO_PIN_DATA(3, 12) /*!< Specify PD.12 Pin Data Input/Output */
+#define PD13 GPIO_PIN_DATA(3, 13) /*!< Specify PD.13 Pin Data Input/Output */
+#define PD14 GPIO_PIN_DATA(3, 14) /*!< Specify PD.14 Pin Data Input/Output */
+#define PD15 GPIO_PIN_DATA(3, 15) /*!< Specify PD.15 Pin Data Input/Output */
+#define PE0 GPIO_PIN_DATA(4, 0 ) /*!< Specify PE.0 Pin Data Input/Output */
+#define PE1 GPIO_PIN_DATA(4, 1 ) /*!< Specify PE.1 Pin Data Input/Output */
+#define PE2 GPIO_PIN_DATA(4, 2 ) /*!< Specify PE.2 Pin Data Input/Output */
+#define PE3 GPIO_PIN_DATA(4, 3 ) /*!< Specify PE.3 Pin Data Input/Output */
+#define PE4 GPIO_PIN_DATA(4, 4 ) /*!< Specify PE.4 Pin Data Input/Output */
+#define PE5 GPIO_PIN_DATA(4, 5 ) /*!< Specify PE.5 Pin Data Input/Output */
+#define PE6 GPIO_PIN_DATA(4, 6 ) /*!< Specify PE.6 Pin Data Input/Output */
+#define PE7 GPIO_PIN_DATA(4, 7 ) /*!< Specify PE.7 Pin Data Input/Output */
+#define PE8 GPIO_PIN_DATA(4, 8 ) /*!< Specify PE.8 Pin Data Input/Output */
+#define PE9 GPIO_PIN_DATA(4, 9 ) /*!< Specify PE.9 Pin Data Input/Output */
+#define PE10 GPIO_PIN_DATA(4, 10) /*!< Specify PE.10 Pin Data Input/Output */
+#define PE11 GPIO_PIN_DATA(4, 11) /*!< Specify PE.11 Pin Data Input/Output */
+#define PE12 GPIO_PIN_DATA(4, 12) /*!< Specify PE.12 Pin Data Input/Output */
+#define PE13 GPIO_PIN_DATA(4, 13) /*!< Specify PE.13 Pin Data Input/Output */
+#define PE14 GPIO_PIN_DATA(4, 14) /*!< Specify PE.14 Pin Data Input/Output */
+#define PF0 GPIO_PIN_DATA(5, 0 ) /*!< Specify PF.0 Pin Data Input/Output */
+#define PF1 GPIO_PIN_DATA(5, 1 ) /*!< Specify PF.1 Pin Data Input/Output */
+#define PF2 GPIO_PIN_DATA(5, 2 ) /*!< Specify PF.2 Pin Data Input/Output */
+#define PF3 GPIO_PIN_DATA(5, 3 ) /*!< Specify PF.3 Pin Data Input/Output */
+#define PF4 GPIO_PIN_DATA(5, 4 ) /*!< Specify PF.4 Pin Data Input/Output */
+#define PF5 GPIO_PIN_DATA(5, 5 ) /*!< Specify PF.5 Pin Data Input/Output */
+#define PF6 GPIO_PIN_DATA(5, 6 ) /*!< Specify PF.6 Pin Data Input/Output */
+#define PF7 GPIO_PIN_DATA(5, 7 ) /*!< Specify PF.7 Pin Data Input/Output */
+
+
+/*@}*/ /* end of group GPIO_EXPORTED_CONSTANTS */
+
+
+/** @addtogroup GPIO_EXPORTED_FUNCTIONS GPIO Exported Functions
+ @{
+*/
+
+/**
+ * @brief Clear GPIO Pin Interrupt Flag
+ *
+ * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE or PF.
+ * @param[in] u32PinMask The single or multiple pins of specified GPIO port.
+ * It could be BIT0 ~ BIT15 for PA, PB, PC and PD.
+ * It could be BIT0 ~ BIT14 for PE.
+ * It could be BIT0 ~ BIT7 for PF.
+ *
+ * @return None
+ *
+ * @details Clear the interrupt status of specified GPIO pin.
+ */
+#define GPIO_CLR_INT_FLAG(port, u32PinMask) ((port)->INTSRC = (u32PinMask))
+
+/**
+ * @brief Disable Pin De-bounce Function
+ *
+ * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE or PF.
+ * @param[in] u32PinMask The single or multiple pins of specified GPIO port.
+ * It could be BIT0 ~ BIT15 for PA, PB, PC and PD.
+ * It could be BIT0 ~ BIT14 for PE.
+ * It could be BIT0 ~ BIT7 for PF.
+ *
+ * @return None
+ *
+ * @details Disable the interrupt de-bounce function of specified GPIO pin.
+ */
+#define GPIO_DISABLE_DEBOUNCE(port, u32PinMask) ((port)->DBEN &= ~(u32PinMask))
+
+/**
+ * @brief Enable Pin De-bounce Function
+ *
+ * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE or PF.
+ * @param[in] u32PinMask The single or multiple pins of specified GPIO port.
+ * It could be BIT0 ~ BIT15 for PA, PB, PC and PD.
+ * It could be BIT0 ~ BIT14 for PE.
+ * It could be BIT0 ~ BIT7 for PF.
+ * @return None
+ *
+ * @details Enable the interrupt de-bounce function of specified GPIO pin.
+ */
+#define GPIO_ENABLE_DEBOUNCE(port, u32PinMask) ((port)->DBEN |= (u32PinMask))
+
+/**
+ * @brief Disable I/O Digital Input Path
+ *
+ * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE or PF.
+ * @param[in] u32PinMask The single or multiple pins of specified GPIO port.
+ * It could be BIT0 ~ BIT15 for PA, PB, PC and PD.
+ * It could be BIT0 ~ BIT14 for PE.
+ * It could be BIT0 ~ BIT7 for PF.
+ *
+ * @return None
+ *
+ * @details Disable I/O digital input path of specified GPIO pin.
+ */
+#define GPIO_DISABLE_DIGITAL_PATH(port, u32PinMask) ((port)->DINOFF |= ((u32PinMask)<<16))
+
+/**
+ * @brief Enable I/O Digital Input Path
+ *
+ * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE or PF.
+ * @param[in] u32PinMask The single or multiple pins of specified GPIO port.
+ * It could be BIT0 ~ BIT15 for PA, PB, PC and PD.
+ * It could be BIT0 ~ BIT14 for PE.
+ * It could be BIT0 ~ BIT7 for PF.
+ *
+ * @return None
+ *
+ * @details Enable I/O digital input path of specified GPIO pin.
+ */
+#define GPIO_ENABLE_DIGITAL_PATH(port, u32PinMask) ((port)->DINOFF &= ~((u32PinMask)<<16))
+
+/**
+ * @brief Disable I/O DOUT mask
+ *
+ * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE or PF.
+ * @param[in] u32PinMask The single or multiple pins of specified GPIO port.
+ * It could be BIT0 ~ BIT15 for PA, PB, PC and PD.
+ * It could be BIT0 ~ BIT14 for PE.
+ * It could be BIT0 ~ BIT7 for PF.
+ *
+ * @return None
+ *
+ * @details Disable I/O DOUT mask of specified GPIO pin.
+ */
+#define GPIO_DISABLE_DOUT_MASK(port, u32PinMask) ((port)->DATMSK &= ~(u32PinMask))
+
+/**
+ * @brief Enable I/O DOUT mask
+ *
+ * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE or PF.
+ * @param[in] u32PinMask The single or multiple pins of specified GPIO port.
+ * It could be BIT0 ~ BIT15 for PA, PB, PC and PD.
+ * It could be BIT0 ~ BIT14 for PE.
+ * It could be BIT0 ~ BIT7 for PF.
+ *
+ * @return None
+ *
+ * @details Enable I/O DOUT mask of specified GPIO pin.
+ */
+#define GPIO_ENABLE_DOUT_MASK(port, u32PinMask) ((port)->DATMSK |= (u32PinMask))
+
+/**
+ * @brief Get GPIO Pin Interrupt Flag
+ *
+ * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE or PF.
+ * @param[in] u32PinMask The single or multiple pins of specified GPIO port.
+ * It could be BIT0 ~ BIT15 for PA, PB, PC and PD.
+ * It could be BIT0 ~ BIT14 for PE.
+ * It could be BIT0 ~ BIT7 for PF.
+ *
+ * @retval 0 No interrupt at specified GPIO pin
+ * @retval 1 The specified GPIO pin generate an interrupt
+ *
+ * @details Get the interrupt status of specified GPIO pin.
+ */
+#define GPIO_GET_INT_FLAG(port, u32PinMask) ((port)->INTSRC & (u32PinMask))
+
+/**
+ * @brief Set De-bounce Sampling Cycle Time
+ *
+ * @param[in] u32ClkSrc The de-bounce counter clock source. It could be GPIO_DBCTL_DBCLKSRC_HCLK or GPIO_DBCTL_DBCLKSRC_LIRC.
+ * @param[in] u32ClkSel The de-bounce sampling cycle selection. It could be
+ * - \ref GPIO_DBCTL_DBCLKSEL_1
+ * - \ref GPIO_DBCTL_DBCLKSEL_2
+ * - \ref GPIO_DBCTL_DBCLKSEL_4
+ * - \ref GPIO_DBCTL_DBCLKSEL_8
+ * - \ref GPIO_DBCTL_DBCLKSEL_16
+ * - \ref GPIO_DBCTL_DBCLKSEL_32
+ * - \ref GPIO_DBCTL_DBCLKSEL_64
+ * - \ref GPIO_DBCTL_DBCLKSEL_128
+ * - \ref GPIO_DBCTL_DBCLKSEL_256
+ * - \ref GPIO_DBCTL_DBCLKSEL_512
+ * - \ref GPIO_DBCTL_DBCLKSEL_1024
+ * - \ref GPIO_DBCTL_DBCLKSEL_2048
+ * - \ref GPIO_DBCTL_DBCLKSEL_4096
+ * - \ref GPIO_DBCTL_DBCLKSEL_8192
+ * - \ref GPIO_DBCTL_DBCLKSEL_16384
+ * - \ref GPIO_DBCTL_DBCLKSEL_32768
+ *
+ * @return None
+ *
+ * @details Set the interrupt de-bounce sampling cycle time based on the debounce counter clock source. \n
+ * Example: _GPIO_SET_DEBOUNCE_TIME(GPIO_DBCTL_DBCLKSRC_LIRC, GPIO_DBCTL_DBCLKSEL_4). \n
+ * It's meaning the De-debounce counter clock source is internal 10 KHz and sampling cycle selection is 4. \n
+ * Then the target de-bounce sampling cycle time is (4)*(1/(10*1000)) s = 4*0.0001 s = 400 us,
+ * and system will sampling interrupt input once per 00 us.
+ */
+#define GPIO_SET_DEBOUNCE_TIME(u32ClkSrc, u32ClkSel) (GPIO->DBCTL = (GPIO_DBCTL_ICLKON_Msk | (u32ClkSrc) | (u32ClkSel)))
+
+/**
+ * @brief Get GPIO Port IN Data
+ *
+ * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE or PF.
+ *
+ * @return The specified port data
+ *
+ * @details Get the PIN register of specified GPIO port.
+ */
+#define GPIO_GET_IN_DATA(port) ((port)->PIN)
+
+/**
+ * @brief Set GPIO Port OUT Data
+ *
+ * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE or PF.
+ * @param[in] u32Data GPIO port data.
+ *
+ * @return None
+ *
+ * @details Set the Data into specified GPIO port.
+ */
+#define GPIO_SET_OUT_DATA(port, u32Data) ((port)->DOUT = (u32Data))
+
+/**
+ * @brief Toggle Specified GPIO pin
+ *
+ * @param[in] u32Pin Pxy
+ *
+ * @return None
+ *
+ * @details Toggle the specified GPIO pint.
+ */
+#define GPIO_TOGGLE(u32Pin) ((u32Pin) ^= 1)
+
+
+/**
+* @brief Enable External GPIO interrupt
+*
+* @param[in] port GPIO port. It could be PA, PB, PC, PD, PE or PF.
+* @param[in] u32Pin The pin of specified GPIO port.
+* It could be 0 ~ 15 for PA, PB, PC and PD GPIO port.
+* It could be 0 ~ 14 for PE GPIO port.
+* It could be 0 ~ 7 for PF GPIO port.
+* @param[in] u32IntAttribs The interrupt attribute of specified GPIO pin. It could be \n
+* GPIO_INT_RISING, GPIO_INT_FALLING, GPIO_INT_BOTH_EDGE, GPIO_INT_HIGH, GPIO_INT_LOW.
+*
+* @return None
+*
+* @details This function is used to enable specified GPIO pin interrupt.
+*/
+#define GPIO_EnableEINT GPIO_EnableInt
+
+/**
+* @brief Disable External GPIO interrupt
+*
+* @param[in] port GPIO port. It could be PA, PB, PC, PD, PE or PF.
+* @param[in] u32Pin The pin of specified GPIO port.
+* It could be 0 ~ 15 for PA, PB, PC and PD GPIO port.
+* It could be 0 ~ 14 for PE GPIO port.
+* It could be 0 ~ 7 for PF GPIO port.
+*
+* @return None
+*
+* @details This function is used to enable specified GPIO pin interrupt.
+*/
+#define GPIO_DisableEINT GPIO_DisableInt
+
+
+void GPIO_SetMode(GPIO_T *port, uint32_t u32PinMask, uint32_t u32Mode);
+void GPIO_EnableInt(GPIO_T *port, uint32_t u32Pin, uint32_t u32IntAttribs);
+void GPIO_DisableInt(GPIO_T *port, uint32_t u32Pin);
+
+
+/*@}*/ /* end of group GPIO_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group GPIO_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __GPIO_H__
+
+/*** (C) COPYRIGHT 2013~2015 Nuvoton Technology Corp. ***/
diff --git a/bsp/nuvoton_m451/Libraries/StdDriver/inc/i2c.h b/bsp/nuvoton_m451/Libraries/StdDriver/inc/i2c.h
new file mode 100644
index 0000000000000000000000000000000000000000..775946c3481333105086201a76f8f3607114b828
--- /dev/null
+++ b/bsp/nuvoton_m451/Libraries/StdDriver/inc/i2c.h
@@ -0,0 +1,413 @@
+/**************************************************************************//**
+ * @file I2C.h
+ * @version V3.0
+ * $Revision: 19 $
+ * $Date: 15/08/11 10:26a $
+ * @brief M451 Series I2C Driver Header File
+ *
+ * @note
+ * Copyright (C) 2014~2015 Nuvoton Technology Corp. All rights reserved.
+ *
+ ******************************************************************************/
+#ifndef __I2C_H__
+#define __I2C_H__
+
+#include "M451Series.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup Standard_Driver Standard Driver
+ @{
+*/
+
+/** @addtogroup I2C_Driver I2C Driver
+ @{
+*/
+
+/** @addtogroup I2C_EXPORTED_CONSTANTS I2C Exported Constants
+ @{
+*/
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* I2C_CTL constant definitions. */
+/*---------------------------------------------------------------------------------------------------------*/
+#define I2C_CTL_STA_SI 0x28UL /*!< I2C_CTL setting for I2C control bits. It would set STA and SI bits */
+#define I2C_CTL_STA_SI_AA 0x2CUL /*!< I2C_CTL setting for I2C control bits. It would set STA, SI and AA bits */
+#define I2C_CTL_STO_SI 0x18UL /*!< I2C_CTL setting for I2C control bits. It would set STO and SI bits */
+#define I2C_CTL_STO_SI_AA 0x1CUL /*!< I2C_CTL setting for I2C control bits. It would set STO, SI and AA bits */
+#define I2C_CTL_SI 0x08UL /*!< I2C_CTL setting for I2C control bits. It would set SI bit */
+#define I2C_CTL_SI_AA 0x0CUL /*!< I2C_CTL setting for I2C control bits. It would set SI and AA bits */
+#define I2C_CTL_STA 0x20UL /*!< I2C_CTL setting for I2C control bits. It would set STA bit */
+#define I2C_CTL_STO 0x10UL /*!< I2C_CTL setting for I2C control bits. It would set STO bit */
+#define I2C_CTL_AA 0x04UL /*!< I2C_CTL setting for I2C control bits. It would set AA bit */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* I2C GCMode constant definitions. */
+/*---------------------------------------------------------------------------------------------------------*/
+#define I2C_GCMODE_ENABLE 1 /*!< Enable I2C GC Mode */
+#define I2C_GCMODE_DISABLE 0 /*!< Disable I2C GC Mode */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* I2C SMBUS constant definitions. */
+/*---------------------------------------------------------------------------------------------------------*/
+#define I2C_SMBH_ENABLE 1 /*!< Enable SMBus Host Mode enable */
+#define I2C_SMBD_ENABLE 0 /*!< Enable SMBus Device Mode enable */
+#define I2C_PECTX_ENABLE 1 /*!< Enable SMBus Packet Error Check Transmit function */
+#define I2C_PECTX_DISABLE 0 /*!< Disable SMBus Packet Error Check Transmit function */
+
+/*@}*/ /* end of group I2C_EXPORTED_CONSTANTS */
+
+/** @addtogroup I2C_EXPORTED_FUNCTIONS I2C Exported Functions
+ @{
+*/
+/**
+ * @brief The macro is used to set I2C bus condition at One Time
+ *
+ * @param[in] i2c Specify I2C port
+ * @param[in] u8Ctrl A byte writes to I2C control register
+ *
+ * @return None
+ *
+ * @details Set I2C_CTL register to control I2C bus conditions of START, STOP, SI, ACK.
+ */
+#define I2C_SET_CONTROL_REG(i2c, u8Ctrl) ((i2c)->CTL = ((i2c)->CTL & ~0x3c) | (u8Ctrl))
+
+/**
+ * @brief The macro is used to set START condition of I2C Bus
+ *
+ * @param[in] i2c Specify I2C port
+ *
+ * @return None
+ *
+ * @details Set the I2C bus START condition in I2C_CTL register.
+ */
+#define I2C_START(i2c) ((i2c)->CTL = ((i2c)->CTL & ~I2C_CTL_SI_Msk) | I2C_CTL_STA_Msk)
+
+/**
+ * @brief The macro is used to wait I2C bus status get ready
+ *
+ * @param[in] i2c Specify I2C port
+ *
+ * @return None
+ *
+ * @details When a new status is presented of I2C bus, the SI flag will be set in I2C_CTL register.
+ */
+#define I2C_WAIT_READY(i2c) while(!((i2c)->CTL & I2C_CTL_SI_Msk))
+
+/**
+ * @brief The macro is used to Read I2C Bus Data Register
+ *
+ * @param[in] i2c Specify I2C port
+ *
+ * @return A byte of I2C data register
+ *
+ * @details I2C controller read data from bus and save it in I2CDAT register.
+ */
+#define I2C_GET_DATA(i2c) ((i2c)->DAT)
+
+/**
+ * @brief Write a Data to I2C Data Register
+ *
+ * @param[in] i2c Specify I2C port
+ * @param[in] u8Data A byte that writes to data register
+ *
+ * @return None
+ *
+ * @details When write a data to I2C_DAT register, the I2C controller will shift it to I2C bus.
+ */
+#define I2C_SET_DATA(i2c, u8Data) ((i2c)->DAT = (u8Data))
+
+/**
+ * @brief Get I2C Bus status code
+ *
+ * @param[in] i2c Specify I2C port
+ *
+ * @return I2C status code
+ *
+ * @details To get this status code to monitor I2C bus event.
+ */
+#define I2C_GET_STATUS(i2c) ((i2c)->STATUS)
+
+/**
+ * @brief Get Time-out flag from I2C Bus
+ *
+ * @param[in] i2c Specify I2C port
+ *
+ * @retval 0 I2C Bus time-out is not happened
+ * @retval 1 I2C Bus time-out is happened
+ *
+ * @details When I2C bus occurs time-out event, the time-out flag will be set.
+ */
+#define I2C_GET_TIMEOUT_FLAG(i2c) ( ((i2c)->TOCTL & I2C_TOCTL_TOIF_Msk) == I2C_TOCTL_TOIF_Msk ? 1:0 )
+
+/**
+ * @brief To get wake-up flag from I2C Bus
+ *
+ * @param[in] i2c Specify I2C port
+ *
+ * @retval 0 Chip is not woken-up from power-down mode
+ * @retval 1 Chip is woken-up from power-down mode
+ *
+ * @details I2C bus occurs wake-up event, wake-up flag will be set.
+ */
+#define I2C_GET_WAKEUP_FLAG(i2c) ( ((i2c)->WKSTS & I2C_WKSTS_WKIF_Msk) == I2C_WKSTS_WKIF_Msk ? 1:0 )
+
+/**
+ * @brief To clear wake-up flag
+ *
+ * @param[in] i2c Specify I2C port
+ *
+ * @return None
+ *
+ * @details If wake-up flag is set, use this macro to clear it.
+ */
+#define I2C_CLEAR_WAKEUP_FLAG(i2c) ((i2c)->WKSTS = I2C_WKSTS_WKIF_Msk)
+
+/**
+ * @brief To get SMBus Status
+ *
+ * @param[in] i2c Specify I2C port
+ *
+ * @return SMBus status
+ *
+ * @details To get the Bus Management status of I2C_BUSSTS register
+ *
+ */
+#define I2C_SMBUS_GET_STATUS(i2c) ((i2c)->BUSSTS)
+
+/**
+ * @brief Get SMBus CRC value
+ *
+ * @param[in] i2c Specify I2C port
+ *
+ * @return Packet error check byte value
+ *
+ * @details The CRC check value after a transmission or a reception by count by using CRC8
+ *
+ */
+#define I2C_SMBUS_GET_PEC_VALUE(i2c) ((i2c)->PKTCRC)
+
+/**
+ * @brief Set SMBus Bytes number of Transmission or reception
+ *
+ * @param[in] i2c Specify I2C port
+ * @param[in] u32PktSize Transmit / Receive bytes
+ *
+ * @return None
+ *
+ * @details The transmission or receive byte number in one transaction when PECEN is set. The maximum is 255 bytes.
+ *
+ */
+#define I2C_SMBUS_SET_PACKET_BYTE_COUNT(i2c, u32PktSize) ((i2c)->PKTSIZE = (u32PktSize))
+
+/**
+ * @brief Enable SMBus Alert function
+ *
+ * @param[in] i2c Specify I2C port
+ *
+ * @return None
+ *
+ * @details Device Mode(BMHEN=0): If ALERTEN(I2C_BUSCTL[4]) is set, the Alert pin will pull lo, and reply ACK when get ARP from host
+ * Host Mode(BMHEN=1): If ALERTEN(I2C_BUSCTL[4]) is set, the Alert pin is supported to receive alert state(Lo trigger)
+ *
+ */
+#define I2C_SMBUS_ENABLE_ALERT(i2c) ((i2c)->BUSCTL |= I2C_BUSCTL_ALERTEN_Msk)
+
+/**
+ * @brief Disable SMBus Alert pin function
+ *
+ * @param[in] i2c Specify I2C port
+ *
+ * @return None
+ *
+ * @details Device Mode(BMHEN=0): If ALERTEN(I2C_BUSCTL[4]) is clear, the Alert pin will pull hi, and reply NACK when get ARP from host
+ * Host Mode(BMHEN=1): If ALERTEN(I2C_BUSCTL[4]) is clear, the Alert pin is not supported to receive alert state(Lo trigger)
+ *
+ */
+#define I2C_SMBUS_DISABLE_ALERT(i2c) ((i2c)->BUSCTL &= ~I2C_BUSCTL_ALERTEN_Msk)
+
+/**
+ * @brief Set SMBus SUSCON pin is output mode
+ *
+ * @param[in] i2c Specify I2C port
+ *
+ * @return None
+ *
+ * @details This function to set SUSCON(I2C_BUSCTL[6]) pin is output mode.
+ *
+ *
+ */
+#define I2C_SMBUS_SET_SUSCON_OUT(i2c) ((i2c)->BUSCTL |= I2C_BUSCTL_SCTLOEN_Msk)
+
+/**
+ * @brief Set SMBus SUSCON pin is input mode
+ *
+ * @param[in] i2c Specify I2C port
+ *
+ * @return None
+ *
+ * @details This function to set SUSCON(I2C_BUSCTL[6]) pin is input mode.
+ *
+ *
+ */
+#define I2C_SMBUS_SET_SUSCON_IN(i2c) ((i2c)->BUSCTL &= ~I2C_BUSCTL_SCTLOEN_Msk)
+
+/**
+ * @brief Set SMBus SUSCON pin output high state
+ *
+ * @param[in] i2c Specify I2C port
+ *
+ * @return None
+ *
+ * @details This function to set SUSCON(I2C_BUSCTL[6]) pin is output hi state.
+ *
+ */
+#define I2C_SMBUS_SET_SUSCON_HIGH(i2c) ((i2c)->BUSCTL |= I2C_BUSCTL_SCTLOSTS_Msk)
+
+
+/**
+ * @brief Set SMBus SUSCON pin output low state
+ *
+ * @param[in] i2c Specify I2C port
+ *
+ * @return None
+ *
+ * @details This function to set SUSCON(I2C_BUSCTL[6]) pin is output lo state.
+ *
+ */
+#define I2C_SMBUS_SET_SUSCON_LOW(i2c) ((i2c)->BUSCTL &= ~I2C_BUSCTL_SCTLOSTS_Msk)
+
+/**
+ * @brief Enable SMBus Acknowledge control by manual
+ *
+ * @param[in] i2c Specify I2C port
+ *
+ * @return None
+ *
+ * @details The 9th bit can response the ACK or NACK according the received data by user. When the byte is received, SCLK line stretching to low between the 8th and 9th SCLK pulse.
+ *
+ */
+#define I2C_SMBUS_ACK_MANUAL(i2c) ((i2c)->BUSCTL |= I2C_BUSCTL_ACKMEN_Msk)
+
+/**
+ * @brief Disable SMBus Acknowledge control by manual
+ *
+ * @param[in] i2c Specify I2C port
+ *
+ * @return None
+ *
+ * @details Disable acknowledge response control by user.
+ *
+ */
+#define I2C_SMBUS_ACK_AUTO(i2c) ((i2c)->BUSCTL &= ~I2C_BUSCTL_ACKMEN_Msk)
+
+/**
+ * @brief Enable SMBus Acknowledge manual interrupt
+ *
+ * @param[in] i2c Specify I2C port
+ *
+ * @return None
+ *
+ * @details This function is used to enable SMBUS acknowledge manual interrupt on the 9th clock cycle when SMBUS=1 and ACKMEN=1
+ *
+ */
+#define I2C_SMBUS_9THBIT_INT_ENABLE(i2c) ((i2c)->BUSCTL |= I2C_BUSCTL_ACKM9SI_Msk)
+
+/**
+ * @brief Disable SMBus Acknowledge manual interrupt
+ *
+ * @param[in] i2c Specify I2C port
+ *
+ * @return None
+ *
+ * @details This function is used to disable SMBUS acknowledge manual interrupt on the 9th clock cycle when SMBUS=1 and ACKMEN=1
+ *
+ */
+#define I2C_SMBUS_9THBIT_INT_DISABLE(i2c) ((i2c)->BUSCTL &= ~I2C_BUSCTL_ACKM9SI_Msk)
+
+/**
+ * @brief Enable SMBus PEC clear at REPEAT START
+ *
+ * @param[in] i2c Specify I2C port
+ *
+ * @return None
+ *
+ * @details This function is used to enable the condition of REAEAT START can clear the PEC calculation.
+ *
+ */
+#define I2C_SMBUS_RST_PEC_AT_START_ENABLE(i2c) ((i2c)->BUSCTL |= I2C_BUSCTL_PECCLR_Msk)
+
+/**
+ * @brief Disable SMBus PEC clear at Repeat START
+ *
+ * @param[in] i2c Specify I2C port
+ *
+ * @return None
+ *
+ * @details This function is used to disable the condition of Repeat START can clear the PEC calculation.
+ *
+ */
+#define I2C_SMBUS_RST_PEC_AT_START_DISABLE(i2c) ((i2c)->BUSCTL &= ~I2C_BUSCTL_PECCLR_Msk)
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* inline functions */
+/*---------------------------------------------------------------------------------------------------------*/
+/**
+ * @brief The macro is used to set STOP condition of I2C Bus
+ *
+ * @param[in] i2c Specify I2C port
+ *
+ * @return None
+ *
+ * @details Set the I2C bus STOP condition in I2C_CTL register.
+ */
+static __INLINE void I2C_STOP(I2C_T *i2c)
+{
+
+ (i2c)->CTL |= (I2C_CTL_SI_Msk | I2C_CTL_STO_Msk);
+ while(i2c->CTL & I2C_CTL_STO_Msk);
+}
+
+void I2C_ClearTimeoutFlag(I2C_T *i2c);
+void I2C_Close(I2C_T *i2c);
+void I2C_Trigger(I2C_T *i2c, uint8_t u8Start, uint8_t u8Stop, uint8_t u8Si, uint8_t u8Ack);
+void I2C_DisableInt(I2C_T *i2c);
+void I2C_EnableInt(I2C_T *i2c);
+uint32_t I2C_GetBusClockFreq(I2C_T *i2c);
+uint32_t I2C_GetIntFlag(I2C_T *i2c);
+uint32_t I2C_GetStatus(I2C_T *i2c);
+uint32_t I2C_Open(I2C_T *i2c, uint32_t u32BusClock);
+uint8_t I2C_GetData(I2C_T *i2c);
+void I2C_SetSlaveAddr(I2C_T *i2c, uint8_t u8SlaveNo, uint8_t u8SlaveAddr, uint8_t u8GCMode);
+void I2C_SetSlaveAddrMask(I2C_T *i2c, uint8_t u8SlaveNo, uint8_t u8SlaveAddrMask);
+uint32_t I2C_SetBusClockFreq(I2C_T *i2c, uint32_t u32BusClock);
+void I2C_EnableTimeout(I2C_T *i2c, uint8_t u8LongTimeout);
+void I2C_DisableTimeout(I2C_T *i2c);
+void I2C_EnableWakeup(I2C_T *i2c);
+void I2C_DisableWakeup(I2C_T *i2c);
+void I2C_SetData(I2C_T *i2c, uint8_t u8Data);
+
+uint32_t I2C_SMBusGetStatus(I2C_T *i2c);
+void I2C_SMBusClearInterruptFlag(I2C_T *i2c, uint8_t u8ClrSMBusIntFlag);
+void I2C_SMBusSetPacketByteCount(I2C_T *i2c, uint32_t u32PktSize);
+void I2C_SMBusOpen(I2C_T *i2c, uint8_t u8HostDevice);
+void I2C_SMBusClose(I2C_T *i2c);
+void I2C_SMBusPECTxEnable(I2C_T *i2c, uint8_t u8PECTxEn);
+uint8_t I2C_SMBusGetPECValue(I2C_T *i2c);
+void I2C_SMBusIdleTimeout(I2C_T *i2c, uint32_t us, uint32_t u32Hclk);
+void I2C_SMBusTimeout(I2C_T *i2c, uint32_t ms, uint32_t u32Pclk);
+void I2C_SMBusClockLoTimeout(I2C_T *i2c, uint32_t ms, uint32_t u32Pclk);
+/*@}*/ /* end of group I2C_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group I2C_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+#endif //__I2C_H__
diff --git a/bsp/nuvoton_m451/Libraries/StdDriver/inc/otg.h b/bsp/nuvoton_m451/Libraries/StdDriver/inc/otg.h
new file mode 100644
index 0000000000000000000000000000000000000000..4137650aa5cd1db3881faa26c34f83f2d8d64940
--- /dev/null
+++ b/bsp/nuvoton_m451/Libraries/StdDriver/inc/otg.h
@@ -0,0 +1,260 @@
+/**************************************************************************//**
+ * @file otg.h
+ * @version V0.10
+ * $Revision: 3 $
+ * $Date: 15/08/11 10:26a $
+ * @brief M451 Series OTG Driver Header File
+ *
+ * @note
+ * Copyright (C) 2014~2015 Nuvoton Technology Corp. All rights reserved.
+ *
+ ******************************************************************************/
+#ifndef __OTG_H__
+#define __OTG_H__
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Include related headers */
+/*---------------------------------------------------------------------------------------------------------*/
+#include "M451Series.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup Standard_Driver Standard Driver
+ @{
+*/
+
+/** @addtogroup OTG_Driver OTG Driver
+ @{
+*/
+
+
+/** @addtogroup OTG_EXPORTED_CONSTANTS OTG Exported Constants
+ @{
+*/
+
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* OTG constant definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define OTG_VBUS_EN_ACTIVE_HIGH (0UL) /*!< USB VBUS power switch enable signal is active high. */
+#define OTG_VBUS_EN_ACTIVE_LOW (1UL) /*!< USB VBUS power switch enable signal is active low. */
+#define OTG_VBUS_ST_VALID_HIGH (0UL) /*!< USB VBUS power switch valid status is high. */
+#define OTG_VBUS_ST_VALID_LOW (1UL) /*!< USB VBUS power switch valid status is low. */
+
+
+/*@}*/ /* end of group OTG_EXPORTED_CONSTANTS */
+
+
+/** @addtogroup OTG_EXPORTED_FUNCTIONS OTG Exported Functions
+ @{
+*/
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Define Macros and functions */
+/*---------------------------------------------------------------------------------------------------------*/
+
+
+/**
+ * @brief This macro is used to enable OTG function
+ * @param None
+ * @return None
+ * @details This macro will set OTGEN bit of OTG_CTL register to enable OTG function.
+ */
+#define OTG_ENABLE() (OTG->CTL |= OTG_CTL_OTGEN_Msk)
+
+/**
+ * @brief This macro is used to disable OTG function
+ * @param None
+ * @return None
+ * @details This macro will clear OTGEN bit of OTG_CTL register to disable OTG function.
+ */
+#define OTG_DISABLE() (OTG->CTL &= ~OTG_CTL_OTGEN_Msk)
+
+/**
+ * @brief This macro is used to enable USB PHY
+ * @param None
+ * @return None
+ * @details When the USB role is selected as OTG device, use this macro to enable USB PHY.
+ * This macro will set OTGPHYEN bit of OTG_PHYCTL register to enable USB PHY.
+ */
+#define OTG_ENABLE_PHY() (OTG->PHYCTL |= OTG_PHYCTL_OTGPHYEN_Msk)
+
+/**
+ * @brief This macro is used to disable USB PHY
+ * @param None
+ * @return None
+ * @details This macro will clear OTGPHYEN bit of OTG_PHYCTL register to disable USB PHY.
+ */
+#define OTG_DISABLE_PHY() (OTG->PHYCTL &= ~OTG_PHYCTL_OTGPHYEN_Msk)
+
+/**
+ * @brief This macro is used to enable ID detection function
+ * @param None
+ * @return None
+ * @details This macro will set IDDETEN bit of OTG_PHYCTL register to enable ID detection function.
+ */
+#define OTG_ENABLE_ID_DETECT() (OTG->PHYCTL |= OTG_PHYCTL_IDDETEN_Msk)
+
+/**
+ * @brief This macro is used to disable ID detection function
+ * @param None
+ * @return None
+ * @details This macro will clear IDDETEN bit of OTG_PHYCTL register to disable ID detection function.
+ */
+#define OTG_DISABLE_ID_DETECT() (OTG->PHYCTL &= ~OTG_PHYCTL_IDDETEN_Msk)
+
+/**
+ * @brief This macro is used to enable OTG wake-up function
+ * @param None
+ * @return None
+ * @details This macro will set WKEN bit of OTG_CTL register to enable OTG wake-up function.
+ */
+#define OTG_ENABLE_WAKEUP() (OTG->CTL |= OTG_CTL_WKEN_Msk)
+
+/**
+ * @brief This macro is used to disable OTG wake-up function
+ * @param None
+ * @return None
+ * @details This macro will clear WKEN bit of OTG_CTL register to disable OTG wake-up function.
+ */
+#define OTG_DISABLE_WAKEUP() (OTG->CTL &= ~OTG_CTL_WKEN_Msk)
+
+/**
+ * @brief This macro is used to set the polarity of USB_VBUS_EN pin
+ * @param[in] u32Pol The polarity selection. Valid values are listed below.
+ * - \ref OTG_VBUS_EN_ACTIVE_HIGH
+ * - \ref OTG_VBUS_EN_ACTIVE_LOW
+ * @return None
+ * @details This macro is used to set the polarity of external USB VBUS power switch enable signal.
+ */
+#define OTG_SET_VBUS_EN_POL(u32Pol) (OTG->PHYCTL = (OTG->PHYCTL & (~OTG_PHYCTL_VBENPOL_Msk)) | ((u32Pol)<PHYCTL = (OTG->PHYCTL & (~OTG_PHYCTL_VBSTSPOL_Msk)) | ((u32Pol)<INTEN |= (u32Mask))
+
+/**
+ * @brief This macro is used to disable OTG related interrupts
+ * @param[in] u32Mask The combination of interrupt source. Each bit corresponds to a interrupt source. Valid values are listed below.
+ * - \ref OTG_INTEN_ROLECHGIEN_Msk
+ * - \ref OTG_INTEN_VBEIEN_Msk
+ * - \ref OTG_INTEN_SRPFIEN_Msk
+ * - \ref OTG_INTEN_HNPFIEN_Msk
+ * - \ref OTG_INTEN_GOIDLEIEN_Msk
+ * - \ref OTG_INTEN_IDCHGIEN_Msk
+ * - \ref OTG_INTEN_PDEVIEN_Msk
+ * - \ref OTG_INTEN_HOSTIEN_Msk
+ * - \ref OTG_INTEN_BVLDCHGIEN_Msk
+ * - \ref OTG_INTEN_AVLDCHGIEN_Msk
+ * - \ref OTG_INTEN_VBCHGIEN_Msk
+ * - \ref OTG_INTEN_SECHGIEN_Msk
+ * - \ref OTG_INTEN_SRPDETIEN_Msk
+ * @return None
+ * @details This macro will disable OTG related interrupts specified by u32Mask parameter.
+ */
+#define OTG_DISABLE_INT(u32Mask) (OTG->INTEN &= ~(u32Mask))
+
+/**
+ * @brief This macro is used to get OTG related interrupt flags
+ * @param[in] u32Mask The combination of interrupt source. Each bit corresponds to a interrupt source. Valid values are listed below.
+ * - \ref OTG_INTSTS_ROLECHGIF_Msk
+ * - \ref OTG_INTSTS_VBEIF_Msk
+ * - \ref OTG_INTSTS_SRPFIF_Msk
+ * - \ref OTG_INTSTS_HNPFIF_Msk
+ * - \ref OTG_INTSTS_GOIDLEIF_Msk
+ * - \ref OTG_INTSTS_IDCHGIF_Msk
+ * - \ref OTG_INTSTS_PDEVIF_Msk
+ * - \ref OTG_INTSTS_HOSTIF_Msk
+ * - \ref OTG_INTSTS_BVLDCHGIF_Msk
+ * - \ref OTG_INTSTS_AVLDCHGIF_Msk
+ * - \ref OTG_INTSTS_VBCHGIF_Msk
+ * - \ref OTG_INTSTS_SECHGIF_Msk
+ * - \ref OTG_INTSTS_SRPDETIF_Msk
+ * @return Interrupt flags of selected sources.
+ * @details This macro will return OTG related interrupt flags specified by u32Mask parameter.
+ */
+#define OTG_GET_INT_FLAG(u32Mask) (OTG->INTSTS & (u32Mask))
+
+/**
+ * @brief This macro is used to clear OTG related interrupt flags
+ * @param[in] u32Mask The combination of interrupt source. Each bit corresponds to a interrupt source. Valid values are listed below.
+ * - \ref OTG_INTSTS_ROLECHGIF_Msk
+ * - \ref OTG_INTSTS_VBEIF_Msk
+ * - \ref OTG_INTSTS_SRPFIF_Msk
+ * - \ref OTG_INTSTS_HNPFIF_Msk
+ * - \ref OTG_INTSTS_GOIDLEIF_Msk
+ * - \ref OTG_INTSTS_IDCHGIF_Msk
+ * - \ref OTG_INTSTS_PDEVIF_Msk
+ * - \ref OTG_INTSTS_HOSTIF_Msk
+ * - \ref OTG_INTSTS_BVLDCHGIF_Msk
+ * - \ref OTG_INTSTS_AVLDCHGIF_Msk
+ * - \ref OTG_INTSTS_VBCHGIF_Msk
+ * - \ref OTG_INTSTS_SECHGIF_Msk
+ * - \ref OTG_INTSTS_SRPDETIF_Msk
+ * @return None
+ * @details This macro will clear OTG related interrupt flags specified by u32Mask parameter.
+ */
+#define OTG_CLR_INT_FLAG(u32Mask) (OTG->INTSTS = (u32Mask))
+
+/**
+ * @brief This macro is used to get OTG related status
+ * @param[in] u32Mask The combination of user specified source. Valid values are listed below.
+ * - \ref OTG_STATUS_OVERCUR_Msk
+ * - \ref OTG_STATUS_IDSTS_Msk
+ * - \ref OTG_STATUS_SESSEND_Msk
+ * - \ref OTG_STATUS_BVLD_Msk
+ * - \ref OTG_STATUS_AVLD_Msk
+ * - \ref OTG_STATUS_VBUSVLD_Msk
+ * @return The user specified status.
+ * @details This macro will return OTG related status specified by u32Mask parameter.
+ */
+#define OTG_GET_STATUS(u32Mask) (OTG->STATUS & (u32Mask))
+
+
+
+/*@}*/ /* end of group OTG_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group OTG_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif //__OTG_H__
+
+/*** (C) COPYRIGHT 2014~2015 Nuvoton Technology Corp. ***/
diff --git a/bsp/nuvoton_m451/Libraries/StdDriver/inc/pdma.h b/bsp/nuvoton_m451/Libraries/StdDriver/inc/pdma.h
new file mode 100644
index 0000000000000000000000000000000000000000..7ca4b45a9e418432babe859a2d73013f4bffbafe
--- /dev/null
+++ b/bsp/nuvoton_m451/Libraries/StdDriver/inc/pdma.h
@@ -0,0 +1,300 @@
+/**************************************************************************//**
+ * @file pdma.h
+ * @version V1.00
+ * $Revision: 15 $
+ * $Date: 15/08/11 10:26a $
+ * @brief M451 series PDMA driver header file
+ *
+ * @note
+ * Copyright (C) 2014~2015 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __PDMA_H__
+#define __PDMA_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup Standard_Driver Standard Driver
+ @{
+*/
+
+/** @addtogroup PDMA_Driver PDMA Driver
+ @{
+*/
+
+/** @addtogroup PDMA_EXPORTED_CONSTANTS PDMA Exported Constants
+ @{
+*/
+#define PDMA_CH_MAX 12 /*!< Specify Maximum Channels of PDMA \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Operation Mode Constant Definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define PDMA_OP_STOP 0x00000000UL /*!INTSTS))
+
+/**
+ * @brief Get Transfer Done Interrupt Status
+ *
+ * @param[in] None
+ *
+ * @return None
+ *
+ * @details Get the transfer done Interrupt status.
+ */
+#define PDMA_GET_TD_STS() ((uint32_t)(PDMA->TDSTS))
+
+/**
+ * @brief Clear Transfer Done Interrupt Status
+ *
+ * @param[in] u32Mask The channel mask
+ *
+ * @return None
+ *
+ * @details Clear the transfer done Interrupt status.
+ */
+#define PDMA_CLR_TD_FLAG(u32Mask) ((uint32_t)(PDMA->TDSTS = (u32Mask)))
+
+/**
+ * @brief Get Target Abort Interrupt Status
+ *
+ * @param[in] None
+ *
+ * @return None
+ *
+ * @details Get the target abort Interrupt status.
+ */
+#define PDMA_GET_ABORT_STS() ((uint32_t)(PDMA->ABTSTS))
+
+/**
+ * @brief Clear Target Abort Interrupt Status
+ *
+ * @param[in] u32Mask The channel mask
+ *
+ * @return None
+ *
+ * @details Clear the target abort Interrupt status.
+ */
+#define PDMA_CLR_ABORT_FLAG(u32Mask) ((uint32_t)(PDMA->ABTSTS = (u32Mask)))
+
+/**
+ * @brief Get Scatter-Gather Table Empty Interrupt Status
+ *
+ * @param[in] None
+ *
+ * @return None
+ *
+ * @details Get the scatter-gather table empty Interrupt status.
+ */
+#define PDMA_GET_EMPTY_STS() ((uint32_t)(PDMA->SCATSTS))
+
+/**
+ * @brief Clear Scatter-Gather Table Empty Interrupt Status
+ *
+ * @param[in] u32Mask The channel mask
+ *
+ * @return None
+ *
+ * @details Clear the scatter-gather table empty Interrupt status.
+ */
+#define PDMA_CLR_EMPTY_FLAG(u32Mask) ((uint32_t)(PDMA->SCATSTS = (u32Mask)))
+
+/**
+ * @brief Clear Timeout Interrupt Status
+ *
+ * @param[in] u32Ch The selected channel
+ *
+ * @return None
+ *
+ * @details Clear the selected channel timeout interrupt status.
+ * @note This function is only supported in M45xD/M45xC.
+ */
+#define PDMA_CLR_TMOUT_FLAG(u32Ch) ((uint32_t)(PDMA->INTSTS = (1 << ((u32Ch) + 8))))
+
+/**
+ * @brief Check Channel Status
+ *
+ * @param[in] u32Ch The selected channel
+ *
+ * @retval 0 Idle state
+ * @retval 1 Busy state
+ *
+ * @details Check the selected channel is busy or not.
+ */
+#define PDMA_IS_CH_BUSY(u32Ch) ((uint32_t)(PDMA->TRGSTS & (1 << (u32Ch)))? 1 : 0)
+
+/**
+ * @brief Set Source Address
+ *
+ * @param[in] u32Ch The selected channel
+ * @param[in] u32Addr The selected address
+ *
+ * @return None
+ *
+ * @details This macro set the selected channel source address.
+ */
+#define PDMA_SET_SRC_ADDR(u32Ch, u32Addr) ((uint32_t)(PDMA->DSCT[(u32Ch)].SA = (u32Addr)))
+
+/**
+ * @brief Set Destination Address
+ *
+ * @param[in] u32Ch The selected channel
+ * @param[in] u32Addr The selected address
+ *
+ * @return None
+ *
+ * @details This macro set the selected channel destination address.
+ */
+#define PDMA_SET_DST_ADDR(u32Ch, u32Addr) ((uint32_t)(PDMA->DSCT[(u32Ch)].DA = (u32Addr)))
+
+/**
+ * @brief Set Transfer Count
+ *
+ * @param[in] u32Ch The selected channel
+ * @param[in] u32TransCount Transfer Count
+ *
+ * @return None
+ *
+ * @details This macro set the selected channel transfer count.
+ */
+#define PDMA_SET_TRANS_CNT(u32Ch, u32TransCount) ((uint32_t)(PDMA->DSCT[(u32Ch)].CTL=(PDMA->DSCT[(u32Ch)].CTL&~PDMA_DSCT_CTL_TXCNT_Msk)|((u32TransCount-1) << PDMA_DSCT_CTL_TXCNT_Pos)))
+
+/**
+ * @brief Set Scatter-gather descriptor Address
+ *
+ * @param[in] u32Ch The selected channel
+ * @param[in] u32Addr The descriptor address
+ *
+ * @return None
+ *
+ * @details This macro set the selected channel scatter-gather descriptor address.
+ */
+#define PDMA_SET_SCATTER_DESC(u32Ch, u32Addr) ((uint32_t)(PDMA->DSCT[(u32Ch)].NEXT = (u32Addr) - (PDMA->SCATBA)))
+
+/**
+ * @brief Stop the channel
+ *
+ * @param[in] u32Ch The selected channel
+ *
+ * @return None
+ *
+ * @details This macro stop the selected channel.
+ */
+#define PDMA_STOP(u32Ch) ((uint32_t)(PDMA->STOP = (1 << (u32Ch))))
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Define PWM functions prototype */
+/*---------------------------------------------------------------------------------------------------------*/
+void PDMA_Open(uint32_t u32Mask);
+void PDMA_Close(void);
+void PDMA_SetTransferCnt(uint32_t u32Ch, uint32_t u32Width, uint32_t u32TransCount);
+void PDMA_SetTransferAddr(uint32_t u32Ch, uint32_t u32SrcAddr, uint32_t u32SrcCtrl, uint32_t u32DstAddr, uint32_t u32DstCtrl);
+void PDMA_SetTransferMode(uint32_t u32Ch, uint32_t u32Peripheral, uint32_t u32ScatterEn, uint32_t u32DescAddr);
+void PDMA_SetBurstType(uint32_t u32Ch, uint32_t u32BurstType, uint32_t u32BurstSize);
+void PDMA_EnableTimeout(uint32_t u32Mask);
+void PDMA_DisableTimeout(uint32_t u32Mask);
+void PDMA_SetTimeOut(uint32_t u32Ch, uint32_t u32OnOff, uint32_t u32TimeOutCnt);
+void PDMA_Trigger(uint32_t u32Ch);
+void PDMA_EnableInt(uint32_t u32Ch, uint32_t u32Mask);
+void PDMA_DisableInt(uint32_t u32Ch, uint32_t u32Mask);
+
+
+/*@}*/ /* end of group PDMA_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group PDMA_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif //__PDMA_H__
+
+/*** (C) COPYRIGHT 2014~2015 Nuvoton Technology Corp. ***/
diff --git a/bsp/nuvoton_m451/Libraries/StdDriver/inc/pwm.h b/bsp/nuvoton_m451/Libraries/StdDriver/inc/pwm.h
new file mode 100644
index 0000000000000000000000000000000000000000..4f382394d5c7f597fe22928075fd913d24949874
--- /dev/null
+++ b/bsp/nuvoton_m451/Libraries/StdDriver/inc/pwm.h
@@ -0,0 +1,555 @@
+/**************************************************************************//**
+ * @file pwm.h
+ * @version V1.00
+ * $Revision: 26 $
+ * $Date: 15/08/11 10:26a $
+ * @brief M451 series PWM driver header file
+ *
+ * @note
+ * Copyright (C) 2014~2015 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __PWM_H__
+#define __PWM_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup Standard_Driver Standard Driver
+ @{
+*/
+
+/** @addtogroup PWM_Driver PWM Driver
+ @{
+*/
+
+/** @addtogroup PWM_EXPORTED_CONSTANTS PWM Exported Constants
+ @{
+*/
+#define PWM_CHANNEL_NUM (6) /*!< PWM channel number */
+#define PWM_CH_0_MASK (0x1UL) /*!< PWM channel 0 mask \hideinitializer */
+#define PWM_CH_1_MASK (0x2UL) /*!< PWM channel 1 mask \hideinitializer */
+#define PWM_CH_2_MASK (0x4UL) /*!< PWM channel 2 mask \hideinitializer */
+#define PWM_CH_3_MASK (0x8UL) /*!< PWM channel 3 mask \hideinitializer */
+#define PWM_CH_4_MASK (0x10UL) /*!< PWM channel 4 mask \hideinitializer */
+#define PWM_CH_5_MASK (0x20UL) /*!< PWM channel 5 mask \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Counter Type Constant Definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define PWM_UP_COUNTER (0UL) /*!< Up counter type */
+#define PWM_DOWN_COUNTER (1UL) /*!< Down counter type */
+#define PWM_UP_DOWN_COUNTER (2UL) /*!< Up-Down counter type */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Aligned Type Constant Definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define PWM_EDGE_ALIGNED (1UL) /*!< PWM working in edge aligned type(down count) */
+#define PWM_CENTER_ALIGNED (2UL) /*!< PWM working in center aligned type */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Output Level Constant Definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define PWM_OUTPUT_NOTHING (0UL) /*!< PWM output nothing */
+#define PWM_OUTPUT_LOW (1UL) /*!< PWM output low */
+#define PWM_OUTPUT_HIGH (2UL) /*!< PWM output high */
+#define PWM_OUTPUT_TOGGLE (3UL) /*!< PWM output toggle */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Trigger Source Select Constant Definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define PWM_TRIGGER_ADC_EVEN_ZERO_POINT (0UL) /*!< PWM trigger ADC while counter of even channel matches zero point */
+#define PWM_TRIGGER_ADC_EVEN_PERIOD_POINT (1UL) /*!< PWM trigger ADC while counter of even channel matches period point */
+#define PWM_TRIGGER_ADC_EVEN_ZERO_OR_PERIOD_POINT (2UL) /*!< PWM trigger ADC while counter of even channel matches zero or period point */
+#define PWM_TRIGGER_ADC_EVEN_COMPARE_UP_COUNT_POINT (3UL) /*!< PWM trigger ADC while counter of even channel matches up count to comparator point */
+#define PWM_TRIGGER_ADC_EVEN_COMPARE_DOWN_COUNT_POINT (4UL) /*!< PWM trigger ADC while counter of even channel matches down count to comparator point */
+#define PWM_TRIGGER_ADC_ODD_ZERO_POINT (5UL) /*!< PWM trigger ADC while counter of odd channel matches zero point */
+#define PWM_TRIGGER_ADC_ODD_PERIOD_POINT (6UL) /*!< PWM trigger ADC while counter of odd channel matches period point */
+#define PWM_TRIGGER_ADC_ODD_ZERO_OR_PERIOD_POINT (7UL) /*!< PWM trigger ADC while counter of odd channel matches zero or period point */
+#define PWM_TRIGGER_ADC_ODD_COMPARE_UP_COUNT_POINT (8UL) /*!< PWM trigger ADC while counter of odd channel matches up count to comparator point */
+#define PWM_TRIGGER_ADC_ODD_COMPARE_DOWN_COUNT_POINT (9UL) /*!< PWM trigger ADC while counter of odd channel matches down count to comparator point */
+#define PWM_TRIGGER_ADC_CH_0_FREE_COMPARE_UP_COUNT_POINT (10UL) /*!< PWM trigger ADC while counter of channel 0 matches up count to free comparator point */
+#define PWM_TRIGGER_ADC_CH_0_FREE_COMPARE_DOWN_COUNT_POINT (11UL) /*!< PWM trigger ADC while counter of channel 0 matches down count to free comparator point */
+#define PWM_TRIGGER_ADC_CH_2_FREE_COMPARE_UP_COUNT_POINT (12UL) /*!< PWM trigger ADC while counter of channel 2 matches up count to free comparator point */
+#define PWM_TRIGGER_ADC_CH_2_FREE_COMPARE_DOWN_COUNT_POINT (13UL) /*!< PWM trigger ADC while counter of channel 2 matches down count to free comparator point */
+#define PWM_TRIGGER_ADC_CH_4_FREE_COMPARE_UP_COUNT_POINT (14UL) /*!< PWM trigger ADC while counter of channel 4 matches up count to free comparator point */
+#define PWM_TRIGGER_ADC_CH_4_FREE_COMPARE_DOWN_COUNT_POINT (15UL) /*!< PWM trigger ADC while counter of channel 4 matches down count to free comparator point */
+
+#define PWM_TRIGGER_DAC_ZERO_POINT (0x1UL) /*!< PWM trigger ADC while counter down count to 0 \hideinitializer */
+#define PWM_TRIGGER_DAC_PERIOD_POINT (0x100UL) /*!< PWM trigger ADC while counter matches (PERIOD + 1) \hideinitializer */
+#define PWM_TRIGGER_DAC_COMPARE_UP_COUNT_POINT (0x10000UL) /*!< PWM trigger ADC while counter up count to CMPDAT \hideinitializer */
+#define PWM_TRIGGER_DAC_COMPARE_DOWN_COUNT_POINT (0x1000000UL) /*!< PWM trigger ADC while counter down count to CMPDAT \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Fail brake Control Constant Definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define PWM_FB_EDGE_ACMP0 (PWM_BRKCTL0_1_CPO0EBEN_Msk) /*!< Comparator 0 as edge-detect fault brake source */
+#define PWM_FB_EDGE_ACMP1 (PWM_BRKCTL0_1_CPO1EBEN_Msk) /*!< Comparator 1 as edge-detect fault brake source */
+#define PWM_FB_EDGE_BKP0 (PWM_BRKCTL0_1_BRKP0EEN_Msk) /*!< BKP0 pin as edge-detect fault brake source */
+#define PWM_FB_EDGE_BKP1 (PWM_BRKCTL0_1_BRKP1EEN_Msk) /*!< BKP1 pin as edge-detect fault brake source */
+#define PWM_FB_EDGE_SYS_CSS (PWM_BRKCTL0_1_SYSEBEN_Msk | PWM_FAILBRK_CSSBRKEN_Msk) /*!< System fail condition: clock security system detection as edge-detect fault brake source */
+#define PWM_FB_EDGE_SYS_BOD (PWM_BRKCTL0_1_SYSEBEN_Msk | PWM_FAILBRK_BODBRKEN_Msk) /*!< System fail condition: brown-out detection as edge-detect fault brake source */
+#define PWM_FB_EDGE_SYS_RAM (PWM_BRKCTL0_1_SYSEBEN_Msk | PWM_FAILBRK_RAMBRKEN_Msk) /*!< System fail condition: SRAM parity error detection as edge-detect fault brake source */
+#define PWM_FB_EDGE_SYS_COR (PWM_BRKCTL0_1_SYSEBEN_Msk | PWM_FAILBRK_CORBRKEN_Msk) /*!< System fail condition: core lockup detection as edge-detect fault brake source */
+
+#define PWM_FB_LEVEL_ACMP0 (PWM_BRKCTL0_1_CPO0LBEN_Msk) /*!< Comparator 0 as level-detect fault brake source */
+#define PWM_FB_LEVEL_ACMP1 (PWM_BRKCTL0_1_CPO1LBEN_Msk) /*!< Comparator 1 as level-detect fault brake source */
+#define PWM_FB_LEVEL_BKP0 (PWM_BRKCTL0_1_BRKP0LEN_Msk) /*!< BKP0 pin as level-detect fault brake source */
+#define PWM_FB_LEVEL_BKP1 (PWM_BRKCTL0_1_BRKP1LEN_Msk) /*!< BKP1 pin as level-detect fault brake source */
+#define PWM_FB_LEVEL_SYS_CSS (PWM_BRKCTL0_1_SYSLBEN_Msk | PWM_FAILBRK_CSSBRKEN_Msk) /*!< System fail condition: clock security system detection as level-detect fault brake source */
+#define PWM_FB_LEVEL_SYS_BOD (PWM_BRKCTL0_1_SYSLBEN_Msk | PWM_FAILBRK_BODBRKEN_Msk) /*!< System fail condition: brown-out detection as level-detect fault brake source */
+#define PWM_FB_LEVEL_SYS_RAM (PWM_BRKCTL0_1_SYSLBEN_Msk | PWM_FAILBRK_RAMBRKEN_Msk) /*!< System fail condition: SRAM parity error detection as level-detect fault brake source */
+#define PWM_FB_LEVEL_SYS_COR (PWM_BRKCTL0_1_SYSLBEN_Msk | PWM_FAILBRK_CORBRKEN_Msk) /*!< System fail condition: core lockup detection as level-detect fault brake source */
+
+#define PWM_FB_EDGE (0UL) /*!< edge-detect fault brake */
+#define PWM_FB_LEVEL (8UL) /*!< level-detect fault brake */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Capture Control Constant Definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define PWM_CAPTURE_INT_RISING_LATCH (1UL) /*!< PWM capture interrupt if channel has rising transition */
+#define PWM_CAPTURE_INT_FALLING_LATCH (0x100UL) /*!< PWM capture interrupt if channel has falling transition */
+
+#define PWM_CAPTURE_PDMA_RISING_LATCH (0x2UL) /*!< PWM capture rising latched data transfer by PDMA */
+#define PWM_CAPTURE_PDMA_FALLING_LATCH (0x4UL) /*!< PWM capture falling latched data transfer by PDMA */
+#define PWM_CAPTURE_PDMA_RISING_FALLING_LATCH (0x6UL) /*!< PWM capture rising and falling latched data transfer by PDMA */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Duty Interrupt Type Constant Definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define PWM_DUTY_INT_DOWN_COUNT_MATCH_CMP (PWM_INTEN0_CMPDIEN0_Msk) /*!< PWM duty interrupt triggered if down count match comparator */
+#define PWM_DUTY_INT_UP_COUNT_MATCH_CMP (PWM_INTEN0_CMPUIEN0_Msk) /*!< PWM duty interrupt triggered if up down match comparator */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Interrupt Flag Accumulator Constant Definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define PWM_IFA_EVEN_ZERO_POINT (0UL) /*!< PWM counter equal to zero in even channel \hideinitializer */
+#define PWM_IFA_EVEN_PERIOD_POINT (1UL) /*!< PWM counter equal to period in even channel \hideinitializer */
+#define PWM_IFA_EVEN_COMPARE_UP_COUNT_POINT (2UL) /*!< PWM counter up count to comparator value in even channel \hideinitializer */
+#define PWM_IFA_EVEN_COMPARE_DOWN_COUNT_POINT (3UL) /*!< PWM counter down count to comparator value in even channel \hideinitializer */
+#define PWM_IFA_ODD_ZERO_POINT (4UL) /*!< PWM counter equal to zero in odd channel \hideinitializer */
+#define PWM_IFA_ODD_PERIOD_POINT (5UL) /*!< PWM counter equal to period in odd channel \hideinitializer */
+#define PWM_IFA_ODD_COMPARE_UP_COUNT_POINT (6UL) /*!< PWM counter up count to comparator value in odd channel \hideinitializer */
+#define PWM_IFA_ODD_COMPARE_DOWN_COUNT_POINT (7UL) /*!< PWM counter down count to comparator value in odd channel \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Load Mode Constant Definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define PWM_LOAD_MODE_IMMEDIATE (PWM_CTL0_IMMLDEN0_Msk) /*!< PWM immediately load mode \hideinitializer */
+#define PWM_LOAD_MODE_WINDOW (PWM_CTL0_WINLDEN0_Msk) /*!< PWM window load mode \hideinitializer */
+#define PWM_LOAD_MODE_CENTER (PWM_CTL0_CTRLD0_Msk) /*!< PWM center load mode \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Synchronize Control Constant Definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define PWM_SYNC_OUT_FROM_SYNCIN_SWSYNC (0UL) /*!< Synchronize source from SYNC_IN or SWSYNC \hideinitializer */
+#define PWM_SYNC_OUT_FROM_COUNT_TO_ZERO (1UL) /*!< Synchronize source from counter equal to 0 \hideinitializer */
+#define PWM_SYNC_OUT_FROM_COUNT_TO_COMPARATOR (2UL) /*!< Synchronize source from counter equal to CMPDAT1, CMPDAT3, CMPDAT5 \hideinitializer */
+#define PWM_SYNC_OUT_DISABLE (3UL) /*!< SYNC_OUT will not be generated \hideinitializer */
+#define PWM_PHS_DIR_DECREMENT (0UL) /*!< PWM counter count decrement \hideinitializer */
+#define PWM_PHS_DIR_INCREMENT (1UL) /*!< PWM counter count increment \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Noise Filter Clock Divide Select Constant Definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define PWM_NF_CLK_DIV_1 (0UL) /*!< Noise filter clock is HCLK divide by 1 \hideinitializer */
+#define PWM_NF_CLK_DIV_2 (1UL) /*!< Noise filter clock is HCLK divide by 2 \hideinitializer */
+#define PWM_NF_CLK_DIV_4 (2UL) /*!< Noise filter clock is HCLK divide by 4 \hideinitializer */
+#define PWM_NF_CLK_DIV_8 (3UL) /*!< Noise filter clock is HCLK divide by 8 \hideinitializer */
+#define PWM_NF_CLK_DIV_16 (4UL) /*!< Noise filter clock is HCLK divide by 16 \hideinitializer */
+#define PWM_NF_CLK_DIV_32 (5UL) /*!< Noise filter clock is HCLK divide by 32 \hideinitializer */
+#define PWM_NF_CLK_DIV_64 (6UL) /*!< Noise filter clock is HCLK divide by 64 \hideinitializer */
+#define PWM_NF_CLK_DIV_128 (7UL) /*!< Noise filter clock is HCLK divide by 128 \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Clock Source Select Constant Definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define PWM_CLKSRC_PWM_CLK (0UL) /*!< PWM Clock source selects to PWM0_CLK or PWM1_CLK \hideinitializer */
+#define PWM_CLKSRC_TIMER0 (1UL) /*!< PWM Clock source selects to TIMER0 overflow \hideinitializer */
+#define PWM_CLKSRC_TIMER1 (2UL) /*!< PWM Clock source selects to TIMER1 overflow \hideinitializer */
+#define PWM_CLKSRC_TIMER2 (3UL) /*!< PWM Clock source selects to TIMER2 overflow \hideinitializer */
+#define PWM_CLKSRC_TIMER3 (4UL) /*!< PWM Clock source selects to TIMER3 overflow \hideinitializer */
+
+
+/*@}*/ /* end of group PWM_EXPORTED_CONSTANTS */
+
+
+/** @addtogroup PWM_EXPORTED_FUNCTIONS PWM Exported Functions
+ @{
+*/
+
+/**
+ * @brief This macro enable complementary mode
+ * @param[in] pwm The pointer of the specified PWM module
+ * @return None
+ * @details This macro is used to enable complementary mode of PWM module.
+ * \hideinitializer
+ */
+#define PWM_ENABLE_COMPLEMENTARY_MODE(pwm) ((pwm)->CTL1 = (pwm)->CTL1 | PWM_CTL1_OUTMODEn_Msk)
+
+/**
+ * @brief This macro disable complementary mode, and enable independent mode.
+ * @param[in] pwm The pointer of the specified PWM module
+ * @return None
+ * @details This macro is used to disable complementary mode of PWM module.
+ * \hideinitializer
+ */
+#define PWM_DISABLE_COMPLEMENTARY_MODE(pwm) ((pwm)->CTL1 = (pwm)->CTL1 & ~PWM_CTL1_OUTMODEn_Msk)
+
+/**
+ * @brief This macro enable group mode
+ * @param[in] pwm The pointer of the specified PWM module
+ * @return None
+ * @details This macro is used to enable group mode of PWM module.
+ * \hideinitializer
+ */
+#define PWM_ENABLE_GROUP_MODE(pwm) ((pwm)->CTL0 = (pwm)->CTL0 | PWM_CTL0_GROUPEN_Msk)
+
+/**
+ * @brief This macro disable group mode
+ * @param[in] pwm The pointer of the specified PWM module
+ * @return None
+ * @details This macro is used to disable group mode of PWM module.
+ * \hideinitializer
+ */
+#define PWM_DISABLE_GROUP_MODE(pwm) ((pwm)->CTL0 = (pwm)->CTL0 & ~PWM_CTL0_GROUPEN_Msk)
+
+/**
+ * @brief Enable timer synchronous mode of specified channel(s)
+ * @param[in] pwm The pointer of the specified PWM module
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
+ * Bit 0 represents channel 0, bit 1 represents channel 1...
+ * @return None
+ * @details This macro is used to enable timer synchronous mode of specified channel(s).
+ * \hideinitializer
+ */
+#define PWM_ENABLE_TIMER_SYNC(pwm, u32ChannelMask) ((pwm)->SSCTL |= (u32ChannelMask))
+
+/**
+ * @brief Disable timer synchronous mode of specified channel(s)
+ * @param[in] pwm The pointer of the specified PWM module
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
+ * Bit 0 represents channel 0, bit 1 represents channel 1...
+ * @return None
+ * @details This macro is used to disable timer synchronous mode of specified channel(s).
+ * \hideinitializer
+ */
+#define PWM_DISABLE_TIMER_SYNC(pwm, u32ChannelMask) \
+ do{ \
+ int i;\
+ for(i = 0; i < 6; i++) { \
+ if((u32ChannelMask) & (1 << i)) \
+ (pwm)->SSCTL &= ~(1UL << i); \
+ } \
+ }while(0)
+
+/**
+ * @brief This macro enable output inverter of specified channel(s)
+ * @param[in] pwm The pointer of the specified PWM module
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
+ * Bit 0 represents channel 0, bit 1 represents channel 1...
+ * @return None
+ * @details This macro is used to enable output inverter of specified channel(s).
+ * \hideinitializer
+ */
+#define PWM_ENABLE_OUTPUT_INVERTER(pwm, u32ChannelMask) ((pwm)->POLCTL = (u32ChannelMask))
+
+/**
+ * @brief This macro get captured rising data
+ * @param[in] pwm The pointer of the specified PWM module
+ * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
+ * @return None
+ * @details This macro is used to get captured rising data of specified channel.
+ * \hideinitializer
+ */
+#define PWM_GET_CAPTURE_RISING_DATA(pwm, u32ChannelNum) (*(__IO uint32_t *) (&((pwm)->RCAPDAT0) + 2 * (u32ChannelNum)))
+
+/**
+ * @brief This macro get captured falling data
+ * @param[in] pwm The pointer of the specified PWM module
+ * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
+ * @return None
+ * @details This macro is used to get captured falling data of specified channel.
+ * \hideinitializer
+ */
+#define PWM_GET_CAPTURE_FALLING_DATA(pwm, u32ChannelNum) (*(__IO uint32_t *) (&((pwm)->FCAPDAT0) + 2 * (u32ChannelNum)))
+
+/**
+ * @brief This macro mask output logic to high or low
+ * @param[in] pwm The pointer of the specified PWM module
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
+ * Bit 0 represents channel 0, bit 1 represents channel 1...
+ * @param[in] u32LevelMask Output logic to high or low
+ * @return None
+ * @details This macro is used to mask output logic to high or low of specified channel(s).
+ * @note If u32ChannelMask parameter is 0, then mask function will be disabled.
+ * \hideinitializer
+ */
+#define PWM_MASK_OUTPUT(pwm, u32ChannelMask, u32LevelMask) \
+ { \
+ (pwm)->MSKEN = (u32ChannelMask); \
+ (pwm)->MSK = (u32LevelMask); \
+ }
+
+/**
+ * @brief This macro set the prescaler of the selected channel
+ * @param[in] pwm The pointer of the specified PWM module
+ * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
+ * @param[in] u32Prescaler Clock prescaler of specified channel. Valid values are between 1 ~ 0xFFF
+ * @return None
+ * @details This macro is used to set the prescaler of specified channel.
+ * @note Every even channel N, and channel (N + 1) share a prescaler. So if channel 0 prescaler changed,
+ * channel 1 will also be affected.
+ * \hideinitializer
+ */
+#define PWM_SET_PRESCALER(pwm, u32ChannelNum, u32Prescaler) (*(__IO uint32_t *) (&((pwm)->CLKPSC0_1) + ((u32ChannelNum) >> 1)) = (u32Prescaler))
+
+/**
+ * @brief This macro set the comparator of the selected channel
+ * @param[in] pwm The pointer of the specified PWM module
+ * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
+ * @param[in] u32CMR Comparator of specified channel. Valid values are between 0~0xFFFF
+ * @return None
+ * @details This macro is used to set the comparator of specified channel.
+ * @note This new setting will take effect on next PWM period.
+ * \hideinitializer
+ */
+#define PWM_SET_CMR(pwm, u32ChannelNum, u32CMR) ((pwm)->CMPDAT[(u32ChannelNum)]= (u32CMR))
+
+/**
+ * @brief This macro set the free trigger comparator of the selected channel
+ * @param[in] pwm The pointer of the specified PWM module
+ * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
+ * @param[in] u32FTCMR Free trigger comparator of specified channel. Valid values are between 0~0xFFFF
+ * @return None
+ * @details This macro is used to set the free trigger comparator of specified channel.
+ * @note This new setting will take effect on next PWM period.
+ * \hideinitializer
+ */
+#define PWM_SET_FTCMR(pwm, u32ChannelNum, u32FTCMR) (*(__IO uint32_t *) (&((pwm)->FTCMPDAT0_1) + ((u32ChannelNum) >> 1)) = (u32FTCMR))
+
+/**
+ * @brief This macro set the period of the selected channel
+ * @param[in] pwm The pointer of the specified PWM module
+ * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
+ * @param[in] u32CNR Period of specified channel. Valid values are between 0~0xFFFF
+ * @return None
+ * @details This macro is used to set the period of specified channel.
+ * @note This new setting will take effect on next PWM period.
+ * @note PWM counter will stop if period length set to 0.
+ * \hideinitializer
+ */
+#define PWM_SET_CNR(pwm, u32ChannelNum, u32CNR) ((pwm)->PERIOD[(u32ChannelNum)] = (u32CNR))
+
+/**
+ * @brief This macro set the PWM aligned type
+ * @param[in] pwm The pointer of the specified PWM module
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
+ * Bit 0 represents channel 0, bit 1 represents channel 1...
+ * @param[in] u32AlignedType PWM aligned type, valid values are:
+ * - \ref PWM_EDGE_ALIGNED
+ * - \ref PWM_CENTER_ALIGNED
+ * @return None
+ * @details This macro is used to set the PWM aligned type of specified channel(s).
+ * \hideinitializer
+ */
+#define PWM_SET_ALIGNED_TYPE(pwm, u32ChannelMask, u32AlignedType) \
+ do{ \
+ int i; \
+ for(i = 0; i < 6; i++) { \
+ if((u32ChannelMask) & (1 << i)) \
+ (pwm)->CTL1 = (((pwm)->CTL1 & ~(3UL << (2 * i))) | ((u32AlignedType) << ( 2 * i))); \
+ } \
+ }while(0)
+
+/**
+ * @brief Set load window of window loading mode for specified channel(s)
+ * @param[in] pwm The pointer of the specified PWM module
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
+ * Bit 0 represents channel 0, bit 1 represents channel 1...
+ * @return None
+ * @details This macro is used to set load window of window loading mode for specified channel(s).
+ * \hideinitializer
+ */
+#define PWM_SET_LOAD_WINDOW(pwm, u32ChannelMask) ((pwm)->LOAD |= (u32ChannelMask))
+
+/**
+ * @brief Trigger synchronous event from specified channel(s)
+ * @param[in] pwm The pointer of the specified PWM module
+ * @param[in] u32ChannelNum PWM channel number. Valid values are 0, 2, 4
+ * Bit 0 represents channel 0, bit 1 represents channel 2 and bit 2 represents channel 4
+ * @return None
+ * @details This macro is used to trigger synchronous event from specified channel(s).
+ * \hideinitializer
+ */
+#define PWM_TRIGGER_SYNC(pwm, u32ChannelNum) ((pwm)->SWSYNC |= (1 << ((u32ChannelNum) >> 1)))
+
+/**
+ * @brief Clear counter of specified channel(s)
+ * @param[in] pwm The pointer of the specified PWM module
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
+ * Bit 0 represents channel 0, bit 1 represents channel 1...
+ * @return None
+ * @details This macro is used to clear counter of specified channel(s).
+ * \hideinitializer
+ */
+#define PWM_CLR_COUNTER(pwm, u32ChannelMask) ((pwm)->CNTCLR |= (u32ChannelMask))
+
+/**
+ * @brief Set output level at zero, compare up, period(center) and compare down of specified channel(s)
+ * @param[in] pwm The pointer of the specified PWM module
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
+ * Bit 0 represents channel 0, bit 1 represents channel 1...
+ * @param[in] u32ZeroLevel output level at zero point, valid values are:
+ * - \ref PWM_OUTPUT_NOTHING
+ * - \ref PWM_OUTPUT_LOW
+ * - \ref PWM_OUTPUT_HIGH
+ * - \ref PWM_OUTPUT_TOGGLE
+ * @param[in] u32CmpUpLevel output level at compare up point, valid values are:
+ * - \ref PWM_OUTPUT_NOTHING
+ * - \ref PWM_OUTPUT_LOW
+ * - \ref PWM_OUTPUT_HIGH
+ * - \ref PWM_OUTPUT_TOGGLE
+ * @param[in] u32PeriodLevel output level at period(center) point, valid values are:
+ * - \ref PWM_OUTPUT_NOTHING
+ * - \ref PWM_OUTPUT_LOW
+ * - \ref PWM_OUTPUT_HIGH
+ * - \ref PWM_OUTPUT_TOGGLE
+ * @param[in] u32CmpDownLevel output level at compare down point, valid values are:
+ * - \ref PWM_OUTPUT_NOTHING
+ * - \ref PWM_OUTPUT_LOW
+ * - \ref PWM_OUTPUT_HIGH
+ * - \ref PWM_OUTPUT_TOGGLE
+ * @return None
+ * @details This macro is used to Set output level at zero, compare up, period(center) and compare down of specified channel(s).
+ * \hideinitializer
+ */
+#define PWM_SET_OUTPUT_LEVEL(pwm, u32ChannelMask, u32ZeroLevel, u32CmpUpLevel, u32PeriodLevel, u32CmpDownLevel) \
+ do{ \
+ int i; \
+ for(i = 0; i < 6; i++) { \
+ if((u32ChannelMask) & (1 << i)) { \
+ (pwm)->WGCTL0 = (((pwm)->WGCTL0 & ~(3UL << (2 * i))) | ((u32ZeroLevel) << (2 * i))); \
+ (pwm)->WGCTL0 = (((pwm)->WGCTL0 & ~(3UL << (PWM_WGCTL0_PRDPCTLn_Pos + (2 * i)))) | ((u32PeriodLevel) << (PWM_WGCTL0_PRDPCTLn_Pos + (2 * i)))); \
+ (pwm)->WGCTL1 = (((pwm)->WGCTL1 & ~(3UL << (2 * i))) | ((u32CmpUpLevel) << (2 * i))); \
+ (pwm)->WGCTL1 = (((pwm)->WGCTL1 & ~(3UL << (PWM_WGCTL1_CMPDCTLn_Pos + (2 * i)))) | ((u32CmpDownLevel) << (PWM_WGCTL1_CMPDCTLn_Pos + (2 * i)))); \
+ } \
+ } \
+ }while(0)
+
+/**
+ * @brief Trigger brake event from specified channel(s)
+ * @param[in] pwm The pointer of the specified PWM module
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
+ * Bit 0 represents channel 0, bit 1 represents channel 2 and bit 2 represents channel 4
+ * @param[in] u32BrakeType Type of brake trigger. PWM_FB_EDGE of this macro is only supported in M45xD/M45xC.
+ * - \ref PWM_FB_EDGE
+ * - \ref PWM_FB_LEVEL
+ * @return None
+ * @details This macro is used to trigger brake event from specified channel(s).
+ * \hideinitializer
+ */
+#define PWM_TRIGGER_BRAKE(pwm, u32ChannelMask, u32BrakeType) ((pwm)->SWBRK |= ((u32ChannelMask) << (u32BrakeType)))
+
+/**
+ * @brief Set Dead zone clock source
+ * @param[in] pwm The pointer of the specified PWM module
+ * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
+ * @param[in] u32AfterPrescaler Dead zone clock source is from prescaler output. Valid values are TRUE (after prescaler) or FALSE (before prescaler).
+ * @return None
+ * @details This macro is used to set Dead zone clock source. Every two channels share the same setting.
+ * @note The write-protection function should be disabled before using this function.
+ * @note This function is only supported in M45xD/M45xC.
+ * \hideinitializer
+ */
+#define PWM_SET_DEADZONE_CLK_SRC(pwm, u32ChannelNum, u32AfterPrescaler) \
+ (*(__IO uint32_t *) (&((pwm)->DTCTL0_1) + ((u32ChannelNum) >> 1)) = (*(__IO uint32_t *) (&((pwm)->DTCTL0_1) + ((u32ChannelNum) >> 1)) & ~PWM_DTCTL0_1_DTCKSEL_Msk) | \
+ ((u32AfterPrescaler) << PWM_DTCTL0_1_DTCKSEL_Pos))
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Define PWM functions prototype */
+/*---------------------------------------------------------------------------------------------------------*/
+uint32_t PWM_ConfigCaptureChannel(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32UnitTimeNsec, uint32_t u32CaptureEdge);
+uint32_t PWM_ConfigOutputChannel(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Frequency, uint32_t u32DutyCycle);
+void PWM_Start(PWM_T *pwm, uint32_t u32ChannelMask);
+void PWM_Stop(PWM_T *pwm, uint32_t u32ChannelMask);
+void PWM_ForceStop(PWM_T *pwm, uint32_t u32ChannelMask);
+void PWM_EnableADCTrigger(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Condition);
+void PWM_DisableADCTrigger(PWM_T *pwm, uint32_t u32ChannelNum);
+void PWM_ClearADCTriggerFlag(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Condition);
+uint32_t PWM_GetADCTriggerFlag(PWM_T *pwm, uint32_t u32ChannelNum);
+void PWM_EnableDACTrigger(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Condition);
+void PWM_DisableDACTrigger(PWM_T *pwm, uint32_t u32ChannelNum);
+void PWM_ClearDACTriggerFlag(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Condition);
+uint32_t PWM_GetDACTriggerFlag(PWM_T *pwm, uint32_t u32ChannelNum);
+void PWM_EnableFaultBrake(PWM_T *pwm, uint32_t u32ChannelMask, uint32_t u32LevelMask, uint32_t u32BrakeSource);
+void PWM_EnableCapture(PWM_T *pwm, uint32_t u32ChannelMask);
+void PWM_DisableCapture(PWM_T *pwm, uint32_t u32ChannelMask);
+void PWM_EnableOutput(PWM_T *pwm, uint32_t u32ChannelMask);
+void PWM_DisableOutput(PWM_T *pwm, uint32_t u32ChannelMask);
+void PWM_EnablePDMA(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32RisingFirst, uint32_t u32Mode);
+void PWM_DisablePDMA(PWM_T *pwm, uint32_t u32ChannelNum);
+void PWM_EnableDeadZone(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Duration);
+void PWM_DisableDeadZone(PWM_T *pwm, uint32_t u32ChannelNum);
+void PWM_EnableCaptureInt(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Edge);
+void PWM_DisableCaptureInt(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Edge);
+void PWM_ClearCaptureIntFlag(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Edge);
+uint32_t PWM_GetCaptureIntFlag(PWM_T *pwm, uint32_t u32ChannelNum);
+void PWM_EnableDutyInt(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32IntDutyType);
+void PWM_DisableDutyInt(PWM_T *pwm, uint32_t u32ChannelNum);
+void PWM_ClearDutyIntFlag(PWM_T *pwm, uint32_t u32ChannelNum);
+uint32_t PWM_GetDutyIntFlag(PWM_T *pwm, uint32_t u32ChannelNum);
+void PWM_EnableFaultBrakeInt(PWM_T *pwm, uint32_t u32BrakeSource);
+void PWM_DisableFaultBrakeInt(PWM_T *pwm, uint32_t u32BrakeSource);
+void PWM_ClearFaultBrakeIntFlag(PWM_T *pwm, uint32_t u32BrakeSource);
+uint32_t PWM_GetFaultBrakeIntFlag(PWM_T *pwm, uint32_t u32BrakeSource);
+void PWM_EnablePeriodInt(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32IntPeriodType);
+void PWM_DisablePeriodInt(PWM_T *pwm, uint32_t u32ChannelNum);
+void PWM_ClearPeriodIntFlag(PWM_T *pwm, uint32_t u32ChannelNum);
+uint32_t PWM_GetPeriodIntFlag(PWM_T *pwm, uint32_t u32ChannelNum);
+void PWM_EnableZeroInt(PWM_T *pwm, uint32_t u32ChannelNum);
+void PWM_DisableZeroInt(PWM_T *pwm, uint32_t u32ChannelNum);
+void PWM_ClearZeroIntFlag(PWM_T *pwm, uint32_t u32ChannelNum);
+uint32_t PWM_GetZeroIntFlag(PWM_T *pwm, uint32_t u32ChannelNum);
+void PWM_EnableAcc(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32IntFlagCnt, uint32_t u32IntAccSrc);
+void PWM_DisableAcc(PWM_T *pwm, uint32_t u32ChannelNum);
+void PWM_EnableAccInt(PWM_T *pwm, uint32_t u32ChannelNum);
+void PWM_DisableAccInt(PWM_T *pwm, uint32_t u32ChannelNum);
+void PWM_ClearAccInt(PWM_T *pwm, uint32_t u32ChannelNum);
+uint32_t PWM_GetAccInt(PWM_T *pwm, uint32_t u32ChannelNum);
+void PWM_ClearFTDutyIntFlag(PWM_T *pwm, uint32_t u32ChannelNum);
+uint32_t PWM_GetFTDutyIntFlag(PWM_T *pwm, uint32_t u32ChannelNum);
+void PWM_EnableLoadMode(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32LoadMode);
+void PWM_DisableLoadMode(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32LoadMode);
+void PWM_ConfigSyncPhase(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32SyncSrc, uint32_t u32Direction, uint32_t u32StartPhase);
+void PWM_EnableSyncPhase(PWM_T *pwm, uint32_t u32ChannelMask);
+void PWM_DisableSyncPhase(PWM_T *pwm, uint32_t u32ChannelMask);
+void PWM_EnableSyncNoiseFilter(PWM_T *pwm, uint32_t u32ClkCnt, uint32_t u32ClkDivSel);
+void PWM_DisableSyncNoiseFilter(PWM_T *pwm);
+void PWM_EnableSyncPinInverse(PWM_T *pwm);
+void PWM_DisableSyncPinInverse(PWM_T *pwm);
+void PWM_SetClockSource(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32ClkSrcSel);
+void PWM_EnableBrakeNoiseFilter(PWM_T *pwm, uint32_t u32BrakePinNum, uint32_t u32ClkCnt, uint32_t u32ClkDivSel);
+void PWM_DisableBrakeNoiseFilter(PWM_T *pwm, uint32_t u32BrakePinNum);
+void PWM_EnableBrakePinInverse(PWM_T *pwm, uint32_t u32BrakePinNum);
+void PWM_DisableBrakePinInverse(PWM_T *pwm, uint32_t u32BrakePinNum);
+void PWM_SetBrakePinSource(PWM_T *pwm, uint32_t u32BrakePinNum, uint32_t u32SelAnotherModule);
+uint32_t PWM_GetWrapAroundFlag(PWM_T *pwm, uint32_t u32ChannelNum);
+void PWM_ClearWrapAroundFlag(PWM_T *pwm, uint32_t u32ChannelNum);
+
+
+/*@}*/ /* end of group PWM_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group PWM_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif //__PWM_H__
+
+/*** (C) COPYRIGHT 2014~2015 Nuvoton Technology Corp. ***/
diff --git a/bsp/nuvoton_m451/Libraries/StdDriver/inc/rtc.h b/bsp/nuvoton_m451/Libraries/StdDriver/inc/rtc.h
new file mode 100644
index 0000000000000000000000000000000000000000..fd0c44222d699295644fea1d7200a74d4aa8d9d3
--- /dev/null
+++ b/bsp/nuvoton_m451/Libraries/StdDriver/inc/rtc.h
@@ -0,0 +1,272 @@
+/**************************************************************************//**
+ * @file rtc.h
+ * @version V3.00
+ * $Revision: 10 $
+ * $Date: 15/08/11 10:26a $
+ * @brief M451 series RTC driver header file
+ *
+ * @note
+ * Copyright (C) 2013~2015 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __RTC_H__
+#define __RTC_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup Standard_Driver Standard Driver
+ @{
+*/
+
+/** @addtogroup RTC_Driver RTC Driver
+ @{
+*/
+
+/** @addtogroup RTC_EXPORTED_CONSTANTS RTC Exported Constants
+ @{
+*/
+/*---------------------------------------------------------------------------------------------------------*/
+/* RTC Initial Keyword Constant Definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define RTC_INIT_KEY 0xA5EB1357UL /*!< RTC Initiation Key to make RTC leaving reset state */
+#define RTC_WRITE_KEY 0x0000A965UL /*!< RTC Register Access Enable Key to enable RTC read/write accessible and kept 1024 RTC clock */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* RTC Time Attribute Constant Definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define RTC_CLOCK_12 0 /*!< RTC as 12-hour time scale with AM and PM indication */
+#define RTC_CLOCK_24 1 /*!< RTC as 24-hour time scale */
+#define RTC_AM 1 /*!< RTC as AM indication */
+#define RTC_PM 2 /*!< RTC as PM indication */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* RTC Tick Period Constant Definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define RTC_TICK_1_SEC 0x0UL /*!< RTC time tick period is 1 second */
+#define RTC_TICK_1_2_SEC 0x1UL /*!< RTC time tick period is 1/2 second */
+#define RTC_TICK_1_4_SEC 0x2UL /*!< RTC time tick period is 1/4 second */
+#define RTC_TICK_1_8_SEC 0x3UL /*!< RTC time tick period is 1/8 second */
+#define RTC_TICK_1_16_SEC 0x4UL /*!< RTC time tick period is 1/16 second */
+#define RTC_TICK_1_32_SEC 0x5UL /*!< RTC time tick period is 1/32 second */
+#define RTC_TICK_1_64_SEC 0x6UL /*!< RTC time tick period is 1/64 second */
+#define RTC_TICK_1_128_SEC 0x7UL /*!< RTC time tick period is 1/128 second */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* RTC Day of Week Constant Definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define RTC_SUNDAY 0x0UL /*!< Day of the Week is Sunday */
+#define RTC_MONDAY 0x1UL /*!< Day of the Week is Monday */
+#define RTC_TUESDAY 0x2UL /*!< Day of the Week is Tuesday */
+#define RTC_WEDNESDAY 0x3UL /*!< Day of the Week is Wednesday */
+#define RTC_THURSDAY 0x4UL /*!< Day of the Week is Thursday */
+#define RTC_FRIDAY 0x5UL /*!< Day of the Week is Friday */
+#define RTC_SATURDAY 0x6UL /*!< Day of the Week is Saturday */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* RTC Snooper Detection Mode Constant Definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define RTC_SNOOPER_LOW_LEVEL 0x0UL /*!< Snooper pin detected is low-level trigger */
+#define RTC_SNOOPER_HIGH_LEVEL 0x2UL /*!< Snooper pin detected is high-level trigger */
+#define RTC_SNOOPER_FALLING_EDGE 0x8UL /*!< Snooper pin detected is falling-edge trigger */
+#define RTC_SNOOPER_RISING_EDGE 0xAUL /*!< Snooper pin detected is rising-edge trigger */
+#define RTC_SNOOPER_DETECT_Msk 0xAUL /*!< Snooper pin detected mask bits */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* RTC Miscellaneous Constant Definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define RTC_WAIT_COUNT 0xFFFFFFFF /*!< Initial Time-out Value */
+#define RTC_YEAR2000 2000 /*!< RTC Reference for compute year data */
+#define RTC_FCR_REFERENCE 32761 /*!< RTC Reference for frequency compensation */
+
+/*@}*/ /* end of group RTC_EXPORTED_CONSTANTS */
+
+
+/** @addtogroup RTC_EXPORTED_STRUCTS RTC Exported Structs
+ @{
+*/
+/**
+ * @details RTC define Time Data Struct
+ */
+typedef struct
+{
+ uint32_t u32Year; /*!< Year value */
+ uint32_t u32Month; /*!< Month value */
+ uint32_t u32Day; /*!< Day value */
+ uint32_t u32DayOfWeek; /*!< Day of week value */
+ uint32_t u32Hour; /*!< Hour value */
+ uint32_t u32Minute; /*!< Minute value */
+ uint32_t u32Second; /*!< Second value */
+ uint32_t u32TimeScale; /*!< 12-Hour, 24-Hour */
+ uint32_t u32AmPm; /*!< Only Time Scale select 12-hr used */
+} S_RTC_TIME_DATA_T;
+
+/*@}*/ /* end of group RTC_EXPORTED_STRUCTS */
+
+
+/** @addtogroup RTC_EXPORTED_FUNCTIONS RTC Exported Functions
+ @{
+*/
+
+/**
+ * @brief Indicate is Leap Year or not
+ *
+ * @param None
+ *
+ * @retval 0 This year is not a leap year
+ * @retval 1 This year is a leap year
+ *
+ * @details According to current date, return this year is leap year or not.
+ */
+#define RTC_IS_LEAP_YEAR() (RTC->LEAPYEAR & RTC_LEAPYEAR_LEAPYEAR_Msk ? 1:0)
+
+/**
+ * @brief Clear RTC Alarm Interrupt Flag
+ *
+ * @param None
+ *
+ * @return None
+ *
+ * @details This macro is used to clear RTC alarm interrupt flag.
+ */
+#define RTC_CLEAR_ALARM_INT_FLAG() (RTC->INTSTS = (RTC->INTSTS & ~(RTC_INTSTS_TICKIF_Msk | RTC_INTSTS_SNPDIF_Msk)) | RTC_INTSTS_ALMIF_Msk)
+
+/**
+ * @brief Clear RTC Tick Interrupt Flag
+ *
+ * @param None
+ *
+ * @return None
+ *
+ * @details This macro is used to clear RTC tick interrupt flag.
+ */
+#define RTC_CLEAR_TICK_INT_FLAG() (RTC->INTSTS = (RTC->INTSTS & ~(RTC_INTSTS_ALMIF_Msk | RTC_INTSTS_SNPDIF_Msk)) | RTC_INTSTS_TICKIF_Msk)
+
+/**
+ * @brief Clear RTC Snooper Interrupt Flag
+ *
+ * @param None
+ *
+ * @return None
+ *
+ * @details This macro is used to clear RTC snooper pin interrupt flag.
+ */
+#define RTC_CLEAR_SNOOPER_INT_FLAG() (RTC->INTSTS = (RTC->INTSTS & ~(RTC_INTSTS_ALMIF_Msk | RTC_INTSTS_TICKIF_Msk)) | RTC_INTSTS_SNPDIF_Msk)
+
+/**
+ * @brief Get RTC Alarm Interrupt Flag
+ *
+ * @param None
+ *
+ * @retval 0 RTC alarm interrupt did not occur
+ * @retval 1 RTC alarm interrupt occurred
+ *
+ * @details This macro indicates RTC alarm interrupt occurred or not.
+ */
+#define RTC_GET_ALARM_INT_FLAG() ((RTC->INTSTS & RTC_INTSTS_ALMIF_Msk)? 1:0)
+
+/**
+ * @brief Get RTC Time Tick Interrupt Flag
+ *
+ * @param None
+ *
+ * @retval 0 RTC time tick interrupt did not occur
+ * @retval 1 RTC time tick interrupt occurred
+ *
+ * @details This macro indicates RTC time tick interrupt occurred or not.
+ */
+#define RTC_GET_TICK_INT_FLAG() ((RTC->INTSTS & RTC_INTSTS_TICKIF_Msk)? 1:0)
+
+/**
+ * @brief Get RTC Snooper Interrupt Flag
+ *
+ * @param None
+ *
+ * @retval 0 RTC snooper pin interrupt did not occur
+ * @retval 1 RTC snooper pin interrupt occurred
+ *
+ * @details This macro indicates RTC snooper pin interrupt occurred or not.
+ */
+#define RTC_GET_SNPPOER_INT_FLAG() ((RTC->INTSTS & RTC_INTSTS_SNPDIF_Msk)? 1:0)
+
+/**
+ * @brief Read Spare Register
+ *
+ * @param[in] u32RegNum The spare register number, 0~19.
+ *
+ * @return Spare register content
+ *
+ * @details Read the specify spare register content.
+ * @note The returned value is valid only when SPRRDY(SPRCTL[7] SPR Register Ready) bit is set. \n
+ * And its controlled by RTC Access Enable Register.
+ */
+#define RTC_READ_SPARE_REGISTER(u32RegNum) (RTC->SPR[(u32RegNum)])
+
+/**
+ * @brief Write Spare Register
+ *
+ * @param[in] u32RegNum The spare register number, 0~19.
+ * @param[in] u32RegValue The spare register value.
+ *
+ * @return None
+ *
+ * @details Write specify data to spare register.
+ * @note This macro is effect only when SPRRDY(SPRCTL[7] SPR Register Ready) bit is set. \n
+ * And its controlled by RTC Access Enable Register(RTC_RWEN).
+ */
+#define RTC_WRITE_SPARE_REGISTER(u32RegNum, u32RegValue) (RTC->SPR[(u32RegNum)] = (u32RegValue))
+
+/**
+ * @brief Wait RTC Access Enable
+ *
+ * @param None
+ *
+ * @return None
+ *
+ * @details This function is used to enable the maximum RTC read/write accessible time.
+ */
+static __INLINE void RTC_WaitAccessEnable(void)
+{
+ /* To wait RWENF bit is cleared and enable RWENF bit (Access Enable bit) again */
+ while((RTC->RWEN & RTC_RWEN_RWENF_Msk) == RTC_RWEN_RWENF_Msk);
+ RTC->RWEN = RTC_WRITE_KEY;
+
+ /* To wait RWENF bit is set and user can access the protected-register of RTC from now on */
+ while((RTC->RWEN & RTC_RWEN_RWENF_Msk) == 0x0);
+}
+
+void RTC_Open(S_RTC_TIME_DATA_T *sPt);
+void RTC_Close(void);
+void RTC_32KCalibration(int32_t i32FrequencyX100);
+void RTC_GetDateAndTime(S_RTC_TIME_DATA_T *sPt);
+void RTC_GetAlarmDateAndTime(S_RTC_TIME_DATA_T *sPt);
+void RTC_SetDateAndTime(S_RTC_TIME_DATA_T *sPt);
+void RTC_SetAlarmDateAndTime(S_RTC_TIME_DATA_T *sPt);
+void RTC_SetDate(uint32_t u32Year, uint32_t u32Month, uint32_t u32Day, uint32_t u32DayOfWeek);
+void RTC_SetTime(uint32_t u32Hour, uint32_t u32Minute, uint32_t u32Second, uint32_t u32TimeMode, uint32_t u32AmPm);
+void RTC_SetAlarmDate(uint32_t u32Year, uint32_t u32Month, uint32_t u32Day);
+void RTC_SetAlarmTime(uint32_t u32Hour, uint32_t u32Minute, uint32_t u32Second, uint32_t u32TimeMode, uint32_t u32AmPm);
+uint32_t RTC_GetDayOfWeek(void);
+void RTC_SetTickPeriod(uint32_t u32TickSelection);
+void RTC_EnableInt(uint32_t u32IntFlagMask);
+void RTC_DisableInt(uint32_t u32IntFlagMask);
+void RTC_EnableSpareAccess(void);
+void RTC_DisableSpareRegister(void);
+void RTC_EnableSnooperDetection(uint32_t u32PinCondition);
+void RTC_DisableSnooperDetection(void);
+
+/*@}*/ /* end of group RTC_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group RTC_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif //__RTC_H__
+
+/*** (C) COPYRIGHT 2013~2015 Nuvoton Technology Corp. ***/
diff --git a/bsp/nuvoton_m451/Libraries/StdDriver/inc/sc.h b/bsp/nuvoton_m451/Libraries/StdDriver/inc/sc.h
new file mode 100644
index 0000000000000000000000000000000000000000..295e872110b3d3eaff4df08f62118d5f0c913630
--- /dev/null
+++ b/bsp/nuvoton_m451/Libraries/StdDriver/inc/sc.h
@@ -0,0 +1,269 @@
+/**************************************************************************//**
+ * @file sc.h
+ * @version V3.00
+ * $Revision: 13 $
+ * $Date: 15/08/11 10:26a $
+ * @brief M451 series Smartcard (SC) driver header file
+ *
+ * @note
+ * Copyright (C) 2013~2015 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __SC_H__
+#define __SC_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup Standard_Driver Standard Driver
+ @{
+*/
+
+/** @addtogroup SC_Driver SC Driver
+ @{
+*/
+
+/** @addtogroup SC_EXPORTED_CONSTANTS SC Exported Constants
+ @{
+*/
+#define SC_INTERFACE_NUM 1 /*!< Smartcard interface numbers */ /* M451 series has only one SC interface */
+#define SC_PIN_STATE_HIGH 1 /*!< Smartcard pin status high */
+#define SC_PIN_STATE_LOW 0 /*!< Smartcard pin status low */
+#define SC_PIN_STATE_IGNORE 0xFFFFFFFF /*!< Ignore pin status */
+#define SC_CLK_ON 1 /*!< Smartcard clock on */
+#define SC_CLK_OFF 0 /*!< Smartcard clock off */
+
+#define SC_TMR_MODE_0 (0ul << SC_TMRCTL0_OPMODE_Pos) /*!INTEN |= (u32Mask))
+
+/**
+ * @brief Disable smartcard interrupt.
+ * @param[in] sc The pointer of smartcard module.
+ * @param[in] u32Mask Interrupt mask to be disabled. A combination of
+ * - \ref SC_INTEN_ACERRIEN_Msk
+ * - \ref SC_INTEN_RXTOIF_Msk
+ * - \ref SC_INTEN_INITIEN_Msk
+ * - \ref SC_INTEN_CDIEN_Msk
+ * - \ref SC_INTEN_BGTIEN_Msk
+ * - \ref SC_INTEN_TMR2IEN_Msk
+ * - \ref SC_INTEN_TMR1IEN_Msk
+ * - \ref SC_INTEN_TMR0IEN_Msk
+ * - \ref SC_INTEN_TERRIEN_Msk
+ * - \ref SC_INTEN_TBEIEN_Msk
+ * - \ref SC_INTEN_RDAIEN_Msk
+ * @return None
+ * @details The macro is used to disable Auto-convention error interrupt, Receiver buffer time-out interrupt, Initial end interrupt,
+ * Card detect interrupt, Block guard time interrupt, Timer2 interrupt, Timer1 interrupt, Timer0 interrupt,
+ * Transfer error interrupt, Transmit buffer empty interrupt or Receive data reach trigger level interrupt.
+ * \hideinitializer
+ */
+#define SC_DISABLE_INT(sc, u32Mask) ((sc)->INTEN &= ~(u32Mask))
+
+/**
+ * @brief This macro set VCC pin state of smartcard interface.
+ * @param[in] sc The pointer of smartcard module.
+ * @param[in] u32State Pin state of VCC pin, valid parameters are:
+ * \ref SC_PIN_STATE_HIGH :Smartcard pin status high.
+ * \ref SC_PIN_STATE_LOW :Smartcard pin status low.
+ * @return None
+ * @details User can set PWREN (SC_PINCTL[0]) and PWRINV (SC_PINCTL[11])to decide SC_PWR pin is in high or low level.
+ * \hideinitializer
+ */
+#define SC_SET_VCC_PIN(sc, u32State) \
+ do {\
+ while((sc)->PINCTL & SC_PINCTL_SYNC_Msk);\
+ if(u32State)\
+ (sc)->PINCTL |= SC_PINCTL_PWREN_Msk;\
+ else\
+ (sc)->PINCTL &= ~SC_PINCTL_PWREN_Msk;\
+ }while(0)
+
+
+/**
+ * @brief Set CLK output status.
+ * @param[in] sc The pointer of smartcard module.
+ * @param[in] u32OnOff Clock on or off for selected smartcard module, valid values are:
+ * \ref SC_CLK_ON :Smartcard clock on.
+ * \ref SC_CLK_OFF :Smartcard clock off.
+ * @return None
+ * @details User can set CLKKEEP (SC_PINCTL[6]) to decide SC_CLK pin always keeps free running or not.
+ * \hideinitializer
+ */
+#define SC_SET_CLK_PIN(sc, u32OnOff)\
+ do {\
+ while((sc)->PINCTL & SC_PINCTL_SYNC_Msk);\
+ if(u32OnOff)\
+ (sc)->PINCTL |= SC_PINCTL_CLKKEEP_Msk;\
+ else\
+ (sc)->PINCTL &= ~(SC_PINCTL_CLKKEEP_Msk);\
+ }while(0)
+
+/**
+ * @brief Set I/O pin state.
+ * @param[in] sc The pointer of smartcard module.
+ * @param[in] u32State Pin state of I/O pin, valid parameters are:
+ * \ref SC_PIN_STATE_HIGH :Smartcard pin status high.
+ * \ref SC_PIN_STATE_LOW :Smartcard pin status low.
+ * @return None
+ * @details User can set SCDOUT(SC_PINCTL[9]) to decide SCDOUT pin to high or low.
+ * \hideinitializer
+ */
+#define SC_SET_IO_PIN(sc, u32State)\
+ do {\
+ while((sc)->PINCTL & SC_PINCTL_SYNC_Msk);\
+ if(u32State)\
+ (sc)->PINCTL |= SC_PINCTL_SCDOUT_Msk;\
+ else\
+ (sc)->PINCTL &= ~SC_PINCTL_SCDOUT_Msk;\
+ }while(0)
+
+/**
+ * @brief Set RST pin state.
+ * @param[in] sc The pointer of smartcard module.
+ * @param[in] u32State Pin state of RST pin, valid parameters are:
+ * \ref SC_PIN_STATE_HIGH :Smartcard pin status high.
+ * \ref SC_PIN_STATE_LOW :Smartcard pin status low.
+ * @return None
+ * @details User can set SCRST(SC_PINCTL[1]) to decide SCRST pin to high or low.
+ * \hideinitializer
+ */
+#define SC_SET_RST_PIN(sc, u32State)\
+ do {\
+ while((sc)->PINCTL & SC_PINCTL_SYNC_Msk);\
+ if(u32State)\
+ (sc)->PINCTL |= SC_PINCTL_SCRST_Msk;\
+ else\
+ (sc)->PINCTL &= ~SC_PINCTL_SCRST_Msk;\
+ }while(0)
+
+/**
+ * @brief Read one byte from smartcard module receive FIFO.
+ * @param[in] sc The pointer of smartcard module.
+ * @return One byte read from receive FIFO.
+ * @details By reading DAT register, the SC will return an 8-bit received data.
+ * \hideinitializer
+ */
+#define SC_READ(sc) ((char)((sc)->DAT))
+
+/**
+ * @brief Write one byte to smartcard module transmit FIFO.
+ * @param[in] sc The pointer of smartcard module.
+ * @param[in] u8Data Data to write to transmit FIFO.
+ * @return None
+ * @details By writing data to DAT register, the SC will send out an 8-bit data.
+ * \hideinitializer
+ */
+#define SC_WRITE(sc, u8Data) ((sc)->DAT = (u8Data))
+
+/**
+ * @brief This macro set smartcard stop bit length.
+ * @param[in] sc The pointer of smartcard module.
+ * @param[in] u32Len Stop bit length, ether 1 or 2.
+ * @return None
+ * @details Stop bit length must be 1 for T = 1 protocol and 2 for T = 0 protocol.
+ * \hideinitializer
+ */
+#define SC_SET_STOP_BIT_LEN(sc, u32Len) ((sc)->CTL = ((sc)->CTL & ~SC_CTL_NSB_Msk) | ((u32Len) == 1 ? SC_CTL_NSB_Msk : 0))
+
+/**
+ * @brief Enable/Disable Tx error retry, and set Tx error retry count.
+ * @param[in] sc The pointer of smartcard module.
+ * @param[in] u32Count The number of times of Tx error retry count, between 0~8. 0 means disable Tx error retry.
+ * @return None
+ * @details This macro enable/disable transmitter retry function when parity error has occurred, and set error retry count.
+ */
+__STATIC_INLINE void SC_SetTxRetry(SC_T *sc, uint32_t u32Count)
+{
+ while((sc)->CTL & SC_CTL_SYNC_Msk);
+ if(u32Count == 0) { // disable Tx error retry
+ (sc)->CTL &= ~(SC_CTL_TXRTY_Msk | SC_CTL_TXRTYEN_Msk);
+ } else {
+ (sc)->CTL = ((sc)->CTL & ~SC_CTL_TXRTY_Msk) | ((u32Count - 1) << SC_CTL_TXRTY_Pos) | SC_CTL_TXRTYEN_Msk;
+ }
+}
+
+/**
+ * @brief Enable/Disable Rx error retry, and set Rx error retry count.
+ * @param[in] sc The pointer of smartcard module.
+ * @param[in] u32Count The number of times of Rx error retry count, between 0~8. 0 means disable Rx error retry.
+ * @return None
+ * @details This macro enable/disable receiver retry function when parity error has occurred, and set error retry count.
+ */
+__STATIC_INLINE void SC_SetRxRetry(SC_T *sc, uint32_t u32Count)
+{
+ while((sc)->CTL & SC_CTL_SYNC_Msk);
+ if(u32Count == 0) { // disable Rx error retry
+ (sc)->CTL &= ~(SC_CTL_RXRTY_Msk | SC_CTL_RXRTYEN_Msk);
+ } else {
+ (sc)->CTL = ((sc)->CTL & ~SC_CTL_RXRTY_Msk) | ((u32Count - 1) << SC_CTL_RXRTY_Pos) | SC_CTL_RXRTYEN_Msk;
+ }
+}
+
+
+uint32_t SC_IsCardInserted(SC_T *sc);
+void SC_ClearFIFO(SC_T *sc);
+void SC_Close(SC_T *sc);
+void SC_Open(SC_T *sc, uint32_t u32CardDet, uint32_t u32PWR);
+void SC_ResetReader(SC_T *sc);
+void SC_SetBlockGuardTime(SC_T *sc, uint32_t u32BGT);
+void SC_SetCharGuardTime(SC_T *sc, uint32_t u32CGT);
+void SC_StopAllTimer(SC_T *sc);
+void SC_StartTimer(SC_T *sc, uint32_t u32TimerNum, uint32_t u32Mode, uint32_t u32ETUCount);
+void SC_StopTimer(SC_T *sc, uint32_t u32TimerNum);
+
+
+/*@}*/ /* end of group SC_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group SC_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif //__SC_H__
+
+/*** (C) COPYRIGHT 2013~2015 Nuvoton Technology Corp. ***/
+
diff --git a/bsp/nuvoton_m451/Libraries/StdDriver/inc/scuart.h b/bsp/nuvoton_m451/Libraries/StdDriver/inc/scuart.h
new file mode 100644
index 0000000000000000000000000000000000000000..0ab13abe6968d47c7fe32ef648927c00da2dc786
--- /dev/null
+++ b/bsp/nuvoton_m451/Libraries/StdDriver/inc/scuart.h
@@ -0,0 +1,279 @@
+/**************************************************************************//**
+ * @file sc.h
+ * @version V3.00
+ * $Revision: 7 $
+ * $Date: 15/08/11 10:26a $
+ * @brief M451 series Smartcard UART mode (SCUART) driver header file
+ *
+ * @note
+ * Copyright (C) 2013~2015 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __SCUART_H__
+#define __SCUART_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup Standard_Driver Standard Driver
+ @{
+*/
+
+/** @addtogroup SCUART_Driver SCUART Driver
+ @{
+*/
+
+/** @addtogroup SCUART_EXPORTED_CONSTANTS SCUART Exported Constants
+ @{
+*/
+#define SCUART_CHAR_LEN_5 (0x3ul << SC_UARTCTL_WLS_Pos) /*!< Set SCUART word length to 5 bits */
+#define SCUART_CHAR_LEN_6 (0x2ul << SC_UARTCTL_WLS_Pos) /*!< Set SCUART word length to 6 bits */
+#define SCUART_CHAR_LEN_7 (0x1ul << SC_UARTCTL_WLS_Pos) /*!< Set SCUART word length to 7 bits */
+#define SCUART_CHAR_LEN_8 (0) /*!< Set SCUART word length to 8 bits */
+
+#define SCUART_PARITY_NONE (SC_UARTCTL_PBOFF_Msk) /*!< Set SCUART transfer with no parity */
+#define SCUART_PARITY_ODD (SC_UARTCTL_OPE_Msk) /*!< Set SCUART transfer with odd parity */
+#define SCUART_PARITY_EVEN (0) /*!< Set SCUART transfer with even parity */
+
+#define SCUART_STOP_BIT_1 (SC_CTL_NSB_Msk) /*!< Set SCUART transfer with one stop bit */
+#define SCUART_STOP_BIT_2 (0) /*!< Set SCUART transfer with two stop bits */
+
+
+/*@}*/ /* end of group SCUART_EXPORTED_CONSTANTS */
+
+
+/** @addtogroup SCUART_EXPORTED_FUNCTIONS SCUART Exported Functions
+ @{
+*/
+
+/* TX Macros */
+/**
+ * @brief Write Data to Tx data register.
+ * @param[in] sc The pointer of smartcard module.
+ * @param[in] u8Data Data byte to transmit.
+ * @return None
+ * @details By writing data to DAT register, the SC will send out an 8-bit data.
+ * \hideinitializer
+ */
+#define SCUART_WRITE(sc, u8Data) ((sc)-> DAT = (u8Data))
+
+/**
+ * @brief Get TX FIFO empty flag status from register.
+ * @param[in] sc The pointer of smartcard module.
+ * @return Transmit FIFO empty status.
+ * @retval 0 Transmit FIFO is not empty.
+ * @retval SC_STATUS_TXEMPTY_Msk Transmit FIFO is empty.
+ * @details When the last byte of TX buffer has been transferred to Transmitter Shift Register, hardware sets TXEMPTY bit (SC_STATUS[9]) high.
+ * It will be cleared when writing data into DAT (SC_DAT[7:0]).
+ * \hideinitializer
+ */
+#define SCUART_GET_TX_EMPTY(sc) ((sc)->STATUS & SC_STATUS_TXEMPTY_Msk)
+
+/**
+ * @brief Get TX FIFO full flag status from register.
+ * @param[in] sc The pointer of smartcard module.
+ * @retval 0 Transmit FIFO is not full.
+ * @retval SC_STATUS_TXFULL_Msk Transmit FIFO is full.
+ * @details TXFULL(SC_STATUS[10]) is set when TX pointer is equal to 4, otherwise is cleared by hardware.
+ * \hideinitializer
+ */
+#define SCUART_GET_TX_FULL(sc) ((sc)->STATUS & SC_STATUS_TXFULL_Msk)
+
+/**
+ * @brief Wait specified smartcard port transmission complete.
+ * @param[in] sc The pointer of smartcard module.
+ * @return None
+ * @details TXACT (SC_STATUS[31]) is cleared automatically when TX transfer is finished or the last byte transmission has completed.
+ * @note This macro blocks until transmit complete.
+ * \hideinitializer
+ */
+#define SCUART_WAIT_TX_EMPTY(sc) while((sc)->STATUS & SC_STATUS_TXACT_Msk)
+
+/**
+ * @brief Check specified smartcard port transmit FIFO is full or not.
+ * @param[in] sc The pointer of smartcard module.
+ * @retval 0 Transmit FIFO is not full.
+ * @retval 1 Transmit FIFO is full.
+ * @details TXFULL(SC_STATUS[10]) indicates TX buffer full or not.
+ * This is set when TX pointer is equal to 4, otherwise is cleared by hardware.
+ * \hideinitializer
+ */
+#define SCUART_IS_TX_FULL(sc) ((sc)->STATUS & SC_STATUS_TXFULL_Msk ? 1 : 0)
+
+/**
+ * @brief Check specified smartcard port transmission is over.
+ * @param[in] sc The pointer of smartcard module.
+ * @retval 0 Transmit is not complete.
+ * @retval 1 Transmit complete.
+ * @details TXACT (SC_STATUS[31]) is set by hardware when TX transfer is in active and the STOP bit of the last byte has been transmitted.
+ * \hideinitializer
+ */
+#define SCUART_IS_TX_EMPTY(sc) ((sc)->STATUS & SC_STATUS_TXACT_Msk ? 0 : 1)
+
+
+/* RX Macros */
+
+/**
+ * @brief Read Rx data register.
+ * @param[in] sc The pointer of smartcard module.
+ * @return The oldest data byte in RX FIFO.
+ * @details By reading DAT register, the SC will return an 8-bit received data.
+ * \hideinitializer
+ */
+#define SCUART_READ(sc) ((sc)->DAT)
+
+/**
+ * @brief Get RX FIFO empty flag status from register.
+ * @param[in] sc The pointer of smartcard module.
+ * @retval 0 Receive FIFO is not empty.
+ * @retval SC_STATUS_RXEMPTY_Msk Receive FIFO is empty.
+ * @details When the last byte of Rx buffer has been read by CPU, hardware sets RXEMPTY(SC_STATUS[1]) high.
+ * It will be cleared when SC receives any new data.
+ * \hideinitializer
+ */
+#define SCUART_GET_RX_EMPTY(sc) ((sc)->STATUS & SC_STATUS_RXEMPTY_Msk)
+
+
+/**
+ * @brief Get RX FIFO full flag status from register.
+ * @param[in] sc The pointer of smartcard module.
+ * @retval 0 Receive FIFO is not full.
+ * @retval SC_STATUS_TXFULL_Msk Receive FIFO is full.
+ * @details RXFULLF(SC_STATUS[2]) is set when RX pointer is equal to 4, otherwise it is cleared by hardware.
+ * \hideinitializer
+ */
+#define SCUART_GET_RX_FULL(sc) ((sc)->STATUS & SC_STATUS_RXFULL_Msk)
+
+/**
+ * @brief Check if receive data number in FIFO reach FIFO trigger level or not.
+ * @param[in] sc The pointer of smartcard module.
+ * @retval 0 The number of bytes in receive FIFO is less than trigger level.
+ * @retval 1 The number of bytes in receive FIFO equals or larger than trigger level.
+ * @details RDAIF(SC_INTSTS[0]) is used for received data reaching trigger level RXTRGLV (SC_CTL[7:6]) interrupt status flag.
+ * @note If receive trigger level is \b not 1 byte, this macro return 0 does not necessary indicates there is no data in FIFO.
+ * \hideinitializer
+ */
+#define SCUART_IS_RX_READY(sc) ((sc)->INTSTS & SC_INTSTS_RDAIF_Msk ? 1 : 0)
+
+/**
+ * @brief Check specified smartcard port receive FIFO is full or not.
+ * @param[in] sc The pointer of smartcard module.
+ * @retval 0 Receive FIFO is not full.
+ * @retval 1 Receive FIFO is full.
+ * @details RXFULLF(SC_STATUS[2]) is set when RX pointer is equal to 4, otherwise it is cleared by hardware.
+ * \hideinitializer
+ */
+#define SCUART_IS_RX_FULL(sc) ((sc)->STATUS & SC_STATUS_RXFULL_Msk ? 1 : 0)
+
+/* Interrupt Macros */
+
+/**
+ * @brief Enable specified interrupts.
+ * @param[in] sc The pointer of smartcard module.
+ * @param[in] u32Mask Interrupt masks to enable, a combination of following bits.
+ * - \ref SC_INTEN_RXTOIF_Msk
+ * - \ref SC_INTEN_TERRIEN_Msk
+ * - \ref SC_INTEN_TBEIEN_Msk
+ * - \ref SC_INTEN_RDAIEN_Msk
+ * @return None
+ * @details The macro is used to enable receiver buffer time-out interrupt, transfer error interrupt,
+ * transmit buffer empty interrupt or receive data reach trigger level interrupt.
+ * \hideinitializer
+ */
+#define SCUART_ENABLE_INT(sc, u32Mask) ((sc)->INTEN |= (u32Mask))
+
+/**
+ * @brief Disable specified interrupts.
+ * @param[in] sc The pointer of smartcard module.
+ * @param[in] u32Mask Interrupt masks to disable, a combination of following bits.
+ * - \ref SC_INTEN_RXTOIF_Msk
+ * - \ref SC_INTEN_TERRIEN_Msk
+ * - \ref SC_INTEN_TBEIEN_Msk
+ * - \ref SC_INTEN_RDAIEN_Msk
+ * @return None
+ * @details The macro is used to disable receiver buffer time-out interrupt, transfer error interrupt,
+ * transmit buffer empty interrupt or receive data reach trigger level interrupt.
+ * \hideinitializer
+ */
+#define SCUART_DISABLE_INT(sc, u32Mask) ((sc)->INTEN &= ~(u32Mask))
+
+/**
+ * @brief Get specified interrupt flag/status.
+ * @param[in] sc The pointer of smartcard module.
+ * @param[in] u32Type Interrupt flag/status to check, could be one of following value:
+ * - \ref SC_INTSTS_RBTOIF_Msk
+ * - \ref SC_INTSTS_TERRIF_Msk
+ * - \ref SC_INTSTS_TBEIF_Msk
+ * - \ref SC_INTSTS_RDAIF_Msk
+ * @return The status of specified interrupt.
+ * @retval 0 Specified interrupt does not happened.
+ * @retval 1 Specified interrupt happened.
+ * @details The macro is used to get receiver buffer time-out interrupt status, transfer error interrupt status,
+ * transmit buffer empty interrupt status or receive data reach interrupt status.
+ * \hideinitializer
+ */
+#define SCUART_GET_INT_FLAG(sc, u32Type) ((sc)->INTSTS & (u32Type) ? 1 : 0)
+
+/**
+ * @brief Clear specified interrupt flag/status.
+ * @param[in] sc The pointer of smartcard module.
+ * @param[in] u32Type Interrupt flag/status to clear, could be the combination of following values:
+ * - \ref SC_INTSTS_RBTOIF_Msk
+ * - \ref SC_INTSTS_TERRIF_Msk
+ * - \ref SC_INTSTS_TBEIF_Msk
+ * @return None
+ * @details The macro is used to clear receiver buffer time-out interrupt flag, transfer error interrupt flag or
+ * transmit buffer empty interrupt flag.
+ * \hideinitializer
+ */
+#define SCUART_CLR_INT_FLAG(sc, u32Type) ((sc)->INTSTS = (u32Type))
+
+/**
+ * @brief Get receive error flag/status.
+ * @param[in] sc The pointer of smartcard module.
+ * @return Current receive error status, could one of following errors:
+ * @retval SC_STATUS_PEF_Msk Parity error.
+ * @retval SC_STATUS_FEF_Msk Frame error.
+ * @retval SC_STATUS_BEF_Msk Break error.
+ * @details The macro is used to get receiver parity error status, receiver frame error status or
+ * receiver break error status.
+ * \hideinitializer
+ */
+#define SCUART_GET_ERR_FLAG(sc) ((sc)->STATUS & (SC_STATUS_PEF_Msk | SC_STATUS_FEF_Msk | SC_STATUS_BEF_Msk))
+
+/**
+ * @brief Clear specified receive error flag/status.
+ * @param[in] sc The pointer of smartcard module.
+ * @param[in] u32Mask Receive error flag/status to clear, combination following values:
+ * - \ref SC_STATUS_PEF_Msk
+ * - \ref SC_STATUS_FEF_Msk
+ * - \ref SC_STATUS_BEF_Msk
+ * @return None
+ * @details The macro is used to clear receiver parity error flag, receiver frame error flag or
+ * receiver break error flag.
+ * \hideinitializer
+ */
+#define SCUART_CLR_ERR_FLAG(sc, u32Mask) ((sc)->STATUS = (u32Mask))
+
+void SCUART_Close(SC_T* sc);
+uint32_t SCUART_Open(SC_T* sc, uint32_t u32baudrate);
+uint32_t SCUART_Read(SC_T* sc, uint8_t *pu8RxBuf, uint32_t u32ReadBytes);
+uint32_t SCUART_SetLineConfig(SC_T* sc, uint32_t u32Baudrate, uint32_t u32DataWidth, uint32_t u32Parity, uint32_t u32StopBits);
+void SCUART_SetTimeoutCnt(SC_T* sc, uint32_t u32TOC);
+void SCUART_Write(SC_T* sc, uint8_t *pu8TxBuf, uint32_t u32WriteBytes);
+
+/*@}*/ /* end of group SCUART_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group SCUART_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif //__SCUART_H__
+
+/*** (C) COPYRIGHT 2013~2015 Nuvoton Technology Corp. ***/
diff --git a/bsp/nuvoton_m451/Libraries/StdDriver/inc/spi.h b/bsp/nuvoton_m451/Libraries/StdDriver/inc/spi.h
new file mode 100644
index 0000000000000000000000000000000000000000..02d2469190a10e24483e3e7f8ce5b5a3b4fd0c53
--- /dev/null
+++ b/bsp/nuvoton_m451/Libraries/StdDriver/inc/spi.h
@@ -0,0 +1,630 @@
+/******************************************************************************
+ * @file spi.h
+ * @version V0.10
+ * $Revision: 17 $
+ * $Date: 15/08/11 10:26a $
+ * @brief M451 series SPI driver header file
+ *
+ * @note
+ * Copyright (C) 2014~2015 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#ifndef __SPI_H__
+#define __SPI_H__
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Include related headers */
+/*---------------------------------------------------------------------------------------------------------*/
+#include "M451Series.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup Standard_Driver Standard Driver
+ @{
+*/
+
+/** @addtogroup SPI_Driver SPI Driver
+ @{
+*/
+
+/** @addtogroup SPI_EXPORTED_CONSTANTS SPI Exported Constants
+ @{
+*/
+
+#define SPI_MODE_0 (SPI_CTL_TXNEG_Msk) /*!< CLKPOL=0; RXNEG=0; TXNEG=1 */
+#define SPI_MODE_1 (SPI_CTL_RXNEG_Msk) /*!< CLKPOL=0; RXNEG=1; TXNEG=0 */
+#define SPI_MODE_2 (SPI_CTL_CLKPOL_Msk | SPI_CTL_RXNEG_Msk) /*!< CLKPOL=1; RXNEG=1; TXNEG=0 */
+#define SPI_MODE_3 (SPI_CTL_CLKPOL_Msk | SPI_CTL_TXNEG_Msk) /*!< CLKPOL=1; RXNEG=0; TXNEG=1 */
+
+#define SPI_SLAVE (SPI_CTL_SLAVE_Msk) /*!< Set as slave */
+#define SPI_MASTER (0x0) /*!< Set as master */
+
+#define SPI_SS (SPI_SSCTL_SS_Msk) /*!< Set SS */
+#define SPI_SS_ACTIVE_HIGH (SPI_SSCTL_SSACTPOL_Msk) /*!< SS active high */
+#define SPI_SS_ACTIVE_LOW (0x0) /*!< SS active low */
+
+/* SPI Interrupt Mask */
+#define SPI_UNIT_INT_MASK (0x001) /*!< Unit transfer interrupt mask */
+#define SPI_SSACT_INT_MASK (0x002) /*!< Slave selection signal active interrupt mask */
+#define SPI_SSINACT_INT_MASK (0x004) /*!< Slave selection signal inactive interrupt mask */
+#define SPI_SLVUR_INT_MASK (0x008) /*!< Slave under run interrupt mask */
+#define SPI_SLVBE_INT_MASK (0x010) /*!< Slave bit count error interrupt mask */
+#define SPI_SLVTO_INT_MASK (0x020) /*!< Slave time-out interrupt mask */
+#define SPI_TXUF_INT_MASK (0x040) /*!< Slave TX underflow interrupt mask */
+#define SPI_FIFO_TXTH_INT_MASK (0x080) /*!< FIFO TX threshold interrupt mask */
+#define SPI_FIFO_RXTH_INT_MASK (0x100) /*!< FIFO RX threshold interrupt mask */
+#define SPI_FIFO_RXOV_INT_MASK (0x200) /*!< FIFO RX overrun interrupt mask */
+#define SPI_FIFO_RXTO_INT_MASK (0x400) /*!< FIFO RX time-out interrupt mask */
+
+/* SPI Status Mask */
+#define SPI_BUSY_MASK (0x01) /*!< Busy status mask */
+#define SPI_RX_EMPTY_MASK (0x02) /*!< RX empty status mask */
+#define SPI_RX_FULL_MASK (0x04) /*!< RX full status mask */
+#define SPI_TX_EMPTY_MASK (0x08) /*!< TX empty status mask */
+#define SPI_TX_FULL_MASK (0x10) /*!< TX full status mask */
+#define SPI_TXRX_RESET_MASK (0x20) /*!< TX or RX reset status mask */
+#define SPI_SPIEN_STS_MASK (0x40) /*!< SPIEN status mask */
+#define SPI_SSLINE_STS_MASK (0x80) /*!< SPIn_SS line status mask */
+
+
+/* I2S Data Width */
+#define I2S_DATABIT_8 (0 << SPI_I2SCTL_WDWIDTH_Pos) /*!< I2S data width is 8-bit */
+#define I2S_DATABIT_16 (1 << SPI_I2SCTL_WDWIDTH_Pos) /*!< I2S data width is 16-bit */
+#define I2S_DATABIT_24 (2 << SPI_I2SCTL_WDWIDTH_Pos) /*!< I2S data width is 24-bit */
+#define I2S_DATABIT_32 (3 << SPI_I2SCTL_WDWIDTH_Pos) /*!< I2S data width is 32-bit */
+
+/* I2S Audio Format */
+#define I2S_MONO SPI_I2SCTL_MONO_Msk /*!< Monaural channel */
+#define I2S_STEREO 0 /*!< Stereo channel */
+
+/* I2S Data Format */
+#define I2S_FORMAT_I2S (0<STATUS = SPI_STATUS_UNITIF_Msk)
+
+/**
+ * @brief Disable 2-bit Transfer mode.
+ * @param[in] spi The pointer of the specified SPI module.
+ * @return None.
+ * @details Clear TWOBIT bit of SPI_CTL register to disable 2-bit Transfer mode.
+ */
+#define SPI_DISABLE_2BIT_MODE(spi) ((spi)->CTL &= ~SPI_CTL_TWOBIT_Msk)
+
+/**
+ * @brief Disable Slave 3-wire mode.
+ * @param[in] spi The pointer of the specified SPI module.
+ * @return None.
+ * @details Clear SLV3WIRE bit of SPI_SSCTL register to disable Slave 3-wire mode.
+ */
+#define SPI_DISABLE_3WIRE_MODE(spi) ((spi)->SSCTL &= ~SPI_SSCTL_SLV3WIRE_Msk)
+
+/**
+ * @brief Disable Dual I/O mode.
+ * @param[in] spi The pointer of the specified SPI module.
+ * @return None.
+ * @details Clear DUALIOEN bit of SPI_CTL register to disable Dual I/O mode.
+ */
+#define SPI_DISABLE_DUAL_MODE(spi) ((spi)->CTL &= ~SPI_CTL_DUALIOEN_Msk)
+
+/**
+ * @brief Disable Quad I/O mode.
+ * @param[in] spi The pointer of the specified SPI module.
+ * @return None.
+ * @details Clear QUADIOEN bit of SPI_CTL register to disable Quad I/O mode.
+ */
+#define SPI_DISABLE_QUAD_MODE(spi) ((spi)->CTL &= ~SPI_CTL_QUADIOEN_Msk)
+
+/**
+ * @brief Enable 2-bit Transfer mode.
+ * @param[in] spi The pointer of the specified SPI module.
+ * @return None.
+ * @details Set TWOBIT bit of SPI_CTL register to enable 2-bit Transfer mode.
+ */
+#define SPI_ENABLE_2BIT_MODE(spi) ((spi)->CTL |= SPI_CTL_TWOBIT_Msk)
+
+/**
+ * @brief Enable Slave 3-wire mode.
+ * @param[in] spi The pointer of the specified SPI module.
+ * @return None.
+ * @details Set SLV3WIRE bit of SPI_SSCTL register to enable Slave 3-wire mode.
+ */
+#define SPI_ENABLE_3WIRE_MODE(spi) ((spi)->SSCTL |= SPI_SSCTL_SLV3WIRE_Msk)
+
+/**
+ * @brief Enable Dual input mode.
+ * @param[in] spi The pointer of the specified SPI module.
+ * @return None.
+ * @details Clear QDIODIR bit and set DUALIOEN bit of SPI_CTL register to enable Dual input mode.
+ */
+#define SPI_ENABLE_DUAL_INPUT_MODE(spi) ((spi)->CTL = ((spi)->CTL & (~SPI_CTL_QDIODIR_Msk)) | SPI_CTL_DUALIOEN_Msk)
+
+/**
+ * @brief Enable Dual output mode.
+ * @param[in] spi The pointer of the specified SPI module.
+ * @return None.
+ * @details Set QDIODIR bit and DUALIOEN bit of SPI_CTL register to enable Dual output mode.
+ */
+#define SPI_ENABLE_DUAL_OUTPUT_MODE(spi) ((spi)->CTL |= (SPI_CTL_QDIODIR_Msk | SPI_CTL_DUALIOEN_Msk))
+
+/**
+ * @brief Enable Quad input mode.
+ * @param[in] spi The pointer of the specified SPI module.
+ * @return None.
+ * @details Clear QDIODIR bit and set QUADIOEN bit of SPI_CTL register to enable Quad input mode.
+ */
+#define SPI_ENABLE_QUAD_INPUT_MODE(spi) ((spi)->CTL = ((spi)->CTL & (~SPI_CTL_QDIODIR_Msk)) | SPI_CTL_QUADIOEN_Msk)
+
+/**
+ * @brief Enable Quad output mode.
+ * @param[in] spi The pointer of the specified SPI module.
+ * @return None.
+ * @details Set QDIODIR bit and QUADIOEN bit of SPI_CTL register to enable Quad output mode.
+ */
+#define SPI_ENABLE_QUAD_OUTPUT_MODE(spi) ((spi)->CTL |= (SPI_CTL_QDIODIR_Msk | SPI_CTL_QUADIOEN_Msk))
+
+/**
+ * @brief Trigger RX PDMA function.
+ * @param[in] spi The pointer of the specified SPI module.
+ * @return None.
+ * @details Set RXPDMAEN bit of SPI_PDMACTL register to enable RX PDMA transfer function.
+ */
+#define SPI_TRIGGER_RX_PDMA(spi) ((spi)->PDMACTL |= SPI_PDMACTL_RXPDMAEN_Msk)
+
+/**
+ * @brief Trigger TX PDMA function.
+ * @param[in] spi The pointer of the specified SPI module.
+ * @return None.
+ * @details Set TXPDMAEN bit of SPI_PDMACTL register to enable TX PDMA transfer function.
+ */
+#define SPI_TRIGGER_TX_PDMA(spi) ((spi)->PDMACTL |= SPI_PDMACTL_TXPDMAEN_Msk)
+
+/**
+ * @brief Disable RX PDMA transfer.
+ * @param[in] spi The pointer of the specified SPI module.
+ * @return None.
+ * @details Clear RXPDMAEN bit of SPI_PDMACTL register to disable RX PDMA transfer function.
+ */
+#define SPI_DISABLE_RX_PDMA(spi) ( (spi)->PDMACTL &= ~SPI_PDMACTL_RXPDMAEN_Msk )
+
+/**
+ * @brief Disable TX PDMA transfer.
+ * @param[in] spi The pointer of the specified SPI module.
+ * @return None.
+ * @details Clear TXPDMAEN bit of SPI_PDMACTL register to disable TX PDMA transfer function.
+ */
+#define SPI_DISABLE_TX_PDMA(spi) ( (spi)->PDMACTL &= ~SPI_PDMACTL_TXPDMAEN_Msk )
+
+/**
+ * @brief Get the count of available data in RX FIFO.
+ * @param[in] spi The pointer of the specified SPI module.
+ * @return The count of available data in RX FIFO.
+ * @details Read RXCNT (SPI_STATUS[27:24]) to get the count of available data in RX FIFO.
+ */
+#define SPI_GET_RX_FIFO_COUNT(spi) (((spi)->STATUS & SPI_STATUS_RXCNT_Msk) >> SPI_STATUS_RXCNT_Pos)
+
+/**
+ * @brief Get the RX FIFO empty flag.
+ * @param[in] spi The pointer of the specified SPI module.
+ * @retval 0 RX FIFO is not empty.
+ * @retval 1 RX FIFO is empty.
+ * @details Read RXEMPTY bit of SPI_STATUS register to get the RX FIFO empty flag.
+ */
+#define SPI_GET_RX_FIFO_EMPTY_FLAG(spi) (((spi)->STATUS & SPI_STATUS_RXEMPTY_Msk)>>SPI_STATUS_RXEMPTY_Pos)
+
+/**
+ * @brief Get the TX FIFO empty flag.
+ * @param[in] spi The pointer of the specified SPI module.
+ * @retval 0 TX FIFO is not empty.
+ * @retval 1 TX FIFO is empty.
+ * @details Read TXEMPTY bit of SPI_STATUS register to get the TX FIFO empty flag.
+ */
+#define SPI_GET_TX_FIFO_EMPTY_FLAG(spi) (((spi)->STATUS & SPI_STATUS_TXEMPTY_Msk)>>SPI_STATUS_TXEMPTY_Pos)
+
+/**
+ * @brief Get the TX FIFO full flag.
+ * @param[in] spi The pointer of the specified SPI module.
+ * @retval 0 TX FIFO is not full.
+ * @retval 1 TX FIFO is full.
+ * @details Read TXFULL bit of SPI_STATUS register to get the TX FIFO full flag.
+ */
+#define SPI_GET_TX_FIFO_FULL_FLAG(spi) (((spi)->STATUS & SPI_STATUS_TXFULL_Msk)>>SPI_STATUS_TXFULL_Pos)
+
+/**
+ * @brief Get the datum read from RX register.
+ * @param[in] spi The pointer of the specified SPI module.
+ * @return Data in RX register.
+ * @details Read SPI_RX register to get the received datum.
+ */
+#define SPI_READ_RX(spi) ((spi)->RX)
+
+/**
+ * @brief Write datum to TX register.
+ * @param[in] spi The pointer of the specified SPI module.
+ * @param[in] u32TxData The datum which user attempt to transfer through SPI bus.
+ * @return None.
+ * @details Write u32TxData to SPI_TX register.
+ */
+#define SPI_WRITE_TX(spi, u32TxData) ((spi)->TX = (u32TxData))
+
+/**
+ * @brief Set SPIn_SS pin to high state.
+ * @param[in] spi The pointer of the specified SPI module.
+ * @return None.
+ * @details Disable automatic slave selection function and set SPIn_SS pin to high state.
+ */
+#define SPI_SET_SS_HIGH(spi) ((spi)->SSCTL = ((spi)->SSCTL & (~SPI_SSCTL_AUTOSS_Msk)) | (SPI_SSCTL_SSACTPOL_Msk | SPI_SSCTL_SS_Msk))
+
+/**
+ * @brief Set SPIn_SS pin to low state.
+ * @param[in] spi The pointer of the specified SPI module.
+ * @return None.
+ * @details Disable automatic slave selection function and set SPIn_SS pin to low state.
+ */
+#define SPI_SET_SS_LOW(spi) ((spi)->SSCTL = ((spi)->SSCTL & (~(SPI_SSCTL_AUTOSS_Msk | SPI_SSCTL_SSACTPOL_Msk))) | SPI_SSCTL_SS_Msk)
+
+/**
+ * @brief Enable Byte Reorder function.
+ * @param[in] spi The pointer of the specified SPI module.
+ * @return None.
+ * @details Enable Byte Reorder function. The suspend interval depends on the setting of SUSPITV (SPI_CTL[7:4]).
+ */
+#define SPI_ENABLE_BYTE_REORDER(spi) ((spi)->CTL |= SPI_CTL_REORDER_Msk)
+
+/**
+ * @brief Disable Byte Reorder function.
+ * @param[in] spi The pointer of the specified SPI module.
+ * @return None.
+ * @details Clear REORDER bit field of SPI_CTL register to disable Byte Reorder function.
+ */
+#define SPI_DISABLE_BYTE_REORDER(spi) ((spi)->CTL &= ~SPI_CTL_REORDER_Msk)
+
+/**
+ * @brief Set the length of suspend interval.
+ * @param[in] spi The pointer of the specified SPI module.
+ * @param[in] u32SuspCycle Decides the length of suspend interval. It could be 0 ~ 15.
+ * @return None.
+ * @details Set the length of suspend interval according to u32SuspCycle.
+ * The length of suspend interval is ((u32SuspCycle + 0.5) * the length of one SPI bus clock cycle).
+ */
+#define SPI_SET_SUSPEND_CYCLE(spi, u32SuspCycle) ((spi)->CTL = ((spi)->CTL & ~SPI_CTL_SUSPITV_Msk) | ((u32SuspCycle) << SPI_CTL_SUSPITV_Pos))
+
+/**
+ * @brief Set the SPI transfer sequence with LSB first.
+ * @param[in] spi The pointer of the specified SPI module.
+ * @return None.
+ * @details Set LSB bit of SPI_CTL register to set the SPI transfer sequence with LSB first.
+ */
+#define SPI_SET_LSB_FIRST(spi) ((spi)->CTL |= SPI_CTL_LSB_Msk)
+
+/**
+ * @brief Set the SPI transfer sequence with MSB first.
+ * @param[in] spi The pointer of the specified SPI module.
+ * @return None.
+ * @details Clear LSB bit of SPI_CTL register to set the SPI transfer sequence with MSB first.
+ */
+#define SPI_SET_MSB_FIRST(spi) ((spi)->CTL &= ~SPI_CTL_LSB_Msk)
+
+/**
+ * @brief Set the data width of a SPI transaction.
+ * @param[in] spi The pointer of the specified SPI module.
+ * @param[in] u32Width The bit width of one transaction.
+ * @return None.
+ * @details The data width can be 8 ~ 32 bits.
+ */
+#define SPI_SET_DATA_WIDTH(spi, u32Width) ((spi)->CTL = ((spi)->CTL & ~SPI_CTL_DWIDTH_Msk) | (((u32Width)&0x1F) << SPI_CTL_DWIDTH_Pos))
+
+/**
+ * @brief Get the SPI busy state.
+ * @param[in] spi The pointer of the specified SPI module.
+ * @retval 0 SPI controller is not busy.
+ * @retval 1 SPI controller is busy.
+ * @details This macro will return the busy state of SPI controller.
+ */
+#define SPI_IS_BUSY(spi) ( ((spi)->STATUS & SPI_STATUS_BUSY_Msk)>>SPI_STATUS_BUSY_Pos )
+
+/**
+ * @brief Enable SPI controller.
+ * @param[in] spi The pointer of the specified SPI module.
+ * @return None.
+ * @details Set SPIEN (SPI_CTL[0]) to enable SPI controller.
+ */
+#define SPI_ENABLE(spi) ((spi)->CTL |= SPI_CTL_SPIEN_Msk)
+
+/**
+ * @brief Disable SPI controller.
+ * @param[in] spi The pointer of the specified SPI module.
+ * @return None.
+ * @details Clear SPIEN (SPI_CTL[0]) to disable SPI controller.
+ */
+#define SPI_DISABLE(spi) ((spi)->CTL &= ~SPI_CTL_SPIEN_Msk)
+
+
+/**
+ * @brief Enable zero cross detection function.
+ * @param[in] i2s The pointer of the specified I2S module.
+ * @param[in] u32ChMask The mask for left or right channel. Valid values are:
+ * - \ref I2S_RIGHT
+ * - \ref I2S_LEFT
+ * @return None
+ * @details This function will set RZCEN or LZCEN bit of SPI_I2SCTL register to enable zero cross detection function.
+ */
+static __INLINE void I2S_ENABLE_TX_ZCD(SPI_T *i2s, uint32_t u32ChMask)
+{
+ if(u32ChMask == I2S_RIGHT)
+ i2s->I2SCTL |= SPI_I2SCTL_RZCEN_Msk;
+ else
+ i2s->I2SCTL |= SPI_I2SCTL_LZCEN_Msk;
+}
+
+/**
+ * @brief Disable zero cross detection function.
+ * @param[in] i2s The pointer of the specified I2S module.
+ * @param[in] u32ChMask The mask for left or right channel. Valid values are:
+ * - \ref I2S_RIGHT
+ * - \ref I2S_LEFT
+ * @return None
+ * @details This function will clear RZCEN or LZCEN bit of SPI_I2SCTL register to disable zero cross detection function.
+ */
+static __INLINE void I2S_DISABLE_TX_ZCD(SPI_T *i2s, uint32_t u32ChMask)
+{
+ if(u32ChMask == I2S_RIGHT)
+ i2s->I2SCTL &= ~SPI_I2SCTL_RZCEN_Msk;
+ else
+ i2s->I2SCTL &= ~SPI_I2SCTL_LZCEN_Msk;
+}
+
+/**
+ * @brief Enable I2S TX DMA function.
+ * @param[in] i2s The pointer of the specified I2S module.
+ * @return None
+ * @details This macro will set TXPDMAEN bit of SPI_PDMACTL register to transmit data with PDMA.
+ */
+#define I2S_ENABLE_TXDMA(i2s) ( (i2s)->PDMACTL |= SPI_PDMACTL_TXPDMAEN_Msk )
+
+/**
+ * @brief Disable I2S TX DMA function.
+ * @param[in] i2s The pointer of the specified I2S module.
+ * @return None
+ * @details This macro will clear TXPDMAEN bit of SPI_PDMACTL register to disable TX DMA function.
+ */
+#define I2S_DISABLE_TXDMA(i2s) ( (i2s)->PDMACTL &= ~SPI_PDMACTL_TXPDMAEN_Msk )
+
+/**
+ * @brief Enable I2S RX DMA function.
+ * @param[in] i2s The pointer of the specified I2S module.
+ * @return None
+ * @details This macro will set RXPDMAEN bit of SPI_PDMACTL register to receive data with PDMA.
+ */
+#define I2S_ENABLE_RXDMA(i2s) ( (i2s)->PDMACTL |= SPI_PDMACTL_RXPDMAEN_Msk )
+
+/**
+ * @brief Disable I2S RX DMA function.
+ * @param[in] i2s The pointer of the specified I2S module.
+ * @return None
+ * @details This macro will clear RXPDMAEN bit of SPI_PDMACTL register to disable RX DMA function.
+ */
+#define I2S_DISABLE_RXDMA(i2s) ( (i2s)->PDMACTL &= ~SPI_PDMACTL_RXPDMAEN_Msk )
+
+/**
+ * @brief Enable I2S TX function.
+ * @param[in] i2s The pointer of the specified I2S module.
+ * @return None
+ * @details This macro will set TXEN bit of SPI_I2SCTL register to enable I2S TX function.
+ */
+#define I2S_ENABLE_TX(i2s) ( (i2s)->I2SCTL |= SPI_I2SCTL_TXEN_Msk )
+
+/**
+ * @brief Disable I2S TX function.
+ * @param[in] i2s The pointer of the specified I2S module.
+ * @return None
+ * @details This macro will clear TXEN bit of SPI_I2SCTL register to disable I2S TX function.
+ */
+#define I2S_DISABLE_TX(i2s) ( (i2s)->I2SCTL &= ~SPI_I2SCTL_TXEN_Msk )
+
+/**
+ * @brief Enable I2S RX function.
+ * @param[in] i2s The pointer of the specified I2S module.
+ * @return None
+ * @details This macro will set RXEN bit of SPI_I2SCTL register to enable I2S RX function.
+ */
+#define I2S_ENABLE_RX(i2s) ( (i2s)->I2SCTL |= SPI_I2SCTL_RXEN_Msk )
+
+/**
+ * @brief Disable I2S RX function.
+ * @param[in] i2s The pointer of the specified I2S module.
+ * @return None
+ * @details This macro will clear RXEN bit of SPI_I2SCTL register to disable I2S RX function.
+ */
+#define I2S_DISABLE_RX(i2s) ( (i2s)->I2SCTL &= ~SPI_I2SCTL_RXEN_Msk )
+
+/**
+ * @brief Enable TX Mute function.
+ * @param[in] i2s The pointer of the specified I2S module.
+ * @return None
+ * @details This macro will set MUTE bit of SPI_I2SCTL register to enable I2S TX mute function.
+ */
+#define I2S_ENABLE_TX_MUTE(i2s) ( (i2s)->I2SCTL |= SPI_I2SCTL_MUTE_Msk )
+
+/**
+ * @brief Disable TX Mute function.
+ * @param[in] i2s The pointer of the specified I2S module.
+ * @return None
+ * @details This macro will clear MUTE bit of SPI_I2SCTL register to disable I2S TX mute function.
+ */
+#define I2S_DISABLE_TX_MUTE(i2s) ( (i2s)->I2SCTL &= ~SPI_I2SCTL_MUTE_Msk )
+
+/**
+ * @brief Clear TX FIFO.
+ * @param[in] i2s The pointer of the specified I2S module.
+ * @return None
+ * @details This macro will clear TX FIFO. The internal TX FIFO pointer will be reset to FIFO start point.
+ */
+#define I2S_CLR_TX_FIFO(i2s) ( (i2s)->FIFOCTL |= SPI_FIFOCTL_TXFBCLR_Msk )
+
+/**
+ * @brief Clear RX FIFO.
+ * @param[in] i2s The pointer of the specified I2S module.
+ * @return None
+ * @details This macro will clear RX FIFO. The internal RX FIFO pointer will be reset to FIFO start point.
+ */
+#define I2S_CLR_RX_FIFO(i2s) ( (i2s)->FIFOCTL |= SPI_FIFOCTL_RXFBCLR_Msk )
+
+/**
+ * @brief This function sets the recording source channel when mono mode is used.
+ * @param[in] i2s The pointer of the specified I2S module.
+ * @param[in] u32Ch left or right channel. Valid values are:
+ * - \ref I2S_MONO_LEFT
+ * - \ref I2S_MONO_RIGHT
+ * @return None
+ * @details This function selects the recording source channel of monaural mode.
+ */
+static __INLINE void I2S_SET_MONO_RX_CHANNEL(SPI_T *i2s, uint32_t u32Ch)
+{
+ u32Ch == I2S_MONO_LEFT ?
+ (i2s->I2SCTL |= SPI_I2SCTL_RXLCH_Msk) :
+ (i2s->I2SCTL &= ~SPI_I2SCTL_RXLCH_Msk);
+}
+
+/**
+ * @brief Write data to I2S TX FIFO.
+ * @param[in] i2s The pointer of the specified I2S module.
+ * @param[in] u32Data The value written to TX FIFO.
+ * @return None
+ * @details This macro will write a value to TX FIFO.
+ */
+#define I2S_WRITE_TX_FIFO(i2s, u32Data) ( (i2s)->TX = (u32Data) )
+
+/**
+ * @brief Read RX FIFO.
+ * @param[in] i2s The pointer of the specified I2S module.
+ * @return The value read from RX FIFO.
+ * @details This function will return a value read from RX FIFO.
+ */
+#define I2S_READ_RX_FIFO(i2s) ( (i2s)->RX )
+
+/**
+ * @brief Get the interrupt flag.
+ * @param[in] i2s The pointer of the specified I2S module.
+ * @param[in] u32Mask The mask value for all interrupt flags.
+ * @return The interrupt flags specified by the u32mask parameter.
+ * @details This macro will return the combination interrupt flags of SPI_I2SSTS register. The flags are specified by the u32mask parameter.
+ */
+#define I2S_GET_INT_FLAG(i2s, u32Mask) ( (i2s)->I2SSTS & (u32Mask) )
+
+/**
+ * @brief Clear the interrupt flag.
+ * @param[in] i2s The pointer of the specified I2S module.
+ * @param[in] u32Mask The mask value for all interrupt flags.
+ * @return None
+ * @details This macro will clear the interrupt flags specified by the u32mask parameter.
+ * @note Except TX and RX FIFO threshold interrupt flags, the other interrupt flags can be cleared by writing 1 to itself.
+ */
+#define I2S_CLR_INT_FLAG(i2s, u32Mask) ( (i2s)->I2SSTS = (u32Mask) )
+
+/**
+ * @brief Get transmit FIFO level
+ * @param[in] i2s The pointer of the specified I2S module.
+ * @return TX FIFO level
+ * @details This macro will return the number of available words in TX FIFO.
+ */
+#define I2S_GET_TX_FIFO_LEVEL(i2s) ( ((i2s)->I2SSTS & SPI_I2SSTS_TXCNT_Msk) >> SPI_I2SSTS_TXCNT_Pos )
+
+/**
+ * @brief Get receive FIFO level
+ * @param[in] i2s The pointer of the specified I2S module.
+ * @return RX FIFO level
+ * @details This macro will return the number of available words in RX FIFO.
+ */
+#define I2S_GET_RX_FIFO_LEVEL(i2s) ( ((i2s)->I2SSTS & SPI_I2SSTS_RXCNT_Msk) >> SPI_I2SSTS_RXCNT_Pos )
+
+
+
+/* Function prototype declaration */
+uint32_t SPI_Open(SPI_T *spi, uint32_t u32MasterSlave, uint32_t u32SPIMode, uint32_t u32DataWidth, uint32_t u32BusClock);
+void SPI_Close(SPI_T *spi);
+void SPI_ClearRxFIFO(SPI_T *spi);
+void SPI_ClearTxFIFO(SPI_T *spi);
+void SPI_DisableAutoSS(SPI_T *spi);
+void SPI_EnableAutoSS(SPI_T *spi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel);
+uint32_t SPI_SetBusClock(SPI_T *spi, uint32_t u32BusClock);
+void SPI_SetFIFO(SPI_T *spi, uint32_t u32TxThreshold, uint32_t u32RxThreshold);
+uint32_t SPI_GetBusClock(SPI_T *spi);
+void SPI_EnableInt(SPI_T *spi, uint32_t u32Mask);
+void SPI_DisableInt(SPI_T *spi, uint32_t u32Mask);
+uint32_t SPI_GetIntFlag(SPI_T *spi, uint32_t u32Mask);
+void SPI_ClearIntFlag(SPI_T *spi, uint32_t u32Mask);
+uint32_t SPI_GetStatus(SPI_T *spi, uint32_t u32Mask);
+
+uint32_t I2S_Open(SPI_T *i2s, uint32_t u32MasterSlave, uint32_t u32SampleRate, uint32_t u32WordWidth, uint32_t u32Channels, uint32_t u32DataFormat);
+void I2S_Close(SPI_T *i2s);
+void I2S_EnableInt(SPI_T *i2s, uint32_t u32Mask);
+void I2S_DisableInt(SPI_T *i2s, uint32_t u32Mask);
+uint32_t I2S_EnableMCLK(SPI_T *i2s, uint32_t u32BusClock);
+void I2S_DisableMCLK(SPI_T *i2s);
+void I2S_SetFIFO(SPI_T *i2s, uint32_t u32TxThreshold, uint32_t u32RxThreshold);
+
+
+/*@}*/ /* end of group SPI_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group SPI_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif //__SPI_H__
+
+/*** (C) COPYRIGHT 2014~2015 Nuvoton Technology Corp. ***/
diff --git a/bsp/nuvoton_m451/Libraries/StdDriver/inc/sys.h b/bsp/nuvoton_m451/Libraries/StdDriver/inc/sys.h
new file mode 100644
index 0000000000000000000000000000000000000000..28b4a2618e3fc2493c1e035e147f89d7a38b9a3d
--- /dev/null
+++ b/bsp/nuvoton_m451/Libraries/StdDriver/inc/sys.h
@@ -0,0 +1,970 @@
+/**************************************************************************//**
+ * @file SYS.h
+ * @version V3.0
+ * $Revision 1 $
+ * $Date: 15/08/11 10:26a $
+ * @brief M451 Series SYS Header File
+ *
+ * @note
+ * Copyright (C) 2013~2015 Nuvoton Technology Corp. All rights reserved.
+ ******************************************************************************/
+
+#ifndef __SYS_H__
+#define __SYS_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/** @addtogroup Standard_Driver Standard Driver
+ @{
+*/
+
+/** @addtogroup SYS_Driver SYS Driver
+ @{
+*/
+
+/** @addtogroup SYS_EXPORTED_CONSTANTS SYS Exported Constants
+ @{
+*/
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Module Reset Control Resister constant definitions. */
+/*---------------------------------------------------------------------------------------------------------*/
+#define PDMA_RST ((0x0<<24) | SYS_IPRST0_PDMARST_Pos ) /*!< Reset PDMA */
+#define EBI_RST ((0x0<<24) | SYS_IPRST0_EBIRST_Pos ) /*!< Reset EBI */
+#define USBH_RST ((0x0<<24) | SYS_IPRST0_USBHRST_Pos ) /*!< Reset USBH */
+#define CRC_RST ((0x0<<24) | SYS_IPRST0_CRCRST_Pos ) /*!< Reset CRC */
+
+#define GPIO_RST ((0x4<<24) | SYS_IPRST1_GPIORST_Pos ) /*!< Reset GPIO */
+#define TMR0_RST ((0x4<<24) | SYS_IPRST1_TMR0RST_Pos ) /*!< Reset TMR0 */
+#define TMR1_RST ((0x4<<24) | SYS_IPRST1_TMR1RST_Pos ) /*!< Reset TMR1 */
+#define TMR2_RST ((0x4<<24) | SYS_IPRST1_TMR2RST_Pos ) /*!< Reset TMR2 */
+#define TMR3_RST ((0x4<<24) | SYS_IPRST1_TMR3RST_Pos ) /*!< Reset TMR3 */
+#define ACMP01_RST ((0x4<<24) | SYS_IPRST1_ACMP01RST_Pos ) /*!< Reset ACMP01 */
+#define I2C0_RST ((0x4<<24) | SYS_IPRST1_I2C0RST_Pos ) /*!< Reset I2C0 */
+#define I2C1_RST ((0x4<<24) | SYS_IPRST1_I2C1RST_Pos ) /*!< Reset I2C1 */
+#define SPI0_RST ((0x4<<24) | SYS_IPRST1_SPI0RST_Pos ) /*!< Reset SPI0 */
+#define SPI1_RST ((0x4<<24) | SYS_IPRST1_SPI1RST_Pos ) /*!< Reset SPI1 */
+#define SPI2_RST ((0x4<<24) | SYS_IPRST1_SPI2RST_Pos ) /*!< Reset SPI2 */
+#define UART0_RST ((0x4<<24) | SYS_IPRST1_UART0RST_Pos ) /*!< Reset UART0 */
+#define UART1_RST ((0x4<<24) | SYS_IPRST1_UART1RST_Pos ) /*!< Reset UART1 */
+#define UART2_RST ((0x4<<24) | SYS_IPRST1_UART2RST_Pos ) /*!< Reset UART2 */
+#define UART3_RST ((0x4<<24) | SYS_IPRST1_UART3RST_Pos ) /*!< Reset UART3 */
+#define CAN0_RST ((0x4<<24) | SYS_IPRST1_CAN0RST_Pos ) /*!< Reset CAN0 */
+#define OTG_RST ((0x4<<24) | SYS_IPRST1_OTGRST_Pos ) /*!< Reset OTG */
+#define USBD_RST ((0x4<<24) | SYS_IPRST1_USBDRST_Pos ) /*!< Reset USBD */
+#define EADC_RST ((0x4<<24) | SYS_IPRST1_EADCRST_Pos ) /*!< Reset EADC */
+
+#define SC0_RST ((0x8<<24) | SYS_IPRST2_SC0RST_Pos ) /*!< Reset SC0 */
+#define DAC_RST ((0x8<<24) | SYS_IPRST2_DACRST_Pos ) /*!< Reset DAC */
+#define PWM0_RST ((0x8<<24) | SYS_IPRST2_PWM0RST_Pos ) /*!< Reset PWM0 */
+#define PWM1_RST ((0x8<<24) | SYS_IPRST2_PWM1RST_Pos ) /*!< Reset PWM1 */
+#define TK_RST ((0x8<<24) | SYS_IPRST2_TKRST_Pos ) /*!< Reset TK */
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Brown Out Detector Threshold Voltage Selection constant definitions. */
+/*---------------------------------------------------------------------------------------------------------*/
+#define SYS_BODCTL_BOD_RST_EN (1UL<GPA_MFPL = (SYS->GPA_MFPL & (~SYS_GPA_MFPL_PA0MFP_Msk) ) | SYS_GPA_MFPL_PA0_MFP_SC0_CLK ;
+
+*/
+//PA0 MFP
+#define SYS_GPA_MFPL_PA0MFP_GPIO (0ul << SYS_GPA_MFPL_PA0MFP_Pos) /*!< GPA_MFPL PA0 setting for GPIO*/
+#define SYS_GPA_MFPL_PA0MFP_UART1_nCTS (1ul << SYS_GPA_MFPL_PA0MFP_Pos) /*!< GPA_MFPL PA0 setting for UART1_nCTS*/
+#define SYS_GPA_MFPL_PA0MFP_UART1_TXD (3ul << SYS_GPA_MFPL_PA0MFP_Pos) /*!< GPA_MFPL PA0 setting for UART1_TXD*/
+#define SYS_GPA_MFPL_PA0MFP_CAN0_RXD (4ul << SYS_GPA_MFPL_PA0MFP_Pos) /*!< GPA_MFPL PA0 setting for CAN0_RXD*/
+#define SYS_GPA_MFPL_PA0MFP_SC0_CLK (5ul << SYS_GPA_MFPL_PA0MFP_Pos) /*!< GPA_MFPL PA0 setting for SC0_CLK*/
+#define SYS_GPA_MFPL_PA0MFP_PWM1_CH5 (6ul << SYS_GPA_MFPL_PA0MFP_Pos) /*!< GPA_MFPL PA0 setting for PWM1_CH5*/
+#define SYS_GPA_MFPL_PA0MFP_EBI_AD0 (7ul << SYS_GPA_MFPL_PA0MFP_Pos) /*!< GPA_MFPL PA0 setting for EBI_AD0*/
+#define SYS_GPA_MFPL_PA0MFP_INT0 (8ul << SYS_GPA_MFPL_PA0MFP_Pos) /*!< GPA_MFPL PA0 setting for INT0*/
+#define SYS_GPA_MFPL_PA0MFP_SPI1_I2SMCLK (9ul << SYS_GPA_MFPL_PA0MFP_Pos) /*!< GPA_MFPL PA0 setting for SPI1_I2SMCLK*/
+
+//PA1 MFP
+#define SYS_GPA_MFPL_PA1MFP_GPIO (0ul << SYS_GPA_MFPL_PA1MFP_Pos) /*!< GPA_MFPL PA1 setting for GPIO*/
+#define SYS_GPA_MFPL_PA1MFP_UART1_nRTS (1ul << SYS_GPA_MFPL_PA1MFP_Pos) /*!< GPA_MFPL PA1 setting for UART1_nRTS*/
+#define SYS_GPA_MFPL_PA1MFP_UART1_RXD (3ul << SYS_GPA_MFPL_PA1MFP_Pos) /*!< GPA_MFPL PA1 setting for UART1_RXD*/
+#define SYS_GPA_MFPL_PA1MFP_CAN0_TXD (4ul << SYS_GPA_MFPL_PA1MFP_Pos) /*!< GPA_MFPL PA1 setting for CAN0_TXD*/
+#define SYS_GPA_MFPL_PA1MFP_SC0_DAT (5ul << SYS_GPA_MFPL_PA1MFP_Pos) /*!< GPA_MFPL PA1 setting for SC0_DAT*/
+#define SYS_GPA_MFPL_PA1MFP_PWM1_CH4 (6ul << SYS_GPA_MFPL_PA1MFP_Pos) /*!< GPA_MFPL PA1 setting for PWM1_CH4*/
+#define SYS_GPA_MFPL_PA1MFP_EBI_AD1 (7ul << SYS_GPA_MFPL_PA1MFP_Pos) /*!< GPA_MFPL PA1 setting for EBI_AD1*/
+#define SYS_GPA_MFPL_PA1MFP_STADC (10ul << SYS_GPA_MFPL_PA1MFP_Pos) /*!< GPA_MFPL PA1 setting for STADC*/
+
+//PA2 MFP
+#define SYS_GPA_MFPL_PA2MFP_GPIO (0ul << SYS_GPA_MFPL_PA2MFP_Pos) /*!< GPA_MFPL PA2 setting for GPIO*/
+#define SYS_GPA_MFPL_PA2MFP_USB_VBUS_EN (1ul << SYS_GPA_MFPL_PA2MFP_Pos) /*!< GPA_MFPL PA2 setting for USB_VBUS_EN*/
+#define SYS_GPA_MFPL_PA2MFP_UART0_TXD (2ul << SYS_GPA_MFPL_PA2MFP_Pos) /*!< GPA_MFPL PA2 setting for UART0_TXD*/
+#define SYS_GPA_MFPL_PA2MFP_UART0_nCTS (3ul << SYS_GPA_MFPL_PA2MFP_Pos) /*!< GPA_MFPL PA2 setting for UART0_nCTS*/
+#define SYS_GPA_MFPL_PA2MFP_I2C0_SDA (4ul << SYS_GPA_MFPL_PA2MFP_Pos) /*!< GPA_MFPL PA2 setting for I2C0_SDA*/
+#define SYS_GPA_MFPL_PA2MFP_SC0_RST (5ul << SYS_GPA_MFPL_PA2MFP_Pos) /*!< GPA_MFPL PA2 setting for SC0_RST*/
+#define SYS_GPA_MFPL_PA2MFP_PWM1_CH3 (6ul << SYS_GPA_MFPL_PA2MFP_Pos) /*!< GPA_MFPL PA2 setting for PWM1_CH3*/
+#define SYS_GPA_MFPL_PA2MFP_EBI_AD2 (7ul << SYS_GPA_MFPL_PA2MFP_Pos) /*!< GPA_MFPL PA2 setting for EBI_AD2*/
+
+//PA3 MFP
+#define SYS_GPA_MFPL_PA3MFP_GPIO (0ul << SYS_GPA_MFPL_PA3MFP_Pos) /*!< GPA_MFPL PA3 setting for GPIO*/
+#define SYS_GPA_MFPL_PA3MFP_USB_VBUS_ST (1ul << SYS_GPA_MFPL_PA3MFP_Pos) /*!< GPA_MFPL PA3 setting for USB_VBUS_ST*/
+#define SYS_GPA_MFPL_PA3MFP_UART0_RXD (2ul << SYS_GPA_MFPL_PA3MFP_Pos) /*!< GPA_MFPL PA3 setting for UART0_RXD*/
+#define SYS_GPA_MFPL_PA3MFP_UART0_nRTS (3ul << SYS_GPA_MFPL_PA3MFP_Pos) /*!< GPA_MFPL PA3 setting for UART0_nRTS*/
+#define SYS_GPA_MFPL_PA3MFP_I2C0_SCL (4ul << SYS_GPA_MFPL_PA3MFP_Pos) /*!< GPA_MFPL PA3 setting for I2C0_SCL*/
+#define SYS_GPA_MFPL_PA3MFP_SC0_PWR (5ul << SYS_GPA_MFPL_PA3MFP_Pos) /*!< GPA_MFPL PA3 setting for SC0_PWR*/
+#define SYS_GPA_MFPL_PA3MFP_PWM1_CH2 (6ul << SYS_GPA_MFPL_PA3MFP_Pos) /*!< GPA_MFPL PA3 setting for PWM1_CH2*/
+#define SYS_GPA_MFPL_PA3MFP_EBI_AD3 (7ul << SYS_GPA_MFPL_PA3MFP_Pos) /*!< GPA_MFPL PA3 setting for EBI_AD3*/
+
+//PA4 MFP
+#define SYS_GPA_MFPL_PA4MFP_GPIO (0ul << SYS_GPA_MFPL_PA4MFP_Pos) /*!< GPA_MFPL PA4 setting for GPIO*/
+#define SYS_GPA_MFPL_PA4MFP_SPI1_SS (2ul << SYS_GPA_MFPL_PA4MFP_Pos) /*!< GPA_MFPL PA4 setting for SPI1_SS*/
+#define SYS_GPA_MFPL_PA4MFP_EBI_AD4 (7ul << SYS_GPA_MFPL_PA4MFP_Pos) /*!< GPA_MFPL PA4 setting for EBI_AD4*/
+
+//PA5 MFP
+#define SYS_GPA_MFPL_PA5MFP_GPIO (0ul << SYS_GPA_MFPL_PA5MFP_Pos) /*!< GPA_MFPL PA5 setting for GPIO*/
+#define SYS_GPA_MFPL_PA5MFP_SPI1_MOSI (2ul << SYS_GPA_MFPL_PA5MFP_Pos) /*!< GPA_MFPL PA5 setting for SPI1_MOSI*/
+#define SYS_GPA_MFPL_PA5MFP_T2_EXT (3ul << SYS_GPA_MFPL_PA5MFP_Pos) /*!< GPA_MFPL PA5 setting for T2_EXT*/
+#define SYS_GPA_MFPL_PA5MFP_EBI_AD5 (7ul << SYS_GPA_MFPL_PA5MFP_Pos) /*!< GPA_MFPL PA5 setting for EBI_AD5*/
+
+//PA6 MFP
+#define SYS_GPA_MFPL_PA6MFP_GPIO (0ul << SYS_GPA_MFPL_PA6MFP_Pos) /*!< GPA_MFPL PA6 setting for GPIO*/
+#define SYS_GPA_MFPL_PA6MFP_SPI1_MISO (2ul << SYS_GPA_MFPL_PA6MFP_Pos) /*!< GPA_MFPL PA6 setting for SPI1_MISO*/
+#define SYS_GPA_MFPL_PA6MFP_T1_EXT (3ul << SYS_GPA_MFPL_PA6MFP_Pos) /*!< GPA_MFPL PA6 setting for T1_EXT*/
+#define SYS_GPA_MFPL_PA6MFP_EBI_AD6 (7ul << SYS_GPA_MFPL_PA6MFP_Pos) /*!< GPA_MFPL PA6 setting for EBI_AD6*/
+
+//PA7 MFP
+#define SYS_GPA_MFPL_PA7MFP_GPIO (0ul << SYS_GPA_MFPL_PA7MFP_Pos) /*!< GPA_MFPL PA7 setting for GPIO*/
+#define SYS_GPA_MFPL_PA7MFP_SPI1_CLK (2ul << SYS_GPA_MFPL_PA7MFP_Pos) /*!< GPA_MFPL PA7 setting for SPI1_CLK*/
+#define SYS_GPA_MFPL_PA7MFP_T0_EXT (3ul << SYS_GPA_MFPL_PA7MFP_Pos) /*!< GPA_MFPL PA7 setting for T0_EXT*/
+#define SYS_GPA_MFPL_PA7MFP_EBI_AD7 (7ul << SYS_GPA_MFPL_PA7MFP_Pos) /*!< GPA_MFPL PA7 setting for EBI_AD7*/
+
+//PA8 MFP
+#define SYS_GPA_MFPH_PA8MFP_GPIO (0ul << SYS_GPA_MFPH_PA8MFP_Pos) /*!< GPA_MFPH PA8 setting for GPIO*/
+#define SYS_GPA_MFPH_PA8MFP_UART3_TXD (3ul << SYS_GPA_MFPH_PA8MFP_Pos) /*!< GPA_MFPH PA8 setting for UART3_TXD*/
+
+//PA9 MFP
+#define SYS_GPA_MFPH_PA9MFP_GPIO (0ul << SYS_GPA_MFPH_PA9MFP_Pos) /*!< GPA_MFPH PA9 setting for GPIO*/
+#define SYS_GPA_MFPH_PA9MFP_UART3_RXD (3ul << SYS_GPA_MFPH_PA9MFP_Pos) /*!< GPA_MFPH PA9 setting for UART3_RXD*/
+
+//PA10 MFP
+#define SYS_GPA_MFPH_PA10MFP_GPIO (0ul << SYS_GPA_MFPH_PA10MFP_Pos) /*!< GPA_MFPH PA10 setting for GPIO*/
+#define SYS_GPA_MFPH_PA10MFP_UART3_nCTS (3ul << SYS_GPA_MFPH_PA10MFP_Pos) /*!< GPA_MFPH PA10 setting for UART3_nCTS*/
+
+//PA11 MFP
+#define SYS_GPA_MFPH_PA11MFP_GPIO (0ul << SYS_GPA_MFPH_PA11MFP_Pos) /*!< GPA_MFPH PA11 setting for GPIO*/
+#define SYS_GPA_MFPH_PA11MFP_UART3_nRTS (3ul << SYS_GPA_MFPH_PA11MFP_Pos) /*!< GPA_MFPH PA11 setting for UART3_nRTS*/
+
+//PA12 MFP
+#define SYS_GPA_MFPH_PA12MFP_GPIO (0ul << SYS_GPA_MFPH_PA12MFP_Pos) /*!< GPA_MFPH PA12 setting for GPIO*/
+#define SYS_GPA_MFPH_PA12MFP_SPI1_I2SMCLK (2ul << SYS_GPA_MFPH_PA12MFP_Pos) /*!< GPA_MFPH PA12 setting for SPI1_I2SMCLK*/
+#define SYS_GPA_MFPH_PA12MFP_CAN0_TXD (4ul << SYS_GPA_MFPH_PA12MFP_Pos) /*!< GPA_MFPH PA12 setting for CAN0_TXD*/
+
+//PA13 MFP
+#define SYS_GPA_MFPH_PA13MFP_GPIO (0ul << SYS_GPA_MFPH_PA13MFP_Pos) /*!< GPA_MFPH PA13 setting for GPIO*/
+#define SYS_GPA_MFPH_PA13MFP_CAN0_RXD (4ul << SYS_GPA_MFPH_PA13MFP_Pos) /*!< GPA_MFPH PA13 setting for CAN0_RXD*/
+
+//PA14 MFP
+#define SYS_GPA_MFPH_PA14MFP_GPIO (0ul << SYS_GPA_MFPH_PA14MFP_Pos) /*!< GPA_MFPH PA14 setting for GPIO*/
+#define SYS_GPA_MFPH_PA14MFP_UART2_nCTS (3ul << SYS_GPA_MFPH_PA14MFP_Pos) /*!< GPA_MFPH PA14 setting for UART2_nCTS*/
+#define SYS_GPA_MFPH_PA14MFP_I2C0_SMBAL (4ul << SYS_GPA_MFPH_PA14MFP_Pos) /*!< GPA_MFPH PA14 setting for I2C0_SMBAL*/
+
+//PA15 MFP
+#define SYS_GPA_MFPH_PA15MFP_GPIO (0ul << SYS_GPA_MFPH_PA15MFP_Pos) /*!< GPA_MFPH PA15 setting for GPIO*/
+#define SYS_GPA_MFPH_PA15MFP_UART2_nRTS (3ul << SYS_GPA_MFPH_PA15MFP_Pos) /*!< GPA_MFPH PA15 setting for UART2_nRTS*/
+#define SYS_GPA_MFPH_PA15MFP_I2C0_SMBSUS (4ul << SYS_GPA_MFPH_PA15MFP_Pos) /*!< GPA_MFPH PA15 setting for I2C0_SMBSUS*/
+
+//PB0 MFP
+#define SYS_GPB_MFPL_PB0MFP_GPIO (0ul << SYS_GPB_MFPL_PB0MFP_Pos) /*!< GPB_MFPL PB0 setting for GPIO*/
+#define SYS_GPB_MFPL_PB0MFP_EADC_CH0 (1ul << SYS_GPB_MFPL_PB0MFP_Pos) /*!< GPB_MFPL PB0 setting for EADC_CH0*/
+#define SYS_GPB_MFPL_PB0MFP_SPI0_MOSI1 (2ul << SYS_GPB_MFPL_PB0MFP_Pos) /*!< GPB_MFPL PB0 setting for SPI0_MOSI1*/
+#define SYS_GPB_MFPL_PB0MFP_UART2_RXD (3ul << SYS_GPB_MFPL_PB0MFP_Pos) /*!< GPB_MFPL PB0 setting for UART2_RXD*/
+#define SYS_GPB_MFPL_PB0MFP_T2 (4ul << SYS_GPB_MFPL_PB0MFP_Pos) /*!< GPB_MFPL PB0 setting for T2*/
+#define SYS_GPB_MFPL_PB0MFP_DAC (5ul << SYS_GPB_MFPL_PB0MFP_Pos) /*!< GPB_MFPL PB0 setting for DAC*/
+#define SYS_GPB_MFPL_PB0MFP_EBI_nWRL (7ul << SYS_GPB_MFPL_PB0MFP_Pos) /*!< GPB_MFPL PB0 setting for EBI_nWRL*/
+#define SYS_GPB_MFPL_PB0MFP_INT1 (8ul << SYS_GPB_MFPL_PB0MFP_Pos) /*!< GPB_MFPL PB0 setting for INT1*/
+
+//PB1 MFP
+#define SYS_GPB_MFPL_PB1MFP_GPIO (0ul << SYS_GPB_MFPL_PB1MFP_Pos) /*!< GPB_MFPL PB1 setting for GPIO*/
+#define SYS_GPB_MFPL_PB1MFP_EADC_CH1 (1ul << SYS_GPB_MFPL_PB1MFP_Pos) /*!< GPB_MFPL PB1 setting for EADC_CH1*/
+#define SYS_GPB_MFPL_PB1MFP_SPI0_MISO1 (2ul << SYS_GPB_MFPL_PB1MFP_Pos) /*!< GPB_MFPL PB1 setting for SPI0_MISO1*/
+#define SYS_GPB_MFPL_PB1MFP_UART2_TXD (3ul << SYS_GPB_MFPL_PB1MFP_Pos) /*!< GPB_MFPL PB1 setting for UART2_TXD*/
+#define SYS_GPB_MFPL_PB1MFP_T3 (4ul << SYS_GPB_MFPL_PB1MFP_Pos) /*!< GPB_MFPL PB1 setting for T3*/
+#define SYS_GPB_MFPL_PB1MFP_SC0_RST (5ul << SYS_GPB_MFPL_PB1MFP_Pos) /*!< GPB_MFPL PB1 setting for SC0_RST*/
+#define SYS_GPB_MFPL_PB1MFP_PWM0_SYNC_OUT (6ul << SYS_GPB_MFPL_PB1MFP_Pos) /*!< GPB_MFPL PB1 setting for PWM0_SYNC_OUT*/
+#define SYS_GPB_MFPL_PB1MFP_EBI_nWRH (7ul << SYS_GPB_MFPL_PB1MFP_Pos) /*!< GPB_MFPL PB1 setting for EBI_nWRH*/
+
+//PB2 MFP
+#define SYS_GPB_MFPL_PB2MFP_GPIO (0ul << SYS_GPB_MFPL_PB2MFP_Pos) /*!< GPB_MFPL PB2 setting for GPIO*/
+#define SYS_GPB_MFPL_PB2MFP_EADC_CH2 (1ul << SYS_GPB_MFPL_PB2MFP_Pos) /*!< GPB_MFPL PB2 setting for EADC_CH2*/
+#define SYS_GPB_MFPL_PB2MFP_SPI0_CLK (2ul << SYS_GPB_MFPL_PB2MFP_Pos) /*!< GPB_MFPL PB2 setting for SPI0_CLK*/
+#define SYS_GPB_MFPL_PB2MFP_SPI1_CLK (3ul << SYS_GPB_MFPL_PB2MFP_Pos) /*!< GPB_MFPL PB2 setting for SPI1_CLK*/
+#define SYS_GPB_MFPL_PB2MFP_UART1_RXD (4ul << SYS_GPB_MFPL_PB2MFP_Pos) /*!< GPB_MFPL PB2 setting for UART1_RXD*/
+#define SYS_GPB_MFPL_PB2MFP_SC0_CD (5ul << SYS_GPB_MFPL_PB2MFP_Pos) /*!< GPB_MFPL PB2 setting for SC0_CD*/
+#define SYS_GPB_MFPL_PB2MFP_UART3_RXD (9ul << SYS_GPB_MFPL_PB2MFP_Pos) /*!< GPB_MFPL PB2 setting for UART3_RXD*/
+#define SYS_GPB_MFPL_PB2MFP_T2_EXT (11ul << SYS_GPB_MFPL_PB2MFP_Pos) /*!< GPB_MFPL PB2 setting for T2_EXT*/
+
+//PB3
+#define SYS_GPB_MFPL_PB3MFP_GPIO (0ul << SYS_GPB_MFPL_PB3MFP_Pos) /*!< GPB_MFPL PB3 setting for GPIO*/
+#define SYS_GPB_MFPL_PB3MFP_EADC_CH3 (1ul << SYS_GPB_MFPL_PB3MFP_Pos) /*!< GPB_MFPL PB3 setting for EADC_CH3*/
+#define SYS_GPB_MFPL_PB3MFP_SPI0_MISO0 (2ul << SYS_GPB_MFPL_PB3MFP_Pos) /*!< GPB_MFPL PB3 setting for SPI0_MISO0*/
+#define SYS_GPB_MFPL_PB3MFP_SPI1_MISO (3ul << SYS_GPB_MFPL_PB3MFP_Pos) /*!< GPB_MFPL PB3 setting for SPI1_MISO*/
+#define SYS_GPB_MFPL_PB3MFP_UART1_TXD (4ul << SYS_GPB_MFPL_PB3MFP_Pos) /*!< GPB_MFPL PB3 setting for UART1_TXD*/
+#define SYS_GPB_MFPL_PB3MFP_UART3_TXD (9ul << SYS_GPB_MFPL_PB3MFP_Pos) /*!< GPB_MFPL PB3 setting for UART3_TXD*/
+#define SYS_GPB_MFPL_PB3MFP_T0_EXT (11ul << SYS_GPB_MFPL_PB3MFP_Pos) /*!< GPB_MFPL PB3 setting for T0_EXT*/
+
+//PB4
+#define SYS_GPB_MFPL_PB4MFP_GPIO (0ul << SYS_GPB_MFPL_PB4MFP_Pos) /*!< GPB_MFPL PB4 setting for GPIO*/
+#define SYS_GPB_MFPL_PB4MFP_EADC_CH4 (1ul << SYS_GPB_MFPL_PB4MFP_Pos) /*!< GPB_MFPL PB4 setting for EADC_CH4*/
+#define SYS_GPB_MFPL_PB4MFP_SPI0_SS (2ul << SYS_GPB_MFPL_PB4MFP_Pos) /*!< GPB_MFPL PB4 setting for SPI0_SS*/
+#define SYS_GPB_MFPL_PB4MFP_SPI1_SS (3ul << SYS_GPB_MFPL_PB4MFP_Pos) /*!< GPB_MFPL PB4 setting for SPI1_SS*/
+#define SYS_GPB_MFPL_PB4MFP_UART1_nCTS (4ul << SYS_GPB_MFPL_PB4MFP_Pos) /*!< GPB_MFPL PB4 setting for UART1_nCTS*/
+#define SYS_GPB_MFPL_PB4MFP_ACMP0_N (5ul << SYS_GPB_MFPL_PB4MFP_Pos) /*!< GPB_MFPL PB4 setting for ACMP0_N*/
+#define SYS_GPB_MFPL_PB4MFP_EBI_AD7 (7ul << SYS_GPB_MFPL_PB4MFP_Pos) /*!< GPB_MFPL PB4 setting for EBI_AD7*/
+#define SYS_GPB_MFPL_PB4MFP_UART2_TXD (9ul << SYS_GPB_MFPL_PB4MFP_Pos) /*!< GPB_MFPL PB4 setting for UART2_TXD*/
+#define SYS_GPB_MFPL_PB4MFP_T1_EXT (11ul << SYS_GPB_MFPL_PB4MFP_Pos) /*!< GPB_MFPL PB4 setting for T1_EXT*/
+
+//PB5
+#define SYS_GPB_MFPL_PB5MFP_GPIO (0ul << SYS_GPB_MFPL_PB5MFP_Pos) /*!< GPB_MFPL PB5 setting for GPIO*/
+#define SYS_GPB_MFPL_PB5MFP_EADC_CH13 (1ul << SYS_GPB_MFPL_PB5MFP_Pos) /*!< GPB_MFPL PB5 setting for EADC_CH13*/
+#define SYS_GPB_MFPL_PB5MFP_SPI0_MOSI0 (2ul << SYS_GPB_MFPL_PB5MFP_Pos) /*!< GPB_MFPL PB5 setting for SPI0_MOSI0*/
+#define SYS_GPB_MFPL_PB5MFP_SPI1_MOSI (3ul << SYS_GPB_MFPL_PB5MFP_Pos) /*!< GPB_MFPL PB5 setting for SPI1_MOSI*/
+#define SYS_GPB_MFPL_PB5MFP_TK3 (4ul << SYS_GPB_MFPL_PB5MFP_Pos) /*!< GPB_MFPL PB5 setting for TK3*/
+#define SYS_GPB_MFPL_PB5MFP_ACMP0_P2 (5ul << SYS_GPB_MFPL_PB5MFP_Pos) /*!< GPB_MFPL PB5 setting for ACMP0_P2*/
+#define SYS_GPB_MFPL_PB5MFP_EBI_AD6 (7ul << SYS_GPB_MFPL_PB5MFP_Pos) /*!< GPB_MFPL PB5 setting for EBI_AD6*/
+#define SYS_GPB_MFPL_PB5MFP_UART2_RXD (9ul << SYS_GPB_MFPL_PB5MFP_Pos) /*!< GPB_MFPL PB5 setting for UART2_RXD*/
+
+//PB6
+#define SYS_GPB_MFPL_PB6MFP_GPIO (0ul << SYS_GPB_MFPL_PB6MFP_Pos) /*!< GPB_MFPL PB6 setting for GPIO*/
+#define SYS_GPB_MFPL_PB6MFP_EADC_CH14 (1ul << SYS_GPB_MFPL_PB6MFP_Pos) /*!< GPB_MFPL PB6 setting for EADC_CH14*/
+#define SYS_GPB_MFPL_PB6MFP_SPI0_MISO0 (2ul << SYS_GPB_MFPL_PB6MFP_Pos) /*!< GPB_MFPL PB6 setting for SPI0_MISO0*/
+#define SYS_GPB_MFPL_PB6MFP_SPI1_MISO (3ul << SYS_GPB_MFPL_PB6MFP_Pos) /*!< GPB_MFPL PB6 setting for SPI1_MISO*/
+#define SYS_GPB_MFPL_PB6MFP_TK4 (4ul << SYS_GPB_MFPL_PB6MFP_Pos) /*!< GPB_MFPL PB6 setting for TK4*/
+#define SYS_GPB_MFPL_PB6MFP_ACMP0_P1 (5ul << SYS_GPB_MFPL_PB6MFP_Pos) /*!< GPB_MFPL PB6 setting for ACMP0_P1*/
+#define SYS_GPB_MFPL_PB6MFP_EBI_AD5 (7ul << SYS_GPB_MFPL_PB6MFP_Pos) /*!< GPB_MFPL PB6 setting for EBI_AD5*/
+
+//PB7
+#define SYS_GPB_MFPL_PB7MFP_GPIO (0ul << SYS_GPB_MFPL_PB7MFP_Pos) /*!< GPB_MFPL PB7 setting for GPIO*/
+#define SYS_GPB_MFPL_PB7MFP_EADC_CH15 (1ul << SYS_GPB_MFPL_PB7MFP_Pos) /*!< GPB_MFPL PB7 setting for EADC_CH15*/
+#define SYS_GPB_MFPL_PB7MFP_SPI0_CLK (2ul << SYS_GPB_MFPL_PB7MFP_Pos) /*!< GPB_MFPL PB7 setting for SPI0_CLK*/
+#define SYS_GPB_MFPL_PB7MFP_SPI1_CLK (3ul << SYS_GPB_MFPL_PB7MFP_Pos) /*!< GPB_MFPL PB7 setting for SPI1_CLK*/
+#define SYS_GPB_MFPL_PB7MFP_TK5 (4ul << SYS_GPB_MFPL_PB7MFP_Pos) /*!< GPB_MFPL PB7 setting for TK5*/
+#define SYS_GPB_MFPL_PB7MFP_ACMP0_P0 (5ul << SYS_GPB_MFPL_PB7MFP_Pos) /*!< GPB_MFPL PB7 setting for ACMP0_P0*/
+#define SYS_GPB_MFPL_PB7MFP_EBI_AD4 (7ul << SYS_GPB_MFPL_PB7MFP_Pos) /*!< GPB_MFPL PB7 setting for EBI_AD4*/
+#define SYS_GPB_MFPL_PB7MFP_STADC (10ul << SYS_GPB_MFPL_PB7MFP_Pos) /*!< GPB_MFPL PB7 setting for STADC*/
+
+//PB8
+#define SYS_GPB_MFPH_PB8MFP_GPIO (0ul << SYS_GPB_MFPH_PB8MFP_Pos) /*!< GPB_MFPH PB8 setting for GPIO*/
+#define SYS_GPB_MFPH_PB8MFP_EADC_CH5 (1ul << SYS_GPB_MFPH_PB8MFP_Pos) /*!< GPB_MFPH PB8 setting for EADC_CH5*/
+#define SYS_GPB_MFPH_PB8MFP_UART1_nRTS (4ul << SYS_GPB_MFPH_PB8MFP_Pos) /*!< GPB_MFPH PB8 setting for UART1_nRTS*/
+#define SYS_GPB_MFPH_PB8MFP_PWM0_CH2 (6ul << SYS_GPB_MFPH_PB8MFP_Pos) /*!< GPB_MFPH PB8 setting for PWM0_CH2*/
+
+//PB9
+#define SYS_GPB_MFPH_PB9MFP_GPIO (0ul << SYS_GPB_MFPH_PB9MFP_Pos) /*!< GPB_MFPH PB9 setting for GPIO*/
+#define SYS_GPB_MFPH_PB9MFP_EADC_CH6 (1ul << SYS_GPB_MFPH_PB9MFP_Pos) /*!< GPB_MFPH PB9 setting for EADC_CH6*/
+
+//PB10
+#define SYS_GPB_MFPH_PB10MFP_GPIO (0ul << SYS_GPB_MFPH_PB10MFP_Pos) /*!< GPB_MFPH_ PB10 setting for GPIO*/
+#define SYS_GPB_MFPH_PB10MFP_EADC_CH7 (1ul << SYS_GPB_MFPH_PB10MFP_Pos) /*!< GPB_MFPH_ PB10 setting for EADC_CH7*/
+
+//PB11
+#define SYS_GPB_MFPH_PB11MFP_GPIO (0ul << SYS_GPB_MFPH_PB11MFP_Pos) /*!< GPB_MFPH_ PB11 setting for GPIO*/
+#define SYS_GPB_MFPH_PB11MFP_EADC_CH8 (1ul << SYS_GPB_MFPH_PB11MFP_Pos) /*!< GPB_MFPH_ PB11 setting for EADC_CH8*/
+#define SYS_GPB_MFPH_PB11MFP_TK0 (4ul << SYS_GPB_MFPH_PB11MFP_Pos) /*!< GPB_MFPH_ PB11 setting for TK0*/
+
+//PB12
+#define SYS_GPB_MFPH_PB12MFP_GPIO (0ul << SYS_GPB_MFPH_PB12MFP_Pos) /*!< GPB_MFPH_ PB12 setting for GPIO*/
+#define SYS_GPB_MFPH_PB12MFP_EADC_CH9 (1ul << SYS_GPB_MFPH_PB12MFP_Pos) /*!< GPB_MFPH_ PB12 setting for EADC_CH9*/
+#define SYS_GPB_MFPH_PB12MFP_TK1 (4ul << SYS_GPB_MFPH_PB12MFP_Pos) /*!< GPB_MFPH_ PB12 setting for TK1*/
+
+//PB13
+#define SYS_GPB_MFPH_PB13MFP_GPIO (0ul << SYS_GPB_MFPH_PB13MFP_Pos) /*!< GPB_MFPH PB13 setting for GPIO*/
+#define SYS_GPB_MFPH_PB13MFP_EADC_CH10 (1ul << SYS_GPB_MFPH_PB13MFP_Pos) /*!< GPB_MFPH PB13 setting for EADC_CH10*/
+
+//PB14
+#define SYS_GPB_MFPH_PB14MFP_GPIO (0ul << SYS_GPB_MFPH_PB14MFP_Pos) /*!< GPB_MFPH PB14 setting for GPIO*/
+#define SYS_GPB_MFPH_PB14MFP_EADC_CH11 (1ul << SYS_GPB_MFPH_PB14MFP_Pos) /*!< GPB_MFPH PB14 setting for EADC_CH11*/
+
+//PB15
+#define SYS_GPB_MFPH_PB15MFP_GPIO (0ul << SYS_GPB_MFPH_PB15MFP_Pos) /*!< GPB_MFPH PB15 setting for GPIO*/
+#define SYS_GPB_MFPH_PB15MFP_EADC_CH12 (1ul << SYS_GPB_MFPH_PB15MFP_Pos) /*!< GPB_MFPH PB15 setting for EADC_CH12*/
+#define SYS_GPB_MFPH_PB15MFP_TK2 (4ul << SYS_GPB_MFPH_PB15MFP_Pos) /*!< GPB_MFPH PB15 setting for TK2*/
+#define SYS_GPB_MFPH_PB15MFP_ACMP0_P3 (5ul << SYS_GPB_MFPH_PB15MFP_Pos) /*!< GPB_MFPH PB15 setting for ACMP0_P3*/
+#define SYS_GPB_MFPH_PB15MFP_EBI_nCS1 (7ul << SYS_GPB_MFPH_PB15MFP_Pos) /*!< GPB_MFPH PB15 setting for EBI_nCS1*/
+
+//PC0
+#define SYS_GPC_MFPL_PC0MFP_GPIO (0ul << SYS_GPC_MFPL_PC0MFP_Pos) /*!< GPC_MFPL PC0 setting for GPIO*/
+#define SYS_GPC_MFPL_PC0MFP_SPI2_CLK (2ul << SYS_GPC_MFPL_PC0MFP_Pos) /*!< GPC_MFPL PC0 setting for SPI2_CLK*/
+#define SYS_GPC_MFPL_PC0MFP_UART2_nCTS (3ul << SYS_GPC_MFPL_PC0MFP_Pos) /*!< GPC_MFPL PC0 setting for UART2_nCTS*/
+#define SYS_GPC_MFPL_PC0MFP_CAN0_TXD (4ul << SYS_GPC_MFPL_PC0MFP_Pos) /*!< GPC_MFPL PC0 setting for CAN0_TXD*/
+#define SYS_GPC_MFPL_PC0MFP_PWM0_CH0 (6ul << SYS_GPC_MFPL_PC0MFP_Pos) /*!< GPC_MFPL PC0 setting for PWM0_CH0*/
+#define SYS_GPC_MFPL_PC0MFP_EBI_AD8 (7ul << SYS_GPC_MFPL_PC0MFP_Pos) /*!< GPC_MFPL PC0 setting for EBI_AD8*/
+#define SYS_GPC_MFPL_PC0MFP_INT2 (8ul << SYS_GPC_MFPL_PC0MFP_Pos) /*!< GPC_MFPL PC0 setting for INT2*/
+#define SYS_GPC_MFPL_PC0MFP_UART3_TXD (9ul << SYS_GPC_MFPL_PC0MFP_Pos) /*!< GPC_MFPL PC0 setting for UART3_TXD*/
+#define SYS_GPC_MFPL_PC0MFP_T3_EXT (11ul << SYS_GPC_MFPL_PC0MFP_Pos) /*!< GPC_MFPL PC0 setting for T3_EXT*/
+
+//PC1
+#define SYS_GPC_MFPL_PC1MFP_GPIO (0ul << SYS_GPC_MFPL_PC1MFP_Pos) /*!< GPC_MFPL PC1 setting for GPIO*/
+#define SYS_GPC_MFPL_PC1MFP_CLKO (1ul << SYS_GPC_MFPL_PC1MFP_Pos) /*!< GPC_MFPL PC1 setting for CLKO*/
+#define SYS_GPC_MFPL_PC1MFP_STDAC (2ul << SYS_GPC_MFPL_PC1MFP_Pos) /*!< GPC_MFPL PC1 setting for STDAC*/
+#define SYS_GPC_MFPL_PC1MFP_UART2_nRTS (3ul << SYS_GPC_MFPL_PC1MFP_Pos) /*!< GPC_MFPL PC1 setting for UART2_nRTS*/
+#define SYS_GPC_MFPL_PC1MFP_CAN0_RXD (4ul << SYS_GPC_MFPL_PC1MFP_Pos) /*!< GPC_MFPL PC1 setting for CAN0_RXD*/
+#define SYS_GPC_MFPL_PC1MFP_PWM0_CH1 (6ul << SYS_GPC_MFPL_PC1MFP_Pos) /*!< GPC_MFPL PC1 setting for PWM0_CH1*/
+#define SYS_GPC_MFPL_PC1MFP_EBI_AD9 (7ul << SYS_GPC_MFPL_PC1MFP_Pos) /*!< GPC_MFPL PC1 setting for EBI_AD9*/
+#define SYS_GPC_MFPL_PC1MFP_UART3_RXD (9ul << SYS_GPC_MFPL_PC1MFP_Pos) /*!< GPC_MFPL PC1 setting for UART3_RXD*/
+
+//PC2
+#define SYS_GPC_MFPL_PC2MFP_GPIO (0ul << SYS_GPC_MFPL_PC2MFP_Pos) /*!< GPC_MFPL PC2 setting for GPIO*/
+#define SYS_GPC_MFPL_PC2MFP_SPI2_SS (2ul << SYS_GPC_MFPL_PC2MFP_Pos) /*!< GPC_MFPL PC2 setting for SPI2_SS*/
+#define SYS_GPC_MFPL_PC2MFP_UART2_TXD (3ul << SYS_GPC_MFPL_PC2MFP_Pos) /*!< GPC_MFPL PC2 setting for UART2_TXD*/
+#define SYS_GPC_MFPL_PC2MFP_ACMP1_O (5ul << SYS_GPC_MFPL_PC2MFP_Pos) /*!< GPC_MFPL PC2 setting for ACMP1_O*/
+#define SYS_GPC_MFPL_PC2MFP_PWM0_CH2 (6ul << SYS_GPC_MFPL_PC2MFP_Pos) /*!< GPC_MFPL PC2 setting for PWM0_CH2*/
+#define SYS_GPC_MFPL_PC2MFP_EBI_AD10 (7ul << SYS_GPC_MFPL_PC2MFP_Pos) /*!< GPC_MFPL PC2 setting for EBI_AD10*/
+
+//PC3
+#define SYS_GPC_MFPL_PC3MFP_GPIO (0ul << SYS_GPC_MFPL_PC3MFP_Pos) /*!< GPC_MFPL PC3 setting for GPIO*/
+#define SYS_GPC_MFPL_PC3MFP_SPI2_MOSI (2ul << SYS_GPC_MFPL_PC3MFP_Pos) /*!< GPC_MFPL PC3 setting for SPI2_MOSI*/
+#define SYS_GPC_MFPL_PC3MFP_UART2_RXD (3ul << SYS_GPC_MFPL_PC3MFP_Pos) /*!< GPC_MFPL PC3 setting for UART2_RXD*/
+#define SYS_GPC_MFPL_PC3MFP_USB_VBUS_ST (4ul << SYS_GPC_MFPL_PC3MFP_Pos) /*!< GPC_MFPL PC3 setting for USB_VBUS_ST*/
+#define SYS_GPC_MFPL_PC3MFP_PWM0_CH3 (6ul << SYS_GPC_MFPL_PC3MFP_Pos) /*!< GPC_MFPL PC3 setting for PWM0_CH3*/
+#define SYS_GPC_MFPL_PC3MFP_EBI_AD11 (7ul << SYS_GPC_MFPL_PC3MFP_Pos) /*!< GPC_MFPL PC3 setting for EBI_AD11*/
+
+//PC4
+#define SYS_GPC_MFPL_PC4MFP_GPIO (0ul << SYS_GPC_MFPL_PC4MFP_Pos) /*!< GPC_MFPL PC4 setting for GPIO*/
+#define SYS_GPC_MFPL_PC4MFP_SPI2_MISO (2ul << SYS_GPC_MFPL_PC4MFP_Pos) /*!< GPC_MFPL PC4 setting for SPI2_MISO*/
+#define SYS_GPC_MFPL_PC4MFP_I2C1_SCL (3ul << SYS_GPC_MFPL_PC4MFP_Pos) /*!< GPC_MFPL PC4 setting for I2C1_SCL*/
+#define SYS_GPC_MFPL_PC4MFP_USB_VBUS_EN (4ul << SYS_GPC_MFPL_PC4MFP_Pos) /*!< GPC_MFPL PC4 setting for USB_VBUS_EN*/
+#define SYS_GPC_MFPL_PC4MFP_PWM0_CH4 (6ul << SYS_GPC_MFPL_PC4MFP_Pos) /*!< GPC_MFPL PC4 setting for PWM0_CH4*/
+#define SYS_GPC_MFPL_PC4MFP_EBI_AD12 (7ul << SYS_GPC_MFPL_PC4MFP_Pos) /*!< GPC_MFPL PC4 setting for EBI_AD12*/
+
+//PC5
+#define SYS_GPC_MFPL_PC5MFP_GPIO (0ul << SYS_GPC_MFPL_PC5MFP_Pos) /*!< GPC_MFPL PC5 setting for GPIO*/
+#define SYS_GPC_MFPL_PC5MFP_SPI2_I2SMCLK (2ul << SYS_GPC_MFPL_PC5MFP_Pos) /*!< GPC_MFPL PC5 setting for SPI2_I2SMCLK*/
+#define SYS_GPC_MFPL_PC5MFP_PWM0_CH5 (6ul << SYS_GPC_MFPL_PC5MFP_Pos) /*!< GPC_MFPL PC5 setting for PWM0_CH5*/
+#define SYS_GPC_MFPL_PC5MFP_EBI_AD13 (7ul << SYS_GPC_MFPL_PC5MFP_Pos) /*!< GPC_MFPL PC5 setting for EBI_AD13*/
+
+//PC6
+#define SYS_GPC_MFPL_PC6MFP_GPIO (0ul << SYS_GPC_MFPL_PC6MFP_Pos) /*!< GPC_MFPL PC6 setting for GPIO*/
+#define SYS_GPC_MFPL_PC6MFP_I2C1_SMBAL (3ul << SYS_GPC_MFPL_PC6MFP_Pos) /*!< GPC_MFPL PC6 setting for I2C1_SMBAL*/
+#define SYS_GPC_MFPL_PC6MFP_ACMP1_O (5ul << SYS_GPC_MFPL_PC6MFP_Pos) /*!< GPC_MFPL PC6 setting for ACMP1_O*/
+#define SYS_GPC_MFPL_PC6MFP_PWM1_CH0 (6ul << SYS_GPC_MFPL_PC6MFP_Pos) /*!< GPC_MFPL PC6 setting for PWM1_CH0*/
+#define SYS_GPC_MFPL_PC6MFP_EBI_AD14 (7ul << SYS_GPC_MFPL_PC6MFP_Pos) /*!< GPC_MFPL PC6 setting for EBI_AD14*/
+#define SYS_GPC_MFPL_PC6MFP_UART0_TXD (9ul << SYS_GPC_MFPL_PC6MFP_Pos) /*!< GPC_MFPL PC6 setting for UART0_TXD*/
+
+//PC7
+#define SYS_GPC_MFPL_PC7MFP_GPIO (0ul << SYS_GPC_MFPL_PC7MFP_Pos) /*!< GPC_MFPL PC7 setting for GPIO*/
+#define SYS_GPC_MFPL_PC7MFP_I2C1_SMBSUS (3ul << SYS_GPC_MFPL_PC7MFP_Pos) /*!< GPC_MFPL PC7 setting for I2C1_SMBSUS*/
+#define SYS_GPC_MFPL_PC7MFP_PWM1_CH1 (6ul << SYS_GPC_MFPL_PC7MFP_Pos) /*!< GPC_MFPL PC7 setting for PWM1_CH1*/
+#define SYS_GPC_MFPL_PC7MFP_EBI_AD15 (7ul << SYS_GPC_MFPL_PC7MFP_Pos) /*!< GPC_MFPL PC7 setting for EBI_AD15*/
+#define SYS_GPC_MFPL_PC7MFP_UART0_RXD (9ul << SYS_GPC_MFPL_PC7MFP_Pos) /*!< GPC_MFPL PC7 setting for UART0_RXD*/
+
+//PC8
+#define SYS_GPC_MFPH_PC8MFP_GPIO (0ul << SYS_GPC_MFPH_PC8MFP_Pos) /*!< GPC_MFPH_ PC8 setting for GPIO*/
+#define SYS_GPC_MFPH_PC8MFP_TK7 (4ul << SYS_GPC_MFPH_PC8MFP_Pos) /*!< GPC_MFPH_ PC8 setting for TK7*/
+
+//PC9
+#define SYS_GPC_MFPH_PC9MFP_GPIO (0ul << SYS_GPC_MFPH_PC9MFP_Pos) /*!< GPC_MFPH PC9 setting for GPIO*/
+#define SYS_GPC_MFPH_PC9MFP_SPI2_I2SMCLK (2ul << SYS_GPC_MFPH_PC9MFP_Pos) /*!< GPC_MFPH PC9 setting for SPI2_I2SMCLK*/
+#define SYS_GPC_MFPH_PC9MFP_PWM1_CH0 (6ul << SYS_GPC_MFPH_PC9MFP_Pos) /*!< GPC_MFPH PC9 setting for PWM1_CH0*/
+
+//PC10
+#define SYS_GPC_MFPH_PC10MFP_GPIO (0ul << SYS_GPC_MFPH_PC10MFP_Pos) /*!< GPC_MFPH PC10 setting for GPIO*/
+#define SYS_GPC_MFPH_PC10MFP_SPI2_MOSI (2ul << SYS_GPC_MFPH_PC10MFP_Pos) /*!< GPC_MFPH PC10 setting for SPI2_MOSI*/
+#define SYS_GPC_MFPH_PC10MFP_PWM1_CH1 (6ul << SYS_GPC_MFPH_PC10MFP_Pos) /*!< GPC_MFPH PC10 setting for PWM1_CH1*/
+
+//PC11
+#define SYS_GPC_MFPH_PC11MFP_GPIO (0ul << SYS_GPC_MFPH_PC11MFP_Pos) /*!< GPC_MFPH PC11 setting for GPIO*/
+#define SYS_GPC_MFPH_PC11MFP_SPI2_MISO (2ul << SYS_GPC_MFPH_PC11MFP_Pos) /*!< GPC_MFPH PC11 setting for SPI2_MISO*/
+#define SYS_GPC_MFPH_PC11MFP_PWM1_CH2 (6ul << SYS_GPC_MFPH_PC11MFP_Pos) /*!< GPC_MFPH PC11 setting for PWM1_CH2*/
+
+//PC12
+#define SYS_GPC_MFPH_PC12MFP_GPIO (0ul << SYS_GPC_MFPH_PC12MFP_Pos) /*!< GPC_MFPH PC12 setting for GPIO*/
+#define SYS_GPC_MFPH_PC12MFP_SPI2_CLK (2ul << SYS_GPC_MFPH_PC12MFP_Pos) /*!< GPC_MFPH PC12 setting for SPI2_CLK*/
+#define SYS_GPC_MFPH_PC12MFP_PWM1_CH3 (6ul << SYS_GPC_MFPH_PC12MFP_Pos) /*!< GPC_MFPH PC12 setting for PWM1_CH3*/
+
+//PC13
+#define SYS_GPC_MFPH_PC13MFP_GPIO (0ul << SYS_GPC_MFPH_PC13MFP_Pos) /*!< GPC_MFPH PC13 setting for GPIO*/
+#define SYS_GPC_MFPH_PC13MFP_SPI2_SS (2ul << SYS_GPC_MFPH_PC13MFP_Pos) /*!< GPC_MFPH PC13 setting for SPI2_SS*/
+#define SYS_GPC_MFPH_PC13MFP_PWM1_CH4 (6ul << SYS_GPC_MFPH_PC13MFP_Pos) /*!< GPC_MFPH PC13 setting for PWM1_CH4*/
+
+//PC14
+#define SYS_GPC_MFPH_PC14MFP_GPIO (0ul << SYS_GPC_MFPH_PC14MFP_Pos) /*!< GPC_MFPH PC14 setting for GPIO*/
+#define SYS_GPC_MFPH_PC14MFP_PWM1_CH5 (6ul << SYS_GPC_MFPH_PC14MFP_Pos) /*!< GPC_MFPH PC14 setting for PWM1_CH5*/
+
+//PC15
+#define SYS_GPC_MFPH_PC15MFP_GPIO (0ul << SYS_GPC_MFPH_PC15MFP_Pos) /*!< GPC_MFPH PC15 setting for GPIO*/
+#define SYS_GPC_MFPH_PC15MFP_PWM1_CH0 (6ul << SYS_GPC_MFPH_PC15MFP_Pos) /*!< GPC_MFPH PC15 setting for PWM1_CH0*/
+
+//PD0
+#define SYS_GPD_MFPL_PD0MFP_GPIO (0ul << SYS_GPD_MFPL_PD0MFP_Pos) /*!< GPD_MFPL PD0 setting for GPIO*/
+#define SYS_GPD_MFPL_PD0MFP_EADC_CH6 (1ul << SYS_GPD_MFPL_PD0MFP_Pos) /*!< GPD_MFPL PD0 setting for EADC_CH6*/
+#define SYS_GPD_MFPL_PD0MFP_SPI1_I2SMCLK (2ul << SYS_GPD_MFPL_PD0MFP_Pos) /*!< GPD_MFPL PD0 setting for SPI1_I2SMCLK*/
+#define SYS_GPD_MFPL_PD0MFP_UART0_RXD (3ul << SYS_GPD_MFPL_PD0MFP_Pos) /*!< GPD_MFPL PD0 setting for UART0_RXD*/
+#define SYS_GPD_MFPL_PD0MFP_TK6 (4ul << SYS_GPD_MFPL_PD0MFP_Pos) /*!< GPD_MFPL PD0 setting for TK6*/
+#define SYS_GPD_MFPL_PD0MFP_ACMP1_N (5ul << SYS_GPD_MFPL_PD0MFP_Pos) /*!< GPD_MFPL PD0 setting for ACMP1_N*/
+#define SYS_GPD_MFPL_PD0MFP_INT3 (8ul << SYS_GPD_MFPL_PD0MFP_Pos) /*!< GPD_MFPL PD0 setting for INT3*/
+#define SYS_GPD_MFPL_PD0MFP_T3 (11ul << SYS_GPD_MFPL_PD0MFP_Pos) /*!< GPD_MFPL PD0 setting for T3*/
+
+//PD1
+#define SYS_GPD_MFPL_PD1MFP_GPIO (0ul << SYS_GPD_MFPL_PD1MFP_Pos) /*!< GPD_MFPL PD1 setting for GPIO*/
+#define SYS_GPD_MFPL_PD1MFP_EADC_CH11 (1ul << SYS_GPD_MFPL_PD1MFP_Pos) /*!< GPD_MFPL PD1 setting for EADC_CH11*/
+#define SYS_GPD_MFPL_PD1MFP_PWM0_SYNC_IN (2ul << SYS_GPD_MFPL_PD1MFP_Pos) /*!< GPD_MFPL PD1 setting for PWM0_SYNC_IN*/
+#define SYS_GPD_MFPL_PD1MFP_UART0_TXD (3ul << SYS_GPD_MFPL_PD1MFP_Pos) /*!< GPD_MFPL PD1 setting for UART0_TXD*/
+#define SYS_GPD_MFPL_PD1MFP_TK10 (4ul << SYS_GPD_MFPL_PD1MFP_Pos) /*!< GPD_MFPL PD1 setting for TK10*/
+#define SYS_GPD_MFPL_PD1MFP_ACMP1_P2 (5ul << SYS_GPD_MFPL_PD1MFP_Pos) /*!< GPD_MFPL PD1 setting for ACMP1_P2*/
+#define SYS_GPD_MFPL_PD1MFP_T0 (6ul << SYS_GPD_MFPL_PD1MFP_Pos) /*!< GPD_MFPL PD1 setting for T0*/
+#define SYS_GPD_MFPL_PD1MFP_EBI_nRD (7ul << SYS_GPD_MFPL_PD1MFP_Pos) /*!< GPD_MFPL PD1 setting for EBI_nRD*/
+
+//PD2
+#define SYS_GPD_MFPL_PD2MFP_GPIO (0ul << SYS_GPD_MFPL_PD2MFP_Pos) /*!< GPD_MFPL PD2 setting for GPIO*/
+#define SYS_GPD_MFPL_PD2MFP_STADC (1ul << SYS_GPD_MFPL_PD2MFP_Pos) /*!< GPD_MFPL PD2 setting for STADC*/
+#define SYS_GPD_MFPL_PD2MFP_T0_EXT (3ul << SYS_GPD_MFPL_PD2MFP_Pos) /*!< GPD_MFPL PD2 setting for T0_EXT*/
+#define SYS_GPD_MFPL_PD2MFP_TK11 (4ul << SYS_GPD_MFPL_PD2MFP_Pos) /*!< GPD_MFPL PD2 setting for TK11*/
+#define SYS_GPD_MFPL_PD2MFP_ACMP1_P1 (5ul << SYS_GPD_MFPL_PD2MFP_Pos) /*!< GPD_MFPL PD2 setting for ACMP1_P1*/
+#define SYS_GPD_MFPL_PD2MFP_PWM0_BRAKE0 (6ul << SYS_GPD_MFPL_PD2MFP_Pos) /*!< GPD_MFPL PD2 setting for PWM0_BRAKE0*/
+#define SYS_GPD_MFPL_PD2MFP_EBI_nWR (7ul << SYS_GPD_MFPL_PD2MFP_Pos) /*!< GPD_MFPL PD2 setting for EBI_nWR*/
+#define SYS_GPD_MFPL_PD2MFP_INT0 (8ul << SYS_GPD_MFPL_PD2MFP_Pos) /*!< GPD_MFPL PD2 setting for INT0*/
+
+//PD3
+#define SYS_GPD_MFPL_PD3MFP_GPIO (0ul << SYS_GPD_MFPL_PD3MFP_Pos) /*!< GPD_MFPL PD3 setting for GPIO*/
+#define SYS_GPD_MFPL_PD3MFP_T2 (1ul << SYS_GPD_MFPL_PD3MFP_Pos) /*!< GPD_MFPL PD3 setting for T2*/
+#define SYS_GPD_MFPL_PD3MFP_T1_EXT (3ul << SYS_GPD_MFPL_PD3MFP_Pos) /*!< GPD_MFPL PD3 setting for T1_EXT*/
+#define SYS_GPD_MFPL_PD3MFP_TK12 (4ul << SYS_GPD_MFPL_PD3MFP_Pos) /*!< GPD_MFPL PD3 setting for TK12*/
+#define SYS_GPD_MFPL_PD3MFP_ACMP1_P0 (5ul << SYS_GPD_MFPL_PD3MFP_Pos) /*!< GPD_MFPL PD3 setting for ACMP1_P0*/
+#define SYS_GPD_MFPL_PD3MFP_PWM0_BRAKE1 (6ul << SYS_GPD_MFPL_PD3MFP_Pos) /*!< GPD_MFPL PD3 setting for PWM0_BRAKE1*/
+#define SYS_GPD_MFPL_PD3MFP_EBI_MCLK (7ul << SYS_GPD_MFPL_PD3MFP_Pos) /*!< GPD_MFPL PD3 setting for EBI_MCLK*/
+#define SYS_GPD_MFPL_PD3MFP_INT1 (8ul << SYS_GPD_MFPL_PD3MFP_Pos) /*!< GPD_MFPL PD3 setting for INT1*/
+
+//PD4
+#define SYS_GPD_MFPL_PD4MFP_GPIO (0ul << SYS_GPD_MFPL_PD4MFP_Pos) /*!< GPD_MFPL PD4 setting for GPIO*/
+#define SYS_GPD_MFPL_PD4MFP_SPI1_CLK (2ul << SYS_GPD_MFPL_PD4MFP_Pos) /*!< GPD_MFPL PD4 setting for SPI1_CLK*/
+#define SYS_GPD_MFPL_PD4MFP_I2C0_SDA (3ul << SYS_GPD_MFPL_PD4MFP_Pos) /*!< GPD_MFPL PD4 setting for I2C0_SDA*/
+#define SYS_GPD_MFPL_PD4MFP_TK13 (4ul << SYS_GPD_MFPL_PD4MFP_Pos) /*!< GPD_MFPL PD4 setting for TK13*/
+#define SYS_GPD_MFPL_PD4MFP_PWM0_BRAKE0 (5ul << SYS_GPD_MFPL_PD4MFP_Pos) /*!< GPD_MFPL PD4 setting for PWM0_BRAKE0*/
+#define SYS_GPD_MFPL_PD4MFP_T0 (6ul << SYS_GPD_MFPL_PD4MFP_Pos) /*!< GPD_MFPL PD4 setting for T0*/
+
+//PD5
+#define SYS_GPD_MFPL_PD5MFP_GPIO (0ul << SYS_GPD_MFPL_PD5MFP_Pos) /*!< GPD_MFPL PD5 setting for GPIO*/
+#define SYS_GPD_MFPL_PD5MFP_CLKO (1ul << SYS_GPD_MFPL_PD5MFP_Pos) /*!< GPD_MFPL PD5 setting for CLKO*/
+#define SYS_GPD_MFPL_PD5MFP_SPI1_MISO (2ul << SYS_GPD_MFPL_PD5MFP_Pos) /*!< GPD_MFPL PD5 setting for SPI1_MISO*/
+#define SYS_GPD_MFPL_PD5MFP_I2C0_SCL (3ul << SYS_GPD_MFPL_PD5MFP_Pos) /*!< GPD_MFPL PD5 setting for I2C0_SCL*/
+#define SYS_GPD_MFPL_PD5MFP_TK14 (4ul << SYS_GPD_MFPL_PD5MFP_Pos) /*!< GPD_MFPL PD5 setting for TK14*/
+#define SYS_GPD_MFPL_PD5MFP_PWM0_BRAKE1 (5ul << SYS_GPD_MFPL_PD5MFP_Pos) /*!< GPD_MFPL PD5 setting for PWM0_BRAKE1*/
+#define SYS_GPD_MFPL_PD5MFP_T1 (6ul << SYS_GPD_MFPL_PD5MFP_Pos) /*!< GPD_MFPL PD5 setting for T1*/
+
+//PD6
+#define SYS_GPD_MFPL_PD6MFP_GPIO (0ul << SYS_GPD_MFPL_PD6MFP_Pos) /*!< GPD_MFPL PD6 setting for GPIO*/
+#define SYS_GPD_MFPL_PD6MFP_CLKO (1ul << SYS_GPD_MFPL_PD6MFP_Pos) /*!< GPD_MFPL PD6 setting for CLKO*/
+#define SYS_GPD_MFPL_PD6MFP_SPI1_SS (2ul << SYS_GPD_MFPL_PD6MFP_Pos) /*!< GPD_MFPL PD6 setting for SPI1_SS*/
+#define SYS_GPD_MFPL_PD6MFP_UART0_RXD (3ul << SYS_GPD_MFPL_PD6MFP_Pos) /*!< GPD_MFPL PD6 setting for UART0_RXD*/
+#define SYS_GPD_MFPL_PD6MFP_TK16 (4ul << SYS_GPD_MFPL_PD6MFP_Pos) /*!< GPD_MFPL PD6 setting for TK16*/
+#define SYS_GPD_MFPL_PD6MFP_ACMP0_O (5ul << SYS_GPD_MFPL_PD6MFP_Pos) /*!< GPD_MFPL PD6 setting for ACMP0_O*/
+#define SYS_GPD_MFPL_PD6MFP_PWM0_CH5 (6ul << SYS_GPD_MFPL_PD6MFP_Pos) /*!< GPD_MFPL PD6 setting for PWM0_CH5*/
+#define SYS_GPD_MFPL_PD6MFP_EBI_nWR (7ul << SYS_GPD_MFPL_PD6MFP_Pos) /*!< GPD_MFPL PD6 setting for EBI_nWR*/
+
+//PD7
+#define SYS_GPD_MFPL_PD7MFP_GPIO (0ul << SYS_GPD_MFPL_PD7MFP_Pos) /*!< GPD_MFPL PD7 setting for GPIO*/
+#define SYS_GPD_MFPL_PD7MFP_PWM0_SYNC_IN (3ul << SYS_GPD_MFPL_PD7MFP_Pos) /*!< GPD_MFPL PD7 setting for PWM0_SYNC_IN*/
+#define SYS_GPD_MFPL_PD7MFP_T1 (4ul << SYS_GPD_MFPL_PD7MFP_Pos) /*!< GPD_MFPL PD7 setting for T1*/
+#define SYS_GPD_MFPL_PD7MFP_ACMP0_O (5ul << SYS_GPD_MFPL_PD7MFP_Pos) /*!< GPD_MFPL PD7 setting for ACMP0_O*/
+#define SYS_GPD_MFPL_PD7MFP_PWM0_CH5 (6ul << SYS_GPD_MFPL_PD7MFP_Pos) /*!< GPD_MFPL PD7 setting for PWM0_CH5*/
+#define SYS_GPD_MFPL_PD7MFP_EBI_nRD (7ul << SYS_GPD_MFPL_PD7MFP_Pos) /*!< GPD_MFPL PD7 setting for EBI_nRD*/
+
+//PD8
+#define SYS_GPD_MFPH_PD8MFP_GPIO (0ul << SYS_GPD_MFPH_PD8MFP_Pos) /*!< GPD_MFPH PD8 setting for GPIO*/
+#define SYS_GPD_MFPH_PD8MFP_EADC_CH7 (1ul << SYS_GPD_MFPH_PD8MFP_Pos) /*!< GPD_MFPH PD8 setting for EADC_CH7*/
+#define SYS_GPD_MFPH_PD8MFP_TK8 (4ul << SYS_GPD_MFPH_PD8MFP_Pos) /*!< GPD_MFPH PD8 setting for TK8*/
+#define SYS_GPD_MFPH_PD8MFP_EBI_nCS0 (7ul << SYS_GPD_MFPH_PD8MFP_Pos) /*!< GPD_MFPH PD8 setting for EBI_nCS0*/
+
+//PD9
+#define SYS_GPD_MFPH_PD9MFP_GPIO (0ul << SYS_GPD_MFPH_PD9MFP_Pos) /*!< GPD_MFPH PD9 setting for GPIO*/
+#define SYS_GPD_MFPH_PD9MFP_EADC_CH10 (1ul << SYS_GPD_MFPH_PD9MFP_Pos) /*!< GPD_MFPH PD9 setting for EADC_CH10*/
+#define SYS_GPD_MFPH_PD9MFP_TK9 (4ul << SYS_GPD_MFPH_PD9MFP_Pos) /*!< GPD_MFPH PD9 setting for TK9*/
+#define SYS_GPD_MFPH_PD9MFP_ACMP1_P3 (5ul << SYS_GPD_MFPH_PD9MFP_Pos) /*!< GPD_MFPH PD9 setting for ACMP1_P3*/
+#define SYS_GPD_MFPH_PD9MFP_EBI_ALE (7ul << SYS_GPD_MFPH_PD9MFP_Pos) /*!< GPD_MFPH PD9 setting for EBI_ALE*/
+
+//PD10
+#define SYS_GPD_MFPH_PD10MFP_GPIO (0ul << SYS_GPD_MFPH_PD10MFP_Pos) /*!< GPD_MFPH PD10 setting for GPIO*/
+#define SYS_GPD_MFPH_PD10MFP_T2 (4ul << SYS_GPD_MFPH_PD10MFP_Pos) /*!< GPD_MFPH PD10 setting for T2*/
+
+//PD11
+#define SYS_GPD_MFPH_PD11MFP_GPIO (0ul << SYS_GPD_MFPH_PD11MFP_Pos) /*!< GPD_MFPH PD11 setting for GPIO*/
+#define SYS_GPD_MFPH_PD11MFP_T3 (4ul << SYS_GPD_MFPH_PD11MFP_Pos) /*!< GPD_MFPH PD11 setting for T3*/
+
+//PD12
+#define SYS_GPD_MFPH_PD12MFP_GPIO (0ul << SYS_GPD_MFPH_PD12MFP_Pos) /*!< GPD_MFPH PD12 setting for GPIO*/
+#define SYS_GPD_MFPH_PD12MFP_SPI2_SS (2ul << SYS_GPD_MFPH_PD12MFP_Pos) /*!< GPD_MFPH PD12 setting for SPI2_SS*/
+#define SYS_GPD_MFPH_PD12MFP_UART3_TXD (3ul << SYS_GPD_MFPH_PD12MFP_Pos) /*!< GPD_MFPH PD12 setting for UART3_TXD*/
+#define SYS_GPD_MFPH_PD12MFP_PWM1_CH0 (6ul << SYS_GPD_MFPH_PD12MFP_Pos) /*!< GPD_MFPH PD12 setting for PWM1_CH0*/
+#define SYS_GPD_MFPH_PD12MFP_EBI_ADR16 (7ul << SYS_GPD_MFPH_PD12MFP_Pos) /*!< GPD_MFPH PD12 setting for EBI_ADR16*/
+
+//PD13
+#define SYS_GPD_MFPH_PD13MFP_GPIO (0ul << SYS_GPD_MFPH_PD13MFP_Pos) /*!< GPD_MFPH PD13 setting for GPIO*/
+#define SYS_GPD_MFPH_PD13MFP_SPI2_MOSI (2ul << SYS_GPD_MFPH_PD13MFP_Pos) /*!< GPD_MFPH PD13 setting for SPI2_MOSI*/
+#define SYS_GPD_MFPH_PD13MFP_UART3_RXD (3ul << SYS_GPD_MFPH_PD13MFP_Pos) /*!< GPD_MFPH PD13 setting for UART3_RXD*/
+#define SYS_GPD_MFPH_PD13MFP_PWM1_CH1 (6ul << SYS_GPD_MFPH_PD13MFP_Pos) /*!< GPD_MFPH PD13 setting for PWM1_CH1*/
+#define SYS_GPD_MFPH_PD13MFP_EBI_ADR17 (7ul << SYS_GPD_MFPH_PD13MFP_Pos) /*!< GPD_MFPH PD13 setting for EBI_ADR17*/
+
+//PD14
+#define SYS_GPD_MFPH_PD14MFP_GPIO (0ul << SYS_GPD_MFPH_PD14MFP_Pos) /*!< GPD_MFPH_ PD14 setting for GPIO*/
+#define SYS_GPD_MFPH_PD14MFP_SPI2_MISO (2ul << SYS_GPD_MFPH_PD14MFP_Pos) /*!< GPD_MFPH_ PD14 setting for SPI2_MISO*/
+#define SYS_GPD_MFPH_PD14MFP_UART3_nCTS (3ul << SYS_GPD_MFPH_PD14MFP_Pos) /*!< GPD_MFPH_ PD14 setting for UART3_nCTS*/
+#define SYS_GPD_MFPH_PD14MFP_PWM1_CH2 (6ul << SYS_GPD_MFPH_PD14MFP_Pos) /*!< GPD_MFPH_ PD14 setting for PWM1_CH2*/
+#define SYS_GPD_MFPH_PD14MFP_EBI_ADR18 (7ul << SYS_GPD_MFPH_PD14MFP_Pos) /*!< GPD_MFPH_ PD14 setting for EBI_ADR18*/
+
+//PD15
+#define SYS_GPD_MFPH_PD15MFP_GPIO (0ul << SYS_GPD_MFPH_PD15MFP_Pos) /*!< GPD_MFPH_ PD15 setting for GPIO*/
+#define SYS_GPD_MFPH_PD15MFP_SPI2_CLK (2ul << SYS_GPD_MFPH_PD15MFP_Pos) /*!< GPD_MFPH_ PD15 setting for SPI2_CLK*/
+#define SYS_GPD_MFPH_PD15MFP_UART3_nRTS (3ul << SYS_GPD_MFPH_PD15MFP_Pos) /*!< GPD_MFPH_ PD15 setting for UART3_nRTS*/
+#define SYS_GPD_MFPH_PD15MFP_PWM1_CH3 (6ul << SYS_GPD_MFPH_PD15MFP_Pos) /*!< GPD_MFPH_ PD15 setting for PWM1_CH3*/
+#define SYS_GPD_MFPH_PD15MFP_EBI_ADR19 (7ul << SYS_GPD_MFPH_PD15MFP_Pos) /*!< GPD_MFPH_ PD15 setting for EBI_ADR19*/
+
+//PE0
+#define SYS_GPE_MFPL_PE0MFP_GPIO (0ul << SYS_GPE_MFPL_PE0MFP_Pos) /*!< GPE_MFPL PE0 setting for GPIO*/
+#define SYS_GPE_MFPL_PE0MFP_SPI2_CLK (2ul << SYS_GPE_MFPL_PE0MFP_Pos) /*!< GPE_MFPL PE0 setting for SPI2_CLK*/
+#define SYS_GPE_MFPL_PE0MFP_I2C1_SDA (3ul << SYS_GPE_MFPL_PE0MFP_Pos) /*!< GPE_MFPL PE0 setting for I2C1_SDA*/
+#define SYS_GPE_MFPL_PE0MFP_T2_EXT (4ul << SYS_GPE_MFPL_PE0MFP_Pos) /*!< GPE_MFPL PE0 setting for T2_EXT*/
+#define SYS_GPE_MFPL_PE0MFP_SC0_CD (5ul << SYS_GPE_MFPL_PE0MFP_Pos) /*!< GPE_MFPL PE0 setting for SC0_CD*/
+#define SYS_GPE_MFPL_PE0MFP_PWM0_CH0 (6ul << SYS_GPE_MFPL_PE0MFP_Pos) /*!< GPE_MFPL PE0 setting for PWM0_CH0*/
+#define SYS_GPE_MFPL_PE0MFP_EBI_nCS1 (7ul << SYS_GPE_MFPL_PE0MFP_Pos) /*!< GPE_MFPL PE0 setting for EBI_nCS1*/
+#define SYS_GPE_MFPL_PE0MFP_INT4 (8ul << SYS_GPE_MFPL_PE0MFP_Pos) /*!< GPE_MFPL PE0 setting for INT4*/
+
+//PE1
+#define SYS_GPE_MFPL_PE1MFP_GPIO (0ul << SYS_GPE_MFPL_PE1MFP_Pos) /*!< GPE_MFPL PE1 setting for GPIO*/
+#define SYS_GPE_MFPL_PE1MFP_T3_EXT (3ul << SYS_GPE_MFPL_PE1MFP_Pos) /*!< GPE_MFPL PE1 setting for T3_EXT*/
+#define SYS_GPE_MFPL_PE1MFP_SC0_CD (5ul << SYS_GPE_MFPL_PE1MFP_Pos) /*!< GPE_MFPL PE1 setting for SC0_CD*/
+#define SYS_GPE_MFPL_PE1MFP_PWM0_CH1 (6ul << SYS_GPE_MFPL_PE1MFP_Pos) /*!< GPE_MFPL PE1 setting for PWM0_CH1*/
+
+//PE2
+#define SYS_GPE_MFPL_PE2MFP_GPIO (0ul << SYS_GPE_MFPL_PE2MFP_Pos) /*!< GPE_MFPL PE2 setting for GPIO*/
+#define SYS_GPE_MFPL_PE2MFP_PWM1_CH1 (6ul << SYS_GPE_MFPL_PE2MFP_Pos) /*!< GPE_MFPL PE2 setting for PWM1_CH1*/
+
+//PE3
+#define SYS_GPE_MFPL_PE3MFP_GPIO (0ul << SYS_GPE_MFPL_PE3MFP_Pos) /*!< GPE_MFPL PE3 setting for GPIO*/
+#define SYS_GPE_MFPL_PE3MFP_SPI1_MOSI (2ul << SYS_GPE_MFPL_PE3MFP_Pos) /*!< GPE_MFPL PE3 setting for SPI1_MOSI*/
+#define SYS_GPE_MFPL_PE3MFP_TK15 (4ul << SYS_GPE_MFPL_PE3MFP_Pos) /*!< GPE_MFPL PE3 setting for TK15*/
+#define SYS_GPE_MFPL_PE3MFP_PWM0_CH3 (6ul << SYS_GPE_MFPL_PE3MFP_Pos) /*!< GPE_MFPL PE3 setting for PWM0_CH3*/
+
+//PE4
+#define SYS_GPE_MFPL_PE4MFP_GPIO (0ul << SYS_GPE_MFPL_PE4MFP_Pos) /*!< GPE_MFPL PE4 setting for GPIO*/
+#define SYS_GPE_MFPL_PE4MFP_I2C1_SCL (3ul << SYS_GPE_MFPL_PE4MFP_Pos) /*!< GPE_MFPL PE4 setting for I2C1_SCL*/
+#define SYS_GPE_MFPL_PE4MFP_SC0_PWR (5ul << SYS_GPE_MFPL_PE4MFP_Pos) /*!< GPE_MFPL PE4 setting for SC0_PWR*/
+#define SYS_GPE_MFPL_PE4MFP_PWM1_BRAKE0 (6ul << SYS_GPE_MFPL_PE4MFP_Pos) /*!< GPE_MFPL PE4 setting for PWM1_BRAKE0*/
+#define SYS_GPE_MFPL_PE4MFP_EBI_nCS0 (7ul << SYS_GPE_MFPL_PE4MFP_Pos) /*!< GPE_MFPL PE4 setting for EBI_nCS0*/
+#define SYS_GPE_MFPL_PE4MFP_INT0 (8ul << SYS_GPE_MFPL_PE4MFP_Pos) /*!< GPE_MFPL PE4 setting for INT0*/
+
+//PE5
+#define SYS_GPE_MFPL_PE5MFP_GPIO (0ul << SYS_GPE_MFPL_PE5MFP_Pos) /*!< GPE_MFPL PE5 setting for GPIO*/
+#define SYS_GPE_MFPL_PE5MFP_I2C1_SDA (3ul << SYS_GPE_MFPL_PE5MFP_Pos) /*!< GPE_MFPL PE5 setting for I2C1_SDA*/
+#define SYS_GPE_MFPL_PE5MFP_SC0_RST (5ul << SYS_GPE_MFPL_PE5MFP_Pos) /*!< GPE_MFPL PE5 setting for SC0_RST*/
+#define SYS_GPE_MFPL_PE5MFP_PWM1_BRAKE1 (6ul << SYS_GPE_MFPL_PE5MFP_Pos) /*!< GPE_MFPL PE5 setting for PWM1_BRAKE1*/
+#define SYS_GPE_MFPL_PE5MFP_EBI_ALE (7ul << SYS_GPE_MFPL_PE5MFP_Pos) /*!< GPE_MFPL PE5 setting for EBI_ALE*/
+#define SYS_GPE_MFPL_PE5MFP_INT1 (8ul << SYS_GPE_MFPL_PE5MFP_Pos) /*!< GPE_MFPL PE5 setting for INT1*/
+
+//PE6
+#define SYS_GPE_MFPL_PE6MFP_GPIO (0ul << SYS_GPE_MFPL_PE6MFP_Pos) /*!< GPE_MFPL PE6 setting for GPIO*/
+#define SYS_GPE_MFPL_PE6MFP_T3_EXT (3ul << SYS_GPE_MFPL_PE6MFP_Pos) /*!< GPE_MFPL PE6 setting for T3_EXT*/
+
+//PE7
+#define SYS_GPE_MFPL_PE7MFP_GPIO (0ul << SYS_GPE_MFPL_PE7MFP_Pos) /*!< GPE_MFPL PE7 setting for GPIO*/
+
+//PE8
+#define SYS_GPE_MFPH_PE8MFP_GPIO (0ul << SYS_GPE_MFPH_PE8MFP_Pos) /*!< GPE_MFPH PE8 setting for GPIO*/
+#define SYS_GPE_MFPH_PE8MFP_UART1_TXD (1ul << SYS_GPE_MFPH_PE8MFP_Pos) /*!< GPE_MFPH PE8 setting for UART1_TXD*/
+#define SYS_GPE_MFPH_PE8MFP_SPI0_MISO1 (2ul << SYS_GPE_MFPH_PE8MFP_Pos) /*!< GPE_MFPH PE8 setting for SPI0_MISO1*/
+#define SYS_GPE_MFPH_PE8MFP_I2C1_SCL (4ul << SYS_GPE_MFPH_PE8MFP_Pos) /*!< GPE_MFPH PE8 setting for I2C1_SCL*/
+#define SYS_GPE_MFPH_PE8MFP_SC0_PWR (5ul << SYS_GPE_MFPH_PE8MFP_Pos) /*!< GPE_MFPH PE8 setting for SC0_PWR*/
+#define SYS_GPE_MFPH_PE8MFP_CLKO (9ul << SYS_GPE_MFPH_PE8MFP_Pos) /*!< GPE_MFPH PE8 setting for CLKO*/
+#define SYS_GPE_MFPH_PE8MFP_PWM0_BRAKE0 (10ul << SYS_GPE_MFPH_PE8MFP_Pos) /*!< GPE_MFPH PE8 setting for PWM0_BRAKE0*/
+#define SYS_GPE_MFPH_PE8MFP_T1 (11ul << SYS_GPE_MFPH_PE8MFP_Pos) /*!< GPE_MFPH PE8 setting for T1*/
+
+//PE9
+#define SYS_GPE_MFPH_PE9MFP_GPIO (0ul << SYS_GPE_MFPH_PE9MFP_Pos) /*!< GPE_MFPH PE9 setting for GPIO*/
+#define SYS_GPE_MFPH_PE9MFP_UART1_RXD (1ul << SYS_GPE_MFPH_PE9MFP_Pos) /*!< GPE_MFPH PE9 setting for UART1_RXD*/
+#define SYS_GPE_MFPH_PE9MFP_SPI0_MOSI1 (2ul << SYS_GPE_MFPH_PE9MFP_Pos) /*!< GPE_MFPH PE9 setting for SPI0_MOSI1*/
+#define SYS_GPE_MFPH_PE9MFP_I2C1_SDA (4ul << SYS_GPE_MFPH_PE9MFP_Pos) /*!< GPE_MFPH PE9 setting for I2C1_SDA*/
+#define SYS_GPE_MFPH_PE9MFP_SC0_RST (5ul << SYS_GPE_MFPH_PE9MFP_Pos) /*!< GPE_MFPH PE9 setting for SC0_RST*/
+#define SYS_GPE_MFPH_PE9MFP_SPI1_I2SMCLK (9ul << SYS_GPE_MFPH_PE9MFP_Pos) /*!< GPE_MFPH PE9 setting for SPI1_I2SMCLK*/
+#define SYS_GPE_MFPH_PE9MFP_PWM1_BRAKE1 (10ul << SYS_GPE_MFPH_PE9MFP_Pos) /*!< GPE_MFPH PE9 setting for PWM1_BRAKE1*/
+#define SYS_GPE_MFPH_PE9MFP_T2 (11ul << SYS_GPE_MFPH_PE9MFP_Pos) /*!< GPE_MFPH PE9 setting for T2*/
+
+//PE10
+#define SYS_GPE_MFPH_PE10MFP_GPIO (0ul << SYS_GPE_MFPH_PE10MFP_Pos) /*!< GPE_MFPH PE10 setting for GPIO*/
+#define SYS_GPE_MFPH_PE10MFP_SPI1_MISO (1ul << SYS_GPE_MFPH_PE10MFP_Pos) /*!< GPE_MFPH PE10 setting for SPI1_MISO*/
+#define SYS_GPE_MFPH_PE10MFP_SPI0_MISO0 (2ul << SYS_GPE_MFPH_PE10MFP_Pos) /*!< GPE_MFPH PE10 setting for SPI0_MISO0*/
+#define SYS_GPE_MFPH_PE10MFP_UART1_nCTS (3ul << SYS_GPE_MFPH_PE10MFP_Pos) /*!< GPE_MFPH PE10 setting for UART1_nCTS*/
+#define SYS_GPE_MFPH_PE10MFP_I2C0_SMBAL (4ul << SYS_GPE_MFPH_PE10MFP_Pos) /*!< GPE_MFPH PE10 setting for I2C0_SMBAL*/
+#define SYS_GPE_MFPH_PE10MFP_SC0_DAT (5ul << SYS_GPE_MFPH_PE10MFP_Pos) /*!< GPE_MFPH PE10 setting for SC0_DAT*/
+#define SYS_GPE_MFPH_PE10MFP_UART3_TXD (9ul << SYS_GPE_MFPH_PE10MFP_Pos) /*!< GPE_MFPH PE10 setting for UART3_TXD*/
+#define SYS_GPE_MFPH_PE10MFP_I2C1_SCL (11ul << SYS_GPE_MFPH_PE10MFP_Pos) /*!< GPE_MFPH PE10 setting for I2C1_SCL*/
+
+//PE11
+#define SYS_GPE_MFPH_PE11MFP_GPIO (0ul << SYS_GPE_MFPH_PE11MFP_Pos) /*!< GPE_MFPH PE11 setting for GPIO*/
+#define SYS_GPE_MFPH_PE11MFP_SPI1_MOSI (1ul << SYS_GPE_MFPH_PE11MFP_Pos) /*!< GPE_MFPH PE11 setting for SPI1_MOSI*/
+#define SYS_GPE_MFPH_PE11MFP_SPI0_MOSI0 (2ul << SYS_GPE_MFPH_PE11MFP_Pos) /*!< GPE_MFPH PE11 setting for SPI0_MOSI0*/
+#define SYS_GPE_MFPH_PE11MFP_UART1_nRTS (3ul << SYS_GPE_MFPH_PE11MFP_Pos) /*!< GPE_MFPH PE11 setting for UART1_nRTS*/
+#define SYS_GPE_MFPH_PE11MFP_I2C0_SMBSUS (4ul << SYS_GPE_MFPH_PE11MFP_Pos) /*!< GPE_MFPH PE11 setting for I2C0_SMBSUS*/
+#define SYS_GPE_MFPH_PE11MFP_SC0_CLK (5ul << SYS_GPE_MFPH_PE11MFP_Pos) /*!< GPE_MFPH PE11 setting for SC0_CLK*/
+#define SYS_GPE_MFPH_PE11MFP_UART3_RXD (9ul << SYS_GPE_MFPH_PE11MFP_Pos) /*!< GPE_MFPH PE11 setting for UART3_RXD*/
+#define SYS_GPE_MFPH_PE11MFP_I2C1_SDA (11ul << SYS_GPE_MFPH_PE11MFP_Pos) /*!< GPE_MFPH PE11 setting for I2C1_SDA*/
+
+//PE12
+#define SYS_GPE_MFPH_PE12MFP_GPIO (0ul << SYS_GPE_MFPH_PE12MFP_Pos) /*!< GPE_MFPH PE12 setting for GPIO*/
+#define SYS_GPE_MFPH_PE12MFP_SPI1_SS (1ul << SYS_GPE_MFPH_PE12MFP_Pos) /*!< GPE_MFPH PE12 setting for SPI1_SS*/
+#define SYS_GPE_MFPH_PE12MFP_SPI0_SS (2ul << SYS_GPE_MFPH_PE12MFP_Pos) /*!< GPE_MFPH PE12 setting for SPI0_SS*/
+#define SYS_GPE_MFPH_PE12MFP_UART1_TXD (3ul << SYS_GPE_MFPH_PE12MFP_Pos) /*!< GPE_MFPH PE12 setting for UART1_TXD*/
+#define SYS_GPE_MFPH_PE12MFP_I2C0_SCL (4ul << SYS_GPE_MFPH_PE12MFP_Pos) /*!< GPE_MFPH PE12 setting for I2C0_SCL*/
+
+//PE13
+#define SYS_GPE_MFPH_PE13MFP_GPIO (0ul << SYS_GPE_MFPH_PE13MFP_Pos) /*!< GPE_MFPH PE13 setting for GPIO*/
+#define SYS_GPE_MFPH_PE13MFP_SPI1_CLK (1ul << SYS_GPE_MFPH_PE13MFP_Pos) /*!< GPE_MFPH PE13 setting for SPI1_CLK*/
+#define SYS_GPE_MFPH_PE13MFP_SPI0_CLK (2ul << SYS_GPE_MFPH_PE13MFP_Pos) /*!< GPE_MFPH PE13 setting for SPI0_CLK*/
+#define SYS_GPE_MFPH_PE13MFP_UART1_RXD (3ul << SYS_GPE_MFPH_PE13MFP_Pos) /*!< GPE_MFPH PE13 setting for UART1_RXD*/
+#define SYS_GPE_MFPH_PE13MFP_I2C0_SDA (4ul << SYS_GPE_MFPH_PE13MFP_Pos) /*!< GPE_MFPH PE13 setting for I2C0_SDA*/
+
+//PE14
+#define SYS_GPE_MFPH_PE14MFP_GPIO (0ul << SYS_GPE_MFPH_PE14MFP_Pos) /*!< GPE_MFPH PE14 setting for GPIO*/
+
+//PF0
+#define SYS_GPF_MFPL_PF0MFP_GPIO (0ul << SYS_GPF_MFPL_PF0MFP_Pos) /*!< GPF_MFPL PF0 setting for GPIO*/
+#define SYS_GPF_MFPL_PF0MFP_X32_OUT (1ul << SYS_GPF_MFPL_PF0MFP_Pos) /*!< GPF_MFPL PF0 setting for X32_OUT*/
+#define SYS_GPF_MFPL_PF0MFP_INT5 (8ul << SYS_GPF_MFPL_PF0MFP_Pos) /*!< GPF_MFPL PF0 setting for INT5*/
+
+//PF1
+#define SYS_GPF_MFPL_PF1MFP_GPIO (0ul << SYS_GPF_MFPL_PF1MFP_Pos) /*!< GPF_MFPL PF1 setting for GPIO*/
+#define SYS_GPF_MFPL_PF1MFP_X32_IN (1ul << SYS_GPF_MFPL_PF1MFP_Pos) /*!< GPF_MFPL PF1 setting for X32_IN*/
+
+//PF2
+#define SYS_GPF_MFPL_PF2MFP_GPIO (0ul << SYS_GPF_MFPL_PF2MFP_Pos) /*!< GPF_MFPL PF2 setting for GPIO*/
+#define SYS_GPF_MFPL_PF2MFP_TAMPER (1ul << SYS_GPF_MFPL_PF2MFP_Pos) /*!< GPF_MFPL PF2 setting for TAMPER*/
+
+//PF3
+#define SYS_GPF_MFPL_PF3MFP_GPIO (0ul << SYS_GPF_MFPL_PF3MFP_Pos) /*!< GPF_MFPL PF3 setting for GPIO*/
+#define SYS_GPF_MFPL_PF3MFP_XT1_OUT (1ul << SYS_GPF_MFPL_PF3MFP_Pos) /*!< GPF_MFPL PF3 setting for XT1_OUT*/
+#define SYS_GPF_MFPL_PF3MFP_I2C1_SCL (3ul << SYS_GPF_MFPL_PF3MFP_Pos) /*!< GPF_MFPL PF3 setting for I2C1_SCL*/
+
+//PF4
+#define SYS_GPF_MFPL_PF4MFP_GPIO (0ul << SYS_GPF_MFPL_PF4MFP_Pos) /*!< GPF_MFPL PF4 setting for GPIO*/
+#define SYS_GPF_MFPL_PF4MFP_XT1_IN (1ul << SYS_GPF_MFPL_PF4MFP_Pos) /*!< GPF_MFPL PF4 setting for XT1_IN*/
+#define SYS_GPF_MFPL_PF4MFP_I2C1_SDA (3ul << SYS_GPF_MFPL_PF4MFP_Pos) /*!< GPF_MFPL PF4 setting for I2C1_SDA*/
+
+//PF5
+#define SYS_GPF_MFPL_PF5MFP_GPIO (0ul << SYS_GPF_MFPL_PF5MFP_Pos) /*!< GPF_MFPL PF5 setting for GPIO*/
+#define SYS_GPF_MFPL_PF5MFP_ICE_CLK (1ul << SYS_GPF_MFPL_PF5MFP_Pos) /*!< GPF_MFPL PF5 setting for ICE_CLK*/
+
+//PF6
+#define SYS_GPF_MFPL_PF6MFP_GPIO (0ul << SYS_GPF_MFPL_PF6MFP_Pos) /*!< GPF_MFPL PF6 setting for GPIO*/
+#define SYS_GPF_MFPL_PF6MFP_ICE_DAT (1ul << SYS_GPF_MFPL_PF6MFP_Pos) /*!< GPF_MFPL PF6 setting for ICE_DAT*/
+
+//PF7
+#define SYS_GPF_MFPL_PF7MFP_GPIO (0ul << SYS_GPF_MFPL_PF7MFP_Pos) /*!< GPF_MFPL PF7 setting for GPIO*/
+
+
+/*@}*/ /* end of group SYS_EXPORTED_CONSTANTS */
+
+
+/** @addtogroup SYS_EXPORTED_FUNCTIONS SYS Exported Functions
+ @{
+*/
+
+
+/**
+ * @brief Clear Brown-out detector interrupt flag
+ * @param None
+ * @return None
+ * @details This macro clear Brown-out detector interrupt flag.
+ */
+#define SYS_CLEAR_BOD_INT_FLAG() (SYS->BODCTL |= SYS_BODCTL_BODIF_Msk)
+
+/**
+ * @brief Set Brown-out detector function to normal mode
+ * @param None
+ * @return None
+ * @details This macro set Brown-out detector to normal mode.
+ * The register write-protection function should be disabled before using this macro.
+ */
+#define SYS_CLEAR_BOD_LPM() (SYS->BODCTL &= ~SYS_BODCTL_BODLPM_Msk)
+
+/**
+ * @brief Disable Brown-out detector function
+ * @param None
+ * @return None
+ * @details This macro disable Brown-out detector function.
+ * The register write-protection function should be disabled before using this macro.
+ */
+#define SYS_DISABLE_BOD() (SYS->BODCTL &= ~SYS_BODCTL_BODEN_Msk)
+
+/**
+ * @brief Enable Brown-out detector function
+ * @param None
+ * @return None
+ * @details This macro enable Brown-out detector function.
+ * The register write-protection function should be disabled before using this macro.
+ */
+#define SYS_ENABLE_BOD() (SYS->BODCTL |= SYS_BODCTL_BODEN_Msk)
+
+/**
+ * @brief Get Brown-out detector interrupt flag
+ * @param None
+ * @retval 0 Brown-out detect interrupt flag is not set.
+ * @retval >=1 Brown-out detect interrupt flag is set.
+ * @details This macro get Brown-out detector interrupt flag.
+ */
+#define SYS_GET_BOD_INT_FLAG() (SYS->BODCTL & SYS_BODCTL_BODIF_Msk)
+
+/**
+ * @brief Get Brown-out detector status
+ * @param None
+ * @retval 0 System voltage is higher than BOD threshold voltage setting or BOD function is disabled.
+ * @retval >=1 System voltage is lower than BOD threshold voltage setting.
+ * @details This macro get Brown-out detector output status.
+ * If the BOD function is disabled, this function always return 0.
+ */
+#define SYS_GET_BOD_OUTPUT() (SYS->BODCTL & SYS_BODCTL_BODOUT_Msk)
+
+/**
+ * @brief Enable Brown-out detector interrupt function
+ * @param None
+ * @return None
+ * @details This macro enable Brown-out detector interrupt function.
+ * The register write-protection function should be disabled before using this macro.
+ */
+#define SYS_DISABLE_BOD_RST() (SYS->BODCTL &= ~SYS_BODCTL_BODRSTEN_Msk)
+
+/**
+ * @brief Enable Brown-out detector reset function
+ * @param None
+ * @return None
+ * @details This macro enable Brown-out detect reset function.
+ * The register write-protection function should be disabled before using this macro.
+ */
+#define SYS_ENABLE_BOD_RST() (SYS->BODCTL |= SYS_BODCTL_BODRSTEN_Msk)
+
+/**
+ * @brief Set Brown-out detector function low power mode
+ * @param None
+ * @return None
+ * @details This macro set Brown-out detector to low power mode.
+ * The register write-protection function should be disabled before using this macro.
+ */
+#define SYS_SET_BOD_LPM() (SYS->BODCTL |= SYS_BODCTL_BODLPM_Msk)
+
+/**
+ * @brief Set Brown-out detector voltage level
+ * @param[in] u32Level is Brown-out voltage level. Including :
+ * - \ref SYS_BODCTL_BODVL_4_5V
+ * - \ref SYS_BODCTL_BODVL_3_7V
+ * - \ref SYS_BODCTL_BODVL_2_7V
+ * - \ref SYS_BODCTL_BODVL_2_2V
+ * @return None
+ * @details This macro set Brown-out detector voltage level.
+ * The write-protection function should be disabled before using this macro.
+ */
+#define SYS_SET_BOD_LEVEL(u32Level) (SYS->BODCTL = (SYS->BODCTL & ~SYS_BODCTL_BODVL_Msk) | (u32Level))
+
+/**
+ * @brief Get reset source is from Brown-out detector reset
+ * @param None
+ * @retval 0 Previous reset source is not from Brown-out detector reset
+ * @retval >=1 Previous reset source is from Brown-out detector reset
+ * @details This macro get previous reset source is from Brown-out detect reset or not.
+ */
+#define SYS_IS_BOD_RST() (SYS->RSTSTS & SYS_RSTSTS_BODRF_Msk)
+
+/**
+ * @brief Get reset source is from CPU reset
+ * @param None
+ * @retval 0 Previous reset source is not from CPU reset
+ * @retval >=1 Previous reset source is from CPU reset
+ * @details This macro get previous reset source is from CPU reset.
+ */
+#define SYS_IS_CPU_RST() (SYS->RSTSTS & SYS_RSTSTS_CPURF_Msk)
+
+/**
+ * @brief Get reset source is from LVR Reset
+ * @param None
+ * @retval 0 Previous reset source is not from Low-Voltage-Reset
+ * @retval >=1 Previous reset source is from Low-Voltage-Reset
+ * @details This macro get previous reset source is from Low-Voltage-Reset.
+ */
+#define SYS_IS_LVR_RST() (SYS->RSTSTS & SYS_RSTSTS_LVRF_Msk)
+
+/**
+ * @brief Get reset source is from Power-on Reset
+ * @param None
+ * @retval 0 Previous reset source is not from Power-on Reset
+ * @retval >=1 Previous reset source is from Power-on Reset
+ * @details This macro get previous reset source is from Power-on Reset.
+ */
+#define SYS_IS_POR_RST() (SYS->RSTSTS & SYS_RSTSTS_PORF_Msk)
+
+/**
+ * @brief Get reset source is from reset pin reset
+ * @param None
+ * @retval 0 Previous reset source is not from reset pin reset
+ * @retval >=1 Previous reset source is from reset pin reset
+ * @details This macro get previous reset source is from reset pin reset.
+ */
+#define SYS_IS_RSTPIN_RST() (SYS->RSTSTS & SYS_RSTSTS_PINRF_Msk)
+
+/**
+ * @brief Get reset source is from system reset
+ * @param None
+ * @retval 0 Previous reset source is not from system reset
+ * @retval >=1 Previous reset source is from system reset
+ * @details This macro get previous reset source is from system reset.
+ */
+#define SYS_IS_SYSTEM_RST() (SYS->RSTSTS & SYS_RSTSTS_SYSRF_Msk)
+
+/**
+ * @brief Get reset source is from window watch dog reset
+ * @param None
+ * @retval 0 Previous reset source is not from window watch dog reset
+ * @retval >=1 Previous reset source is from window watch dog reset
+ * @details This macro get previous reset source is from window watch dog reset.
+ */
+#define SYS_IS_WDT_RST() (SYS->RSTSTS & SYS_RSTSTS_WDTRF_Msk)
+
+/**
+ * @brief Disable Low-Voltage-Reset function
+ * @param None
+ * @return None
+ * @details This macro disable Low-Voltage-Reset function.
+ * The register write-protection function should be disabled before using this macro.
+ */
+#define SYS_DISABLE_LVR() (SYS->BODCTL &= ~SYS_BODCTL_LVREN_Msk)
+
+/**
+ * @brief Enable Low-Voltage-Reset function
+ * @param None
+ * @return None
+ * @details This macro enable Low-Voltage-Reset function.
+ * The register write-protection function should be disabled before using this macro.
+ */
+#define SYS_ENABLE_LVR() (SYS->BODCTL |= SYS_BODCTL_LVREN_Msk)
+
+/**
+ * @brief Disable Power-on Reset function
+ * @param None
+ * @return None
+ * @details This macro disable Power-on Reset function.
+ * The register write-protection function should be disabled before using this macro.
+ */
+#define SYS_DISABLE_POR() (SYS->PORCTL = 0x5AA5)
+
+/**
+ * @brief Enable Power-on Reset function
+ * @param None
+ * @return None
+ * @details This macro enable Power-on Reset function.
+ * The register write-protection function should be disabled before using this macro.
+ */
+#define SYS_ENABLE_POR() (SYS->PORCTL = 0)
+
+/**
+ * @brief Clear reset source flag
+ * @param[in] u32RstSrc is reset source. Including :
+ * - \ref SYS_RSTSTS_PORF_Msk
+ * - \ref SYS_RSTSTS_PINRF_Msk
+ * - \ref SYS_RSTSTS_WDTRF_Msk
+ * - \ref SYS_RSTSTS_LVRF_Msk
+ * - \ref SYS_RSTSTS_BODRF_Msk
+ * - \ref SYS_RSTSTS_SYSRF_Msk
+ * - \ref SYS_RSTSTS_CPURF_Msk
+ * - \ref SYS_RSTSTS_CPULKRF_Msk
+ * @return None
+ * @details This macro clear reset source flag.
+ */
+#define SYS_CLEAR_RST_SOURCE(u32RstSrc) ((SYS->RSTSTS) = (u32RstSrc) )
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* static inline functions */
+/*---------------------------------------------------------------------------------------------------------*/
+
+
+/**
+ * @brief Disable register write-protection function
+ * @param None
+ * @return None
+ * @details This function disable register write-protection function.
+ * To unlock the protected register to allow write access.
+ */
+__STATIC_INLINE void SYS_UnlockReg(void)
+{
+ do
+ {
+ SYS->REGLCTL = 0x59;
+ SYS->REGLCTL = 0x16;
+ SYS->REGLCTL = 0x88;
+ }
+ while(SYS->REGLCTL == 0);
+}
+
+/**
+ * @brief Enable register write-protection function
+ * @param None
+ * @return None
+ * @details This function is used to enable register write-protection function.
+ * To lock the protected register to forbid write access.
+ */
+__STATIC_INLINE void SYS_LockReg(void)
+{
+ SYS->REGLCTL = 0;
+}
+
+
+void SYS_ClearResetSrc(uint32_t u32Src);
+uint32_t SYS_GetBODStatus(void);
+uint32_t SYS_GetResetSrc(void);
+uint32_t SYS_IsRegLocked(void);
+uint32_t SYS_ReadPDID(void);
+void SYS_ResetChip(void);
+void SYS_ResetCPU(void);
+void SYS_ResetModule(uint32_t u32ModuleIndex);
+void SYS_EnableBOD(int32_t i32Mode, uint32_t u32BODLevel);
+void SYS_DisableBOD(void);
+
+
+/*@}*/ /* end of group SYS_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group SYS_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif //__SYS_H__
diff --git a/bsp/nuvoton_m451/Libraries/StdDriver/inc/timer.h b/bsp/nuvoton_m451/Libraries/StdDriver/inc/timer.h
new file mode 100644
index 0000000000000000000000000000000000000000..de11f6774f8ce8dfe8dee5fc7b6b2df2aee533df
--- /dev/null
+++ b/bsp/nuvoton_m451/Libraries/StdDriver/inc/timer.h
@@ -0,0 +1,415 @@
+/**************************************************************************//**
+ * @file timer.h
+ * @version V3.00
+ * $Revision: 10 $
+ * $Date: 15/08/11 10:26a $
+ * @brief M451 series Timer driver header file
+ *
+ * @note
+ * Copyright (C) 2013~2015 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __TIMER_H__
+#define __TIMER_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup Standard_Driver Standard Driver
+ @{
+*/
+
+/** @addtogroup TIMER_Driver TIMER Driver
+ @{
+*/
+
+/** @addtogroup TIMER_EXPORTED_CONSTANTS TIMER Exported Constants
+ @{
+*/
+/*---------------------------------------------------------------------------------------------------------*/
+/* TIMER Operation Mode, External Counter and Capture Mode Constant Definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define TIMER_ONESHOT_MODE (0UL << TIMER_CTL_OPMODE_Pos) /*!< Timer working in one-shot mode */
+#define TIMER_PERIODIC_MODE (1UL << TIMER_CTL_OPMODE_Pos) /*!< Timer working in periodic mode */
+#define TIMER_TOGGLE_MODE (2UL << TIMER_CTL_OPMODE_Pos) /*!< Timer working in toggle-output mode */
+#define TIMER_CONTINUOUS_MODE (3UL << TIMER_CTL_OPMODE_Pos) /*!< Timer working in continuous counting mode */
+#define TIMER_TOUT_PIN_FROM_TX (0UL << TIMER_CTL_TGLPINSEL_Pos) /*!< Timer toggle-output pin is from Tx pin */
+#define TIMER_TOUT_PIN_FROM_TX_EXT (1UL << TIMER_CTL_TGLPINSEL_Pos) /*!< Timer toggle-output pin is from Tx_EXT pin */
+#define TIMER_CAPTURE_FREE_COUNTING_MODE (0UL << TIMER_EXTCTL_CAPFUNCS_Pos) /*!< Timer capture event to get timer counter value */
+#define TIMER_CAPTURE_COUNTER_RESET_MODE (1UL << TIMER_EXTCTL_CAPFUNCS_Pos) /*!< Timer capture event to reset timer counter */
+#define TIMER_CAPTURE_FALLING_EDGE (0UL << TIMER_EXTCTL_CAPEDGE_Pos) /*!< Falling edge detection to trigger timer capture */
+#define TIMER_CAPTURE_RISING_EDGE (1UL << TIMER_EXTCTL_CAPEDGE_Pos) /*!< Rising edge detection to trigger timer capture */
+#define TIMER_CAPTURE_FALLING_AND_RISING_EDGE (2UL << TIMER_EXTCTL_CAPEDGE_Pos) /*!< Both falling and rising edge detection to trigger timer capture */
+#define TIMER_COUNTER_FALLING_EDGE (0UL << TIMER_EXTCTL_CNTPHASE_Pos) /*!< Counter increase on falling edge detection */
+#define TIMER_COUNTER_RISING_EDGE (1UL << TIMER_EXTCTL_CNTPHASE_Pos) /*!< Counter increase on rising edge detection */
+
+/*@}*/ /* end of group TIMER_EXPORTED_CONSTANTS */
+
+
+/** @addtogroup TIMER_EXPORTED_FUNCTIONS TIMER Exported Functions
+ @{
+*/
+
+/**
+ * @brief Set Timer Compared Value
+ *
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+ * @param[in] u32Value Timer compare value. Valid values are between 2 to 0xFFFFFF.
+ *
+ * @return None
+ *
+ * @details This macro is used to set timer compared value to adjust timer time-out interval.
+ * @note 1. Never write 0x0 or 0x1 in this field, or the core will run into unknown state. \n
+ * 2. If update timer compared value in continuous counting mode, timer counter value will keep counting continuously. \n
+ * But if timer is operating at other modes, the timer up counter will restart counting and start from 0.
+ */
+#define TIMER_SET_CMP_VALUE(timer, u32Value) ((timer)->CMP = (u32Value))
+
+/**
+ * @brief Set Timer Prescale Value
+ *
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+ * @param[in] u32Value Timer prescale value. Valid values are between 0 to 0xFF.
+ *
+ * @return None
+ *
+ * @details This macro is used to set timer prescale value and timer source clock will be divided by (prescale + 1) \n
+ * before it is fed into timer.
+ */
+#define TIMER_SET_PRESCALE_VALUE(timer, u32Value) ((timer)->CTL = ((timer)->CTL & ~TIMER_CTL_PSC_Msk) | (u32Value))
+
+/**
+ * @brief Check specify Timer Status
+ *
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+ *
+ * @retval 0 Timer 24-bit up counter is inactive
+ * @retval 1 Timer 24-bit up counter is active
+ *
+ * @details This macro is used to check if specify Timer counter is inactive or active.
+ */
+#define TIMER_IS_ACTIVE(timer) (((timer)->CTL & TIMER_CTL_ACTSTS_Msk)? 1 : 0)
+
+/**
+ * @brief Select Toggle-output Pin
+ *
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+ * @param[in] u32ToutSel Toggle-output pin selection, valid values are:
+ * - \ref TIMER_TOUT_PIN_FROM_TX
+ * - \ref TIMER_TOUT_PIN_FROM_TX_EXT
+ *
+ * @return None
+ *
+ * @details This macro is used to select timer toggle-output pin is output on Tx or Tx_EXT pin.
+ */
+#define TIMER_SELECT_TOUT_PIN(timer, u32ToutSel) ((timer)->CTL = ((timer)->CTL & ~TIMER_CTL_TGLPINSEL_Msk) | (u32ToutSel))
+
+/**
+ * @brief Start Timer Counting
+ *
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+ *
+ * @return None
+ *
+ * @details This function is used to start Timer counting.
+ */
+static __INLINE void TIMER_Start(TIMER_T *timer)
+{
+ timer->CTL |= TIMER_CTL_CNTEN_Msk;
+}
+
+/**
+ * @brief Stop Timer Counting
+ *
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+ *
+ * @return None
+ *
+ * @details This function is used to stop/suspend Timer counting.
+ */
+static __INLINE void TIMER_Stop(TIMER_T *timer)
+{
+ timer->CTL &= ~TIMER_CTL_CNTEN_Msk;
+}
+
+/**
+ * @brief Enable Timer Interrupt Wake-up Function
+ *
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+ *
+ * @return None
+ *
+ * @details This function is used to enable the timer interrupt wake-up function and interrupt source could be time-out interrupt, \n
+ * counter event interrupt or capture trigger interrupt.
+ * @note To wake the system from Power-down mode, timer clock source must be ether LXT or LIRC.
+ */
+static __INLINE void TIMER_EnableWakeup(TIMER_T *timer)
+{
+ timer->CTL |= TIMER_CTL_WKEN_Msk;
+}
+
+/**
+ * @brief Disable Timer Wake-up Function
+ *
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+ *
+ * @return None
+ *
+ * @details This function is used to disable the timer interrupt wake-up function.
+ */
+static __INLINE void TIMER_DisableWakeup(TIMER_T *timer)
+{
+ timer->CTL &= ~TIMER_CTL_WKEN_Msk;
+}
+
+/**
+ * @brief Enable Capture Pin De-bounce
+ *
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+ *
+ * @return None
+ *
+ * @details This function is used to enable the detect de-bounce function of capture pin.
+ */
+static __INLINE void TIMER_EnableCaptureDebounce(TIMER_T *timer)
+{
+ timer->EXTCTL |= TIMER_EXTCTL_CAPDBEN_Msk;
+}
+
+/**
+ * @brief Disable Capture Pin De-bounce
+ *
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+ *
+ * @return None
+ *
+ * @details This function is used to disable the detect de-bounce function of capture pin.
+ */
+static __INLINE void TIMER_DisableCaptureDebounce(TIMER_T *timer)
+{
+ timer->EXTCTL &= ~TIMER_EXTCTL_CAPDBEN_Msk;
+}
+
+/**
+ * @brief Enable Counter Pin De-bounce
+ *
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+ *
+ * @return None
+ *
+ * @details This function is used to enable the detect de-bounce function of counter pin.
+ */
+static __INLINE void TIMER_EnableEventCounterDebounce(TIMER_T *timer)
+{
+ timer->EXTCTL |= TIMER_EXTCTL_CNTDBEN_Msk;
+}
+
+/**
+ * @brief Disable Counter Pin De-bounce
+ *
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+ *
+ * @return None
+ *
+ * @details This function is used to disable the detect de-bounce function of counter pin.
+ */
+static __INLINE void TIMER_DisableEventCounterDebounce(TIMER_T *timer)
+{
+ timer->EXTCTL &= ~TIMER_EXTCTL_CNTDBEN_Msk;
+}
+
+/**
+ * @brief Enable Timer Time-out Interrupt
+ *
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+ *
+ * @return None
+ *
+ * @details This function is used to enable the timer time-out interrupt function.
+ */
+static __INLINE void TIMER_EnableInt(TIMER_T *timer)
+{
+ timer->CTL |= TIMER_CTL_INTEN_Msk;
+}
+
+/**
+ * @brief Disable Timer Time-out Interrupt
+ *
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+ *
+ * @return None
+ *
+ * @details This function is used to disable the timer time-out interrupt function.
+ */
+static __INLINE void TIMER_DisableInt(TIMER_T *timer)
+{
+ timer->CTL &= ~TIMER_CTL_INTEN_Msk;
+}
+
+/**
+ * @brief Enable Capture Trigger Interrupt
+ *
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+ *
+ * @return None
+ *
+ * @details This function is used to enable the timer capture trigger interrupt function.
+ */
+static __INLINE void TIMER_EnableCaptureInt(TIMER_T *timer)
+{
+ timer->EXTCTL |= TIMER_EXTCTL_CAPIEN_Msk;
+}
+
+/**
+ * @brief Disable Capture Trigger Interrupt
+ *
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+ *
+ * @return None
+ *
+ * @details This function is used to disable the timer capture trigger interrupt function.
+ */
+static __INLINE void TIMER_DisableCaptureInt(TIMER_T *timer)
+{
+ timer->EXTCTL &= ~TIMER_EXTCTL_CAPIEN_Msk;
+}
+
+/**
+ * @brief Get Timer Time-out Interrupt Flag
+ *
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+ *
+ * @retval 0 Timer time-out interrupt did not occur
+ * @retval 1 Timer time-out interrupt occurred
+ *
+ * @details This function indicates timer time-out interrupt occurred or not.
+ */
+static __INLINE uint32_t TIMER_GetIntFlag(TIMER_T *timer)
+{
+ return ((timer->INTSTS & TIMER_INTSTS_TIF_Msk) ? 1 : 0);
+}
+
+/**
+ * @brief Clear Timer Time-out Interrupt Flag
+ *
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+ *
+ * @return None
+ *
+ * @details This function clears timer time-out interrupt flag to 0.
+ */
+static __INLINE void TIMER_ClearIntFlag(TIMER_T *timer)
+{
+ timer->INTSTS = (timer->INTSTS & ~TIMER_INTSTS_TWKF_Msk) | TIMER_INTSTS_TIF_Msk;
+}
+
+/**
+ * @brief Get Timer Capture Interrupt Flag
+ *
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+ *
+ * @retval 0 Timer capture interrupt did not occur
+ * @retval 1 Timer capture interrupt occurred
+ *
+ * @details This function indicates timer capture trigger interrupt occurred or not.
+ */
+static __INLINE uint32_t TIMER_GetCaptureIntFlag(TIMER_T *timer)
+{
+ return timer->EINTSTS;
+}
+
+/**
+ * @brief Clear Timer Capture Interrupt Flag
+ *
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+ *
+ * @return None
+ *
+ * @details This function clears timer capture trigger interrupt flag to 0.
+ */
+static __INLINE void TIMER_ClearCaptureIntFlag(TIMER_T *timer)
+{
+ timer->EINTSTS = TIMER_EINTSTS_CAPIF_Msk;
+}
+
+/**
+ * @brief Get Timer Wake-up Flag
+ *
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+ *
+ * @retval 0 Timer does not cause CPU wake-up
+ * @retval 1 Timer interrupt event cause CPU wake-up
+ *
+ * @details This function indicates timer interrupt event has waked up system or not.
+ */
+static __INLINE uint32_t TIMER_GetWakeupFlag(TIMER_T *timer)
+{
+ return (timer->INTSTS & TIMER_INTSTS_TWKF_Msk ? 1 : 0);
+}
+
+/**
+ * @brief Clear Timer Wake-up Flag
+ *
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+ *
+ * @return None
+ *
+ * @details This function clears the timer wake-up system flag to 0.
+ */
+static __INLINE void TIMER_ClearWakeupFlag(TIMER_T *timer)
+{
+ timer->INTSTS = (timer->INTSTS & ~TIMER_INTSTS_TIF_Msk) | TIMER_INTSTS_TWKF_Msk;
+}
+
+/**
+ * @brief Get Capture value
+ *
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+ *
+ * @return 24-bit Capture Value
+ *
+ * @details This function reports the current 24-bit timer capture value.
+ */
+static __INLINE uint32_t TIMER_GetCaptureData(TIMER_T *timer)
+{
+ return timer->CAP;
+}
+
+/**
+ * @brief Get Counter value
+ *
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+ *
+ * @return 24-bit Counter Value
+ *
+ * @details This function reports the current 24-bit timer counter value.
+ */
+static __INLINE uint32_t TIMER_GetCounter(TIMER_T *timer)
+{
+ return timer->CNT;
+}
+
+uint32_t TIMER_Open(TIMER_T *timer, uint32_t u32Mode, uint32_t u32Freq);
+void TIMER_Close(TIMER_T *timer);
+void TIMER_Delay(TIMER_T *timer, uint32_t u32Usec);
+void TIMER_EnableCapture(TIMER_T *timer, uint32_t u32CapMode, uint32_t u32Edge);
+void TIMER_DisableCapture(TIMER_T *timer);
+void TIMER_EnableEventCounter(TIMER_T *timer, uint32_t u32Edge);
+void TIMER_DisableEventCounter(TIMER_T *timer);
+uint32_t TIMER_GetModuleClock(TIMER_T *timer);
+
+/*@}*/ /* end of group TIMER_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group TIMER_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif //__TIMER_H__
+
+/*** (C) COPYRIGHT 2013~2015 Nuvoton Technology Corp. ***/
diff --git a/bsp/nuvoton_m451/Libraries/StdDriver/inc/tk.h b/bsp/nuvoton_m451/Libraries/StdDriver/inc/tk.h
new file mode 100644
index 0000000000000000000000000000000000000000..ccbbadf6574a0711fe42811cdeda7b702615ec69
--- /dev/null
+++ b/bsp/nuvoton_m451/Libraries/StdDriver/inc/tk.h
@@ -0,0 +1,302 @@
+/**************************************************************************//**
+ * @file tk.h
+ * @version V1.00
+ * $Revision: 6 $
+ * $Date: 15/08/24 4:52p $
+ * @brief M451 Series TK Driver Header File
+ *
+ * @note
+ * Copyright (C) 2014~2015 Nuvoton Technology Corp. All rights reserved.
+ *
+ ******************************************************************************/
+#ifndef __TK_H__
+#define __TK_H__
+
+#include "M451Series.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup Standard_Driver Standard Driver
+ @{
+*/
+
+/** @addtogroup TK_Driver TK Driver
+ @{
+*/
+
+/** @addtogroup TK_EXPORTED_CONSTANTS TK Exported Constants
+ @{
+*/
+
+#define TK_SCAN_MODE_SINGLE (0UL) /*!< Touch key single scan mode */
+#define TK_SCAN_MODE_PERIODIC (TK_CTL_TMRTRGEN_Msk) /*!< Touch key periodic scan mode */
+#define TK_SCAN_MODE_ALL_KEY (TK_REFCTL_SCANALL_Msk) /*!< Touch key all keys scan mode */
+#define TK_SCAN_MODE_PERIODIC_ALL_KEY (TK_CTL_TMRTRGEN_Msk | TK_REFCTL_SCANALL_Msk) /*!< Touch key periodic with all keys scan mode */
+
+#define TK_SENSE_PULSE_1 (0UL << TK_REFCTL_SENPTCTL_Pos) /*!< Touch key sensing pulse width is 1us */
+#define TK_SENSE_PULSE_2 (1UL << TK_REFCTL_SENPTCTL_Pos) /*!< Touch key sensing pulse width is 2us */
+#define TK_SENSE_PULSE_4 (2UL << TK_REFCTL_SENPTCTL_Pos) /*!< Touch key sensing pulse width is 4us */
+#define TK_SENSE_PULSE_8 (3UL << TK_REFCTL_SENPTCTL_Pos) /*!< Touch key sensing pulse width is 8us */
+
+#define TK_SENSE_CNT_128 (0UL << TK_REFCTL_SENTCTL_Pos) /*!< Touch key sensing count is 128 */
+#define TK_SENSE_CNT_255 (1UL << TK_REFCTL_SENTCTL_Pos) /*!< Touch key sensing count is 255 */
+#define TK_SENSE_CNT_511 (2UL << TK_REFCTL_SENTCTL_Pos) /*!< Touch key sensing count is 511 */
+#define TK_SENSE_CNT_1023 (3UL << TK_REFCTL_SENTCTL_Pos) /*!< Touch key sensing count is 1023 */
+
+#define TK_AVCCH_1_DIV_16 (0UL << TK_CTL_AVCCHSEL_Pos) /*!< Touch key AVCCH voltage is 1/16 VDD */
+#define TK_AVCCH_1_DIV_8 (1UL << TK_CTL_AVCCHSEL_Pos) /*!< Touch key AVCCH voltage is 1/8 VDD */
+#define TK_AVCCH_3_DIV_16 (2UL << TK_CTL_AVCCHSEL_Pos) /*!< Touch key AVCCH voltage is 3/16 VDD */
+#define TK_AVCCH_1_DIV_4 (3UL << TK_CTL_AVCCHSEL_Pos) /*!< Touch key AVCCH voltage is 1/4 VDD */
+#define TK_AVCCH_5_DIV_16 (4UL << TK_CTL_AVCCHSEL_Pos) /*!< Touch key AVCCH voltage is 5/16 VDD */
+#define TK_AVCCH_3_DIV_8 (5UL << TK_CTL_AVCCHSEL_Pos) /*!< Touch key AVCCH voltage is 3/8 VDD */
+#define TK_AVCCH_7_DIV_16 (6UL << TK_CTL_AVCCHSEL_Pos) /*!< Touch key AVCCH voltage is 7/16 VDD */
+#define TK_AVCCH_1_DIV_2 (7UL << TK_CTL_AVCCHSEL_Pos) /*!< Touch key AVCCH voltage is 1/2 VDD */
+
+#define TK_CAP_BANK_POL_SEL_GND (0UL << TK_POLCTL_CBPOLSEL_Pos) /*!< Touch key capacitor bank polarity is GND */
+#define TK_CAP_BANK_POL_SEL_AVCCH (1UL << TK_POLCTL_CBPOLSEL_Pos) /*!< Touch key capacitor bank polarity is AVCCH */
+#define TK_CAP_BANK_POL_SEL_VDD (2UL << TK_POLCTL_CBPOLSEL_Pos) /*!< Touch key capacitor bank polarity is VDD */
+
+#define TK_TKn_POL_SEL_GND (0UL) /*!< Touch key polarity is GND */
+#define TK_TKn_POL_SEL_AVCCH (1UL) /*!< Touch key polarity is AVCCH */
+#define TK_TKn_POL_SEL_VDD (2UL) /*!< Touch key polarity is VDD */
+
+#define TK_INT_EN_SCAN_COMPLETE (TK_INTEN_SCINTEN_Msk) /*!< Touch key enable scan complete interrupt */
+#define TK_INT_EN_SCAN_COMPLETE_EDGE_TH (TK_INTEN_SCTHIEN_Msk) /*!< Touch key enable scan complete with threshold interrupt of edge trigger mode */
+#define TK_INT_EN_SCAN_COMPLETE_LEVEL_TH (TK_INTEN_THIMOD_Msk | TK_INTEN_SCTHIEN_Msk) /*!< Touch key enable scan complete with threshold interrupt of level trigger mode */
+
+#define TK_INT_SCAN_COMPLETE (TK_STATUS_SCIF_Msk) /*!< Touch key scan complete interrupt */
+#define TK_INT_SCAN_COMPLETE_TH_ALL (0x1FFFF02UL) /*!< Touch key scan complete or all touch keys threshold control interrupt */
+#define TK_INT_SCAN_TH_ALL (0x1FFFF00UL) /*!< ALL Touch key threshold control interrupt */
+#define TK_INT_SCAN_TH_TK0 (TK_STATUS_TKIF0_Msk) /*!< Touch key 0 threshold control interrupt */
+#define TK_INT_SCAN_TH_TK1 (TK_STATUS_TKIF1_Msk) /*!< Touch key 1 threshold control interrupt */
+#define TK_INT_SCAN_TH_TK2 (TK_STATUS_TKIF2_Msk) /*!< Touch key 2 threshold control interrupt */
+#define TK_INT_SCAN_TH_TK3 (TK_STATUS_TKIF3_Msk) /*!< Touch key 3 threshold control interrupt */
+#define TK_INT_SCAN_TH_TK4 (TK_STATUS_TKIF4_Msk) /*!< Touch key 4 threshold control interrupt */
+#define TK_INT_SCAN_TH_TK5 (TK_STATUS_TKIF5_Msk) /*!< Touch key 5 threshold control interrupt */
+#define TK_INT_SCAN_TH_TK6 (TK_STATUS_TKIF6_Msk) /*!< Touch key 6 threshold control interrupt */
+#define TK_INT_SCAN_TH_TK7 (TK_STATUS_TKIF7_Msk) /*!< Touch key 7 threshold control interrupt */
+#define TK_INT_SCAN_TH_TK8 (TK_STATUS_TKIF8_Msk) /*!< Touch key 8 threshold control interrupt */
+#define TK_INT_SCAN_TH_TK9 (TK_STATUS_TKIF9_Msk) /*!< Touch key 9 threshold control interrupt */
+#define TK_INT_SCAN_TH_TK10 (TK_STATUS_TKIF10_Msk) /*!< Touch key 10 threshold control interrupt */
+#define TK_INT_SCAN_TH_TK11 (TK_STATUS_TKIF11_Msk) /*!< Touch key 11 threshold control interrupt */
+#define TK_INT_SCAN_TH_TK12 (TK_STATUS_TKIF12_Msk) /*!< Touch key 12 threshold control interrupt */
+#define TK_INT_SCAN_TH_TK13 (TK_STATUS_TKIF13_Msk) /*!< Touch key 13 threshold control interrupt */
+#define TK_INT_SCAN_TH_TK14 (TK_STATUS_TKIF14_Msk) /*!< Touch key 14 threshold control interrupt */
+#define TK_INT_SCAN_TH_TK15 (TK_STATUS_TKIF15_Msk) /*!< Touch key 15 threshold control interrupt */
+#define TK_INT_SCAN_TH_TK16 (TK_STATUS_TKIF16_Msk) /*!< Touch key 16 threshold control interrupt */
+
+
+/*@}*/ /* end of group TK_EXPORTED_CONSTANTS */
+
+
+/** @addtogroup TK_EXPORTED_FUNCTIONS TK Exported Functions
+ @{
+*/
+
+/**
+ * @brief Enable scan key(s)
+ * @param[in] u32Mask Combination of enabled scan keys. Each bit corresponds to a touch key.
+ * Bit 0 represents touch key 0, bit 1 represents touch key 1...
+ * @return None
+ * @note Touch key 16 is the default reference key, so touch key 16 is enabled.
+ * \hideinitializer
+ */
+#define TK_ENABLE_SCAN_KEY(u32Mask) (TK->CTL |= (u32Mask))
+
+/**
+ * @brief Disable scan key(s)
+ * @param[in] u32Mask Combination of disabled scan keys. Each bit corresponds to a touch key.
+ * Bit 0 represents touch key 0, bit 1 represents touch key 1...
+ * @return None
+ * \hideinitializer
+ */
+#define TK_DISABLE_SCAN_KEY(u32Mask) (TK->CTL &= ~(u32Mask))
+
+/**
+ * @brief Enable reference key(s)
+ * @param[in] u32Mask Combination of enabled reference keys. Each bit corresponds to a touch key.
+ * Bit 0 represents touch key 0, bit 1 represents touch key 1...
+ * @return None
+ * @note Touch key 16 is the default reference key, so touch key 16 is enabled.
+ * \hideinitializer
+ */
+#define TK_ENABLE_REF_KEY(u32Mask) (TK->REFCTL |= (u32Mask))
+
+/**
+ * @brief Disable reference key(s)
+ * @param[in] u32Mask Combination of disabled reference keys. Each bit corresponds to a touch key.
+ * Bit 0 represents touch key 0, bit 1 represents touch key 1...
+ * @return None
+ * @note It must enable a reference key and touch key 16 is the default reference key.
+ * If no any one touch key as reference key except touch key 16, then reference Touch key 16 can't be disable.
+ * \hideinitializer
+ */
+#define TK_DISABLE_REF_KEY(u32Mask) (TK->REFCTL &= ~(u32Mask))
+
+/**
+ * @brief Initiate enabled key(s) scan immediately.
+ * @param None
+ * @return None
+ * \hideinitializer
+ */
+#define TK_START_SCAN() (TK->CTL |= TK_CTL_SCAN_Msk)
+
+/**
+ * @brief Set touch key Sensing pulse width.
+ * @param[in] u32PulseWidth Sensing pulse width.
+ * - \ref TK_SENSE_PULSE_1
+ * - \ref TK_SENSE_PULSE_2
+ * - \ref TK_SENSE_PULSE_4
+ * - \ref TK_SENSE_PULSE_8
+ * @return None
+ * \hideinitializer
+ */
+#define TK_SET_PULSE_WIDTH(u32PulseWidth) (TK->REFCTL = (TK->REFCTL & ~TK_REFCTL_SENPTCTL_Msk) | (u32PulseWidth))
+
+/**
+ * @brief Set touch key Sensing count.
+ * @param[in] u32SenseCnt Sensing count.
+ * - \ref TK_SENSE_CNT_128
+ * - \ref TK_SENSE_CNT_255
+ * - \ref TK_SENSE_CNT_511
+ * - \ref TK_SENSE_CNT_1023
+ * @return None
+ * \hideinitializer
+ */
+#define TK_SET_SENSING_CNT(u32SenseCnt) (TK->REFCTL = (TK->REFCTL & ~TK_REFCTL_SENTCTL_Msk) | (u32SenseCnt))
+
+
+/**
+ * @brief Set touch key AVCCH voltage.
+ * @param[in] u32AVCCHSel voltage selection.
+ * - \ref TK_AVCCH_1_DIV_16
+ * - \ref TK_AVCCH_1_DIV_8
+ * - \ref TK_AVCCH_3_DIV_16
+ * - \ref TK_AVCCH_1_DIV_4
+ * - \ref TK_AVCCH_5_DIV_16
+ * - \ref TK_AVCCH_3_DIV_8
+ * - \ref TK_AVCCH_7_DIV_16
+ * - \ref TK_AVCCH_1_DIV_2
+ * @return None
+ * \hideinitializer
+ */
+#define TK_SET_AVCCH(u32AVCCHSel) (TK->CTL = (TK->CTL & ~TK_CTL_AVCCHSEL_Msk) | (u32AVCCHSel))
+
+/**
+ * @brief Get touch key complement capacitor bank data.
+ * @param[in] u32TKNum Touch key number. The valid value is 0~16.
+ * @return Complement capacitor bank data
+ * \hideinitializer
+ */
+#define TK_GET_COMP_CAP_BANK_DATA(u32TKNum) (((*(__IO uint32_t *) (&(TK->CCBDAT0) + ((u32TKNum) >> 2))) >> ((u32TKNum) % 4 * 8) & TK_CCBDAT0_CCBDAT0_Msk))
+
+/**
+ * @brief Get touch key sensing result data.
+ * @param[in] u32TKNum Touch key number. The valid value is 0~16.
+ * @return Sensing result data
+ * \hideinitializer
+ */
+#define TK_GET_SENSE_DATA(u32TKNum) (((*(__IO uint32_t *) (&(TK->DAT0) + ((u32TKNum) >> 2))) >> ((u32TKNum) % 4 * 8) & TK_DAT0_TKDAT0_Msk))
+
+/**
+ * @brief Get touch key busy status.
+ * @param None
+ * @retval 0 Touch key is scan completed or stopped.
+ * @retval 1 Touch key is busy.
+ * \hideinitializer
+ */
+#define TK_IS_BUSY() ((TK->STATUS & TK_STATUS_BUSY_Msk) ? 1: 0)
+
+/**
+ * @brief Get touch key interrupt flag.
+ * @param[in] u32Mask Interrupt flag type selection.
+ * - \ref TK_INT_SCAN_COMPLETE
+ * - \ref TK_INT_SCAN_COMPLETE_TH_ALL
+ * - \ref TK_INT_SCAN_TH_ALL
+ * - \ref TK_INT_SCAN_TH_TK0
+ * - \ref TK_INT_SCAN_TH_TK1
+ * - \ref TK_INT_SCAN_TH_TK2
+ * - \ref TK_INT_SCAN_TH_TK3
+ * - \ref TK_INT_SCAN_TH_TK4
+ * - \ref TK_INT_SCAN_TH_TK5
+ * - \ref TK_INT_SCAN_TH_TK6
+ * - \ref TK_INT_SCAN_TH_TK7
+ * - \ref TK_INT_SCAN_TH_TK8
+ * - \ref TK_INT_SCAN_TH_TK9
+ * - \ref TK_INT_SCAN_TH_TK10
+ * - \ref TK_INT_SCAN_TH_TK11
+ * - \ref TK_INT_SCAN_TH_TK12
+ * - \ref TK_INT_SCAN_TH_TK13
+ * - \ref TK_INT_SCAN_TH_TK14
+ * - \ref TK_INT_SCAN_TH_TK15
+ * - \ref TK_INT_SCAN_TH_TK16
+ * @retval 0 Touch key has no interrupt.
+ * @retval 1 Touch key is scan completed or threshold control event occurs.
+ * \hideinitializer
+ */
+#define TK_GET_INT_STATUS(u32Mask) ((TK->STATUS & (u32Mask)) ? 1: 0)
+
+/**
+ * @brief Clear touch key interrupt flag.
+ * @param[in] u32Mask Interrupt flag type selection.
+ * - \ref TK_INT_SCAN_COMPLETE
+ * - \ref TK_INT_SCAN_COMPLETE_TH_ALL
+ * - \ref TK_INT_SCAN_TH_ALL
+ * - \ref TK_INT_SCAN_TH_TK0
+ * - \ref TK_INT_SCAN_TH_TK1
+ * - \ref TK_INT_SCAN_TH_TK2
+ * - \ref TK_INT_SCAN_TH_TK3
+ * - \ref TK_INT_SCAN_TH_TK4
+ * - \ref TK_INT_SCAN_TH_TK5
+ * - \ref TK_INT_SCAN_TH_TK6
+ * - \ref TK_INT_SCAN_TH_TK7
+ * - \ref TK_INT_SCAN_TH_TK8
+ * - \ref TK_INT_SCAN_TH_TK9
+ * - \ref TK_INT_SCAN_TH_TK10
+ * - \ref TK_INT_SCAN_TH_TK11
+ * - \ref TK_INT_SCAN_TH_TK12
+ * - \ref TK_INT_SCAN_TH_TK13
+ * - \ref TK_INT_SCAN_TH_TK14
+ * - \ref TK_INT_SCAN_TH_TK15
+ * - \ref TK_INT_SCAN_TH_TK16
+ * @return None
+ * \hideinitializer
+ */
+#define TK_CLR_INT_FLAG(u32Mask) (TK->STATUS = (u32Mask))
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Define TK functions prototype */
+/*---------------------------------------------------------------------------------------------------------*/
+void TK_Open(void);
+void TK_Close(void);
+void TK_SetScanMode(uint32_t u32Mode);
+void TK_ConfigSensitivity(uint32_t u32PulseWidth, uint32_t u32SenseCnt, uint32_t u32AVCCHSel);
+void TK_SetCapBankPol(uint32_t u32CapBankPolSel);
+void TK_EnableTkPolarity(uint32_t u32Mask);
+void TK_DisableTkPolarity(uint32_t u32Mask);
+void TK_SetCompCapBankData(uint32_t u32TKNum, uint32_t u32CapData);
+void TK_SetTkPol(uint32_t u32Mask, uint32_t u32PolSel);
+void TK_SetRefKeyCapBankData(uint32_t u32CapData);
+void TK_SetScanThreshold(uint32_t u32TKNum, uint32_t u32HighLevel, uint32_t u32LowLevel);
+void TK_EnableInt(uint32_t u32Msk);
+void TK_DisableInt(uint32_t u32Msk);
+
+
+/*@}*/ /* end of group TK_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group TK_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif //__TK_H__
+
+/*** (C) COPYRIGHT 2014~2015 Nuvoton Technology Corp. ***/
diff --git a/bsp/nuvoton_m451/Libraries/StdDriver/inc/uart.h b/bsp/nuvoton_m451/Libraries/StdDriver/inc/uart.h
new file mode 100644
index 0000000000000000000000000000000000000000..071f4ff7b5d9b444a51c48e8bc19ef07d3458342
--- /dev/null
+++ b/bsp/nuvoton_m451/Libraries/StdDriver/inc/uart.h
@@ -0,0 +1,460 @@
+/******************************************************************************
+ * @file uart.h
+ * @version V3.00
+ * $Revision: 36 $
+ * $Date: 15/08/11 10:26a $
+ * @brief M451 series UART driver header file
+ *
+ * @note
+ * Copyright (C) 2013~2015 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#ifndef __UART_H__
+#define __UART_H__
+
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup Standard_Driver Standard Driver
+ @{
+*/
+
+/** @addtogroup UART_Driver UART Driver
+ @{
+*/
+
+/** @addtogroup UART_EXPORTED_CONSTANTS UART Exported Constants
+ @{
+*/
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* UART FIFO size constants definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+
+#define UART0_FIFO_SIZE 16 /*!< UART0 supports separated receive/transmit 16/16 bytes entry FIFO */
+#define UART1_FIFO_SIZE 16 /*!< UART1 supports separated receive/transmit 16/16 bytes entry FIFO */
+#define UART2_FIFO_SIZE 16 /*!< UART2 supports separated receive/transmit 16/16 bytes entry FIFO */
+#define UART3_FIFO_SIZE 16 /*!< UART3 supports separated receive/transmit 16/16 bytes entry FIFO */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* UART_FIFO constants definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+
+#define UART_FIFO_RFITL_1BYTE (0x0 << UART_FIFO_RFITL_Pos) /*!< UART_FIFO setting to set RX FIFO Trigger Level to 1 byte */
+#define UART_FIFO_RFITL_4BYTES (0x1 << UART_FIFO_RFITL_Pos) /*!< UART_FIFO setting to set RX FIFO Trigger Level to 4 bytes */
+#define UART_FIFO_RFITL_8BYTES (0x2 << UART_FIFO_RFITL_Pos) /*!< UART_FIFO setting to set RX FIFO Trigger Level to 8 bytes */
+#define UART_FIFO_RFITL_14BYTES (0x3 << UART_FIFO_RFITL_Pos) /*!< UART_FIFO setting to set RX FIFO Trigger Level to 14 bytes */
+
+#define UART_FIFO_RTSTRGLV_1BYTE (0x0 << UART_FIFO_RTSTRGLV_Pos) /*!< UART_FIFO setting to set RTS Trigger Level to 1 byte */
+#define UART_FIFO_RTSTRGLV_4BYTES (0x1 << UART_FIFO_RTSTRGLV_Pos) /*!< UART_FIFO setting to set RTS Trigger Level to 4 bytes */
+#define UART_FIFO_RTSTRGLV_8BYTES (0x2 << UART_FIFO_RTSTRGLV_Pos) /*!< UART_FIFO setting to set RTS Trigger Level to 8 bytes */
+#define UART_FIFO_RTSTRGLV_14BYTES (0x3 << UART_FIFO_RTSTRGLV_Pos) /*!< UART_FIFO setting to set RTS Trigger Level to 14 bytes */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* UART_LINE constants definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define UART_WORD_LEN_5 (0) /*!< UART_LINE setting to set UART word length to 5 bits */
+#define UART_WORD_LEN_6 (1) /*!< UART_LINE setting to set UART word length to 6 bits */
+#define UART_WORD_LEN_7 (2) /*!< UART_LINE setting to set UART word length to 7 bits */
+#define UART_WORD_LEN_8 (3) /*!< UART_LINE setting to set UART word length to 8 bits */
+
+#define UART_PARITY_NONE (0x0 << UART_LINE_PBE_Pos) /*!< UART_LINE setting to set UART as no parity */
+#define UART_PARITY_ODD (0x1 << UART_LINE_PBE_Pos) /*!< UART_LINE setting to set UART as odd parity */
+#define UART_PARITY_EVEN (0x3 << UART_LINE_PBE_Pos) /*!< UART_LINE setting to set UART as even parity */
+#define UART_PARITY_MARK (0x5 << UART_LINE_PBE_Pos) /*!< UART_LINE setting to keep parity bit as '1' */
+#define UART_PARITY_SPACE (0x7 << UART_LINE_PBE_Pos) /*!< UART_LINE setting to keep parity bit as '0' */
+
+#define UART_STOP_BIT_1 (0x0 << UART_LINE_NSB_Pos) /*!< UART_LINE setting for one stop bit */
+#define UART_STOP_BIT_1_5 (0x1 << UART_LINE_NSB_Pos) /*!< UART_LINE setting for 1.5 stop bit when 5-bit word length */
+#define UART_STOP_BIT_2 (0x1 << UART_LINE_NSB_Pos) /*!< UART_LINE setting for two stop bit when 6, 7, 8-bit word length */
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* UART RTS ACTIVE LEVEL constants definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define UART_RTS_IS_LOW_LEV_ACTIVE (0x1 << UART_MODEM_RTSACTLV_Pos) /*!< Set RTS is Low Level Active */
+#define UART_RTS_IS_HIGH_LEV_ACTIVE (0x0 << UART_MODEM_RTSACTLV_Pos) /*!< Set RTS is High Level Active */
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* UART_IRDA constants definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define UART_IRDA_TXEN (0x1 << UART_IRDA_TXEN_Pos) /*!< Set IrDA function Tx mode */
+#define UART_IRDA_RXEN (0x0 << UART_IRDA_TXEN_Pos) /*!< Set IrDA function Rx mode */
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* UART_FUNCSEL constants definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define UART_FUNCSEL_UART (0x0 << UART_FUNCSEL_FUNCSEL_Pos) /*!< UART_FUNCSEL setting to set UART Function (Default) */
+#define UART_FUNCSEL_LIN (0x1 << UART_FUNCSEL_FUNCSEL_Pos) /*!< UART_FUNCSEL setting to set LIN Function */
+#define UART_FUNCSEL_IrDA (0x2 << UART_FUNCSEL_FUNCSEL_Pos) /*!< UART_FUNCSEL setting to set IrDA Function */
+#define UART_FUNCSEL_RS485 (0x3 << UART_FUNCSEL_FUNCSEL_Pos) /*!< UART_FUNCSEL setting to set RS485 Function */
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* UART_LINCTL constants definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define UART_LINCTL_BRKFL(x) (((x)-1) << UART_LINCTL_BRKFL_Pos) /*!< UART_LINCTL setting to set LIN Break Field Length, x = 10 ~ 15, default value is 12 */
+#define UART_LINCTL_BSL(x) (((x)-1) << UART_LINCTL_BSL_Pos) /*!< UART_LINCTL setting to set LIN Break/Sync Delimiter Length, x = 1 ~ 4 */
+#define UART_LINCTL_HSEL_BREAK (0x0UL << UART_LINCTL_HSEL_Pos) /*!< UART_LINCTL setting to set LIN Header Select to break field */
+#define UART_LINCTL_HSEL_BREAK_SYNC (0x1UL << UART_LINCTL_HSEL_Pos) /*!< UART_LINCTL setting to set LIN Header Select to break field and sync field */
+#define UART_LINCTL_HSEL_BREAK_SYNC_ID (0x2UL << UART_LINCTL_HSEL_Pos) /*!< UART_LINCTL setting to set LIN Header Select to break field, sync field and ID field*/
+#define UART_LINCTL_PID(x) ((x) << UART_LINCTL_PID_Pos) /*!< UART_LINCTL setting to set LIN PID value */
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* UART BAUDRATE MODE constants definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define UART_BAUD_MODE0 (0) /*!< Set UART Baudrate Mode is Mode0 */
+#define UART_BAUD_MODE2 (UART_BAUD_BAUDM1_Msk | UART_BAUD_BAUDM0_Msk) /*!< Set UART Baudrate Mode is Mode2 */
+
+
+/*@}*/ /* end of group UART_EXPORTED_CONSTANTS */
+
+
+/** @addtogroup UART_EXPORTED_FUNCTIONS UART Exported Functions
+ @{
+*/
+
+
+/**
+ * @brief Calculate UART baudrate mode0 divider
+ *
+ * @param[in] u32SrcFreq UART clock frequency
+ * @param[in] u32BaudRate Baudrate of UART module
+ *
+ * @return UART baudrate mode0 divider
+ *
+ * @details This macro calculate UART baudrate mode0 divider.
+ */
+#define UART_BAUD_MODE0_DIVIDER(u32SrcFreq, u32BaudRate) ((((u32SrcFreq) + ((u32BaudRate)*8)) / (u32BaudRate) >> 4)-2)
+
+
+/**
+ * @brief Calculate UART baudrate mode2 divider
+ *
+ * @param[in] u32SrcFreq UART clock frequency
+ * @param[in] u32BaudRate Baudrate of UART module
+ *
+ * @return UART baudrate mode2 divider
+ *
+ * @details This macro calculate UART baudrate mode2 divider.
+ */
+#define UART_BAUD_MODE2_DIVIDER(u32SrcFreq, u32BaudRate) ((((u32SrcFreq) + ((u32BaudRate)/2)) / (u32BaudRate))-2)
+
+
+/**
+ * @brief Write UART data
+ *
+ * @param[in] uart The pointer of the specified UART module
+ * @param[in] u8Data Data byte to transmit.
+ *
+ * @return None
+ *
+ * @details This macro write Data to Tx data register.
+ */
+#define UART_WRITE(uart, u8Data) ((uart)->DAT = (u8Data))
+
+
+/**
+ * @brief Read UART data
+ *
+ * @param[in] uart The pointer of the specified UART module
+ *
+ * @return The oldest data byte in RX FIFO.
+ *
+ * @details This macro read Rx data register.
+ */
+#define UART_READ(uart) ((uart)->DAT)
+
+
+/**
+ * @brief Get Tx empty
+ *
+ * @param[in] uart The pointer of the specified UART module
+ *
+ * @retval 0 Tx FIFO is not empty
+ * @retval >=1 Tx FIFO is empty
+ *
+ * @details This macro get Transmitter FIFO empty register value.
+ */
+#define UART_GET_TX_EMPTY(uart) ((uart)->FIFOSTS & UART_FIFOSTS_TXEMPTY_Msk)
+
+
+/**
+ * @brief Get Rx empty
+ *
+ * @param[in] uart The pointer of the specified UART module
+ *
+ * @retval 0 Rx FIFO is not empty
+ * @retval >=1 Rx FIFO is empty
+ *
+ * @details This macro get Receiver FIFO empty register value.
+ */
+#define UART_GET_RX_EMPTY(uart) ((uart)->FIFOSTS & UART_FIFOSTS_RXEMPTY_Msk)
+
+
+/**
+ * @brief Check specified uart port transmission is over.
+ *
+ * @param[in] uart The pointer of the specified UART module
+ *
+ * @retval 0 Tx transmission is not over
+ * @retval 1 Tx transmission is over
+ *
+ * @details This macro return Transmitter Empty Flag register bit value.
+ * It indicates if specified uart port transmission is over nor not.
+ */
+#define UART_IS_TX_EMPTY(uart) (((uart)->FIFOSTS & UART_FIFOSTS_TXEMPTYF_Msk) >> UART_FIFOSTS_TXEMPTYF_Pos)
+
+
+/**
+ * @brief Wait specified uart port transmission is over
+ *
+ * @param[in] uart The pointer of the specified UART module
+ *
+ * @return None
+ *
+ * @details This macro wait specified uart port transmission is over.
+ */
+#define UART_WAIT_TX_EMPTY(uart) while(!((((uart)->FIFOSTS) & UART_FIFOSTS_TXEMPTYF_Msk) >> UART_FIFOSTS_TXEMPTYF_Pos))
+
+
+/**
+ * @brief Check RX is ready or not
+ *
+ * @param[in] uart The pointer of the specified UART module
+ *
+ * @retval 0 The number of bytes in the RX FIFO is less than the RFITL
+ * @retval 1 The number of bytes in the RX FIFO equals or larger than RFITL
+ *
+ * @details This macro check receive data available interrupt flag is set or not.
+ */
+#define UART_IS_RX_READY(uart) (((uart)->INTSTS & UART_INTSTS_RDAIF_Msk)>>UART_INTSTS_RDAIF_Pos)
+
+
+/**
+ * @brief Check TX FIFO is full or not
+ *
+ * @param[in] uart The pointer of the specified UART module
+ *
+ * @retval 1 TX FIFO is full
+ * @retval 0 TX FIFO is not full
+ *
+ * @details This macro check TX FIFO is full or not.
+ */
+#define UART_IS_TX_FULL(uart) (((uart)->FIFOSTS & UART_FIFOSTS_TXFULL_Msk)>>UART_FIFOSTS_TXFULL_Pos)
+
+
+/**
+ * @brief Check RX FIFO is full or not
+ *
+ * @param[in] uart The pointer of the specified UART module
+ *
+ * @retval 1 RX FIFO is full
+ * @retval 0 RX FIFO is not full
+ *
+ * @details This macro check RX FIFO is full or not.
+ */
+#define UART_IS_RX_FULL(uart) (((uart)->FIFOSTS & UART_FIFOSTS_RXFULL_Msk)>>UART_FIFOSTS_RXFULL_Pos)
+
+
+/**
+ * @brief Get Tx full register value
+ *
+ * @param[in] uart The pointer of the specified UART module
+ *
+ * @retval 0 Tx FIFO is not full.
+ * @retval >=1 Tx FIFO is full.
+ *
+ * @details This macro get Tx full register value.
+ */
+#define UART_GET_TX_FULL(uart) ((uart)->FIFOSTS & UART_FIFOSTS_TXFULL_Msk)
+
+
+/**
+ * @brief Get Rx full register value
+ *
+ * @param[in] uart The pointer of the specified UART module
+ *
+ * @retval 0 Rx FIFO is not full.
+ * @retval >=1 Rx FIFO is full.
+ *
+ * @details This macro get Rx full register value.
+ */
+#define UART_GET_RX_FULL(uart) ((uart)->FIFOSTS & UART_FIFOSTS_RXFULL_Msk)
+
+
+/**
+ * @brief Enable specified UART interrupt
+ *
+ * @param[in] uart The pointer of the specified UART module
+ * @param[in] u32eIntSel Interrupt type select
+ * - \ref UART_INTEN_ABRIEN_Msk : Auto baud rate interrupt
+ * - \ref UART_INTEN_WKCTSIEN_Msk : CTS wakeup interrupt
+ * - \ref UART_INTEN_WKDATIEN_Msk : Data wakeup interrupt
+ * - \ref UART_INTEN_LINIEN_Msk : Lin bus interrupt
+ * - \ref UART_INTEN_BUFERRIEN_Msk : Buffer Error interrupt
+ * - \ref UART_INTEN_RXTOIEN_Msk : Rx time-out interrupt
+ * - \ref UART_INTEN_MODEMIEN_Msk : Modem interrupt
+ * - \ref UART_INTEN_RLSIEN_Msk : Rx Line status interrupt
+ * - \ref UART_INTEN_THREIEN_Msk : Tx empty interrupt
+ * - \ref UART_INTEN_RDAIEN_Msk : Rx ready interrupt
+ *
+ * @return None
+ *
+ * @details This macro enable specified UART interrupt.
+ */
+#define UART_ENABLE_INT(uart, u32eIntSel) ((uart)->INTEN |= (u32eIntSel))
+
+
+/**
+ * @brief Disable specified UART interrupt
+ *
+ * @param[in] uart The pointer of the specified UART module
+ * @param[in] u32eIntSel Interrupt type select
+ * - \ref UART_INTEN_ABRIEN_Msk : Auto baud rate interrupt
+ * - \ref UART_INTEN_WKCTSIEN_Msk : CTS wakeup interrupt
+ * - \ref UART_INTEN_WKDATIEN_Msk : Data wakeup interrupt
+ * - \ref UART_INTEN_LINIEN_Msk : Lin bus interrupt
+ * - \ref UART_INTEN_BUFERRIEN_Msk : Buffer Error interrupt
+ * - \ref UART_INTEN_RXTOIEN_Msk : Rx time-out interrupt
+ * - \ref UART_INTEN_MODEMIEN_Msk : Modem status interrupt
+ * - \ref UART_INTEN_RLSIEN_Msk : Receive Line status interrupt
+ * - \ref UART_INTEN_THREIEN_Msk : Tx empty interrupt
+ * - \ref UART_INTEN_RDAIEN_Msk : Rx ready interrupt
+ *
+ * @return None
+ *
+ * @details This macro enable specified UART interrupt.
+ */
+#define UART_DISABLE_INT(uart, u32eIntSel) ((uart)->INTEN &= ~ (u32eIntSel))
+
+
+/**
+ * @brief Get specified interrupt flag/status
+ *
+ * @param[in] uart The pointer of the specified UART module
+ * @param[in] u32eIntTypeFlag Interrupt Type Flag, should be
+ * - \ref UART_INTSTS_HWBUFEINT_Msk : In DMA Mode, Buffer Error Interrupt Indicator
+ * - \ref UART_INTSTS_HWTOINT_Msk : In DMA Mode, Time-out Interrupt Indicator
+ * - \ref UART_INTSTS_HWMODINT_Msk : In DMA Mode, MODEM Status Interrupt Indicator
+ * - \ref UART_INTSTS_HWRLSINT_Msk : In DMA Mode, Receive Line Status Interrupt Indicator
+ * - \ref UART_INTSTS_HWBUFEIF_Msk : In DMA Mode, Buffer Error Interrupt Flag
+ * - \ref UART_INTSTS_HWTOIF_Msk : In DMA Mode, Time-out Interrupt Flag
+ * - \ref UART_INTSTS_HWMODIF_Msk : In DMA Mode, MODEM Interrupt Flag
+ * - \ref UART_INTSTS_HWRLSIF_Msk : In DMA Mode, Receive Line Status Flag
+ * - \ref UART_INTSTS_LININT_Msk : LIN Bus Interrupt Indicator
+ * - \ref UART_INTSTS_BUFERRINT_Msk : Buffer Error Interrupt Indicator
+ * - \ref UART_INTSTS_RXTOINT_Msk : Time-out Interrupt Indicator
+ * - \ref UART_INTSTS_MODEMINT_Msk : Modem Status Interrupt Indicator
+ * - \ref UART_INTSTS_RLSINT_Msk : Receive Line Status Interrupt Indicator
+ * - \ref UART_INTSTS_THREINT_Msk : Transmit Holding Register Empty Interrupt Indicator
+ * - \ref UART_INTSTS_RDAINT_Msk : Receive Data Available Interrupt Indicator
+ * - \ref UART_INTSTS_LINIF_Msk : LIN Bus Flag
+ * - \ref UART_INTSTS_BUFERRIF_Msk : Buffer Error Interrupt Flag
+ * - \ref UART_INTSTS_RXTOIF_Msk : Rx Time-out Interrupt Flag
+ * - \ref UART_INTSTS_MODEMIF_Msk : Modem Interrupt Flag
+ * - \ref UART_INTSTS_RLSIF_Msk : Receive Line Status Interrupt Flag
+ * - \ref UART_INTSTS_THREIF_Msk : Tx Empty Interrupt Flag
+ * - \ref UART_INTSTS_RDAIF_Msk : Rx Ready Interrupt Flag
+ *
+ * @retval 0 The specified interrupt is not happened.
+ * 1 The specified interrupt is happened.
+ *
+ * @details This macro get specified interrupt flag or interrupt indicator status.
+ */
+#define UART_GET_INT_FLAG(uart,u32eIntTypeFlag) (((uart)->INTSTS & (u32eIntTypeFlag))?1:0)
+
+
+/**
+ * @brief Set RTS pin to low
+ *
+ * @param[in] uart The pointer of the specified UART module
+ *
+ * @return None
+ *
+ * @details This macro set RTS pin to low.
+ */
+__STATIC_INLINE void UART_CLEAR_RTS(UART_T* uart)
+{
+ uart->MODEM |= UART_MODEM_RTSACTLV_Msk;
+ uart->MODEM &= ~UART_MODEM_RTS_Msk;
+}
+
+
+/**
+ * @brief Set RTS pin to high
+ *
+ * @param[in] uart The pointer of the specified UART module
+ *
+ * @return None
+ *
+ * @details This macro set RTS pin to high.
+ */
+__STATIC_INLINE void UART_SET_RTS(UART_T* uart)
+{
+ uart->MODEM |= UART_MODEM_RTSACTLV_Msk | UART_MODEM_RTS_Msk;
+}
+
+
+/**
+ * @brief Clear RS-485 Address Byte Detection Flag
+ *
+ * @param[in] uart The pointer of the specified UART module
+ *
+ * @return None
+ *
+ * @details This macro clear RS-485 address byte detection flag.
+ */
+#define UART_RS485_CLEAR_ADDR_FLAG(uart) ((uart)->FIFOSTS = UART_FIFOSTS_ADDRDETF_Msk)
+
+
+/**
+ * @brief Get RS-485 Address Byte Detection Flag
+ *
+ * @param[in] uart The pointer of the specified UART module
+ *
+ * @retval 0 Receiver detects a data that is not an address bit.
+ * @retval 1 Receiver detects a data that is an address bit.
+ *
+ * @details This macro get RS-485 address byte detection flag.
+ */
+#define UART_RS485_GET_ADDR_FLAG(uart) (((uart)->FIFOSTS & UART_FIFOSTS_ADDRDETF_Msk) >> UART_FIFOSTS_ADDRDETF_Pos)
+
+
+void UART_ClearIntFlag(UART_T* uart , uint32_t u32InterruptFlag);
+void UART_Close(UART_T* uart);
+void UART_DisableFlowCtrl(UART_T* uart);
+void UART_DisableInt(UART_T* uart, uint32_t u32InterruptFlag);
+void UART_EnableFlowCtrl(UART_T* uart);
+void UART_EnableInt(UART_T* uart, uint32_t u32InterruptFlag);
+void UART_Open(UART_T* uart, uint32_t u32baudrate);
+uint32_t UART_Read(UART_T* uart, uint8_t *pu8RxBuf, uint32_t u32ReadBytes);
+void UART_SetLine_Config(UART_T* uart, uint32_t u32baudrate, uint32_t u32data_width, uint32_t u32parity, uint32_t u32stop_bits);
+void UART_SetTimeoutCnt(UART_T* uart, uint32_t u32TOC);
+void UART_SelectIrDAMode(UART_T* uart, uint32_t u32Buadrate, uint32_t u32Direction);
+void UART_SelectRS485Mode(UART_T* uart, uint32_t u32Mode, uint32_t u32Addr);
+void UART_SelectLINMode(UART_T* uart, uint32_t u32Mode, uint32_t u32BreakLength);
+uint32_t UART_Write(UART_T* uart, uint8_t *pu8TxBuf, uint32_t u32WriteBytes);
+
+
+
+
+/*@}*/ /* end of group UART_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group UART_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif //__UART_H__
+
+/*** (C) COPYRIGHT 2013~2015 Nuvoton Technology Corp. ***/
diff --git a/bsp/nuvoton_m451/Libraries/StdDriver/inc/usbd.h b/bsp/nuvoton_m451/Libraries/StdDriver/inc/usbd.h
new file mode 100644
index 0000000000000000000000000000000000000000..3943b8476b4eb246451334064c70e933815c4956
--- /dev/null
+++ b/bsp/nuvoton_m451/Libraries/StdDriver/inc/usbd.h
@@ -0,0 +1,657 @@
+/******************************************************************************
+ * @file usbd.h
+ * @brief M451 series USB driver header file
+ * @version 2.0.0
+ * @date 10, January, 2014
+ *
+ * @note
+ * Copyright (C) 2014~2015 Nuvoton Technology Corp. All rights reserved.
+ ******************************************************************************/
+#ifndef __USBD_H__
+#define __USBD_H__
+
+
+/** @addtogroup Standard_Driver Standard Driver
+ @{
+*/
+
+/** @addtogroup USBD_Driver USBD Driver
+ @{
+*/
+
+/** @addtogroup USBD_EXPORTED_STRUCTS USBD Exported Structs
+ @{
+*/
+typedef struct s_usbd_info
+{
+ const uint8_t *gu8DevDesc; /*!< Pointer for USB Device Descriptor */
+ const uint8_t *gu8ConfigDesc; /*!< Pointer for USB Configuration Descriptor */
+ const uint8_t **gu8StringDesc; /*!< Pointer for USB String Descriptor pointers */
+ const uint8_t **gu8HidReportDesc; /*!< Pointer for USB HID Report Descriptor */
+ const uint32_t *gu32HidReportSize; /*!< Pointer for HID Report descriptor Size */
+ const uint32_t *gu32ConfigHidDescIdx; /*!< Pointer for HID Descriptor start index */
+
+} S_USBD_INFO_T;
+
+extern const S_USBD_INFO_T gsInfo;
+
+/*@}*/ /* end of group USBD_EXPORTED_STRUCTS */
+
+
+
+
+/** @addtogroup USBD_EXPORTED_CONSTANTS USBD Exported Constants
+ @{
+*/
+#define USBD_BUF_BASE (USBD_BASE+0x100)
+#define USBD_MAX_EP 8
+
+#define EP0 0 /*!< Endpoint 0 */
+#define EP1 1 /*!< Endpoint 1 */
+#define EP2 2 /*!< Endpoint 2 */
+#define EP3 3 /*!< Endpoint 3 */
+#define EP4 4 /*!< Endpoint 4 */
+#define EP5 5 /*!< Endpoint 5 */
+#define EP6 6 /*!< Endpoint 6 */
+#define EP7 7 /*!< Endpoint 7 */
+
+
+/*! b, then return a. Otherwise, return b.
+ */
+#define Maximum(a,b) ((a)>(b) ? (a) : (b))
+
+
+/**
+ * @brief Compare two input numbers and return minimum one
+ *
+ * @param[in] a First number to be compared
+ * @param[in] b Second number to be compared
+ *
+ * @return Minimum value between a and b
+ *
+ * @details If a < b, then return a. Otherwise, return b.
+ */
+#define Minimum(a,b) ((a)<(b) ? (a) : (b))
+
+
+/**
+ * @brief Enable USB
+ *
+ * @param None
+ *
+ * @return None
+ *
+ * @details To set USB ATTR control register to enable USB and PHY.
+ *
+ */
+#define USBD_ENABLE_USB() ((uint32_t)(USBD->ATTR |= (USBD_USB_EN|USBD_PHY_EN)))
+
+/**
+ * @brief Disable USB
+ *
+ * @param None
+ *
+ * @return None
+ *
+ * @details To set USB ATTR control register to disable USB.
+ *
+ */
+#define USBD_DISABLE_USB() ((uint32_t)(USBD->ATTR &= ~USBD_USB_EN))
+
+/**
+ * @brief Enable USB PHY
+ *
+ * @param None
+ *
+ * @return None
+ *
+ * @details To set USB ATTR control register to enable USB PHY.
+ *
+ */
+#define USBD_ENABLE_PHY() ((uint32_t)(USBD->ATTR |= USBD_PHY_EN))
+
+/**
+ * @brief Disable USB PHY
+ *
+ * @param None
+ *
+ * @return None
+ *
+ * @details To set USB ATTR control register to disable USB PHY.
+ *
+ */
+#define USBD_DISABLE_PHY() ((uint32_t)(USBD->ATTR &= ~USBD_PHY_EN))
+
+/**
+ * @brief Enable SE0. Force USB PHY transceiver to drive SE0.
+ *
+ * @param None
+ *
+ * @return None
+ *
+ * @details Set DRVSE0 bit of USB_DRVSE0 register to enable software-disconnect function. Force USB PHY transceiver to drive SE0 to bus.
+ *
+ */
+#define USBD_SET_SE0() ((uint32_t)(USBD->SE0 |= USBD_DRVSE0))
+
+/**
+ * @brief Disable SE0
+ *
+ * @param None
+ *
+ * @return None
+ *
+ * @details Clear DRVSE0 bit of USB_DRVSE0 register to disable software-disconnect function.
+ *
+ */
+#define USBD_CLR_SE0() ((uint32_t)(USBD->SE0 &= ~USBD_DRVSE0))
+
+/**
+ * @brief Set USB device address
+ *
+ * @param[in] addr The USB device address.
+ *
+ * @return None
+ *
+ * @details Write USB device address to USB_FADDR register.
+ *
+ */
+#define USBD_SET_ADDR(addr) (USBD->FADDR = (addr))
+
+/**
+ * @brief Get USB device address
+ *
+ * @param None
+ *
+ * @return USB device address
+ *
+ * @details Read USB_FADDR register to get USB device address.
+ *
+ */
+#define USBD_GET_ADDR() ((uint32_t)(USBD->FADDR))
+
+/**
+ * @brief Enable USB interrupt function
+ *
+ * @param[in] intr The combination of the specified interrupt enable bits.
+ * Each bit corresponds to a interrupt enable bit.
+ * This parameter decides which interrupts will be enabled.
+ * (USBD_INT_WAKEUP, USBD_INT_FLDET, USBD_INT_USB, USBD_INT_BUS)
+ *
+ * @return None
+ *
+ * @details Enable USB related interrupt functions specified by intr parameter.
+ *
+ */
+#define USBD_ENABLE_INT(intr) (USBD->INTEN |= (intr))
+
+/**
+ * @brief Get interrupt status
+ *
+ * @param None
+ *
+ * @return The value of USB_INTSTS register
+ *
+ * @details Return all interrupt flags of USB_INTSTS register.
+ *
+ */
+#define USBD_GET_INT_FLAG() ((uint32_t)(USBD->INTSTS))
+
+/**
+ * @brief Clear USB interrupt flag
+ *
+ * @param[in] flag The combination of the specified interrupt flags.
+ * Each bit corresponds to a interrupt source.
+ * This parameter decides which interrupt flags will be cleared.
+ * (USBD_INTSTS_WAKEUP, USBD_INTSTS_FLDET, USBD_INTSTS_BUS, USBD_INTSTS_USB)
+ *
+ * @return None
+ *
+ * @details Clear USB related interrupt flags specified by flag parameter.
+ *
+ */
+#define USBD_CLR_INT_FLAG(flag) (USBD->INTSTS = (flag))
+
+/**
+ * @brief Get endpoint status
+ *
+ * @param None
+ *
+ * @return The value of USB_EPSTS register.
+ *
+ * @details Return all endpoint status.
+ *
+ */
+#define USBD_GET_EP_FLAG() ((uint32_t)(USBD->EPSTS))
+
+/**
+ * @brief Get USB bus state
+ *
+ * @param None
+ *
+ * @return The value of USB_ATTR[3:0].
+ * Bit 0 indicates USB bus reset status.
+ * Bit 1 indicates USB bus suspend status.
+ * Bit 2 indicates USB bus resume status.
+ * Bit 3 indicates USB bus time-out status.
+ *
+ * @details Return USB_ATTR[3:0] for USB bus events.
+ *
+ */
+#define USBD_GET_BUS_STATE() ((uint32_t)(USBD->ATTR & 0xf))
+
+/**
+ * @brief Check cable connection state
+ *
+ * @param None
+ *
+ * @retval 0 USB cable is not attached.
+ * @retval 1 USB cable is attached.
+ *
+ * @details Check the connection state by FLDET bit of USB_FLDET register.
+ *
+ */
+#define USBD_IS_ATTACHED() ((uint32_t)(USBD->VBUSDET & USBD_VBUSDET_VBUSDET_Msk))
+
+/**
+ * @brief Stop USB transaction of the specified endpoint ID
+ *
+ * @param[in] ep The USB endpoint ID. M451 Series supports 8 hardware endpoint ID. This parameter could be 0 ~ 7.
+ *
+ * @return None
+ *
+ * @details Write 1 to CLRRDY bit of USB_CFGPx register to stop USB transaction of the specified endpoint ID.
+ *
+ */
+#define USBD_STOP_TRANSACTION(ep) (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFGP + (uint32_t)((ep) << 4))) |= USBD_CFGP_CLRRDY_Msk)
+
+/**
+ * @brief Set USB DATA1 PID for the specified endpoint ID
+ *
+ * @param[in] ep The USB endpoint ID. M451 Series supports 8 hardware endpoint ID. This parameter could be 0 ~ 7.
+ *
+ * @return None
+ *
+ * @details Set DSQ_SYNC bit of USB_CFGx register to specify the DATA1 PID for the following IN token transaction.
+ * Base on this setting, hardware will toggle PID between DATA0 and DATA1 automatically for IN token transactions.
+ *
+ */
+#define USBD_SET_DATA1(ep) (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFG + (uint32_t)((ep) << 4))) |= USBD_CFG_DSQSYNC_Msk)
+
+/**
+ * @brief Set USB DATA0 PID for the specified endpoint ID
+ *
+ * @param[in] ep The USB endpoint ID. M451 Series supports 8 hardware endpoint ID. This parameter could be 0 ~ 7.
+ *
+ * @return None
+ *
+ * @details Clear DSQ_SYNC bit of USB_CFGx register to specify the DATA0 PID for the following IN token transaction.
+ * Base on this setting, hardware will toggle PID between DATA0 and DATA1 automatically for IN token transactions.
+ *
+ */
+#define USBD_SET_DATA0(ep) (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFG + (uint32_t)((ep) << 4))) &= (~USBD_CFG_DSQSYNC_Msk))
+
+/**
+ * @brief Set USB payload size (IN data)
+ *
+ * @param[in] ep The USB endpoint ID. M451 Series supports 8 hardware endpoint ID. This parameter could be 0 ~ 7.
+ *
+ * @param[in] size The transfer length.
+ *
+ * @return None
+ *
+ * @details This macro will write the transfer length to USB_MXPLDx register for IN data transaction.
+ *
+ */
+#define USBD_SET_PAYLOAD_LEN(ep, size) (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].MXPLD + (uint32_t)((ep) << 4))) = (size))
+
+/**
+ * @brief Get USB payload size (OUT data)
+ *
+ * @param[in] ep The USB endpoint ID. M451 Series supports 8 endpoint ID. This parameter could be 0 ~ 7.
+ *
+ * @return The value of USB_MXPLDx register.
+ *
+ * @details Get the data length of OUT data transaction by reading USB_MXPLDx register.
+ *
+ */
+#define USBD_GET_PAYLOAD_LEN(ep) ((uint32_t)*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].MXPLD + (uint32_t)((ep) << 4))))
+
+/**
+ * @brief Configure endpoint
+ *
+ * @param[in] ep The USB endpoint ID. M451 Series supports 8 hardware endpoint ID. This parameter could be 0 ~ 7.
+ *
+ * @param[in] config The USB configuration.
+ *
+ * @return None
+ *
+ * @details This macro will write config parameter to USB_CFGx register of specified endpoint ID.
+ *
+ */
+#define USBD_CONFIG_EP(ep, config) (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFG + (uint32_t)((ep) << 4))) = (config))
+
+/**
+ * @brief Set USB endpoint buffer
+ *
+ * @param[in] ep The USB endpoint ID. M451 Series supports 8 hardware endpoint ID. This parameter could be 0 ~ 7.
+ *
+ * @param[in] offset The SRAM offset.
+ *
+ * @return None
+ *
+ * @details This macro will set the SRAM offset for the specified endpoint ID.
+ *
+ */
+#define USBD_SET_EP_BUF_ADDR(ep, offset) (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].BUFSEG + (uint32_t)((ep) << 4))) = (offset))
+
+/**
+ * @brief Get the offset of the specified USB endpoint buffer
+ *
+ * @param[in] ep The USB endpoint ID. M451 Series supports 8 hardware endpoint ID. This parameter could be 0 ~ 7.
+ *
+ * @return The offset of the specified endpoint buffer.
+ *
+ * @details This macro will return the SRAM offset of the specified endpoint ID.
+ *
+ */
+#define USBD_GET_EP_BUF_ADDR(ep) ((uint32_t)*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].BUFSEG + (uint32_t)((ep) << 4))))
+
+/**
+ * @brief Set USB endpoint stall state
+ *
+ * @param[in] ep The USB endpoint ID. M451 Series supports 8 hardware endpoint ID. This parameter could be 0 ~ 7.
+ *
+ * @return None
+ *
+ * @details Set USB endpoint stall state for the specified endpoint ID. Endpoint will respond STALL token automatically.
+ *
+ */
+#define USBD_SET_EP_STALL(ep) (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFGP + (uint32_t)((ep) << 4))) |= USBD_CFGP_SSTALL_Msk)
+
+/**
+ * @brief Clear USB endpoint stall state
+ *
+ * @param[in] ep The USB endpoint ID. M451 Series supports 8 hardware endpoint ID. This parameter could be 0 ~ 7.
+ *
+ * @return None
+ *
+ * @details Clear USB endpoint stall state for the specified endpoint ID. Endpoint will respond ACK/NAK token.
+ */
+#define USBD_CLR_EP_STALL(ep) (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFGP + (uint32_t)((ep) << 4))) &= ~USBD_CFGP_SSTALL_Msk)
+
+/**
+ * @brief Get USB endpoint stall state
+ *
+ * @param[in] ep The USB endpoint ID. M451 Series supports 8 hardware endpoint ID. This parameter could be 0 ~ 7.
+ *
+ * @retval 0 USB endpoint is not stalled.
+ * @retval Others USB endpoint is stalled.
+ *
+ * @details Get USB endpoint stall state of the specified endpoint ID.
+ *
+ */
+#define USBD_GET_EP_STALL(ep) (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFGP + (uint32_t)((ep) << 4))) & USBD_CFGP_SSTALL_Msk)
+
+/**
+ * @brief To support byte access between USB SRAM and system SRAM
+ *
+ * @param[in] dest Destination pointer.
+ *
+ * @param[in] src Source pointer.
+ *
+ * @param[in] size Byte count.
+ *
+ * @return None
+ *
+ * @details This function will copy the number of data specified by size and src parameters to the address specified by dest parameter.
+ *
+ */
+static __INLINE void USBD_MemCopy(uint8_t *dest, uint8_t *src, int32_t size)
+{
+ while(size--) *dest++ = *src++;
+}
+
+
+/**
+ * @brief Set USB endpoint stall state
+ *
+ * @param[in] epnum USB endpoint number
+ *
+ * @return None
+ *
+ * @details Set USB endpoint stall state. Endpoint will respond STALL token automatically.
+ *
+ */
+static __INLINE void USBD_SetStall(uint8_t epnum)
+{
+ uint32_t u32CfgAddr;
+ uint32_t u32Cfg;
+ int i;
+
+ for(i = 0; i < USBD_MAX_EP; i++)
+ {
+ u32CfgAddr = (uint32_t)(i << 4) + (uint32_t)&USBD->EP[0].CFG; /* USBD_CFG0 */
+ u32Cfg = *((__IO uint32_t *)(u32CfgAddr));
+
+ if((u32Cfg & 0xf) == epnum)
+ {
+ u32CfgAddr = (uint32_t)(i << 4) + (uint32_t)&USBD->EP[0].CFGP; /* USBD_CFGP0 */
+ u32Cfg = *((__IO uint32_t *)(u32CfgAddr));
+
+ *((__IO uint32_t *)(u32CfgAddr)) = (u32Cfg | USBD_CFGP_SSTALL);
+ break;
+ }
+ }
+}
+
+/**
+ * @brief Clear USB endpoint stall state
+ *
+ * @param[in] epnum USB endpoint number
+ *
+ * @return None
+ *
+ * @details Clear USB endpoint stall state. Endpoint will respond ACK/NAK token.
+ */
+static __INLINE void USBD_ClearStall(uint8_t epnum)
+{
+ uint32_t u32CfgAddr;
+ uint32_t u32Cfg;
+ int i;
+
+ for(i = 0; i < USBD_MAX_EP; i++)
+ {
+ u32CfgAddr = (uint32_t)(i << 4) + (uint32_t)&USBD->EP[0].CFG; /* USBD_CFG0 */
+ u32Cfg = *((__IO uint32_t *)(u32CfgAddr));
+
+ if((u32Cfg & 0xf) == epnum)
+ {
+ u32CfgAddr = (uint32_t)(i << 4) + (uint32_t)&USBD->EP[0].CFGP; /* USBD_CFGP0 */
+ u32Cfg = *((__IO uint32_t *)(u32CfgAddr));
+
+ *((__IO uint32_t *)(u32CfgAddr)) = (u32Cfg & ~USBD_CFGP_SSTALL);
+ break;
+ }
+ }
+}
+
+/**
+ * @brief Get USB endpoint stall state
+ *
+ * @param[in] epnum USB endpoint number
+ *
+ * @retval 0 USB endpoint is not stalled.
+ * @retval Others USB endpoint is stalled.
+ *
+ * @details Get USB endpoint stall state.
+ *
+ */
+static __INLINE uint32_t USBD_GetStall(uint8_t epnum)
+{
+ uint32_t u32CfgAddr;
+ uint32_t u32Cfg;
+ int i;
+
+ for(i = 0; i < USBD_MAX_EP; i++)
+ {
+ u32CfgAddr = (uint32_t)(i << 4) + (uint32_t)&USBD->EP[0].CFG; /* USBD_CFG0 */
+ u32Cfg = *((__IO uint32_t *)(u32CfgAddr));
+
+ if((u32Cfg & 0xf) == epnum)
+ {
+ u32CfgAddr = (uint32_t)(i << 4) + (uint32_t)&USBD->EP[0].CFGP; /* USBD_CFGP0 */
+ break;
+ }
+ }
+
+ return ((*((__IO uint32_t *)(u32CfgAddr))) & USBD_CFGP_SSTALL);
+}
+
+
+extern volatile uint8_t g_usbd_RemoteWakeupEn;
+
+
+typedef void (*VENDOR_REQ)(void); /*!< Functional pointer type definition for Vendor class */
+typedef void (*CLASS_REQ)(void); /*!< Functional pointer type declaration for USB class request callback handler */
+typedef void (*SET_INTERFACE_REQ)(void); /*!< Functional pointer type declaration for USB set interface request callback handler */
+typedef void (*SET_CONFIG_CB)(void); /*!< Functional pointer type declaration for USB set configuration request callback handler */
+
+
+/*--------------------------------------------------------------------*/
+void USBD_Open(const S_USBD_INFO_T *param, CLASS_REQ pfnClassReq, SET_INTERFACE_REQ pfnSetInterface);
+void USBD_Start(void);
+void USBD_GetSetupPacket(uint8_t *buf);
+void USBD_ProcessSetupPacket(void);
+void USBD_StandardRequest(void);
+void USBD_PrepareCtrlIn(uint8_t *pu8Buf, uint32_t u32Size);
+void USBD_CtrlIn(void);
+void USBD_PrepareCtrlOut(uint8_t *pu8Buf, uint32_t u32Size);
+void USBD_CtrlOut(void);
+void USBD_SwReset(void);
+void USBD_SetVendorRequest(VENDOR_REQ pfnVendorReq);
+void USBD_SetConfigCallback(SET_CONFIG_CB pfnSetConfigCallback);
+void USBD_LockEpStall(uint32_t u32EpBitmap);
+
+/*@}*/ /* end of group USBD_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group USBD_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+
+#endif //__USBD_H__
+
+/*** (C) COPYRIGHT 2014~2015 Nuvoton Technology Corp. ***/
diff --git a/bsp/nuvoton_m451/Libraries/StdDriver/inc/wdt.h b/bsp/nuvoton_m451/Libraries/StdDriver/inc/wdt.h
new file mode 100644
index 0000000000000000000000000000000000000000..3c22721916d0421d131aa430a14eb173ae097010
--- /dev/null
+++ b/bsp/nuvoton_m451/Libraries/StdDriver/inc/wdt.h
@@ -0,0 +1,201 @@
+/**************************************************************************//**
+ * @file wdt.h
+ * @version V3.00
+ * $Revision: 7 $
+ * $Date: 15/08/11 10:26a $
+ * @brief M451 series WDT driver header file
+ *
+ * @note
+ * Copyright (C) 2013~2015 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __WDT_H__
+#define __WDT_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup Standard_Driver Standard Driver
+ @{
+*/
+
+/** @addtogroup WDT_Driver WDT Driver
+ @{
+*/
+
+/** @addtogroup WDT_EXPORTED_CONSTANTS WDT Exported Constants
+ @{
+*/
+/*---------------------------------------------------------------------------------------------------------*/
+/* WDT Time-out Interval Period Constant Definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define WDT_TIMEOUT_2POW4 (0UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^4 * WDT clocks */
+#define WDT_TIMEOUT_2POW6 (1UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^6 * WDT clocks */
+#define WDT_TIMEOUT_2POW8 (2UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^8 * WDT clocks */
+#define WDT_TIMEOUT_2POW10 (3UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^10 * WDT clocks */
+#define WDT_TIMEOUT_2POW12 (4UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^12 * WDT clocks */
+#define WDT_TIMEOUT_2POW14 (5UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^14 * WDT clocks */
+#define WDT_TIMEOUT_2POW16 (6UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^16 * WDT clocks */
+#define WDT_TIMEOUT_2POW18 (7UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^18 * WDT clocks */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* WDT Reset Delay Period Constant Definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define WDT_RESET_DELAY_1026CLK (0UL << WDT_ALTCTL_RSTDSEL_Pos) /*!< Setting WDT reset delay period to 1026 * WDT clocks */
+#define WDT_RESET_DELAY_130CLK (1UL << WDT_ALTCTL_RSTDSEL_Pos) /*!< Setting WDT reset delay period to 130 * WDT clocks */
+#define WDT_RESET_DELAY_18CLK (2UL << WDT_ALTCTL_RSTDSEL_Pos) /*!< Setting WDT reset delay period to 18 * WDT clocks */
+#define WDT_RESET_DELAY_3CLK (3UL << WDT_ALTCTL_RSTDSEL_Pos) /*!< Setting WDT reset delay period to 3 * WDT clocks */
+
+/*@}*/ /* end of group WDT_EXPORTED_CONSTANTS */
+
+
+/** @addtogroup WDT_EXPORTED_FUNCTIONS WDT Exported Functions
+ @{
+*/
+
+/**
+ * @brief Clear WDT Reset System Flag
+ *
+ * @param None
+ *
+ * @return None
+ *
+ * @details This macro clears WDT time-out reset system flag.
+ */
+#define WDT_CLEAR_RESET_FLAG() (WDT->CTL = (WDT->CTL & ~(WDT_CTL_IF_Msk | WDT_CTL_WKF_Msk)) | WDT_CTL_RSTF_Msk)
+
+/**
+ * @brief Clear WDT Time-out Interrupt Flag
+ *
+ * @param None
+ *
+ * @return None
+ *
+ * @details This macro clears WDT time-out interrupt flag.
+ */
+#define WDT_CLEAR_TIMEOUT_INT_FLAG() (WDT->CTL = (WDT->CTL & ~(WDT_CTL_RSTF_Msk | WDT_CTL_WKF_Msk)) | WDT_CTL_IF_Msk)
+
+/**
+ * @brief Clear WDT Wake-up Flag
+ *
+ * @param None
+ *
+ * @return None
+ *
+ * @details This macro clears WDT time-out wake-up system flag.
+ */
+#define WDT_CLEAR_TIMEOUT_WAKEUP_FLAG() (WDT->CTL = (WDT->CTL & ~(WDT_CTL_RSTF_Msk | WDT_CTL_IF_Msk)) | WDT_CTL_WKF_Msk)
+
+/**
+ * @brief Get WDT Time-out Reset Flag
+ *
+ * @param None
+ *
+ * @retval 0 WDT time-out reset system did not occur
+ * @retval 1 WDT time-out reset system occurred
+ *
+ * @details This macro indicates system has been reset by WDT time-out reset or not.
+ */
+#define WDT_GET_RESET_FLAG() ((WDT->CTL & WDT_CTL_RSTF_Msk)? 1 : 0)
+
+/**
+ * @brief Get WDT Time-out Interrupt Flag
+ *
+ * @param None
+ *
+ * @retval 0 WDT time-out interrupt did not occur
+ * @retval 1 WDT time-out interrupt occurred
+ *
+ * @details This macro indicates WDT time-out interrupt occurred or not.
+ */
+#define WDT_GET_TIMEOUT_INT_FLAG() ((WDT->CTL & WDT_CTL_IF_Msk)? 1 : 0)
+
+/**
+ * @brief Get WDT Time-out Wake-up Flag
+ *
+ * @param None
+ *
+ * @retval 0 WDT time-out interrupt does not cause CPU wake-up
+ * @retval 1 WDT time-out interrupt event cause CPU wake-up
+ *
+ * @details This macro indicates WDT time-out interrupt event has waked up system or not.
+ */
+#define WDT_GET_TIMEOUT_WAKEUP_FLAG() ((WDT->CTL & WDT_CTL_WKF_Msk)? 1 : 0)
+
+/**
+ * @brief Reset WDT Counter
+ *
+ * @param None
+ *
+ * @return None
+ *
+ * @details This macro is used to reset the internal 18-bit WDT up counter value.
+ * @note If WDT is activated and time-out reset system function is enabled also, user should \n
+ * reset the 18-bit WDT up counter value to avoid generate WDT time-out reset signal to \n
+ * reset system before the WDT time-out reset delay period expires.
+ */
+#define WDT_RESET_COUNTER() (WDT->CTL = (WDT->CTL & ~(WDT_CTL_IF_Msk | WDT_CTL_WKF_Msk | WDT_CTL_RSTF_Msk)) | WDT_CTL_RSTCNT_Msk)
+
+/**
+ * @brief Stop WDT Counting
+ *
+ * @param None
+ *
+ * @return None
+ *
+ * @details This function will stop WDT counting and disable WDT module.
+ */
+static __INLINE void WDT_Close(void)
+{
+ WDT->CTL = 0;
+ return;
+}
+
+/**
+ * @brief Enable WDT Time-out Interrupt
+ *
+ * @param None
+ *
+ * @return None
+ *
+ * @details This function will enable the WDT time-out interrupt function.
+ */
+static __INLINE void WDT_EnableInt(void)
+{
+ WDT->CTL |= WDT_CTL_INTEN_Msk;
+ return;
+}
+
+/**
+ * @brief Disable WDT Time-out Interrupt
+ *
+ * @param None
+ *
+ * @return None
+ *
+ * @details This function will disable the WDT time-out interrupt function.
+ */
+static __INLINE void WDT_DisableInt(void)
+{
+ // Do not touch another write 1 clear bits
+ WDT->CTL &= ~(WDT_CTL_INTEN_Msk | WDT_CTL_RSTF_Msk | WDT_CTL_IF_Msk | WDT_CTL_WKF_Msk);
+ return;
+}
+
+void WDT_Open(uint32_t u32TimeoutInterval, uint32_t u32ResetDelay, uint32_t u32EnableReset, uint32_t u32EnableWakeup);
+
+/*@}*/ /* end of group WDT_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group WDT_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif //__WDT_H__
+
+/*** (C) COPYRIGHT 2013~2015 Nuvoton Technology Corp. ***/
diff --git a/bsp/nuvoton_m451/Libraries/StdDriver/inc/wwdt.h b/bsp/nuvoton_m451/Libraries/StdDriver/inc/wwdt.h
new file mode 100644
index 0000000000000000000000000000000000000000..56e8a831e1546b61fe590f9c4aa64531682c4b6b
--- /dev/null
+++ b/bsp/nuvoton_m451/Libraries/StdDriver/inc/wwdt.h
@@ -0,0 +1,148 @@
+/**************************************************************************//**
+ * @file wwdt.h
+ * @version V3.00
+ * $Revision: 7 $
+ * $Date: 15/08/11 10:26a $
+ * @brief M451 series WWDT driver header file
+ *
+ * @note
+ * Copyright (C) 2013~2015 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __WWDT_H__
+#define __WWDT_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup Standard_Driver Standard Driver
+ @{
+*/
+
+/** @addtogroup WWDT_Driver WWDT Driver
+ @{
+*/
+
+/** @addtogroup WWDT_EXPORTED_CONSTANTS WWDT Exported Constants
+ @{
+*/
+/*---------------------------------------------------------------------------------------------------------*/
+/* WWDT Prescale Period Constant Definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define WWDT_PRESCALER_1 (0 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 1 * (64*WWDT_CLK) */
+#define WWDT_PRESCALER_2 (1 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 2 * (64*WWDT_CLK) */
+#define WWDT_PRESCALER_4 (2 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 4 * (64*WWDT_CLK) */
+#define WWDT_PRESCALER_8 (3 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 8 * (64*WWDT_CLK) */
+#define WWDT_PRESCALER_16 (4 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 16 * (64*WWDT_CLK) */
+#define WWDT_PRESCALER_32 (5 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 32 * (64*WWDT_CLK) */
+#define WWDT_PRESCALER_64 (6 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 64 * (64*WWDT_CLK) */
+#define WWDT_PRESCALER_128 (7 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 128 * (64*WWDT_CLK) */
+#define WWDT_PRESCALER_192 (8 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 192 * (64*WWDT_CLK) */
+#define WWDT_PRESCALER_256 (9 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 256 * (64*WWDT_CLK) */
+#define WWDT_PRESCALER_384 (10 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 384 * (64*WWDT_CLK) */
+#define WWDT_PRESCALER_512 (11 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 512 * (64*WWDT_CLK) */
+#define WWDT_PRESCALER_768 (12 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 768 * (64*WWDT_CLK) */
+#define WWDT_PRESCALER_1024 (13 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 1024 * (64*WWDT_CLK) */
+#define WWDT_PRESCALER_1536 (14 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 1536 * (64*WWDT_CLK) */
+#define WWDT_PRESCALER_2048 (15 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 2048 * (64*WWDT_CLK) */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* WWDT Reload Counter Keyword Constant Definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define WWDT_RELOAD_WORD (0x00005AA5) /*!< Fill this value to WWDT_RLDCNT register to reload WWDT counter */
+
+/*@}*/ /* end of group WWDT_EXPORTED_CONSTANTS */
+
+
+/** @addtogroup WWDT_EXPORTED_FUNCTIONS WWDT Exported Functions
+ @{
+*/
+
+/**
+ * @brief Clear WWDT Reset System Flag
+ *
+ * @param None
+ *
+ * @return None
+ *
+ * @details This macro is used to clear WWDT time-out reset system flag.
+ */
+#define WWDT_CLEAR_RESET_FLAG() (WWDT->STATUS = (WWDT->STATUS & ~WWDT_STATUS_WWDTIF_Msk) | WWDT_STATUS_WWDTRF_Msk)
+
+/**
+ * @brief Clear WWDT Compared Match Interrupt Flag
+ *
+ * @param None
+ *
+ * @return None
+ *
+ * @details This macro is used to clear WWDT compared match interrupt flag.
+ */
+#define WWDT_CLEAR_INT_FLAG() (WWDT->STATUS = (WWDT->STATUS & ~WWDT_STATUS_WWDTRF_Msk) | WWDT_STATUS_WWDTIF_Msk)
+
+/**
+ * @brief Get WWDT Reset System Flag
+ *
+ * @param None
+ *
+ * @retval 0 WWDT time-out reset system did not occur
+ * @retval 1 WWDT time-out reset system occurred
+ *
+ * @details This macro is used to indicate system has been reset by WWDT time-out reset or not.
+ */
+#define WWDT_GET_RESET_FLAG() ((WWDT->STATUS & WWDT_STATUS_WWDTRF_Msk)? 1 : 0)
+
+/**
+ * @brief Get WWDT Compared Match Interrupt Flag
+ *
+ * @param None
+ *
+ * @retval 0 WWDT compare match interrupt did not occur
+ * @retval 1 WWDT compare match interrupt occurred
+ *
+ * @details This macro is used to indicate WWDT counter value matches CMPDAT value or not.
+ */
+#define WWDT_GET_INT_FLAG() ((WWDT->STATUS & WWDT_STATUS_WWDTIF_Msk)? 1 : 0)
+
+/**
+ * @brief Get WWDT Counter
+ *
+ * @param None
+ *
+ * @return WWDT Counter Value
+ *
+ * @details This macro reflects the current WWDT counter value.
+ */
+#define WWDT_GET_COUNTER() (WWDT->CNT)
+
+/**
+ * @brief Reload WWDT Counter
+ *
+ * @param None
+ *
+ * @return None
+ *
+ * @details This macro is used to reload the WWDT counter value to 0x3F.
+ * @note User can only write WWDT_RLDCNT register to reload WWDT counter value when current WWDT counter value \n
+ * between 0 and CMPDAT value. If user writes WWDT_RLDCNT when current WWDT counter value is larger than CMPDAT, \n
+ * WWDT reset signal will generate immediately to reset system.
+ */
+#define WWDT_RELOAD_COUNTER() (WWDT->RLDCNT = WWDT_RELOAD_WORD)
+
+void WWDT_Open(uint32_t u32PreScale, uint32_t u32CmpValue, uint32_t u32EnableInt);
+
+/*@}*/ /* end of group WWDT_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group WWDT_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif //__WWDT_H__
+
+/*** (C) COPYRIGHT 2013~2015 Nuvoton Technology Corp. ***/
diff --git a/bsp/nuvoton_m451/Libraries/StdDriver/src/acmp.c b/bsp/nuvoton_m451/Libraries/StdDriver/src/acmp.c
new file mode 100644
index 0000000000000000000000000000000000000000..6b5edd129063b2c692c63817a8638c27111e3154
--- /dev/null
+++ b/bsp/nuvoton_m451/Libraries/StdDriver/src/acmp.c
@@ -0,0 +1,84 @@
+/**************************************************************************//**
+ * @file acmp.c
+ * @version V3.00
+ * $Revision: 4 $
+ * $Date: 15/08/11 10:26a $
+ * @brief M451 series Analog Comparator(ACMP) driver source file
+ *
+ * @note
+ * Copyright (C) 2014~2015 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+
+#include "M451Series.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/** @addtogroup Standard_Driver Standard Driver
+ @{
+*/
+
+/** @addtogroup ACMP_Driver ACMP Driver
+ @{
+*/
+
+
+/** @addtogroup ACMP_EXPORTED_FUNCTIONS ACMP Exported Functions
+ @{
+*/
+
+
+/**
+ * @brief Configure the specified ACMP module
+ *
+ * @param[in] Acmp The pointer of the specified ACMP module
+ * @param[in] u32ChNum Comparator number.
+ * @param[in] u32NegSrc Comparator negative input selection. Including:
+ * - \ref ACMP_CTL_NEGSEL_PIN
+ * - \ref ACMP_CTL_NEGSEL_CRV
+ * - \ref ACMP_CTL_NEGSEL_VBG
+ * - \ref ACMP_CTL_NEGSEL_DAC
+ * @param[in] u32HysteresisEn The hysteresis function option. Including:
+ * - \ref ACMP_CTL_HYSTERESIS_ENABLE
+ * - \ref ACMP_CTL_HYSTERESIS_DISABLE
+ *
+ * @return None
+ *
+ * @details Configure hysteresis function, select the source of negative input and enable analog comparator.
+ */
+void ACMP_Open(ACMP_T *Acmp, uint32_t u32ChNum, uint32_t u32NegSrc, uint32_t u32HysteresisEn)
+{
+ Acmp->CTL[u32ChNum] = (Acmp->CTL[u32ChNum] & (~(ACMP_CTL_NEGSEL_Msk | ACMP_CTL_HYSEN_Msk))) | (u32NegSrc | u32HysteresisEn | ACMP_CTL_ACMPEN_Msk);
+}
+
+/**
+ * @brief Close analog comparator
+ *
+ * @param[in] Acmp The pointer of the specified ACMP module
+ * @param[in] u32ChNum Comparator number.
+ *
+ * @return None
+ *
+ * @details This function will clear ACMPEN bit of ACMP_CTL register to disable analog comparator.
+ */
+void ACMP_Close(ACMP_T *Acmp, uint32_t u32ChNum)
+{
+ Acmp->CTL[u32ChNum] &= (~ACMP_CTL_ACMPEN_Msk);
+}
+
+
+
+/*@}*/ /* end of group ACMP_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group ACMP_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+/*** (C) COPYRIGHT 2014~2015 Nuvoton Technology Corp. ***/
+
diff --git a/bsp/nuvoton_m451/Libraries/StdDriver/src/can.c b/bsp/nuvoton_m451/Libraries/StdDriver/src/can.c
new file mode 100644
index 0000000000000000000000000000000000000000..a1ab3a906239ec01c67203e267d17c208dd83ab6
--- /dev/null
+++ b/bsp/nuvoton_m451/Libraries/StdDriver/src/can.c
@@ -0,0 +1,1004 @@
+/**************************************************************************//**
+ * @file can.c
+ * @version V2.00
+ * $Revision: 8 $
+ * $Date: 15/08/11 10:26a $
+ * @brief M451 series CAN driver source file
+ *
+ * @note
+ * Copyright (C) 2014~2015 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#include "M451Series.h"
+
+/** @addtogroup Standard_Driver Standard Driver
+ @{
+*/
+
+/** @addtogroup CAN_Driver CAN Driver
+ @{
+*/
+
+/** @addtogroup CAN_EXPORTED_FUNCTIONS CAN Exported Functions
+ @{
+*/
+
+/// @cond HIDDEN_SYMBOLS
+
+#if defined(CAN1)
+static uint8_t gu8LockCanIf[2][2] = {0}; // The chip has two CANs.
+#elif defined(CAN0) || defined(CAN)
+static uint8_t gu8LockCanIf[1][2] = {0}; // The chip only has one CAN.
+#endif
+
+#define RETRY_COUNTS (0x10000000)
+
+//#define DEBUG_PRINTF printf
+#define DEBUG_PRINTF(...)
+
+/**
+ * @brief Check if any interface is available then lock it for usage.
+ * @param[in] tCAN The pointer to CAN module base address.
+ * @retval 0 IF0 is free
+ * @retval 1 IF1 is free
+ * @retval 2 No IF is free
+ * @details Search the first free message interface, starting from 0. If a interface is
+ * available, set a flag to lock the interface.
+ */
+static uint32_t LockIF(CAN_T *tCAN)
+{
+ uint32_t u32CanNo;
+ uint32_t u32FreeIfNo;
+ uint32_t u32IntMask;
+
+#if defined(CAN1)
+ u32CanNo = (tCAN == CAN1) ? 1 : 0;
+#else // defined(CAN0) || defined(CAN)
+ u32CanNo = 0;
+#endif
+
+ u32FreeIfNo = 2;
+
+ /* Disable CAN interrupt */
+ u32IntMask = tCAN->CON & (CAN_CON_IE_Msk | CAN_CON_SIE_Msk | CAN_CON_EIE_Msk);
+ tCAN->CON = tCAN->CON & ~(CAN_CON_IE_Msk | CAN_CON_SIE_Msk | CAN_CON_EIE_Msk);
+
+ /* Check interface 1 is available or not */
+ if((tCAN->IF[0].CREQ & CAN_IF_CREQ_BUSY_Msk) == 0)
+ {
+ if(gu8LockCanIf[u32CanNo][0] == FALSE)
+ {
+ gu8LockCanIf[u32CanNo][0] = TRUE;
+ u32FreeIfNo = 0;
+ }
+ }
+
+ /* Or check interface 2 is available or not */
+ if(u32FreeIfNo == 2 && (tCAN->IF[1].CREQ & CAN_IF_CREQ_BUSY_Msk) == 0)
+ {
+ if(gu8LockCanIf[u32CanNo][1] == FALSE)
+ {
+ gu8LockCanIf[u32CanNo][1] = TRUE;
+ u32FreeIfNo = 1;
+ }
+ }
+
+ /* Enable CAN interrupt */
+ tCAN->CON |= u32IntMask;
+
+ return u32FreeIfNo;
+}
+
+/**
+ * @brief Check if any interface is available in a time limitation then lock it for usage.
+ * @param[in] tCAN The pointer to CAN module base address.
+ * @retval 0 IF0 is free
+ * @retval 1 IF1 is free
+ * @retval 2 No IF is free
+ * @details Search the first free message interface, starting from 0. If no interface is
+ * it will try again until time out. If a interface is available, set a flag to
+ * lock the interface.
+ */
+static uint32_t LockIF_TL(CAN_T *tCAN)
+{
+ uint32_t u32Count;
+ uint32_t u32FreeIfNo;
+
+ for(u32Count = 0; u32Count < RETRY_COUNTS; u32Count++)
+ {
+ if((u32FreeIfNo = LockIF(tCAN)) != 2)
+ return u32FreeIfNo;
+ }
+
+ return u32FreeIfNo;
+}
+
+/**
+ * @brief Release locked interface.
+ * @param[in] tCAN The pointer to CAN module base address.
+ * @param[in] u32Info The interface number, 0 or 1.
+ * @return none
+ * @details Release the locked interface.
+ */
+static void ReleaseIF(CAN_T *tCAN, uint32_t u32IfNo)
+{
+ uint32_t u32IntMask;
+ uint32_t u32CanNo;
+
+ if(u32IfNo >= 2)
+ return;
+
+#if defined(CAN1)
+ u32CanNo = (tCAN == CAN1) ? 1 : 0;
+#else // defined(CAN0) || defined(CAN)
+ u32CanNo = 0;
+#endif
+
+ /* Disable CAN interrupt */
+ u32IntMask = tCAN->CON & (CAN_CON_IE_Msk | CAN_CON_SIE_Msk | CAN_CON_EIE_Msk);
+ tCAN->CON = tCAN->CON & ~(CAN_CON_IE_Msk | CAN_CON_SIE_Msk | CAN_CON_EIE_Msk);
+
+ gu8LockCanIf[u32CanNo][u32IfNo] = FALSE;
+
+ /* Enable CAN interrupt */
+ tCAN->CON |= u32IntMask;
+}
+
+/**
+ * @brief Enter initialization mode
+ * @param[in] tCAN The pointer to CAN module base address.
+ * @param[in] Following values can be used.
+ * \ref CAN_CON_DAR_Msk Disable automatic retransmission.
+ * \ref CAN_CON_EIE_Msk Enable error interrupt.
+ * \ref CAN_CON_SIE_Msk Enable status interrupt.
+ * \ref CAN_CON_IE_Msk CAN interrupt.
+ * @return None
+ * @details This function is used to set CAN to enter initialization mode and enable access bit timing
+ * register. After bit timing configuration ready, user must call CAN_LeaveInitMode()
+ * to leave initialization mode and lock bit timing register to let new configuration
+ * take effect.
+ */
+void CAN_EnterInitMode(CAN_T *tCAN, uint8_t u8Mask)
+{
+ tCAN->CON = u8Mask | (CAN_CON_INIT_Msk | CAN_CON_CCE_Msk);
+}
+
+
+/**
+ * @brief Leave initialization mode
+ * @param[in] tCAN The pointer to CAN module base address.
+ * @return None
+ * @details This function is used to set CAN to leave initialization mode to let
+ * bit timing configuration take effect after configuration ready.
+ */
+void CAN_LeaveInitMode(CAN_T *tCAN)
+{
+ tCAN->CON &= (~(CAN_CON_INIT_Msk | CAN_CON_CCE_Msk));
+ while(tCAN->CON & CAN_CON_INIT_Msk); /* Check INIT bit is released */
+}
+
+/**
+ * @brief Wait message into message buffer in basic mode.
+ * @param[in] tCAN The pointer to CAN module base address.
+ * @return None
+ * @details This function is used to wait message into message buffer in basic mode. Please notice the
+ * function is polling NEWDAT bit of MCON register by while loop and it is used in basic mode.
+ */
+void CAN_WaitMsg(CAN_T *tCAN)
+{
+ tCAN->STATUS = 0x0; /* clr status */
+
+ while(1)
+ {
+ if(tCAN->IF[1].MCON & CAN_IF_MCON_NEWDAT_Msk) /* check new data */
+ {
+ DEBUG_PRINTF("New Data IN\n");
+ break;
+ }
+
+ if(tCAN->STATUS & CAN_STATUS_RXOK_Msk)
+ DEBUG_PRINTF("Rx OK\n");
+
+ if(tCAN->STATUS & CAN_STATUS_LEC_Msk)
+ {
+ DEBUG_PRINTF("Error\n");
+ }
+ }
+}
+
+/**
+ * @brief Get current bit rate
+ * @param[in] tCAN The pointer to CAN module base address.
+ * @return Current Bit-Rate (kilo bit per second)
+ * @details Return current CAN bit rate according to the user bit-timing parameter settings
+ */
+uint32_t CAN_GetCANBitRate(CAN_T *tCAN)
+{
+ uint8_t u8Tseg1, u8Tseg2;
+ uint32_t u32Bpr;
+
+ u8Tseg1 = (tCAN->BTIME & CAN_BTIME_TSEG1_Msk) >> CAN_BTIME_TSEG1_Pos;
+ u8Tseg2 = (tCAN->BTIME & CAN_BTIME_TSEG2_Msk) >> CAN_BTIME_TSEG2_Pos;
+ u32Bpr = (tCAN->BTIME & CAN_BTIME_BRP_Msk) | (tCAN->BRPE << 6);
+
+ return (SystemCoreClock / (u32Bpr + 1) / (u8Tseg1 + u8Tseg2 + 3));
+}
+
+/**
+ * @brief Switch the CAN into test mode.
+ * @param[in] tCAN The pointer to CAN module base address.
+ * @param[in] u8TestMask Specifies the configuration in test modes
+ * \ref CAN_TEST_BASIC_Msk Enable basic mode of test mode
+ * \ref CAN_TEST_SILENT_Msk Enable silent mode of test mode
+ * \ref CAN_TEST_LBACK_Msk Enable Loop Back Mode of test mode
+ * \ref CAN_TEST_TX0_Msk / \ref CAN_TEST_TX1_Msk Control CAN_TX pin bit field
+ * @return None
+ * @details Switch the CAN into test mode. There are four test mode (BASIC/SILENT/LOOPBACK/
+ * LOOPBACK combined SILENT/CONTROL_TX_PIN)could be selected. After setting test mode,user
+ * must call CAN_LeaveInitMode() to let the setting take effect.
+ */
+void CAN_EnterTestMode(CAN_T *tCAN, uint8_t u8TestMask)
+{
+ tCAN->CON |= CAN_CON_TEST_Msk;
+ tCAN->TEST = u8TestMask;
+}
+
+
+/**
+ * @brief Leave the test mode
+ * @param[in] tCAN The pointer to CAN module base address.
+ * @return None
+ * @details This function is used to Leave the test mode (switch into normal mode).
+ */
+void CAN_LeaveTestMode(CAN_T *tCAN)
+{
+ tCAN->CON |= CAN_CON_TEST_Msk;
+ tCAN->TEST &= ~(CAN_TEST_LBACK_Msk | CAN_TEST_SILENT_Msk | CAN_TEST_BASIC_Msk);
+ tCAN->CON &= (~CAN_CON_TEST_Msk);
+}
+
+/**
+ * @brief Get the waiting status of a received message.
+ * @param[in] tCAN The pointer to CAN module base address.
+ * @param[in] u8MsgObj Specifies the Message object number, from 0 to 31.
+ * @retval non-zero The corresponding message object has a new data bit is set.
+ * @retval 0 No message object has new data.
+ * @details This function is used to get the waiting status of a received message.
+ */
+uint32_t CAN_IsNewDataReceived(CAN_T *tCAN, uint8_t u8MsgObj)
+{
+ return (u8MsgObj < 16 ? tCAN->NDAT1 & (1 << u8MsgObj) : tCAN->NDAT2 & (1 << (u8MsgObj - 16)));
+}
+
+
+/**
+ * @brief Send CAN message in BASIC mode of test mode
+ * @param[in] tCAN The pointer to CAN module base address.
+ * @param[in] pCanMsg Pointer to the message structure containing data to transmit.
+ * @return TRUE: Transmission OK
+ * FALSE: Check busy flag of interface 0 is timeout
+ * @details The function is used to send CAN message in BASIC mode of test mode. Before call the API,
+ * the user should be call CAN_EnterTestMode(CAN_TEST_BASIC) and let CAN controller enter
+ * basic mode of test mode. Please notice IF1 Registers used as Tx Buffer in basic mode.
+ */
+int32_t CAN_BasicSendMsg(CAN_T *tCAN, STR_CANMSG_T* pCanMsg)
+{
+ uint32_t i = 0;
+ while(tCAN->IF[0].CREQ & CAN_IF_CREQ_BUSY_Msk);
+
+ tCAN->STATUS &= (~CAN_STATUS_TXOK_Msk);
+
+ if(pCanMsg->IdType == CAN_STD_ID)
+ {
+ /* standard ID*/
+ tCAN->IF[0].ARB1 = 0;
+ tCAN->IF[0].ARB2 = (((pCanMsg->Id) & 0x7FF) << 2) ;
+ }
+ else
+ {
+ /* extended ID*/
+ tCAN->IF[0].ARB1 = (pCanMsg->Id) & 0xFFFF;
+ tCAN->IF[0].ARB2 = ((pCanMsg->Id) & 0x1FFF0000) >> 16 | CAN_IF_ARB2_XTD_Msk;
+
+ }
+
+ if(pCanMsg->FrameType)
+ tCAN->IF[0].ARB2 |= CAN_IF_ARB2_DIR_Msk;
+ else
+ tCAN->IF[0].ARB2 &= (~CAN_IF_ARB2_DIR_Msk);
+
+ tCAN->IF[0].MCON = (tCAN->IF[0].MCON & (~CAN_IF_MCON_DLC_Msk)) | pCanMsg->DLC;
+ tCAN->IF[0].DAT_A1 = ((uint16_t)pCanMsg->Data[1] << 8) | pCanMsg->Data[0];
+ tCAN->IF[0].DAT_A2 = ((uint16_t)pCanMsg->Data[3] << 8) | pCanMsg->Data[2];
+ tCAN->IF[0].DAT_B1 = ((uint16_t)pCanMsg->Data[5] << 8) | pCanMsg->Data[4];
+ tCAN->IF[0].DAT_B2 = ((uint16_t)pCanMsg->Data[7] << 8) | pCanMsg->Data[6];
+
+ /* request transmission*/
+ tCAN->IF[0].CREQ &= (~CAN_IF_CREQ_BUSY_Msk);
+ if(tCAN->IF[0].CREQ & CAN_IF_CREQ_BUSY_Msk)
+ {
+ DEBUG_PRINTF("Cannot clear busy for sending ...\n");
+ return FALSE;
+ }
+
+ tCAN->IF[0].CREQ |= CAN_IF_CREQ_BUSY_Msk; // sending
+
+ for(i = 0; i < 0xFFFFF; i++)
+ {
+ if((tCAN->IF[0].CREQ & CAN_IF_CREQ_BUSY_Msk) == 0)
+ break;
+ }
+
+ if(i >= 0xFFFFF)
+ {
+ DEBUG_PRINTF("Cannot send out...\n");
+ return FALSE;
+ }
+
+ return TRUE;
+}
+
+/**
+ * @brief Get a message information in BASIC mode.
+ *
+ * @param[in] tCAN The pointer to CAN module base address.
+ * @param[in] pCanMsg Pointer to the message structure where received data is copied.
+ *
+ * @return FALSE No any message received.
+ * TRUE Receive a message success.
+ *
+ */
+int32_t CAN_BasicReceiveMsg(CAN_T *tCAN, STR_CANMSG_T* pCanMsg)
+{
+
+ if((tCAN->IF[1].MCON & CAN_IF_MCON_NEWDAT_Msk) == 0) /* In basic mode, receive data always save in IF2 */
+ {
+ return FALSE;
+ }
+
+ tCAN->STATUS &= (~CAN_STATUS_RXOK_Msk);
+
+ tCAN->IF[1].CMASK = CAN_IF_CMASK_ARB_Msk
+ | CAN_IF_CMASK_CONTROL_Msk
+ | CAN_IF_CMASK_DATAA_Msk
+ | CAN_IF_CMASK_DATAB_Msk;
+
+ if((tCAN->IF[1].ARB2 & CAN_IF_ARB2_XTD_Msk) == 0)
+ {
+ /* standard ID*/
+ pCanMsg->IdType = CAN_STD_ID;
+ pCanMsg->Id = (tCAN->IF[1].ARB2 >> 2) & 0x07FF;
+
+ }
+ else
+ {
+ /* extended ID*/
+ pCanMsg->IdType = CAN_EXT_ID;
+ pCanMsg->Id = (tCAN->IF[1].ARB2 & 0x1FFF) << 16;
+ pCanMsg->Id |= (uint32_t)tCAN->IF[1].ARB1;
+ }
+
+ pCanMsg->FrameType = !((tCAN->IF[1].ARB2 & CAN_IF_ARB2_DIR_Msk) >> CAN_IF_ARB2_DIR_Pos);
+
+ pCanMsg->DLC = tCAN->IF[1].MCON & CAN_IF_MCON_DLC_Msk;
+ pCanMsg->Data[0] = tCAN->IF[1].DAT_A1 & CAN_IF_DAT_A1_DATA0_Msk;
+ pCanMsg->Data[1] = (tCAN->IF[1].DAT_A1 & CAN_IF_DAT_A1_DATA1_Msk) >> CAN_IF_DAT_A1_DATA1_Pos;
+ pCanMsg->Data[2] = tCAN->IF[1].DAT_A2 & CAN_IF_DAT_A2_DATA2_Msk;
+ pCanMsg->Data[3] = (tCAN->IF[1].DAT_A2 & CAN_IF_DAT_A2_DATA3_Msk) >> CAN_IF_DAT_A2_DATA3_Pos;
+ pCanMsg->Data[4] = tCAN->IF[1].DAT_B1 & CAN_IF_DAT_B1_DATA4_Msk;
+ pCanMsg->Data[5] = (tCAN->IF[1].DAT_B1 & CAN_IF_DAT_B1_DATA5_Msk) >> CAN_IF_DAT_B1_DATA5_Pos;
+ pCanMsg->Data[6] = tCAN->IF[1].DAT_B2 & CAN_IF_DAT_B2_DATA6_Msk;
+ pCanMsg->Data[7] = (tCAN->IF[1].DAT_B2 & CAN_IF_DAT_B2_DATA7_Msk) >> CAN_IF_DAT_B2_DATA7_Pos;
+
+ return TRUE;
+}
+
+/**
+ * @brief Set Rx message object, include ID mask.
+ * @param[in] u8MsgObj Specifies the Message object number, from 0 to 31.
+ * @param[in] u8idType Specifies the identifier type of the frames that will be transmitted
+ * This parameter can be one of the following values:
+ * \ref CAN_STD_ID (standard ID, 11-bit)
+ * \ref CAN_EXT_ID (extended ID, 29-bit)
+ * @param[in] u32id Specifies the identifier used for acceptance filtering.
+ * @param[in] u8singleOrFifoLast Specifies the end-of-buffer indicator.
+ * This parameter can be one of the following values:
+ * TRUE: for a single receive object or a FIFO receive object that is the last one of the FIFO.
+ * FALSE: for a FIFO receive object that is not the last one.
+ * @retval TRUE SUCCESS
+ * @retval FALSE No useful interface
+ * @details The function is used to configure a receive message object.
+ */
+int32_t CAN_SetRxMsgObjAndMsk(CAN_T *tCAN, uint8_t u8MsgObj, uint8_t u8idType, uint32_t u32id, uint32_t u32idmask, uint8_t u8singleOrFifoLast)
+{
+ uint8_t u8MsgIfNum;
+
+ /* Get and lock a free interface */
+ if((u8MsgIfNum = LockIF_TL(tCAN)) == 2)
+ return FALSE;
+
+ /* Command Setting */
+ tCAN->IF[u8MsgIfNum].CMASK = CAN_IF_CMASK_WRRD_Msk | CAN_IF_CMASK_MASK_Msk | CAN_IF_CMASK_ARB_Msk |
+ CAN_IF_CMASK_CONTROL_Msk | CAN_IF_CMASK_DATAA_Msk | CAN_IF_CMASK_DATAB_Msk;
+
+ if(u8idType == CAN_STD_ID) /* According STD/EXT ID format,Configure Mask and Arbitration register */
+ {
+ tCAN->IF[u8MsgIfNum].ARB1 = 0;
+ tCAN->IF[u8MsgIfNum].ARB2 = CAN_IF_ARB2_MSGVAL_Msk | (u32id & 0x7FF) << 2;
+ }
+ else
+ {
+ tCAN->IF[u8MsgIfNum].ARB1 = u32id & 0xFFFF;
+ tCAN->IF[u8MsgIfNum].ARB2 = CAN_IF_ARB2_MSGVAL_Msk | CAN_IF_ARB2_XTD_Msk | (u32id & 0x1FFF0000) >> 16;
+ }
+
+ tCAN->IF[u8MsgIfNum].MASK1 = (u32idmask & 0xFFFF);
+ tCAN->IF[u8MsgIfNum].MASK2 = (u32idmask >> 16) & 0xFFFF;
+
+ //tCAN->IF[u8MsgIfNum].MCON |= CAN_IF_MCON_UMASK_Msk | CAN_IF_MCON_RXIE_Msk;
+ tCAN->IF[u8MsgIfNum].MCON = CAN_IF_MCON_UMASK_Msk | CAN_IF_MCON_RXIE_Msk;
+ if(u8singleOrFifoLast)
+ tCAN->IF[u8MsgIfNum].MCON |= CAN_IF_MCON_EOB_Msk;
+ else
+ tCAN->IF[u8MsgIfNum].MCON &= (~CAN_IF_MCON_EOB_Msk);
+
+ tCAN->IF[u8MsgIfNum].DAT_A1 = 0;
+ tCAN->IF[u8MsgIfNum].DAT_A2 = 0;
+ tCAN->IF[u8MsgIfNum].DAT_B1 = 0;
+ tCAN->IF[u8MsgIfNum].DAT_B2 = 0;
+
+ tCAN->IF[u8MsgIfNum].CREQ = 1 + u8MsgObj;
+ ReleaseIF(tCAN, u8MsgIfNum);
+
+ return TRUE;
+}
+
+/**
+ * @brief Set Rx message object
+ * @param[in] u8MsgObj Specifies the Message object number, from 0 to 31.
+ * @param[in] u8idType Specifies the identifier type of the frames that will be transmitted
+ * This parameter can be one of the following values:
+ * \ref CAN_STD_ID (standard ID, 11-bit)
+ * \ref CAN_EXT_ID (extended ID, 29-bit)
+ * @param[in] u32id Specifies the identifier used for acceptance filtering.
+ * @param[in] u8singleOrFifoLast Specifies the end-of-buffer indicator.
+ * This parameter can be one of the following values:
+ * TRUE: for a single receive object or a FIFO receive object that is the last one of the FIFO.
+ * FALSE: for a FIFO receive object that is not the last one.
+ * @retval TRUE SUCCESS
+ * @retval FALSE No useful interface
+ * @details The function is used to configure a receive message object.
+ */
+int32_t CAN_SetRxMsgObj(CAN_T *tCAN, uint8_t u8MsgObj, uint8_t u8idType, uint32_t u32id, uint8_t u8singleOrFifoLast)
+{
+ uint8_t u8MsgIfNum;
+
+ /* Get and lock a free interface */
+ if((u8MsgIfNum = LockIF_TL(tCAN)) == 2)
+ return FALSE;
+
+ /* Command Setting */
+ tCAN->IF[u8MsgIfNum].CMASK = CAN_IF_CMASK_WRRD_Msk | CAN_IF_CMASK_MASK_Msk | CAN_IF_CMASK_ARB_Msk |
+ CAN_IF_CMASK_CONTROL_Msk | CAN_IF_CMASK_DATAA_Msk | CAN_IF_CMASK_DATAB_Msk;
+
+ if(u8idType == CAN_STD_ID) /* According STD/EXT ID format,Configure Mask and Arbitration register */
+ {
+ tCAN->IF[u8MsgIfNum].ARB1 = 0;
+ tCAN->IF[u8MsgIfNum].ARB2 = CAN_IF_ARB2_MSGVAL_Msk | (u32id & 0x7FF) << 2;
+ }
+ else
+ {
+ tCAN->IF[u8MsgIfNum].ARB1 = u32id & 0xFFFF;
+ tCAN->IF[u8MsgIfNum].ARB2 = CAN_IF_ARB2_MSGVAL_Msk | CAN_IF_ARB2_XTD_Msk | (u32id & 0x1FFF0000) >> 16;
+ }
+
+ //tCAN->IF[u8MsgIfNum].MCON |= CAN_IF_MCON_UMASK_Msk | CAN_IF_MCON_RXIE_Msk;
+ tCAN->IF[u8MsgIfNum].MCON = CAN_IF_MCON_UMASK_Msk | CAN_IF_MCON_RXIE_Msk;
+ if(u8singleOrFifoLast)
+ tCAN->IF[u8MsgIfNum].MCON |= CAN_IF_MCON_EOB_Msk;
+ else
+ tCAN->IF[u8MsgIfNum].MCON &= (~CAN_IF_MCON_EOB_Msk);
+
+ tCAN->IF[u8MsgIfNum].DAT_A1 = 0;
+ tCAN->IF[u8MsgIfNum].DAT_A2 = 0;
+ tCAN->IF[u8MsgIfNum].DAT_B1 = 0;
+ tCAN->IF[u8MsgIfNum].DAT_B2 = 0;
+
+ tCAN->IF[u8MsgIfNum].CREQ = 1 + u8MsgObj;
+ ReleaseIF(tCAN, u8MsgIfNum);
+
+ return TRUE;
+}
+
+/**
+ * @brief Gets the message
+ * @param[in] u8MsgObj Specifies the Message object number, from 0 to 31.
+ * @param[in] u8Release Specifies the message release indicator.
+ * This parameter can be one of the following values:
+ * TRUE: the message object is released when getting the data.
+ * FALSE:the message object is not released.
+ * @param[in] pCanMsg Pointer to the message structure where received data is copied.
+ * @retval TRUE Success
+ * @retval FALSE No any message received
+ * @details Gets the message, if received.
+ */
+int32_t CAN_ReadMsgObj(CAN_T *tCAN, uint8_t u8MsgObj, uint8_t u8Release, STR_CANMSG_T* pCanMsg)
+{
+ uint8_t u8MsgIfNum;
+
+ if(!CAN_IsNewDataReceived(tCAN, u8MsgObj))
+ return FALSE;
+
+ /* Get and lock a free interface */
+ if((u8MsgIfNum = LockIF_TL(tCAN)) == 2)
+ return FALSE;
+
+ tCAN->STATUS &= (~CAN_STATUS_RXOK_Msk);
+
+ /* read the message contents*/
+ tCAN->IF[u8MsgIfNum].CMASK = CAN_IF_CMASK_MASK_Msk
+ | CAN_IF_CMASK_ARB_Msk
+ | CAN_IF_CMASK_CONTROL_Msk
+ | CAN_IF_CMASK_CLRINTPND_Msk
+ | (u8Release ? CAN_IF_CMASK_TXRQSTNEWDAT_Msk : 0)
+ | CAN_IF_CMASK_DATAA_Msk
+ | CAN_IF_CMASK_DATAB_Msk;
+
+ tCAN->IF[u8MsgIfNum].CREQ = 1 + u8MsgObj;
+
+ while(tCAN->IF[u8MsgIfNum].CREQ & CAN_IF_CREQ_BUSY_Msk)
+ {
+ /*Wait*/
+ }
+
+ if((tCAN->IF[u8MsgIfNum].ARB2 & CAN_IF_ARB2_XTD_Msk) == 0)
+ {
+ /* standard ID*/
+ pCanMsg->IdType = CAN_STD_ID;
+ pCanMsg->Id = (tCAN->IF[u8MsgIfNum].ARB2 & CAN_IF_ARB2_ID_Msk) >> 2;
+ }
+ else
+ {
+ /* extended ID*/
+ pCanMsg->IdType = CAN_EXT_ID;
+ pCanMsg->Id = (((tCAN->IF[u8MsgIfNum].ARB2) & 0x1FFF) << 16) | tCAN->IF[u8MsgIfNum].ARB1;
+ }
+
+ pCanMsg->DLC = tCAN->IF[u8MsgIfNum].MCON & CAN_IF_MCON_DLC_Msk;
+ pCanMsg->Data[0] = tCAN->IF[u8MsgIfNum].DAT_A1 & CAN_IF_DAT_A1_DATA0_Msk;
+ pCanMsg->Data[1] = (tCAN->IF[u8MsgIfNum].DAT_A1 & CAN_IF_DAT_A1_DATA1_Msk) >> CAN_IF_DAT_A1_DATA1_Pos;
+ pCanMsg->Data[2] = tCAN->IF[u8MsgIfNum].DAT_A2 & CAN_IF_DAT_A2_DATA2_Msk;
+ pCanMsg->Data[3] = (tCAN->IF[u8MsgIfNum].DAT_A2 & CAN_IF_DAT_A2_DATA3_Msk) >> CAN_IF_DAT_A2_DATA3_Pos;
+ pCanMsg->Data[4] = tCAN->IF[u8MsgIfNum].DAT_B1 & CAN_IF_DAT_B1_DATA4_Msk;
+ pCanMsg->Data[5] = (tCAN->IF[u8MsgIfNum].DAT_B1 & CAN_IF_DAT_B1_DATA5_Msk) >> CAN_IF_DAT_B1_DATA5_Pos;
+ pCanMsg->Data[6] = tCAN->IF[u8MsgIfNum].DAT_B2 & CAN_IF_DAT_B2_DATA6_Msk;
+ pCanMsg->Data[7] = (tCAN->IF[u8MsgIfNum].DAT_B2 & CAN_IF_DAT_B2_DATA7_Msk) >> CAN_IF_DAT_B2_DATA7_Pos;
+
+ ReleaseIF(tCAN, u8MsgIfNum);
+ return TRUE;
+}
+
+/// @endcond HIDDEN_SYMBOLS
+
+
+/**
+ * @brief Set bus baud-rate.
+ *
+ * @param[in] tCAN The pointer to CAN module base address.
+ * @param[in] u32BaudRate The target CAN baud-rate. The range of u32BaudRate is 1~1000KHz.
+ *
+ * @return u32CurrentBitRate Real baud-rate value.
+ *
+ * @details The function is used to set bus timing parameter according current clock and target baud-rate.
+ */
+uint32_t CAN_SetBaudRate(CAN_T *tCAN, uint32_t u32BaudRate)
+{
+ uint8_t u8Tseg1, u8Tseg2;
+ uint32_t u32Brp;
+ uint32_t u32Value;
+
+ CAN_EnterInitMode(tCAN, 0);
+ SystemCoreClockUpdate();
+ u32Value = SystemCoreClock / u32BaudRate;
+
+#if 0
+ u8Tseg1 = 2;
+ u8Tseg2 = 1;
+ while(1)
+ {
+ if(((u32Value % (u8Tseg1 + u8Tseg2 + 3)) == 0))
+ break;
+ if(u8Tseg1 < 7)
+ u8Tseg2++;
+
+ if((u32Value % (u8Tseg1 + u8Tseg2 + 3)) == 0)
+ break;
+ if(u8Tseg1 < 15)
+ u8Tseg1++;
+ else
+ {
+ u8Tseg1 = 2;
+ u8Tseg2 = 1;
+ break;
+ }
+ }
+#else
+
+ /* Fix for most standard baud rates, include 125K */
+
+ u8Tseg1 = 3;
+ u8Tseg2 = 2;
+ while(1)
+ {
+ if(((u32Value % (u8Tseg1 + u8Tseg2 + 3)) == 0) | (u8Tseg1 >= 15))
+ break;
+
+ u8Tseg1++;
+
+ if((u32Value % (u8Tseg1 + u8Tseg2 + 3)) == 0)
+ break;
+
+ if(u8Tseg2 < 7)
+ u8Tseg2++;
+ }
+#endif
+ u32Brp = SystemCoreClock / (u32BaudRate) / (u8Tseg1 + u8Tseg2 + 3) - 1;
+
+ u32Value = ((uint32_t)u8Tseg2 << CAN_BTIME_TSEG2_Pos) | ((uint32_t)u8Tseg1 << CAN_BTIME_TSEG1_Pos) |
+ (u32Brp & CAN_BTIME_BRP_Msk) | (tCAN->BTIME & CAN_BTIME_SJW_Msk);
+ tCAN->BTIME = u32Value;
+ tCAN->BRPE = (u32Brp >> 6) & 0x0F;
+
+ CAN_LeaveInitMode(tCAN);
+
+ return (CAN_GetCANBitRate(tCAN));
+}
+
+/**
+ * @brief The function is used to disable all CAN interrupt.
+ *
+ * @param[in] tCAN The pointer to CAN module base address.
+ *
+ * @return None
+ *
+ * @details No Status Change Interrupt and Error Status Interrupt will be generated.
+ */
+void CAN_Close(CAN_T *tCAN)
+{
+ CAN_DisableInt(tCAN, (CAN_CON_IE_Msk | CAN_CON_SIE_Msk | CAN_CON_EIE_Msk));
+}
+
+/**
+ * @brief Set CAN operation mode and target baud-rate.
+ *
+ * @param[in] tCAN The pointer to CAN module base address.
+ * @param[in] u32BaudRate The target CAN baud-rate. The range of u32BaudRate is 1~1000KHz.
+ * @param[in] u32Mode The CAN operation mode. Valid values are:
+ * - \ref CAN_NORMAL_MODE Normal operation.
+ * - \ref CAN_BASIC_MODE Basic mode.
+ * @return u32CurrentBitRate Real baud-rate value.
+ *
+ * @details Set bus timing parameter according current clock and target baud-rate.
+ * In Basic mode, IF1 Registers used as Tx Buffer, IF2 Registers used as Rx Buffer.
+ */
+uint32_t CAN_Open(CAN_T *tCAN, uint32_t u32BaudRate, uint32_t u32Mode)
+{
+ uint32_t u32CurrentBitRate;
+
+ u32CurrentBitRate = CAN_SetBaudRate(tCAN, u32BaudRate);
+
+ if(u32Mode == CAN_BASIC_MODE)
+ CAN_EnterTestMode(tCAN, CAN_TEST_BASIC_Msk);
+
+ return u32CurrentBitRate;
+}
+
+/**
+ * @brief The function is used to configure a transmit object.
+ *
+ * @param[in] tCAN The pointer to CAN module base address.
+ * @param[in] u32MsgNum Specifies the Message object number, from 0 to 31.
+ * @param[in] pCanMsg Pointer to the message structure where received data is copied.
+ *
+ * @retval FALSE No useful interface.
+ * @retval TRUE Config message object success.
+ *
+ * @details The two sets of interface registers (IF1 and IF2) control the software access to the Message RAM.
+ * They buffer the data to be transferred to and from the RAM, avoiding conflicts between software accesses and message reception/transmission.
+ */
+int32_t CAN_SetTxMsg(CAN_T *tCAN, uint32_t u32MsgNum , STR_CANMSG_T* pCanMsg)
+{
+ uint8_t u8MsgIfNum;
+
+ if((u8MsgIfNum = LockIF_TL(tCAN)) == 2)
+ return FALSE;
+
+ /* update the contents needed for transmission*/
+ tCAN->IF[u8MsgIfNum].CMASK = CAN_IF_CMASK_WRRD_Msk | CAN_IF_CMASK_MASK_Msk | CAN_IF_CMASK_ARB_Msk |
+ CAN_IF_CMASK_CONTROL_Msk | CAN_IF_CMASK_DATAA_Msk | CAN_IF_CMASK_DATAB_Msk;
+
+ if(pCanMsg->IdType == CAN_STD_ID)
+ {
+ /* standard ID*/
+ tCAN->IF[u8MsgIfNum].ARB1 = 0;
+ tCAN->IF[u8MsgIfNum].ARB2 = (((pCanMsg->Id) & 0x7FF) << 2) | CAN_IF_ARB2_DIR_Msk | CAN_IF_ARB2_MSGVAL_Msk;
+ }
+ else
+ {
+ /* extended ID*/
+ tCAN->IF[u8MsgIfNum].ARB1 = (pCanMsg->Id) & 0xFFFF;
+ tCAN->IF[u8MsgIfNum].ARB2 = ((pCanMsg->Id) & 0x1FFF0000) >> 16 |
+ CAN_IF_ARB2_DIR_Msk | CAN_IF_ARB2_XTD_Msk | CAN_IF_ARB2_MSGVAL_Msk;
+ }
+
+ if(pCanMsg->FrameType)
+ tCAN->IF[u8MsgIfNum].ARB2 |= CAN_IF_ARB2_DIR_Msk;
+ else
+ tCAN->IF[u8MsgIfNum].ARB2 &= (~CAN_IF_ARB2_DIR_Msk);
+
+ tCAN->IF[u8MsgIfNum].DAT_A1 = ((uint16_t)pCanMsg->Data[1] << 8) | pCanMsg->Data[0];
+ tCAN->IF[u8MsgIfNum].DAT_A2 = ((uint16_t)pCanMsg->Data[3] << 8) | pCanMsg->Data[2];
+ tCAN->IF[u8MsgIfNum].DAT_B1 = ((uint16_t)pCanMsg->Data[5] << 8) | pCanMsg->Data[4];
+ tCAN->IF[u8MsgIfNum].DAT_B2 = ((uint16_t)pCanMsg->Data[7] << 8) | pCanMsg->Data[6];
+
+ tCAN->IF[u8MsgIfNum].MCON = CAN_IF_MCON_NEWDAT_Msk | pCanMsg->DLC | CAN_IF_MCON_TXIE_Msk | CAN_IF_MCON_EOB_Msk;
+ tCAN->IF[u8MsgIfNum].CREQ = 1 + u32MsgNum;
+
+ ReleaseIF(tCAN, u8MsgIfNum);
+ return TRUE;
+}
+
+/**
+ * @brief Set transmit request bit.
+ *
+ * @param[in] tCAN The pointer to CAN module base address.
+ * @param[in] u32MsgNum Specifies the Message object number, from 0 to 31.
+ *
+ * @return TRUE: Start transmit message.
+ *
+ * @details If a transmission is requested by programming bit TxRqst/NewDat (IFn_CMASK[2]), the TxRqst (IFn_MCON[8]) will be ignored.
+ */
+int32_t CAN_TriggerTxMsg(CAN_T *tCAN, uint32_t u32MsgNum)
+{
+ uint8_t u8MsgIfNum;
+
+ if((u8MsgIfNum = LockIF_TL(tCAN)) == 2)
+ return FALSE;
+
+ tCAN->STATUS &= (~CAN_STATUS_TXOK_Msk);
+
+ /* read the message contents*/
+ tCAN->IF[u8MsgIfNum].CMASK = CAN_IF_CMASK_CLRINTPND_Msk
+ | CAN_IF_CMASK_TXRQSTNEWDAT_Msk;
+
+ tCAN->IF[u8MsgIfNum].CREQ = 1 + u32MsgNum;
+
+ while(tCAN->IF[u8MsgIfNum].CREQ & CAN_IF_CREQ_BUSY_Msk)
+ {
+ /*Wait*/
+ }
+ tCAN->IF[u8MsgIfNum].CMASK = CAN_IF_CMASK_WRRD_Msk | CAN_IF_CMASK_TXRQSTNEWDAT_Msk;
+ tCAN->IF[u8MsgIfNum].CREQ = 1 + u32MsgNum;
+
+ ReleaseIF(tCAN, u8MsgIfNum);
+ return TRUE;
+}
+
+/**
+ * @brief Enable CAN interrupt.
+ *
+ * @param[in] tCAN The pointer to CAN module base address.
+ * @param[in] u32Mask Interrupt Mask. Valid values are:
+ * - \ref CAN_CON_IE_Msk Module interrupt enable.
+ * - \ref CAN_CON_SIE_Msk Status change interrupt enable.
+ * - \ref CAN_CON_EIE_Msk Error interrupt enable.
+ *
+ * @return None
+ *
+ * @details The application software has two possibilities to follow the source of a message interrupt.
+ * First, it can follow the IntId in the Interrupt Register and second it can poll the Interrupt Pending Register.
+ */
+void CAN_EnableInt(CAN_T *tCAN, uint32_t u32Mask)
+{
+ tCAN->CON = (tCAN->CON & ~(CAN_CON_IE_Msk | CAN_CON_SIE_Msk | CAN_CON_EIE_Msk)) |
+ (u32Mask & (CAN_CON_IE_Msk | CAN_CON_SIE_Msk | CAN_CON_EIE_Msk));
+}
+
+/**
+ * @brief Disable CAN interrupt.
+ *
+ * @param[in] tCAN The pointer to CAN module base address.
+ * @param[in] u32Mask Interrupt Mask. (CAN_CON_IE_Msk / CAN_CON_SIE_Msk / CAN_CON_EIE_Msk).
+ *
+ * @return None
+ *
+ * @details The interrupt remains active until the Interrupt Register is back to value zero (the cause of the interrupt is reset) or until IE is reset.
+ */
+void CAN_DisableInt(CAN_T *tCAN, uint32_t u32Mask)
+{
+ tCAN->CON = tCAN->CON & ~((u32Mask & (CAN_CON_IE_Msk | CAN_CON_SIE_Msk | CAN_CON_EIE_Msk)));
+}
+
+
+/**
+ * @brief The function is used to configure a receive message object.
+ *
+ * @param[in] tCAN The pointer to CAN module base address.
+ * @param[in] u32MsgNum Specifies the Message object number, from 0 to 31.
+ * @param[in] u32IDType Specifies the identifier type of the frames that will be transmitted. Valid values are:
+ * - \ref CAN_STD_ID The 11-bit identifier.
+ * - \ref CAN_EXT_ID The 29-bit identifier.
+ * @param[in] u32ID Specifies the identifier used for acceptance filtering.
+ *
+ * @retval FALSE No useful interface.
+ * @retval TRUE Configure a receive message object success.
+ *
+ * @details If the RxIE bit (CAN_IFn_MCON[10]) is set, the IntPnd bit (CAN_IFn_MCON[13])
+ * will be set when a received Data Frame is accepted and stored in the Message Object.
+ */
+int32_t CAN_SetRxMsg(CAN_T *tCAN, uint32_t u32MsgNum , uint32_t u32IDType, uint32_t u32ID)
+{
+ uint32_t u32TimeOutCount = 0;
+
+ while(CAN_SetRxMsgObj(tCAN, u32MsgNum, u32IDType, u32ID, TRUE) == FALSE)
+ {
+ if(++u32TimeOutCount >= RETRY_COUNTS) return FALSE;
+ }
+
+ return TRUE;
+}
+
+/**
+ * @brief The function is used to configure a receive message object.
+ *
+ * @param[in] tCAN The pointer to CAN module base address.
+ * @param[in] u32MsgNum Specifies the Message object number, from 0 to 31.
+ * @param[in] u32IDType Specifies the identifier type of the frames that will be transmitted. Valid values are:
+ * - \ref CAN_STD_ID The 11-bit identifier.
+ * - \ref CAN_EXT_ID The 29-bit identifier.
+ * @param[in] u32ID Specifies the identifier used for acceptance filtering.
+ * @param[in] u32IDMask Specifies the identifier mask used for acceptance filtering.
+ *
+ * @retval FALSE No useful interface.
+ * @retval TRUE Configure a receive message object success.
+ *
+ * @details If the RxIE bit (CAN_IFn_MCON[10]) is set, the IntPnd bit (CAN_IFn_MCON[13])
+ * will be set when a received Data Frame is accepted and stored in the Message Object.
+ */
+int32_t CAN_SetRxMsgAndMsk(CAN_T *tCAN, uint32_t u32MsgNum , uint32_t u32IDType, uint32_t u32ID, uint32_t u32IDMask)
+{
+ uint32_t u32TimeOutCount = 0;
+
+ while(CAN_SetRxMsgObjAndMsk(tCAN, u32MsgNum, u32IDType, u32ID, u32IDMask, TRUE) == FALSE)
+ {
+ if(++u32TimeOutCount >= RETRY_COUNTS) return FALSE;
+ }
+
+ return TRUE;
+}
+
+/**
+ * @brief The function is used to configure several receive message objects.
+ *
+ * @param[in] tCAN The pointer to CAN module base address.
+ * @param[in] u32MsgNum The starting MSG RAM number(0 ~ 31).
+ * @param[in] u32MsgCount the number of MSG RAM of the FIFO.
+ * @param[in] u32IDType Specifies the identifier type of the frames that will be transmitted. Valid values are:
+ * - \ref CAN_STD_ID The 11-bit identifier.
+ * - \ref CAN_EXT_ID The 29-bit identifier.
+ * @param[in] u32ID Specifies the identifier used for acceptance filtering.
+ *
+ * @retval FALSE No useful interface.
+ * @retval TRUE Configure receive message objects success.
+ *
+ * @details The Interface Registers avoid conflict between the CPU accesses to the Message RAM and CAN message reception
+ * and transmission by buffering the data to be transferred.
+ */
+int32_t CAN_SetMultiRxMsg(CAN_T *tCAN, uint32_t u32MsgNum , uint32_t u32MsgCount, uint32_t u32IDType, uint32_t u32ID)
+{
+ uint32_t i = 0;
+ uint32_t u32TimeOutCount;
+ uint32_t u32EOB_Flag = 0;
+
+ for(i = 1; i < u32MsgCount; i++)
+ {
+ u32TimeOutCount = 0;
+
+ u32MsgNum += (i - 1);
+
+ if(i == u32MsgCount) u32EOB_Flag = 1;
+
+ while(CAN_SetRxMsgObj(tCAN, u32MsgNum, u32IDType, u32ID, u32EOB_Flag) == FALSE)
+ {
+ if(++u32TimeOutCount >= RETRY_COUNTS) return FALSE;
+ }
+ }
+
+ return TRUE;
+}
+
+
+/**
+ * @brief Send CAN message.
+ * @param[in] tCAN The pointer to CAN module base address.
+ * @param[in] u32MsgNum Specifies the Message object number, from 0 to 31.
+ * @param[in] pCanMsg Pointer to the message structure where received data is copied.
+ *
+ * @retval FALSE 1. When operation in basic mode: Transmit message time out. \n
+ * 2. When operation in normal mode: No useful interface. \n
+ * @retval TRUE Transmit Message success.
+ *
+ * @details The receive/transmit priority for the Message Objects is attached to the message number.
+ * Message Object 1 has the highest priority, while Message Object 32 has the lowest priority.
+ */
+int32_t CAN_Transmit(CAN_T *tCAN, uint32_t u32MsgNum , STR_CANMSG_T* pCanMsg)
+{
+ if((tCAN->CON & CAN_CON_TEST_Msk) && (tCAN->TEST & CAN_TEST_BASIC_Msk))
+ {
+ return (CAN_BasicSendMsg(tCAN, pCanMsg));
+ }
+ else
+ {
+ if(CAN_SetTxMsg(tCAN, u32MsgNum, pCanMsg) == FALSE)
+ return FALSE;
+ CAN_TriggerTxMsg(tCAN, u32MsgNum);
+ }
+
+ return TRUE;
+}
+
+
+/**
+ * @brief Gets the message, if received.
+ * @param[in] tCAN The pointer to CAN module base address.
+ * @param[in] u32MsgNum Specifies the Message object number, from 0 to 31.
+ * @param[in] pCanMsg Pointer to the message structure where received data is copied.
+ *
+ * @retval FALSE No any message received.
+ * @retval TRUE Receive Message success.
+ *
+ * @details The Interface Registers avoid conflict between the CPU accesses to the Message RAM and CAN message reception
+ * and transmission by buffering the data to be transferred.
+ */
+int32_t CAN_Receive(CAN_T *tCAN, uint32_t u32MsgNum , STR_CANMSG_T* pCanMsg)
+{
+ if((tCAN->CON & CAN_CON_TEST_Msk) && (tCAN->TEST & CAN_TEST_BASIC_Msk))
+ {
+ return (CAN_BasicReceiveMsg(tCAN, pCanMsg));
+ }
+ else
+ {
+ return CAN_ReadMsgObj(tCAN, u32MsgNum, TRUE, pCanMsg);
+ }
+}
+
+/**
+ * @brief Clear interrupt pending bit.
+ * @param[in] tCAN The pointer to CAN module base address.
+ * @param[in] u32MsgNum Specifies the Message object number, from 0 to 31.
+ *
+ * @return None
+ *
+ * @details An interrupt remains pending until the application software has cleared it.
+ */
+void CAN_CLR_INT_PENDING_BIT(CAN_T *tCAN, uint8_t u32MsgNum)
+{
+ uint32_t u32MsgIfNum;
+
+ if((u32MsgIfNum = LockIF_TL(tCAN)) == 2)
+ u32MsgIfNum = 0;
+
+ tCAN->IF[u32MsgIfNum].CMASK = CAN_IF_CMASK_CLRINTPND_Msk | CAN_IF_CMASK_TXRQSTNEWDAT_Msk;
+ tCAN->IF[u32MsgIfNum].CREQ = 1 + u32MsgNum;
+
+ ReleaseIF(tCAN, u32MsgIfNum);
+}
+
+
+/*@}*/ /* end of group CAN_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group CAN_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+/*** (C) COPYRIGHT 2014~2015 Nuvoton Technology Corp. ***/
+
diff --git a/bsp/nuvoton_m451/Libraries/StdDriver/src/clk.c b/bsp/nuvoton_m451/Libraries/StdDriver/src/clk.c
new file mode 100644
index 0000000000000000000000000000000000000000..eae295ea443c0e070c2122bd2c13137f5de865ab
--- /dev/null
+++ b/bsp/nuvoton_m451/Libraries/StdDriver/src/clk.c
@@ -0,0 +1,751 @@
+/**************************************************************************//**
+ * @file clk.c
+ * @version V3.00
+ * $Revision: 35 $
+ * $Date: 15/08/11 10:26a $
+ * @brief M451 series CLK driver source file
+ *
+ * @note
+ * Copyright (C) 2014~2015 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+
+#include "M451Series.h"
+
+/** @addtogroup Standard_Driver Standard Driver
+ @{
+*/
+
+/** @addtogroup CLK_Driver CLK Driver
+ @{
+*/
+
+/** @addtogroup CLK_EXPORTED_FUNCTIONS CLK Exported Functions
+ @{
+*/
+
+/**
+ * @brief Disable clock divider output function
+ * @param None
+ * @return None
+ * @details This function disable clock divider output function.
+ */
+void CLK_DisableCKO(void)
+{
+ /* Disable CKO clock source */
+ CLK_DisableModuleClock(CLKO_MODULE);
+}
+
+/**
+ * @brief This function enable clock divider output module clock,
+ * enable clock divider output function and set frequency selection.
+ * @param[in] u32ClkSrc is frequency divider function clock source. Including :
+ * - \ref CLK_CLKSEL1_CLKOSEL_HXT
+ * - \ref CLK_CLKSEL1_CLKOSEL_LXT
+ * - \ref CLK_CLKSEL1_CLKOSEL_HCLK
+ * - \ref CLK_CLKSEL1_CLKOSEL_HIRC
+ * @param[in] u32ClkDiv is divider output frequency selection. It could be 0~15.
+ * @param[in] u32ClkDivBy1En is clock divided by one enabled.
+ * @return None
+ * @details Output selected clock to CKO. The output clock frequency is divided by u32ClkDiv. \n
+ * The formula is: \n
+ * CKO frequency = (Clock source frequency) / 2^(u32ClkDiv + 1) \n
+ * This function is just used to set CKO clock.
+ * User must enable I/O for CKO clock output pin by themselves. \n
+ */
+void CLK_EnableCKO(uint32_t u32ClkSrc, uint32_t u32ClkDiv, uint32_t u32ClkDivBy1En)
+{
+ /* CKO = clock source / 2^(u32ClkDiv + 1) */
+ CLK->CLKOCTL = CLK_CLKOCTL_CLKOEN_Msk | u32ClkDiv | (u32ClkDivBy1En << CLK_CLKOCTL_DIV1EN_Pos);
+
+ /* Enable CKO clock source */
+ CLK_EnableModuleClock(CLKO_MODULE);
+
+ /* Select CKO clock source */
+ CLK_SetModuleClock(CLKO_MODULE, u32ClkSrc, 0);
+}
+
+/**
+ * @brief Enter to Power-down mode
+ * @param None
+ * @return None
+ * @details This function is used to let system enter to Power-down mode. \n
+ * The register write-protection function should be disabled before using this function.
+ */
+void CLK_PowerDown(void)
+{
+ /* Set the processor uses deep sleep as its low power mode */
+ SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
+
+ /* Set system Power-down enabled and Power-down entry condition */
+ CLK->PWRCTL |= (CLK_PWRCTL_PDEN_Msk | CLK_PWRCTL_PDWTCPU_Msk);
+
+ /* Chip enter Power-down mode after CPU run WFI instruction */
+ __WFI();
+}
+
+/**
+ * @brief Enter to Idle mode
+ * @param None
+ * @return None
+ * @details This function let system enter to Idle mode. \n
+ * The register write-protection function should be disabled before using this function.
+ */
+void CLK_Idle(void)
+{
+ /* Set the processor uses sleep as its low power mode */
+ SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
+
+ /* Set chip in idle mode because of WFI command */
+ CLK->PWRCTL &= ~CLK_PWRCTL_PDEN_Msk;
+
+ /* Chip enter idle mode after CPU run WFI instruction */
+ __WFI();
+}
+
+/**
+ * @brief Get external high speed crystal clock frequency
+ * @param None
+ * @return External high frequency crystal frequency
+ * @details This function get external high frequency crystal frequency. The frequency unit is Hz.
+ */
+uint32_t CLK_GetHXTFreq(void)
+{
+ if(CLK->PWRCTL & CLK_PWRCTL_HXTEN_Msk)
+ return __HXT;
+ else
+ return 0;
+}
+
+
+/**
+ * @brief Get external low speed crystal clock frequency
+ * @param None
+ * @return External low speed crystal clock frequency
+ * @details This function get external low frequency crystal frequency. The frequency unit is Hz.
+ */
+uint32_t CLK_GetLXTFreq(void)
+{
+ if(CLK->PWRCTL & CLK_PWRCTL_LXTEN_Msk)
+ return __LXT;
+ else
+ return 0;
+}
+
+/**
+ * @brief Get PCLK0 frequency
+ * @param None
+ * @return PCLK0 frequency
+ * @details This function get PCLK0 frequency. The frequency unit is Hz.
+ */
+uint32_t CLK_GetPCLK0Freq(void)
+{
+ SystemCoreClockUpdate();
+ if(CLK->CLKSEL0 & CLK_CLKSEL0_PCLK0SEL_Msk)
+ return SystemCoreClock / 2;
+ else
+ return SystemCoreClock;
+}
+
+
+/**
+ * @brief Get PCLK1 frequency
+ * @param None
+ * @return PCLK1 frequency
+ * @details This function get PCLK1 frequency. The frequency unit is Hz.
+ */
+uint32_t CLK_GetPCLK1Freq(void)
+{
+ SystemCoreClockUpdate();
+ if(CLK->CLKSEL0 & CLK_CLKSEL0_PCLK1SEL_Msk)
+ return SystemCoreClock / 2;
+ else
+ return SystemCoreClock;
+}
+
+
+/**
+ * @brief Get HCLK frequency
+ * @param None
+ * @return HCLK frequency
+ * @details This function get HCLK frequency. The frequency unit is Hz.
+ */
+uint32_t CLK_GetHCLKFreq(void)
+{
+ SystemCoreClockUpdate();
+ return SystemCoreClock;
+}
+
+
+/**
+ * @brief Get CPU frequency
+ * @param None
+ * @return CPU frequency
+ * @details This function get CPU frequency. The frequency unit is Hz.
+ */
+uint32_t CLK_GetCPUFreq(void)
+{
+ SystemCoreClockUpdate();
+ return SystemCoreClock;
+}
+
+
+/**
+ * @brief Set HCLK frequency
+ * @param[in] u32Hclk is HCLK frequency. The range of u32Hclk is 25 MHz ~ 72 MHz.
+ * @return HCLK frequency
+ * @details This function is used to set HCLK frequency. The frequency unit is Hz. \n
+ * It would configure PLL frequency to 50MHz ~ 144MHz,
+ * set HCLK clock divider as 2 and switch HCLK clock source to PLL. \n
+ * The register write-protection function should be disabled before using this function.
+ */
+uint32_t CLK_SetCoreClock(uint32_t u32Hclk)
+{
+ uint32_t u32HIRCSTB;
+
+ /* Read HIRC clock source stable flag */
+ u32HIRCSTB = CLK->STATUS & CLK_STATUS_HIRCSTB_Msk;
+
+ /* The range of u32Hclk is 25 MHz ~ 72 MHz */
+ if(u32Hclk > FREQ_72MHZ)
+ u32Hclk = FREQ_72MHZ;
+ if(u32Hclk < FREQ_25MHZ)
+ u32Hclk = FREQ_25MHZ;
+
+ /* Switch HCLK clock source to HIRC clock for safe */
+ CLK->PWRCTL |= CLK_PWRCTL_HIRCEN_Msk;
+ CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk);
+ CLK->CLKSEL0 |= CLK_CLKSEL0_HCLKSEL_Msk;
+ CLK->CLKDIV0 &= (~CLK_CLKDIV0_HCLKDIV_Msk);
+
+ /* Configure PLL setting if HXT clock is enabled */
+ if(CLK->PWRCTL & CLK_PWRCTL_HXTEN_Msk)
+ u32Hclk = CLK_EnablePLL(CLK_PLLCTL_PLLSRC_HXT, (u32Hclk << 1));
+
+ /* Configure PLL setting if HXT clock is not enabled */
+ else
+ {
+ u32Hclk = CLK_EnablePLL(CLK_PLLCTL_PLLSRC_HIRC, (u32Hclk << 1));
+
+ /* Read HIRC clock source stable flag */
+ u32HIRCSTB = CLK->STATUS & CLK_STATUS_HIRCSTB_Msk;
+ }
+
+ /* Select HCLK clock source to PLL,
+ Select HCLK clock source divider as 2
+ and update system core clock
+ */
+ CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_PLL, CLK_CLKDIV0_HCLK(2));
+
+ /* Disable HIRC if HIRC is disabled before setting core clock */
+ if(u32HIRCSTB == 0)
+ CLK->PWRCTL &= ~CLK_PWRCTL_HIRCEN_Msk;
+
+ /* Return actually HCLK frequency is PLL frequency divide 2 */
+ return u32Hclk >> 1;
+}
+
+/**
+ * @brief This function set HCLK clock source and HCLK clock divider
+ * @param[in] u32ClkSrc is HCLK clock source. Including :
+ * - \ref CLK_CLKSEL0_HCLKSEL_HXT
+ * - \ref CLK_CLKSEL0_HCLKSEL_LXT
+ * - \ref CLK_CLKSEL0_HCLKSEL_PLL
+ * - \ref CLK_CLKSEL0_HCLKSEL_LIRC
+ * - \ref CLK_CLKSEL0_HCLKSEL_HIRC
+ * @param[in] u32ClkDiv is HCLK clock divider. Including :
+ * - \ref CLK_CLKDIV0_HCLK(x)
+ * @return None
+ * @details This function set HCLK clock source and HCLK clock divider. \n
+ * The register write-protection function should be disabled before using this function.
+ */
+void CLK_SetHCLK(uint32_t u32ClkSrc, uint32_t u32ClkDiv)
+{
+ uint32_t u32HIRCSTB;
+
+ /* Read HIRC clock source stable flag */
+ u32HIRCSTB = CLK->STATUS & CLK_STATUS_HIRCSTB_Msk;
+
+ /* Switch to HIRC for Safe. Avoid HCLK too high when applying new divider. */
+ CLK->PWRCTL |= CLK_PWRCTL_HIRCEN_Msk;
+ CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk);
+ CLK->CLKSEL0 = (CLK->CLKSEL0 & (~CLK_CLKSEL0_HCLKSEL_Msk)) | CLK_CLKSEL0_HCLKSEL_HIRC;
+
+ /* Apply new Divider */
+ CLK->CLKDIV0 = (CLK->CLKDIV0 & (~CLK_CLKDIV0_HCLKDIV_Msk)) | u32ClkDiv;
+
+ /* Switch HCLK to new HCLK source */
+ CLK->CLKSEL0 = (CLK->CLKSEL0 & (~CLK_CLKSEL0_HCLKSEL_Msk)) | u32ClkSrc;
+
+ /* Update System Core Clock */
+ SystemCoreClockUpdate();
+
+ /* Disable HIRC if HIRC is disabled before switching HCLK source */
+ if(u32HIRCSTB == 0)
+ CLK->PWRCTL &= ~CLK_PWRCTL_HIRCEN_Msk;
+}
+
+/**
+ * @brief This function set selected module clock source and module clock divider
+ * @param[in] u32ModuleIdx is module index.
+ * @param[in] u32ClkSrc is module clock source.
+ * @param[in] u32ClkDiv is module clock divider.
+ * @return None
+ * @details Valid parameter combinations listed in following table:
+ *
+ * |Module index |Clock source |Divider |
+ * | :---------------- | :----------------------------------- | :---------------------- |
+ * |\ref WDT_MODULE |\ref CLK_CLKSEL1_WDTSEL_LXT | x |
+ * |\ref WDT_MODULE |\ref CLK_CLKSEL1_WDTSEL_PCLK0_DIV2048 | x |
+ * |\ref WDT_MODULE |\ref CLK_CLKSEL1_WDTSEL_LIRC | x |
+ * |\ref RTC_MODULE |\ref CLK_CLKSEL3_RTCSEL_LXT | x |
+ * |\ref RTC_MODULE |\ref CLK_CLKSEL3_RTCSEL_LIRC | x |
+ * |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0SEL_HXT | x |
+ * |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0SEL_LXT | x |
+ * |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0SEL_PCLK0 | x |
+ * |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0SEL_EXT_TRG | x |
+ * |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0SEL_LIRC | x |
+ * |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0SEL_HIRC | x |
+ * |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1SEL_HXT | x |
+ * |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1SEL_LXT | x |
+ * |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1SEL_PCLK0 | x |
+ * |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1SEL_EXT_TRG | x |
+ * |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1SEL_LIRC | x |
+ * |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1SEL_HIRC | x |
+ * |\ref TMR2_MODULE |\ref CLK_CLKSEL1_TMR2SEL_HXT | x |
+ * |\ref TMR2_MODULE |\ref CLK_CLKSEL1_TMR2SEL_LXT | x |
+ * |\ref TMR2_MODULE |\ref CLK_CLKSEL1_TMR2SEL_PCLK1 | x |
+ * |\ref TMR2_MODULE |\ref CLK_CLKSEL1_TMR2SEL_EXT_TRG | x |
+ * |\ref TMR2_MODULE |\ref CLK_CLKSEL1_TMR2SEL_LIRC | x |
+ * |\ref TMR2_MODULE |\ref CLK_CLKSEL1_TMR2SEL_HIRC | x |
+ * |\ref TMR3_MODULE |\ref CLK_CLKSEL1_TMR3SEL_HXT | x |
+ * |\ref TMR3_MODULE |\ref CLK_CLKSEL1_TMR3SEL_LXT | x |
+ * |\ref TMR3_MODULE |\ref CLK_CLKSEL1_TMR3SEL_PCLK1 | x |
+ * |\ref TMR3_MODULE |\ref CLK_CLKSEL1_TMR3SEL_EXT_TRG | x |
+ * |\ref TMR3_MODULE |\ref CLK_CLKSEL1_TMR3SEL_LIRC | x |
+ * |\ref TMR3_MODULE |\ref CLK_CLKSEL1_TMR3SEL_HIRC | x |
+ * |\ref CLKO_MODULE |\ref CLK_CLKSEL1_CLKOSEL_HXT | x |
+ * |\ref CLKO_MODULE |\ref CLK_CLKSEL1_CLKOSEL_LXT | x |
+ * |\ref CLKO_MODULE |\ref CLK_CLKSEL1_CLKOSEL_HCLK | x |
+ * |\ref CLKO_MODULE |\ref CLK_CLKSEL1_CLKOSEL_HIRC | x |
+ * |\ref SPI0_MODULE |\ref CLK_CLKSEL2_SPI0SEL_HXT | x |
+ * |\ref SPI0_MODULE |\ref CLK_CLKSEL2_SPI0SEL_PLL | x |
+ * |\ref SPI0_MODULE |\ref CLK_CLKSEL2_SPI0SEL_PCLK0 | x |
+ * |\ref SPI0_MODULE |\ref CLK_CLKSEL2_SPI0SEL_HIRC | x |
+ * |\ref SPI1_MODULE |\ref CLK_CLKSEL2_SPI1SEL_HXT | x |
+ * |\ref SPI1_MODULE |\ref CLK_CLKSEL2_SPI1SEL_PLL | x |
+ * |\ref SPI1_MODULE |\ref CLK_CLKSEL2_SPI1SEL_PCLK1 | x |
+ * |\ref SPI1_MODULE |\ref CLK_CLKSEL2_SPI1SEL_HIRC | x |
+ * |\ref SPI2_MODULE |\ref CLK_CLKSEL2_SPI2SEL_HXT | x |
+ * |\ref SPI2_MODULE |\ref CLK_CLKSEL2_SPI2SEL_PLL | x |
+ * |\ref SPI2_MODULE |\ref CLK_CLKSEL2_SPI2SEL_PCLK0 | x |
+ * |\ref SPI2_MODULE |\ref CLK_CLKSEL2_SPI2SEL_HIRC | x |
+ * |\ref UART0_MODULE |\ref CLK_CLKSEL1_UARTSEL_HXT |\ref CLK_CLKDIV0_UART(x) |
+ * |\ref UART0_MODULE |\ref CLK_CLKSEL1_UARTSEL_PLL |\ref CLK_CLKDIV0_UART(x) |
+ * |\ref UART0_MODULE |\ref CLK_CLKSEL1_UARTSEL_LXT |\ref CLK_CLKDIV0_UART(x) |
+ * |\ref UART0_MODULE |\ref CLK_CLKSEL1_UARTSEL_HIRC |\ref CLK_CLKDIV0_UART(x) |
+ * |\ref UART1_MODULE |\ref CLK_CLKSEL1_UARTSEL_HXT |\ref CLK_CLKDIV0_UART(x) |
+ * |\ref UART1_MODULE |\ref CLK_CLKSEL1_UARTSEL_PLL |\ref CLK_CLKDIV0_UART(x) |
+ * |\ref UART1_MODULE |\ref CLK_CLKSEL1_UARTSEL_LXT |\ref CLK_CLKDIV0_UART(x) |
+ * |\ref UART1_MODULE |\ref CLK_CLKSEL1_UARTSEL_HIRC |\ref CLK_CLKDIV0_UART(x) |
+ * |\ref UART2_MODULE |\ref CLK_CLKSEL1_UARTSEL_HXT |\ref CLK_CLKDIV0_UART(x) |
+ * |\ref UART2_MODULE |\ref CLK_CLKSEL1_UARTSEL_PLL |\ref CLK_CLKDIV0_UART(x) |
+ * |\ref UART2_MODULE |\ref CLK_CLKSEL1_UARTSEL_LXT |\ref CLK_CLKDIV0_UART(x) |
+ * |\ref UART2_MODULE |\ref CLK_CLKSEL1_UARTSEL_HIRC |\ref CLK_CLKDIV0_UART(x) |
+ * |\ref UART3_MODULE |\ref CLK_CLKSEL1_UARTSEL_HXT |\ref CLK_CLKDIV0_UART(x) |
+ * |\ref UART3_MODULE |\ref CLK_CLKSEL1_UARTSEL_LXT |\ref CLK_CLKDIV0_UART(x) |
+ * |\ref UART3_MODULE |\ref CLK_CLKSEL1_UARTSEL_PLL |\ref CLK_CLKDIV0_UART(x) |
+ * |\ref UART3_MODULE |\ref CLK_CLKSEL1_UARTSEL_HIRC |\ref CLK_CLKDIV0_UART(x) |
+ * |\ref USBH_MODULE | x |\ref CLK_CLKDIV0_USB(x) |
+ * |\ref USBD_MODULE | x |\ref CLK_CLKDIV0_USB(x) |
+ * |\ref OTG_MODULE | x |\ref CLK_CLKDIV0_USB(x) |
+ * |\ref EADC_MODULE | x |\ref CLK_CLKDIV0_EADC(x) |
+ * |\ref SC0_MODULE |\ref CLK_CLKSEL3_SC0SEL_HXT |\ref CLK_CLKDIV1_SC0(x) |
+ * |\ref SC0_MODULE |\ref CLK_CLKSEL3_SC0SEL_PLL |\ref CLK_CLKDIV1_SC0(x) |
+ * |\ref SC0_MODULE |\ref CLK_CLKSEL3_SC0SEL_PCLK0 |\ref CLK_CLKDIV1_SC0(x) |
+ * |\ref SC0_MODULE |\ref CLK_CLKSEL3_SC0SEL_HIRC |\ref CLK_CLKDIV1_SC0(x) |
+ * |\ref PWM0_MODULE |\ref CLK_CLKSEL2_PWM0SEL_PLL | x |
+ * |\ref PWM0_MODULE |\ref CLK_CLKSEL2_PWM0SEL_PCLK0 | x |
+ * |\ref PWM1_MODULE |\ref CLK_CLKSEL2_PWM1SEL_PLL | x |
+ * |\ref PWM1_MODULE |\ref CLK_CLKSEL2_PWM1SEL_PCLK1 | x |
+ * |\ref WWDT_MODULE |\ref CLK_CLKSEL1_WWDTSEL_PCLK0_DIV2048 | x |
+ * |\ref WWDT_MODULE |\ref CLK_CLKSEL1_WWDTSEL_LIRC | x |
+ */
+void CLK_SetModuleClock(uint32_t u32ModuleIdx, uint32_t u32ClkSrc, uint32_t u32ClkDiv)
+{
+ uint32_t u32sel = 0, u32div = 0;
+
+ if(MODULE_CLKDIV_Msk(u32ModuleIdx) != MODULE_NoMsk)
+ {
+ /* Get clock divider control register address */
+ u32div = (uint32_t)&CLK->CLKDIV0 + ((MODULE_CLKDIV(u32ModuleIdx)) * 4);
+ /* Apply new divider */
+ M32(u32div) = (M32(u32div) & (~(MODULE_CLKDIV_Msk(u32ModuleIdx) << MODULE_CLKDIV_Pos(u32ModuleIdx)))) | u32ClkDiv;
+ }
+
+ if(MODULE_CLKSEL_Msk(u32ModuleIdx) != MODULE_NoMsk)
+ {
+ /* Get clock select control register address */
+ u32sel = (uint32_t)&CLK->CLKSEL0 + ((MODULE_CLKSEL(u32ModuleIdx)) * 4);
+ /* Set new clock selection setting */
+ M32(u32sel) = (M32(u32sel) & (~(MODULE_CLKSEL_Msk(u32ModuleIdx) << MODULE_CLKSEL_Pos(u32ModuleIdx)))) | u32ClkSrc;
+ }
+}
+
+
+/**
+ * @brief Set SysTick clock source
+ * @param[in] u32ClkSrc is module clock source. Including:
+ * - \ref CLK_CLKSEL0_STCLKSEL_HXT
+ * - \ref CLK_CLKSEL0_STCLKSEL_LXT
+ * - \ref CLK_CLKSEL0_STCLKSEL_HXT_DIV2
+ * - \ref CLK_CLKSEL0_STCLKSEL_HCLK_DIV2
+ * - \ref CLK_CLKSEL0_STCLKSEL_HIRC_DIV2
+ * @return None
+ * @details This function set SysTick clock source. \n
+ * The register write-protection function should be disabled before using this function.
+ */
+void CLK_SetSysTickClockSrc(uint32_t u32ClkSrc)
+{
+ CLK->CLKSEL0 = (CLK->CLKSEL0 & ~CLK_CLKSEL0_STCLKSEL_Msk) | u32ClkSrc;
+
+}
+
+/**
+ * @brief Enable clock source
+ * @param[in] u32ClkMask is clock source mask. Including :
+ * - \ref CLK_PWRCTL_HXTEN_Msk
+ * - \ref CLK_PWRCTL_LXTEN_Msk
+ * - \ref CLK_PWRCTL_HIRCEN_Msk
+ * - \ref CLK_PWRCTL_LIRCEN_Msk
+ * @return None
+ * @details This function enable clock source. \n
+ * The register write-protection function should be disabled before using this function.
+ */
+void CLK_EnableXtalRC(uint32_t u32ClkMask)
+{
+ CLK->PWRCTL |= u32ClkMask;
+}
+
+/**
+ * @brief Disable clock source
+ * @param[in] u32ClkMask is clock source mask. Including :
+ * - \ref CLK_PWRCTL_HXTEN_Msk
+ * - \ref CLK_PWRCTL_LXTEN_Msk
+ * - \ref CLK_PWRCTL_HIRCEN_Msk
+ * - \ref CLK_PWRCTL_LIRCEN_Msk
+ * @return None
+ * @details This function disable clock source. \n
+ * The register write-protection function should be disabled before using this function.
+ */
+void CLK_DisableXtalRC(uint32_t u32ClkMask)
+{
+ CLK->PWRCTL &= ~u32ClkMask;
+}
+
+/**
+ * @brief Enable module clock
+ * @param[in] u32ModuleIdx is module index. Including :
+ * - \ref PDMA_MODULE
+ * - \ref ISP_MODULE
+ * - \ref EBI_MODULE
+ * - \ref USBH_MODULE
+ * - \ref CRC_MODULE
+ * - \ref WDT_MODULE
+ * - \ref WWDT_MODULE
+ * - \ref RTC_MODULE
+ * - \ref TMR0_MODULE
+ * - \ref TMR1_MODULE
+ * - \ref TMR2_MODULE
+ * - \ref TMR3_MODULE
+ * - \ref CLKO_MODULE
+ * - \ref ACMP01_MODULE
+ * - \ref I2C0_MODULE
+ * - \ref I2C1_MODULE
+ * - \ref SPI0_MODULE
+ * - \ref SPI1_MODULE
+ * - \ref SPI2_MODULE
+ * - \ref UART0_MODULE
+ * - \ref UART1_MODULE
+ * - \ref UART2_MODULE
+ * - \ref UART3_MODULE
+ * - \ref CAN0_MODULE
+ * - \ref OTG_MODULE
+ * - \ref USBD_MODULE
+ * - \ref EADC_MODULE
+ * - \ref SC0_MODULE
+ * - \ref DAC_MODULE
+ * - \ref PWM0_MODULE
+ * - \ref PWM1_MODULE
+ * - \ref TK_MODULE
+ * @return None
+ * @details This function is used to enable module clock.
+ */
+void CLK_EnableModuleClock(uint32_t u32ModuleIdx)
+{
+ *(volatile uint32_t *)((uint32_t)&CLK->AHBCLK + (MODULE_APBCLK(u32ModuleIdx) * 4)) |= 1 << MODULE_IP_EN_Pos(u32ModuleIdx);
+}
+
+/**
+ * @brief Disable module clock
+ * @param[in] u32ModuleIdx is module index. Including :
+ * - \ref PDMA_MODULE
+ * - \ref ISP_MODULE
+ * - \ref EBI_MODULE
+ * - \ref USBH_MODULE
+ * - \ref CRC_MODULE
+ * - \ref WDT_MODULE
+ * - \ref WWDT_MODULE
+ * - \ref RTC_MODULE
+ * - \ref TMR0_MODULE
+ * - \ref TMR1_MODULE
+ * - \ref TMR2_MODULE
+ * - \ref TMR3_MODULE
+ * - \ref CLKO_MODULE
+ * - \ref ACMP01_MODULE
+ * - \ref I2C0_MODULE
+ * - \ref I2C1_MODULE
+ * - \ref SPI0_MODULE
+ * - \ref SPI1_MODULE
+ * - \ref SPI2_MODULE
+ * - \ref UART0_MODULE
+ * - \ref UART1_MODULE
+ * - \ref UART2_MODULE
+ * - \ref UART3_MODULE
+ * - \ref CAN0_MODULE
+ * - \ref OTG_MODULE
+ * - \ref USBD_MODULE
+ * - \ref EADC_MODULE
+ * - \ref SC0_MODULE
+ * - \ref DAC_MODULE
+ * - \ref PWM0_MODULE
+ * - \ref PWM1_MODULE
+ * - \ref TK_MODULE
+ * @return None
+ * @details This function is used to disable module clock.
+ */
+void CLK_DisableModuleClock(uint32_t u32ModuleIdx)
+{
+ *(volatile uint32_t *)((uint32_t)&CLK->AHBCLK + (MODULE_APBCLK(u32ModuleIdx) * 4)) &= ~(1 << MODULE_IP_EN_Pos(u32ModuleIdx));
+}
+
+
+/**
+ * @brief Set PLL frequency
+ * @param[in] u32PllClkSrc is PLL clock source. Including :
+ * - \ref CLK_PLLCTL_PLLSRC_HXT
+ * - \ref CLK_PLLCTL_PLLSRC_HIRC
+ * @param[in] u32PllFreq is PLL frequency.
+ * @return PLL frequency
+ * @details This function is used to configure PLLCTL register to set specified PLL frequency. \n
+ * The register write-protection function should be disabled before using this function.
+ */
+uint32_t CLK_EnablePLL(uint32_t u32PllClkSrc, uint32_t u32PllFreq)
+{
+ uint32_t u32PllSrcClk, u32NR, u32NF, u32NO, u32CLK_SRC;
+ uint32_t u32Tmp, u32Tmp2, u32Tmp3, u32Min, u32MinNF, u32MinNR;
+
+ /* Disable PLL first to avoid unstable when setting PLL */
+ CLK_DisablePLL();
+
+ /* PLL source clock is from HXT */
+ if(u32PllClkSrc == CLK_PLLCTL_PLLSRC_HXT)
+ {
+ /* Enable HXT clock */
+ CLK->PWRCTL |= CLK_PWRCTL_HXTEN_Msk;
+
+ /* Wait for HXT clock ready */
+ CLK_WaitClockReady(CLK_STATUS_HXTSTB_Msk);
+
+ /* Select PLL source clock from HXT */
+ u32CLK_SRC = CLK_PLLCTL_PLLSRC_HXT;
+ u32PllSrcClk = __HXT;
+
+ /* u32NR start from 2 */
+ u32NR = 2;
+ }
+
+ /* PLL source clock is from HIRC */
+ else
+ {
+ /* Enable HIRC clock */
+ CLK->PWRCTL |= CLK_PWRCTL_HIRCEN_Msk;
+
+ /* Wait for HIRC clock ready */
+ CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk);
+
+ /* Select PLL source clock from HIRC */
+ u32CLK_SRC = CLK_PLLCTL_PLLSRC_HIRC;
+ u32PllSrcClk = __HIRC;
+
+ /* u32NR start from 4 when FIN = 22.1184MHz to avoid calculation overflow */
+ u32NR = 4;
+ }
+
+ /* Select "NO" according to request frequency */
+ if((u32PllFreq <= FREQ_500MHZ) && (u32PllFreq > FREQ_250MHZ))
+ {
+ u32NO = 0;
+ }
+ else if((u32PllFreq <= FREQ_250MHZ) && (u32PllFreq > FREQ_125MHZ))
+ {
+ u32NO = 1;
+ u32PllFreq = u32PllFreq << 1;
+ }
+ else if((u32PllFreq <= FREQ_125MHZ) && (u32PllFreq >= FREQ_50MHZ))
+ {
+ u32NO = 3;
+ u32PllFreq = u32PllFreq << 2;
+ }
+ else
+ {
+ /* Wrong frequency request. Just return default setting. */
+ goto lexit;
+ }
+
+ /* Find best solution */
+ u32Min = (uint32_t) - 1;
+ u32MinNR = 0;
+ u32MinNF = 0;
+ for(; u32NR <= 33; u32NR++)
+ {
+ u32Tmp = u32PllSrcClk / u32NR;
+ if((u32Tmp > 1600000) && (u32Tmp < 16000000))
+ {
+ for(u32NF = 2; u32NF <= 513; u32NF++)
+ {
+ u32Tmp2 = u32Tmp * u32NF;
+ if((u32Tmp2 >= 200000000) && (u32Tmp2 <= 500000000))
+ {
+ u32Tmp3 = (u32Tmp2 > u32PllFreq) ? u32Tmp2 - u32PllFreq : u32PllFreq - u32Tmp2;
+ if(u32Tmp3 < u32Min)
+ {
+ u32Min = u32Tmp3;
+ u32MinNR = u32NR;
+ u32MinNF = u32NF;
+
+ /* Break when get good results */
+ if(u32Min == 0)
+ break;
+ }
+ }
+ }
+ }
+ }
+
+ /* Enable and apply new PLL setting. */
+ CLK->PLLCTL = u32CLK_SRC | (u32NO << 14) | ((u32MinNR - 2) << 9) | (u32MinNF - 2);
+
+ /* Wait for PLL clock stable */
+ CLK_WaitClockReady(CLK_STATUS_PLLSTB_Msk);
+
+ /* Return actual PLL output clock frequency */
+ return u32PllSrcClk / ((u32NO + 1) * u32MinNR) * u32MinNF;
+
+lexit:
+
+ /* Apply default PLL setting and return */
+ if(u32PllClkSrc == CLK_PLLCTL_PLLSRC_HXT)
+ CLK->PLLCTL = CLK_PLLCTL_72MHz_HXT; /* 72MHz */
+ else
+ CLK->PLLCTL = CLK_PLLCTL_72MHz_HIRC; /* 71.8848MHz */
+
+ /* Wait for PLL clock stable */
+ CLK_WaitClockReady(CLK_STATUS_PLLSTB_Msk);
+
+ return CLK_GetPLLClockFreq();
+
+}
+
+/**
+ * @brief Disable PLL
+ * @param None
+ * @return None
+ * @details This function set PLL in Power-down mode. \n
+ * The register write-protection function should be disabled before using this function.
+ */
+void CLK_DisablePLL(void)
+{
+ CLK->PLLCTL |= CLK_PLLCTL_PD_Msk;
+}
+
+
+/**
+ * @brief This function check selected clock source status
+ * @param[in] u32ClkMask is selected clock source. Including :
+ * - \ref CLK_STATUS_HXTSTB_Msk
+ * - \ref CLK_STATUS_LXTSTB_Msk
+ * - \ref CLK_STATUS_HIRCSTB_Msk
+ * - \ref CLK_STATUS_LIRCSTB_Msk
+ * - \ref CLK_STATUS_PLLSTB_Msk
+ * @retval 0 clock is not stable
+ * @retval 1 clock is stable
+ * @details To wait for clock ready by specified clock source stable flag or timeout (~300ms)
+ */
+uint32_t CLK_WaitClockReady(uint32_t u32ClkMask)
+{
+ int32_t i32TimeOutCnt = 2160000;
+
+ while((CLK->STATUS & u32ClkMask) != u32ClkMask)
+ {
+ if(i32TimeOutCnt-- <= 0)
+ return 0;
+ }
+
+ return 1;
+}
+
+/**
+ * @brief Enable System Tick counter
+ * @param[in] u32ClkSrc is System Tick clock source. Including:
+ * - \ref CLK_CLKSEL0_STCLKSEL_HXT
+ * - \ref CLK_CLKSEL0_STCLKSEL_LXT
+ * - \ref CLK_CLKSEL0_STCLKSEL_HXT_DIV2
+ * - \ref CLK_CLKSEL0_STCLKSEL_HCLK_DIV2
+ * - \ref CLK_CLKSEL0_STCLKSEL_HIRC_DIV2
+ * - \ref CLK_CLKSEL0_STCLKSEL_HCLK
+ * @param[in] u32Count is System Tick reload value. It could be 0~0xFFFFFF.
+ * @return None
+ * @details This function set System Tick clock source, reload value, enable System Tick counter and interrupt. \n
+ * The register write-protection function should be disabled before using this function.
+ */
+void CLK_EnableSysTick(uint32_t u32ClkSrc, uint32_t u32Count)
+{
+ /* Set System Tick counter disabled */
+ SysTick->CTRL = 0;
+
+ /* Set System Tick clock source */
+ if( u32ClkSrc == CLK_CLKSEL0_STCLKSEL_HCLK )
+ SysTick->CTRL |= SysTick_CTRL_CLKSOURCE_Msk;
+ else
+ CLK->CLKSEL0 = (CLK->CLKSEL0 & ~CLK_CLKSEL0_STCLKSEL_Msk) | u32ClkSrc;
+
+ /* Set System Tick reload value */
+ SysTick->LOAD = u32Count;
+
+ /* Clear System Tick current value and counter flag */
+ SysTick->VAL = 0;
+
+ /* Set System Tick interrupt enabled and counter enabled */
+ SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk;
+}
+
+/**
+ * @brief Disable System Tick counter
+ * @param None
+ * @return None
+ * @details This function disable System Tick counter.
+ */
+void CLK_DisableSysTick(void)
+{
+ /* Set System Tick counter disabled */
+ SysTick->CTRL = 0;
+}
+
+
+/*@}*/ /* end of group CLK_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group CLK_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+/*** (C) COPYRIGHT 2014~2015 Nuvoton Technology Corp. ***/
diff --git a/bsp/nuvoton_m451/Libraries/StdDriver/src/crc.c b/bsp/nuvoton_m451/Libraries/StdDriver/src/crc.c
new file mode 100644
index 0000000000000000000000000000000000000000..346a6a5991f1172866822daeb5549d6268b68443
--- /dev/null
+++ b/bsp/nuvoton_m451/Libraries/StdDriver/src/crc.c
@@ -0,0 +1,93 @@
+/**************************************************************************//**
+ * @file crc.c
+ * @version V3.00
+ * $Revision: 7 $
+ * $Date: 15/08/11 10:26a $
+ * @brief M451 series CRC driver source file
+ *
+ * @note
+ * Copyright (C) 2013~2015 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#include "M451Series.h"
+
+
+/** @addtogroup Standard_Driver Standard Driver
+ @{
+*/
+
+/** @addtogroup CRC_Driver CRC Driver
+ @{
+*/
+
+/** @addtogroup CRC_EXPORTED_FUNCTIONS CRC Exported Functions
+ @{
+*/
+
+/**
+ * @brief CRC Open
+ *
+ * @param[in] u32Mode CRC operation polynomial mode. Valid values are:
+ * - \ref CRC_CCITT
+ * - \ref CRC_8
+ * - \ref CRC_16
+ * - \ref CRC_32
+ * @param[in] u32Attribute CRC operation data attribute. Valid values are combined with:
+ * - \ref CRC_CHECKSUM_COM
+ * - \ref CRC_CHECKSUM_RVS
+ * - \ref CRC_WDATA_COM
+ * - \ref CRC_WDATA_RVS
+ * @param[in] u32Seed Seed value.
+ * @param[in] u32DataLen CPU Write Data Length. Valid values are:
+ * - \ref CRC_CPU_WDATA_8
+ * - \ref CRC_CPU_WDATA_16
+ * - \ref CRC_CPU_WDATA_32
+ *
+ * @return None
+ *
+ * @details This function will enable the CRC controller by specify CRC operation mode, attribute, initial seed and write data length. \n
+ * After that, user can start to perform CRC calculate by calling CRC_WRITE_DATA macro or CRC_DAT register directly.
+ */
+void CRC_Open(uint32_t u32Mode, uint32_t u32Attribute, uint32_t u32Seed, uint32_t u32DataLen)
+{
+ CRC->SEED = u32Seed;
+ CRC->CTL = u32Mode | u32Attribute | u32DataLen | CRC_CTL_CRCEN_Msk;
+
+ /* Setting CRCRST bit will reload the initial seed value(CRC_SEED register) to CRC controller */
+ CRC->CTL |= CRC_CTL_CRCRST_Msk;
+}
+
+/**
+ * @brief Get CRC Checksum
+ *
+ * @param[in] None
+ *
+ * @return Checksum Result
+ *
+ * @details This macro gets the CRC checksum result by current CRC polynomial mode.
+ */
+uint32_t CRC_GetChecksum(void)
+{
+ switch(CRC->CTL & CRC_CTL_CRCMODE_Msk)
+ {
+ case CRC_CCITT:
+ case CRC_16:
+ return (CRC->CHECKSUM & 0xFFFF);
+
+ case CRC_32:
+ return (CRC->CHECKSUM);
+
+ case CRC_8:
+ return (CRC->CHECKSUM & 0xFF);
+
+ default:
+ return 0;
+ }
+}
+
+/*@}*/ /* end of group CRC_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group CRC_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+/*** (C) COPYRIGHT 2013~2015 Nuvoton Technology Corp. ***/
diff --git a/bsp/nuvoton_m451/Libraries/StdDriver/src/dac.c b/bsp/nuvoton_m451/Libraries/StdDriver/src/dac.c
new file mode 100644
index 0000000000000000000000000000000000000000..4baffbd8012fc1dcfdcb3cca1b4d7312ba079ea8
--- /dev/null
+++ b/bsp/nuvoton_m451/Libraries/StdDriver/src/dac.c
@@ -0,0 +1,94 @@
+/**************************************************************************//**
+ * @file dac.c
+ * @version V2.00
+ * $Revision: 8 $
+ * $Date: 15/08/11 10:26a $
+ * @brief M451 series DAC driver source file
+ *
+ * @note
+ * Copyright (C) 2014~2015 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#include "M451Series.h"
+
+/** @addtogroup Standard_Driver Standard Driver
+ @{
+*/
+
+/** @addtogroup DAC_Driver DAC Driver
+ @{
+*/
+
+/** @addtogroup DAC_EXPORTED_FUNCTIONS DAC Exported Functions
+ @{
+*/
+
+/**
+ * @brief This function make DAC module be ready to convert.
+ * @param[in] dac Base address of DAC module.
+ * @param[in] u32Ch Not used in M451 Series DAC.
+ * @param[in] u32TrgSrc Decides the trigger source. Valid values are:
+ * - \ref DAC_WRITE_DAT_TRIGGER :Write DAC_DAT trigger
+ * - \ref DAC_SOFTWARE_TRIGGER :Software trigger
+ * - \ref DAC_LOW_LEVEL_TRIGGER :STDAC pin low level trigger
+ * - \ref DAC_HIGH_LEVEL_TRIGGER :STDAC pin high level trigger
+ * - \ref DAC_FALLING_EDGE_TRIGGER :STDAC pin falling edge trigger
+ * - \ref DAC_RISING_EDGE_TRIGGER :STDAC pin rising edge trigger
+ * - \ref DAC_TIMER0_TRIGGER :Timer 0 trigger
+ * - \ref DAC_TIMER1_TRIGGER :Timer 1 trigger
+ * - \ref DAC_TIMER2_TRIGGER :Timer 2 trigger
+ * - \ref DAC_TIMER3_TRIGGER :Timer 3 trigger
+ * - \ref DAC_PWM0_TRIGGER :PWM0 trigger
+ * - \ref DAC_PWM1_TRIGGER :PWM1 trigger
+ * @return None
+ * @details The DAC conversion can be started by writing DAC_DAT, software trigger or hardware trigger.
+ * When TRGEN (DAC_CTL[4]) is 0, the data conversion is started by writing DAC_DAT register.
+ * When TRGEN (DAC_CTL[4]) is 1, the data conversion is started by SWTRG (DAC_SWTRG[0]) is set to 1,
+ * external STDAC pin, timer event, or PWM timer event.
+ */
+void DAC_Open(DAC_T *dac,
+ uint32_t u32Ch,
+ uint32_t u32TrgSrc)
+{
+ dac->CTL &= ~(DAC_CTL_ETRGSEL_Msk | DAC_CTL_TRGSEL_Msk | DAC_CTL_TRGEN_Msk);
+
+ dac->CTL |= (u32TrgSrc | DAC_CTL_DACEN_Msk);
+}
+
+/**
+ * @brief Disable DAC analog power.
+ * @param[in] dac Base address of DAC module.
+ * @param[in] u32Ch Not used in M451 Series DAC.
+ * @return None
+ * @details Disable DAC analog power for saving power consumption.
+ */
+void DAC_Close(DAC_T *dac, uint32_t u32Ch)
+{
+ dac->CTL &= (~DAC_CTL_DACEN_Msk);
+}
+
+/**
+ * @brief Set delay time for DAC to become stable.
+ * @param[in] dac Base address of DAC module.
+ * @param[in] u32Delay Decides the DAC conversion settling time, the range is from 0~(1023/PCLK*1000000) micro seconds.
+ * @return Real DAC conversion settling time (micro second).
+ * @details For example, DAC controller clock speed is 72MHz and DAC conversion setting time is 1 us, SETTLET (DAC_TCTL[9:0]) value must be greater than 0x48.
+ * @note User needs to write appropriate value to meet DAC conversion settling time base on PCLK (APB clock) speed.
+ */
+float DAC_SetDelayTime(DAC_T *dac, uint32_t u32Delay)
+{
+ SystemCoreClockUpdate();
+
+ dac->TCTL = ((SystemCoreClock * u32Delay / 1000000) & 0x3FF);
+
+ return ((dac->TCTL) * 1000000 / SystemCoreClock);
+}
+
+
+
+/*@}*/ /* end of group DAC_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group DAC_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+/*** (C) COPYRIGHT 2014~2015 Nuvoton Technology Corp. ***/
diff --git a/bsp/nuvoton_m451/Libraries/StdDriver/src/eadc.c b/bsp/nuvoton_m451/Libraries/StdDriver/src/eadc.c
new file mode 100644
index 0000000000000000000000000000000000000000..741e51dcc0fa3106c4a49c618d8d728a1ee3da1a
--- /dev/null
+++ b/bsp/nuvoton_m451/Libraries/StdDriver/src/eadc.c
@@ -0,0 +1,159 @@
+/**************************************************************************//**
+ * @file eadc.c
+ * @version V2.00
+ * $Revision: 8 $
+ * $Date: 15/08/11 10:26a $
+ * @brief M451 series EADC driver source file
+ *
+ * @note
+ * Copyright (C) 2014~2015 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#include "M451Series.h"
+
+/** @addtogroup Standard_Driver Standard Driver
+ @{
+*/
+
+/** @addtogroup EADC_Driver EADC Driver
+ @{
+*/
+
+/** @addtogroup EADC_EXPORTED_FUNCTIONS EADC Exported Functions
+ @{
+*/
+
+/**
+ * @brief This function make EADC_module be ready to convert.
+ * @param[in] eadc The pointer of the specified EADC module.
+ * @param[in] u32InputMode Decides the input mode.
+ * - \ref EADC_CTL_DIFFEN_SINGLE_END :Single end input mode.
+ * - \ref EADC_CTL_DIFFEN_DIFFERENTIAL :Differential input type.
+ * @return None
+ * @details This function is used to set analog input mode and enable A/D Converter.
+ * Before starting A/D conversion function, ADCEN bit (EADC_CTL[0]) should be set to 1.
+ * @note
+ */
+void EADC_Open(EADC_T *eadc, uint32_t u32InputMode)
+{
+ eadc->CTL &= (~EADC_CTL_DIFFEN_Msk);
+
+ eadc->CTL |= (u32InputMode | EADC_CTL_ADCEN_Msk);
+}
+
+/**
+ * @brief Disable EADC_module.
+ * @param[in] eadc The pointer of the specified EADC module..
+ * @return None
+ * @details Clear ADCEN bit (EADC_CTL[0]) to disable A/D converter analog circuit power consumption.
+ */
+void EADC_Close(EADC_T *eadc)
+{
+ eadc->CTL &= ~EADC_CTL_ADCEN_Msk;
+}
+
+/**
+ * @brief Configure the sample control logic module.
+ * @param[in] eadc The pointer of the specified EADC module.
+ * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 15.
+ * @param[in] u32TriggerSrc Decides the trigger source. Valid values are:
+ * - \ref EADC_SOFTWARE_TRIGGER : Disable trigger
+ * - \ref EADC_FALLING_EDGE_TRIGGER : STADC pin falling edge trigger
+ * - \ref EADC_RISING_EDGE_TRIGGER : STADC pin rising edge trigger
+ * - \ref EADC_FALLING_RISING_EDGE_TRIGGER : STADC pin both falling and rising edge trigger
+ * - \ref EADC_ADINT0_TRIGGER : ADC ADINT0 interrupt EOC pulse trigger
+ * - \ref EADC_ADINT1_TRIGGER : ADC ADINT1 interrupt EOC pulse trigger
+ * - \ref EADC_TIMER0_TRIGGER : Timer0 overflow pulse trigger
+ * - \ref EADC_TIMER1_TRIGGER : Timer1 overflow pulse trigger
+ * - \ref EADC_TIMER2_TRIGGER : Timer2 overflow pulse trigger
+ * - \ref EADC_TIMER3_TRIGGER : Timer3 overflow pulse trigger
+ * - \ref EADC_PWM0TG0_TRIGGER : PWM0TG0 trigger
+ * - \ref EADC_PWM0TG1_TRIGGER : PWM0TG1 trigger
+ * - \ref EADC_PWM0TG2_TRIGGER : PWM0TG2 trigger
+ * - \ref EADC_PWM0TG3_TRIGGER : PWM0TG3 trigger
+ * - \ref EADC_PWM0TG4_TRIGGER : PWM0TG4 trigger
+ * - \ref EADC_PWM0TG5_TRIGGER : PWM0TG5 trigger
+ * - \ref EADC_PWM1TG0_TRIGGER : PWM1TG0 trigger
+ * - \ref EADC_PWM1TG1_TRIGGER : PWM1TG1 trigger
+ * - \ref EADC_PWM1TG2_TRIGGER : PWM1TG2 trigger
+ * - \ref EADC_PWM1TG3_TRIGGER : PWM1TG3 trigger
+ * - \ref EADC_PWM1TG4_TRIGGER : PWM1TG4 trigger
+ * - \ref EADC_PWM1TG5_TRIGGER : PWM1TG5 trigger
+ * @param[in] u32Channel Specifies the sample module channel, valid value are from 0 to 15.
+ * @return None
+ * @details Each of ADC control logic modules 0~15 which is configurable for ADC converter channel EADC_CH0~15 and trigger source.
+ * sample module 16~18 is fixed for ADC channel 16, 17, 18 input sources as band-gap voltage, temperature sensor, and battery power (VBAT).
+ */
+void EADC_ConfigSampleModule(EADC_T *eadc, \
+ uint32_t u32ModuleNum, \
+ uint32_t u32TriggerSrc, \
+ uint32_t u32Channel)
+{
+ eadc->SCTL[u32ModuleNum] &= ~(EADC_SCTL_EXTFEN_Msk | EADC_SCTL_EXTREN_Msk | EADC_SCTL_TRGSEL_Msk | EADC_SCTL_CHSEL_Msk);
+ eadc->SCTL[u32ModuleNum] |= (u32TriggerSrc | u32Channel);
+}
+
+
+/**
+ * @brief Set trigger delay time.
+ * @param[in] eadc The pointer of the specified EADC module.
+ * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 15.
+ * @param[in] u32TriggerDelayTime Decides the trigger delay time, valid range are between 0~0xFF.
+ * @param[in] u32DelayClockDivider Decides the trigger delay clock divider. Valid values are:
+ * - \ref EADC_SCTL_TRGDLYDIV_DIVIDER_1 : Trigger delay clock frequency is ADC_CLK/1
+ * - \ref EADC_SCTL_TRGDLYDIV_DIVIDER_2 : Trigger delay clock frequency is ADC_CLK/2
+ * - \ref EADC_SCTL_TRGDLYDIV_DIVIDER_4 : Trigger delay clock frequency is ADC_CLK/4
+ * - \ref EADC_SCTL_TRGDLYDIV_DIVIDER_16 : Trigger delay clock frequency is ADC_CLK/16
+ * @return None
+ * @details User can configure the trigger delay time by setting TRGDLYCNT (EADC_SCTLn[15:8], n=0~15) and TRGDLYDIV (EADC_SCTLn[7:6], n=0~15).
+ * Trigger delay time = (u32TriggerDelayTime) x Trigger delay clock period.
+ */
+void EADC_SetTriggerDelayTime(EADC_T *eadc, \
+ uint32_t u32ModuleNum, \
+ uint32_t u32TriggerDelayTime, \
+ uint32_t u32DelayClockDivider)
+{
+ eadc->SCTL[u32ModuleNum] &= ~(EADC_SCTL_TRGDLYDIV_Msk | EADC_SCTL_TRGDLYCNT_Msk);
+ eadc->SCTL[u32ModuleNum] |= ((u32TriggerDelayTime << EADC_SCTL_TRGDLYCNT_Pos) | u32DelayClockDivider);
+}
+
+/**
+ * @brief Set ADC internal sample time.
+ * @param[in] eadc The pointer of the specified EADC module.
+ * @param[in] u32SampleTime Decides the internal sampling time, the range is from 1~8 ADC clock. Valid value are from 1 to 8.
+ * @return None
+ * @details When A/D operation at high ADC clock rate, the sampling time of analog input voltage may not enough
+ * if the analog channel has heavy loading to cause fully charge time is longer.
+ * User can set SMPTSEL (EADC_CTL[18:16]) to select the sampling cycle in ADC.
+ */
+void EADC_SetInternalSampleTime(EADC_T *eadc, uint32_t u32SampleTime)
+{
+ eadc->CTL &= ~EADC_CTL_SMPTSEL_Msk;
+
+ eadc->CTL |= (u32SampleTime - 1) << EADC_CTL_SMPTSEL_Pos;
+
+}
+
+/**
+ * @brief Set ADC extend sample time.
+ * @param[in] eadc The pointer of the specified EADC module.
+ * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 18.
+ * @param[in] u32ExtendSampleTime Decides the extend sampling time, the range is from 0~255 ADC clock. Valid value are from 0 to 0xFF.
+ * @return None
+ * @details When A/D converting at high conversion rate, the sampling time of analog input voltage may not enough if input channel loading is heavy,
+ * user can extend A/D sampling time after trigger source is coming to get enough sampling time.
+ */
+void EADC_SetExtendSampleTime(EADC_T *eadc, uint32_t u32ModuleNum, uint32_t u32ExtendSampleTime)
+{
+ eadc->SCTL[u32ModuleNum] &= ~EADC_SCTL_EXTSMPT_Msk;
+
+ eadc->SCTL[u32ModuleNum] |= (u32ExtendSampleTime << EADC_SCTL_EXTSMPT_Pos);
+
+}
+
+/*@}*/ /* end of group EADC_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group EADC_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+/*** (C) COPYRIGHT 2014~2015 Nuvoton Technology Corp. ***/
diff --git a/bsp/nuvoton_m451/Libraries/StdDriver/src/ebi.c b/bsp/nuvoton_m451/Libraries/StdDriver/src/ebi.c
new file mode 100644
index 0000000000000000000000000000000000000000..e4d7b7ca2f02bdb99ccf9c3afa929afc020b1c23
--- /dev/null
+++ b/bsp/nuvoton_m451/Libraries/StdDriver/src/ebi.c
@@ -0,0 +1,178 @@
+/**************************************************************************//**
+ * @file ebi.c
+ * @version V3.00
+ * $Revision: 9 $
+ * $Date: 15/08/11 10:26a $
+ * @brief M451 series EBI driver source file
+ *
+ * @note
+ * Copyright (C) 2013~2015 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#include "M451Series.h"
+
+
+/** @addtogroup Standard_Driver Standard Driver
+ @{
+*/
+
+/** @addtogroup EBI_Driver EBI Driver
+ @{
+*/
+
+/** @addtogroup EBI_EXPORTED_FUNCTIONS EBI Exported Functions
+ @{
+*/
+
+/**
+ * @brief Initialize EBI for specify Bank
+ *
+ * @param[in] u32Bank Bank number for EBI. Valid values are:
+ * - \ref EBI_BANK0
+ * - \ref EBI_BANK1
+ * @param[in] u32DataWidth Data bus width. Valid values are:
+ * - \ref EBI_BUSWIDTH_8BIT
+ * - \ref EBI_BUSWIDTH_16BIT
+ * @param[in] u32TimingClass Default timing configuration. Valid values are:
+ * - \ref EBI_TIMING_FASTEST
+ * - \ref EBI_TIMING_VERYFAST
+ * - \ref EBI_TIMING_FAST
+ * - \ref EBI_TIMING_NORMAL
+ * - \ref EBI_TIMING_SLOW
+ * - \ref EBI_TIMING_VERYSLOW
+ * - \ref EBI_TIMING_SLOWEST
+ * @param[in] u32BusMode Enable EBI separate mode. This parameter is current not used.
+ * @param[in] u32CSActiveLevel CS is active High/Low. Valid values are:
+ * - \ref EBI_CS_ACTIVE_HIGH
+ * - \ref EBI_CS_ACTIVE_LOW
+ *
+ * @return none
+ *
+ * @details This function is used to open specify EBI bank with different bus width, timing setting and \n
+ * active level of CS pin to access EBI device.
+ * @note Write Buffer Enable(WBUFEN) and Extend Time Of ALE(TALE) are only available in EBI bank0 control register.
+ */
+void EBI_Open(uint32_t u32Bank, uint32_t u32DataWidth, uint32_t u32TimingClass, uint32_t u32BusMode, uint32_t u32CSActiveLevel)
+{
+ volatile uint32_t *pu32EBICTL = (uint32_t *)((uint32_t)&EBI->CTL0 + (u32Bank * 0x10));
+ volatile uint32_t *pu32EBITCTL = (uint32_t *)((uint32_t)&EBI->TCTL0 + (u32Bank * 0x10));
+
+ if(u32DataWidth == EBI_BUSWIDTH_8BIT)
+ *pu32EBICTL &= ~EBI_CTL0_DW16_Msk;
+ else
+ *pu32EBICTL |= EBI_CTL0_DW16_Msk;
+
+ switch(u32TimingClass)
+ {
+ case EBI_TIMING_FASTEST:
+ *pu32EBICTL = (*pu32EBICTL & ~(EBI_CTL0_MCLKDIV_Msk | EBI_CTL0_TALE_Msk)) |
+ (EBI_MCLKDIV_1 << EBI_CTL0_MCLKDIV_Pos) |
+ (u32CSActiveLevel << EBI_CTL0_CSPOLINV_Pos) | EBI_CTL0_EN_Msk;
+ *pu32EBITCTL = 0x0;
+ break;
+
+ case EBI_TIMING_VERYFAST:
+ *pu32EBICTL = (*pu32EBICTL & ~(EBI_CTL0_MCLKDIV_Msk | EBI_CTL0_TALE_Msk)) |
+ (EBI_MCLKDIV_1 << EBI_CTL0_MCLKDIV_Pos) |
+ (u32CSActiveLevel << EBI_CTL0_CSPOLINV_Pos) | EBI_CTL0_EN_Msk |
+ (0x3 << EBI_CTL0_TALE_Pos) ;
+ *pu32EBITCTL = 0x03003318;
+ break;
+
+ case EBI_TIMING_FAST:
+ *pu32EBICTL = (*pu32EBICTL & ~(EBI_CTL0_MCLKDIV_Msk | EBI_CTL0_TALE_Msk)) |
+ (EBI_MCLKDIV_2 << EBI_CTL0_MCLKDIV_Pos) |
+ (u32CSActiveLevel << EBI_CTL0_CSPOLINV_Pos) | EBI_CTL0_EN_Msk;
+ *pu32EBITCTL = 0x0;
+ break;
+
+ case EBI_TIMING_NORMAL:
+ *pu32EBICTL = (*pu32EBICTL & ~(EBI_CTL0_MCLKDIV_Msk | EBI_CTL0_TALE_Msk)) |
+ (EBI_MCLKDIV_2 << EBI_CTL0_MCLKDIV_Pos) |
+ (u32CSActiveLevel << EBI_CTL0_CSPOLINV_Pos) | EBI_CTL0_EN_Msk |
+ (0x3 << EBI_CTL0_TALE_Pos) ;
+ *pu32EBITCTL = 0x03003318;
+ break;
+
+ case EBI_TIMING_SLOW:
+ *pu32EBICTL = (*pu32EBICTL & ~(EBI_CTL0_MCLKDIV_Msk | EBI_CTL0_TALE_Msk)) |
+ (EBI_MCLKDIV_2 << EBI_CTL0_MCLKDIV_Pos) |
+ (u32CSActiveLevel << EBI_CTL0_CSPOLINV_Pos) | EBI_CTL0_EN_Msk |
+ (0x7 << EBI_CTL0_TALE_Pos) ;
+ *pu32EBITCTL = 0x07007738;
+ break;
+
+ case EBI_TIMING_VERYSLOW:
+ *pu32EBICTL = (*pu32EBICTL & ~(EBI_CTL0_MCLKDIV_Msk | EBI_CTL0_TALE_Msk)) |
+ (EBI_MCLKDIV_4 << EBI_CTL0_MCLKDIV_Pos) |
+ (u32CSActiveLevel << EBI_CTL0_CSPOLINV_Pos) | EBI_CTL0_EN_Msk |
+ (0x7 << EBI_CTL0_TALE_Pos) ;
+ *pu32EBITCTL = 0x07007738;
+ break;
+
+ case EBI_TIMING_SLOWEST:
+ *pu32EBICTL = (*pu32EBICTL & ~(EBI_CTL0_MCLKDIV_Msk | EBI_CTL0_TALE_Msk)) |
+ (EBI_MCLKDIV_8 << EBI_CTL0_MCLKDIV_Pos) |
+ (u32CSActiveLevel << EBI_CTL0_CSPOLINV_Pos) | EBI_CTL0_EN_Msk |
+ (0x7 << EBI_CTL0_TALE_Pos) ;
+ *pu32EBITCTL = 0x07007738;
+ break;
+
+ default:
+ *pu32EBICTL &= ~EBI_CTL0_EN_Msk;
+ break;
+ }
+}
+
+/**
+ * @brief Disable EBI on specify Bank
+ *
+ * @param[in] u32Bank Bank number for EBI. Valid values are:
+ * - \ref EBI_BANK0
+ * - \ref EBI_BANK1
+ *
+ * @return none
+ *
+ * @details This function is used to close specify EBI function.
+ */
+void EBI_Close(uint32_t u32Bank)
+{
+ volatile uint32_t *pu32EBICTL = (uint32_t *)((uint32_t)&EBI->CTL0 + (u32Bank * 0x10));
+
+ *pu32EBICTL &= ~EBI_CTL0_EN_Msk;
+}
+
+/**
+ * @brief Set EBI Bus Timing for specify Bank
+ *
+ * @param[in] u32Bank Bank number for EBI. Valid values are:
+ * - \ref EBI_BANK0
+ * - \ref EBI_BANK1
+ * @param[in] u32TimingConfig Configure EBI timing settings, includes TACC, TAHD, W2X and R2R setting.
+ * @param[in] u32MclkDiv Divider for MCLK. Valid values are:
+ * - \ref EBI_MCLKDIV_1
+ * - \ref EBI_MCLKDIV_2
+ * - \ref EBI_MCLKDIV_4
+ * - \ref EBI_MCLKDIV_8
+ * - \ref EBI_MCLKDIV_16
+ * - \ref EBI_MCLKDIV_32
+ *
+ * @return none
+ *
+ * @details This function is used to configure specify EBI bus timing for access EBI device.
+ */
+void EBI_SetBusTiming(uint32_t u32Bank, uint32_t u32TimingConfig, uint32_t u32MclkDiv)
+{
+ volatile uint32_t *pu32EBICTL = (uint32_t *)((uint32_t)&EBI->CTL0 + (u32Bank * 0x10));
+ volatile uint32_t *pu32EBITCTL = (uint32_t *)((uint32_t)&EBI->TCTL0 + (u32Bank * 0x10));
+
+ *pu32EBICTL = (*pu32EBICTL & ~EBI_CTL0_MCLKDIV_Msk) | (u32MclkDiv << EBI_CTL0_MCLKDIV_Pos);
+ *pu32EBITCTL = u32TimingConfig;
+}
+
+/*@}*/ /* end of group EBI_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group EBI_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+/*** (C) COPYRIGHT 2013~2015 Nuvoton Technology Corp. ***/
diff --git a/bsp/nuvoton_m451/Libraries/StdDriver/src/fmc.c b/bsp/nuvoton_m451/Libraries/StdDriver/src/fmc.c
new file mode 100644
index 0000000000000000000000000000000000000000..01fcb84e95b2dd8b1e6fe40095334cf7ebb7931a
--- /dev/null
+++ b/bsp/nuvoton_m451/Libraries/StdDriver/src/fmc.c
@@ -0,0 +1,320 @@
+/**************************************************************************//**
+ * @file fmc.c
+ * @version V3.00
+ * $Revision: 7 $
+ * $Date: 15/08/11 10:26a $
+ * @brief M451 series FMC driver source file
+ *
+ * @note
+ * Copyright (C) 2014~2015 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+
+//* Includes ------------------------------------------------------------------*/
+#include
+#include "M451Series.h"
+
+/** @addtogroup Standard_Driver Standard Driver
+ @{
+*/
+
+/** @addtogroup FMC_Driver FMC Driver
+ @{
+*/
+
+
+/** @addtogroup FMC_EXPORTED_FUNCTIONS FMC Exported Functions
+ @{
+*/
+
+
+/**
+ * @brief Set boot source from LDROM or APROM after next software reset
+ *
+ * @param[in] i32BootSrc
+ * 1: Boot from LDROM,
+ * 0: Boot from APROM
+ *
+ * @return None
+ *
+ * @details This function is used to switch APROM boot or LDROM boot. User need to call
+ * FMC_SetBootSource to select boot source first, then use CPU reset or
+ * System Reset Request to reset system.
+ *
+ */
+void FMC_SetBootSource(int32_t i32BootSrc)
+{
+ if(i32BootSrc)
+ FMC->ISPCTL |= FMC_ISPCTL_BS_Msk; /* Boot from LDROM */
+ else
+ FMC->ISPCTL &= ~FMC_ISPCTL_BS_Msk;/* Boot from APROM */
+}
+
+
+/**
+ * @brief Disable ISP Functions
+ *
+ * @param None
+ *
+ * @return None
+ *
+ * @details This function will clear ISPEN bit of ISPCTL to disable ISP function
+ *
+ */
+void FMC_Close(void)
+{
+ FMC->ISPCTL &= ~FMC_ISPCTL_ISPEN_Msk;
+}
+
+
+/**
+ * @brief Disable APROM update function
+ *
+ * @param None
+ *
+ * @return None
+ *
+ * @details Disable APROM update function will forbid APROM programming when boot form APROM.
+ * APROM update is default to be disable.
+ *
+ */
+void FMC_DisableAPUpdate(void)
+{
+ FMC->ISPCTL &= ~FMC_ISPCTL_APUEN_Msk;
+}
+
+
+/**
+ * @brief Disable User Configuration update function
+ *
+ * @param None
+ *
+ * @return None
+ *
+ * @details Disable User Configuration update function will forbid User Configuration programming.
+ * User Configuration update is default to be disable.
+ */
+void FMC_DisableConfigUpdate(void)
+{
+ FMC->ISPCTL &= ~FMC_ISPCTL_CFGUEN_Msk;
+}
+
+
+/**
+ * @brief Disable LDROM update function
+ *
+ * @param None
+ *
+ * @return None
+
+ * @details Disable LDROM update function will forbid LDROM programming.
+ * LDROM update is default to be disable.
+ */
+void FMC_DisableLDUpdate(void)
+{
+ FMC->ISPCTL &= ~FMC_ISPCTL_LDUEN_Msk;
+}
+
+
+/**
+ * @brief Enable APROM update function
+ *
+ * @param None
+ *
+ * @return None
+ *
+ * @details Enable APROM to be able to program when boot from APROM.
+ *
+ */
+void FMC_EnableAPUpdate(void)
+{
+ FMC->ISPCTL |= FMC_ISPCTL_APUEN_Msk;
+}
+
+
+/**
+ * @brief Enable User Configuration update function
+ *
+ * @param None
+ *
+ * @return None
+ *
+ * @details Enable User Configuration to be able to program.
+ *
+ */
+void FMC_EnableConfigUpdate(void)
+{
+ FMC->ISPCTL |= FMC_ISPCTL_CFGUEN_Msk;
+}
+
+
+/**
+ * @brief Enable LDROM update function
+ *
+ * @param None
+ *
+ * @return None
+ *
+ * @details Enable LDROM to be able to program.
+ *
+ */
+void FMC_EnableLDUpdate(void)
+{
+ FMC->ISPCTL |= FMC_ISPCTL_LDUEN_Msk;
+}
+
+
+/**
+ * @brief Get the current boot source
+ *
+ * @param None
+ *
+ * @retval 0 This chip is currently booting from APROM
+ * @retval 1 This chip is currently booting from LDROM
+ *
+ * @note This function only show the boot source.
+ * User need to read ISPSTA register to know if IAP mode supported or not in relative boot.
+ */
+int32_t FMC_GetBootSource(void)
+{
+ if(FMC->ISPCTL & FMC_ISPCTL_BS_Msk)
+ return 1;
+ else
+ return 0;
+}
+
+
+/**
+ * @brief Enable FMC ISP function
+ *
+ * @param None
+ *
+ * @return None
+ *
+ * @details ISPEN bit of ISPCTL must be set before we can use ISP commands.
+ * Therefore, To use all FMC function APIs, user needs to call FMC_Open() first to enable ISP functions.
+ *
+ * @note ISP functions are write-protected. user also needs to unlock it by calling SYS_UnlockReg() before using all ISP functions.
+ *
+ */
+void FMC_Open(void)
+{
+ FMC->ISPCTL |= FMC_ISPCTL_ISPEN_Msk;
+}
+
+/**
+ * @brief Get the base address of Data Flash if enabled.
+ *
+ * @param None
+ *
+ * @return The base address of Data Flash
+ *
+ * @details This function is used to return the base address of Data Flash.
+ *
+ */
+uint32_t FMC_ReadDataFlashBaseAddr(void)
+{
+ return FMC->DFBA;
+}
+
+
+/**
+ * @brief Read the User Configuration words.
+ *
+ * @param[out] u32Config The word buffer to store the User Configuration data.
+ * @param[in] u32Count The word count to be read.
+ *
+ * @retval 0 Success
+ * @retval -1 Failed
+ *
+ * @details This function is used to read the settings of user configuration.
+ * if u32Count = 1, Only CONFIG0 will be returned to the buffer specified by u32Config.
+ * if u32Count = 2, Both CONFIG0 and CONFIG1 will be returned.
+ */
+int32_t FMC_ReadConfig(uint32_t *u32Config, uint32_t u32Count)
+{
+ int32_t i;
+
+ for(i = 0; i < u32Count; i++)
+ u32Config[i] = FMC_Read(FMC_CONFIG_BASE + i * 4);
+
+ return 0;
+}
+
+
+/**
+ * @brief Write User Configuration
+ *
+ * @param[in] u32Config The word buffer to store the User Configuration data.
+ * @param[in] u32Count The word count to program to User Configuration.
+ *
+ * @retval 0 Success
+ * @retval -1 Failed
+ *
+ * @details User must enable User Configuration update before writing it.
+ * User must erase User Configuration before writing it.
+ * User Configuration is also be page erase. User needs to backup necessary data
+ * before erase User Configuration.
+ */
+int32_t FMC_WriteConfig(uint32_t *u32Config, uint32_t u32Count)
+{
+ int32_t i;
+
+ for(i = 0; i < u32Count; i++)
+ {
+ FMC_Write(FMC_CONFIG_BASE + i * 4, u32Config[i]);
+ if(FMC_Read(FMC_CONFIG_BASE + i * 4) != u32Config[i])
+ return -1;
+ }
+
+ return 0;
+}
+
+/**
+ * @brief Enable Flash Access Frequency Optimization Mode
+ *
+ * @param[in] u32Mode Optimize flash access cycle mode
+ * - \ref FMC_FTCTL_OPTIMIZE_DISABLE
+ * - \ref FMC_FTCTL_OPTIMIZE_12MHZ
+ * - \ref FMC_FTCTL_OPTIMIZE_36MHZ
+ * - \ref FMC_FTCTL_OPTIMIZE_60MHZ
+ * - \ref FMC_FTCTL_OPTIMIZE_72MHZ
+ *
+ * @return None
+ *
+ * @details This function will set FOM bit fields of FTCTL register to set flash access frequency optimization mode.
+ *
+ * @note The flash optimization mode (FOM) bits are write protect.
+ *
+ */
+void FMC_EnableFreqOptimizeMode(uint32_t u32Mode)
+{
+ FMC->FTCTL &= ~FMC_FTCTL_FOM_Msk;
+ FMC->FTCTL |= (u32Mode << FMC_FTCTL_FOM_Pos);
+}
+
+/**
+ * @brief Disable Flash Access Frequency Optimization Mode
+ *
+ * @param None
+ *
+ * @return None
+ *
+ * @details This function will clear FOM bit fields of FTCTL register to disable flash access frequency optimization mode.
+ *
+ * @note The flash optimization mode (FOM) bits are write protect.
+ *
+ */
+void FMC_DisableFreqOptimizeMode(void)
+{
+ FMC->FTCTL &= ~FMC_FTCTL_FOM_Msk;
+}
+
+/*@}*/ /* end of group FMC_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group FMC_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+/*** (C) COPYRIGHT 2014~2015 Nuvoton Technology Corp. ***/
+
+
diff --git a/bsp/nuvoton_m451/Libraries/StdDriver/src/gpio.c b/bsp/nuvoton_m451/Libraries/StdDriver/src/gpio.c
new file mode 100644
index 0000000000000000000000000000000000000000..7300e4eb9fc270d581bf37dc4da75b046d7dada9
--- /dev/null
+++ b/bsp/nuvoton_m451/Libraries/StdDriver/src/gpio.c
@@ -0,0 +1,102 @@
+/**************************************************************************//**
+ * @file gpio.c
+ * @version V3.00
+ * $Revision: 6 $
+ * $Date: 15/08/11 10:26a $
+ * @brief M451 series GPIO driver source file
+ *
+ * @note
+ * Copyright (C) 2014~2015 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+
+#include "M451Series.h"
+
+/** @addtogroup Standard_Driver Standard Driver
+ @{
+*/
+
+/** @addtogroup GPIO_Driver GPIO Driver
+ @{
+*/
+
+/** @addtogroup GPIO_EXPORTED_FUNCTIONS GPIO Exported Functions
+ @{
+*/
+
+/**
+ * @brief Set GPIO operation mode
+ *
+ * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE or PF.
+ * @param[in] u32PinMask The single or multiple pins of specified GPIO port.
+ * It could be BIT0 ~ BIT15 for PA, PB, PC and PD GPIO port.
+ * It could be BIT0 ~ BIT14 for PE GPIO port.
+ * It could be BIT0 ~ BIT7 for PF GPIO port.
+ * @param[in] u32Mode Operation mode. It could be \n
+ * GPIO_MODE_INPUT, GPIO_MODE_OUTPUT, GPIO_MODE_OPEN_DRAIN, GPIO_MODE_QUASI.
+ *
+ * @return None
+ *
+ * @details This function is used to set specified GPIO operation mode.
+ */
+void GPIO_SetMode(GPIO_T *port, uint32_t u32PinMask, uint32_t u32Mode)
+{
+ uint32_t i;
+
+ for(i = 0; i < GPIO_PIN_MAX; i++)
+ {
+ if(u32PinMask & (1 << i))
+ {
+ port->MODE = (port->MODE & ~(0x3 << (i << 1))) | (u32Mode << (i << 1));
+ }
+ }
+}
+
+/**
+ * @brief Enable GPIO interrupt
+ *
+ * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE or PF.
+ * @param[in] u32Pin The pin of specified GPIO port.
+ * It could be 0 ~ 15 for PA, PB, PC and PD GPIO port.
+ * It could be 0 ~ 14 for PE GPIO port.
+ * It could be 0 ~ 7 for PF GPIO port.
+ * @param[in] u32IntAttribs The interrupt attribute of specified GPIO pin. It could be \n
+ * GPIO_INT_RISING, GPIO_INT_FALLING, GPIO_INT_BOTH_EDGE, GPIO_INT_HIGH, GPIO_INT_LOW.
+ *
+ * @return None
+ *
+ * @details This function is used to enable specified GPIO pin interrupt.
+ */
+void GPIO_EnableInt(GPIO_T *port, uint32_t u32Pin, uint32_t u32IntAttribs)
+{
+ port->INTTYPE |= (((u32IntAttribs >> 24) & 0xFFUL) << u32Pin);
+ port->INTEN |= ((u32IntAttribs & 0xFFFFFFUL) << u32Pin);
+}
+
+
+/**
+ * @brief Disable GPIO interrupt
+ *
+ * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE or PF.
+ * @param[in] u32Pin The pin of specified GPIO port.
+ * It could be 0 ~ 15 for PA, PB, PC and PD GPIO port.
+ * It could be 0 ~ 14 for PE GPIO port.
+ * It could be 0 ~ 7 for PF GPIO port.
+ *
+ * @return None
+ *
+ * @details This function is used to enable specified GPIO pin interrupt.
+ */
+void GPIO_DisableInt(GPIO_T *port, uint32_t u32Pin)
+{
+ port->INTTYPE &= ~(1UL << u32Pin);
+ port->INTEN &= ~((0x00010001UL) << u32Pin);
+}
+
+
+/*@}*/ /* end of group GPIO_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group GPIO_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+/*** (C) COPYRIGHT 2014~2015 Nuvoton Technology Corp. ***/
diff --git a/bsp/nuvoton_m451/Libraries/StdDriver/src/i2c.c b/bsp/nuvoton_m451/Libraries/StdDriver/src/i2c.c
new file mode 100644
index 0000000000000000000000000000000000000000..ad77a32c20fef6bd5c311f62390fff372baeadc3
--- /dev/null
+++ b/bsp/nuvoton_m451/Libraries/StdDriver/src/i2c.c
@@ -0,0 +1,612 @@
+/**************************************************************************//**
+ * @file i2c.c
+ * @version V3.00
+ * $Revision: 23 $
+ * $Date: 15/08/11 10:26a $
+ * @brief M451 series I2C driver source file
+ *
+ * @note
+ * Copyright (C) 2014~2015 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#include "M451Series.h"
+
+/** @addtogroup Standard_Driver Standard Driver
+ @{
+*/
+
+/** @addtogroup I2C_Driver I2C Driver
+ @{
+*/
+
+
+/** @addtogroup I2C_EXPORTED_FUNCTIONS I2C Exported Functions
+ @{
+*/
+
+/**
+ * @brief Enable specify I2C Controller and set Clock Divider
+ *
+ * @param[in] i2c Specify I2C port
+ * @param[in] u32BusClock The target I2C bus clock in Hz
+ *
+ * @return Actual I2C bus clock frequency
+ *
+ * @details The function enable the specify I2C Controller and set proper Clock Divider
+ * in I2C CLOCK DIVIDED REGISTER (I2CLK) according to the target I2C Bus clock.
+ * I2C Bus clock = PCLK / (4*(divider+1).
+ *
+ */
+uint32_t I2C_Open(I2C_T *i2c, uint32_t u32BusClock)
+{
+ uint32_t u32Div;
+
+ u32Div = (uint32_t)(((SystemCoreClock * 10) / (u32BusClock * 4) + 5) / 10 - 1); /* Compute proper divider for I2C clock */
+ i2c->CLKDIV = u32Div;
+
+ /* Enable I2C */
+ i2c->CTL |= I2C_CTL_I2CEN_Msk;
+
+ return (SystemCoreClock / ((u32Div + 1) << 2));
+}
+
+/**
+ * @brief Disable specify I2C Controller
+ *
+ * @param[in] i2c Specify I2C port
+ *
+ * @return None
+ *
+ * @details Reset I2C Controller and disable specify I2C port.
+ *
+ */
+
+void I2C_Close(I2C_T *i2c)
+{
+ /* Reset I2C Controller */
+ if((uint32_t)i2c == I2C0_BASE)
+ {
+ SYS->IPRST1 |= SYS_IPRST1_I2C0RST_Msk;
+ SYS->IPRST1 &= ~SYS_IPRST1_I2C0RST_Msk;
+ }
+ else if((uint32_t)i2c == I2C1_BASE)
+ {
+ SYS->IPRST1 |= SYS_IPRST1_I2C1RST_Msk;
+ SYS->IPRST1 &= ~SYS_IPRST1_I2C1RST_Msk;
+ }
+
+ /* Disable I2C */
+ i2c->CTL &= ~I2C_CTL_I2CEN_Msk;
+}
+
+/**
+ * @brief Clear Time-out Counter flag
+ *
+ * @param[in] i2c Specify I2C port
+ *
+ * @return None
+ *
+ * @details When Time-out flag will be set, use this function to clear I2C Bus Time-out counter flag .
+ *
+ */
+void I2C_ClearTimeoutFlag(I2C_T *i2c)
+{
+ i2c->TOCTL |= I2C_TOCTL_TOIF_Msk;
+}
+
+/**
+ * @brief Set Control bit of I2C Controller
+ *
+ * @param[in] i2c Specify I2C port
+ * @param[in] u8Start Set I2C START condition
+ * @param[in] u8Stop Set I2C STOP condition
+ * @param[in] u8Si Clear SI flag
+ * @param[in] u8Ack Set I2C ACK bit
+ *
+ * @return None
+ *
+ * @details The function set I2C Control bit of I2C Bus protocol.
+ *
+ */
+void I2C_Trigger(I2C_T *i2c, uint8_t u8Start, uint8_t u8Stop, uint8_t u8Si, uint8_t u8Ack)
+{
+ uint32_t u32Reg = 0;
+
+ if(u8Start)
+ u32Reg |= I2C_CTL_STA;
+ if(u8Stop)
+ u32Reg |= I2C_CTL_STO;
+ if(u8Si)
+ u32Reg |= I2C_CTL_SI;
+ if(u8Ack)
+ u32Reg |= I2C_CTL_AA;
+
+ i2c->CTL = (i2c->CTL & ~0x3C) | u32Reg;
+}
+
+/**
+ * @brief Disable Interrupt of I2C Controller
+ *
+ * @param[in] i2c Specify I2C port
+ *
+ * @return None
+ *
+ * @details The function is used for disable I2C interrupt
+ *
+ */
+void I2C_DisableInt(I2C_T *i2c)
+{
+ i2c->CTL &= ~I2C_CTL_INTEN_Msk;
+}
+
+/**
+ * @brief Enable Interrupt of I2C Controller
+ *
+ * @param[in] i2c Specify I2C port
+ *
+ * @return None
+ *
+ * @details The function is used for enable I2C interrupt
+ *
+ */
+void I2C_EnableInt(I2C_T *i2c)
+{
+ i2c->CTL |= I2C_CTL_INTEN_Msk;
+}
+
+/**
+ * @brief Get I2C Bus Clock
+ *
+ * @param[in] i2c Specify I2C port
+ *
+ * @return The actual I2C Bus clock in Hz
+ *
+ * @details To get the actual I2C Bus Clock frequency.
+ */
+uint32_t I2C_GetBusClockFreq(I2C_T *i2c)
+{
+ uint32_t u32Divider = i2c->CLKDIV;
+
+ return (SystemCoreClock / ((u32Divider + 1) << 2));
+}
+
+/**
+ * @brief Set I2C Bus Clock
+ *
+ * @param[in] i2c Specify I2C port
+ * @param[in] u32BusClock The target I2C Bus Clock in Hz
+ *
+ * @return The actual I2C Bus Clock in Hz
+ *
+ * @details To set the actual I2C Bus Clock frequency.
+ */
+uint32_t I2C_SetBusClockFreq(I2C_T *i2c, uint32_t u32BusClock)
+{
+ uint32_t u32Div;
+
+ u32Div = (uint32_t)(((SystemCoreClock * 10) / (u32BusClock * 4) + 5) / 10 - 1); /* Compute proper divider for I2C clock */
+ i2c->CLKDIV = u32Div;
+
+ return (SystemCoreClock / ((u32Div + 1) << 2));
+}
+
+/**
+ * @brief Get Interrupt Flag
+ *
+ * @param[in] i2c Specify I2C port
+ *
+ * @return I2C interrupt flag status
+ *
+ * @details To get I2C Bus interrupt flag.
+ */
+uint32_t I2C_GetIntFlag(I2C_T *i2c)
+{
+ return ((i2c->CTL & I2C_CTL_SI_Msk) == I2C_CTL_SI_Msk ? 1 : 0);
+}
+
+/**
+ * @brief Get I2C Bus Status Code
+ *
+ * @param[in] i2c Specify I2C port
+ *
+ * @return I2C Status Code
+ *
+ * @details To get I2C Bus Status Code.
+ */
+uint32_t I2C_GetStatus(I2C_T *i2c)
+{
+ return (i2c->STATUS);
+}
+
+/**
+ * @brief Read a Byte from I2C Bus
+ *
+ * @param[in] i2c Specify I2C port
+ *
+ * @return I2C Data
+ *
+ * @details To read a bytes data from specify I2C port.
+ */
+uint8_t I2C_GetData(I2C_T *i2c)
+{
+ return (i2c->DAT);
+}
+
+/**
+ * @brief Send a byte to I2C Bus
+ *
+ * @param[in] i2c Specify I2C port
+ * @param[in] u8Data The data to send to I2C bus
+ *
+ * @return None
+ *
+ * @details This function is used to write a byte to specified I2C port
+ */
+void I2C_SetData(I2C_T *i2c, uint8_t u8Data)
+{
+ i2c->DAT = u8Data;
+}
+
+/**
+ * @brief Set 7-bit Slave Address and GC Mode
+ *
+ * @param[in] i2c Specify I2C port
+ * @param[in] u8SlaveNo Set the number of I2C address register (0~3)
+ * @param[in] u8SlaveAddr 7-bit slave address
+ * @param[in] u8GCMode Enable/Disable GC mode (I2C_GCMODE_ENABLE / I2C_GCMODE_DISABLE)
+ *
+ * @return None
+ *
+ * @details This function is used to set 7-bit slave addresses in I2C SLAVE ADDRESS REGISTER (I2CADDR0~3)
+ * and enable GC Mode.
+ *
+ */
+void I2C_SetSlaveAddr(I2C_T *i2c, uint8_t u8SlaveNo, uint8_t u8SlaveAddr, uint8_t u8GCMode)
+{
+ switch(u8SlaveNo)
+ {
+ case 1:
+ i2c->ADDR1 = (u8SlaveAddr << 1) | u8GCMode;
+ break;
+ case 2:
+ i2c->ADDR2 = (u8SlaveAddr << 1) | u8GCMode;
+ break;
+ case 3:
+ i2c->ADDR3 = (u8SlaveAddr << 1) | u8GCMode;
+ break;
+ case 0:
+ default:
+ i2c->ADDR0 = (u8SlaveAddr << 1) | u8GCMode;
+ break;
+ }
+}
+
+/**
+ * @brief Configure the mask bits of 7-bit Slave Address
+ *
+ * @param[in] i2c Specify I2C port
+ * @param[in] u8SlaveNo Set the number of I2C address mask register (0~3)
+ * @param[in] u8SlaveAddrMask A byte for slave address mask
+ *
+ * @return None
+ *
+ * @details This function is used to set 7-bit slave addresses.
+ *
+ */
+void I2C_SetSlaveAddrMask(I2C_T *i2c, uint8_t u8SlaveNo, uint8_t u8SlaveAddrMask)
+{
+ switch(u8SlaveNo)
+ {
+ case 1:
+ i2c->ADDRMSK1 = u8SlaveAddrMask << 1;
+ break;
+ case 2:
+ i2c->ADDRMSK2 = u8SlaveAddrMask << 1;
+ break;
+ case 3:
+ i2c->ADDRMSK3 = u8SlaveAddrMask << 1;
+ break;
+ case 0:
+ default:
+ i2c->ADDRMSK0 = u8SlaveAddrMask << 1;
+ break;
+ }
+}
+
+/**
+ * @brief Enable Time-out Counter Function and support Long Time-out
+ *
+ * @param[in] i2c Specify I2C port
+ * @param[in] u8LongTimeout Configure DIV4 to enable Long Time-out (0/1)
+ *
+ * @return None
+ *
+ * @details This function enable Time-out Counter function and configure DIV4 to support Long
+ * Time-out.
+ *
+ */
+void I2C_EnableTimeout(I2C_T *i2c, uint8_t u8LongTimeout)
+{
+ if(u8LongTimeout)
+ i2c->TOCTL |= I2C_TOCTL_TOCDIV4_Msk;
+ else
+ i2c->TOCTL &= ~I2C_TOCTL_TOCDIV4_Msk;
+
+ i2c->TOCTL |= I2C_TOCTL_TOCEN_Msk;
+}
+
+/**
+ * @brief Disable Time-out Counter Function
+ *
+ * @param[in] i2c Specify I2C port
+ *
+ * @return None
+ *
+ * @details To disable Time-out Counter function in I2CTOC register.
+ *
+ */
+void I2C_DisableTimeout(I2C_T *i2c)
+{
+ i2c->TOCTL &= ~I2C_TOCTL_TOCEN_Msk;
+}
+
+/**
+ * @brief Enable I2C Wake-up Function
+ *
+ * @param[in] i2c Specify I2C port
+ *
+ * @return None
+ *
+ * @details To enable Wake-up function of I2C Wake-up control register.
+ *
+ */
+void I2C_EnableWakeup(I2C_T *i2c)
+{
+ i2c->WKCTL |= I2C_WKCTL_WKEN_Msk;
+}
+
+/**
+ * @brief Disable I2C Wake-up Function
+ *
+ * @param[in] i2c Specify I2C port
+ *
+ * @return None
+ *
+ * @details To disable Wake-up function of I2C Wake-up control register.
+ *
+ */
+void I2C_DisableWakeup(I2C_T *i2c)
+{
+ i2c->WKCTL &= ~I2C_WKCTL_WKEN_Msk;
+}
+
+/**
+ * @brief To get SMBus Status
+ *
+ * @param[in] i2c Specify I2C port
+ *
+ * @return SMBus status
+ *
+ * @details To get the Bus Management status of I2C_BUSSTS register
+ *
+ */
+uint32_t I2C_SMBusGetStatus(I2C_T *i2c)
+{
+ return (i2c->BUSSTS);
+}
+
+/**
+ * @brief Clear SMBus Interrupt Flag
+ *
+ * @param[in] i2c Specify I2C port
+ * @param[in] u8SMBusIntFlag Specify SMBus interrupt flag
+ *
+ * @return None
+ *
+ * @details To clear flags of I2C_BUSSTS status register if interrupt set.
+ *
+ */
+void I2C_SMBusClearInterruptFlag(I2C_T *i2c, uint8_t u8SMBusIntFlag)
+{
+ i2c->BUSSTS |= u8SMBusIntFlag;
+}
+
+/**
+ * @brief Set SMBus Bytes Counts of Transmission or Reception
+ *
+ * @param[in] i2c Specify I2C port
+ * @param[in] u32PktSize Transmit / Receive bytes
+ *
+ * @return None
+ *
+ * @details The transmission or receive byte number in one transaction when PECEN is set. The maximum is 255 bytes.
+ *
+ */
+void I2C_SMBusSetPacketByteCount(I2C_T *i2c, uint32_t u32PktSize)
+{
+ i2c->PKTSIZE = u32PktSize;
+}
+
+/**
+ * @brief Init SMBus Host/Device Mode
+ *
+ * @param[in] i2c Specify I2C port
+ * @param[in] u8HostDevice Init SMBus port mode(I2C_SMBH_ENABLE(1)/I2C_SMBD_ENABLE(0))
+ *
+ * @return None
+ *
+ * @details Using SMBus communication must specify the port is a Host or a Device.
+ *
+ */
+void I2C_SMBusOpen(I2C_T *i2c, uint8_t u8HostDevice)
+{
+ /* Clear BMHEN, BMDEN of BUSCTL Register */
+ i2c->BUSCTL &= ~(I2C_BUSCTL_BMHEN_Msk | I2C_BUSCTL_BMDEN_Msk);
+
+ /* Set SMBus Host/Device Mode, and enable Bus Management*/
+ if(u8HostDevice == I2C_SMBH_ENABLE)
+ i2c->BUSCTL |= (I2C_BUSCTL_BMHEN_Msk | I2C_BUSCTL_BUSEN_Msk);
+ else
+ i2c->BUSCTL |= (I2C_BUSCTL_BMDEN_Msk | I2C_BUSCTL_BUSEN_Msk);
+}
+
+/**
+ * @brief Disable SMBus function
+ *
+ * @param[in] i2c Specify I2C port
+ *
+ * @return None
+ *
+ * @details Disable all SMBus function include Bus disable, CRC check, Acknowledge by manual, Host/Device Mode.
+ *
+ */
+void I2C_SMBusClose(I2C_T *i2c)
+{
+
+ i2c->BUSCTL = 0x00;
+}
+
+/**
+ * @brief Enable SMBus PEC Transmit Function
+ *
+ * @param[in] i2c Specify I2C port
+ * @param[in] u8PECTxEn CRC transmit enable(PECTX_ENABLE) or disable(PECTX_DISABLE)
+ *
+ * @return None
+ *
+ * @details When enable CRC check function, the Host or Device needs to transmit CRC byte.
+ *
+ */
+void I2C_SMBusPECTxEnable(I2C_T *i2c, uint8_t u8PECTxEn)
+{
+ i2c->BUSCTL &= ~I2C_BUSCTL_PECTXEN_Msk;
+
+ if(u8PECTxEn)
+ i2c->BUSCTL |= (I2C_BUSCTL_PECEN_Msk | I2C_BUSCTL_PECTXEN_Msk);
+ else
+ i2c->BUSCTL |= I2C_BUSCTL_PECEN_Msk;
+}
+
+/**
+ * @brief Get SMBus CRC value
+ *
+ * @param[in] i2c Specify I2C port
+ *
+ * @return A byte is packet error check value
+ *
+ * @details The CRC check value after a transmission or a reception by count by using CRC8
+ *
+ */
+uint8_t I2C_SMBusGetPECValue(I2C_T *i2c)
+{
+ return i2c->PKTCRC;
+}
+
+/**
+ * @brief Calculate Time-out of SMBus idle period
+ *
+ * @param[in] i2c Specify I2C port
+ * @param[in] us Time-out length(us)
+ * @param[in] u32Hclk I2C peripheral clock frequency
+ *
+ * @return None
+ *
+ * @details This function is used to set SMBus Time-out length when bus is in Idle state.
+ *
+ */
+
+void I2C_SMBusIdleTimeout(I2C_T *i2c, uint32_t us, uint32_t u32Hclk)
+{
+ uint32_t u32Div, u32Hclk_kHz;
+
+ i2c->BUSCTL |= I2C_BUSCTL_TIDLE_Msk;
+ u32Hclk_kHz = u32Hclk / 1000;
+ u32Div = (((us * u32Hclk_kHz) / 1000) >> 2) - 1;
+ if(u32Div > 255)
+ {
+ i2c->BUSTOUT = 0xFF;
+ }
+ else
+ {
+ i2c->BUSTOUT = u32Div;
+ }
+
+}
+
+/**
+ * @brief Calculate Time-out of SMBus active period
+ *
+ * @param[in] i2c Specify I2C port
+ * @param[in] ms Time-out length(ms)
+ * @param[in] u32Pclk peripheral clock frequency
+ *
+ * @return None
+ *
+ * @details This function is used to set SMBus Time-out length when bus is in active state.
+ * Time-out length is calculate the SCL line "one clock" pull low timing.
+ *
+ */
+
+void I2C_SMBusTimeout(I2C_T *i2c, uint32_t ms, uint32_t u32Pclk)
+{
+ uint32_t u32Div, u32Pclk_kHz;
+
+ i2c->BUSCTL &= ~I2C_BUSCTL_TIDLE_Msk;
+
+ /* DIV4 disabled */
+ i2c->TOCTL &= ~I2C_TOCTL_TOCEN_Msk;
+ u32Pclk_kHz = u32Pclk / 1000;
+ u32Div = ((ms * u32Pclk_kHz) / (16 * 1024)) - 1;
+ if(u32Div <= 0xFF)
+ {
+ i2c->BUSTOUT = u32Div;
+ return;
+ }
+
+ /* DIV4 enabled */
+ i2c->TOCTL |= I2C_TOCTL_TOCEN_Msk;
+
+ i2c->BUSTOUT = (((ms * u32Pclk_kHz) / (16 * 1024 * 4)) - 1) & 0xFF; //The max value is 255
+}
+
+/**
+ * @brief Calculate Cumulative Clock low Time-out of SMBus active period
+ *
+ * @param[in] i2c Specify I2C port
+ * @param[in] ms Time-out length(ms)
+ * @param[in] u32Pclk peripheral clock frequency
+ *
+ * @return None
+ *
+ * @details This function is used to set SMBus Time-out length when bus is in Active state.
+ * Time-out length is calculate the SCL line "clocks" low cumulative timing.
+ *
+ */
+
+void I2C_SMBusClockLoTimeout(I2C_T *i2c, uint32_t ms, uint32_t u32Pclk)
+{
+ uint32_t u32Div, u32Pclk_kHz;
+
+ i2c->BUSCTL &= ~I2C_BUSCTL_TIDLE_Msk;
+
+ /* DIV4 disabled */
+ i2c->TOCTL &= ~I2C_TOCTL_TOCEN_Msk;
+ u32Pclk_kHz = u32Pclk / 1000;
+ u32Div = ((ms * u32Pclk_kHz) / (16 * 1024)) - 1;
+ if(u32Div <= 0xFF)
+ {
+ i2c->CLKTOUT = u32Div;
+ return;
+ }
+
+ /* DIV4 enabled */
+ i2c->TOCTL |= I2C_TOCTL_TOCEN_Msk;
+ i2c->CLKTOUT = (((ms * u32Pclk_kHz) / (16 * 1024 * 4)) - 1) & 0xFF; //The max value is 255
+}
+
+/*@}*/ /* end of group I2C_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group I2C_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+/*** (C) COPYRIGHT 2014~2015 Nuvoton Technology Corp. ***/
diff --git a/bsp/nuvoton_m451/Libraries/StdDriver/src/pdma.c b/bsp/nuvoton_m451/Libraries/StdDriver/src/pdma.c
new file mode 100644
index 0000000000000000000000000000000000000000..53f4420c1c6828155215f5dcabccd1ab064925df
--- /dev/null
+++ b/bsp/nuvoton_m451/Libraries/StdDriver/src/pdma.c
@@ -0,0 +1,389 @@
+/**************************************************************************//**
+ * @file pdma.c
+ * @version V1.00
+ * $Revision: 12 $
+ * $Date: 15/08/11 10:26a $
+ * @brief M451 series PDMA driver source file
+ *
+ * @note
+ * Copyright (C) 2014~2015 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#include "M451Series.h"
+
+
+static uint8_t u32ChSelect[PDMA_CH_MAX];
+
+/** @addtogroup Standard_Driver Standard Driver
+ @{
+*/
+
+/** @addtogroup PDMA_Driver PDMA Driver
+ @{
+*/
+
+
+/** @addtogroup PDMA_EXPORTED_FUNCTIONS PDMA Exported Functions
+ @{
+*/
+
+/**
+ * @brief PDMA Open
+ *
+ * @param[in] u32Mask Channel enable bits.
+ *
+ * @return None
+ *
+ * @details This function enable the PDMA channels.
+ */
+void PDMA_Open(uint32_t u32Mask)
+{
+ int volatile i;
+
+ for(i = 0; i < PDMA_CH_MAX; i++)
+ {
+ PDMA->DSCT[i].CTL = 0;
+ u32ChSelect[i] = 0x1f;
+ }
+
+ PDMA->CHCTL |= u32Mask;
+}
+
+/**
+ * @brief PDMA Close
+ *
+ * @param None
+ *
+ * @return None
+ *
+ * @details This function disable all PDMA channels.
+ */
+void PDMA_Close(void)
+{
+ PDMA->CHCTL = 0;
+}
+
+/**
+ * @brief Set PDMA Transfer Count
+ *
+ * @param[in] u32Ch The selected channel
+ * @param[in] u32Width Data width. Valid values are
+ * - \ref PDMA_WIDTH_8
+ * - \ref PDMA_WIDTH_16
+ * - \ref PDMA_WIDTH_32
+ * @param[in] u32TransCount Transfer count
+ *
+ * @return None
+ *
+ * @details This function set the selected channel data width and transfer count.
+ */
+void PDMA_SetTransferCnt(uint32_t u32Ch, uint32_t u32Width, uint32_t u32TransCount)
+{
+ PDMA->DSCT[u32Ch].CTL &= ~(PDMA_DSCT_CTL_TXCNT_Msk | PDMA_DSCT_CTL_TXWIDTH_Msk);
+ PDMA->DSCT[u32Ch].CTL |= (u32Width | ((u32TransCount - 1) << PDMA_DSCT_CTL_TXCNT_Pos));
+}
+
+/**
+ * @brief Set PDMA Transfer Address
+ *
+ * @param[in] u32Ch The selected channel
+ * @param[in] u32SrcAddr Source address
+ * @param[in] u32SrcCtrl Source control attribute. Valid values are
+ * - \ref PDMA_SAR_INC
+ * - \ref PDMA_SAR_FIX
+ * @param[in] u32DstAddr destination address
+ * @param[in] u32DstCtrl destination control attribute. Valid values are
+ * - \ref PDMA_DAR_INC
+ * - \ref PDMA_DAR_FIX
+ *
+ * @return None
+ *
+ * @details This function set the selected channel source/destination address and attribute.
+ */
+void PDMA_SetTransferAddr(uint32_t u32Ch, uint32_t u32SrcAddr, uint32_t u32SrcCtrl, uint32_t u32DstAddr, uint32_t u32DstCtrl)
+{
+ PDMA->DSCT[u32Ch].SA = u32SrcAddr;
+ PDMA->DSCT[u32Ch].DA = u32DstAddr;
+ PDMA->DSCT[u32Ch].CTL &= ~(PDMA_DSCT_CTL_SAINC_Msk | PDMA_DSCT_CTL_DAINC_Msk);
+ PDMA->DSCT[u32Ch].CTL |= (u32SrcCtrl | u32DstCtrl);
+}
+
+/**
+ * @brief Set PDMA Transfer Mode
+ *
+ * @param[in] u32Ch The selected channel
+ * @param[in] u32Peripheral The selected peripheral. Valid values are
+ * - \ref PDMA_SPI0_TX
+ * - \ref PDMA_SPI1_TX
+ * - \ref PDMA_SPI2_TX
+ * - \ref PDMA_UART0_TX
+ * - \ref PDMA_UART1_TX
+ * - \ref PDMA_UART2_TX
+ * - \ref PDMA_UART3_TX
+ * - \ref PDMA_DAC_TX
+ * - \ref PDMA_ADC_RX
+ * - \ref PDMA_PWM0_P1_RX
+ * - \ref PDMA_PWM0_P2_RX
+ * - \ref PDMA_PWM0_P3_RX
+ * - \ref PDMA_PWM1_P1_RX
+ * - \ref PDMA_PWM1_P2_RX
+ * - \ref PDMA_PWM1_P3_RX
+ * - \ref PDMA_SPI0_RX
+ * - \ref PDMA_SPI1_RX
+ * - \ref PDMA_SPI2_RX
+ * - \ref PDMA_UART0_RX
+ * - \ref PDMA_UART1_RX
+ * - \ref PDMA_UART2_RX
+ * - \ref PDMA_UART3_RX
+ * - \ref PDMA_MEM
+ * @param[in] u32ScatterEn Scatter-gather mode enable
+ * @param[in] u32DescAddr Scatter-gather descriptor address
+ *
+ * @return None
+ *
+ * @details This function set the selected channel transfer mode. Include peripheral setting.
+ */
+void PDMA_SetTransferMode(uint32_t u32Ch, uint32_t u32Peripheral, uint32_t u32ScatterEn, uint32_t u32DescAddr)
+{
+ u32ChSelect[u32Ch] = u32Peripheral;
+ switch(u32Ch)
+ {
+ case 0:
+ PDMA->REQSEL0_3 = (PDMA->REQSEL0_3 & ~PDMA_REQSEL0_3_REQSRC0_Msk) | u32Peripheral;
+ break;
+ case 1:
+ PDMA->REQSEL0_3 = (PDMA->REQSEL0_3 & ~PDMA_REQSEL0_3_REQSRC1_Msk) | (u32Peripheral << PDMA_REQSEL0_3_REQSRC1_Pos);
+ break;
+ case 2:
+ PDMA->REQSEL0_3 = (PDMA->REQSEL0_3 & ~PDMA_REQSEL0_3_REQSRC2_Msk) | (u32Peripheral << PDMA_REQSEL0_3_REQSRC2_Pos);
+ break;
+ case 3:
+ PDMA->REQSEL0_3 = (PDMA->REQSEL0_3 & ~PDMA_REQSEL0_3_REQSRC3_Msk) | (u32Peripheral << PDMA_REQSEL0_3_REQSRC3_Pos);
+ break;
+ case 4:
+ PDMA->REQSEL4_7 = (PDMA->REQSEL4_7 & ~PDMA_REQSEL4_7_REQSRC4_Msk) | u32Peripheral;
+ break;
+ case 5:
+ PDMA->REQSEL4_7 = (PDMA->REQSEL4_7 & ~PDMA_REQSEL4_7_REQSRC5_Msk) | (u32Peripheral << PDMA_REQSEL4_7_REQSRC5_Pos);
+ break;
+ case 6:
+ PDMA->REQSEL4_7 = (PDMA->REQSEL4_7 & ~PDMA_REQSEL4_7_REQSRC6_Msk) | (u32Peripheral << PDMA_REQSEL4_7_REQSRC6_Pos);
+ break;
+ case 7:
+ PDMA->REQSEL4_7 = (PDMA->REQSEL4_7 & ~PDMA_REQSEL4_7_REQSRC7_Msk) | (u32Peripheral << PDMA_REQSEL4_7_REQSRC7_Pos);
+ break;
+ case 8:
+ PDMA->REQSEL8_11 = (PDMA->REQSEL8_11 & ~PDMA_REQSEL8_11_REQSRC8_Msk) | u32Peripheral;
+ break;
+ case 9:
+ PDMA->REQSEL8_11 = (PDMA->REQSEL8_11 & ~PDMA_REQSEL8_11_REQSRC9_Msk) | (u32Peripheral << PDMA_REQSEL8_11_REQSRC9_Pos);
+ break;
+ case 10:
+ PDMA->REQSEL8_11 = (PDMA->REQSEL8_11 & ~PDMA_REQSEL8_11_REQSRC10_Msk) | (u32Peripheral << PDMA_REQSEL8_11_REQSRC10_Pos);
+ break;
+ case 11:
+ PDMA->REQSEL8_11 = (PDMA->REQSEL8_11 & ~PDMA_REQSEL8_11_REQSRC11_Msk) | (u32Peripheral << PDMA_REQSEL8_11_REQSRC11_Pos);
+ break;
+ default:
+ ;
+ }
+
+ if(u32ScatterEn)
+ {
+ PDMA->DSCT[u32Ch].CTL = (PDMA->DSCT[u32Ch].CTL & ~PDMA_DSCT_CTL_OPMODE_Msk) | PDMA_OP_SCATTER;
+ PDMA->DSCT[u32Ch].NEXT = u32DescAddr - (PDMA->SCATBA);
+ }
+ else
+ PDMA->DSCT[u32Ch].CTL = (PDMA->DSCT[u32Ch].CTL & ~PDMA_DSCT_CTL_OPMODE_Msk) | PDMA_OP_BASIC;
+}
+
+/**
+ * @brief Set PDMA Burst Type and Size
+ *
+ * @param[in] u32Ch The selected channel
+ * @param[in] u32BurstType Burst mode or single mode. Valid values are
+ * - \ref PDMA_REQ_SINGLE
+ * - \ref PDMA_REQ_BURST
+ * @param[in] u32BurstSize Set the size of burst mode. Valid values are
+ * - \ref PDMA_BURST_128
+ * - \ref PDMA_BURST_64
+ * - \ref PDMA_BURST_32
+ * - \ref PDMA_BURST_16
+ * - \ref PDMA_BURST_8
+ * - \ref PDMA_BURST_4
+ * - \ref PDMA_BURST_2
+ * - \ref PDMA_BURST_1
+ *
+ * @return None
+ *
+ * @details This function set the selected channel burst type and size.
+ */
+void PDMA_SetBurstType(uint32_t u32Ch, uint32_t u32BurstType, uint32_t u32BurstSize)
+{
+ PDMA->DSCT[u32Ch].CTL &= ~(PDMA_DSCT_CTL_TXTYPE_Msk | PDMA_DSCT_CTL_BURSIZE_Msk);
+ PDMA->DSCT[u32Ch].CTL |= (u32BurstType | u32BurstSize);
+}
+
+/**
+ * @brief Enable timeout function
+ *
+ * @param[in] u32Mask Channel enable bits.
+ *
+ * @return None
+ *
+ * @details This function enable timeout function of the selected channel(s).
+ * @note This function is only supported in M45xD/M45xC.
+ */
+void PDMA_EnableTimeout(uint32_t u32Mask)
+{
+ PDMA->TOUTEN |= u32Mask;
+}
+
+/**
+ * @brief Disable timeout function
+ *
+ * @param[in] u32Mask Channel enable bits.
+ *
+ * @return None
+ *
+ * @details This function disable timeout function of the selected channel(s).
+ * @note This function is only supported in M45xD/M45xC.
+ */
+void PDMA_DisableTimeout(uint32_t u32Mask)
+{
+ PDMA->TOUTEN &= ~u32Mask;
+}
+
+/**
+ * @brief Set PDMA Timeout Count
+ *
+ * @param[in] u32Ch The selected channel
+ * @param[in] u32OnOff Enable/disable time out function
+ * @param[in] u32TimeOutCnt Timeout count
+ *
+ * @return None
+ *
+ * @details This function set the timeout count.
+ * @note This function is only supported in M45xD/M45xC.
+ */
+void PDMA_SetTimeOut(uint32_t u32Ch, uint32_t u32OnOff, uint32_t u32TimeOutCnt)
+{
+ switch(u32Ch)
+ {
+ case 0:
+ PDMA->TOC0_1 = (PDMA->TOC0_1 & ~PDMA_TOC0_1_TOC0_Msk) | u32TimeOutCnt;
+ break;
+ case 1:
+ PDMA->TOC0_1 = (PDMA->TOC0_1 & ~PDMA_TOC0_1_TOC1_Msk) | (u32TimeOutCnt << PDMA_TOC0_1_TOC1_Pos);
+ break;
+ case 2:
+ PDMA->TOC2_3 = (PDMA->TOC2_3 & ~PDMA_TOC2_3_TOC2_Msk) | u32TimeOutCnt;
+ break;
+ case 3:
+ PDMA->TOC2_3 = (PDMA->TOC2_3 & ~PDMA_TOC2_3_TOC3_Msk) | (u32TimeOutCnt << PDMA_TOC2_3_TOC3_Pos);
+ break;
+ case 4:
+ PDMA->TOC4_5 = (PDMA->TOC4_5 & ~PDMA_TOC4_5_TOC4_Msk) | u32TimeOutCnt;
+ break;
+ case 5:
+ PDMA->TOC4_5 = (PDMA->TOC4_5 & ~PDMA_TOC4_5_TOC5_Msk) | (u32TimeOutCnt << PDMA_TOC4_5_TOC5_Pos);
+ break;
+ case 6:
+ PDMA->TOC6_7 = (PDMA->TOC6_7 & ~PDMA_TOC6_7_TOC6_Msk) | u32TimeOutCnt;
+ break;
+ case 7:
+ PDMA->TOC6_7 = (PDMA->TOC6_7 & ~PDMA_TOC6_7_TOC7_Msk) | (u32TimeOutCnt << PDMA_TOC6_7_TOC7_Pos);
+ break;
+
+ default:
+ ;
+ }
+}
+
+/**
+ * @brief Trigger PDMA
+ *
+ * @param[in] u32Ch The selected channel
+ *
+ * @return None
+ *
+ * @details This function trigger the selected channel.
+ */
+void PDMA_Trigger(uint32_t u32Ch)
+{
+ if(u32ChSelect[u32Ch] == PDMA_MEM)
+ PDMA->SWREQ = (1 << u32Ch);
+}
+
+/**
+ * @brief Enable Interrupt
+ *
+ * @param[in] u32Ch The selected channel
+ * @param[in] u32Mask The Interrupt Type. Valid values are
+ * - \ref PDMA_INT_TRANS_DONE
+ * - \ref PDMA_INT_TEMPTY
+ * - \ref PDMA_INT_TIMEOUT
+ *
+ * @return None
+ *
+ * @details This function enable the selected channel interrupt.
+ * @note PDMA_INT_TIMEOUT is only supported in M45xD/M45xC.
+ */
+void PDMA_EnableInt(uint32_t u32Ch, uint32_t u32Mask)
+{
+ switch(u32Mask)
+ {
+ case PDMA_INT_TRANS_DONE:
+ PDMA->INTEN |= (1 << u32Ch);
+ break;
+ case PDMA_INT_TEMPTY:
+ PDMA->DSCT[u32Ch].CTL &= ~PDMA_DSCT_CTL_TBINTDIS_Msk;
+ break;
+ case PDMA_INT_TIMEOUT:
+ PDMA->TOUTIEN |= (1 << u32Ch);
+ break;
+
+ default:
+ ;
+ }
+}
+
+/**
+ * @brief Disable Interrupt
+ *
+ * @param[in] u32Ch The selected channel
+ * @param[in] u32Mask The Interrupt Type. Valid values are
+ * - \ref PDMA_INT_TRANS_DONE
+ * - \ref PDMA_INT_TEMPTY
+ * - \ref PDMA_INT_TIMEOUT
+ *
+ * @return None
+ *
+ * @details This function disable the selected channel interrupt.
+ * @note PDMA_INT_TIMEOUT is only supported in M45xD/M45xC.
+ */
+void PDMA_DisableInt(uint32_t u32Ch, uint32_t u32Mask)
+{
+ switch(u32Mask)
+ {
+ case PDMA_INT_TRANS_DONE:
+ PDMA->INTEN &= ~(1 << u32Ch);
+ break;
+ case PDMA_INT_TEMPTY:
+ PDMA->DSCT[u32Ch].CTL |= PDMA_DSCT_CTL_TBINTDIS_Msk;
+ break;
+ case PDMA_INT_TIMEOUT:
+ PDMA->TOUTIEN &= ~(1 << u32Ch);
+ break;
+
+ default:
+ ;
+ }
+}
+
+/*@}*/ /* end of group PDMA_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group PDMA_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+/*** (C) COPYRIGHT 2014~2015 Nuvoton Technology Corp. ***/
diff --git a/bsp/nuvoton_m451/Libraries/StdDriver/src/pwm.c b/bsp/nuvoton_m451/Libraries/StdDriver/src/pwm.c
new file mode 100644
index 0000000000000000000000000000000000000000..897fc21e59a388d43429f0eb1de2aaa3e72618ea
--- /dev/null
+++ b/bsp/nuvoton_m451/Libraries/StdDriver/src/pwm.c
@@ -0,0 +1,1351 @@
+/**************************************************************************//**
+ * @file pwm.c
+ * @version V3.00
+ * $Revision: 21 $
+ * $Date: 15/08/11 10:26a $
+ * @brief M451 series PWM driver source file
+ *
+ * @note
+ * Copyright (C) 2014~2015 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#include "M451Series.h"
+
+/** @addtogroup Standard_Driver Standard Driver
+ @{
+*/
+
+/** @addtogroup PWM_Driver PWM Driver
+ @{
+*/
+
+
+/** @addtogroup PWM_EXPORTED_FUNCTIONS PWM Exported Functions
+ @{
+*/
+
+/**
+ * @brief Configure PWM capture and get the nearest unit time.
+ * @param[in] pwm The pointer of the specified PWM module
+ * - PWM0 : PWM Group 0
+ * - PWM1 : PWM Group 1
+ * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
+ * @param[in] u32UnitTimeNsec The unit time of counter
+ * @param[in] u32CaptureEdge The condition to latch the counter. This parameter is not used
+ * @return The nearest unit time in nano second.
+ * @details This function is used to Configure PWM capture and get the nearest unit time.
+ */
+uint32_t PWM_ConfigCaptureChannel(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32UnitTimeNsec, uint32_t u32CaptureEdge)
+{
+ uint32_t u32Src;
+ uint32_t u32PWMClockSrc;
+ uint32_t u32NearestUnitTimeNsec;
+ uint16_t u16Prescale = 1, u16CNR = 0xFFFF;
+
+ if(pwm == PWM0)
+ u32Src = CLK->CLKSEL2 & CLK_CLKSEL2_PWM0SEL_Msk;
+ else//(pwm == PWM1)
+ u32Src = CLK->CLKSEL2 & CLK_CLKSEL2_PWM1SEL_Msk;
+
+ if(u32Src == 0)
+ {
+ //clock source is from PLL clock
+ u32PWMClockSrc = CLK_GetPLLClockFreq();
+ }
+ else
+ {
+ //clock source is from PCLK
+ SystemCoreClockUpdate();
+ u32PWMClockSrc = SystemCoreClock;
+ }
+
+ u32PWMClockSrc /= 1000;
+ for(u16Prescale = 1; u16Prescale <= 0x1000; u16Prescale++)
+ {
+ u32NearestUnitTimeNsec = (1000000 * u16Prescale) / u32PWMClockSrc;
+ if(u32NearestUnitTimeNsec < u32UnitTimeNsec)
+ {
+ if(u16Prescale == 0x1000) //limit to the maximum unit time(nano second)
+ break;
+ if(!((1000000 * (u16Prescale + 1) > (u32NearestUnitTimeNsec * u32PWMClockSrc))))
+ break;
+ continue;
+ }
+ break;
+ }
+
+ // convert to real register value
+ // every two channels share a prescaler
+ PWM_SET_PRESCALER(pwm, u32ChannelNum, --u16Prescale);
+
+ // set PWM to down count type(edge aligned)
+ (pwm)->CTL1 = ((pwm)->CTL1 & ~(PWM_CTL1_CNTTYPE0_Msk << (2 * u32ChannelNum))) | (1UL << (2 * u32ChannelNum));
+ // set PWM to auto-reload mode
+ (pwm)->CTL1 &= ~(PWM_CTL1_CNTMODE0_Msk << u32ChannelNum);
+ PWM_SET_CNR(pwm, u32ChannelNum, u16CNR);
+
+ return (u32NearestUnitTimeNsec);
+}
+
+/**
+ * @brief This function Configure PWM generator and get the nearest frequency in edge aligned auto-reload mode
+ * @param[in] pwm The pointer of the specified PWM module
+ * - PWM0 : PWM Group 0
+ * - PWM1 : PWM Group 1
+ * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
+ * @param[in] u32Frequency Target generator frequency
+ * @param[in] u32DutyCycle Target generator duty cycle percentage. Valid range are between 0 ~ 100. 10 means 10%, 20 means 20%...
+ * @return Nearest frequency clock in nano second
+ * @note Since every two channels, (0 & 1), (2 & 3), shares a prescaler. Call this API to configure PWM frequency may affect
+ * existing frequency of other channel.
+ */
+uint32_t PWM_ConfigOutputChannel(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Frequency, uint32_t u32DutyCycle)
+{
+ uint32_t u32Src;
+ uint32_t u32PWMClockSrc;
+ uint32_t i;
+ uint16_t u16Prescale = 1, u16CNR = 0xFFFF;
+
+ if(pwm == PWM0)
+ u32Src = CLK->CLKSEL2 & CLK_CLKSEL2_PWM0SEL_Msk;
+ else//(pwm == PWM1)
+ u32Src = CLK->CLKSEL2 & CLK_CLKSEL2_PWM1SEL_Msk;
+
+ if(u32Src == 0)
+ {
+ //clock source is from PLL clock
+ u32PWMClockSrc = CLK_GetPLLClockFreq();
+ }
+ else
+ {
+ //clock source is from PCLK
+ SystemCoreClockUpdate();
+ u32PWMClockSrc = SystemCoreClock;
+ }
+
+ for(u16Prescale = 1; u16Prescale < 0xFFF; u16Prescale++)//prescale could be 0~0xFFF
+ {
+ i = (u32PWMClockSrc / u32Frequency) / u16Prescale;
+ // If target value is larger than CNR, need to use a larger prescaler
+ if(i > (0x10000))
+ continue;
+
+ u16CNR = i;
+ break;
+ }
+ // Store return value here 'cos we're gonna change u16Prescale & u16CNR to the real value to fill into register
+ i = u32PWMClockSrc / (u16Prescale * u16CNR);
+
+ // convert to real register value
+ // every two channels share a prescaler
+ PWM_SET_PRESCALER(pwm, u32ChannelNum, --u16Prescale);
+ // set PWM to down count type(edge aligned)
+ (pwm)->CTL1 = ((pwm)->CTL1 & ~(PWM_CTL1_CNTTYPE0_Msk << (2 * u32ChannelNum))) | (1UL << (2 * u32ChannelNum));
+ // set PWM to auto-reload mode
+ (pwm)->CTL1 &= ~(PWM_CTL1_CNTMODE0_Msk << u32ChannelNum);
+
+ PWM_SET_CNR(pwm, u32ChannelNum, --u16CNR);
+ if(u32DutyCycle)
+ {
+ PWM_SET_CMR(pwm, u32ChannelNum, u32DutyCycle * (u16CNR + 1) / 100 - 1);
+ (pwm)->WGCTL0 &= ~((PWM_WGCTL0_PRDPCTL0_Msk | PWM_WGCTL0_ZPCTL0_Msk) << (u32ChannelNum * 2));
+ (pwm)->WGCTL0 |= (PWM_OUTPUT_LOW << (u32ChannelNum * 2 + PWM_WGCTL0_PRDPCTL0_Pos));
+ (pwm)->WGCTL1 &= ~((PWM_WGCTL1_CMPDCTL0_Msk | PWM_WGCTL1_CMPUCTL0_Msk) << (u32ChannelNum * 2));
+ (pwm)->WGCTL1 |= (PWM_OUTPUT_HIGH << (u32ChannelNum * 2 + PWM_WGCTL1_CMPDCTL0_Pos));
+ }
+ else
+ {
+ PWM_SET_CMR(pwm, u32ChannelNum, 0);
+ (pwm)->WGCTL0 &= ~((PWM_WGCTL0_PRDPCTL0_Msk | PWM_WGCTL0_ZPCTL0_Msk) << (u32ChannelNum * 2));
+ (pwm)->WGCTL0 |= (PWM_OUTPUT_LOW << (u32ChannelNum * 2 + PWM_WGCTL0_ZPCTL0_Pos));
+ (pwm)->WGCTL1 &= ~((PWM_WGCTL1_CMPDCTL0_Msk | PWM_WGCTL1_CMPUCTL0_Msk) << (u32ChannelNum * 2));
+ (pwm)->WGCTL1 |= (PWM_OUTPUT_HIGH << (u32ChannelNum * 2 + PWM_WGCTL1_CMPDCTL0_Pos));
+ }
+
+ return(i);
+}
+
+/**
+ * @brief Start PWM module
+ * @param[in] pwm The pointer of the specified PWM module
+ * - PWM0 : PWM Group 0
+ * - PWM1 : PWM Group 1
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel.
+ * Bit 0 is channel 0, bit 1 is channel 1...
+ * @return None
+ * @details This function is used to start PWM module.
+ */
+void PWM_Start(PWM_T *pwm, uint32_t u32ChannelMask)
+{
+ (pwm)->CNTEN |= u32ChannelMask;
+}
+
+/**
+ * @brief Stop PWM module
+ * @param[in] pwm The pointer of the specified PWM module
+ * - PWM0 : PWM Group 0
+ * - PWM1 : PWM Group 1
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel.
+ * Bit 0 is channel 0, bit 1 is channel 1...
+ * @return None
+ * @details This function is used to stop PWM module.
+ */
+void PWM_Stop(PWM_T *pwm, uint32_t u32ChannelMask)
+{
+ uint32_t i;
+ for(i = 0; i < PWM_CHANNEL_NUM; i ++)
+ {
+ if(u32ChannelMask & (1 << i))
+ {
+ (pwm)->PERIOD[i] = 0;
+ }
+ }
+}
+
+/**
+ * @brief Stop PWM generation immediately by clear channel enable bit
+ * @param[in] pwm The pointer of the specified PWM module
+ * - PWM0 : PWM Group 0
+ * - PWM1 : PWM Group 1
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel.
+ * Bit 0 is channel 0, bit 1 is channel 1...
+ * @return None
+ * @details This function is used to stop PWM generation immediately by clear channel enable bit.
+ */
+void PWM_ForceStop(PWM_T *pwm, uint32_t u32ChannelMask)
+{
+ (pwm)->CNTEN &= ~u32ChannelMask;
+}
+
+/**
+ * @brief Enable selected channel to trigger EADC
+ * @param[in] pwm The pointer of the specified PWM module
+ * - PWM0 : PWM Group 0
+ * - PWM1 : PWM Group 1
+ * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
+ * @param[in] u32Condition The condition to trigger EADC. Combination of following conditions:
+ * - \ref PWM_TRIGGER_ADC_EVEN_ZERO_POINT
+ * - \ref PWM_TRIGGER_ADC_EVEN_PERIOD_POINT
+ * - \ref PWM_TRIGGER_ADC_EVEN_ZERO_OR_PERIOD_POINT
+ * - \ref PWM_TRIGGER_ADC_EVEN_COMPARE_UP_COUNT_POINT
+ * - \ref PWM_TRIGGER_ADC_EVEN_COMPARE_DOWN_COUNT_POINT
+ * - \ref PWM_TRIGGER_ADC_ODD_ZERO_POINT
+ * - \ref PWM_TRIGGER_ADC_ODD_PERIOD_POINT
+ * - \ref PWM_TRIGGER_ADC_ODD_ZERO_OR_PERIOD_POINT
+ * - \ref PWM_TRIGGER_ADC_ODD_COMPARE_UP_COUNT_POINT
+ * - \ref PWM_TRIGGER_ADC_ODD_COMPARE_DOWN_COUNT_POINT
+ * - \ref PWM_TRIGGER_ADC_CH_0_FREE_COMPARE_UP_COUNT_POINT
+ * - \ref PWM_TRIGGER_ADC_CH_0_FREE_COMPARE_DOWN_COUNT_POINT
+ * - \ref PWM_TRIGGER_ADC_CH_2_FREE_COMPARE_UP_COUNT_POINT
+ * - \ref PWM_TRIGGER_ADC_CH_2_FREE_COMPARE_DOWN_COUNT_POINT
+ * - \ref PWM_TRIGGER_ADC_CH_4_FREE_COMPARE_UP_COUNT_POINT
+ * - \ref PWM_TRIGGER_ADC_CH_4_FREE_COMPARE_DOWN_COUNT_POINT
+ * @return None
+ * @details This function is used to enable selected channel to trigger EADC.
+ */
+void PWM_EnableADCTrigger(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Condition)
+{
+ if(u32ChannelNum < 4)
+ {
+ (pwm)->EADCTS0 &= ~((PWM_EADCTS0_TRGSEL0_Msk) << (u32ChannelNum * 8));
+ (pwm)->EADCTS0 |= ((PWM_EADCTS0_TRGEN0_Msk | u32Condition) << (u32ChannelNum * 8));
+ }
+ else
+ {
+ (pwm)->EADCTS1 &= ~((PWM_EADCTS1_TRGSEL4_Msk) << ((u32ChannelNum - 4) * 8));
+ (pwm)->EADCTS1 |= ((PWM_EADCTS1_TRGEN4_Msk | u32Condition) << ((u32ChannelNum - 4) * 8));
+ }
+}
+
+/**
+ * @brief Disable selected channel to trigger EADC
+ * @param[in] pwm The pointer of the specified PWM module
+ * - PWM0 : PWM Group 0
+ * - PWM1 : PWM Group 1
+ * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
+ * @return None
+ * @details This function is used to disable selected channel to trigger EADC.
+ */
+void PWM_DisableADCTrigger(PWM_T *pwm, uint32_t u32ChannelNum)
+{
+ if(u32ChannelNum < 4)
+ {
+ (pwm)->EADCTS0 &= ~(PWM_EADCTS0_TRGEN0_Msk << (u32ChannelNum * 8));
+ }
+ else
+ {
+ (pwm)->EADCTS1 &= ~(PWM_EADCTS1_TRGEN4_Msk << ((u32ChannelNum - 4) * 8));
+ }
+}
+
+/**
+ * @brief Clear selected channel trigger EADC flag
+ * @param[in] pwm The pointer of the specified PWM module
+ * - PWM0 : PWM Group 0
+ * - PWM1 : PWM Group 1
+ * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
+ * @param[in] u32Condition This parameter is not used
+ * @return None
+ * @details This function is used to clear selected channel trigger EADC flag.
+ */
+void PWM_ClearADCTriggerFlag(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Condition)
+{
+ (pwm)->STATUS = (PWM_STATUS_ADCTRGF0_Msk << u32ChannelNum);
+}
+
+/**
+ * @brief Get selected channel trigger EADC flag
+ * @param[in] pwm The pointer of the specified PWM module
+ * - PWM0 : PWM Group 0
+ * - PWM1 : PWM Group 1
+ * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
+ * @retval 0 The specified channel trigger EADC to start of conversion flag is not set
+ * @retval 1 The specified channel trigger EADC to start of conversion flag is set
+ * @details This function is used to get PWM trigger EADC to start of conversion flag for specified channel.
+ */
+uint32_t PWM_GetADCTriggerFlag(PWM_T *pwm, uint32_t u32ChannelNum)
+{
+ return (((pwm)->STATUS & (PWM_STATUS_ADCTRGF0_Msk << u32ChannelNum)) ? 1 : 0);
+}
+
+/**
+ * @brief Enable selected channel to trigger DAC
+ * @param[in] pwm The pointer of the specified PWM module
+ * - PWM0 : PWM Group 0
+ * - PWM1 : PWM Group 1
+ * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
+ * @param[in] u32Condition The condition to trigger DAC. Combination of following conditions:
+ * - \ref PWM_TRIGGER_DAC_ZERO_POINT
+ * - \ref PWM_TRIGGER_DAC_PERIOD_POINT
+ * - \ref PWM_TRIGGER_DAC_COMPARE_UP_COUNT_POINT
+ * - \ref PWM_TRIGGER_DAC_COMPARE_DOWN_COUNT_POINT
+ * @return None
+ * @details This function is used to enable selected channel to trigger DAC.
+ */
+void PWM_EnableDACTrigger(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Condition)
+{
+ (pwm)->DACTRGEN |= (u32Condition << u32ChannelNum);
+}
+
+/**
+ * @brief Disable selected channel to trigger DAC
+ * @param[in] pwm The pointer of the specified PWM module
+ * - PWM0 : PWM Group 0
+ * - PWM1 : PWM Group 1
+ * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
+ * @return None
+ * @details This function is used to disable selected channel to trigger DAC.
+ */
+void PWM_DisableDACTrigger(PWM_T *pwm, uint32_t u32ChannelNum)
+{
+ (pwm)->DACTRGEN &= ~((PWM_TRIGGER_DAC_ZERO_POINT | PWM_TRIGGER_DAC_PERIOD_POINT | PWM_TRIGGER_DAC_COMPARE_UP_COUNT_POINT | \
+ PWM_TRIGGER_DAC_COMPARE_DOWN_COUNT_POINT) << u32ChannelNum);
+}
+
+/**
+ * @brief Clear selected channel trigger DAC flag
+ * @param[in] pwm The pointer of the specified PWM module
+ * - PWM0 : PWM Group 0
+ * - PWM1 : PWM Group 1
+ * @param[in] u32ChannelNum PWM channel number. This parameter is not used
+ * @param[in] u32Condition The condition to trigger DAC. This parameter is not used
+ * @return None
+ * @details This function is used to clear selected channel trigger DAC flag.
+ */
+void PWM_ClearDACTriggerFlag(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Condition)
+{
+ (pwm)->STATUS = PWM_STATUS_DACTRGF_Msk;
+}
+
+/**
+ * @brief Get selected channel trigger DAC flag
+ * @param[in] pwm The pointer of the specified PWM module
+ * - PWM0 : PWM Group 0
+ * - PWM1 : PWM Group 1
+ * @param[in] u32ChannelNum PWM channel number. This parameter is not used
+ * @retval 0 The specified channel trigger DAC to start of conversion flag is not set
+ * @retval 1 The specified channel trigger DAC to start of conversion flag is set
+ * @details This function is used to get selected channel trigger DAC flag.
+ */
+uint32_t PWM_GetDACTriggerFlag(PWM_T *pwm, uint32_t u32ChannelNum)
+{
+ return (((pwm)->STATUS & PWM_STATUS_DACTRGF_Msk) ? 1 : 0);
+}
+
+/**
+ * @brief This function enable fault brake of selected channel(s)
+ * @param[in] pwm The pointer of the specified PWM module
+ * - PWM0 : PWM Group 0
+ * - PWM1 : PWM Group 1
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel.
+ * @param[in] u32LevelMask Output high or low while fault brake occurs, each bit represent the level of a channel
+ * while fault brake occurs. Bit 0 represents channel 0, bit 1 represents channel 1...
+ * @param[in] u32BrakeSource Fault brake source, could be one of following source
+ * - \ref PWM_FB_EDGE_ACMP0
+ * - \ref PWM_FB_EDGE_ACMP1
+ * - \ref PWM_FB_EDGE_BKP0
+ * - \ref PWM_FB_EDGE_BKP1
+ * - \ref PWM_FB_EDGE_SYS_CSS
+ * - \ref PWM_FB_EDGE_SYS_BOD
+ * - \ref PWM_FB_EDGE_SYS_RAM
+ * - \ref PWM_FB_EDGE_SYS_COR
+ * - \ref PWM_FB_LEVEL_ACMP0
+ * - \ref PWM_FB_LEVEL_ACMP1
+ * - \ref PWM_FB_LEVEL_BKP0
+ * - \ref PWM_FB_LEVEL_BKP1
+ * - \ref PWM_FB_LEVEL_SYS_CSS
+ * - \ref PWM_FB_LEVEL_SYS_BOD
+ * - \ref PWM_FB_LEVEL_SYS_RAM
+ * - \ref PWM_FB_LEVEL_SYS_COR
+ * @return None
+ * @details This function is used to enable fault brake of selected channel(s).
+ * The write-protection function should be disabled before using this function.
+ */
+void PWM_EnableFaultBrake(PWM_T *pwm, uint32_t u32ChannelMask, uint32_t u32LevelMask, uint32_t u32BrakeSource)
+{
+ uint32_t i;
+ for(i = 0; i < PWM_CHANNEL_NUM; i ++)
+ {
+ if(u32ChannelMask & (1 << i))
+ {
+ if((u32BrakeSource == PWM_FB_EDGE_SYS_CSS) || (u32BrakeSource == PWM_FB_EDGE_SYS_BOD) || \
+ (u32BrakeSource == PWM_FB_EDGE_SYS_RAM) || (u32BrakeSource == PWM_FB_EDGE_SYS_COR) || \
+ (u32BrakeSource == PWM_FB_LEVEL_SYS_CSS) || (u32BrakeSource == PWM_FB_LEVEL_SYS_BOD) || \
+ (u32BrakeSource == PWM_FB_LEVEL_SYS_RAM) || (u32BrakeSource == PWM_FB_LEVEL_SYS_COR))
+ {
+ *(__IO uint32_t *)(&((pwm)->BRKCTL0_1) + (i >> 1)) |= (u32BrakeSource & (PWM_BRKCTL0_1_SYSEBEN_Msk | PWM_BRKCTL0_1_SYSLBEN_Msk));
+ (pwm)->FAILBRK |= (u32BrakeSource & 0xF);
+ }
+ else
+ {
+ *(__IO uint32_t *)(&((pwm)->BRKCTL0_1) + (i >> 1)) |= u32BrakeSource;
+ }
+ }
+
+ if(u32LevelMask & (1 << i))
+ {
+ if(i % 2 == 0)
+ {
+ //set brake action as high level for even channel
+ *(__IO uint32_t *)(&((pwm)->BRKCTL0_1) + (i >> 1)) &= ~PWM_BRKCTL0_1_BRKAEVEN_Msk;
+ *(__IO uint32_t *)(&((pwm)->BRKCTL0_1) + (i >> 1)) |= ((3UL) << PWM_BRKCTL0_1_BRKAEVEN_Pos);
+ }
+ else
+ {
+ //set brake action as high level for odd channel
+ *(__IO uint32_t *)(&((pwm)->BRKCTL0_1) + (i >> 1)) &= ~PWM_BRKCTL0_1_BRKAODD_Msk;
+ *(__IO uint32_t *)(&((pwm)->BRKCTL0_1) + (i >> 1)) |= ((3UL) << PWM_BRKCTL0_1_BRKAODD_Pos);
+ }
+ }
+ else
+ {
+ if(i % 2 == 0)
+ {
+ //set brake action as low level for even channel
+ *(__IO uint32_t *)(&((pwm)->BRKCTL0_1) + (i >> 1)) &= ~PWM_BRKCTL0_1_BRKAEVEN_Msk;
+ *(__IO uint32_t *)(&((pwm)->BRKCTL0_1) + (i >> 1)) |= ((2UL) << PWM_BRKCTL0_1_BRKAEVEN_Pos);
+ }
+ else
+ {
+ //set brake action as low level for odd channel
+ *(__IO uint32_t *)(&((pwm)->BRKCTL0_1) + (i >> 1)) &= ~PWM_BRKCTL0_1_BRKAODD_Msk;
+ *(__IO uint32_t *)(&((pwm)->BRKCTL0_1) + (i >> 1)) |= ((2UL) << PWM_BRKCTL0_1_BRKAODD_Pos);
+ }
+ }
+ }
+
+}
+
+/**
+ * @brief Enable capture of selected channel(s)
+ * @param[in] pwm The pointer of the specified PWM module
+ * - PWM0 : PWM Group 0
+ * - PWM1 : PWM Group 1
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel.
+ * Bit 0 is channel 0, bit 1 is channel 1...
+ * @return None
+ * @details This function is used to enable capture of selected channel(s).
+ */
+void PWM_EnableCapture(PWM_T *pwm, uint32_t u32ChannelMask)
+{
+ (pwm)->CAPINEN |= u32ChannelMask;
+ (pwm)->CAPCTL |= u32ChannelMask;
+}
+
+/**
+ * @brief Disable capture of selected channel(s)
+ * @param[in] pwm The pointer of the specified PWM module
+ * - PWM0 : PWM Group 0
+ * - PWM1 : PWM Group 1
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel.
+ * Bit 0 is channel 0, bit 1 is channel 1...
+ * @return None
+ * @details This function is used to disable capture of selected channel(s).
+ */
+void PWM_DisableCapture(PWM_T *pwm, uint32_t u32ChannelMask)
+{
+ (pwm)->CAPINEN &= ~u32ChannelMask;
+ (pwm)->CAPCTL &= ~u32ChannelMask;
+}
+
+/**
+ * @brief Enables PWM output generation of selected channel(s)
+ * @param[in] pwm The pointer of the specified PWM module
+ * - PWM0 : PWM Group 0
+ * - PWM1 : PWM Group 1
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel.
+ * Set bit 0 to 1 enables channel 0 output, set bit 1 to 1 enables channel 1 output...
+ * @return None
+ * @details This function is used to enable PWM output generation of selected channel(s).
+ */
+void PWM_EnableOutput(PWM_T *pwm, uint32_t u32ChannelMask)
+{
+ (pwm)->POEN |= u32ChannelMask;
+}
+
+/**
+ * @brief Disables PWM output generation of selected channel(s)
+ * @param[in] pwm The pointer of the specified PWM module
+ * - PWM0 : PWM Group 0
+ * - PWM1 : PWM Group 1
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
+ * Set bit 0 to 1 disables channel 0 output, set bit 1 to 1 disables channel 1 output...
+ * @return None
+ * @details This function is used to disable PWM output generation of selected channel(s).
+ */
+void PWM_DisableOutput(PWM_T *pwm, uint32_t u32ChannelMask)
+{
+ (pwm)->POEN &= ~u32ChannelMask;
+}
+
+/**
+ * @brief Enables PDMA transfer of selected channel for PWM capture
+ * @param[in] pwm The pointer of the specified PWM module
+ * - PWM0 : PWM Group 0
+ * - PWM1 : PWM Group 1
+ * @param[in] u32ChannelNum PWM channel number.
+ * @param[in] u32RisingFirst The capture order is rising, falling first. Every two channels share the same setting. Valid values are TRUE and FALSE.
+ * @param[in] u32Mode Captured data transferred by PDMA interrupt type. It could be either
+ * - \ref PWM_CAPTURE_PDMA_RISING_LATCH
+ * - \ref PWM_CAPTURE_PDMA_FALLING_LATCH
+ * - \ref PWM_CAPTURE_PDMA_RISING_FALLING_LATCH
+ * @return None
+ * @details This function is used to enable PDMA transfer of selected channel(s) for PWM capture.
+ * @note This function can only selects even or odd channel of pairs to do PDMA transfer.
+ */
+void PWM_EnablePDMA(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32RisingFirst, uint32_t u32Mode)
+{
+ uint32_t u32IsOddCh;
+ u32IsOddCh = u32ChannelNum % 2;
+ (pwm)->PDMACTL = ((pwm)->PDMACTL & ~((PWM_PDMACTL_CHSEL0_1_Msk | PWM_PDMACTL_CAPORD0_1_Msk | PWM_PDMACTL_CAPMOD0_1_Msk) << ((u32ChannelNum >> 1) * 8))) | \
+ (((u32IsOddCh << PWM_PDMACTL_CHSEL0_1_Pos) | (u32RisingFirst << PWM_PDMACTL_CAPORD0_1_Pos) | \
+ u32Mode | PWM_PDMACTL_CHEN0_1_Msk) << ((u32ChannelNum >> 1) * 8));
+}
+
+/**
+ * @brief Disables PDMA transfer of selected channel for PWM capture
+ * @param[in] pwm The pointer of the specified PWM module
+ * - PWM0 : PWM Group 0
+ * - PWM1 : PWM Group 1
+ * @param[in] u32ChannelNum PWM channel number.
+ * @return None
+ * @details This function is used to enable PDMA transfer of selected channel(s) for PWM capture.
+ */
+void PWM_DisablePDMA(PWM_T *pwm, uint32_t u32ChannelNum)
+{
+ (pwm)->PDMACTL &= ~(PWM_PDMACTL_CHEN0_1_Msk << ((u32ChannelNum >> 1) * 8));
+}
+
+/**
+ * @brief Enable Dead zone of selected channel
+ * @param[in] pwm The pointer of the specified PWM module
+ * - PWM0 : PWM Group 0
+ * - PWM1 : PWM Group 1
+ * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
+ * @param[in] u32Duration Dead zone length in PWM clock count, valid values are between 0~0xFFF, but 0 means there is no Dead zone.
+ * @return None
+ * @details This function is used to enable Dead zone of selected channel.
+ * The write-protection function should be disabled before using this function.
+ * @note Every two channels share the same setting.
+ */
+void PWM_EnableDeadZone(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Duration)
+{
+ // every two channels share the same setting
+ *(__IO uint32_t *)(&((pwm)->DTCTL0_1) + (u32ChannelNum >> 1)) &= ~PWM_DTCTL0_1_DTCNT_Msk;
+ *(__IO uint32_t *)(&((pwm)->DTCTL0_1) + (u32ChannelNum >> 1)) |= PWM_DTCTL0_1_DTEN_Msk | u32Duration;
+}
+
+/**
+ * @brief Disable Dead zone of selected channel
+ * @param[in] pwm The pointer of the specified PWM module
+ * - PWM0 : PWM Group 0
+ * - PWM1 : PWM Group 1
+ * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
+ * @return None
+ * @details This function is used to disable Dead zone of selected channel.
+ * The write-protection function should be disabled before using this function.
+ */
+void PWM_DisableDeadZone(PWM_T *pwm, uint32_t u32ChannelNum)
+{
+ // every two channels shares the same setting
+ *(__IO uint32_t *)(&((pwm)->DTCTL0_1) + (u32ChannelNum >> 1)) &= ~PWM_DTCTL0_1_DTEN_Msk;
+}
+
+/**
+ * @brief Enable capture interrupt of selected channel.
+ * @param[in] pwm The pointer of the specified PWM module
+ * - PWM0 : PWM Group 0
+ * - PWM1 : PWM Group 1
+ * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
+ * @param[in] u32Edge Rising or falling edge to latch counter.
+ * - \ref PWM_CAPTURE_INT_RISING_LATCH
+ * - \ref PWM_CAPTURE_INT_FALLING_LATCH
+ * @return None
+ * @details This function is used to enable capture interrupt of selected channel.
+ */
+void PWM_EnableCaptureInt(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Edge)
+{
+ (pwm)->CAPIEN |= (u32Edge << u32ChannelNum);
+}
+
+/**
+ * @brief Disable capture interrupt of selected channel.
+ * @param[in] pwm The pointer of the specified PWM module
+ * - PWM0 : PWM Group 0
+ * - PWM1 : PWM Group 1
+ * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
+ * @param[in] u32Edge Rising or falling edge to latch counter.
+ * - \ref PWM_CAPTURE_INT_RISING_LATCH
+ * - \ref PWM_CAPTURE_INT_FALLING_LATCH
+ * @return None
+ * @details This function is used to disable capture interrupt of selected channel.
+ */
+void PWM_DisableCaptureInt(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Edge)
+{
+ (pwm)->CAPIEN &= ~(u32Edge << u32ChannelNum);
+}
+
+/**
+ * @brief Clear capture interrupt of selected channel.
+ * @param[in] pwm The pointer of the specified PWM module
+ * - PWM0 : PWM Group 0
+ * - PWM1 : PWM Group 1
+ * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
+ * @param[in] u32Edge Rising or falling edge to latch counter.
+ * - \ref PWM_CAPTURE_INT_RISING_LATCH
+ * - \ref PWM_CAPTURE_INT_FALLING_LATCH
+ * @return None
+ * @details This function is used to clear capture interrupt of selected channel.
+ */
+void PWM_ClearCaptureIntFlag(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Edge)
+{
+ (pwm)->CAPIF = (u32Edge << u32ChannelNum);
+}
+
+/**
+ * @brief Get capture interrupt of selected channel.
+ * @param[in] pwm The pointer of the specified PWM module
+ * - PWM0 : PWM Group 0
+ * - PWM1 : PWM Group 1
+ * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
+ * @retval 0 No capture interrupt
+ * @retval 1 Rising edge latch interrupt
+ * @retval 2 Falling edge latch interrupt
+ * @retval 3 Rising and falling latch interrupt
+ * @details This function is used to get capture interrupt of selected channel.
+ */
+uint32_t PWM_GetCaptureIntFlag(PWM_T *pwm, uint32_t u32ChannelNum)
+{
+ return (((((pwm)->CAPIF & (PWM_CAPIF_CFLIF0_Msk << u32ChannelNum)) ? 1 : 0) << 1) | \
+ (((pwm)->CAPIF & (PWM_CAPIF_CRLIF0_Msk << u32ChannelNum)) ? 1 : 0));
+}
+/**
+ * @brief Enable duty interrupt of selected channel
+ * @param[in] pwm The pointer of the specified PWM module
+ * - PWM0 : PWM Group 0
+ * - PWM1 : PWM Group 1
+ * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
+ * @param[in] u32IntDutyType Duty interrupt type, could be either
+ * - \ref PWM_DUTY_INT_DOWN_COUNT_MATCH_CMP
+ * - \ref PWM_DUTY_INT_UP_COUNT_MATCH_CMP
+ * @return None
+ * @details This function is used to enable duty interrupt of selected channel.
+ */
+void PWM_EnableDutyInt(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32IntDutyType)
+{
+ (pwm)->INTEN0 |= (u32IntDutyType << u32ChannelNum);
+}
+
+/**
+ * @brief Disable duty interrupt of selected channel
+ * @param[in] pwm The pointer of the specified PWM module
+ * - PWM0 : PWM Group 0
+ * - PWM1 : PWM Group 1
+ * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
+ * @return None
+ * @details This function is used to disable duty interrupt of selected channel.
+ */
+void PWM_DisableDutyInt(PWM_T *pwm, uint32_t u32ChannelNum)
+{
+ (pwm)->INTEN0 &= ~((PWM_DUTY_INT_DOWN_COUNT_MATCH_CMP | PWM_DUTY_INT_UP_COUNT_MATCH_CMP) << u32ChannelNum);
+}
+
+/**
+ * @brief Clear duty interrupt flag of selected channel
+ * @param[in] pwm The pointer of the specified PWM module
+ * - PWM0 : PWM Group 0
+ * - PWM1 : PWM Group 1
+ * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
+ * @return None
+ * @details This function is used to clear duty interrupt flag of selected channel.
+ */
+void PWM_ClearDutyIntFlag(PWM_T *pwm, uint32_t u32ChannelNum)
+{
+ (pwm)->INTSTS0 = (PWM_INTSTS0_CMPUIF0_Msk | PWM_INTSTS0_CMPDIF0_Msk) << u32ChannelNum;
+}
+
+/**
+ * @brief Get duty interrupt flag of selected channel
+ * @param[in] pwm The pointer of the specified PWM module
+ * - PWM0 : PWM Group 0
+ * - PWM1 : PWM Group 1
+ * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
+ * @return Duty interrupt flag of specified channel
+ * @retval 0 Duty interrupt did not occur
+ * @retval 1 Duty interrupt occurred
+ * @details This function is used to get duty interrupt flag of selected channel.
+ */
+uint32_t PWM_GetDutyIntFlag(PWM_T *pwm, uint32_t u32ChannelNum)
+{
+ return ((((pwm)->INTSTS0 & ((PWM_INTSTS0_CMPDIF0_Msk | PWM_INTSTS0_CMPUIF0_Msk) << u32ChannelNum))) ? 1 : 0);
+}
+
+/**
+ * @brief This function enable fault brake interrupt
+ * @param[in] pwm The pointer of the specified PWM module
+ * @param[in] u32BrakeSource Fault brake source.
+ * - \ref PWM_FB_EDGE
+ * - \ref PWM_FB_LEVEL
+ * @return None
+ * @details This function is used to enable fault brake interrupt.
+ * The write-protection function should be disabled before using this function.
+ * @note Every two channels share the same setting.
+ */
+void PWM_EnableFaultBrakeInt(PWM_T *pwm, uint32_t u32BrakeSource)
+{
+ (pwm)->INTEN1 |= (0x7 << u32BrakeSource);
+}
+
+/**
+ * @brief This function disable fault brake interrupt
+ * @param[in] pwm The pointer of the specified PWM module
+ * @param[in] u32BrakeSource Fault brake source.
+ * - \ref PWM_FB_EDGE
+ * - \ref PWM_FB_LEVEL
+ * @return None
+ * @details This function is used to disable fault brake interrupt.
+ * The write-protection function should be disabled before using this function.
+ * @note Every two channels share the same setting.
+ */
+void PWM_DisableFaultBrakeInt(PWM_T *pwm, uint32_t u32BrakeSource)
+{
+ (pwm)->INTEN1 &= ~(0x7 << u32BrakeSource);
+}
+
+/**
+ * @brief This function clear fault brake interrupt of selected source
+ * @param[in] pwm The pointer of the specified PWM module
+ * @param[in] u32BrakeSource Fault brake source.
+ * - \ref PWM_FB_EDGE
+ * - \ref PWM_FB_LEVEL
+ * @return None
+ * @details This function is used to clear fault brake interrupt of selected source.
+ * The write-protection function should be disabled before using this function.
+ */
+void PWM_ClearFaultBrakeIntFlag(PWM_T *pwm, uint32_t u32BrakeSource)
+{
+ (pwm)->INTSTS1 = (0x3f << u32BrakeSource);
+}
+
+/**
+ * @brief This function get fault brake interrupt flag of selected source
+ * @param[in] pwm The pointer of the specified PWM module
+ * @param[in] u32BrakeSource Fault brake source, could be either
+ * - \ref PWM_FB_EDGE
+ * - \ref PWM_FB_LEVEL
+ * @return Fault brake interrupt flag of specified source
+ * @retval 0 Fault brake interrupt did not occurred
+ * @retval 1 Fault brake interrupt occurred
+ * @details This function is used to get fault brake interrupt flag of selected source.
+ */
+uint32_t PWM_GetFaultBrakeIntFlag(PWM_T *pwm, uint32_t u32BrakeSource)
+{
+ return (((pwm)->INTSTS1 & (0x3f << u32BrakeSource)) ? 1 : 0);
+}
+
+/**
+ * @brief Enable period interrupt of selected channel
+ * @param[in] pwm The pointer of the specified PWM module
+ * - PWM0 : PWM Group 0
+ * - PWM1 : PWM Group 1
+ * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
+ * @param[in] u32IntPeriodType Period interrupt type. This parameter is not used.
+ * @return None
+ * @details This function is used to enable period interrupt of selected channel.
+ */
+void PWM_EnablePeriodInt(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32IntPeriodType)
+{
+ (pwm)->INTEN0 |= (PWM_INTEN0_PIEN0_Msk << u32ChannelNum);
+}
+
+/**
+ * @brief Disable period interrupt of selected channel
+ * @param[in] pwm The pointer of the specified PWM module
+ * - PWM0 : PWM Group 0
+ * - PWM1 : PWM Group 1
+ * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
+ * @return None
+ * @details This function is used to disable period interrupt of selected channel.
+ */
+void PWM_DisablePeriodInt(PWM_T *pwm, uint32_t u32ChannelNum)
+{
+ (pwm)->INTEN0 &= ~(PWM_INTEN0_PIEN0_Msk << u32ChannelNum);
+}
+
+/**
+ * @brief Clear period interrupt of selected channel
+ * @param[in] pwm The pointer of the specified PWM module
+ * - PWM0 : PWM Group 0
+ * - PWM1 : PWM Group 1
+ * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
+ * @return None
+ * @details This function is used to clear period interrupt of selected channel.
+ */
+void PWM_ClearPeriodIntFlag(PWM_T *pwm, uint32_t u32ChannelNum)
+{
+ (pwm)->INTSTS0 = (PWM_INTSTS0_PIF0_Msk << u32ChannelNum);
+}
+
+/**
+ * @brief Get period interrupt of selected channel
+ * @param[in] pwm The pointer of the specified PWM module
+ * - PWM0 : PWM Group 0
+ * - PWM1 : PWM Group 1
+ * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
+ * @return Period interrupt flag of specified channel
+ * @retval 0 Period interrupt did not occur
+ * @retval 1 Period interrupt occurred
+ * @details This function is used to get period interrupt of selected channel.
+ */
+uint32_t PWM_GetPeriodIntFlag(PWM_T *pwm, uint32_t u32ChannelNum)
+{
+ return ((((pwm)->INTSTS0 & (PWM_INTSTS0_PIF0_Msk << u32ChannelNum))) ? 1 : 0);
+}
+
+/**
+ * @brief Enable zero interrupt of selected channel
+ * @param[in] pwm The pointer of the specified PWM module
+ * - PWM0 : PWM Group 0
+ * - PWM1 : PWM Group 1
+ * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
+ * @return None
+ * @details This function is used to enable zero interrupt of selected channel.
+ */
+void PWM_EnableZeroInt(PWM_T *pwm, uint32_t u32ChannelNum)
+{
+ (pwm)->INTEN0 |= (PWM_INTEN0_ZIEN0_Msk << u32ChannelNum);
+}
+
+/**
+ * @brief Disable zero interrupt of selected channel
+ * @param[in] pwm The pointer of the specified PWM module
+ * - PWM0 : PWM Group 0
+ * - PWM1 : PWM Group 1
+ * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
+ * @return None
+ * @details This function is used to disable zero interrupt of selected channel.
+ */
+void PWM_DisableZeroInt(PWM_T *pwm, uint32_t u32ChannelNum)
+{
+ (pwm)->INTEN0 &= ~(PWM_INTEN0_ZIEN0_Msk << u32ChannelNum);
+}
+
+/**
+ * @brief Clear zero interrupt of selected channel
+ * @param[in] pwm The pointer of the specified PWM module
+ * - PWM0 : PWM Group 0
+ * - PWM1 : PWM Group 1
+ * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
+ * @return None
+ * @details This function is used to clear zero interrupt of selected channel.
+ */
+void PWM_ClearZeroIntFlag(PWM_T *pwm, uint32_t u32ChannelNum)
+{
+ (pwm)->INTSTS0 = (PWM_INTSTS0_ZIF0_Msk << u32ChannelNum);
+}
+
+/**
+ * @brief Get zero interrupt of selected channel
+ * @param[in] pwm The pointer of the specified PWM module
+ * - PWM0 : PWM Group 0
+ * - PWM1 : PWM Group 1
+ * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
+ * @return Zero interrupt flag of specified channel
+ * @retval 0 Zero interrupt did not occur
+ * @retval 1 Zero interrupt occurred
+ * @details This function is used to get zero interrupt of selected channel.
+ */
+uint32_t PWM_GetZeroIntFlag(PWM_T *pwm, uint32_t u32ChannelNum)
+{
+ return ((((pwm)->INTSTS0 & (PWM_INTSTS0_ZIF0_Msk << u32ChannelNum))) ? 1 : 0);
+}
+
+/**
+ * @brief Enable interrupt flag accumulator of selected channel
+ * @param[in] pwm The pointer of the specified PWM module
+ * - PWM0 : PWM Group 0
+ * - PWM1 : PWM Group 1
+ * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
+ * @param[in] u32IntFlagCnt Interrupt flag counter. Valid values are between 0~15.
+ * @param[in] u32IntAccSrc Interrupt flag accumulator source selection.
+ * - \ref PWM_IFA_EVEN_ZERO_POINT
+ * - \ref PWM_IFA_EVEN_PERIOD_POINT
+ * - \ref PWM_IFA_EVEN_COMPARE_UP_COUNT_POINT
+ * - \ref PWM_IFA_EVEN_COMPARE_DOWN_COUNT_POINT
+ * - \ref PWM_IFA_ODD_ZERO_POINT
+ * - \ref PWM_IFA_ODD_PERIOD_POINT
+ * - \ref PWM_IFA_ODD_COMPARE_UP_COUNT_POINT
+ * - \ref PWM_IFA_ODD_COMPARE_DOWN_COUNT_POINT
+ * @return None
+ * @details This function is used to enable interrupt flag accumulator of selected channel.
+ * @note Every two channels share the same setting.
+ */
+void PWM_EnableAcc(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32IntFlagCnt, uint32_t u32IntAccSrc)
+{
+ (pwm)->IFA = ((pwm)->IFA & ~((PWM_IFA_IFCNT0_1_Msk | PWM_IFA_IFSEL0_1_Msk) << ((u32ChannelNum >> 1) * 8))) | \
+ ((PWM_IFA_IFAEN0_1_Msk | (u32IntAccSrc << PWM_IFA_IFSEL0_1_Pos) | u32IntFlagCnt) << ((u32ChannelNum >> 1) * 8));
+}
+
+/**
+ * @brief Disable interrupt flag accumulator of selected channel
+ * @param[in] pwm The pointer of the specified PWM module
+ * - PWM0 : PWM Group 0
+ * - PWM1 : PWM Group 1
+ * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
+ * @return None
+ * @details This function is used to Disable interrupt flag accumulator of selected channel.
+ * @note Every two channels share the same setting.
+ */
+void PWM_DisableAcc(PWM_T *pwm, uint32_t u32ChannelNum)
+{
+ (pwm)->IFA = (pwm)->IFA & ~(PWM_IFA_IFAEN0_1_Msk << ((u32ChannelNum >> 1) * 8));
+}
+
+/**
+ * @brief Enable interrupt flag accumulator interrupt of selected channel
+ * @param[in] pwm The pointer of the specified PWM module
+ * - PWM0 : PWM Group 0
+ * - PWM1 : PWM Group 1
+ * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
+ * @return None
+ * @details This function is used to enable interrupt flag accumulator interrupt of selected channel.
+ * @note Every two channels share the same setting.
+ */
+void PWM_EnableAccInt(PWM_T *pwm, uint32_t u32ChannelNum)
+{
+ (pwm)->INTEN0 |= (PWM_INTEN0_IFAIEN0_1_Msk << ((u32ChannelNum >> 1) * 8));
+}
+
+/**
+ * @brief Disable interrupt flag accumulator interrupt of selected channel
+ * @param[in] pwm The pointer of the specified PWM module
+ * - PWM0 : PWM Group 0
+ * - PWM1 : PWM Group 1
+ * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
+ * @return None
+ * @details This function is used to disable interrupt flag accumulator interrupt of selected channel.
+ * @note Every two channels share the same setting.
+ */
+void PWM_DisableAccInt(PWM_T *pwm, uint32_t u32ChannelNum)
+{
+ (pwm)->INTEN0 &= ~(PWM_INTEN0_IFAIEN0_1_Msk << ((u32ChannelNum >> 1) * 8));
+}
+
+/**
+ * @brief Clear interrupt flag accumulator interrupt of selected channel
+ * @param[in] pwm The pointer of the specified PWM module
+ * - PWM0 : PWM Group 0
+ * - PWM1 : PWM Group 1
+ * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
+ * @return None
+ * @details This function is used to clear interrupt flag accumulator interrupt of selected channel.
+ * @note Every two channels share the same setting.
+ */
+void PWM_ClearAccInt(PWM_T *pwm, uint32_t u32ChannelNum)
+{
+ (pwm)->INTSTS0 = (PWM_INTSTS0_IFAIF0_1_Msk << ((u32ChannelNum >> 1) * 8));
+}
+
+/**
+ * @brief Get interrupt flag accumulator interrupt of selected channel
+ * @param[in] pwm The pointer of the specified PWM module
+ * - PWM0 : PWM Group 0
+ * - PWM1 : PWM Group 1
+ * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
+ * @retval 0 Accumulator interrupt did not occur
+ * @retval 1 Accumulator interrupt occurred
+ * @details This function is used to Get interrupt flag accumulator interrupt of selected channel.
+ * @note Every two channels share the same setting.
+ */
+uint32_t PWM_GetAccInt(PWM_T *pwm, uint32_t u32ChannelNum)
+{
+ return (((pwm)->INTSTS0 & (PWM_INTSTS0_IFAIF0_1_Msk << ((u32ChannelNum >> 1) * 8))) ? 1 : 0);
+}
+
+/**
+ * @brief Clear free trigger duty interrupt flag of selected channel
+ * @param[in] pwm The pointer of the specified PWM module
+ * - PWM0 : PWM Group 0
+ * - PWM1 : PWM Group 1
+ * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
+ * @return None
+ * @details This function is used to clear free trigger duty interrupt flag of selected channel.
+ */
+void PWM_ClearFTDutyIntFlag(PWM_T *pwm, uint32_t u32ChannelNum)
+{
+ (pwm)->FTCI = ((PWM_FTCI_FTCMU0_Msk | PWM_FTCI_FTCMD0_Msk) << (u32ChannelNum >> 1));
+}
+
+/**
+ * @brief Get free trigger duty interrupt flag of selected channel
+ * @param[in] pwm The pointer of the specified PWM module
+ * - PWM0 : PWM Group 0
+ * - PWM1 : PWM Group 1
+ * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
+ * @return Duty interrupt flag of specified channel
+ * @retval 0 Free trigger duty interrupt did not occur
+ * @retval 1 Free trigger duty interrupt occurred
+ * @details This function is used to get free trigger duty interrupt flag of selected channel.
+ */
+uint32_t PWM_GetFTDutyIntFlag(PWM_T *pwm, uint32_t u32ChannelNum)
+{
+ return (((pwm)->FTCI & ((PWM_FTCI_FTCMU0_Msk | PWM_FTCI_FTCMD0_Msk) << (u32ChannelNum >> 1))) ? 1 : 0);
+}
+
+/**
+ * @brief Enable load mode of selected channel
+ * @param[in] pwm The pointer of the specified PWM module
+ * - PWM0 : PWM Group 0
+ * - PWM1 : PWM Group 1
+ * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
+ * @param[in] u32LoadMode PWM counter loading mode.
+ * - \ref PWM_LOAD_MODE_IMMEDIATE
+ * - \ref PWM_LOAD_MODE_WINDOW
+ * - \ref PWM_LOAD_MODE_CENTER
+ * @return None
+ * @details This function is used to enable load mode of selected channel.
+ */
+void PWM_EnableLoadMode(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32LoadMode)
+{
+ (pwm)->CTL0 |= (u32LoadMode << u32ChannelNum);
+}
+
+/**
+ * @brief Disable load mode of selected channel
+ * @param[in] pwm The pointer of the specified PWM module
+ * - PWM0 : PWM Group 0
+ * - PWM1 : PWM Group 1
+ * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
+ * @param[in] u32LoadMode PWM counter loading mode.
+ * - \ref PWM_LOAD_MODE_IMMEDIATE
+ * - \ref PWM_LOAD_MODE_WINDOW
+ * - \ref PWM_LOAD_MODE_CENTER
+ * @return None
+ * @details This function is used to disable load mode of selected channel.
+ */
+void PWM_DisableLoadMode(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32LoadMode)
+{
+ (pwm)->CTL0 &= ~(u32LoadMode << u32ChannelNum);
+}
+
+/**
+ * @brief Configure synchronization phase of selected channel
+ * @param[in] pwm The pointer of the specified PWM module
+ * - PWM0 : PWM Group 0
+ * - PWM1 : PWM Group 1
+ * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
+ * @param[in] u32SyncSrc PWM synchronize source selection.
+ * - \ref PWM_SYNC_OUT_FROM_SYNCIN_SWSYNC
+ * - \ref PWM_SYNC_OUT_FROM_COUNT_TO_ZERO
+ * - \ref PWM_SYNC_OUT_FROM_COUNT_TO_COMPARATOR
+ * - \ref PWM_SYNC_OUT_DISABLE
+ * @param[in] u32Direction Phase direction. Control PWM counter count decrement or increment after synchronizing.
+ * - \ref PWM_PHS_DIR_DECREMENT
+ * - \ref PWM_PHS_DIR_INCREMENT
+ * @param[in] u32StartPhase Synchronous start phase value. Valid values are between 0~65535.
+ * @return None
+ * @details This function is used to configure synchronization phase of selected channel.
+ * @note Every two channels share the same setting.
+ */
+void PWM_ConfigSyncPhase(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32SyncSrc, uint32_t u32Direction, uint32_t u32StartPhase)
+{
+ // every two channels shares the same setting
+ u32ChannelNum >>= 1;
+ (pwm)->SYNC = (((pwm)->SYNC & ~((PWM_SYNC_SINSRC0_Msk << (u32ChannelNum << 1)) | (PWM_SYNC_PHSDIR0_Msk << u32ChannelNum))) | \
+ (u32Direction << PWM_SYNC_PHSDIR0_Pos << u32ChannelNum) | (u32SyncSrc << PWM_SYNC_SINSRC0_Pos) << (u32ChannelNum << 1));
+ *(__IO uint32_t *)(&((pwm)->PHS0_1) + u32ChannelNum) = u32StartPhase;
+}
+
+
+/**
+ * @brief Enable SYNC phase of selected channel(s)
+ * @param[in] pwm The pointer of the specified PWM module
+ * - PWM0 : PWM Group 0
+ * - PWM1 : PWM Group 1
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel.
+ * Bit 0 is channel 0, bit 1 is channel 1...
+ * @return None
+ * @details This function is used to enable SYNC phase of selected channel(s).
+ * @note Every two channels share the same setting.
+ */
+void PWM_EnableSyncPhase(PWM_T *pwm, uint32_t u32ChannelMask)
+{
+ uint32_t i;
+ for(i = 0; i < PWM_CHANNEL_NUM; i ++)
+ {
+ if(u32ChannelMask & (1 << i))
+ {
+ (pwm)->SYNC |= (PWM_SYNC_PHSEN0_Msk << (i >> 1));
+ }
+ }
+}
+
+/**
+ * @brief Disable SYNC phase of selected channel(s)
+ * @param[in] pwm The pointer of the specified PWM module
+ * - PWM0 : PWM Group 0
+ * - PWM1 : PWM Group 1
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel.
+ * Bit 0 is channel 0, bit 1 is channel 1...
+ * @return None
+ * @details This function is used to disable SYNC phase of selected channel(s).
+ * @note Every two channels share the same setting.
+ */
+void PWM_DisableSyncPhase(PWM_T *pwm, uint32_t u32ChannelMask)
+{
+ uint32_t i;
+ for(i = 0; i < PWM_CHANNEL_NUM; i ++)
+ {
+ if(u32ChannelMask & (1 << i))
+ {
+ (pwm)->SYNC &= ~(PWM_SYNC_PHSEN0_Msk << (i >> 1));
+ }
+ }
+}
+
+/**
+ * @brief Enable PWM SYNC_IN noise filter function
+ * @param[in] pwm The pointer of the specified PWM module
+ * - PWM0 : PWM Group 0
+ * - PWM1 : PWM Group 1
+ * @param[in] u32ClkCnt SYNC Edge Detector Filter Count. This controls the counter number of edge detector.
+ * The valid value is 0~7.
+ * @param[in] u32ClkDivSel SYNC Edge Detector Filter Clock Selection.
+ * - \ref PWM_NF_CLK_DIV_1
+ * - \ref PWM_NF_CLK_DIV_2
+ * - \ref PWM_NF_CLK_DIV_4
+ * - \ref PWM_NF_CLK_DIV_8
+ * - \ref PWM_NF_CLK_DIV_16
+ * - \ref PWM_NF_CLK_DIV_32
+ * - \ref PWM_NF_CLK_DIV_64
+ * - \ref PWM_NF_CLK_DIV_128
+ * @return None
+ * @details This function is used to enable PWM SYNC_IN noise filter function.
+ */
+void PWM_EnableSyncNoiseFilter(PWM_T *pwm, uint32_t u32ClkCnt, uint32_t u32ClkDivSel)
+{
+ (pwm)->SYNC = ((pwm)->SYNC & ~(PWM_SYNC_SFLTCNT_Msk | PWM_SYNC_SFLTCSEL_Msk)) | \
+ ((u32ClkCnt << PWM_SYNC_SFLTCNT_Pos) | (u32ClkDivSel << PWM_SYNC_SFLTCSEL_Pos) | PWM_SYNC_SNFLTEN_Msk);
+}
+
+/**
+ * @brief Disable PWM SYNC_IN noise filter function
+ * @param[in] pwm The pointer of the specified PWM module
+ * - PWM0 : PWM Group 0
+ * - PWM1 : PWM Group 1
+ * @return None
+ * @details This function is used to Disable PWM SYNC_IN noise filter function.
+ */
+void PWM_DisableSyncNoiseFilter(PWM_T *pwm)
+{
+ (pwm)->SYNC &= ~PWM_SYNC_SNFLTEN_Msk;
+}
+
+/**
+ * @brief Enable PWM SYNC input pin inverse function
+ * @param[in] pwm The pointer of the specified PWM module
+ * - PWM0 : PWM Group 0
+ * - PWM1 : PWM Group 1
+ * @return None
+ * @details This function is used to enable PWM SYNC input pin inverse function.
+ */
+void PWM_EnableSyncPinInverse(PWM_T *pwm)
+{
+ (pwm)->SYNC |= PWM_SYNC_SINPINV_Msk;
+}
+
+/**
+ * @brief Disable PWM SYNC input pin inverse function
+ * @param[in] pwm The pointer of the specified PWM module
+ * - PWM0 : PWM Group 0
+ * - PWM1 : PWM Group 1
+ * @return None
+ * @details This function is used to Disable PWM SYNC input pin inverse function.
+ */
+void PWM_DisableSyncPinInverse(PWM_T *pwm)
+{
+ (pwm)->SYNC &= ~PWM_SYNC_SINPINV_Msk;
+}
+
+/**
+ * @brief Set PWM clock source
+ * @param[in] pwm The pointer of the specified PWM module
+ * - PWM0 : PWM Group 0
+ * - PWM1 : PWM Group 1
+ * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
+ * @param[in] u32ClkSrcSel PWM external clock source.
+ * - \ref PWM_CLKSRC_PWM_CLK
+ * - \ref PWM_CLKSRC_TIMER0
+ * - \ref PWM_CLKSRC_TIMER1
+ * - \ref PWM_CLKSRC_TIMER2
+ * - \ref PWM_CLKSRC_TIMER3
+ * @return None
+ * @details This function is used to set PWM clock source.
+ * @note Every two channels share the same setting.
+ */
+void PWM_SetClockSource(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32ClkSrcSel)
+{
+ (pwm)->CLKSRC = (pwm)->CLKSRC & ~(PWM_CLKSRC_ECLKSRC0_Msk << ((u32ChannelNum >> 1) * PWM_CLKSRC_ECLKSRC2_Pos)) | \
+ (u32ClkSrcSel << ((u32ChannelNum >> 1) * PWM_CLKSRC_ECLKSRC2_Pos));
+}
+
+/**
+ * @brief Enable PWM brake noise filter function
+ * @param[in] pwm The pointer of the specified PWM module
+ * - PWM0 : PWM Group 0
+ * - PWM1 : PWM Group 1
+ * @param[in] u32BrakePinNum Brake pin selection. Valid values are 0 or 1.
+ * @param[in] u32ClkCnt SYNC Edge Detector Filter Count. This controls the counter number of edge detector
+ * @param[in] u32ClkDivSel SYNC Edge Detector Filter Clock Selection.
+ * - \ref PWM_NF_CLK_DIV_1
+ * - \ref PWM_NF_CLK_DIV_2
+ * - \ref PWM_NF_CLK_DIV_4
+ * - \ref PWM_NF_CLK_DIV_8
+ * - \ref PWM_NF_CLK_DIV_16
+ * - \ref PWM_NF_CLK_DIV_32
+ * - \ref PWM_NF_CLK_DIV_64
+ * - \ref PWM_NF_CLK_DIV_128
+ * @return None
+ * @details This function is used to enable PWM brake noise filter function.
+ */
+void PWM_EnableBrakeNoiseFilter(PWM_T *pwm, uint32_t u32BrakePinNum, uint32_t u32ClkCnt, uint32_t u32ClkDivSel)
+{
+ (pwm)->BNF = ((pwm)->BNF & ~((PWM_BNF_BRK0FCNT_Msk | PWM_BNF_BRK0NFSEL_Msk) << (u32BrakePinNum * PWM_BNF_BRK1NFEN_Pos))) | \
+ (((u32ClkCnt << PWM_BNF_BRK0FCNT_Pos) | (u32ClkDivSel << PWM_BNF_BRK0NFSEL_Pos) | PWM_BNF_BRK0NFEN_Msk) << (u32BrakePinNum * PWM_BNF_BRK1NFEN_Pos));
+}
+
+/**
+ * @brief Disable PWM brake noise filter function
+ * @param[in] pwm The pointer of the specified PWM module
+ * - PWM0 : PWM Group 0
+ * - PWM1 : PWM Group 1
+ * @param[in] u32BrakePinNum Brake pin selection. Valid values are 0 or 1.
+ * @return None
+ * @details This function is used to disable PWM brake noise filter function.
+ */
+void PWM_DisableBrakeNoiseFilter(PWM_T *pwm, uint32_t u32BrakePinNum)
+{
+ (pwm)->BNF &= ~(PWM_BNF_BRK0NFEN_Msk << (u32BrakePinNum * PWM_BNF_BRK1NFEN_Pos));
+}
+
+/**
+ * @brief Enable PWM brake pin inverse function
+ * @param[in] pwm The pointer of the specified PWM module
+ * - PWM0 : PWM Group 0
+ * - PWM1 : PWM Group 1
+ * @param[in] u32BrakePinNum Brake pin selection. Valid values are 0 or 1.
+ * @return None
+ * @details This function is used to enable PWM brake pin inverse function.
+ */
+void PWM_EnableBrakePinInverse(PWM_T *pwm, uint32_t u32BrakePinNum)
+{
+ (pwm)->BNF |= (PWM_BNF_BRK0PINV_Msk << (u32BrakePinNum * PWM_BNF_BRK1NFEN_Pos));
+}
+
+/**
+ * @brief Disable PWM brake pin inverse function
+ * @param[in] pwm The pointer of the specified PWM module
+ * - PWM0 : PWM Group 0
+ * - PWM1 : PWM Group 1
+ * @param[in] u32BrakePinNum Brake pin selection. Valid values are 0 or 1.
+ * @return None
+ * @details This function is used to disable PWM brake pin inverse function.
+ */
+void PWM_DisableBrakePinInverse(PWM_T *pwm, uint32_t u32BrakePinNum)
+{
+ (pwm)->BNF &= ~(PWM_BNF_BRK0PINV_Msk << (u32BrakePinNum * PWM_BNF_BRK1NFEN_Pos));
+}
+
+/**
+ * @brief Set PWM brake pin source
+ * @param[in] pwm The pointer of the specified PWM module
+ * - PWM0 : PWM Group 0
+ * - PWM1 : PWM Group 1
+ * @param[in] u32BrakePinNum Brake pin selection. Valid values are 0 or 1.
+ * @param[in] u32SelAnotherModule Select to another module. Valid values are TRUE or FALSE.
+ * @return None
+ * @details This function is used to set PWM brake pin source.
+ * @note This function is only supported in M45xD/M45xC.
+ */
+void PWM_SetBrakePinSource(PWM_T *pwm, uint32_t u32BrakePinNum, uint32_t u32SelAnotherModule)
+{
+ (pwm)->BNF = ((pwm)->BNF & ~(PWM_BNF_BK0SRC_Msk << (u32BrakePinNum * 8))) | (u32SelAnotherModule << (PWM_BNF_BK0SRC_Pos + u32BrakePinNum * 8));
+}
+
+/**
+ * @brief Get the time-base counter reached its maximum value flag of selected channel
+ * @param[in] pwm The pointer of the specified PWM module
+ * - PWM0 : PWM Group 0
+ * - PWM1 : PWM Group 1
+ * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
+ * @return Count to max interrupt flag of specified channel
+ * @retval 0 Count to max interrupt did not occur
+ * @retval 1 Count to max interrupt occurred
+ * @details This function is used to get the time-base counter reached its maximum value flag of selected channel.
+ */
+uint32_t PWM_GetWrapAroundFlag(PWM_T *pwm, uint32_t u32ChannelNum)
+{
+ return (((pwm)->STATUS & (PWM_STATUS_CNTMAXF0_Msk << u32ChannelNum)) ? 1 : 0);
+}
+
+/**
+ * @brief Clear the time-base counter reached its maximum value flag of selected channel
+ * @param[in] pwm The pointer of the specified PWM module
+ * - PWM0 : PWM Group 0
+ * - PWM1 : PWM Group 1
+ * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
+ * @return None
+ * @details This function is used to clear the time-base counter reached its maximum value flag of selected channel.
+ */
+void PWM_ClearWrapAroundFlag(PWM_T *pwm, uint32_t u32ChannelNum)
+{
+ (pwm)->STATUS = (PWM_STATUS_CNTMAXF0_Msk << u32ChannelNum);
+}
+
+
+/*@}*/ /* end of group PWM_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group PWM_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+/*** (C) COPYRIGHT 2014~2015 Nuvoton Technology Corp. ***/
diff --git a/bsp/nuvoton_m451/Libraries/StdDriver/src/retarget.c b/bsp/nuvoton_m451/Libraries/StdDriver/src/retarget.c
new file mode 100644
index 0000000000000000000000000000000000000000..3aeb8aac2b03b5567092c6d6641deef6962f7b83
--- /dev/null
+++ b/bsp/nuvoton_m451/Libraries/StdDriver/src/retarget.c
@@ -0,0 +1,678 @@
+/**************************************************************************//**
+ * @file retarget.c
+ * @version V3.00
+ * $Revision: 13 $
+ * $Date: 15/08/11 10:26a $
+ * @brief M451 Series Debug Port and Semihost Setting Source File
+ *
+ * @note
+ * Copyright (C) 2011~2015 Nuvoton Technology Corp. All rights reserved.
+ *
+ ******************************************************************************/
+
+
+#include
+#include "M451Series.h"
+
+#if defined ( __CC_ARM )
+#if (__ARMCC_VERSION < 400000)
+#else
+/* Insist on keeping widthprec, to avoid X propagation by benign code in C-lib */
+#pragma import _printf_widthprec
+#endif
+#endif
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Global variables */
+/*---------------------------------------------------------------------------------------------------------*/
+#if !(defined(__ICCARM__) && (__VER__ >= 6010000))
+struct __FILE
+{
+ int handle; /* Add whatever you need here */
+};
+#endif
+FILE __stdout;
+FILE __stdin;
+
+enum { r0, r1, r2, r3, r12, lr, pc, psr};
+
+/**
+ * @brief Helper function to dump register while hard fault occurred
+ * @param[in] stack pointer points to the dumped registers in SRAM
+ * @return None
+ * @details This function is implement to print r0, r1, r2, r3, r12, lr, pc, psr
+ */
+static void stackDump(uint32_t stack[])
+{
+ printf("r0 = 0x%x\n", stack[r0]);
+ printf("r1 = 0x%x\n", stack[r1]);
+ printf("r2 = 0x%x\n", stack[r2]);
+ printf("r3 = 0x%x\n", stack[r3]);
+ printf("r12 = 0x%x\n", stack[r12]);
+ printf("lr = 0x%x\n", stack[lr]);
+ printf("pc = 0x%x\n", stack[pc]);
+ printf("psr = 0x%x\n", stack[psr]);
+}
+
+/**
+ * @brief Hard fault handler
+ * @param[in] stack pointer points to the dumped registers in SRAM
+ * @return None
+ * @details Replace while(1) at the end of this function with chip reset if WDT is not enabled for end product
+ */
+void Hard_Fault_Handler(uint32_t stack[])
+{
+ printf("In Hard Fault Handler\n");
+
+ stackDump(stack);
+ // Replace while(1) with chip reset if WDT is not enabled for end product
+ while(1);
+ //SYS->IPRST0 = SYS_IPRST0_CHIPRST_Msk;
+}
+
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Routine to write a char */
+/*---------------------------------------------------------------------------------------------------------*/
+
+#if defined(DEBUG_ENABLE_SEMIHOST)
+/* The static buffer is used to speed up the semihost */
+static char g_buf[16];
+static char g_buf_len = 0;
+
+# if defined(__ICCARM__)
+
+void SH_End(void)
+{
+ asm("MOVS R0,#1 \n" //; Set return value to 1
+ "BX lr \n" //; Return
+ );
+}
+
+void SH_ICE(void)
+{
+ asm("CMP R2,#0 \n"
+ "BEQ SH_End \n"
+ "STR R0,[R2] \n" //; Save the return value to *pn32Out_R0
+ );
+}
+
+/**
+ *
+ * @brief The function to process semihosted command
+ * @param[in] n32In_R0 : semihost register 0
+ * @param[in] n32In_R1 : semihost register 1
+ * @param[out] pn32Out_R0: semihost register 0
+ * @retval 0: No ICE debug
+ * @retval 1: ICE debug
+ *
+ */
+int32_t SH_DoCommand(int32_t n32In_R0, int32_t n32In_R1, int32_t *pn32Out_R0)
+{
+ asm("BKPT 0xAB \n" //; This instruction will cause ICE trap or system HardFault
+ "B SH_ICE \n"
+ "SH_HardFault: \n" //; Captured by HardFault
+ "MOVS R0,#0 \n" //; Set return value to 0
+ "BX lr \n" //; Return
+ );
+
+ return 1; //; Return 1 when it is trap by ICE
+}
+
+/**
+ * @brief Get LR value and branch to Hard_Fault_Handler function
+ * @param None
+ * @return None
+ * @details This function is use to get LR value and branch to Hard_Fault_Handler function.
+ */
+void Get_LR_and_Branch(void)
+{
+ asm("MOV R1, LR \n" //; LR current value
+ "B Hard_Fault_Handler \n"
+ );
+}
+
+/**
+ * @brief Get MSP value and branch to Get_LR_and_Branch function
+ * @param None
+ * @return None
+ * @details This function is use to get stack pointer value and branch to Get_LR_and_Branch function.
+ */
+void Stack_Use_MSP(void)
+{
+ asm("MRS R0, MSP \n" //; read MSP
+ "B Get_LR_and_Branch \n"
+ );
+}
+
+/**
+ * @brief Get stack pointer value and branch to Get_LR_and_Branch function
+ * @param None
+ * @return None
+ * @details This function is use to get stack pointer value and branch to Get_LR_and_Branch function.
+ */
+void HardFault_Handler_Ret(void)
+{
+ asm("MOVS r0, #4 \n"
+ "MOV r1, LR \n"
+ "TST r0, r1 \n" //; check LR bit 2
+ "BEQ Stack_Use_MSP \n" //; stack use MSP
+ "MRS R0, PSP \n" //; stack use PSP, read PSP
+ "B Get_LR_and_Branch \n"
+ );
+}
+
+/**
+ * @brief This function is implemented to support semihost
+ * @param None
+ * @returns None
+ * @details This function is implement to support semihost message print.
+ *
+ */
+void SP_Read_Ready(void)
+{
+ asm("LDR R1, [R0, #24] \n" //; Get previous PC
+ "LDRH R3, [R1] \n" //; Get instruction
+ "LDR R2, [pc, #8] \n" //; The special BKPT instruction
+ "CMP R3, R2 \n" //; Test if the instruction at previous PC is BKPT
+ "BNE HardFault_Handler_Ret \n" //; Not BKPT
+ "ADDS R1, #4 \n" //; Skip BKPT and next line
+ "STR R1, [R0, #24] \n" //; Save previous PC
+ "BX lr \n" //; Return
+ "DCD 0xBEAB \n" //; BKPT instruction code
+ "B HardFault_Handler_Ret \n"
+ );
+}
+
+/**
+ * @brief Get stack pointer value and branch to Get_LR_and_Branch function
+ * @param None
+ * @return None
+ * @details This function is use to get stack pointer value and branch to Get_LR_and_Branch function.
+ */
+void SP_is_PSP(void)
+{
+ asm(
+ "MRS R0, PSP \n" //; stack use PSP, read PSP
+ "B Get_LR_and_Branch \n"
+
+ );
+}
+
+/**
+ * @brief This HardFault handler is implemented to support semihost
+ *
+ * @param None
+ *
+ * @returns None
+ *
+ * @details This function is implement to support semihost message print.
+ *
+ */
+void HardFault_Handler (void)
+{
+ asm("MOV R0, lr \n"
+ "LSLS R0, #29 \n" //; Check bit 2
+ "BMI SP_is_PSP \n" //; previous stack is PSP
+ "MRS R0, MSP \n" //; previous stack is MSP, read MSP
+ "B SP_Read_Ready \n"
+ );
+
+ while(1);
+}
+
+# else
+
+/**
+ * @brief This HardFault handler is implemented to support semihost
+ * @param None
+ * @returns None
+ * @details This function is implement to support semihost message print.
+ *
+ */
+__asm int32_t HardFault_Handler(void)
+{
+ MOV R0, LR
+ LSLS R0, #29 //; Check bit 2
+ BMI SP_is_PSP //; previous stack is PSP
+ MRS R0, MSP //; previous stack is MSP, read MSP
+ B SP_Read_Ready
+SP_is_PSP
+ MRS R0, PSP //; Read PSP
+
+SP_Read_Ready
+ LDR R1, [R0, #24] //; Get previous PC
+ LDRH R3, [R1] //; Get instruction
+ LDR R2, =0xBEAB //; The special BKPT instruction
+ CMP R3, R2 //; Test if the instruction at previous PC is BKPT
+ BNE HardFault_Handler_Ret //; Not BKPT
+
+ ADDS R1, #4 //; Skip BKPT and next line
+ STR R1, [R0, #24] //; Save previous PC
+
+ BX LR //; Return
+HardFault_Handler_Ret
+
+ /* TODO: Implement your own hard fault handler here. */
+ MOVS r0, #4
+ MOV r1, LR
+ TST r0, r1 //; check LR bit 2
+ BEQ Stack_Use_MSP //; stack use MSP
+ MRS R0, PSP ;stack use PSP //; stack use PSP, read PSP
+ B Get_LR_and_Branch
+Stack_Use_MSP
+ MRS R0, MSP ; stack use MSP //; read MSP
+Get_LR_and_Branch
+ MOV R1, LR ; LR current value //; LR current value
+ LDR R2,=__cpp(Hard_Fault_Handler) //; branch to Hard_Fault_Handler
+ BX R2
+
+ B .
+
+ ALIGN
+}
+
+/**
+ *
+ * @brief The function to process semihosted command
+ * @param[in] n32In_R0 : semihost register 0
+ * @param[in] n32In_R1 : semihost register 1
+ * @param[out] pn32Out_R0: semihost register 0
+ * @retval 0: No ICE debug
+ * @retval 1: ICE debug
+ *
+ */
+__asm int32_t SH_DoCommand(int32_t n32In_R0, int32_t n32In_R1, int32_t *pn32Out_R0)
+{
+ BKPT 0xAB //; Wait ICE or HardFault
+ //; ICE will step over BKPT directly
+ //; HardFault will step BKPT and the next line
+ B SH_ICE
+
+SH_HardFault //; Captured by HardFault
+ MOVS R0, #0 //; Set return value to 0
+ BX lr //; Return
+
+SH_ICE //; Captured by ICE
+ //; Save return value
+ CMP R2, #0
+ BEQ SH_End
+ STR R0, [R2] //; Save the return value to *pn32Out_R0
+
+SH_End
+ MOVS R0, #1 //; Set return value to 1
+ BX lr //; Return
+}
+#endif
+
+#else
+
+# if defined(__ICCARM__)
+
+void Get_LR_and_Branch(void)
+{
+ asm("MOV R1, LR \n" //; LR current value
+ "B Hard_Fault_Handler \n"
+ );
+}
+
+void Stack_Use_MSP(void)
+{
+ asm("MRS R0, MSP \n" //; read MSP
+ "B Get_LR_and_Branch \n"
+ );
+}
+
+/**
+ * @brief This HardFault handler is implemented to show r0, r1, r2, r3, r12, lr, pc, psr
+ *
+ * @param None
+ *
+ * @returns None
+ *
+ * @details This function is implement to print r0, r1, r2, r3, r12, lr, pc, psr.
+ *
+ */
+void HardFault_Handler(void)
+{
+ asm("MOVS r0, #4 \n"
+ "MOV r1, LR \n"
+ "TST r0, r1 \n" //; check LR bit 2
+ "BEQ Stack_Use_MSP \n" //; stack use MSP
+ "MRS R0, PSP \n" //; stack use PSP, read PSP
+ "B Get_LR_and_Branch \n"
+ );
+
+ while(1);
+}
+
+# else
+
+/**
+ * @brief This HardFault handler is implemented to show r0, r1, r2, r3, r12, lr, pc, psr
+ *
+ * @param None
+ *
+ * @return None
+ *
+ * @details The function extracts the location of stack frame and passes it to Hard_Fault_Handler function as a pointer
+ *
+ */
+__asm int32_t HardFault_Handler(void)
+{
+ MOVS r0, #4
+ MOV r1, LR
+ TST r0, r1 //; check LR bit 2
+ BEQ Stack_Use_MSP //; stack use MSP
+ MRS R0, PSP //; stack use PSP, read PSP
+ B Get_LR_and_Branch
+Stack_Use_MSP
+ MRS R0, MSP //; read MSP
+Get_LR_and_Branch
+ MOV R1, LR //; LR current value
+ LDR R2,=__cpp(Hard_Fault_Handler) //; branch to Hard_Fault_Handler
+ BX R2
+}
+
+#endif
+
+#endif
+
+
+/**
+ * @brief Routine to send a char
+ *
+ * @param[in] ch Character to send to debug port.
+ *
+ * @returns Send value from UART debug port
+ *
+ * @details Send a target char to UART debug port .
+ */
+#ifndef NONBLOCK_PRINTF
+void SendChar_ToUART(int ch)
+{
+ while(DEBUG_PORT->FIFOSTS & UART_FIFOSTS_TXFULL_Msk);
+
+ DEBUG_PORT->DAT = ch;
+ if(ch == '\n')
+ {
+ while(DEBUG_PORT->FIFOSTS & UART_FIFOSTS_TXFULL_Msk);
+ DEBUG_PORT->DAT = '\r';
+ }
+}
+
+#else
+/* Non-block implement of send char */
+#define BUF_SIZE 2048
+void SendChar_ToUART(int ch)
+{
+ static uint8_t u8Buf[BUF_SIZE] = {0};
+ static int32_t i32Head = 0;
+ static int32_t i32Tail = 0;
+ int32_t i32Tmp;
+
+ /* Only flush the data in buffer to UART when ch == 0 */
+ if(ch)
+ {
+ // Push char
+ i32Tmp = i32Head+1;
+ if(i32Tmp > BUF_SIZE) i32Tmp = 0;
+ if(i32Tmp != i32Tail)
+ {
+ u8Buf[i32Head] = ch;
+ i32Head = i32Tmp;
+ }
+
+ if(ch == '\n')
+ {
+ i32Tmp = i32Head+1;
+ if(i32Tmp > BUF_SIZE) i32Tmp = 0;
+ if(i32Tmp != i32Tail)
+ {
+ u8Buf[i32Head] = '\r';
+ i32Head = i32Tmp;
+ }
+ }
+ }
+ else
+ {
+ if(i32Tail == i32Head)
+ return;
+ }
+
+ // pop char
+ do
+ {
+ i32Tmp = i32Tail + 1;
+ if(i32Tmp > BUF_SIZE) i32Tmp = 0;
+
+ if((DEBUG_PORT->FIFOSTS & UART_FIFOSTS_TXFULL_Msk) == 0)
+ {
+ DEBUG_PORT->DAT = u8Buf[i32Tail];
+ i32Tail = i32Tmp;
+ }
+ else
+ break; // FIFO full
+ }while(i32Tail != i32Head);
+}
+#endif
+
+/**
+ * @brief Routine to send a char
+ *
+ * @param[in] ch Character to send to debug port.
+ *
+ * @returns Send value from UART debug port or semihost
+ *
+ * @details Send a target char to UART debug port or semihost.
+ */
+void SendChar(int ch)
+{
+#if defined(DEBUG_ENABLE_SEMIHOST)
+ g_buf[g_buf_len++] = ch;
+ g_buf[g_buf_len] = '\0';
+ if(g_buf_len + 1 >= sizeof(g_buf) || ch == '\n' || ch == '\0')
+ {
+ /* Send the char */
+ if(SH_DoCommand(0x04, (int)g_buf, NULL) != 0)
+ {
+ g_buf_len = 0;
+ return;
+ }
+ else
+ {
+ int i;
+
+ for(i = 0; i < g_buf_len; i++)
+ SendChar_ToUART(g_buf[i]);
+ g_buf_len = 0;
+ }
+ }
+#else
+ SendChar_ToUART(ch);
+#endif
+}
+
+/**
+ * @brief Routine to get a char
+ *
+ * @param None
+ *
+ * @returns Get value from UART debug port or semihost
+ *
+ * @details Wait UART debug port or semihost to input a char.
+ */
+char GetChar(void)
+{
+#ifdef DEBUG_ENABLE_SEMIHOST
+# if defined (__CC_ARM)
+ int nRet;
+ while(SH_DoCommand(0x101, 0, &nRet) != 0)
+ {
+ if(nRet != 0)
+ {
+ SH_DoCommand(0x07, 0, &nRet);
+ return (char)nRet;
+ }
+ }
+# else
+ int nRet;
+ while(SH_DoCommand(0x7, 0, &nRet) != 0)
+ {
+ if(nRet != 0)
+ return (char)nRet;
+ }
+# endif
+ return (0);
+#else
+
+ while(1)
+ {
+ if((DEBUG_PORT->FIFOSTS & UART_FIFOSTS_RXEMPTY_Msk) == 0)
+ {
+ return (DEBUG_PORT->DAT);
+ }
+ }
+
+#endif
+}
+
+/**
+ * @brief Check any char input from UART
+ *
+ * @param None
+ *
+ * @retval 1: No any char input
+ * @retval 0: Have some char input
+ *
+ * @details Check UART RSR RX EMPTY or not to determine if any char input from UART
+ */
+
+int kbhit(void)
+{
+ return !((DEBUG_PORT->FIFOSTS & UART_FIFOSTS_RXEMPTY_Msk) == 0);
+}
+/**
+ * @brief Check if debug message finished
+ *
+ * @param None
+ *
+ * @retval 1: Message is finished
+ * @retval 0: Message is transmitting.
+ *
+ * @details Check if message finished (FIFO empty of debug port)
+ */
+
+int IsDebugFifoEmpty(void)
+{
+ return ((DEBUG_PORT->FIFOSTS & UART_FIFOSTS_TXEMPTYF_Msk) != 0);
+}
+
+/**
+ * @brief C library retargetting
+ *
+ * @param[in] ch Character to send to debug port.
+ *
+ * @returns None
+ *
+ * @details Check if message finished (FIFO empty of debug port)
+ */
+
+void _ttywrch(int ch)
+{
+ SendChar(ch);
+ return;
+}
+
+
+/**
+ * @brief Write character to stream
+ *
+ * @param[in] ch Character to be written. The character is passed as its int promotion.
+ * @param[in] stream Pointer to a FILE object that identifies the stream where the character is to be written.
+ *
+ * @returns If there are no errors, the same character that has been written is returned.
+ * If an error occurs, EOF is returned and the error indicator is set (see ferror).
+ *
+ * @details Writes a character to the stream and advances the position indicator.\n
+ * The character is written at the current position of the stream as indicated \n
+ * by the internal position indicator, which is then advanced one character.
+ *
+ * @note The above descriptions are copied from http://www.cplusplus.com/reference/clibrary/cstdio/fputc/.
+ *
+ *
+ */
+
+int fputc(int ch, FILE *stream)
+{
+ SendChar(ch);
+ return ch;
+}
+
+
+/**
+ * @brief Get character from UART debug port or semihosting input
+ *
+ * @param[in] stream Pointer to a FILE object that identifies the stream on which the operation is to be performed.
+ *
+ * @returns The character read from UART debug port or semihosting
+ *
+ * @details For get message from debug port or semihosting.
+ *
+ */
+
+int fgetc(FILE *stream)
+{
+ return (GetChar());
+}
+
+/**
+ * @brief Check error indicator
+ *
+ * @param[in] stream Pointer to a FILE object that identifies the stream.
+ *
+ * @returns If the error indicator associated with the stream was set, the function returns a nonzero value.
+ * Otherwise, it returns a zero value.
+ *
+ * @details Checks if the error indicator associated with stream is set, returning a value different
+ * from zero if it is. This indicator is generally set by a previous operation on the stream that failed.
+ *
+ * @note The above descriptions are copied from http://www.cplusplus.com/reference/clibrary/cstdio/ferror/.
+ *
+ */
+
+int ferror(FILE *stream)
+{
+ return EOF;
+}
+
+#ifdef DEBUG_ENABLE_SEMIHOST
+# ifdef __ICCARM__
+void __exit(int return_code)
+{
+
+ /* Check if link with ICE */
+ if(SH_DoCommand(0x18, 0x20026, NULL) == 0)
+ {
+ /* Make sure all message is print out */
+ while(IsDebugFifoEmpty() == 0);
+ }
+label:
+ goto label; /* endless loop */
+}
+# else
+void _sys_exit(int return_code)
+{
+
+ /* Check if link with ICE */
+ if(SH_DoCommand(0x18, 0x20026, NULL) == 0)
+ {
+ /* Make sure all message is print out */
+ while(IsDebugFifoEmpty() == 0);
+ }
+label:
+ goto label; /* endless loop */
+}
+# endif
+#endif
diff --git a/bsp/nuvoton_m451/Libraries/StdDriver/src/rtc.c b/bsp/nuvoton_m451/Libraries/StdDriver/src/rtc.c
new file mode 100644
index 0000000000000000000000000000000000000000..3489e4e61670a367010f0b3223546dee2c62546c
--- /dev/null
+++ b/bsp/nuvoton_m451/Libraries/StdDriver/src/rtc.c
@@ -0,0 +1,789 @@
+/**************************************************************************//**
+ * @file rtc.c
+ * @version V3.00
+ * $Revision: 7 $
+ * $Date: 15/08/11 10:26a $
+ * @brief M451 series RTC driver source file
+ *
+ * @note
+ * Copyright (C) 2013~2015 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#include "M451Series.h"
+
+
+/// @cond HIDDEN_SYMBOLS
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Macro, type and constant definitions */
+/*---------------------------------------------------------------------------------------------------------*/
+#define RTC_GLOBALS
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Global file scope (static) variables */
+/*---------------------------------------------------------------------------------------------------------*/
+static volatile uint32_t g_u32hiYear, g_u32loYear, g_u32hiMonth, g_u32loMonth, g_u32hiDay, g_u32loDay;
+static volatile uint32_t g_u32hiHour, g_u32loHour, g_u32hiMin, g_u32loMin, g_u32hiSec, g_u32loSec;
+
+/// @endcond HIDDEN_SYMBOLS
+
+
+
+
+/** @addtogroup Standard_Driver Standard Driver
+ @{
+*/
+
+/** @addtogroup RTC_Driver RTC Driver
+ @{
+*/
+
+/** @addtogroup RTC_EXPORTED_FUNCTIONS RTC Exported Functions
+ @{
+*/
+
+/**
+ * @brief Initialize RTC module and start counting
+ *
+ * @param[in] sPt Specify the time property and current date and time. It includes: \n
+ * u32Year: Year value, range between 2000 ~ 2099. \n
+ * u32Month: Month value, range between 1 ~ 12. \n
+ * u32Day: Day value, range between 1 ~ 31. \n
+ * u32DayOfWeek: Day of the week. [RTC_SUNDAY / RTC_MONDAY / RTC_TUESDAY /
+ * RTC_WEDNESDAY / RTC_THURSDAY / RTC_FRIDAY /
+ * RTC_SATURDAY] \n
+ * u32Hour: Hour value, range between 0 ~ 23. \n
+ * u32Minute: Minute value, range between 0 ~ 59. \n
+ * u32Second: Second value, range between 0 ~ 59. \n
+ * u32TimeScale: [RTC_CLOCK_12 / RTC_CLOCK_24] \n
+ * u8AmPm: [RTC_AM / RTC_PM] \n
+ *
+ * @return None
+ *
+ * @details This function is used to: \n
+ * 1. Write initial key to let RTC start count. \n
+ * 2. Input parameter indicates start date/time. \n
+ * 3. User has to make sure that parameters of RTC date/time are reasonable. \n
+ * @note Null pointer for using default starting date/time.
+ */
+void RTC_Open(S_RTC_TIME_DATA_T *sPt)
+{
+ RTC->INIT = RTC_INIT_KEY;
+
+ if(RTC->INIT != RTC_INIT_ACTIVE_Msk)
+ {
+ RTC->INIT = RTC_INIT_KEY;
+ while(RTC->INIT != RTC_INIT_ACTIVE_Msk);
+ }
+
+ if(sPt == 0)
+ return ;
+
+ /* Set RTC date and time */
+ RTC_SetDateAndTime(sPt);
+
+ /* Waiting for RTC settings stable */
+ while((RTC->RWEN & RTC_RWEN_RWENF_Msk) == RTC_RWEN_RWENF_Msk);
+}
+
+/**
+ * @brief Disable RTC Clock
+ *
+ * @param None
+ *
+ * @return None
+ *
+ * @details This API will disable RTC peripheral clock and stops RTC counting.
+ */
+void RTC_Close(void)
+{
+ CLK->APBCLK0 &= ~CLK_APBCLK0_RTCCKEN_Msk;
+}
+
+/**
+ * @brief Set 32k Frequency Compensation Data
+ *
+ * @param[in] i32FrequencyX100 Specify the RTC clock X100, ex: 3277365 means 32773.65.
+ *
+ * @return None
+ *
+ * @details This API is used to compensate the 32 kHz frequency by current LXT frequency for RTC application.
+ */
+void RTC_32KCalibration(int32_t i32FrequencyX100)
+{
+ int32_t i32RegInt, i32RegFra;
+
+ /* Compute integer and fraction for RTC FCR register */
+ i32RegInt = (i32FrequencyX100 / 100) - RTC_FCR_REFERENCE;
+ i32RegFra = (((i32FrequencyX100 % 100)) * 60) / 100;
+
+ /* Judge Integer part is reasonable */
+ if((i32RegInt < 0) | (i32RegInt > 15))
+ {
+ return ;
+ }
+
+ RTC_WaitAccessEnable();
+ RTC->FREQADJ = (uint32_t)((i32RegInt << 8) | i32RegFra);
+}
+
+/**
+ * @brief Get Current RTC Date and Time
+ *
+ * @param[out] sPt The returned pointer is specified the current RTC value. It includes: \n
+ * u32Year: Year value \n
+ * u32Month: Month value \n
+ * u32Day: Day value \n
+ * u32DayOfWeek: Day of week \n
+ * u32Hour: Hour value \n
+ * u32Minute: Minute value \n
+ * u32Second: Second value \n
+ * u32TimeScale: [RTC_CLOCK_12 / RTC_CLOCK_24] \n
+ * u8AmPm: [RTC_AM / RTC_PM] \n
+ *
+ * @return None
+ *
+ * @details This API is used to get the current RTC date and time value.
+ */
+void RTC_GetDateAndTime(S_RTC_TIME_DATA_T *sPt)
+{
+ uint32_t u32Tmp;
+
+ sPt->u32TimeScale = RTC->CLKFMT & RTC_CLKFMT_24HEN_Msk; /* 12/24-hour */
+ sPt->u32DayOfWeek = RTC->WEEKDAY & RTC_WEEKDAY_WEEKDAY_Msk; /* Day of the week */
+
+ /* Get [Date digit] data */
+ g_u32hiYear = (RTC->CAL & RTC_CAL_TENYEAR_Msk) >> RTC_CAL_TENYEAR_Pos;
+ g_u32loYear = (RTC->CAL & RTC_CAL_YEAR_Msk) >> RTC_CAL_YEAR_Pos;
+ g_u32hiMonth = (RTC->CAL & RTC_CAL_TENMON_Msk) >> RTC_CAL_TENMON_Pos;
+ g_u32loMonth = (RTC->CAL & RTC_CAL_MON_Msk) >> RTC_CAL_MON_Pos;
+ g_u32hiDay = (RTC->CAL & RTC_CAL_TENDAY_Msk) >> RTC_CAL_TENDAY_Pos;
+ g_u32loDay = (RTC->CAL & RTC_CAL_DAY_Msk) >> RTC_CAL_DAY_Pos;
+
+ /* Get [Time digit] data */
+ g_u32hiHour = (RTC->TIME & RTC_TIME_TENHR_Msk) >> RTC_TIME_TENHR_Pos;
+ g_u32loHour = (RTC->TIME & RTC_TIME_HR_Msk) >> RTC_TIME_HR_Pos;
+ g_u32hiMin = (RTC->TIME & RTC_TIME_TENMIN_Msk) >> RTC_TIME_TENMIN_Pos;
+ g_u32loMin = (RTC->TIME & RTC_TIME_MIN_Msk) >> RTC_TIME_MIN_Pos;
+ g_u32hiSec = (RTC->TIME & RTC_TIME_TENSEC_Msk) >> RTC_TIME_TENSEC_Pos;
+ g_u32loSec = (RTC->TIME & RTC_TIME_SEC_Msk) >> RTC_TIME_SEC_Pos;
+
+ /* Compute to 20XX year */
+ u32Tmp = (g_u32hiYear * 10);
+ u32Tmp += g_u32loYear;
+ sPt->u32Year = u32Tmp + RTC_YEAR2000;
+
+ /* Compute 0~12 month */
+ u32Tmp = (g_u32hiMonth * 10);
+ sPt->u32Month = u32Tmp + g_u32loMonth;
+
+ /* Compute 0~31 day */
+ u32Tmp = (g_u32hiDay * 10);
+ sPt->u32Day = u32Tmp + g_u32loDay;
+
+ /* Compute 12/24 hour */
+ if(sPt->u32TimeScale == RTC_CLOCK_12)
+ {
+ u32Tmp = (g_u32hiHour * 10);
+ u32Tmp += g_u32loHour;
+ sPt->u32Hour = u32Tmp; /* AM: 1~12. PM: 21~32. */
+
+ if(sPt->u32Hour >= 21)
+ {
+ sPt->u32AmPm = RTC_PM;
+ sPt->u32Hour -= 20;
+ }
+ else
+ {
+ sPt->u32AmPm = RTC_AM;
+ }
+
+ u32Tmp = (g_u32hiMin * 10);
+ u32Tmp += g_u32loMin;
+ sPt->u32Minute = u32Tmp;
+
+ u32Tmp = (g_u32hiSec * 10);
+ u32Tmp += g_u32loSec;
+ sPt->u32Second = u32Tmp;
+ }
+ else
+ {
+ u32Tmp = (g_u32hiHour * 10);
+ u32Tmp += g_u32loHour;
+ sPt->u32Hour = u32Tmp;
+
+ u32Tmp = (g_u32hiMin * 10);
+ u32Tmp += g_u32loMin;
+ sPt->u32Minute = u32Tmp;
+
+ u32Tmp = (g_u32hiSec * 10);
+ u32Tmp += g_u32loSec;
+ sPt->u32Second = u32Tmp;
+ }
+}
+
+/**
+ * @brief Get RTC Alarm Date and Time
+ *
+ * @param[out] sPt The returned pointer is specified the RTC alarm value. It includes: \n
+ * u32Year: Year value \n
+ * u32Month: Month value \n
+ * u32Day: Day value \n
+ * u32DayOfWeek: Day of week \n
+ * u32Hour: Hour value \n
+ * u32Minute: Minute value \n
+ * u32Second: Second value \n
+ * u32TimeScale: [RTC_CLOCK_12 / RTC_CLOCK_24] \n
+ * u8AmPm: [RTC_AM / RTC_PM] \n
+ *
+ * @return None
+ *
+ * @details This API is used to get the RTC alarm date and time setting.
+ */
+void RTC_GetAlarmDateAndTime(S_RTC_TIME_DATA_T *sPt)
+{
+ uint32_t u32Tmp;
+
+ sPt->u32TimeScale = RTC->CLKFMT & RTC_CLKFMT_24HEN_Msk; /* 12/24-hour */
+ sPt->u32DayOfWeek = RTC->WEEKDAY & RTC_WEEKDAY_WEEKDAY_Msk; /* Day of the week */
+
+ /* Get alarm [Date digit] data */
+ RTC_WaitAccessEnable();
+ g_u32hiYear = (RTC->CALM & RTC_CALM_TENYEAR_Msk) >> RTC_CALM_TENYEAR_Pos;
+ g_u32loYear = (RTC->CALM & RTC_CALM_YEAR_Msk) >> RTC_CALM_YEAR_Pos;
+ g_u32hiMonth = (RTC->CALM & RTC_CALM_TENMON_Msk) >> RTC_CALM_TENMON_Pos;
+ g_u32loMonth = (RTC->CALM & RTC_CALM_MON_Msk) >> RTC_CALM_MON_Pos;
+ g_u32hiDay = (RTC->CALM & RTC_CALM_TENDAY_Msk) >> RTC_CALM_TENDAY_Pos;
+ g_u32loDay = (RTC->CALM & RTC_CALM_DAY_Msk) >> RTC_CALM_DAY_Pos;
+
+ /* Get alarm [Time digit] data */
+ RTC_WaitAccessEnable();
+ g_u32hiHour = (RTC->TALM & RTC_TALM_TENHR_Msk) >> RTC_TALM_TENHR_Pos;
+ g_u32loHour = (RTC->TALM & RTC_TALM_HR_Msk) >> RTC_TALM_HR_Pos;
+ g_u32hiMin = (RTC->TALM & RTC_TALM_TENMIN_Msk) >> RTC_TALM_TENMIN_Pos;
+ g_u32loMin = (RTC->TALM & RTC_TALM_MIN_Msk) >> RTC_TALM_MIN_Pos;
+ g_u32hiSec = (RTC->TALM & RTC_TALM_TENSEC_Msk) >> RTC_TALM_TENSEC_Pos;
+ g_u32loSec = (RTC->TALM & RTC_TALM_SEC_Msk) >> RTC_TALM_SEC_Pos;
+
+ /* Compute to 20XX year */
+ u32Tmp = (g_u32hiYear * 10);
+ u32Tmp += g_u32loYear;
+ sPt->u32Year = u32Tmp + RTC_YEAR2000;
+
+ /* Compute 0~12 month */
+ u32Tmp = (g_u32hiMonth * 10);
+ sPt->u32Month = u32Tmp + g_u32loMonth;
+
+ /* Compute 0~31 day */
+ u32Tmp = (g_u32hiDay * 10);
+ sPt->u32Day = u32Tmp + g_u32loDay;
+
+ /* Compute 12/24 hour */
+ if(sPt->u32TimeScale == RTC_CLOCK_12)
+ {
+ u32Tmp = (g_u32hiHour * 10);
+ u32Tmp += g_u32loHour;
+ sPt->u32Hour = u32Tmp; /* AM: 1~12. PM: 21~32. */
+
+ if(sPt->u32Hour >= 21)
+ {
+ sPt->u32AmPm = RTC_PM;
+ sPt->u32Hour -= 20;
+ }
+ else
+ {
+ sPt->u32AmPm = RTC_AM;
+ }
+
+ u32Tmp = (g_u32hiMin * 10);
+ u32Tmp += g_u32loMin;
+ sPt->u32Minute = u32Tmp;
+
+ u32Tmp = (g_u32hiSec * 10);
+ u32Tmp += g_u32loSec;
+ sPt->u32Second = u32Tmp;
+
+ }
+ else
+ {
+ u32Tmp = (g_u32hiHour * 10);
+ u32Tmp += g_u32loHour;
+ sPt->u32Hour = u32Tmp;
+
+ u32Tmp = (g_u32hiMin * 10);
+ u32Tmp += g_u32loMin;
+ sPt->u32Minute = u32Tmp;
+
+ u32Tmp = (g_u32hiSec * 10);
+ u32Tmp += g_u32loSec;
+ sPt->u32Second = u32Tmp;
+ }
+}
+
+/**
+ * @brief Update Current RTC Date and Time
+ *
+ * @param[in] sPt Specify the time property and current date and time. It includes: \n
+ * u32Year: Year value, range between 2000 ~ 2099. \n
+ * u32Month: Month value, range between 1 ~ 12. \n
+ * u32Day: Day value, range between 1 ~ 31. \n
+ * u32DayOfWeek: Day of the week. [RTC_SUNDAY / RTC_MONDAY / RTC_TUESDAY /
+ * RTC_WEDNESDAY / RTC_THURSDAY / RTC_FRIDAY /
+ * RTC_SATURDAY] \n
+ * u32Hour: Hour value, range between 0 ~ 23. \n
+ * u32Minute: Minute value, range between 0 ~ 59. \n
+ * u32Second: Second value, range between 0 ~ 59. \n
+ * u32TimeScale: [RTC_CLOCK_12 / RTC_CLOCK_24] \n
+ * u8AmPm: [RTC_AM / RTC_PM] \n
+ *
+ * @return None
+ *
+ * @details This API is used to update current date and time to RTC.
+ */
+void RTC_SetDateAndTime(S_RTC_TIME_DATA_T *sPt)
+{
+ uint32_t u32RegCAL, u32RegTIME;
+
+ if(sPt == 0)
+ return ;
+
+ /*-----------------------------------------------------------------------------------------------------*/
+ /* Set RTC 24/12 hour setting and Day of the Week */
+ /*-----------------------------------------------------------------------------------------------------*/
+ RTC_WaitAccessEnable();
+ if(sPt->u32TimeScale == RTC_CLOCK_12)
+ {
+ RTC->CLKFMT &= ~RTC_CLKFMT_24HEN_Msk;
+
+ /*-------------------------------------------------------------------------------------------------*/
+ /* Important, range of 12-hour PM mode is 21 up to 32 */
+ /*-------------------------------------------------------------------------------------------------*/
+ if(sPt->u32AmPm == RTC_PM)
+ sPt->u32Hour += 20;
+ }
+ else
+ {
+ RTC->CLKFMT |= RTC_CLKFMT_24HEN_Msk;
+ }
+
+ /* Set Day of the Week */
+ RTC->WEEKDAY = sPt->u32DayOfWeek;
+
+ /*-----------------------------------------------------------------------------------------------------*/
+ /* Set RTC Current Date and Time */
+ /*-----------------------------------------------------------------------------------------------------*/
+ u32RegCAL = ((sPt->u32Year - RTC_YEAR2000) / 10) << 20;
+ u32RegCAL |= (((sPt->u32Year - RTC_YEAR2000) % 10) << 16);
+ u32RegCAL |= ((sPt->u32Month / 10) << 12);
+ u32RegCAL |= ((sPt->u32Month % 10) << 8);
+ u32RegCAL |= ((sPt->u32Day / 10) << 4);
+ u32RegCAL |= (sPt->u32Day % 10);
+
+ u32RegTIME = ((sPt->u32Hour / 10) << 20);
+ u32RegTIME |= ((sPt->u32Hour % 10) << 16);
+ u32RegTIME |= ((sPt->u32Minute / 10) << 12);
+ u32RegTIME |= ((sPt->u32Minute % 10) << 8);
+ u32RegTIME |= ((sPt->u32Second / 10) << 4);
+ u32RegTIME |= (sPt->u32Second % 10);
+
+ /*-----------------------------------------------------------------------------------------------------*/
+ /* Set RTC Calender and Time Loading */
+ /*-----------------------------------------------------------------------------------------------------*/
+ RTC_WaitAccessEnable();
+ RTC->CAL = (uint32_t)u32RegCAL;
+ RTC->TIME = (uint32_t)u32RegTIME;
+}
+
+/**
+ * @brief Update RTC Alarm Date and Time
+ *
+ * @param[in] sPt Specify the time property and alarm date and time. It includes: \n
+ * u32Year: Year value, range between 2000 ~ 2099. \n
+ * u32Month: Month value, range between 1 ~ 12. \n
+ * u32Day: Day value, range between 1 ~ 31. \n
+ * u32DayOfWeek: Day of the week. [RTC_SUNDAY / RTC_MONDAY / RTC_TUESDAY /
+ * RTC_WEDNESDAY / RTC_THURSDAY / RTC_FRIDAY /
+ * RTC_SATURDAY] \n
+ * u32Hour: Hour value, range between 0 ~ 23. \n
+ * u32Minute: Minute value, range between 0 ~ 59. \n
+ * u32Second: Second value, range between 0 ~ 59. \n
+ * u32TimeScale: [RTC_CLOCK_12 / RTC_CLOCK_24] \n
+ * u8AmPm: [RTC_AM / RTC_PM] \n
+ *
+ * @return None
+ *
+ * @details This API is used to update alarm date and time setting to RTC.
+ */
+void RTC_SetAlarmDateAndTime(S_RTC_TIME_DATA_T *sPt)
+{
+ uint32_t u32RegCALM, u32RegTALM;
+
+ if(sPt == 0)
+ return ;
+
+ /*-----------------------------------------------------------------------------------------------------*/
+ /* Set RTC 24/12 hour setting and Day of the Week */
+ /*-----------------------------------------------------------------------------------------------------*/
+ RTC_WaitAccessEnable();
+ if(sPt->u32TimeScale == RTC_CLOCK_12)
+ {
+ RTC->CLKFMT &= ~RTC_CLKFMT_24HEN_Msk;
+
+ /*-------------------------------------------------------------------------------------------------*/
+ /* Important, range of 12-hour PM mode is 21 up to 32 */
+ /*-------------------------------------------------------------------------------------------------*/
+ if(sPt->u32AmPm == RTC_PM)
+ sPt->u32Hour += 20;
+ }
+ else
+ {
+ RTC->CLKFMT |= RTC_CLKFMT_24HEN_Msk;
+ }
+
+ /* Set Day of the Week */
+ RTC->WEEKDAY = sPt->u32DayOfWeek;
+
+ /*-----------------------------------------------------------------------------------------------------*/
+ /* Set RTC Alarm Date and Time */
+ /*-----------------------------------------------------------------------------------------------------*/
+ u32RegCALM = ((sPt->u32Year - RTC_YEAR2000) / 10) << 20;
+ u32RegCALM |= (((sPt->u32Year - RTC_YEAR2000) % 10) << 16);
+ u32RegCALM |= ((sPt->u32Month / 10) << 12);
+ u32RegCALM |= ((sPt->u32Month % 10) << 8);
+ u32RegCALM |= ((sPt->u32Day / 10) << 4);
+ u32RegCALM |= (sPt->u32Day % 10);
+
+ u32RegTALM = ((sPt->u32Hour / 10) << 20);
+ u32RegTALM |= ((sPt->u32Hour % 10) << 16);
+ u32RegTALM |= ((sPt->u32Minute / 10) << 12);
+ u32RegTALM |= ((sPt->u32Minute % 10) << 8);
+ u32RegTALM |= ((sPt->u32Second / 10) << 4);
+ u32RegTALM |= (sPt->u32Second % 10);
+
+ RTC_WaitAccessEnable();
+ RTC->CALM = (uint32_t)u32RegCALM;
+ RTC->TALM = (uint32_t)u32RegTALM;
+}
+
+/**
+ * @brief Update RTC Current Date
+ *
+ * @param[in] u32Year The year calendar digit of current RTC setting.
+ * @param[in] u32Month The month calendar digit of current RTC setting.
+ * @param[in] u32Day The day calendar digit of current RTC setting.
+ * @param[in] u32DayOfWeek The Day of the week. [RTC_SUNDAY / RTC_MONDAY / RTC_TUESDAY /
+ * RTC_WEDNESDAY / RTC_THURSDAY / RTC_FRIDAY /
+ * RTC_SATURDAY]
+ *
+ * @return None
+ *
+ * @details This API is used to update current date to RTC.
+ */
+void RTC_SetDate(uint32_t u32Year, uint32_t u32Month, uint32_t u32Day, uint32_t u32DayOfWeek)
+{
+ uint32_t u32RegCAL;
+
+ u32RegCAL = ((u32Year - RTC_YEAR2000) / 10) << 20;
+ u32RegCAL |= (((u32Year - RTC_YEAR2000) % 10) << 16);
+ u32RegCAL |= ((u32Month / 10) << 12);
+ u32RegCAL |= ((u32Month % 10) << 8);
+ u32RegCAL |= ((u32Day / 10) << 4);
+ u32RegCAL |= (u32Day % 10);
+
+ RTC_WaitAccessEnable();
+
+ /* Set Day of the Week */
+ RTC->WEEKDAY = u32DayOfWeek & RTC_WEEKDAY_WEEKDAY_Msk;
+
+ /* Set RTC Calender Loading */
+ RTC->CAL = (uint32_t)u32RegCAL;
+}
+
+/**
+ * @brief Update RTC Current Time
+ *
+ * @param[in] u32Hour The hour time digit of current RTC setting.
+ * @param[in] u32Minute The minute time digit of current RTC setting.
+ * @param[in] u32Second The second time digit of current RTC setting.
+ * @param[in] u32TimeMode The 24-Hour / 12-Hour Time Scale Selection. [RTC_CLOCK_12 / RTC_CLOCK_24]
+ * @param[in] u32AmPm 12-hour time scale with AM and PM indication. Only Time Scale select 12-hour used. [RTC_AM / RTC_PM]
+ *
+ * @return None
+ *
+ * @details This API is used to update current time to RTC.
+ */
+void RTC_SetTime(uint32_t u32Hour, uint32_t u32Minute, uint32_t u32Second, uint32_t u32TimeMode, uint32_t u32AmPm)
+{
+ uint32_t u32RegTIME;
+
+ /* Important, range of 12-hour PM mode is 21 up to 32 */
+ if((u32TimeMode == RTC_CLOCK_12) && (u32AmPm == RTC_PM))
+ u32Hour += 20;
+
+ u32RegTIME = ((u32Hour / 10) << 20);
+ u32RegTIME |= ((u32Hour % 10) << 16);
+ u32RegTIME |= ((u32Minute / 10) << 12);
+ u32RegTIME |= ((u32Minute % 10) << 8);
+ u32RegTIME |= ((u32Second / 10) << 4);
+ u32RegTIME |= (u32Second % 10);
+
+ /*-----------------------------------------------------------------------------------------------------*/
+ /* Set RTC 24/12 hour setting and Day of the Week */
+ /*-----------------------------------------------------------------------------------------------------*/
+ RTC_WaitAccessEnable();
+ if(u32TimeMode == RTC_CLOCK_12)
+ {
+ RTC->CLKFMT &= ~RTC_CLKFMT_24HEN_Msk;
+ }
+ else
+ {
+ RTC->CLKFMT |= RTC_CLKFMT_24HEN_Msk;
+ }
+
+ RTC->TIME = (uint32_t)u32RegTIME;
+}
+
+/**
+ * @brief Update RTC Alarm Date
+ *
+ * @param[in] u32Year The year calendar digit of RTC alarm setting.
+ * @param[in] u32Month The month calendar digit of RTC alarm setting.
+ * @param[in] u32Day The day calendar digit of RTC alarm setting.
+ *
+ * @return None
+ *
+ * @details This API is used to update alarm date setting to RTC.
+ */
+void RTC_SetAlarmDate(uint32_t u32Year, uint32_t u32Month, uint32_t u32Day)
+{
+ uint32_t u32RegCALM;
+
+ u32RegCALM = ((u32Year - RTC_YEAR2000) / 10) << 20;
+ u32RegCALM |= (((u32Year - RTC_YEAR2000) % 10) << 16);
+ u32RegCALM |= ((u32Month / 10) << 12);
+ u32RegCALM |= ((u32Month % 10) << 8);
+ u32RegCALM |= ((u32Day / 10) << 4);
+ u32RegCALM |= (u32Day % 10);
+
+ RTC_WaitAccessEnable();
+
+ /* Set RTC Alarm Date */
+ RTC->CALM = (uint32_t)u32RegCALM;
+}
+
+/**
+ * @brief Update RTC Alarm Time
+ *
+ * @param[in] u32Hour The hour time digit of RTC alarm setting.
+ * @param[in] u32Minute The minute time digit of RTC alarm setting.
+ * @param[in] u32Second The second time digit of RTC alarm setting.
+ * @param[in] u32TimeMode The 24-Hour / 12-Hour Time Scale Selection. [RTC_CLOCK_12 / RTC_CLOCK_24]
+ * @param[in] u32AmPm 12-hour time scale with AM and PM indication. Only Time Scale select 12-hour used. [RTC_AM / RTC_PM]
+ *
+ * @return None
+ *
+ * @details This API is used to update alarm time setting to RTC.
+ */
+void RTC_SetAlarmTime(uint32_t u32Hour, uint32_t u32Minute, uint32_t u32Second, uint32_t u32TimeMode, uint32_t u32AmPm)
+{
+ uint32_t u32RegTALM;
+
+ /* Important, range of 12-hour PM mode is 21 up to 32 */
+ if((u32TimeMode == RTC_CLOCK_12) && (u32AmPm == RTC_PM))
+ u32Hour += 20;
+
+ u32RegTALM = ((u32Hour / 10) << 20);
+ u32RegTALM |= ((u32Hour % 10) << 16);
+ u32RegTALM |= ((u32Minute / 10) << 12);
+ u32RegTALM |= ((u32Minute % 10) << 8);
+ u32RegTALM |= ((u32Second / 10) << 4);
+ u32RegTALM |= (u32Second % 10);
+
+ /*-----------------------------------------------------------------------------------------------------*/
+ /* Set RTC 24/12 hour setting and Day of the Week */
+ /*-----------------------------------------------------------------------------------------------------*/
+ RTC_WaitAccessEnable();
+ if(u32TimeMode == RTC_CLOCK_12)
+ {
+ RTC->CLKFMT &= ~RTC_CLKFMT_24HEN_Msk;
+ }
+ else
+ {
+ RTC->CLKFMT |= RTC_CLKFMT_24HEN_Msk;
+ }
+
+ /* Set RTC Alarm Time */
+ RTC->TALM = (uint32_t)u32RegTALM;
+}
+
+/**
+ * @brief Get Day of the Week
+ *
+ * @param None
+ *
+ * @retval 0 Sunday
+ * @retval 1 Monday
+ * @retval 2 Tuesday
+ * @retval 3 Wednesday
+ * @retval 4 Thursday
+ * @retval 5 Friday
+ * @retval 6 Saturday
+ *
+ * @details This API is used to get day of the week of current RTC date.
+ */
+uint32_t RTC_GetDayOfWeek(void)
+{
+ return (RTC->WEEKDAY & RTC_WEEKDAY_WEEKDAY_Msk);
+}
+
+/**
+ * @brief Set RTC Tick Period Time
+ *
+ * @param[in] u32TickSelection It is used to set the RTC tick period time for Periodic Time Tick request. \n
+ * It consists of: \n
+ * RTC_TICK_1_SEC: Time tick is 1 second \n
+ * RTC_TICK_1_2_SEC: Time tick is 1/2 second \n
+ * RTC_TICK_1_4_SEC: Time tick is 1/4 second \n
+ * RTC_TICK_1_8_SEC: Time tick is 1/8 second \n
+ * RTC_TICK_1_16_SEC: Time tick is 1/16 second \n
+ * RTC_TICK_1_32_SEC: Time tick is 1/32 second \n
+ * RTC_TICK_1_64_SEC: Time tick is 1/64 second \n
+ * RTC_TICK_1_128_SEC: Time tick is 1/128 second
+ *
+ * @return None
+ *
+ * @details This API is used to set RTC tick period time for each tick interrupt.
+ */
+void RTC_SetTickPeriod(uint32_t u32TickSelection)
+{
+ RTC_WaitAccessEnable();
+
+ RTC->TICK = (RTC->TICK & ~RTC_TICK_TICK_Msk) | u32TickSelection;
+}
+
+/**
+ * @brief Enable RTC Interrupt
+ *
+ * @param[in] u32IntFlagMask Specify the interrupt source. It consists of: \n
+ * RTC_INTEN_ALMIEN_Msk: Alarm interrupt \n
+ * RTC_INTEN_TICKIEN_Msk: Tick interrupt \n
+ * RTC_INTEN_SNPDIEN_Msk: Snooper Pin Event Detection interrupt \n
+ *
+ * @return None
+ *
+ * @details This API is used to enable the specify RTC interrupt function.
+ */
+void RTC_EnableInt(uint32_t u32IntFlagMask)
+{
+ RTC->INTEN |= u32IntFlagMask;
+}
+
+/**
+ * @brief Disable RTC Interrupt
+ *
+ * @param[in] u32IntFlagMask Specify the interrupt source. It consists of: \n
+ * RTC_INTEN_ALMIEN_Msk: Alarm interrupt \n
+ * RTC_INTEN_TICKIEN_Msk: Tick interrupt \n
+ * RTC_INTEN_SNPDIEN_Msk: Snooper Pin Event Detection interrupt \n
+ *
+ * @return None
+ *
+ * @details This API is used to disable the specify RTC interrupt function.
+ */
+void RTC_DisableInt(uint32_t u32IntFlagMask)
+{
+ if(u32IntFlagMask & RTC_INTEN_ALMIEN_Msk)
+ {
+ RTC->INTEN &= ~RTC_INTEN_ALMIEN_Msk;
+ RTC->INTSTS = RTC_INTSTS_ALMIF_Msk;
+ }
+
+ if(u32IntFlagMask & RTC_INTEN_TICKIEN_Msk)
+ {
+ RTC->INTEN &= ~RTC_INTEN_TICKIEN_Msk;
+ RTC->INTSTS = RTC_INTSTS_TICKIF_Msk;
+ }
+
+ if(u32IntFlagMask & RTC_INTEN_SNPDIEN_Msk)
+ {
+ RTC->INTEN &= ~RTC_INTEN_SNPDIEN_Msk;
+ RTC->INTSTS = RTC_INTSTS_SNPDIF_Msk;
+ }
+}
+
+/**
+ * @brief Enable Spare Registers Access
+ *
+ * @param None
+ *
+ * @return None
+ *
+ * @details This API is used to enable the spare registers 0~19 can be accessed.
+ */
+void RTC_EnableSpareAccess(void)
+{
+ RTC_WaitAccessEnable();
+
+ RTC->SPRCTL |= RTC_SPRCTL_SPRRWEN_Msk;
+
+ while(!(RTC->SPRCTL & RTC_SPRCTL_SPRRWRDY_Msk));
+}
+
+/**
+ * @brief Disable Spare Register
+ *
+ * @param None
+ *
+ * @return None
+ *
+ * @details This API is used to disable the spare register 0~19 cannot be accessed.
+ */
+void RTC_DisableSpareRegister(void)
+{
+ RTC_WaitAccessEnable();
+
+ RTC->SPRCTL &= ~RTC_SPRCTL_SPRRWEN_Msk;
+}
+
+/**
+ * @brief Enable Snooper Pin Detect
+ *
+ * @param[in] u32PinCondition Snooper pin trigger condition. Possible options are
+ * - \ref RTC_SNOOPER_LOW_LEVEL
+ * - \ref RTC_SNOOPER_HIGH_LEVEL
+ * - \ref RTC_SNOOPER_FALLING_EDGE
+ * - \ref RTC_SNOOPER_RISING_EDGE
+ *
+ * @return None
+ *
+ * @details This API is used to enable the snooper pin detect function with specify trigger condition.
+ */
+void RTC_EnableSnooperDetection(uint32_t u32PinCondition)
+{
+ RTC_WaitAccessEnable();
+
+ RTC->SPRCTL = ((RTC->SPRCTL & ~RTC_SNOOPER_DETECT_Msk) | u32PinCondition) | RTC_SPRCTL_SNPDEN_Msk;
+}
+
+/**
+ * @brief Disable Snooper Pin Detect
+ *
+ * @param None
+ *
+ * @return None
+ *
+ * @details This API is used to disable the snooper pin detect function.
+ */
+void RTC_DisableSnooperDetection(void)
+{
+ RTC_WaitAccessEnable();
+
+ RTC->SPRCTL &= ~RTC_SPRCTL_SNPDEN_Msk;
+}
+
+/*@}*/ /* end of group RTC_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group RTC_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+/*** (C) COPYRIGHT 2013~2015 Nuvoton Technology Corp. ***/
diff --git a/bsp/nuvoton_m451/Libraries/StdDriver/src/sc.c b/bsp/nuvoton_m451/Libraries/StdDriver/src/sc.c
new file mode 100644
index 0000000000000000000000000000000000000000..85aa2bb7b8c8b0986d02b4640f8ae9dfa90f4484
--- /dev/null
+++ b/bsp/nuvoton_m451/Libraries/StdDriver/src/sc.c
@@ -0,0 +1,299 @@
+/**************************************************************************//**
+ * @file sc.c
+ * @version V3.00
+ * $Revision: 9 $
+ * $Date: 15/08/11 10:26a $
+ * @brief M451 series Smartcard(SC) driver source file
+ *
+ * @note
+ * Copyright (C) 2013~2015 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#include "M451Series.h"
+
+// Below are variables used locally by SC driver and does not want to parse by doxygen unless HIDDEN_SYMBOLS is defined
+/// @cond HIDDEN_SYMBOLS
+static uint32_t u32CardStateIgnore[SC_INTERFACE_NUM] = {0};
+
+/// @endcond HIDDEN_SYMBOLS
+
+/** @addtogroup Standard_Driver Standard Driver
+ @{
+*/
+
+/** @addtogroup SC_Driver SC Driver
+ @{
+*/
+
+
+/** @addtogroup SC_EXPORTED_FUNCTIONS SC Exported Functions
+ @{
+*/
+
+/**
+ * @brief This function indicates specified smartcard slot status.
+ * @param[in] sc The pointer of smartcard module.
+ * @retval TRUE Card insert.
+ * @retval FALSE Card remove.
+ * @details This function is used to check if specified smart card slot is presented.
+ */
+uint32_t SC_IsCardInserted(SC_T *sc)
+{
+ // put conditions into two variable to remove IAR compilation warning
+ uint32_t cond1 = ((sc->STATUS & SC_STATUS_CDPINSTS_Msk) >> SC_STATUS_CDPINSTS_Pos);
+ uint32_t cond2 = ((sc->CTL & SC_CTL_CDLV_Msk) >> SC_CTL_CDLV_Pos);
+
+ if(sc == SC0 && u32CardStateIgnore[0] == 1)
+ return TRUE;
+#if 0 /* M451 series has only one SC interface */
+ else if(sc == SC1 && u32CardStateIgnore[1] == 1)
+ return TRUE;
+ else if(sc == SC2 && u32CardStateIgnore[2] == 1)
+ return TRUE;
+ else if(sc == SC3 && u32CardStateIgnore[3] == 1)
+ return TRUE;
+ else if(sc == SC4 && u32CardStateIgnore[4] == 1)
+ return TRUE;
+ else if(sc == SC5 && u32CardStateIgnore[5] == 1)
+ return TRUE;
+#endif
+ else if(cond1 != cond2)
+ return FALSE;
+ else
+ return TRUE;
+}
+
+/**
+ * @brief Reset the Tx/Rx FIFO.
+ * @param[in] sc The pointer of smartcard module.
+ * @return None
+ * @details This function reset both transmit and receive FIFO of specified smartcard module.
+ */
+void SC_ClearFIFO(SC_T *sc)
+{
+ sc->ALTCTL |= (SC_ALTCTL_TXRST_Msk | SC_ALTCTL_RXRST_Msk);
+}
+
+/**
+ * @brief This function disable specified smartcard module.
+ * @param[in] sc The pointer of smartcard module.
+ * @return None
+ * @details SC will force all transition to IDLE state.
+ */
+void SC_Close(SC_T *sc)
+{
+ sc->INTEN = 0;
+ sc->PINCTL = 0;
+ sc->ALTCTL = 0;
+ sc->CTL = 0;
+}
+
+/**
+ * @brief This function initialized smartcard module.
+ * @param[in] sc The pointer of smartcard module.
+ * @param[in] u32CD Card detect polarity, select the CD pin state which indicates card insert. Could be:
+ * -\ref SC_PIN_STATE_HIGH.
+ * -\ref SC_PIN_STATE_LOW.
+ * -\ref SC_PIN_STATE_IGNORE, no card detect pin, always assumes card present.
+ * @param[in] u32PWR Power on polarity, select the PWR pin state which could set smartcard VCC to high level. Could be:
+ * -\ref SC_PIN_STATE_HIGH.
+ * -\ref SC_PIN_STATE_LOW.
+ * @return None
+ * @details Initialization process configures smartcard and enables engine clock.
+ */
+void SC_Open(SC_T *sc, uint32_t u32CD, uint32_t u32PWR)
+{
+ uint32_t u32Reg = 0, u32Intf;
+
+ if(sc == SC0)
+ u32Intf = 0;
+#if 0 /* M451 series has only one SC interface */
+ else if(sc == SC1)
+ u32Intf = 1;
+ else if(sc == SC2)
+ u32Intf = 2;
+ else if(sc == SC3)
+ u32Intf = 3;
+ else if(sc == SC4)
+ u32Intf = 4;
+ else if(sc == SC5)
+ u32Intf = 5;
+#endif
+ else
+ return ;
+
+ if(u32CD != SC_PIN_STATE_IGNORE) {
+ u32Reg = u32CD ? 0: SC_CTL_CDLV_Msk;
+ u32CardStateIgnore[u32Intf] = 0;
+ } else {
+ u32CardStateIgnore[u32Intf] = 1;
+ }
+ while(sc->PINCTL & SC_PINCTL_SYNC_Msk);
+ sc->PINCTL = u32PWR ? 0 : SC_PINCTL_PWRINV_Msk;
+ while(sc->CTL & SC_CTL_SYNC_Msk);
+ sc->CTL = SC_CTL_SCEN_Msk | u32Reg;
+}
+
+/**
+ * @brief This function reset specified smartcard module to its default state for activate smartcard.
+ * @param[in] sc The pointer of smartcard module.
+ * @return None
+ * @details Reset the Tx/Rx FIFO & clock & initial default parameter.
+ */
+void SC_ResetReader(SC_T *sc)
+{
+ uint32_t u32Intf;
+
+ if(sc == SC0)
+ u32Intf = 0;
+#if 0 /* M451 series has only one SC interface */
+ else if(sc == SC1)
+ u32Intf = 1;
+ else if(sc == SC2)
+ u32Intf = 2;
+ else if(sc == SC3)
+ u32Intf = 3;
+ else if(sc == SC4)
+ u32Intf = 4;
+ else if(sc == SC5)
+ u32Intf = 5;
+#endif
+ else
+ return ;
+
+ // Reset FIFO, enable auto de-activation while card removal
+ sc->ALTCTL |= (SC_ALTCTL_TXRST_Msk | SC_ALTCTL_RXRST_Msk | SC_ALTCTL_ADACEN_Msk);
+ // Set Rx trigger level to 1 character, longest card detect debounce period, disable error retry (EMV ATR does not use error retry)
+ while(sc->CTL & SC_CTL_SYNC_Msk);
+ sc->CTL &= ~(SC_CTL_RXTRGLV_Msk | SC_CTL_CDDBSEL_Msk | SC_CTL_TXRTY_Msk | SC_CTL_RXRTY_Msk);
+ // Enable auto convention, and all three smartcard internal timers
+ sc->CTL |= SC_CTL_AUTOCEN_Msk | SC_CTL_TMRSEL_Msk;
+ // Disable Rx timeout
+ sc->RXTOUT = 0;
+ // 372 clocks per ETU by default
+ sc->ETUCTL = 371;
+
+ /* Enable necessary interrupt for smartcard operation */
+ if(u32CardStateIgnore[u32Intf]) // Do not enable card detect interrupt if card present state ignore
+ sc->INTEN = (SC_INTEN_RDAIEN_Msk |
+ SC_INTEN_TERRIEN_Msk |
+ SC_INTEN_TMR0IEN_Msk |
+ SC_INTEN_TMR1IEN_Msk |
+ SC_INTEN_TMR2IEN_Msk |
+ SC_INTEN_BGTIEN_Msk |
+ SC_INTEN_ACERRIEN_Msk);
+ else
+ sc->INTEN = (SC_INTEN_RDAIEN_Msk |
+ SC_INTEN_TERRIEN_Msk |
+ SC_INTEN_TMR0IEN_Msk |
+ SC_INTEN_TMR1IEN_Msk |
+ SC_INTEN_TMR2IEN_Msk |
+ SC_INTEN_BGTIEN_Msk |
+ SC_INTEN_ACERRIEN_Msk |
+ SC_INTEN_CDIEN_Msk);
+
+ return;
+}
+
+/**
+ * @brief Set Block Guard Time.
+ * @param[in] sc The pointer of smartcard module.
+ * @param[in] u32BGT Block guard time using ETU as unit, valid range are between 1 ~ 32.
+ * @return None
+ * @details This function block guard time (BGT) of specified smartcard module.
+ */
+void SC_SetBlockGuardTime(SC_T *sc, uint32_t u32BGT)
+{
+ sc->CTL = (sc->CTL & ~SC_CTL_BGT_Msk) | ((u32BGT - 1) << SC_CTL_BGT_Pos);
+}
+
+/**
+ * @brief Set character guard time.
+ * @param[in] sc The pointer of smartcard module.
+ * @param[in] u32CGT Character guard time using ETU as unit, valid range are between 11 ~ 267.
+ * @return None
+ * @details This function character guard time (CGT) of specified smartcard module.
+ * @note Before using this API, user should set the correct stop bit length first.
+ */
+void SC_SetCharGuardTime(SC_T *sc, uint32_t u32CGT)
+{
+ u32CGT -= sc->CTL & SC_CTL_NSB_Msk ? 11 : 12;
+ sc->EGT = u32CGT;
+}
+
+/**
+ * @brief Stop all Timer counting.
+ * @param[in] sc The pointer of smartcard module.
+ * @return None
+ * @details This function stop all smartcard timer of specified smartcard module.
+ * @note This function stop the timers within smartcard module, \b not timer module.
+ */
+void SC_StopAllTimer(SC_T *sc)
+{
+ sc->ALTCTL &= ~(SC_ALTCTL_CNTEN0_Msk | SC_ALTCTL_CNTEN1_Msk | SC_ALTCTL_CNTEN2_Msk);
+}
+
+/**
+ * @brief This function configure and start a smartcard timer of specified smartcard module.
+ * @param[in] sc The pointer of smartcard module.
+ * @param[in] u32TimerNum Timer(s) to start. Valid values are 0, 1, 2.
+ * @param[in] u32Mode Timer operating mode, valid values are:
+ * - \ref SC_TMR_MODE_0
+ * - \ref SC_TMR_MODE_1
+ * - \ref SC_TMR_MODE_2
+ * - \ref SC_TMR_MODE_3
+ * - \ref SC_TMR_MODE_4
+ * - \ref SC_TMR_MODE_5
+ * - \ref SC_TMR_MODE_6
+ * - \ref SC_TMR_MODE_7
+ * - \ref SC_TMR_MODE_8
+ * - \ref SC_TMR_MODE_F
+ * @param[in] u32ETUCount Timer timeout duration, ETU based. For timer 0, valid range are between 1~0x1000000ETUs.
+ * For timer 1 and timer 2, valid range are between 1 ~ 0x100 ETUs.
+ * @return None
+ * @details Enable Timer starting, counter will count when condition match.
+ * @note This function start the timer within smartcard module, \b not timer module.
+ * @note Depend on the timer operating mode, timer may not start counting immediately.
+ */
+void SC_StartTimer(SC_T *sc, uint32_t u32TimerNum, uint32_t u32Mode, uint32_t u32ETUCount)
+{
+ uint32_t reg = u32Mode | (SC_TMRCTL0_CNT_Msk & (u32ETUCount - 1));
+
+ if(u32TimerNum == 0) {
+ sc->TMRCTL0 = reg;
+ sc->ALTCTL |= SC_ALTCTL_CNTEN0_Msk;
+ } else if(u32TimerNum == 1) {
+ sc->TMRCTL1 = reg;
+ sc->ALTCTL |= SC_ALTCTL_CNTEN1_Msk;
+ } else { // timer 2
+ sc->TMRCTL2 = reg;
+ sc->ALTCTL |= SC_ALTCTL_CNTEN2_Msk;
+ }
+}
+
+/**
+ * @brief Stop Timer counting.
+ * @param[in] sc The pointer of smartcard module.
+ * @param[in] u32TimerNum Timer(s) to stop. Valid values are 0, 1, 2.
+ * @return None
+ * @details This function stop a smartcard timer of specified smartcard module.
+ * @note This function stop the timer within smartcard module, \b not timer module.
+ */
+void SC_StopTimer(SC_T *sc, uint32_t u32TimerNum)
+{
+ if(u32TimerNum == 0)
+ sc->ALTCTL &= ~SC_ALTCTL_CNTEN0_Msk;
+ else if(u32TimerNum == 1)
+ sc->ALTCTL &= ~SC_ALTCTL_CNTEN1_Msk;
+ else // timer 2
+ sc->ALTCTL &= ~SC_ALTCTL_CNTEN2_Msk;
+}
+
+
+
+/*@}*/ /* end of group SC_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group SC_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+/*** (C) COPYRIGHT 2013~2015 Nuvoton Technology Corp. ***/
diff --git a/bsp/nuvoton_m451/Libraries/StdDriver/src/scuart.c b/bsp/nuvoton_m451/Libraries/StdDriver/src/scuart.c
new file mode 100644
index 0000000000000000000000000000000000000000..aca419e22285a3d8fc29965225f273c3758c00d3
--- /dev/null
+++ b/bsp/nuvoton_m451/Libraries/StdDriver/src/scuart.c
@@ -0,0 +1,223 @@
+/**************************************************************************//**
+ * @file scuart.c
+ * @version V3.00
+ * $Revision: 8 $
+ * $Date: 15/08/11 10:26a $
+ * @brief M451 series Smartcard UART mode (SCUART) driver source file
+ *
+ * @note
+ * Copyright (C) 2013~2015 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#include "M451Series.h"
+
+/** @addtogroup Standard_Driver Standard Driver
+ @{
+*/
+
+/** @addtogroup SCUART_Driver SCUART Driver
+ @{
+*/
+
+
+/** @addtogroup SCUART_EXPORTED_FUNCTIONS SCUART Exported Functions
+ @{
+*/
+
+/**
+ * @brief Disable smartcard uart interface.
+ * @param sc The pointer of smartcard module.
+ * @return None
+ * @details The function is used to disable smartcard interface UART mode.
+ */
+void SCUART_Close(SC_T* sc)
+{
+ sc->INTEN = 0;
+ sc->UARTCTL = 0;
+ sc->CTL = 0;
+
+}
+
+/// @cond HIDDEN_SYMBOLS
+/**
+ * @brief This function returns module clock of specified SC interface
+ * @param[in] sc The pointer of smartcard module.
+ * @return Module clock of specified SC interface
+ */
+static uint32_t SCUART_GetClock(SC_T *sc)
+{
+ uint32_t u32ClkSrc, u32Num, u32Clk;
+
+ if(sc == SC0)
+ u32Num = 0;
+#if 0 /* M451 series has only one SC interface */
+ else if(sc == SC1)
+ u32Num = 1;
+ else if(sc == SC2)
+ u32Num = 2;
+ else if(sc == SC3)
+ u32Num = 3;
+ else if(sc == SC4)
+ u32Num = 4;
+ else if(sc == SC5)
+ u32Intf = 5;
+#endif
+ else
+ return FALSE;
+
+ u32ClkSrc = (CLK->CLKSEL3 >> (2 * u32Num)) & CLK_CLKSEL3_SC0SEL_Msk;
+
+ // Get smartcard module clock
+ if(u32ClkSrc == 0)
+ u32Clk = __HXT;
+ else if(u32ClkSrc == 1)
+ u32Clk = CLK_GetPLLClockFreq();
+ else if(u32ClkSrc == 2) {
+ SystemCoreClockUpdate();
+ if(CLK->CLKSEL0 & CLK_CLKSEL0_PCLK0SEL_Msk)
+ u32Clk = SystemCoreClock / 2;
+ else
+ u32Clk = SystemCoreClock;
+ } else
+ u32Clk = __HIRC;
+
+#if 0 /* M451 series has only one SC interface */
+ if(u32Num < 4) {
+ u32Clk /= (((CLK->CLKDIV1 >> (8 * u32Num)) & CLK_CLKDIV1_SC0DIV_Msk) + 1);
+ } else {
+ u32Clk /= (((CLK->CLKDIV2 >> (8 * (u32Num - 4))) & CLK_CLKDIV2_SC4DIV_Msk) + 1);
+ }
+#else
+ u32Clk /= (((CLK->CLKDIV1 >> (8 * u32Num)) & CLK_CLKDIV1_SC0DIV_Msk) + 1);
+#endif
+
+ return u32Clk;
+}
+/// @endcond HIDDEN_SYMBOLS
+
+/**
+ * @brief Enable smartcard uart interface.
+ * @param[in] sc The pointer of smartcard module.
+ * @param[in] u32baudrate Target baudrate of smartcard module.
+ * @return Actual baudrate of smartcard mode.
+ * @details This function use to enable smartcard module UART mode and set baudrate.
+ * @note This function configures character width to 8 bits, 1 stop bit, and no parity.
+ * And can use \ref SCUART_SetLineConfig function to update these settings.
+ */
+uint32_t SCUART_Open(SC_T* sc, uint32_t u32baudrate)
+{
+ uint32_t u32Clk = SCUART_GetClock(sc), u32Div;
+
+ // Calculate divider for target baudrate
+ u32Div = (u32Clk + (u32baudrate >> 1) - 1) / u32baudrate - 1;
+
+ sc->CTL = SC_CTL_SCEN_Msk | SC_CTL_NSB_Msk; // Enable smartcard interface and stop bit = 1
+ sc->UARTCTL = SCUART_CHAR_LEN_8 | SCUART_PARITY_NONE | SC_UARTCTL_UARTEN_Msk; // Enable UART mode, disable parity and 8 bit per character
+ sc->ETUCTL = u32Div;
+
+ return(u32Clk / (u32Div+1));
+}
+
+/**
+ * @brief Read data from smartcard UART interface.
+ * @param[in] sc The pointer of smartcard module.
+ * @param[in] pu8RxBuf The buffer to store receive the data.
+ * @param[in] u32ReadBytes Target number of characters to receive.
+ * @return Actual character number reads to buffer.
+ * @details The function is used to read Rx data from RX FIFO.
+ * @note This function does not block and return immediately if there's no data available.
+ */
+uint32_t SCUART_Read(SC_T* sc, uint8_t *pu8RxBuf, uint32_t u32ReadBytes)
+{
+ uint32_t u32Count;
+
+ for(u32Count = 0; u32Count < u32ReadBytes; u32Count++) {
+ if(SCUART_GET_RX_EMPTY(sc)) { // no data available
+ break;
+ }
+ pu8RxBuf[u32Count] = SCUART_READ(sc); // get data from FIFO
+ }
+
+ return u32Count;
+}
+
+/**
+ * @brief This function use to config smartcard UART mode line setting.
+ * @param[in] sc The pointer of smartcard module.
+ * @param[in] u32Baudrate Target baudrate of smartcard module. If this value is 0, UART baudrate will not change.
+ * @param[in] u32DataWidth The data length, could be:
+ * - \ref SCUART_CHAR_LEN_5
+ * - \ref SCUART_CHAR_LEN_6
+ * - \ref SCUART_CHAR_LEN_7
+ * - \ref SCUART_CHAR_LEN_8
+ * @param[in] u32Parity The parity setting, could be:
+ * - \ref SCUART_PARITY_NONE
+ * - \ref SCUART_PARITY_ODD
+ * - \ref SCUART_PARITY_EVEN
+ * @param[in] u32StopBits The stop bit length, could be:
+ * - \ref SCUART_STOP_BIT_1
+ * - \ref SCUART_STOP_BIT_2
+ * @return Actual baudrate of smartcard.
+ * @details Smartcard UART mode is operated in LIN data frame.
+ */
+uint32_t SCUART_SetLineConfig(SC_T* sc, uint32_t u32Baudrate, uint32_t u32DataWidth, uint32_t u32Parity, uint32_t u32StopBits)
+{
+
+ uint32_t u32Clk = SCUART_GetClock(sc), u32Div;
+
+ if(u32Baudrate == 0) { // keep original baudrate setting
+ u32Div = sc->ETUCTL & SC_ETUCTL_ETURDIV_Msk;
+ } else {
+ // Calculate divider for target baudrate
+ u32Div = (u32Clk + (u32Baudrate >> 1) - 1) / u32Baudrate - 1;
+ sc->ETUCTL = u32Div;
+ }
+
+ sc->CTL = u32StopBits | SC_CTL_SCEN_Msk; // Set stop bit
+ sc->UARTCTL = u32Parity | u32DataWidth | SC_UARTCTL_UARTEN_Msk; // Set character width and parity
+
+ return(u32Clk / (u32Div+1));
+}
+
+/**
+ * @brief This function use to set receive timeout count.
+ * @param[in] sc The pointer of smartcard module.
+ * @param[in] u32TOC Rx timeout counter, using baudrate as counter unit. Valid range are 0~0x1FF,
+ * set this value to 0 will disable timeout counter.
+ * @return None
+ * @details The time-out counter resets and starts counting whenever the RX buffer received a
+ * new data word. Once the counter decrease to 1 and no new data is received or CPU
+ * does not read any data from FIFO, a receiver time-out interrupt will be generated.
+ */
+void SCUART_SetTimeoutCnt(SC_T* sc, uint32_t u32TOC)
+{
+ sc->RXTOUT = u32TOC;
+}
+
+
+/**
+ * @brief Write data to smartcard UART interface.
+ * @param[in] sc The pointer of smartcard module.
+ * @param[in] pu8TxBuf The buffer containing data to send to transmit FIFO.
+ * @param[in] u32WriteBytes Number of data to send.
+ * @return None
+ * @details This function is to write data into transmit FIFO to send data out.
+ * @note This function blocks until all data write into FIFO.
+ */
+void SCUART_Write(SC_T* sc, uint8_t *pu8TxBuf, uint32_t u32WriteBytes)
+{
+ uint32_t u32Count;
+
+ for(u32Count = 0; u32Count != u32WriteBytes; u32Count++) {
+ while(SCUART_GET_TX_FULL(sc)); // Wait 'til FIFO not full
+ sc->DAT = pu8TxBuf[u32Count]; // Write 1 byte to FIFO
+ }
+}
+
+
+/*@}*/ /* end of group SCUART_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group SCUART_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+/*** (C) COPYRIGHT 2013~2015 Nuvoton Technology Corp. ***/
diff --git a/bsp/nuvoton_m451/Libraries/StdDriver/src/spi.c b/bsp/nuvoton_m451/Libraries/StdDriver/src/spi.c
new file mode 100644
index 0000000000000000000000000000000000000000..ad30b8e39a958e7f227fbb20ebf9da24dafa4914
--- /dev/null
+++ b/bsp/nuvoton_m451/Libraries/StdDriver/src/spi.c
@@ -0,0 +1,1154 @@
+/**************************************************************************//**
+ * @file spi.c
+ * @version V3.00
+ * $Revision: 11 $
+ * $Date: 15/08/11 10:26a $
+ * @brief M451 series SPI driver source file
+ *
+ * @note
+ * Copyright (C) 2014~2015 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#include "M451Series.h"
+/** @addtogroup Standard_Driver Standard Driver
+ @{
+*/
+
+/** @addtogroup SPI_Driver SPI Driver
+ @{
+*/
+
+
+/** @addtogroup SPI_EXPORTED_FUNCTIONS SPI Exported Functions
+ @{
+*/
+
+/**
+ * @brief This function make SPI module be ready to transfer.
+ * @param[in] spi The pointer of the specified SPI module.
+ * @param[in] u32MasterSlave Decides the SPI module is operating in master mode or in slave mode. (SPI_SLAVE, SPI_MASTER)
+ * @param[in] u32SPIMode Decides the transfer timing. (SPI_MODE_0, SPI_MODE_1, SPI_MODE_2, SPI_MODE_3)
+ * @param[in] u32DataWidth Decides the data width of a SPI transaction.
+ * @param[in] u32BusClock The expected frequency of SPI bus clock in Hz.
+ * @return Actual frequency of SPI peripheral clock.
+ * @details By default, the SPI transfer sequence is MSB first, the slave selection signal is active low and the automatic
+ * slave selection function is disabled.
+ * In Slave mode, the u32BusClock shall be NULL and the SPI clock divider setting will be 0.
+ * The actual clock rate may be different from the target SPI clock rate.
+ * For example, if the SPI source clock rate is 12MHz and the target SPI bus clock rate is 7MHz, the
+ * actual SPI clock rate will be 6MHz.
+ * @note If u32BusClock = 0, DIVIDER setting will be set to the maximum value.
+ * @note If u32BusClock >= system clock frequency, SPI peripheral clock source will be set to APB clock and DIVIDER will be set to 0.
+ * @note If u32BusClock >= SPI peripheral clock source, DIVIDER will be set to 0.
+ * @note In slave mode, the SPI peripheral clock rate will be equal to APB clock rate.
+ */
+uint32_t SPI_Open(SPI_T *spi,
+ uint32_t u32MasterSlave,
+ uint32_t u32SPIMode,
+ uint32_t u32DataWidth,
+ uint32_t u32BusClock)
+{
+ uint32_t u32ClkSrc = 0, u32Div, u32HCLKFreq;
+
+ if((spi == SPI1) || (spi == SPI2))
+ /* Disable I2S mode */
+ spi->I2SCTL &= ~SPI_I2SCTL_I2SEN_Msk;
+
+ if(u32DataWidth == 32)
+ u32DataWidth = 0;
+
+ /* Get system clock frequency */
+ u32HCLKFreq = CLK_GetHCLKFreq();
+
+ if(u32MasterSlave == SPI_MASTER)
+ {
+ /* Default setting: slave selection signal is active low; disable automatic slave selection function. */
+ spi->SSCTL = SPI_SS_ACTIVE_LOW;
+
+ /* Default setting: MSB first, disable unit transfer interrupt, SP_CYCLE = 0. */
+ spi->CTL = u32MasterSlave | (u32DataWidth << SPI_CTL_DWIDTH_Pos) | (u32SPIMode) | SPI_CTL_SPIEN_Msk;
+
+ if(u32BusClock >= u32HCLKFreq)
+ {
+ /* Select PCLK as the clock source of SPI */
+ if(spi == SPI0)
+ CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI0SEL_Msk)) | CLK_CLKSEL2_SPI0SEL_PCLK0;
+ else if(spi == SPI1)
+ CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI1SEL_Msk)) | CLK_CLKSEL2_SPI1SEL_PCLK1;
+ else
+ CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI2SEL_Msk)) | CLK_CLKSEL2_SPI2SEL_PCLK0;
+ }
+
+ /* Check clock source of SPI */
+ if(spi == SPI0)
+ {
+ if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0SEL_Msk) == CLK_CLKSEL2_SPI0SEL_HXT)
+ u32ClkSrc = __HXT; /* Clock source is HXT */
+ else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0SEL_Msk) == CLK_CLKSEL2_SPI0SEL_PLL)
+ u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */
+ else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0SEL_Msk) == CLK_CLKSEL2_SPI0SEL_PCLK0)
+ {
+ /* Clock source is PCLK0 */
+ if((CLK->CLKSEL0 & CLK_CLKSEL0_PCLK0SEL_Msk) == CLK_CLKSEL0_PCLK0SEL_HCLK_DIV2)
+ u32ClkSrc = (u32HCLKFreq / 2);
+ else
+ u32ClkSrc = u32HCLKFreq;
+ }
+ else
+ u32ClkSrc = __HIRC; /* Clock source is HIRC */
+ }
+ else if(spi == SPI1)
+ {
+ if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI1SEL_Msk) == CLK_CLKSEL2_SPI1SEL_HXT)
+ u32ClkSrc = __HXT; /* Clock source is HXT */
+ else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI1SEL_Msk) == CLK_CLKSEL2_SPI1SEL_PLL)
+ u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */
+ else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI1SEL_Msk) == CLK_CLKSEL2_SPI1SEL_PCLK1)
+ {
+ /* Clock source is PCLK1 */
+ if((CLK->CLKSEL0 & CLK_CLKSEL0_PCLK1SEL_Msk) == CLK_CLKSEL0_PCLK1SEL_HCLK_DIV2)
+ u32ClkSrc = (u32HCLKFreq / 2);
+ else
+ u32ClkSrc = u32HCLKFreq;
+ }
+ else
+ u32ClkSrc = __HIRC; /* Clock source is HIRC */
+ }
+ else
+ {
+ if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI2SEL_Msk) == CLK_CLKSEL2_SPI2SEL_HXT)
+ u32ClkSrc = __HXT; /* Clock source is HXT */
+ else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI2SEL_Msk) == CLK_CLKSEL2_SPI2SEL_PLL)
+ u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */
+ else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI2SEL_Msk) == CLK_CLKSEL2_SPI2SEL_PCLK0)
+ {
+ /* Clock source is PCLK0 */
+ if((CLK->CLKSEL0 & CLK_CLKSEL0_PCLK0SEL_Msk) == CLK_CLKSEL0_PCLK0SEL_HCLK_DIV2)
+ u32ClkSrc = (u32HCLKFreq / 2);
+ else
+ u32ClkSrc = u32HCLKFreq;
+ }
+ else
+ u32ClkSrc = __HIRC; /* Clock source is HIRC */
+ }
+
+ if(u32BusClock >= u32HCLKFreq)
+ {
+ /* Set DIVIDER = 0 */
+ spi->CLKDIV = 0;
+ /* Return master peripheral clock rate */
+ return u32ClkSrc;
+ }
+ else if(u32BusClock >= u32ClkSrc)
+ {
+ /* Set DIVIDER = 0 */
+ spi->CLKDIV = 0;
+ /* Return master peripheral clock rate */
+ return u32ClkSrc;
+ }
+ else if(u32BusClock == 0)
+ {
+ /* Set DIVIDER to the maximum value 0xFF. f_spi = f_spi_clk_src / (DIVIDER + 1) */
+ spi->CLKDIV |= SPI_CLKDIV_DIVIDER_Msk;
+ /* Return master peripheral clock rate */
+ return (u32ClkSrc / (0xFF + 1));
+ }
+ else
+ {
+ u32Div = (((u32ClkSrc * 10) / u32BusClock + 5) / 10) - 1; /* Round to the nearest integer */
+ if(u32Div > 0xFF)
+ {
+ u32Div = 0xFF;
+ spi->CLKDIV |= SPI_CLKDIV_DIVIDER_Msk;
+ /* Return master peripheral clock rate */
+ return (u32ClkSrc / (0xFF + 1));
+ }
+ else
+ {
+ spi->CLKDIV = (spi->CLKDIV & (~SPI_CLKDIV_DIVIDER_Msk)) | (u32Div << SPI_CLKDIV_DIVIDER_Pos);
+ /* Return master peripheral clock rate */
+ return (u32ClkSrc / (u32Div + 1));
+ }
+ }
+ }
+ else /* For slave mode, force the SPI peripheral clock rate to equal APB clock rate. */
+ {
+ /* Default setting: slave selection signal is low level active. */
+ spi->SSCTL = SPI_SS_ACTIVE_LOW;
+
+ /* Default setting: MSB first, disable unit transfer interrupt, SP_CYCLE = 0. */
+ spi->CTL = u32MasterSlave | (u32DataWidth << SPI_CTL_DWIDTH_Pos) | (u32SPIMode) | SPI_CTL_SPIEN_Msk;
+
+ /* Set DIVIDER = 0 */
+ spi->CLKDIV = 0;
+
+ /* Select PCLK as the clock source of SPI */
+ if(spi == SPI0)
+ {
+ CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI0SEL_Msk)) | CLK_CLKSEL2_SPI0SEL_PCLK0;
+ /* Return slave peripheral clock rate */
+ if((CLK->CLKSEL0 & CLK_CLKSEL0_PCLK0SEL_Msk) == CLK_CLKSEL0_PCLK0SEL_HCLK_DIV2)
+ return (u32HCLKFreq / 2);
+ else
+ return u32HCLKFreq;
+ }
+ else if(spi == SPI1)
+ {
+ CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI1SEL_Msk)) | CLK_CLKSEL2_SPI1SEL_PCLK1;
+ /* Return slave peripheral clock rate */
+ if((CLK->CLKSEL0 & CLK_CLKSEL0_PCLK1SEL_Msk) == CLK_CLKSEL0_PCLK1SEL_HCLK_DIV2)
+ return (u32HCLKFreq / 2);
+ else
+ return u32HCLKFreq;
+ }
+ else
+ {
+ CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI2SEL_Msk)) | CLK_CLKSEL2_SPI2SEL_PCLK0;
+ /* Return slave peripheral clock rate */
+ if((CLK->CLKSEL0 & CLK_CLKSEL0_PCLK0SEL_Msk) == CLK_CLKSEL0_PCLK0SEL_HCLK_DIV2)
+ return (u32HCLKFreq / 2);
+ else
+ return u32HCLKFreq;
+ }
+ }
+}
+
+/**
+ * @brief Disable SPI controller.
+ * @param[in] spi The pointer of the specified SPI module.
+ * @return None
+ * @details This function will reset SPI controller.
+ */
+void SPI_Close(SPI_T *spi)
+{
+ if(spi == SPI0)
+ {
+ /* Reset SPI */
+ SYS->IPRST1 |= SYS_IPRST1_SPI0RST_Msk;
+ SYS->IPRST1 &= ~SYS_IPRST1_SPI0RST_Msk;
+ }
+ else if(spi == SPI1)
+ {
+ /* Reset SPI */
+ SYS->IPRST1 |= SYS_IPRST1_SPI1RST_Msk;
+ SYS->IPRST1 &= ~SYS_IPRST1_SPI1RST_Msk;
+ }
+ else
+ {
+ /* Reset SPI */
+ SYS->IPRST1 |= SYS_IPRST1_SPI2RST_Msk;
+ SYS->IPRST1 &= ~SYS_IPRST1_SPI2RST_Msk;
+ }
+}
+
+/**
+ * @brief Clear RX FIFO buffer.
+ * @param[in] spi The pointer of the specified SPI module.
+ * @return None
+ * @details This function will clear SPI RX FIFO buffer. The RXEMPTY (SPI_STATUS[8]) will be set to 1.
+ */
+void SPI_ClearRxFIFO(SPI_T *spi)
+{
+ spi->FIFOCTL |= SPI_FIFOCTL_RXFBCLR_Msk;
+}
+
+/**
+ * @brief Clear TX FIFO buffer.
+ * @param[in] spi The pointer of the specified SPI module.
+ * @return None
+ * @details This function will clear SPI TX FIFO buffer. The TXEMPTY (SPI_STATUS[16]) will be set to 1.
+ * @note The TX shift register will not be cleared.
+ */
+void SPI_ClearTxFIFO(SPI_T *spi)
+{
+ spi->FIFOCTL |= SPI_FIFOCTL_TXFBCLR_Msk;
+}
+
+/**
+ * @brief Disable the automatic slave selection function.
+ * @param[in] spi The pointer of the specified SPI module.
+ * @return None
+ * @details This function will disable the automatic slave selection function and set slave selection signal to inactive state.
+ */
+void SPI_DisableAutoSS(SPI_T *spi)
+{
+ spi->SSCTL &= ~(SPI_SSCTL_AUTOSS_Msk | SPI_SSCTL_SS_Msk);
+}
+
+/**
+ * @brief Enable the automatic slave selection function.
+ * @param[in] spi The pointer of the specified SPI module.
+ * @param[in] u32SSPinMask Specifies slave selection pins. (SPI_SS)
+ * @param[in] u32ActiveLevel Specifies the active level of slave selection signal. (SPI_SS_ACTIVE_HIGH, SPI_SS_ACTIVE_LOW)
+ * @return None
+ * @details This function will enable the automatic slave selection function. Only available in Master mode.
+ * The slave selection pin and the active level will be set in this function.
+ */
+void SPI_EnableAutoSS(SPI_T *spi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel)
+{
+ spi->SSCTL = (spi->SSCTL & (~(SPI_SSCTL_AUTOSS_Msk | SPI_SSCTL_SSACTPOL_Msk | SPI_SSCTL_SS_Msk))) | (u32SSPinMask | u32ActiveLevel | SPI_SSCTL_AUTOSS_Msk);
+}
+
+/**
+ * @brief Set the SPI bus clock.
+ * @param[in] spi The pointer of the specified SPI module.
+ * @param[in] u32BusClock The expected frequency of SPI bus clock in Hz.
+ * @return Actual frequency of SPI bus clock.
+ * @details This function is only available in Master mode. The actual clock rate may be different from the target SPI bus clock rate.
+ * For example, if the SPI source clock rate is 12MHz and the target SPI bus clock rate is 7MHz, the actual SPI bus clock
+ * rate will be 6MHz.
+ * @note If u32BusClock = 0, DIVIDER setting will be set to the maximum value.
+ * @note If u32BusClock >= system clock frequency, SPI peripheral clock source will be set to APB clock and DIVIDER will be set to 0.
+ * @note If u32BusClock >= SPI peripheral clock source, DIVIDER will be set to 0.
+ */
+uint32_t SPI_SetBusClock(SPI_T *spi, uint32_t u32BusClock)
+{
+ uint32_t u32ClkSrc, u32HCLKFreq;
+ uint32_t u32Div;
+
+ /* Get system clock frequency */
+ u32HCLKFreq = CLK_GetHCLKFreq();
+
+ if(u32BusClock >= u32HCLKFreq)
+ {
+ /* Select PCLK as the clock source of SPI */
+ if(spi == SPI0)
+ CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI0SEL_Msk)) | CLK_CLKSEL2_SPI0SEL_PCLK0;
+ else if(spi == SPI1)
+ CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI1SEL_Msk)) | CLK_CLKSEL2_SPI1SEL_PCLK1;
+ else
+ CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI2SEL_Msk)) | CLK_CLKSEL2_SPI2SEL_PCLK0;
+ }
+
+ /* Check clock source of SPI */
+ if(spi == SPI0)
+ {
+ if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0SEL_Msk) == CLK_CLKSEL2_SPI0SEL_HXT)
+ u32ClkSrc = __HXT; /* Clock source is HXT */
+ else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0SEL_Msk) == CLK_CLKSEL2_SPI0SEL_PLL)
+ u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */
+ else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0SEL_Msk) == CLK_CLKSEL2_SPI0SEL_PCLK0)
+ {
+ /* Clock source is PCLK0 */
+ if((CLK->CLKSEL0 & CLK_CLKSEL0_PCLK0SEL_Msk) == CLK_CLKSEL0_PCLK0SEL_HCLK_DIV2)
+ u32ClkSrc = (u32HCLKFreq / 2);
+ else
+ u32ClkSrc = u32HCLKFreq;
+ }
+ else
+ u32ClkSrc = __HIRC; /* Clock source is HIRC */
+ }
+ else if(spi == SPI1)
+ {
+ if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI1SEL_Msk) == CLK_CLKSEL2_SPI1SEL_HXT)
+ u32ClkSrc = __HXT; /* Clock source is HXT */
+ else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI1SEL_Msk) == CLK_CLKSEL2_SPI1SEL_PLL)
+ u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */
+ else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI1SEL_Msk) == CLK_CLKSEL2_SPI1SEL_PCLK1)
+ {
+ /* Clock source is PCLK1 */
+ if((CLK->CLKSEL0 & CLK_CLKSEL0_PCLK1SEL_Msk) == CLK_CLKSEL0_PCLK1SEL_HCLK_DIV2)
+ u32ClkSrc = (u32HCLKFreq / 2);
+ else
+ u32ClkSrc = u32HCLKFreq;
+ }
+ else
+ u32ClkSrc = __HIRC; /* Clock source is HIRC */
+ }
+ else
+ {
+ if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI2SEL_Msk) == CLK_CLKSEL2_SPI2SEL_HXT)
+ u32ClkSrc = __HXT; /* Clock source is HXT */
+ else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI2SEL_Msk) == CLK_CLKSEL2_SPI2SEL_PLL)
+ u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */
+ else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI2SEL_Msk) == CLK_CLKSEL2_SPI2SEL_PCLK0)
+ {
+ /* Clock source is PCLK0 */
+ if((CLK->CLKSEL0 & CLK_CLKSEL0_PCLK0SEL_Msk) == CLK_CLKSEL0_PCLK0SEL_HCLK_DIV2)
+ u32ClkSrc = (u32HCLKFreq / 2);
+ else
+ u32ClkSrc = u32HCLKFreq;
+ }
+ else
+ u32ClkSrc = __HIRC; /* Clock source is HIRC */
+ }
+
+ if(u32BusClock >= u32HCLKFreq)
+ {
+ /* Set DIVIDER = 0 */
+ spi->CLKDIV = 0;
+ /* Return master peripheral clock rate */
+ return u32ClkSrc;
+ }
+ else if(u32BusClock >= u32ClkSrc)
+ {
+ /* Set DIVIDER = 0 */
+ spi->CLKDIV = 0;
+ /* Return master peripheral clock rate */
+ return u32ClkSrc;
+ }
+ else if(u32BusClock == 0)
+ {
+ /* Set DIVIDER to the maximum value 0xFF. f_spi = f_spi_clk_src / (DIVIDER + 1) */
+ spi->CLKDIV |= SPI_CLKDIV_DIVIDER_Msk;
+ /* Return master peripheral clock rate */
+ return (u32ClkSrc / (0xFF + 1));
+ }
+ else
+ {
+ u32Div = (((u32ClkSrc * 10) / u32BusClock + 5) / 10) - 1; /* Round to the nearest integer */
+ if(u32Div > 0xFF)
+ {
+ u32Div = 0xFF;
+ spi->CLKDIV |= SPI_CLKDIV_DIVIDER_Msk;
+ /* Return master peripheral clock rate */
+ return (u32ClkSrc / (0xFF + 1));
+ }
+ else
+ {
+ spi->CLKDIV = (spi->CLKDIV & (~SPI_CLKDIV_DIVIDER_Msk)) | (u32Div << SPI_CLKDIV_DIVIDER_Pos);
+ /* Return master peripheral clock rate */
+ return (u32ClkSrc / (u32Div + 1));
+ }
+ }
+}
+
+/**
+ * @brief Configure FIFO threshold setting.
+ * @param[in] spi The pointer of the specified SPI module.
+ * @param[in] u32TxThreshold Decides the TX FIFO threshold. For SPI0, it could be 0 ~ 7. For SPI1 and SPI2, it could be 0 ~ 3.
+ * @param[in] u32RxThreshold Decides the RX FIFO threshold. For SPI0, it could be 0 ~ 7. For SPI1 and SPI2, it could be 0 ~ 3.
+ * @return None
+ * @details Set TX FIFO threshold and RX FIFO threshold configurations.
+ */
+void SPI_SetFIFO(SPI_T *spi, uint32_t u32TxThreshold, uint32_t u32RxThreshold)
+{
+ spi->FIFOCTL = (spi->FIFOCTL & ~(SPI_FIFOCTL_TXTH_Msk | SPI_FIFOCTL_RXTH_Msk) |
+ (u32TxThreshold << SPI_FIFOCTL_TXTH_Pos) |
+ (u32RxThreshold << SPI_FIFOCTL_RXTH_Pos));
+}
+
+/**
+ * @brief Get the actual frequency of SPI bus clock. Only available in Master mode.
+ * @param[in] spi The pointer of the specified SPI module.
+ * @return Actual SPI bus clock frequency in Hz.
+ * @details This function will calculate the actual SPI bus clock rate according to the SPInSEL and DIVIDER settings. Only available in Master mode.
+ */
+uint32_t SPI_GetBusClock(SPI_T *spi)
+{
+ uint32_t u32Div;
+ uint32_t u32ClkSrc, u32HCLKFreq;
+
+ /* Get DIVIDER setting */
+ u32Div = (spi->CLKDIV & SPI_CLKDIV_DIVIDER_Msk) >> SPI_CLKDIV_DIVIDER_Pos;
+
+ /* Get system clock frequency */
+ u32HCLKFreq = CLK_GetHCLKFreq();
+
+ /* Check clock source of SPI */
+ if(spi == SPI0)
+ {
+ if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0SEL_Msk) == CLK_CLKSEL2_SPI0SEL_HXT)
+ u32ClkSrc = __HXT; /* Clock source is HXT */
+ else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0SEL_Msk) == CLK_CLKSEL2_SPI0SEL_PLL)
+ u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */
+ else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0SEL_Msk) == CLK_CLKSEL2_SPI0SEL_PCLK0)
+ {
+ /* Clock source is PCLK0 */
+ if((CLK->CLKSEL0 & CLK_CLKSEL0_PCLK0SEL_Msk) == CLK_CLKSEL0_PCLK0SEL_HCLK_DIV2)
+ u32ClkSrc = (u32HCLKFreq / 2);
+ else
+ u32ClkSrc = u32HCLKFreq;
+ }
+ else
+ u32ClkSrc = __HIRC; /* Clock source is HIRC */
+ }
+ else if(spi == SPI1)
+ {
+ if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI1SEL_Msk) == CLK_CLKSEL2_SPI1SEL_HXT)
+ u32ClkSrc = __HXT; /* Clock source is HXT */
+ else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI1SEL_Msk) == CLK_CLKSEL2_SPI1SEL_PLL)
+ u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */
+ else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI1SEL_Msk) == CLK_CLKSEL2_SPI1SEL_PCLK1)
+ {
+ /* Clock source is PCLK1 */
+ if((CLK->CLKSEL0 & CLK_CLKSEL0_PCLK1SEL_Msk) == CLK_CLKSEL0_PCLK1SEL_HCLK_DIV2)
+ u32ClkSrc = (u32HCLKFreq / 2);
+ else
+ u32ClkSrc = u32HCLKFreq;
+ }
+ else
+ u32ClkSrc = __HIRC; /* Clock source is HIRC */
+ }
+ else
+ {
+ if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI2SEL_Msk) == CLK_CLKSEL2_SPI2SEL_HXT)
+ u32ClkSrc = __HXT; /* Clock source is HXT */
+ else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI2SEL_Msk) == CLK_CLKSEL2_SPI2SEL_PLL)
+ u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */
+ else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI2SEL_Msk) == CLK_CLKSEL2_SPI2SEL_PCLK0)
+ {
+ /* Clock source is PCLK0 */
+ if((CLK->CLKSEL0 & CLK_CLKSEL0_PCLK0SEL_Msk) == CLK_CLKSEL0_PCLK0SEL_HCLK_DIV2)
+ u32ClkSrc = (u32HCLKFreq / 2);
+ else
+ u32ClkSrc = u32HCLKFreq;
+ }
+ else
+ u32ClkSrc = __HIRC; /* Clock source is HIRC */
+ }
+
+ /* Return SPI bus clock rate */
+ return (u32ClkSrc / (u32Div + 1));
+}
+
+/**
+ * @brief Enable interrupt function.
+ * @param[in] spi The pointer of the specified SPI module.
+ * @param[in] u32Mask The combination of all related interrupt enable bits.
+ * Each bit corresponds to a interrupt enable bit.
+ * This parameter decides which interrupts will be enabled. It is combination of:
+ * - \ref SPI_UNIT_INT_MASK
+ * - \ref SPI_SSACT_INT_MASK
+ * - \ref SPI_SSINACT_INT_MASK
+ * - \ref SPI_SLVUR_INT_MASK
+ * - \ref SPI_SLVBE_INT_MASK
+ * - \ref SPI_SLVTO_INT_MASK
+ * - \ref SPI_TXUF_INT_MASK
+ * - \ref SPI_FIFO_TXTH_INT_MASK
+ * - \ref SPI_FIFO_RXTH_INT_MASK
+ * - \ref SPI_FIFO_RXOV_INT_MASK
+ * - \ref SPI_FIFO_RXTO_INT_MASK
+ *
+ * @return None
+ * @details Enable SPI related interrupts specified by u32Mask parameter.
+ */
+void SPI_EnableInt(SPI_T *spi, uint32_t u32Mask)
+{
+ /* Enable unit transfer interrupt flag */
+ if((u32Mask & SPI_UNIT_INT_MASK) == SPI_UNIT_INT_MASK)
+ spi->CTL |= SPI_CTL_UNITIEN_Msk;
+
+ /* Enable slave selection signal active interrupt flag */
+ if((u32Mask & SPI_SSACT_INT_MASK) == SPI_SSACT_INT_MASK)
+ spi->SSCTL |= SPI_SSCTL_SSACTIEN_Msk;
+
+ /* Enable slave selection signal inactive interrupt flag */
+ if((u32Mask & SPI_SSINACT_INT_MASK) == SPI_SSINACT_INT_MASK)
+ spi->SSCTL |= SPI_SSCTL_SSINAIEN_Msk;
+
+ /* Enable slave TX under run interrupt flag */
+ if((u32Mask & SPI_SLVUR_INT_MASK) == SPI_SLVUR_INT_MASK)
+ spi->SSCTL |= SPI_SSCTL_SLVURIEN_Msk;
+
+ /* Enable slave bit count error interrupt flag */
+ if((u32Mask & SPI_SLVBE_INT_MASK) == SPI_SLVBE_INT_MASK)
+ spi->SSCTL |= SPI_SSCTL_SLVBEIEN_Msk;
+
+ /* Enable slave time-out interrupt flag */
+ if((u32Mask & SPI_SLVTO_INT_MASK) == SPI_SLVTO_INT_MASK)
+ spi->SSCTL |= SPI_SSCTL_SLVTOIEN_Msk;
+
+ /* Enable slave TX underflow interrupt flag */
+ if((u32Mask & SPI_TXUF_INT_MASK) == SPI_TXUF_INT_MASK)
+ spi->FIFOCTL |= SPI_FIFOCTL_TXUFIEN_Msk;
+
+ /* Enable TX threshold interrupt flag */
+ if((u32Mask & SPI_FIFO_TXTH_INT_MASK) == SPI_FIFO_TXTH_INT_MASK)
+ spi->FIFOCTL |= SPI_FIFOCTL_TXTHIEN_Msk;
+
+ /* Enable RX threshold interrupt flag */
+ if((u32Mask & SPI_FIFO_RXTH_INT_MASK) == SPI_FIFO_RXTH_INT_MASK)
+ spi->FIFOCTL |= SPI_FIFOCTL_RXTHIEN_Msk;
+
+ /* Enable RX overrun interrupt flag */
+ if((u32Mask & SPI_FIFO_RXOV_INT_MASK) == SPI_FIFO_RXOV_INT_MASK)
+ spi->FIFOCTL |= SPI_FIFOCTL_RXOVIEN_Msk;
+
+ /* Enable RX time-out interrupt flag */
+ if((u32Mask & SPI_FIFO_RXTO_INT_MASK) == SPI_FIFO_RXTO_INT_MASK)
+ spi->FIFOCTL |= SPI_FIFOCTL_RXTOIEN_Msk;
+}
+
+/**
+ * @brief Disable interrupt function.
+ * @param[in] spi The pointer of the specified SPI module.
+ * @param[in] u32Mask The combination of all related interrupt enable bits.
+ * Each bit corresponds to a interrupt bit.
+ * This parameter decides which interrupts will be disabled. It is combination of:
+ * - \ref SPI_UNIT_INT_MASK
+ * - \ref SPI_SSACT_INT_MASK
+ * - \ref SPI_SSINACT_INT_MASK
+ * - \ref SPI_SLVUR_INT_MASK
+ * - \ref SPI_SLVBE_INT_MASK
+ * - \ref SPI_SLVTO_INT_MASK
+ * - \ref SPI_TXUF_INT_MASK
+ * - \ref SPI_FIFO_TXTH_INT_MASK
+ * - \ref SPI_FIFO_RXTH_INT_MASK
+ * - \ref SPI_FIFO_RXOV_INT_MASK
+ * - \ref SPI_FIFO_RXTO_INT_MASK
+ *
+ * @return None
+ * @details Disable SPI related interrupts specified by u32Mask parameter.
+ */
+void SPI_DisableInt(SPI_T *spi, uint32_t u32Mask)
+{
+ /* Disable unit transfer interrupt flag */
+ if((u32Mask & SPI_UNIT_INT_MASK) == SPI_UNIT_INT_MASK)
+ spi->CTL &= ~SPI_CTL_UNITIEN_Msk;
+
+ /* Disable slave selection signal active interrupt flag */
+ if((u32Mask & SPI_SSACT_INT_MASK) == SPI_SSACT_INT_MASK)
+ spi->SSCTL &= ~SPI_SSCTL_SSACTIEN_Msk;
+
+ /* Disable slave selection signal inactive interrupt flag */
+ if((u32Mask & SPI_SSINACT_INT_MASK) == SPI_SSINACT_INT_MASK)
+ spi->SSCTL &= ~SPI_SSCTL_SSINAIEN_Msk;
+
+ /* Disable slave TX under run interrupt flag */
+ if((u32Mask & SPI_SLVUR_INT_MASK) == SPI_SLVUR_INT_MASK)
+ spi->SSCTL &= ~SPI_SSCTL_SLVURIEN_Msk;
+
+ /* Disable slave bit count error interrupt flag */
+ if((u32Mask & SPI_SLVBE_INT_MASK) == SPI_SLVBE_INT_MASK)
+ spi->SSCTL &= ~SPI_SSCTL_SLVBEIEN_Msk;
+
+ /* Disable slave time-out interrupt flag */
+ if((u32Mask & SPI_SLVTO_INT_MASK) == SPI_SLVTO_INT_MASK)
+ spi->SSCTL &= ~SPI_SSCTL_SLVTOIEN_Msk;
+
+ /* Disable slave TX underflow interrupt flag */
+ if((u32Mask & SPI_TXUF_INT_MASK) == SPI_TXUF_INT_MASK)
+ spi->FIFOCTL &= ~SPI_FIFOCTL_TXUFIEN_Msk;
+
+ /* Disable TX threshold interrupt flag */
+ if((u32Mask & SPI_FIFO_TXTH_INT_MASK) == SPI_FIFO_TXTH_INT_MASK)
+ spi->FIFOCTL &= ~SPI_FIFOCTL_TXTHIEN_Msk;
+
+ /* Disable RX threshold interrupt flag */
+ if((u32Mask & SPI_FIFO_RXTH_INT_MASK) == SPI_FIFO_RXTH_INT_MASK)
+ spi->FIFOCTL &= ~SPI_FIFOCTL_RXTHIEN_Msk;
+
+ /* Disable RX overrun interrupt flag */
+ if((u32Mask & SPI_FIFO_RXOV_INT_MASK) == SPI_FIFO_RXOV_INT_MASK)
+ spi->FIFOCTL &= ~SPI_FIFOCTL_RXOVIEN_Msk;
+
+ /* Disable RX time-out interrupt flag */
+ if((u32Mask & SPI_FIFO_RXTO_INT_MASK) == SPI_FIFO_RXTO_INT_MASK)
+ spi->FIFOCTL &= ~SPI_FIFOCTL_RXTOIEN_Msk;
+}
+
+/**
+ * @brief Get interrupt flag.
+ * @param[in] spi The pointer of the specified SPI module.
+ * @param[in] u32Mask The combination of all related interrupt sources.
+ * Each bit corresponds to a interrupt source.
+ * This parameter decides which interrupt flags will be read. It is combination of:
+ * - \ref SPI_UNIT_INT_MASK
+ * - \ref SPI_SSACT_INT_MASK
+ * - \ref SPI_SSINACT_INT_MASK
+ * - \ref SPI_SLVUR_INT_MASK
+ * - \ref SPI_SLVBE_INT_MASK
+ * - \ref SPI_SLVTO_INT_MASK
+ * - \ref SPI_TXUF_INT_MASK
+ * - \ref SPI_FIFO_TXTH_INT_MASK
+ * - \ref SPI_FIFO_RXTH_INT_MASK
+ * - \ref SPI_FIFO_RXOV_INT_MASK
+ * - \ref SPI_FIFO_RXTO_INT_MASK
+ *
+ * @return Interrupt flags of selected sources.
+ * @details Get SPI related interrupt flags specified by u32Mask parameter.
+ */
+uint32_t SPI_GetIntFlag(SPI_T *spi, uint32_t u32Mask)
+{
+ uint32_t u32IntFlag = 0;
+
+ /* Check unit transfer interrupt flag */
+ if((u32Mask & SPI_UNIT_INT_MASK) && (spi->STATUS & SPI_STATUS_UNITIF_Msk))
+ u32IntFlag |= SPI_UNIT_INT_MASK;
+
+ /* Check slave selection signal active interrupt flag */
+ if((u32Mask & SPI_SSACT_INT_MASK) && (spi->STATUS & SPI_STATUS_SSACTIF_Msk))
+ u32IntFlag |= SPI_SSACT_INT_MASK;
+
+ /* Check slave selection signal inactive interrupt flag */
+ if((u32Mask & SPI_SSINACT_INT_MASK) && (spi->STATUS & SPI_STATUS_SSINAIF_Msk))
+ u32IntFlag |= SPI_SSINACT_INT_MASK;
+
+ /* Check slave TX under run interrupt flag */
+ if((u32Mask & SPI_SLVUR_INT_MASK) && (spi->STATUS & SPI_STATUS_SLVURIF_Msk))
+ u32IntFlag |= SPI_SLVUR_INT_MASK;
+
+ /* Check slave bit count error interrupt flag */
+ if((u32Mask & SPI_SLVBE_INT_MASK) && (spi->STATUS & SPI_STATUS_SLVBEIF_Msk))
+ u32IntFlag |= SPI_SLVBE_INT_MASK;
+
+ /* Check slave time-out interrupt flag */
+ if((u32Mask & SPI_SLVTO_INT_MASK) && (spi->STATUS & SPI_STATUS_SLVTOIF_Msk))
+ u32IntFlag |= SPI_SLVTO_INT_MASK;
+
+ /* Check slave TX underflow interrupt flag */
+ if((u32Mask & SPI_TXUF_INT_MASK) && (spi->STATUS & SPI_STATUS_TXUFIF_Msk))
+ u32IntFlag |= SPI_TXUF_INT_MASK;
+
+ /* Check TX threshold interrupt flag */
+ if((u32Mask & SPI_FIFO_TXTH_INT_MASK) && (spi->STATUS & SPI_STATUS_TXTHIF_Msk))
+ u32IntFlag |= SPI_FIFO_TXTH_INT_MASK;
+
+ /* Check RX threshold interrupt flag */
+ if((u32Mask & SPI_FIFO_RXTH_INT_MASK) && (spi->STATUS & SPI_STATUS_RXTHIF_Msk))
+ u32IntFlag |= SPI_FIFO_RXTH_INT_MASK;
+
+ /* Check RX overrun interrupt flag */
+ if((u32Mask & SPI_FIFO_RXOV_INT_MASK) && (spi->STATUS & SPI_STATUS_RXOVIF_Msk))
+ u32IntFlag |= SPI_FIFO_RXOV_INT_MASK;
+
+ /* Check RX time-out interrupt flag */
+ if((u32Mask & SPI_FIFO_RXTO_INT_MASK) && (spi->STATUS & SPI_STATUS_RXTOIF_Msk))
+ u32IntFlag |= SPI_FIFO_RXTO_INT_MASK;
+
+ return u32IntFlag;
+}
+
+/**
+ * @brief Clear interrupt flag.
+ * @param[in] spi The pointer of the specified SPI module.
+ * @param[in] u32Mask The combination of all related interrupt sources.
+ * Each bit corresponds to a interrupt source.
+ * This parameter decides which interrupt flags will be cleared. It could be the combination of:
+ * - \ref SPI_UNIT_INT_MASK
+ * - \ref SPI_SSACT_INT_MASK
+ * - \ref SPI_SSINACT_INT_MASK
+ * - \ref SPI_SLVUR_INT_MASK
+ * - \ref SPI_SLVBE_INT_MASK
+ * - \ref SPI_SLVTO_INT_MASK
+ * - \ref SPI_TXUF_INT_MASK
+ * - \ref SPI_FIFO_RXOV_INT_MASK
+ * - \ref SPI_FIFO_RXTO_INT_MASK
+ *
+ * @return None
+ * @details Clear SPI related interrupt flags specified by u32Mask parameter.
+ */
+void SPI_ClearIntFlag(SPI_T *spi, uint32_t u32Mask)
+{
+ if(u32Mask & SPI_UNIT_INT_MASK)
+ spi->STATUS = SPI_STATUS_UNITIF_Msk; /* Clear unit transfer interrupt flag */
+
+ if(u32Mask & SPI_SSACT_INT_MASK)
+ spi->STATUS = SPI_STATUS_SSACTIF_Msk; /* Clear slave selection signal active interrupt flag */
+
+ if(u32Mask & SPI_SSINACT_INT_MASK)
+ spi->STATUS = SPI_STATUS_SSINAIF_Msk; /* Clear slave selection signal inactive interrupt flag */
+
+ if(u32Mask & SPI_SLVUR_INT_MASK)
+ spi->STATUS = SPI_STATUS_SLVURIF_Msk; /* Clear slave TX under run interrupt flag */
+
+ if(u32Mask & SPI_SLVBE_INT_MASK)
+ spi->STATUS = SPI_STATUS_SLVBEIF_Msk; /* Clear slave bit count error interrupt flag */
+
+ if(u32Mask & SPI_SLVTO_INT_MASK)
+ spi->STATUS = SPI_STATUS_SLVTOIF_Msk; /* Clear slave time-out interrupt flag */
+
+ if(u32Mask & SPI_TXUF_INT_MASK)
+ spi->STATUS = SPI_STATUS_TXUFIF_Msk; /* Clear slave TX underflow interrupt flag */
+
+ if(u32Mask & SPI_FIFO_RXOV_INT_MASK)
+ spi->STATUS = SPI_STATUS_RXOVIF_Msk; /* Clear RX overrun interrupt flag */
+
+ if(u32Mask & SPI_FIFO_RXTO_INT_MASK)
+ spi->STATUS = SPI_STATUS_RXTOIF_Msk; /* Clear RX time-out interrupt flag */
+}
+
+/**
+ * @brief Get SPI status.
+ * @param[in] spi The pointer of the specified SPI module.
+ * @param[in] u32Mask The combination of all related sources.
+ * Each bit corresponds to a source.
+ * This parameter decides which flags will be read. It is combination of:
+ * - \ref SPI_BUSY_MASK
+ * - \ref SPI_RX_EMPTY_MASK
+ * - \ref SPI_RX_FULL_MASK
+ * - \ref SPI_TX_EMPTY_MASK
+ * - \ref SPI_TX_FULL_MASK
+ * - \ref SPI_TXRX_RESET_MASK
+ * - \ref SPI_SPIEN_STS_MASK
+ * - \ref SPI_SSLINE_STS_MASK
+ *
+ * @return Flags of selected sources.
+ * @details Get SPI related status specified by u32Mask parameter.
+ */
+uint32_t SPI_GetStatus(SPI_T *spi, uint32_t u32Mask)
+{
+ uint32_t u32Flag = 0;
+
+ /* Check busy status */
+ if((u32Mask & SPI_BUSY_MASK) && (spi->STATUS & SPI_STATUS_BUSY_Msk))
+ u32Flag |= SPI_BUSY_MASK;
+
+ /* Check RX empty flag */
+ if((u32Mask & SPI_RX_EMPTY_MASK) && (spi->STATUS & SPI_STATUS_RXEMPTY_Msk))
+ u32Flag |= SPI_RX_EMPTY_MASK;
+
+ /* Check RX full flag */
+ if((u32Mask & SPI_RX_FULL_MASK) && (spi->STATUS & SPI_STATUS_RXFULL_Msk))
+ u32Flag |= SPI_RX_FULL_MASK;
+
+ /* Check TX empty flag */
+ if((u32Mask & SPI_TX_EMPTY_MASK) && (spi->STATUS & SPI_STATUS_TXEMPTY_Msk))
+ u32Flag |= SPI_TX_EMPTY_MASK;
+
+ /* Check TX full flag */
+ if((u32Mask & SPI_TX_FULL_MASK) && (spi->STATUS & SPI_STATUS_TXFULL_Msk))
+ u32Flag |= SPI_TX_FULL_MASK;
+
+ /* Check TX/RX reset flag */
+ if((u32Mask & SPI_TXRX_RESET_MASK) && (spi->STATUS & SPI_STATUS_TXRXRST_Msk))
+ u32Flag |= SPI_TXRX_RESET_MASK;
+
+ /* Check SPIEN flag */
+ if((u32Mask & SPI_SPIEN_STS_MASK) && (spi->STATUS & SPI_STATUS_SPIENSTS_Msk))
+ u32Flag |= SPI_SPIEN_STS_MASK;
+
+ /* Check SPIn_SS line status */
+ if((u32Mask & SPI_SSLINE_STS_MASK) && (spi->STATUS & SPI_STATUS_SSLINE_Msk))
+ u32Flag |= SPI_SSLINE_STS_MASK;
+
+ return u32Flag;
+}
+
+
+/**
+ * @brief This function is used to get I2S source clock frequency.
+ * @param[in] i2s The pointer of the specified I2S module.
+ * @return I2S source clock frequency (Hz).
+ * @details Return the source clock frequency according to the setting of SPI1SEL (CLKSEL2[5:4]) or SPI2SEL (CLKSEL2[7:6]).
+ * @note Only SPI1 and SPI2 support I2S mode.
+ */
+static uint32_t I2S_GetSourceClockFreq(SPI_T *i2s)
+{
+ uint32_t u32Freq, u32HCLKFreq;
+
+ if(i2s == SPI1)
+ {
+ if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI1SEL_Msk) == CLK_CLKSEL2_SPI1SEL_HXT)
+ u32Freq = __HXT; /* Clock source is HXT */
+ else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI1SEL_Msk) == CLK_CLKSEL2_SPI1SEL_PLL)
+ u32Freq = CLK_GetPLLClockFreq(); /* Clock source is PLL */
+ else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI1SEL_Msk) == CLK_CLKSEL2_SPI1SEL_PCLK1)
+ {
+ /* Get system clock frequency */
+ u32HCLKFreq = CLK_GetHCLKFreq();
+ /* Clock source is PCLK1 */
+ if((CLK->CLKSEL0 & CLK_CLKSEL0_PCLK1SEL_Msk) == CLK_CLKSEL0_PCLK1SEL_HCLK_DIV2)
+ u32Freq = (u32HCLKFreq / 2);
+ else
+ u32Freq = u32HCLKFreq;
+ }
+ else
+ u32Freq = __HIRC; /* Clock source is HIRC */
+ }
+ else
+ {
+ if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI2SEL_Msk) == CLK_CLKSEL2_SPI2SEL_HXT)
+ u32Freq = __HXT; /* Clock source is HXT */
+ else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI2SEL_Msk) == CLK_CLKSEL2_SPI2SEL_PLL)
+ u32Freq = CLK_GetPLLClockFreq(); /* Clock source is PLL */
+ else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI2SEL_Msk) == CLK_CLKSEL2_SPI2SEL_PCLK0)
+ {
+ /* Get system clock frequency */
+ u32HCLKFreq = CLK_GetHCLKFreq();
+ /* Clock source is PCLK0 */
+ if((CLK->CLKSEL0 & CLK_CLKSEL0_PCLK0SEL_Msk) == CLK_CLKSEL0_PCLK0SEL_HCLK_DIV2)
+ u32Freq = (u32HCLKFreq / 2);
+ else
+ u32Freq = u32HCLKFreq;
+ }
+ else
+ u32Freq = __HIRC; /* Clock source is HIRC */
+ }
+
+ return u32Freq;
+}
+
+/**
+ * @brief This function configures some parameters of I2S interface for general purpose use.
+ * @param[in] i2s The pointer of the specified I2S module.
+ * @param[in] u32MasterSlave I2S operation mode. Valid values are listed below.
+ * - \ref I2S_MODE_MASTER
+ * - \ref I2S_MODE_SLAVE
+ * @param[in] u32SampleRate Sample rate
+ * @param[in] u32WordWidth Data length. Valid values are listed below.
+ * - \ref I2S_DATABIT_8
+ * - \ref I2S_DATABIT_16
+ * - \ref I2S_DATABIT_24
+ * - \ref I2S_DATABIT_32
+ * @param[in] u32Channels Audio format. Valid values are listed below.
+ * - \ref I2S_MONO
+ * - \ref I2S_STEREO
+ * @param[in] u32DataFormat Data format. Valid values are listed below.
+ * - \ref I2S_FORMAT_I2S
+ * - \ref I2S_FORMAT_MSB
+ * - \ref I2S_FORMAT_PCMA
+ * - \ref I2S_FORMAT_PCMB
+ * @return Real sample rate of master mode or peripheral clock rate of slave mode.
+ * @details This function will reset SPI/I2S controller and configure I2S controller according to the input parameters.
+ * Set TX and RX FIFO threshold to middle value. Both the TX and RX functions will be enabled.
+ * The actual sample rate may be different from the target sample rate. The real sample rate will be returned for reference.
+ * @note Only SPI1 and SPI2 support I2S mode.
+ * @note In slave mode, the SPI peripheral clock rate will be equal to APB clock rate.
+ */
+uint32_t I2S_Open(SPI_T *i2s, uint32_t u32MasterSlave, uint32_t u32SampleRate, uint32_t u32WordWidth, uint32_t u32Channels, uint32_t u32DataFormat)
+{
+ uint32_t u32Divider;
+ uint32_t u32BitRate, u32SrcClk;
+ uint32_t u32HCLKFreq;
+
+ /* Reset SPI/I2S */
+ if(i2s == SPI1)
+ {
+ SYS->IPRST1 |= SYS_IPRST1_SPI1RST_Msk;
+ SYS->IPRST1 &= ~SYS_IPRST1_SPI1RST_Msk;
+ }
+ else
+ {
+ SYS->IPRST1 |= SYS_IPRST1_SPI2RST_Msk;
+ SYS->IPRST1 &= ~SYS_IPRST1_SPI2RST_Msk;
+ }
+
+ /* Configure I2S controller */
+ i2s->I2SCTL = u32MasterSlave | u32WordWidth | u32Channels | u32DataFormat;
+ /* Set TX and RX FIFO threshold to middle value */
+ i2s->FIFOCTL = I2S_FIFO_TX_LEVEL_WORD_2 | I2S_FIFO_RX_LEVEL_WORD_2;
+
+ if(u32MasterSlave == SPI_MASTER)
+ {
+ /* Get the source clock rate */
+ u32SrcClk = I2S_GetSourceClockFreq(i2s);
+
+ /* Calculate the bit clock rate */
+ u32BitRate = u32SampleRate * ((u32WordWidth >> SPI_I2SCTL_WDWIDTH_Pos) + 1) * 16;
+ u32Divider = ((u32SrcClk / u32BitRate) >> 1) - 1;
+ /* Set BCLKDIV setting */
+ i2s->I2SCLK = (i2s->I2SCLK & ~SPI_I2SCLK_BCLKDIV_Msk) | (u32Divider << SPI_I2SCLK_BCLKDIV_Pos);
+
+ /* Calculate bit clock rate */
+ u32BitRate = u32SrcClk / ((u32Divider + 1) * 2);
+ /* Calculate real sample rate */
+ u32SampleRate = u32BitRate / (((u32WordWidth >> SPI_I2SCTL_WDWIDTH_Pos) + 1) * 16);
+
+ /* Enable TX function, RX function and I2S mode. */
+ i2s->I2SCTL |= (SPI_I2SCTL_RXEN_Msk | SPI_I2SCTL_TXEN_Msk | SPI_I2SCTL_I2SEN_Msk);
+
+ /* Return the real sample rate */
+ return u32SampleRate;
+ }
+ else
+ {
+ /* Set BCLKDIV = 0 */
+ i2s->I2SCLK &= ~SPI_I2SCLK_BCLKDIV_Msk;
+ /* Get system clock frequency */
+ u32HCLKFreq = CLK_GetHCLKFreq();
+
+ if(i2s == SPI1)
+ {
+ /* Set the peripheral clock rate to equal APB clock rate */
+ CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI1SEL_Msk)) | CLK_CLKSEL2_SPI1SEL_PCLK1;
+ /* Enable TX function, RX function and I2S mode. */
+ i2s->I2SCTL |= (SPI_I2SCTL_RXEN_Msk | SPI_I2SCTL_TXEN_Msk | SPI_I2SCTL_I2SEN_Msk);
+ /* Return slave peripheral clock rate */
+ if((CLK->CLKSEL0 & CLK_CLKSEL0_PCLK1SEL_Msk) == CLK_CLKSEL0_PCLK1SEL_HCLK_DIV2)
+ return (u32HCLKFreq / 2);
+ else
+ return u32HCLKFreq;
+ }
+ else
+ {
+ /* Set the peripheral clock rate to equal APB clock rate */
+ CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI2SEL_Msk)) | CLK_CLKSEL2_SPI2SEL_PCLK0;
+ /* Enable TX function, RX function and I2S mode. */
+ i2s->I2SCTL |= (SPI_I2SCTL_RXEN_Msk | SPI_I2SCTL_TXEN_Msk | SPI_I2SCTL_I2SEN_Msk);
+ /* Return slave peripheral clock rate */
+ if((CLK->CLKSEL0 & CLK_CLKSEL0_PCLK0SEL_Msk) == CLK_CLKSEL0_PCLK0SEL_HCLK_DIV2)
+ return (u32HCLKFreq / 2);
+ else
+ return u32HCLKFreq;
+ }
+ }
+}
+
+/**
+ * @brief Disable I2S function.
+ * @param[in] i2s The pointer of the specified I2S module.
+ * @return None
+ * @details Disable I2S function.
+ * @note Only SPI1 and SPI2 support I2S mode.
+ */
+void I2S_Close(SPI_T *i2s)
+{
+ i2s->I2SCTL &= ~SPI_I2SCTL_I2SEN_Msk;
+}
+
+/**
+ * @brief Enable interrupt function.
+ * @param[in] i2s The pointer of the specified I2S module.
+ * @param[in] u32Mask The combination of all related interrupt enable bits.
+ * Each bit corresponds to a interrupt source. Valid values are listed below.
+ * - \ref I2S_FIFO_TXTH_INT_MASK
+ * - \ref I2S_FIFO_RXTH_INT_MASK
+ * - \ref I2S_FIFO_RXOV_INT_MASK
+ * - \ref I2S_FIFO_RXTO_INT_MASK
+ * - \ref I2S_TXUF_INT_MASK
+ * - \ref I2S_RIGHT_ZC_INT_MASK
+ * - \ref I2S_LEFT_ZC_INT_MASK
+ * @return None
+ * @details This function enables the interrupt according to the u32Mask parameter.
+ * @note Only SPI1 and SPI2 support I2S mode.
+ */
+void I2S_EnableInt(SPI_T *i2s, uint32_t u32Mask)
+{
+ /* Enable TX threshold interrupt flag */
+ if((u32Mask & I2S_FIFO_TXTH_INT_MASK) == I2S_FIFO_TXTH_INT_MASK)
+ i2s->FIFOCTL |= SPI_FIFOCTL_TXTHIEN_Msk;
+
+ /* Enable RX threshold interrupt flag */
+ if((u32Mask & I2S_FIFO_RXTH_INT_MASK) == I2S_FIFO_RXTH_INT_MASK)
+ i2s->FIFOCTL |= SPI_FIFOCTL_RXTHIEN_Msk;
+
+ /* Enable RX overrun interrupt flag */
+ if((u32Mask & I2S_FIFO_RXOV_INT_MASK) == I2S_FIFO_RXOV_INT_MASK)
+ i2s->FIFOCTL |= SPI_FIFOCTL_RXOVIEN_Msk;
+
+ /* Enable RX time-out interrupt flag */
+ if((u32Mask & I2S_FIFO_RXTO_INT_MASK) == I2S_FIFO_RXTO_INT_MASK)
+ i2s->FIFOCTL |= SPI_FIFOCTL_RXTOIEN_Msk;
+
+ /* Enable TX underflow interrupt flag */
+ if((u32Mask & I2S_TXUF_INT_MASK) == I2S_TXUF_INT_MASK)
+ i2s->FIFOCTL |= SPI_FIFOCTL_TXUFIEN_Msk;
+
+ /* Enable right channel zero cross interrupt flag */
+ if((u32Mask & I2S_RIGHT_ZC_INT_MASK) == I2S_RIGHT_ZC_INT_MASK)
+ i2s->I2SCTL |= SPI_I2SCTL_RZCIEN_Msk;
+
+ /* Enable left channel zero cross interrupt flag */
+ if((u32Mask & I2S_LEFT_ZC_INT_MASK) == I2S_LEFT_ZC_INT_MASK)
+ i2s->I2SCTL |= SPI_I2SCTL_LZCIEN_Msk;
+}
+
+/**
+ * @brief Disable interrupt function.
+ * @param[in] i2s The pointer of the specified I2S module.
+ * @param[in] u32Mask The combination of all related interrupt enable bits.
+ * Each bit corresponds to a interrupt source. Valid values are listed below.
+ * - \ref I2S_FIFO_TXTH_INT_MASK
+ * - \ref I2S_FIFO_RXTH_INT_MASK
+ * - \ref I2S_FIFO_RXOV_INT_MASK
+ * - \ref I2S_FIFO_RXTO_INT_MASK
+ * - \ref I2S_TXUF_INT_MASK
+ * - \ref I2S_RIGHT_ZC_INT_MASK
+ * - \ref I2S_LEFT_ZC_INT_MASK
+ * @return None
+ * @details This function disables the interrupt according to the u32Mask parameter.
+ * @note Only SPI1 and SPI2 support I2S mode.
+ */
+void I2S_DisableInt(SPI_T *i2s, uint32_t u32Mask)
+{
+ /* Disable TX threshold interrupt flag */
+ if((u32Mask & I2S_FIFO_TXTH_INT_MASK) == I2S_FIFO_TXTH_INT_MASK)
+ i2s->FIFOCTL &= ~SPI_FIFOCTL_TXTHIEN_Msk;
+
+ /* Disable RX threshold interrupt flag */
+ if((u32Mask & I2S_FIFO_RXTH_INT_MASK) == I2S_FIFO_RXTH_INT_MASK)
+ i2s->FIFOCTL &= ~SPI_FIFOCTL_RXTHIEN_Msk;
+
+ /* Disable RX overrun interrupt flag */
+ if((u32Mask & I2S_FIFO_RXOV_INT_MASK) == I2S_FIFO_RXOV_INT_MASK)
+ i2s->FIFOCTL &= ~SPI_FIFOCTL_RXOVIEN_Msk;
+
+ /* Disable RX time-out interrupt flag */
+ if((u32Mask & I2S_FIFO_RXTO_INT_MASK) == I2S_FIFO_RXTO_INT_MASK)
+ i2s->FIFOCTL &= ~SPI_FIFOCTL_RXTOIEN_Msk;
+
+ /* Disable TX underflow interrupt flag */
+ if((u32Mask & I2S_TXUF_INT_MASK) == I2S_TXUF_INT_MASK)
+ i2s->FIFOCTL &= ~SPI_FIFOCTL_TXUFIEN_Msk;
+
+ /* Disable right channel zero cross interrupt flag */
+ if((u32Mask & I2S_RIGHT_ZC_INT_MASK) == I2S_RIGHT_ZC_INT_MASK)
+ i2s->I2SCTL &= ~SPI_I2SCTL_RZCIEN_Msk;
+
+ /* Disable left channel zero cross interrupt flag */
+ if((u32Mask & I2S_LEFT_ZC_INT_MASK) == I2S_LEFT_ZC_INT_MASK)
+ i2s->I2SCTL &= ~SPI_I2SCTL_LZCIEN_Msk;
+}
+
+/**
+ * @brief Enable master clock (MCLK).
+ * @param[in] i2s The pointer of the specified I2S module.
+ * @param[in] u32BusClock The target MCLK clock rate.
+ * @return Actual MCLK clock rate
+ * @details Set the master clock rate according to u32BusClock parameter and enable master clock output.
+ * The actual master clock rate may be different from the target master clock rate. The real master clock rate will be returned for reference.
+ * @note Only SPI1 and SPI2 support I2S mode.
+ */
+uint32_t I2S_EnableMCLK(SPI_T *i2s, uint32_t u32BusClock)
+{
+ uint32_t u32Divider;
+ uint32_t u32SrcClk;
+
+ u32SrcClk = I2S_GetSourceClockFreq(i2s);
+ if(u32BusClock == u32SrcClk)
+ u32Divider = 0;
+ else
+ {
+ u32Divider = (u32SrcClk / u32BusClock) >> 1;
+ /* MCLKDIV is a 6-bit width configuration. The maximum value is 0x3F. */
+ if(u32Divider > 0x3F)
+ u32Divider = 0x3F;
+ }
+
+ /* Write u32Divider to MCLKDIV (SPI_I2SCLK[5:0]) */
+ i2s->I2SCLK = (i2s->I2SCLK & ~SPI_I2SCLK_MCLKDIV_Msk) | (u32Divider << SPI_I2SCLK_MCLKDIV_Pos);
+
+ /* Enable MCLK output */
+ i2s->I2SCTL |= SPI_I2SCTL_MCLKEN_Msk;
+
+ if(u32Divider == 0)
+ return u32SrcClk; /* If MCLKDIV=0, master clock rate is equal to the source clock rate. */
+ else
+ return ((u32SrcClk >> 1) / u32Divider); /* If MCLKDIV>0, master clock rate = source clock rate / (MCLKDIV * 2) */
+}
+
+/**
+ * @brief Disable master clock (MCLK).
+ * @param[in] i2s The pointer of the specified I2S module.
+ * @return None
+ * @details Clear MCLKEN bit of SPI_I2SCTL register to disable master clock output.
+ * @note Only SPI1 and SPI2 support I2S mode.
+ */
+void I2S_DisableMCLK(SPI_T *i2s)
+{
+ i2s->I2SCTL &= ~SPI_I2SCTL_MCLKEN_Msk;
+}
+
+/**
+ * @brief Configure FIFO threshold setting.
+ * @param[in] i2s The pointer of the specified I2S module.
+ * @param[in] u32TxThreshold Decides the TX FIFO threshold. It could be 0 ~ 3.
+ * @param[in] u32RxThreshold Decides the RX FIFO threshold. It could be 0 ~ 3.
+ * @return None
+ * @details Set TX FIFO threshold and RX FIFO threshold configurations.
+ */
+void I2S_SetFIFO(SPI_T *i2s, uint32_t u32TxThreshold, uint32_t u32RxThreshold)
+{
+ i2s->FIFOCTL = (i2s->FIFOCTL & ~(SPI_FIFOCTL_TXTH_Msk | SPI_FIFOCTL_RXTH_Msk) |
+ (u32TxThreshold << SPI_FIFOCTL_TXTH_Pos) |
+ (u32RxThreshold << SPI_FIFOCTL_RXTH_Pos));
+}
+
+/*@}*/ /* end of group SPI_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group SPI_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+/*** (C) COPYRIGHT 2014~2015 Nuvoton Technology Corp. ***/
diff --git a/bsp/nuvoton_m451/Libraries/StdDriver/src/sys.c b/bsp/nuvoton_m451/Libraries/StdDriver/src/sys.c
new file mode 100644
index 0000000000000000000000000000000000000000..bc127c7e3fd22cac7816a57c81fdeba39e3a3d46
--- /dev/null
+++ b/bsp/nuvoton_m451/Libraries/StdDriver/src/sys.c
@@ -0,0 +1,213 @@
+/**************************************************************************//**
+ * @file sys.c
+ * @version V3.00
+ * $Revision: 12 $
+ * $Date: 15/08/11 10:26a $
+ * @brief M451 series SYS driver source file
+ *
+ * @note
+ * Copyright (C) 2014~2015 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+
+#include "M451Series.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/** @addtogroup Standard_Driver Standard Driver
+ @{
+*/
+
+/** @addtogroup SYS_Driver SYS Driver
+ @{
+*/
+
+
+/** @addtogroup SYS_EXPORTED_FUNCTIONS SYS Exported Functions
+ @{
+*/
+
+/**
+ * @brief Clear reset source
+ * @param[in] u32Src is system reset source. Including :
+ * - \ref SYS_RSTSTS_CPURF_Msk
+ * - \ref SYS_RSTSTS_SYSRF_Msk
+ * - \ref SYS_RSTSTS_BODRF_Msk
+ * - \ref SYS_RSTSTS_LVRF_Msk
+ * - \ref SYS_RSTSTS_WDTRF_Msk
+ * - \ref SYS_RSTSTS_PINRF_Msk
+ * - \ref SYS_RSTSTS_PORF_Msk
+ * @return None
+ * @details This function clear the selected system reset source.
+ */
+void SYS_ClearResetSrc(uint32_t u32Src)
+{
+ SYS->RSTSTS |= u32Src;
+}
+
+/**
+ * @brief Get Brown-out detector output status
+ * @param None
+ * @retval 0 System voltage is higher than BOD_VL setting or BOD_EN is 0.
+ * @retval 1 System voltage is lower than BOD_VL setting.
+ * @details This function get Brown-out detector output status.
+ */
+uint32_t SYS_GetBODStatus(void)
+{
+ return ((SYS->BODCTL & SYS_BODCTL_BODOUT_Msk) >> SYS_BODCTL_BODOUT_Pos);
+}
+
+/**
+ * @brief Get reset status register value
+ * @param None
+ * @return Reset source
+ * @details This function get the system reset status register value.
+ */
+uint32_t SYS_GetResetSrc(void)
+{
+ return (SYS->RSTSTS);
+}
+
+/**
+ * @brief Check if register is locked nor not
+ * @param None
+ * @retval 0 Write-protection function is disabled.
+ * 1 Write-protection function is enabled.
+ * @details This function check register write-protection bit setting.
+ */
+uint32_t SYS_IsRegLocked(void)
+{
+ return !(SYS->REGLCTL & 0x1);
+}
+
+/**
+ * @brief Get product ID
+ * @param None
+ * @return Product ID
+ * @details This function get product ID.
+ */
+uint32_t SYS_ReadPDID(void)
+{
+ return SYS->PDID;
+}
+
+/**
+ * @brief Reset chip with chip reset
+ * @param None
+ * @return None
+ * @details This function reset chip with chip reset.
+ * The register write-protection function should be disabled before using this function.
+ */
+void SYS_ResetChip(void)
+{
+ SYS->IPRST0 |= SYS_IPRST0_CHIPRST_Msk;
+}
+
+/**
+ * @brief Reset chip with CPU reset
+ * @param None
+ * @return None
+ * @details This function reset CPU with CPU reset.
+ * The register write-protection function should be disabled before using this function.
+ */
+void SYS_ResetCPU(void)
+{
+ SYS->IPRST0 |= SYS_IPRST0_CPURST_Msk;
+}
+
+/**
+ * @brief Reset selected module
+ * @param[in] u32ModuleIndex is module index. Including :
+ * - \ref PDMA_RST
+ * - \ref EBI_RST
+ * - \ref USBH_RST
+ * - \ref CRC_RST
+ * - \ref GPIO_RST
+ * - \ref TMR0_RST
+ * - \ref TMR1_RST
+ * - \ref TMR2_RST
+ * - \ref TMR3_RST
+ * - \ref ACMP01_RST
+ * - \ref I2C0_RST
+ * - \ref I2C1_RST
+ * - \ref SPI0_RST
+ * - \ref SPI1_RST
+ * - \ref SPI2_RST
+ * - \ref UART0_RST
+ * - \ref UART1_RST
+ * - \ref UART2_RST
+ * - \ref UART3_RST
+ * - \ref CAN0_RST
+ * - \ref OTG_RST
+ * - \ref USBD_RST
+ * - \ref EADC_RST
+ * - \ref SC0_RST
+ * - \ref DAC_RST
+ * - \ref PWM0_RST
+ * - \ref PWM1_RST
+ * - \ref TK_RST
+ * @return None
+ * @details This function reset selected module.
+ */
+void SYS_ResetModule(uint32_t u32ModuleIndex)
+{
+ /* Generate reset signal to the corresponding module */
+ *(volatile uint32_t *)((uint32_t)&SYS->IPRST0 + (u32ModuleIndex >> 24)) |= 1 << (u32ModuleIndex & 0x00ffffff);
+
+ /* Release corresponding module from reset state */
+ *(volatile uint32_t *)((uint32_t)&SYS->IPRST0 + (u32ModuleIndex >> 24)) &= ~(1 << (u32ModuleIndex & 0x00ffffff));
+}
+
+/**
+ * @brief Enable and configure Brown-out detector function
+ * @param[in] i32Mode is reset or interrupt mode. Including :
+ * - \ref SYS_BODCTL_BOD_RST_EN
+ * - \ref SYS_BODCTL_BOD_INTERRUPT_EN
+ * @param[in] u32BODLevel is Brown-out voltage level. Including :
+ * - \ref SYS_BODCTL_BODVL_4_5V
+ * - \ref SYS_BODCTL_BODVL_3_7V
+ * - \ref SYS_BODCTL_BODVL_2_7V
+ * - \ref SYS_BODCTL_BODVL_2_2V
+ * @return None
+ * @details This function configure Brown-out detector reset or interrupt mode, enable Brown-out function and set Brown-out voltage level.
+ * The register write-protection function should be disabled before using this function.
+ */
+void SYS_EnableBOD(int32_t i32Mode, uint32_t u32BODLevel)
+{
+ /* Enable Brown-out Detector function */
+ SYS->BODCTL |= SYS_BODCTL_BODEN_Msk;
+
+ /* Enable Brown-out interrupt or reset function */
+ SYS->BODCTL = (SYS->BODCTL & ~SYS_BODCTL_BODRSTEN_Msk) | i32Mode;
+
+ /* Select Brown-out Detector threshold voltage */
+ SYS->BODCTL = (SYS->BODCTL & ~SYS_BODCTL_BODVL_Msk) | u32BODLevel;
+}
+
+/**
+ * @brief Disable Brown-out detector function
+ * @param None
+ * @return None
+ * @details This function disable Brown-out detector function.
+ * The register write-protection function should be disabled before using this function.
+ */
+void SYS_DisableBOD(void)
+{
+ SYS->BODCTL &= ~SYS_BODCTL_BODEN_Msk;
+}
+
+
+
+/*@}*/ /* end of group SYS_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group SYS_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+/*** (C) COPYRIGHT 2014~2015 Nuvoton Technology Corp. ***/
diff --git a/bsp/nuvoton_m451/Libraries/StdDriver/src/timer.c b/bsp/nuvoton_m451/Libraries/StdDriver/src/timer.c
new file mode 100644
index 0000000000000000000000000000000000000000..db8ce4225ccf94650e82ec8c3d4cedac3f1c13a4
--- /dev/null
+++ b/bsp/nuvoton_m451/Libraries/StdDriver/src/timer.c
@@ -0,0 +1,292 @@
+/**************************************************************************//**
+ * @file timer.c
+ * @version V3.00
+ * $Revision: 6 $
+ * $Date: 15/08/11 10:26a $
+ * @brief M451 series Timer driver source file
+ *
+ * @note
+ * Copyright (C) 2013~2015 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#include "M451Series.h"
+
+
+/** @addtogroup Standard_Driver Standard Driver
+ @{
+*/
+
+/** @addtogroup TIMER_Driver TIMER Driver
+ @{
+*/
+
+/** @addtogroup TIMER_EXPORTED_FUNCTIONS TIMER Exported Functions
+ @{
+*/
+
+/**
+ * @brief Open Timer with Operate Mode and Frequency
+ *
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+ * @param[in] u32Mode Operation mode. Possible options are
+ * - \ref TIMER_ONESHOT_MODE
+ * - \ref TIMER_PERIODIC_MODE
+ * - \ref TIMER_TOGGLE_MODE
+ * - \ref TIMER_CONTINUOUS_MODE
+ * @param[in] u32Freq Target working frequency
+ *
+ * @return Real timer working frequency
+ *
+ * @details This API is used to configure timer to operate in specified mode and frequency.
+ * If timer cannot work in target frequency, a closest frequency will be chose and returned.
+ * @note After calling this API, Timer is \b NOT running yet. But could start timer running be calling
+ * \ref TIMER_Start macro or program registers directly.
+ */
+uint32_t TIMER_Open(TIMER_T *timer, uint32_t u32Mode, uint32_t u32Freq)
+{
+ uint32_t u32Clk = TIMER_GetModuleClock(timer);
+ uint32_t u32Cmpr = 0, u32Prescale = 0;
+
+ // Fastest possible timer working freq is (u32Clk / 2). While cmpr = 2, pre-scale = 0.
+ if(u32Freq > (u32Clk / 2))
+ {
+ u32Cmpr = 2;
+ }
+ else
+ {
+ if(u32Clk > 64000000)
+ {
+ u32Prescale = 7; // real prescaler value is 8
+ u32Clk >>= 3;
+ }
+ else if(u32Clk > 32000000)
+ {
+ u32Prescale = 3; // real prescaler value is 4
+ u32Clk >>= 2;
+ }
+ else if(u32Clk > 16000000)
+ {
+ u32Prescale = 1; // real prescaler value is 2
+ u32Clk >>= 1;
+ }
+
+ u32Cmpr = u32Clk / u32Freq;
+ }
+
+ timer->CTL = u32Mode | u32Prescale;
+ timer->CMP = u32Cmpr;
+
+ return(u32Clk / (u32Cmpr * (u32Prescale + 1)));
+}
+
+/**
+ * @brief Stop Timer Counting
+ *
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+ *
+ * @return None
+ *
+ * @details This API stops timer counting and disable all timer interrupt function.
+ */
+void TIMER_Close(TIMER_T *timer)
+{
+ timer->CTL = 0;
+ timer->EXTCTL = 0;
+}
+
+/**
+ * @brief Create a specify Delay Time
+ *
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+ * @param[in] u32Usec Delay period in micro seconds. Valid values are between 100~1000000 (100 micro second ~ 1 second).
+ *
+ * @return None
+ *
+ * @details This API is used to create a delay loop for u32usec micro seconds by using timer one-shot mode.
+ * @note This API overwrites the register setting of the timer used to count the delay time.
+ * @note This API use polling mode. So there is no need to enable interrupt for the timer module used to generate delay.
+ */
+void TIMER_Delay(TIMER_T *timer, uint32_t u32Usec)
+{
+ uint32_t u32Clk = TIMER_GetModuleClock(timer);
+ uint32_t u32Prescale = 0, delay = (SystemCoreClock / u32Clk) + 1;
+ uint32_t u32Cmpr, u32NsecPerTick;
+
+ // Clear current timer configuration/
+ timer->CTL = 0;
+ timer->EXTCTL = 0;
+
+ if(u32Clk <= 1000000) // min delay is 1000 us if timer clock source is <= 1 MHz
+ {
+ if(u32Usec < 1000)
+ u32Usec = 1000;
+ if(u32Usec > 1000000)
+ u32Usec = 1000000;
+ }
+ else
+ {
+ if(u32Usec < 100)
+ u32Usec = 100;
+ if(u32Usec > 1000000)
+ u32Usec = 1000000;
+ }
+
+ if(u32Clk <= 1000000)
+ {
+ u32Prescale = 0;
+ u32NsecPerTick = 1000000000 / u32Clk;
+ u32Cmpr = (u32Usec * 1000) / u32NsecPerTick;
+ }
+ else
+ {
+ if(u32Clk > 64000000)
+ {
+ u32Prescale = 7; // real prescaler value is 8
+ u32Clk >>= 3;
+ }
+ else if(u32Clk > 32000000)
+ {
+ u32Prescale = 3; // real prescaler value is 4
+ u32Clk >>= 2;
+ }
+ else if(u32Clk > 16000000)
+ {
+ u32Prescale = 1; // real prescaler value is 2
+ u32Clk >>= 1;
+ }
+
+ if(u32Usec < 250)
+ {
+ u32Cmpr = (u32Usec * u32Clk) / 1000000;
+ }
+ else
+ {
+ u32NsecPerTick = 1000000000 / u32Clk;
+ u32Cmpr = (u32Usec * 1000) / u32NsecPerTick;
+ }
+ }
+
+ timer->CMP = u32Cmpr;
+ timer->CTL = TIMER_CTL_CNTEN_Msk | TIMER_ONESHOT_MODE | u32Prescale;
+
+ // When system clock is faster than timer clock, it is possible timer active bit cannot set in time while we check it.
+ // And the while loop below return immediately, so put a tiny delay here allowing timer start counting and raise active flag.
+ for(; delay > 0; delay--)
+ {
+ __NOP();
+ }
+
+ while(timer->CTL & TIMER_CTL_ACTSTS_Msk);
+}
+
+/**
+ * @brief Enable Timer Capture Function
+ *
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+ * @param[in] u32CapMode Timer capture mode. Could be
+ * - \ref TIMER_CAPTURE_FREE_COUNTING_MODE
+ * - \ref TIMER_CAPTURE_COUNTER_RESET_MODE
+ * @param[in] u32Edge Timer capture trigger edge. Possible values are
+ * - \ref TIMER_CAPTURE_FALLING_EDGE
+ * - \ref TIMER_CAPTURE_RISING_EDGE
+ * - \ref TIMER_CAPTURE_FALLING_AND_RISING_EDGE
+ *
+ * @return None
+ *
+ * @details This API is used to enable timer capture function with specify capture trigger edge \n
+ * to get current counter value or reset counter value to 0.
+ * @note Timer frequency should be configured separately by using \ref TIMER_Open API, or program registers directly.
+ */
+void TIMER_EnableCapture(TIMER_T *timer, uint32_t u32CapMode, uint32_t u32Edge)
+{
+
+ timer->EXTCTL = (timer->EXTCTL & ~(TIMER_EXTCTL_CAPFUNCS_Msk | TIMER_EXTCTL_CAPEDGE_Msk)) |
+ u32CapMode | u32Edge | TIMER_EXTCTL_CAPEN_Msk;
+}
+
+/**
+ * @brief Disable Timer Capture Function
+ *
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+ *
+ * @return None
+ *
+ * @details This API is used to disable the timer capture function.
+ */
+void TIMER_DisableCapture(TIMER_T *timer)
+{
+ timer->EXTCTL &= ~TIMER_EXTCTL_CAPEN_Msk;
+}
+
+/**
+ * @brief Enable Timer Counter Function
+ *
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+ * @param[in] u32Edge Detection edge of counter pin. Could be ether
+ * - \ref TIMER_COUNTER_FALLING_EDGE, or
+ * - \ref TIMER_COUNTER_RISING_EDGE
+ *
+ * @return None
+ *
+ * @details This function is used to enable the timer counter function with specify detection edge.
+ * @note Timer compare value should be configured separately by using \ref TIMER_SET_CMP_VALUE macro or program registers directly.
+ * @note While using event counter function, \ref TIMER_TOGGLE_MODE cannot set as timer operation mode.
+ */
+void TIMER_EnableEventCounter(TIMER_T *timer, uint32_t u32Edge)
+{
+ timer->EXTCTL = (timer->EXTCTL & ~TIMER_EXTCTL_CNTPHASE_Msk) | u32Edge;
+ timer->CTL |= TIMER_CTL_EXTCNTEN_Msk;
+}
+
+/**
+ * @brief Disable Timer Counter Function
+ *
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+ *
+ * @return None
+ *
+ * @details This API is used to disable the timer event counter function.
+ */
+void TIMER_DisableEventCounter(TIMER_T *timer)
+{
+ timer->CTL &= ~TIMER_CTL_EXTCNTEN_Msk;
+}
+
+/**
+ * @brief Get Timer Clock Frequency
+ *
+ * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+ *
+ * @return Timer clock frequency
+ *
+ * @details This API is used to get the timer clock frequency.
+ * @note This API cannot return correct clock rate if timer source is from external clock input.
+ */
+uint32_t TIMER_GetModuleClock(TIMER_T *timer)
+{
+ uint32_t u32Src;
+ const uint32_t au32Clk[] = {__HXT, __LXT, 0, 0, 0, __LIRC, 0, __HIRC};
+
+ if(timer == TIMER0)
+ u32Src = (CLK->CLKSEL1 & CLK_CLKSEL1_TMR0SEL_Msk) >> CLK_CLKSEL1_TMR0SEL_Pos;
+ else if(timer == TIMER1)
+ u32Src = (CLK->CLKSEL1 & CLK_CLKSEL1_TMR1SEL_Msk) >> CLK_CLKSEL1_TMR1SEL_Pos;
+ else if(timer == TIMER2)
+ u32Src = (CLK->CLKSEL1 & CLK_CLKSEL1_TMR2SEL_Msk) >> CLK_CLKSEL1_TMR2SEL_Pos;
+ else // Timer 3
+ u32Src = (CLK->CLKSEL1 & CLK_CLKSEL1_TMR3SEL_Msk) >> CLK_CLKSEL1_TMR3SEL_Pos;
+
+ if(u32Src == 2)
+ {
+ return (SystemCoreClock);
+ }
+
+ return (au32Clk[u32Src]);
+}
+
+/*@}*/ /* end of group TIMER_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group TIMER_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+/*** (C) COPYRIGHT 2013~2015 Nuvoton Technology Corp. ***/
diff --git a/bsp/nuvoton_m451/Libraries/StdDriver/src/tk.c b/bsp/nuvoton_m451/Libraries/StdDriver/src/tk.c
new file mode 100644
index 0000000000000000000000000000000000000000..4dcd0dc97d91b0994726a92112cd6a9550234b77
--- /dev/null
+++ b/bsp/nuvoton_m451/Libraries/StdDriver/src/tk.c
@@ -0,0 +1,265 @@
+/**************************************************************************//**
+ * @file tk.c
+ * @version V1.00
+ * $Revision: 6 $
+ * $Date: 15/08/24 4:54p $
+ * @brief M451 series TK driver source file
+ *
+ * @note
+ * Copyright (C) 2014~2015 Nuvoton Technology Corp. All rights reserved.
+ *
+*****************************************************************************/
+#include "M451Series.h"
+
+/** @addtogroup Standard_Driver Standard Driver
+ @{
+*/
+
+/** @addtogroup TK_Driver TK Driver
+ @{
+*/
+
+
+/** @addtogroup TK_EXPORTED_FUNCTIONS TK Exported Functions
+ @{
+*/
+
+
+/**
+ * @brief Enable touch key function
+ * @param None
+ * @return None
+ * @note This function will enable touch key function and initial idle and polarity state as GND first for all scan keys
+ * \hideinitializer
+ */
+
+void TK_Open(void)
+{
+ TK->CTL |= TK_CTL_TKEN_Msk;
+ //set idle and polarity state as GND
+ TK->IDLESEL = 0;
+ TK->POLSEL = 0;
+ TK->POLCTL &= ~(TK_POLCTL_IDLS16_Msk | TK_POLCTL_POLSEL16_Msk);
+}
+
+/**
+ * @brief Disable touch key function
+ * @param None
+ * @return None
+ * \hideinitializer
+ */
+void TK_Close(void)
+{
+ TK->CTL &= ~TK_CTL_TKEN_Msk;
+}
+
+/**
+ * @brief Set touch key scan mode
+ * @param[in] u32Mode Single ,periodic or all key scan mode
+ * - \ref TK_SCAN_MODE_SINGLE
+ * - \ref TK_SCAN_MODE_PERIODIC
+ * - \ref TK_SCAN_MODE_ALL_KEY
+ * - \ref TK_SCAN_MODE_PERIODIC_ALL_KEY
+ * @return None
+ * @details This function is used to set touch key scan mode.
+ * @note If touch key controller sets as periodic mode, touch key will be trigger scan by Timer0. So Timer0 must be enabled and operated in periodic mode.
+ * If touch key controller sets as single scan mode, touch key can be trigger scan by calling TK_START_SCAN().
+ * \hideinitializer
+ */
+void TK_SetScanMode(uint32_t u32Mode)
+{
+ TK->CTL &= ~TK_CTL_TMRTRGEN_Msk;
+ TK->REFCTL &= ~TK_REFCTL_SCANALL_Msk;
+ if(u32Mode == TK_SCAN_MODE_PERIODIC)
+ {
+ TK->CTL |= u32Mode;
+ }
+ else if(u32Mode == TK_SCAN_MODE_ALL_KEY)
+ {
+ TK->REFCTL |= u32Mode;
+ }
+ else if(u32Mode == TK_SCAN_MODE_PERIODIC_ALL_KEY)
+ {
+ TK->CTL |= TK_CTL_TMRTRGEN_Msk;
+ TK->REFCTL |= TK_REFCTL_SCANALL_Msk;
+ }
+}
+
+/**
+ * @brief Configure touch key scan sensitivity
+ * @param[in] u32PulseWidth Sensing pulse width
+ * - \ref TK_SENSE_PULSE_1
+ * - \ref TK_SENSE_PULSE_2
+ * - \ref TK_SENSE_PULSE_4
+ * - \ref TK_SENSE_PULSE_8
+ * @param[in] u32SenseCnt Sensing count
+ * - \ref TK_SENSE_CNT_128
+ * - \ref TK_SENSE_CNT_255
+ * - \ref TK_SENSE_CNT_511
+ * - \ref TK_SENSE_CNT_1023
+ * @param[in] u32AVCCHSel voltage selection
+ * - \ref TK_AVCCH_1_DIV_16
+ * - \ref TK_AVCCH_1_DIV_8
+ * - \ref TK_AVCCH_3_DIV_16
+ * - \ref TK_AVCCH_1_DIV_4
+ * - \ref TK_AVCCH_5_DIV_16
+ * - \ref TK_AVCCH_3_DIV_8
+ * - \ref TK_AVCCH_7_DIV_16
+ * - \ref TK_AVCCH_1_DIV_2
+ * @return None
+ * @details This function is used to configure touch key scan sensitivity.
+ * \hideinitializer
+ */
+void TK_ConfigSensitivity(uint32_t u32PulseWidth, uint32_t u32SenseCnt, uint32_t u32AVCCHSel)
+{
+ TK->REFCTL = (TK->REFCTL & ~(TK_REFCTL_SENPTCTL_Msk | TK_REFCTL_SENTCTL_Msk)) | (u32PulseWidth | u32SenseCnt);
+ TK->CTL = (TK->CTL & ~TK_CTL_AVCCHSEL_Msk) | u32AVCCHSel;
+}
+
+/**
+ * @brief Set touch key capacitor bank polarity
+ * @param[in] u32CapBankPolSel capacitor bank polarity selection
+ * - \ref TK_CAP_BANK_POL_SEL_GND
+ * - \ref TK_CAP_BANK_POL_SEL_AVCCH
+ * - \ref TK_CAP_BANK_POL_SEL_VDD
+ * @return None
+ * @details This function is used to set touch key capacitor bank polarity.
+ * \hideinitializer
+ */
+void TK_SetCapBankPol(uint32_t u32CapBankPolSel)
+{
+ TK->POLCTL = (TK->POLCTL & ~TK_POLCTL_CBPOLSEL_Msk) | u32CapBankPolSel;
+}
+
+/**
+ * @brief Configure touch key polarity
+ * @param[in] u32Mask Combination of touch keys which need to be configured
+ * @param[in] u32TKnPolSel touch key polarity selection
+ * - \ref TK_TKn_POL_SEL_GND
+ * - \ref TK_TKn_POL_SEL_AVCCH
+ * - \ref TK_TKn_POL_SEL_VDD
+ * @return None
+ * @details This function is used to configure touch key polarity.
+ * \hideinitializer
+ */
+void TK_SetTkPol(uint32_t u32Mask, uint32_t u32PolSel)
+{
+ uint32_t i;
+
+ if((1ul << 16) & u32Mask)
+ TK->POLCTL = (TK->POLCTL & ~TK_POLCTL_POLSEL16_Msk) | (u32PolSel << TK_POLCTL_POLSEL16_Pos);
+
+ for(i = 0 ; i < 16 ; i++)
+ {
+ if((1ul << i) & u32Mask)
+ TK->POLSEL = (TK->POLSEL & ~(TK_POLSEL_POLSELn_Msk << (i*2))) | (u32PolSel << (i*2));
+ }
+}
+
+/**
+ * @brief Enable the polarity of specified touch key(s)
+ * @param[in] u32Mask Combination of enabled scan keys. Each bit corresponds to a touch key
+ * Bit 0 represents touch key 0, bit 1 represents touch key 1...
+ * @return None
+ * @details This function is used to enable the polarity of specified touch key(s).
+ * \hideinitializer
+ */
+void TK_EnableTkPolarity(uint32_t u32Mask)
+{
+ TK->POLCTL |= (u32Mask << TK_POLCTL_POLEN0_Pos);
+}
+
+/**
+ * @brief Disable the polarity of specified touch key(s)
+ * @param[in] u32Mask Combination of enabled scan keys. Each bit corresponds to a touch key
+ * Bit 0 represents touch key 0, bit 1 represents touch key 1...
+ * @return None
+ * @details This function is used to disable the polarity of specified touch key(s).
+ * \hideinitializer
+ */
+void TK_DisableTkPolarity(uint32_t u32Mask)
+{
+ TK->POLCTL &= ~(u32Mask << TK_POLCTL_POLEN0_Pos);
+}
+
+/**
+ * @brief Set complement capacitor bank data of specified touch key
+ * @param[in] u32TKNum Touch key number. The valid value is 0~16.
+ * @param[in] u32CapData Complement capacitor bank data. The valid value is 0~0xFF.
+ * @return None
+ * @details This function is used to set complement capacitor bank data of specified touch key.
+ * \hideinitializer
+ */
+void TK_SetCompCapBankData(uint32_t u32TKNum, uint32_t u32CapData)
+{
+ *(__IO uint32_t *)(&(TK->CCBDAT0) + (u32TKNum >> 2)) &= ~(TK_CCBDAT0_CCBDAT0_Msk << (u32TKNum % 4 * 8));
+ *(__IO uint32_t *)(&(TK->CCBDAT0) + (u32TKNum >> 2)) |= (u32CapData << (u32TKNum % 4 * 8));
+}
+
+/**
+ * @brief Set complement capacitor bank data of reference touch key
+ * @param[in] u32CapData Complement capacitor bank data. The valid value is 0~0xFF.
+ * @return None
+ * @details This function is used to set complement capacitor bank data of reference touch key.
+ * \hideinitializer
+ */
+void TK_SetRefKeyCapBankData(uint32_t u32CapData)
+{
+ TK->CCBDAT4 = (TK->CCBDAT4 & ~TK_CCBDAT4_REFCBDAT_Msk) | (u32CapData << TK_CCBDAT4_REFCBDAT_Pos);
+}
+
+/**
+ * @brief Set high and low threshold of specified touch key for threshold control interrupt
+ * @param[in] u32TKNum Touch key number. The valid value is 0~16.
+ * @param[in] u32HighLevel High level for touch key threshold control. The valid value is 0~0xFF.
+ * @param[in] u32LowLevel Low level for touch key threshold control. The valid value is 0~0xFF.
+ * @return None
+ * @details This function is used to set high and low threshold of specified touch key for threshold control interrupt.
+ * \hideinitializer
+ */
+void TK_SetScanThreshold(uint32_t u32TKNum, uint32_t u32HighLevel, uint32_t u32LowLevel)
+{
+ *(__IO uint32_t *)(&(TK->TH0_1) + (u32TKNum >> 1)) &= ~((TK_TH0_1_HTH0_Msk | TK_TH0_1_LTH0_Msk) << (u32TKNum % 2 * 16));
+ *(__IO uint32_t *)(&(TK->TH0_1) + (u32TKNum >> 1)) |= ((u32HighLevel << TK_TH0_1_HTH0_Pos) | (u32LowLevel << TK_TH0_1_LTH0_Pos)) << (u32TKNum % 2 * 16);
+}
+
+/**
+ * @brief Enable touch key scan interrupt
+ * @param[in] u32Msk Interrupt type selection.
+ * - \ref TK_INT_EN_SCAN_COMPLETE
+ * - \ref TK_INT_EN_SCAN_COMPLETE_EDGE_TH
+ * - \ref TK_INT_EN_SCAN_COMPLETE_LEVEL_TH
+ * @return None
+ * @details This function is used to enable touch key scan interrupt.
+ * @note It need disable the enabled interrupt type first by TK_DisableInt() before to change enabled interrupt type.
+ * \hideinitializer
+ */
+void TK_EnableInt(uint32_t u32Msk)
+{
+ TK->INTEN |= u32Msk;
+}
+
+/**
+ * @brief Disable touch key scan interrupt
+ * @param[in] u32Msk Interrupt type selection.
+ * - \ref TK_INT_EN_SCAN_COMPLETE
+ * - \ref TK_INT_EN_SCAN_COMPLETE_EDGE_TH
+ * - \ref TK_INT_EN_SCAN_COMPLETE_LEVEL_TH
+ * @return None
+ * @details This function is used to disable touch key scan interrupt.
+* @note It need disable the enabled interrupt type first by TK_DisableInt() before to change enabled interrupt type.
+ * \hideinitializer
+ */
+void TK_DisableInt(uint32_t u32Msk)
+{
+ TK->INTEN &= ~u32Msk;
+}
+
+
+/*@}*/ /* end of group TK_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group TK_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+/*** (C) COPYRIGHT 2014~2015 Nuvoton Technology Corp. ***/
diff --git a/bsp/nuvoton_m451/Libraries/StdDriver/src/uart.c b/bsp/nuvoton_m451/Libraries/StdDriver/src/uart.c
new file mode 100644
index 0000000000000000000000000000000000000000..7b9047b70a970f926e924a7ae50c87a46e183ccc
--- /dev/null
+++ b/bsp/nuvoton_m451/Libraries/StdDriver/src/uart.c
@@ -0,0 +1,512 @@
+/**************************************************************************//**
+ * @file uart.c
+ * @version V3.00
+ * $Revision: 22 $
+ * $Date: 15/08/11 10:26a $
+ * @brief M451 series UART driver source file
+ *
+ * @note
+ * Copyright (C) 2013~2015 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+
+#include
+#include "M451Series.h"
+
+/** @addtogroup Standard_Driver Standard Driver
+ @{
+*/
+
+/** @addtogroup UART_Driver UART Driver
+ @{
+*/
+
+/** @addtogroup UART_EXPORTED_FUNCTIONS UART Exported Functions
+ @{
+*/
+
+/**
+ * @brief Clear UART specified interrupt flag
+ *
+ * @param[in] uart The pointer of the specified UART module.
+ * @param[in] u32InterruptFlag The specified interrupt of UART module.
+ * - \ref UART_INTSTS_LININT_Msk : LIN bus interrupt
+ * - \ref UART_INTSTS_DATWKIF_Msk : Data Wake-up interrupt
+ * - \ref UART_INTSTS_CTSWKIF_Msk : CTS Wake-up interrupt
+ * - \ref UART_INTSTS_BUFERRINT_Msk : Buffer Error interrupt
+ * - \ref UART_INTSTS_MODEMINT_Msk : Modem Status interrupt
+ * - \ref UART_INTSTS_RLSINT_Msk : Receive Line Status interrupt
+ *
+ * @return None
+ *
+ * @details The function is used to clear UART specified interrupt flag.
+ */
+
+void UART_ClearIntFlag(UART_T* uart , uint32_t u32InterruptFlag)
+{
+
+ if(u32InterruptFlag & UART_INTSTS_RLSINT_Msk) /* Clear Receive Line Status Interrupt */
+ {
+ uart->FIFOSTS = UART_FIFOSTS_BIF_Msk | UART_FIFOSTS_FEF_Msk | UART_FIFOSTS_FEF_Msk;
+ uart->FIFOSTS = UART_FIFOSTS_ADDRDETF_Msk;
+ }
+
+ if(u32InterruptFlag & UART_INTSTS_MODEMINT_Msk) /* Clear Modem Status Interrupt */
+ uart->MODEMSTS |= UART_MODEMSTS_CTSDETF_Msk;
+
+ if(u32InterruptFlag & UART_INTSTS_BUFERRINT_Msk) /* Clear Buffer Error Interrupt */
+ {
+ uart->FIFOSTS = UART_FIFOSTS_RXOVIF_Msk | UART_FIFOSTS_TXOVIF_Msk;
+ }
+
+ if(u32InterruptFlag & UART_INTSTS_CTSWKIF_Msk) /* Clear CTS Wake-up Interrupt */
+ {
+ uart->INTSTS = UART_INTSTS_CTSWKIF_Msk;
+ }
+
+ if(u32InterruptFlag & UART_INTSTS_DATWKIF_Msk) /* Clear Data Wake-up Interrupt */
+ {
+ uart->INTSTS = UART_INTSTS_DATWKIF_Msk;
+ }
+
+ if(u32InterruptFlag & UART_INTSTS_LININT_Msk) /* Clear LIN Bus Interrupt */
+ {
+ uart->INTSTS = UART_INTSTS_LINIF_Msk;
+ uart->LINSTS = UART_LINSTS_BITEF_Msk | UART_LINSTS_BRKDETF_Msk |
+ UART_LINSTS_SLVSYNCF_Msk | UART_LINSTS_SLVIDPEF_Msk |
+ UART_LINSTS_SLVHEF_Msk | UART_LINSTS_SLVHDETF_Msk ;
+ }
+}
+
+
+/**
+ * @brief Disable UART interrupt
+ *
+ * @param[in] uart The pointer of the specified UART module.
+ *
+ * @return None
+ *
+ * @details The function is used to disable UART interrupt.
+ */
+void UART_Close(UART_T* uart)
+{
+ uart->INTEN = 0;
+}
+
+
+/**
+ * @brief Disable UART auto flow control function
+ *
+ * @param[in] uart The pointer of the specified UART module.
+ *
+ * @return None
+ *
+ * @details The function is used to disable UART auto flow control.
+ */
+void UART_DisableFlowCtrl(UART_T* uart)
+{
+ uart->INTEN &= ~(UART_INTEN_ATORTSEN_Msk | UART_INTEN_ATOCTSEN_Msk);
+}
+
+
+/**
+ * @brief Disable UART specified interrupt
+ *
+ * @param[in] uart The pointer of the specified UART module.
+ * @param[in] u32InterruptFlag The specified interrupt of UART module.
+ * - \ref UART_INTEN_WKCTSIEN_Msk : CTS wake-up interrupt
+ * - \ref UART_INTEN_WKDATIEN_Msk : Data wake-up interrupt
+ * - \ref UART_INTEN_LINIEN_Msk : Lin bus interrupt
+ * - \ref UART_INTEN_BUFERRIEN_Msk : Buffer Error interrupt
+ * - \ref UART_INTEN_RXTOIEN_Msk : Rx time-out interrupt
+ * - \ref UART_INTEN_MODEMIEN_Msk : Modem status interrupt
+ * - \ref UART_INTEN_RLSIEN_Msk : Receive Line status interrupt
+ * - \ref UART_INTEN_THREIEN_Msk : Tx empty interrupt
+ * - \ref UART_INTEN_RDAIEN_Msk : Rx ready interrupt *
+ *
+ * @return None
+ *
+ * @details The function is used to disable UART specified interrupt and disable NVIC UART IRQ.
+ */
+void UART_DisableInt(UART_T* uart, uint32_t u32InterruptFlag)
+{
+ /* Disable UART specified interrupt */
+ UART_DISABLE_INT(uart, u32InterruptFlag);
+
+ /* Disable NVIC UART IRQ */
+ if(uart == UART0)
+ NVIC_DisableIRQ(UART0_IRQn);
+ else if(uart == UART1)
+ NVIC_DisableIRQ(UART1_IRQn);
+ else if(uart == UART2)
+ NVIC_DisableIRQ(UART2_IRQn);
+ else
+ NVIC_DisableIRQ(UART3_IRQn);
+}
+
+
+/**
+ * @brief Enable UART auto flow control function
+ *
+ * @param[in] uart The pointer of the specified UART module.
+ *
+ * @return None
+ *
+ * @details The function is used to Enable UART auto flow control.
+ */
+void UART_EnableFlowCtrl(UART_T* uart)
+{
+ /* Set RTS pin output is low level active */
+ uart->MODEM |= UART_MODEM_RTSACTLV_Msk;
+
+ /* Set CTS pin input is low level active */
+ uart->MODEMSTS |= UART_MODEMSTS_CTSACTLV_Msk;
+
+ /* Set RTS and CTS auto flow control enable */
+ uart->INTEN |= UART_INTEN_ATORTSEN_Msk | UART_INTEN_ATOCTSEN_Msk;
+}
+
+
+/**
+ * @brief The function is used to enable UART specified interrupt and enable NVIC UART IRQ.
+ *
+ * @param[in] uart The pointer of the specified UART module.
+ * @param[in] u32InterruptFlag The specified interrupt of UART module:
+ * - \ref UART_INTEN_WKCTSIEN_Msk : CTS wake-up interrupt
+ * - \ref UART_INTEN_WKDATIEN_Msk : Data wake-up interrupt
+ * - \ref UART_INTEN_LINIEN_Msk : Lin bus interrupt
+ * - \ref UART_INTEN_BUFERRIEN_Msk : Buffer Error interrupt
+ * - \ref UART_INTEN_RXTOIEN_Msk : Rx time-out interrupt
+ * - \ref UART_INTEN_MODEMIEN_Msk : Modem status interrupt
+ * - \ref UART_INTEN_RLSIEN_Msk : Receive Line status interrupt
+ * - \ref UART_INTEN_THREIEN_Msk : Tx empty interrupt
+ * - \ref UART_INTEN_RDAIEN_Msk : Rx ready interrupt *
+ *
+ * @return None
+ *
+ * @details The function is used to enable UART specified interrupt and enable NVIC UART IRQ.
+ */
+void UART_EnableInt(UART_T* uart, uint32_t u32InterruptFlag)
+{
+
+ /* Enable UART specified interrupt */
+ UART_ENABLE_INT(uart, u32InterruptFlag);
+
+ /* Enable NVIC UART IRQ */
+ if(uart == UART0)
+ NVIC_EnableIRQ(UART0_IRQn);
+ else if(uart == UART1)
+ NVIC_EnableIRQ(UART1_IRQn);
+ else if(uart == UART2)
+ NVIC_EnableIRQ(UART2_IRQn);
+ else
+ NVIC_EnableIRQ(UART3_IRQn);
+
+}
+
+
+/**
+ * @brief Open and set UART function
+ *
+ * @param[in] uart The pointer of the specified UART module.
+ * @param[in] u32baudrate The baudrate of UART module.
+ *
+ * @return None
+ *
+ * @details This function use to enable UART function and set baud-rate.
+ */
+void UART_Open(UART_T* uart, uint32_t u32baudrate)
+{
+ uint8_t u8UartClkSrcSel, u8UartClkDivNum;
+ uint32_t u32ClkTbl[4] = {__HXT, 0, __LXT, __HIRC};
+ uint32_t u32Baud_Div = 0;
+
+ /* Get UART clock source selection */
+ u8UartClkSrcSel = (CLK->CLKSEL1 & CLK_CLKSEL1_UARTSEL_Msk) >> CLK_CLKSEL1_UARTSEL_Pos;
+
+ /* Get UART clock divider number */
+ u8UartClkDivNum = (CLK->CLKDIV0 & CLK_CLKDIV0_UARTDIV_Msk) >> CLK_CLKDIV0_UARTDIV_Pos;
+
+ /* Select UART function */
+ uart->FUNCSEL = UART_FUNCSEL_UART;
+
+ /* Set UART line configuration */
+ uart->LINE = UART_WORD_LEN_8 | UART_PARITY_NONE | UART_STOP_BIT_1;
+
+ /* Set UART Rx and RTS trigger level */
+ uart->FIFO &= ~(UART_FIFO_RFITL_Msk | UART_FIFO_RTSTRGLV_Msk);
+
+ /* Get PLL clock frequency if UART clock source selection is PLL */
+ if(u8UartClkSrcSel == 1)
+ u32ClkTbl[u8UartClkSrcSel] = CLK_GetPLLClockFreq();
+
+ /* Set UART baud rate */
+ if(u32baudrate != 0)
+ {
+ u32Baud_Div = UART_BAUD_MODE2_DIVIDER((u32ClkTbl[u8UartClkSrcSel]) / (u8UartClkDivNum + 1), u32baudrate);
+
+ if(u32Baud_Div > 0xFFFF)
+ uart->BAUD = (UART_BAUD_MODE0 | UART_BAUD_MODE0_DIVIDER((u32ClkTbl[u8UartClkSrcSel]) / (u8UartClkDivNum + 1), u32baudrate));
+ else
+ uart->BAUD = (UART_BAUD_MODE2 | u32Baud_Div);
+ }
+}
+
+
+/**
+ * @brief Read UART data
+ *
+ * @param[in] uart The pointer of the specified UART module.
+ * @param[in] pu8RxBuf The buffer to receive the data of receive FIFO.
+ * @param[in] u32ReadBytes The the read bytes number of data.
+ *
+ * @return u32Count Receive byte count
+ *
+ * @details The function is used to read Rx data from RX FIFO and the data will be stored in pu8RxBuf.
+ */
+uint32_t UART_Read(UART_T* uart, uint8_t *pu8RxBuf, uint32_t u32ReadBytes)
+{
+ uint32_t u32Count, u32delayno;
+
+ for(u32Count = 0; u32Count < u32ReadBytes; u32Count++)
+ {
+ u32delayno = 0;
+
+ while(uart->FIFOSTS & UART_FIFOSTS_RXEMPTY_Msk) /* Check RX empty => failed */
+ {
+ u32delayno++;
+ if(u32delayno >= 0x40000000)
+ return FALSE;
+ }
+ pu8RxBuf[u32Count] = uart->DAT; /* Get Data from UART RX */
+ }
+
+ return u32Count;
+
+}
+
+
+/**
+ * @brief Set UART line configuration
+ *
+ * @param[in] uart The pointer of the specified UART module.
+ * @param[in] u32baudrate The register value of baudrate of UART module.
+ * If u32baudrate = 0, UART baudrate will not change.
+ * @param[in] u32data_width The data length of UART module.
+ * - \ref UART_WORD_LEN_5
+ * - \ref UART_WORD_LEN_6
+ * - \ref UART_WORD_LEN_7
+ * - \ref UART_WORD_LEN_8
+ * @param[in] u32parity The parity setting (none/odd/even/mark/space) of UART module.
+ * - \ref UART_PARITY_NONE
+ * - \ref UART_PARITY_ODD
+ * - \ref UART_PARITY_EVEN
+ * - \ref UART_PARITY_MARK
+ * - \ref UART_PARITY_SPACE
+ * @param[in] u32stop_bits The stop bit length (1/1.5/2 bit) of UART module.
+ * - \ref UART_STOP_BIT_1
+ * - \ref UART_STOP_BIT_1_5
+ * - \ref UART_STOP_BIT_2
+ *
+ * @return None
+ *
+ * @details This function use to config UART line setting.
+ */
+void UART_SetLine_Config(UART_T* uart, uint32_t u32baudrate, uint32_t u32data_width, uint32_t u32parity, uint32_t u32stop_bits)
+{
+ uint8_t u8UartClkSrcSel, u8UartClkDivNum;
+ uint32_t u32ClkTbl[4] = {__HXT, 0, __LXT, __HIRC};
+ uint32_t u32Baud_Div = 0;
+
+ /* Get UART clock source selection */
+ u8UartClkSrcSel = (CLK->CLKSEL1 & CLK_CLKSEL1_UARTSEL_Msk) >> CLK_CLKSEL1_UARTSEL_Pos;
+
+ /* Get UART clock divider number */
+ u8UartClkDivNum = (CLK->CLKDIV0 & CLK_CLKDIV0_UARTDIV_Msk) >> CLK_CLKDIV0_UARTDIV_Pos;
+
+ /* Get PLL clock frequency if UART clock source selection is PLL */
+ if(u8UartClkSrcSel == 1)
+ u32ClkTbl[u8UartClkSrcSel] = CLK_GetPLLClockFreq();
+
+ /* Set UART baud rate */
+ if(u32baudrate != 0)
+ {
+ u32Baud_Div = UART_BAUD_MODE2_DIVIDER((u32ClkTbl[u8UartClkSrcSel]) / (u8UartClkDivNum + 1), u32baudrate);
+
+ if(u32Baud_Div > 0xFFFF)
+ uart->BAUD = (UART_BAUD_MODE0 | UART_BAUD_MODE0_DIVIDER((u32ClkTbl[u8UartClkSrcSel]) / (u8UartClkDivNum + 1), u32baudrate));
+ else
+ uart->BAUD = (UART_BAUD_MODE2 | u32Baud_Div);
+ }
+
+ /* Set UART line configuration */
+ uart->LINE = u32data_width | u32parity | u32stop_bits;
+}
+
+
+/**
+ * @brief Set Rx timeout count
+ *
+ * @param[in] uart The pointer of the specified UART module.
+ * @param[in] u32TOC Rx timeout counter.
+ *
+ * @return None
+ *
+ * @details This function use to set Rx timeout count.
+ */
+void UART_SetTimeoutCnt(UART_T* uart, uint32_t u32TOC)
+{
+ /* Set time-out interrupt comparator */
+ uart->TOUT = (uart->TOUT & ~UART_TOUT_TOIC_Msk) | (u32TOC);
+
+ /* Set time-out counter enable */
+ uart->INTEN |= UART_INTEN_TOCNTEN_Msk;
+}
+
+
+/**
+ * @brief Select and configure IrDA function
+ *
+ * @param[in] uart The pointer of the specified UART module.
+ * @param[in] u32Buadrate The baudrate of UART module.
+ * @param[in] u32Direction The direction of UART module in IrDA mode:
+ * - \ref UART_IRDA_TXEN
+ * - \ref UART_IRDA_RXEN
+ *
+ * @return None
+ *
+ * @details The function is used to configure IrDA relative settings. It consists of TX or RX mode and baudrate.
+ */
+void UART_SelectIrDAMode(UART_T* uart, uint32_t u32Buadrate, uint32_t u32Direction)
+{
+ uint8_t u8UartClkSrcSel, u8UartClkDivNum;
+ uint32_t u32ClkTbl[4] = {__HXT, 0, __LXT, __HIRC};
+ uint32_t u32Baud_Div;
+
+ /* Select IrDA function mode */
+ uart->FUNCSEL = UART_FUNCSEL_IrDA;
+
+ /* Get UART clock source selection */
+ u8UartClkSrcSel = (CLK->CLKSEL1 & CLK_CLKSEL1_UARTSEL_Msk) >> CLK_CLKSEL1_UARTSEL_Pos;
+
+ /* Get UART clock divider number */
+ u8UartClkDivNum = (CLK->CLKDIV0 & CLK_CLKDIV0_UARTDIV_Msk) >> CLK_CLKDIV0_UARTDIV_Pos;
+
+ /* Get PLL clock frequency if UART clock source selection is PLL */
+ if(u8UartClkSrcSel == 1)
+ u32ClkTbl[u8UartClkSrcSel] = CLK_GetPLLClockFreq();
+
+ /* Set UART IrDA baud rate in mode 0 */
+ if(u32Buadrate != 0)
+ {
+ u32Baud_Div = UART_BAUD_MODE0_DIVIDER((u32ClkTbl[u8UartClkSrcSel]) / (u8UartClkDivNum + 1), u32Buadrate);
+
+ if(u32Baud_Div < 0xFFFF)
+ uart->BAUD = (UART_BAUD_MODE0 | u32Baud_Div);
+ }
+
+ /* Configure IrDA relative settings */
+ if(u32Direction == UART_IRDA_RXEN)
+ {
+ uart->IRDA |= UART_IRDA_RXINV_Msk; //Rx signal is inverse
+ uart->IRDA &= ~UART_IRDA_TXEN_Msk;
+ }
+ else
+ {
+ uart->IRDA &= ~UART_IRDA_TXINV_Msk; //Tx signal is not inverse
+ uart->IRDA |= UART_IRDA_TXEN_Msk;
+ }
+
+}
+
+
+/**
+ * @brief Select and configure RS485 function
+ *
+ * @param[in] uart The pointer of the specified UART module.
+ * @param[in] u32Mode The operation mode(NMM/AUD/AAD).
+ * - \ref UART_ALTCTL_RS485NMM_Msk
+ * - \ref UART_ALTCTL_RS485AUD_Msk
+ * - \ref UART_ALTCTL_RS485AAD_Msk
+ * @param[in] u32Addr The RS485 address.
+ *
+ * @return None
+ *
+ * @details The function is used to set RS485 relative setting.
+ */
+void UART_SelectRS485Mode(UART_T* uart, uint32_t u32Mode, uint32_t u32Addr)
+{
+ /* Select UART RS485 function mode */
+ uart->FUNCSEL = UART_FUNCSEL_RS485;
+
+ /* Set RS585 configuration */
+ uart->ALTCTL &= ~(UART_ALTCTL_RS485NMM_Msk | UART_ALTCTL_RS485AUD_Msk | UART_ALTCTL_RS485AAD_Msk | UART_ALTCTL_ADDRMV_Msk);
+ uart->ALTCTL |= (u32Mode | (u32Addr << UART_ALTCTL_ADDRMV_Pos));
+}
+
+
+/**
+ * @brief Select and configure LIN function
+ *
+ * @param[in] uart The pointer of the specified UART module.
+ * @param[in] u32Mode The LIN direction :
+ * - \ref UART_ALTCTL_LINTXEN_Msk
+ * - \ref UART_ALTCTL_LINRXEN_Msk
+ * @param[in] u32BreakLength The breakfield length.
+ *
+ * @return None
+ *
+ * @details The function is used to set LIN relative setting.
+ */
+void UART_SelectLINMode(UART_T* uart, uint32_t u32Mode, uint32_t u32BreakLength)
+{
+ /* Select LIN function mode */
+ uart->FUNCSEL = UART_FUNCSEL_LIN;
+
+ /* Select LIN function setting : Tx enable, Rx enable and break field length */
+ uart->ALTCTL &= ~(UART_ALTCTL_LINTXEN_Msk | UART_ALTCTL_LINRXEN_Msk | UART_ALTCTL_BRKFL_Msk);
+ uart->ALTCTL |= (u32Mode | (u32BreakLength << UART_ALTCTL_BRKFL_Pos));
+}
+
+
+/**
+ * @brief Write UART data
+ *
+ * @param[in] uart The pointer of the specified UART module.
+ * @param[in] pu8TxBuf The buffer to send the data to UART transmission FIFO.
+ * @param[out] u32WriteBytes The byte number of data.
+ *
+ * @return u32Count transfer byte count
+ *
+ * @details The function is to write data into TX buffer to transmit data by UART.
+ */
+uint32_t UART_Write(UART_T* uart, uint8_t *pu8TxBuf, uint32_t u32WriteBytes)
+{
+ uint32_t u32Count, u32delayno;
+
+ for(u32Count = 0; u32Count != u32WriteBytes; u32Count++)
+ {
+ u32delayno = 0;
+ while((uart->FIFOSTS & UART_FIFOSTS_TXEMPTYF_Msk) == 0) /* Wait Tx empty and Time-out manner */
+ {
+ u32delayno++;
+ if(u32delayno >= 0x40000000)
+ return FALSE;
+ }
+ uart->DAT = pu8TxBuf[u32Count]; /* Send UART Data from buffer */
+ }
+
+ return u32Count;
+
+}
+
+
+/*@}*/ /* end of group UART_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group UART_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+/*** (C) COPYRIGHT 2012~2015 Nuvoton Technology Corp. ***/
+
+
+
diff --git a/bsp/nuvoton_m451/Libraries/StdDriver/src/usbd.c b/bsp/nuvoton_m451/Libraries/StdDriver/src/usbd.c
new file mode 100644
index 0000000000000000000000000000000000000000..1759b1c82d67c0ec16989d81b8b6192d8b8f6fe3
--- /dev/null
+++ b/bsp/nuvoton_m451/Libraries/StdDriver/src/usbd.c
@@ -0,0 +1,728 @@
+/**************************************************************************//**
+ * @file usbd.c
+ * @version V1.00
+ * $Revision: 21 $
+ * $Date: 15/08/21 3:34p $
+ * @brief M451 series USBD driver source file
+ *
+ * @note
+ * Copyright (C) 2014~2015 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+
+#include
+#include "M451Series.h"
+
+#if 0
+#define DBG_PRINTF printf
+#else
+#define DBG_PRINTF(...)
+#endif
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/** @addtogroup Standard_Driver Standard Driver
+ @{
+*/
+
+/** @addtogroup USBD_Driver USBD Driver
+ @{
+*/
+
+
+/** @addtogroup USBD_EXPORTED_FUNCTIONS USBD Exported Functions
+ @{
+*/
+
+/* Global variables for Control Pipe */
+uint8_t g_usbd_SetupPacket[8] = {0}; /*!< Setup packet buffer */
+volatile uint8_t g_usbd_RemoteWakeupEn = 0; /*!< Remote wake up function enable flag */
+
+/**
+ * @cond HIDDEN_SYMBOLS
+ */
+static volatile uint8_t *g_usbd_CtrlInPointer = 0;
+static volatile uint32_t g_usbd_CtrlInSize = 0;
+static volatile uint8_t *g_usbd_CtrlOutPointer = 0;
+static volatile uint32_t g_usbd_CtrlOutSize = 0;
+static volatile uint32_t g_usbd_CtrlOutSizeLimit = 0;
+static volatile uint32_t g_usbd_UsbAddr = 0;
+static volatile uint32_t g_usbd_UsbConfig = 0;
+static volatile uint32_t g_usbd_CtrlMaxPktSize = 8;
+static volatile uint32_t g_usbd_UsbAltInterface = 0;
+/**
+ * @endcond
+ */
+
+const S_USBD_INFO_T *g_usbd_sInfo; /*!< A pointer for USB information structure */
+
+VENDOR_REQ g_usbd_pfnVendorRequest = NULL; /*!< USB Vendor Request Functional Pointer */
+CLASS_REQ g_usbd_pfnClassRequest = NULL; /*!< USB Class Request Functional Pointer */
+SET_INTERFACE_REQ g_usbd_pfnSetInterface = NULL; /*!< USB Set Interface Functional Pointer */
+SET_CONFIG_CB g_usbd_pfnSetConfigCallback = NULL; /*!< USB Set configuration callback function pointer */
+uint32_t g_u32EpStallLock = 0; /*!< Bit map flag to lock specified EP when SET_FEATURE */
+
+/**
+ * @brief This function makes USBD module to be ready to use
+ *
+ * @param[in] param The structure of USBD information.
+ * @param[in] pfnClassReq USB Class request callback function.
+ * @param[in] pfnSetInterface USB Set Interface request callback function.
+ *
+ * @return None
+ *
+ * @details This function will enable USB controller, USB PHY transceiver and pull-up resistor of USB_D+ pin. USB PHY will drive SE0 to bus.
+ */
+void USBD_Open(const S_USBD_INFO_T *param, CLASS_REQ pfnClassReq, SET_INTERFACE_REQ pfnSetInterface)
+{
+ g_usbd_sInfo = param;
+ g_usbd_pfnClassRequest = pfnClassReq;
+ g_usbd_pfnSetInterface = pfnSetInterface;
+
+ /* get EP0 maximum packet size */
+ g_usbd_CtrlMaxPktSize = g_usbd_sInfo->gu8DevDesc[7];
+
+ /* Initial USB engine */
+ USBD->ATTR = 0x7D0;
+ /* Force SE0 */
+ USBD_SET_SE0();
+}
+
+/**
+ * @brief This function makes USB host to recognize the device
+ *
+ * @param None
+ *
+ * @return None
+ *
+ * @details Enable WAKEUP, FLDET, USB and BUS interrupts. Disable software-disconnect function after 100ms delay with SysTick timer.
+ */
+void USBD_Start(void)
+{
+ CLK_SysTickDelay(100000);
+ /* Disable software-disconnect function */
+ USBD_CLR_SE0();
+
+ /* Clear USB-related interrupts before enable interrupt */
+ USBD_CLR_INT_FLAG(USBD_INT_BUS | USBD_INT_USB | USBD_INT_FLDET | USBD_INT_WAKEUP);
+
+ /* Enable USB-related interrupts. */
+ USBD_ENABLE_INT(USBD_INT_BUS | USBD_INT_USB | USBD_INT_FLDET | USBD_INT_WAKEUP);
+}
+
+/**
+ * @brief Get the received SETUP packet
+ *
+ * @param[in] buf A buffer pointer used to store 8-byte SETUP packet.
+ *
+ * @return None
+ *
+ * @details Store SETUP packet to a user-specified buffer.
+ *
+ */
+void USBD_GetSetupPacket(uint8_t *buf)
+{
+ USBD_MemCopy(buf, g_usbd_SetupPacket, 8);
+}
+
+/**
+ * @brief Process SETUP packet
+ *
+ * @param None
+ *
+ * @return None
+ *
+ * @details Parse SETUP packet and perform the corresponding action.
+ *
+ */
+void USBD_ProcessSetupPacket(void)
+{
+ /* Get SETUP packet from USB buffer */
+ USBD_MemCopy(g_usbd_SetupPacket, (uint8_t *)USBD_BUF_BASE, 8);
+ /* Check the request type */
+ switch(g_usbd_SetupPacket[0] & 0x60)
+ {
+ case REQ_STANDARD: // Standard
+ {
+ USBD_StandardRequest();
+ break;
+ }
+ case REQ_CLASS: // Class
+ {
+ if(g_usbd_pfnClassRequest != NULL)
+ {
+ g_usbd_pfnClassRequest();
+ }
+ break;
+ }
+ case REQ_VENDOR: // Vendor
+ {
+ if(g_usbd_pfnVendorRequest != NULL)
+ {
+ g_usbd_pfnVendorRequest();
+ }
+ break;
+ }
+ default: // reserved
+ {
+ /* Setup error, stall the device */
+ USBD_SET_EP_STALL(EP0);
+ USBD_SET_EP_STALL(EP1);
+ break;
+ }
+ }
+}
+
+/**
+ * @brief Process GetDescriptor request
+ *
+ * @param None
+ *
+ * @return None
+ *
+ * @details Parse GetDescriptor request and perform the corresponding action.
+ *
+ */
+void USBD_GetDescriptor(void)
+{
+ uint32_t u32Len;
+
+ u32Len = 0;
+ u32Len = g_usbd_SetupPacket[7];
+ u32Len <<= 8;
+ u32Len += g_usbd_SetupPacket[6];
+
+ switch(g_usbd_SetupPacket[3])
+ {
+ // Get Device Descriptor
+ case DESC_DEVICE:
+ {
+ u32Len = Minimum(u32Len, LEN_DEVICE);
+ DBG_PRINTF("Get device desc, %d\n", u32Len);
+
+ USBD_PrepareCtrlIn((uint8_t *)g_usbd_sInfo->gu8DevDesc, u32Len);
+
+ break;
+ }
+ // Get Configuration Descriptor
+ case DESC_CONFIG:
+ {
+ uint32_t u32TotalLen;
+
+ u32TotalLen = g_usbd_sInfo->gu8ConfigDesc[3];
+ u32TotalLen = g_usbd_sInfo->gu8ConfigDesc[2] + (u32TotalLen << 8);
+
+ DBG_PRINTF("Get config desc len %d, acture len %d\n", u32Len, u32TotalLen);
+ u32Len = Minimum(u32Len, u32TotalLen);
+ DBG_PRINTF("Minimum len %d\n", u32Len);
+
+ USBD_PrepareCtrlIn((uint8_t *)g_usbd_sInfo->gu8ConfigDesc, u32Len);
+
+ break;
+ }
+ // Get HID Descriptor
+ case DESC_HID:
+ {
+ /* CV3.0 HID Class Descriptor Test,
+ Need to indicate index of the HID Descriptor within gu8ConfigDescriptor, specifically HID Composite device. */
+ uint32_t u32ConfigDescOffset; // u32ConfigDescOffset is configuration descriptor offset (HID descriptor start index)
+ u32Len = Minimum(u32Len, LEN_HID);
+ DBG_PRINTF("Get HID desc, %d\n", u32Len);
+
+ u32ConfigDescOffset = g_usbd_sInfo->gu32ConfigHidDescIdx[g_usbd_SetupPacket[4]];
+ USBD_PrepareCtrlIn((uint8_t *)&g_usbd_sInfo->gu8ConfigDesc[u32ConfigDescOffset], u32Len);
+
+ break;
+ }
+ // Get Report Descriptor
+ case DESC_HID_RPT:
+ {
+ DBG_PRINTF("Get HID report, %d\n", u32Len);
+
+ u32Len = Minimum(u32Len, g_usbd_sInfo->gu32HidReportSize[g_usbd_SetupPacket[4]]);
+ USBD_PrepareCtrlIn((uint8_t *)g_usbd_sInfo->gu8HidReportDesc[g_usbd_SetupPacket[4]], u32Len);
+ break;
+ }
+ // Get String Descriptor
+ case DESC_STRING:
+ {
+ // Get String Descriptor
+ if(g_usbd_SetupPacket[2] < 4)
+ {
+ u32Len = Minimum(u32Len, g_usbd_sInfo->gu8StringDesc[g_usbd_SetupPacket[2]][0]);
+ DBG_PRINTF("Get string desc %d\n", u32Len);
+
+ USBD_PrepareCtrlIn((uint8_t *)g_usbd_sInfo->gu8StringDesc[g_usbd_SetupPacket[2]], u32Len);
+
+
+ break;
+ }
+ else
+ {
+ // Not support. Reply STALL.
+ USBD_SET_EP_STALL(EP0);
+ USBD_SET_EP_STALL(EP1);
+
+ DBG_PRINTF("Unsupported string desc (%d). Stall ctrl pipe.\n", g_usbd_SetupPacket[2]);
+
+ break;
+ }
+ }
+ default:
+ // Not support. Reply STALL.
+ USBD_SET_EP_STALL(EP0);
+ USBD_SET_EP_STALL(EP1);
+
+ DBG_PRINTF("Unsupported get desc type. stall ctrl pipe\n");
+
+ break;
+ }
+}
+
+/**
+ * @brief Process standard request
+ *
+ * @param None
+ *
+ * @return None
+ *
+ * @details Parse standard request and perform the corresponding action.
+ *
+ */
+void USBD_StandardRequest(void)
+{
+
+ /* clear global variables for new request */
+ g_usbd_CtrlInPointer = 0;
+ g_usbd_CtrlInSize = 0;
+
+ if(g_usbd_SetupPacket[0] & 0x80) /* request data transfer direction */
+ {
+ // Device to host
+ switch(g_usbd_SetupPacket[1])
+ {
+ case GET_CONFIGURATION:
+ {
+ // Return current configuration setting
+ /* Data stage */
+ M8(USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0)) = g_usbd_UsbConfig;
+ USBD_SET_DATA1(EP0);
+ USBD_SET_PAYLOAD_LEN(EP0, 1);
+ /* Status stage */
+ USBD_PrepareCtrlOut(0,0);
+
+ DBG_PRINTF("Get configuration\n");
+
+ break;
+ }
+ case GET_DESCRIPTOR:
+ {
+ USBD_GetDescriptor();
+ USBD_PrepareCtrlOut(0, 0); /* For status stage */
+ break;
+ }
+ case GET_INTERFACE:
+ {
+ // Return current interface setting
+ /* Data stage */
+ M8(USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0)) = g_usbd_UsbAltInterface;
+ USBD_SET_DATA1(EP0);
+ USBD_SET_PAYLOAD_LEN(EP0, 1);
+ /* Status stage */
+ USBD_PrepareCtrlOut(0, 0);
+
+ DBG_PRINTF("Get interface\n");
+
+ break;
+ }
+ case GET_STATUS:
+ {
+ // Device
+ if(g_usbd_SetupPacket[0] == 0x80)
+ {
+ uint8_t u8Tmp;
+
+ u8Tmp = 0;
+ if(g_usbd_sInfo->gu8ConfigDesc[7] & 0x40) u8Tmp |= 1; // Self-Powered/Bus-Powered.
+ if(g_usbd_sInfo->gu8ConfigDesc[7] & 0x20) u8Tmp |= (g_usbd_RemoteWakeupEn << 1); // Remote wake up
+
+ M8(USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0)) = u8Tmp;
+
+ }
+ // Interface
+ else if(g_usbd_SetupPacket[0] == 0x81)
+ M8(USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0)) = 0;
+ // Endpoint
+ else if(g_usbd_SetupPacket[0] == 0x82)
+ {
+ uint8_t ep = g_usbd_SetupPacket[4] & 0xF;
+ M8(USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0)) = USBD_GetStall(ep) ? 1 : 0;
+ }
+
+ M8(USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0) + 1) = 0;
+ /* Data stage */
+ USBD_SET_DATA1(EP0);
+ USBD_SET_PAYLOAD_LEN(EP0, 2);
+ /* Status stage */
+ USBD_PrepareCtrlOut(0, 0);
+
+ DBG_PRINTF("Get status\n");
+
+ break;
+ }
+ default:
+ {
+ /* Setup error, stall the device */
+ USBD_SET_EP_STALL(EP0);
+ USBD_SET_EP_STALL(EP1);
+
+ DBG_PRINTF("Unknown request. stall ctrl pipe.\n");
+
+ break;
+ }
+ }
+ }
+ else
+ {
+ // Host to device
+ switch(g_usbd_SetupPacket[1])
+ {
+ case CLEAR_FEATURE:
+ {
+ if(g_usbd_SetupPacket[2] == FEATURE_ENDPOINT_HALT)
+ {
+ int32_t epNum, i;
+
+ /* EP number stall is not allow to be clear in MSC class "Error Recovery Test".
+ a flag: g_u32EpStallLock is added to support it */
+ epNum = g_usbd_SetupPacket[4] & 0xF;
+ for(i = 0; i < USBD_MAX_EP; i++)
+ {
+ if(((USBD->EP[i].CFG & 0xF) == epNum) && ((g_u32EpStallLock & (1 << i)) == 0))
+ {
+ USBD->EP[i].CFGP &= ~USBD_CFGP_SSTALL_Msk;
+ DBG_PRINTF("Clr stall ep%d %x\n", i, USBD->EP[i].CFGP);
+ }
+ }
+ }
+ else if(g_usbd_SetupPacket[2] == FEATURE_DEVICE_REMOTE_WAKEUP)
+ g_usbd_RemoteWakeupEn = 0;
+
+ /* Status stage */
+ USBD_SET_DATA1(EP0);
+ USBD_SET_PAYLOAD_LEN(EP0, 0);
+
+ DBG_PRINTF("Clear feature op %d\n", g_usbd_SetupPacket[2]);
+
+ break;
+ }
+ case SET_ADDRESS:
+ {
+ g_usbd_UsbAddr = g_usbd_SetupPacket[2];
+ DBG_PRINTF("Set addr to %d\n", g_usbd_UsbAddr);
+
+ // DATA IN for end of setup
+ /* Status Stage */
+ USBD_SET_DATA1(EP0);
+ USBD_SET_PAYLOAD_LEN(EP0, 0);
+
+ break;
+ }
+ case SET_CONFIGURATION:
+ {
+ g_usbd_UsbConfig = g_usbd_SetupPacket[2];
+
+ if(g_usbd_pfnSetConfigCallback)
+ g_usbd_pfnSetConfigCallback();
+
+ // DATA IN for end of setup
+ /* Status stage */
+ USBD_SET_DATA1(EP0);
+ USBD_SET_PAYLOAD_LEN(EP0, 0);
+
+ DBG_PRINTF("Set config to %d\n", g_usbd_UsbConfig);
+
+ break;
+ }
+ case SET_FEATURE:
+ {
+ if(g_usbd_SetupPacket[2] == FEATURE_ENDPOINT_HALT)
+ {
+ USBD_SetStall(g_usbd_SetupPacket[4] & 0xF);
+ DBG_PRINTF("Set feature. stall ep %d\n", g_usbd_SetupPacket[4] & 0xF);
+ }
+ else if(g_usbd_SetupPacket[2] == FEATURE_DEVICE_REMOTE_WAKEUP)
+ {
+ g_usbd_RemoteWakeupEn = 1;
+ DBG_PRINTF("Set feature. enable remote wakeup\n");
+ }
+
+ /* Status stage */
+ USBD_SET_DATA1(EP0);
+ USBD_SET_PAYLOAD_LEN(EP0, 0);
+
+
+
+ break;
+ }
+ case SET_INTERFACE:
+ {
+ g_usbd_UsbAltInterface = g_usbd_SetupPacket[2];
+ if(g_usbd_pfnSetInterface != NULL)
+ g_usbd_pfnSetInterface();
+ /* Status stage */
+ USBD_SET_DATA1(EP0);
+ USBD_SET_PAYLOAD_LEN(EP0, 0);
+
+ DBG_PRINTF("Set interface to %d\n", g_usbd_UsbAltInterface);
+
+ break;
+ }
+ default:
+ {
+ /* Setup error, stall the device */
+ USBD_SET_EP_STALL(EP0);
+ USBD_SET_EP_STALL(EP1);
+
+ DBG_PRINTF("Unsupported request. stall ctrl pipe.\n");
+
+ break;
+ }
+ }
+ }
+}
+
+/**
+ * @brief Prepare the first Control IN pipe
+ *
+ * @param[in] pu8Buf The pointer of data sent to USB host.
+ * @param[in] u32Size The IN transfer size.
+ *
+ * @return None
+ *
+ * @details Prepare data for Control IN transfer.
+ *
+ */
+void USBD_PrepareCtrlIn(uint8_t *pu8Buf, uint32_t u32Size)
+{
+ DBG_PRINTF("Prepare Ctrl In %d\n", u32Size);
+ if(u32Size > g_usbd_CtrlMaxPktSize)
+ {
+ // Data size > MXPLD
+ g_usbd_CtrlInPointer = pu8Buf + g_usbd_CtrlMaxPktSize;
+ g_usbd_CtrlInSize = u32Size - g_usbd_CtrlMaxPktSize;
+ USBD_SET_DATA1(EP0);
+ USBD_MemCopy((uint8_t *)USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0), pu8Buf, g_usbd_CtrlMaxPktSize);
+ USBD_SET_PAYLOAD_LEN(EP0, g_usbd_CtrlMaxPktSize);
+ }
+ else
+ {
+ // Data size <= MXPLD
+ g_usbd_CtrlInPointer = 0;
+ g_usbd_CtrlInSize = 0;
+ USBD_SET_DATA1(EP0);
+ USBD_MemCopy((uint8_t *)USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0), pu8Buf, u32Size);
+ USBD_SET_PAYLOAD_LEN(EP0, u32Size);
+ }
+}
+
+/**
+ * @brief Repeat Control IN pipe
+ *
+ * @param None
+ *
+ * @return None
+ *
+ * @details This function processes the remained data of Control IN transfer.
+ *
+ */
+void USBD_CtrlIn(void)
+{
+ static uint8_t u8ZeroFlag = 0;
+
+ DBG_PRINTF("Ctrl In Ack. residue %d\n", g_usbd_CtrlInSize);
+ if(g_usbd_CtrlInSize)
+ {
+ // Process remained data
+ if(g_usbd_CtrlInSize > g_usbd_CtrlMaxPktSize)
+ {
+ // Data size > MXPLD
+ USBD_MemCopy((uint8_t *)USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0), (uint8_t *)g_usbd_CtrlInPointer, g_usbd_CtrlMaxPktSize);
+ USBD_SET_PAYLOAD_LEN(EP0, g_usbd_CtrlMaxPktSize);
+ g_usbd_CtrlInPointer += g_usbd_CtrlMaxPktSize;
+ g_usbd_CtrlInSize -= g_usbd_CtrlMaxPktSize;
+ }
+ else
+ {
+ // Data size <= MXPLD
+ USBD_MemCopy((uint8_t *)USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0), (uint8_t *)g_usbd_CtrlInPointer, g_usbd_CtrlInSize);
+ USBD_SET_PAYLOAD_LEN(EP0, g_usbd_CtrlInSize);
+ if(g_usbd_CtrlInSize == g_usbd_CtrlMaxPktSize)
+ u8ZeroFlag = 1;
+ g_usbd_CtrlInPointer = 0;
+ g_usbd_CtrlInSize = 0;
+ }
+ }
+ else // No more data for IN token
+ {
+ // In ACK for Set address
+ if((g_usbd_SetupPacket[0] == REQ_STANDARD) && (g_usbd_SetupPacket[1] == SET_ADDRESS))
+ {
+ if((USBD_GET_ADDR() != g_usbd_UsbAddr) && (USBD_GET_ADDR() == 0))
+ {
+ USBD_SET_ADDR(g_usbd_UsbAddr);
+ }
+ }
+
+ /* For the case of data size is integral times maximum packet size */
+ if(u8ZeroFlag)
+ {
+ USBD_SET_PAYLOAD_LEN(EP0, 0);
+ u8ZeroFlag = 0;
+ }
+
+ DBG_PRINTF("Ctrl In done.\n");
+
+ }
+}
+
+/**
+ * @brief Prepare the first Control OUT pipe
+ *
+ * @param[in] pu8Buf The pointer of data received from USB host.
+ * @param[in] u32Size The OUT transfer size.
+ *
+ * @return None
+ *
+ * @details This function is used to prepare the first Control OUT transfer.
+ *
+ */
+void USBD_PrepareCtrlOut(uint8_t *pu8Buf, uint32_t u32Size)
+{
+ g_usbd_CtrlOutPointer = pu8Buf;
+ g_usbd_CtrlOutSize = 0;
+ g_usbd_CtrlOutSizeLimit = u32Size;
+ USBD_SET_PAYLOAD_LEN(EP1, g_usbd_CtrlMaxPktSize);
+}
+
+/**
+ * @brief Repeat Control OUT pipe
+ *
+ * @param None
+ *
+ * @return None
+ *
+ * @details This function processes the successive Control OUT transfer.
+ *
+ */
+void USBD_CtrlOut(void)
+{
+ uint32_t u32Size;
+
+ DBG_PRINTF("Ctrl Out Ack %d\n", g_usbd_CtrlOutSize);
+
+ if(g_usbd_CtrlOutSize < g_usbd_CtrlOutSizeLimit)
+ {
+ u32Size = USBD_GET_PAYLOAD_LEN(EP1);
+ USBD_MemCopy((uint8_t *)g_usbd_CtrlOutPointer, (uint8_t *)USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP1), u32Size);
+ g_usbd_CtrlOutPointer += u32Size;
+ g_usbd_CtrlOutSize += u32Size;
+
+ if(g_usbd_CtrlOutSize < g_usbd_CtrlOutSizeLimit)
+ USBD_SET_PAYLOAD_LEN(EP1, g_usbd_CtrlMaxPktSize);
+
+ }
+}
+
+/**
+ * @brief Reset software flags
+ *
+ * @param None
+ *
+ * @return None
+ *
+ * @details This function resets all variables for protocol and resets USB device address to 0.
+ *
+ */
+void USBD_SwReset(void)
+{
+ int i;
+
+ // Reset all variables for protocol
+ g_usbd_CtrlInPointer = 0;
+ g_usbd_CtrlInSize = 0;
+ g_usbd_CtrlOutPointer = 0;
+ g_usbd_CtrlOutSize = 0;
+ g_usbd_CtrlOutSizeLimit = 0;
+ g_u32EpStallLock = 0;
+ memset(g_usbd_SetupPacket, 0, 8);
+
+ /* Reset PID DATA0 */
+ for(i=0; iEP[i].CFG &= ~USBD_CFG_DSQSYNC_Msk;
+
+ // Reset USB device address
+ USBD_SET_ADDR(0);
+}
+
+/**
+ * @brief USBD Set Vendor Request
+ *
+ * @param[in] pfnVendorReq Vendor Request Callback Function
+ *
+ * @return None
+ *
+ * @details This function is used to set USBD vendor request callback function
+ */
+void USBD_SetVendorRequest(VENDOR_REQ pfnVendorReq)
+{
+ g_usbd_pfnVendorRequest = pfnVendorReq;
+}
+
+/**
+ * @brief The callback function which called when get SET CONFIGURATION request
+ *
+ * @param[in] pfnSetConfigCallback Callback function pointer for SET CONFIGURATION request
+ *
+ * @return None
+ *
+ * @details This function is used to set the callback function which will be called at SET CONFIGURATION request.
+ */
+void USBD_SetConfigCallback(SET_CONFIG_CB pfnSetConfigCallback)
+{
+ g_usbd_pfnSetConfigCallback = pfnSetConfigCallback;
+}
+
+
+/**
+ * @brief EP stall lock function to avoid stall clear by USB SET FEATURE request.
+ *
+ * @param[in] u32EpBitmap Use bitmap to select which endpoints will be locked
+ *
+ * @return None
+ *
+ * @details This function is used to lock relative endpoint to avoid stall clear by SET FEATURE requst.
+ * If ep stall locked, user needs to reset USB device or re-configure device to clear it.
+ */
+void USBD_LockEpStall(uint32_t u32EpBitmap)
+{
+ g_u32EpStallLock = u32EpBitmap;
+}
+
+
+
+
+
+/*@}*/ /* end of group USBD_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group USBD_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+/*** (C) COPYRIGHT 2014~2015 Nuvoton Technology Corp. ***/
diff --git a/bsp/nuvoton_m451/Libraries/StdDriver/src/wdt.c b/bsp/nuvoton_m451/Libraries/StdDriver/src/wdt.c
new file mode 100644
index 0000000000000000000000000000000000000000..b8718b5529301f35214e85a4d537c8ad51e26cd4
--- /dev/null
+++ b/bsp/nuvoton_m451/Libraries/StdDriver/src/wdt.c
@@ -0,0 +1,71 @@
+/**************************************************************************//**
+ * @file wdt.c
+ * @version V3.00
+ * $Revision: 5 $
+ * $Date: 15/08/11 10:26a $
+ * @brief M451 series WDT driver source file
+ *
+ * @note
+ * Copyright (C) 2013~2015 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#include "M451Series.h"
+
+
+/** @addtogroup Standard_Driver Standard Driver
+ @{
+*/
+
+/** @addtogroup WDT_Driver WDT Driver
+ @{
+*/
+
+/** @addtogroup WDT_EXPORTED_FUNCTIONS WDT Exported Functions
+ @{
+*/
+
+/**
+ * @brief Initialize WDT and start counting
+ *
+ * @param[in] u32TimeoutInterval Time-out interval period of WDT module. Valid values are:
+ * - \ref WDT_TIMEOUT_2POW4
+ * - \ref WDT_TIMEOUT_2POW6
+ * - \ref WDT_TIMEOUT_2POW8
+ * - \ref WDT_TIMEOUT_2POW10
+ * - \ref WDT_TIMEOUT_2POW12
+ * - \ref WDT_TIMEOUT_2POW14
+ * - \ref WDT_TIMEOUT_2POW16
+ * - \ref WDT_TIMEOUT_2POW18
+ * @param[in] u32ResetDelay Configure WDT time-out reset delay period. Valid values are:
+ * - \ref WDT_RESET_DELAY_1026CLK
+ * - \ref WDT_RESET_DELAY_130CLK
+ * - \ref WDT_RESET_DELAY_18CLK
+ * - \ref WDT_RESET_DELAY_3CLK
+ * @param[in] u32EnableReset Enable WDT time-out reset system function. Valid values are TRUE and FALSE.
+ * @param[in] u32EnableWakeup Enable WDT time-out wake-up system function. Valid values are TRUE and FALSE.
+ *
+ * @return None
+ *
+ * @details This function makes WDT module start counting with different time-out interval, reset delay period and choose to \n
+ * enable or disable WDT time-out reset system or wake-up system.
+ * @note Please make sure that Register Write-Protection Function has been disabled before using this function.
+ */
+void WDT_Open(uint32_t u32TimeoutInterval,
+ uint32_t u32ResetDelay,
+ uint32_t u32EnableReset,
+ uint32_t u32EnableWakeup)
+{
+ WDT->ALTCTL = u32ResetDelay;
+
+ WDT->CTL = u32TimeoutInterval | WDT_CTL_WDTEN_Msk |
+ (u32EnableReset << WDT_CTL_RSTEN_Pos) |
+ (u32EnableWakeup << WDT_CTL_WKEN_Pos);
+ return;
+}
+
+/*@}*/ /* end of group WDT_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group WDT_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+/*** (C) COPYRIGHT 2013~2015 Nuvoton Technology Corp. ***/
diff --git a/bsp/nuvoton_m451/Libraries/StdDriver/src/wwdt.c b/bsp/nuvoton_m451/Libraries/StdDriver/src/wwdt.c
new file mode 100644
index 0000000000000000000000000000000000000000..439dbaf8cbba3c9ee3e2cd0f78f462d10f1b018b
--- /dev/null
+++ b/bsp/nuvoton_m451/Libraries/StdDriver/src/wwdt.c
@@ -0,0 +1,71 @@
+/**************************************************************************//**
+ * @file wwdt.c
+ * @version V3.00
+ * $Revision: 4 $
+ * $Date: 15/08/11 10:26a $
+ * @brief M451 series WWDT driver source file
+ *
+ * @note
+ * Copyright (C) 2013~2015 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#include "M451Series.h"
+
+
+/** @addtogroup Standard_Driver Standard Driver
+ @{
+*/
+
+/** @addtogroup WWDT_Driver WWDT Driver
+ @{
+*/
+
+/** @addtogroup WWDT_EXPORTED_FUNCTIONS WWDT Exported Functions
+ @{
+*/
+
+/**
+ * @brief Open WWDT and start counting
+ *
+ * @param[in] u32PreScale Pre-scale setting of WWDT counter. Valid values are:
+ * - \ref WWDT_PRESCALER_1
+ * - \ref WWDT_PRESCALER_2
+ * - \ref WWDT_PRESCALER_4
+ * - \ref WWDT_PRESCALER_8
+ * - \ref WWDT_PRESCALER_16
+ * - \ref WWDT_PRESCALER_32
+ * - \ref WWDT_PRESCALER_64
+ * - \ref WWDT_PRESCALER_128
+ * - \ref WWDT_PRESCALER_192
+ * - \ref WWDT_PRESCALER_256
+ * - \ref WWDT_PRESCALER_384
+ * - \ref WWDT_PRESCALER_512
+ * - \ref WWDT_PRESCALER_768
+ * - \ref WWDT_PRESCALER_1024
+ * - \ref WWDT_PRESCALER_1536
+ * - \ref WWDT_PRESCALER_2048
+ * @param[in] u32CmpValue Setting the window compared value. Valid values are between 0x0 to 0x3F.
+ * @param[in] u32EnableInt Enable WWDT time-out interrupt function. Valid values are TRUE and FALSE.
+ *
+ * @return None
+ *
+ * @details This function makes WWDT module start counting with different counter period by pre-scale setting and compared window value.
+ * @note This WWDT_CTL register can be write only one time after chip is powered on or reset.
+ */
+void WWDT_Open(uint32_t u32PreScale,
+ uint32_t u32CmpValue,
+ uint32_t u32EnableInt)
+{
+ WWDT->CTL = u32PreScale |
+ (u32CmpValue << WWDT_CTL_CMPDAT_Pos) |
+ ((u32EnableInt == TRUE) ? WWDT_CTL_INTEN_Msk : 0) |
+ WWDT_CTL_WWDTEN_Msk;
+ return;
+}
+
+/*@}*/ /* end of group WWDT_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group WWDT_Driver */
+
+/*@}*/ /* end of group Standard_Driver */
+
+/*** (C) COPYRIGHT 2013~2015 Nuvoton Technology Corp. ***/
diff --git a/bsp/nuvoton_m451/README.md b/bsp/nuvoton_m451/README.md
new file mode 100644
index 0000000000000000000000000000000000000000..b9f039ca53ffef28fa7afd1cf767b29d898c5c6e
--- /dev/null
+++ b/bsp/nuvoton_m451/README.md
@@ -0,0 +1,29 @@
+# 新唐M451系列单片机
+## 简介
+这里参考[BrightPan](https://github.com/bright-pan)之前移植的[nuvoton_m05x](https://github.com/RT-Thread/rt-thread/tree/master/bsp/nuvoton_m05x)，将RT-thread移植到了Nuvoton(新唐/芯唐) M451单片机上。
+
+目前的工程基于M451 Series_BSP_CMSIS_V3.01.001，运行在Nuvoton M451 NuEdu Board上，仅在application.c内开了一个线程实现了简单的闪灯功能。
+
+目前已经测试过的平台有：
+
+平台 | 版本
+-----|----------
+Keil | MDK4&MDK5
+GCC | GNU Tools ARM Embedded 5.4
+
+## 使用
+### Keil
+使用前请前往[新唐官网](http://www.nuvoton.com)下载驱动*NuLink_Keil_Driver*。MDK5请安装对应的*Nuvoton Pack*。
+
+* 配置rtconfig.py里的`CROSS_TOOL`为keil以及`EXEC_PATH`为你的Keil根目录
+* 使用`scons --target=mdk/mdk4/mdk5 -s`生成对应的工程文件。或者使用`scons`直接编译。
+
+### GCC
+这里使用的是*gcc-arm-none-eabi*
+
+* 配置rtconfig.py里的`CROSS_TOOL`为gcc以及`EXEC_PATH`为你gcc-arm-none-eabi可执行文件的位置
+* 使用`scons`直接编译。
+
+
+
+
diff --git a/bsp/nuvoton_m451/SConscript b/bsp/nuvoton_m451/SConscript
new file mode 100644
index 0000000000000000000000000000000000000000..fe0ae941ae9a759ae478de901caec1c961e56af8
--- /dev/null
+++ b/bsp/nuvoton_m451/SConscript
@@ -0,0 +1,14 @@
+# for module compiling
+import os
+Import('RTT_ROOT')
+
+cwd = str(Dir('#'))
+objs = []
+list = os.listdir(cwd)
+
+for d in list:
+ path = os.path.join(cwd, d)
+ if os.path.isfile(os.path.join(path, 'SConscript')):
+ objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
+Return('objs')
diff --git a/bsp/nuvoton_m451/SConstruct b/bsp/nuvoton_m451/SConstruct
new file mode 100644
index 0000000000000000000000000000000000000000..b7994463ee19ae14009c150f6af1f0e3bc99348e
--- /dev/null
+++ b/bsp/nuvoton_m451/SConstruct
@@ -0,0 +1,34 @@
+import os
+import sys
+import rtconfig
+
+if os.getenv('RTT_ROOT'):
+ RTT_ROOT = os.getenv('RTT_ROOT')
+else:
+ RTT_ROOT = os.path.normpath(os.getcwd() + '/../..')
+
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+from building import *
+
+TARGET = 'rtthread-nuvotan_m451.' + rtconfig.TARGET_EXT
+
+env = Environment(tools = ['mingw'],
+ AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+ CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
+ AR = rtconfig.AR, ARFLAGS = '-rc',
+ LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
+env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+
+if rtconfig.PLATFORM == 'iar':
+ env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
+ env.Replace(ARFLAGS = [''])
+ env.Replace(LINKCOM = ['$LINK $SOURCES $LINKFLAGS -o $TARGET --map project.map'])
+
+Export('RTT_ROOT')
+Export('rtconfig')
+
+# prepare building environment
+objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
+
+# make a building
+DoBuilding(TARGET, objs)
diff --git a/bsp/nuvoton_m451/applications/SConscript b/bsp/nuvoton_m451/applications/SConscript
new file mode 100644
index 0000000000000000000000000000000000000000..d5c25a0f8b7bb25eced420560d61aa26c6b442a4
--- /dev/null
+++ b/bsp/nuvoton_m451/applications/SConscript
@@ -0,0 +1,13 @@
+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+
+cwd = GetCurrentDir()
+src = Glob('*.c')
+
+CPPPATH = [str(Dir('#')), cwd]
+
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
diff --git a/bsp/nuvoton_m451/applications/application.c b/bsp/nuvoton_m451/applications/application.c
new file mode 100644
index 0000000000000000000000000000000000000000..d018b3bff12299f2e1d08ef32e8fa92b71a2bbe7
--- /dev/null
+++ b/bsp/nuvoton_m451/applications/application.c
@@ -0,0 +1,80 @@
+/*
+ * File : application.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2014, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2016-12-05 Pluto first implementation
+ */
+/**
+ * @addtogroup NUVOTON_M451
+ */
+
+/*@{*/
+
+#include
+
+#include
+#include
+#ifdef RT_USING_COMPONENTS_INIT
+#include
+#endif /* RT_USING_COMPONENTS_INIT */
+
+#include "led.h"
+
+/* led thread entry */
+static void led_thread_entry(void* parameter)
+{
+ rt_hw_led_init();
+ while(1)
+ {
+ rt_hw_led_on();
+ rt_thread_delay(RT_TICK_PER_SECOND);
+ rt_hw_led_off();
+ rt_thread_delay(RT_TICK_PER_SECOND);
+ }
+}
+
+static void rt_init_thread_entry(void* parameter)
+{
+ rt_thread_t led_thread;
+
+/* Initialization RT-Thread Components */
+#ifdef RT_USING_COMPONENTS_INIT
+ rt_components_init();
+#endif
+
+ /* Create led thread */
+ led_thread = rt_thread_create("led",
+ led_thread_entry, RT_NULL,
+ 256, 20, 20);
+ if(led_thread != RT_NULL)
+ rt_thread_startup(led_thread);
+}
+
+int rt_application_init()
+{
+ rt_thread_t init_thread;
+
+#if (RT_THREAD_PRIORITY_MAX == 32)
+ init_thread = rt_thread_create("init",
+ rt_init_thread_entry, RT_NULL,
+ 512, 8, 20);
+#else
+ init_thread = rt_thread_create("init",
+ rt_init_thread_entry, RT_NULL,
+ 512, 80, 20);
+#endif
+ if(init_thread != RT_NULL)
+ rt_thread_startup(init_thread);
+
+ return 0;
+}
+
+
+/*@}*/
diff --git a/bsp/nuvoton_m451/applications/startup.c b/bsp/nuvoton_m451/applications/startup.c
new file mode 100644
index 0000000000000000000000000000000000000000..af8375d697f66647ab6df9d90dbbb712e7396b79
--- /dev/null
+++ b/bsp/nuvoton_m451/applications/startup.c
@@ -0,0 +1,121 @@
+/*
+ * File : startup.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2014, RT-Thread Develop Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://openlab.rt-thread.com/license/LICENSE
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2016-12-05 Pluto first implementation
+ */
+
+#include
+#include
+
+#include "board.h"
+
+/**
+ * @addtogroup NUVOTON_M451
+ */
+
+/*@{*/
+
+extern int rt_application_init(void);
+#ifdef RT_USING_FINSH
+extern void finsh_system_init(void);
+extern void finsh_set_device(const char* device);
+#endif
+
+#ifdef __CC_ARM
+extern int Image$$RW_IRAM1$$ZI$$Limit;
+#define M451_SRAM_BEGIN (&Image$$RW_IRAM1$$ZI$$Limit)
+#elif __ICCARM__
+#pragma section="HEAP"
+#define M451_SRAM_BEGIN (__segment_end("HEAP"))
+#else
+extern int __bss_end;
+#define M451_SRAM_BEGIN (&__bss_end)
+#endif
+
+/*******************************************************************************
+* Function Name : assert_failed
+* Description : Reports the name of the source file and the source line number
+* where the assert error has occurred.
+* Input : - file: pointer to the source file name
+* - line: assert error line source number
+* Output : None
+* Return : None
+*******************************************************************************/
+void assert_failed(uint8_t* file, uint32_t line)
+{
+ rt_kprintf("\n\r Wrong parameter value detected on\r\n");
+ rt_kprintf(" file %s\r\n", file);
+ rt_kprintf(" line %d\r\n", line);
+
+ while (1) ;
+}
+
+/**
+ * This function will startup RT-Thread RTOS.
+ */
+void rtthread_startup(void)
+{
+ /* init board */
+ rt_hw_board_init();
+
+ /* show version */
+ rt_show_version();
+
+ /* init tick */
+ rt_system_tick_init();
+
+ /* init kernel object */
+ rt_system_object_init();
+
+ /* init timer system */
+ rt_system_timer_init();
+
+#ifdef RT_USING_HEAP
+ rt_system_heap_init((void*)M451_SRAM_BEGIN, (void*)M451_SRAM_END);
+#endif
+
+ /* init scheduler system */
+ rt_system_scheduler_init();
+
+ /* init application */
+ rt_application_init();
+
+/* Set finsh device */
+#ifdef RT_USING_FINSH
+ finsh_system_init();
+ finsh_set_device(RT_CONSOLE_DEVICE_NAME);
+#endif /* RT_USING_FINSH */
+
+ /* init timer thread */
+ rt_system_timer_thread_init();
+
+ /* init idle thread */
+ rt_thread_idle_init();
+
+ /* start scheduler */
+ rt_system_scheduler_start();
+
+ /* never reach here */
+ return ;
+}
+
+int main(void)
+{
+ /* disable interrupt first */
+ rt_hw_interrupt_disable();
+
+ /* startup RT-Thread RTOS */
+ rtthread_startup();
+
+ return 0;
+}
+
+/*@}*/
diff --git a/bsp/nuvoton_m451/drivers/SConscript b/bsp/nuvoton_m451/drivers/SConscript
new file mode 100644
index 0000000000000000000000000000000000000000..9f55277d1101c7dd5875e288972a525534eb586b
--- /dev/null
+++ b/bsp/nuvoton_m451/drivers/SConscript
@@ -0,0 +1,12 @@
+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd = GetCurrentDir()
+src = Glob('*.c')
+
+CPPPATH = [cwd]
+
+group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
\ No newline at end of file
diff --git a/bsp/nuvoton_m451/drivers/board.c b/bsp/nuvoton_m451/drivers/board.c
new file mode 100644
index 0000000000000000000000000000000000000000..dd3b0ba504a5820a9b50f7b02b449341391b67b4
--- /dev/null
+++ b/bsp/nuvoton_m451/drivers/board.c
@@ -0,0 +1,127 @@
+/*
+ * File : board.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2014 RT-Thread Develop Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2016-12-05 Pluto first implementation
+ */
+
+#include
+#include
+#include "board.h"
+#include "usart.h"
+/* RT_USING_COMPONENTS_INIT */
+#ifdef RT_USING_COMPONENTS_INIT
+#include
+#endif
+/**
+ * @addtogroup NUVOTON_M451
+ */
+
+/*@{*/
+
+/*******************************************************************************
+* Function Name : NVIC_Configuration
+* Description : Configures Vector Table base location.
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void NVIC_Configuration(void)
+{
+// NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2);
+}
+
+/**
+* @brief Inserts a delay time.
+* @param nCount: specifies the delay time length.
+* @retval None
+*/
+static void delay(__IO uint32_t nCount)
+{
+ /* Decrement nCount value */
+ while (nCount != 0)
+ {
+ nCount--;
+ }
+}
+
+static void rt_hw_system_init(void)
+{
+ /*---------------------------------------------------------------------------------------------------------*/
+ /* Init System Clock */
+ /*---------------------------------------------------------------------------------------------------------*/
+ /* Unlock protected registers */
+ SYS_UnlockReg();
+
+ /* Enable HIRC clock (Internal RC 22.1184MHz) */
+ CLK_EnableXtalRC(CLK_PWRCTL_HIRCEN_Msk);
+
+ /* Wait for HIRC clock ready */
+ CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk);
+
+ /* Select HCLK clock source as HIRC and and HCLK clock divider as 1 */
+ CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_HIRC, CLK_CLKDIV0_HCLK(1));
+
+ /* Enable HXT clock (external XTAL 12MHz) */
+ CLK_EnableXtalRC(CLK_PWRCTL_HXTEN_Msk);
+
+ /* Wait for HXT clock ready */
+ CLK_WaitClockReady(CLK_STATUS_HXTSTB_Msk);
+
+ /* Set core clock as PLL_CLOCK from PLL */
+ CLK_SetCoreClock(BOARD_PLL_CLOCK);
+
+ /* Set SysTick clock source to HCLK source divide 2 */
+ CLK_SetSysTickClockSrc(CLK_CLKSEL0_STCLKSEL_HCLK_DIV2);
+
+ /* Lock protected registers */
+ SYS_LockReg();
+}
+
+/**
+ * This is the timer interrupt service routine.
+ *
+ */
+void SysTick_Handler(void)
+{
+ /* enter interrupt */
+ rt_interrupt_enter();
+
+ rt_tick_increase();
+
+ /* leave interrupt */
+ rt_interrupt_leave();
+}
+/**
+ * This function will initial Nuvoton board.
+ */
+void rt_hw_board_init()
+{
+ /* NVIC Configuration */
+ NVIC_Configuration();
+
+ /* Configure the system clock */
+ rt_hw_system_init();
+ /* Configure the SysTick */
+ SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND);
+
+ /* Initial usart deriver, and set console device */
+ rt_hw_usart_init();
+#ifdef RT_USING_CONSOLE
+ rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
+#endif
+
+ /* Call components board initial (use INIT_BOARD_EXPORT()) */
+#ifdef RT_USING_COMPONENTS_INIT
+ rt_components_board_init();
+#endif
+}
+
+/*@}*/
diff --git a/bsp/nuvoton_m451/drivers/board.h b/bsp/nuvoton_m451/drivers/board.h
new file mode 100644
index 0000000000000000000000000000000000000000..3a51aa099c553d863935353da1dffe43ab09fb4e
--- /dev/null
+++ b/bsp/nuvoton_m451/drivers/board.h
@@ -0,0 +1,35 @@
+/*
+ * File : board.h
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2014, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2016-12-05 Pluto first implementation
+ */
+
+// <<< Use Configuration Wizard in Context Menu >>>
+#ifndef __BOARD_H__
+#define __BOARD_H__
+
+#include "M451Series.h"
+
+#define BOARD_PLL_CLOCK 72000000
+
+/* board configuration */
+// Internal SRAM memory size[Kbytes]
+// Default: 64
+#define M451_SRAM_SIZE 32
+#define M451_SRAM_END (0x20000000 + M451_SRAM_SIZE * 1024)
+
+void rt_hw_board_init(void);
+
+//#define PRINT_RCC_FREQ_INFO
+
+#endif
+
+// <<< Use Configuration Wizard in Context Menu >>>
diff --git a/bsp/nuvoton_m451/drivers/led.c b/bsp/nuvoton_m451/drivers/led.c
new file mode 100644
index 0000000000000000000000000000000000000000..9a0621d2c4aa39f09111e89b415085cdb937d9b6
--- /dev/null
+++ b/bsp/nuvoton_m451/drivers/led.c
@@ -0,0 +1,47 @@
+/*
+ * File : led.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2014, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2016-12-05 Pluto first implementation
+ */
+
+#include "led.h"
+/* RT_USING_COMPONENTS_INIT */
+#ifdef RT_USING_COMPONENTS_INIT
+#include
+#endif
+
+/*
+ LED: PC9 for M451 SDK
+*/
+#define LED_PORT PC
+#define LED_DATA(dat) (PC9 = dat)
+#define LED_BIT BIT9
+
+/* Initial led gpio pin */
+int rt_hw_led_init(void)
+{
+ /* Configure the GPIO_LED pin */
+ GPIO_SetMode(LED_PORT, LED_BIT, GPIO_MODE_OUTPUT);
+ return 0;
+}
+
+void rt_hw_led_on(void)
+{
+ LED_DATA(0);
+}
+
+void rt_hw_led_off(void)
+{
+ LED_DATA(1);
+}
+
+/* Initial components for device */
+INIT_DEVICE_EXPORT(rt_hw_led_init);
diff --git a/bsp/nuvoton_m451/drivers/led.h b/bsp/nuvoton_m451/drivers/led.h
new file mode 100644
index 0000000000000000000000000000000000000000..b85ef3bf064fc45ab7ba6fc3e1547c477168a04e
--- /dev/null
+++ b/bsp/nuvoton_m451/drivers/led.h
@@ -0,0 +1,26 @@
+/*
+ * File : led.h
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2014, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2016-12-05 Pluto first implementation
+ */
+
+#ifndef __LED_H__
+#define __LED_H__
+
+#include
+#include
+#include "M451Series.h"
+
+void rt_hw_led_on(void);
+void rt_hw_led_off(void);
+int rt_hw_led_init(void);
+
+#endif
diff --git a/bsp/nuvoton_m451/drivers/usart.c b/bsp/nuvoton_m451/drivers/usart.c
new file mode 100644
index 0000000000000000000000000000000000000000..a75f26d18cb265fc49cfdfa0c437987ff2d31a1c
--- /dev/null
+++ b/bsp/nuvoton_m451/drivers/usart.c
@@ -0,0 +1,132 @@
+/*
+ * File : usart.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006-2014, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2016-12-05 Pluto first implementation
+ */
+
+#include "usart.h"
+
+
+static rt_err_t m451_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
+{
+ UART_T* uart;
+
+ uart = (UART_T *)serial->parent.user_data;
+#if defined(RT_USING_UART0)
+ if (uart == UART0) {
+ /* Enable UART module clock */
+ CLK_EnableModuleClock(UART0_MODULE);
+
+ /* Select UART module clock source as HXT and UART module clock divider as 1 */
+ CLK_SetModuleClock(UART0_MODULE, CLK_CLKSEL1_UARTSEL_HXT, CLK_CLKDIV0_UART(1));
+
+ /* Set PD multi-function pins for UART0 RXD(PD.0) and TXD(PD.1) */
+ SYS->GPD_MFPL &= ~(SYS_GPD_MFPL_PD0MFP_Msk | SYS_GPD_MFPL_PD1MFP_Msk);
+ SYS->GPD_MFPL |= (SYS_GPD_MFPL_PD0MFP_UART0_RXD | SYS_GPD_MFPL_PD1MFP_UART0_TXD);
+
+ /* Reset UART module */
+ SYS_ResetModule(UART0_RST);
+
+ /* Configure UART0 and set UART0 Baudrate */
+ UART_Open(UART0, cfg->baud_rate);
+
+ /* Enable Interrupt */
+ UART_EnableInt(UART0, UART_INTEN_RDAIEN_Msk);
+ }
+#endif /* RT_USING_UART0 */
+
+#if defined(RT_USING_UART1)
+#endif /* RT_USING_UART1 */
+ return RT_EOK;
+}
+
+static rt_err_t m451_control(struct rt_serial_device *serial, int cmd, void *arg)
+{
+ UART_T* uart;
+ uart = (UART_T *)serial->parent.user_data;
+
+ switch (cmd)
+ {
+ case RT_DEVICE_CTRL_CLR_INT: {
+ /* Disable Interrupt */
+ UART_DisableInt(uart, UART_INTEN_RDAIEN_Msk);
+ break;
+ }
+ case RT_DEVICE_CTRL_SET_INT: {
+ UART_EnableInt(UART0, UART_INTEN_RDAIEN_Msk);
+ break;
+ }
+ }
+
+ return RT_EOK;
+}
+
+static int m451_putc(struct rt_serial_device *serial, char c)
+{
+ UART_T* uart;
+ uart = (UART_T *)serial->parent.user_data;
+ if (UART_IS_TX_FULL(uart)) {
+ UART_WAIT_TX_EMPTY(uart);
+ }
+ UART_WRITE(uart, c);
+ return 1;
+}
+
+static int m451_getc(struct rt_serial_device *serial)
+{
+ int ch = -1;
+ UART_T* uart;
+ uart = (UART_T *)serial->parent.user_data;
+
+ if (UART_IS_RX_READY(uart))
+ ch = UART_READ(uart);
+ return ch;
+}
+
+static const struct rt_uart_ops m451_uart_ops =
+{
+ m451_configure,
+ m451_control,
+ m451_putc,
+ m451_getc,
+};
+
+#if defined(RT_USING_UART0)
+struct rt_serial_device serial0;
+
+void UART0_IRQHandler(void)
+{
+ /* enter interrupt */
+ rt_interrupt_enter();
+
+ if (UART_IS_RX_READY(UART0)) {
+ rt_hw_serial_isr(&serial0, RT_SERIAL_EVENT_RX_IND);
+ }
+ /* leave interrupt */
+ rt_interrupt_leave();
+}
+#endif /* RT_USING_UART0 */
+
+void rt_hw_usart_init(void)
+{
+#ifdef RT_USING_UART0
+ struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
+ config.baud_rate = BAUD_RATE_115200;
+ serial0.ops = &m451_uart_ops;
+ serial0.config = config;
+
+ /* register UART0 device */
+ rt_hw_serial_register(&serial0, "uart0",
+ RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
+ UART0);
+#endif /* RT_USING_UART0 */
+
+}
diff --git a/bsp/nuvoton_m451/drivers/usart.h b/bsp/nuvoton_m451/drivers/usart.h
new file mode 100644
index 0000000000000000000000000000000000000000..1ae28389e58ba88c0c69ec59e16ae2d26fbfb98b
--- /dev/null
+++ b/bsp/nuvoton_m451/drivers/usart.h
@@ -0,0 +1,28 @@
+/*
+ * File : usart.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006-2014, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2016-12-05 Pluto first implementation
+ */
+
+#ifndef __USART_H__
+#define __USART_H__
+
+#include "M451Series.h"
+#include
+#include
+#include
+
+#define RT_USING_UART0
+//#define RT_USING_UART1
+
+void rt_hw_usart_init(void);
+
+#endif
diff --git a/bsp/nuvoton_m451/nuvoton_m451.ld b/bsp/nuvoton_m451/nuvoton_m451.ld
new file mode 100644
index 0000000000000000000000000000000000000000..ae2678dee3f670f4808b6e64e65257446a2151d8
--- /dev/null
+++ b/bsp/nuvoton_m451/nuvoton_m451.ld
@@ -0,0 +1,142 @@
+/*
+ * linker script for M451 with GNU ld
+ */
+
+/* Program Entry, set to mark it as "used" and avoid gc */
+MEMORY
+{
+ CODE (rx) : ORIGIN = 0x00000000, LENGTH = 256k /* 64KB flash */
+ DATA (rw) : ORIGIN = 0x20000000, LENGTH = 32k /* 4K sram */
+}
+ENTRY(Reset_Handler)
+_system_stack_size = 0x100;
+
+SECTIONS
+{
+ .text :
+ {
+ . = ALIGN(4);
+ /* Here Changed*/
+
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ *(.text) /* remaining code */
+ *(.text.*) /* remaining code */
+ *(.rodata) /* read-only data (constants) */
+ *(.rodata*)
+ *(.glue_7)
+ *(.glue_7t)
+ *(.gnu.linkonce.t*)
+
+ /* section information for finsh shell */
+ . = ALIGN(4);
+ __fsymtab_start = .;
+ KEEP(*(FSymTab))
+ __fsymtab_end = .;
+ . = ALIGN(4);
+ __vsymtab_start = .;
+ KEEP(*(VSymTab))
+ __vsymtab_end = .;
+ . = ALIGN(4);
+
+ /* section information for initial. */
+ . = ALIGN(4);
+ __rt_init_start = .;
+ KEEP(*(SORT(.rti_fn*)))
+ __rt_init_end = .;
+ . = ALIGN(4);
+
+ . = ALIGN(4);
+ _etext = .;
+ } > CODE = 0
+
+ /* .ARM.exidx is sorted, so has to go in its own output section. */
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+
+ /* This is used by the startup in order to initialize the .data secion */
+ _sidata = .;
+ } > CODE
+ __exidx_end = .;
+
+ /* .data section which is used for initialized data */
+
+ .data : AT (_sidata)
+ {
+ . = ALIGN(4);
+ /* This is used by the startup in order to initialize the .data secion */
+ _sdata = . ;
+
+ *(.data)
+ *(.data.*)
+ *(.gnu.linkonce.d*)
+
+ . = ALIGN(4);
+ /* This is used by the startup in order to initialize the .data secion */
+ _edata = . ;
+ } >DATA
+
+ .stack :
+ {
+ . = . + _system_stack_size;
+ . = ALIGN(4);
+ _estack = .;
+ } >DATA
+
+ __bss_start = .;
+ .bss :
+ {
+ . = ALIGN(4);
+ /* This is used by the startup in order to initialize the .bss secion */
+ _sbss = .;
+
+ *(.bss)
+ *(.bss.*)
+ *(COMMON)
+
+ . = ALIGN(4);
+ /* This is used by the startup in order to initialize the .bss secion */
+ _ebss = . ;
+
+ *(.bss.init)
+ } > DATA
+ __bss_end = .;
+
+ _end = .;
+
+ /* Stabs debugging sections. */
+ .stab 0 : { *(.stab) }
+ .stabstr 0 : { *(.stabstr) }
+ .stab.excl 0 : { *(.stab.excl) }
+ .stab.exclstr 0 : { *(.stab.exclstr) }
+ .stab.index 0 : { *(.stab.index) }
+ .stab.indexstr 0 : { *(.stab.indexstr) }
+ .comment 0 : { *(.comment) }
+ /* DWARF debug sections.
+ * Symbols in the DWARF debugging sections are relative to the beginning
+ * of the section so we begin them at 0. */
+ /* DWARF 1 */
+ .debug 0 : { *(.debug) }
+ .line 0 : { *(.line) }
+ /* GNU DWARF 1 extensions */
+ .debug_srcinfo 0 : { *(.debug_srcinfo) }
+ .debug_sfnames 0 : { *(.debug_sfnames) }
+ /* DWARF 1.1 and DWARF 2 */
+ .debug_aranges 0 : { *(.debug_aranges) }
+ .debug_pubnames 0 : { *(.debug_pubnames) }
+ /* DWARF 2 */
+ .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
+ .debug_abbrev 0 : { *(.debug_abbrev) }
+ .debug_line 0 : { *(.debug_line) }
+ .debug_frame 0 : { *(.debug_frame) }
+ .debug_str 0 : { *(.debug_str) }
+ .debug_loc 0 : { *(.debug_loc) }
+ .debug_macinfo 0 : { *(.debug_macinfo) }
+ /* SGI/MIPS DWARF 2 extensions */
+ .debug_weaknames 0 : { *(.debug_weaknames) }
+ .debug_funcnames 0 : { *(.debug_funcnames) }
+ .debug_typenames 0 : { *(.debug_typenames) }
+ .debug_varnames 0 : { *(.debug_varnames) }
+}
diff --git a/bsp/nuvoton_m451/nuvoton_m451.sct b/bsp/nuvoton_m451/nuvoton_m451.sct
new file mode 100644
index 0000000000000000000000000000000000000000..45489c568749553afc926b7ea6397707f0749220
--- /dev/null
+++ b/bsp/nuvoton_m451/nuvoton_m451.sct
@@ -0,0 +1,15 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x00000000 0x00040000 { ; load region size_region
+ ER_IROM1 0x00000000 0x00040000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+ RW_IRAM1 0x20000000 0x00008000 { ; RW data
+ .ANY (+RW +ZI)
+ }
+}
+
diff --git a/bsp/nuvoton_m451/project.uvproj b/bsp/nuvoton_m451/project.uvproj
new file mode 100644
index 0000000000000000000000000000000000000000..6b3251539d2dca032c6f0bd1980df42f014fa48a
--- /dev/null
+++ b/bsp/nuvoton_m451/project.uvproj
@@ -0,0 +1,793 @@
+
+
+
+ 1.1
+
+ ### uVision Project, (C) Keil Software
+
+
+
+ Template
+ 0x4
+ ARM-ADS
+ 5060061::V5.06 update 1 (build 61)::ARMCC
+
+
+ M453VG6AE
+ Nuvoton
+ IRAM(0x20000000-0x20007FFF) IROM(0-0x3FFFF) CLOCK(50000000) CPUTYPE("Cortex-M4") FPU2
+
+ undefined
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+ fromelf --bin ".\obj\@L.axf" --output ".\obj\@L.bin"
+ fromelf --text -c ".\obj\@L.axf" --output ".\obj\@L.txt"
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+ .;applications;drivers;Libraries\Device\Nuvoton\M451Series\Include;Libraries\CMSIS\Include;Libraries\StdDriver\inc;..\..\include;..\..\libcpu\arm\cortex-m4;..\..\libcpu\arm\common;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\finsh
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+ --keep *.o(FSymTab) --keep *.o(VSymTab)
+
+
+
+
+
+
+
+ Applications
+
+
+ application.c
+ 1
+ applications\application.c
+
+
+ startup.c
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+
+
+
+
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+
+
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+
+ led.c
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+ usart.c
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+
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+
+
+ CMSIS
+
+
+ system_M451Series.c
+ 1
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+
+
+ startup_M451Series.s
+ 2
+ Libraries\Device\Nuvoton\M451Series\Source\ARM\startup_M451Series.s
+
+
+
+
+ StdDriver
+
+
+ acmp.c
+ 1
+ Libraries\StdDriver\src\acmp.c
+
+
+ can.c
+ 1
+ Libraries\StdDriver\src\can.c
+
+
+ clk.c
+ 1
+ Libraries\StdDriver\src\clk.c
+
+
+ crc.c
+ 1
+ Libraries\StdDriver\src\crc.c
+
+
+ dac.c
+ 1
+ Libraries\StdDriver\src\dac.c
+
+
+ eadc.c
+ 1
+ Libraries\StdDriver\src\eadc.c
+
+
+ ebi.c
+ 1
+ Libraries\StdDriver\src\ebi.c
+
+
+ fmc.c
+ 1
+ Libraries\StdDriver\src\fmc.c
+
+
+ gpio.c
+ 1
+ Libraries\StdDriver\src\gpio.c
+
+
+ i2c.c
+ 1
+ Libraries\StdDriver\src\i2c.c
+
+
+ pdma.c
+ 1
+ Libraries\StdDriver\src\pdma.c
+
+
+ pwm.c
+ 1
+ Libraries\StdDriver\src\pwm.c
+
+
+ rtc.c
+ 1
+ Libraries\StdDriver\src\rtc.c
+
+
+ sc.c
+ 1
+ Libraries\StdDriver\src\sc.c
+
+
+ scuart.c
+ 1
+ Libraries\StdDriver\src\scuart.c
+
+
+ spi.c
+ 1
+ Libraries\StdDriver\src\spi.c
+
+
+ sys.c
+ 1
+ Libraries\StdDriver\src\sys.c
+
+
+ timer.c
+ 1
+ Libraries\StdDriver\src\timer.c
+
+
+ tk.c
+ 1
+ Libraries\StdDriver\src\tk.c
+
+
+ uart.c
+ 1
+ Libraries\StdDriver\src\uart.c
+
+
+ usbd.c
+ 1
+ Libraries\StdDriver\src\usbd.c
+
+
+ wdt.c
+ 1
+ Libraries\StdDriver\src\wdt.c
+
+
+ wwdt.c
+ 1
+ Libraries\StdDriver\src\wwdt.c
+
+
+
+
+ Kernel
+
+
+ clock.c
+ 1
+ ..\..\src\clock.c
+
+
+ device.c
+ 1
+ ..\..\src\device.c
+
+
+ idle.c
+ 1
+ ..\..\src\idle.c
+
+
+ ipc.c
+ 1
+ ..\..\src\ipc.c
+
+
+ irq.c
+ 1
+ ..\..\src\irq.c
+
+
+ kservice.c
+ 1
+ ..\..\src\kservice.c
+
+
+ mem.c
+ 1
+ ..\..\src\mem.c
+
+
+ mempool.c
+ 1
+ ..\..\src\mempool.c
+
+
+ object.c
+ 1
+ ..\..\src\object.c
+
+
+ scheduler.c
+ 1
+ ..\..\src\scheduler.c
+
+
+ thread.c
+ 1
+ ..\..\src\thread.c
+
+
+ src_timer.c
+ 1
+ ..\..\src\timer.c
+
+
+
+
+ CORTEX-M4
+
+
+ cpuport.c
+ 1
+ ..\..\libcpu\arm\cortex-m4\cpuport.c
+
+
+ context_rvds.S
+ 2
+ ..\..\libcpu\arm\cortex-m4\context_rvds.S
+
+
+ backtrace.c
+ 1
+ ..\..\libcpu\arm\common\backtrace.c
+
+
+ div0.c
+ 1
+ ..\..\libcpu\arm\common\div0.c
+
+
+ showmem.c
+ 1
+ ..\..\libcpu\arm\common\showmem.c
+
+
+
+
+ DeviceDrivers
+
+
+ serial.c
+ 1
+ ..\..\components\drivers\serial\serial.c
+
+
+ completion.c
+ 1
+ ..\..\components\drivers\src\completion.c
+
+
+ dataqueue.c
+ 1
+ ..\..\components\drivers\src\dataqueue.c
+
+
+ pipe.c
+ 1
+ ..\..\components\drivers\src\pipe.c
+
+
+ portal.c
+ 1
+ ..\..\components\drivers\src\portal.c
+
+
+ ringbuffer.c
+ 1
+ ..\..\components\drivers\src\ringbuffer.c
+
+
+ workqueue.c
+ 1
+ ..\..\components\drivers\src\workqueue.c
+
+
+
+
+ finsh
+
+
+ shell.c
+ 1
+ ..\..\components\finsh\shell.c
+
+
+ symbol.c
+ 1
+ ..\..\components\finsh\symbol.c
+
+
+ cmd.c
+ 1
+ ..\..\components\finsh\cmd.c
+
+
+ finsh_compiler.c
+ 1
+ ..\..\components\finsh\finsh_compiler.c
+
+
+ finsh_error.c
+ 1
+ ..\..\components\finsh\finsh_error.c
+
+
+ finsh_heap.c
+ 1
+ ..\..\components\finsh\finsh_heap.c
+
+
+ finsh_init.c
+ 1
+ ..\..\components\finsh\finsh_init.c
+
+
+ finsh_node.c
+ 1
+ ..\..\components\finsh\finsh_node.c
+
+
+ finsh_ops.c
+ 1
+ ..\..\components\finsh\finsh_ops.c
+
+
+ finsh_parser.c
+ 1
+ ..\..\components\finsh\finsh_parser.c
+
+
+ finsh_var.c
+ 1
+ ..\..\components\finsh\finsh_var.c
+
+
+ finsh_vm.c
+ 1
+ ..\..\components\finsh\finsh_vm.c
+
+
+ finsh_token.c
+ 1
+ ..\..\components\finsh\finsh_token.c
+
+
+
+
+
+
+
+
diff --git a/bsp/nuvoton_m451/project.uvprojx b/bsp/nuvoton_m451/project.uvprojx
new file mode 100644
index 0000000000000000000000000000000000000000..f8cead88b8f7989bc20b4eac2c9e256f39322f3b
--- /dev/null
+++ b/bsp/nuvoton_m451/project.uvprojx
@@ -0,0 +1,754 @@
+
+
+
+ 2.1
+
+ ### uVision Project, (C) Keil Software
+
+
+
+ template
+ 0x4
+ ARM-ADS
+ 5060061::V5.06 update 1 (build 61)::ARMCC
+
+
+ M451VG6AE
+ Nuvoton
+ Nuvoton.NuMicro_DFP.1.0.5
+ http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack
+ IROM(0x00000000,0x40000) IRAM(0x20000000,0x8000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000)
+
+
+ UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0M451_AP_256 -FS00 -FL040000 -FP0($$Device:M451VG6AE$Flash\M451_AP_256.FLM))
+ 0
+ $$Device:M451VG6AE$Device\M451\Include\M451Series.h
+
+
+
+
+
+
+
+
+
+ $$Device:M451VG6AE$SVD\Nuvoton\M451_v1.SVD
+ 0
+ 0
+
+
+
+
+
+
+ 0
+ 0
+ 0
+ 0
+ 1
+
+ .\Objects\
+ template
+ 1
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+ 1
+ 1
+ .\Listings\
+ 1
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+ 0
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+ 0
+ 0
+ 3
+
+
+ 1
+
+
+ SARMCM3.DLL
+
+ DCM.DLL
+ -pCM4
+ SARMCM3.DLL
+
+ TCM.DLL
+ -pCM4
+
+
+
+ 1
+ 0
+ 0
+ 0
+ 16
+
+
+
+
+ 1
+ 0
+ 0
+ 1
+ 1
+ 4096
+
+ 1
+ BIN\UL2CM3.DLL
+ "" ()
+
+
+
+
+ 0
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+
+
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+ "Cortex-M4"
+
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+
+
+
+ .;applications;drivers;Libraries\Device\Nuvoton\M451Series\Include;Libraries\CMSIS\Include;Libraries\StdDriver\inc;..\..\include;..\..\libcpu\arm\cortex-m4;..\..\libcpu\arm\common;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\finsh
+
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+
+
+
+
+ 1
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+ 0
+ 0
+ 1
+ 0
+ 0x00000000
+ 0x20000000
+
+
+
+
+ --keep *.o(FSymTab) --keep *.o(VSymTab)
+
+
+
+
+
+
+
+ Applications
+
+
+ application.c
+ 1
+ applications\application.c
+
+
+ startup.c
+ 1
+ applications\startup.c
+
+
+
+
+ Drivers
+
+
+ board.c
+ 1
+ drivers\board.c
+
+
+ led.c
+ 1
+ drivers\led.c
+
+
+ usart.c
+ 1
+ drivers\usart.c
+
+
+
+
+ CMSIS
+
+
+ system_M451Series.c
+ 1
+ Libraries\Device\Nuvoton\M451Series\Source\system_M451Series.c
+
+
+ startup_M451Series.s
+ 2
+ Libraries\Device\Nuvoton\M451Series\Source\ARM\startup_M451Series.s
+
+
+
+
+ StdDriver
+
+
+ acmp.c
+ 1
+ Libraries\StdDriver\src\acmp.c
+
+
+ can.c
+ 1
+ Libraries\StdDriver\src\can.c
+
+
+ clk.c
+ 1
+ Libraries\StdDriver\src\clk.c
+
+
+ crc.c
+ 1
+ Libraries\StdDriver\src\crc.c
+
+
+ dac.c
+ 1
+ Libraries\StdDriver\src\dac.c
+
+
+ eadc.c
+ 1
+ Libraries\StdDriver\src\eadc.c
+
+
+ ebi.c
+ 1
+ Libraries\StdDriver\src\ebi.c
+
+
+ fmc.c
+ 1
+ Libraries\StdDriver\src\fmc.c
+
+
+ gpio.c
+ 1
+ Libraries\StdDriver\src\gpio.c
+
+
+ i2c.c
+ 1
+ Libraries\StdDriver\src\i2c.c
+
+
+ pdma.c
+ 1
+ Libraries\StdDriver\src\pdma.c
+
+
+ pwm.c
+ 1
+ Libraries\StdDriver\src\pwm.c
+
+
+ rtc.c
+ 1
+ Libraries\StdDriver\src\rtc.c
+
+
+ sc.c
+ 1
+ Libraries\StdDriver\src\sc.c
+
+
+ scuart.c
+ 1
+ Libraries\StdDriver\src\scuart.c
+
+
+ spi.c
+ 1
+ Libraries\StdDriver\src\spi.c
+
+
+ sys.c
+ 1
+ Libraries\StdDriver\src\sys.c
+
+
+ timer.c
+ 1
+ Libraries\StdDriver\src\timer.c
+
+
+ tk.c
+ 1
+ Libraries\StdDriver\src\tk.c
+
+
+ uart.c
+ 1
+ Libraries\StdDriver\src\uart.c
+
+
+ usbd.c
+ 1
+ Libraries\StdDriver\src\usbd.c
+
+
+ wdt.c
+ 1
+ Libraries\StdDriver\src\wdt.c
+
+
+ wwdt.c
+ 1
+ Libraries\StdDriver\src\wwdt.c
+
+
+
+
+ Kernel
+
+
+ clock.c
+ 1
+ ..\..\src\clock.c
+
+
+ device.c
+ 1
+ ..\..\src\device.c
+
+
+ idle.c
+ 1
+ ..\..\src\idle.c
+
+
+ ipc.c
+ 1
+ ..\..\src\ipc.c
+
+
+ irq.c
+ 1
+ ..\..\src\irq.c
+
+
+ kservice.c
+ 1
+ ..\..\src\kservice.c
+
+
+ mem.c
+ 1
+ ..\..\src\mem.c
+
+
+ mempool.c
+ 1
+ ..\..\src\mempool.c
+
+
+ object.c
+ 1
+ ..\..\src\object.c
+
+
+ scheduler.c
+ 1
+ ..\..\src\scheduler.c
+
+
+ thread.c
+ 1
+ ..\..\src\thread.c
+
+
+ src_timer.c
+ 1
+ ..\..\src\timer.c
+
+
+
+
+ CORTEX-M4
+
+
+ cpuport.c
+ 1
+ ..\..\libcpu\arm\cortex-m4\cpuport.c
+
+
+ context_rvds.S
+ 2
+ ..\..\libcpu\arm\cortex-m4\context_rvds.S
+
+
+ backtrace.c
+ 1
+ ..\..\libcpu\arm\common\backtrace.c
+
+
+ div0.c
+ 1
+ ..\..\libcpu\arm\common\div0.c
+
+
+ showmem.c
+ 1
+ ..\..\libcpu\arm\common\showmem.c
+
+
+
+
+ DeviceDrivers
+
+
+ serial.c
+ 1
+ ..\..\components\drivers\serial\serial.c
+
+
+ completion.c
+ 1
+ ..\..\components\drivers\src\completion.c
+
+
+ dataqueue.c
+ 1
+ ..\..\components\drivers\src\dataqueue.c
+
+
+ pipe.c
+ 1
+ ..\..\components\drivers\src\pipe.c
+
+
+ portal.c
+ 1
+ ..\..\components\drivers\src\portal.c
+
+
+ ringbuffer.c
+ 1
+ ..\..\components\drivers\src\ringbuffer.c
+
+
+ workqueue.c
+ 1
+ ..\..\components\drivers\src\workqueue.c
+
+
+
+
+ finsh
+
+
+ shell.c
+ 1
+ ..\..\components\finsh\shell.c
+
+
+ symbol.c
+ 1
+ ..\..\components\finsh\symbol.c
+
+
+ cmd.c
+ 1
+ ..\..\components\finsh\cmd.c
+
+
+ finsh_compiler.c
+ 1
+ ..\..\components\finsh\finsh_compiler.c
+
+
+ finsh_error.c
+ 1
+ ..\..\components\finsh\finsh_error.c
+
+
+ finsh_heap.c
+ 1
+ ..\..\components\finsh\finsh_heap.c
+
+
+ finsh_init.c
+ 1
+ ..\..\components\finsh\finsh_init.c
+
+
+ finsh_node.c
+ 1
+ ..\..\components\finsh\finsh_node.c
+
+
+ finsh_ops.c
+ 1
+ ..\..\components\finsh\finsh_ops.c
+
+
+ finsh_parser.c
+ 1
+ ..\..\components\finsh\finsh_parser.c
+
+
+ finsh_var.c
+ 1
+ ..\..\components\finsh\finsh_var.c
+
+
+ finsh_vm.c
+ 1
+ ..\..\components\finsh\finsh_vm.c
+
+
+ finsh_token.c
+ 1
+ ..\..\components\finsh\finsh_token.c
+
+
+
+
+
+
+
+
diff --git a/bsp/nuvoton_m451/rtconfig.h b/bsp/nuvoton_m451/rtconfig.h
new file mode 100644
index 0000000000000000000000000000000000000000..58cdfdcb24ddf45b8fda082524c40cd46dafff53
--- /dev/null
+++ b/bsp/nuvoton_m451/rtconfig.h
@@ -0,0 +1,114 @@
+/* RT-Thread config file */
+#ifndef __RTTHREAD_CFG_H__
+#define __RTTHREAD_CFG_H__
+
+/* RT_NAME_MAX*/
+#define RT_NAME_MAX 8
+
+/* RT_ALIGN_SIZE*/
+#define RT_ALIGN_SIZE 4
+
+/* PRIORITY_MAX */
+#define RT_THREAD_PRIORITY_MAX 32
+//#define IDLE_THREAD_STACK_SIZE 128
+/* Tick per Second */
+#define RT_TICK_PER_SECOND 1000
+
+/* SECTION: RT_DEBUG */
+/* Thread Debug */
+#define RT_DEBUG
+#define RT_DEBUG_INIT 1
+#define RT_USING_OVERFLOW_CHECK
+
+/* Using Hook */
+//#define RT_USING_HOOK
+
+/* Using Software Timer */
+/* #define RT_USING_TIMER_SOFT */
+#define RT_TIMER_THREAD_PRIO 4
+#define RT_TIMER_THREAD_STACK_SIZE 512
+#define RT_TIMER_TICK_PER_SECOND 10
+
+/* SECTION: IPC */
+/* Using Semaphore*/
+#define RT_USING_SEMAPHORE
+
+/* Using Mutex */
+#define RT_USING_MUTEX
+
+/* Using Event */
+#define RT_USING_EVENT
+
+/* Using MailBox */
+#define RT_USING_MAILBOX
+
+/* Using Message Queue */
+#define RT_USING_MESSAGEQUEUE
+
+/* SECTION: Memory Management */
+/* Using Memory Pool Management*/
+#define RT_USING_MEMPOOL
+
+/* Using Dynamic Heap Management */
+#define RT_USING_HEAP
+
+/* Using Small MM */
+#define RT_USING_SMALL_MEM
+
+//
+//#define RT_USING_COMPONENTS_INIT
+
+/* SECTION: Device System */
+/* Using Device System */
+#define RT_USING_DEVICE
+//
+#define RT_USING_DEVICE_IPC
+//
+#define RT_USING_SERIAL
+
+/* SECTION: Console options */
+#define RT_USING_CONSOLE
+/* the buffer size of console*/
+#define RT_CONSOLEBUF_SIZE 128
+//
+#define RT_CONSOLE_DEVICE_NAME "uart0"
+
+
+
+/* SECTION: finsh, a C-Express shell */
+#define RT_USING_FINSH
+/* configure finsh parameters */
+/*
+#define FINSH_THREAD_PRIORITY 25
+#define FINSH_THREAD_STACK_SIZE 1024
+#define FINSH_USING_HISTORY 0
+#define FINSH_HISTORY_LINES 1
+*/
+/* Using symbol table */
+#define FINSH_USING_SYMTAB
+#define FINSH_USING_DESCRIPTION
+
+/* SECTION: libc management */
+//#define RT_USING_LIBC
+
+/* SECTION: device filesystem */
+/* #define RT_USING_DFS */
+//#define RT_USING_DFS_ELMFAT
+#define RT_DFS_ELM_WORD_ACCESS
+/* Reentrancy (thread safe) of the FatFs module. */
+#define RT_DFS_ELM_REENTRANT
+/* Number of volumes (logical drives) to be used. */
+#define RT_DFS_ELM_DRIVES 2
+/* #define RT_DFS_ELM_USE_LFN 1 */
+#define RT_DFS_ELM_MAX_LFN 255
+/* Maximum sector size to be handled. */
+#define RT_DFS_ELM_MAX_SECTOR_SIZE 512
+
+#define RT_USING_DFS_ROMFS
+
+/* the max number of mounted filesystem */
+#define DFS_FILESYSTEMS_MAX 2
+/* the max number of opened files */
+#define DFS_FD_MAX 4
+
+#endif
diff --git a/bsp/nuvoton_m451/rtconfig.py b/bsp/nuvoton_m451/rtconfig.py
new file mode 100644
index 0000000000000000000000000000000000000000..799aa803d4fe6fc549926661f8c71e671e5fdb8c
--- /dev/null
+++ b/bsp/nuvoton_m451/rtconfig.py
@@ -0,0 +1,125 @@
+import os
+
+# toolchains options
+ARCH='arm'
+CPU='cortex-m4'
+CROSS_TOOL='keil'
+
+if os.getenv('RTT_CC'):
+ CROSS_TOOL = os.getenv('RTT_CC')
+
+# cross_tool provides the cross compiler
+# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR
+if CROSS_TOOL == 'iar': # not support gcc
+ PLATFORM = 'iar'
+ EXEC_PATH = 'C:/IAR'
+ print('Not Supported')
+ exit(0)
+elif CROSS_TOOL == 'keil':
+ PLATFORM = 'armcc'
+ EXEC_PATH = r'C:\Keil_v5'
+elif CROSS_TOOL == 'gcc':
+ PLATFORM = 'gcc'
+ EXEC_PATH = r'C:\Program Files\GNU Tools ARM Embedded\5.4 2016q3\bin'
+
+if os.getenv('RTT_EXEC_PATH'):
+ EXEC_PATH = os.getenv('RTT_EXEC_PATH')
+
+BUILD = 'debug'
+
+if PLATFORM == 'gcc':
+ # toolchains
+ PREFIX = 'arm-none-eabi-'
+ CC = PREFIX + 'gcc'
+ AS = PREFIX + 'gcc'
+ AR = PREFIX + 'ar'
+ LINK = PREFIX + 'gcc'
+ TARGET_EXT = 'elf'
+ SIZE = PREFIX + 'size'
+ OBJDUMP = PREFIX + 'objdump'
+ OBJCPY = PREFIX + 'objcopy'
+
+ DEVICE = ' -mcpu=cortex-m4 -mthumb -ffunction-sections -fdata-sections'
+ CFLAGS = DEVICE + ' -std=gnu9x'
+ AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp'
+ LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread-nuvoton_m451.map,-cref,-u,Reset_Handler -T nuvoton_m451.ld'
+
+ CPATH = ''
+ LPATH = ''
+
+ if BUILD == 'debug':
+ CFLAGS += ' -O0 -gdwarf-2'
+ AFLAGS += ' -gdwarf-2'
+ else:
+ CFLAGS += ' -O2'
+
+ POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread-nuvoton_m451.bin\n' + OBJCPY + ' -O ihex $TARGET rtthread-nuvoton_m451.hex\n' + SIZE + ' $TARGET \n'
+
+elif PLATFORM == 'armcc':
+ # toolchains
+ CC = 'armcc'
+ AS = 'armasm'
+ AR = 'armar'
+ LINK = 'armlink'
+ TARGET_EXT = 'axf'
+
+ DEVICE = ' --device DARMSTM'
+ CFLAGS = DEVICE + ' --apcs=interwork'
+ AFLAGS = DEVICE
+ LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers --list rtthread-nuvoton_m451.map --scatter nuvoton_m451.sct'
+
+ CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include'
+ LFLAGS += ' --libpath ' + EXEC_PATH + '/ARM/ARMCC/lib'
+
+ EXEC_PATH += '/ARM/ARMCC/bin'
+
+ if BUILD == 'debug':
+ CFLAGS += ' -g -O0'
+ AFLAGS += ' -g'
+ else:
+ CFLAGS += ' -O2'
+
+ POST_ACTION = 'fromelf --bin $TARGET --output rtthread-nuvoton_m451.bin \nfromelf -z $TARGET'
+
+elif PLATFORM == 'iar':
+ # toolchains
+ CC = 'iccarm'
+ AS = 'iasmarm'
+ AR = 'iarchive'
+ LINK = 'ilinkarm'
+ TARGET_EXT = 'out'
+
+ DEVICE = ' -D USE_STDPERIPH_DRIVER' + ' -D STM32F10X_HD'
+
+ CFLAGS = DEVICE
+ CFLAGS += ' --diag_suppress Pa050'
+ CFLAGS += ' --no_cse'
+ CFLAGS += ' --no_unroll'
+ CFLAGS += ' --no_inline'
+ CFLAGS += ' --no_code_motion'
+ CFLAGS += ' --no_tbaa'
+ CFLAGS += ' --no_clustering'
+ CFLAGS += ' --no_scheduling'
+ CFLAGS += ' --debug'
+ CFLAGS += ' --endian=little'
+ CFLAGS += ' --cpu=Cortex-M4'
+ CFLAGS += ' -e'
+ CFLAGS += ' --fpu=None'
+ CFLAGS += ' --dlib_config "' + IAR_PATH + '/arm/INC/c/DLib_Config_Normal.h"'
+ CFLAGS += ' -Ol'
+ CFLAGS += ' --use_c++_inline'
+
+ AFLAGS = ''
+ AFLAGS += ' -s+'
+ AFLAGS += ' -w+'
+ AFLAGS += ' -r'
+ AFLAGS += ' --cpu Cortex-M4'
+ AFLAGS += ' --fpu None'
+
+ LFLAGS = ' --config stm32f0xx_flash.icf'
+ LFLAGS += ' --redirect _Printf=_PrintfTiny'
+ LFLAGS += ' --redirect _Scanf=_ScanfSmall'
+ LFLAGS += ' --entry __iar_program_start'
+
+ EXEC_PATH = IAR_PATH + '/arm/bin/'
+ POST_ACTION = ''
diff --git a/bsp/nuvoton_m451/template.uvproj b/bsp/nuvoton_m451/template.uvproj
new file mode 100644
index 0000000000000000000000000000000000000000..79adf561a9e52cd2160eec3f6d0928d6fd587921
--- /dev/null
+++ b/bsp/nuvoton_m451/template.uvproj
@@ -0,0 +1,397 @@
+
+
+
+ 1.1
+
+ ### uVision Project, (C) Keil Software
+
+
+
+ Template
+ 0x4
+ ARM-ADS
+
+
+ M453VG6AE
+ Nuvoton
+ IRAM(0x20000000-0x20007FFF) IROM(0-0x3FFFF) CLOCK(50000000) CPUTYPE("Cortex-M4") FPU2
+
+ undefined
+
+ 0
+
+
+
+
+
+
+
+
+
+
+ SFD\Nuvoton\M451_v1.SFR
+ 0
+
+
+
+
+
+
+ 0
+ 0
+ 0
+ 0
+ 1
+
+ .\obj\
+ template
+ 1
+ 0
+ 0
+ 1
+ 1
+ .\lst\
+ 1
+ 0
+ 0
+
+ 0
+ 0
+
+
+ 0
+ 0
+ 0
+ 0
+
+
+ 0
+ 0
+
+
+ 0
+ 0
+
+
+ 1
+ 1
+ fromelf --bin ".\obj\@L.axf" --output ".\obj\@L.bin"
+ fromelf --text -c ".\obj\@L.axf" --output ".\obj\@L.txt"
+ 0
+ 0
+
+ 0
+
+
+
+ 0
+ 0
+ 0
+ 0
+ 0
+ 1
+ 0
+ 0
+ 0
+ 0
+ 3
+
+
+
+
+ SARMCM3.DLL
+
+ DARMCM1.DLL
+
+ SARMCM3.DLL
+
+ TARMCM1.DLL
+
+
+
+
+ 1
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+
+
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+ 0
+ 1
+ 0
+
+ 0
+ 11
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Bin\Nu_Link.dll
+
+
+
+
+ 1
+ 0
+ 0
+ 1
+ 1
+ 4102
+
+ 0
+ Bin\Nu_Link.dll
+
+
+
+
+
+ 0
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+ 1
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+ 1
+ 1
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+ 1
+ 1
+ 0
+ 0
+ 1
+ 1
+ 0
+ 1
+ 1
+ 1
+ 0
+ 0
+ 0
+ 1
+ 1
+ "Cortex-M4"
+
+ 0
+ 0
+ 0
+ 1
+ 1
+ 0
+ 0
+ 2
+ 0
+ 0
+ 8
+ 0
+ 0
+ 0
+ 3
+ 5
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 1
+ 0
+ 0
+ 0
+ 0
+ 1
+ 0
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 0
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+ 0x0
+
+
+ 0
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+ 0x0
+
+
+ 0
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+ 0x0
+
+
+ 0
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+ 0x0
+
+
+ 0
+ 0x20000000
+ 0x8000
+
+
+ 1
+ 0x0
+ 0x40000
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 1
+ 0x0
+ 0x0
+
+
+ 1
+ 0x0
+ 0x0
+
+
+ 1
+ 0x0
+ 0x0
+
+
+ 1
+ 0x0
+ 0x40000
+
+
+ 1
+ 0x0
+ 0x0
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 0
+ 0x0
+ 0x0
+
+
+ 0
+ 0x20000000
+ 0x8000
+
+
+ 0
+ 0x0
+ 0x0
+
+
+
+
+
+ 1
+ 1
+ 0
+ 0
+ 1
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+
+
+
+
+
+
+
+
+ 1
+ 0
+ 0
+ 1
+ 0
+ 0
+ 0
+ 0
+ 0
+
+
+
+
+
+
+
+
+ 1
+ 0
+ 0
+ 0
+ 1
+ 0
+ 0x00000000
+ 0x20000000
+
+
+
+ --map --first='startup_M451Series.o(RESET)' --datacompressor=off --info=inline --entry Reset_Handler
+
+
+
+
+
+
+
+
+
+
+
diff --git a/bsp/nuvoton_m451/template.uvprojx b/bsp/nuvoton_m451/template.uvprojx
new file mode 100644
index 0000000000000000000000000000000000000000..95a182e35b5faa2873ae6294b815f6160f6224ff
--- /dev/null
+++ b/bsp/nuvoton_m451/template.uvprojx
@@ -0,0 +1,376 @@
+
+
+
+ 2.1
+
+ ### uVision Project, (C) Keil Software
+
+
+
+ template
+ 0x4
+ ARM-ADS
+
+
+ M451VG6AE
+ Nuvoton
+ Nuvoton.NuMicro_DFP.1.0.5
+ http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack
+ IROM(0x00000000,0x40000) IRAM(0x20000000,0x8000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000)
+
+
+ UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0M451_AP_256 -FS00 -FL040000 -FP0($$Device:M451VG6AE$Flash\M451_AP_256.FLM))
+ 0
+ $$Device:M451VG6AE$Device\M451\Include\M451Series.h
+
+
+
+
+
+
+
+
+
+ $$Device:M451VG6AE$SVD\Nuvoton\M451_v1.SVD
+ 0
+ 0
+
+
+
+
+
+
+ 0
+ 0
+ 0
+ 0
+ 1
+
+ .\Objects\
+ template
+ 1
+ 0
+ 0
+ 1
+ 1
+ .\Listings\
+ 1
+ 0
+ 0
+
+ 0
+ 0
+
+
+ 0
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+
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+
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+ 0
+
+
+
+ 0
+ 0
+ 0
+ 0
+ 0
+ 1
+ 0
+ 0
+ 0
+ 0
+ 3
+
+
+ 1
+
+
+ SARMCM3.DLL
+
+ DCM.DLL
+ -pCM4
+ SARMCM3.DLL
+
+ TCM.DLL
+ -pCM4
+
+
+
+ 1
+ 0
+ 0
+ 0
+ 16
+
+
+
+
+ 1
+ 0
+ 0
+ 1
+ 1
+ 4096
+
+ 1
+ BIN\UL2CM3.DLL
+ "" ()
+
+
+
+
+ 0
+
+
+
+ 0
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
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+ 1
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+ 1
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+ 1
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+ 0
+ "Cortex-M4"
+
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+
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+