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提交 5c420c0c 编写于 作者: B Bernard Xiong
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Merge branch 'master' of https://github.com/RT-Thread/rt-thread

上级 41f2f182 44712ba2
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Showing with 148740 addition and 296 deletion
bsp/imxrt1052-evk/drivers/drv_eth_fire.c
浏览文件 @ 5c420c0c
......@@ -319,7 +319,7 @@ static void _enet_io_init(void)
static void _enet_clk_init(void)
{
const clock_enet_pll_config_t config = {true, false, false, 1, 1};
const clock_enet_pll_config_t config = {true, false, 1};
CLOCK_InitEnetPll(&config);
IOMUXC_EnableMode(IOMUXC_GPR, kIOMUXC_GPR_ENET1TxClkOutputDir, true);
......
bsp/imxrt1052-evk/drivers/drv_pin.c
浏览文件 @ 5c420c0c
......@@ -436,13 +436,11 @@ static void rt1052_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
if(rt1052_pin_map[pin].gpio != GPIO5)
{
CLOCK_EnableClock(kCLOCK_Iomuxc);
IOMUXC_SetPinMux(0x401F8010U + pin*4, 0x5U, 0, 0, 0, 1);
}
else
{
CLOCK_EnableClock(kCLOCK_IomuxcSnvs);
IOMUXC_SetPinMux(0x400A8000U + (pin-125)*4, 0x5U, 0, 0, 0, 1);
}
......@@ -566,6 +564,7 @@ static rt_err_t rt1052_pin_irq_enable(struct rt_device *device, rt_base_t pin, r
{
gpio_pin_config_t gpio;
IRQn_Type irq_num;
rt_uint32_t config_value = 0x1b0a0;
struct rt1052_pin* pin_map = RT_NULL;
struct rt1052_irq* irq_map = RT_NULL;
......@@ -639,6 +638,15 @@ static rt_err_t rt1052_pin_irq_enable(struct rt_device *device, rt_base_t pin, r
break;
}
if(rt1052_pin_map[pin].gpio != GPIO5)
{
IOMUXC_SetPinConfig(0, 0, 0, 0, 0x401F8200U + pin*4, config_value);
}
else
{
IOMUXC_SetPinConfig(0, 0, 0, 0, 0x400A8018U + (pin-125)*4, config_value);
}
irq_num = rt1052_get_irqnum(rt1052_pin_map[pin].gpio, rt1052_pin_map[pin].gpio_pin);
NVIC_SetPriority(irq_num, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 5, 0));
......
bsp/qemu-vexpress-a9/qemu-dbg.sh 0 → 100755
浏览文件 @ 5c420c0c
if [ ! -f "sd.bin" ]; then
dd if=/dev/zero of=sd.bin bs=1024 count=65536
fi
qemu-system-arm -M vexpress-a9 -kernel rtthread.elf -serial vc -serial vc -sd sd.bin -S -s
\ No newline at end of file
bsp/qemu-vexpress-a9/qemu-nographic.sh
浏览文件 @ 5c420c0c
if [ ! -f "sd.bin" ]; then
dd if=/dev/zero of=sd.bin bs=64M count=1
dd if=/dev/zero of=sd.bin bs=1024 count=65536
fi
qemu-system-arm -M vexpress-a9 -kernel rtthread.elf -nographic -sd sd.bin -net nic -net tap
......
bsp/qemu-vexpress-a9/qemu.sh
浏览文件 @ 5c420c0c
if [ ! -f "sd.bin" ]; then
dd if=/dev/zero of=sd.bin bs=64M count=1
dd if=/dev/zero of=sd.bin bs=1024 count=65536
fi
qemu-system-arm -M vexpress-a9 -kernel rtthread.elf -serial stdio -sd sd.bin
bsp/stm32f10x-HAL/drivers/board.c
浏览文件 @ 5c420c0c
......@@ -49,11 +49,12 @@ void HAL_MspInit(void)
void SystemClock_Config(void)
{
rt_err_t result;
rt_err_t ret = RT_EOK;
RCC_OscInitTypeDef RCC_OscInitStruct;
RCC_ClkInitTypeDef RCC_ClkInitStruct;
/**Initializes the CPU, AHB and APB busses clocks
*/
#if !defined(RT_USING_HSI)
/* Initializes the CPU, AHB and APB busses clocks */
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
RCC_OscInitStruct.HSEPredivValue = RCC_HSE_PREDIV_DIV1;
......@@ -61,25 +62,45 @@ void SystemClock_Config(void)
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL9;
result = HAL_RCC_OscConfig(&RCC_OscInitStruct);
RT_ASSERT(result == HAL_OK);
/**Initializes the CPU, AHB and APB busses clocks
*/
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
ret = HAL_RCC_OscConfig(&RCC_OscInitStruct);
RT_ASSERT(ret == HAL_OK);
/* Initializes the CPU, AHB and APB busses clocks */
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK |
RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
result = HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2);
RT_ASSERT(result == HAL_OK);
/**Configure the Systick interrupt time
*/
ret = HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2);
RT_ASSERT(ret == HAL_OK);
HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq() / RT_TICK_PER_SECOND);
/**Configure the Systick
*/
HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK);
/* SysTick_IRQn interrupt configuration */
HAL_NVIC_SetPriority(SysTick_IRQn, 15, 0);
#else
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
RCC_OscInitStruct.HSICalibrationValue = 16;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI_DIV2;
RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL16;
ret = HAL_RCC_OscConfig(&RCC_OscInitStruct);
RT_ASSERT(ret == HAL_OK);
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK |
RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
ret = HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2);
RT_ASSERT(ret == HAL_OK);
HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq()/RT_TICK_PER_SECOND);
HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK);
HAL_NVIC_SetPriority(SysTick_IRQn, 15, 0);
#endif
}
/**
......
bsp/stm32f10x-HAL/drivers/drv_gpio.c
浏览文件 @ 5c420c0c
......@@ -18,76 +18,142 @@
#include <board.h>
#include <rtthread.h>
#ifdef RT_USING_PIN
#define __STM32_PIN(index, gpio, gpio_index) {index, GPIO##gpio##_CLK_ENABLE, GPIO##gpio, GPIO_PIN_##gpio_index}
#define __STM32_PIN_DEFAULT {-1, 0, 0, 0}
#define __STM32_PIN(index, gpio, gpio_index) (gpio | gpio_index)
#define __STM32_PIN_DEFAULT 0
static void GPIOA_CLK_ENABLE(void)
#define A (1U << 8)
#define B (2U << 8)
#define C (3U << 8)
#define D (4U << 8)
#define E (5U << 8)
#define F (6U << 8)
#define G (7U << 8)
#define H (8U << 8)
#define I (9U << 8)
#define J (10U << 8)
#define K (11U << 8)
static GPIO_TypeDef * get_st_gpio(rt_uint16_t gpio_pin)
{
#ifdef __HAL_RCC_GPIOA_CLK_ENABLE
__HAL_RCC_GPIOA_CLK_ENABLE();
#endif
switch(gpio_pin & 0xFF00)
{
case A:
#ifdef GPIOA
return GPIOA;
#endif
case B:
#ifdef GPIOB
return GPIOB;
#endif
case C:
#ifdef GPIOC
return GPIOC;
#endif
case D:
#ifdef GPIOD
return GPIOD;
#endif
case E:
#ifdef GPIOE
return GPIOE;
#endif
case F:
#ifdef GPIOF
return GPIOF;
#endif
case G:
#ifdef GPIOG
return GPIOG;
#endif
case H:
#ifdef GPIOH
return GPIOH;
#endif
case I:
#ifdef GPIOI
return GPIOI;
#endif
case J:
#ifdef GPIOJ
return GPIOJ;
#endif
case K:
#ifdef GPIOK
return GPIOK;
#endif
default:
return RT_NULL;
}
}
static void GPIOB_CLK_ENABLE(void)
#define get_st_pin(gpio_pin) (0x01 << (gpio_pin&0xFF))
static void drv_clock_enable(rt_uint16_t gpio_pin)
{
#ifdef __HAL_RCC_GPIOB_CLK_ENABLE
switch(gpio_pin & 0xFF00)
{
case A:
#ifdef __HAL_RCC_GPIOA_CLK_ENABLE
__HAL_RCC_GPIOA_CLK_ENABLE();
#endif
break;
case B:
#ifdef __HAL_RCC_GPIOB_CLK_ENABLE
__HAL_RCC_GPIOB_CLK_ENABLE();
#endif
}
#if (STM32F10X_PIN_NUMBERS >36)
static void GPIOC_CLK_ENABLE(void)
{
#ifdef __HAL_RCC_GPIOC_CLK_ENABLE
#endif
break;
case C:
#ifdef __HAL_RCC_GPIOC_CLK_ENABLE
__HAL_RCC_GPIOC_CLK_ENABLE();
#endif
}
#if (STM32F10X_PIN_NUMBERS >48)
static void GPIOD_CLK_ENABLE(void)
{
#ifdef __HAL_RCC_GPIOD_CLK_ENABLE
#endif
break;
case D:
#ifdef __HAL_RCC_GPIOD_CLK_ENABLE
__HAL_RCC_GPIOD_CLK_ENABLE();
#endif
}
#if (STM32F10X_PIN_NUMBERS >64)
static void GPIOE_CLK_ENABLE(void)
{
#ifdef __HAL_RCC_GPIOE_CLK_ENABLE
#endif
break;
case E:
#ifdef __HAL_RCC_GPIOE_CLK_ENABLE
__HAL_RCC_GPIOE_CLK_ENABLE();
#endif
}
#if (STM32F10X_PIN_NUMBERS >100)
static void GPIOF_CLK_ENABLE(void)
{
#ifdef __HAL_RCC_GPIOF_CLK_ENABLE
#endif
break;
case F:
#ifdef __HAL_RCC_GPIOF_CLK_ENABLE
__HAL_RCC_GPIOF_CLK_ENABLE();
#endif
}
static void GPIOG_CLK_ENABLE(void)
{
#ifdef __HAL_RCC_GPIOG_CLK_ENABLE
#endif
break;
case G:
#ifdef __HAL_RCC_GPIOG_CLK_ENABLE
__HAL_RCC_GPIOG_CLK_ENABLE();
#endif
}
static void GPIOH_CLK_ENABLE(void)
{
#ifdef __HAL_RCC_GPIOH_CLK_ENABLE
#endif
break;
case H:
#ifdef __HAL_RCC_GPIOH_CLK_ENABLE
__HAL_RCC_GPIOH_CLK_ENABLE();
#endif
#endif
break;
case I:
#ifdef __HAL_RCC_GPIOI_CLK_ENABLE
__HAL_RCC_GPIOI_CLK_ENABLE();
#endif
break;
case J:
#ifdef __HAL_RCC_GPIOJ_CLK_ENABLE
__HAL_RCC_GPIOJ_CLK_ENABLE();
#endif
break;
case K:
#ifdef __HAL_RCC_GPIOK_CLK_ENABLE
__HAL_RCC_GPIOK_CLK_ENABLE();
#endif
break;
default:
break;
}
}
#endif
#endif
#endif
#endif
/* STM32 GPIO driver */
struct pin_index
{
int index;
void (*rcc)(void);
GPIO_TypeDef *gpio;
uint32_t pin;
};
static const struct pin_index pins[] =
/* STM32 GPIO driver */
static const rt_uint16_t pins[] =
{
#if (STM32F10X_PIN_NUMBERS == 36)
__STM32_PIN_DEFAULT,
......@@ -361,7 +427,6 @@ static const struct pin_index pins[] =
__STM32_PIN(7, C, 13),
__STM32_PIN(8, C, 14),
__STM32_PIN(9, C, 15),
__STM32_PIN(10, F, 0),
__STM32_PIN(11, F, 1),
__STM32_PIN(12, F, 2),
......@@ -545,74 +610,58 @@ struct rt_pin_irq_hdr pin_irq_hdr_tab[] =
};
#define ITEM_NUM(items) sizeof(items) / sizeof(items[0])
const struct pin_index *get_pin(uint8_t pin)
static rt_uint16_t get_pin(uint8_t pin)
{
const struct pin_index *index;
rt_uint16_t gpio_pin = __STM32_PIN_DEFAULT;
if (pin < ITEM_NUM(pins))
{
index = &pins[pin];
if (index->index == -1)
index = RT_NULL;
}
else
{
index = RT_NULL;
gpio_pin = pins[pin];
}
return index;
return gpio_pin;
};
void stm32_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
{
const struct pin_index *index;
index = get_pin(pin);
if (index == RT_NULL)
rt_uint16_t gpio_pin;
gpio_pin = get_pin(pin);
if (get_st_gpio(gpio_pin) == RT_NULL)
{
return;
}
HAL_GPIO_WritePin(index->gpio, index->pin, (GPIO_PinState)value);
HAL_GPIO_WritePin(get_st_gpio(gpio_pin), get_st_pin(gpio_pin), (GPIO_PinState)value);
}
int stm32_pin_read(rt_device_t dev, rt_base_t pin)
{
int value;
const struct pin_index *index;
value = PIN_LOW;
index = get_pin(pin);
if (index == RT_NULL)
rt_uint16_t gpio_pin;
gpio_pin = get_pin(pin);
if (get_st_gpio(gpio_pin) == RT_NULL)
{
return value;
return PIN_LOW;
}
value = HAL_GPIO_ReadPin(index->gpio, index->pin);
return value;
return HAL_GPIO_ReadPin(get_st_gpio(gpio_pin), get_st_pin(gpio_pin));
}
void stm32_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
{
const struct pin_index *index;
rt_uint16_t gpio_pin;
GPIO_InitTypeDef GPIO_InitStruct;
index = get_pin(pin);
if (index == RT_NULL)
gpio_pin = get_pin(pin);
if (get_st_gpio(gpio_pin) == RT_NULL)
{
return;
}
/* GPIO Periph clock enable */
index->rcc();
drv_clock_enable(gpio_pin);
/* Configure GPIO_InitStructure */
GPIO_InitStruct.Pin = index->pin;
GPIO_InitStruct.Pin = get_st_pin(gpio_pin);
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
if (mode == PIN_MODE_OUTPUT)
{
/* output setting */
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
}
else if (mode == PIN_MODE_INPUT)
if (mode == PIN_MODE_INPUT)
{
/* input setting: not pull. */
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
GPIO_InitStruct.Pull = GPIO_NOPULL;
}
else if (mode == PIN_MODE_INPUT_PULLUP)
{
......@@ -630,45 +679,32 @@ void stm32_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
{
/* output setting: od. */
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_OD;
GPIO_InitStruct.Pull = GPIO_NOPULL;
}
HAL_GPIO_Init(index->gpio, &GPIO_InitStruct);
}
rt_inline rt_int32_t bit2bitno(rt_uint32_t bit)
{
int i;
for (i = 0; i < 32; i++)
{
if ((0x01 << i) == bit)
{
return i;
}
}
return -1;
HAL_GPIO_Init(get_st_gpio(gpio_pin), &GPIO_InitStruct);
}
rt_inline const struct pin_irq_map *get_pin_irq_map(uint32_t pinbit)
rt_inline const struct pin_irq_map *get_pin_irq_map(rt_uint16_t gpio_pin)
{
rt_int32_t mapindex = bit2bitno(pinbit);
rt_int32_t mapindex = gpio_pin & 0x00FF;
if (mapindex < 0 || mapindex >= ITEM_NUM(pin_irq_map))
{
return RT_NULL;
}
return &pin_irq_map[mapindex];
};
rt_err_t stm32_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
rt_uint32_t mode, void (*hdr)(void *args), void *args)
{
const struct pin_index *index;
rt_uint16_t gpio_pin;
rt_base_t level;
rt_int32_t irqindex = -1;
index = get_pin(pin);
if (index == RT_NULL)
gpio_pin = get_pin(pin);
if (get_st_gpio(gpio_pin) == RT_NULL)
{
return RT_ENOSYS;
}
irqindex = bit2bitno(index->pin);
irqindex = gpio_pin & 0x00FF;
if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map))
{
return RT_ENOSYS;
......@@ -697,15 +733,15 @@ rt_err_t stm32_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
rt_err_t stm32_pin_detach_irq(struct rt_device *device, rt_int32_t pin)
{
const struct pin_index *index;
rt_uint16_t gpio_pin;
rt_base_t level;
rt_int32_t irqindex = -1;
index = get_pin(pin);
if (index == RT_NULL)
gpio_pin = get_pin(pin);
if (get_st_gpio(gpio_pin) == RT_NULL)
{
return RT_ENOSYS;
}
irqindex = bit2bitno(index->pin);
irqindex = gpio_pin & 0x00FF;
if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map))
{
return RT_ENOSYS;
......@@ -727,19 +763,19 @@ rt_err_t stm32_pin_detach_irq(struct rt_device *device, rt_int32_t pin)
rt_err_t stm32_pin_irq_enable(struct rt_device *device, rt_base_t pin,
rt_uint32_t enabled)
{
const struct pin_index *index;
rt_uint16_t gpio_pin;
const struct pin_irq_map *irqmap;
rt_base_t level;
rt_int32_t irqindex = -1;
GPIO_InitTypeDef GPIO_InitStruct;
index = get_pin(pin);
if (index == RT_NULL)
gpio_pin = get_pin(pin);
if (get_st_gpio(gpio_pin) == RT_NULL)
{
return RT_ENOSYS;
}
if (enabled == PIN_IRQ_ENABLE)
{
irqindex = bit2bitno(index->pin);
irqindex = gpio_pin & 0x00FF;
if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map))
{
return RT_ENOSYS;
......@@ -752,33 +788,31 @@ rt_err_t stm32_pin_irq_enable(struct rt_device *device, rt_base_t pin,
}
irqmap = &pin_irq_map[irqindex];
/* GPIO Periph clock enable */
index->rcc();
drv_clock_enable(gpio_pin);
/* Configure GPIO_InitStructure */
GPIO_InitStruct.Pin = index->pin;
GPIO_InitStruct.Pin = get_st_pin(gpio_pin);
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
switch (pin_irq_hdr_tab[irqindex].mode)
{
case PIN_IRQ_MODE_RISING:
GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING;
GPIO_InitStruct.Pull = GPIO_PULLDOWN;
break;
case PIN_IRQ_MODE_FALLING:
GPIO_InitStruct.Mode = GPIO_MODE_IT_FALLING;
GPIO_InitStruct.Pull = GPIO_PULLUP;
break;
case PIN_IRQ_MODE_RISING_FALLING:
GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING_FALLING;
GPIO_InitStruct.Pull = GPIO_NOPULL;
break;
}
HAL_GPIO_Init(index->gpio, &GPIO_InitStruct);
HAL_GPIO_Init(get_st_gpio(gpio_pin), &GPIO_InitStruct);
HAL_NVIC_SetPriority(irqmap->irqno, 5, 0);
HAL_NVIC_EnableIRQ(irqmap->irqno);
rt_hw_interrupt_enable(level);
}
else if (enabled == PIN_IRQ_DISABLE)
{
irqmap = get_pin_irq_map(index->pin);
irqmap = get_pin_irq_map(gpio_pin);
if (irqmap == RT_NULL)
{
return RT_ENOSYS;
......@@ -810,8 +844,18 @@ int rt_hw_pin_init(void)
}
INIT_BOARD_EXPORT(rt_hw_pin_init);
rt_inline void pin_irq_hdr(int irqno)
rt_inline void pin_irq_hdr(uint16_t GPIO_Pin)
{
uint16_t irqno;
for (irqno = 0; irqno < 16; irqno++)
{
if ((0x01 << irqno) == GPIO_Pin)
{
break;
}
}
if (irqno == 16)
return;
if (pin_irq_hdr_tab[irqno].hdr)
{
pin_irq_hdr_tab[irqno].hdr(pin_irq_hdr_tab[irqno].args);
......@@ -820,7 +864,7 @@ rt_inline void pin_irq_hdr(int irqno)
void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)
{
pin_irq_hdr(bit2bitno(GPIO_Pin));
pin_irq_hdr(GPIO_Pin);
}
void EXTI0_IRQHandler(void)
......
bsp/stm32f10x-HAL/drivers/drv_gpio.h
浏览文件 @ 5c420c0c
......@@ -12,14 +12,7 @@
* 2015-01-05 Bernard the first version
* 2017-11-35 ZYH update to 3.0.0
*/
#ifndef GPIO_H__
#define GPIO_H__
struct stm32_hw_pin_userdata
{
int pin;
uint32_t mode;
};
#define PIN_USERDATA_END {-1,0}
extern struct stm32_hw_pin_userdata stm32_pins[];
int rt_hw_pin_init(void);
#ifndef __DRV_GPIO_H__
#define __DRV_GPIO_H__
extern int rt_hw_pin_init(void);
#endif
bsp/stm32f10x-HAL/drivers/stm32f1xx_hal_conf.h
浏览文件 @ 5c420c0c
......@@ -103,7 +103,11 @@ extern "C" {
* This value is used by the RCC HAL module to compute the system frequency
* (when HSE is used as system clock source, directly or through the PLL).
*/
#if !defined(RT_USING_HSI)
#define HSE_VALUE ((unsigned int)RT_HSE_VALUE)
#endif
//#define HSE_VALUE ((unsigned int)RT_HSE_VALUE)
#if !defined (HSE_VALUE)
#if defined(USE_STM3210C_EVAL)
......
bsp/stm32f4xx-HAL/Kconfig
浏览文件 @ 5c420c0c
......@@ -286,6 +286,10 @@ endchoice
config RT_USING_HSI
bool "Using HSI as clock source"
default n
config BSP_HSE_BY_PASS
bool "HES Bypass"
depends on !RT_USING_HSI
default n
config RT_HSE_VALUE
int "HSE Value"
default 8000000
......@@ -321,12 +325,12 @@ config RT_USING_SPI3
endif
if RT_USING_W25QXX
config RT_W25QXX_CS_PIN
int "W25QXX CS Pin index"
if RT_USING_W25QXX || RT_USING_SFUD
config RT_FLASH_CS_PIN
int "SPI NOR Flash CS pin index"
default 0
config RT_W25QXX_SPI_BUS_NAME
string "W25QXX Spi bus name"
config RT_FLASH_SPI_BUS_NAME
string "SPI NOR Flash Spi bus name"
default "spi1"
endif
......
bsp/stm32f4xx-HAL/drivers/SConscript
浏览文件 @ 5c420c0c
......@@ -19,7 +19,7 @@ if GetDepend(['RT_USING_SERIAL']):
if GetDepend(['RT_USING_SPI']):
src += ['drv_spi.c']
if GetDepend(['RT_USING_W25QXX']):
if GetDepend(['RT_USING_W25QXX']) or GetDepend(['RT_USING_SFUD']):
src += ['drv_spiflash.c']
if GetDepend(['RT_USING_WDT']):
......
bsp/stm32f4xx-HAL/drivers/board.c
浏览文件 @ 5c420c0c
......@@ -50,7 +50,11 @@ static void SystemClock_Config(void)
RCC_OscInitStruct.OscillatorType |= RCC_OSCILLATORTYPE_LSI;
RCC_OscInitStruct.LSIState = RCC_LSI_ON;
#endif
#ifdef BSP_HSE_BY_PASS
RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS;
#elif !defined(RT_USING_HSI)
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
#endif
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
if (hse_clk % 2 == 0)
......
bsp/stm32f4xx-HAL/drivers/drv_spiflash.c
浏览文件 @ 5c420c0c
......@@ -12,13 +12,32 @@
* 2017-11-08 ZYH the first version
*/
#include <rtthread.h>
#if defined(RT_USING_W25QXX) || defined(RT_USING_SFUD)
#include <drv_spi.h>
#ifdef RT_USING_W25QXX
#include <drv_spi.h>
#include "spi_flash_w25qxx.h"
int rt_w25qxx_init(void)
#include "spi_flash_w25qxx.h"
#elif defined(RT_USING_SFUD)
#include "string.h"
#include "spi_flash.h"
#include "spi_flash_sfud.h"
sfud_flash sfud_norflash0;
rt_spi_flash_device_t spi_device;
#endif
int rt_nor_flash_init(void)
{
stm32_spi_bus_attach_device(RT_W25QXX_CS_PIN, RT_W25QXX_SPI_BUS_NAME, "w25qxx");
return w25qxx_init("flash0", "w25qxx");
stm32_spi_bus_attach_device(RT_FLASH_CS_PIN, RT_FLASH_SPI_BUS_NAME, "norspi");
#ifdef RT_USING_W25QXX
return w25qxx_init("flash0", "norspi");
#elif defined(RT_USING_SFUD)
spi_device = rt_sfud_flash_probe("flash0", "norspi");
if (spi_device == RT_NULL)
{
return -RT_ERROR;
}
memcpy(&sfud_norflash0, spi_device->user_data, sizeof(sfud_flash));
return 0;
#endif
}
INIT_DEVICE_EXPORT(rt_w25qxx_init);
INIT_DEVICE_EXPORT(rt_nor_flash_init);
#endif
bsp/tm4c129x-dk/.config 0 → 100644
浏览文件 @ 5c420c0c
#
# Automatically generated file; DO NOT EDIT.
# RT-Thread Configuration
#
#
# RT-Thread Kernel
#
CONFIG_RT_NAME_MAX=8
CONFIG_RT_ALIGN_SIZE=4
CONFIG_RT_THREAD_PRIORITY_MAX=32
CONFIG_RT_TICK_PER_SECOND=100
CONFIG_RT_DEBUG=y
CONFIG_RT_USING_OVERFLOW_CHECK=y
CONFIG_RT_DEBUG_INIT=0
# CONFIG_RT_DEBUG_THREAD is not set
CONFIG_RT_USING_HOOK=y
CONFIG_IDLE_THREAD_STACK_SIZE=256
CONFIG_RT_USING_TIMER_SOFT=y
CONFIG_RT_TIMER_THREAD_PRIO=4
CONFIG_RT_TIMER_THREAD_STACK_SIZE=512
#
# Inter-Thread communication
#
CONFIG_RT_USING_SEMAPHORE=y
CONFIG_RT_USING_MUTEX=y
CONFIG_RT_USING_EVENT=y
CONFIG_RT_USING_MAILBOX=y
CONFIG_RT_USING_MESSAGEQUEUE=y
# CONFIG_RT_USING_SIGNALS is not set
#
# Memory Management
#
CONFIG_RT_USING_MEMPOOL=y
CONFIG_RT_USING_MEMHEAP=y
CONFIG_RT_USING_HEAP=y
CONFIG_RT_USING_SMALL_MEM=y
# CONFIG_RT_USING_SLAB is not set
#
# Kernel Device Object
#
CONFIG_RT_USING_DEVICE=y
CONFIG_RT_USING_CONSOLE=y
CONFIG_RT_CONSOLEBUF_SIZE=128
CONFIG_RT_CONSOLE_DEVICE_NAME="uart0"
# CONFIG_RT_USING_MODULE is not set
#
# RT-Thread Components
#
CONFIG_RT_USING_COMPONENTS_INIT=y
CONFIG_RT_USING_USER_MAIN=y
#
# C++ features
#
# CONFIG_RT_USING_CPLUSPLUS is not set
#
# Command shell
#
CONFIG_RT_USING_FINSH=y
CONFIG_FINSH_USING_HISTORY=y
CONFIG_FINSH_USING_SYMTAB=y
CONFIG_FINSH_USING_DESCRIPTION=y
CONFIG_FINSH_THREAD_PRIORITY=20
CONFIG_FINSH_THREAD_STACK_SIZE=4096
CONFIG_FINSH_CMD_SIZE=80
# CONFIG_FINSH_USING_AUTH is not set
# CONFIG_FINSH_USING_MSH is not set
#
# Device virtual file system
#
# CONFIG_RT_USING_DFS is not set
#
# Device Drivers
#
CONFIG_RT_USING_DEVICE_IPC=y
CONFIG_RT_USING_SERIAL=y
# CONFIG_RT_USING_CAN is not set
# CONFIG_RT_USING_HWTIMER is not set
# CONFIG_RT_USING_I2C is not set
# CONFIG_RT_USING_PIN is not set
# CONFIG_RT_USING_MTD_NOR is not set
# CONFIG_RT_USING_MTD_NAND is not set
# CONFIG_RT_USING_RTC is not set
# CONFIG_RT_USING_SDIO is not set
# CONFIG_RT_USING_SPI is not set
# CONFIG_RT_USING_WDT is not set
# CONFIG_RT_USING_USB_HOST is not set
# CONFIG_RT_USING_USB_DEVICE is not set
#
# POSIX layer and C standard library
#
# CONFIG_RT_USING_LIBC is not set
# CONFIG_RT_USING_PTHREADS is not set
#
# Network stack
#
#
# light weight TCP/IP stack
#
CONFIG_RT_USING_LWIP=y
CONFIG_RT_USING_LWIP141=y
# CONFIG_RT_USING_LWIP202 is not set
# CONFIG_RT_LWIP_IGMP is not set
CONFIG_RT_LWIP_ICMP=y
# CONFIG_RT_LWIP_SNMP is not set
CONFIG_RT_LWIP_DNS=y
CONFIG_RT_LWIP_DHCP=y
CONFIG_IP_SOF_BROADCAST=1
CONFIG_IP_SOF_BROADCAST_RECV=1
# CONFIG_LWIP_USING_DHCPD is not set
#
# Static IPv4 Address
#
CONFIG_RT_LWIP_IPADDR="192.168.1.30"
CONFIG_RT_LWIP_GWADDR="192.168.1.1"
CONFIG_RT_LWIP_MSKADDR="255.255.255.0"
CONFIG_RT_LWIP_UDP=y
CONFIG_RT_LWIP_TCP=y
# CONFIG_RT_LWIP_RAW is not set
# CONFIG_RT_LWIP_PPP is not set
# CONFIG_RT_LWIP_PPPOE is not set
# CONFIG_RT_LWIP_PPPOS is not set
CONFIG_RT_LWIP_PBUF_NUM=16
CONFIG_RT_LWIP_RAW_PCB_NUM=4
CONFIG_RT_LWIP_UDP_PCB_NUM=4
CONFIG_RT_LWIP_TCP_PCB_NUM=4
CONFIG_RT_LWIP_TCP_SEG_NUM=40
CONFIG_RT_LWIP_TCP_SND_BUF=8196
CONFIG_RT_LWIP_TCP_WND=8196
CONFIG_RT_LWIP_TCPTHREAD_PRIORITY=10
CONFIG_RT_LWIP_TCPTHREAD_MBOX_SIZE=8
CONFIG_RT_LWIP_TCPTHREAD_STACKSIZE=1024
CONFIG_RT_LWIP_ETHTHREAD_PRIORITY=12
CONFIG_RT_LWIP_ETHTHREAD_STACKSIZE=1024
CONFIG_RT_LWIP_ETHTHREAD_MBOX_SIZE=8
# CONFIG_RT_LWIP_REASSEMBLY_FRAG is not set
CONFIG_LWIP_NETIF_STATUS_CALLBACK=1
CONFIG_SO_REUSE=1
CONFIG_LWIP_SO_RCVTIMEO=1
CONFIG_LWIP_SO_SNDTIMEO=1
CONFIG_LWIP_SO_RCVBUF=1
#
# Modbus master and slave stack
#
# CONFIG_RT_USING_MODBUS is not set
# CONFIG_RT_USING_NETUTILS is not set
#
# RT-Thread UI Engine
#
# CONFIG_PKG_USING_GUIENGINE is not set
#
# RT-Thread online packages
#
#
# system packages
#
# CONFIG_PKG_USING_PARTITION is not set
# CONFIG_PKG_USING_SQLITE is not set
#
# IoT - internet of things
#
# CONFIG_PKG_USING_PAHOMQTT is not set
# CONFIG_PKG_USING_WEBCLIENT is not set
# CONFIG_PKG_USING_MONGOOSE is not set
# CONFIG_PKG_USING_WEBTERMINAL is not set
# CONFIG_PKG_USING_CJSON is not set
# CONFIG_PKG_USING_EZXML is not set
#
# Marvell WiFi
#
# CONFIG_PKG_USING_MARVELLWIFI is not set
#
# security packages
#
# CONFIG_PKG_USING_MBEDTLS is not set
#
# language packages
#
# CONFIG_PKG_USING_JERRYSCRIPT is not set
#
# multimedia packages
#
#
# tools packages
#
# CONFIG_PKG_USING_CMBACKTRACE is not set
# CONFIG_PKG_USING_EASYLOGGER is not set
#
# miscellaneous packages
#
# CONFIG_PKG_USING_HELLO is not set
#
# BSP_SPECIAL CONFIG
#
CONFIG_RT_USING_UART0=y
bsp/tm4c129x-dk/Kconfig 0 → 100644
浏览文件 @ 5c420c0c
mainmenu "RT-Thread Configuration"
config $BSP_DIR
string
option env="BSP_ROOT"
default "."
config $RTT_DIR
string
option env="RTT_ROOT"
default "../.."
config $PKGS_DIR
string
option env="PKGS_ROOT"
default "packages"
source "$RTT_DIR/Kconfig"
source "$PKGS_DIR/Kconfig"
config RT_USING_UART0
bool "Using RT_USING_UART0"
default y
bsp/tm4c129x-dk/README.md 0 → 100644
浏览文件 @ 5c420c0c
# TM4C129X-Development Board
http://www.ti.com/tool/dk-tm4c129x
## 1. 简介
TM4C129X-DK是TI官方的开发板，此为其中一款开发板，带屏幕，配置更高。
TI官方提供了详细的SDK支持，含USB，LWIP，甚至图形库。
核心板板载主要资源如下：
| 硬件 | 描述 |
| -- | -- |
|芯片型号| TM4C129XNCZAD |
|CPU| ARM Cortex-M4F |
|主频| 120MHz |
|片内Flash| 1024B |
|片内SRAM| 256KB |
## 2. 编译说明
TM4C129X-DK板级包目前仅支持MDK5编译器，以下是具体版本信息：
| IDE/编译器 | 已测试版本 |
| ---------- | ---------------------------- |
| MDK5 | MDK521a |
## 3. 烧写及执行
TM4C129X-DK本身提供了一个烧录接口，是Stellaris ICDI，keil本身不提供该驱动，需自行下载。
http://www.ti.com.cn/tool/cn/stellaris_icdi_drivers
供电方式：使用ICDI接口即可供电
### 3.1 运行结果
如果编译 & 烧写无误，当复位设备后，会在串口上看到RT-Thread的启动logo信息：
```bash
\ | /
- RT - Thread Operating System
/ | \ 3.0.3 build Feb 28 2018
2006 - 2018 Copyright by rt-thread team
finsh />
```
## 4. 驱动支持情况及计划
| 驱动 | 支持情况 | 备注 |
| ------ | ---- | :------: |
### 4.1 IO在板级支持包中的映射情况
| IO号 | 板级包中的定义 |
| -- | -- |
## 5. 联系人信息
维护人：[zero](https://github.com/Zero-Sky)
## 6. 参考
bsp/tm4c129x-dk/SConscript 0 → 100644
浏览文件 @ 5c420c0c
# for module compiling
import os
Import('RTT_ROOT')
cwd = str(Dir('#'))
objs = []
list = os.listdir(cwd)
for d in list:
path = os.path.join(cwd, d)
if os.path.isfile(os.path.join(path, 'SConscript')):
objs = objs + SConscript(os.path.join(d, 'SConscript'))
Return('objs')
bsp/tm4c129x-dk/SConstruct 0 → 100644
浏览文件 @ 5c420c0c
import os
import sys
import rtconfig
if os.getenv('RTT_ROOT'):
RTT_ROOT = os.getenv('RTT_ROOT')
else:
RTT_ROOT = os.path.normpath(os.getcwd() + '/../..')
sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
from building import *
TARGET = 'rtthread.' + rtconfig.TARGET_EXT
env = Environment(tools = ['mingw'],
AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
AR = rtconfig.AR, ARFLAGS = '-rc',
LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
Export('RTT_ROOT')
Export('rtconfig')
# prepare building environment
objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
# make a building
DoBuilding(TARGET, objs)
bsp/tm4c129x-dk/applications/SConscript 0 → 100644
浏览文件 @ 5c420c0c
Import('RTT_ROOT')
Import('rtconfig')
from building import *
cwd = os.path.join(str(Dir('#')), 'applications')
src = Glob('*.c')
CPPPATH = [cwd, str(Dir('#'))]
group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
Return('group')
bsp/tm4c129x-dk/applications/application.c 0 → 100644
浏览文件 @ 5c420c0c
/*
* File : application.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2014, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2014-07-18 ArdaFu the first version for TM4C129X
*/
#include <rtthread.h>
int main(void)
{
/* user app entry */
}
bsp/tm4c129x-dk/applications/board.c 0 → 100644
浏览文件 @ 5c420c0c
/*
* File : board.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2013 RT-Thread Develop Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2009-01-05 Bernard first implementation
* 2014-07-18 ArdaFu Port to TM4C129X
*/
#include <rthw.h>
#include <rtthread.h>
#include "board.h"
#include "driverlib/interrupt.h"
#include "driverlib/sysctl.h"
#include "driverlib/systick.h"
#include "driverlib/fpu.h"
#include "driverlib/rom_map.h"
#define SYS_CLOCK_DEFAULT 120000000
uint32_t SystemCoreClock;
#define FAULT_NMI 2 // NMI fault
#define FAULT_HARD 3 // Hard fault
#define FAULT_MPU 4 // MPU fault
#define FAULT_BUS 5 // Bus fault
#define FAULT_USAGE 6 // Usage fault
#define FAULT_SVCALL 11 // SVCall
#define FAULT_DEBUG 12 // Debug monitor
#define FAULT_PENDSV 14 // PendSV
#define FAULT_SYSTICK 15 // System Tick
/**
* This is the timer interrupt service routine.
*
*/
void SysTick_Handler(void)
{
/* enter interrupt */
rt_interrupt_enter();
rt_tick_increase();
/* leave interrupt */
rt_interrupt_leave();
}
extern void PendSV_Handler(void);
extern void HardFault_Handler(void);
/**
* This function will initial LPC40xx board.
*/
void rt_hw_board_init()
{
//init low level drivers. e.g. cpu uart etc.
rt_components_board_init();
//redirect RTT stdio to CONSOLE device
rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
}
int rt_hw_cpu_init(void)
{
MAP_IntMasterDisable();
IntRegister(FAULT_HARD, HardFault_Handler);
IntRegister(FAULT_PENDSV, PendSV_Handler);
IntRegister(FAULT_SYSTICK, SysTick_Handler);
// Enable lazy stacking for interrupt handlers. This allows floating-point
// instructions to be used within interrupt handlers, but at the expense of
// extra stack usage.
MAP_FPULazyStackingEnable();
// Set the clocking to run directly from the external crystal/oscillator.
// TODO: The SYSCTL_XTAL_ value must be changed to match the value of the
// crystal on your board.
SystemCoreClock = MAP_SysCtlClockFreqSet(
(SYSCTL_XTAL_25MHZ | SYSCTL_OSC_MAIN | SYSCTL_USE_PLL | SYSCTL_CFG_VCO_480),
SYS_CLOCK_DEFAULT);
MAP_SysTickDisable();
MAP_SysTickPeriodSet(SystemCoreClock/ RT_TICK_PER_SECOND - 1);
MAP_SysTickIntEnable();
MAP_SysTickEnable();
return 0;
}
// rt_hw_cpu_init should be run before any other INIT_BOARD_EXPORT
// We use INIT_EXPORT here and set the sequence index to "0.xxxx"
INIT_EXPORT(rt_hw_cpu_init, "0.post");
bsp/tm4c129x-dk/applications/board.h 0 → 100644
浏览文件 @ 5c420c0c
/*
* File : board.h
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2009, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2009-09-22 Bernard add board.h to this bsp
* 2010-02-04 Magicoe add board.h to LPC176x bsp
* 2014-07-18 ArdaFu port it to TM4C129X bsp
*/
#ifndef __BOARD_H__
#define __BOARD_H__
#include "tm4c1294ncpdt.h"
#include <rtthread.h>
#include <stdbool.h>
#include <stdint.h>
extern uint32_t SystemCoreClock;
#ifdef __CC_ARM
extern int Image$$RW_IRAM$$ZI$$Limit;
#define HEAP_BEGIN ((void *)&Image$$RW_IRAM$$ZI$$Limit)
#elif __ICCARM__
#pragma section="HEAP"
#define HEAP_BEGIN (__segment_end("HEAP"))
#else
extern int _ebss;
#define HEAP_BEGIN ((void *)&_ebss)
#endif
#define HEAP_END (0x20000000 + 256*1024)
#define FINSH_DEVICE_NAME RT_CONSOLE_DEVICE_NAME
void rt_hw_board_init(void);
#endif
bsp/tm4c129x-dk/context_rvds.lst 0 → 100644
浏览文件 @ 5c420c0c
此差异已折叠。
bsp/tm4c129x-dk/drivers/SConscript 0 → 100644
浏览文件 @ 5c420c0c
from building import *
cwd = GetCurrentDir()
src = Glob('*.c')
# remove no need file.
if GetDepend('RT_USING_LWIP') == False:
SrcRemove(src, 'drv_emac.c')
CPPPATH = [cwd]
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
Return('group')
bsp/tm4c129x-dk/drivers/drv_eth.c 0 → 100644
浏览文件 @ 5c420c0c
此差异已折叠。
bsp/tm4c129x-dk/drivers/drv_eth.h 0 → 100644
浏览文件 @ 5c420c0c
/*
* File : drv_eth.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2009-2013 RT-Thread Develop Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2014-07-25 ArdaFu Port to TM4C129X
*/
#ifndef __TIVA_ETH_H__
#define __TIVA_ETH_H__
int rt_hw_tiva_eth_init(void);
#endif
bsp/tm4c129x-dk/drivers/drv_uart.c 0 → 100644
浏览文件 @ 5c420c0c
/*
* File : drv_uart.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2009-2013 RT-Thread Develop Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2013-05-18 Bernard The first version for LPC40xx
* 2014-07-18 ArdaFu Port to TM4C129X
*/
#include <rthw.h>
#include <rtthread.h>
#include <rtdevice.h>
#include "board.h"
#include "inc/hw_memmap.h"
#include "driverlib/sysctl.h"
#include "driverlib/gpio.h"
#include "driverlib/uart.h"
#include "driverlib/pin_map.h"
#include "driverlib/interrupt.h"
#include "driverlib/rom_map.h"
typedef struct hw_uart_device
{
uint32_t hw_base; // base address
}hw_uart_t;
#define mUartGetHwPtr(serial) ((hw_uart_t*)(serial->parent.user_data))
static rt_err_t hw_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
{
uint32_t config = 0;
hw_uart_t* uart;
RT_ASSERT(serial != RT_NULL);
uart = mUartGetHwPtr(serial);
MAP_UARTDisable(uart->hw_base);
// build UART Configuration parameter structure
switch(cfg->data_bits)
{
case DATA_BITS_9:
// enable 9bit address mode and set DATA_BIT_8
MAP_UART9BitEnable(uart->hw_base);
case DATA_BITS_8:
config |= UART_CONFIG_WLEN_8;
break;
case DATA_BITS_7:
config |= UART_CONFIG_WLEN_7;
break;
case DATA_BITS_6:
config |= UART_CONFIG_WLEN_6;
break;
case DATA_BITS_5:
config |= UART_CONFIG_WLEN_5;
break;
default:
RT_ASSERT(0);
break;
}
switch(cfg->parity)
{
case PARITY_ODD:
config |= UART_CONFIG_PAR_ODD;
break;
case PARITY_EVEN:
config |= UART_CONFIG_PAR_EVEN;
break;
case PARITY_NONE:
config |= UART_CONFIG_PAR_NONE;
break;
default:
RT_ASSERT(0);
break;
}
switch(cfg->stop_bits)
{
case STOP_BITS_1:
config |= UART_CONFIG_STOP_ONE;
break;
case STOP_BITS_2:
config |= UART_CONFIG_STOP_TWO;
break;
default:
RT_ASSERT(0);
break;
}
// Initialize UART0 peripheral with given to corresponding parameter
MAP_UARTConfigSetExpClk(uart->hw_base, SystemCoreClock, cfg->baud_rate, config);
MAP_UARTFIFOEnable(uart->hw_base);
// Enable the UART.
MAP_UARTEnable(uart->hw_base);
return RT_EOK;
}
static rt_err_t hw_control(struct rt_serial_device *serial, int cmd, void *arg)
{
hw_uart_t* uart;
RT_ASSERT(serial != RT_NULL);
uart = mUartGetHwPtr(serial);
switch (cmd)
{
case RT_DEVICE_CTRL_CLR_INT:
/* disable rx irq */
MAP_UARTIntDisable(uart->hw_base, UART_INT_RX | UART_INT_RT);
break;
case RT_DEVICE_CTRL_SET_INT:
/* enable rx irq */
MAP_UARTIntEnable(uart->hw_base, UART_INT_RX | UART_INT_RT);
break;
}
return RT_EOK;
}
static int hw_putc(struct rt_serial_device *serial, char c)
{
hw_uart_t* uart;
RT_ASSERT(serial != RT_NULL);
uart = mUartGetHwPtr(serial);
MAP_UARTCharPut(uart->hw_base, *((uint8_t *)&c));
return 1;
}
static int hw_getc(struct rt_serial_device *serial)
{
hw_uart_t* uart;
RT_ASSERT(serial != RT_NULL);
uart = mUartGetHwPtr(serial);
return MAP_UARTCharGetNonBlocking(uart->hw_base);
}
static const struct rt_uart_ops hw_uart_ops =
{
hw_configure,
hw_control,
hw_putc,
hw_getc,
};
#if defined(RT_USING_UART0)
/* UART0 device driver structure */
struct rt_serial_device serial0;
hw_uart_t uart0 =
{
UART0_BASE,
};
void UART0_IRQHandler(void)
{
uint32_t intsrc;
hw_uart_t *uart = &uart0;
/* enter interrupt */
rt_interrupt_enter();
/* Determine the interrupt source */
intsrc = MAP_UARTIntStatus(uart->hw_base, true);
// Receive Data Available or Character time-out
if (intsrc & (UART_INT_RX | UART_INT_RT))
{
MAP_UARTIntClear(uart->hw_base, intsrc);
rt_hw_serial_isr(&serial0, RT_SERIAL_EVENT_RX_IND);
}
/* leave interrupt */
rt_interrupt_leave();
}
#endif
int rt_hw_uart_init(void)
{
hw_uart_t* uart;
struct serial_configure config;
config.baud_rate = BAUD_RATE_115200;
config.bit_order = BIT_ORDER_LSB;
config.data_bits = DATA_BITS_8;
config.parity = PARITY_NONE;
config.stop_bits = STOP_BITS_1;
config.invert = NRZ_NORMAL;
config.bufsz = RT_SERIAL_RB_BUFSZ;
#ifdef RT_USING_UART0
uart = &uart0;
serial0.ops = &hw_uart_ops;
serial0.config = config;
MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA);
MAP_GPIOPinConfigure(GPIO_PA0_U0RX);
MAP_GPIOPinConfigure(GPIO_PA1_U0TX);
MAP_GPIOPinTypeUART(GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1);
MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0);
/* preemption = 1, sub-priority = 1 */
//IntPrioritySet(INT_UART0, ((0x01 << 5) | 0x01));
/* Enable Interrupt for UART channel */
UARTIntRegister(uart->hw_base, UART0_IRQHandler);
MAP_IntEnable(INT_UART0);
MAP_UARTEnable(uart->hw_base);
/* register UART0 device */
rt_hw_serial_register(&serial0, "uart0",
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
uart);
#endif
return 0;
}
INIT_BOARD_EXPORT(rt_hw_uart_init);
bsp/tm4c129x-dk/drivers/drv_uart.h 0 → 100644
浏览文件 @ 5c420c0c
/*
* File : drv_uart.h
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2009-2013 RT-Thread Develop Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2013-05-18 Bernard The first version for LPC40xx
* 2014-07-18 ArdaFu Port to TM4C129X
*/
#ifndef __UART_H__
#define __UART_H__
void rt_hw_uart_init(void);
#endif
bsp/tm4c129x-dk/libraries/SConscript 0 → 100644
浏览文件 @ 5c420c0c
Import('RTT_ROOT')
Import('rtconfig')
from building import *
# The set of source files associated with this SConscript file.
cwd = GetCurrentDir()
src = Glob('driverlib/*.c')
SrcRemove(src, 'onewire.c')
CCFLAGS = ''
# add for startup script
if rtconfig.CROSS_TOOL == 'gcc':
src += ['startup/startup_gcc.c']
elif rtconfig.CROSS_TOOL == 'keil':
src += ['startup/startup_rvmdk.S']
elif rtconfig.CROSS_TOOL == 'iar':
src += ['startup/startup_ewarm.c']
CCFLAGS += ' --diag_suppress=pe177'
CPPPATH = [cwd, cwd + '/inc', cwd + '/driverlib']
CPPDEFINES = [rtconfig.PART_TYPE]
group = DefineGroup('Libraries', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES, CCFLAGS = CCFLAGS)
Return('group')
bsp/tm4c129x-dk/libraries/driverlib/adc.c 0 → 100644
浏览文件 @ 5c420c0c
此差异已折叠。
bsp/tm4c129x-dk/libraries/driverlib/adc.h 0 → 100644
浏览文件 @ 5c420c0c
//*****************************************************************************
//
// adc.h - ADC headers for using the ADC driver functions.
//
// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __DRIVERLIB_ADC_H__
#define __DRIVERLIB_ADC_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Values that can be passed to ADCSequenceConfigure as the ui32Trigger
// parameter.
//
//*****************************************************************************
#define ADC_TRIGGER_PROCESSOR 0x00000000 // Processor event
#define ADC_TRIGGER_COMP0 0x00000001 // Analog comparator 0 event
#define ADC_TRIGGER_COMP1 0x00000002 // Analog comparator 1 event
#define ADC_TRIGGER_COMP2 0x00000003 // Analog comparator 2 event
#define ADC_TRIGGER_EXTERNAL 0x00000004 // External event
#define ADC_TRIGGER_TIMER 0x00000005 // Timer event
#define ADC_TRIGGER_PWM0 0x00000006 // PWM0 event
#define ADC_TRIGGER_PWM1 0x00000007 // PWM1 event
#define ADC_TRIGGER_PWM2 0x00000008 // PWM2 event
#define ADC_TRIGGER_PWM3 0x00000009 // PWM3 event
#define ADC_TRIGGER_NEVER 0x0000000E // Never Trigger
#define ADC_TRIGGER_ALWAYS 0x0000000F // Always event
#define ADC_TRIGGER_PWM_MOD0 0x00000000 // PWM triggers from PWM0
#define ADC_TRIGGER_PWM_MOD1 0x00000010 // PWM triggers from PWM1
//*****************************************************************************
//
// Values that can be passed to ADCSequenceStepConfigure as the ui32Config
// parameter.
//
//*****************************************************************************
#define ADC_CTL_TS 0x00000080 // Temperature sensor select
#define ADC_CTL_IE 0x00000040 // Interrupt enable
#define ADC_CTL_END 0x00000020 // Sequence end select
#define ADC_CTL_D 0x00000010 // Differential select
#define ADC_CTL_CH0 0x00000000 // Input channel 0
#define ADC_CTL_CH1 0x00000001 // Input channel 1
#define ADC_CTL_CH2 0x00000002 // Input channel 2
#define ADC_CTL_CH3 0x00000003 // Input channel 3
#define ADC_CTL_CH4 0x00000004 // Input channel 4
#define ADC_CTL_CH5 0x00000005 // Input channel 5
#define ADC_CTL_CH6 0x00000006 // Input channel 6
#define ADC_CTL_CH7 0x00000007 // Input channel 7
#define ADC_CTL_CH8 0x00000008 // Input channel 8
#define ADC_CTL_CH9 0x00000009 // Input channel 9
#define ADC_CTL_CH10 0x0000000A // Input channel 10
#define ADC_CTL_CH11 0x0000000B // Input channel 11
#define ADC_CTL_CH12 0x0000000C // Input channel 12
#define ADC_CTL_CH13 0x0000000D // Input channel 13
#define ADC_CTL_CH14 0x0000000E // Input channel 14
#define ADC_CTL_CH15 0x0000000F // Input channel 15
#define ADC_CTL_CH16 0x00000100 // Input channel 16
#define ADC_CTL_CH17 0x00000101 // Input channel 17
#define ADC_CTL_CH18 0x00000102 // Input channel 18
#define ADC_CTL_CH19 0x00000103 // Input channel 19
#define ADC_CTL_CH20 0x00000104 // Input channel 20
#define ADC_CTL_CH21 0x00000105 // Input channel 21
#define ADC_CTL_CH22 0x00000106 // Input channel 22
#define ADC_CTL_CH23 0x00000107 // Input channel 23
#define ADC_CTL_CMP0 0x00080000 // Select Comparator 0
#define ADC_CTL_CMP1 0x00090000 // Select Comparator 1
#define ADC_CTL_CMP2 0x000A0000 // Select Comparator 2
#define ADC_CTL_CMP3 0x000B0000 // Select Comparator 3
#define ADC_CTL_CMP4 0x000C0000 // Select Comparator 4
#define ADC_CTL_CMP5 0x000D0000 // Select Comparator 5
#define ADC_CTL_CMP6 0x000E0000 // Select Comparator 6
#define ADC_CTL_CMP7 0x000F0000 // Select Comparator 7
#define ADC_CTL_SHOLD_4 0x00000000 // Sample and hold 4 ADC clocks
#define ADC_CTL_SHOLD_8 0x00200000 // Sample and hold 8 ADC clocks
#define ADC_CTL_SHOLD_16 0x00400000 // Sample and hold 16 ADC clocks
#define ADC_CTL_SHOLD_32 0x00600000 // Sample and hold 32 ADC clocks
#define ADC_CTL_SHOLD_64 0x00800000 // Sample and hold 64 ADC clocks
#define ADC_CTL_SHOLD_128 0x00A00000 // Sample and hold 128 ADC clocks
#define ADC_CTL_SHOLD_256 0x00C00000 // Sample and hold 256 ADC clocks
//*****************************************************************************
//
// Values that can be passed to ADCComparatorConfigure as part of the
// ui32Config parameter.
//
//*****************************************************************************
#define ADC_COMP_TRIG_NONE 0x00000000 // Trigger Disabled
#define ADC_COMP_TRIG_LOW_ALWAYS \
0x00001000 // Trigger Low Always
#define ADC_COMP_TRIG_LOW_ONCE 0x00001100 // Trigger Low Once
#define ADC_COMP_TRIG_LOW_HALWAYS \
0x00001200 // Trigger Low Always (Hysteresis)
#define ADC_COMP_TRIG_LOW_HONCE 0x00001300 // Trigger Low Once (Hysteresis)
#define ADC_COMP_TRIG_MID_ALWAYS \
0x00001400 // Trigger Mid Always
#define ADC_COMP_TRIG_MID_ONCE 0x00001500 // Trigger Mid Once
#define ADC_COMP_TRIG_HIGH_ALWAYS \
0x00001C00 // Trigger High Always
#define ADC_COMP_TRIG_HIGH_ONCE 0x00001D00 // Trigger High Once
#define ADC_COMP_TRIG_HIGH_HALWAYS \
0x00001E00 // Trigger High Always (Hysteresis)
#define ADC_COMP_TRIG_HIGH_HONCE \
0x00001F00 // Trigger High Once (Hysteresis)
#define ADC_COMP_INT_NONE 0x00000000 // Interrupt Disabled
#define ADC_COMP_INT_LOW_ALWAYS \
0x00000010 // Interrupt Low Always
#define ADC_COMP_INT_LOW_ONCE 0x00000011 // Interrupt Low Once
#define ADC_COMP_INT_LOW_HALWAYS \
0x00000012 // Interrupt Low Always
// (Hysteresis)
#define ADC_COMP_INT_LOW_HONCE 0x00000013 // Interrupt Low Once (Hysteresis)
#define ADC_COMP_INT_MID_ALWAYS \
0x00000014 // Interrupt Mid Always
#define ADC_COMP_INT_MID_ONCE 0x00000015 // Interrupt Mid Once
#define ADC_COMP_INT_HIGH_ALWAYS \
0x0000001C // Interrupt High Always
#define ADC_COMP_INT_HIGH_ONCE 0x0000001D // Interrupt High Once
#define ADC_COMP_INT_HIGH_HALWAYS \
0x0000001E // Interrupt High Always
// (Hysteresis)
#define ADC_COMP_INT_HIGH_HONCE \
0x0000001F // Interrupt High Once (Hysteresis)
//*****************************************************************************
//
// Values that can be used to modify the sequence number passed to
// ADCProcessorTrigger in order to get cross-module synchronous processor
// triggers.
//
//*****************************************************************************
#define ADC_TRIGGER_WAIT 0x08000000 // Wait for the synchronous trigger
#define ADC_TRIGGER_SIGNAL 0x80000000 // Signal the synchronous trigger
//*****************************************************************************
//
// Values that can be passed to ADCPhaseDelaySet as the ui32Phase parameter and
// returned from ADCPhaseDelayGet.
//
//*****************************************************************************
#define ADC_PHASE_0 0x00000000 // 0 degrees
#define ADC_PHASE_22_5 0x00000001 // 22.5 degrees
#define ADC_PHASE_45 0x00000002 // 45 degrees
#define ADC_PHASE_67_5 0x00000003 // 67.5 degrees
#define ADC_PHASE_90 0x00000004 // 90 degrees
#define ADC_PHASE_112_5 0x00000005 // 112.5 degrees
#define ADC_PHASE_135 0x00000006 // 135 degrees
#define ADC_PHASE_157_5 0x00000007 // 157.5 degrees
#define ADC_PHASE_180 0x00000008 // 180 degrees
#define ADC_PHASE_202_5 0x00000009 // 202.5 degrees
#define ADC_PHASE_225 0x0000000A // 225 degrees
#define ADC_PHASE_247_5 0x0000000B // 247.5 degrees
#define ADC_PHASE_270 0x0000000C // 270 degrees
#define ADC_PHASE_292_5 0x0000000D // 292.5 degrees
#define ADC_PHASE_315 0x0000000E // 315 degrees
#define ADC_PHASE_337_5 0x0000000F // 337.5 degrees
//*****************************************************************************
//
// Values that can be passed to ADCReferenceSet as the ui32Ref parameter.
//
//*****************************************************************************
#define ADC_REF_INT 0x00000000 // Internal reference
#define ADC_REF_EXT_3V 0x00000001 // External 3V reference
//*****************************************************************************
//
// Values that can be passed to ADCIntDisableEx(), ADCIntEnableEx(),
// ADCIntClearEx() and ADCIntStatusEx().
//
//*****************************************************************************
#define ADC_INT_SS0 0x00000001
#define ADC_INT_SS1 0x00000002
#define ADC_INT_SS2 0x00000004
#define ADC_INT_SS3 0x00000008
#define ADC_INT_DMA_SS0 0x00000100
#define ADC_INT_DMA_SS1 0x00000200
#define ADC_INT_DMA_SS2 0x00000400
#define ADC_INT_DMA_SS3 0x00000800
#define ADC_INT_DCON_SS0 0x00010000
#define ADC_INT_DCON_SS1 0x00020000
#define ADC_INT_DCON_SS2 0x00040000
#define ADC_INT_DCON_SS3 0x00080000
//*****************************************************************************
//
// Values that can be passed to ADCClockConfigSet() and ADCClockConfigGet().
//
//*****************************************************************************
#define ADC_CLOCK_RATE_FULL 0x00000070
#define ADC_CLOCK_RATE_HALF 0x00000050
#define ADC_CLOCK_RATE_FOURTH 0x00000030
#define ADC_CLOCK_RATE_EIGHTH 0x00000010
#define ADC_CLOCK_SRC_PLL 0x00000000
#define ADC_CLOCK_SRC_PIOSC 0x00000001
#define ADC_CLOCK_SRC_ALTCLK 0x00000001
#define ADC_CLOCK_SRC_MOSC 0x00000002
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
extern void ADCIntRegister(uint32_t ui32Base, uint32_t ui32SequenceNum,
void (*pfnHandler)(void));
extern void ADCIntUnregister(uint32_t ui32Base, uint32_t ui32SequenceNum);
extern void ADCIntDisable(uint32_t ui32Base, uint32_t ui32SequenceNum);
extern void ADCIntEnable(uint32_t ui32Base, uint32_t ui32SequenceNum);
extern uint32_t ADCIntStatus(uint32_t ui32Base, uint32_t ui32SequenceNum,
bool bMasked);
extern void ADCIntClear(uint32_t ui32Base, uint32_t ui32SequenceNum);
extern void ADCSequenceEnable(uint32_t ui32Base, uint32_t ui32SequenceNum);
extern void ADCSequenceDisable(uint32_t ui32Base, uint32_t ui32SequenceNum);
extern void ADCSequenceConfigure(uint32_t ui32Base, uint32_t ui32SequenceNum,
uint32_t ui32Trigger, uint32_t ui32Priority);
extern void ADCSequenceStepConfigure(uint32_t ui32Base,
uint32_t ui32SequenceNum,
uint32_t ui32Step, uint32_t ui32Config);
extern int32_t ADCSequenceOverflow(uint32_t ui32Base,
uint32_t ui32SequenceNum);
extern void ADCSequenceOverflowClear(uint32_t ui32Base,
uint32_t ui32SequenceNum);
extern int32_t ADCSequenceUnderflow(uint32_t ui32Base,
uint32_t ui32SequenceNum);
extern void ADCSequenceUnderflowClear(uint32_t ui32Base,
uint32_t ui32SequenceNum);
extern int32_t ADCSequenceDataGet(uint32_t ui32Base, uint32_t ui32SequenceNum,
uint32_t *pui32Buffer);
extern void ADCProcessorTrigger(uint32_t ui32Base, uint32_t ui32SequenceNum);
extern void ADCSoftwareOversampleConfigure(uint32_t ui32Base,
uint32_t ui32SequenceNum,
uint32_t ui32Factor);
extern void ADCSoftwareOversampleStepConfigure(uint32_t ui32Base,
uint32_t ui32SequenceNum,
uint32_t ui32Step,
uint32_t ui32Config);
extern void ADCSoftwareOversampleDataGet(uint32_t ui32Base,
uint32_t ui32SequenceNum,
uint32_t *pui32Buffer,
uint32_t ui32Count);
extern void ADCHardwareOversampleConfigure(uint32_t ui32Base,
uint32_t ui32Factor);
extern void ADCClockConfigSet(uint32_t ui32Base, uint32_t ui32Config,
uint32_t ui32ClockDiv);
extern uint32_t ADCClockConfigGet(uint32_t ui32Base, uint32_t *pui32ClockDiv);
extern void ADCComparatorConfigure(uint32_t ui32Base, uint32_t ui32Comp,
uint32_t ui32Config);
extern void ADCComparatorRegionSet(uint32_t ui32Base, uint32_t ui32Comp,
uint32_t ui32LowRef, uint32_t ui32HighRef);
extern void ADCComparatorReset(uint32_t ui32Base, uint32_t ui32Comp,
bool bTrigger, bool bInterrupt);
extern void ADCComparatorIntDisable(uint32_t ui32Base,
uint32_t ui32SequenceNum);
extern void ADCComparatorIntEnable(uint32_t ui32Base,
uint32_t ui32SequenceNum);
extern uint32_t ADCComparatorIntStatus(uint32_t ui32Base);
extern void ADCComparatorIntClear(uint32_t ui32Base, uint32_t ui32Status);
extern void ADCIntDisableEx(uint32_t ui32Base, uint32_t ui32IntFlags);
extern void ADCIntEnableEx(uint32_t ui32Base, uint32_t ui32IntFlags);
extern uint32_t ADCIntStatusEx(uint32_t ui32Base, bool bMasked);
extern void ADCIntClearEx(uint32_t ui32Base, uint32_t ui32IntFlags);
extern void ADCSequenceDMAEnable(uint32_t ui32Base, uint32_t ui32SequenceNum);
extern void ADCSequenceDMADisable(uint32_t ui32Base, uint32_t ui32SequenceNum);
extern bool ADCBusy(uint32_t ui32Base);
extern void ADCReferenceSet(uint32_t ui32Base, uint32_t ui32Ref);
extern uint32_t ADCReferenceGet(uint32_t ui32Base);
extern void ADCPhaseDelaySet(uint32_t ui32Base, uint32_t ui32Phase);
extern uint32_t ADCPhaseDelayGet(uint32_t ui32Base);
extern void ADCSampleRateSet(uint32_t ui32Base, uint32_t ui32ADCClock,
uint32_t ui32Rate);
extern uint32_t ADCSampleRateGet(uint32_t ui32Base);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __DRIVERLIB_ADC_H__
bsp/tm4c129x-dk/libraries/driverlib/aes.c 0 → 100644
浏览文件 @ 5c420c0c
此差异已折叠。
bsp/tm4c129x-dk/libraries/driverlib/aes.h 0 → 100644
浏览文件 @ 5c420c0c
//*****************************************************************************
//
// aes.h - Defines and Macros for the AES module.
//
// Copyright (c) 2012-2017 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __DRIVERLIB_AES_H__
#define __DRIVERLIB_AES_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// The following defines are used to specify the operation direction in the
// ui32Config argument in the AESConfig function. Only one is permitted.
//
//*****************************************************************************
#define AES_CFG_DIR_ENCRYPT 0x00000004
#define AES_CFG_DIR_DECRYPT 0x00000000
//*****************************************************************************
//
// The following defines are used to specify the key size in the ui32Config
// argument in the AESConfig function. Only one is permitted.
//
//*****************************************************************************
#define AES_CFG_KEY_SIZE_128BIT 0x00000008
#define AES_CFG_KEY_SIZE_192BIT 0x00000010
#define AES_CFG_KEY_SIZE_256BIT 0x00000018
//*****************************************************************************
//
// The following defines are used to specify the mode of operation in the
// ui32Config argument in the AESConfig function. Only one is permitted.
//
//*****************************************************************************
#define AES_CFG_MODE_M 0x2007fe60
#define AES_CFG_MODE_ECB 0x00000000
#define AES_CFG_MODE_CBC 0x00000020
#define AES_CFG_MODE_CTR 0x00000040
#define AES_CFG_MODE_ICM 0x00000200
#define AES_CFG_MODE_CFB 0x00000400
#define AES_CFG_MODE_XTS_TWEAKJL \
0x00000800
#define AES_CFG_MODE_XTS_K2IJL \
0x00001000
#define AES_CFG_MODE_XTS_K2ILJ0 \
0x00001800
#define AES_CFG_MODE_F8 0x00002000
#define AES_CFG_MODE_F9 0x20004000
#define AES_CFG_MODE_CBCMAC 0x20008000
#define AES_CFG_MODE_GCM_HLY0ZERO \
0x20010000
#define AES_CFG_MODE_GCM_HLY0CALC \
0x20020040
#define AES_CFG_MODE_GCM_HY0CALC \
0x20030040
#define AES_CFG_MODE_CCM 0x20040040
//*****************************************************************************
//
// The following defines are used to specify the counter width in the
// ui32Config argument in the AESConfig function. It is only required to
// be defined when using CTR, CCM, or GCM modes. Only one length is permitted.
//
//*****************************************************************************
#define AES_CFG_CTR_WIDTH_32 0x00000000
#define AES_CFG_CTR_WIDTH_64 0x00000080
#define AES_CFG_CTR_WIDTH_96 0x00000100
#define AES_CFG_CTR_WIDTH_128 0x00000180
//*****************************************************************************
//
// The following defines are used to define the width of the length field for
// CCM operation through the ui32Config argument in the AESConfig function.
// This value is also known as L. Only one is permitted.
//
//*****************************************************************************
#define AES_CFG_CCM_L_1 0x00000000
#define AES_CFG_CCM_L_2 0x00080000
#define AES_CFG_CCM_L_3 0x00100000
#define AES_CFG_CCM_L_4 0x00180000
#define AES_CFG_CCM_L_5 0x00200000
#define AES_CFG_CCM_L_6 0x00280000
#define AES_CFG_CCM_L_7 0x00300000
#define AES_CFG_CCM_L_8 0x00380000
//*****************************************************************************
//
// The following defines are used to define the length of the authentication
// field for CCM operations through the ui32Config argument in the AESConfig
// function. This value is also known as M. Only one is permitted.
//
//*****************************************************************************
#define AES_CFG_CCM_M_4 0x00400000
#define AES_CFG_CCM_M_6 0x00800000
#define AES_CFG_CCM_M_8 0x00c00000
#define AES_CFG_CCM_M_10 0x01000000
#define AES_CFG_CCM_M_12 0x01400000
#define AES_CFG_CCM_M_14 0x01800000
#define AES_CFG_CCM_M_16 0x01c00000
//*****************************************************************************
//
// Interrupt flags for use with the AESIntEnable, AESIntDisable, and
// AESIntStatus functions.
//
//*****************************************************************************
#define AES_INT_CONTEXT_IN 0x00000001
#define AES_INT_CONTEXT_OUT 0x00000008
#define AES_INT_DATA_IN 0x00000002
#define AES_INT_DATA_OUT 0x00000004
#define AES_INT_DMA_CONTEXT_IN 0x00010000
#define AES_INT_DMA_CONTEXT_OUT 0x00080000
#define AES_INT_DMA_DATA_IN 0x00020000
#define AES_INT_DMA_DATA_OUT 0x00040000
//*****************************************************************************
//
// Defines used when enabling and disabling DMA requests in the
// AESEnableDMA and AESDisableDMA functions.
//
//*****************************************************************************
#define AES_DMA_DATA_IN 0x00000020
#define AES_DMA_DATA_OUT 0x00000040
#define AES_DMA_CONTEXT_IN 0x00000080
#define AES_DMA_CONTEXT_OUT 0x00000100
//*****************************************************************************
//
// Function prototypes.
//
//*****************************************************************************
extern void AESAuthLengthSet(uint32_t ui32Base, uint32_t ui32Length);
extern void AESConfigSet(uint32_t ui32Base, uint32_t ui32Config);
extern void AESDataRead(uint32_t ui32Base, uint32_t *pui32Dest);
extern bool AESDataReadNonBlocking(uint32_t ui32Base, uint32_t *pui32Dest);
extern bool AESDataProcess(uint32_t ui32Base, uint32_t *pui32Src,
uint32_t *pui32Dest, uint32_t ui32Length);
extern bool AESDataAuth(uint32_t ui32Base, uint32_t *pui32Src,
uint32_t ui32Length, uint32_t *pui32Tag);
extern bool AESDataProcessAuth(uint32_t ui32Base, uint32_t *pui32Src,
uint32_t *pui32Dest, uint32_t ui32Length,
uint32_t *pui32AuthSrc,
uint32_t ui32AuthLength, uint32_t *pui32Tag);
extern void AESDataWrite(uint32_t ui32Base, uint32_t *pui32Src);
extern bool AESDataWriteNonBlocking(uint32_t ui32Base, uint32_t *pui32Src);
extern void AESDMADisable(uint32_t ui32Base, uint32_t ui32Flags);
extern void AESDMAEnable(uint32_t ui32Base, uint32_t ui32Flags);
extern void AESIntClear(uint32_t ui32Base, uint32_t ui32IntFlags);
extern void AESIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags);
extern void AESIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags);
extern void AESIntRegister(uint32_t ui32Base, void (*pfnHandler)(void));
extern uint32_t AESIntStatus(uint32_t ui32Base, bool bMasked);
extern void AESIntUnregister(uint32_t ui32Base);
extern void AESIVSet(uint32_t ui32Base, uint32_t *pui32IVdata);
extern void AESIVRead(uint32_t ui32Base, uint32_t *pui32IVdata);
extern void AESKey1Set(uint32_t ui32Base, uint32_t *pui32Key,
uint32_t ui32Keysize);
extern void AESKey2Set(uint32_t ui32Base, uint32_t *pui32Key,
uint32_t ui32Keysize);
extern void AESKey3Set(uint32_t ui32Base, uint32_t *pui32Key);
extern void AESLengthSet(uint32_t ui32Base, uint64_t ui64Length);
extern void AESReset(uint32_t ui32Base);
extern void AESTagRead(uint32_t ui32Base, uint32_t *pui32TagData);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __DRIVERLIB_AES_H__
bsp/tm4c129x-dk/libraries/driverlib/can.c 0 → 100644
浏览文件 @ 5c420c0c
此差异已折叠。
bsp/tm4c129x-dk/libraries/driverlib/can.h 0 → 100644
浏览文件 @ 5c420c0c
//*****************************************************************************
//
// can.h - Defines and Macros for the CAN controller.
//
// Copyright (c) 2006-2017 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __DRIVERLIB_CAN_H__
#define __DRIVERLIB_CAN_H__
//*****************************************************************************
//
//! \addtogroup can_api
//! @{
//
//*****************************************************************************
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Miscellaneous defines for Message ID Types
//
//*****************************************************************************
//*****************************************************************************
//
// These are the flags used by the tCANMsgObject.ui32Flags value when calling
// the CANMessageSet() and CANMessageGet() functions.
//
//*****************************************************************************
//
//! This indicates that transmit interrupts are enabled.
//
#define MSG_OBJ_TX_INT_ENABLE 0x00000001
//
//! This indicates that receive interrupts are enabled.
//
#define MSG_OBJ_RX_INT_ENABLE 0x00000002
//
//! This indicates that a message object is using an extended identifier.
//
#define MSG_OBJ_EXTENDED_ID 0x00000004
//
//! This indicates that a message object is using filtering based on the
//! object's message identifier.
//
#define MSG_OBJ_USE_ID_FILTER 0x00000008
//
//! This indicates that new data was available in the message object.
//
#define MSG_OBJ_NEW_DATA 0x00000080
//
//! This indicates that data was lost since this message object was last
//! read.
//
#define MSG_OBJ_DATA_LOST 0x00000100
//
//! This indicates that a message object uses or is using filtering
//! based on the direction of the transfer. If the direction filtering is
//! used, then ID filtering must also be enabled.
//
#define MSG_OBJ_USE_DIR_FILTER (0x00000010 | MSG_OBJ_USE_ID_FILTER)
//
//! This indicates that a message object uses or is using message
//! identifier filtering based on the extended identifier. If the extended
//! identifier filtering is used, then ID filtering must also be enabled.
//
#define MSG_OBJ_USE_EXT_FILTER (0x00000020 | MSG_OBJ_USE_ID_FILTER)
//
//! This indicates that a message object is a remote frame.
//
#define MSG_OBJ_REMOTE_FRAME 0x00000040
//
//! This indicates that this message object is part of a FIFO structure and
//! not the final message object in a FIFO.
//
#define MSG_OBJ_FIFO 0x00000200
//
//! This indicates that a message object has no flags set.
//
#define MSG_OBJ_NO_FLAGS 0x00000000
//*****************************************************************************
//
//! This define is used with the flag values to allow checking only status
//! flags and not configuration flags.
//
//*****************************************************************************
#define MSG_OBJ_STATUS_MASK (MSG_OBJ_NEW_DATA | MSG_OBJ_DATA_LOST)
//*****************************************************************************
//
//! The structure used for encapsulating all the items associated with a CAN
//! message object in the CAN controller.
//
//*****************************************************************************
typedef struct
{
//
//! The CAN message identifier used for 11 or 29 bit identifiers.
//
uint32_t ui32MsgID;
//
//! The message identifier mask used when identifier filtering is enabled.
//
uint32_t ui32MsgIDMask;
//
//! This value holds various status flags and settings specified by
//! tCANObjFlags.
//
uint32_t ui32Flags;
//
//! This value is the number of bytes of data in the message object.
//
uint32_t ui32MsgLen;
//
//! This is a pointer to the message object's data.
//
uint8_t *pui8MsgData;
}
tCANMsgObject;
//*****************************************************************************
//
//! This structure is used for encapsulating the values associated with setting
//! up the bit timing for a CAN controller. The structure is used when calling
//! the CANGetBitTiming and CANSetBitTiming functions.
//
//*****************************************************************************
typedef struct
{
//
//! This value holds the sum of the Synchronization, Propagation, and Phase
//! Buffer 1 segments, measured in time quanta. The valid values for this
//! setting range from 2 to 16.
//
uint32_t ui32SyncPropPhase1Seg;
//
//! This value holds the Phase Buffer 2 segment in time quanta. The valid
//! values for this setting range from 1 to 8.
//
uint32_t ui32Phase2Seg;
//
//! This value holds the Resynchronization Jump Width in time quanta. The
//! valid values for this setting range from 1 to 4.
//
uint32_t ui32SJW;
//
//! This value holds the CAN_CLK divider used to determine time quanta.
//! The valid values for this setting range from 1 to 1023.
//
uint32_t ui32QuantumPrescaler;
}
tCANBitClkParms;
//*****************************************************************************
//
//! This data type is used to identify the interrupt status register. This is
//! used when calling the CANIntStatus() function.
//
//*****************************************************************************
typedef enum
{
//
//! Read the CAN interrupt status information.
//
CAN_INT_STS_CAUSE,
//
//! Read a message object's interrupt status.
//
CAN_INT_STS_OBJECT
}
tCANIntStsReg;
//*****************************************************************************
//
//! This data type is used to identify which of several status registers to
//! read when calling the CANStatusGet() function.
//
//*****************************************************************************
typedef enum
{
//
//! Read the full CAN controller status.
//
CAN_STS_CONTROL,
//
//! Read the full 32-bit mask of message objects with a transmit request
//! set.
//
CAN_STS_TXREQUEST,
//
//! Read the full 32-bit mask of message objects with new data available.
//
CAN_STS_NEWDAT,
//
//! Read the full 32-bit mask of message objects that are enabled.
//
CAN_STS_MSGVAL
}
tCANStsReg;
//*****************************************************************************
//
// These definitions are used to specify interrupt sources to CANIntEnable()
// and CANIntDisable().
//
//*****************************************************************************
//
//! This flag is used to allow a CAN controller to generate error
//! interrupts.
//
#define CAN_INT_ERROR 0x00000008
//
//! This flag is used to allow a CAN controller to generate status
//! interrupts.
//
#define CAN_INT_STATUS 0x00000004
//
//! This flag is used to allow a CAN controller to generate any CAN
//! interrupts. If this is not set, then no interrupts are generated
//! by the CAN controller.
//
#define CAN_INT_MASTER 0x00000002
//*****************************************************************************
//
//! This definition is used to determine the type of message object that is
//! set up via a call to the CANMessageSet() API.
//
//*****************************************************************************
typedef enum
{
//
//! Transmit message object.
//
MSG_OBJ_TYPE_TX,
//
//! Transmit remote request message object
//
MSG_OBJ_TYPE_TX_REMOTE,
//
//! Receive message object.
//
MSG_OBJ_TYPE_RX,
//
//! Receive remote request message object.
//
MSG_OBJ_TYPE_RX_REMOTE,
//
//! Remote frame receive remote, with auto-transmit message object.
//
MSG_OBJ_TYPE_RXTX_REMOTE
}
tMsgObjType;
//*****************************************************************************
//
// The following enumeration contains all error or status indicators that can
// be returned when calling the CANStatusGet() function.
//
//*****************************************************************************
//
//! CAN controller has entered a Bus Off state.
//
#define CAN_STATUS_BUS_OFF 0x00000080
//
//! CAN controller error level has reached warning level.
//
#define CAN_STATUS_EWARN 0x00000040
//
//! CAN controller error level has reached error passive level.
//
#define CAN_STATUS_EPASS 0x00000020
//
//! A message was received successfully since the last read of this status.
//
#define CAN_STATUS_RXOK 0x00000010
//
//! A message was transmitted successfully since the last read of this
//! status.
//
#define CAN_STATUS_TXOK 0x00000008
//
//! This is the mask for the last error code field.
//
#define CAN_STATUS_LEC_MSK 0x00000007
//
//! There was no error.
//
#define CAN_STATUS_LEC_NONE 0x00000000
//
//! A bit stuffing error has occurred.
//
#define CAN_STATUS_LEC_STUFF 0x00000001
//
//! A formatting error has occurred.
//
#define CAN_STATUS_LEC_FORM 0x00000002
//
//! An acknowledge error has occurred.
//
#define CAN_STATUS_LEC_ACK 0x00000003
//
//! The bus remained a bit level of 1 for longer than is allowed.
//
#define CAN_STATUS_LEC_BIT1 0x00000004
//
//! The bus remained a bit level of 0 for longer than is allowed.
//
#define CAN_STATUS_LEC_BIT0 0x00000005
//
//! A CRC error has occurred.
//
#define CAN_STATUS_LEC_CRC 0x00000006
//
//! This is the mask for the CAN Last Error Code (LEC).
//
#define CAN_STATUS_LEC_MASK 0x00000007
//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************
//*****************************************************************************
//
// API Function prototypes
//
//*****************************************************************************
extern void CANBitTimingGet(uint32_t ui32Base, tCANBitClkParms *psClkParms);
extern void CANBitTimingSet(uint32_t ui32Base, tCANBitClkParms *psClkParms);
extern uint32_t CANBitRateSet(uint32_t ui32Base, uint32_t ui32SourceClock,
uint32_t ui32BitRate);
extern void CANDisable(uint32_t ui32Base);
extern void CANEnable(uint32_t ui32Base);
extern bool CANErrCntrGet(uint32_t ui32Base, uint32_t *pui32RxCount,
uint32_t *pui32TxCount);
extern void CANInit(uint32_t ui32Base);
extern void CANIntClear(uint32_t ui32Base, uint32_t ui32IntClr);
extern void CANIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags);
extern void CANIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags);
extern void CANIntRegister(uint32_t ui32Base, void (*pfnHandler)(void));
extern uint32_t CANIntStatus(uint32_t ui32Base, tCANIntStsReg eIntStsReg);
extern void CANIntUnregister(uint32_t ui32Base);
extern void CANMessageClear(uint32_t ui32Base, uint32_t ui32ObjID);
extern void CANMessageGet(uint32_t ui32Base, uint32_t ui32ObjID,
tCANMsgObject *psMsgObject, bool bClrPendingInt);
extern void CANMessageSet(uint32_t ui32Base, uint32_t ui32ObjID,
tCANMsgObject *psMsgObject, tMsgObjType eMsgType);
extern bool CANRetryGet(uint32_t ui32Base);
extern void CANRetrySet(uint32_t ui32Base, bool bAutoRetry);
extern uint32_t CANStatusGet(uint32_t ui32Base, tCANStsReg eStatusReg);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __DRIVERLIB_CAN_H__
bsp/tm4c129x-dk/libraries/driverlib/comp.c 0 → 100644
浏览文件 @ 5c420c0c
//*****************************************************************************
//
// comp.c - Driver for the analog comparator.
//
// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library.
//
//*****************************************************************************
//*****************************************************************************
//
//! \addtogroup comp_api
//! @{
//
//*****************************************************************************
#include <stdbool.h>
#include <stdint.h>
#include "inc/hw_comp.h"
#include "inc/hw_ints.h"
#include "inc/hw_memmap.h"
#include "inc/hw_types.h"
#include "driverlib/comp.h"
#include "driverlib/debug.h"
#include "driverlib/interrupt.h"
//*****************************************************************************
//
//! Configures a comparator.
//!
//! \param ui32Base is the base address of the comparator module.
//! \param ui32Comp is the index of the comparator to configure.
//! \param ui32Config is the configuration of the comparator.
//!
//! This function configures a comparator. The \e ui32Config parameter is the
//! result of a logical OR operation between the \b COMP_TRIG_xxx,
//! \b COMP_INT_xxx, \b COMP_ASRCP_xxx, and \b COMP_OUTPUT_xxx values.
//!
//! The \b COMP_TRIG_xxx term can take on the following values:
//!
//! - \b COMP_TRIG_NONE to have no trigger to the ADC.
//! - \b COMP_TRIG_HIGH to trigger the ADC when the comparator output is high.
//! - \b COMP_TRIG_LOW to trigger the ADC when the comparator output is low.
//! - \b COMP_TRIG_FALL to trigger the ADC when the comparator output goes low.
//! - \b COMP_TRIG_RISE to trigger the ADC when the comparator output goes
//! high.
//! - \b COMP_TRIG_BOTH to trigger the ADC when the comparator output goes low
//! or high.
//!
//! The \b COMP_INT_xxx term can take on the following values:
//!
//! - \b COMP_INT_HIGH to generate an interrupt when the comparator output is
//! high.
//! - \b COMP_INT_LOW to generate an interrupt when the comparator output is
//! low.
//! - \b COMP_INT_FALL to generate an interrupt when the comparator output goes
//! low.
//! - \b COMP_INT_RISE to generate an interrupt when the comparator output goes
//! high.
//! - \b COMP_INT_BOTH to generate an interrupt when the comparator output goes
//! low or high.
//!
//! The \b COMP_ASRCP_xxx term can take on the following values:
//!
//! - \b COMP_ASRCP_PIN to use the dedicated Comp+ pin as the reference
//! voltage.
//! - \b COMP_ASRCP_PIN0 to use the Comp0+ pin as the reference voltage (this
//! the same as \b COMP_ASRCP_PIN for the comparator 0).
//! - \b COMP_ASRCP_REF to use the internally generated voltage as the
//! reference voltage.
//!
//! The \b COMP_OUTPUT_xxx term can take on the following values:
//!
//! - \b COMP_OUTPUT_NORMAL to enable a non-inverted output from the comparator
//! to a device pin.
//! - \b COMP_OUTPUT_INVERT to enable an inverted output from the comparator to
//! a device pin.
//!
//! \return None.
//
//*****************************************************************************
void
ComparatorConfigure(uint32_t ui32Base, uint32_t ui32Comp, uint32_t ui32Config)
{
//
// Check the arguments.
//
ASSERT(ui32Base == COMP_BASE);
ASSERT(ui32Comp < 3);
//
// Configure this comparator.
//
HWREG(ui32Base + (ui32Comp * 0x20) + COMP_O_ACCTL0) = ui32Config;
}
//*****************************************************************************
//
//! Sets the internal reference voltage.
//!
//! \param ui32Base is the base address of the comparator module.
//! \param ui32Ref is the desired reference voltage.
//!
//! This function sets the internal reference voltage value. The voltage is
//! specified as one of the following values:
//!
//! - \b COMP_REF_OFF to turn off the reference voltage
//! - \b COMP_REF_0V to set the reference voltage to 0 V
//! - \b COMP_REF_0_1375V to set the reference voltage to 0.1375 V
//! - \b COMP_REF_0_275V to set the reference voltage to 0.275 V
//! - \b COMP_REF_0_4125V to set the reference voltage to 0.4125 V
//! - \b COMP_REF_0_55V to set the reference voltage to 0.55 V
//! - \b COMP_REF_0_6875V to set the reference voltage to 0.6875 V
//! - \b COMP_REF_0_825V to set the reference voltage to 0.825 V
//! - \b COMP_REF_0_928125V to set the reference voltage to 0.928125 V
//! - \b COMP_REF_0_9625V to set the reference voltage to 0.9625 V
//! - \b COMP_REF_1_03125V to set the reference voltage to 1.03125 V
//! - \b COMP_REF_1_134375V to set the reference voltage to 1.134375 V
//! - \b COMP_REF_1_1V to set the reference voltage to 1.1 V
//! - \b COMP_REF_1_2375V to set the reference voltage to 1.2375 V
//! - \b COMP_REF_1_340625V to set the reference voltage to 1.340625 V
//! - \b COMP_REF_1_375V to set the reference voltage to 1.375 V
//! - \b COMP_REF_1_44375V to set the reference voltage to 1.44375 V
//! - \b COMP_REF_1_5125V to set the reference voltage to 1.5125 V
//! - \b COMP_REF_1_546875V to set the reference voltage to 1.546875 V
//! - \b COMP_REF_1_65V to set the reference voltage to 1.65 V
//! - \b COMP_REF_1_753125V to set the reference voltage to 1.753125 V
//! - \b COMP_REF_1_7875V to set the reference voltage to 1.7875 V
//! - \b COMP_REF_1_85625V to set the reference voltage to 1.85625 V
//! - \b COMP_REF_1_925V to set the reference voltage to 1.925 V
//! - \b COMP_REF_1_959375V to set the reference voltage to 1.959375 V
//! - \b COMP_REF_2_0625V to set the reference voltage to 2.0625 V
//! - \b COMP_REF_2_165625V to set the reference voltage to 2.165625 V
//! - \b COMP_REF_2_26875V to set the reference voltage to 2.26875 V
//! - \b COMP_REF_2_371875V to set the reference voltage to 2.371875 V
//!
//! \return None.
//
//*****************************************************************************
void
ComparatorRefSet(uint32_t ui32Base, uint32_t ui32Ref)
{
//
// Check the arguments.
//
ASSERT(ui32Base == COMP_BASE);
//
// Set the voltage reference voltage as requested.
//
HWREG(ui32Base + COMP_O_ACREFCTL) = ui32Ref;
}
//*****************************************************************************
//
//! Gets the current comparator output value.
//!
//! \param ui32Base is the base address of the comparator module.
//! \param ui32Comp is the index of the comparator.
//!
//! This function retrieves the current value of the comparator output.
//!
//! \return Returns \b true if the comparator output is high and \b false if
//! the comparator output is low.
//
//*****************************************************************************
bool
ComparatorValueGet(uint32_t ui32Base, uint32_t ui32Comp)
{
//
// Check the arguments.
//
ASSERT(ui32Base == COMP_BASE);
ASSERT(ui32Comp < 3);
//
// Return the appropriate value based on the comparator's present output
// value.
//
if(HWREG(ui32Base + (ui32Comp * 0x20) + COMP_O_ACSTAT0) &
COMP_ACSTAT0_OVAL)
{
return(true);
}
else
{
return(false);
}
}
//*****************************************************************************
//
//! Registers an interrupt handler for the comparator interrupt.
//!
//! \param ui32Base is the base address of the comparator module.
//! \param ui32Comp is the index of the comparator.
//! \param pfnHandler is a pointer to the function to be called when the
//! comparator interrupt occurs.
//!
//! This function sets the handler to be called when the comparator interrupt
//! occurs and enables the interrupt in the interrupt controller. It is the
//! interrupt handler's responsibility to clear the interrupt source via
//! ComparatorIntClear().
//!
//! \sa IntRegister() for important information about registering interrupt
//! handlers.
//!
//! \return None.
//
//*****************************************************************************
void
ComparatorIntRegister(uint32_t ui32Base, uint32_t ui32Comp,
void (*pfnHandler)(void))
{
//
// Check the arguments.
//
ASSERT(ui32Base == COMP_BASE);
ASSERT(ui32Comp < 3);
//
// Register the interrupt handler, returning an error if an error occurs.
//
IntRegister(INT_COMP0_TM4C123 + ui32Comp, pfnHandler);
//
// Enable the interrupt in the interrupt controller.
//
IntEnable(INT_COMP0_TM4C123 + ui32Comp);
//
// Enable the comparator interrupt.
//
HWREG(ui32Base + COMP_O_ACINTEN) |= 1 << ui32Comp;
}
//*****************************************************************************
//
//! Unregisters an interrupt handler for a comparator interrupt.
//!
//! \param ui32Base is the base address of the comparator module.
//! \param ui32Comp is the index of the comparator.
//!
//! This function clears the handler to be called when a comparator interrupt
//! occurs. This function also masks off the interrupt in the interrupt
//! controller so that the interrupt handler no longer is called.
//!
//! \sa IntRegister() for important information about registering interrupt
//! handlers.
//!
//! \return None.
//
//*****************************************************************************
void
ComparatorIntUnregister(uint32_t ui32Base, uint32_t ui32Comp)
{
//
// Check the arguments.
//
ASSERT(ui32Base == COMP_BASE);
ASSERT(ui32Comp < 3);
//
// Disable the comparator interrupt.
//
HWREG(ui32Base + COMP_O_ACINTEN) &= ~(1 << ui32Comp);
//
// Disable the interrupt in the interrupt controller.
//
IntDisable(INT_COMP0_TM4C123 + ui32Comp);
//
// Unregister the interrupt handler.
//
IntUnregister(INT_COMP0_TM4C123 + ui32Comp);
}
//*****************************************************************************
//
//! Enables the comparator interrupt.
//!
//! \param ui32Base is the base address of the comparator module.
//! \param ui32Comp is the index of the comparator.
//!
//! This function enables generation of an interrupt from the specified
//! comparator. Only enabled comparator interrupts can be reflected
//! to the processor.
//!
//! \return None.
//
//*****************************************************************************
void
ComparatorIntEnable(uint32_t ui32Base, uint32_t ui32Comp)
{
//
// Check the arguments.
//
ASSERT(ui32Base == COMP_BASE);
ASSERT(ui32Comp < 3);
//
// Enable the comparator interrupt.
//
HWREG(ui32Base + COMP_O_ACINTEN) |= 1 << ui32Comp;
}
//*****************************************************************************
//
//! Disables the comparator interrupt.
//!
//! \param ui32Base is the base address of the comparator module.
//! \param ui32Comp is the index of the comparator.
//!
//! This function disables generation of an interrupt from the specified
//! comparator. Only enabled comparator interrupts can be reflected
//! to the processor.
//!
//! \return None.
//
//*****************************************************************************
void
ComparatorIntDisable(uint32_t ui32Base, uint32_t ui32Comp)
{
//
// Check the arguments.
//
ASSERT(ui32Base == COMP_BASE);
ASSERT(ui32Comp < 3);
//
// Disable the comparator interrupt.
//
HWREG(ui32Base + COMP_O_ACINTEN) &= ~(1 << ui32Comp);
}
//*****************************************************************************
//
//! Gets the current interrupt status.
//!
//! \param ui32Base is the base address of the comparator module.
//! \param ui32Comp is the index of the comparator.
//! \param bMasked is \b false if the raw interrupt status is required and
//! \b true if the masked interrupt status is required.
//!
//! This function returns the interrupt status for the comparator. Either the
//! raw or the masked interrupt status can be returned.
//!
//! \return \b true if the interrupt is asserted and \b false if it is not
//! asserted.
//
//*****************************************************************************
bool
ComparatorIntStatus(uint32_t ui32Base, uint32_t ui32Comp, bool bMasked)
{
//
// Check the arguments.
//
ASSERT(ui32Base == COMP_BASE);
ASSERT(ui32Comp < 3);
//
// Return either the interrupt status or the raw interrupt status as
// requested.
//
if(bMasked)
{
return(((HWREG(ui32Base + COMP_O_ACMIS) >> ui32Comp) & 1) ? true :
false);
}
else
{
return(((HWREG(ui32Base + COMP_O_ACRIS) >> ui32Comp) & 1) ? true :
false);
}
}
//*****************************************************************************
//
//! Clears a comparator interrupt.
//!
//! \param ui32Base is the base address of the comparator module.
//! \param ui32Comp is the index of the comparator.
//!
//! The comparator interrupt is cleared, so that it no longer asserts. This
//! function must be called in the interrupt handler to keep the handler from
//! being called again immediately upon exit. Note that for a level-triggered
//! interrupt, the interrupt cannot be cleared until it stops asserting.
//!
//! \note Because there is a write buffer in the Cortex-M processor, it may
//! take several clock cycles before the interrupt source is actually cleared.
//! Therefore, it is recommended that the interrupt source be cleared early in
//! the interrupt handler (as opposed to the very last action) to avoid
//! returning from the interrupt handler before the interrupt source is
//! actually cleared. Failure to do so may result in the interrupt handler
//! being immediately reentered (because the interrupt controller still sees
//! the interrupt source asserted).
//!
//! \return None.
//
//*****************************************************************************
void
ComparatorIntClear(uint32_t ui32Base, uint32_t ui32Comp)
{
//
// Check the arguments.
//
ASSERT(ui32Base == COMP_BASE);
ASSERT(ui32Comp < 3);
//
// Clear the interrupt.
//
HWREG(ui32Base + COMP_O_ACMIS) = 1 << ui32Comp;
}
//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************
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