diff --git a/bsp/mipssim/Kconfig b/bsp/mipssim/Kconfig new file mode 100644 index 0000000000000000000000000000000000000000..1d490c06380dfaf34b0fbc7ee8a3209990e104a5 --- /dev/null +++ b/bsp/mipssim/Kconfig @@ -0,0 +1,31 @@ +mainmenu "RT-Thread Configuration" + +config BSP_DIR + string + option env="BSP_ROOT" + default "." + +config RTT_DIR + string + option env="RTT_ROOT" + default "../.." + +# you can change the RTT_ROOT default "../.." to your rtthread_root, +# example : default "F:/git_repositories/rt-thread" + +config PKGS_DIR + string + option env="PKGS_ROOT" + default "packages" + +source "$RTT_DIR/Kconfig" +source "$RTT_DIR/libcpu/mips/common/Kconfig" +source "$PKGS_DIR/Kconfig" + +config MIPSSIM + bool + select ARCH_MIPS + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN + select RT_USING_DEVICE + default y diff --git a/bsp/mipssim/README.md b/bsp/mipssim/README.md new file mode 100644 index 0000000000000000000000000000000000000000..9ef1d67068523ff22ccfbab90e617511baa4da71 --- /dev/null +++ b/bsp/mipssim/README.md @@ -0,0 +1,15 @@ +MIPSSIM 板级支持包 + + +--- + +## 1. 简介 + +本BSP用于在MIPSSIM或QEMU的MIPSSIM Machine模拟器中运行RT-Thread。 +使用mips-sde-elf工具链编译。 +在QEMU中使用如下命令运行： +``` +qemu-system-mipsel -M mipssim -cpu P5600 -nographic -kernel ./rtthread.elf +``` + +MIPSSIM拥有一个8250串口和一个MIPSNET网卡外设，本BSP目前仅实现了串口。 \ No newline at end of file diff --git a/bsp/mipssim/SConscript b/bsp/mipssim/SConscript new file mode 100644 index 0000000000000000000000000000000000000000..09926124102749b1b0ffbdb1941950ca1e5ef65f --- /dev/null +++ b/bsp/mipssim/SConscript @@ -0,0 +1,12 @@ +from building import * + +cwd = GetCurrentDir() +objs = [] +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') diff --git a/bsp/mipssim/SConstruct b/bsp/mipssim/SConstruct new file mode 100644 index 0000000000000000000000000000000000000000..beea1486643bb77447a6da59f337650649640015 --- /dev/null +++ b/bsp/mipssim/SConstruct @@ -0,0 +1,38 @@ +import os +import sys +import rtconfig + +from rtconfig import RTT_ROOT + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +from building import * + +TARGET = 'rtthread.' + rtconfig.TARGET_EXT + +rtconfig.AFLAGS += ' -I' + str(Dir('#')) + +DefaultEnvironment(tools=[]) +env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) + +Export('RTT_ROOT') +Export('rtconfig') + + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT) + +env.Replace(LINKFLAGS = rtconfig.LFLAGS) + +if GetDepend('RT_USING_FPU'): + env['CCFLAGS'] = env['CCFLAGS'].replace('-msoft-float', '-mhard-float') + env['ASFLAGS'] = env['ASFLAGS'].replace('-msoft-float', '-mhard-float') + env['CXXFLAGS'] = env['CXXFLAGS'].replace('-msoft-float', '-mhard-float') + env['LINKFLAGS'] = env['LINKFLAGS'].replace('-msoft-float', '-mhard-float') + +# make a building +DoBuilding(TARGET, objs) diff --git a/bsp/mipssim/applications/SConscript b/bsp/mipssim/applications/SConscript new file mode 100644 index 0000000000000000000000000000000000000000..fb5ce2ce9328be8a24e1003d4d3161fe5c19bd57 --- /dev/null +++ b/bsp/mipssim/applications/SConscript @@ -0,0 +1,8 @@ +from building import * + +cwd = GetCurrentDir() +src = Glob('*.c') + +group = DefineGroup('Applications', src, depend = ['']) + +Return('group') diff --git a/bsp/mipssim/applications/main.c b/bsp/mipssim/applications/main.c new file mode 100644 index 0000000000000000000000000000000000000000..fac004d83217549b59bdcd416e74a8aef8173d1c --- /dev/null +++ b/bsp/mipssim/applications/main.c @@ -0,0 +1,17 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-05-10 zhuangwei first version + */ + +#include + +int main(int argc, char** argv) +{ + + return 0; +} diff --git a/bsp/mipssim/drivers/SConscript b/bsp/mipssim/drivers/SConscript new file mode 100644 index 0000000000000000000000000000000000000000..d5542b768f13877cd6fb933767564f4846aad919 --- /dev/null +++ b/bsp/mipssim/drivers/SConscript @@ -0,0 +1,10 @@ +from building import * + +cwd = GetCurrentDir() +src = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S') + +CPPPATH = [cwd] + +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/mipssim/drivers/board.c b/bsp/mipssim/drivers/board.c new file mode 100644 index 0000000000000000000000000000000000000000..a0ef220bc7a00354832e8d218ef06bbf56c3da6a --- /dev/null +++ b/bsp/mipssim/drivers/board.c @@ -0,0 +1,113 @@ +/* + * Copyright (c) 2006-2019, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-12-04 Jiaxun Yang Initial version + */ + +/** + * @addtogroup mipssim + */ + +/*@{*/ + +#include +#include + +#include "mips_regs.h" +#include "exception.h" +#include "drv_uart.h" + +#define CPU_HZ (100 * 1000 * 1000) +#define RT_HW_HEAP_END (0x80000000 + 64 * 1024 * 1024) + +extern unsigned char __bss_end; + +/** + * this function will reset CPU + * + */ +void rt_hw_cpu_reset(void) +{ + rt_kprintf("reboot system...\n"); + while (1); +} + +/** + * this function will shutdown CPU + * + */ +void rt_hw_cpu_shutdown(void) +{ + rt_kprintf("shutdown...\n"); + + while (1); +} + + +/** + * This is the timer interrupt service routine. + */ +void rt_hw_timer_handler(void) +{ + unsigned int count; + + count = read_c0_compare(); + write_c0_compare(count); + write_c0_count(0); + /* increase a OS tick */ + rt_tick_increase(); +} + +/** + * This function will initial OS timer + */ +void rt_hw_timer_init(void) +{ + write_c0_compare(CPU_HZ/2/RT_TICK_PER_SECOND); + write_c0_count(0); + mips_unmask_cpu_irq(7); +} + +/** + * Board level initialization + */ +void rt_hw_board_init(void) +{ + rt_hw_exception_init(); + + /* init hardware interrupt */ + rt_hw_interrupt_init(); + + #ifdef RT_USING_FPU + /* init hardware fpu */ + rt_hw_fpu_init(); + #endif + +#ifdef RT_USING_SERIAL + /* init hardware UART device */ + rt_hw_uart_init(); + /* set console device */ + rt_console_set_device("uart"); +#endif + +#ifdef RT_USING_HEAP + rt_system_heap_init((void*)&__bss_end, (void*)RT_HW_HEAP_END); +#endif + + /* init operating system timer */ + rt_hw_timer_init(); + + +#ifdef RT_USING_COMPONENTS_INIT + rt_components_board_init(); +#endif + + rt_kprintf("Current SR: 0x%08x\n", read_c0_status()); + +} + +/*@}*/ diff --git a/bsp/mipssim/drivers/cpuinit_gcc.S b/bsp/mipssim/drivers/cpuinit_gcc.S new file mode 100644 index 0000000000000000000000000000000000000000..611f68235253cfbaf905b9dda5ca804a0cc4e7f4 --- /dev/null +++ b/bsp/mipssim/drivers/cpuinit_gcc.S @@ -0,0 +1,26 @@ +/* + * Copyright (c) 2006-2019, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-12-04 Jiaxun Yang Initial version + */ + +#ifndef __ASSEMBLY__ +#define __ASSEMBLY__ +#endif + +#include + + .section ".text", "ax" + .set noreorder + + .globl rt_cpu_early_init +rt_cpu_early_init: + mfc0 t0, CP0_CONFIG + ori t0, 3 + mtc0 t0, CP0_CONFIG + ehb + jr ra \ No newline at end of file diff --git a/bsp/mipssim/drivers/drv_uart.c b/bsp/mipssim/drivers/drv_uart.c new file mode 100644 index 0000000000000000000000000000000000000000..a8e7abee591ea3a6c6a9afdecf56750144953f57 --- /dev/null +++ b/bsp/mipssim/drivers/drv_uart.c @@ -0,0 +1,178 @@ +/* + * Copyright (c) 2006-2019, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-12-04 Jiaxun Yang Initial version + */ + +/** + * @addtogroup mipssim + */ + +/*@{*/ + +#include +#include +#include +#include "drv_uart.h" + +#define TRUE 1 +#define FALSE 0 + +struct rt_uart_mipssim +{ + void *base; + rt_uint32_t IRQ; +}; + +static rt_err_t mipssim_uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg) +{ + struct rt_uart_mipssim *uart_dev = RT_NULL; + + RT_ASSERT(serial != RT_NULL); + RT_ASSERT(cfg != RT_NULL); + + uart_dev = (struct rt_uart_mipssim *)serial->parent.user_data; + + UART_IER(uart_dev->base) = 0; /* clear interrupt */ + UART_FCR(uart_dev->base) = 0xc1; /* reset UART Rx/Tx */ + /* set databits, stopbits and parity. (8-bit data, 1 stopbit, no parity) */ + UART_LCR(uart_dev->base) = 0x3; + UART_MCR(uart_dev->base) = 0x3; + UART_LSR(uart_dev->base) = 0x60; + UART_MSR(uart_dev->base) = 0xb0; + + return RT_EOK; +} + +static rt_err_t mipssim_uart_control(struct rt_serial_device *serial, int cmd, void *arg) +{ + struct rt_uart_mipssim *uart_dev = RT_NULL; + + RT_ASSERT(serial != RT_NULL); + uart_dev = (struct rt_uart_mipssim *)serial->parent.user_data; + + switch (cmd) + { + case RT_DEVICE_CTRL_CLR_INT: /* Disable RX IRQ */ + rt_hw_interrupt_mask(uart_dev->IRQ); + break; + + case RT_DEVICE_CTRL_SET_INT: /* Enable RX IRQ */ + rt_hw_interrupt_umask(uart_dev->IRQ); + UART_IER(uart_dev->base) |= (IER_IRxE|IER_ILE); + break; + + default: + break; + } + + return RT_EOK; + +} + +static rt_bool_t uart_is_transmit_empty(struct rt_uart_mipssim *uart_dev) +{ + unsigned char status = UART_LSR(uart_dev->base); + + if (status & (UARTLSR_TE | UARTLSR_TFE)) + { + return TRUE; + } + else + { + return FALSE; + } +} + +static int mipssim_uart_putc(struct rt_serial_device *serial, char c) +{ + struct rt_uart_mipssim *uart_dev = RT_NULL; + + RT_ASSERT(serial != RT_NULL); + + uart_dev = (struct rt_uart_mipssim *)serial->parent.user_data; + + while (FALSE == uart_is_transmit_empty(uart_dev)) + ; + + UART_DAT(uart_dev->base) = c; + + return 1; +} + +static int mipssim_uart_getc(struct rt_serial_device *serial) +{ + struct rt_uart_mipssim *uart_dev = RT_NULL; + + RT_ASSERT(serial != RT_NULL); + + uart_dev = (struct rt_uart_mipssim *)serial->parent.user_data; + + if (LSR_RXRDY & UART_LSR(uart_dev->base)) + { + return UART_DAT(uart_dev->base); + } + + return -1; +} + +/* UART interrupt handler */ +static void uart_irq_handler(int vector, void *param) +{ + struct rt_serial_device *serial = (struct rt_serial_device *)param; + struct rt_uart_mipssim *uart_dev = RT_NULL; + + RT_ASSERT(serial != RT_NULL); + + uart_dev = (struct rt_uart_mipssim *)serial->parent.user_data; + unsigned char iir = UART_IIR(uart_dev->base); + + /* Find out interrupt reason */ + if ((IIR_RXTOUT & iir) || (IIR_RXRDY & iir)) + { + rt_interrupt_enter(); + rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND); + rt_interrupt_leave(); + } + +} + +static const struct rt_uart_ops mipssim_uart_ops = +{ + mipssim_uart_configure, + mipssim_uart_control, + mipssim_uart_putc, + mipssim_uart_getc, +}; + +struct rt_uart_mipssim uart_dev0 = +{ + (void *)UART0_BASE, + 4, +}; +struct rt_serial_device serial; + + +void rt_hw_uart_init(void) +{ + struct rt_uart_mipssim *uart; + struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT; + + uart = &uart_dev0; + + serial.ops = &mipssim_uart_ops; + serial.config = config; + + rt_hw_interrupt_install(uart->IRQ, uart_irq_handler, &serial, "UART"); + + /* register UART device */ + rt_hw_serial_register(&serial, + "uart", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, + uart); +} +/*@}*/ diff --git a/bsp/mipssim/drivers/drv_uart.h b/bsp/mipssim/drivers/drv_uart.h new file mode 100644 index 0000000000000000000000000000000000000000..0501337a396a46ea81c6993cb1756aeea476278e --- /dev/null +++ b/bsp/mipssim/drivers/drv_uart.h @@ -0,0 +1,114 @@ +/* + * Copyright (c) 2006-2019, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-12-04 Jiaxun Yang Initial version + */ + +#ifndef _MIPSSIM_DRV_UART_H__ +#define _MIPSSIM_DRV_UART_H__ + +#include "mipssim.h" +#include + +/* UART registers */ +#define UART_DAT(base) HWREG8(base + 0x00) +#define UART_IER(base) HWREG8(base + 0x01) +#define UART_IIR(base) HWREG8(base + 0x02) +#define UART_FCR(base) HWREG8(base + 0x02) +#define UART_LCR(base) HWREG8(base + 0x03) +#define UART_MCR(base) HWREG8(base + 0x04) +#define UART_LSR(base) HWREG8(base + 0x05) +#define UART_MSR(base) HWREG8(base + 0x06) + +#define UART_LSB(base) HWREG8(base + 0x00) +#define UART_MSB(base) HWREG8(base + 0x01) + +/* interrupt enable register */ +#define IER_IRxE 0x1 /* 接收有效数据中断使能 */ +#define IER_ITxE 0x2 /* 传输保存寄存器为空中断使能 */ +#define IER_ILE 0x4 /* 接收器线路状态中断使能 */ +#define IER_IME 0x8 /* Modem状态中断使能 */ + +/* interrupt identification register */ +#define IIR_IMASK 0xf /* mask */ +#define IIR_RXTOUT 0xc /* receive timeout */ +#define IIR_RLS 0x6 /* receive line status */ +#define IIR_RXRDY 0x4 /* receive ready */ +#define IIR_TXRDY 0x2 /* transmit ready */ +#define IIR_NOPEND 0x1 /* nothing */ +#define IIR_MLSC 0x0 /* modem status */ +#define IIR_FIFO_MASK 0xc0 /* set if FIFOs are enabled */ + +/* fifo control register */ +#define FIFO_ENABLE 0x01 /* enable fifo */ +#define FIFO_RCV_RST 0x02 /* reset receive fifo */ +#define FIFO_XMT_RST 0x04 /* reset transmit fifo */ +#define FIFO_DMA_MODE 0x08 /* enable dma mode */ +#define FIFO_TRIGGER_1 0x00 /* trigger at 1 char */ +#define FIFO_TRIGGER_4 0x40 /* trigger at 4 chars */ +#define FIFO_TRIGGER_8 0x80 /* trigger at 8 chars */ +#define FIFO_TRIGGER_14 0xc0 /* trigger at 14 chars */ + +// 线路控制寄存器 +/* character format control register */ +#define CFCR_DLAB 0x80 /* divisor latch */ +#define CFCR_SBREAK 0x40 /* send break */ +#define CFCR_PZERO 0x30 /* zero parity */ +#define CFCR_PONE 0x20 /* one parity */ +#define CFCR_PEVEN 0x10 /* even parity */ +#define CFCR_PODD 0x00 /* odd parity */ +#define CFCR_PENAB 0x08 /* parity enable */ +#define CFCR_STOPB 0x04 /* 2 stop bits */ +#define CFCR_8BITS 0x03 /* 8 data bits */ +#define CFCR_7BITS 0x02 /* 7 data bits */ +#define CFCR_6BITS 0x01 /* 6 data bits */ +#define CFCR_5BITS 0x00 /* 5 data bits */ + +/* modem control register */ +#define MCR_LOOPBACK 0x10 /* loopback */ +#define MCR_IENABLE 0x08 /* output 2 = int enable */ +#define MCR_DRS 0x04 /* output 1 = xxx */ +#define MCR_RTS 0x02 /* enable RTS */ +#define MCR_DTR 0x01 /* enable DTR */ + +/* line status register */ +#define LSR_RCV_FIFO 0x80 /* error in receive fifo */ +#define LSR_TSRE 0x40 /* transmitter empty */ +#define LSR_TXRDY 0x20 /* transmitter ready */ +#define LSR_BI 0x10 /* break detected */ +#define LSR_FE 0x08 /* framing error */ +#define LSR_PE 0x04 /* parity error */ +#define LSR_OE 0x02 /* overrun error */ +#define LSR_RXRDY 0x01 /* receiver ready */ +#define LSR_RCV_MASK 0x1f + + +/* UART interrupt enable register value */ +#define UARTIER_IME (1 << 3) +#define UARTIER_ILE (1 << 2) +#define UARTIER_ITXE (1 << 1) +#define UARTIER_IRXE (1 << 0) + +/* UART line control register value */ +#define UARTLCR_DLAB (1 << 7) +#define UARTLCR_BCB (1 << 6) +#define UARTLCR_SPB (1 << 5) +#define UARTLCR_EPS (1 << 4) +#define UARTLCR_PE (1 << 3) +#define UARTLCR_SB (1 << 2) + +/* UART line status register value */ +#define UARTLSR_ERROR (1 << 7) +#define UARTLSR_TE (1 << 6) +#define UARTLSR_TFE (1 << 5) +#define UARTLSR_BI (1 << 4) +#define UARTLSR_FE (1 << 3) +#define UARTLSR_PE (1 << 2) +#define UARTLSR_OE (1 << 1) +#define UARTLSR_DR (1 << 0) + +#endif \ No newline at end of file diff --git a/bsp/mipssim/drivers/interrupt.c b/bsp/mipssim/drivers/interrupt.c new file mode 100644 index 0000000000000000000000000000000000000000..accd3543ad21873d391e25b20ba8d0d52fd81435 --- /dev/null +++ b/bsp/mipssim/drivers/interrupt.c @@ -0,0 +1,89 @@ +/* + * Copyright (c) 2006-2019, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-12-04 Jiaxun Yang Initial version + */ + +/** + * @addtogroup mipssim + */ + +/*@{*/ + +#include +#include +#include + +#define MAX_INTR 32 + +static struct rt_irq_desc irq_handle_table[MAX_INTR]; + +static void rt_hw_interrupt_handler(int vector, void *param) +{ + rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); +} + +/** + * This function will initialize hardware interrupt + */ +void rt_hw_interrupt_init(void) +{ + rt_uint32_t idx; + rt_memset(irq_handle_table, 0x00, sizeof(irq_handle_table)); + for (idx = 0; idx < MAX_INTR; idx ++) + { + irq_handle_table[idx].handler = rt_hw_interrupt_handler; + } +} + +rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, + void *param, const char *name) +{ + rt_isr_handler_t old_handler = RT_NULL; + + if (vector >= 0 && vector < MAX_INTR) + { + old_handler = irq_handle_table[vector].handler; + +#ifdef RT_USING_INTERRUPT_INFO + rt_strncpy(irq_handle_table[vector].name, name, RT_NAME_MAX); +#endif /* RT_USING_INTERRUPT_INFO */ + irq_handle_table[vector].handler = handler; + irq_handle_table[vector].param = param; + } + + return old_handler; +} + +void rt_hw_timer_handler(void); + +void rt_do_mips_cpu_irq(rt_uint32_t ip) +{ + void *param; + rt_isr_handler_t irq_func; + + if (ip == 7) { + rt_hw_timer_handler(); + } else { + irq_func = irq_handle_table[ip].handler; + param = irq_handle_table[ip].param; + + /* do interrupt */ + irq_func(ip, param); + } +} + +void rt_hw_interrupt_umask(int irq) +{ + mips_unmask_cpu_irq(irq); +} + +void rt_hw_interrupt_mask(int irq) +{ + mips_mask_cpu_irq(irq); +} +/*@}*/ diff --git a/bsp/mipssim/drivers/mipssim.h b/bsp/mipssim/drivers/mipssim.h new file mode 100644 index 0000000000000000000000000000000000000000..03669ab0ea00955d879550546f9df2b5a394ffb4 --- /dev/null +++ b/bsp/mipssim/drivers/mipssim.h @@ -0,0 +1,14 @@ +#ifndef _MIPSSIM_H__ +#define _MIPSSIM_H__ + +#include + +#define ISA_MMIO_BASE 0x1fd00000 + +#define UART0_ISA_OFF 0x3f8 +#define UART0_BASE KSEG1ADDR(ISA_MMIO_BASE + UART0_ISA_OFF) + +void rt_hw_timer_handler(void); +void rt_hw_uart_init(void); + +#endif \ No newline at end of file diff --git a/bsp/mipssim/mipssim_ram.lds b/bsp/mipssim/mipssim_ram.lds new file mode 100644 index 0000000000000000000000000000000000000000..196b6e8e0254faef49127b8db1ac7215ddb486fd --- /dev/null +++ b/bsp/mipssim/mipssim_ram.lds @@ -0,0 +1,141 @@ +/* + * Copyright (c) 2006-2019, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-12-04 Jiaxun Yang Initial version + */ + +OUTPUT_ARCH(mips) +GROUP(-lgcc -lc) + +ENTRY(_start) +SECTIONS +{ + . = 0x80000000 ; + .text : + { + __ebase_entry = .; + KEEP(*(.exc_vectors)) + __ebase_end = .; + start = .; + *(.start); + . = ALIGN(4); + *(.text) + *(.text.*) + *(.rodata) + *(.rodata.*) + *(.rodata1) + *(.rodata1.*) + + + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(4); + + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + . = ALIGN(4); + + . = ALIGN(4); + __rt_utest_tc_tab_start = .; + KEEP(*(UtestTcTab)) + __rt_utest_tc_tab_end = .; + . = ALIGN(4); + } + + .eh_frame_hdr : + { + *(.eh_frame_hdr) + *(.eh_frame_entry) + } + .eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) } + + . = ALIGN(4); + .data : + { + *(.data) + *(.data.*) + + *(.data1) + *(.data1.*) + + . = ALIGN(8); + _gp = ABSOLUTE(.); /* Base of small data */ + + *(.sdata) + *(.sdata.*) + } + + .stack : + { + . = ALIGN(8); + _system_stack_start = .; + . = . + 0x1000; + _system_stack = .; + } + + .sbss : + { + __bss_start = .; + *(.sbss) + *(.sbss.*) + *(.dynsbss) + *(.scommon) + } + + .bss : + { + *(.bss) + *(.bss.*) + *(.dynbss) + *(COMMON) + __bss_end = .; + } + _end = .; + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + * Symbols in the DWARF debugging sections are relative to the beginning + * of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } +} diff --git a/bsp/mipssim/rtconfig.h b/bsp/mipssim/rtconfig.h new file mode 100644 index 0000000000000000000000000000000000000000..6b253ec882f2d679e6acb99d12c9dcd1ae3fdd44 --- /dev/null +++ b/bsp/mipssim/rtconfig.h @@ -0,0 +1,160 @@ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ + +/* Automatically generated file; DO NOT EDIT. */ +/* RT-Thread Configuration */ + +/* RT-Thread Kernel */ + + +#define RT_NAME_MAX 8 +#define RT_ALIGN_SIZE 4 +#define RT_THREAD_PRIORITY_32 +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 100 +#define RT_USING_OVERFLOW_CHECK +#define RT_USING_HOOK +#define RT_USING_IDLE_HOOK +#define RT_IDLE_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 2048 +#define RT_USING_TIMER_SOFT +#define RT_TIMER_THREAD_PRIO 4 +#define RT_TIMER_THREAD_STACK_SIZE 2048 +#define RT_DEBUG + +/* Inter-Thread communication */ + +#define RT_USING_SEMAPHORE +#define RT_USING_MUTEX +#define RT_USING_EVENT +#define RT_USING_MAILBOX +#define RT_USING_MESSAGEQUEUE + +/* Memory Management */ + +#define RT_USING_MEMPOOL +#define RT_USING_SMALL_MEM +#define RT_USING_HEAP + +/* Kernel Device Object */ + +#define RT_USING_DEVICE +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 512 +#define RT_CONSOLE_DEVICE_NAME "uart" +#define RT_VER_NUM 0x40002 +#define ARCH_MIPS + +/* RT-Thread Components */ + +#define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 2048 +#define RT_MAIN_THREAD_PRIORITY 10 + +/* C++ features */ + + +/* Command shell */ + +#define RT_USING_FINSH +#define FINSH_THREAD_NAME "tshell" +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 5 +#define FINSH_USING_SYMTAB +#define FINSH_USING_DESCRIPTION +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 4096 +#define FINSH_CMD_SIZE 80 +#define FINSH_USING_MSH +#define FINSH_USING_MSH_DEFAULT +#define FINSH_ARG_MAX 10 + +/* Device virtual file system */ + + +/* Device Drivers */ + +#define RT_USING_DEVICE_IPC +#define RT_PIPE_BUFSZ 512 +#define RT_USING_SERIAL +#define RT_SERIAL_USING_DMA +#define RT_SERIAL_RB_BUFSZ 64 + +/* Using USB */ + + +/* POSIX layer and C standard library */ + +#define RT_USING_LIBC +#define RT_USING_PTHREADS +#define PTHREAD_NUM_MAX 8 + +/* Network */ + +/* Socket abstraction layer */ + + +/* Network interface device */ + + +/* light weight TCP/IP stack */ + + +/* AT commands */ + + +/* VBUS(Virtual Software BUS) */ + + +/* Utilities */ + +#define RT_USING_UTEST +#define UTEST_THR_STACK_SIZE 4096 +#define UTEST_THR_PRIORITY 20 + +/* RT-Thread MIPS CPU */ + + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + + +/* Wi-Fi */ + +/* Marvell WiFi */ + + +/* Wiced WiFi */ + + +/* IoT Cloud */ + + +/* security packages */ + + +/* language packages */ + + +/* multimedia packages */ + + +/* tools packages */ + + +/* system packages */ + + +/* peripheral libraries and drivers */ + + +/* miscellaneous packages */ + + +/* samples: kernel and components samples */ + +#define MIPSSIM + +#endif diff --git a/bsp/mipssim/rtconfig.py b/bsp/mipssim/rtconfig.py new file mode 100644 index 0000000000000000000000000000000000000000..ac3d425d6c5e4bd9e1349631a695784e304c35a4 --- /dev/null +++ b/bsp/mipssim/rtconfig.py @@ -0,0 +1,61 @@ +import os + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = '../..' + +# CPU options +ARCH='mips' +CPU ='common' + +# toolchains options +CROSS_TOOL = 'gcc' + +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') + +if CROSS_TOOL == 'gcc': + PLATFORM = 'gcc' + EXEC_PATH = "/opt/mips-2016.05/bin" +# EXEC_PATH = r'D:\mgc\embedded\codebench\bin' +else: + print('================ERROR===========================') + print('Not support %s yet!' % CROSS_TOOL) + print('=================================================') + exit(0) + +if os.getenv('RTT_EXEC_PATH'): + EXEC_PATH = os.getenv('RTT_EXEC_PATH') + +BUILD = 'debug' + +PREFIX = 'mips-sde-elf-' +CC = PREFIX + 'gcc' +AS = PREFIX + 'gcc' +AR = PREFIX + 'ar' +LINK = PREFIX + 'gcc' +TARGET_EXT = 'elf' +SIZE = PREFIX + 'size' +OBJDUMP = PREFIX + 'objdump' +OBJCPY = PREFIX + 'objcopy' +READELF = PREFIX + 'readelf' + +DEVICE = ' -mips32r2 -msoft-float -mfp32' +CFLAGS = DEVICE + ' -EL -G0 -mno-abicalls -fno-pic -fno-builtin -fno-exceptions -ffunction-sections -fomit-frame-pointer' +AFLAGS = ' -c' + DEVICE + ' -EL -fno-pic -fno-builtin -mno-abicalls -x assembler-with-cpp' +LFLAGS = DEVICE + ' -nostartfiles -EL -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T mipssim_ram.lds' +CXXFLAGS = CFLAGS + +CPATH = '' +LPATH = '' + +if BUILD == 'debug': + CFLAGS += ' -O0 -gdwarf-2' + AFLAGS += ' -gdwarf-2' +else: + CFLAGS += ' -O2' + +DUMP_ACTION = OBJDUMP + ' -D -S $TARGET > rtt.asm\n' +READELF_ACTION = READELF + ' -a $TARGET > rtt.map\n' +POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'