From 017d2b766270fd88786a6b8d3dc736bca5e27878 Mon Sep 17 00:00:00 2001 From: qiuyiuestc Date: Sat, 26 Dec 2009 12:40:15 +0000 Subject: [PATCH] support GCC compiler for LM3S platform git-svn-id: https://rt-thread.googlecode.com/svn/trunk@235 bbd45198-f89e-11dd-88c7-29a3b14d5316 --- bsp/lm3s/lm3s_rom.sct | 15 +++ bsp/lm3s/rtconfig.py | 24 +--- libcpu/arm/lm3s/fault_gcc.S | 31 +++++ libcpu/arm/lm3s/start_gcc.c | 242 ------------------------------------ libcpu/arm/lm3s/start_gcc.s | 195 +++++++++++++++++++++++++++++ 5 files changed, 243 insertions(+), 264 deletions(-) create mode 100644 bsp/lm3s/lm3s_rom.sct create mode 100644 libcpu/arm/lm3s/fault_gcc.S delete mode 100644 libcpu/arm/lm3s/start_gcc.c create mode 100644 libcpu/arm/lm3s/start_gcc.s diff --git a/bsp/lm3s/lm3s_rom.sct b/bsp/lm3s/lm3s_rom.sct new file mode 100644 index 0000000000..79a39c72e8 --- /dev/null +++ b/bsp/lm3s/lm3s_rom.sct @@ -0,0 +1,15 @@ +; ************************************************************* +; *** Scatter-Loading Description File generated by uVision *** +; ************************************************************* + +LR_IROM1 0x00000000 0x00040000 { ; load region size_region + ER_IROM1 0x00000000 0x00040000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + RW_IRAM1 0x20000000 0x00010000 { ; RW data + .ANY (+RW +ZI) + } +} + diff --git a/bsp/lm3s/rtconfig.py b/bsp/lm3s/rtconfig.py index 190566216e..334745dace 100644 --- a/bsp/lm3s/rtconfig.py +++ b/bsp/lm3s/rtconfig.py @@ -21,8 +21,6 @@ CPU='lm3s' #EXEC_PATH = 'E:/Program Files/CodeSourcery/Sourcery G++ Lite/bin' PLATFORM = 'armcc' EXEC_PATH = 'E:/Keil' -#PLATFORM = 'iar' -#EXEC_PATH = 'E:/Program Files/IAR Systems/Embedded Workbench 5.4/' BUILD = 'debug' if PLATFORM == 'gcc': @@ -40,7 +38,7 @@ if PLATFORM == 'gcc': DEVICE = ' -mcpu=cortex-m3 -mthumb' CFLAGS = DEVICE + ' -Dsourcerygxx' + ' -DRT_USING_MINILIBC' AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp' - LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread-lm3s.map,-cref,-u,ResetISR -T lm3s_rom.ld' + LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread-lm3s.map,-cref,-u,Reset_Handler -T lm3s_rom.ld' CPATH = '' LPATH = '' @@ -65,7 +63,7 @@ elif PLATFORM == 'armcc': DEVICE = ' --device DARMSTM' CFLAGS = DEVICE + ' --apcs=interwork' AFLAGS = DEVICE - LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers --list rtthread-stm32.map --scatter stm32_rom.sct' + LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers --list rtthread-lm3s.map --scatter lm3s_rom.sct' CFLAGS += ' -I' + EXEC_PATH + '/ARM/RV31/INC' LFLAGS += ' --libpath ' + EXEC_PATH + '/ARM/RV31/LIB' @@ -82,21 +80,3 @@ elif PLATFORM == 'armcc': if RT_USING_FINSH: LFLAGS += ' --keep __fsym_* --keep __vsym_*' POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' - -elif PLATFORM == 'iar': - # toolchains - CC = 'iccarm' - AS = 'iasmarm' - AR = 'iarchive' - LINK = 'ilinkarm' - TARGET_EXT = 'out' - - DEVICE = ' --cpu DARMSTM --thumb' - - CFLAGS = '' - AFLAGS = '' - LFLAGS = ' --config stm32f10x_flash.icf' - - EXEC_PATH += '/arm/bin/' - RT_USING_MINILIBC = False - POST_ACTION = '' diff --git a/libcpu/arm/lm3s/fault_gcc.S b/libcpu/arm/lm3s/fault_gcc.S new file mode 100644 index 0000000000..fc8f1d79e4 --- /dev/null +++ b/libcpu/arm/lm3s/fault_gcc.S @@ -0,0 +1,31 @@ +/* + * File : fault_gcc.S + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2009, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2009-10-11 Bernard first version + */ + +.cpu cortex-m3 +.fpu softvfp +.syntax unified +.thumb +.text + +.global rt_hw_hard_fault +.type rt_hw_hard_fault, %function +rt_hw_hard_fault: + /* get current context */ + MRS r0, psp /* get fault thread stack pointer */ + PUSH {lr} + BL rt_hw_hard_fault_exception + POP {lr} + + ORR lr, lr, #0x04 + BX lr diff --git a/libcpu/arm/lm3s/start_gcc.c b/libcpu/arm/lm3s/start_gcc.c deleted file mode 100644 index fa1398e35c..0000000000 --- a/libcpu/arm/lm3s/start_gcc.c +++ /dev/null @@ -1,242 +0,0 @@ -//***************************************************************************** -// -// startup.c - Boot code for Stellaris. -// -// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved. -// -// Software License Agreement -// -// Luminary Micro, Inc. (LMI) is supplying this software for use solely and -// exclusively on LMI's microcontroller products. -// -// The software is owned by LMI and/or its suppliers, and is protected under -// applicable copyright laws. All rights are reserved. You may not combine -// this software with "viral" open-source software in order to form a larger -// program. Any use in violation of the foregoing restrictions may subject -// the user to criminal sanctions under applicable laws, as well as to civil -// liability for the breach of the terms and conditions of this license. -// -// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -// -// This is part of revision 2752 of the Stellaris Peripheral Driver Library. -// -//***************************************************************************** - -//***************************************************************************** -// -// Forward declaration of the default fault handlers. -// -//***************************************************************************** -void ResetISR(void); -static void NmiSR(void); -static void FaultISR(void); -static void IntDefaultHandler(void); - -//***************************************************************************** -// -// The entry point for the application. -// -//***************************************************************************** -extern int main(void); - -//***************************************************************************** -// -// Reserve space for the system stack. -// -//***************************************************************************** -#ifndef STACK_SIZE -#define STACK_SIZE 64 -#endif -static unsigned long pulStack[STACK_SIZE]; - -//***************************************************************************** -// -// The minimal vector table for a Cortex M3. Note that the proper constructs -// must be placed on this to ensure that it ends up at physical address -// 0x0000.0000. -// -//***************************************************************************** -__attribute__ ((section(".isr_vector"))) -void (* const g_pfnVectors[])(void) = -{ - (void (*)(void))((unsigned long)pulStack + sizeof(pulStack)), - // The initial stack pointer - ResetISR, // The reset handler - NmiSR, // The NMI handler - FaultISR, // The hard fault handler - IntDefaultHandler, // The MPU fault handler - IntDefaultHandler, // The bus fault handler - IntDefaultHandler, // The usage fault handler - 0, // Reserved - 0, // Reserved - 0, // Reserved - 0, // Reserved - IntDefaultHandler, // SVCall handler - IntDefaultHandler, // Debug monitor handler - 0, // Reserved - IntDefaultHandler, // The PendSV handler - IntDefaultHandler, // The SysTick handler - IntDefaultHandler, // GPIO Port A - IntDefaultHandler, // GPIO Port B - IntDefaultHandler, // GPIO Port C - IntDefaultHandler, // GPIO Port D - IntDefaultHandler, // GPIO Port E - IntDefaultHandler, // UART0 Rx and Tx - IntDefaultHandler, // UART1 Rx and Tx - IntDefaultHandler, // SSI Rx and Tx - IntDefaultHandler, // I2C Master and Slave - IntDefaultHandler, // PWM Fault - IntDefaultHandler, // PWM Generator 0 - IntDefaultHandler, // PWM Generator 1 - IntDefaultHandler, // PWM Generator 2 - IntDefaultHandler, // Quadrature Encoder - IntDefaultHandler, // ADC Sequence 0 - IntDefaultHandler, // ADC Sequence 1 - IntDefaultHandler, // ADC Sequence 2 - IntDefaultHandler, // ADC Sequence 3 - IntDefaultHandler, // Watchdog timer - IntDefaultHandler, // Timer 0 subtimer A - IntDefaultHandler, // Timer 0 subtimer B - IntDefaultHandler, // Timer 1 subtimer A - IntDefaultHandler, // Timer 1 subtimer B - IntDefaultHandler, // Timer 2 subtimer A - IntDefaultHandler, // Timer 2 subtimer B - IntDefaultHandler, // Analog Comparator 0 - IntDefaultHandler, // Analog Comparator 1 - IntDefaultHandler, // Analog Comparator 2 - IntDefaultHandler, // System Control (PLL, OSC, BO) - IntDefaultHandler, // FLASH Control - IntDefaultHandler, // GPIO Port F - IntDefaultHandler, // GPIO Port G - IntDefaultHandler, // GPIO Port H - IntDefaultHandler, // UART2 Rx and Tx - IntDefaultHandler, // SSI1 Rx and Tx - IntDefaultHandler, // Timer 3 subtimer A - IntDefaultHandler, // Timer 3 subtimer B - IntDefaultHandler, // I2C1 Master and Slave - IntDefaultHandler, // Quadrature Encoder 1 - IntDefaultHandler, // CAN0 - IntDefaultHandler, // CAN1 - IntDefaultHandler, // CAN2 - IntDefaultHandler, // Ethernet - IntDefaultHandler, // Hibernate - IntDefaultHandler, // USB0 - IntDefaultHandler, // PWM Generator 3 - IntDefaultHandler, // uDMA Software Transfer - IntDefaultHandler // uDMA Error -}; - -//***************************************************************************** -// -// The following are constructs created by the linker, indicating where the -// the "data" and "bss" segments reside in memory. The initializers for the -// for the "data" segment resides immediately following the "text" segment. -// -//***************************************************************************** -extern unsigned long _etext; -extern unsigned long _sdata; -extern unsigned long _edata; -extern unsigned long _sbss; -extern unsigned long _ebss; - -//***************************************************************************** -// -// This is the code that gets called when the processor first starts execution -// following a reset event. Only the absolutely necessary set is performed, -// after which the application supplied main() routine is called. Any fancy -// actions (such as making decisions based on the reset cause register, and -// resetting the bits in that register) are left solely in the hands of the -// application. -// -//***************************************************************************** -void -ResetISR(void) -{ - unsigned long *pulSrc, *pulDest; - - // - // Copy the data segment initializers from flash to SRAM. - // - pulSrc = &_etext; - for(pulDest = &_sdata; pulDest < &_edata; ) - { - *pulDest++ = *pulSrc++; - } - - // - // Zero fill the bss segment. This is done with inline assembly since this - // will clear the value of pulDest if it is not kept in a register. - // - __asm(" ldr r0, =_sbss\n" - " ldr r1, =_ebss\n" - " mov r2, #0\n" - " .thumb_func\n" - "zero_loop:\n" - " cmp r0, r1\n" - " it lt\n" - " strlt r2, [r0], #4\n" - " blt zero_loop"); - - // - // Call the application's entry point. - // - main(); -} - -//***************************************************************************** -// -// This is the code that gets called when the processor receives a NMI. This -// simply enters an infinite loop, preserving the system state for examination -// by a debugger. -// -//***************************************************************************** -static void -NmiSR(void) -{ - // - // Enter an infinite loop. - // - while(1) - { - } -} - -//***************************************************************************** -// -// This is the code that gets called when the processor receives a fault -// interrupt. This simply enters an infinite loop, preserving the system state -// for examination by a debugger. -// -//***************************************************************************** -static void -FaultISR(void) -{ - // - // Enter an infinite loop. - // - while(1) - { - } -} - -//***************************************************************************** -// -// This is the code that gets called when the processor receives an unexpected -// interrupt. This simply enters an infinite loop, preserving the system state -// for examination by a debugger. -// -//***************************************************************************** -static void -IntDefaultHandler(void) -{ - // - // Go into an infinite loop. - // - while(1) - { - } -} diff --git a/libcpu/arm/lm3s/start_gcc.s b/libcpu/arm/lm3s/start_gcc.s new file mode 100644 index 0000000000..81bca5b719 --- /dev/null +++ b/libcpu/arm/lm3s/start_gcc.s @@ -0,0 +1,195 @@ +/** + ****************************************************************************** + * @file startup_stm32f10x_hd.s + * @author MCD Application Team + * @version V3.1.2 + * @date 09/28/2009 + * @brief STM32F10x High Density Devices vector table for RIDE7 toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address, + * - Configure external SRAM mounted on STM3210E-EVAL board + * to be used as data memory (optional, to be enabled by user) + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M3 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2009 STMicroelectronics

+ */ +.section .bss.init +.equ Stack_Size, 0x00000200 +.space Stack_Size +Initial_spTop: + + .syntax unified + .cpu cortex-m3 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +// .equ Initial_spTop, 0x20000200 +.equ BootRAM, 0xF1E0F85F +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: +/* restore original stack pointer */ + LDR r0, =Initial_spTop + MSR msp, r0 +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss +/* Call the application's entry point.*/ + bl main + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler + +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word Initial_spTop + .word Reset_Handler + .word Default_Handler //NMI_Handler + .word rt_hw_hard_fault + .word Default_Handler //MemManage_Handler + .word Default_Handler //BusFault_Handler + .word Default_Handler //UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word Default_Handler //SVC_Handler + .word Default_Handler //DebugMon_Handler + .word 0 + .word rt_hw_pend_sv + .word rt_hw_timer_handler + .word Default_Handler // GPIO Port A + .word Default_Handler // GPIO Port B + .word Default_Handler // GPIO Port C + .word Default_Handler // GPIO Port D + .word Default_Handler // GPIO Port E + .word rt_hw_uart_isr_1 // UART0 Rx and Tx + .word Default_Handler // UART1 Rx and Tx + .word Default_Handler // SSI Rx and Tx + .word Default_Handler // I2C Master and Slave + .word Default_Handler // PWM Fault + .word Default_Handler // PWM Generator 0 + .word Default_Handler // PWM Generator 1 + .word Default_Handler // PWM Generator 2 + .word Default_Handler // Quadrature Encoder + .word Default_Handler // ADC Sequence 0 + .word Default_Handler // ADC Sequence 1 + .word Default_Handler // ADC Sequence 2 + .word Default_Handler // ADC Sequence 3 + .word Default_Handler // Watchdog timer + .word Default_Handler // Timer 0 subtimer A + .word Default_Handler // Timer 0 subtimer B + .word Default_Handler // Timer 1 subtimer A + .word Default_Handler // Timer 1 subtimer B + .word Default_Handler // Timer 2 subtimer A + .word Default_Handler // Timer 2 subtimer B + .word Default_Handler // Analog Comparator 0 + .word Default_Handler // Analog Comparator 1 + .word Default_Handler // Analog Comparator 2 + .word Default_Handler // System Control (PLL, OSC, + .word Default_Handler // FLASH Control + .word Default_Handler // GPIO Port F + .word Default_Handler // GPIO Port G + .word Default_Handler // GPIO Port H + .word Default_Handler // UART2 Rx and Tx + .word Default_Handler // SSI1 Rx and Tx + .word Default_Handler // Timer 3 subtimer A + .word Default_Handler // Timer 3 subtimer B + .word Default_Handler // I2C1 Master and Slave + .word Default_Handler // Quadrature Encoder 1 + .word Default_Handler // CAN0 + .word Default_Handler // CAN1 + .word Default_Handler // CAN2 + .word luminaryif_isr // Ethernet + .word Default_Handler // Hibernate + .word Default_Handler // USB0 + .word Default_Handler // PWM Generator 3 + .word Default_Handler // uDMA Software Transfer + .word Default_Handler // uDMA Error -- GitLab