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体验新版 GitCode,发现更多精彩内容 >>
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f9e67335
编写于
6月 18, 2013
作者:
wuyangyong
浏览文件
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电子邮件补丁
差异文件
update libcpu/arm/cortex-m4: restore MSP.
上级
bee9103e
变更
3
显示空白变更内容
内联
并排
Showing
3 changed file
with
35 addition
and
8 deletion
+35
-8
libcpu/arm/cortex-m4/context_gcc.S
libcpu/arm/cortex-m4/context_gcc.S
+15
-6
libcpu/arm/cortex-m4/context_iar.S
libcpu/arm/cortex-m4/context_iar.S
+9
-0
libcpu/arm/cortex-m4/context_rvds.S
libcpu/arm/cortex-m4/context_rvds.S
+11
-2
未找到文件。
libcpu/arm/cortex-m4/context_gcc.S
浏览文件 @
f9e67335
...
@@ -11,6 +11,7 @@
...
@@ -11,6 +11,7 @@
*
Date
Author
Notes
*
Date
Author
Notes
*
2009
-
10
-
11
Bernard
first
version
*
2009
-
10
-
11
Bernard
first
version
*
2012
-
01
-
01
aozima
support
context
switch
load
/
store
FPU
register
.
*
2012
-
01
-
01
aozima
support
context
switch
load
/
store
FPU
register
.
*
2013
-
06
-
18
aozima
add
restore
MSP
feature
.
*/
*/
/**
/**
...
@@ -23,6 +24,7 @@
...
@@ -23,6 +24,7 @@
.
thumb
.
thumb
.
text
.
text
.
equ
SCB_VTOR
,
0xE000ED04
/*
Vector
Table
Offset
Register
*/
.
equ
NVIC_INT_CTRL
,
0xE000ED04
/*
interrupt
control
state
register
*/
.
equ
NVIC_INT_CTRL
,
0xE000ED04
/*
interrupt
control
state
register
*/
.
equ
NVIC_SYSPRI2
,
0xE000ED20
/*
system
priority
register
(
2
)
*/
.
equ
NVIC_SYSPRI2
,
0xE000ED20
/*
system
priority
register
(
2
)
*/
.
equ
NVIC_PENDSV_PRI
,
0x00FF0000
/*
PendSV
priority
value
(
lowest
)
*/
.
equ
NVIC_PENDSV_PRI
,
0x00FF0000
/*
PendSV
priority
value
(
lowest
)
*/
...
@@ -164,6 +166,13 @@ rt_hw_context_switch_to:
...
@@ -164,6 +166,13 @@ rt_hw_context_switch_to:
LDR
r1
,
=
NVIC_PENDSVSET
LDR
r1
,
=
NVIC_PENDSVSET
STR
r1
,
[
r0
]
STR
r1
,
[
r0
]
/
*
restore
MSP
*/
LDR
r0
,
=
SCB_VTOR
LDR
r0
,
[
r0
]
LDR
r0
,
[
r0
]
NOP
MSR
msp
,
r0
CPSIE
I
/*
enable
interrupts
at
processor
level
*/
CPSIE
I
/*
enable
interrupts
at
processor
level
*/
/
*
never
reach
here
!
*/
/
*
never
reach
here
!
*/
...
...
libcpu/arm/cortex-m4/context_iar.S
浏览文件 @
f9e67335
...
@@ -12,6 +12,7 @@
...
@@ -12,6 +12,7 @@
; * 2009-01-17 Bernard first version
; * 2009-01-17 Bernard first version
; * 2009-09-27 Bernard add protect when contex switch occurs
; * 2009-09-27 Bernard add protect when contex switch occurs
; * 2012-01-01 aozima support context switch load/store FPU register.
; * 2012-01-01 aozima support context switch load/store FPU register.
; * 2013-06-18 aozima add restore MSP feature.
; */
; */
;/**
;/**
...
@@ -19,6 +20,7 @@
...
@@ -19,6 +20,7 @@
; */
; */
;/*@{*/
;/*@{*/
SCB_VTOR
EQU
0xE000ED08
; Vector Table Offset Register
NVIC_INT_CTRL
EQU
0xE000ED04
; interrupt control state register
NVIC_INT_CTRL
EQU
0xE000ED04
; interrupt control state register
NVIC_SYSPRI2
EQU
0xE000ED20
; system priority register (2)
NVIC_SYSPRI2
EQU
0xE000ED20
; system priority register (2)
NVIC_PENDSV_PRI
EQU
0x00FF0000
; PendSV priority value (lowest)
NVIC_PENDSV_PRI
EQU
0x00FF0000
; PendSV priority value (lowest)
...
@@ -162,6 +164,13 @@ rt_hw_context_switch_to:
...
@@ -162,6 +164,13 @@ rt_hw_context_switch_to:
LDR
r1
,
=
NVIC_PENDSVSET
LDR
r1
,
=
NVIC_PENDSVSET
STR
r1
,
[
r0
]
STR
r1
,
[
r0
]
; restore MSP
LDR
r0
,
=
SCB_VTOR
LDR
r0
,
[
r0
]
LDR
r0
,
[
r0
]
NOP
MSR
msp
,
r0
CPSIE
I
; enable interrupts at processor level
CPSIE
I
; enable interrupts at processor level
; never reach here!
; never reach here!
...
...
libcpu/arm/cortex-m4/context_rvds.S
浏览文件 @
f9e67335
...
@@ -11,6 +11,7 @@
...
@@ -11,6 +11,7 @@
; * Date Author Notes
; * Date Author Notes
; * 2009-01-17 Bernard first version.
; * 2009-01-17 Bernard first version.
; * 2012-01-01 aozima support context switch load/store FPU register.
; * 2012-01-01 aozima support context switch load/store FPU register.
; * 2013-06-18 aozima add restore MSP feature.
; */
; */
;/**
;/**
...
@@ -18,6 +19,7 @@
...
@@ -18,6 +19,7 @@
; */
; */
;/*@{*/
;/*@{*/
SCB_VTOR
EQU
0xE000ED08
; Vector Table Offset Register
NVIC_INT_CTRL
EQU
0xE000ED04
; interrupt control state register
NVIC_INT_CTRL
EQU
0xE000ED04
; interrupt control state register
NVIC_SYSPRI2
EQU
0xE000ED20
; system priority register (2)
NVIC_SYSPRI2
EQU
0xE000ED20
; system priority register (2)
NVIC_PENDSV_PRI
EQU
0x00FF0000
; PendSV priority value (lowest)
NVIC_PENDSV_PRI
EQU
0x00FF0000
; PendSV priority value (lowest)
...
@@ -169,6 +171,13 @@ rt_hw_context_switch_to PROC
...
@@ -169,6 +171,13 @@ rt_hw_context_switch_to PROC
LDR
r1
,
=
NVIC_PENDSVSET
LDR
r1
,
=
NVIC_PENDSVSET
STR
r1
,
[
r0
]
STR
r1
,
[
r0
]
; restore MSP
LDR
r0
,
=
SCB_VTOR
LDR
r0
,
[
r0
]
LDR
r0
,
[
r0
]
NOP
MSR
msp
,
r0
; enable interrupts at processor level
; enable interrupts at processor level
CPSIE
I
CPSIE
I
...
...
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