From 012aa0e0d083c3e8c3ea67e02092d9a318567492 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=E6=9D=A8=E7=86=99?= Date: Thu, 15 Dec 2022 12:34:08 +0800 Subject: [PATCH] [bsp][lpc55sxx] add support for LPC55S16 (#6743) * [bsp][lpc55sxx] add support for LPC55S16 * [bsp][lpc55s16] formating LPC55S16 driver --- .../Libraries/LPC55S16/LPC55S16/LPC55S16.h | 33285 ++++++++++++++++ .../LPC55S16/LPC55S16/LPC55S16_features.h | 451 + .../LPC55S16/LPC55S16/arm/LPC551XX_256.FLM | Bin 0 -> 18064 bytes .../LPC55S16/LPC55S16/arm/LPC551XX_S_256.FLM | Bin 0 -> 18080 bytes .../LPC55S16/LPC55S16/arm/LPC55S16_flash.scf | 86 + .../LPC55S16/LPC55S16/arm/LPC55S16_ram.scf | 83 + .../LPC55S16/LPC55S16/arm/LPC55S1xx.dbgconf | 18 + .../LPC55S16/LPC55S16/arm/startup_LPC55S16.S | 812 + .../LPC55S16/LPC55S16/drivers/fsl_anactrl.c | 251 + .../LPC55S16/LPC55S16/drivers/fsl_anactrl.h | 377 + .../LPC55S16/LPC55S16/drivers/fsl_casper.c | 3433 ++ .../LPC55S16/LPC55S16/drivers/fsl_casper.h | 386 + .../LPC55S16/LPC55S16/drivers/fsl_cdog.c | 314 + .../LPC55S16/LPC55S16/drivers/fsl_cdog.h | 325 + .../LPC55S16/LPC55S16/drivers/fsl_clock.c | 2179 + .../LPC55S16/LPC55S16/drivers/fsl_clock.h | 1525 + .../LPC55S16/LPC55S16/drivers/fsl_cmp.c | 128 + .../LPC55S16/LPC55S16/drivers/fsl_cmp.h | 291 + .../LPC55S16/LPC55S16/drivers/fsl_common.c | 85 + .../LPC55S16/LPC55S16/drivers/fsl_common.h | 316 + .../LPC55S16/drivers/fsl_common_arm.c | 233 + .../LPC55S16/drivers/fsl_common_arm.h | 671 + .../LPC55S16/LPC55S16/drivers/fsl_crc.c | 185 + .../LPC55S16/LPC55S16/drivers/fsl_crc.h | 195 + .../LPC55S16/LPC55S16/drivers/fsl_ctimer.c | 577 + .../LPC55S16/LPC55S16/drivers/fsl_ctimer.h | 533 + .../LPC55S16/LPC55S16/drivers/fsl_dma.c | 1079 + .../LPC55S16/LPC55S16/drivers/fsl_dma.h | 892 + .../LPC55S16/LPC55S16/drivers/fsl_flexcomm.c | 412 + .../LPC55S16/LPC55S16/drivers/fsl_flexcomm.h | 64 + .../LPC55S16/LPC55S16/drivers/fsl_fro_calib.h | 61 + .../LPC55S16/LPC55S16/drivers/fsl_gint.c | 372 + .../LPC55S16/LPC55S16/drivers/fsl_gint.h | 222 + .../LPC55S16/LPC55S16/drivers/fsl_gpio.c | 317 + .../LPC55S16/LPC55S16/drivers/fsl_gpio.h | 364 + .../LPC55S16/LPC55S16/drivers/fsl_hashcrypt.c | 1726 + .../LPC55S16/LPC55S16/drivers/fsl_hashcrypt.h | 531 + .../LPC55S16/LPC55S16/drivers/fsl_i2c.c | 2085 + .../LPC55S16/LPC55S16/drivers/fsl_i2c.h | 1148 + .../LPC55S16/LPC55S16/drivers/fsl_i2c_dma.c | 652 + .../LPC55S16/LPC55S16/drivers/fsl_i2c_dma.h | 124 + .../LPC55S16/LPC55S16/drivers/fsl_i2s.c | 1198 + .../LPC55S16/LPC55S16/drivers/fsl_i2s.h | 513 + .../LPC55S16/LPC55S16/drivers/fsl_i2s_dma.c | 848 + .../LPC55S16/LPC55S16/drivers/fsl_i2s_dma.h | 235 + .../LPC55S16/LPC55S16/drivers/fsl_iap.c | 666 + .../LPC55S16/LPC55S16/drivers/fsl_iap.h | 528 + .../LPC55S16/LPC55S16/drivers/fsl_iap_ffr.h | 388 + .../LPC55S16/LPC55S16/drivers/fsl_iap_kbp.h | 245 + .../drivers/fsl_iap_skboot_authenticate.h | 77 + .../LPC55S16/LPC55S16/drivers/fsl_inputmux.c | 135 + .../LPC55S16/LPC55S16/drivers/fsl_inputmux.h | 97 + .../drivers/fsl_inputmux_connections.h | 481 + .../LPC55S16/LPC55S16/drivers/fsl_iocon.h | 215 + .../LPC55S16/LPC55S16/drivers/fsl_lpadc.c | 612 + .../LPC55S16/LPC55S16/drivers/fsl_lpadc.h | 964 + .../LPC55S16/LPC55S16/drivers/fsl_mcan.c | 1744 + .../LPC55S16/LPC55S16/drivers/fsl_mcan.h | 1056 + .../LPC55S16/LPC55S16/drivers/fsl_mrt.c | 152 + .../LPC55S16/LPC55S16/drivers/fsl_mrt.h | 366 + .../LPC55S16/LPC55S16/drivers/fsl_ostimer.c | 381 + .../LPC55S16/LPC55S16/drivers/fsl_ostimer.h | 273 + .../LPC55S16/LPC55S16/drivers/fsl_pint.c | 971 + .../LPC55S16/LPC55S16/drivers/fsl_pint.h | 581 + .../LPC55S16/LPC55S16/drivers/fsl_plu.c | 163 + .../LPC55S16/LPC55S16/drivers/fsl_plu.h | 374 + .../LPC55S16/LPC55S16/drivers/fsl_power.c | 1985 + .../LPC55S16/LPC55S16/drivers/fsl_power.h | 598 + .../LPC55S16/LPC55S16/drivers/fsl_prince.c | 1096 + .../LPC55S16/LPC55S16/drivers/fsl_prince.h | 522 + .../LPC55S16/LPC55S16/drivers/fsl_puf.c | 949 + .../LPC55S16/LPC55S16/drivers/fsl_puf.h | 335 + .../LPC55S16/LPC55S16/drivers/fsl_reset.c | 99 + .../LPC55S16/LPC55S16/drivers/fsl_reset.h | 267 + .../LPC55S16/LPC55S16/drivers/fsl_rng.c | 212 + .../LPC55S16/LPC55S16/drivers/fsl_rng.h | 104 + .../LPC55S16/LPC55S16/drivers/fsl_rtc.c | 322 + .../LPC55S16/LPC55S16/drivers/fsl_rtc.h | 493 + .../LPC55S16/LPC55S16/drivers/fsl_sctimer.c | 791 + .../LPC55S16/LPC55S16/drivers/fsl_sctimer.h | 1258 + .../LPC55S16/LPC55S16/drivers/fsl_spi.c | 1072 + .../LPC55S16/LPC55S16/drivers/fsl_spi.h | 746 + .../LPC55S16/LPC55S16/drivers/fsl_spi_dma.c | 568 + .../LPC55S16/LPC55S16/drivers/fsl_spi_dma.h | 208 + .../LPC55S16/LPC55S16/drivers/fsl_sysctl.c | 203 + .../LPC55S16/LPC55S16/drivers/fsl_sysctl.h | 186 + .../LPC55S16/LPC55S16/drivers/fsl_usart.c | 1206 + .../LPC55S16/LPC55S16/drivers/fsl_usart.h | 903 + .../LPC55S16/LPC55S16/drivers/fsl_usart_dma.c | 392 + .../LPC55S16/LPC55S16/drivers/fsl_usart_dma.h | 175 + .../LPC55S16/LPC55S16/drivers/fsl_utick.c | 230 + .../LPC55S16/LPC55S16/drivers/fsl_utick.h | 118 + .../LPC55S16/LPC55S16/drivers/fsl_wwdt.c | 275 + .../LPC55S16/LPC55S16/drivers/fsl_wwdt.h | 276 + .../LPC55S16/LPC55S16/fsl_device_registers.h | 36 + .../LPC55S16/LPC55S16/gcc/LPC55S16_flash.ld | 215 + .../LPC55S16/LPC55S16/gcc/LPC55S16_ram.ld | 214 + .../LPC55S16/LPC55S16/gcc/startup_LPC55S16.S | 895 + .../LPC55S16/LPC55S16/iar/LPC55S16_flash.icf | 101 + .../LPC55S16/LPC55S16/iar/LPC55S16_ram.icf | 98 + .../LPC55S16/LPC55S16/iar/startup_LPC55S16.s | 643 + .../LPC55S16/LPC55S16/system_LPC55S16.c | 392 + .../LPC55S16/LPC55S16/system_LPC55S16.h | 112 + bsp/lpc55sxx/Libraries/LPC55S16/SConscript | 51 + bsp/lpc55sxx/lpc55s16_nxp_evk/.config | 758 + bsp/lpc55sxx/lpc55s16_nxp_evk/Kconfig | 27 + bsp/lpc55sxx/lpc55s16_nxp_evk/README.md | 124 + bsp/lpc55sxx/lpc55s16_nxp_evk/SConscript | 14 + bsp/lpc55sxx/lpc55s16_nxp_evk/SConstruct | 67 + .../lpc55s16_nxp_evk/applications/SConscript | 19 + .../lpc55s16_nxp_evk/applications/main.c | 45 + .../lpc55s16_nxp_evk/applications/mnt.c | 32 + .../lpc55s16_nxp_evk/applications/tfm_ps.c | 110 + bsp/lpc55sxx/lpc55s16_nxp_evk/board/Kconfig | 224 + .../board/MCUX_Config/board/clock_config.c | 380 + .../board/MCUX_Config/board/clock_config.h | 173 + .../board/MCUX_Config/board/pin_mux.c | 118 + .../board/MCUX_Config/board/pin_mux.h | 61 + .../lpc55s16_nxp_evk/board/SConscript | 16 + bsp/lpc55sxx/lpc55s16_nxp_evk/board/board.c | 138 + bsp/lpc55sxx/lpc55s16_nxp_evk/board/board.h | 71 + .../board/linker_scripts/LPC55S16_flash.icf | 101 + .../board/linker_scripts/LPC55S16_flash.ld | 215 + .../board/linker_scripts/LPC55S16_flash.scf | 86 + .../lpc55s16_nxp_evk/figures/board.png | Bin 0 -> 453829 bytes .../lpc55s16_nxp_evk/figures/flash.png | Bin 0 -> 25990 bytes bsp/lpc55sxx/lpc55s16_nxp_evk/flashdebug.ini | 11 + bsp/lpc55sxx/lpc55s16_nxp_evk/project.uvoptx | 1208 + bsp/lpc55sxx/lpc55s16_nxp_evk/project.uvprojx | 842 + bsp/lpc55sxx/lpc55s16_nxp_evk/rtconfig.h | 216 + bsp/lpc55sxx/lpc55s16_nxp_evk/rtconfig.py | 162 + bsp/lpc55sxx/lpc55s16_nxp_evk/template.uvoptx | 179 + .../lpc55s16_nxp_evk/template.uvprojx | 400 + 133 files changed, 94194 insertions(+) create mode 100644 bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/LPC55S16.h create mode 100644 bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/LPC55S16_features.h create mode 100644 bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/arm/LPC551XX_256.FLM create mode 100644 bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/arm/LPC551XX_S_256.FLM create mode 100644 bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/arm/LPC55S16_flash.scf create mode 100644 bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/arm/LPC55S16_ram.scf create mode 100644 bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/arm/LPC55S1xx.dbgconf create mode 100644 bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/arm/startup_LPC55S16.S create mode 100644 bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_anactrl.c create mode 100644 bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_anactrl.h create mode 100644 bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_casper.c create mode 100644 bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_casper.h create mode 100644 bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_cdog.c create mode 100644 bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_cdog.h create mode 100644 bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_clock.c create mode 100644 bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_clock.h create mode 100644 bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_cmp.c create mode 100644 bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_cmp.h create mode 100644 bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_common.c create mode 100644 bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_common.h create mode 100644 bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_common_arm.c create mode 100644 bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_common_arm.h create mode 100644 bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_crc.c create mode 100644 bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_crc.h create mode 100644 bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_ctimer.c create mode 100644 bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_ctimer.h create mode 100644 bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_dma.c create mode 100644 bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_dma.h create mode 100644 bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_flexcomm.c create mode 100644 bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_flexcomm.h create mode 100644 bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_fro_calib.h create mode 100644 bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_gint.c create mode 100644 bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_gint.h create mode 100644 bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_gpio.c create mode 100644 bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_gpio.h create mode 100644 bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_hashcrypt.c create mode 100644 bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_hashcrypt.h create mode 100644 bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_i2c.c create mode 100644 bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_i2c.h create mode 100644 bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_i2c_dma.c create mode 100644 bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_i2c_dma.h create mode 100644 bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_i2s.c create mode 100644 bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_i2s.h create mode 100644 bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_i2s_dma.c create mode 100644 bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_i2s_dma.h create mode 100644 bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_iap.c create mode 100644 bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_iap.h create mode 100644 bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_iap_ffr.h create mode 100644 bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_iap_kbp.h create mode 100644 bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_iap_skboot_authenticate.h create mode 100644 bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_inputmux.c create mode 100644 bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_inputmux.h create mode 100644 bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_inputmux_connections.h create mode 100644 bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_iocon.h create mode 100644 bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_lpadc.c create mode 100644 bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_lpadc.h create mode 100644 bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_mcan.c create mode 100644 bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_mcan.h create mode 100644 bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_mrt.c create mode 100644 bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_mrt.h create mode 100644 bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_ostimer.c create mode 100644 bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_ostimer.h create mode 100644 bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_pint.c create mode 100644 bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_pint.h create mode 100644 bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_plu.c create mode 100644 bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_plu.h create mode 100644 bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_power.c create mode 100644 bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_power.h create mode 100644 bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_prince.c create mode 100644 bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_prince.h create mode 100644 bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_puf.c create mode 100644 bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_puf.h create mode 100644 bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_reset.c create mode 100644 bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_reset.h create mode 100644 bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_rng.c create mode 100644 bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_rng.h create mode 100644 bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_rtc.c create mode 100644 bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_rtc.h create mode 100644 bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_sctimer.c create mode 100644 bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_sctimer.h create mode 100644 bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_spi.c create mode 100644 bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_spi.h create mode 100644 bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_spi_dma.c create mode 100644 bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_spi_dma.h create mode 100644 bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_sysctl.c create mode 100644 bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_sysctl.h create mode 100644 bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_usart.c create mode 100644 bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_usart.h create mode 100644 bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_usart_dma.c create mode 100644 bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_usart_dma.h create mode 100644 bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_utick.c create mode 100644 bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_utick.h create mode 100644 bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_wwdt.c create mode 100644 bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_wwdt.h create mode 100644 bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/fsl_device_registers.h create mode 100644 bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/gcc/LPC55S16_flash.ld create mode 100644 bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/gcc/LPC55S16_ram.ld create mode 100644 bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/gcc/startup_LPC55S16.S create mode 100644 bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/iar/LPC55S16_flash.icf create mode 100644 bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/iar/LPC55S16_ram.icf create mode 100644 bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/iar/startup_LPC55S16.s create mode 100644 bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/system_LPC55S16.c create mode 100644 bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/system_LPC55S16.h create mode 100644 bsp/lpc55sxx/Libraries/LPC55S16/SConscript create mode 100644 bsp/lpc55sxx/lpc55s16_nxp_evk/.config create mode 100644 bsp/lpc55sxx/lpc55s16_nxp_evk/Kconfig create mode 100644 bsp/lpc55sxx/lpc55s16_nxp_evk/README.md create mode 100644 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/dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/LPC55S16.h @@ -0,0 +1,33285 @@ +/* +** ################################################################### +** Processors: LPC55S16JBD100 +** LPC55S16JBD64 +** LPC55S16JEV59 +** LPC55S16JEV98 +** +** Compilers: GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** Keil ARM C/C++ Compiler +** MCUXpresso Compiler +** +** Reference manual: LPC55S1x/LPC551x User manual Rev.0.6 15 November 2019 +** Version: rev. 1.1, 2019-12-03 +** Build: b220301 +** +** Abstract: +** CMSIS Peripheral Access Layer for LPC55S16 +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2022 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2018-08-22) +** Initial version based on v0.2UM +** - rev. 1.1 (2019-12-03) +** Initial version based on v0.6UM +** +** ################################################################### +*/ + +/*! + * @file LPC55S16.h + * @version 1.1 + * @date 2019-12-03 + * @brief CMSIS Peripheral Access Layer for LPC55S16 + * + * CMSIS Peripheral Access Layer for LPC55S16 + */ + +#ifndef _LPC55S16_H_ +#define _LPC55S16_H_ /**< Symbol preventing repeated inclusion */ + +/** Memory map major version (memory maps with equal major version number are + * compatible) */ +#define MCU_MEM_MAP_VERSION 0x0100U +/** Memory map minor version */ +#define MCU_MEM_MAP_VERSION_MINOR 0x0001U + + +/* ---------------------------------------------------------------------------- + -- Interrupt vector numbers + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Interrupt_vector_numbers Interrupt vector numbers + * @{ + */ + +/** Interrupt Number Definitions */ +#define NUMBER_OF_INT_VECTORS 77 /**< Number of interrupts in the Vector table */ + +typedef enum IRQn { + /* Auxiliary constants */ + NotAvail_IRQn = -128, /**< Not available device specific interrupt */ + + /* Core interrupts */ + NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< Cortex-M33 SV Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /**< Cortex-M33 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< Cortex-M33 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< Cortex-M33 Usage Fault Interrupt */ + SecureFault_IRQn = -9, /**< Cortex-M33 Secure Fault Interrupt */ + SVCall_IRQn = -5, /**< Cortex-M33 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< Cortex-M33 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< Cortex-M33 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< Cortex-M33 System Tick Interrupt */ + + /* Device specific interrupts */ + WDT_BOD_IRQn = 0, /**< Windowed watchdog timer, Brownout detect, Flash interrupt */ + DMA0_IRQn = 1, /**< DMA0 controller */ + GINT0_IRQn = 2, /**< GPIO group 0 */ + GINT1_IRQn = 3, /**< GPIO group 1 */ + PIN_INT0_IRQn = 4, /**< Pin interrupt 0 or pattern match engine slice 0 */ + PIN_INT1_IRQn = 5, /**< Pin interrupt 1or pattern match engine slice 1 */ + PIN_INT2_IRQn = 6, /**< Pin interrupt 2 or pattern match engine slice 2 */ + PIN_INT3_IRQn = 7, /**< Pin interrupt 3 or pattern match engine slice 3 */ + UTICK0_IRQn = 8, /**< Micro-tick Timer */ + MRT0_IRQn = 9, /**< Multi-rate timer */ + CTIMER0_IRQn = 10, /**< Standard counter/timer CTIMER0 */ + CTIMER1_IRQn = 11, /**< Standard counter/timer CTIMER1 */ + SCT0_IRQn = 12, /**< SCTimer/PWM */ + CTIMER3_IRQn = 13, /**< Standard counter/timer CTIMER3 */ + FLEXCOMM0_IRQn = 14, /**< Flexcomm Interface 0 (USART, SPI, I2C, I2S, FLEXCOMM) */ + FLEXCOMM1_IRQn = 15, /**< Flexcomm Interface 1 (USART, SPI, I2C, I2S, FLEXCOMM) */ + FLEXCOMM2_IRQn = 16, /**< Flexcomm Interface 2 (USART, SPI, I2C, I2S, FLEXCOMM) */ + FLEXCOMM3_IRQn = 17, /**< Flexcomm Interface 3 (USART, SPI, I2C, I2S, FLEXCOMM) */ + FLEXCOMM4_IRQn = 18, /**< Flexcomm Interface 4 (USART, SPI, I2C, I2S, FLEXCOMM) */ + FLEXCOMM5_IRQn = 19, /**< Flexcomm Interface 5 (USART, SPI, I2C, I2S, FLEXCOMM) */ + FLEXCOMM6_IRQn = 20, /**< Flexcomm Interface 6 (USART, SPI, I2C, I2S, FLEXCOMM) */ + FLEXCOMM7_IRQn = 21, /**< Flexcomm Interface 7 (USART, SPI, I2C, I2S, FLEXCOMM) */ + ADC0_IRQn = 22, /**< ADC0 */ + Reserved39_IRQn = 23, /**< Reserved interrupt */ + ACMP_IRQn = 24, /**< ACMP interrupts */ + Reserved41_IRQn = 25, /**< Reserved interrupt */ + Reserved42_IRQn = 26, /**< Reserved interrupt */ + USB0_NEEDCLK_IRQn = 27, /**< USB Activity Wake-up Interrupt */ + USB0_IRQn = 28, /**< USB device */ + RTC_IRQn = 29, /**< RTC alarm and wake-up interrupts */ + Reserved46_IRQn = 30, /**< Reserved interrupt */ + Reserved47_IRQn = 31, /**< Reserved interrupt */ + PIN_INT4_IRQn = 32, /**< Pin interrupt 4 or pattern match engine slice 4 int */ + PIN_INT5_IRQn = 33, /**< Pin interrupt 5 or pattern match engine slice 5 int */ + PIN_INT6_IRQn = 34, /**< Pin interrupt 6 or pattern match engine slice 6 int */ + PIN_INT7_IRQn = 35, /**< Pin interrupt 7 or pattern match engine slice 7 int */ + CTIMER2_IRQn = 36, /**< Standard counter/timer CTIMER2 */ + CTIMER4_IRQn = 37, /**< Standard counter/timer CTIMER4 */ + OS_EVENT_IRQn = 38, /**< OS_EVENT_TIMER and OS_EVENT_WAKEUP interrupts */ + Reserved55_IRQn = 39, /**< Reserved interrupt */ + Reserved56_IRQn = 40, /**< Reserved interrupt */ + Reserved57_IRQn = 41, /**< Reserved interrupt */ + Reserved58_IRQn = 42, /**< Reserved interrupt */ + CAN0_IRQ0_IRQn = 43, /**< CAN0 interrupt0 */ + CAN0_IRQ1_IRQn = 44, /**< CAN0 interrupt1 */ + Reserved61_IRQn = 45, /**< Reserved interrupt */ + USB1_PHY_IRQn = 46, /**< USB1_PHY */ + USB1_IRQn = 47, /**< USB1 interrupt */ + USB1_NEEDCLK_IRQn = 48, /**< USB1 activity */ + SEC_HYPERVISOR_CALL_IRQn = 49, /**< SEC_HYPERVISOR_CALL interrupt */ + SEC_GPIO_INT0_IRQ0_IRQn = 50, /**< SEC_GPIO_INT0_IRQ0 interrupt */ + SEC_GPIO_INT0_IRQ1_IRQn = 51, /**< SEC_GPIO_INT0_IRQ1 interrupt */ + PLU_IRQn = 52, /**< PLU interrupt */ + SEC_VIO_IRQn = 53, /**< SEC_VIO interrupt */ + HASHCRYPT_IRQn = 54, /**< SHA interrupt */ + CASER_IRQn = 55, /**< CASPER interrupt */ + PUF_IRQn = 56, /**< PUF interrupt */ + Reserved73_IRQn = 57, /**< Reserved interrupt */ + DMA1_IRQn = 58, /**< DMA1 interrupt */ + FLEXCOMM8_IRQn = 59, /**< Flexcomm Interface 8 (SPI, , FLEXCOMM) */ + CDOG_IRQn = 60 /**< CDOG interrupt */ +} IRQn_Type; + +/*! + * @} + */ /* end of group Interrupt_vector_numbers */ + + +/* ---------------------------------------------------------------------------- + -- Cortex M33 Core Configuration + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Cortex_Core_Configuration Cortex M33 Core Configuration + * @{ + */ + +#define __MPU_PRESENT 1 /**< Defines if an MPU is present or not */ +#define __NVIC_PRIO_BITS 3 /**< Number of priority bits implemented in the NVIC */ +#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */ +#define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */ +#define __DSP_PRESENT 1 /**< Defines if Armv8-M Mainline core supports DSP instructions */ +#define __SAUREGION_PRESENT 1 /**< Defines if an SAU is present or not */ + +#include "core_cm33.h" /* Core Peripheral Access Layer */ +#include "system_LPC55S16.h" /* Device specific configuration file */ + +/*! + * @} + */ /* end of group Cortex_Core_Configuration */ + + +/* ---------------------------------------------------------------------------- + -- Mapping Information + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Mapping_Information Mapping Information + * @{ + */ + +/** Mapping Information */ +/*! + * @addtogroup dma_request + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! + * @brief Structure for the DMA hardware request + * + * Defines the structure for the DMA hardware request collections. The user can configure the + * hardware request to trigger the DMA transfer accordingly. The index + * of the hardware request varies according to the to SoC. + */ +typedef enum _dma_request_source +{ + kDma0RequestHashCrypt = 0U, /**< HashCrypt */ + kDma1RequestHashCrypt = 0U, /**< HashCrypt */ + kDma0RequestNoDMARequest1 = 1U, /**< No DMA request 1 */ + kDma1RequestNoDMARequest1 = 1U, /**< No DMA request 1 */ + kDma0RequestFlexcomm8Rx = 2U, /**< Flexcomm Interface 8 RX */ + kDma1RequestFlexcomm8Rx = 2U, /**< Flexcomm Interface 8 RX */ + kDma0RequestFlexcomm8Tx = 3U, /**< Flexcomm Interface 8 TX */ + kDma1RequestFlexcomm8Tx = 3U, /**< Flexcomm Interface 8 TX */ + kDma0RequestFlexcomm0Rx = 4U, /**< Flexcomm Interface 0 RX/I2C Slave */ + kDma1RequestFlexcomm0Rx = 4U, /**< Flexcomm Interface 0 RX/I2C Slave */ + kDma0RequestFlexcomm0Tx = 5U, /**< Flexcomm Interface 0 TX/I2C Master */ + kDma1RequestFlexcomm0Tx = 5U, /**< Flexcomm Interface 0 TX/I2C Master */ + kDma0RequestFlexcomm1Rx = 6U, /**< Flexcomm Interface 1 RX/I2C Slave */ + kDma1RequestFlexcomm1Rx = 6U, /**< Flexcomm Interface 1 RX/I2C Slave */ + kDma0RequestFlexcomm1Tx = 7U, /**< Flexcomm Interface 1 TX/I2C Master */ + kDma1RequestFlexcomm1Tx = 7U, /**< Flexcomm Interface 1 TX/I2C Master */ + kDma0RequestFlexcomm3Rx = 8U, /**< Flexcomm Interface 3 RX/I2C Slave */ + kDma1RequestFlexcomm3Rx = 8U, /**< Flexcomm Interface 3 RX/I2C Slave */ + kDma0RequestFlexcomm3Tx = 9U, /**< Flexcomm Interface 3 TX/I2C Master */ + kDma1RequestFlexcomm3Tx = 9U, /**< Flexcomm Interface 3 TX/I2C Master */ + kDma0RequestFlexcomm2Rx = 10U, /**< Flexcomm Interface 2 RX/I2C Slave */ + kDma0RequestFlexcomm2Tx = 11U, /**< Flexcomm Interface 2 TX/I2C Master */ + kDma0RequestFlexcomm4Rx = 12U, /**< Flexcomm Interface 4 RX/I2C Slave */ + kDma0RequestFlexcomm4Tx = 13U, /**< Flexcomm Interface 4 TX/I2C Master */ + kDma0RequestFlexcomm5Rx = 14U, /**< Flexcomm Interface 5 RX/I2C Slave */ + kDma0RequestFlexcomm5Tx = 15U, /**< Flexcomm Interface 5 TX/I2C Master */ + kDma0RequestFlexcomm6Rx = 16U, /**< Flexcomm Interface 6 RX/I2C Slave */ + kDma0RequestFlexcomm6Tx = 17U, /**< Flexcomm Interface 6 TX/I2C Master */ + kDma0RequestFlexcomm7Rx = 18U, /**< Flexcomm Interface 7 RX/I2C Slave */ + kDma0RequestFlexcomm7Tx = 19U, /**< Flexcomm Interface 7 TX/I2C Master */ + kDma0RequestNoDMARequest20 = 20U, /**< No DMA request 20 */ + kDma0RequestADC0FIFO0 = 21U, /**< ADC0 FIFO 0 */ + kDma0RequestADC0FIFO1 = 22U, /**< ADC0 FIFO 1 */ +} dma_request_source_t; + +/* @} */ + + +/*! + * @} + */ /* end of group Mapping_Information */ + + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- ADC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer + * @{ + */ + +/** ADC - Register Layout Typedef */ +typedef struct { + __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ + __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ + uint8_t RESERVED_0[8]; + __IO uint32_t CTRL; /**< ADC Control Register, offset: 0x10 */ + __IO uint32_t STAT; /**< ADC Status Register, offset: 0x14 */ + __IO uint32_t IE; /**< Interrupt Enable Register, offset: 0x18 */ + __IO uint32_t DE; /**< DMA Enable Register, offset: 0x1C */ + __IO uint32_t CFG; /**< ADC Configuration Register, offset: 0x20 */ + __IO uint32_t PAUSE; /**< ADC Pause Register, offset: 0x24 */ + uint8_t RESERVED_1[12]; + __O uint32_t SWTRIG; /**< Software Trigger Register, offset: 0x34 */ + __IO uint32_t TSTAT; /**< Trigger Status Register, offset: 0x38 */ + uint8_t RESERVED_2[4]; + __IO uint32_t OFSTRIM; /**< ADC Offset Trim Register, offset: 0x40 */ + uint8_t RESERVED_3[92]; + __IO uint32_t TCTRL[16]; /**< Trigger Control Register, array offset: 0xA0, array step: 0x4 */ + __IO uint32_t FCTRL[2]; /**< FIFO Control Register, array offset: 0xE0, array step: 0x4 */ + uint8_t RESERVED_4[8]; + __I uint32_t GCC[2]; /**< Gain Calibration Control, array offset: 0xF0, array step: 0x4 */ + __IO uint32_t GCR[2]; /**< Gain Calculation Result, array offset: 0xF8, array step: 0x4 */ + struct { /* offset: 0x100, array step: 0x8 */ + __IO uint32_t CMDL; /**< ADC Command Low Buffer Register, array offset: 0x100, array step: 0x8 */ + __IO uint32_t CMDH; /**< ADC Command High Buffer Register, array offset: 0x104, array step: 0x8 */ + } CMD[15]; + uint8_t RESERVED_5[136]; + __IO uint32_t CV[4]; /**< Compare Value Register, array offset: 0x200, array step: 0x4 */ + uint8_t RESERVED_6[240]; + __I uint32_t RESFIFO[2]; /**< ADC Data Result FIFO Register, array offset: 0x300, array step: 0x4 */ + uint8_t RESERVED_7[248]; + __IO uint32_t CAL_GAR[33]; /**< Calibration General A-Side Registers, array offset: 0x400, array step: 0x4 */ + uint8_t RESERVED_8[124]; + __IO uint32_t CAL_GBR[33]; /**< Calibration General B-Side Registers, array offset: 0x500, array step: 0x4 */ +} ADC_Type; + +/* ---------------------------------------------------------------------------- + -- ADC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ADC_Register_Masks ADC Register Masks + * @{ + */ + +/*! @name VERID - Version ID Register */ +/*! @{ */ + +#define ADC_VERID_RES_MASK (0x1U) +#define ADC_VERID_RES_SHIFT (0U) +/*! RES - Resolution + * 0b0..Up to 13-bit differential/12-bit single ended resolution supported. + * 0b1..Up to 16-bit differential/16-bit single ended resolution supported. + */ +#define ADC_VERID_RES(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_RES_SHIFT)) & ADC_VERID_RES_MASK) + +#define ADC_VERID_DIFFEN_MASK (0x2U) +#define ADC_VERID_DIFFEN_SHIFT (1U) +/*! DIFFEN - Differential Supported + * 0b0..Differential operation not supported. + * 0b1..Differential operation supported. CMDLa[CTYPE] controls fields implemented. + */ +#define ADC_VERID_DIFFEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_DIFFEN_SHIFT)) & ADC_VERID_DIFFEN_MASK) + +#define ADC_VERID_MVI_MASK (0x8U) +#define ADC_VERID_MVI_SHIFT (3U) +/*! MVI - Multi Vref Implemented + * 0b0..Single voltage reference high (VREFH) input supported. + * 0b1..Multiple voltage reference high (VREFH) inputs supported. + */ +#define ADC_VERID_MVI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MVI_SHIFT)) & ADC_VERID_MVI_MASK) + +#define ADC_VERID_CSW_MASK (0x70U) +#define ADC_VERID_CSW_SHIFT (4U) +/*! CSW - Channel Scale Width + * 0b000..Channel scaling not supported. + * 0b001..Channel scaling supported. 1-bit CSCALE control field. + * 0b110..Channel scaling supported. 6-bit CSCALE control field. + */ +#define ADC_VERID_CSW(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_CSW_SHIFT)) & ADC_VERID_CSW_MASK) + +#define ADC_VERID_VR1RNGI_MASK (0x100U) +#define ADC_VERID_VR1RNGI_SHIFT (8U) +/*! VR1RNGI - Voltage Reference 1 Range Control Bit Implemented + * 0b0..Range control not required. CFG[VREF1RNG] is not implemented. + * 0b1..Range control required. CFG[VREF1RNG] is implemented. + */ +#define ADC_VERID_VR1RNGI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_VR1RNGI_SHIFT)) & ADC_VERID_VR1RNGI_MASK) + +#define ADC_VERID_IADCKI_MASK (0x200U) +#define ADC_VERID_IADCKI_SHIFT (9U) +/*! IADCKI - Internal ADC Clock implemented + * 0b0..Internal clock source not implemented. + * 0b1..Internal clock source (and CFG[ADCKEN]) implemented. + */ +#define ADC_VERID_IADCKI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_IADCKI_SHIFT)) & ADC_VERID_IADCKI_MASK) + +#define ADC_VERID_CALOFSI_MASK (0x400U) +#define ADC_VERID_CALOFSI_SHIFT (10U) +/*! CALOFSI - Calibration Function Implemented + * 0b0..Calibration Not Implemented. + * 0b1..Calibration Implemented. + */ +#define ADC_VERID_CALOFSI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_CALOFSI_SHIFT)) & ADC_VERID_CALOFSI_MASK) + +#define ADC_VERID_NUM_SEC_MASK (0x800U) +#define ADC_VERID_NUM_SEC_SHIFT (11U) +/*! NUM_SEC - Number of Single Ended Outputs Supported + * 0b0..This design supports one single ended conversion at a time. + * 0b1..This design supports two simultanious single ended conversions. + */ +#define ADC_VERID_NUM_SEC(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_NUM_SEC_SHIFT)) & ADC_VERID_NUM_SEC_MASK) + +#define ADC_VERID_NUM_FIFO_MASK (0x7000U) +#define ADC_VERID_NUM_FIFO_SHIFT (12U) +/*! NUM_FIFO - Number of FIFOs + * 0b000..N/A + * 0b001..This design supports one result FIFO. + * 0b010..This design supports two result FIFOs. + * 0b011..This design supports three result FIFOs. + * 0b100..This design supports four result FIFOs. + */ +#define ADC_VERID_NUM_FIFO(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_NUM_FIFO_SHIFT)) & ADC_VERID_NUM_FIFO_MASK) + +#define ADC_VERID_MINOR_MASK (0xFF0000U) +#define ADC_VERID_MINOR_SHIFT (16U) +/*! MINOR - Minor Version Number + */ +#define ADC_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MINOR_SHIFT)) & ADC_VERID_MINOR_MASK) + +#define ADC_VERID_MAJOR_MASK (0xFF000000U) +#define ADC_VERID_MAJOR_SHIFT (24U) +/*! MAJOR - Major Version Number + */ +#define ADC_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MAJOR_SHIFT)) & ADC_VERID_MAJOR_MASK) +/*! @} */ + +/*! @name PARAM - Parameter Register */ +/*! @{ */ + +#define ADC_PARAM_TRIG_NUM_MASK (0xFFU) +#define ADC_PARAM_TRIG_NUM_SHIFT (0U) +/*! TRIG_NUM - Trigger Number + */ +#define ADC_PARAM_TRIG_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_TRIG_NUM_SHIFT)) & ADC_PARAM_TRIG_NUM_MASK) + +#define ADC_PARAM_FIFOSIZE_MASK (0xFF00U) +#define ADC_PARAM_FIFOSIZE_SHIFT (8U) +/*! FIFOSIZE - Result FIFO Depth + * 0b00000001..Result FIFO depth = 1 dataword. + * 0b00000100..Result FIFO depth = 4 datawords. + * 0b00001000..Result FIFO depth = 8 datawords. + * 0b00010000..Result FIFO depth = 16 datawords. + * 0b00100000..Result FIFO depth = 32 datawords. + * 0b01000000..Result FIFO depth = 64 datawords. + */ +#define ADC_PARAM_FIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_FIFOSIZE_SHIFT)) & ADC_PARAM_FIFOSIZE_MASK) + +#define ADC_PARAM_CV_NUM_MASK (0xFF0000U) +#define ADC_PARAM_CV_NUM_SHIFT (16U) +/*! CV_NUM - Compare Value Number + */ +#define ADC_PARAM_CV_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_CV_NUM_SHIFT)) & ADC_PARAM_CV_NUM_MASK) + +#define ADC_PARAM_CMD_NUM_MASK (0xFF000000U) +#define ADC_PARAM_CMD_NUM_SHIFT (24U) +/*! CMD_NUM - Command Buffer Number + */ +#define ADC_PARAM_CMD_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_CMD_NUM_SHIFT)) & ADC_PARAM_CMD_NUM_MASK) +/*! @} */ + +/*! @name CTRL - ADC Control Register */ +/*! @{ */ + +#define ADC_CTRL_ADCEN_MASK (0x1U) +#define ADC_CTRL_ADCEN_SHIFT (0U) +/*! ADCEN - ADC Enable + * 0b0..ADC is disabled. + * 0b1..ADC is enabled. + */ +#define ADC_CTRL_ADCEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_ADCEN_SHIFT)) & ADC_CTRL_ADCEN_MASK) + +#define ADC_CTRL_RST_MASK (0x2U) +#define ADC_CTRL_RST_SHIFT (1U) +/*! RST - Software Reset + * 0b0..ADC logic is not reset. + * 0b1..ADC logic is reset. + */ +#define ADC_CTRL_RST(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RST_SHIFT)) & ADC_CTRL_RST_MASK) + +#define ADC_CTRL_DOZEN_MASK (0x4U) +#define ADC_CTRL_DOZEN_SHIFT (2U) +/*! DOZEN - Doze Enable + * 0b0..ADC is enabled in Doze mode. + * 0b1..ADC is disabled in Doze mode. + */ +#define ADC_CTRL_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_DOZEN_SHIFT)) & ADC_CTRL_DOZEN_MASK) + +#define ADC_CTRL_CAL_REQ_MASK (0x8U) +#define ADC_CTRL_CAL_REQ_SHIFT (3U) +/*! CAL_REQ - Auto-Calibration Request + * 0b0..No request for auto-calibration has been made. + * 0b1..A request for auto-calibration has been made + */ +#define ADC_CTRL_CAL_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CAL_REQ_SHIFT)) & ADC_CTRL_CAL_REQ_MASK) + +#define ADC_CTRL_CALOFS_MASK (0x10U) +#define ADC_CTRL_CALOFS_SHIFT (4U) +/*! CALOFS - Configure for offset calibration function + * 0b0..Calibration function disabled + * 0b1..Request for offset calibration function + */ +#define ADC_CTRL_CALOFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CALOFS_SHIFT)) & ADC_CTRL_CALOFS_MASK) + +#define ADC_CTRL_RSTFIFO0_MASK (0x100U) +#define ADC_CTRL_RSTFIFO0_SHIFT (8U) +/*! RSTFIFO0 - Reset FIFO 0 + * 0b0..No effect. + * 0b1..FIFO 0 is reset. + */ +#define ADC_CTRL_RSTFIFO0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RSTFIFO0_SHIFT)) & ADC_CTRL_RSTFIFO0_MASK) + +#define ADC_CTRL_RSTFIFO1_MASK (0x200U) +#define ADC_CTRL_RSTFIFO1_SHIFT (9U) +/*! RSTFIFO1 - Reset FIFO 1 + * 0b0..No effect. + * 0b1..FIFO 1 is reset. + */ +#define ADC_CTRL_RSTFIFO1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RSTFIFO1_SHIFT)) & ADC_CTRL_RSTFIFO1_MASK) + +#define ADC_CTRL_CAL_AVGS_MASK (0x70000U) +#define ADC_CTRL_CAL_AVGS_SHIFT (16U) +/*! CAL_AVGS - Auto-Calibration Averages + * 0b000..Single conversion. + * 0b001..2 conversions averaged. + * 0b010..4 conversions averaged. + * 0b011..8 conversions averaged. + * 0b100..16 conversions averaged. + * 0b101..32 conversions averaged. + * 0b110..64 conversions averaged. + * 0b111..128 conversions averaged. + */ +#define ADC_CTRL_CAL_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CAL_AVGS_SHIFT)) & ADC_CTRL_CAL_AVGS_MASK) +/*! @} */ + +/*! @name STAT - ADC Status Register */ +/*! @{ */ + +#define ADC_STAT_RDY0_MASK (0x1U) +#define ADC_STAT_RDY0_SHIFT (0U) +/*! RDY0 - Result FIFO 0 Ready Flag + * 0b0..Result FIFO 0 data level not above watermark level. + * 0b1..Result FIFO 0 holding data above watermark level. + */ +#define ADC_STAT_RDY0(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_RDY0_SHIFT)) & ADC_STAT_RDY0_MASK) + +#define ADC_STAT_FOF0_MASK (0x2U) +#define ADC_STAT_FOF0_SHIFT (1U) +/*! FOF0 - Result FIFO 0 Overflow Flag + * 0b0..No result FIFO 0 overflow has occurred since the last time the flag was cleared. + * 0b1..At least one result FIFO 0 overflow has occurred since the last time the flag was cleared. + */ +#define ADC_STAT_FOF0(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_FOF0_SHIFT)) & ADC_STAT_FOF0_MASK) + +#define ADC_STAT_RDY1_MASK (0x4U) +#define ADC_STAT_RDY1_SHIFT (2U) +/*! RDY1 - Result FIFO1 Ready Flag + * 0b0..Result FIFO1 data level not above watermark level. + * 0b1..Result FIFO1 holding data above watermark level. + */ +#define ADC_STAT_RDY1(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_RDY1_SHIFT)) & ADC_STAT_RDY1_MASK) + +#define ADC_STAT_FOF1_MASK (0x8U) +#define ADC_STAT_FOF1_SHIFT (3U) +/*! FOF1 - Result FIFO1 Overflow Flag + * 0b0..No result FIFO1 overflow has occurred since the last time the flag was cleared. + * 0b1..At least one result FIFO1 overflow has occurred since the last time the flag was cleared. + */ +#define ADC_STAT_FOF1(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_FOF1_SHIFT)) & ADC_STAT_FOF1_MASK) + +#define ADC_STAT_TEXC_INT_MASK (0x100U) +#define ADC_STAT_TEXC_INT_SHIFT (8U) +/*! TEXC_INT - Interrupt Flag For High Priority Trigger Exception + * 0b0..No trigger exceptions have occurred. + * 0b1..A trigger exception has occurred and is pending acknowledgement. + */ +#define ADC_STAT_TEXC_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TEXC_INT_SHIFT)) & ADC_STAT_TEXC_INT_MASK) + +#define ADC_STAT_TCOMP_INT_MASK (0x200U) +#define ADC_STAT_TCOMP_INT_SHIFT (9U) +/*! TCOMP_INT - Interrupt Flag For Trigger Completion + * 0b0..Either IE[TCOMP_IE] is set to 0, or no trigger sequences have run to completion. + * 0b1..Trigger sequence has been completed and all data is stored in the associated FIFO. + */ +#define ADC_STAT_TCOMP_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TCOMP_INT_SHIFT)) & ADC_STAT_TCOMP_INT_MASK) + +#define ADC_STAT_CAL_RDY_MASK (0x400U) +#define ADC_STAT_CAL_RDY_SHIFT (10U) +/*! CAL_RDY - Calibration Ready + * 0b0..Calibration is incomplete or hasn't been ran. + * 0b1..The ADC is calibrated. + */ +#define ADC_STAT_CAL_RDY(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_CAL_RDY_SHIFT)) & ADC_STAT_CAL_RDY_MASK) + +#define ADC_STAT_ADC_ACTIVE_MASK (0x800U) +#define ADC_STAT_ADC_ACTIVE_SHIFT (11U) +/*! ADC_ACTIVE - ADC Active + * 0b0..The ADC is IDLE. There are no pending triggers to service and no active commands are being processed. + * 0b1..The ADC is processing a conversion, running through the power up delay, or servicing a trigger. + */ +#define ADC_STAT_ADC_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_ADC_ACTIVE_SHIFT)) & ADC_STAT_ADC_ACTIVE_MASK) + +#define ADC_STAT_TRGACT_MASK (0xF0000U) +#define ADC_STAT_TRGACT_SHIFT (16U) +/*! TRGACT - Trigger Active + * 0b0000..Command (sequence) associated with Trigger 0 currently being executed. + * 0b0001..Command (sequence) associated with Trigger 1 currently being executed. + * 0b0010..Command (sequence) associated with Trigger 2 currently being executed. + * 0b0011-0b1111..Command (sequence) from the associated Trigger number is currently being executed. + */ +#define ADC_STAT_TRGACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TRGACT_SHIFT)) & ADC_STAT_TRGACT_MASK) + +#define ADC_STAT_CMDACT_MASK (0xF000000U) +#define ADC_STAT_CMDACT_SHIFT (24U) +/*! CMDACT - Command Active + * 0b0000..No command is currently in progress. + * 0b0001..Command 1 currently being executed. + * 0b0010..Command 2 currently being executed. + * 0b0011-0b1111..Associated command number is currently being executed. + */ +#define ADC_STAT_CMDACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_CMDACT_SHIFT)) & ADC_STAT_CMDACT_MASK) +/*! @} */ + +/*! @name IE - Interrupt Enable Register */ +/*! @{ */ + +#define ADC_IE_FWMIE0_MASK (0x1U) +#define ADC_IE_FWMIE0_SHIFT (0U) +/*! FWMIE0 - FIFO 0 Watermark Interrupt Enable + * 0b0..FIFO 0 watermark interrupts are not enabled. + * 0b1..FIFO 0 watermark interrupts are enabled. + */ +#define ADC_IE_FWMIE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FWMIE0_SHIFT)) & ADC_IE_FWMIE0_MASK) + +#define ADC_IE_FOFIE0_MASK (0x2U) +#define ADC_IE_FOFIE0_SHIFT (1U) +/*! FOFIE0 - Result FIFO 0 Overflow Interrupt Enable + * 0b0..FIFO 0 overflow interrupts are not enabled. + * 0b1..FIFO 0 overflow interrupts are enabled. + */ +#define ADC_IE_FOFIE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FOFIE0_SHIFT)) & ADC_IE_FOFIE0_MASK) + +#define ADC_IE_FWMIE1_MASK (0x4U) +#define ADC_IE_FWMIE1_SHIFT (2U) +/*! FWMIE1 - FIFO1 Watermark Interrupt Enable + * 0b0..FIFO1 watermark interrupts are not enabled. + * 0b1..FIFO1 watermark interrupts are enabled. + */ +#define ADC_IE_FWMIE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FWMIE1_SHIFT)) & ADC_IE_FWMIE1_MASK) + +#define ADC_IE_FOFIE1_MASK (0x8U) +#define ADC_IE_FOFIE1_SHIFT (3U) +/*! FOFIE1 - Result FIFO1 Overflow Interrupt Enable + * 0b0..No result FIFO1 overflow has occurred since the last time the flag was cleared. + * 0b1..At least one result FIFO1 overflow has occurred since the last time the flag was cleared. + */ +#define ADC_IE_FOFIE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FOFIE1_SHIFT)) & ADC_IE_FOFIE1_MASK) + +#define ADC_IE_TEXC_IE_MASK (0x100U) +#define ADC_IE_TEXC_IE_SHIFT (8U) +/*! TEXC_IE - Trigger Exception Interrupt Enable + * 0b0..Trigger exception interrupts are disabled. + * 0b1..Trigger exception interrupts are enabled. + */ +#define ADC_IE_TEXC_IE(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_TEXC_IE_SHIFT)) & ADC_IE_TEXC_IE_MASK) + +#define ADC_IE_TCOMP_IE_MASK (0xFFFF0000U) +#define ADC_IE_TCOMP_IE_SHIFT (16U) +/*! TCOMP_IE - Trigger Completion Interrupt Enable + * 0b0000000000000000..Trigger completion interrupts are disabled. + * 0b0000000000000001..Trigger completion interrupts are enabled for trigger source 0 only. + * 0b0000000000000010..Trigger completion interrupts are enabled for trigger source 1 only. + * 0b0000000000000011-0b1111111111111110..Associated trigger completion interrupts are enabled. + * 0b1111111111111111..Trigger completion interrupts are enabled for every trigger source. + */ +#define ADC_IE_TCOMP_IE(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_TCOMP_IE_SHIFT)) & ADC_IE_TCOMP_IE_MASK) +/*! @} */ + +/*! @name DE - DMA Enable Register */ +/*! @{ */ + +#define ADC_DE_FWMDE0_MASK (0x1U) +#define ADC_DE_FWMDE0_SHIFT (0U) +/*! FWMDE0 - FIFO 0 Watermark DMA Enable + * 0b0..DMA request disabled. + * 0b1..DMA request enabled. + */ +#define ADC_DE_FWMDE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_DE_FWMDE0_SHIFT)) & ADC_DE_FWMDE0_MASK) + +#define ADC_DE_FWMDE1_MASK (0x2U) +#define ADC_DE_FWMDE1_SHIFT (1U) +/*! FWMDE1 - FIFO1 Watermark DMA Enable + * 0b0..DMA request disabled. + * 0b1..DMA request enabled. + */ +#define ADC_DE_FWMDE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_DE_FWMDE1_SHIFT)) & ADC_DE_FWMDE1_MASK) +/*! @} */ + +/*! @name CFG - ADC Configuration Register */ +/*! @{ */ + +#define ADC_CFG_TPRICTRL_MASK (0x3U) +#define ADC_CFG_TPRICTRL_SHIFT (0U) +/*! TPRICTRL - ADC trigger priority control + * 0b00..If a higher priority trigger is detected during command processing, the current conversion is aborted + * and the new command specified by the trigger is started. + * 0b01..If a higher priority trigger is received during command processing, the current command is stopped after + * after completing the current conversion. If averaging is enabled, the averaging loop will be completed. + * However, CMDHa[LOOP] will be ignored and the higher priority trigger will be serviced. + * 0b10..If a higher priority trigger is received during command processing, the current command will be + * completed (averaging, looping, compare) before servicing the higher priority trigger. + * 0b11..RESERVED + */ +#define ADC_CFG_TPRICTRL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TPRICTRL_SHIFT)) & ADC_CFG_TPRICTRL_MASK) + +#define ADC_CFG_PWRSEL_MASK (0x30U) +#define ADC_CFG_PWRSEL_SHIFT (4U) +/*! PWRSEL - Power Configuration Select + * 0b00..Lowest power setting. + * 0b01..Higher power setting than 0b0. + * 0b10..Higher power setting than 0b1. + * 0b11..Highest power setting. + */ +#define ADC_CFG_PWRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PWRSEL_SHIFT)) & ADC_CFG_PWRSEL_MASK) + +#define ADC_CFG_REFSEL_MASK (0xC0U) +#define ADC_CFG_REFSEL_SHIFT (6U) +/*! REFSEL - Voltage Reference Selection + * 0b00..(Default) Option 1 setting. + * 0b01..Option 2 setting. + * 0b10..Option 3 setting. + * 0b11..Reserved + */ +#define ADC_CFG_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_REFSEL_SHIFT)) & ADC_CFG_REFSEL_MASK) + +#define ADC_CFG_TRES_MASK (0x100U) +#define ADC_CFG_TRES_SHIFT (8U) +/*! TRES - Trigger Resume Enable + * 0b0..Trigger sequences interrupted by a high priority trigger exception will not be automatically resumed or restarted. + * 0b1..Trigger sequences interrupted by a high priority trigger exception will be automatically resumed or restarted. + */ +#define ADC_CFG_TRES(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TRES_SHIFT)) & ADC_CFG_TRES_MASK) + +#define ADC_CFG_TCMDRES_MASK (0x200U) +#define ADC_CFG_TCMDRES_SHIFT (9U) +/*! TCMDRES - Trigger Command Resume + * 0b0..Trigger sequences interrupted by a high priority trigger exception will be automatically restarted. + * 0b1..Trigger sequences interrupted by a high priority trigger exception will be resumed from the command executing before the exception. + */ +#define ADC_CFG_TCMDRES(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TCMDRES_SHIFT)) & ADC_CFG_TCMDRES_MASK) + +#define ADC_CFG_HPT_EXDI_MASK (0x400U) +#define ADC_CFG_HPT_EXDI_SHIFT (10U) +/*! HPT_EXDI - High Priority Trigger Exception Disable + * 0b0..High priority trigger exceptions are enabled. + * 0b1..High priority trigger exceptions are disabled. + */ +#define ADC_CFG_HPT_EXDI(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_HPT_EXDI_SHIFT)) & ADC_CFG_HPT_EXDI_MASK) + +#define ADC_CFG_PUDLY_MASK (0xFF0000U) +#define ADC_CFG_PUDLY_SHIFT (16U) +/*! PUDLY - Power Up Delay + */ +#define ADC_CFG_PUDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PUDLY_SHIFT)) & ADC_CFG_PUDLY_MASK) + +#define ADC_CFG_PWREN_MASK (0x10000000U) +#define ADC_CFG_PWREN_SHIFT (28U) +/*! PWREN - ADC Analog Pre-Enable + * 0b0..ADC analog circuits are only enabled while conversions are active. Performance is affected due to analog startup delays. + * 0b1..ADC analog circuits are pre-enabled and ready to execute conversions without startup delays (at the cost + * of higher DC current consumption). A single power up delay (CFG[PUDLY]) is executed immediately once PWREN + * is set, and any detected trigger does not begin ADC operation until the power up delay time has passed. + * After this initial delay expires the analog will remain pre-enabled, and no additional delays will be + * executed. + */ +#define ADC_CFG_PWREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PWREN_SHIFT)) & ADC_CFG_PWREN_MASK) +/*! @} */ + +/*! @name PAUSE - ADC Pause Register */ +/*! @{ */ + +#define ADC_PAUSE_PAUSEDLY_MASK (0x1FFU) +#define ADC_PAUSE_PAUSEDLY_SHIFT (0U) +/*! PAUSEDLY - Pause Delay + */ +#define ADC_PAUSE_PAUSEDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_PAUSE_PAUSEDLY_SHIFT)) & ADC_PAUSE_PAUSEDLY_MASK) + +#define ADC_PAUSE_PAUSEEN_MASK (0x80000000U) +#define ADC_PAUSE_PAUSEEN_SHIFT (31U) +/*! PAUSEEN - PAUSE Option Enable + * 0b0..Pause operation disabled + * 0b1..Pause operation enabled + */ +#define ADC_PAUSE_PAUSEEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_PAUSE_PAUSEEN_SHIFT)) & ADC_PAUSE_PAUSEEN_MASK) +/*! @} */ + +/*! @name SWTRIG - Software Trigger Register */ +/*! @{ */ + +#define ADC_SWTRIG_SWT0_MASK (0x1U) +#define ADC_SWTRIG_SWT0_SHIFT (0U) +/*! SWT0 - Software trigger 0 event + * 0b0..No trigger 0 event generated. + * 0b1..Trigger 0 event generated. + */ +#define ADC_SWTRIG_SWT0(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT0_SHIFT)) & ADC_SWTRIG_SWT0_MASK) + +#define ADC_SWTRIG_SWT1_MASK (0x2U) +#define ADC_SWTRIG_SWT1_SHIFT (1U) +/*! SWT1 - Software trigger 1 event + * 0b0..No trigger 1 event generated. + * 0b1..Trigger 1 event generated. + */ +#define ADC_SWTRIG_SWT1(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT1_SHIFT)) & ADC_SWTRIG_SWT1_MASK) + +#define ADC_SWTRIG_SWT2_MASK (0x4U) +#define ADC_SWTRIG_SWT2_SHIFT (2U) +/*! SWT2 - Software trigger 2 event + * 0b0..No trigger 2 event generated. + * 0b1..Trigger 2 event generated. + */ +#define ADC_SWTRIG_SWT2(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT2_SHIFT)) & ADC_SWTRIG_SWT2_MASK) + +#define ADC_SWTRIG_SWT3_MASK (0x8U) +#define ADC_SWTRIG_SWT3_SHIFT (3U) +/*! SWT3 - Software trigger 3 event + * 0b0..No trigger 3 event generated. + * 0b1..Trigger 3 event generated. + */ +#define ADC_SWTRIG_SWT3(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT3_SHIFT)) & ADC_SWTRIG_SWT3_MASK) + +#define ADC_SWTRIG_SWT4_MASK (0x10U) +#define ADC_SWTRIG_SWT4_SHIFT (4U) +/*! SWT4 - Software trigger 4 event + * 0b0..No trigger 4 event generated. + * 0b1..Trigger 4 event generated. + */ +#define ADC_SWTRIG_SWT4(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT4_SHIFT)) & ADC_SWTRIG_SWT4_MASK) + +#define ADC_SWTRIG_SWT5_MASK (0x20U) +#define ADC_SWTRIG_SWT5_SHIFT (5U) +/*! SWT5 - Software trigger 5 event + * 0b0..No trigger 5 event generated. + * 0b1..Trigger 5 event generated. + */ +#define ADC_SWTRIG_SWT5(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT5_SHIFT)) & ADC_SWTRIG_SWT5_MASK) + +#define ADC_SWTRIG_SWT6_MASK (0x40U) +#define ADC_SWTRIG_SWT6_SHIFT (6U) +/*! SWT6 - Software trigger 6 event + * 0b0..No trigger 6 event generated. + * 0b1..Trigger 6 event generated. + */ +#define ADC_SWTRIG_SWT6(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT6_SHIFT)) & ADC_SWTRIG_SWT6_MASK) + +#define ADC_SWTRIG_SWT7_MASK (0x80U) +#define ADC_SWTRIG_SWT7_SHIFT (7U) +/*! SWT7 - Software trigger 7 event + * 0b0..No trigger 7 event generated. + * 0b1..Trigger 7 event generated. + */ +#define ADC_SWTRIG_SWT7(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT7_SHIFT)) & ADC_SWTRIG_SWT7_MASK) + +#define ADC_SWTRIG_SWT8_MASK (0x100U) +#define ADC_SWTRIG_SWT8_SHIFT (8U) +/*! SWT8 - Software trigger 8 event + * 0b0..No trigger 8 event generated. + * 0b1..Trigger 8 event generated. + */ +#define ADC_SWTRIG_SWT8(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT8_SHIFT)) & ADC_SWTRIG_SWT8_MASK) + +#define ADC_SWTRIG_SWT9_MASK (0x200U) +#define ADC_SWTRIG_SWT9_SHIFT (9U) +/*! SWT9 - Software trigger 9 event + * 0b0..No trigger 9 event generated. + * 0b1..Trigger 9 event generated. + */ +#define ADC_SWTRIG_SWT9(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT9_SHIFT)) & ADC_SWTRIG_SWT9_MASK) + +#define ADC_SWTRIG_SWT10_MASK (0x400U) +#define ADC_SWTRIG_SWT10_SHIFT (10U) +/*! SWT10 - Software trigger 10 event + * 0b0..No trigger 10 event generated. + * 0b1..Trigger 10 event generated. + */ +#define ADC_SWTRIG_SWT10(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT10_SHIFT)) & ADC_SWTRIG_SWT10_MASK) + +#define ADC_SWTRIG_SWT11_MASK (0x800U) +#define ADC_SWTRIG_SWT11_SHIFT (11U) +/*! SWT11 - Software trigger 11 event + * 0b0..No trigger 11 event generated. + * 0b1..Trigger 11 event generated. + */ +#define ADC_SWTRIG_SWT11(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT11_SHIFT)) & ADC_SWTRIG_SWT11_MASK) + +#define ADC_SWTRIG_SWT12_MASK (0x1000U) +#define ADC_SWTRIG_SWT12_SHIFT (12U) +/*! SWT12 - Software trigger 12 event + * 0b0..No trigger 12 event generated. + * 0b1..Trigger 12 event generated. + */ +#define ADC_SWTRIG_SWT12(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT12_SHIFT)) & ADC_SWTRIG_SWT12_MASK) + +#define ADC_SWTRIG_SWT13_MASK (0x2000U) +#define ADC_SWTRIG_SWT13_SHIFT (13U) +/*! SWT13 - Software trigger 13 event + * 0b0..No trigger 13 event generated. + * 0b1..Trigger 13 event generated. + */ +#define ADC_SWTRIG_SWT13(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT13_SHIFT)) & ADC_SWTRIG_SWT13_MASK) + +#define ADC_SWTRIG_SWT14_MASK (0x4000U) +#define ADC_SWTRIG_SWT14_SHIFT (14U) +/*! SWT14 - Software trigger 14 event + * 0b0..No trigger 14 event generated. + * 0b1..Trigger 14 event generated. + */ +#define ADC_SWTRIG_SWT14(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT14_SHIFT)) & ADC_SWTRIG_SWT14_MASK) + +#define ADC_SWTRIG_SWT15_MASK (0x8000U) +#define ADC_SWTRIG_SWT15_SHIFT (15U) +/*! SWT15 - Software trigger 15 event + * 0b0..No trigger 15 event generated. + * 0b1..Trigger 15 event generated. + */ +#define ADC_SWTRIG_SWT15(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT15_SHIFT)) & ADC_SWTRIG_SWT15_MASK) +/*! @} */ + +/*! @name TSTAT - Trigger Status Register */ +/*! @{ */ + +#define ADC_TSTAT_TEXC_NUM_MASK (0xFFFFU) +#define ADC_TSTAT_TEXC_NUM_SHIFT (0U) +/*! TEXC_NUM - Trigger Exception Number + * 0b0000000000000000..No triggers have been interrupted by a high priority exception. Or CFG[TRES] = 1. + * 0b0000000000000001..Trigger 0 has been interrupted by a high priority exception. + * 0b0000000000000010..Trigger 1 has been interrupted by a high priority exception. + * 0b0000000000000011-0b1111111111111110..Associated trigger sequence has interrupted by a high priority exception. + * 0b1111111111111111..Every trigger sequence has been interrupted by a high priority exception. + */ +#define ADC_TSTAT_TEXC_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_TSTAT_TEXC_NUM_SHIFT)) & ADC_TSTAT_TEXC_NUM_MASK) + +#define ADC_TSTAT_TCOMP_FLAG_MASK (0xFFFF0000U) +#define ADC_TSTAT_TCOMP_FLAG_SHIFT (16U) +/*! TCOMP_FLAG - Trigger Completion Flag + * 0b0000000000000000..No triggers have been completed. Trigger completion interrupts are disabled. + * 0b0000000000000001..Trigger 0 has been completed and triger 0 has enabled completion interrupts. + * 0b0000000000000010..Trigger 1 has been completed and triger 1 has enabled completion interrupts. + * 0b0000000000000011-0b1111111111111110..Associated trigger sequence has completed and has enabled completion interrupts. + * 0b1111111111111111..Every trigger sequence has been completed and every trigger has enabled completion interrupts. + */ +#define ADC_TSTAT_TCOMP_FLAG(x) (((uint32_t)(((uint32_t)(x)) << ADC_TSTAT_TCOMP_FLAG_SHIFT)) & ADC_TSTAT_TCOMP_FLAG_MASK) +/*! @} */ + +/*! @name OFSTRIM - ADC Offset Trim Register */ +/*! @{ */ + +#define ADC_OFSTRIM_OFSTRIM_A_MASK (0x1FU) +#define ADC_OFSTRIM_OFSTRIM_A_SHIFT (0U) +/*! OFSTRIM_A - Trim for offset + */ +#define ADC_OFSTRIM_OFSTRIM_A(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFSTRIM_OFSTRIM_A_SHIFT)) & ADC_OFSTRIM_OFSTRIM_A_MASK) + +#define ADC_OFSTRIM_OFSTRIM_B_MASK (0x1F0000U) +#define ADC_OFSTRIM_OFSTRIM_B_SHIFT (16U) +/*! OFSTRIM_B - Trim for offset + */ +#define ADC_OFSTRIM_OFSTRIM_B(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFSTRIM_OFSTRIM_B_SHIFT)) & ADC_OFSTRIM_OFSTRIM_B_MASK) +/*! @} */ + +/*! @name TCTRL - Trigger Control Register */ +/*! @{ */ + +#define ADC_TCTRL_HTEN_MASK (0x1U) +#define ADC_TCTRL_HTEN_SHIFT (0U) +/*! HTEN - Trigger enable + * 0b0..Hardware trigger source disabled + * 0b1..Hardware trigger source enabled + */ +#define ADC_TCTRL_HTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_HTEN_SHIFT)) & ADC_TCTRL_HTEN_MASK) + +#define ADC_TCTRL_FIFO_SEL_A_MASK (0x2U) +#define ADC_TCTRL_FIFO_SEL_A_SHIFT (1U) +/*! FIFO_SEL_A - SAR Result Destination For Channel A + * 0b0..Result written to FIFO 0 + * 0b1..Result written to FIFO 1 + */ +#define ADC_TCTRL_FIFO_SEL_A(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_FIFO_SEL_A_SHIFT)) & ADC_TCTRL_FIFO_SEL_A_MASK) + +#define ADC_TCTRL_FIFO_SEL_B_MASK (0x4U) +#define ADC_TCTRL_FIFO_SEL_B_SHIFT (2U) +/*! FIFO_SEL_B - SAR Result Destination For Channel B + * 0b0..Result written to FIFO 0 + * 0b1..Result written to FIFO 1 + */ +#define ADC_TCTRL_FIFO_SEL_B(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_FIFO_SEL_B_SHIFT)) & ADC_TCTRL_FIFO_SEL_B_MASK) + +#define ADC_TCTRL_TPRI_MASK (0xF00U) +#define ADC_TCTRL_TPRI_SHIFT (8U) +/*! TPRI - Trigger priority setting + * 0b0000..Set to highest priority, Level 1 + * 0b0001-0b1110..Set to corresponding priority level + * 0b1111..Set to lowest priority, Level 16 + */ +#define ADC_TCTRL_TPRI(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TPRI_SHIFT)) & ADC_TCTRL_TPRI_MASK) + +#define ADC_TCTRL_RSYNC_MASK (0x8000U) +#define ADC_TCTRL_RSYNC_SHIFT (15U) +/*! RSYNC - Trigger Resync + */ +#define ADC_TCTRL_RSYNC(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_RSYNC_SHIFT)) & ADC_TCTRL_RSYNC_MASK) + +#define ADC_TCTRL_TDLY_MASK (0xF0000U) +#define ADC_TCTRL_TDLY_SHIFT (16U) +/*! TDLY - Trigger delay select + */ +#define ADC_TCTRL_TDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TDLY_SHIFT)) & ADC_TCTRL_TDLY_MASK) + +#define ADC_TCTRL_TCMD_MASK (0xF000000U) +#define ADC_TCTRL_TCMD_SHIFT (24U) +/*! TCMD - Trigger command select + * 0b0000..Not a valid selection from the command buffer. Trigger event is ignored. + * 0b0001..CMD1 is executed + * 0b0010-0b1110..Corresponding CMD is executed + * 0b1111..CMD15 is executed + */ +#define ADC_TCTRL_TCMD(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TCMD_SHIFT)) & ADC_TCTRL_TCMD_MASK) +/*! @} */ + +/* The count of ADC_TCTRL */ +#define ADC_TCTRL_COUNT (16U) + +/*! @name FCTRL - FIFO Control Register */ +/*! @{ */ + +#define ADC_FCTRL_FCOUNT_MASK (0x1FU) +#define ADC_FCTRL_FCOUNT_SHIFT (0U) +/*! FCOUNT - Result FIFO counter + */ +#define ADC_FCTRL_FCOUNT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FCTRL_FCOUNT_SHIFT)) & ADC_FCTRL_FCOUNT_MASK) + +#define ADC_FCTRL_FWMARK_MASK (0xF0000U) +#define ADC_FCTRL_FWMARK_SHIFT (16U) +/*! FWMARK - Watermark level selection + */ +#define ADC_FCTRL_FWMARK(x) (((uint32_t)(((uint32_t)(x)) << ADC_FCTRL_FWMARK_SHIFT)) & ADC_FCTRL_FWMARK_MASK) +/*! @} */ + +/* The count of ADC_FCTRL */ +#define ADC_FCTRL_COUNT (2U) + +/*! @name GCC - Gain Calibration Control */ +/*! @{ */ + +#define ADC_GCC_GAIN_CAL_MASK (0xFFFFU) +#define ADC_GCC_GAIN_CAL_SHIFT (0U) +/*! GAIN_CAL - Gain Calibration Value + */ +#define ADC_GCC_GAIN_CAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_GCC_GAIN_CAL_SHIFT)) & ADC_GCC_GAIN_CAL_MASK) + +#define ADC_GCC_RDY_MASK (0x1000000U) +#define ADC_GCC_RDY_SHIFT (24U) +/*! RDY - Gain Calibration Value Valid + * 0b0..The gain calibration value is invalid. Run the auto-calibration routine for this value to be written. + * 0b1..The gain calibration value is valid. It should be used to update the GCRa[GCALR] register field. + */ +#define ADC_GCC_RDY(x) (((uint32_t)(((uint32_t)(x)) << ADC_GCC_RDY_SHIFT)) & ADC_GCC_RDY_MASK) +/*! @} */ + +/* The count of ADC_GCC */ +#define ADC_GCC_COUNT (2U) + +/*! @name GCR - Gain Calculation Result */ +/*! @{ */ + +#define ADC_GCR_GCALR_MASK (0xFFFFU) +#define ADC_GCR_GCALR_SHIFT (0U) +/*! GCALR - Gain Calculation Result + */ +#define ADC_GCR_GCALR(x) (((uint32_t)(((uint32_t)(x)) << ADC_GCR_GCALR_SHIFT)) & ADC_GCR_GCALR_MASK) + +#define ADC_GCR_RDY_MASK (0x1000000U) +#define ADC_GCR_RDY_SHIFT (24U) +/*! RDY - Gain Calculation Ready + * 0b0..The gain offset calculation value is invalid. + * 0b1..The gain calibration value is valid. + */ +#define ADC_GCR_RDY(x) (((uint32_t)(((uint32_t)(x)) << ADC_GCR_RDY_SHIFT)) & ADC_GCR_RDY_MASK) +/*! @} */ + +/* The count of ADC_GCR */ +#define ADC_GCR_COUNT (2U) + +/*! @name CMDL - ADC Command Low Buffer Register */ +/*! @{ */ + +#define ADC_CMDL_ADCH_MASK (0x1FU) +#define ADC_CMDL_ADCH_SHIFT (0U) +/*! ADCH - Input channel select + * 0b00000..Select CH0A or CH0B or CH0A/CH0B pair. + * 0b00001..Select CH1A or CH1B or CH1A/CH1B pair. + * 0b00010..Select CH2A or CH2B or CH2A/CH2B pair. + * 0b00011..Select CH3A or CH3B or CH3A/CH3B pair. + * 0b00100-0b11101..Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + * 0b11110..Select CH30A or CH30B or CH30A/CH30B pair. + * 0b11111..Select CH31A or CH31B or CH31A/CH31B pair. + */ +#define ADC_CMDL_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_ADCH_SHIFT)) & ADC_CMDL_ADCH_MASK) + +#define ADC_CMDL_CTYPE_MASK (0x60U) +#define ADC_CMDL_CTYPE_SHIFT (5U) +/*! CTYPE - Conversion Type + * 0b00..Single-Ended Mode. Only A side channel is converted. + * 0b01..Single-Ended Mode. Only B side channel is converted. + * 0b10..Differential Mode. A-B. + * 0b11..Dual-Single-Ended Mode. Both A side and B side channels are converted independently. + */ +#define ADC_CMDL_CTYPE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_CTYPE_SHIFT)) & ADC_CMDL_CTYPE_MASK) + +#define ADC_CMDL_MODE_MASK (0x80U) +#define ADC_CMDL_MODE_SHIFT (7U) +/*! MODE - Select resolution of conversions + * 0b0..Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion with 2's complement output. + * 0b1..High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with 2's complement output. + */ +#define ADC_CMDL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_MODE_SHIFT)) & ADC_CMDL_MODE_MASK) +/*! @} */ + +/* The count of ADC_CMDL */ +#define ADC_CMDL_COUNT (15U) + +/*! @name CMDH - ADC Command High Buffer Register */ +/*! @{ */ + +#define ADC_CMDH_CMPEN_MASK (0x3U) +#define ADC_CMDH_CMPEN_SHIFT (0U) +/*! CMPEN - Compare Function Enable + * 0b00..Compare disabled. + * 0b01..Reserved + * 0b10..Compare enabled. Store on true. + * 0b11..Compare enabled. Repeat channel acquisition (sample/convert/compare) until true. + */ +#define ADC_CMDH_CMPEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_CMPEN_SHIFT)) & ADC_CMDH_CMPEN_MASK) + +#define ADC_CMDH_WAIT_TRIG_MASK (0x4U) +#define ADC_CMDH_WAIT_TRIG_SHIFT (2U) +/*! WAIT_TRIG - Wait for trigger assertion before execution. + * 0b0..This command will be automatically executed. + * 0b1..The active trigger must be asserted again before executing this command. + */ +#define ADC_CMDH_WAIT_TRIG(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_WAIT_TRIG_SHIFT)) & ADC_CMDH_WAIT_TRIG_MASK) + +#define ADC_CMDH_LWI_MASK (0x80U) +#define ADC_CMDH_LWI_SHIFT (7U) +/*! LWI - Loop with Increment + * 0b0..Auto channel increment disabled + * 0b1..Auto channel increment enabled + */ +#define ADC_CMDH_LWI(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_LWI_SHIFT)) & ADC_CMDH_LWI_MASK) + +#define ADC_CMDH_STS_MASK (0x700U) +#define ADC_CMDH_STS_SHIFT (8U) +/*! STS - Sample Time Select + * 0b000..Minimum sample time of 3 ADCK cycles. + * 0b001..3 + 21 ADCK cycles; 5 ADCK cycles total sample time. + * 0b010..3 + 22 ADCK cycles; 7 ADCK cycles total sample time. + * 0b011..3 + 23 ADCK cycles; 11 ADCK cycles total sample time. + * 0b100..3 + 24 ADCK cycles; 19 ADCK cycles total sample time. + * 0b101..3 + 25 ADCK cycles; 35 ADCK cycles total sample time. + * 0b110..3 + 26 ADCK cycles; 67 ADCK cycles total sample time. + * 0b111..3 + 27 ADCK cycles; 131 ADCK cycles total sample time. + */ +#define ADC_CMDH_STS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_STS_SHIFT)) & ADC_CMDH_STS_MASK) + +#define ADC_CMDH_AVGS_MASK (0x7000U) +#define ADC_CMDH_AVGS_SHIFT (12U) +/*! AVGS - Hardware Average Select + * 0b000..Single conversion. + * 0b001..2 conversions averaged. + * 0b010..4 conversions averaged. + * 0b011..8 conversions averaged. + * 0b100..16 conversions averaged. + * 0b101..32 conversions averaged. + * 0b110..64 conversions averaged. + * 0b111..128 conversions averaged. + */ +#define ADC_CMDH_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_AVGS_SHIFT)) & ADC_CMDH_AVGS_MASK) + +#define ADC_CMDH_LOOP_MASK (0xF0000U) +#define ADC_CMDH_LOOP_SHIFT (16U) +/*! LOOP - Loop Count Select + * 0b0000..Looping not enabled. Command executes 1 time. + * 0b0001..Loop 1 time. Command executes 2 times. + * 0b0010..Loop 2 times. Command executes 3 times. + * 0b0011-0b1110..Loop corresponding number of times. Command executes LOOP+1 times. + * 0b1111..Loop 15 times. Command executes 16 times. + */ +#define ADC_CMDH_LOOP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_LOOP_SHIFT)) & ADC_CMDH_LOOP_MASK) + +#define ADC_CMDH_NEXT_MASK (0xF000000U) +#define ADC_CMDH_NEXT_SHIFT (24U) +/*! NEXT - Next Command Select + * 0b0000..No next command defined. Terminate conversions at completion of current command. If lower priority + * trigger pending, begin command associated with lower priority trigger. + * 0b0001..Select CMD1 command buffer register as next command. + * 0b0010-0b1110..Select corresponding CMD command buffer register as next command + * 0b1111..Select CMD15 command buffer register as next command. + */ +#define ADC_CMDH_NEXT(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_NEXT_SHIFT)) & ADC_CMDH_NEXT_MASK) +/*! @} */ + +/* The count of ADC_CMDH */ +#define ADC_CMDH_COUNT (15U) + +/*! @name CV - Compare Value Register */ +/*! @{ */ + +#define ADC_CV_CVL_MASK (0xFFFFU) +#define ADC_CV_CVL_SHIFT (0U) +/*! CVL - Compare Value Low. + */ +#define ADC_CV_CVL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CVL_SHIFT)) & ADC_CV_CVL_MASK) + +#define ADC_CV_CVH_MASK (0xFFFF0000U) +#define ADC_CV_CVH_SHIFT (16U) +/*! CVH - Compare Value High. + */ +#define ADC_CV_CVH(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CVH_SHIFT)) & ADC_CV_CVH_MASK) +/*! @} */ + +/* The count of ADC_CV */ +#define ADC_CV_COUNT (4U) + +/*! @name RESFIFO - ADC Data Result FIFO Register */ +/*! @{ */ + +#define ADC_RESFIFO_D_MASK (0xFFFFU) +#define ADC_RESFIFO_D_SHIFT (0U) +/*! D - Data result + */ +#define ADC_RESFIFO_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_D_SHIFT)) & ADC_RESFIFO_D_MASK) + +#define ADC_RESFIFO_TSRC_MASK (0xF0000U) +#define ADC_RESFIFO_TSRC_SHIFT (16U) +/*! TSRC - Trigger Source + * 0b0000..Trigger source 0 initiated this conversion. + * 0b0001..Trigger source 1 initiated this conversion. + * 0b0010-0b1110..Corresponding trigger source initiated this conversion. + * 0b1111..Trigger source 15 initiated this conversion. + */ +#define ADC_RESFIFO_TSRC(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_TSRC_SHIFT)) & ADC_RESFIFO_TSRC_MASK) + +#define ADC_RESFIFO_LOOPCNT_MASK (0xF00000U) +#define ADC_RESFIFO_LOOPCNT_SHIFT (20U) +/*! LOOPCNT - Loop count value + * 0b0000..Result is from initial conversion in command. + * 0b0001..Result is from second conversion in command. + * 0b0010-0b1110..Result is from LOOPCNT+1 conversion in command. + * 0b1111..Result is from 16th conversion in command. + */ +#define ADC_RESFIFO_LOOPCNT(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_LOOPCNT_SHIFT)) & ADC_RESFIFO_LOOPCNT_MASK) + +#define ADC_RESFIFO_CMDSRC_MASK (0xF000000U) +#define ADC_RESFIFO_CMDSRC_SHIFT (24U) +/*! CMDSRC - Command Buffer Source + * 0b0000..Not a valid value CMDSRC value for a dataword in RESFIFO. 0x0 is only found in initial FIFO state + * prior to an ADC conversion result dataword being stored to a RESFIFO buffer. + * 0b0001..CMD1 buffer used as control settings for this conversion. + * 0b0010-0b1110..Corresponding command buffer used as control settings for this conversion. + * 0b1111..CMD15 buffer used as control settings for this conversion. + */ +#define ADC_RESFIFO_CMDSRC(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_CMDSRC_SHIFT)) & ADC_RESFIFO_CMDSRC_MASK) + +#define ADC_RESFIFO_VALID_MASK (0x80000000U) +#define ADC_RESFIFO_VALID_SHIFT (31U) +/*! VALID - FIFO entry is valid + * 0b0..FIFO is empty. Discard any read from RESFIFO. + * 0b1..FIFO record read from RESFIFO is valid. + */ +#define ADC_RESFIFO_VALID(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_VALID_SHIFT)) & ADC_RESFIFO_VALID_MASK) +/*! @} */ + +/* The count of ADC_RESFIFO */ +#define ADC_RESFIFO_COUNT (2U) + +/*! @name CAL_GAR - Calibration General A-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GAR_CAL_GAR_VAL_MASK (0xFFFFU) +#define ADC_CAL_GAR_CAL_GAR_VAL_SHIFT (0U) +/*! CAL_GAR_VAL - Calibration General A Side Register Element + */ +#define ADC_CAL_GAR_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR_CAL_GAR_VAL_MASK) +/*! @} */ + +/* The count of ADC_CAL_GAR */ +#define ADC_CAL_GAR_COUNT (33U) + +/*! @name CAL_GBR - Calibration General B-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GBR_CAL_GBR_VAL_MASK (0xFFFFU) +#define ADC_CAL_GBR_CAL_GBR_VAL_SHIFT (0U) +/*! CAL_GBR_VAL - Calibration General B Side Register Element + */ +#define ADC_CAL_GBR_CAL_GBR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR_CAL_GBR_VAL_MASK) +/*! @} */ + +/* The count of ADC_CAL_GBR */ +#define ADC_CAL_GBR_COUNT (33U) + + +/*! + * @} + */ /* end of group ADC_Register_Masks */ + + +/* ADC - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral ADC0 base address */ + #define ADC0_BASE (0x500A0000u) + /** Peripheral ADC0 base address */ + #define ADC0_BASE_NS (0x400A0000u) + /** Peripheral ADC0 base pointer */ + #define ADC0 ((ADC_Type *)ADC0_BASE) + /** Peripheral ADC0 base pointer */ + #define ADC0_NS ((ADC_Type *)ADC0_BASE_NS) + /** Array initializer of ADC peripheral base addresses */ + #define ADC_BASE_ADDRS { ADC0_BASE } + /** Array initializer of ADC peripheral base pointers */ + #define ADC_BASE_PTRS { ADC0 } + /** Array initializer of ADC peripheral base addresses */ + #define ADC_BASE_ADDRS_NS { ADC0_BASE_NS } + /** Array initializer of ADC peripheral base pointers */ + #define ADC_BASE_PTRS_NS { ADC0_NS } +#else + /** Peripheral ADC0 base address */ + #define ADC0_BASE (0x400A0000u) + /** Peripheral ADC0 base pointer */ + #define ADC0 ((ADC_Type *)ADC0_BASE) + /** Array initializer of ADC peripheral base addresses */ + #define ADC_BASE_ADDRS { ADC0_BASE } + /** Array initializer of ADC peripheral base pointers */ + #define ADC_BASE_PTRS { ADC0 } +#endif +/** Interrupt vectors for the ADC peripheral type */ +#define ADC_IRQS { ADC0_IRQn } + +/*! + * @} + */ /* end of group ADC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- AHB_SECURE_CTRL Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup AHB_SECURE_CTRL_Peripheral_Access_Layer AHB_SECURE_CTRL Peripheral Access Layer + * @{ + */ + +/** AHB_SECURE_CTRL - Register Layout Typedef */ +typedef struct { + struct { /* offset: 0x0, array step: 0x30 */ + __IO uint32_t SLAVE_RULE; /**< Security access rules for Flash and ROM slaves., array offset: 0x0, array step: 0x30 */ + uint8_t RESERVED_0[12]; + __IO uint32_t SEC_CTRL_FLASH_MEM_RULE[1]; /**< Security access rules for FLASH sector 0 to sector 7. Each Flash sector is 32 Kbytes. There are 8 FLASH sectors in total., array offset: 0x10, array step: index*0x30, index2*0x4 */ + uint8_t RESERVED_1[12]; + __IO uint32_t SEC_CTRL_ROM_MEM_RULE[4]; /**< Security access rules for ROM sector 0 to sector 31. Each ROM sector is 4 Kbytes. There are 32 ROM sectors in total., array offset: 0x20, array step: index*0x30, index2*0x4 */ + } SEC_CTRL_FLASH_ROM[1]; + struct { /* offset: 0x30, array step: 0x14 */ + __IO uint32_t SLAVE_RULE; /**< Security access rules for RAMX slaves., array offset: 0x30, array step: 0x14 */ + uint8_t RESERVED_0[12]; + __IO uint32_t MEM_RULE[1]; /**< Security access rules for RAMX slaves., array offset: 0x40, array step: index*0x14, index2*0x4 */ + } SEC_CTRL_RAMX[1]; + uint8_t RESERVED_0[12]; + struct { /* offset: 0x50, array step: 0x14 */ + __IO uint32_t SLAVE_RULE; /**< Security access rules for RAM0 slaves., array offset: 0x50, array step: 0x14 */ + uint8_t RESERVED_0[12]; + __IO uint32_t MEM_RULE[1]; /**< Security access rules for RAM0 slaves., array offset: 0x60, array step: index*0x14, index2*0x4 */ + } SEC_CTRL_RAM0[1]; + uint8_t RESERVED_1[12]; + struct { /* offset: 0x70, array step: 0x14 */ + __IO uint32_t SLAVE_RULE; /**< Security access rules for RAM1 slaves., array offset: 0x70, array step: 0x14 */ + uint8_t RESERVED_0[12]; + __IO uint32_t MEM_RULE[1]; /**< Security access rules for RAM1 slaves., array offset: 0x80, array step: index*0x14, index2*0x4 */ + } SEC_CTRL_RAM1[1]; + uint8_t RESERVED_2[12]; + struct { /* offset: 0x90, array step: 0x14 */ + __IO uint32_t SLAVE_RULE; /**< Security access rules for RAM2 slaves., array offset: 0x90, array step: 0x14 */ + uint8_t RESERVED_0[12]; + __IO uint32_t MEM_RULE[1]; /**< Security access rules for RAM2 slaves., array offset: 0xA0, array step: index*0x14, index2*0x4 */ + } SEC_CTRL_RAM2[1]; + uint8_t RESERVED_3[12]; + struct { /* offset: 0xB0, array step: 0x14 */ + __IO uint32_t SLAVE_RULE; /**< Security access rules for USB High speed RAM slaves., array offset: 0xB0, array step: 0x14 */ + uint8_t RESERVED_0[12]; + __IO uint32_t MEM_RULE[1]; /**< Security access rules for RAM_USB_HS., array offset: 0xC0, array step: index*0x14, index2*0x4 */ + } SEC_CTRL_USB_HS[1]; + uint8_t RESERVED_4[12]; + struct { /* offset: 0xD0, array step: 0x30 */ + __IO uint32_t SLAVE_RULE; /**< Security access rules for both APB Bridges slaves., array offset: 0xD0, array step: 0x30 */ + uint8_t RESERVED_0[12]; + __IO uint32_t SEC_CTRL_APB_BRIDGE0_MEM_CTRL0; /**< Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total., array offset: 0xE0, array step: 0x30 */ + __IO uint32_t SEC_CTRL_APB_BRIDGE0_MEM_CTRL1; /**< Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total., array offset: 0xE4, array step: 0x30 */ + __IO uint32_t SEC_CTRL_APB_BRIDGE0_MEM_CTRL2; /**< Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total., array offset: 0xE8, array step: 0x30 */ + uint8_t RESERVED_1[4]; + __IO uint32_t SEC_CTRL_APB_BRIDGE1_MEM_CTRL0; /**< Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total., array offset: 0xF0, array step: 0x30 */ + __IO uint32_t SEC_CTRL_APB_BRIDGE1_MEM_CTRL1; /**< Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total., array offset: 0xF4, array step: 0x30 */ + __IO uint32_t SEC_CTRL_APB_BRIDGE1_MEM_CTRL2; /**< Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total., array offset: 0xF8, array step: 0x30 */ + __IO uint32_t SEC_CTRL_APB_BRIDGE1_MEM_CTRL3; /**< Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total., array offset: 0xFC, array step: 0x30 */ + } SEC_CTRL_APB_BRIDGE[1]; + __IO uint32_t SEC_CTRL_AHB_PORT7_SLAVE0_RULE; /**< Security access rules for AHB peripherals., offset: 0x100 */ + __IO uint32_t SEC_CTRL_AHB_PORT7_SLAVE1_RULE; /**< Security access rules for AHB peripherals., offset: 0x104 */ + uint8_t RESERVED_5[8]; + __IO uint32_t SEC_CTRL_AHB_PORT8_SLAVE0_RULE; /**< Security access rules for AHB peripherals., offset: 0x110 */ + __IO uint32_t SEC_CTRL_AHB_PORT8_SLAVE1_RULE; /**< Security access rules for AHB peripherals., offset: 0x114 */ + uint8_t RESERVED_6[8]; + struct { /* offset: 0x120, array step: 0x14 */ + __IO uint32_t SLAVE0_RULE; /**< Security access rules for AHB peripherals., array offset: 0x120, array step: 0x14 */ + __IO uint32_t SLAVE1_RULE; /**< Security access rules for AHB peripherals., array offset: 0x124, array step: 0x14 */ + uint8_t RESERVED_0[8]; + __IO uint32_t SEC_CTRL_AHB_SEC_CTRL_MEM_RULE[1]; /**< Security access rules for AHB_SEC_CTRL_AHB., array offset: 0x130, array step: index*0x14, index2*0x4 */ + } SEC_CTRL_AHB_PORT9[1]; + uint8_t RESERVED_7[3276]; + __I uint32_t SEC_VIO_ADDR[10]; /**< most recent security violation address for AHB layer n, array offset: 0xE00, array step: 0x4 */ + uint8_t RESERVED_8[88]; + __I uint32_t SEC_VIO_MISC_INFO[10]; /**< most recent security violation miscellaneous information for AHB layer n, array offset: 0xE80, array step: 0x4 */ + uint8_t RESERVED_9[88]; + __IO uint32_t SEC_VIO_INFO_VALID; /**< security violation address/information registers valid flags, offset: 0xF00 */ + uint8_t RESERVED_10[124]; + __IO uint32_t SEC_GPIO_MASK0; /**< Secure GPIO mask for port 0 pins., offset: 0xF80 */ + __IO uint32_t SEC_GPIO_MASK1; /**< Secure GPIO mask for port 1 pins., offset: 0xF84 */ + uint8_t RESERVED_11[52]; + __IO uint32_t SEC_MASK_LOCK; /**< Security General Purpose register access control., offset: 0xFBC */ + uint8_t RESERVED_12[16]; + __IO uint32_t MASTER_SEC_LEVEL; /**< master secure level register, offset: 0xFD0 */ + __IO uint32_t MASTER_SEC_ANTI_POL_REG; /**< master secure level anti-pole register, offset: 0xFD4 */ + uint8_t RESERVED_13[20]; + __IO uint32_t CPU0_LOCK_REG; /**< Miscalleneous control signals for in Cortex M33 (CPU0), offset: 0xFEC */ + uint8_t RESERVED_14[8]; + __IO uint32_t MISC_CTRL_DP_REG; /**< secure control duplicate register, offset: 0xFF8 */ + __IO uint32_t MISC_CTRL_REG; /**< secure control register, offset: 0xFFC */ +} AHB_SECURE_CTRL_Type; + +/* ---------------------------------------------------------------------------- + -- AHB_SECURE_CTRL Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup AHB_SECURE_CTRL_Register_Masks AHB_SECURE_CTRL Register Masks + * @{ + */ + +/*! @name SEC_CTRL_FLASH_ROM_SLAVE_RULE - Security access rules for Flash and ROM slaves. */ +/*! @{ */ + +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_FLASH_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_FLASH_RULE_SHIFT (0U) +/*! FLASH_RULE - Security access rules for the whole FLASH : 0x0000_0000 - 0x0003_FFFF + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_FLASH_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_FLASH_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_FLASH_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_ROM_RULE_MASK (0x30U) +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_ROM_RULE_SHIFT (4U) +/*! ROM_RULE - Security access rules for the whole ROM : 0x0300_0000 - 0x0301_FFFF + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_ROM_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_ROM_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_ROM_RULE_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_COUNT (1U) + +/*! @name SEC_CTRL_FLASH_MEM_RULE - Security access rules for FLASH sector 0 to sector 7. Each Flash sector is 32 Kbytes. There are 8 FLASH sectors in total. */ +/*! @{ */ + +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE0_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE0_SHIFT (0U) +/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE0_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE1_MASK (0x30U) +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE1_SHIFT (4U) +/*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE1_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE2_MASK (0x300U) +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE2_SHIFT (8U) +/*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE2_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE3_MASK (0x3000U) +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE3_SHIFT (12U) +/*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE3_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE4_MASK (0x30000U) +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE4_SHIFT (16U) +/*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE4_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE5_MASK (0x300000U) +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE5_SHIFT (20U) +/*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE5_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE6_MASK (0x3000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE6_SHIFT (24U) +/*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE6_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE7_MASK (0x30000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE7_SHIFT (28U) +/*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE7_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_COUNT (1U) + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_COUNT2 (1U) + +/*! @name SEC_CTRL_ROM_MEM_RULE - Security access rules for ROM sector 0 to sector 31. Each ROM sector is 4 Kbytes. There are 32 ROM sectors in total. */ +/*! @{ */ + +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE0_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE0_SHIFT (0U) +/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE0_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE1_MASK (0x30U) +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE1_SHIFT (4U) +/*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE1_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE2_MASK (0x300U) +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE2_SHIFT (8U) +/*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE2_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE3_MASK (0x3000U) +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE3_SHIFT (12U) +/*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE3_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE4_MASK (0x30000U) +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE4_SHIFT (16U) +/*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE4_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE5_MASK (0x300000U) +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE5_SHIFT (20U) +/*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE5_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE6_MASK (0x3000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE6_SHIFT (24U) +/*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE6_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE7_MASK (0x30000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE7_SHIFT (28U) +/*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE7_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_COUNT (1U) + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_COUNT2 (4U) + +/*! @name SEC_CTRL_RAMX_SLAVE_RULE - Security access rules for RAMX slaves. */ +/*! @{ */ + +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE_RAMX_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE_RAMX_RULE_SHIFT (0U) +/*! RAMX_RULE - Security access rules for the whole RAMX : 0x0400_0000 - 0x0400_7FFF + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE_RAMX_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE_RAMX_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE_RAMX_RULE_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE_COUNT (1U) + +/*! @name SEC_CTRL_RAMX_MEM_RULE - Security access rules for RAMX slaves. */ +/*! @{ */ + +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE0_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE0_SHIFT (0U) +/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE0_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE1_MASK (0x30U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE1_SHIFT (4U) +/*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE1_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE2_MASK (0x300U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE2_SHIFT (8U) +/*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE2_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE3_MASK (0x3000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE3_SHIFT (12U) +/*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE3_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_COUNT (1U) + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_COUNT2 (1U) + +/*! @name SEC_CTRL_RAM0_SLAVE_RULE - Security access rules for RAM0 slaves. */ +/*! @{ */ + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE_RAM0_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE_RAM0_RULE_SHIFT (0U) +/*! RAM0_RULE - Security access rules for the whole RAM0 : 0x2000_0000 - 0x2000_7FFF + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE_RAM0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE_RAM0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE_RAM0_RULE_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE_COUNT (1U) + +/*! @name SEC_CTRL_RAM0_MEM_RULE - Security access rules for RAM0 slaves. */ +/*! @{ */ + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE0_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE0_SHIFT (0U) +/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE0_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE1_MASK (0x30U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE1_SHIFT (4U) +/*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE1_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE2_MASK (0x300U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE2_SHIFT (8U) +/*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE2_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE3_MASK (0x3000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE3_SHIFT (12U) +/*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE3_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE4_MASK (0x30000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE4_SHIFT (16U) +/*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE4_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE5_MASK (0x300000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE5_SHIFT (20U) +/*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE5_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE6_MASK (0x3000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE6_SHIFT (24U) +/*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE6_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE7_MASK (0x30000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE7_SHIFT (28U) +/*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE7_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_COUNT (1U) + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_COUNT2 (1U) + +/*! @name SEC_CTRL_RAM1_SLAVE_RULE - Security access rules for RAM1 slaves. */ +/*! @{ */ + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_RAM1_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_RAM1_RULE_SHIFT (0U) +/*! RAM1_RULE - Security access rules for the whole RAM1 : 0x2000_8000 - 0x2000_BFFF + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_RAM1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_RAM1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_RAM1_RULE_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_COUNT (1U) + +/*! @name SEC_CTRL_RAM1_MEM_RULE - Security access rules for RAM1 slaves. */ +/*! @{ */ + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE0_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE0_SHIFT (0U) +/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE0_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE1_MASK (0x30U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE1_SHIFT (4U) +/*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE1_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE2_MASK (0x300U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE2_SHIFT (8U) +/*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE2_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE3_MASK (0x3000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE3_SHIFT (12U) +/*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE3_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_COUNT (1U) + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_COUNT2 (1U) + +/*! @name SEC_CTRL_RAM2_SLAVE_RULE - Security access rules for RAM2 slaves. */ +/*! @{ */ + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE_RAM2_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE_RAM2_RULE_SHIFT (0U) +/*! RAM2_RULE - Security access rules for the whole RAM2 : 0x2000_C000 - 0x2000_FFFF + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE_RAM2_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE_RAM2_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE_RAM2_RULE_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE_COUNT (1U) + +/*! @name SEC_CTRL_RAM2_MEM_RULE - Security access rules for RAM2 slaves. */ +/*! @{ */ + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE0_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE0_SHIFT (0U) +/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE0_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE1_MASK (0x30U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE1_SHIFT (4U) +/*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE1_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE2_MASK (0x300U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE2_SHIFT (8U) +/*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE2_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE3_MASK (0x3000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE3_SHIFT (12U) +/*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE3_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_COUNT (1U) + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_COUNT2 (1U) + +/*! @name SEC_CTRL_USB_HS_SLAVE_RULE - Security access rules for USB High speed RAM slaves. */ +/*! @{ */ + +#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE_RAM_USB_HS_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE_RAM_USB_HS_RULE_SHIFT (0U) +/*! RAM_USB_HS_RULE - Security access rules for the whole USB High Speed RAM : 0x2001_0000 - 0x2001_3FFF + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE_RAM_USB_HS_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE_RAM_USB_HS_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE_RAM_USB_HS_RULE_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE_COUNT (1U) + +/*! @name SEC_CTRL_USB_HS_MEM_RULE - Security access rules for RAM_USB_HS. */ +/*! @{ */ + +#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_0_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_0_RULE_SHIFT (0U) +/*! SRAM_SECT_0_RULE - Address space: 0x2001_0000 - 0x2001_0FFF + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_0_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_1_RULE_MASK (0x30U) +#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_1_RULE_SHIFT (4U) +/*! SRAM_SECT_1_RULE - Address space: 0x2001_1000 - 0x2001_1FFF + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_1_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_2_RULE_MASK (0x300U) +#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_2_RULE_SHIFT (8U) +/*! SRAM_SECT_2_RULE - Address space: 0x2001_2000 - 0x2001_2FFF + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_2_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_2_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_2_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_3_RULE_MASK (0x3000U) +#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_3_RULE_SHIFT (12U) +/*! SRAM_SECT_3_RULE - Address space: 0x2001_3000 - 0x2001_3FFF + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_3_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_3_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_3_RULE_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_COUNT (1U) + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_COUNT2 (1U) + +/*! @name SEC_CTRL_APB_BRIDGE_SLAVE_RULE - Security access rules for both APB Bridges slaves. */ +/*! @{ */ + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE0_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE0_RULE_SHIFT (0U) +/*! APBBRIDGE0_RULE - Security access rules for the whole APB Bridge 0 + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE0_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE1_RULE_MASK (0x30U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE1_RULE_SHIFT (4U) +/*! APBBRIDGE1_RULE - Security access rules for the whole APB Bridge 1 + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE1_RULE_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_COUNT (1U) + +/*! @name SEC_CTRL_APB_BRIDGE0_MEM_CTRL0 - Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total. */ +/*! @{ */ + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SYSCON_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SYSCON_RULE_SHIFT (0U) +/*! SYSCON_RULE - System Configuration + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SYSCON_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SYSCON_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SYSCON_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_IOCON_RULE_MASK (0x30U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_IOCON_RULE_SHIFT (4U) +/*! IOCON_RULE - I/O Configuration + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_IOCON_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_IOCON_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_IOCON_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT0_RULE_MASK (0x300U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT0_RULE_SHIFT (8U) +/*! GINT0_RULE - GPIO input Interrupt 0 + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT0_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT1_RULE_MASK (0x3000U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT1_RULE_SHIFT (12U) +/*! GINT1_RULE - GPIO input Interrupt 1 + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT1_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PINT_RULE_MASK (0x30000U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PINT_RULE_SHIFT (16U) +/*! PINT_RULE - Pin Interrupt and Pattern match + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PINT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PINT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PINT_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SEC_PINT_RULE_MASK (0x300000U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SEC_PINT_RULE_SHIFT (20U) +/*! SEC_PINT_RULE - Secure Pin Interrupt and Pattern match + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SEC_PINT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SEC_PINT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SEC_PINT_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_INPUTMUX_RULE_MASK (0x3000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_INPUTMUX_RULE_SHIFT (24U) +/*! INPUTMUX_RULE - Peripheral input multiplexing + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_INPUTMUX_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_INPUTMUX_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_INPUTMUX_RULE_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0 */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_COUNT (1U) + +/*! @name SEC_CTRL_APB_BRIDGE0_MEM_CTRL1 - Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total. */ +/*! @{ */ + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER0_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER0_RULE_SHIFT (0U) +/*! CTIMER0_RULE - Standard counter/Timer 0 + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER0_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER1_RULE_MASK (0x30U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER1_RULE_SHIFT (4U) +/*! CTIMER1_RULE - Standard counter/Timer 1 + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER1_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_WWDT_RULE_MASK (0x30000U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_WWDT_RULE_SHIFT (16U) +/*! WWDT_RULE - Windiwed wtachdog Timer + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_WWDT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_WWDT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_WWDT_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_MRT_RULE_MASK (0x300000U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_MRT_RULE_SHIFT (20U) +/*! MRT_RULE - Multi-rate Timer + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_MRT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_MRT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_MRT_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_UTICK_RULE_MASK (0x3000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_UTICK_RULE_SHIFT (24U) +/*! UTICK_RULE - Micro-Timer + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_UTICK_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_UTICK_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_UTICK_RULE_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1 */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_COUNT (1U) + +/*! @name SEC_CTRL_APB_BRIDGE0_MEM_CTRL2 - Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total. */ +/*! @{ */ + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_ANACTRL_RULE_MASK (0x3000U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_ANACTRL_RULE_SHIFT (12U) +/*! ANACTRL_RULE - Analog Modules controller + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_ANACTRL_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_ANACTRL_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_ANACTRL_RULE_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2 */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_COUNT (1U) + +/*! @name SEC_CTRL_APB_BRIDGE1_MEM_CTRL0 - Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total. */ +/*! @{ */ + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PMC_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PMC_RULE_SHIFT (0U) +/*! PMC_RULE - Power Management Controller + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PMC_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PMC_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PMC_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SYSCTRL_RULE_MASK (0x3000U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SYSCTRL_RULE_SHIFT (12U) +/*! SYSCTRL_RULE - System Controller + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SYSCTRL_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SYSCTRL_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SYSCTRL_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SPI_FILTER_RULE_MASK (0x30000U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SPI_FILTER_RULE_SHIFT (16U) +/*! SPI_FILTER_RULE - SPI FILTER control + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SPI_FILTER_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SPI_FILTER_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SPI_FILTER_RULE_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0 */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_COUNT (1U) + +/*! @name SEC_CTRL_APB_BRIDGE1_MEM_CTRL1 - Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total. */ +/*! @{ */ + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER2_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER2_RULE_SHIFT (0U) +/*! CTIMER2_RULE - Standard counter/Timer 2 + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER2_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER2_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER2_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER3_RULE_MASK (0x30U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER3_RULE_SHIFT (4U) +/*! CTIMER3_RULE - Standard counter/Timer 3 + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER3_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER3_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER3_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER4_RULE_MASK (0x300U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER4_RULE_SHIFT (8U) +/*! CTIMER4_RULE - Standard counter/Timer 4 + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER4_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER4_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER4_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_RTC_RULE_MASK (0x30000U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_RTC_RULE_SHIFT (16U) +/*! RTC_RULE - Real Time Counter + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_RTC_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_RTC_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_RTC_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_OSEVENT_RULE_MASK (0x300000U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_OSEVENT_RULE_SHIFT (20U) +/*! OSEVENT_RULE - OS Event Timer + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_OSEVENT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_OSEVENT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_OSEVENT_RULE_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1 */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_COUNT (1U) + +/*! @name SEC_CTRL_APB_BRIDGE1_MEM_CTRL2 - Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total. */ +/*! @{ */ + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_FLASH_CTRL_RULE_MASK (0x30000U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_FLASH_CTRL_RULE_SHIFT (16U) +/*! FLASH_CTRL_RULE - Flash Controller + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_FLASH_CTRL_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_FLASH_CTRL_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_FLASH_CTRL_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_PRINCE_RULE_MASK (0x300000U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_PRINCE_RULE_SHIFT (20U) +/*! PRINCE_RULE - Prince + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_PRINCE_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_PRINCE_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_PRINCE_RULE_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2 */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_COUNT (1U) + +/*! @name SEC_CTRL_APB_BRIDGE1_MEM_CTRL3 - Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total. */ +/*! @{ */ + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_USBHPHY_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_USBHPHY_RULE_SHIFT (0U) +/*! USBHPHY_RULE - USB High Speed Phy controller + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_USBHPHY_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_USBHPHY_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_USBHPHY_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_RNG_RULE_MASK (0x300U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_RNG_RULE_SHIFT (8U) +/*! RNG_RULE - True Random Number Generator + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_RNG_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_RNG_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_RNG_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PUF_RULE_MASK (0x3000U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PUF_RULE_SHIFT (12U) +/*! PUF_RULE - PUF + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PUF_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PUF_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PUF_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PLU_RULE_MASK (0x300000U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PLU_RULE_SHIFT (20U) +/*! PLU_RULE - Programmable Look-Up logic + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PLU_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PLU_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PLU_RULE_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3 */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_COUNT (1U) + +/*! @name SEC_CTRL_AHB_PORT7_SLAVE0_RULE - Security access rules for AHB peripherals. */ +/*! @{ */ + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE0_RULE_DMA0_RULE_MASK (0x300U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE0_RULE_DMA0_RULE_SHIFT (8U) +/*! DMA0_RULE - DMA Controller + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE0_RULE_DMA0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE0_RULE_DMA0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE0_RULE_DMA0_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE0_RULE_FS_USB_DEV_RULE_MASK (0x30000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE0_RULE_FS_USB_DEV_RULE_SHIFT (16U) +/*! FS_USB_DEV_RULE - USB Full-speed device + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE0_RULE_FS_USB_DEV_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE0_RULE_FS_USB_DEV_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE0_RULE_FS_USB_DEV_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE0_RULE_SCT_RULE_MASK (0x300000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE0_RULE_SCT_RULE_SHIFT (20U) +/*! SCT_RULE - SCTimer + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE0_RULE_SCT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE0_RULE_SCT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE0_RULE_SCT_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE0_RULE_FLEXCOMM0_RULE_MASK (0x3000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE0_RULE_FLEXCOMM0_RULE_SHIFT (24U) +/*! FLEXCOMM0_RULE - Flexcomm interface 0 + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE0_RULE_FLEXCOMM0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE0_RULE_FLEXCOMM0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE0_RULE_FLEXCOMM0_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE0_RULE_FLEXCOMM1_RULE_MASK (0x30000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE0_RULE_FLEXCOMM1_RULE_SHIFT (28U) +/*! FLEXCOMM1_RULE - Flexcomm interface 1 + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE0_RULE_FLEXCOMM1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE0_RULE_FLEXCOMM1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE0_RULE_FLEXCOMM1_RULE_MASK) +/*! @} */ + +/*! @name SEC_CTRL_AHB_PORT7_SLAVE1_RULE - Security access rules for AHB peripherals. */ +/*! @{ */ + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE1_RULE_FLEXCOMM2_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE1_RULE_FLEXCOMM2_RULE_SHIFT (0U) +/*! FLEXCOMM2_RULE - Flexcomm interface 2 + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE1_RULE_FLEXCOMM2_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE1_RULE_FLEXCOMM2_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE1_RULE_FLEXCOMM2_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE1_RULE_FLEXCOMM3_RULE_MASK (0x30U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE1_RULE_FLEXCOMM3_RULE_SHIFT (4U) +/*! FLEXCOMM3_RULE - Flexcomm interface 3 + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE1_RULE_FLEXCOMM3_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE1_RULE_FLEXCOMM3_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE1_RULE_FLEXCOMM3_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE1_RULE_FLEXCOMM4_RULE_MASK (0x300U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE1_RULE_FLEXCOMM4_RULE_SHIFT (8U) +/*! FLEXCOMM4_RULE - Flexcomm interface 4 + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE1_RULE_FLEXCOMM4_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE1_RULE_FLEXCOMM4_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE1_RULE_FLEXCOMM4_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE1_RULE_GPIO0_RULE_MASK (0x30000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE1_RULE_GPIO0_RULE_SHIFT (16U) +/*! GPIO0_RULE - High Speed GPIO + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE1_RULE_GPIO0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE1_RULE_GPIO0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT7_SLAVE1_RULE_GPIO0_RULE_MASK) +/*! @} */ + +/*! @name SEC_CTRL_AHB_PORT8_SLAVE0_RULE - Security access rules for AHB peripherals. */ +/*! @{ */ + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_USB_HS_DEV_RULE_MASK (0x30000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_USB_HS_DEV_RULE_SHIFT (16U) +/*! USB_HS_DEV_RULE - USB high Speed device registers + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_USB_HS_DEV_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_USB_HS_DEV_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_USB_HS_DEV_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_CRC_RULE_MASK (0x300000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_CRC_RULE_SHIFT (20U) +/*! CRC_RULE - CRC engine + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_CRC_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_CRC_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_CRC_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM5_RULE_MASK (0x3000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM5_RULE_SHIFT (24U) +/*! FLEXCOMM5_RULE - Flexcomm interface 5 + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM5_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM5_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM5_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM6_RULE_MASK (0x30000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM6_RULE_SHIFT (28U) +/*! FLEXCOMM6_RULE - Flexcomm interface 6 + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM6_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM6_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM6_RULE_MASK) +/*! @} */ + +/*! @name SEC_CTRL_AHB_PORT8_SLAVE1_RULE - Security access rules for AHB peripherals. */ +/*! @{ */ + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM7_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM7_RULE_SHIFT (0U) +/*! FLEXCOMM7_RULE - Flexcomm interface 7 + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM7_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM7_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM7_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_DBG_MAILBOX_RULE_MASK (0x30000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_DBG_MAILBOX_RULE_SHIFT (16U) +/*! DBG_MAILBOX_RULE - Debug mailbox (aka ISP-AP) + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_DBG_MAILBOX_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_DBG_MAILBOX_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_DBG_MAILBOX_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_CAN0_RULE_MASK (0x300000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_CAN0_RULE_SHIFT (20U) +/*! CAN0_RULE - CAN-FD + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_CAN0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_CAN0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_CAN0_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_HS_LSPI_RULE_MASK (0x30000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_HS_LSPI_RULE_SHIFT (28U) +/*! HS_LSPI_RULE - High Speed SPI + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_HS_LSPI_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_HS_LSPI_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_HS_LSPI_RULE_MASK) +/*! @} */ + +/*! @name SEC_CTRL_AHB_PORT9_SLAVE0_RULE - Security access rules for AHB peripherals. */ +/*! @{ */ + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_ADC_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_ADC_RULE_SHIFT (0U) +/*! ADC_RULE - ADC + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_ADC_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_ADC_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_ADC_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_USB_FS_HOST_RULE_MASK (0x300U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_USB_FS_HOST_RULE_SHIFT (8U) +/*! USB_FS_HOST_RULE - USB Full Speed Host registers. + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_USB_FS_HOST_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_USB_FS_HOST_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_USB_FS_HOST_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_USB_HS_HOST_RULE_MASK (0x3000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_USB_HS_HOST_RULE_SHIFT (12U) +/*! USB_HS_HOST_RULE - USB High speed host registers + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_USB_HS_HOST_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_USB_HS_HOST_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_USB_HS_HOST_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_HASH_RULE_MASK (0x30000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_HASH_RULE_SHIFT (16U) +/*! HASH_RULE - SHA-2 crypto registers + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_HASH_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_HASH_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_HASH_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_CASPER_RULE_MASK (0x300000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_CASPER_RULE_SHIFT (20U) +/*! CASPER_RULE - RSA/ECC crypto accelerator + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_CASPER_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_CASPER_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_CASPER_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_DMA1_RULE_MASK (0x30000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_DMA1_RULE_SHIFT (28U) +/*! DMA1_RULE - DMA Controller (Secure) + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_DMA1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_DMA1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_DMA1_RULE_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_COUNT (1U) + +/*! @name SEC_CTRL_AHB_PORT9_SLAVE1_RULE - Security access rules for AHB peripherals. */ +/*! @{ */ + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_GPIO1_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_GPIO1_RULE_SHIFT (0U) +/*! GPIO1_RULE - Secure High Speed GPIO + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_GPIO1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_GPIO1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_GPIO1_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_AHB_SEC_CTRL_RULE_MASK (0x30U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_AHB_SEC_CTRL_RULE_SHIFT (4U) +/*! AHB_SEC_CTRL_RULE - AHB Secure Controller + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_AHB_SEC_CTRL_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_AHB_SEC_CTRL_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_AHB_SEC_CTRL_RULE_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_COUNT (1U) + +/*! @name SEC_CTRL_AHB_SEC_CTRL_MEM_RULE - Security access rules for AHB_SEC_CTRL_AHB. */ +/*! @{ */ + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_0_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_0_RULE_SHIFT (0U) +/*! AHB_SEC_CTRL_SECT_0_RULE - Address space: 0x400A_0000 - 0x400A_CFFF + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_0_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_1_RULE_MASK (0x30U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_1_RULE_SHIFT (4U) +/*! AHB_SEC_CTRL_SECT_1_RULE - Address space: 0x400A_D000 - 0x400A_DFFF + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_1_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_2_RULE_MASK (0x300U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_2_RULE_SHIFT (8U) +/*! AHB_SEC_CTRL_SECT_2_RULE - Address space: 0x400A_E000 - 0x400A_EFFF + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_2_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_2_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_2_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_3_RULE_MASK (0x3000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_3_RULE_SHIFT (12U) +/*! AHB_SEC_CTRL_SECT_3_RULE - Address space: 0x400A_F000 - 0x400A_FFFF + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_3_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_3_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_3_RULE_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_COUNT (1U) + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_COUNT2 (1U) + +/*! @name SEC_VIO_ADDR - most recent security violation address for AHB layer n */ +/*! @{ */ + +#define AHB_SECURE_CTRL_SEC_VIO_ADDR_SEC_VIO_ADDR_MASK (0xFFFFFFFFU) +#define AHB_SECURE_CTRL_SEC_VIO_ADDR_SEC_VIO_ADDR_SHIFT (0U) +/*! SEC_VIO_ADDR - security violation address for AHB layer + */ +#define AHB_SECURE_CTRL_SEC_VIO_ADDR_SEC_VIO_ADDR(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_ADDR_SEC_VIO_ADDR_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_ADDR_SEC_VIO_ADDR_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_VIO_ADDR */ +#define AHB_SECURE_CTRL_SEC_VIO_ADDR_COUNT (10U) + +/*! @name SEC_VIO_MISC_INFO - most recent security violation miscellaneous information for AHB layer n */ +/*! @{ */ + +#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_MASK (0x1U) +#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_SHIFT (0U) +/*! SEC_VIO_INFO_WRITE - security violation access read/write indicator. + * 0b0..Read access. + * 0b1..Write access. + */ +#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_MASK) + +#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_MASK (0x2U) +#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_SHIFT (1U) +/*! SEC_VIO_INFO_DATA_ACCESS - security violation access data/code indicator. + * 0b0..Code access. + * 0b1..Data access. + */ +#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_MASK) + +#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_MASK (0xF0U) +#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_SHIFT (4U) +/*! SEC_VIO_INFO_MASTER_SEC_LEVEL - bit [5:4]: master sec level and privilege level bit [7:6]: anti-pol value for master sec level and privilege level + */ +#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_MASK) + +#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_MASK (0xF00U) +#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SHIFT (8U) +/*! SEC_VIO_INFO_MASTER - security violation master number + * 0b0000..CPU0 Code. + * 0b0001..CPU0 System. + * 0b0100..USB-HS Device. + * 0b0101..SDMA0. + * 0b1010..HASH. + * 0b1011..USB-FS Host. + * 0b1100..SDMA1. + * 0b1101..CAN-FD. + */ +#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_VIO_MISC_INFO */ +#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_COUNT (10U) + +/*! @name SEC_VIO_INFO_VALID - security violation address/information registers valid flags */ +/*! @{ */ + +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_MASK (0x1U) +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_SHIFT (0U) +/*! VIO_INFO_VALID0 - violation information valid flag for AHB port 0. Write 1 to clear. + * 0b0..Not valid. + * 0b1..Valid (violation occurred). + */ +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_MASK) + +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_MASK (0x2U) +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_SHIFT (1U) +/*! VIO_INFO_VALID1 - violation information valid flag for AHB port 1. Write 1 to clear. + * 0b0..Not valid. + * 0b1..Valid (violation occurred). + */ +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_MASK) + +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_MASK (0x4U) +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_SHIFT (2U) +/*! VIO_INFO_VALID2 - violation information valid flag for AHB port 2. Write 1 to clear. + * 0b0..Not valid. + * 0b1..Valid (violation occurred). + */ +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_MASK) + +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_MASK (0x8U) +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_SHIFT (3U) +/*! VIO_INFO_VALID3 - violation information valid flag for AHB port 3. Write 1 to clear. + * 0b0..Not valid. + * 0b1..Valid (violation occurred). + */ +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_MASK) + +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_MASK (0x10U) +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_SHIFT (4U) +/*! VIO_INFO_VALID4 - violation information valid flag for AHB port 4. Write 1 to clear. + * 0b0..Not valid. + * 0b1..Valid (violation occurred). + */ +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_MASK) + +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_MASK (0x20U) +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_SHIFT (5U) +/*! VIO_INFO_VALID5 - violation information valid flag for AHB port 5. Write 1 to clear. + * 0b0..Not valid. + * 0b1..Valid (violation occurred). + */ +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_MASK) + +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_MASK (0x40U) +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_SHIFT (6U) +/*! VIO_INFO_VALID6 - violation information valid flag for AHB port 6. Write 1 to clear. + * 0b0..Not valid. + * 0b1..Valid (violation occurred). + */ +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_MASK) + +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_MASK (0x80U) +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_SHIFT (7U) +/*! VIO_INFO_VALID7 - violation information valid flag for AHB port 7. Write 1 to clear. + * 0b0..Not valid. + * 0b1..Valid (violation occurred). + */ +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_MASK) + +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_MASK (0x100U) +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_SHIFT (8U) +/*! VIO_INFO_VALID8 - violation information valid flag for AHB port 8. Write 1 to clear. + * 0b0..Not valid. + * 0b1..Valid (violation occurred). + */ +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_MASK) + +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_MASK (0x200U) +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_SHIFT (9U) +/*! VIO_INFO_VALID9 - violation information valid flag for AHB port 9. Write 1 to clear. + * 0b0..Not valid. + * 0b1..Valid (violation occurred). + */ +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_MASK) +/*! @} */ + +/*! @name SEC_GPIO_MASK0 - Secure GPIO mask for port 0 pins. */ +/*! @{ */ + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN0_SEC_MASK_MASK (0x1U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN0_SEC_MASK_SHIFT (0U) +/*! PIO0_PIN0_SEC_MASK - Secure mask for pin P0_0 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN0_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN0_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN0_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN1_SEC_MASK_MASK (0x2U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN1_SEC_MASK_SHIFT (1U) +/*! PIO0_PIN1_SEC_MASK - Secure mask for pin P0_1 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN1_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN1_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN1_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN2_SEC_MASK_MASK (0x4U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN2_SEC_MASK_SHIFT (2U) +/*! PIO0_PIN2_SEC_MASK - Secure mask for pin P0_2 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN2_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN2_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN2_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN3_SEC_MASK_MASK (0x8U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN3_SEC_MASK_SHIFT (3U) +/*! PIO0_PIN3_SEC_MASK - Secure mask for pin P0_3 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN3_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN3_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN3_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN4_SEC_MASK_MASK (0x10U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN4_SEC_MASK_SHIFT (4U) +/*! PIO0_PIN4_SEC_MASK - Secure mask for pin P0_4 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN4_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN4_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN4_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN5_SEC_MASK_MASK (0x20U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN5_SEC_MASK_SHIFT (5U) +/*! PIO0_PIN5_SEC_MASK - Secure mask for pin P0_5 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN5_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN5_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN5_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN6_SEC_MASK_MASK (0x40U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN6_SEC_MASK_SHIFT (6U) +/*! PIO0_PIN6_SEC_MASK - Secure mask for pin P0_6 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN6_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN6_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN6_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN7_SEC_MASK_MASK (0x80U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN7_SEC_MASK_SHIFT (7U) +/*! PIO0_PIN7_SEC_MASK - Secure mask for pin P0_7 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN7_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN7_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN7_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN8_SEC_MASK_MASK (0x100U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN8_SEC_MASK_SHIFT (8U) +/*! PIO0_PIN8_SEC_MASK - Secure mask for pin P0_8 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN8_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN8_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN8_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN9_SEC_MASK_MASK (0x200U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN9_SEC_MASK_SHIFT (9U) +/*! PIO0_PIN9_SEC_MASK - Secure mask for pin P0_9 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN9_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN9_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN9_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN10_SEC_MASK_MASK (0x400U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN10_SEC_MASK_SHIFT (10U) +/*! PIO0_PIN10_SEC_MASK - Secure mask for pin P0_10 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN10_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN10_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN10_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN11_SEC_MASK_MASK (0x800U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN11_SEC_MASK_SHIFT (11U) +/*! PIO0_PIN11_SEC_MASK - Secure mask for pin P0_11 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN11_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN11_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN11_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN12_SEC_MASK_MASK (0x1000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN12_SEC_MASK_SHIFT (12U) +/*! PIO0_PIN12_SEC_MASK - Secure mask for pin P0_12 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN12_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN12_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN12_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN13_SEC_MASK_MASK (0x2000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN13_SEC_MASK_SHIFT (13U) +/*! PIO0_PIN13_SEC_MASK - Secure mask for pin P0_13 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN13_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN13_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN13_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN14_SEC_MASK_MASK (0x4000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN14_SEC_MASK_SHIFT (14U) +/*! PIO0_PIN14_SEC_MASK - Secure mask for pin P0_14 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN14_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN14_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN14_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN15_SEC_MASK_MASK (0x8000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN15_SEC_MASK_SHIFT (15U) +/*! PIO0_PIN15_SEC_MASK - Secure mask for pin P0_15 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN15_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN15_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN15_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN16_SEC_MASK_MASK (0x10000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN16_SEC_MASK_SHIFT (16U) +/*! PIO0_PIN16_SEC_MASK - Secure mask for pin P0_16 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN16_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN16_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN16_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN17_SEC_MASK_MASK (0x20000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN17_SEC_MASK_SHIFT (17U) +/*! PIO0_PIN17_SEC_MASK - Secure mask for pin P0_17 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN17_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN17_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN17_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN18_SEC_MASK_MASK (0x40000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN18_SEC_MASK_SHIFT (18U) +/*! PIO0_PIN18_SEC_MASK - Secure mask for pin P0_18 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN18_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN18_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN18_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN19_SEC_MASK_MASK (0x80000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN19_SEC_MASK_SHIFT (19U) +/*! PIO0_PIN19_SEC_MASK - Secure mask for pin P0_19 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN19_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN19_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN19_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN20_SEC_MASK_MASK (0x100000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN20_SEC_MASK_SHIFT (20U) +/*! PIO0_PIN20_SEC_MASK - Secure mask for pin P0_20 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN20_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN20_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN20_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN21_SEC_MASK_MASK (0x200000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN21_SEC_MASK_SHIFT (21U) +/*! PIO0_PIN21_SEC_MASK - Secure mask for pin P0_21 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN21_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN21_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN21_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN22_SEC_MASK_MASK (0x400000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN22_SEC_MASK_SHIFT (22U) +/*! PIO0_PIN22_SEC_MASK - Secure mask for pin P0_22 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN22_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN22_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN22_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN23_SEC_MASK_MASK (0x800000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN23_SEC_MASK_SHIFT (23U) +/*! PIO0_PIN23_SEC_MASK - Secure mask for pin P0_23 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN23_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN23_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN23_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN24_SEC_MASK_MASK (0x1000000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN24_SEC_MASK_SHIFT (24U) +/*! PIO0_PIN24_SEC_MASK - Secure mask for pin P0_24 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN24_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN24_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN24_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN25_SEC_MASK_MASK (0x2000000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN25_SEC_MASK_SHIFT (25U) +/*! PIO0_PIN25_SEC_MASK - Secure mask for pin P0_25 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN25_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN25_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN25_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN26_SEC_MASK_MASK (0x4000000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN26_SEC_MASK_SHIFT (26U) +/*! PIO0_PIN26_SEC_MASK - Secure mask for pin P0_26 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN26_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN26_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN26_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN27_SEC_MASK_MASK (0x8000000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN27_SEC_MASK_SHIFT (27U) +/*! PIO0_PIN27_SEC_MASK - Secure mask for pin P0_27 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN27_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN27_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN27_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN28_SEC_MASK_MASK (0x10000000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN28_SEC_MASK_SHIFT (28U) +/*! PIO0_PIN28_SEC_MASK - Secure mask for pin P0_28 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN28_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN28_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN28_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN29_SEC_MASK_MASK (0x20000000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN29_SEC_MASK_SHIFT (29U) +/*! PIO0_PIN29_SEC_MASK - Secure mask for pin P0_29 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN29_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN29_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN29_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN30_SEC_MASK_MASK (0x40000000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN30_SEC_MASK_SHIFT (30U) +/*! PIO0_PIN30_SEC_MASK - Secure mask for pin P0_30 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN30_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN30_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN30_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN31_SEC_MASK_MASK (0x80000000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN31_SEC_MASK_SHIFT (31U) +/*! PIO0_PIN31_SEC_MASK - Secure mask for pin P0_31 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN31_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN31_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN31_SEC_MASK_MASK) +/*! @} */ + +/*! @name SEC_GPIO_MASK1 - Secure GPIO mask for port 1 pins. */ +/*! @{ */ + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN0_SEC_MASK_MASK (0x1U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN0_SEC_MASK_SHIFT (0U) +/*! PIO1_PIN0_SEC_MASK - Secure mask for pin P1_0 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN0_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN0_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN0_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN1_SEC_MASK_MASK (0x2U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN1_SEC_MASK_SHIFT (1U) +/*! PIO1_PIN1_SEC_MASK - Secure mask for pin P1_1 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN1_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN1_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN1_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN2_SEC_MASK_MASK (0x4U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN2_SEC_MASK_SHIFT (2U) +/*! PIO1_PIN2_SEC_MASK - Secure mask for pin P1_2 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN2_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN2_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN2_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN3_SEC_MASK_MASK (0x8U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN3_SEC_MASK_SHIFT (3U) +/*! PIO1_PIN3_SEC_MASK - Secure mask for pin P1_3 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN3_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN3_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN3_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN4_SEC_MASK_MASK (0x10U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN4_SEC_MASK_SHIFT (4U) +/*! PIO1_PIN4_SEC_MASK - Secure mask for pin P1_4 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN4_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN4_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN4_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN5_SEC_MASK_MASK (0x20U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN5_SEC_MASK_SHIFT (5U) +/*! PIO1_PIN5_SEC_MASK - Secure mask for pin P1_5 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN5_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN5_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN5_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN6_SEC_MASK_MASK (0x40U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN6_SEC_MASK_SHIFT (6U) +/*! PIO1_PIN6_SEC_MASK - Secure mask for pin P1_6 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN6_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN6_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN6_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN7_SEC_MASK_MASK (0x80U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN7_SEC_MASK_SHIFT (7U) +/*! PIO1_PIN7_SEC_MASK - Secure mask for pin P1_7 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN7_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN7_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN7_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN8_SEC_MASK_MASK (0x100U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN8_SEC_MASK_SHIFT (8U) +/*! PIO1_PIN8_SEC_MASK - Secure mask for pin P1_8 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN8_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN8_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN8_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN9_SEC_MASK_MASK (0x200U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN9_SEC_MASK_SHIFT (9U) +/*! PIO1_PIN9_SEC_MASK - Secure mask for pin P1_9 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN9_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN9_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN9_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN10_SEC_MASK_MASK (0x400U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN10_SEC_MASK_SHIFT (10U) +/*! PIO1_PIN10_SEC_MASK - Secure mask for pin P1_10 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN10_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN10_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN10_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN11_SEC_MASK_MASK (0x800U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN11_SEC_MASK_SHIFT (11U) +/*! PIO1_PIN11_SEC_MASK - Secure mask for pin P1_11 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN11_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN11_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN11_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN12_SEC_MASK_MASK (0x1000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN12_SEC_MASK_SHIFT (12U) +/*! PIO1_PIN12_SEC_MASK - Secure mask for pin P1_12 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN12_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN12_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN12_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN13_SEC_MASK_MASK (0x2000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN13_SEC_MASK_SHIFT (13U) +/*! PIO1_PIN13_SEC_MASK - Secure mask for pin P1_13 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN13_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN13_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN13_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN14_SEC_MASK_MASK (0x4000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN14_SEC_MASK_SHIFT (14U) +/*! PIO1_PIN14_SEC_MASK - Secure mask for pin P1_14 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN14_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN14_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN14_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN15_SEC_MASK_MASK (0x8000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN15_SEC_MASK_SHIFT (15U) +/*! PIO1_PIN15_SEC_MASK - Secure mask for pin P1_15 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN15_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN15_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN15_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN16_SEC_MASK_MASK (0x10000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN16_SEC_MASK_SHIFT (16U) +/*! PIO1_PIN16_SEC_MASK - Secure mask for pin P1_16 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN16_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN16_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN16_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN17_SEC_MASK_MASK (0x20000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN17_SEC_MASK_SHIFT (17U) +/*! PIO1_PIN17_SEC_MASK - Secure mask for pin P1_17 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN17_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN17_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN17_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN18_SEC_MASK_MASK (0x40000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN18_SEC_MASK_SHIFT (18U) +/*! PIO1_PIN18_SEC_MASK - Secure mask for pin P1_18 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN18_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN18_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN18_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN19_SEC_MASK_MASK (0x80000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN19_SEC_MASK_SHIFT (19U) +/*! PIO1_PIN19_SEC_MASK - Secure mask for pin P1_19 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN19_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN19_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN19_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN20_SEC_MASK_MASK (0x100000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN20_SEC_MASK_SHIFT (20U) +/*! PIO1_PIN20_SEC_MASK - Secure mask for pin P1_20 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN20_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN20_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN20_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN21_SEC_MASK_MASK (0x200000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN21_SEC_MASK_SHIFT (21U) +/*! PIO1_PIN21_SEC_MASK - Secure mask for pin P1_21 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN21_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN21_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN21_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN22_SEC_MASK_MASK (0x400000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN22_SEC_MASK_SHIFT (22U) +/*! PIO1_PIN22_SEC_MASK - Secure mask for pin P1_22 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN22_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN22_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN22_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN23_SEC_MASK_MASK (0x800000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN23_SEC_MASK_SHIFT (23U) +/*! PIO1_PIN23_SEC_MASK - Secure mask for pin P1_23 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN23_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN23_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN23_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN24_SEC_MASK_MASK (0x1000000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN24_SEC_MASK_SHIFT (24U) +/*! PIO1_PIN24_SEC_MASK - Secure mask for pin P1_24 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN24_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN24_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN24_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN25_SEC_MASK_MASK (0x2000000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN25_SEC_MASK_SHIFT (25U) +/*! PIO1_PIN25_SEC_MASK - Secure mask for pin P1_25 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN25_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN25_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN25_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN26_SEC_MASK_MASK (0x4000000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN26_SEC_MASK_SHIFT (26U) +/*! PIO1_PIN26_SEC_MASK - Secure mask for pin P1_26 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN26_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN26_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN26_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN27_SEC_MASK_MASK (0x8000000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN27_SEC_MASK_SHIFT (27U) +/*! PIO1_PIN27_SEC_MASK - Secure mask for pin P1_27 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN27_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN27_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN27_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN28_SEC_MASK_MASK (0x10000000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN28_SEC_MASK_SHIFT (28U) +/*! PIO1_PIN28_SEC_MASK - Secure mask for pin P1_28 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN28_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN28_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN28_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN29_SEC_MASK_MASK (0x20000000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN29_SEC_MASK_SHIFT (29U) +/*! PIO1_PIN29_SEC_MASK - Secure mask for pin P1_29 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN29_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN29_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN29_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN30_SEC_MASK_MASK (0x40000000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN30_SEC_MASK_SHIFT (30U) +/*! PIO1_PIN30_SEC_MASK - Secure mask for pin P1_30 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN30_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN30_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN30_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN31_SEC_MASK_MASK (0x80000000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN31_SEC_MASK_SHIFT (31U) +/*! PIO1_PIN31_SEC_MASK - Secure mask for pin P1_31 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN31_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN31_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN31_SEC_MASK_MASK) +/*! @} */ + +/*! @name SEC_MASK_LOCK - Security General Purpose register access control. */ +/*! @{ */ + +#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK0_LOCK_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK0_LOCK_SHIFT (0U) +/*! SEC_GPIO_MASK0_LOCK - SEC_GPIO_MASK0 register write-lock. + * 0b10..Writable. + * 0b01..Restricted mode. + */ +#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK0_LOCK_SHIFT)) & AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK0_LOCK_MASK) + +#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK1_LOCK_MASK (0xCU) +#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK1_LOCK_SHIFT (2U) +/*! SEC_GPIO_MASK1_LOCK - SEC_GPIO_MASK1 register write-lock. + * 0b10..Writable. + * 0b01..Restricted mode. + */ +#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK1_LOCK_SHIFT)) & AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK1_LOCK_MASK) +/*! @} */ + +/*! @name MASTER_SEC_LEVEL - master secure level register */ +/*! @{ */ + +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSD_MASK (0x300U) +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSD_SHIFT (8U) +/*! USBFSD - USB Full Speed Device. + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSD(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSD_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSD_MASK) + +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA0_MASK (0xC00U) +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA0_SHIFT (10U) +/*! SDMA0 - System DMA 0. + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA0_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA0_MASK) + +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_HASH_MASK (0x300000U) +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_HASH_SHIFT (20U) +/*! HASH - Hash. + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_HASH(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_HASH_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_HASH_MASK) + +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSH_MASK (0xC00000U) +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSH_SHIFT (22U) +/*! USBFSH - USB Full speed Host. + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSH(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSH_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSH_MASK) + +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA1_MASK (0x3000000U) +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA1_SHIFT (24U) +/*! SDMA1 - System DMA 1 security level. + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA1_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA1_MASK) + +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CANFD_MASK (0xC000000U) +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CANFD_SHIFT (26U) +/*! CANFD - CAN FD. + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CANFD(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CANFD_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CANFD_MASK) + +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK_MASK (0xC0000000U) +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK_SHIFT (30U) +/*! MASTER_SEC_LEVEL_LOCK - MASTER_SEC_LEVEL write-lock. + * 0b10..Writable. + * 0b01..Restricted mode. + */ +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK_MASK) +/*! @} */ + +/*! @name MASTER_SEC_ANTI_POL_REG - master secure level anti-pole register */ +/*! @{ */ + +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSD_MASK (0x300U) +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSD_SHIFT (8U) +/*! USBFSD - USB Full Speed Device. Must be equal to NOT(MASTER_SEC_LEVEL.USBFSD) + * 0b11..Non-secure and Non-priviledge user access allowed. + * 0b10..Non-secure and Privilege access allowed. + * 0b01..Secure and Non-priviledge user access allowed. + * 0b00..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSD(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSD_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSD_MASK) + +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA0_MASK (0xC00U) +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA0_SHIFT (10U) +/*! SDMA0 - System DMA 0. Must be equal to NOT(MASTER_SEC_LEVEL.SDMA0) + * 0b11..Non-secure and Non-priviledge user access allowed. + * 0b10..Non-secure and Privilege access allowed. + * 0b01..Secure and Non-priviledge user access allowed. + * 0b00..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA0_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA0_MASK) + +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_HASH_MASK (0x300000U) +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_HASH_SHIFT (20U) +/*! HASH - Hash. Must be equal to NOT(MASTER_SEC_LEVEL.HASH) + * 0b11..Non-secure and Non-priviledge user access allowed. + * 0b10..Non-secure and Privilege access allowed. + * 0b01..Secure and Non-priviledge user access allowed. + * 0b00..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_HASH(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_HASH_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_HASH_MASK) + +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSH_MASK (0xC00000U) +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSH_SHIFT (22U) +/*! USBFSH - USB Full speed Host. Must be equal to NOT(MASTER_SEC_LEVEL.USBFSH) + * 0b11..Non-secure and Non-priviledge user access allowed. + * 0b10..Non-secure and Privilege access allowed. + * 0b01..Secure and Non-priviledge user access allowed. + * 0b00..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSH(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSH_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSH_MASK) + +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA1_MASK (0x3000000U) +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA1_SHIFT (24U) +/*! SDMA1 - System DMA 1 security level. Must be equal to NOT(MASTER_SEC_LEVEL.SDMA1) + * 0b11..Non-secure and Non-priviledge user access allowed. + * 0b10..Non-secure and Privilege access allowed. + * 0b01..Secure and Non-priviledge user access allowed. + * 0b00..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA1_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA1_MASK) + +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CANFD_MASK (0xC000000U) +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CANFD_SHIFT (26U) +/*! CANFD - CAN FD. Must be equal to NOT(MASTER_SEC_LEVEL.CANFD) + * 0b11..Non-secure and Non-priviledge user access allowed. + * 0b10..Non-secure and Privilege access allowed. + * 0b01..Secure and Non-priviledge user access allowed. + * 0b00..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CANFD(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CANFD_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CANFD_MASK) + +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK_MASK (0xC0000000U) +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK_SHIFT (30U) +/*! MASTER_SEC_LEVEL_ANTIPOL_LOCK - MASTER_SEC_ANTI_POL_REG register write-lock. + * 0b10..Writable. + * 0b01..Restricted mode. + */ +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK_MASK) +/*! @} */ + +/*! @name CPU0_LOCK_REG - Miscalleneous control signals for in Cortex M33 (CPU0) */ +/*! @{ */ + +#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_VTOR_MASK (0x3U) +#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_VTOR_SHIFT (0U) +/*! LOCK_NS_VTOR - Cortex M33 (CPU0) VTOR_NS register write-lock. + * 0b10..Writable. + * 0b01..Restricted mode. + */ +#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_VTOR(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_VTOR_SHIFT)) & AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_VTOR_MASK) + +#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_MPU_MASK (0xCU) +#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_MPU_SHIFT (2U) +/*! LOCK_NS_MPU - Cortex M33 (CPU0) non-secure MPU register write-lock. + * 0b10..Writable. + * 0b01..Restricted mode. + */ +#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_MPU(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_MPU_SHIFT)) & AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_MPU_MASK) + +#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_VTAIRCR_MASK (0x30U) +#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_VTAIRCR_SHIFT (4U) +/*! LOCK_S_VTAIRCR - Cortex M33 (CPU0) VTOR_S, AIRCR.PRIS, IRCR.BFHFNMINS registers write-lock. + * 0b10..Writable. + * 0b01..Restricted mode. + */ +#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_VTAIRCR(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_VTAIRCR_SHIFT)) & AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_VTAIRCR_MASK) + +#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_MPU_MASK (0xC0U) +#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_MPU_SHIFT (6U) +/*! LOCK_S_MPU - Cortex M33 (CPU0) Secure MPU registers write-lock. + * 0b10..Writable. + * 0b01..Restricted mode. + */ +#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_MPU(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_MPU_SHIFT)) & AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_MPU_MASK) + +#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_SAU_MASK (0x300U) +#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_SAU_SHIFT (8U) +/*! LOCK_SAU - Cortex M33 (CPU0) SAU registers write-lock. + * 0b10..Writable. + * 0b01..Restricted mode. + */ +#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_SAU(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_SAU_SHIFT)) & AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_SAU_MASK) + +#define AHB_SECURE_CTRL_CPU0_LOCK_REG_CPU0_LOCK_REG_LOCK_MASK (0xC0000000U) +#define AHB_SECURE_CTRL_CPU0_LOCK_REG_CPU0_LOCK_REG_LOCK_SHIFT (30U) +/*! CPU0_LOCK_REG_LOCK - CPU0_LOCK_REG write-lock. + * 0b10..Writable. + * 0b01..Restricted mode. + */ +#define AHB_SECURE_CTRL_CPU0_LOCK_REG_CPU0_LOCK_REG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU0_LOCK_REG_CPU0_LOCK_REG_LOCK_SHIFT)) & AHB_SECURE_CTRL_CPU0_LOCK_REG_CPU0_LOCK_REG_LOCK_MASK) +/*! @} */ + +/*! @name MISC_CTRL_DP_REG - secure control duplicate register */ +/*! @{ */ + +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_WRITE_LOCK_MASK (0x3U) +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_WRITE_LOCK_SHIFT (0U) +/*! WRITE_LOCK - Write lock. + * 0b10..Secure control registers can be written. + * 0b01..Restricted mode. + */ +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_WRITE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_WRITE_LOCK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_WRITE_LOCK_MASK) + +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_MASK (0xCU) +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_SHIFT (2U) +/*! ENABLE_SECURE_CHECKING - Enable secure check for AHB matrix. + * 0b10..Disable check. + * 0b01..Restricted mode. + */ +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_MASK) + +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_MASK (0x30U) +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_SHIFT (4U) +/*! ENABLE_S_PRIV_CHECK - Enable secure privilege check for AHB matrix. + * 0b10..Disable check. + * 0b01..Restricted mode. + */ +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_MASK) + +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_MASK (0xC0U) +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_SHIFT (6U) +/*! ENABLE_NS_PRIV_CHECK - Enable non-secure privilege check for AHB matrix. + * 0b10..Disable check. + * 0b01..Restricted mode. + */ +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_MASK) + +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_MASK (0x300U) +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_SHIFT (8U) +/*! DISABLE_VIOLATION_ABORT - Disable secure violation abort. + * 0b10..Enable abort fort secure checker. + * 0b01..Disable abort fort secure checker. + */ +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_MASK) + +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_MASK (0xC00U) +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_SHIFT (10U) +/*! DISABLE_SIMPLE_MASTER_STRICT_MODE - Disable simple master strict mode. + * 0b10..Simple master in strict mode. + * 0b01..Simple master in tier mode. + */ +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_MASK) + +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SMART_MASTER_STRICT_MODE_MASK (0x3000U) +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SMART_MASTER_STRICT_MODE_SHIFT (12U) +/*! DISABLE_SMART_MASTER_STRICT_MODE - Disable smart master strict mode. + * 0b10..Smart master in strict mode. + * 0b01..Smart master in tier mode. + */ +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SMART_MASTER_STRICT_MODE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SMART_MASTER_STRICT_MODE_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SMART_MASTER_STRICT_MODE_MASK) + +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_IDAU_ALL_NS_MASK (0xC000U) +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_IDAU_ALL_NS_SHIFT (14U) +/*! IDAU_ALL_NS - Disable IDAU. + * 0b10..IDAU is enabled. + * 0b01..IDAU is disable. + */ +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_IDAU_ALL_NS(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_IDAU_ALL_NS_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_IDAU_ALL_NS_MASK) +/*! @} */ + +/*! @name MISC_CTRL_REG - secure control register */ +/*! @{ */ + +#define AHB_SECURE_CTRL_MISC_CTRL_REG_WRITE_LOCK_MASK (0x3U) +#define AHB_SECURE_CTRL_MISC_CTRL_REG_WRITE_LOCK_SHIFT (0U) +/*! WRITE_LOCK - Write lock. + * 0b10..Secure control registers can be written. + * 0b01..Restricted mode. + */ +#define AHB_SECURE_CTRL_MISC_CTRL_REG_WRITE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_WRITE_LOCK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_WRITE_LOCK_MASK) + +#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_MASK (0xCU) +#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_SHIFT (2U) +/*! ENABLE_SECURE_CHECKING - Enable secure check for AHB matrix. + * 0b10..Disable check. + * 0b01..Enabled (restricted mode) + */ +#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_MASK) + +#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_MASK (0x30U) +#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_SHIFT (4U) +/*! ENABLE_S_PRIV_CHECK - Enable secure privilege check for AHB matrix. + * 0b10..Disable check. + * 0b01..Enabled (restricted mode) + */ +#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_MASK) + +#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_MASK (0xC0U) +#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_SHIFT (6U) +/*! ENABLE_NS_PRIV_CHECK - Enable non-secure privilege check for AHB matrix. + * 0b10..Disable check. + * 0b01..Enabled (restricted mode) + */ +#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_MASK) + +#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_MASK (0x300U) +#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_SHIFT (8U) +/*! DISABLE_VIOLATION_ABORT - Disable secure violation abort. + * 0b10..Enable abort fort secure checker. + * 0b01..Disable abort fort secure checker. + */ +#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_MASK) + +#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_MASK (0xC00U) +#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_SHIFT (10U) +/*! DISABLE_SIMPLE_MASTER_STRICT_MODE - Disable simple master strict mode. + * 0b10..Simple master in strict mode. + * 0b01..Simple master in tier mode. + */ +#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_MASK) + +#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SMART_MASTER_STRICT_MODE_MASK (0x3000U) +#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SMART_MASTER_STRICT_MODE_SHIFT (12U) +/*! DISABLE_SMART_MASTER_STRICT_MODE - Disable smart master strict mode. + * 0b10..Smart master in strict mode. + * 0b01..Smart master in tier mode. + */ +#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SMART_MASTER_STRICT_MODE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SMART_MASTER_STRICT_MODE_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SMART_MASTER_STRICT_MODE_MASK) + +#define AHB_SECURE_CTRL_MISC_CTRL_REG_IDAU_ALL_NS_MASK (0xC000U) +#define AHB_SECURE_CTRL_MISC_CTRL_REG_IDAU_ALL_NS_SHIFT (14U) +/*! IDAU_ALL_NS - Disable IDAU. + * 0b10..IDAU is enabled. + * 0b01..IDAU is disable. + */ +#define AHB_SECURE_CTRL_MISC_CTRL_REG_IDAU_ALL_NS(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_IDAU_ALL_NS_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_IDAU_ALL_NS_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group AHB_SECURE_CTRL_Register_Masks */ + + +/* AHB_SECURE_CTRL - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral AHB_SECURE_CTRL base address */ + #define AHB_SECURE_CTRL_BASE (0x500AC000u) + /** Peripheral AHB_SECURE_CTRL base address */ + #define AHB_SECURE_CTRL_BASE_NS (0x400AC000u) + /** Peripheral AHB_SECURE_CTRL base pointer */ + #define AHB_SECURE_CTRL ((AHB_SECURE_CTRL_Type *)AHB_SECURE_CTRL_BASE) + /** Peripheral AHB_SECURE_CTRL base pointer */ + #define AHB_SECURE_CTRL_NS ((AHB_SECURE_CTRL_Type *)AHB_SECURE_CTRL_BASE_NS) + /** Array initializer of AHB_SECURE_CTRL peripheral base addresses */ + #define AHB_SECURE_CTRL_BASE_ADDRS { AHB_SECURE_CTRL_BASE } + /** Array initializer of AHB_SECURE_CTRL peripheral base pointers */ + #define AHB_SECURE_CTRL_BASE_PTRS { AHB_SECURE_CTRL } + /** Array initializer of AHB_SECURE_CTRL peripheral base addresses */ + #define AHB_SECURE_CTRL_BASE_ADDRS_NS { AHB_SECURE_CTRL_BASE_NS } + /** Array initializer of AHB_SECURE_CTRL peripheral base pointers */ + #define AHB_SECURE_CTRL_BASE_PTRS_NS { AHB_SECURE_CTRL_NS } +#else + /** Peripheral AHB_SECURE_CTRL base address */ + #define AHB_SECURE_CTRL_BASE (0x400AC000u) + /** Peripheral AHB_SECURE_CTRL base pointer */ + #define AHB_SECURE_CTRL ((AHB_SECURE_CTRL_Type *)AHB_SECURE_CTRL_BASE) + /** Array initializer of AHB_SECURE_CTRL peripheral base addresses */ + #define AHB_SECURE_CTRL_BASE_ADDRS { AHB_SECURE_CTRL_BASE } + /** Array initializer of AHB_SECURE_CTRL peripheral base pointers */ + #define AHB_SECURE_CTRL_BASE_PTRS { AHB_SECURE_CTRL } +#endif + +/*! + * @} + */ /* end of group AHB_SECURE_CTRL_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- ANACTRL Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ANACTRL_Peripheral_Access_Layer ANACTRL Peripheral Access Layer + * @{ + */ + +/** ANACTRL - Register Layout Typedef */ +typedef struct { + __IO uint32_t ANALOG_CTRL_CFG; /**< Various Analog blocks configuration (like FRO 192MHz trimmings source ...), offset: 0x0 */ + __I uint32_t ANALOG_CTRL_STATUS; /**< Analog Macroblock Identity registers, Flash Status registers, offset: 0x4 */ + uint8_t RESERVED_0[4]; + __IO uint32_t FREQ_ME_CTRL; /**< Frequency Measure function control register, offset: 0xC */ + __IO uint32_t FRO192M_CTRL; /**< 192MHz Free Running OScillator (FRO) Control register, offset: 0x10 */ + __I uint32_t FRO192M_STATUS; /**< 192MHz Free Running OScillator (FRO) Status register, offset: 0x14 */ + __IO uint32_t ADC_CTRL; /**< General Purpose ADC VBAT Divider branch control, offset: 0x18 */ + uint8_t RESERVED_1[4]; + __IO uint32_t XO32M_CTRL; /**< High speed Crystal Oscillator Control register, offset: 0x20 */ + __I uint32_t XO32M_STATUS; /**< High speed Crystal Oscillator Status register, offset: 0x24 */ + uint8_t RESERVED_2[8]; + __IO uint32_t BOD_DCDC_INT_CTRL; /**< Brown Out Detectors (BoDs) & DCDC interrupts generation control register, offset: 0x30 */ + __I uint32_t BOD_DCDC_INT_STATUS; /**< BoDs & DCDC interrupts status register, offset: 0x34 */ + uint8_t RESERVED_3[8]; + __IO uint32_t RINGO0_CTRL; /**< First Ring Oscillator module control register., offset: 0x40 */ + __IO uint32_t RINGO1_CTRL; /**< Second Ring Oscillator module control register., offset: 0x44 */ + __IO uint32_t RINGO2_CTRL; /**< Third Ring Oscillator module control register., offset: 0x48 */ + uint8_t RESERVED_4[100]; + __IO uint32_t LDO_XO32M; /**< High Speed Crystal Oscillator (12 MHz - 32 MHz) Voltage Source Supply Control register, offset: 0xB0 */ + __IO uint32_t AUX_BIAS; /**< AUX_BIAS, offset: 0xB4 */ + uint8_t RESERVED_5[64]; + __IO uint32_t DUMMY_CTRL; /**< Dummy Control bus to analog modules, offset: 0xF8 */ + uint8_t RESERVED_6[4]; + __IO uint32_t USBHS_PHY_CTRL; /**< USB High Speed Phy Control, offset: 0x100 */ + __IO uint32_t USBHS_PHY_TRIM; /**< USB High Speed Phy Trim values, offset: 0x104 */ +} ANACTRL_Type; + +/* ---------------------------------------------------------------------------- + -- ANACTRL Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ANACTRL_Register_Masks ANACTRL Register Masks + * @{ + */ + +/*! @name ANALOG_CTRL_CFG - Various Analog blocks configuration (like FRO 192MHz trimmings source ...) */ +/*! @{ */ + +#define ANACTRL_ANALOG_CTRL_CFG_FRO192M_TRIM_SRC_MASK (0x1U) +#define ANACTRL_ANALOG_CTRL_CFG_FRO192M_TRIM_SRC_SHIFT (0U) +/*! FRO192M_TRIM_SRC - FRO192M trimming and 'Enable' source. + * 0b0..FRO192M trimming and 'Enable' comes from eFUSE. + * 0b1..FRO192M trimming and 'Enable' comes from FRO192M_CTRL registers. + */ +#define ANACTRL_ANALOG_CTRL_CFG_FRO192M_TRIM_SRC(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_ANALOG_CTRL_CFG_FRO192M_TRIM_SRC_SHIFT)) & ANACTRL_ANALOG_CTRL_CFG_FRO192M_TRIM_SRC_MASK) +/*! @} */ + +/*! @name ANALOG_CTRL_STATUS - Analog Macroblock Identity registers, Flash Status registers */ +/*! @{ */ + +#define ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN_MASK (0x1000U) +#define ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN_SHIFT (12U) +/*! FLASH_PWRDWN - Flash Power Down status. + * 0b0..Flash is not in power down mode. + * 0b1..Flash is in power down mode. + */ +#define ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN_SHIFT)) & ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN_MASK) + +#define ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR_MASK (0x2000U) +#define ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR_SHIFT (13U) +/*! FLASH_INIT_ERROR - Flash initialization error status. + * 0b0..No error. + * 0b1..At least one error occured during flash initialization.. + */ +#define ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR_SHIFT)) & ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR_MASK) +/*! @} */ + +/*! @name FREQ_ME_CTRL - Frequency Measure function control register */ +/*! @{ */ + +#define ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE_MASK (0x7FFFFFFFU) +#define ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE_SHIFT (0U) +/*! CAPVAL_SCALE - Frequency measure result /Frequency measur scale + */ +#define ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE_SHIFT)) & ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE_MASK) + +#define ANACTRL_FREQ_ME_CTRL_PROG_MASK (0x80000000U) +#define ANACTRL_FREQ_ME_CTRL_PROG_SHIFT (31U) +/*! PROG - Set this bit to one to initiate a frequency measurement cycle. Hardware clears this bit + * when the measurement cycle has completed and there is valid capture data in the CAPVAL field + * (bits 30:0). + */ +#define ANACTRL_FREQ_ME_CTRL_PROG(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FREQ_ME_CTRL_PROG_SHIFT)) & ANACTRL_FREQ_ME_CTRL_PROG_MASK) +/*! @} */ + +/*! @name FRO192M_CTRL - 192MHz Free Running OScillator (FRO) Control register */ +/*! @{ */ + +#define ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_MASK (0x4000U) +#define ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_SHIFT (14U) +/*! ENA_12MHZCLK - 12 MHz clock control. + * 0b0..12 MHz clock is disabled. + * 0b1..12 MHz clock is enabled. + */ +#define ANACTRL_FRO192M_CTRL_ENA_12MHZCLK(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_SHIFT)) & ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_MASK) + +#define ANACTRL_FRO192M_CTRL_DAC_TRIM_MASK (0xFF0000U) +#define ANACTRL_FRO192M_CTRL_DAC_TRIM_SHIFT (16U) +/*! DAC_TRIM - Frequency trim. + */ +#define ANACTRL_FRO192M_CTRL_DAC_TRIM(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_DAC_TRIM_SHIFT)) & ANACTRL_FRO192M_CTRL_DAC_TRIM_MASK) + +#define ANACTRL_FRO192M_CTRL_USBCLKADJ_MASK (0x1000000U) +#define ANACTRL_FRO192M_CTRL_USBCLKADJ_SHIFT (24U) +/*! USBCLKADJ - If this bit is set and the USB peripheral is enabled into full speed device mode, + * the USB block will provide FRO clock adjustments to lock it to the host clock using the SOF + * packets. + */ +#define ANACTRL_FRO192M_CTRL_USBCLKADJ(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_USBCLKADJ_SHIFT)) & ANACTRL_FRO192M_CTRL_USBCLKADJ_MASK) + +#define ANACTRL_FRO192M_CTRL_USBMODCHG_MASK (0x2000000U) +#define ANACTRL_FRO192M_CTRL_USBMODCHG_SHIFT (25U) +/*! USBMODCHG - If it reads as 1 when reading the DAC_TRIM field and USBCLKADJ=1, it should be re-read until it is 0. + */ +#define ANACTRL_FRO192M_CTRL_USBMODCHG(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_USBMODCHG_SHIFT)) & ANACTRL_FRO192M_CTRL_USBMODCHG_MASK) + +#define ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK (0x40000000U) +#define ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_SHIFT (30U) +/*! ENA_96MHZCLK - 96 MHz clock control. + * 0b0..96 MHz clock is disabled. + * 0b1..96 MHz clock is enabled. + */ +#define ANACTRL_FRO192M_CTRL_ENA_96MHZCLK(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_SHIFT)) & ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK) + +#define ANACTRL_FRO192M_CTRL_WRTRIM_MASK (0x80000000U) +#define ANACTRL_FRO192M_CTRL_WRTRIM_SHIFT (31U) +/*! WRTRIM - This must be written to 1 to modify the BIAS_TRIM and TEMP_TRIM fields. + */ +#define ANACTRL_FRO192M_CTRL_WRTRIM(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_WRTRIM_SHIFT)) & ANACTRL_FRO192M_CTRL_WRTRIM_MASK) +/*! @} */ + +/*! @name FRO192M_STATUS - 192MHz Free Running OScillator (FRO) Status register */ +/*! @{ */ + +#define ANACTRL_FRO192M_STATUS_CLK_VALID_MASK (0x1U) +#define ANACTRL_FRO192M_STATUS_CLK_VALID_SHIFT (0U) +/*! CLK_VALID - Output clock valid signal. Indicates that CCO clock has settled. + * 0b0..No output clock present (None of 12 MHz, 48 MHz or 96 MHz clock is available). + * 0b1..Clock is present (12 MHz, 48 MHz or 96 MHz can be output if they are enable respectively by + * FRO192M_CTRL.ENA_12MHZCLK/ENA_48MHZCLK/ENA_96MHZCLK). + */ +#define ANACTRL_FRO192M_STATUS_CLK_VALID(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_STATUS_CLK_VALID_SHIFT)) & ANACTRL_FRO192M_STATUS_CLK_VALID_MASK) + +#define ANACTRL_FRO192M_STATUS_ATB_VCTRL_MASK (0x2U) +#define ANACTRL_FRO192M_STATUS_ATB_VCTRL_SHIFT (1U) +/*! ATB_VCTRL - CCO threshold voltage detector output (signal vcco_ok). Once the CCO voltage crosses + * the threshold voltage of a SLVT transistor, this output signal will go high. It is also + * possible to observe the clk_valid signal. + */ +#define ANACTRL_FRO192M_STATUS_ATB_VCTRL(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_STATUS_ATB_VCTRL_SHIFT)) & ANACTRL_FRO192M_STATUS_ATB_VCTRL_MASK) +/*! @} */ + +/*! @name ADC_CTRL - General Purpose ADC VBAT Divider branch control */ +/*! @{ */ + +#define ANACTRL_ADC_CTRL_VBATDIVENABLE_MASK (0x1U) +#define ANACTRL_ADC_CTRL_VBATDIVENABLE_SHIFT (0U) +/*! VBATDIVENABLE - Switch On/Off VBAT divider branch. + * 0b0..VBAT divider branch is disabled. + * 0b1..VBAT divider branch is enabled. + */ +#define ANACTRL_ADC_CTRL_VBATDIVENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_ADC_CTRL_VBATDIVENABLE_SHIFT)) & ANACTRL_ADC_CTRL_VBATDIVENABLE_MASK) +/*! @} */ + +/*! @name XO32M_CTRL - High speed Crystal Oscillator Control register */ +/*! @{ */ + +#define ANACTRL_XO32M_CTRL_SLAVE_MASK (0x10U) +#define ANACTRL_XO32M_CTRL_SLAVE_SHIFT (4U) +/*! SLAVE - Xo in slave mode. + */ +#define ANACTRL_XO32M_CTRL_SLAVE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_SLAVE_SHIFT)) & ANACTRL_XO32M_CTRL_SLAVE_MASK) + +#define ANACTRL_XO32M_CTRL_OSC_CAP_IN_MASK (0x7F00U) +#define ANACTRL_XO32M_CTRL_OSC_CAP_IN_SHIFT (8U) +/*! OSC_CAP_IN - Tune capa banks of High speed Crystal Oscillator input pin + */ +#define ANACTRL_XO32M_CTRL_OSC_CAP_IN(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_OSC_CAP_IN_SHIFT)) & ANACTRL_XO32M_CTRL_OSC_CAP_IN_MASK) + +#define ANACTRL_XO32M_CTRL_OSC_CAP_OUT_MASK (0x3F8000U) +#define ANACTRL_XO32M_CTRL_OSC_CAP_OUT_SHIFT (15U) +/*! OSC_CAP_OUT - Tune capa banks of High speed Crystal Oscillator output pin + */ +#define ANACTRL_XO32M_CTRL_OSC_CAP_OUT(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_OSC_CAP_OUT_SHIFT)) & ANACTRL_XO32M_CTRL_OSC_CAP_OUT_MASK) + +#define ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_MASK (0x400000U) +#define ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_SHIFT (22U) +/*! ACBUF_PASS_ENABLE - Bypass enable of XO AC buffer enable in pll and top level. + * 0b0..XO AC buffer bypass is disabled. + * 0b1..XO AC buffer bypass is enabled. + */ +#define ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_SHIFT)) & ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_MASK) + +#define ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_MASK (0x800000U) +#define ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_SHIFT (23U) +/*! ENABLE_PLL_USB_OUT - Enable High speed Crystal oscillator output to USB HS PLL. + * 0b0..High speed Crystal oscillator output to USB HS PLL is disabled. + * 0b1..High speed Crystal oscillator output to USB HS PLL is enabled. + */ +#define ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_SHIFT)) & ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_MASK) + +#define ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK (0x1000000U) +#define ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_SHIFT (24U) +/*! ENABLE_SYSTEM_CLK_OUT - Enable High speed Crystal oscillator output to CPU system. + * 0b0..High speed Crystal oscillator output to CPU system is disabled. + * 0b1..High speed Crystal oscillator output to CPU system is enabled. + */ +#define ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_SHIFT)) & ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK) +/*! @} */ + +/*! @name XO32M_STATUS - High speed Crystal Oscillator Status register */ +/*! @{ */ + +#define ANACTRL_XO32M_STATUS_XO_READY_MASK (0x1U) +#define ANACTRL_XO32M_STATUS_XO_READY_SHIFT (0U) +/*! XO_READY - Indicates XO out frequency statibilty. + * 0b0..XO output frequency is not yet stable. + * 0b1..XO output frequency is stable. + */ +#define ANACTRL_XO32M_STATUS_XO_READY(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_STATUS_XO_READY_SHIFT)) & ANACTRL_XO32M_STATUS_XO_READY_MASK) +/*! @} */ + +/*! @name BOD_DCDC_INT_CTRL - Brown Out Detectors (BoDs) & DCDC interrupts generation control register */ +/*! @{ */ + +#define ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_ENABLE_MASK (0x1U) +#define ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_ENABLE_SHIFT (0U) +/*! BODVBAT_INT_ENABLE - BOD VBAT interrupt control. + * 0b0..BOD VBAT interrupt is disabled. + * 0b1..BOD VBAT interrupt is enabled. + */ +#define ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_ENABLE_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_ENABLE_MASK) + +#define ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_CLEAR_MASK (0x2U) +#define ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_CLEAR_SHIFT (1U) +/*! BODVBAT_INT_CLEAR - BOD VBAT interrupt clear.1: Clear the interrupt. Self-cleared bit. + */ +#define ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_CLEAR_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_CLEAR_MASK) + +#define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE_MASK (0x4U) +#define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE_SHIFT (2U) +/*! BODCORE_INT_ENABLE - BOD CORE interrupt control. + * 0b0..BOD CORE interrupt is disabled. + * 0b1..BOD CORE interrupt is enabled. + */ +#define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE_MASK) + +#define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_CLEAR_MASK (0x8U) +#define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_CLEAR_SHIFT (3U) +/*! BODCORE_INT_CLEAR - BOD CORE interrupt clear.1: Clear the interrupt. Self-cleared bit. + */ +#define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_CLEAR_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_CLEAR_MASK) + +#define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE_MASK (0x10U) +#define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE_SHIFT (4U) +/*! DCDC_INT_ENABLE - DCDC interrupt control. + * 0b0..DCDC interrupt is disabled. + * 0b1..DCDC interrupt is enabled. + */ +#define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE_MASK) + +#define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_CLEAR_MASK (0x20U) +#define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_CLEAR_SHIFT (5U) +/*! DCDC_INT_CLEAR - DCDC interrupt clear.1: Clear the interrupt. Self-cleared bit. + */ +#define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_CLEAR_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_CLEAR_MASK) +/*! @} */ + +/*! @name BOD_DCDC_INT_STATUS - BoDs & DCDC interrupts status register */ +/*! @{ */ + +#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_STATUS_MASK (0x1U) +#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_STATUS_SHIFT (0U) +/*! BODVBAT_STATUS - BOD VBAT Interrupt status before Interrupt Enable. + * 0b0..No interrupt pending.. + * 0b1..Interrupt pending.. + */ +#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_STATUS_MASK) + +#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_INT_STATUS_MASK (0x2U) +#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_INT_STATUS_SHIFT (1U) +/*! BODVBAT_INT_STATUS - BOD VBAT Interrupt status after Interrupt Enable. + * 0b0..No interrupt pending.. + * 0b1..Interrupt pending.. + */ +#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_INT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_INT_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_INT_STATUS_MASK) + +#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_VAL_MASK (0x4U) +#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_VAL_SHIFT (2U) +/*! BODVBAT_VAL - Current value of BOD VBAT power status output. + * 0b0..VBAT voltage level is below the threshold. + * 0b1..VBAT voltage level is above the threshold. + */ +#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_VAL(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_VAL_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_VAL_MASK) + +#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS_MASK (0x8U) +#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS_SHIFT (3U) +/*! BODCORE_STATUS - BOD CORE Interrupt status before Interrupt Enable. + * 0b0..No interrupt pending.. + * 0b1..Interrupt pending.. + */ +#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS_MASK) + +#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS_MASK (0x10U) +#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS_SHIFT (4U) +/*! BODCORE_INT_STATUS - BOD CORE Interrupt status after Interrupt Enable. + * 0b0..No interrupt pending.. + * 0b1..Interrupt pending.. + */ +#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS_MASK) + +#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL_MASK (0x20U) +#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL_SHIFT (5U) +/*! BODCORE_VAL - Current value of BOD CORE power status output. + * 0b0..CORE voltage level is below the threshold. + * 0b1..CORE voltage level is above the threshold. + */ +#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL_MASK) + +#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS_MASK (0x40U) +#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS_SHIFT (6U) +/*! DCDC_STATUS - DCDC Interrupt status before Interrupt Enable. + * 0b0..No interrupt pending.. + * 0b1..Interrupt pending.. + */ +#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS_MASK) + +#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS_MASK (0x80U) +#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS_SHIFT (7U) +/*! DCDC_INT_STATUS - DCDC Interrupt status after Interrupt Enable. + * 0b0..No interrupt pending.. + * 0b1..Interrupt pending.. + */ +#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS_MASK) + +#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_VAL_MASK (0x100U) +#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_VAL_SHIFT (8U) +/*! DCDC_VAL - Current value of DCDC power status output. + * 0b0..DCDC output Voltage is below the targeted regulation level. + * 0b1..DCDC output Voltage is above the targeted regulation level. + */ +#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_VAL(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_DCDC_VAL_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_DCDC_VAL_MASK) +/*! @} */ + +/*! @name RINGO0_CTRL - First Ring Oscillator module control register. */ +/*! @{ */ + +#define ANACTRL_RINGO0_CTRL_SL_MASK (0x1U) +#define ANACTRL_RINGO0_CTRL_SL_SHIFT (0U) +/*! SL - Select short or long ringo (for all ringos types). + * 0b0..Select short ringo (few elements). + * 0b1..Select long ringo (many elements). + */ +#define ANACTRL_RINGO0_CTRL_SL(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_SL_SHIFT)) & ANACTRL_RINGO0_CTRL_SL_MASK) + +#define ANACTRL_RINGO0_CTRL_FS_MASK (0x2U) +#define ANACTRL_RINGO0_CTRL_FS_SHIFT (1U) +/*! FS - Ringo frequency output divider. + * 0b0..High frequency output (frequency lower than 100 MHz). + * 0b1..Low frequency output (frequency lower than 10 MHz). + */ +#define ANACTRL_RINGO0_CTRL_FS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_FS_SHIFT)) & ANACTRL_RINGO0_CTRL_FS_MASK) + +#define ANACTRL_RINGO0_CTRL_SWN_SWP_MASK (0xCU) +#define ANACTRL_RINGO0_CTRL_SWN_SWP_SHIFT (2U) +/*! SWN_SWP - PN-Ringos (P-Transistor and N-Transistor processing) control. + * 0b00..Normal mode. + * 0b01..P-Monitor mode. Measure with weak P transistor. + * 0b10..P-Monitor mode. Measure with weak N transistor. + * 0b11..Don't use. + */ +#define ANACTRL_RINGO0_CTRL_SWN_SWP(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_SWN_SWP_SHIFT)) & ANACTRL_RINGO0_CTRL_SWN_SWP_MASK) + +#define ANACTRL_RINGO0_CTRL_PD_MASK (0x10U) +#define ANACTRL_RINGO0_CTRL_PD_SHIFT (4U) +/*! PD - Ringo module Power control. + * 0b0..The Ringo module is enabled. + * 0b1..The Ringo module is disabled. + */ +#define ANACTRL_RINGO0_CTRL_PD(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_PD_SHIFT)) & ANACTRL_RINGO0_CTRL_PD_MASK) + +#define ANACTRL_RINGO0_CTRL_E_ND0_MASK (0x20U) +#define ANACTRL_RINGO0_CTRL_E_ND0_SHIFT (5U) +/*! E_ND0 - First NAND2-based ringo control. + * 0b0..First NAND2-based ringo is disabled. + * 0b1..First NAND2-based ringo is enabled. + */ +#define ANACTRL_RINGO0_CTRL_E_ND0(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_ND0_SHIFT)) & ANACTRL_RINGO0_CTRL_E_ND0_MASK) + +#define ANACTRL_RINGO0_CTRL_E_ND1_MASK (0x40U) +#define ANACTRL_RINGO0_CTRL_E_ND1_SHIFT (6U) +/*! E_ND1 - Second NAND2-based ringo control. + * 0b0..Second NAND2-based ringo is disabled. + * 0b1..Second NAND2-based ringo is enabled. + */ +#define ANACTRL_RINGO0_CTRL_E_ND1(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_ND1_SHIFT)) & ANACTRL_RINGO0_CTRL_E_ND1_MASK) + +#define ANACTRL_RINGO0_CTRL_E_NR0_MASK (0x80U) +#define ANACTRL_RINGO0_CTRL_E_NR0_SHIFT (7U) +/*! E_NR0 - First NOR2-based ringo control. + * 0b0..First NOR2-based ringo is disabled. + * 0b1..First NOR2-based ringo is enabled. + */ +#define ANACTRL_RINGO0_CTRL_E_NR0(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_NR0_SHIFT)) & ANACTRL_RINGO0_CTRL_E_NR0_MASK) + +#define ANACTRL_RINGO0_CTRL_E_NR1_MASK (0x100U) +#define ANACTRL_RINGO0_CTRL_E_NR1_SHIFT (8U) +/*! E_NR1 - Second NOR2-based ringo control. + * 0b0..Second NORD2-based ringo is disabled. + * 0b1..Second NORD2-based ringo is enabled. + */ +#define ANACTRL_RINGO0_CTRL_E_NR1(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_NR1_SHIFT)) & ANACTRL_RINGO0_CTRL_E_NR1_MASK) + +#define ANACTRL_RINGO0_CTRL_E_IV0_MASK (0x200U) +#define ANACTRL_RINGO0_CTRL_E_IV0_SHIFT (9U) +/*! E_IV0 - First Inverter-based ringo control. + * 0b0..First INV-based ringo is disabled. + * 0b1..First INV-based ringo is enabled. + */ +#define ANACTRL_RINGO0_CTRL_E_IV0(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_IV0_SHIFT)) & ANACTRL_RINGO0_CTRL_E_IV0_MASK) + +#define ANACTRL_RINGO0_CTRL_E_IV1_MASK (0x400U) +#define ANACTRL_RINGO0_CTRL_E_IV1_SHIFT (10U) +/*! E_IV1 - Second Inverter-based ringo control. + * 0b0..Second INV-based ringo is disabled. + * 0b1..Second INV-based ringo is enabled. + */ +#define ANACTRL_RINGO0_CTRL_E_IV1(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_IV1_SHIFT)) & ANACTRL_RINGO0_CTRL_E_IV1_MASK) + +#define ANACTRL_RINGO0_CTRL_E_PN0_MASK (0x800U) +#define ANACTRL_RINGO0_CTRL_E_PN0_SHIFT (11U) +/*! E_PN0 - First PN (P-Transistor and N-Transistor processing) monitor control. + * 0b0..First PN-based ringo is disabled. + * 0b1..First PN-based ringo is enabled. + */ +#define ANACTRL_RINGO0_CTRL_E_PN0(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_PN0_SHIFT)) & ANACTRL_RINGO0_CTRL_E_PN0_MASK) + +#define ANACTRL_RINGO0_CTRL_E_PN1_MASK (0x1000U) +#define ANACTRL_RINGO0_CTRL_E_PN1_SHIFT (12U) +/*! E_PN1 - Second PN (P-Transistor and N-Transistor processing) monitor control. + * 0b0..Second PN-based ringo is disabled. + * 0b1..Second PN-based ringo is enabled. + */ +#define ANACTRL_RINGO0_CTRL_E_PN1(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_PN1_SHIFT)) & ANACTRL_RINGO0_CTRL_E_PN1_MASK) + +#define ANACTRL_RINGO0_CTRL_DIVISOR_MASK (0xF0000U) +#define ANACTRL_RINGO0_CTRL_DIVISOR_SHIFT (16U) +/*! DIVISOR - Ringo out Clock divider value. Frequency Output = Frequency input / (DIViSOR+1). (minimum = Frequency input / 16) + */ +#define ANACTRL_RINGO0_CTRL_DIVISOR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_DIVISOR_SHIFT)) & ANACTRL_RINGO0_CTRL_DIVISOR_MASK) + +#define ANACTRL_RINGO0_CTRL_DIV_UPDATE_REQ_MASK (0x80000000U) +#define ANACTRL_RINGO0_CTRL_DIV_UPDATE_REQ_SHIFT (31U) +/*! DIV_UPDATE_REQ - Ringo clock out Divider status flag. Set when a change is made to the divider + * value, cleared when the change is complete. + */ +#define ANACTRL_RINGO0_CTRL_DIV_UPDATE_REQ(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_DIV_UPDATE_REQ_SHIFT)) & ANACTRL_RINGO0_CTRL_DIV_UPDATE_REQ_MASK) +/*! @} */ + +/*! @name RINGO1_CTRL - Second Ring Oscillator module control register. */ +/*! @{ */ + +#define ANACTRL_RINGO1_CTRL_S_MASK (0x1U) +#define ANACTRL_RINGO1_CTRL_S_SHIFT (0U) +/*! S - Select short or long ringo (for all ringos types). + * 0b0..Select short ringo (few elements). + * 0b1..Select long ringo (many elements). + */ +#define ANACTRL_RINGO1_CTRL_S(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_S_SHIFT)) & ANACTRL_RINGO1_CTRL_S_MASK) + +#define ANACTRL_RINGO1_CTRL_FS_MASK (0x2U) +#define ANACTRL_RINGO1_CTRL_FS_SHIFT (1U) +/*! FS - Ringo frequency output divider. + * 0b0..High frequency output (frequency lower than 100 MHz). + * 0b1..Low frequency output (frequency lower than 10 MHz). + */ +#define ANACTRL_RINGO1_CTRL_FS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_FS_SHIFT)) & ANACTRL_RINGO1_CTRL_FS_MASK) + +#define ANACTRL_RINGO1_CTRL_PD_MASK (0x4U) +#define ANACTRL_RINGO1_CTRL_PD_SHIFT (2U) +/*! PD - Ringo module Power control. + * 0b0..The Ringo module is enabled. + * 0b1..The Ringo module is disabled. + */ +#define ANACTRL_RINGO1_CTRL_PD(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_PD_SHIFT)) & ANACTRL_RINGO1_CTRL_PD_MASK) + +#define ANACTRL_RINGO1_CTRL_E_R24_MASK (0x8U) +#define ANACTRL_RINGO1_CTRL_E_R24_SHIFT (3U) +/*! E_R24 - . + * 0b0..Ringo is disabled. + * 0b1..Ringo is enabled. + */ +#define ANACTRL_RINGO1_CTRL_E_R24(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_E_R24_SHIFT)) & ANACTRL_RINGO1_CTRL_E_R24_MASK) + +#define ANACTRL_RINGO1_CTRL_E_R35_MASK (0x10U) +#define ANACTRL_RINGO1_CTRL_E_R35_SHIFT (4U) +/*! E_R35 - . + * 0b0..Ringo is disabled. + * 0b1..Ringo is enabled. + */ +#define ANACTRL_RINGO1_CTRL_E_R35(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_E_R35_SHIFT)) & ANACTRL_RINGO1_CTRL_E_R35_MASK) + +#define ANACTRL_RINGO1_CTRL_E_M2_MASK (0x20U) +#define ANACTRL_RINGO1_CTRL_E_M2_SHIFT (5U) +/*! E_M2 - Metal 2 (M2) monitor control. + * 0b0..Ringo is disabled. + * 0b1..Ringo is enabled. + */ +#define ANACTRL_RINGO1_CTRL_E_M2(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_E_M2_SHIFT)) & ANACTRL_RINGO1_CTRL_E_M2_MASK) + +#define ANACTRL_RINGO1_CTRL_E_M3_MASK (0x40U) +#define ANACTRL_RINGO1_CTRL_E_M3_SHIFT (6U) +/*! E_M3 - Metal 3 (M3) monitor control. + * 0b0..Ringo is disabled. + * 0b1..Ringo is enabled. + */ +#define ANACTRL_RINGO1_CTRL_E_M3(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_E_M3_SHIFT)) & ANACTRL_RINGO1_CTRL_E_M3_MASK) + +#define ANACTRL_RINGO1_CTRL_E_M4_MASK (0x80U) +#define ANACTRL_RINGO1_CTRL_E_M4_SHIFT (7U) +/*! E_M4 - Metal 4 (M4) monitor control. + * 0b0..Ringo is disabled. + * 0b1..Ringo is enabled. + */ +#define ANACTRL_RINGO1_CTRL_E_M4(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_E_M4_SHIFT)) & ANACTRL_RINGO1_CTRL_E_M4_MASK) + +#define ANACTRL_RINGO1_CTRL_E_M5_MASK (0x100U) +#define ANACTRL_RINGO1_CTRL_E_M5_SHIFT (8U) +/*! E_M5 - Metal 5 (M5) monitor control. + * 0b0..Ringo is disabled. + * 0b1..Ringo is enabled. + */ +#define ANACTRL_RINGO1_CTRL_E_M5(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_E_M5_SHIFT)) & ANACTRL_RINGO1_CTRL_E_M5_MASK) + +#define ANACTRL_RINGO1_CTRL_DIVISOR_MASK (0xF0000U) +#define ANACTRL_RINGO1_CTRL_DIVISOR_SHIFT (16U) +/*! DIVISOR - Ringo out Clock divider value. Frequency Output = Frequency input / (DIViSOR+1). (minimum = Frequency input / 16) + */ +#define ANACTRL_RINGO1_CTRL_DIVISOR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_DIVISOR_SHIFT)) & ANACTRL_RINGO1_CTRL_DIVISOR_MASK) + +#define ANACTRL_RINGO1_CTRL_DIV_UPDATE_REQ_MASK (0x80000000U) +#define ANACTRL_RINGO1_CTRL_DIV_UPDATE_REQ_SHIFT (31U) +/*! DIV_UPDATE_REQ - Ringo clock out Divider status flag. Set when a change is made to the divider + * value, cleared when the change is complete. + */ +#define ANACTRL_RINGO1_CTRL_DIV_UPDATE_REQ(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_DIV_UPDATE_REQ_SHIFT)) & ANACTRL_RINGO1_CTRL_DIV_UPDATE_REQ_MASK) +/*! @} */ + +/*! @name RINGO2_CTRL - Third Ring Oscillator module control register. */ +/*! @{ */ + +#define ANACTRL_RINGO2_CTRL_S_MASK (0x1U) +#define ANACTRL_RINGO2_CTRL_S_SHIFT (0U) +/*! S - Select short or long ringo (for all ringos types). + * 0b0..Select short ringo (few elements). + * 0b1..Select long ringo (many elements). + */ +#define ANACTRL_RINGO2_CTRL_S(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_S_SHIFT)) & ANACTRL_RINGO2_CTRL_S_MASK) + +#define ANACTRL_RINGO2_CTRL_FS_MASK (0x2U) +#define ANACTRL_RINGO2_CTRL_FS_SHIFT (1U) +/*! FS - Ringo frequency output divider. + * 0b0..High frequency output (frequency lower than 100 MHz). + * 0b1..Low frequency output (frequency lower than 10 MHz). + */ +#define ANACTRL_RINGO2_CTRL_FS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_FS_SHIFT)) & ANACTRL_RINGO2_CTRL_FS_MASK) + +#define ANACTRL_RINGO2_CTRL_PD_MASK (0x4U) +#define ANACTRL_RINGO2_CTRL_PD_SHIFT (2U) +/*! PD - Ringo module Power control. + * 0b0..The Ringo module is enabled. + * 0b1..The Ringo module is disabled. + */ +#define ANACTRL_RINGO2_CTRL_PD(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_PD_SHIFT)) & ANACTRL_RINGO2_CTRL_PD_MASK) + +#define ANACTRL_RINGO2_CTRL_E_R24_MASK (0x8U) +#define ANACTRL_RINGO2_CTRL_E_R24_SHIFT (3U) +/*! E_R24 - . + * 0b0..Ringo is disabled. + * 0b1..Ringo is enabled. + */ +#define ANACTRL_RINGO2_CTRL_E_R24(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_E_R24_SHIFT)) & ANACTRL_RINGO2_CTRL_E_R24_MASK) + +#define ANACTRL_RINGO2_CTRL_E_R35_MASK (0x10U) +#define ANACTRL_RINGO2_CTRL_E_R35_SHIFT (4U) +/*! E_R35 - . + * 0b0..Ringo is disabled. + * 0b1..Ringo is enabled. + */ +#define ANACTRL_RINGO2_CTRL_E_R35(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_E_R35_SHIFT)) & ANACTRL_RINGO2_CTRL_E_R35_MASK) + +#define ANACTRL_RINGO2_CTRL_E_M2_MASK (0x20U) +#define ANACTRL_RINGO2_CTRL_E_M2_SHIFT (5U) +/*! E_M2 - Metal 2 (M2) monitor control. + * 0b0..Ringo is disabled. + * 0b1..Ringo is enabled. + */ +#define ANACTRL_RINGO2_CTRL_E_M2(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_E_M2_SHIFT)) & ANACTRL_RINGO2_CTRL_E_M2_MASK) + +#define ANACTRL_RINGO2_CTRL_E_M3_MASK (0x40U) +#define ANACTRL_RINGO2_CTRL_E_M3_SHIFT (6U) +/*! E_M3 - Metal 3 (M3) monitor control. + * 0b0..Ringo is disabled. + * 0b1..Ringo is enabled. + */ +#define ANACTRL_RINGO2_CTRL_E_M3(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_E_M3_SHIFT)) & ANACTRL_RINGO2_CTRL_E_M3_MASK) + +#define ANACTRL_RINGO2_CTRL_E_M4_MASK (0x80U) +#define ANACTRL_RINGO2_CTRL_E_M4_SHIFT (7U) +/*! E_M4 - Metal 4 (M4) monitor control. + * 0b0..Ringo is disabled. + * 0b1..Ringo is enabled. + */ +#define ANACTRL_RINGO2_CTRL_E_M4(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_E_M4_SHIFT)) & ANACTRL_RINGO2_CTRL_E_M4_MASK) + +#define ANACTRL_RINGO2_CTRL_E_M5_MASK (0x100U) +#define ANACTRL_RINGO2_CTRL_E_M5_SHIFT (8U) +/*! E_M5 - Metal 5 (M5) monitor control. + * 0b0..Ringo is disabled. + * 0b1..Ringo is enabled. + */ +#define ANACTRL_RINGO2_CTRL_E_M5(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_E_M5_SHIFT)) & ANACTRL_RINGO2_CTRL_E_M5_MASK) + +#define ANACTRL_RINGO2_CTRL_DIVISOR_MASK (0xF0000U) +#define ANACTRL_RINGO2_CTRL_DIVISOR_SHIFT (16U) +/*! DIVISOR - Ringo out Clock divider value. Frequency Output = Frequency input / (DIViSOR+1). (minimum = Frequency input / 16) + */ +#define ANACTRL_RINGO2_CTRL_DIVISOR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_DIVISOR_SHIFT)) & ANACTRL_RINGO2_CTRL_DIVISOR_MASK) + +#define ANACTRL_RINGO2_CTRL_DIV_UPDATE_REQ_MASK (0x80000000U) +#define ANACTRL_RINGO2_CTRL_DIV_UPDATE_REQ_SHIFT (31U) +/*! DIV_UPDATE_REQ - Ringo clock out Divider status flag. Set when a change is made to the divider + * value, cleared when the change is complete. + */ +#define ANACTRL_RINGO2_CTRL_DIV_UPDATE_REQ(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_DIV_UPDATE_REQ_SHIFT)) & ANACTRL_RINGO2_CTRL_DIV_UPDATE_REQ_MASK) +/*! @} */ + +/*! @name LDO_XO32M - High Speed Crystal Oscillator (12 MHz - 32 MHz) Voltage Source Supply Control register */ +/*! @{ */ + +#define ANACTRL_LDO_XO32M_BYPASS_MASK (0x2U) +#define ANACTRL_LDO_XO32M_BYPASS_SHIFT (1U) +/*! BYPASS - Activate LDO bypass. + * 0b0..Disable bypass mode (for normal operations). + * 0b1..Activate LDO bypass. + */ +#define ANACTRL_LDO_XO32M_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_LDO_XO32M_BYPASS_SHIFT)) & ANACTRL_LDO_XO32M_BYPASS_MASK) + +#define ANACTRL_LDO_XO32M_HIGHZ_MASK (0x4U) +#define ANACTRL_LDO_XO32M_HIGHZ_SHIFT (2U) +/*! HIGHZ - . + * 0b0..Output in High normal state. + * 0b1..Output in High Impedance state. + */ +#define ANACTRL_LDO_XO32M_HIGHZ(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_LDO_XO32M_HIGHZ_SHIFT)) & ANACTRL_LDO_XO32M_HIGHZ_MASK) + +#define ANACTRL_LDO_XO32M_VOUT_MASK (0x38U) +#define ANACTRL_LDO_XO32M_VOUT_SHIFT (3U) +/*! VOUT - Sets the LDO output level. + * 0b000..0.750 V. + * 0b001..0.775 V. + * 0b010..0.800 V. + * 0b011..0.825 V. + * 0b100..0.850 V. + * 0b101..0.875 V. + * 0b110..0.900 V. + * 0b111..0.925 V. + */ +#define ANACTRL_LDO_XO32M_VOUT(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_LDO_XO32M_VOUT_SHIFT)) & ANACTRL_LDO_XO32M_VOUT_MASK) + +#define ANACTRL_LDO_XO32M_IBIAS_MASK (0xC0U) +#define ANACTRL_LDO_XO32M_IBIAS_SHIFT (6U) +/*! IBIAS - Adjust the biasing current. + */ +#define ANACTRL_LDO_XO32M_IBIAS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_LDO_XO32M_IBIAS_SHIFT)) & ANACTRL_LDO_XO32M_IBIAS_MASK) + +#define ANACTRL_LDO_XO32M_STABMODE_MASK (0x300U) +#define ANACTRL_LDO_XO32M_STABMODE_SHIFT (8U) +/*! STABMODE - Stability configuration. + */ +#define ANACTRL_LDO_XO32M_STABMODE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_LDO_XO32M_STABMODE_SHIFT)) & ANACTRL_LDO_XO32M_STABMODE_MASK) +/*! @} */ + +/*! @name AUX_BIAS - AUX_BIAS */ +/*! @{ */ + +#define ANACTRL_AUX_BIAS_VREF1VENABLE_MASK (0x2U) +#define ANACTRL_AUX_BIAS_VREF1VENABLE_SHIFT (1U) +/*! VREF1VENABLE - Control output of 1V reference voltage. + * 0b0..Output of 1V reference voltage buffer is bypassed. + * 0b1..Output of 1V reference voltage is enabled. + */ +#define ANACTRL_AUX_BIAS_VREF1VENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_AUX_BIAS_VREF1VENABLE_SHIFT)) & ANACTRL_AUX_BIAS_VREF1VENABLE_MASK) + +#define ANACTRL_AUX_BIAS_ITRIM_MASK (0x7CU) +#define ANACTRL_AUX_BIAS_ITRIM_SHIFT (2U) +/*! ITRIM - current trimming control word. + */ +#define ANACTRL_AUX_BIAS_ITRIM(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_AUX_BIAS_ITRIM_SHIFT)) & ANACTRL_AUX_BIAS_ITRIM_MASK) + +#define ANACTRL_AUX_BIAS_PTATITRIM_MASK (0xF80U) +#define ANACTRL_AUX_BIAS_PTATITRIM_SHIFT (7U) +/*! PTATITRIM - current trimming control word for ptat current. + */ +#define ANACTRL_AUX_BIAS_PTATITRIM(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_AUX_BIAS_PTATITRIM_SHIFT)) & ANACTRL_AUX_BIAS_PTATITRIM_MASK) + +#define ANACTRL_AUX_BIAS_VREF1VTRIM_MASK (0x1F000U) +#define ANACTRL_AUX_BIAS_VREF1VTRIM_SHIFT (12U) +/*! VREF1VTRIM - voltage trimming control word. + */ +#define ANACTRL_AUX_BIAS_VREF1VTRIM(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_AUX_BIAS_VREF1VTRIM_SHIFT)) & ANACTRL_AUX_BIAS_VREF1VTRIM_MASK) + +#define ANACTRL_AUX_BIAS_VREF1VCURVETRIM_MASK (0xE0000U) +#define ANACTRL_AUX_BIAS_VREF1VCURVETRIM_SHIFT (17U) +/*! VREF1VCURVETRIM - Control bit to configure trimming state of mirror. + */ +#define ANACTRL_AUX_BIAS_VREF1VCURVETRIM(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_AUX_BIAS_VREF1VCURVETRIM_SHIFT)) & ANACTRL_AUX_BIAS_VREF1VCURVETRIM_MASK) + +#define ANACTRL_AUX_BIAS_ITRIMCTRL0_MASK (0x100000U) +#define ANACTRL_AUX_BIAS_ITRIMCTRL0_SHIFT (20U) +/*! ITRIMCTRL0 - Control bit to configure trimming state of mirror. + */ +#define ANACTRL_AUX_BIAS_ITRIMCTRL0(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_AUX_BIAS_ITRIMCTRL0_SHIFT)) & ANACTRL_AUX_BIAS_ITRIMCTRL0_MASK) + +#define ANACTRL_AUX_BIAS_ITRIMCTRL1_MASK (0x200000U) +#define ANACTRL_AUX_BIAS_ITRIMCTRL1_SHIFT (21U) +/*! ITRIMCTRL1 - Control bit to configure trimming state of mirror. + */ +#define ANACTRL_AUX_BIAS_ITRIMCTRL1(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_AUX_BIAS_ITRIMCTRL1_SHIFT)) & ANACTRL_AUX_BIAS_ITRIMCTRL1_MASK) +/*! @} */ + +/*! @name DUMMY_CTRL - Dummy Control bus to analog modules */ +/*! @{ */ + +#define ANACTRL_DUMMY_CTRL_XO32M_ADC_CLK_MODE_MASK (0xC00U) +#define ANACTRL_DUMMY_CTRL_XO32M_ADC_CLK_MODE_SHIFT (10U) +/*! XO32M_ADC_CLK_MODE - Control High speed Crystal oscillator mode of the ADC clock. + * 0b00..High speed Crystal oscillator output to ADC is disabled. + * 0b01..High speed Crystal oscillator output to ADC is enable. + */ +#define ANACTRL_DUMMY_CTRL_XO32M_ADC_CLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_DUMMY_CTRL_XO32M_ADC_CLK_MODE_SHIFT)) & ANACTRL_DUMMY_CTRL_XO32M_ADC_CLK_MODE_MASK) +/*! @} */ + +/*! @name USBHS_PHY_CTRL - USB High Speed Phy Control */ +/*! @{ */ + +#define ANACTRL_USBHS_PHY_CTRL_usb_vbusvalid_ext_MASK (0x1U) +#define ANACTRL_USBHS_PHY_CTRL_usb_vbusvalid_ext_SHIFT (0U) +/*! usb_vbusvalid_ext - Override value for Vbus if using external detectors. + */ +#define ANACTRL_USBHS_PHY_CTRL_usb_vbusvalid_ext(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_CTRL_usb_vbusvalid_ext_SHIFT)) & ANACTRL_USBHS_PHY_CTRL_usb_vbusvalid_ext_MASK) + +#define ANACTRL_USBHS_PHY_CTRL_usb_id_ext_MASK (0x2U) +#define ANACTRL_USBHS_PHY_CTRL_usb_id_ext_SHIFT (1U) +/*! usb_id_ext - Override value for ID if using external detectors. + */ +#define ANACTRL_USBHS_PHY_CTRL_usb_id_ext(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_CTRL_usb_id_ext_SHIFT)) & ANACTRL_USBHS_PHY_CTRL_usb_id_ext_MASK) + +#define ANACTRL_USBHS_PHY_CTRL_iso_atx_MASK (0x8U) +#define ANACTRL_USBHS_PHY_CTRL_iso_atx_SHIFT (3U) +/*! iso_atx - . + */ +#define ANACTRL_USBHS_PHY_CTRL_iso_atx(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_CTRL_iso_atx_SHIFT)) & ANACTRL_USBHS_PHY_CTRL_iso_atx_MASK) +/*! @} */ + +/*! @name USBHS_PHY_TRIM - USB High Speed Phy Trim values */ +/*! @{ */ + +#define ANACTRL_USBHS_PHY_TRIM_trim_usb_reg_env_tail_adj_vd_MASK (0x3U) +#define ANACTRL_USBHS_PHY_TRIM_trim_usb_reg_env_tail_adj_vd_SHIFT (0U) +/*! trim_usb_reg_env_tail_adj_vd - Adjusts time constant of HS RX squelch (envelope) comparator. + */ +#define ANACTRL_USBHS_PHY_TRIM_trim_usb_reg_env_tail_adj_vd(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_TRIM_trim_usb_reg_env_tail_adj_vd_SHIFT)) & ANACTRL_USBHS_PHY_TRIM_trim_usb_reg_env_tail_adj_vd_MASK) + +#define ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_d_cal_MASK (0x3CU) +#define ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_d_cal_SHIFT (2U) +/*! trim_usbphy_tx_d_cal - . + */ +#define ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_d_cal(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_d_cal_SHIFT)) & ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_d_cal_MASK) + +#define ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dp_MASK (0x7C0U) +#define ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dp_SHIFT (6U) +/*! trim_usbphy_tx_cal45dp - . + */ +#define ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dp(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dp_SHIFT)) & ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dp_MASK) + +#define ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dm_MASK (0xF800U) +#define ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dm_SHIFT (11U) +/*! trim_usbphy_tx_cal45dm - . + */ +#define ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dm(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dm_SHIFT)) & ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dm_MASK) + +#define ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_tst_MASK (0x30000U) +#define ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_tst_SHIFT (16U) +/*! trim_usb2_refbias_tst - . + */ +#define ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_tst(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_tst_SHIFT)) & ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_tst_MASK) + +#define ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_vbgadj_MASK (0x1C0000U) +#define ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_vbgadj_SHIFT (18U) +/*! trim_usb2_refbias_vbgadj - . + */ +#define ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_vbgadj(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_vbgadj_SHIFT)) & ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_vbgadj_MASK) + +#define ANACTRL_USBHS_PHY_TRIM_trim_pll_ctrl0_div_sel_MASK (0xE00000U) +#define ANACTRL_USBHS_PHY_TRIM_trim_pll_ctrl0_div_sel_SHIFT (21U) +/*! trim_pll_ctrl0_div_sel - . + */ +#define ANACTRL_USBHS_PHY_TRIM_trim_pll_ctrl0_div_sel(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_TRIM_trim_pll_ctrl0_div_sel_SHIFT)) & ANACTRL_USBHS_PHY_TRIM_trim_pll_ctrl0_div_sel_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group ANACTRL_Register_Masks */ + + +/* ANACTRL - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral ANACTRL base address */ + #define ANACTRL_BASE (0x50013000u) + /** Peripheral ANACTRL base address */ + #define ANACTRL_BASE_NS (0x40013000u) + /** Peripheral ANACTRL base pointer */ + #define ANACTRL ((ANACTRL_Type *)ANACTRL_BASE) + /** Peripheral ANACTRL base pointer */ + #define ANACTRL_NS ((ANACTRL_Type *)ANACTRL_BASE_NS) + /** Array initializer of ANACTRL peripheral base addresses */ + #define ANACTRL_BASE_ADDRS { ANACTRL_BASE } + /** Array initializer of ANACTRL peripheral base pointers */ + #define ANACTRL_BASE_PTRS { ANACTRL } + /** Array initializer of ANACTRL peripheral base addresses */ + #define ANACTRL_BASE_ADDRS_NS { ANACTRL_BASE_NS } + /** Array initializer of ANACTRL peripheral base pointers */ + #define ANACTRL_BASE_PTRS_NS { ANACTRL_NS } +#else + /** Peripheral ANACTRL base address */ + #define ANACTRL_BASE (0x40013000u) + /** Peripheral ANACTRL base pointer */ + #define ANACTRL ((ANACTRL_Type *)ANACTRL_BASE) + /** Array initializer of ANACTRL peripheral base addresses */ + #define ANACTRL_BASE_ADDRS { ANACTRL_BASE } + /** Array initializer of ANACTRL peripheral base pointers */ + #define ANACTRL_BASE_PTRS { ANACTRL } +#endif + +/*! + * @} + */ /* end of group ANACTRL_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- CAN Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CAN_Peripheral_Access_Layer CAN Peripheral Access Layer + * @{ + */ + +/** CAN - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[12]; + __IO uint32_t DBTP; /**< Data Bit Timing Prescaler Register, offset: 0xC */ + __IO uint32_t TEST; /**< Test Register, offset: 0x10 */ + uint8_t RESERVED_1[4]; + __IO uint32_t CCCR; /**< CC Control Register, offset: 0x18 */ + __IO uint32_t NBTP; /**< Nominal Bit Timing and Prescaler Register, offset: 0x1C */ + __IO uint32_t TSCC; /**< Timestamp Counter Configuration, offset: 0x20 */ + __I uint32_t TSCV; /**< Timestamp Counter Value, offset: 0x24 */ + __IO uint32_t TOCC; /**< Timeout Counter Configuration, offset: 0x28 */ + __I uint32_t TOCV; /**< Timeout Counter Value, offset: 0x2C */ + uint8_t RESERVED_2[16]; + __I uint32_t ECR; /**< Error Counter Register, offset: 0x40 */ + __I uint32_t PSR; /**< Protocol Status Register, offset: 0x44 */ + __IO uint32_t TDCR; /**< Transmitter Delay Compensator Register, offset: 0x48 */ + uint8_t RESERVED_3[4]; + __IO uint32_t IR; /**< Interrupt Register, offset: 0x50 */ + __IO uint32_t IE; /**< Interrupt Enable, offset: 0x54 */ + __IO uint32_t ILS; /**< Interrupt Line Select, offset: 0x58 */ + __IO uint32_t ILE; /**< Interrupt Line Enable, offset: 0x5C */ + uint8_t RESERVED_4[32]; + __IO uint32_t GFC; /**< Global Filter Configuration, offset: 0x80 */ + __IO uint32_t SIDFC; /**< Standard ID Filter Configuration, offset: 0x84 */ + __IO uint32_t XIDFC; /**< Extended ID Filter Configuration, offset: 0x88 */ + uint8_t RESERVED_5[4]; + __IO uint32_t XIDAM; /**< Extended ID AND Mask, offset: 0x90 */ + __I uint32_t HPMS; /**< High Priority Message Status, offset: 0x94 */ + __IO uint32_t NDAT1; /**< New Data 1, offset: 0x98 */ + __IO uint32_t NDAT2; /**< New Data 2, offset: 0x9C */ + __IO uint32_t RXF0C; /**< Rx FIFO 0 Configuration, offset: 0xA0 */ + __I uint32_t RXF0S; /**< Rx FIFO 0 Status, offset: 0xA4 */ + __IO uint32_t RXF0A; /**< Rx FIFO 0 Acknowledge, offset: 0xA8 */ + __IO uint32_t RXBC; /**< Rx Buffer Configuration, offset: 0xAC */ + __IO uint32_t RXF1C; /**< Rx FIFO 1 Configuration, offset: 0xB0 */ + __I uint32_t RXF1S; /**< Rx FIFO 1 Status, offset: 0xB4 */ + __IO uint32_t RXF1A; /**< Rx FIFO 1 Acknowledge, offset: 0xB8 */ + __IO uint32_t RXESC; /**< Rx Buffer and FIFO Element Size Configuration, offset: 0xBC */ + __IO uint32_t TXBC; /**< Tx Buffer Configuration, offset: 0xC0 */ + __IO uint32_t TXFQS; /**< Tx FIFO/Queue Status, offset: 0xC4 */ + __IO uint32_t TXESC; /**< Tx Buffer Element Size Configuration, offset: 0xC8 */ + __I uint32_t TXBRP; /**< Tx Buffer Request Pending, offset: 0xCC */ + __IO uint32_t TXBAR; /**< Tx Buffer Add Request, offset: 0xD0 */ + __IO uint32_t TXBCR; /**< Tx Buffer Cancellation Request, offset: 0xD4 */ + __I uint32_t TXBTO; /**< Tx Buffer Transmission Occurred, offset: 0xD8 */ + __I uint32_t TXBCF; /**< Tx Buffer Cancellation Finished, offset: 0xDC */ + __IO uint32_t TXBTIE; /**< Tx Buffer Transmission Interrupt Enable, offset: 0xE0 */ + __IO uint32_t TXBCIE; /**< Tx Buffer Cancellation Finished Interrupt Enable, offset: 0xE4 */ + uint8_t RESERVED_6[8]; + __IO uint32_t TXEFC; /**< Tx Event FIFO Configuration, offset: 0xF0 */ + __I uint32_t TXEFS; /**< Tx Event FIFO Status, offset: 0xF4 */ + __IO uint32_t TXEFA; /**< Tx Event FIFO Acknowledge, offset: 0xF8 */ + uint8_t RESERVED_7[260]; + __IO uint32_t MRBA; /**< CAN Message RAM Base Address, offset: 0x200 */ + uint8_t RESERVED_8[508]; + __IO uint32_t ETSCC; /**< External Timestamp Counter Configuration, offset: 0x400 */ + uint8_t RESERVED_9[508]; + __IO uint32_t ETSCV; /**< External Timestamp Counter Value, offset: 0x600 */ +} CAN_Type; + +/* ---------------------------------------------------------------------------- + -- CAN Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CAN_Register_Masks CAN Register Masks + * @{ + */ + +/*! @name DBTP - Data Bit Timing Prescaler Register */ +/*! @{ */ + +#define CAN_DBTP_DSJW_MASK (0xFU) +#define CAN_DBTP_DSJW_SHIFT (0U) +/*! DSJW - Data (re)synchronization jump width. + */ +#define CAN_DBTP_DSJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBTP_DSJW_SHIFT)) & CAN_DBTP_DSJW_MASK) + +#define CAN_DBTP_DTSEG2_MASK (0xF0U) +#define CAN_DBTP_DTSEG2_SHIFT (4U) +/*! DTSEG2 - Data time segment after sample point. + */ +#define CAN_DBTP_DTSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBTP_DTSEG2_SHIFT)) & CAN_DBTP_DTSEG2_MASK) + +#define CAN_DBTP_DTSEG1_MASK (0x1F00U) +#define CAN_DBTP_DTSEG1_SHIFT (8U) +/*! DTSEG1 - Data time segment before sample point. + */ +#define CAN_DBTP_DTSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBTP_DTSEG1_SHIFT)) & CAN_DBTP_DTSEG1_MASK) + +#define CAN_DBTP_DBRP_MASK (0x1F0000U) +#define CAN_DBTP_DBRP_SHIFT (16U) +/*! DBRP - Data bit rate prescaler. + */ +#define CAN_DBTP_DBRP(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBTP_DBRP_SHIFT)) & CAN_DBTP_DBRP_MASK) + +#define CAN_DBTP_TDC_MASK (0x800000U) +#define CAN_DBTP_TDC_SHIFT (23U) +/*! TDC - Transmitter delay compensation. + */ +#define CAN_DBTP_TDC(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBTP_TDC_SHIFT)) & CAN_DBTP_TDC_MASK) +/*! @} */ + +/*! @name TEST - Test Register */ +/*! @{ */ + +#define CAN_TEST_LBCK_MASK (0x10U) +#define CAN_TEST_LBCK_SHIFT (4U) +/*! LBCK - Loop back mode. + */ +#define CAN_TEST_LBCK(x) (((uint32_t)(((uint32_t)(x)) << CAN_TEST_LBCK_SHIFT)) & CAN_TEST_LBCK_MASK) + +#define CAN_TEST_TX_MASK (0x60U) +#define CAN_TEST_TX_SHIFT (5U) +/*! TX - Control of transmit pin. + */ +#define CAN_TEST_TX(x) (((uint32_t)(((uint32_t)(x)) << CAN_TEST_TX_SHIFT)) & CAN_TEST_TX_MASK) + +#define CAN_TEST_RX_MASK (0x80U) +#define CAN_TEST_RX_SHIFT (7U) +/*! RX - Monitors the actual value of the CAN_RXD. + */ +#define CAN_TEST_RX(x) (((uint32_t)(((uint32_t)(x)) << CAN_TEST_RX_SHIFT)) & CAN_TEST_RX_MASK) +/*! @} */ + +/*! @name CCCR - CC Control Register */ +/*! @{ */ + +#define CAN_CCCR_INIT_MASK (0x1U) +#define CAN_CCCR_INIT_SHIFT (0U) +/*! INIT - Initialization. + */ +#define CAN_CCCR_INIT(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_INIT_SHIFT)) & CAN_CCCR_INIT_MASK) + +#define CAN_CCCR_CCE_MASK (0x2U) +#define CAN_CCCR_CCE_SHIFT (1U) +/*! CCE - Configuration change enable. + */ +#define CAN_CCCR_CCE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_CCE_SHIFT)) & CAN_CCCR_CCE_MASK) + +#define CAN_CCCR_ASM_MASK (0x4U) +#define CAN_CCCR_ASM_SHIFT (2U) +/*! ASM - Restricted operational mode. + */ +#define CAN_CCCR_ASM(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_ASM_SHIFT)) & CAN_CCCR_ASM_MASK) + +#define CAN_CCCR_CSA_MASK (0x8U) +#define CAN_CCCR_CSA_SHIFT (3U) +/*! CSA - Clock Stop Acknowledge. + */ +#define CAN_CCCR_CSA(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_CSA_SHIFT)) & CAN_CCCR_CSA_MASK) + +#define CAN_CCCR_CSR_MASK (0x10U) +#define CAN_CCCR_CSR_SHIFT (4U) +/*! CSR - Clock Stop Request. + */ +#define CAN_CCCR_CSR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_CSR_SHIFT)) & CAN_CCCR_CSR_MASK) + +#define CAN_CCCR_MON_MASK (0x20U) +#define CAN_CCCR_MON_SHIFT (5U) +/*! MON - Bus monitoring mode. + */ +#define CAN_CCCR_MON(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_MON_SHIFT)) & CAN_CCCR_MON_MASK) + +#define CAN_CCCR_DAR_MASK (0x40U) +#define CAN_CCCR_DAR_SHIFT (6U) +/*! DAR - Disable automatic retransmission. + */ +#define CAN_CCCR_DAR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_DAR_SHIFT)) & CAN_CCCR_DAR_MASK) + +#define CAN_CCCR_TEST_MASK (0x80U) +#define CAN_CCCR_TEST_SHIFT (7U) +/*! TEST - Test mode enable. + */ +#define CAN_CCCR_TEST(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_TEST_SHIFT)) & CAN_CCCR_TEST_MASK) + +#define CAN_CCCR_FDOE_MASK (0x100U) +#define CAN_CCCR_FDOE_SHIFT (8U) +/*! FDOE - CAN FD operation enable. + */ +#define CAN_CCCR_FDOE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_FDOE_SHIFT)) & CAN_CCCR_FDOE_MASK) + +#define CAN_CCCR_BRSE_MASK (0x200U) +#define CAN_CCCR_BRSE_SHIFT (9U) +/*! BRSE - When CAN FD operation is disabled, this bit is not evaluated. + */ +#define CAN_CCCR_BRSE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_BRSE_SHIFT)) & CAN_CCCR_BRSE_MASK) + +#define CAN_CCCR_PXHD_MASK (0x1000U) +#define CAN_CCCR_PXHD_SHIFT (12U) +/*! PXHD - Protocol exception handling disable. + */ +#define CAN_CCCR_PXHD(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_PXHD_SHIFT)) & CAN_CCCR_PXHD_MASK) + +#define CAN_CCCR_EFBI_MASK (0x2000U) +#define CAN_CCCR_EFBI_SHIFT (13U) +/*! EFBI - Edge filtering during bus integration. + */ +#define CAN_CCCR_EFBI(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_EFBI_SHIFT)) & CAN_CCCR_EFBI_MASK) + +#define CAN_CCCR_TXP_MASK (0x4000U) +#define CAN_CCCR_TXP_SHIFT (14U) +/*! TXP - Transmit pause. + */ +#define CAN_CCCR_TXP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_TXP_SHIFT)) & CAN_CCCR_TXP_MASK) + +#define CAN_CCCR_NISO_MASK (0x8000U) +#define CAN_CCCR_NISO_SHIFT (15U) +/*! NISO - Non ISO operation. + */ +#define CAN_CCCR_NISO(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_NISO_SHIFT)) & CAN_CCCR_NISO_MASK) +/*! @} */ + +/*! @name NBTP - Nominal Bit Timing and Prescaler Register */ +/*! @{ */ + +#define CAN_NBTP_NTSEG2_MASK (0x7FU) +#define CAN_NBTP_NTSEG2_SHIFT (0U) +/*! NTSEG2 - Nominal time segment after sample point. + */ +#define CAN_NBTP_NTSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_NBTP_NTSEG2_SHIFT)) & CAN_NBTP_NTSEG2_MASK) + +#define CAN_NBTP_NTSEG1_MASK (0xFF00U) +#define CAN_NBTP_NTSEG1_SHIFT (8U) +/*! NTSEG1 - Nominal time segment before sample point. + */ +#define CAN_NBTP_NTSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_NBTP_NTSEG1_SHIFT)) & CAN_NBTP_NTSEG1_MASK) + +#define CAN_NBTP_NBRP_MASK (0x1FF0000U) +#define CAN_NBTP_NBRP_SHIFT (16U) +/*! NBRP - Nominal bit rate prescaler. + */ +#define CAN_NBTP_NBRP(x) (((uint32_t)(((uint32_t)(x)) << CAN_NBTP_NBRP_SHIFT)) & CAN_NBTP_NBRP_MASK) + +#define CAN_NBTP_NSJW_MASK (0xFE000000U) +#define CAN_NBTP_NSJW_SHIFT (25U) +/*! NSJW - Nominal (re)synchronization jump width. + */ +#define CAN_NBTP_NSJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_NBTP_NSJW_SHIFT)) & CAN_NBTP_NSJW_MASK) +/*! @} */ + +/*! @name TSCC - Timestamp Counter Configuration */ +/*! @{ */ + +#define CAN_TSCC_TSS_MASK (0x3U) +#define CAN_TSCC_TSS_SHIFT (0U) +/*! TSS - Timestamp select. + */ +#define CAN_TSCC_TSS(x) (((uint32_t)(((uint32_t)(x)) << CAN_TSCC_TSS_SHIFT)) & CAN_TSCC_TSS_MASK) + +#define CAN_TSCC_TCP_MASK (0xF0000U) +#define CAN_TSCC_TCP_SHIFT (16U) +/*! TCP - Timestamp counter prescaler Configures the timestamp and timeout counters time unit in multiple of CAN bit times. + */ +#define CAN_TSCC_TCP(x) (((uint32_t)(((uint32_t)(x)) << CAN_TSCC_TCP_SHIFT)) & CAN_TSCC_TCP_MASK) +/*! @} */ + +/*! @name TSCV - Timestamp Counter Value */ +/*! @{ */ + +#define CAN_TSCV_TSC_MASK (0xFFFFU) +#define CAN_TSCV_TSC_SHIFT (0U) +/*! TSC - Timestamp counter. + */ +#define CAN_TSCV_TSC(x) (((uint32_t)(((uint32_t)(x)) << CAN_TSCV_TSC_SHIFT)) & CAN_TSCV_TSC_MASK) +/*! @} */ + +/*! @name TOCC - Timeout Counter Configuration */ +/*! @{ */ + +#define CAN_TOCC_ETOC_MASK (0x1U) +#define CAN_TOCC_ETOC_SHIFT (0U) +/*! ETOC - Enable timeout counter. + */ +#define CAN_TOCC_ETOC(x) (((uint32_t)(((uint32_t)(x)) << CAN_TOCC_ETOC_SHIFT)) & CAN_TOCC_ETOC_MASK) + +#define CAN_TOCC_TOS_MASK (0x6U) +#define CAN_TOCC_TOS_SHIFT (1U) +/*! TOS - Timeout select. + */ +#define CAN_TOCC_TOS(x) (((uint32_t)(((uint32_t)(x)) << CAN_TOCC_TOS_SHIFT)) & CAN_TOCC_TOS_MASK) + +#define CAN_TOCC_TOP_MASK (0xFFFF0000U) +#define CAN_TOCC_TOP_SHIFT (16U) +/*! TOP - Timeout period. + */ +#define CAN_TOCC_TOP(x) (((uint32_t)(((uint32_t)(x)) << CAN_TOCC_TOP_SHIFT)) & CAN_TOCC_TOP_MASK) +/*! @} */ + +/*! @name TOCV - Timeout Counter Value */ +/*! @{ */ + +#define CAN_TOCV_TOC_MASK (0xFFFFU) +#define CAN_TOCV_TOC_SHIFT (0U) +/*! TOC - Timeout counter. + */ +#define CAN_TOCV_TOC(x) (((uint32_t)(((uint32_t)(x)) << CAN_TOCV_TOC_SHIFT)) & CAN_TOCV_TOC_MASK) +/*! @} */ + +/*! @name ECR - Error Counter Register */ +/*! @{ */ + +#define CAN_ECR_TEC_MASK (0xFFU) +#define CAN_ECR_TEC_SHIFT (0U) +/*! TEC - Transmit error counter. + */ +#define CAN_ECR_TEC(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TEC_SHIFT)) & CAN_ECR_TEC_MASK) + +#define CAN_ECR_REC_MASK (0x7F00U) +#define CAN_ECR_REC_SHIFT (8U) +/*! REC - Receive error counter. + */ +#define CAN_ECR_REC(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_REC_SHIFT)) & CAN_ECR_REC_MASK) + +#define CAN_ECR_RP_MASK (0x8000U) +#define CAN_ECR_RP_SHIFT (15U) +/*! RP - Receive error passive. + */ +#define CAN_ECR_RP(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RP_SHIFT)) & CAN_ECR_RP_MASK) + +#define CAN_ECR_CEL_MASK (0xFF0000U) +#define CAN_ECR_CEL_SHIFT (16U) +/*! CEL - CAN error logging. + */ +#define CAN_ECR_CEL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_CEL_SHIFT)) & CAN_ECR_CEL_MASK) +/*! @} */ + +/*! @name PSR - Protocol Status Register */ +/*! @{ */ + +#define CAN_PSR_LEC_MASK (0x7U) +#define CAN_PSR_LEC_SHIFT (0U) +/*! LEC - Last error code. + */ +#define CAN_PSR_LEC(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_LEC_SHIFT)) & CAN_PSR_LEC_MASK) + +#define CAN_PSR_ACT_MASK (0x18U) +#define CAN_PSR_ACT_SHIFT (3U) +/*! ACT - Activity. + */ +#define CAN_PSR_ACT(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_ACT_SHIFT)) & CAN_PSR_ACT_MASK) + +#define CAN_PSR_EP_MASK (0x20U) +#define CAN_PSR_EP_SHIFT (5U) +/*! EP - Error Passive. + */ +#define CAN_PSR_EP(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_EP_SHIFT)) & CAN_PSR_EP_MASK) + +#define CAN_PSR_EW_MASK (0x40U) +#define CAN_PSR_EW_SHIFT (6U) +/*! EW - Warning status. + */ +#define CAN_PSR_EW(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_EW_SHIFT)) & CAN_PSR_EW_MASK) + +#define CAN_PSR_BO_MASK (0x80U) +#define CAN_PSR_BO_SHIFT (7U) +/*! BO - Bus Off Status. + */ +#define CAN_PSR_BO(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_BO_SHIFT)) & CAN_PSR_BO_MASK) + +#define CAN_PSR_DLEC_MASK (0x700U) +#define CAN_PSR_DLEC_SHIFT (8U) +/*! DLEC - Data phase last error code. + */ +#define CAN_PSR_DLEC(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_DLEC_SHIFT)) & CAN_PSR_DLEC_MASK) + +#define CAN_PSR_RESI_MASK (0x800U) +#define CAN_PSR_RESI_SHIFT (11U) +/*! RESI - ESI flag of the last received CAN FD message. + */ +#define CAN_PSR_RESI(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_RESI_SHIFT)) & CAN_PSR_RESI_MASK) + +#define CAN_PSR_RBRS_MASK (0x1000U) +#define CAN_PSR_RBRS_SHIFT (12U) +/*! RBRS - BRS flag of last received CAN FD message. + */ +#define CAN_PSR_RBRS(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_RBRS_SHIFT)) & CAN_PSR_RBRS_MASK) + +#define CAN_PSR_RFDF_MASK (0x2000U) +#define CAN_PSR_RFDF_SHIFT (13U) +/*! RFDF - Received a CAN FD message. + */ +#define CAN_PSR_RFDF(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_RFDF_SHIFT)) & CAN_PSR_RFDF_MASK) + +#define CAN_PSR_PXE_MASK (0x4000U) +#define CAN_PSR_PXE_SHIFT (14U) +/*! PXE - Protocol exception event. + */ +#define CAN_PSR_PXE(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_PXE_SHIFT)) & CAN_PSR_PXE_MASK) + +#define CAN_PSR_TDCV_MASK (0x7F0000U) +#define CAN_PSR_TDCV_SHIFT (16U) +/*! TDCV - Transmitter delay compensation value. + */ +#define CAN_PSR_TDCV(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_TDCV_SHIFT)) & CAN_PSR_TDCV_MASK) +/*! @} */ + +/*! @name TDCR - Transmitter Delay Compensator Register */ +/*! @{ */ + +#define CAN_TDCR_TDCF_MASK (0x7FU) +#define CAN_TDCR_TDCF_SHIFT (0U) +/*! TDCF - Transmitter delay compensation filter window length. + */ +#define CAN_TDCR_TDCF(x) (((uint32_t)(((uint32_t)(x)) << CAN_TDCR_TDCF_SHIFT)) & CAN_TDCR_TDCF_MASK) + +#define CAN_TDCR_TDCO_MASK (0x7F00U) +#define CAN_TDCR_TDCO_SHIFT (8U) +/*! TDCO - Transmitter delay compensation offset. + */ +#define CAN_TDCR_TDCO(x) (((uint32_t)(((uint32_t)(x)) << CAN_TDCR_TDCO_SHIFT)) & CAN_TDCR_TDCO_MASK) +/*! @} */ + +/*! @name IR - Interrupt Register */ +/*! @{ */ + +#define CAN_IR_RF0N_MASK (0x1U) +#define CAN_IR_RF0N_SHIFT (0U) +/*! RF0N - Rx FIFO 0 new message. + */ +#define CAN_IR_RF0N(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF0N_SHIFT)) & CAN_IR_RF0N_MASK) + +#define CAN_IR_RF0W_MASK (0x2U) +#define CAN_IR_RF0W_SHIFT (1U) +/*! RF0W - Rx FIFO 0 watermark reached. + */ +#define CAN_IR_RF0W(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF0W_SHIFT)) & CAN_IR_RF0W_MASK) + +#define CAN_IR_RF0F_MASK (0x4U) +#define CAN_IR_RF0F_SHIFT (2U) +/*! RF0F - Rx FIFO 0 full. + */ +#define CAN_IR_RF0F(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF0F_SHIFT)) & CAN_IR_RF0F_MASK) + +#define CAN_IR_RF0L_MASK (0x8U) +#define CAN_IR_RF0L_SHIFT (3U) +/*! RF0L - Rx FIFO 0 message lost. + */ +#define CAN_IR_RF0L(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF0L_SHIFT)) & CAN_IR_RF0L_MASK) + +#define CAN_IR_RF1N_MASK (0x10U) +#define CAN_IR_RF1N_SHIFT (4U) +/*! RF1N - Rx FIFO 1 new message. + */ +#define CAN_IR_RF1N(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF1N_SHIFT)) & CAN_IR_RF1N_MASK) + +#define CAN_IR_RF1W_MASK (0x20U) +#define CAN_IR_RF1W_SHIFT (5U) +/*! RF1W - Rx FIFO 1 watermark reached. + */ +#define CAN_IR_RF1W(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF1W_SHIFT)) & CAN_IR_RF1W_MASK) + +#define CAN_IR_RF1F_MASK (0x40U) +#define CAN_IR_RF1F_SHIFT (6U) +/*! RF1F - Rx FIFO 1 full. + */ +#define CAN_IR_RF1F(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF1F_SHIFT)) & CAN_IR_RF1F_MASK) + +#define CAN_IR_RF1L_MASK (0x80U) +#define CAN_IR_RF1L_SHIFT (7U) +/*! RF1L - Rx FIFO 1 message lost. + */ +#define CAN_IR_RF1L(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF1L_SHIFT)) & CAN_IR_RF1L_MASK) + +#define CAN_IR_HPM_MASK (0x100U) +#define CAN_IR_HPM_SHIFT (8U) +/*! HPM - High priority message. + */ +#define CAN_IR_HPM(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_HPM_SHIFT)) & CAN_IR_HPM_MASK) + +#define CAN_IR_TC_MASK (0x200U) +#define CAN_IR_TC_SHIFT (9U) +/*! TC - Transmission completed. + */ +#define CAN_IR_TC(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TC_SHIFT)) & CAN_IR_TC_MASK) + +#define CAN_IR_TCF_MASK (0x400U) +#define CAN_IR_TCF_SHIFT (10U) +/*! TCF - Transmission cancellation finished. + */ +#define CAN_IR_TCF(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TCF_SHIFT)) & CAN_IR_TCF_MASK) + +#define CAN_IR_TFE_MASK (0x800U) +#define CAN_IR_TFE_SHIFT (11U) +/*! TFE - Tx FIFO empty. + */ +#define CAN_IR_TFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TFE_SHIFT)) & CAN_IR_TFE_MASK) + +#define CAN_IR_TEFN_MASK (0x1000U) +#define CAN_IR_TEFN_SHIFT (12U) +/*! TEFN - Tx event FIFO new entry. + */ +#define CAN_IR_TEFN(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TEFN_SHIFT)) & CAN_IR_TEFN_MASK) + +#define CAN_IR_TEFW_MASK (0x2000U) +#define CAN_IR_TEFW_SHIFT (13U) +/*! TEFW - Tx event FIFO watermark reached. + */ +#define CAN_IR_TEFW(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TEFW_SHIFT)) & CAN_IR_TEFW_MASK) + +#define CAN_IR_TEFF_MASK (0x4000U) +#define CAN_IR_TEFF_SHIFT (14U) +/*! TEFF - Tx event FIFO full. + */ +#define CAN_IR_TEFF(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TEFF_SHIFT)) & CAN_IR_TEFF_MASK) + +#define CAN_IR_TEFL_MASK (0x8000U) +#define CAN_IR_TEFL_SHIFT (15U) +/*! TEFL - Tx event FIFO element lost. + */ +#define CAN_IR_TEFL(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TEFL_SHIFT)) & CAN_IR_TEFL_MASK) + +#define CAN_IR_TSW_MASK (0x10000U) +#define CAN_IR_TSW_SHIFT (16U) +/*! TSW - Timestamp wraparound. + */ +#define CAN_IR_TSW(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TSW_SHIFT)) & CAN_IR_TSW_MASK) + +#define CAN_IR_MRAF_MASK (0x20000U) +#define CAN_IR_MRAF_SHIFT (17U) +/*! MRAF - Message RAM access failure. + */ +#define CAN_IR_MRAF(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_MRAF_SHIFT)) & CAN_IR_MRAF_MASK) + +#define CAN_IR_TOO_MASK (0x40000U) +#define CAN_IR_TOO_SHIFT (18U) +/*! TOO - Timeout occurred. + */ +#define CAN_IR_TOO(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TOO_SHIFT)) & CAN_IR_TOO_MASK) + +#define CAN_IR_DRX_MASK (0x80000U) +#define CAN_IR_DRX_SHIFT (19U) +/*! DRX - Message stored in dedicated Rx buffer. + */ +#define CAN_IR_DRX(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_DRX_SHIFT)) & CAN_IR_DRX_MASK) + +#define CAN_IR_BEC_MASK (0x100000U) +#define CAN_IR_BEC_SHIFT (20U) +/*! BEC - Bit error corrected. + */ +#define CAN_IR_BEC(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_BEC_SHIFT)) & CAN_IR_BEC_MASK) + +#define CAN_IR_BEU_MASK (0x200000U) +#define CAN_IR_BEU_SHIFT (21U) +/*! BEU - Bit error uncorrected. + */ +#define CAN_IR_BEU(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_BEU_SHIFT)) & CAN_IR_BEU_MASK) + +#define CAN_IR_ELO_MASK (0x400000U) +#define CAN_IR_ELO_SHIFT (22U) +/*! ELO - Error logging overflow. + */ +#define CAN_IR_ELO(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_ELO_SHIFT)) & CAN_IR_ELO_MASK) + +#define CAN_IR_EP_MASK (0x800000U) +#define CAN_IR_EP_SHIFT (23U) +/*! EP - Error passive. + */ +#define CAN_IR_EP(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_EP_SHIFT)) & CAN_IR_EP_MASK) + +#define CAN_IR_EW_MASK (0x1000000U) +#define CAN_IR_EW_SHIFT (24U) +/*! EW - Warning status. + */ +#define CAN_IR_EW(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_EW_SHIFT)) & CAN_IR_EW_MASK) + +#define CAN_IR_BO_MASK (0x2000000U) +#define CAN_IR_BO_SHIFT (25U) +/*! BO - Bus_Off Status. + */ +#define CAN_IR_BO(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_BO_SHIFT)) & CAN_IR_BO_MASK) + +#define CAN_IR_WDI_MASK (0x4000000U) +#define CAN_IR_WDI_SHIFT (26U) +/*! WDI - Watchdog interrupt. + */ +#define CAN_IR_WDI(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_WDI_SHIFT)) & CAN_IR_WDI_MASK) + +#define CAN_IR_PEA_MASK (0x8000000U) +#define CAN_IR_PEA_SHIFT (27U) +/*! PEA - Protocol error in arbitration phase. + */ +#define CAN_IR_PEA(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_PEA_SHIFT)) & CAN_IR_PEA_MASK) + +#define CAN_IR_PED_MASK (0x10000000U) +#define CAN_IR_PED_SHIFT (28U) +/*! PED - Protocol error in data phase. + */ +#define CAN_IR_PED(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_PED_SHIFT)) & CAN_IR_PED_MASK) + +#define CAN_IR_ARA_MASK (0x20000000U) +#define CAN_IR_ARA_SHIFT (29U) +/*! ARA - Access to reserved address. + */ +#define CAN_IR_ARA(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_ARA_SHIFT)) & CAN_IR_ARA_MASK) +/*! @} */ + +/*! @name IE - Interrupt Enable */ +/*! @{ */ + +#define CAN_IE_RF0NE_MASK (0x1U) +#define CAN_IE_RF0NE_SHIFT (0U) +/*! RF0NE - Rx FIFO 0 new message interrupt enable. + */ +#define CAN_IE_RF0NE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF0NE_SHIFT)) & CAN_IE_RF0NE_MASK) + +#define CAN_IE_RF0WE_MASK (0x2U) +#define CAN_IE_RF0WE_SHIFT (1U) +/*! RF0WE - Rx FIFO 0 watermark reached interrupt enable. + */ +#define CAN_IE_RF0WE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF0WE_SHIFT)) & CAN_IE_RF0WE_MASK) + +#define CAN_IE_RF0FE_MASK (0x4U) +#define CAN_IE_RF0FE_SHIFT (2U) +/*! RF0FE - Rx FIFO 0 full interrupt enable. + */ +#define CAN_IE_RF0FE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF0FE_SHIFT)) & CAN_IE_RF0FE_MASK) + +#define CAN_IE_RF0LE_MASK (0x8U) +#define CAN_IE_RF0LE_SHIFT (3U) +/*! RF0LE - Rx FIFO 0 message lost interrupt enable. + */ +#define CAN_IE_RF0LE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF0LE_SHIFT)) & CAN_IE_RF0LE_MASK) + +#define CAN_IE_RF1NE_MASK (0x10U) +#define CAN_IE_RF1NE_SHIFT (4U) +/*! RF1NE - Rx FIFO 1 new message interrupt enable. + */ +#define CAN_IE_RF1NE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF1NE_SHIFT)) & CAN_IE_RF1NE_MASK) + +#define CAN_IE_RF1WE_MASK (0x20U) +#define CAN_IE_RF1WE_SHIFT (5U) +/*! RF1WE - Rx FIFO 1 watermark reached interrupt enable. + */ +#define CAN_IE_RF1WE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF1WE_SHIFT)) & CAN_IE_RF1WE_MASK) + +#define CAN_IE_RF1FE_MASK (0x40U) +#define CAN_IE_RF1FE_SHIFT (6U) +/*! RF1FE - Rx FIFO 1 full interrupt enable. + */ +#define CAN_IE_RF1FE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF1FE_SHIFT)) & CAN_IE_RF1FE_MASK) + +#define CAN_IE_RF1LE_MASK (0x80U) +#define CAN_IE_RF1LE_SHIFT (7U) +/*! RF1LE - Rx FIFO 1 message lost interrupt enable. + */ +#define CAN_IE_RF1LE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF1LE_SHIFT)) & CAN_IE_RF1LE_MASK) + +#define CAN_IE_HPME_MASK (0x100U) +#define CAN_IE_HPME_SHIFT (8U) +/*! HPME - High priority message interrupt enable. + */ +#define CAN_IE_HPME(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_HPME_SHIFT)) & CAN_IE_HPME_MASK) + +#define CAN_IE_TCE_MASK (0x200U) +#define CAN_IE_TCE_SHIFT (9U) +/*! TCE - Transmission completed interrupt enable. + */ +#define CAN_IE_TCE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TCE_SHIFT)) & CAN_IE_TCE_MASK) + +#define CAN_IE_TCFE_MASK (0x400U) +#define CAN_IE_TCFE_SHIFT (10U) +/*! TCFE - Transmission cancellation finished interrupt enable. + */ +#define CAN_IE_TCFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TCFE_SHIFT)) & CAN_IE_TCFE_MASK) + +#define CAN_IE_TFEE_MASK (0x800U) +#define CAN_IE_TFEE_SHIFT (11U) +/*! TFEE - Tx FIFO empty interrupt enable. + */ +#define CAN_IE_TFEE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TFEE_SHIFT)) & CAN_IE_TFEE_MASK) + +#define CAN_IE_TEFNE_MASK (0x1000U) +#define CAN_IE_TEFNE_SHIFT (12U) +/*! TEFNE - Tx event FIFO new entry interrupt enable. + */ +#define CAN_IE_TEFNE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TEFNE_SHIFT)) & CAN_IE_TEFNE_MASK) + +#define CAN_IE_TEFWE_MASK (0x2000U) +#define CAN_IE_TEFWE_SHIFT (13U) +/*! TEFWE - Tx event FIFO watermark reached interrupt enable. + */ +#define CAN_IE_TEFWE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TEFWE_SHIFT)) & CAN_IE_TEFWE_MASK) + +#define CAN_IE_TEFFE_MASK (0x4000U) +#define CAN_IE_TEFFE_SHIFT (14U) +/*! TEFFE - Tx event FIFO full interrupt enable. + */ +#define CAN_IE_TEFFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TEFFE_SHIFT)) & CAN_IE_TEFFE_MASK) + +#define CAN_IE_TEFLE_MASK (0x8000U) +#define CAN_IE_TEFLE_SHIFT (15U) +/*! TEFLE - Tx event FIFO element lost interrupt enable. + */ +#define CAN_IE_TEFLE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TEFLE_SHIFT)) & CAN_IE_TEFLE_MASK) + +#define CAN_IE_TSWE_MASK (0x10000U) +#define CAN_IE_TSWE_SHIFT (16U) +/*! TSWE - Timestamp wraparound interrupt enable. + */ +#define CAN_IE_TSWE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TSWE_SHIFT)) & CAN_IE_TSWE_MASK) + +#define CAN_IE_MRAFE_MASK (0x20000U) +#define CAN_IE_MRAFE_SHIFT (17U) +/*! MRAFE - Message RAM access failure interrupt enable. + */ +#define CAN_IE_MRAFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_MRAFE_SHIFT)) & CAN_IE_MRAFE_MASK) + +#define CAN_IE_TOOE_MASK (0x40000U) +#define CAN_IE_TOOE_SHIFT (18U) +/*! TOOE - Timeout occurred interrupt enable. + */ +#define CAN_IE_TOOE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TOOE_SHIFT)) & CAN_IE_TOOE_MASK) + +#define CAN_IE_DRXE_MASK (0x80000U) +#define CAN_IE_DRXE_SHIFT (19U) +/*! DRXE - Message stored in dedicated Rx buffer interrupt enable. + */ +#define CAN_IE_DRXE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_DRXE_SHIFT)) & CAN_IE_DRXE_MASK) + +#define CAN_IE_BECE_MASK (0x100000U) +#define CAN_IE_BECE_SHIFT (20U) +/*! BECE - Bit error corrected interrupt enable. + */ +#define CAN_IE_BECE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_BECE_SHIFT)) & CAN_IE_BECE_MASK) + +#define CAN_IE_BEUE_MASK (0x200000U) +#define CAN_IE_BEUE_SHIFT (21U) +/*! BEUE - Bit error uncorrected interrupt enable. + */ +#define CAN_IE_BEUE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_BEUE_SHIFT)) & CAN_IE_BEUE_MASK) + +#define CAN_IE_ELOE_MASK (0x400000U) +#define CAN_IE_ELOE_SHIFT (22U) +/*! ELOE - Error logging overflow interrupt enable. + */ +#define CAN_IE_ELOE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_ELOE_SHIFT)) & CAN_IE_ELOE_MASK) + +#define CAN_IE_EPE_MASK (0x800000U) +#define CAN_IE_EPE_SHIFT (23U) +/*! EPE - Error passive interrupt enable. + */ +#define CAN_IE_EPE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_EPE_SHIFT)) & CAN_IE_EPE_MASK) + +#define CAN_IE_EWE_MASK (0x1000000U) +#define CAN_IE_EWE_SHIFT (24U) +/*! EWE - Warning status interrupt enable. + */ +#define CAN_IE_EWE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_EWE_SHIFT)) & CAN_IE_EWE_MASK) + +#define CAN_IE_BOE_MASK (0x2000000U) +#define CAN_IE_BOE_SHIFT (25U) +/*! BOE - Bus_Off Status interrupt enable. + */ +#define CAN_IE_BOE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_BOE_SHIFT)) & CAN_IE_BOE_MASK) + +#define CAN_IE_WDIE_MASK (0x4000000U) +#define CAN_IE_WDIE_SHIFT (26U) +/*! WDIE - Watchdog interrupt enable. + */ +#define CAN_IE_WDIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_WDIE_SHIFT)) & CAN_IE_WDIE_MASK) + +#define CAN_IE_PEAE_MASK (0x8000000U) +#define CAN_IE_PEAE_SHIFT (27U) +/*! PEAE - Protocol error in arbitration phase interrupt enable. + */ +#define CAN_IE_PEAE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_PEAE_SHIFT)) & CAN_IE_PEAE_MASK) + +#define CAN_IE_PEDE_MASK (0x10000000U) +#define CAN_IE_PEDE_SHIFT (28U) +/*! PEDE - Protocol error in data phase interrupt enable. + */ +#define CAN_IE_PEDE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_PEDE_SHIFT)) & CAN_IE_PEDE_MASK) + +#define CAN_IE_ARAE_MASK (0x20000000U) +#define CAN_IE_ARAE_SHIFT (29U) +/*! ARAE - Access to reserved address interrupt enable. + */ +#define CAN_IE_ARAE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_ARAE_SHIFT)) & CAN_IE_ARAE_MASK) +/*! @} */ + +/*! @name ILS - Interrupt Line Select */ +/*! @{ */ + +#define CAN_ILS_RF0NL_MASK (0x1U) +#define CAN_ILS_RF0NL_SHIFT (0U) +/*! RF0NL - Rx FIFO 0 new message interrupt line. + */ +#define CAN_ILS_RF0NL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF0NL_SHIFT)) & CAN_ILS_RF0NL_MASK) + +#define CAN_ILS_RF0WL_MASK (0x2U) +#define CAN_ILS_RF0WL_SHIFT (1U) +/*! RF0WL - Rx FIFO 0 watermark reached interrupt line. + */ +#define CAN_ILS_RF0WL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF0WL_SHIFT)) & CAN_ILS_RF0WL_MASK) + +#define CAN_ILS_RF0FL_MASK (0x4U) +#define CAN_ILS_RF0FL_SHIFT (2U) +/*! RF0FL - Rx FIFO 0 full interrupt line. + */ +#define CAN_ILS_RF0FL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF0FL_SHIFT)) & CAN_ILS_RF0FL_MASK) + +#define CAN_ILS_RF0LL_MASK (0x8U) +#define CAN_ILS_RF0LL_SHIFT (3U) +/*! RF0LL - Rx FIFO 0 message lost interrupt line. + */ +#define CAN_ILS_RF0LL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF0LL_SHIFT)) & CAN_ILS_RF0LL_MASK) + +#define CAN_ILS_RF1NL_MASK (0x10U) +#define CAN_ILS_RF1NL_SHIFT (4U) +/*! RF1NL - Rx FIFO 1 new message interrupt line. + */ +#define CAN_ILS_RF1NL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF1NL_SHIFT)) & CAN_ILS_RF1NL_MASK) + +#define CAN_ILS_RF1WL_MASK (0x20U) +#define CAN_ILS_RF1WL_SHIFT (5U) +/*! RF1WL - Rx FIFO 1 watermark reached interrupt line. + */ +#define CAN_ILS_RF1WL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF1WL_SHIFT)) & CAN_ILS_RF1WL_MASK) + +#define CAN_ILS_RF1FL_MASK (0x40U) +#define CAN_ILS_RF1FL_SHIFT (6U) +/*! RF1FL - Rx FIFO 1 full interrupt line. + */ +#define CAN_ILS_RF1FL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF1FL_SHIFT)) & CAN_ILS_RF1FL_MASK) + +#define CAN_ILS_RF1LL_MASK (0x80U) +#define CAN_ILS_RF1LL_SHIFT (7U) +/*! RF1LL - Rx FIFO 1 message lost interrupt line. + */ +#define CAN_ILS_RF1LL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF1LL_SHIFT)) & CAN_ILS_RF1LL_MASK) + +#define CAN_ILS_HPML_MASK (0x100U) +#define CAN_ILS_HPML_SHIFT (8U) +/*! HPML - High priority message interrupt line. + */ +#define CAN_ILS_HPML(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_HPML_SHIFT)) & CAN_ILS_HPML_MASK) + +#define CAN_ILS_TCL_MASK (0x200U) +#define CAN_ILS_TCL_SHIFT (9U) +/*! TCL - Transmission completed interrupt line. + */ +#define CAN_ILS_TCL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TCL_SHIFT)) & CAN_ILS_TCL_MASK) + +#define CAN_ILS_TCFL_MASK (0x400U) +#define CAN_ILS_TCFL_SHIFT (10U) +/*! TCFL - Transmission cancellation finished interrupt line. + */ +#define CAN_ILS_TCFL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TCFL_SHIFT)) & CAN_ILS_TCFL_MASK) + +#define CAN_ILS_TFEL_MASK (0x800U) +#define CAN_ILS_TFEL_SHIFT (11U) +/*! TFEL - Tx FIFO empty interrupt line. + */ +#define CAN_ILS_TFEL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TFEL_SHIFT)) & CAN_ILS_TFEL_MASK) + +#define CAN_ILS_TEFNL_MASK (0x1000U) +#define CAN_ILS_TEFNL_SHIFT (12U) +/*! TEFNL - Tx event FIFO new entry interrupt line. + */ +#define CAN_ILS_TEFNL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TEFNL_SHIFT)) & CAN_ILS_TEFNL_MASK) + +#define CAN_ILS_TEFWL_MASK (0x2000U) +#define CAN_ILS_TEFWL_SHIFT (13U) +/*! TEFWL - Tx event FIFO watermark reached interrupt line. + */ +#define CAN_ILS_TEFWL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TEFWL_SHIFT)) & CAN_ILS_TEFWL_MASK) + +#define CAN_ILS_TEFFL_MASK (0x4000U) +#define CAN_ILS_TEFFL_SHIFT (14U) +/*! TEFFL - Tx event FIFO full interrupt line. + */ +#define CAN_ILS_TEFFL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TEFFL_SHIFT)) & CAN_ILS_TEFFL_MASK) + +#define CAN_ILS_TEFLL_MASK (0x8000U) +#define CAN_ILS_TEFLL_SHIFT (15U) +/*! TEFLL - Tx event FIFO element lost interrupt line. + */ +#define CAN_ILS_TEFLL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TEFLL_SHIFT)) & CAN_ILS_TEFLL_MASK) + +#define CAN_ILS_TSWL_MASK (0x10000U) +#define CAN_ILS_TSWL_SHIFT (16U) +/*! TSWL - Timestamp wraparound interrupt line. + */ +#define CAN_ILS_TSWL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TSWL_SHIFT)) & CAN_ILS_TSWL_MASK) + +#define CAN_ILS_MRAFL_MASK (0x20000U) +#define CAN_ILS_MRAFL_SHIFT (17U) +/*! MRAFL - Message RAM access failure interrupt line. + */ +#define CAN_ILS_MRAFL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_MRAFL_SHIFT)) & CAN_ILS_MRAFL_MASK) + +#define CAN_ILS_TOOL_MASK (0x40000U) +#define CAN_ILS_TOOL_SHIFT (18U) +/*! TOOL - Timeout occurred interrupt line. + */ +#define CAN_ILS_TOOL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TOOL_SHIFT)) & CAN_ILS_TOOL_MASK) + +#define CAN_ILS_DRXL_MASK (0x80000U) +#define CAN_ILS_DRXL_SHIFT (19U) +/*! DRXL - Message stored in dedicated Rx buffer interrupt line. + */ +#define CAN_ILS_DRXL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_DRXL_SHIFT)) & CAN_ILS_DRXL_MASK) + +#define CAN_ILS_BECL_MASK (0x100000U) +#define CAN_ILS_BECL_SHIFT (20U) +/*! BECL - Bit error corrected interrupt line. + */ +#define CAN_ILS_BECL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_BECL_SHIFT)) & CAN_ILS_BECL_MASK) + +#define CAN_ILS_BEUL_MASK (0x200000U) +#define CAN_ILS_BEUL_SHIFT (21U) +/*! BEUL - Bit error uncorrected interrupt line. + */ +#define CAN_ILS_BEUL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_BEUL_SHIFT)) & CAN_ILS_BEUL_MASK) + +#define CAN_ILS_ELOL_MASK (0x400000U) +#define CAN_ILS_ELOL_SHIFT (22U) +/*! ELOL - Error logging overflow interrupt line. + */ +#define CAN_ILS_ELOL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_ELOL_SHIFT)) & CAN_ILS_ELOL_MASK) + +#define CAN_ILS_EPL_MASK (0x800000U) +#define CAN_ILS_EPL_SHIFT (23U) +/*! EPL - Error passive interrupt line. + */ +#define CAN_ILS_EPL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_EPL_SHIFT)) & CAN_ILS_EPL_MASK) + +#define CAN_ILS_EWL_MASK (0x1000000U) +#define CAN_ILS_EWL_SHIFT (24U) +/*! EWL - Warning status interrupt line. + */ +#define CAN_ILS_EWL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_EWL_SHIFT)) & CAN_ILS_EWL_MASK) + +#define CAN_ILS_BOL_MASK (0x2000000U) +#define CAN_ILS_BOL_SHIFT (25U) +/*! BOL - Bus_Off Status interrupt line. + */ +#define CAN_ILS_BOL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_BOL_SHIFT)) & CAN_ILS_BOL_MASK) + +#define CAN_ILS_WDIL_MASK (0x4000000U) +#define CAN_ILS_WDIL_SHIFT (26U) +/*! WDIL - Watchdog interrupt line. + */ +#define CAN_ILS_WDIL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_WDIL_SHIFT)) & CAN_ILS_WDIL_MASK) + +#define CAN_ILS_PEAL_MASK (0x8000000U) +#define CAN_ILS_PEAL_SHIFT (27U) +/*! PEAL - Protocol error in arbitration phase interrupt line. + */ +#define CAN_ILS_PEAL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_PEAL_SHIFT)) & CAN_ILS_PEAL_MASK) + +#define CAN_ILS_PEDL_MASK (0x10000000U) +#define CAN_ILS_PEDL_SHIFT (28U) +/*! PEDL - Protocol error in data phase interrupt line. + */ +#define CAN_ILS_PEDL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_PEDL_SHIFT)) & CAN_ILS_PEDL_MASK) + +#define CAN_ILS_ARAL_MASK (0x20000000U) +#define CAN_ILS_ARAL_SHIFT (29U) +/*! ARAL - Access to reserved address interrupt line. + */ +#define CAN_ILS_ARAL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_ARAL_SHIFT)) & CAN_ILS_ARAL_MASK) +/*! @} */ + +/*! @name ILE - Interrupt Line Enable */ +/*! @{ */ + +#define CAN_ILE_EINT0_MASK (0x1U) +#define CAN_ILE_EINT0_SHIFT (0U) +/*! EINT0 - Enable interrupt line 0. + */ +#define CAN_ILE_EINT0(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILE_EINT0_SHIFT)) & CAN_ILE_EINT0_MASK) + +#define CAN_ILE_EINT1_MASK (0x2U) +#define CAN_ILE_EINT1_SHIFT (1U) +/*! EINT1 - Enable interrupt line 1. + */ +#define CAN_ILE_EINT1(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILE_EINT1_SHIFT)) & CAN_ILE_EINT1_MASK) +/*! @} */ + +/*! @name GFC - Global Filter Configuration */ +/*! @{ */ + +#define CAN_GFC_RRFE_MASK (0x1U) +#define CAN_GFC_RRFE_SHIFT (0U) +/*! RRFE - Reject remote frames extended. + */ +#define CAN_GFC_RRFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_GFC_RRFE_SHIFT)) & CAN_GFC_RRFE_MASK) + +#define CAN_GFC_RRFS_MASK (0x2U) +#define CAN_GFC_RRFS_SHIFT (1U) +/*! RRFS - Reject remote frames standard. + */ +#define CAN_GFC_RRFS(x) (((uint32_t)(((uint32_t)(x)) << CAN_GFC_RRFS_SHIFT)) & CAN_GFC_RRFS_MASK) + +#define CAN_GFC_ANFE_MASK (0xCU) +#define CAN_GFC_ANFE_SHIFT (2U) +/*! ANFE - Accept non-matching frames extended. + */ +#define CAN_GFC_ANFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_GFC_ANFE_SHIFT)) & CAN_GFC_ANFE_MASK) + +#define CAN_GFC_ANFS_MASK (0x30U) +#define CAN_GFC_ANFS_SHIFT (4U) +/*! ANFS - Accept non-matching frames standard. + */ +#define CAN_GFC_ANFS(x) (((uint32_t)(((uint32_t)(x)) << CAN_GFC_ANFS_SHIFT)) & CAN_GFC_ANFS_MASK) +/*! @} */ + +/*! @name SIDFC - Standard ID Filter Configuration */ +/*! @{ */ + +#define CAN_SIDFC_FLSSA_MASK (0xFFFCU) +#define CAN_SIDFC_FLSSA_SHIFT (2U) +/*! FLSSA - Filter list standard start address. + */ +#define CAN_SIDFC_FLSSA(x) (((uint32_t)(((uint32_t)(x)) << CAN_SIDFC_FLSSA_SHIFT)) & CAN_SIDFC_FLSSA_MASK) + +#define CAN_SIDFC_LSS_MASK (0xFF0000U) +#define CAN_SIDFC_LSS_SHIFT (16U) +/*! LSS - List size standard 0 = No standard message ID filter. + */ +#define CAN_SIDFC_LSS(x) (((uint32_t)(((uint32_t)(x)) << CAN_SIDFC_LSS_SHIFT)) & CAN_SIDFC_LSS_MASK) +/*! @} */ + +/*! @name XIDFC - Extended ID Filter Configuration */ +/*! @{ */ + +#define CAN_XIDFC_FLESA_MASK (0xFFFCU) +#define CAN_XIDFC_FLESA_SHIFT (2U) +/*! FLESA - Filter list extended start address. + */ +#define CAN_XIDFC_FLESA(x) (((uint32_t)(((uint32_t)(x)) << CAN_XIDFC_FLESA_SHIFT)) & CAN_XIDFC_FLESA_MASK) + +#define CAN_XIDFC_LSE_MASK (0xFF0000U) +#define CAN_XIDFC_LSE_SHIFT (16U) +/*! LSE - List size extended 0 = No extended message ID filter. + */ +#define CAN_XIDFC_LSE(x) (((uint32_t)(((uint32_t)(x)) << CAN_XIDFC_LSE_SHIFT)) & CAN_XIDFC_LSE_MASK) +/*! @} */ + +/*! @name XIDAM - Extended ID AND Mask */ +/*! @{ */ + +#define CAN_XIDAM_EIDM_MASK (0x1FFFFFFFU) +#define CAN_XIDAM_EIDM_SHIFT (0U) +/*! EIDM - Extended ID mask. + */ +#define CAN_XIDAM_EIDM(x) (((uint32_t)(((uint32_t)(x)) << CAN_XIDAM_EIDM_SHIFT)) & CAN_XIDAM_EIDM_MASK) +/*! @} */ + +/*! @name HPMS - High Priority Message Status */ +/*! @{ */ + +#define CAN_HPMS_BIDX_MASK (0x3FU) +#define CAN_HPMS_BIDX_SHIFT (0U) +/*! BIDX - Buffer index. + */ +#define CAN_HPMS_BIDX(x) (((uint32_t)(((uint32_t)(x)) << CAN_HPMS_BIDX_SHIFT)) & CAN_HPMS_BIDX_MASK) + +#define CAN_HPMS_MSI_MASK (0xC0U) +#define CAN_HPMS_MSI_SHIFT (6U) +/*! MSI - Message storage indicator. + */ +#define CAN_HPMS_MSI(x) (((uint32_t)(((uint32_t)(x)) << CAN_HPMS_MSI_SHIFT)) & CAN_HPMS_MSI_MASK) + +#define CAN_HPMS_FIDX_MASK (0x7F00U) +#define CAN_HPMS_FIDX_SHIFT (8U) +/*! FIDX - Filter index. + */ +#define CAN_HPMS_FIDX(x) (((uint32_t)(((uint32_t)(x)) << CAN_HPMS_FIDX_SHIFT)) & CAN_HPMS_FIDX_MASK) + +#define CAN_HPMS_FLST_MASK (0x8000U) +#define CAN_HPMS_FLST_SHIFT (15U) +/*! FLST - Filter list. + */ +#define CAN_HPMS_FLST(x) (((uint32_t)(((uint32_t)(x)) << CAN_HPMS_FLST_SHIFT)) & CAN_HPMS_FLST_MASK) +/*! @} */ + +/*! @name NDAT1 - New Data 1 */ +/*! @{ */ + +#define CAN_NDAT1_ND_MASK (0xFFFFFFFFU) +#define CAN_NDAT1_ND_SHIFT (0U) +/*! ND - New Data. + */ +#define CAN_NDAT1_ND(x) (((uint32_t)(((uint32_t)(x)) << CAN_NDAT1_ND_SHIFT)) & CAN_NDAT1_ND_MASK) +/*! @} */ + +/*! @name NDAT2 - New Data 2 */ +/*! @{ */ + +#define CAN_NDAT2_ND_MASK (0xFFFFFFFFU) +#define CAN_NDAT2_ND_SHIFT (0U) +/*! ND - New Data. + */ +#define CAN_NDAT2_ND(x) (((uint32_t)(((uint32_t)(x)) << CAN_NDAT2_ND_SHIFT)) & CAN_NDAT2_ND_MASK) +/*! @} */ + +/*! @name RXF0C - Rx FIFO 0 Configuration */ +/*! @{ */ + +#define CAN_RXF0C_F0SA_MASK (0xFFFCU) +#define CAN_RXF0C_F0SA_SHIFT (2U) +/*! F0SA - Rx FIFO 0 start address. + */ +#define CAN_RXF0C_F0SA(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0C_F0SA_SHIFT)) & CAN_RXF0C_F0SA_MASK) + +#define CAN_RXF0C_F0S_MASK (0x7F0000U) +#define CAN_RXF0C_F0S_SHIFT (16U) +/*! F0S - Rx FIFO 0 size. + */ +#define CAN_RXF0C_F0S(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0C_F0S_SHIFT)) & CAN_RXF0C_F0S_MASK) + +#define CAN_RXF0C_F0WM_MASK (0x7F000000U) +#define CAN_RXF0C_F0WM_SHIFT (24U) +/*! F0WM - Rx FIFO 0 watermark 0 = Watermark interrupt disabled. + */ +#define CAN_RXF0C_F0WM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0C_F0WM_SHIFT)) & CAN_RXF0C_F0WM_MASK) + +#define CAN_RXF0C_F0OM_MASK (0x80000000U) +#define CAN_RXF0C_F0OM_SHIFT (31U) +/*! F0OM - FIFO 0 operation mode. + */ +#define CAN_RXF0C_F0OM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0C_F0OM_SHIFT)) & CAN_RXF0C_F0OM_MASK) +/*! @} */ + +/*! @name RXF0S - Rx FIFO 0 Status */ +/*! @{ */ + +#define CAN_RXF0S_F0FL_MASK (0x7FU) +#define CAN_RXF0S_F0FL_SHIFT (0U) +/*! F0FL - Rx FIFO 0 fill level. + */ +#define CAN_RXF0S_F0FL(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0S_F0FL_SHIFT)) & CAN_RXF0S_F0FL_MASK) + +#define CAN_RXF0S_F0GI_MASK (0x3F00U) +#define CAN_RXF0S_F0GI_SHIFT (8U) +/*! F0GI - Rx FIFO 0 get index. + */ +#define CAN_RXF0S_F0GI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0S_F0GI_SHIFT)) & CAN_RXF0S_F0GI_MASK) + +#define CAN_RXF0S_F0PI_MASK (0x3F0000U) +#define CAN_RXF0S_F0PI_SHIFT (16U) +/*! F0PI - Rx FIFO 0 put index. + */ +#define CAN_RXF0S_F0PI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0S_F0PI_SHIFT)) & CAN_RXF0S_F0PI_MASK) + +#define CAN_RXF0S_F0F_MASK (0x1000000U) +#define CAN_RXF0S_F0F_SHIFT (24U) +/*! F0F - Rx FIFO 0 full. + */ +#define CAN_RXF0S_F0F(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0S_F0F_SHIFT)) & CAN_RXF0S_F0F_MASK) + +#define CAN_RXF0S_RF0L_MASK (0x2000000U) +#define CAN_RXF0S_RF0L_SHIFT (25U) +/*! RF0L - Rx FIFO 0 message lost. + */ +#define CAN_RXF0S_RF0L(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0S_RF0L_SHIFT)) & CAN_RXF0S_RF0L_MASK) +/*! @} */ + +/*! @name RXF0A - Rx FIFO 0 Acknowledge */ +/*! @{ */ + +#define CAN_RXF0A_F0AI_MASK (0x3FU) +#define CAN_RXF0A_F0AI_SHIFT (0U) +/*! F0AI - Rx FIFO 0 acknowledge index. + */ +#define CAN_RXF0A_F0AI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0A_F0AI_SHIFT)) & CAN_RXF0A_F0AI_MASK) +/*! @} */ + +/*! @name RXBC - Rx Buffer Configuration */ +/*! @{ */ + +#define CAN_RXBC_RBSA_MASK (0xFFFCU) +#define CAN_RXBC_RBSA_SHIFT (2U) +/*! RBSA - Rx buffer start address. + */ +#define CAN_RXBC_RBSA(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXBC_RBSA_SHIFT)) & CAN_RXBC_RBSA_MASK) +/*! @} */ + +/*! @name RXF1C - Rx FIFO 1 Configuration */ +/*! @{ */ + +#define CAN_RXF1C_F1SA_MASK (0xFFFCU) +#define CAN_RXF1C_F1SA_SHIFT (2U) +/*! F1SA - Rx FIFO 1 start address. + */ +#define CAN_RXF1C_F1SA(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1C_F1SA_SHIFT)) & CAN_RXF1C_F1SA_MASK) + +#define CAN_RXF1C_F1S_MASK (0x7F0000U) +#define CAN_RXF1C_F1S_SHIFT (16U) +/*! F1S - Rx FIFO 1 size 0 = No Rx FIFO 1. + */ +#define CAN_RXF1C_F1S(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1C_F1S_SHIFT)) & CAN_RXF1C_F1S_MASK) + +#define CAN_RXF1C_F1WM_MASK (0x7F000000U) +#define CAN_RXF1C_F1WM_SHIFT (24U) +/*! F1WM - Rx FIFO 1 watermark 0 = Watermark interrupt disabled. + */ +#define CAN_RXF1C_F1WM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1C_F1WM_SHIFT)) & CAN_RXF1C_F1WM_MASK) + +#define CAN_RXF1C_F1OM_MASK (0x80000000U) +#define CAN_RXF1C_F1OM_SHIFT (31U) +/*! F1OM - FIFO 1 operation mode. + */ +#define CAN_RXF1C_F1OM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1C_F1OM_SHIFT)) & CAN_RXF1C_F1OM_MASK) +/*! @} */ + +/*! @name RXF1S - Rx FIFO 1 Status */ +/*! @{ */ + +#define CAN_RXF1S_F1FL_MASK (0x7FU) +#define CAN_RXF1S_F1FL_SHIFT (0U) +/*! F1FL - Rx FIFO 1 fill level. + */ +#define CAN_RXF1S_F1FL(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1S_F1FL_SHIFT)) & CAN_RXF1S_F1FL_MASK) + +#define CAN_RXF1S_F1GI_MASK (0x3F00U) +#define CAN_RXF1S_F1GI_SHIFT (8U) +/*! F1GI - Rx FIFO 1 get index. + */ +#define CAN_RXF1S_F1GI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1S_F1GI_SHIFT)) & CAN_RXF1S_F1GI_MASK) + +#define CAN_RXF1S_F1PI_MASK (0x3F0000U) +#define CAN_RXF1S_F1PI_SHIFT (16U) +/*! F1PI - Rx FIFO 1 put index. + */ +#define CAN_RXF1S_F1PI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1S_F1PI_SHIFT)) & CAN_RXF1S_F1PI_MASK) + +#define CAN_RXF1S_F1F_MASK (0x1000000U) +#define CAN_RXF1S_F1F_SHIFT (24U) +/*! F1F - Rx FIFO 1 full. + */ +#define CAN_RXF1S_F1F(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1S_F1F_SHIFT)) & CAN_RXF1S_F1F_MASK) + +#define CAN_RXF1S_RF1L_MASK (0x2000000U) +#define CAN_RXF1S_RF1L_SHIFT (25U) +/*! RF1L - Rx FIFO 1 message lost. + */ +#define CAN_RXF1S_RF1L(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1S_RF1L_SHIFT)) & CAN_RXF1S_RF1L_MASK) +/*! @} */ + +/*! @name RXF1A - Rx FIFO 1 Acknowledge */ +/*! @{ */ + +#define CAN_RXF1A_F1AI_MASK (0x3FU) +#define CAN_RXF1A_F1AI_SHIFT (0U) +/*! F1AI - Rx FIFO 1 acknowledge index. + */ +#define CAN_RXF1A_F1AI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1A_F1AI_SHIFT)) & CAN_RXF1A_F1AI_MASK) +/*! @} */ + +/*! @name RXESC - Rx Buffer and FIFO Element Size Configuration */ +/*! @{ */ + +#define CAN_RXESC_F0DS_MASK (0x7U) +#define CAN_RXESC_F0DS_SHIFT (0U) +/*! F0DS - Rx FIFO 0 data field size. + */ +#define CAN_RXESC_F0DS(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXESC_F0DS_SHIFT)) & CAN_RXESC_F0DS_MASK) + +#define CAN_RXESC_F1DS_MASK (0x70U) +#define CAN_RXESC_F1DS_SHIFT (4U) +/*! F1DS - Rx FIFO 1 data field size. + */ +#define CAN_RXESC_F1DS(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXESC_F1DS_SHIFT)) & CAN_RXESC_F1DS_MASK) + +#define CAN_RXESC_RBDS_MASK (0x700U) +#define CAN_RXESC_RBDS_SHIFT (8U) +/*! RBDS - . + */ +#define CAN_RXESC_RBDS(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXESC_RBDS_SHIFT)) & CAN_RXESC_RBDS_MASK) +/*! @} */ + +/*! @name TXBC - Tx Buffer Configuration */ +/*! @{ */ + +#define CAN_TXBC_TBSA_MASK (0xFFFCU) +#define CAN_TXBC_TBSA_SHIFT (2U) +/*! TBSA - Tx buffers start address. + */ +#define CAN_TXBC_TBSA(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBC_TBSA_SHIFT)) & CAN_TXBC_TBSA_MASK) + +#define CAN_TXBC_NDTB_MASK (0x3F0000U) +#define CAN_TXBC_NDTB_SHIFT (16U) +/*! NDTB - Number of dedicated transmit buffers 0 = No dedicated Tx buffers. + */ +#define CAN_TXBC_NDTB(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBC_NDTB_SHIFT)) & CAN_TXBC_NDTB_MASK) + +#define CAN_TXBC_TFQS_MASK (0x3F000000U) +#define CAN_TXBC_TFQS_SHIFT (24U) +/*! TFQS - Transmit FIFO/queue size 0 = No tx FIFO/Queue. + */ +#define CAN_TXBC_TFQS(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBC_TFQS_SHIFT)) & CAN_TXBC_TFQS_MASK) + +#define CAN_TXBC_TFQM_MASK (0x40000000U) +#define CAN_TXBC_TFQM_SHIFT (30U) +/*! TFQM - Tx FIFO/queue mode. + */ +#define CAN_TXBC_TFQM(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBC_TFQM_SHIFT)) & CAN_TXBC_TFQM_MASK) +/*! @} */ + +/*! @name TXFQS - Tx FIFO/Queue Status */ +/*! @{ */ + +#define CAN_TXFQS_TFGI_MASK (0x1F00U) +#define CAN_TXFQS_TFGI_SHIFT (8U) +/*! TFGI - Tx FIFO get index. + */ +#define CAN_TXFQS_TFGI(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXFQS_TFGI_SHIFT)) & CAN_TXFQS_TFGI_MASK) + +#define CAN_TXFQS_TFQPI_MASK (0x1F0000U) +#define CAN_TXFQS_TFQPI_SHIFT (16U) +/*! TFQPI - Tx FIFO/queue put index. + */ +#define CAN_TXFQS_TFQPI(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXFQS_TFQPI_SHIFT)) & CAN_TXFQS_TFQPI_MASK) + +#define CAN_TXFQS_TFQF_MASK (0x200000U) +#define CAN_TXFQS_TFQF_SHIFT (21U) +/*! TFQF - Tx FIFO/queue full. + */ +#define CAN_TXFQS_TFQF(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXFQS_TFQF_SHIFT)) & CAN_TXFQS_TFQF_MASK) +/*! @} */ + +/*! @name TXESC - Tx Buffer Element Size Configuration */ +/*! @{ */ + +#define CAN_TXESC_TBDS_MASK (0x7U) +#define CAN_TXESC_TBDS_SHIFT (0U) +/*! TBDS - Tx buffer data field size. + */ +#define CAN_TXESC_TBDS(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXESC_TBDS_SHIFT)) & CAN_TXESC_TBDS_MASK) +/*! @} */ + +/*! @name TXBRP - Tx Buffer Request Pending */ +/*! @{ */ + +#define CAN_TXBRP_TRP_MASK (0xFFFFFFFFU) +#define CAN_TXBRP_TRP_SHIFT (0U) +/*! TRP - Transmission request pending. + */ +#define CAN_TXBRP_TRP(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBRP_TRP_SHIFT)) & CAN_TXBRP_TRP_MASK) +/*! @} */ + +/*! @name TXBAR - Tx Buffer Add Request */ +/*! @{ */ + +#define CAN_TXBAR_AR_MASK (0xFFFFFFFFU) +#define CAN_TXBAR_AR_SHIFT (0U) +/*! AR - Add request. + */ +#define CAN_TXBAR_AR(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBAR_AR_SHIFT)) & CAN_TXBAR_AR_MASK) +/*! @} */ + +/*! @name TXBCR - Tx Buffer Cancellation Request */ +/*! @{ */ + +#define CAN_TXBCR_CR_MASK (0xFFFFFFFFU) +#define CAN_TXBCR_CR_SHIFT (0U) +/*! CR - Cancellation request. + */ +#define CAN_TXBCR_CR(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBCR_CR_SHIFT)) & CAN_TXBCR_CR_MASK) +/*! @} */ + +/*! @name TXBTO - Tx Buffer Transmission Occurred */ +/*! @{ */ + +#define CAN_TXBTO_TO_MASK (0xFFFFFFFFU) +#define CAN_TXBTO_TO_SHIFT (0U) +/*! TO - Transmission occurred. + */ +#define CAN_TXBTO_TO(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBTO_TO_SHIFT)) & CAN_TXBTO_TO_MASK) +/*! @} */ + +/*! @name TXBCF - Tx Buffer Cancellation Finished */ +/*! @{ */ + +#define CAN_TXBCF_TO_MASK (0xFFFFFFFFU) +#define CAN_TXBCF_TO_SHIFT (0U) +/*! TO - Cancellation finished. + */ +#define CAN_TXBCF_TO(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBCF_TO_SHIFT)) & CAN_TXBCF_TO_MASK) +/*! @} */ + +/*! @name TXBTIE - Tx Buffer Transmission Interrupt Enable */ +/*! @{ */ + +#define CAN_TXBTIE_TIE_MASK (0xFFFFFFFFU) +#define CAN_TXBTIE_TIE_SHIFT (0U) +/*! TIE - Transmission interrupt enable. + */ +#define CAN_TXBTIE_TIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBTIE_TIE_SHIFT)) & CAN_TXBTIE_TIE_MASK) +/*! @} */ + +/*! @name TXBCIE - Tx Buffer Cancellation Finished Interrupt Enable */ +/*! @{ */ + +#define CAN_TXBCIE_CFIE_MASK (0xFFFFFFFFU) +#define CAN_TXBCIE_CFIE_SHIFT (0U) +/*! CFIE - Cancellation finished interrupt enable. + */ +#define CAN_TXBCIE_CFIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBCIE_CFIE_SHIFT)) & CAN_TXBCIE_CFIE_MASK) +/*! @} */ + +/*! @name TXEFC - Tx Event FIFO Configuration */ +/*! @{ */ + +#define CAN_TXEFC_EFSA_MASK (0xFFFCU) +#define CAN_TXEFC_EFSA_SHIFT (2U) +/*! EFSA - Event FIFO start address. + */ +#define CAN_TXEFC_EFSA(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFC_EFSA_SHIFT)) & CAN_TXEFC_EFSA_MASK) + +#define CAN_TXEFC_EFS_MASK (0x3F0000U) +#define CAN_TXEFC_EFS_SHIFT (16U) +/*! EFS - Event FIFO size 0 = Tx event FIFO disabled. + */ +#define CAN_TXEFC_EFS(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFC_EFS_SHIFT)) & CAN_TXEFC_EFS_MASK) + +#define CAN_TXEFC_EFWM_MASK (0x3F000000U) +#define CAN_TXEFC_EFWM_SHIFT (24U) +/*! EFWM - Event FIFO watermark 0 = Watermark interrupt disabled. + */ +#define CAN_TXEFC_EFWM(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFC_EFWM_SHIFT)) & CAN_TXEFC_EFWM_MASK) +/*! @} */ + +/*! @name TXEFS - Tx Event FIFO Status */ +/*! @{ */ + +#define CAN_TXEFS_EFFL_MASK (0x3FU) +#define CAN_TXEFS_EFFL_SHIFT (0U) +/*! EFFL - Event FIFO fill level. + */ +#define CAN_TXEFS_EFFL(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFS_EFFL_SHIFT)) & CAN_TXEFS_EFFL_MASK) + +#define CAN_TXEFS_EFGI_MASK (0x1F00U) +#define CAN_TXEFS_EFGI_SHIFT (8U) +/*! EFGI - Event FIFO get index. + */ +#define CAN_TXEFS_EFGI(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFS_EFGI_SHIFT)) & CAN_TXEFS_EFGI_MASK) + +#define CAN_TXEFS_EFPI_MASK (0x3F0000U) +#define CAN_TXEFS_EFPI_SHIFT (16U) +/*! EFPI - Event FIFO put index. + */ +#define CAN_TXEFS_EFPI(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFS_EFPI_SHIFT)) & CAN_TXEFS_EFPI_MASK) + +#define CAN_TXEFS_EFF_MASK (0x1000000U) +#define CAN_TXEFS_EFF_SHIFT (24U) +/*! EFF - Event FIFO full. + */ +#define CAN_TXEFS_EFF(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFS_EFF_SHIFT)) & CAN_TXEFS_EFF_MASK) + +#define CAN_TXEFS_TEFL_MASK (0x2000000U) +#define CAN_TXEFS_TEFL_SHIFT (25U) +/*! TEFL - Tx event FIFO element lost. + */ +#define CAN_TXEFS_TEFL(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFS_TEFL_SHIFT)) & CAN_TXEFS_TEFL_MASK) +/*! @} */ + +/*! @name TXEFA - Tx Event FIFO Acknowledge */ +/*! @{ */ + +#define CAN_TXEFA_EFAI_MASK (0x1FU) +#define CAN_TXEFA_EFAI_SHIFT (0U) +/*! EFAI - Event FIFO acknowledge index. + */ +#define CAN_TXEFA_EFAI(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFA_EFAI_SHIFT)) & CAN_TXEFA_EFAI_MASK) +/*! @} */ + +/*! @name MRBA - CAN Message RAM Base Address */ +/*! @{ */ + +#define CAN_MRBA_BA_MASK (0xFFFF0000U) +#define CAN_MRBA_BA_SHIFT (16U) +/*! BA - Base address for the message RAM in the chip memory map. + */ +#define CAN_MRBA_BA(x) (((uint32_t)(((uint32_t)(x)) << CAN_MRBA_BA_SHIFT)) & CAN_MRBA_BA_MASK) +/*! @} */ + +/*! @name ETSCC - External Timestamp Counter Configuration */ +/*! @{ */ + +#define CAN_ETSCC_ETCP_MASK (0x7FFU) +#define CAN_ETSCC_ETCP_SHIFT (0U) +/*! ETCP - External timestamp prescaler value. + */ +#define CAN_ETSCC_ETCP(x) (((uint32_t)(((uint32_t)(x)) << CAN_ETSCC_ETCP_SHIFT)) & CAN_ETSCC_ETCP_MASK) + +#define CAN_ETSCC_ETCE_MASK (0x80000000U) +#define CAN_ETSCC_ETCE_SHIFT (31U) +/*! ETCE - External timestamp counter enable. + */ +#define CAN_ETSCC_ETCE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ETSCC_ETCE_SHIFT)) & CAN_ETSCC_ETCE_MASK) +/*! @} */ + +/*! @name ETSCV - External Timestamp Counter Value */ +/*! @{ */ + +#define CAN_ETSCV_ETSC_MASK (0xFFFFU) +#define CAN_ETSCV_ETSC_SHIFT (0U) +/*! ETSC - External timestamp counter. + */ +#define CAN_ETSCV_ETSC(x) (((uint32_t)(((uint32_t)(x)) << CAN_ETSCV_ETSC_SHIFT)) & CAN_ETSCV_ETSC_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group CAN_Register_Masks */ + + +/* CAN - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral CAN0 base address */ + #define CAN0_BASE (0x5009D000u) + /** Peripheral CAN0 base address */ + #define CAN0_BASE_NS (0x4009D000u) + /** Peripheral CAN0 base pointer */ + #define CAN0 ((CAN_Type *)CAN0_BASE) + /** Peripheral CAN0 base pointer */ + #define CAN0_NS ((CAN_Type *)CAN0_BASE_NS) + /** Array initializer of CAN peripheral base addresses */ + #define CAN_BASE_ADDRS { CAN0_BASE } + /** Array initializer of CAN peripheral base pointers */ + #define CAN_BASE_PTRS { CAN0 } + /** Array initializer of CAN peripheral base addresses */ + #define CAN_BASE_ADDRS_NS { CAN0_BASE_NS } + /** Array initializer of CAN peripheral base pointers */ + #define CAN_BASE_PTRS_NS { CAN0_NS } +#else + /** Peripheral CAN0 base address */ + #define CAN0_BASE (0x4009D000u) + /** Peripheral CAN0 base pointer */ + #define CAN0 ((CAN_Type *)CAN0_BASE) + /** Array initializer of CAN peripheral base addresses */ + #define CAN_BASE_ADDRS { CAN0_BASE } + /** Array initializer of CAN peripheral base pointers */ + #define CAN_BASE_PTRS { CAN0 } +#endif +/** Interrupt vectors for the CAN peripheral type */ +#define CAN_IRQS { { CAN0_IRQ0_IRQn, CAN0_IRQ1_IRQn } } + +/*! + * @} + */ /* end of group CAN_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- CASPER Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CASPER_Peripheral_Access_Layer CASPER Peripheral Access Layer + * @{ + */ + +/** CASPER - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL0; /**< Contains the offsets of AB and CD in the RAM., offset: 0x0 */ + __IO uint32_t CTRL1; /**< Contains the opcode mode, iteration count, and result offset (in RAM) and also launches the accelerator. Note: with CP version: CTRL0 and CRTL1 can be written in one go with MCRR., offset: 0x4 */ + __IO uint32_t LOADER; /**< Contains an optional loader to load into CTRL0/1 in steps to perform a set of operations., offset: 0x8 */ + __IO uint32_t STATUS; /**< Indicates operational status and would contain the carry bit if used., offset: 0xC */ + __IO uint32_t INTENSET; /**< Sets interrupts, offset: 0x10 */ + __IO uint32_t INTENCLR; /**< Clears interrupts, offset: 0x14 */ + __I uint32_t INTSTAT; /**< Interrupt status bits (mask of INTENSET and STATUS), offset: 0x18 */ + uint8_t RESERVED_0[4]; + __IO uint32_t AREG; /**< A register, offset: 0x20 */ + __IO uint32_t BREG; /**< B register, offset: 0x24 */ + __IO uint32_t CREG; /**< C register, offset: 0x28 */ + __IO uint32_t DREG; /**< D register, offset: 0x2C */ + __IO uint32_t RES0; /**< Result register 0, offset: 0x30 */ + __IO uint32_t RES1; /**< Result register 1, offset: 0x34 */ + __IO uint32_t RES2; /**< Result register 2, offset: 0x38 */ + __IO uint32_t RES3; /**< Result register 3, offset: 0x3C */ + uint8_t RESERVED_1[32]; + __IO uint32_t MASK; /**< Optional mask register, offset: 0x60 */ + __IO uint32_t REMASK; /**< Optional re-mask register, offset: 0x64 */ + uint8_t RESERVED_2[24]; + __IO uint32_t LOCK; /**< Security lock register, offset: 0x80 */ +} CASPER_Type; + +/* ---------------------------------------------------------------------------- + -- CASPER Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CASPER_Register_Masks CASPER Register Masks + * @{ + */ + +/*! @name CTRL0 - Contains the offsets of AB and CD in the RAM. */ +/*! @{ */ + +#define CASPER_CTRL0_ABBPAIR_MASK (0x1U) +#define CASPER_CTRL0_ABBPAIR_SHIFT (0U) +/*! ABBPAIR - Which bank-pair the offset ABOFF is within. This must be 0 if only 2-up + * 0b0..Bank-pair 0 (1st) + * 0b1..Bank-pair 1 (2nd) + */ +#define CASPER_CTRL0_ABBPAIR(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL0_ABBPAIR_SHIFT)) & CASPER_CTRL0_ABBPAIR_MASK) + +#define CASPER_CTRL0_ABOFF_MASK (0x1FFCU) +#define CASPER_CTRL0_ABOFF_SHIFT (2U) +/*! ABOFF - Word or DWord Offset of AB values, with B at [2]=0 and A at [2]=1 as far as the code + * sees (normally will be an interleaved bank so only sequential to AHB). Word offset only allowed + * if 32 bit operation. Ideally not in the same RAM as the CD values if 4-up + */ +#define CASPER_CTRL0_ABOFF(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL0_ABOFF_SHIFT)) & CASPER_CTRL0_ABOFF_MASK) + +#define CASPER_CTRL0_CDBPAIR_MASK (0x10000U) +#define CASPER_CTRL0_CDBPAIR_SHIFT (16U) +/*! CDBPAIR - Which bank-pair the offset CDOFF is within. This must be 0 if only 2-up + * 0b0..Bank-pair 0 (1st) + * 0b1..Bank-pair 1 (2nd) + */ +#define CASPER_CTRL0_CDBPAIR(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL0_CDBPAIR_SHIFT)) & CASPER_CTRL0_CDBPAIR_MASK) + +#define CASPER_CTRL0_CDOFF_MASK (0x1FFC0000U) +#define CASPER_CTRL0_CDOFF_SHIFT (18U) +/*! CDOFF - Word or DWord Offset of CD, with D at [2]=0 and C at [2]=1 as far as the code sees + * (normally will be an interleaved bank so only sequential to AHB). Word offset only allowed if 32 + * bit operation. Ideally not in the same RAM as the AB values + */ +#define CASPER_CTRL0_CDOFF(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL0_CDOFF_SHIFT)) & CASPER_CTRL0_CDOFF_MASK) +/*! @} */ + +/*! @name CTRL1 - Contains the opcode mode, iteration count, and result offset (in RAM) and also launches the accelerator. Note: with CP version: CTRL0 and CRTL1 can be written in one go with MCRR. */ +/*! @{ */ + +#define CASPER_CTRL1_ITER_MASK (0xFFU) +#define CASPER_CTRL1_ITER_SHIFT (0U) +/*! ITER - Iteration counter. Is number_cycles - 1. write 0 means Does one cycle - does not iterate. + */ +#define CASPER_CTRL1_ITER(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL1_ITER_SHIFT)) & CASPER_CTRL1_ITER_MASK) + +#define CASPER_CTRL1_MODE_MASK (0xFF00U) +#define CASPER_CTRL1_MODE_SHIFT (8U) +/*! MODE - Operation mode to perform. write 0 means Accelerator is inactive. write others means accelerator is active. + */ +#define CASPER_CTRL1_MODE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL1_MODE_SHIFT)) & CASPER_CTRL1_MODE_MASK) + +#define CASPER_CTRL1_RESBPAIR_MASK (0x10000U) +#define CASPER_CTRL1_RESBPAIR_SHIFT (16U) +/*! RESBPAIR - Which bank-pair the offset RESOFF is within. This must be 0 if only 2-up. Ideally + * this is not the same bank as ABBPAIR (when 4-up supported) + * 0b0..Bank-pair 0 (1st) + * 0b1..Bank-pair 1 (2nd) + */ +#define CASPER_CTRL1_RESBPAIR(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL1_RESBPAIR_SHIFT)) & CASPER_CTRL1_RESBPAIR_MASK) + +#define CASPER_CTRL1_RESOFF_MASK (0x1FFC0000U) +#define CASPER_CTRL1_RESOFF_SHIFT (18U) +/*! RESOFF - Word or DWord Offset of result. Word offset only allowed if 32 bit operation. Ideally + * not in the same RAM as the AB and CD values + */ +#define CASPER_CTRL1_RESOFF(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL1_RESOFF_SHIFT)) & CASPER_CTRL1_RESOFF_MASK) + +#define CASPER_CTRL1_CSKIP_MASK (0xC0000000U) +#define CASPER_CTRL1_CSKIP_SHIFT (30U) +/*! CSKIP - Skip rules on Carry if needed. This operation will be skipped based on Carry value (from previous operation) if not 0: + * 0b00..No Skip + * 0b01..Skip if Carry is 1 + * 0b10..Skip if Carry is 0 + * 0b11..Set CTRLOFF to CDOFF and Skip + */ +#define CASPER_CTRL1_CSKIP(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL1_CSKIP_SHIFT)) & CASPER_CTRL1_CSKIP_MASK) +/*! @} */ + +/*! @name LOADER - Contains an optional loader to load into CTRL0/1 in steps to perform a set of operations. */ +/*! @{ */ + +#define CASPER_LOADER_COUNT_MASK (0xFFU) +#define CASPER_LOADER_COUNT_SHIFT (0U) +/*! COUNT - Number of control pairs to load 0 relative (so 1 means load 1). write 1 means Does one + * op - does not iterate, write N means N control pairs to load + */ +#define CASPER_LOADER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CASPER_LOADER_COUNT_SHIFT)) & CASPER_LOADER_COUNT_MASK) + +#define CASPER_LOADER_CTRLBPAIR_MASK (0x10000U) +#define CASPER_LOADER_CTRLBPAIR_SHIFT (16U) +/*! CTRLBPAIR - Which bank-pair the offset CTRLOFF is within. This must be 0 if only 2-up. Does not + * matter which bank is used as this is loaded when not performing an operation. + * 0b0..Bank-pair 0 (1st) + * 0b1..Bank-pair 1 (2nd) + */ +#define CASPER_LOADER_CTRLBPAIR(x) (((uint32_t)(((uint32_t)(x)) << CASPER_LOADER_CTRLBPAIR_SHIFT)) & CASPER_LOADER_CTRLBPAIR_MASK) + +#define CASPER_LOADER_CTRLOFF_MASK (0x1FFC0000U) +#define CASPER_LOADER_CTRLOFF_SHIFT (18U) +/*! CTRLOFF - DWord Offset of CTRL pair to load next. + */ +#define CASPER_LOADER_CTRLOFF(x) (((uint32_t)(((uint32_t)(x)) << CASPER_LOADER_CTRLOFF_SHIFT)) & CASPER_LOADER_CTRLOFF_MASK) +/*! @} */ + +/*! @name STATUS - Indicates operational status and would contain the carry bit if used. */ +/*! @{ */ + +#define CASPER_STATUS_DONE_MASK (0x1U) +#define CASPER_STATUS_DONE_SHIFT (0U) +/*! DONE - Indicates if the accelerator has finished an operation. Write 1 to clear, or write CTRL1 to clear. + * 0b0..Busy or just cleared + * 0b1..Completed last operation + */ +#define CASPER_STATUS_DONE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_STATUS_DONE_SHIFT)) & CASPER_STATUS_DONE_MASK) + +#define CASPER_STATUS_CARRY_MASK (0x10U) +#define CASPER_STATUS_CARRY_SHIFT (4U) +/*! CARRY - Last carry value if operation produced a carry bit + * 0b0..Carry was 0 or no carry + * 0b1..Carry was 1 + */ +#define CASPER_STATUS_CARRY(x) (((uint32_t)(((uint32_t)(x)) << CASPER_STATUS_CARRY_SHIFT)) & CASPER_STATUS_CARRY_MASK) + +#define CASPER_STATUS_BUSY_MASK (0x20U) +#define CASPER_STATUS_BUSY_SHIFT (5U) +/*! BUSY - Indicates if the accelerator is busy performing an operation + * 0b0..Not busy - is idle + * 0b1..Is busy + */ +#define CASPER_STATUS_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CASPER_STATUS_BUSY_SHIFT)) & CASPER_STATUS_BUSY_MASK) +/*! @} */ + +/*! @name INTENSET - Sets interrupts */ +/*! @{ */ + +#define CASPER_INTENSET_DONE_MASK (0x1U) +#define CASPER_INTENSET_DONE_SHIFT (0U) +/*! DONE - Set if the accelerator should interrupt when done. + * 0b0..Do not interrupt when done + * 0b1..Interrupt when done + */ +#define CASPER_INTENSET_DONE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_INTENSET_DONE_SHIFT)) & CASPER_INTENSET_DONE_MASK) +/*! @} */ + +/*! @name INTENCLR - Clears interrupts */ +/*! @{ */ + +#define CASPER_INTENCLR_DONE_MASK (0x1U) +#define CASPER_INTENCLR_DONE_SHIFT (0U) +/*! DONE - Written to clear an interrupt set with INTENSET. + * 0b0..If written 0, ignored + * 0b1..If written 1, do not Interrupt when done + */ +#define CASPER_INTENCLR_DONE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_INTENCLR_DONE_SHIFT)) & CASPER_INTENCLR_DONE_MASK) +/*! @} */ + +/*! @name INTSTAT - Interrupt status bits (mask of INTENSET and STATUS) */ +/*! @{ */ + +#define CASPER_INTSTAT_DONE_MASK (0x1U) +#define CASPER_INTSTAT_DONE_SHIFT (0U) +/*! DONE - If set, interrupt is caused by accelerator being done. + * 0b0..Not caused by accelerator being done + * 0b1..Caused by accelerator being done + */ +#define CASPER_INTSTAT_DONE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_INTSTAT_DONE_SHIFT)) & CASPER_INTSTAT_DONE_MASK) +/*! @} */ + +/*! @name AREG - A register */ +/*! @{ */ + +#define CASPER_AREG_REG_VALUE_MASK (0xFFFFFFFFU) +#define CASPER_AREG_REG_VALUE_SHIFT (0U) +/*! REG_VALUE - Register to be fed into Multiplier. Is not normally written or read by application, + * but is available when accelerator not busy. + */ +#define CASPER_AREG_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_AREG_REG_VALUE_SHIFT)) & CASPER_AREG_REG_VALUE_MASK) +/*! @} */ + +/*! @name BREG - B register */ +/*! @{ */ + +#define CASPER_BREG_REG_VALUE_MASK (0xFFFFFFFFU) +#define CASPER_BREG_REG_VALUE_SHIFT (0U) +/*! REG_VALUE - Register to be fed into Multiplier. Is not normally written or read by application, + * but is available when accelerator not busy. + */ +#define CASPER_BREG_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_BREG_REG_VALUE_SHIFT)) & CASPER_BREG_REG_VALUE_MASK) +/*! @} */ + +/*! @name CREG - C register */ +/*! @{ */ + +#define CASPER_CREG_REG_VALUE_MASK (0xFFFFFFFFU) +#define CASPER_CREG_REG_VALUE_SHIFT (0U) +/*! REG_VALUE - Register to be fed into Multiplier. Is not normally written or read by application, + * but is available when accelerator not busy. + */ +#define CASPER_CREG_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CREG_REG_VALUE_SHIFT)) & CASPER_CREG_REG_VALUE_MASK) +/*! @} */ + +/*! @name DREG - D register */ +/*! @{ */ + +#define CASPER_DREG_REG_VALUE_MASK (0xFFFFFFFFU) +#define CASPER_DREG_REG_VALUE_SHIFT (0U) +/*! REG_VALUE - Register to be fed into Multiplier. Is not normally written or read by application, + * but is available when accelerator not busy. + */ +#define CASPER_DREG_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_DREG_REG_VALUE_SHIFT)) & CASPER_DREG_REG_VALUE_MASK) +/*! @} */ + +/*! @name RES0 - Result register 0 */ +/*! @{ */ + +#define CASPER_RES0_REG_VALUE_MASK (0xFFFFFFFFU) +#define CASPER_RES0_REG_VALUE_SHIFT (0U) +/*! REG_VALUE - Register to hold working result (from multiplier, adder/xor, etc). Is not normally + * written or read by application, but is available when accelerator not busy. + */ +#define CASPER_RES0_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_RES0_REG_VALUE_SHIFT)) & CASPER_RES0_REG_VALUE_MASK) +/*! @} */ + +/*! @name RES1 - Result register 1 */ +/*! @{ */ + +#define CASPER_RES1_REG_VALUE_MASK (0xFFFFFFFFU) +#define CASPER_RES1_REG_VALUE_SHIFT (0U) +/*! REG_VALUE - Register to hold working result (from multiplier, adder/xor, etc). Is not normally + * written or read by application, but is available when accelerator not busy. + */ +#define CASPER_RES1_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_RES1_REG_VALUE_SHIFT)) & CASPER_RES1_REG_VALUE_MASK) +/*! @} */ + +/*! @name RES2 - Result register 2 */ +/*! @{ */ + +#define CASPER_RES2_REG_VALUE_MASK (0xFFFFFFFFU) +#define CASPER_RES2_REG_VALUE_SHIFT (0U) +/*! REG_VALUE - Register to hold working result (from multiplier, adder/xor, etc). Is not normally + * written or read by application, but is available when accelerator not busy. + */ +#define CASPER_RES2_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_RES2_REG_VALUE_SHIFT)) & CASPER_RES2_REG_VALUE_MASK) +/*! @} */ + +/*! @name RES3 - Result register 3 */ +/*! @{ */ + +#define CASPER_RES3_REG_VALUE_MASK (0xFFFFFFFFU) +#define CASPER_RES3_REG_VALUE_SHIFT (0U) +/*! REG_VALUE - Register to hold working result (from multiplier, adder/xor, etc). Is not normally + * written or read by application, but is available when accelerator not busy. + */ +#define CASPER_RES3_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_RES3_REG_VALUE_SHIFT)) & CASPER_RES3_REG_VALUE_MASK) +/*! @} */ + +/*! @name MASK - Optional mask register */ +/*! @{ */ + +#define CASPER_MASK_MASK_MASK (0xFFFFFFFFU) +#define CASPER_MASK_MASK_SHIFT (0U) +/*! MASK - Mask to apply as side channel countermeasure. 0: No mask to be used. N: Mask to XOR onto values + */ +#define CASPER_MASK_MASK(x) (((uint32_t)(((uint32_t)(x)) << CASPER_MASK_MASK_SHIFT)) & CASPER_MASK_MASK_MASK) +/*! @} */ + +/*! @name REMASK - Optional re-mask register */ +/*! @{ */ + +#define CASPER_REMASK_MASK_MASK (0xFFFFFFFFU) +#define CASPER_REMASK_MASK_SHIFT (0U) +/*! MASK - Mask to apply as side channel countermeasure. 0: No mask to be used. N: Mask to XOR onto values + */ +#define CASPER_REMASK_MASK(x) (((uint32_t)(((uint32_t)(x)) << CASPER_REMASK_MASK_SHIFT)) & CASPER_REMASK_MASK_MASK) +/*! @} */ + +/*! @name LOCK - Security lock register */ +/*! @{ */ + +#define CASPER_LOCK_LOCK_MASK (0x1U) +#define CASPER_LOCK_LOCK_SHIFT (0U) +/*! LOCK - Reads back with security level locked to, or 0. Writes as 0 to unlock, 1 to lock. + * 0b0..unlock + * 0b1..Lock to current security level + */ +#define CASPER_LOCK_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CASPER_LOCK_LOCK_SHIFT)) & CASPER_LOCK_LOCK_MASK) + +#define CASPER_LOCK_KEY_MASK (0x1FFF0U) +#define CASPER_LOCK_KEY_SHIFT (4U) +/*! KEY - Must be written as 0x73D to change the register. + * 0b0011100111101..If set during write, will allow lock or unlock + */ +#define CASPER_LOCK_KEY(x) (((uint32_t)(((uint32_t)(x)) << CASPER_LOCK_KEY_SHIFT)) & CASPER_LOCK_KEY_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group CASPER_Register_Masks */ + + +/* CASPER - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral CASPER base address */ + #define CASPER_BASE (0x500A5000u) + /** Peripheral CASPER base address */ + #define CASPER_BASE_NS (0x400A5000u) + /** Peripheral CASPER base pointer */ + #define CASPER ((CASPER_Type *)CASPER_BASE) + /** Peripheral CASPER base pointer */ + #define CASPER_NS ((CASPER_Type *)CASPER_BASE_NS) + /** Array initializer of CASPER peripheral base addresses */ + #define CASPER_BASE_ADDRS { CASPER_BASE } + /** Array initializer of CASPER peripheral base pointers */ + #define CASPER_BASE_PTRS { CASPER } + /** Array initializer of CASPER peripheral base addresses */ + #define CASPER_BASE_ADDRS_NS { CASPER_BASE_NS } + /** Array initializer of CASPER peripheral base pointers */ + #define CASPER_BASE_PTRS_NS { CASPER_NS } +#else + /** Peripheral CASPER base address */ + #define CASPER_BASE (0x400A5000u) + /** Peripheral CASPER base pointer */ + #define CASPER ((CASPER_Type *)CASPER_BASE) + /** Array initializer of CASPER peripheral base addresses */ + #define CASPER_BASE_ADDRS { CASPER_BASE } + /** Array initializer of CASPER peripheral base pointers */ + #define CASPER_BASE_PTRS { CASPER } +#endif +/** Interrupt vectors for the CASPER peripheral type */ +#define CASPER_IRQS { CASER_IRQn } + +/*! + * @} + */ /* end of group CASPER_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- CDOG Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CDOG_Peripheral_Access_Layer CDOG Peripheral Access Layer + * @{ + */ + +/** CDOG - Register Layout Typedef */ +typedef struct { + __IO uint32_t CONTROL; /**< The control fields, which constitute CONTROL, control all controllable attributes of the module, including those of CONTROL itself., offset: 0x0 */ + __IO uint32_t RELOAD; /**< Instruction timer reload, offset: 0x4 */ + __IO uint32_t INSTRUCTION_TIMER; /**< The INSTRUCTION TIMER itself, offset: 0x8 */ + __IO uint32_t SECURE_COUNTER; /**< Also known as SEC_CNT, offset: 0xC */ + __I uint32_t STATUS; /**< Status register (1 of 2), offset: 0x10 */ + __I uint32_t STATUS2; /**< STATUS register (2 of 2), offset: 0x14 */ + __IO uint32_t FLAGS; /**< Hardware flags, offset: 0x18 */ + __IO uint32_t PERSISTENT; /**< Persistent (Ad. Hoc., quasi-NV) data storage, offset: 0x1C */ + __O uint32_t START; /**< Write address for issuing the START command., offset: 0x20 */ + __O uint32_t STOP; /**< Write address for issuing the STOP command., offset: 0x24 */ + __O uint32_t RESTART; /**< Write address for issuing the RESTART command., offset: 0x28 */ + __O uint32_t ADD; /**< Write address for issuing the ADD command., offset: 0x2C */ + __O uint32_t ADD1; /**< Write address for issuing the ADD1 command., offset: 0x30 */ + __O uint32_t ADD16; /**< Write address for issuing the ADD16 command., offset: 0x34 */ + __O uint32_t ADD256; /**< Write address for issuing the ADD16 command., offset: 0x38 */ + __O uint32_t SUB; /**< Write address for issuing the SUB command., offset: 0x3C */ + __O uint32_t SUB1; /**< Write address for issuing the SUB1 command., offset: 0x40 */ + __O uint32_t SUB16; /**< Write address for issuing the SUB16 command., offset: 0x44 */ + __O uint32_t SUB256; /**< Write address for issuing the SUB256 command., offset: 0x48 */ +} CDOG_Type; + +/* ---------------------------------------------------------------------------- + -- CDOG Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CDOG_Register_Masks CDOG Register Masks + * @{ + */ + +/*! @name CONTROL - The control fields, which constitute CONTROL, control all controllable attributes of the module, including those of CONTROL itself. */ +/*! @{ */ + +#define CDOG_CONTROL_LOCK_CTRL_MASK (0x3U) +#define CDOG_CONTROL_LOCK_CTRL_SHIFT (0U) +/*! LOCK_CTRL - Lock control field + */ +#define CDOG_CONTROL_LOCK_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_LOCK_CTRL_SHIFT)) & CDOG_CONTROL_LOCK_CTRL_MASK) + +#define CDOG_CONTROL_TIMEOUT_CTRL_MASK (0x1CU) +#define CDOG_CONTROL_TIMEOUT_CTRL_SHIFT (2U) +/*! TIMEOUT_CTRL - TIMEOUT control + */ +#define CDOG_CONTROL_TIMEOUT_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_TIMEOUT_CTRL_SHIFT)) & CDOG_CONTROL_TIMEOUT_CTRL_MASK) + +#define CDOG_CONTROL_MISCOMPARE_CTRL_MASK (0xE0U) +#define CDOG_CONTROL_MISCOMPARE_CTRL_SHIFT (5U) +/*! MISCOMPARE_CTRL - MISCOMPARE control field + */ +#define CDOG_CONTROL_MISCOMPARE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_MISCOMPARE_CTRL_SHIFT)) & CDOG_CONTROL_MISCOMPARE_CTRL_MASK) + +#define CDOG_CONTROL_SEQUENCE_CTRL_MASK (0x700U) +#define CDOG_CONTROL_SEQUENCE_CTRL_SHIFT (8U) +/*! SEQUENCE_CTRL - SEQUENCE control field + */ +#define CDOG_CONTROL_SEQUENCE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_SEQUENCE_CTRL_SHIFT)) & CDOG_CONTROL_SEQUENCE_CTRL_MASK) + +#define CDOG_CONTROL_CONTROL_CTRL_MASK (0x3800U) +#define CDOG_CONTROL_CONTROL_CTRL_SHIFT (11U) +/*! CONTROL_CTRL - CONTROL control field + */ +#define CDOG_CONTROL_CONTROL_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_CONTROL_CTRL_SHIFT)) & CDOG_CONTROL_CONTROL_CTRL_MASK) + +#define CDOG_CONTROL_STATE_CTRL_MASK (0x1C000U) +#define CDOG_CONTROL_STATE_CTRL_SHIFT (14U) +/*! STATE_CTRL - STATE control field + */ +#define CDOG_CONTROL_STATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_STATE_CTRL_SHIFT)) & CDOG_CONTROL_STATE_CTRL_MASK) + +#define CDOG_CONTROL_ADDRESS_CTRL_MASK (0xE0000U) +#define CDOG_CONTROL_ADDRESS_CTRL_SHIFT (17U) +/*! ADDRESS_CTRL - ADDRESS control field + */ +#define CDOG_CONTROL_ADDRESS_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_ADDRESS_CTRL_SHIFT)) & CDOG_CONTROL_ADDRESS_CTRL_MASK) + +#define CDOG_CONTROL_Un_Imps_MASK (0xFF00000U) +#define CDOG_CONTROL_Un_Imps_SHIFT (20U) +/*! Un_Imps - The un-imps are un-IMPs! + */ +#define CDOG_CONTROL_Un_Imps(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_Un_Imps_SHIFT)) & CDOG_CONTROL_Un_Imps_MASK) + +#define CDOG_CONTROL_IRQ_PAUSE_MASK (0x30000000U) +#define CDOG_CONTROL_IRQ_PAUSE_SHIFT (28U) +/*! IRQ_PAUSE - IRQ pause control field + */ +#define CDOG_CONTROL_IRQ_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_IRQ_PAUSE_SHIFT)) & CDOG_CONTROL_IRQ_PAUSE_MASK) + +#define CDOG_CONTROL_DEBUG_HALT_CTRL_MASK (0xC0000000U) +#define CDOG_CONTROL_DEBUG_HALT_CTRL_SHIFT (30U) +/*! DEBUG_HALT_CTRL - DEBUG_HALT control field + */ +#define CDOG_CONTROL_DEBUG_HALT_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_DEBUG_HALT_CTRL_SHIFT)) & CDOG_CONTROL_DEBUG_HALT_CTRL_MASK) +/*! @} */ + +/*! @name RELOAD - Instruction timer reload */ +/*! @{ */ + +#define CDOG_RELOAD_RLOAD_MASK (0xFFFFFFFFU) +#define CDOG_RELOAD_RLOAD_SHIFT (0U) +/*! RLOAD - Inst. Timer reload value + */ +#define CDOG_RELOAD_RLOAD(x) (((uint32_t)(((uint32_t)(x)) << CDOG_RELOAD_RLOAD_SHIFT)) & CDOG_RELOAD_RLOAD_MASK) +/*! @} */ + +/*! @name INSTRUCTION_TIMER - The INSTRUCTION TIMER itself */ +/*! @{ */ + +#define CDOG_INSTRUCTION_TIMER_INSTIM_MASK (0xFFFFFFFFU) +#define CDOG_INSTRUCTION_TIMER_INSTIM_SHIFT (0U) +/*! INSTIM - INSTRUCTION TIMER 32-bit value + */ +#define CDOG_INSTRUCTION_TIMER_INSTIM(x) (((uint32_t)(((uint32_t)(x)) << CDOG_INSTRUCTION_TIMER_INSTIM_SHIFT)) & CDOG_INSTRUCTION_TIMER_INSTIM_MASK) +/*! @} */ + +/*! @name SECURE_COUNTER - Also known as SEC_CNT */ +/*! @{ */ + +#define CDOG_SECURE_COUNTER_SECCNT_MASK (0xFFFFFFFFU) +#define CDOG_SECURE_COUNTER_SECCNT_SHIFT (0U) +/*! SECCNT - Secure Counter + */ +#define CDOG_SECURE_COUNTER_SECCNT(x) (((uint32_t)(((uint32_t)(x)) << CDOG_SECURE_COUNTER_SECCNT_SHIFT)) & CDOG_SECURE_COUNTER_SECCNT_MASK) +/*! @} */ + +/*! @name STATUS - Status register (1 of 2) */ +/*! @{ */ + +#define CDOG_STATUS_NUMTOF_MASK (0xFFU) +#define CDOG_STATUS_NUMTOF_SHIFT (0U) +/*! NUMTOF - Number of Timeout Faults + */ +#define CDOG_STATUS_NUMTOF(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS_NUMTOF_SHIFT)) & CDOG_STATUS_NUMTOF_MASK) + +#define CDOG_STATUS_NUMMISCOMPF_MASK (0xFF00U) +#define CDOG_STATUS_NUMMISCOMPF_SHIFT (8U) +/*! NUMMISCOMPF - Number of Miscompare Faults + */ +#define CDOG_STATUS_NUMMISCOMPF(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS_NUMMISCOMPF_SHIFT)) & CDOG_STATUS_NUMMISCOMPF_MASK) + +#define CDOG_STATUS_NUMILSEQF_MASK (0xFF0000U) +#define CDOG_STATUS_NUMILSEQF_SHIFT (16U) +/*! NUMILSEQF - Number of illegal sequence faults + */ +#define CDOG_STATUS_NUMILSEQF(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS_NUMILSEQF_SHIFT)) & CDOG_STATUS_NUMILSEQF_MASK) + +#define CDOG_STATUS_CURST_MASK (0xF000000U) +#define CDOG_STATUS_CURST_SHIFT (24U) +/*! CURST - Current State + */ +#define CDOG_STATUS_CURST(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS_CURST_SHIFT)) & CDOG_STATUS_CURST_MASK) + +#define CDOG_STATUS_uN_iMps_MASK (0xF0000000U) +#define CDOG_STATUS_uN_iMps_SHIFT (28U) +/*! uN_iMps - Un implemented + */ +#define CDOG_STATUS_uN_iMps(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS_uN_iMps_SHIFT)) & CDOG_STATUS_uN_iMps_MASK) +/*! @} */ + +/*! @name STATUS2 - STATUS register (2 of 2) */ +/*! @{ */ + +#define CDOG_STATUS2_NUMCNTF_MASK (0xFFU) +#define CDOG_STATUS2_NUMCNTF_SHIFT (0U) +/*! NUMCNTF - Number (of) control faults + */ +#define CDOG_STATUS2_NUMCNTF(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS2_NUMCNTF_SHIFT)) & CDOG_STATUS2_NUMCNTF_MASK) + +#define CDOG_STATUS2_NUMILLSTF_MASK (0xFF00U) +#define CDOG_STATUS2_NUMILLSTF_SHIFT (8U) +/*! NUMILLSTF - Number (of) state faults + */ +#define CDOG_STATUS2_NUMILLSTF(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS2_NUMILLSTF_SHIFT)) & CDOG_STATUS2_NUMILLSTF_MASK) + +#define CDOG_STATUS2_NUMILLA_MASK (0xFF0000U) +#define CDOG_STATUS2_NUMILLA_SHIFT (16U) +/*! NUMILLA - Number of (illegal) address faults + */ +#define CDOG_STATUS2_NUMILLA(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS2_NUMILLA_SHIFT)) & CDOG_STATUS2_NUMILLA_MASK) + +#define CDOG_STATUS2_un_imPs_MASK (0xFF000000U) +#define CDOG_STATUS2_un_imPs_SHIFT (24U) +/*! un_imPs - Unimplemented bits, such as these here, aren't there. + */ +#define CDOG_STATUS2_un_imPs(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS2_un_imPs_SHIFT)) & CDOG_STATUS2_un_imPs_MASK) +/*! @} */ + +/*! @name FLAGS - Hardware flags */ +/*! @{ */ + +#define CDOG_FLAGS_TO_FLAG_MASK (0x1U) +#define CDOG_FLAGS_TO_FLAG_SHIFT (0U) +/*! TO_FLAG - Timeout flag + */ +#define CDOG_FLAGS_TO_FLAG(x) (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_TO_FLAG_SHIFT)) & CDOG_FLAGS_TO_FLAG_MASK) + +#define CDOG_FLAGS_MISCOM_FLAG_MASK (0x2U) +#define CDOG_FLAGS_MISCOM_FLAG_SHIFT (1U) +/*! MISCOM_FLAG - Miscompare flag + */ +#define CDOG_FLAGS_MISCOM_FLAG(x) (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_MISCOM_FLAG_SHIFT)) & CDOG_FLAGS_MISCOM_FLAG_MASK) + +#define CDOG_FLAGS_SEQ_FLAG_MASK (0x4U) +#define CDOG_FLAGS_SEQ_FLAG_SHIFT (2U) +/*! SEQ_FLAG - Sequence flag + */ +#define CDOG_FLAGS_SEQ_FLAG(x) (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_SEQ_FLAG_SHIFT)) & CDOG_FLAGS_SEQ_FLAG_MASK) + +#define CDOG_FLAGS_CNT_FLAG_MASK (0x8U) +#define CDOG_FLAGS_CNT_FLAG_SHIFT (3U) +/*! CNT_FLAG - Control (fault) flag + */ +#define CDOG_FLAGS_CNT_FLAG(x) (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_CNT_FLAG_SHIFT)) & CDOG_FLAGS_CNT_FLAG_MASK) + +#define CDOG_FLAGS_STATE_FLAG_MASK (0x10U) +#define CDOG_FLAGS_STATE_FLAG_SHIFT (4U) +/*! STATE_FLAG - State flag + */ +#define CDOG_FLAGS_STATE_FLAG(x) (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_STATE_FLAG_SHIFT)) & CDOG_FLAGS_STATE_FLAG_MASK) + +#define CDOG_FLAGS_ADDR_FLAG_MASK (0x20U) +#define CDOG_FLAGS_ADDR_FLAG_SHIFT (5U) +/*! ADDR_FLAG - Address flag + */ +#define CDOG_FLAGS_ADDR_FLAG(x) (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_ADDR_FLAG_SHIFT)) & CDOG_FLAGS_ADDR_FLAG_MASK) + +#define CDOG_FLAGS_POR_FLAG_MASK (0x10000U) +#define CDOG_FLAGS_POR_FLAG_SHIFT (16U) +/*! POR_FLAG - Power-on reset flag + */ +#define CDOG_FLAGS_POR_FLAG(x) (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_POR_FLAG_SHIFT)) & CDOG_FLAGS_POR_FLAG_MASK) +/*! @} */ + +/*! @name PERSISTENT - Persistent (Ad. Hoc., quasi-NV) data storage */ +/*! @{ */ + +#define CDOG_PERSISTENT_PERSIS_MASK (0xFFFFFFFFU) +#define CDOG_PERSISTENT_PERSIS_SHIFT (0U) +/*! PERSIS - 32 regs free for user SW to enjoy + */ +#define CDOG_PERSISTENT_PERSIS(x) (((uint32_t)(((uint32_t)(x)) << CDOG_PERSISTENT_PERSIS_SHIFT)) & CDOG_PERSISTENT_PERSIS_MASK) +/*! @} */ + +/*! @name START - Write address for issuing the START command. */ +/*! @{ */ + +#define CDOG_START_STRT_MASK (0xFFFFFFFFU) +#define CDOG_START_STRT_SHIFT (0U) +/*! STRT - Address of start command access + */ +#define CDOG_START_STRT(x) (((uint32_t)(((uint32_t)(x)) << CDOG_START_STRT_SHIFT)) & CDOG_START_STRT_MASK) +/*! @} */ + +/*! @name STOP - Write address for issuing the STOP command. */ +/*! @{ */ + +#define CDOG_STOP_STP_MASK (0xFFFFFFFFU) +#define CDOG_STOP_STP_SHIFT (0U) +/*! STP - Address of stop command access + */ +#define CDOG_STOP_STP(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STOP_STP_SHIFT)) & CDOG_STOP_STP_MASK) +/*! @} */ + +/*! @name RESTART - Write address for issuing the RESTART command. */ +/*! @{ */ + +#define CDOG_RESTART_RSTRT_MASK (0xFFFFFFFFU) +#define CDOG_RESTART_RSTRT_SHIFT (0U) +/*! RSTRT - Write address for issuing the RESTART command. + */ +#define CDOG_RESTART_RSTRT(x) (((uint32_t)(((uint32_t)(x)) << CDOG_RESTART_RSTRT_SHIFT)) & CDOG_RESTART_RSTRT_MASK) +/*! @} */ + +/*! @name ADD - Write address for issuing the ADD command. */ +/*! @{ */ + +#define CDOG_ADD_AD_MASK (0xFFFFFFFFU) +#define CDOG_ADD_AD_SHIFT (0U) +/*! AD - Address of ADD command + */ +#define CDOG_ADD_AD(x) (((uint32_t)(((uint32_t)(x)) << CDOG_ADD_AD_SHIFT)) & CDOG_ADD_AD_MASK) +/*! @} */ + +/*! @name ADD1 - Write address for issuing the ADD1 command. */ +/*! @{ */ + +#define CDOG_ADD1_AD1_MASK (0xFFFFFFFFU) +#define CDOG_ADD1_AD1_SHIFT (0U) +/*! AD1 - Address of ADD1 command. + */ +#define CDOG_ADD1_AD1(x) (((uint32_t)(((uint32_t)(x)) << CDOG_ADD1_AD1_SHIFT)) & CDOG_ADD1_AD1_MASK) +/*! @} */ + +/*! @name ADD16 - Write address for issuing the ADD16 command. */ +/*! @{ */ + +#define CDOG_ADD16_AD16_MASK (0xFFFFFFFFU) +#define CDOG_ADD16_AD16_SHIFT (0U) +/*! AD16 - Address of ADD16 + */ +#define CDOG_ADD16_AD16(x) (((uint32_t)(((uint32_t)(x)) << CDOG_ADD16_AD16_SHIFT)) & CDOG_ADD16_AD16_MASK) +/*! @} */ + +/*! @name ADD256 - Write address for issuing the ADD16 command. */ +/*! @{ */ + +#define CDOG_ADD256_AD256_MASK (0xFFFFFFFFU) +#define CDOG_ADD256_AD256_SHIFT (0U) +/*! AD256 - Address of ADD256 command + */ +#define CDOG_ADD256_AD256(x) (((uint32_t)(((uint32_t)(x)) << CDOG_ADD256_AD256_SHIFT)) & CDOG_ADD256_AD256_MASK) +/*! @} */ + +/*! @name SUB - Write address for issuing the SUB command. */ +/*! @{ */ + +#define CDOG_SUB_S0B_MASK (0xFFFFFFFFU) +#define CDOG_SUB_S0B_SHIFT (0U) +/*! S0B - Address of SUB command. + */ +#define CDOG_SUB_S0B(x) (((uint32_t)(((uint32_t)(x)) << CDOG_SUB_S0B_SHIFT)) & CDOG_SUB_S0B_MASK) +/*! @} */ + +/*! @name SUB1 - Write address for issuing the SUB1 command. */ +/*! @{ */ + +#define CDOG_SUB1_S1B_MASK (0xFFFFFFFFU) +#define CDOG_SUB1_S1B_SHIFT (0U) +/*! S1B - Address of SUB1 command. + */ +#define CDOG_SUB1_S1B(x) (((uint32_t)(((uint32_t)(x)) << CDOG_SUB1_S1B_SHIFT)) & CDOG_SUB1_S1B_MASK) +/*! @} */ + +/*! @name SUB16 - Write address for issuing the SUB16 command. */ +/*! @{ */ + +#define CDOG_SUB16_SB16_MASK (0xFFFFFFFFU) +#define CDOG_SUB16_SB16_SHIFT (0U) +/*! SB16 - Address of SUB16 command. + */ +#define CDOG_SUB16_SB16(x) (((uint32_t)(((uint32_t)(x)) << CDOG_SUB16_SB16_SHIFT)) & CDOG_SUB16_SB16_MASK) +/*! @} */ + +/*! @name SUB256 - Write address for issuing the SUB256 command. */ +/*! @{ */ + +#define CDOG_SUB256_SB256_MASK (0xFFFFFFFFU) +#define CDOG_SUB256_SB256_SHIFT (0U) +/*! SB256 - Address of (you guessed it) SUB256 command. + */ +#define CDOG_SUB256_SB256(x) (((uint32_t)(((uint32_t)(x)) << CDOG_SUB256_SB256_SHIFT)) & CDOG_SUB256_SB256_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group CDOG_Register_Masks */ + + +/* CDOG - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral CDOG base address */ + #define CDOG_BASE (0x500A1000u) + /** Peripheral CDOG base address */ + #define CDOG_BASE_NS (0x400A1000u) + /** Peripheral CDOG base pointer */ + #define CDOG ((CDOG_Type *)CDOG_BASE) + /** Peripheral CDOG base pointer */ + #define CDOG_NS ((CDOG_Type *)CDOG_BASE_NS) + /** Array initializer of CDOG peripheral base addresses */ + #define CDOG_BASE_ADDRS { CDOG_BASE } + /** Array initializer of CDOG peripheral base pointers */ + #define CDOG_BASE_PTRS { CDOG } + /** Array initializer of CDOG peripheral base addresses */ + #define CDOG_BASE_ADDRS_NS { CDOG_BASE_NS } + /** Array initializer of CDOG peripheral base pointers */ + #define CDOG_BASE_PTRS_NS { CDOG_NS } +#else + /** Peripheral CDOG base address */ + #define CDOG_BASE (0x400A1000u) + /** Peripheral CDOG base pointer */ + #define CDOG ((CDOG_Type *)CDOG_BASE) + /** Array initializer of CDOG peripheral base addresses */ + #define CDOG_BASE_ADDRS { CDOG_BASE } + /** Array initializer of CDOG peripheral base pointers */ + #define CDOG_BASE_PTRS { CDOG } +#endif +/** Interrupt vectors for the CDOG peripheral type */ +#define CDOG_IRQS { CDOG_IRQn } + +/*! + * @} + */ /* end of group CDOG_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- CRC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer + * @{ + */ + +/** CRC - Register Layout Typedef */ +typedef struct { + __IO uint32_t MODE; /**< CRC mode register, offset: 0x0 */ + __IO uint32_t SEED; /**< CRC seed register, offset: 0x4 */ + union { /* offset: 0x8 */ + __I uint32_t SUM; /**< CRC checksum register, offset: 0x8 */ + __O uint32_t WR_DATA; /**< CRC data register, offset: 0x8 */ + }; +} CRC_Type; + +/* ---------------------------------------------------------------------------- + -- CRC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CRC_Register_Masks CRC Register Masks + * @{ + */ + +/*! @name MODE - CRC mode register */ +/*! @{ */ + +#define CRC_MODE_CRC_POLY_MASK (0x3U) +#define CRC_MODE_CRC_POLY_SHIFT (0U) +/*! CRC_POLY - CRC polynomial: 1X = CRC-32 polynomial 01 = CRC-16 polynomial 00 = CRC-CCITT polynomial + */ +#define CRC_MODE_CRC_POLY(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CRC_POLY_SHIFT)) & CRC_MODE_CRC_POLY_MASK) + +#define CRC_MODE_BIT_RVS_WR_MASK (0x4U) +#define CRC_MODE_BIT_RVS_WR_SHIFT (2U) +/*! BIT_RVS_WR - Data bit order: 1 = Bit order reverse for CRC_WR_DATA (per byte) 0 = No bit order reverse for CRC_WR_DATA (per byte) + */ +#define CRC_MODE_BIT_RVS_WR(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_BIT_RVS_WR_SHIFT)) & CRC_MODE_BIT_RVS_WR_MASK) + +#define CRC_MODE_CMPL_WR_MASK (0x8U) +#define CRC_MODE_CMPL_WR_SHIFT (3U) +/*! CMPL_WR - Data complement: 1 = 1's complement for CRC_WR_DATA 0 = No 1's complement for CRC_WR_DATA + */ +#define CRC_MODE_CMPL_WR(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CMPL_WR_SHIFT)) & CRC_MODE_CMPL_WR_MASK) + +#define CRC_MODE_BIT_RVS_SUM_MASK (0x10U) +#define CRC_MODE_BIT_RVS_SUM_SHIFT (4U) +/*! BIT_RVS_SUM - CRC sum bit order: 1 = Bit order reverse for CRC_SUM 0 = No bit order reverse for CRC_SUM + */ +#define CRC_MODE_BIT_RVS_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_BIT_RVS_SUM_SHIFT)) & CRC_MODE_BIT_RVS_SUM_MASK) + +#define CRC_MODE_CMPL_SUM_MASK (0x20U) +#define CRC_MODE_CMPL_SUM_SHIFT (5U) +/*! CMPL_SUM - CRC sum complement: 1 = 1's complement for CRC_SUM 0 = No 1's complement for CRC_SUM + */ +#define CRC_MODE_CMPL_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CMPL_SUM_SHIFT)) & CRC_MODE_CMPL_SUM_MASK) +/*! @} */ + +/*! @name SEED - CRC seed register */ +/*! @{ */ + +#define CRC_SEED_CRC_SEED_MASK (0xFFFFFFFFU) +#define CRC_SEED_CRC_SEED_SHIFT (0U) +/*! CRC_SEED - A write access to this register will load CRC seed value to CRC_SUM register with + * selected bit order and 1's complement pre-processes. A write access to this register will + * overrule the CRC calculation in progresses. + */ +#define CRC_SEED_CRC_SEED(x) (((uint32_t)(((uint32_t)(x)) << CRC_SEED_CRC_SEED_SHIFT)) & CRC_SEED_CRC_SEED_MASK) +/*! @} */ + +/*! @name SUM - CRC checksum register */ +/*! @{ */ + +#define CRC_SUM_CRC_SUM_MASK (0xFFFFFFFFU) +#define CRC_SUM_CRC_SUM_SHIFT (0U) +/*! CRC_SUM - The most recent CRC sum can be read through this register with selected bit order and 1's complement post-processes. + */ +#define CRC_SUM_CRC_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_SUM_CRC_SUM_SHIFT)) & CRC_SUM_CRC_SUM_MASK) +/*! @} */ + +/*! @name WR_DATA - CRC data register */ +/*! @{ */ + +#define CRC_WR_DATA_CRC_WR_DATA_MASK (0xFFFFFFFFU) +#define CRC_WR_DATA_CRC_WR_DATA_SHIFT (0U) +/*! CRC_WR_DATA - Data written to this register will be taken to perform CRC calculation with + * selected bit order and 1's complement pre-process. Any write size 8, 16 or 32-bit are allowed and + * accept back-to-back transactions. + */ +#define CRC_WR_DATA_CRC_WR_DATA(x) (((uint32_t)(((uint32_t)(x)) << CRC_WR_DATA_CRC_WR_DATA_SHIFT)) & CRC_WR_DATA_CRC_WR_DATA_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group CRC_Register_Masks */ + + +/* CRC - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral CRC_ENGINE base address */ + #define CRC_ENGINE_BASE (0x50095000u) + /** Peripheral CRC_ENGINE base address */ + #define CRC_ENGINE_BASE_NS (0x40095000u) + /** Peripheral CRC_ENGINE base pointer */ + #define CRC_ENGINE ((CRC_Type *)CRC_ENGINE_BASE) + /** Peripheral CRC_ENGINE base pointer */ + #define CRC_ENGINE_NS ((CRC_Type *)CRC_ENGINE_BASE_NS) + /** Array initializer of CRC peripheral base addresses */ + #define CRC_BASE_ADDRS { CRC_ENGINE_BASE } + /** Array initializer of CRC peripheral base pointers */ + #define CRC_BASE_PTRS { CRC_ENGINE } + /** Array initializer of CRC peripheral base addresses */ + #define CRC_BASE_ADDRS_NS { CRC_ENGINE_BASE_NS } + /** Array initializer of CRC peripheral base pointers */ + #define CRC_BASE_PTRS_NS { CRC_ENGINE_NS } +#else + /** Peripheral CRC_ENGINE base address */ + #define CRC_ENGINE_BASE (0x40095000u) + /** Peripheral CRC_ENGINE base pointer */ + #define CRC_ENGINE ((CRC_Type *)CRC_ENGINE_BASE) + /** Array initializer of CRC peripheral base addresses */ + #define CRC_BASE_ADDRS { CRC_ENGINE_BASE } + /** Array initializer of CRC peripheral base pointers */ + #define CRC_BASE_PTRS { CRC_ENGINE } +#endif + +/*! + * @} + */ /* end of group CRC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- CTIMER Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CTIMER_Peripheral_Access_Layer CTIMER Peripheral Access Layer + * @{ + */ + +/** CTIMER - Register Layout Typedef */ +typedef struct { + __IO uint32_t IR; /**< Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending., offset: 0x0 */ + __IO uint32_t TCR; /**< Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR., offset: 0x4 */ + __IO uint32_t TC; /**< Timer Counter, offset: 0x8 */ + __IO uint32_t PR; /**< Prescale Register, offset: 0xC */ + __IO uint32_t PC; /**< Prescale Counter, offset: 0x10 */ + __IO uint32_t MCR; /**< Match Control Register, offset: 0x14 */ + __IO uint32_t MR[4]; /**< Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC., array offset: 0x18, array step: 0x4 */ + __IO uint32_t CCR; /**< Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place., offset: 0x28 */ + __I uint32_t CR[4]; /**< Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input., array offset: 0x2C, array step: 0x4 */ + __IO uint32_t EMR; /**< External Match Register. The EMR controls the match function and the external match pins., offset: 0x3C */ + uint8_t RESERVED_0[48]; + __IO uint32_t CTCR; /**< Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting., offset: 0x70 */ + __IO uint32_t PWMC; /**< PWM Control Register. This register enables PWM mode for the external match pins., offset: 0x74 */ + __IO uint32_t MSR[4]; /**< Match Shadow Register, array offset: 0x78, array step: 0x4 */ +} CTIMER_Type; + +/* ---------------------------------------------------------------------------- + -- CTIMER Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CTIMER_Register_Masks CTIMER Register Masks + * @{ + */ + +/*! @name IR - Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */ +/*! @{ */ + +#define CTIMER_IR_MR0INT_MASK (0x1U) +#define CTIMER_IR_MR0INT_SHIFT (0U) +/*! MR0INT - Interrupt flag for match channel 0. + */ +#define CTIMER_IR_MR0INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR0INT_SHIFT)) & CTIMER_IR_MR0INT_MASK) + +#define CTIMER_IR_MR1INT_MASK (0x2U) +#define CTIMER_IR_MR1INT_SHIFT (1U) +/*! MR1INT - Interrupt flag for match channel 1. + */ +#define CTIMER_IR_MR1INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR1INT_SHIFT)) & CTIMER_IR_MR1INT_MASK) + +#define CTIMER_IR_MR2INT_MASK (0x4U) +#define CTIMER_IR_MR2INT_SHIFT (2U) +/*! MR2INT - Interrupt flag for match channel 2. + */ +#define CTIMER_IR_MR2INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR2INT_SHIFT)) & CTIMER_IR_MR2INT_MASK) + +#define CTIMER_IR_MR3INT_MASK (0x8U) +#define CTIMER_IR_MR3INT_SHIFT (3U) +/*! MR3INT - Interrupt flag for match channel 3. + */ +#define CTIMER_IR_MR3INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR3INT_SHIFT)) & CTIMER_IR_MR3INT_MASK) + +#define CTIMER_IR_CR0INT_MASK (0x10U) +#define CTIMER_IR_CR0INT_SHIFT (4U) +/*! CR0INT - Interrupt flag for capture channel 0 event. + */ +#define CTIMER_IR_CR0INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR0INT_SHIFT)) & CTIMER_IR_CR0INT_MASK) + +#define CTIMER_IR_CR1INT_MASK (0x20U) +#define CTIMER_IR_CR1INT_SHIFT (5U) +/*! CR1INT - Interrupt flag for capture channel 1 event. + */ +#define CTIMER_IR_CR1INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR1INT_SHIFT)) & CTIMER_IR_CR1INT_MASK) + +#define CTIMER_IR_CR2INT_MASK (0x40U) +#define CTIMER_IR_CR2INT_SHIFT (6U) +/*! CR2INT - Interrupt flag for capture channel 2 event. + */ +#define CTIMER_IR_CR2INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR2INT_SHIFT)) & CTIMER_IR_CR2INT_MASK) + +#define CTIMER_IR_CR3INT_MASK (0x80U) +#define CTIMER_IR_CR3INT_SHIFT (7U) +/*! CR3INT - Interrupt flag for capture channel 3 event. + */ +#define CTIMER_IR_CR3INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR3INT_SHIFT)) & CTIMER_IR_CR3INT_MASK) +/*! @} */ + +/*! @name TCR - Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */ +/*! @{ */ + +#define CTIMER_TCR_CEN_MASK (0x1U) +#define CTIMER_TCR_CEN_SHIFT (0U) +/*! CEN - Counter enable. + * 0b0..Disabled.The counters are disabled. + * 0b1..Enabled. The Timer Counter and Prescale Counter are enabled. + */ +#define CTIMER_TCR_CEN(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CEN_SHIFT)) & CTIMER_TCR_CEN_MASK) + +#define CTIMER_TCR_CRST_MASK (0x2U) +#define CTIMER_TCR_CRST_SHIFT (1U) +/*! CRST - Counter reset. + * 0b0..Disabled. Do nothing. + * 0b1..Enabled. The Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of + * the APB bus clock. The counters remain reset until TCR[1] is returned to zero. + */ +#define CTIMER_TCR_CRST(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CRST_SHIFT)) & CTIMER_TCR_CRST_MASK) +/*! @} */ + +/*! @name TC - Timer Counter */ +/*! @{ */ + +#define CTIMER_TC_TCVAL_MASK (0xFFFFFFFFU) +#define CTIMER_TC_TCVAL_SHIFT (0U) +/*! TCVAL - Timer counter value. + */ +#define CTIMER_TC_TCVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TC_TCVAL_SHIFT)) & CTIMER_TC_TCVAL_MASK) +/*! @} */ + +/*! @name PR - Prescale Register */ +/*! @{ */ + +#define CTIMER_PR_PRVAL_MASK (0xFFFFFFFFU) +#define CTIMER_PR_PRVAL_SHIFT (0U) +/*! PRVAL - Prescale counter value. + */ +#define CTIMER_PR_PRVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PR_PRVAL_SHIFT)) & CTIMER_PR_PRVAL_MASK) +/*! @} */ + +/*! @name PC - Prescale Counter */ +/*! @{ */ + +#define CTIMER_PC_PCVAL_MASK (0xFFFFFFFFU) +#define CTIMER_PC_PCVAL_SHIFT (0U) +/*! PCVAL - Prescale counter value. + */ +#define CTIMER_PC_PCVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PC_PCVAL_SHIFT)) & CTIMER_PC_PCVAL_MASK) +/*! @} */ + +/*! @name MCR - Match Control Register */ +/*! @{ */ + +#define CTIMER_MCR_MR0I_MASK (0x1U) +#define CTIMER_MCR_MR0I_SHIFT (0U) +/*! MR0I - Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC. + */ +#define CTIMER_MCR_MR0I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0I_SHIFT)) & CTIMER_MCR_MR0I_MASK) + +#define CTIMER_MCR_MR0R_MASK (0x2U) +#define CTIMER_MCR_MR0R_SHIFT (1U) +/*! MR0R - Reset on MR0: the TC will be reset if MR0 matches it. + */ +#define CTIMER_MCR_MR0R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0R_SHIFT)) & CTIMER_MCR_MR0R_MASK) + +#define CTIMER_MCR_MR0S_MASK (0x4U) +#define CTIMER_MCR_MR0S_SHIFT (2U) +/*! MR0S - Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC. + */ +#define CTIMER_MCR_MR0S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0S_SHIFT)) & CTIMER_MCR_MR0S_MASK) + +#define CTIMER_MCR_MR1I_MASK (0x8U) +#define CTIMER_MCR_MR1I_SHIFT (3U) +/*! MR1I - Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC. + */ +#define CTIMER_MCR_MR1I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1I_SHIFT)) & CTIMER_MCR_MR1I_MASK) + +#define CTIMER_MCR_MR1R_MASK (0x10U) +#define CTIMER_MCR_MR1R_SHIFT (4U) +/*! MR1R - Reset on MR1: the TC will be reset if MR1 matches it. + */ +#define CTIMER_MCR_MR1R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1R_SHIFT)) & CTIMER_MCR_MR1R_MASK) + +#define CTIMER_MCR_MR1S_MASK (0x20U) +#define CTIMER_MCR_MR1S_SHIFT (5U) +/*! MR1S - Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC. + */ +#define CTIMER_MCR_MR1S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1S_SHIFT)) & CTIMER_MCR_MR1S_MASK) + +#define CTIMER_MCR_MR2I_MASK (0x40U) +#define CTIMER_MCR_MR2I_SHIFT (6U) +/*! MR2I - Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC. + */ +#define CTIMER_MCR_MR2I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2I_SHIFT)) & CTIMER_MCR_MR2I_MASK) + +#define CTIMER_MCR_MR2R_MASK (0x80U) +#define CTIMER_MCR_MR2R_SHIFT (7U) +/*! MR2R - Reset on MR2: the TC will be reset if MR2 matches it. + */ +#define CTIMER_MCR_MR2R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2R_SHIFT)) & CTIMER_MCR_MR2R_MASK) + +#define CTIMER_MCR_MR2S_MASK (0x100U) +#define CTIMER_MCR_MR2S_SHIFT (8U) +/*! MR2S - Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC. + */ +#define CTIMER_MCR_MR2S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2S_SHIFT)) & CTIMER_MCR_MR2S_MASK) + +#define CTIMER_MCR_MR3I_MASK (0x200U) +#define CTIMER_MCR_MR3I_SHIFT (9U) +/*! MR3I - Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC. + */ +#define CTIMER_MCR_MR3I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3I_SHIFT)) & CTIMER_MCR_MR3I_MASK) + +#define CTIMER_MCR_MR3R_MASK (0x400U) +#define CTIMER_MCR_MR3R_SHIFT (10U) +/*! MR3R - Reset on MR3: the TC will be reset if MR3 matches it. + */ +#define CTIMER_MCR_MR3R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3R_SHIFT)) & CTIMER_MCR_MR3R_MASK) + +#define CTIMER_MCR_MR3S_MASK (0x800U) +#define CTIMER_MCR_MR3S_SHIFT (11U) +/*! MR3S - Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC. + */ +#define CTIMER_MCR_MR3S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3S_SHIFT)) & CTIMER_MCR_MR3S_MASK) + +#define CTIMER_MCR_MR0RL_MASK (0x1000000U) +#define CTIMER_MCR_MR0RL_SHIFT (24U) +/*! MR0RL - Reload MR0 with the contents of the Match 0 Shadow Register when the TC is reset to zero + * (either via a match event or a write to bit 1 of the TCR). + */ +#define CTIMER_MCR_MR0RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0RL_SHIFT)) & CTIMER_MCR_MR0RL_MASK) + +#define CTIMER_MCR_MR1RL_MASK (0x2000000U) +#define CTIMER_MCR_MR1RL_SHIFT (25U) +/*! MR1RL - Reload MR1 with the contents of the Match 1 Shadow Register when the TC is reset to zero + * (either via a match event or a write to bit 1 of the TCR). + */ +#define CTIMER_MCR_MR1RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1RL_SHIFT)) & CTIMER_MCR_MR1RL_MASK) + +#define CTIMER_MCR_MR2RL_MASK (0x4000000U) +#define CTIMER_MCR_MR2RL_SHIFT (26U) +/*! MR2RL - Reload MR2 with the contents of the Match 2 Shadow Register when the TC is reset to zero + * (either via a match event or a write to bit 1 of the TCR). + */ +#define CTIMER_MCR_MR2RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2RL_SHIFT)) & CTIMER_MCR_MR2RL_MASK) + +#define CTIMER_MCR_MR3RL_MASK (0x8000000U) +#define CTIMER_MCR_MR3RL_SHIFT (27U) +/*! MR3RL - Reload MR3 with the contents of the Match 3 Shadow Register when the TC is reset to zero + * (either via a match event or a write to bit 1 of the TCR). + */ +#define CTIMER_MCR_MR3RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3RL_SHIFT)) & CTIMER_MCR_MR3RL_MASK) +/*! @} */ + +/*! @name MR - Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */ +/*! @{ */ + +#define CTIMER_MR_MATCH_MASK (0xFFFFFFFFU) +#define CTIMER_MR_MATCH_SHIFT (0U) +/*! MATCH - Timer counter match value. + */ +#define CTIMER_MR_MATCH(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MR_MATCH_SHIFT)) & CTIMER_MR_MATCH_MASK) +/*! @} */ + +/* The count of CTIMER_MR */ +#define CTIMER_MR_COUNT (4U) + +/*! @name CCR - Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */ +/*! @{ */ + +#define CTIMER_CCR_CAP0RE_MASK (0x1U) +#define CTIMER_CCR_CAP0RE_SHIFT (0U) +/*! CAP0RE - Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded with + * the contents of TC. 0 = disabled. 1 = enabled. + */ +#define CTIMER_CCR_CAP0RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0RE_SHIFT)) & CTIMER_CCR_CAP0RE_MASK) + +#define CTIMER_CCR_CAP0FE_MASK (0x2U) +#define CTIMER_CCR_CAP0FE_SHIFT (1U) +/*! CAP0FE - Falling edge of capture channel 0: a sequence of 1 then 0 causes CR0 to be loaded with + * the contents of TC. 0 = disabled. 1 = enabled. + */ +#define CTIMER_CCR_CAP0FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0FE_SHIFT)) & CTIMER_CCR_CAP0FE_MASK) + +#define CTIMER_CCR_CAP0I_MASK (0x4U) +#define CTIMER_CCR_CAP0I_SHIFT (2U) +/*! CAP0I - Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt. + */ +#define CTIMER_CCR_CAP0I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0I_SHIFT)) & CTIMER_CCR_CAP0I_MASK) + +#define CTIMER_CCR_CAP1RE_MASK (0x8U) +#define CTIMER_CCR_CAP1RE_SHIFT (3U) +/*! CAP1RE - Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with + * the contents of TC. 0 = disabled. 1 = enabled. + */ +#define CTIMER_CCR_CAP1RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1RE_SHIFT)) & CTIMER_CCR_CAP1RE_MASK) + +#define CTIMER_CCR_CAP1FE_MASK (0x10U) +#define CTIMER_CCR_CAP1FE_SHIFT (4U) +/*! CAP1FE - Falling edge of capture channel 1: a sequence of 1 then 0 causes CR1 to be loaded with + * the contents of TC. 0 = disabled. 1 = enabled. + */ +#define CTIMER_CCR_CAP1FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1FE_SHIFT)) & CTIMER_CCR_CAP1FE_MASK) + +#define CTIMER_CCR_CAP1I_MASK (0x20U) +#define CTIMER_CCR_CAP1I_SHIFT (5U) +/*! CAP1I - Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt. + */ +#define CTIMER_CCR_CAP1I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1I_SHIFT)) & CTIMER_CCR_CAP1I_MASK) + +#define CTIMER_CCR_CAP2RE_MASK (0x40U) +#define CTIMER_CCR_CAP2RE_SHIFT (6U) +/*! CAP2RE - Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded with + * the contents of TC. 0 = disabled. 1 = enabled. + */ +#define CTIMER_CCR_CAP2RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2RE_SHIFT)) & CTIMER_CCR_CAP2RE_MASK) + +#define CTIMER_CCR_CAP2FE_MASK (0x80U) +#define CTIMER_CCR_CAP2FE_SHIFT (7U) +/*! CAP2FE - Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with + * the contents of TC. 0 = disabled. 1 = enabled. + */ +#define CTIMER_CCR_CAP2FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2FE_SHIFT)) & CTIMER_CCR_CAP2FE_MASK) + +#define CTIMER_CCR_CAP2I_MASK (0x100U) +#define CTIMER_CCR_CAP2I_SHIFT (8U) +/*! CAP2I - Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt. + */ +#define CTIMER_CCR_CAP2I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2I_SHIFT)) & CTIMER_CCR_CAP2I_MASK) + +#define CTIMER_CCR_CAP3RE_MASK (0x200U) +#define CTIMER_CCR_CAP3RE_SHIFT (9U) +/*! CAP3RE - Rising edge of capture channel 3: a sequence of 0 then 1 causes CR3 to be loaded with + * the contents of TC. 0 = disabled. 1 = enabled. + */ +#define CTIMER_CCR_CAP3RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3RE_SHIFT)) & CTIMER_CCR_CAP3RE_MASK) + +#define CTIMER_CCR_CAP3FE_MASK (0x400U) +#define CTIMER_CCR_CAP3FE_SHIFT (10U) +/*! CAP3FE - Falling edge of capture channel 3: a sequence of 1 then 0 causes CR3 to be loaded with + * the contents of TC. 0 = disabled. 1 = enabled. + */ +#define CTIMER_CCR_CAP3FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3FE_SHIFT)) & CTIMER_CCR_CAP3FE_MASK) + +#define CTIMER_CCR_CAP3I_MASK (0x800U) +#define CTIMER_CCR_CAP3I_SHIFT (11U) +/*! CAP3I - Generate interrupt on channel 3 capture event: a CR3 load generates an interrupt. + */ +#define CTIMER_CCR_CAP3I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3I_SHIFT)) & CTIMER_CCR_CAP3I_MASK) +/*! @} */ + +/*! @name CR - Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input. */ +/*! @{ */ + +#define CTIMER_CR_CAP_MASK (0xFFFFFFFFU) +#define CTIMER_CR_CAP_SHIFT (0U) +/*! CAP - Timer counter capture value. + */ +#define CTIMER_CR_CAP(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CR_CAP_SHIFT)) & CTIMER_CR_CAP_MASK) +/*! @} */ + +/* The count of CTIMER_CR */ +#define CTIMER_CR_COUNT (4U) + +/*! @name EMR - External Match Register. The EMR controls the match function and the external match pins. */ +/*! @{ */ + +#define CTIMER_EMR_EM0_MASK (0x1U) +#define CTIMER_EMR_EM0_SHIFT (0U) +/*! EM0 - External Match 0. This bit reflects the state of output MAT0, whether or not this output + * is connected to a pin. When a match occurs between the TC and MR0, this bit can either toggle, + * go LOW, go HIGH, or do nothing, as selected by EMR[5:4]. This bit is driven to the MAT pins if + * the match function is selected via IOCON. 0 = LOW. 1 = HIGH. + */ +#define CTIMER_EMR_EM0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM0_SHIFT)) & CTIMER_EMR_EM0_MASK) + +#define CTIMER_EMR_EM1_MASK (0x2U) +#define CTIMER_EMR_EM1_SHIFT (1U) +/*! EM1 - External Match 1. This bit reflects the state of output MAT1, whether or not this output + * is connected to a pin. When a match occurs between the TC and MR1, this bit can either toggle, + * go LOW, go HIGH, or do nothing, as selected by EMR[7:6]. This bit is driven to the MAT pins if + * the match function is selected via IOCON. 0 = LOW. 1 = HIGH. + */ +#define CTIMER_EMR_EM1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM1_SHIFT)) & CTIMER_EMR_EM1_MASK) + +#define CTIMER_EMR_EM2_MASK (0x4U) +#define CTIMER_EMR_EM2_SHIFT (2U) +/*! EM2 - External Match 2. This bit reflects the state of output MAT2, whether or not this output + * is connected to a pin. When a match occurs between the TC and MR2, this bit can either toggle, + * go LOW, go HIGH, or do nothing, as selected by EMR[9:8]. This bit is driven to the MAT pins if + * the match function is selected via IOCON. 0 = LOW. 1 = HIGH. + */ +#define CTIMER_EMR_EM2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM2_SHIFT)) & CTIMER_EMR_EM2_MASK) + +#define CTIMER_EMR_EM3_MASK (0x8U) +#define CTIMER_EMR_EM3_SHIFT (3U) +/*! EM3 - External Match 3. This bit reflects the state of output MAT3, whether or not this output + * is connected to a pin. When a match occurs between the TC and MR3, this bit can either toggle, + * go LOW, go HIGH, or do nothing, as selected by MR[11:10]. This bit is driven to the MAT pins + * if the match function is selected via IOCON. 0 = LOW. 1 = HIGH. + */ +#define CTIMER_EMR_EM3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM3_SHIFT)) & CTIMER_EMR_EM3_MASK) + +#define CTIMER_EMR_EMC0_MASK (0x30U) +#define CTIMER_EMR_EMC0_SHIFT (4U) +/*! EMC0 - External Match Control 0. Determines the functionality of External Match 0. + * 0b00..Do Nothing. + * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT0 pin is LOW if pinned out). + * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT0 pin is HIGH if pinned out). + * 0b11..Toggle. Toggle the corresponding External Match bit/output. + */ +#define CTIMER_EMR_EMC0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC0_SHIFT)) & CTIMER_EMR_EMC0_MASK) + +#define CTIMER_EMR_EMC1_MASK (0xC0U) +#define CTIMER_EMR_EMC1_SHIFT (6U) +/*! EMC1 - External Match Control 1. Determines the functionality of External Match 1. + * 0b00..Do Nothing. + * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT1 pin is LOW if pinned out). + * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT1 pin is HIGH if pinned out). + * 0b11..Toggle. Toggle the corresponding External Match bit/output. + */ +#define CTIMER_EMR_EMC1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC1_SHIFT)) & CTIMER_EMR_EMC1_MASK) + +#define CTIMER_EMR_EMC2_MASK (0x300U) +#define CTIMER_EMR_EMC2_SHIFT (8U) +/*! EMC2 - External Match Control 2. Determines the functionality of External Match 2. + * 0b00..Do Nothing. + * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT2 pin is LOW if pinned out). + * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT2 pin is HIGH if pinned out). + * 0b11..Toggle. Toggle the corresponding External Match bit/output. + */ +#define CTIMER_EMR_EMC2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC2_SHIFT)) & CTIMER_EMR_EMC2_MASK) + +#define CTIMER_EMR_EMC3_MASK (0xC00U) +#define CTIMER_EMR_EMC3_SHIFT (10U) +/*! EMC3 - External Match Control 3. Determines the functionality of External Match 3. + * 0b00..Do Nothing. + * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT3 pin is LOW if pinned out). + * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT3 pin is HIGH if pinned out). + * 0b11..Toggle. Toggle the corresponding External Match bit/output. + */ +#define CTIMER_EMR_EMC3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC3_SHIFT)) & CTIMER_EMR_EMC3_MASK) +/*! @} */ + +/*! @name CTCR - Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */ +/*! @{ */ + +#define CTIMER_CTCR_CTMODE_MASK (0x3U) +#define CTIMER_CTCR_CTMODE_SHIFT (0U) +/*! CTMODE - Counter/Timer Mode This field selects which rising APB bus clock edges can increment + * Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC + * is incremented when the Prescale Counter matches the Prescale Register. + * 0b00..Timer Mode. Incremented every rising APB bus clock edge. + * 0b01..Counter Mode rising edge. TC is incremented on rising edges on the CAP input selected by bits 3:2. + * 0b10..Counter Mode falling edge. TC is incremented on falling edges on the CAP input selected by bits 3:2. + * 0b11..Counter Mode dual edge. TC is incremented on both edges on the CAP input selected by bits 3:2. + */ +#define CTIMER_CTCR_CTMODE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CTMODE_SHIFT)) & CTIMER_CTCR_CTMODE_MASK) + +#define CTIMER_CTCR_CINSEL_MASK (0xCU) +#define CTIMER_CTCR_CINSEL_SHIFT (2U) +/*! CINSEL - Count Input Select When bits 1:0 in this register are not 00, these bits select which + * CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input + * in the CTCR, the 3 bits for that input in the Capture Control Register (CCR) must be + * programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the + * same timer. + * 0b00..Channel 0. CAPn.0 for CTIMERn + * 0b01..Channel 1. CAPn.1 for CTIMERn + * 0b10..Channel 2. CAPn.2 for CTIMERn + * 0b11..Channel 3. CAPn.3 for CTIMERn + */ +#define CTIMER_CTCR_CINSEL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CINSEL_SHIFT)) & CTIMER_CTCR_CINSEL_MASK) + +#define CTIMER_CTCR_ENCC_MASK (0x10U) +#define CTIMER_CTCR_ENCC_SHIFT (4U) +/*! ENCC - Setting this bit to 1 enables clearing of the timer and the prescaler when the + * capture-edge event specified in bits 7:5 occurs. + */ +#define CTIMER_CTCR_ENCC(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_ENCC_SHIFT)) & CTIMER_CTCR_ENCC_MASK) + +#define CTIMER_CTCR_SELCC_MASK (0xE0U) +#define CTIMER_CTCR_SELCC_SHIFT (5U) +/*! SELCC - Edge select. When bit 4 is 1, these bits select which capture input edge will cause the + * timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to + * 0x3 and 0x6 to 0x7 are reserved. + * 0b000..Channel 0 Rising Edge. Rising edge of the signal on capture channel 0 clears the timer (if bit 4 is set). + * 0b001..Channel 0 Falling Edge. Falling edge of the signal on capture channel 0 clears the timer (if bit 4 is set). + * 0b010..Channel 1 Rising Edge. Rising edge of the signal on capture channel 1 clears the timer (if bit 4 is set). + * 0b011..Channel 1 Falling Edge. Falling edge of the signal on capture channel 1 clears the timer (if bit 4 is set). + * 0b100..Channel 2 Rising Edge. Rising edge of the signal on capture channel 2 clears the timer (if bit 4 is set). + * 0b101..Channel 2 Falling Edge. Falling edge of the signal on capture channel 2 clears the timer (if bit 4 is set). + */ +#define CTIMER_CTCR_SELCC(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_SELCC_SHIFT)) & CTIMER_CTCR_SELCC_MASK) +/*! @} */ + +/*! @name PWMC - PWM Control Register. This register enables PWM mode for the external match pins. */ +/*! @{ */ + +#define CTIMER_PWMC_PWMEN0_MASK (0x1U) +#define CTIMER_PWMC_PWMEN0_SHIFT (0U) +/*! PWMEN0 - PWM mode enable for channel0. + * 0b0..Match. CTIMERn_MAT0 is controlled by EM0. + * 0b1..PWM. PWM mode is enabled for CTIMERn_MAT0. + */ +#define CTIMER_PWMC_PWMEN0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN0_SHIFT)) & CTIMER_PWMC_PWMEN0_MASK) + +#define CTIMER_PWMC_PWMEN1_MASK (0x2U) +#define CTIMER_PWMC_PWMEN1_SHIFT (1U) +/*! PWMEN1 - PWM mode enable for channel1. + * 0b0..Match. CTIMERn_MAT01 is controlled by EM1. + * 0b1..PWM. PWM mode is enabled for CTIMERn_MAT1. + */ +#define CTIMER_PWMC_PWMEN1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN1_SHIFT)) & CTIMER_PWMC_PWMEN1_MASK) + +#define CTIMER_PWMC_PWMEN2_MASK (0x4U) +#define CTIMER_PWMC_PWMEN2_SHIFT (2U) +/*! PWMEN2 - PWM mode enable for channel2. + * 0b0..Match. CTIMERn_MAT2 is controlled by EM2. + * 0b1..PWM. PWM mode is enabled for CTIMERn_MAT2. + */ +#define CTIMER_PWMC_PWMEN2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN2_SHIFT)) & CTIMER_PWMC_PWMEN2_MASK) + +#define CTIMER_PWMC_PWMEN3_MASK (0x8U) +#define CTIMER_PWMC_PWMEN3_SHIFT (3U) +/*! PWMEN3 - PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle. + * 0b0..Match. CTIMERn_MAT3 is controlled by EM3. + * 0b1..PWM. PWM mode is enabled for CT132Bn_MAT3. + */ +#define CTIMER_PWMC_PWMEN3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN3_SHIFT)) & CTIMER_PWMC_PWMEN3_MASK) +/*! @} */ + +/*! @name MSR - Match Shadow Register */ +/*! @{ */ + +#define CTIMER_MSR_SHADOW_MASK (0xFFFFFFFFU) +#define CTIMER_MSR_SHADOW_SHIFT (0U) +/*! SHADOW - Timer counter match shadow value. + */ +#define CTIMER_MSR_SHADOW(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MSR_SHADOW_SHIFT)) & CTIMER_MSR_SHADOW_MASK) +/*! @} */ + +/* The count of CTIMER_MSR */ +#define CTIMER_MSR_COUNT (4U) + + +/*! + * @} + */ /* end of group CTIMER_Register_Masks */ + + +/* CTIMER - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral CTIMER0 base address */ + #define CTIMER0_BASE (0x50008000u) + /** Peripheral CTIMER0 base address */ + #define CTIMER0_BASE_NS (0x40008000u) + /** Peripheral CTIMER0 base pointer */ + #define CTIMER0 ((CTIMER_Type *)CTIMER0_BASE) + /** Peripheral CTIMER0 base pointer */ + #define CTIMER0_NS ((CTIMER_Type *)CTIMER0_BASE_NS) + /** Peripheral CTIMER1 base address */ + #define CTIMER1_BASE (0x50009000u) + /** Peripheral CTIMER1 base address */ + #define CTIMER1_BASE_NS (0x40009000u) + /** Peripheral CTIMER1 base pointer */ + #define CTIMER1 ((CTIMER_Type *)CTIMER1_BASE) + /** Peripheral CTIMER1 base pointer */ + #define CTIMER1_NS ((CTIMER_Type *)CTIMER1_BASE_NS) + /** Peripheral CTIMER2 base address */ + #define CTIMER2_BASE (0x50028000u) + /** Peripheral CTIMER2 base address */ + #define CTIMER2_BASE_NS (0x40028000u) + /** Peripheral CTIMER2 base pointer */ + #define CTIMER2 ((CTIMER_Type *)CTIMER2_BASE) + /** Peripheral CTIMER2 base pointer */ + #define CTIMER2_NS ((CTIMER_Type *)CTIMER2_BASE_NS) + /** Peripheral CTIMER3 base address */ + #define CTIMER3_BASE (0x50029000u) + /** Peripheral CTIMER3 base address */ + #define CTIMER3_BASE_NS (0x40029000u) + /** Peripheral CTIMER3 base pointer */ + #define CTIMER3 ((CTIMER_Type *)CTIMER3_BASE) + /** Peripheral CTIMER3 base pointer */ + #define CTIMER3_NS ((CTIMER_Type *)CTIMER3_BASE_NS) + /** Peripheral CTIMER4 base address */ + #define CTIMER4_BASE (0x5002A000u) + /** Peripheral CTIMER4 base address */ + #define CTIMER4_BASE_NS (0x4002A000u) + /** Peripheral CTIMER4 base pointer */ + #define CTIMER4 ((CTIMER_Type *)CTIMER4_BASE) + /** Peripheral CTIMER4 base pointer */ + #define CTIMER4_NS ((CTIMER_Type *)CTIMER4_BASE_NS) + /** Array initializer of CTIMER peripheral base addresses */ + #define CTIMER_BASE_ADDRS { CTIMER0_BASE, CTIMER1_BASE, CTIMER2_BASE, CTIMER3_BASE, CTIMER4_BASE } + /** Array initializer of CTIMER peripheral base pointers */ + #define CTIMER_BASE_PTRS { CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4 } + /** Array initializer of CTIMER peripheral base addresses */ + #define CTIMER_BASE_ADDRS_NS { CTIMER0_BASE_NS, CTIMER1_BASE_NS, CTIMER2_BASE_NS, CTIMER3_BASE_NS, CTIMER4_BASE_NS } + /** Array initializer of CTIMER peripheral base pointers */ + #define CTIMER_BASE_PTRS_NS { CTIMER0_NS, CTIMER1_NS, CTIMER2_NS, CTIMER3_NS, CTIMER4_NS } +#else + /** Peripheral CTIMER0 base address */ + #define CTIMER0_BASE (0x40008000u) + /** Peripheral CTIMER0 base pointer */ + #define CTIMER0 ((CTIMER_Type *)CTIMER0_BASE) + /** Peripheral CTIMER1 base address */ + #define CTIMER1_BASE (0x40009000u) + /** Peripheral CTIMER1 base pointer */ + #define CTIMER1 ((CTIMER_Type *)CTIMER1_BASE) + /** Peripheral CTIMER2 base address */ + #define CTIMER2_BASE (0x40028000u) + /** Peripheral CTIMER2 base pointer */ + #define CTIMER2 ((CTIMER_Type *)CTIMER2_BASE) + /** Peripheral CTIMER3 base address */ + #define CTIMER3_BASE (0x40029000u) + /** Peripheral CTIMER3 base pointer */ + #define CTIMER3 ((CTIMER_Type *)CTIMER3_BASE) + /** Peripheral CTIMER4 base address */ + #define CTIMER4_BASE (0x4002A000u) + /** Peripheral CTIMER4 base pointer */ + #define CTIMER4 ((CTIMER_Type *)CTIMER4_BASE) + /** Array initializer of CTIMER peripheral base addresses */ + #define CTIMER_BASE_ADDRS { CTIMER0_BASE, CTIMER1_BASE, CTIMER2_BASE, CTIMER3_BASE, CTIMER4_BASE } + /** Array initializer of CTIMER peripheral base pointers */ + #define CTIMER_BASE_PTRS { CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4 } +#endif +/** Interrupt vectors for the CTIMER peripheral type */ +#define CTIMER_IRQS { CTIMER0_IRQn, CTIMER1_IRQn, CTIMER2_IRQn, CTIMER3_IRQn, CTIMER4_IRQn } + +/*! + * @} + */ /* end of group CTIMER_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- DBGMAILBOX Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DBGMAILBOX_Peripheral_Access_Layer DBGMAILBOX Peripheral Access Layer + * @{ + */ + +/** DBGMAILBOX - Register Layout Typedef */ +typedef struct { + __IO uint32_t CSW; /**< CRC mode register, offset: 0x0 */ + __IO uint32_t REQUEST; /**< CRC seed register, offset: 0x4 */ + __IO uint32_t RETURN; /**< Return value from ROM., offset: 0x8 */ + uint8_t RESERVED_0[240]; + __I uint32_t ID; /**< Identification register, offset: 0xFC */ +} DBGMAILBOX_Type; + +/* ---------------------------------------------------------------------------- + -- DBGMAILBOX Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DBGMAILBOX_Register_Masks DBGMAILBOX Register Masks + * @{ + */ + +/*! @name CSW - CRC mode register */ +/*! @{ */ + +#define DBGMAILBOX_CSW_RESYNCH_REQ_MASK (0x1U) +#define DBGMAILBOX_CSW_RESYNCH_REQ_SHIFT (0U) +/*! RESYNCH_REQ - Debugger will set this bit to 1 to request a resynchronrisation + */ +#define DBGMAILBOX_CSW_RESYNCH_REQ(x) (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_RESYNCH_REQ_SHIFT)) & DBGMAILBOX_CSW_RESYNCH_REQ_MASK) + +#define DBGMAILBOX_CSW_REQ_PENDING_MASK (0x2U) +#define DBGMAILBOX_CSW_REQ_PENDING_SHIFT (1U) +/*! REQ_PENDING - Request is pending from debugger (i.e unread value in REQUEST) + */ +#define DBGMAILBOX_CSW_REQ_PENDING(x) (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_REQ_PENDING_SHIFT)) & DBGMAILBOX_CSW_REQ_PENDING_MASK) + +#define DBGMAILBOX_CSW_DBG_OR_ERR_MASK (0x4U) +#define DBGMAILBOX_CSW_DBG_OR_ERR_SHIFT (2U) +/*! DBG_OR_ERR - Debugger overrun error (previous REQUEST overwritten before being picked up by ROM) + */ +#define DBGMAILBOX_CSW_DBG_OR_ERR(x) (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_DBG_OR_ERR_SHIFT)) & DBGMAILBOX_CSW_DBG_OR_ERR_MASK) + +#define DBGMAILBOX_CSW_AHB_OR_ERR_MASK (0x8U) +#define DBGMAILBOX_CSW_AHB_OR_ERR_SHIFT (3U) +/*! AHB_OR_ERR - AHB overrun Error (Return value overwritten by ROM) + */ +#define DBGMAILBOX_CSW_AHB_OR_ERR(x) (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_AHB_OR_ERR_SHIFT)) & DBGMAILBOX_CSW_AHB_OR_ERR_MASK) + +#define DBGMAILBOX_CSW_SOFT_RESET_MASK (0x10U) +#define DBGMAILBOX_CSW_SOFT_RESET_SHIFT (4U) +/*! SOFT_RESET - Soft Reset for DM (write-only from AHB, not readable and selfclearing). A write to + * this bit will cause a soft reset for DM. + */ +#define DBGMAILBOX_CSW_SOFT_RESET(x) (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_SOFT_RESET_SHIFT)) & DBGMAILBOX_CSW_SOFT_RESET_MASK) + +#define DBGMAILBOX_CSW_CHIP_RESET_REQ_MASK (0x20U) +#define DBGMAILBOX_CSW_CHIP_RESET_REQ_SHIFT (5U) +/*! CHIP_RESET_REQ - Write only bit. Once written will cause the chip to reset (note that the DM is + * not reset by this reset as it is only resettable by a SOFT reset or a POR/BOD event) + */ +#define DBGMAILBOX_CSW_CHIP_RESET_REQ(x) (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_CHIP_RESET_REQ_SHIFT)) & DBGMAILBOX_CSW_CHIP_RESET_REQ_MASK) +/*! @} */ + +/*! @name REQUEST - CRC seed register */ +/*! @{ */ + +#define DBGMAILBOX_REQUEST_REQ_MASK (0xFFFFFFFFU) +#define DBGMAILBOX_REQUEST_REQ_SHIFT (0U) +/*! REQ - Request Value + */ +#define DBGMAILBOX_REQUEST_REQ(x) (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_REQUEST_REQ_SHIFT)) & DBGMAILBOX_REQUEST_REQ_MASK) +/*! @} */ + +/*! @name RETURN - Return value from ROM. */ +/*! @{ */ + +#define DBGMAILBOX_RETURN_RET_MASK (0xFFFFFFFFU) +#define DBGMAILBOX_RETURN_RET_SHIFT (0U) +/*! RET - The Return value from ROM. + */ +#define DBGMAILBOX_RETURN_RET(x) (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_RETURN_RET_SHIFT)) & DBGMAILBOX_RETURN_RET_MASK) +/*! @} */ + +/*! @name ID - Identification register */ +/*! @{ */ + +#define DBGMAILBOX_ID_ID_MASK (0xFFFFFFFFU) +#define DBGMAILBOX_ID_ID_SHIFT (0U) +/*! ID - Identification value. + */ +#define DBGMAILBOX_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_ID_ID_SHIFT)) & DBGMAILBOX_ID_ID_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group DBGMAILBOX_Register_Masks */ + + +/* DBGMAILBOX - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral DBGMAILBOX base address */ + #define DBGMAILBOX_BASE (0x5009C000u) + /** Peripheral DBGMAILBOX base address */ + #define DBGMAILBOX_BASE_NS (0x4009C000u) + /** Peripheral DBGMAILBOX base pointer */ + #define DBGMAILBOX ((DBGMAILBOX_Type *)DBGMAILBOX_BASE) + /** Peripheral DBGMAILBOX base pointer */ + #define DBGMAILBOX_NS ((DBGMAILBOX_Type *)DBGMAILBOX_BASE_NS) + /** Array initializer of DBGMAILBOX peripheral base addresses */ + #define DBGMAILBOX_BASE_ADDRS { DBGMAILBOX_BASE } + /** Array initializer of DBGMAILBOX peripheral base pointers */ + #define DBGMAILBOX_BASE_PTRS { DBGMAILBOX } + /** Array initializer of DBGMAILBOX peripheral base addresses */ + #define DBGMAILBOX_BASE_ADDRS_NS { DBGMAILBOX_BASE_NS } + /** Array initializer of DBGMAILBOX peripheral base pointers */ + #define DBGMAILBOX_BASE_PTRS_NS { DBGMAILBOX_NS } +#else + /** Peripheral DBGMAILBOX base address */ + #define DBGMAILBOX_BASE (0x4009C000u) + /** Peripheral DBGMAILBOX base pointer */ + #define DBGMAILBOX ((DBGMAILBOX_Type *)DBGMAILBOX_BASE) + /** Array initializer of DBGMAILBOX peripheral base addresses */ + #define DBGMAILBOX_BASE_ADDRS { DBGMAILBOX_BASE } + /** Array initializer of DBGMAILBOX peripheral base pointers */ + #define DBGMAILBOX_BASE_PTRS { DBGMAILBOX } +#endif + +/*! + * @} + */ /* end of group DBGMAILBOX_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- DMA Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer + * @{ + */ + +/** DMA - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL; /**< DMA control., offset: 0x0 */ + __I uint32_t INTSTAT; /**< Interrupt status., offset: 0x4 */ + __IO uint32_t SRAMBASE; /**< SRAM address of the channel configuration table., offset: 0x8 */ + uint8_t RESERVED_0[20]; + struct { /* offset: 0x20, array step: 0x5C */ + __IO uint32_t ENABLESET; /**< Channel Enable read and Set for all DMA channels., array offset: 0x20, array step: 0x5C */ + uint8_t RESERVED_0[4]; + __O uint32_t ENABLECLR; /**< Channel Enable Clear for all DMA channels., array offset: 0x28, array step: 0x5C */ + uint8_t RESERVED_1[4]; + __I uint32_t ACTIVE; /**< Channel Active status for all DMA channels., array offset: 0x30, array step: 0x5C */ + uint8_t RESERVED_2[4]; + __I uint32_t BUSY; /**< Channel Busy status for all DMA channels., array offset: 0x38, array step: 0x5C */ + uint8_t RESERVED_3[4]; + __IO uint32_t ERRINT; /**< Error Interrupt status for all DMA channels., array offset: 0x40, array step: 0x5C */ + uint8_t RESERVED_4[4]; + __IO uint32_t INTENSET; /**< Interrupt Enable read and Set for all DMA channels., array offset: 0x48, array step: 0x5C */ + uint8_t RESERVED_5[4]; + __O uint32_t INTENCLR; /**< Interrupt Enable Clear for all DMA channels., array offset: 0x50, array step: 0x5C */ + uint8_t RESERVED_6[4]; + __IO uint32_t INTA; /**< Interrupt A status for all DMA channels., array offset: 0x58, array step: 0x5C */ + uint8_t RESERVED_7[4]; + __IO uint32_t INTB; /**< Interrupt B status for all DMA channels., array offset: 0x60, array step: 0x5C */ + uint8_t RESERVED_8[4]; + __O uint32_t SETVALID; /**< Set ValidPending control bits for all DMA channels., array offset: 0x68, array step: 0x5C */ + uint8_t RESERVED_9[4]; + __O uint32_t SETTRIG; /**< Set Trigger control bits for all DMA channels., array offset: 0x70, array step: 0x5C */ + uint8_t RESERVED_10[4]; + __O uint32_t ABORT; /**< Channel Abort control for all DMA channels., array offset: 0x78, array step: 0x5C */ + } COMMON[1]; + uint8_t RESERVED_1[900]; + struct { /* offset: 0x400, array step: 0x10 */ + __IO uint32_t CFG; /**< Configuration register for DMA channel ., array offset: 0x400, array step: 0x10 */ + __I uint32_t CTLSTAT; /**< Control and status register for DMA channel ., array offset: 0x404, array step: 0x10 */ + __IO uint32_t XFERCFG; /**< Transfer configuration register for DMA channel ., array offset: 0x408, array step: 0x10 */ + uint8_t RESERVED_0[4]; + } CHANNEL[23]; +} DMA_Type; + +/* ---------------------------------------------------------------------------- + -- DMA Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DMA_Register_Masks DMA Register Masks + * @{ + */ + +/*! @name CTRL - DMA control. */ +/*! @{ */ + +#define DMA_CTRL_ENABLE_MASK (0x1U) +#define DMA_CTRL_ENABLE_SHIFT (0U) +/*! ENABLE - DMA controller master enable. + * 0b0..Disabled. The DMA controller is disabled. This clears any triggers that were asserted at the point when + * disabled, but does not prevent re-triggering when the DMA controller is re-enabled. + * 0b1..Enabled. The DMA controller is enabled. + */ +#define DMA_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CTRL_ENABLE_SHIFT)) & DMA_CTRL_ENABLE_MASK) +/*! @} */ + +/*! @name INTSTAT - Interrupt status. */ +/*! @{ */ + +#define DMA_INTSTAT_ACTIVEINT_MASK (0x2U) +#define DMA_INTSTAT_ACTIVEINT_SHIFT (1U) +/*! ACTIVEINT - Summarizes whether any enabled interrupts (other than error interrupts) are pending. + * 0b0..Not pending. No enabled interrupts are pending. + * 0b1..Pending. At least one enabled interrupt is pending. + */ +#define DMA_INTSTAT_ACTIVEINT(x) (((uint32_t)(((uint32_t)(x)) << DMA_INTSTAT_ACTIVEINT_SHIFT)) & DMA_INTSTAT_ACTIVEINT_MASK) + +#define DMA_INTSTAT_ACTIVEERRINT_MASK (0x4U) +#define DMA_INTSTAT_ACTIVEERRINT_SHIFT (2U) +/*! ACTIVEERRINT - Summarizes whether any error interrupts are pending. + * 0b0..Not pending. No error interrupts are pending. + * 0b1..Pending. At least one error interrupt is pending. + */ +#define DMA_INTSTAT_ACTIVEERRINT(x) (((uint32_t)(((uint32_t)(x)) << DMA_INTSTAT_ACTIVEERRINT_SHIFT)) & DMA_INTSTAT_ACTIVEERRINT_MASK) +/*! @} */ + +/*! @name SRAMBASE - SRAM address of the channel configuration table. */ +/*! @{ */ + +#define DMA_SRAMBASE_OFFSET_MASK (0xFFFFFE00U) +#define DMA_SRAMBASE_OFFSET_SHIFT (9U) +/*! OFFSET - Address bits 31:9 of the beginning of the DMA descriptor table. For 18 channels, the + * table must begin on a 512 byte boundary. + */ +#define DMA_SRAMBASE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << DMA_SRAMBASE_OFFSET_SHIFT)) & DMA_SRAMBASE_OFFSET_MASK) +/*! @} */ + +/*! @name COMMON_ENABLESET - Channel Enable read and Set for all DMA channels. */ +/*! @{ */ + +#define DMA_COMMON_ENABLESET_ENA_MASK (0xFFFFFFFFU) +#define DMA_COMMON_ENABLESET_ENA_SHIFT (0U) +/*! ENA - Enable for DMA channels. Bit n enables or disables DMA channel n. The number of bits = + * number of DMA channels in this device. Other bits are reserved. 0 = disabled. 1 = enabled. + */ +#define DMA_COMMON_ENABLESET_ENA(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENA_SHIFT)) & DMA_COMMON_ENABLESET_ENA_MASK) +/*! @} */ + +/* The count of DMA_COMMON_ENABLESET */ +#define DMA_COMMON_ENABLESET_COUNT (1U) + +/*! @name COMMON_ENABLECLR - Channel Enable Clear for all DMA channels. */ +/*! @{ */ + +#define DMA_COMMON_ENABLECLR_CLR_MASK (0xFFFFFFFFU) +#define DMA_COMMON_ENABLECLR_CLR_SHIFT (0U) +/*! CLR - Writing ones to this register clears the corresponding bits in ENABLESET0. Bit n clears + * the channel enable bit n. The number of bits = number of DMA channels in this device. Other bits + * are reserved. + */ +#define DMA_COMMON_ENABLECLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR_SHIFT)) & DMA_COMMON_ENABLECLR_CLR_MASK) +/*! @} */ + +/* The count of DMA_COMMON_ENABLECLR */ +#define DMA_COMMON_ENABLECLR_COUNT (1U) + +/*! @name COMMON_ACTIVE - Channel Active status for all DMA channels. */ +/*! @{ */ + +#define DMA_COMMON_ACTIVE_ACT_MASK (0xFFFFFFFFU) +#define DMA_COMMON_ACTIVE_ACT_SHIFT (0U) +/*! ACT - Active flag for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = + * number of DMA channels in this device. Other bits are reserved. 0 = not active. 1 = active. + */ +#define DMA_COMMON_ACTIVE_ACT(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACT_SHIFT)) & DMA_COMMON_ACTIVE_ACT_MASK) +/*! @} */ + +/* The count of DMA_COMMON_ACTIVE */ +#define DMA_COMMON_ACTIVE_COUNT (1U) + +/*! @name COMMON_BUSY - Channel Busy status for all DMA channels. */ +/*! @{ */ + +#define DMA_COMMON_BUSY_BSY_MASK (0xFFFFFFFFU) +#define DMA_COMMON_BUSY_BSY_SHIFT (0U) +/*! BSY - Busy flag for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = + * number of DMA channels in this device. Other bits are reserved. 0 = not busy. 1 = busy. + */ +#define DMA_COMMON_BUSY_BSY(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BSY_SHIFT)) & DMA_COMMON_BUSY_BSY_MASK) +/*! @} */ + +/* The count of DMA_COMMON_BUSY */ +#define DMA_COMMON_BUSY_COUNT (1U) + +/*! @name COMMON_ERRINT - Error Interrupt status for all DMA channels. */ +/*! @{ */ + +#define DMA_COMMON_ERRINT_ERR_MASK (0xFFFFFFFFU) +#define DMA_COMMON_ERRINT_ERR_SHIFT (0U) +/*! ERR - Error Interrupt flag for DMA channel n. Bit n corresponds to DMA channel n. The number of + * bits = number of DMA channels in this device. Other bits are reserved. 0 = error interrupt is + * not active. 1 = error interrupt is active. + */ +#define DMA_COMMON_ERRINT_ERR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR_SHIFT)) & DMA_COMMON_ERRINT_ERR_MASK) +/*! @} */ + +/* The count of DMA_COMMON_ERRINT */ +#define DMA_COMMON_ERRINT_COUNT (1U) + +/*! @name COMMON_INTENSET - Interrupt Enable read and Set for all DMA channels. */ +/*! @{ */ + +#define DMA_COMMON_INTENSET_INTEN_MASK (0xFFFFFFFFU) +#define DMA_COMMON_INTENSET_INTEN_SHIFT (0U) +/*! INTEN - Interrupt Enable read and set for DMA channel n. Bit n corresponds to DMA channel n. The + * number of bits = number of DMA channels in this device. Other bits are reserved. 0 = + * interrupt for DMA channel is disabled. 1 = interrupt for DMA channel is enabled. + */ +#define DMA_COMMON_INTENSET_INTEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN_SHIFT)) & DMA_COMMON_INTENSET_INTEN_MASK) +/*! @} */ + +/* The count of DMA_COMMON_INTENSET */ +#define DMA_COMMON_INTENSET_COUNT (1U) + +/*! @name COMMON_INTENCLR - Interrupt Enable Clear for all DMA channels. */ +/*! @{ */ + +#define DMA_COMMON_INTENCLR_CLR_MASK (0xFFFFFFFFU) +#define DMA_COMMON_INTENCLR_CLR_SHIFT (0U) +/*! CLR - Writing ones to this register clears corresponding bits in the INTENSET0. Bit n + * corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are + * reserved. + */ +#define DMA_COMMON_INTENCLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR_SHIFT)) & DMA_COMMON_INTENCLR_CLR_MASK) +/*! @} */ + +/* The count of DMA_COMMON_INTENCLR */ +#define DMA_COMMON_INTENCLR_COUNT (1U) + +/*! @name COMMON_INTA - Interrupt A status for all DMA channels. */ +/*! @{ */ + +#define DMA_COMMON_INTA_IA_MASK (0xFFFFFFFFU) +#define DMA_COMMON_INTA_IA_SHIFT (0U) +/*! IA - Interrupt A status for DMA channel n. Bit n corresponds to DMA channel n. The number of + * bits = number of DMA channels in this device. Other bits are reserved. 0 = the DMA channel + * interrupt A is not active. 1 = the DMA channel interrupt A is active. + */ +#define DMA_COMMON_INTA_IA(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_IA_SHIFT)) & DMA_COMMON_INTA_IA_MASK) +/*! @} */ + +/* The count of DMA_COMMON_INTA */ +#define DMA_COMMON_INTA_COUNT (1U) + +/*! @name COMMON_INTB - Interrupt B status for all DMA channels. */ +/*! @{ */ + +#define DMA_COMMON_INTB_IB_MASK (0xFFFFFFFFU) +#define DMA_COMMON_INTB_IB_SHIFT (0U) +/*! IB - Interrupt B status for DMA channel n. Bit n corresponds to DMA channel n. The number of + * bits = number of DMA channels in this device. Other bits are reserved. 0 = the DMA channel + * interrupt B is not active. 1 = the DMA channel interrupt B is active. + */ +#define DMA_COMMON_INTB_IB(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_IB_SHIFT)) & DMA_COMMON_INTB_IB_MASK) +/*! @} */ + +/* The count of DMA_COMMON_INTB */ +#define DMA_COMMON_INTB_COUNT (1U) + +/*! @name COMMON_SETVALID - Set ValidPending control bits for all DMA channels. */ +/*! @{ */ + +#define DMA_COMMON_SETVALID_SV_MASK (0xFFFFFFFFU) +#define DMA_COMMON_SETVALID_SV_SHIFT (0U) +/*! SV - SETVALID control for DMA channel n. Bit n corresponds to DMA channel n. The number of bits + * = number of DMA channels in this device. Other bits are reserved. 0 = no effect. 1 = sets the + * VALIDPENDING control bit for DMA channel n + */ +#define DMA_COMMON_SETVALID_SV(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SV_SHIFT)) & DMA_COMMON_SETVALID_SV_MASK) +/*! @} */ + +/* The count of DMA_COMMON_SETVALID */ +#define DMA_COMMON_SETVALID_COUNT (1U) + +/*! @name COMMON_SETTRIG - Set Trigger control bits for all DMA channels. */ +/*! @{ */ + +#define DMA_COMMON_SETTRIG_TRIG_MASK (0xFFFFFFFFU) +#define DMA_COMMON_SETTRIG_TRIG_SHIFT (0U) +/*! TRIG - Set Trigger control bit for DMA channel 0. Bit n corresponds to DMA channel n. The number + * of bits = number of DMA channels in this device. Other bits are reserved. 0 = no effect. 1 = + * sets the TRIG bit for DMA channel n. + */ +#define DMA_COMMON_SETTRIG_TRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_TRIG_SHIFT)) & DMA_COMMON_SETTRIG_TRIG_MASK) +/*! @} */ + +/* The count of DMA_COMMON_SETTRIG */ +#define DMA_COMMON_SETTRIG_COUNT (1U) + +/*! @name COMMON_ABORT - Channel Abort control for all DMA channels. */ +/*! @{ */ + +#define DMA_COMMON_ABORT_ABORTCTRL_MASK (0xFFFFFFFFU) +#define DMA_COMMON_ABORT_ABORTCTRL_SHIFT (0U) +/*! ABORTCTRL - Abort control for DMA channel 0. Bit n corresponds to DMA channel n. 0 = no effect. + * 1 = aborts DMA operations on channel n. + */ +#define DMA_COMMON_ABORT_ABORTCTRL(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORTCTRL_SHIFT)) & DMA_COMMON_ABORT_ABORTCTRL_MASK) +/*! @} */ + +/* The count of DMA_COMMON_ABORT */ +#define DMA_COMMON_ABORT_COUNT (1U) + +/*! @name CHANNEL_CFG - Configuration register for DMA channel . */ +/*! @{ */ + +#define DMA_CHANNEL_CFG_PERIPHREQEN_MASK (0x1U) +#define DMA_CHANNEL_CFG_PERIPHREQEN_SHIFT (0U) +/*! PERIPHREQEN - Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory + * move, any peripheral DMA request associated with that channel can be disabled to prevent any + * interaction between the peripheral and the DMA controller. + * 0b0..Disabled. Peripheral DMA requests are disabled. + * 0b1..Enabled. Peripheral DMA requests are enabled. + */ +#define DMA_CHANNEL_CFG_PERIPHREQEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_PERIPHREQEN_SHIFT)) & DMA_CHANNEL_CFG_PERIPHREQEN_MASK) + +#define DMA_CHANNEL_CFG_HWTRIGEN_MASK (0x2U) +#define DMA_CHANNEL_CFG_HWTRIGEN_SHIFT (1U) +/*! HWTRIGEN - Hardware Triggering Enable for this channel. + * 0b0..Disabled. Hardware triggering is not used. + * 0b1..Enabled. Use hardware triggering. + */ +#define DMA_CHANNEL_CFG_HWTRIGEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_HWTRIGEN_SHIFT)) & DMA_CHANNEL_CFG_HWTRIGEN_MASK) + +#define DMA_CHANNEL_CFG_TRIGPOL_MASK (0x10U) +#define DMA_CHANNEL_CFG_TRIGPOL_SHIFT (4U) +/*! TRIGPOL - Trigger Polarity. Selects the polarity of a hardware trigger for this channel. + * 0b0..Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE. + * 0b1..Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE. + */ +#define DMA_CHANNEL_CFG_TRIGPOL(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGPOL_SHIFT)) & DMA_CHANNEL_CFG_TRIGPOL_MASK) + +#define DMA_CHANNEL_CFG_TRIGTYPE_MASK (0x20U) +#define DMA_CHANNEL_CFG_TRIGTYPE_SHIFT (5U) +/*! TRIGTYPE - Trigger Type. Selects hardware trigger as edge triggered or level triggered. + * 0b0..Edge. Hardware trigger is edge triggered. Transfers will be initiated and completed, as specified for a single trigger. + * 0b1..Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = + * 0) is selected, only hardware triggers should be used on that channel. Transfers continue as long as the + * trigger level is asserted. Once the trigger is de-asserted, the transfer will be paused until the trigger + * is, again, asserted. However, the transfer will not be paused until any remaining transfers within the + * current BURSTPOWER length are completed. + */ +#define DMA_CHANNEL_CFG_TRIGTYPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGTYPE_SHIFT)) & DMA_CHANNEL_CFG_TRIGTYPE_MASK) + +#define DMA_CHANNEL_CFG_TRIGBURST_MASK (0x40U) +#define DMA_CHANNEL_CFG_TRIGBURST_SHIFT (6U) +/*! TRIGBURST - Trigger Burst. Selects whether hardware triggers cause a single or burst transfer. + * 0b0..Single transfer. Hardware trigger causes a single transfer. + * 0b1..Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a + * burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a + * hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is + * complete. + */ +#define DMA_CHANNEL_CFG_TRIGBURST(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGBURST_SHIFT)) & DMA_CHANNEL_CFG_TRIGBURST_MASK) + +#define DMA_CHANNEL_CFG_BURSTPOWER_MASK (0xF00U) +#define DMA_CHANNEL_CFG_BURSTPOWER_SHIFT (8U) +/*! BURSTPOWER - Burst Power is used in two ways. It always selects the address wrap size when + * SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). + * When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many + * transfers are performed for each DMA trigger. This can be used, for example, with peripherals that + * contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: + * Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). 1010: Burst size = + * 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The + * total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even + * multiple of the burst size. + */ +#define DMA_CHANNEL_CFG_BURSTPOWER(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_BURSTPOWER_SHIFT)) & DMA_CHANNEL_CFG_BURSTPOWER_MASK) + +#define DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK (0x4000U) +#define DMA_CHANNEL_CFG_SRCBURSTWRAP_SHIFT (14U) +/*! SRCBURSTWRAP - Source Burst Wrap. When enabled, the source data address for the DMA is + * 'wrapped', meaning that the source address range for each burst will be the same. As an example, this + * could be used to read several sequential registers from a peripheral for each DMA burst, + * reading the same registers again for each burst. + * 0b0..Disabled. Source burst wrapping is not enabled for this DMA channel. + * 0b1..Enabled. Source burst wrapping is enabled for this DMA channel. + */ +#define DMA_CHANNEL_CFG_SRCBURSTWRAP(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_SRCBURSTWRAP_SHIFT)) & DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK) + +#define DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK (0x8000U) +#define DMA_CHANNEL_CFG_DSTBURSTWRAP_SHIFT (15U) +/*! DSTBURSTWRAP - Destination Burst Wrap. When enabled, the destination data address for the DMA is + * 'wrapped', meaning that the destination address range for each burst will be the same. As an + * example, this could be used to write several sequential registers to a peripheral for each DMA + * burst, writing the same registers again for each burst. + * 0b0..Disabled. Destination burst wrapping is not enabled for this DMA channel. + * 0b1..Enabled. Destination burst wrapping is enabled for this DMA channel. + */ +#define DMA_CHANNEL_CFG_DSTBURSTWRAP(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_DSTBURSTWRAP_SHIFT)) & DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK) + +#define DMA_CHANNEL_CFG_CHPRIORITY_MASK (0x70000U) +#define DMA_CHANNEL_CFG_CHPRIORITY_SHIFT (16U) +/*! CHPRIORITY - Priority of this channel when multiple DMA requests are pending. Eight priority + * levels are supported: 0x0 = highest priority. 0x7 = lowest priority. + */ +#define DMA_CHANNEL_CFG_CHPRIORITY(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_CHPRIORITY_SHIFT)) & DMA_CHANNEL_CFG_CHPRIORITY_MASK) +/*! @} */ + +/* The count of DMA_CHANNEL_CFG */ +#define DMA_CHANNEL_CFG_COUNT (23U) + +/*! @name CHANNEL_CTLSTAT - Control and status register for DMA channel . */ +/*! @{ */ + +#define DMA_CHANNEL_CTLSTAT_VALIDPENDING_MASK (0x1U) +#define DMA_CHANNEL_CTLSTAT_VALIDPENDING_SHIFT (0U) +/*! VALIDPENDING - Valid pending flag for this channel. This bit is set when a 1 is written to the + * corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel. + * 0b0..No effect. No effect on DMA operation. + * 0b1..Valid pending. + */ +#define DMA_CHANNEL_CTLSTAT_VALIDPENDING(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CTLSTAT_VALIDPENDING_SHIFT)) & DMA_CHANNEL_CTLSTAT_VALIDPENDING_MASK) + +#define DMA_CHANNEL_CTLSTAT_TRIG_MASK (0x4U) +#define DMA_CHANNEL_CTLSTAT_TRIG_SHIFT (2U) +/*! TRIG - Trigger flag. Indicates that the trigger for this channel is currently set. This bit is + * cleared at the end of an entire transfer or upon reload when CLRTRIG = 1. + * 0b0..Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out. + * 0b1..Triggered. The trigger for this DMA channel is set. DMA operations will be carried out. + */ +#define DMA_CHANNEL_CTLSTAT_TRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CTLSTAT_TRIG_SHIFT)) & DMA_CHANNEL_CTLSTAT_TRIG_MASK) +/*! @} */ + +/* The count of DMA_CHANNEL_CTLSTAT */ +#define DMA_CHANNEL_CTLSTAT_COUNT (23U) + +/*! @name CHANNEL_XFERCFG - Transfer configuration register for DMA channel . */ +/*! @{ */ + +#define DMA_CHANNEL_XFERCFG_CFGVALID_MASK (0x1U) +#define DMA_CHANNEL_XFERCFG_CFGVALID_SHIFT (0U) +/*! CFGVALID - Configuration Valid flag. This bit indicates whether the current channel descriptor + * is valid and can potentially be acted upon, if all other activation criteria are fulfilled. + * 0b0..Not valid. The channel descriptor is not considered valid until validated by an associated SETVALID0 setting. + * 0b1..Valid. The current channel descriptor is considered valid. + */ +#define DMA_CHANNEL_XFERCFG_CFGVALID(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_CFGVALID_SHIFT)) & DMA_CHANNEL_XFERCFG_CFGVALID_MASK) + +#define DMA_CHANNEL_XFERCFG_RELOAD_MASK (0x2U) +#define DMA_CHANNEL_XFERCFG_RELOAD_SHIFT (1U) +/*! RELOAD - Indicates whether the channel's control structure will be reloaded when the current + * descriptor is exhausted. Reloading allows ping-pong and linked transfers. + * 0b0..Disabled. Do not reload the channels' control structure when the current descriptor is exhausted. + * 0b1..Enabled. Reload the channels' control structure when the current descriptor is exhausted. + */ +#define DMA_CHANNEL_XFERCFG_RELOAD(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_RELOAD_SHIFT)) & DMA_CHANNEL_XFERCFG_RELOAD_MASK) + +#define DMA_CHANNEL_XFERCFG_SWTRIG_MASK (0x4U) +#define DMA_CHANNEL_XFERCFG_SWTRIG_SHIFT (2U) +/*! SWTRIG - Software Trigger. + * 0b0..Not set. When written by software, the trigger for this channel is not set. A new trigger, as defined by + * the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel. + * 0b1..Set. When written by software, the trigger for this channel is set immediately. This feature should not + * be used with level triggering when TRIGBURST = 0. + */ +#define DMA_CHANNEL_XFERCFG_SWTRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SWTRIG_SHIFT)) & DMA_CHANNEL_XFERCFG_SWTRIG_MASK) + +#define DMA_CHANNEL_XFERCFG_CLRTRIG_MASK (0x8U) +#define DMA_CHANNEL_XFERCFG_CLRTRIG_SHIFT (3U) +/*! CLRTRIG - Clear Trigger. + * 0b0..Not cleared. The trigger is not cleared when this descriptor is exhausted. If there is a reload, the next descriptor will be started. + * 0b1..Cleared. The trigger is cleared when this descriptor is exhausted + */ +#define DMA_CHANNEL_XFERCFG_CLRTRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_CLRTRIG_SHIFT)) & DMA_CHANNEL_XFERCFG_CLRTRIG_MASK) + +#define DMA_CHANNEL_XFERCFG_SETINTA_MASK (0x10U) +#define DMA_CHANNEL_XFERCFG_SETINTA_SHIFT (4U) +/*! SETINTA - Set Interrupt flag A for this channel. There is no hardware distinction between + * interrupt A and B. They can be used by software to assist with more complex descriptor usage. By + * convention, interrupt A may be used when only one interrupt flag is needed. + * 0b0..No effect. + * 0b1..Set. The INTA flag for this channel will be set when the current descriptor is exhausted. + */ +#define DMA_CHANNEL_XFERCFG_SETINTA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SETINTA_SHIFT)) & DMA_CHANNEL_XFERCFG_SETINTA_MASK) + +#define DMA_CHANNEL_XFERCFG_SETINTB_MASK (0x20U) +#define DMA_CHANNEL_XFERCFG_SETINTB_SHIFT (5U) +/*! SETINTB - Set Interrupt flag B for this channel. There is no hardware distinction between + * interrupt A and B. They can be used by software to assist with more complex descriptor usage. By + * convention, interrupt A may be used when only one interrupt flag is needed. + * 0b0..No effect. + * 0b1..Set. The INTB flag for this channel will be set when the current descriptor is exhausted. + */ +#define DMA_CHANNEL_XFERCFG_SETINTB(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SETINTB_SHIFT)) & DMA_CHANNEL_XFERCFG_SETINTB_MASK) + +#define DMA_CHANNEL_XFERCFG_WIDTH_MASK (0x300U) +#define DMA_CHANNEL_XFERCFG_WIDTH_SHIFT (8U) +/*! WIDTH - Transfer width used for this DMA channel. + * 0b00..8-bit. 8-bit transfers are performed (8-bit source reads and destination writes). + * 0b01..16-bit. 6-bit transfers are performed (16-bit source reads and destination writes). + * 0b10..32-bit. 32-bit transfers are performed (32-bit source reads and destination writes). + * 0b11..Reserved. Reserved setting, do not use. + */ +#define DMA_CHANNEL_XFERCFG_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_WIDTH_SHIFT)) & DMA_CHANNEL_XFERCFG_WIDTH_MASK) + +#define DMA_CHANNEL_XFERCFG_SRCINC_MASK (0x3000U) +#define DMA_CHANNEL_XFERCFG_SRCINC_SHIFT (12U) +/*! SRCINC - Determines whether the source address is incremented for each DMA transfer. + * 0b00..No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device. + * 0b01..1 x width. The source address is incremented by the amount specified by Width for each transfer. This is + * the usual case when the source is memory. + * 0b10..2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer. + * 0b11..4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer. + */ +#define DMA_CHANNEL_XFERCFG_SRCINC(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SRCINC_SHIFT)) & DMA_CHANNEL_XFERCFG_SRCINC_MASK) + +#define DMA_CHANNEL_XFERCFG_DSTINC_MASK (0xC000U) +#define DMA_CHANNEL_XFERCFG_DSTINC_SHIFT (14U) +/*! DSTINC - Determines whether the destination address is incremented for each DMA transfer. + * 0b00..No increment. The destination address is not incremented for each transfer. This is the usual case when + * the destination is a peripheral device. + * 0b01..1 x width. The destination address is incremented by the amount specified by Width for each transfer. + * This is the usual case when the destination is memory. + * 0b10..2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer. + * 0b11..4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer. + */ +#define DMA_CHANNEL_XFERCFG_DSTINC(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_DSTINC_SHIFT)) & DMA_CHANNEL_XFERCFG_DSTINC_MASK) + +#define DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK (0x3FF0000U) +#define DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT (16U) +/*! XFERCOUNT - Total number of transfers to be performed, minus 1 encoded. The number of bytes + * transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller + * uses this bit field during transfer to count down. Hence, it cannot be used by software to read + * back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 + * transfer will be performed. 0x1 = a total of 2 transfers will be performed. 0x3FF = a total of + * 1,024 transfers will be performed. + */ +#define DMA_CHANNEL_XFERCFG_XFERCOUNT(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT)) & DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK) +/*! @} */ + +/* The count of DMA_CHANNEL_XFERCFG */ +#define DMA_CHANNEL_XFERCFG_COUNT (23U) + + +/*! + * @} + */ /* end of group DMA_Register_Masks */ + + +/* DMA - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral DMA0 base address */ + #define DMA0_BASE (0x50082000u) + /** Peripheral DMA0 base address */ + #define DMA0_BASE_NS (0x40082000u) + /** Peripheral DMA0 base pointer */ + #define DMA0 ((DMA_Type *)DMA0_BASE) + /** Peripheral DMA0 base pointer */ + #define DMA0_NS ((DMA_Type *)DMA0_BASE_NS) + /** Peripheral DMA1 base address */ + #define DMA1_BASE (0x500A7000u) + /** Peripheral DMA1 base address */ + #define DMA1_BASE_NS (0x400A7000u) + /** Peripheral DMA1 base pointer */ + #define DMA1 ((DMA_Type *)DMA1_BASE) + /** Peripheral DMA1 base pointer */ + #define DMA1_NS ((DMA_Type *)DMA1_BASE_NS) + /** Array initializer of DMA peripheral base addresses */ + #define DMA_BASE_ADDRS { DMA0_BASE, DMA1_BASE } + /** Array initializer of DMA peripheral base pointers */ + #define DMA_BASE_PTRS { DMA0, DMA1 } + /** Array initializer of DMA peripheral base addresses */ + #define DMA_BASE_ADDRS_NS { DMA0_BASE_NS, DMA1_BASE_NS } + /** Array initializer of DMA peripheral base pointers */ + #define DMA_BASE_PTRS_NS { DMA0_NS, DMA1_NS } +#else + /** Peripheral DMA0 base address */ + #define DMA0_BASE (0x40082000u) + /** Peripheral DMA0 base pointer */ + #define DMA0 ((DMA_Type *)DMA0_BASE) + /** Peripheral DMA1 base address */ + #define DMA1_BASE (0x400A7000u) + /** Peripheral DMA1 base pointer */ + #define DMA1 ((DMA_Type *)DMA1_BASE) + /** Array initializer of DMA peripheral base addresses */ + #define DMA_BASE_ADDRS { DMA0_BASE, DMA1_BASE } + /** Array initializer of DMA peripheral base pointers */ + #define DMA_BASE_PTRS { DMA0, DMA1 } +#endif +/** Interrupt vectors for the DMA peripheral type */ +#define DMA_IRQS { DMA0_IRQn, DMA1_IRQn } + +/*! + * @} + */ /* end of group DMA_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- FLASH Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FLASH_Peripheral_Access_Layer FLASH Peripheral Access Layer + * @{ + */ + +/** FLASH - Register Layout Typedef */ +typedef struct { + __O uint32_t CMD; /**< command register, offset: 0x0 */ + __O uint32_t EVENT; /**< event register, offset: 0x4 */ + uint8_t RESERVED_0[8]; + __IO uint32_t STARTA; /**< start (or only) address for next flash command, offset: 0x10 */ + __IO uint32_t STOPA; /**< end address for next flash command, if command operates on address ranges, offset: 0x14 */ + uint8_t RESERVED_1[104]; + __IO uint32_t DATAW[4]; /**< data register, word 0-7; Memory data, or command parameter, or command result., array offset: 0x80, array step: 0x4 */ + uint8_t RESERVED_2[3912]; + __O uint32_t INT_CLR_ENABLE; /**< Clear interrupt enable bits, offset: 0xFD8 */ + __O uint32_t INT_SET_ENABLE; /**< Set interrupt enable bits, offset: 0xFDC */ + __I uint32_t INT_STATUS; /**< Interrupt status bits, offset: 0xFE0 */ + __I uint32_t INT_ENABLE; /**< Interrupt enable bits, offset: 0xFE4 */ + __O uint32_t INT_CLR_STATUS; /**< Clear interrupt status bits, offset: 0xFE8 */ + __O uint32_t INT_SET_STATUS; /**< Set interrupt status bits, offset: 0xFEC */ + uint8_t RESERVED_3[12]; + __I uint32_t MODULE_ID; /**< Controller+Memory module identification, offset: 0xFFC */ +} FLASH_Type; + +/* ---------------------------------------------------------------------------- + -- FLASH Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FLASH_Register_Masks FLASH Register Masks + * @{ + */ + +/*! @name CMD - command register */ +/*! @{ */ + +#define FLASH_CMD_CMD_MASK (0xFFFFFFFFU) +#define FLASH_CMD_CMD_SHIFT (0U) +/*! CMD - command register. + */ +#define FLASH_CMD_CMD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMD_CMD_SHIFT)) & FLASH_CMD_CMD_MASK) +/*! @} */ + +/*! @name EVENT - event register */ +/*! @{ */ + +#define FLASH_EVENT_RST_MASK (0x1U) +#define FLASH_EVENT_RST_SHIFT (0U) +/*! RST - When bit is set, the controller and flash are reset. + */ +#define FLASH_EVENT_RST(x) (((uint32_t)(((uint32_t)(x)) << FLASH_EVENT_RST_SHIFT)) & FLASH_EVENT_RST_MASK) + +#define FLASH_EVENT_WAKEUP_MASK (0x2U) +#define FLASH_EVENT_WAKEUP_SHIFT (1U) +/*! WAKEUP - When bit is set, the controller wakes up from whatever low power or powerdown mode was active. + */ +#define FLASH_EVENT_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << FLASH_EVENT_WAKEUP_SHIFT)) & FLASH_EVENT_WAKEUP_MASK) + +#define FLASH_EVENT_ABORT_MASK (0x4U) +#define FLASH_EVENT_ABORT_SHIFT (2U) +/*! ABORT - When bit is set, a running program/erase command is aborted. + */ +#define FLASH_EVENT_ABORT(x) (((uint32_t)(((uint32_t)(x)) << FLASH_EVENT_ABORT_SHIFT)) & FLASH_EVENT_ABORT_MASK) +/*! @} */ + +/*! @name STARTA - start (or only) address for next flash command */ +/*! @{ */ + +#define FLASH_STARTA_STARTA_MASK (0x3FFFFU) +#define FLASH_STARTA_STARTA_SHIFT (0U) +/*! STARTA - Address / Start address for commands that take an address (range) as a parameter. + */ +#define FLASH_STARTA_STARTA(x) (((uint32_t)(((uint32_t)(x)) << FLASH_STARTA_STARTA_SHIFT)) & FLASH_STARTA_STARTA_MASK) +/*! @} */ + +/*! @name STOPA - end address for next flash command, if command operates on address ranges */ +/*! @{ */ + +#define FLASH_STOPA_STOPA_MASK (0x3FFFFU) +#define FLASH_STOPA_STOPA_SHIFT (0U) +/*! STOPA - Stop address for commands that take an address range as a parameter (the word specified + * by STOPA is included in the address range). + */ +#define FLASH_STOPA_STOPA(x) (((uint32_t)(((uint32_t)(x)) << FLASH_STOPA_STOPA_SHIFT)) & FLASH_STOPA_STOPA_MASK) +/*! @} */ + +/*! @name DATAW - data register, word 0-7; Memory data, or command parameter, or command result. */ +/*! @{ */ + +#define FLASH_DATAW_DATAW_MASK (0xFFFFFFFFU) +#define FLASH_DATAW_DATAW_SHIFT (0U) +#define FLASH_DATAW_DATAW(x) (((uint32_t)(((uint32_t)(x)) << FLASH_DATAW_DATAW_SHIFT)) & FLASH_DATAW_DATAW_MASK) +/*! @} */ + +/* The count of FLASH_DATAW */ +#define FLASH_DATAW_COUNT (4U) + +/*! @name INT_CLR_ENABLE - Clear interrupt enable bits */ +/*! @{ */ + +#define FLASH_INT_CLR_ENABLE_FAIL_MASK (0x1U) +#define FLASH_INT_CLR_ENABLE_FAIL_SHIFT (0U) +/*! FAIL - When a CLR_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is cleared. + */ +#define FLASH_INT_CLR_ENABLE_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_ENABLE_FAIL_SHIFT)) & FLASH_INT_CLR_ENABLE_FAIL_MASK) + +#define FLASH_INT_CLR_ENABLE_ERR_MASK (0x2U) +#define FLASH_INT_CLR_ENABLE_ERR_SHIFT (1U) +/*! ERR - When a CLR_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is cleared. + */ +#define FLASH_INT_CLR_ENABLE_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_ENABLE_ERR_SHIFT)) & FLASH_INT_CLR_ENABLE_ERR_MASK) + +#define FLASH_INT_CLR_ENABLE_DONE_MASK (0x4U) +#define FLASH_INT_CLR_ENABLE_DONE_SHIFT (2U) +/*! DONE - When a CLR_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is cleared. + */ +#define FLASH_INT_CLR_ENABLE_DONE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_ENABLE_DONE_SHIFT)) & FLASH_INT_CLR_ENABLE_DONE_MASK) + +#define FLASH_INT_CLR_ENABLE_ECC_ERR_MASK (0x8U) +#define FLASH_INT_CLR_ENABLE_ECC_ERR_SHIFT (3U) +/*! ECC_ERR - When a CLR_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is cleared. + */ +#define FLASH_INT_CLR_ENABLE_ECC_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_ENABLE_ECC_ERR_SHIFT)) & FLASH_INT_CLR_ENABLE_ECC_ERR_MASK) +/*! @} */ + +/*! @name INT_SET_ENABLE - Set interrupt enable bits */ +/*! @{ */ + +#define FLASH_INT_SET_ENABLE_FAIL_MASK (0x1U) +#define FLASH_INT_SET_ENABLE_FAIL_SHIFT (0U) +/*! FAIL - When a SET_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is set. + */ +#define FLASH_INT_SET_ENABLE_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_ENABLE_FAIL_SHIFT)) & FLASH_INT_SET_ENABLE_FAIL_MASK) + +#define FLASH_INT_SET_ENABLE_ERR_MASK (0x2U) +#define FLASH_INT_SET_ENABLE_ERR_SHIFT (1U) +/*! ERR - When a SET_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is set. + */ +#define FLASH_INT_SET_ENABLE_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_ENABLE_ERR_SHIFT)) & FLASH_INT_SET_ENABLE_ERR_MASK) + +#define FLASH_INT_SET_ENABLE_DONE_MASK (0x4U) +#define FLASH_INT_SET_ENABLE_DONE_SHIFT (2U) +/*! DONE - When a SET_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is set. + */ +#define FLASH_INT_SET_ENABLE_DONE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_ENABLE_DONE_SHIFT)) & FLASH_INT_SET_ENABLE_DONE_MASK) + +#define FLASH_INT_SET_ENABLE_ECC_ERR_MASK (0x8U) +#define FLASH_INT_SET_ENABLE_ECC_ERR_SHIFT (3U) +/*! ECC_ERR - When a SET_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is set. + */ +#define FLASH_INT_SET_ENABLE_ECC_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_ENABLE_ECC_ERR_SHIFT)) & FLASH_INT_SET_ENABLE_ECC_ERR_MASK) +/*! @} */ + +/*! @name INT_STATUS - Interrupt status bits */ +/*! @{ */ + +#define FLASH_INT_STATUS_FAIL_MASK (0x1U) +#define FLASH_INT_STATUS_FAIL_SHIFT (0U) +/*! FAIL - This status bit is set if execution of a (legal) command failed. + */ +#define FLASH_INT_STATUS_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_STATUS_FAIL_SHIFT)) & FLASH_INT_STATUS_FAIL_MASK) + +#define FLASH_INT_STATUS_ERR_MASK (0x2U) +#define FLASH_INT_STATUS_ERR_SHIFT (1U) +/*! ERR - This status bit is set if execution of an illegal command is detected. + */ +#define FLASH_INT_STATUS_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_STATUS_ERR_SHIFT)) & FLASH_INT_STATUS_ERR_MASK) + +#define FLASH_INT_STATUS_DONE_MASK (0x4U) +#define FLASH_INT_STATUS_DONE_SHIFT (2U) +/*! DONE - This status bit is set at the end of command execution. + */ +#define FLASH_INT_STATUS_DONE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_STATUS_DONE_SHIFT)) & FLASH_INT_STATUS_DONE_MASK) + +#define FLASH_INT_STATUS_ECC_ERR_MASK (0x8U) +#define FLASH_INT_STATUS_ECC_ERR_SHIFT (3U) +/*! ECC_ERR - This status bit is set if, during a memory read operation (either a user-requested + * read, or a speculative read, or reads performed by a controller command), a correctable or + * uncorrectable error is detected by ECC decoding logic. + */ +#define FLASH_INT_STATUS_ECC_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_STATUS_ECC_ERR_SHIFT)) & FLASH_INT_STATUS_ECC_ERR_MASK) +/*! @} */ + +/*! @name INT_ENABLE - Interrupt enable bits */ +/*! @{ */ + +#define FLASH_INT_ENABLE_FAIL_MASK (0x1U) +#define FLASH_INT_ENABLE_FAIL_SHIFT (0U) +/*! FAIL - If an INT_ENABLE bit is set, an interrupt request will be generated if the corresponding INT_STATUS bit is high. + */ +#define FLASH_INT_ENABLE_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_ENABLE_FAIL_SHIFT)) & FLASH_INT_ENABLE_FAIL_MASK) + +#define FLASH_INT_ENABLE_ERR_MASK (0x2U) +#define FLASH_INT_ENABLE_ERR_SHIFT (1U) +/*! ERR - If an INT_ENABLE bit is set, an interrupt request will be generated if the corresponding INT_STATUS bit is high. + */ +#define FLASH_INT_ENABLE_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_ENABLE_ERR_SHIFT)) & FLASH_INT_ENABLE_ERR_MASK) + +#define FLASH_INT_ENABLE_DONE_MASK (0x4U) +#define FLASH_INT_ENABLE_DONE_SHIFT (2U) +/*! DONE - If an INT_ENABLE bit is set, an interrupt request will be generated if the corresponding INT_STATUS bit is high. + */ +#define FLASH_INT_ENABLE_DONE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_ENABLE_DONE_SHIFT)) & FLASH_INT_ENABLE_DONE_MASK) + +#define FLASH_INT_ENABLE_ECC_ERR_MASK (0x8U) +#define FLASH_INT_ENABLE_ECC_ERR_SHIFT (3U) +/*! ECC_ERR - If an INT_ENABLE bit is set, an interrupt request will be generated if the corresponding INT_STATUS bit is high. + */ +#define FLASH_INT_ENABLE_ECC_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_ENABLE_ECC_ERR_SHIFT)) & FLASH_INT_ENABLE_ECC_ERR_MASK) +/*! @} */ + +/*! @name INT_CLR_STATUS - Clear interrupt status bits */ +/*! @{ */ + +#define FLASH_INT_CLR_STATUS_FAIL_MASK (0x1U) +#define FLASH_INT_CLR_STATUS_FAIL_SHIFT (0U) +/*! FAIL - When a CLR_STATUS bit is written to 1, the corresponding INT_STATUS bit is cleared. + */ +#define FLASH_INT_CLR_STATUS_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_STATUS_FAIL_SHIFT)) & FLASH_INT_CLR_STATUS_FAIL_MASK) + +#define FLASH_INT_CLR_STATUS_ERR_MASK (0x2U) +#define FLASH_INT_CLR_STATUS_ERR_SHIFT (1U) +/*! ERR - When a CLR_STATUS bit is written to 1, the corresponding INT_STATUS bit is cleared. + */ +#define FLASH_INT_CLR_STATUS_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_STATUS_ERR_SHIFT)) & FLASH_INT_CLR_STATUS_ERR_MASK) + +#define FLASH_INT_CLR_STATUS_DONE_MASK (0x4U) +#define FLASH_INT_CLR_STATUS_DONE_SHIFT (2U) +/*! DONE - When a CLR_STATUS bit is written to 1, the corresponding INT_STATUS bit is cleared. + */ +#define FLASH_INT_CLR_STATUS_DONE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_STATUS_DONE_SHIFT)) & FLASH_INT_CLR_STATUS_DONE_MASK) + +#define FLASH_INT_CLR_STATUS_ECC_ERR_MASK (0x8U) +#define FLASH_INT_CLR_STATUS_ECC_ERR_SHIFT (3U) +/*! ECC_ERR - When a CLR_STATUS bit is written to 1, the corresponding INT_STATUS bit is cleared. + */ +#define FLASH_INT_CLR_STATUS_ECC_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_STATUS_ECC_ERR_SHIFT)) & FLASH_INT_CLR_STATUS_ECC_ERR_MASK) +/*! @} */ + +/*! @name INT_SET_STATUS - Set interrupt status bits */ +/*! @{ */ + +#define FLASH_INT_SET_STATUS_FAIL_MASK (0x1U) +#define FLASH_INT_SET_STATUS_FAIL_SHIFT (0U) +/*! FAIL - When a SET_STATUS bit is written to 1, the corresponding INT_STATUS bit is set. + */ +#define FLASH_INT_SET_STATUS_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_STATUS_FAIL_SHIFT)) & FLASH_INT_SET_STATUS_FAIL_MASK) + +#define FLASH_INT_SET_STATUS_ERR_MASK (0x2U) +#define FLASH_INT_SET_STATUS_ERR_SHIFT (1U) +/*! ERR - When a SET_STATUS bit is written to 1, the corresponding INT_STATUS bit is set. + */ +#define FLASH_INT_SET_STATUS_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_STATUS_ERR_SHIFT)) & FLASH_INT_SET_STATUS_ERR_MASK) + +#define FLASH_INT_SET_STATUS_DONE_MASK (0x4U) +#define FLASH_INT_SET_STATUS_DONE_SHIFT (2U) +/*! DONE - When a SET_STATUS bit is written to 1, the corresponding INT_STATUS bit is set. + */ +#define FLASH_INT_SET_STATUS_DONE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_STATUS_DONE_SHIFT)) & FLASH_INT_SET_STATUS_DONE_MASK) + +#define FLASH_INT_SET_STATUS_ECC_ERR_MASK (0x8U) +#define FLASH_INT_SET_STATUS_ECC_ERR_SHIFT (3U) +/*! ECC_ERR - When a SET_STATUS bit is written to 1, the corresponding INT_STATUS bit is set. + */ +#define FLASH_INT_SET_STATUS_ECC_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_STATUS_ECC_ERR_SHIFT)) & FLASH_INT_SET_STATUS_ECC_ERR_MASK) +/*! @} */ + +/*! @name MODULE_ID - Controller+Memory module identification */ +/*! @{ */ + +#define FLASH_MODULE_ID_APERTURE_MASK (0xFFU) +#define FLASH_MODULE_ID_APERTURE_SHIFT (0U) +/*! APERTURE - Aperture i. + */ +#define FLASH_MODULE_ID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_MODULE_ID_APERTURE_SHIFT)) & FLASH_MODULE_ID_APERTURE_MASK) + +#define FLASH_MODULE_ID_MINOR_REV_MASK (0xF00U) +#define FLASH_MODULE_ID_MINOR_REV_SHIFT (8U) +/*! MINOR_REV - Minor revision i. + */ +#define FLASH_MODULE_ID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << FLASH_MODULE_ID_MINOR_REV_SHIFT)) & FLASH_MODULE_ID_MINOR_REV_MASK) + +#define FLASH_MODULE_ID_MAJOR_REV_MASK (0xF000U) +#define FLASH_MODULE_ID_MAJOR_REV_SHIFT (12U) +/*! MAJOR_REV - Major revision i. + */ +#define FLASH_MODULE_ID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << FLASH_MODULE_ID_MAJOR_REV_SHIFT)) & FLASH_MODULE_ID_MAJOR_REV_MASK) + +#define FLASH_MODULE_ID_ID_MASK (0xFFFF0000U) +#define FLASH_MODULE_ID_ID_SHIFT (16U) +/*! ID - Identifier. + */ +#define FLASH_MODULE_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_MODULE_ID_ID_SHIFT)) & FLASH_MODULE_ID_ID_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group FLASH_Register_Masks */ + + +/* FLASH - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral FLASH base address */ + #define FLASH_BASE (0x50034000u) + /** Peripheral FLASH base address */ + #define FLASH_BASE_NS (0x40034000u) + /** Peripheral FLASH base pointer */ + #define FLASH ((FLASH_Type *)FLASH_BASE) + /** Peripheral FLASH base pointer */ + #define FLASH_NS ((FLASH_Type *)FLASH_BASE_NS) + /** Array initializer of FLASH peripheral base addresses */ + #define FLASH_BASE_ADDRS { FLASH_BASE } + /** Array initializer of FLASH peripheral base pointers */ + #define FLASH_BASE_PTRS { FLASH } + /** Array initializer of FLASH peripheral base addresses */ + #define FLASH_BASE_ADDRS_NS { FLASH_BASE_NS } + /** Array initializer of FLASH peripheral base pointers */ + #define FLASH_BASE_PTRS_NS { FLASH_NS } +#else + /** Peripheral FLASH base address */ + #define FLASH_BASE (0x40034000u) + /** Peripheral FLASH base pointer */ + #define FLASH ((FLASH_Type *)FLASH_BASE) + /** Array initializer of FLASH peripheral base addresses */ + #define FLASH_BASE_ADDRS { FLASH_BASE } + /** Array initializer of FLASH peripheral base pointers */ + #define FLASH_BASE_PTRS { FLASH } +#endif + +/*! + * @} + */ /* end of group FLASH_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- FLASH_CFPA Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FLASH_CFPA_Peripheral_Access_Layer FLASH_CFPA Peripheral Access Layer + * @{ + */ + +/** FLASH_CFPA - Register Layout Typedef */ +typedef struct { + __IO uint32_t HEADER; /**< , offset: 0x0 */ + __IO uint32_t VERSION; /**< , offset: 0x4 */ + __IO uint32_t S_FW_VERSION; /**< Secure firmware version (Monotonic counter), offset: 0x8 */ + __IO uint32_t NS_FW_VERSION; /**< Non-Secure firmware version (Monotonic counter), offset: 0xC */ + __IO uint32_t IMAGE_KEY_REVOKE; /**< Image key revocation ID (Monotonic counter), offset: 0x10 */ + uint8_t RESERVED_0[4]; + __IO uint32_t ROTKH_REVOKE; /**< , offset: 0x18 */ + __IO uint32_t VENDOR_USAGE; /**< , offset: 0x1C */ + __IO uint32_t DCFG_CC_SOCU_PIN; /**< With TZ-M, the part can be sold by level 1 customers (secure code developer) to level-2 customers who develops non-secure code only. - In this scenario, or easy of development, Level-I customer releases the part to always allow non-secure debug. - To allow level-2 customers to further seal the part DCFG_CC_SOCU_NS is used. - ROM will use this word to further restrict the debug access., offset: 0x20 */ + __IO uint32_t DCFG_CC_SOCU_DFLT; /**< With TZ-M, the part can be sold by level 1 customers (secure code developer) to level-2 customers who develops non-secure code only. - In this scenario, or easy of development, Level-I customer releases the part to always allow non-secure debug. - To allow level-2 customers to further seal the part DCFG_CC_SOCU_NS is used. - ROM will use this word to further restrict the debug access., offset: 0x24 */ + __IO uint32_t ENABLE_FA_MODE; /**< Enable FA mode. SET_FA_MODE Command should write 0xC33CA55A to this word to indicate boot ROM to enter FA mode., offset: 0x28 */ + __IO uint32_t CMPA_PROG_IN_PROGRESS; /**< CMPA Page programming on going. This field shall be set to 0x5CC55AA5 in the active CFPA page each time CMPA page programming is going on. It shall always be set to 0x00000000 in the CFPA scratch area., offset: 0x2C */ + union { /* offset: 0x30 */ + __IO uint32_t PRINCE_REGION0_IV_CODE[14]; /**< , array offset: 0x30, array step: 0x4 */ + struct { /* offset: 0x30 */ + __IO uint32_t PRINCE_REGION0_IV_HEADER0; /**< , offset: 0x30 */ + __IO uint32_t PRINCE_REGION0_IV_HEADER1; /**< , offset: 0x34 */ + __IO uint32_t PRINCE_REGION0_IV_BODY[12]; /**< , array offset: 0x38, array step: 0x4 */ + } PRINCE_REGION0_IV_CODE_CORE; + }; + union { /* offset: 0x68 */ + __IO uint32_t PRINCE_REGION1_IV_CODE[14]; /**< , array offset: 0x68, array step: 0x4 */ + struct { /* offset: 0x68 */ + __IO uint32_t PRINCE_REGION1_IV_HEADER0; /**< , offset: 0x68 */ + __IO uint32_t PRINCE_REGION1_IV_HEADER1; /**< , offset: 0x6C */ + __IO uint32_t PRINCE_REGION1_IV_BODY[12]; /**< , array offset: 0x70, array step: 0x4 */ + } PRINCE_REGION1_IV_CODE_CORE; + }; + union { /* offset: 0xA0 */ + __IO uint32_t PRINCE_REGION2_IV_CODE[14]; /**< , array offset: 0xA0, array step: 0x4 */ + struct { /* offset: 0xA0 */ + __IO uint32_t PRINCE_REGION2_IV_HEADER0; /**< , offset: 0xA0 */ + __IO uint32_t PRINCE_REGION2_IV_HEADER1; /**< , offset: 0xA4 */ + __IO uint32_t PRINCE_REGION2_IV_BODY[12]; /**< , array offset: 0xA8, array step: 0x4 */ + } PRINCE_REGION2_IV_CODE_CORE; + }; + uint8_t RESERVED_1[40]; + __IO uint32_t CUSTOMER_DEFINED[56]; /**< Customer Defined (Programable through ROM API), array offset: 0x100, array step: 0x4 */ + __IO uint32_t SHA256_DIGEST[8]; /**< SHA256_DIGEST0 for DIGEST[31:0]..SHA256_DIGEST7 for DIGEST[255:224], array offset: 0x1E0, array step: 0x4 */ +} FLASH_CFPA_Type; + +/* ---------------------------------------------------------------------------- + -- FLASH_CFPA Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FLASH_CFPA_Register_Masks FLASH_CFPA Register Masks + * @{ + */ + +/*! @name HEADER - */ +/*! @{ */ + +#define FLASH_CFPA_HEADER_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CFPA_HEADER_FIELD_SHIFT (0U) +#define FLASH_CFPA_HEADER_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_HEADER_FIELD_SHIFT)) & FLASH_CFPA_HEADER_FIELD_MASK) +/*! @} */ + +/*! @name VERSION - */ +/*! @{ */ + +#define FLASH_CFPA_VERSION_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CFPA_VERSION_FIELD_SHIFT (0U) +#define FLASH_CFPA_VERSION_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_VERSION_FIELD_SHIFT)) & FLASH_CFPA_VERSION_FIELD_MASK) +/*! @} */ + +/*! @name S_FW_VERSION - Secure firmware version (Monotonic counter) */ +/*! @{ */ + +#define FLASH_CFPA_S_FW_VERSION_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CFPA_S_FW_VERSION_FIELD_SHIFT (0U) +#define FLASH_CFPA_S_FW_VERSION_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_S_FW_VERSION_FIELD_SHIFT)) & FLASH_CFPA_S_FW_VERSION_FIELD_MASK) +/*! @} */ + +/*! @name NS_FW_VERSION - Non-Secure firmware version (Monotonic counter) */ +/*! @{ */ + +#define FLASH_CFPA_NS_FW_VERSION_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CFPA_NS_FW_VERSION_FIELD_SHIFT (0U) +#define FLASH_CFPA_NS_FW_VERSION_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_NS_FW_VERSION_FIELD_SHIFT)) & FLASH_CFPA_NS_FW_VERSION_FIELD_MASK) +/*! @} */ + +/*! @name IMAGE_KEY_REVOKE - Image key revocation ID (Monotonic counter) */ +/*! @{ */ + +#define FLASH_CFPA_IMAGE_KEY_REVOKE_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CFPA_IMAGE_KEY_REVOKE_FIELD_SHIFT (0U) +#define FLASH_CFPA_IMAGE_KEY_REVOKE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_IMAGE_KEY_REVOKE_FIELD_SHIFT)) & FLASH_CFPA_IMAGE_KEY_REVOKE_FIELD_MASK) +/*! @} */ + +/*! @name ROTKH_REVOKE - */ +/*! @{ */ + +#define FLASH_CFPA_ROTKH_REVOKE_RoTK0_EN_MASK (0x3U) +#define FLASH_CFPA_ROTKH_REVOKE_RoTK0_EN_SHIFT (0U) +/*! RoTK0_EN - RoT Key 0 enable. 00 - Invalid 01 - Enabled 10, 11 - Key revoked + */ +#define FLASH_CFPA_ROTKH_REVOKE_RoTK0_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_ROTKH_REVOKE_RoTK0_EN_SHIFT)) & FLASH_CFPA_ROTKH_REVOKE_RoTK0_EN_MASK) + +#define FLASH_CFPA_ROTKH_REVOKE_RoTK1_EN_MASK (0xCU) +#define FLASH_CFPA_ROTKH_REVOKE_RoTK1_EN_SHIFT (2U) +/*! RoTK1_EN - RoT Key 1 enable. 00 - Invalid 01 - Enabled 10, 11 - Key revoked + */ +#define FLASH_CFPA_ROTKH_REVOKE_RoTK1_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_ROTKH_REVOKE_RoTK1_EN_SHIFT)) & FLASH_CFPA_ROTKH_REVOKE_RoTK1_EN_MASK) + +#define FLASH_CFPA_ROTKH_REVOKE_RoTK2_EN_MASK (0x30U) +#define FLASH_CFPA_ROTKH_REVOKE_RoTK2_EN_SHIFT (4U) +/*! RoTK2_EN - RoT Key 2 enable. 00 - Invalid 01 - Enabled 10, 11 - Key revoked + */ +#define FLASH_CFPA_ROTKH_REVOKE_RoTK2_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_ROTKH_REVOKE_RoTK2_EN_SHIFT)) & FLASH_CFPA_ROTKH_REVOKE_RoTK2_EN_MASK) + +#define FLASH_CFPA_ROTKH_REVOKE_RoTK3_EN_MASK (0xC0U) +#define FLASH_CFPA_ROTKH_REVOKE_RoTK3_EN_SHIFT (6U) +/*! RoTK3_EN - RoT Key 3 enable. 00 - Invalid 01 - Enabled 10, 11 - Key revoked + */ +#define FLASH_CFPA_ROTKH_REVOKE_RoTK3_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_ROTKH_REVOKE_RoTK3_EN_SHIFT)) & FLASH_CFPA_ROTKH_REVOKE_RoTK3_EN_MASK) +/*! @} */ + +/*! @name VENDOR_USAGE - */ +/*! @{ */ + +#define FLASH_CFPA_VENDOR_USAGE_DBG_VENDOR_USAGE_MASK (0xFFFFU) +#define FLASH_CFPA_VENDOR_USAGE_DBG_VENDOR_USAGE_SHIFT (0U) +/*! DBG_VENDOR_USAGE - DBG_VENDOR_USAGE. + */ +#define FLASH_CFPA_VENDOR_USAGE_DBG_VENDOR_USAGE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_VENDOR_USAGE_DBG_VENDOR_USAGE_SHIFT)) & FLASH_CFPA_VENDOR_USAGE_DBG_VENDOR_USAGE_MASK) + +#define FLASH_CFPA_VENDOR_USAGE_INVERSE_VALUE_MASK (0xFFFF0000U) +#define FLASH_CFPA_VENDOR_USAGE_INVERSE_VALUE_SHIFT (16U) +/*! INVERSE_VALUE - inverse value of bits [15:0] + */ +#define FLASH_CFPA_VENDOR_USAGE_INVERSE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_VENDOR_USAGE_INVERSE_VALUE_SHIFT)) & FLASH_CFPA_VENDOR_USAGE_INVERSE_VALUE_MASK) +/*! @} */ + +/*! @name DCFG_CC_SOCU_PIN - With TZ-M, the part can be sold by level 1 customers (secure code developer) to level-2 customers who develops non-secure code only. - In this scenario, or easy of development, Level-I customer releases the part to always allow non-secure debug. - To allow level-2 customers to further seal the part DCFG_CC_SOCU_NS is used. - ROM will use this word to further restrict the debug access. */ +/*! @{ */ + +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_NIDEN_MASK (0x1U) +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_NIDEN_SHIFT (0U) +/*! NIDEN - Non Secure non-invasive debug enable + * 0b0..Use DAP to enable + * 0b1..Fixed state + */ +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_NIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_NIDEN_MASK) + +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_DBGEN_MASK (0x2U) +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_DBGEN_SHIFT (1U) +/*! DBGEN - Non Secure debug enable + * 0b0..Use DAP to enable + * 0b1..Fixed state + */ +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_DBGEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_DBGEN_MASK) + +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_SPNIDEN_MASK (0x4U) +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_SPNIDEN_SHIFT (2U) +/*! SPNIDEN - Secure non-invasive debug enable + * 0b0..Use DAP to enable + * 0b1..Fixed state + */ +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_SPNIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_SPNIDEN_MASK) + +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_SPIDEN_MASK (0x8U) +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_SPIDEN_SHIFT (3U) +/*! SPIDEN - Secure invasive debug enable + * 0b0..Use DAP to enable + * 0b1..Fixed state + */ +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_SPIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_SPIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_SPIDEN_MASK) + +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_TAPEN_MASK (0x10U) +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_TAPEN_SHIFT (4U) +/*! TAPEN - JTAG TAP enable + * 0b0..Use DAP to enable + * 0b1..Fixed state + */ +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_TAPEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_TAPEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_TAPEN_MASK) + +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_ISP_CMD_EN_MASK (0x40U) +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_ISP_CMD_EN_SHIFT (6U) +/*! ISP_CMD_EN - ISP Boot Command enable + * 0b0..Use DAP to enable + * 0b1..Fixed state + */ +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_ISP_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_ISP_CMD_EN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_ISP_CMD_EN_MASK) + +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_FA_ME_CMD_EN_MASK (0x80U) +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_FA_ME_CMD_EN_SHIFT (7U) +/*! FA_ME_CMD_EN - FA Command enable + * 0b0..Use DAP to enable + * 0b1..Fixed state + */ +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_FA_ME_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_FA_ME_CMD_EN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_FA_ME_CMD_EN_MASK) + +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_UUID_CHECK_MASK (0x8000U) +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_UUID_CHECK_SHIFT (15U) +/*! UUID_CHECK - Enforce UUID match during Debug authentication. + */ +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_UUID_CHECK(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_UUID_CHECK_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_UUID_CHECK_MASK) + +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_INVERSE_VALUE_MASK (0xFFFF0000U) +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_INVERSE_VALUE_SHIFT (16U) +/*! INVERSE_VALUE - inverse value of bits [15:0] + */ +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_INVERSE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_INVERSE_VALUE_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_INVERSE_VALUE_MASK) +/*! @} */ + +/*! @name DCFG_CC_SOCU_DFLT - With TZ-M, the part can be sold by level 1 customers (secure code developer) to level-2 customers who develops non-secure code only. - In this scenario, or easy of development, Level-I customer releases the part to always allow non-secure debug. - To allow level-2 customers to further seal the part DCFG_CC_SOCU_NS is used. - ROM will use this word to further restrict the debug access. */ +/*! @{ */ + +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_NIDEN_MASK (0x1U) +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_NIDEN_SHIFT (0U) +/*! NIDEN - Non Secure non-invasive debug fixed state + * 0b0..Disable + * 0b1..Enable + */ +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_NIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_NIDEN_MASK) + +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_DBGEN_MASK (0x2U) +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_DBGEN_SHIFT (1U) +/*! DBGEN - Non Secure debug fixed state + * 0b0..Disable + * 0b1..Enable + */ +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_DBGEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_DBGEN_MASK) + +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPNIDEN_MASK (0x4U) +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPNIDEN_SHIFT (2U) +/*! SPNIDEN - Secure non-invasive debug fixed state + * 0b0..Disable + * 0b1..Enable + */ +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPNIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPNIDEN_MASK) + +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPIDEN_MASK (0x8U) +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPIDEN_SHIFT (3U) +/*! SPIDEN - Secure invasive debug fixed state + * 0b0..Disable + * 0b1..Enable + */ +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPIDEN_MASK) + +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_TAPEN_MASK (0x10U) +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_TAPEN_SHIFT (4U) +/*! TAPEN - JTAG TAP fixed state + * 0b0..Disable + * 0b1..Enable + */ +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_TAPEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_TAPEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_TAPEN_MASK) + +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_ISP_CMD_EN_MASK (0x40U) +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_ISP_CMD_EN_SHIFT (6U) +/*! ISP_CMD_EN - ISP Boot Command fixed state + * 0b0..Disable + * 0b1..Enable + */ +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_ISP_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_ISP_CMD_EN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_ISP_CMD_EN_MASK) + +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_FA_ME_CMD_EN_MASK (0x80U) +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_FA_ME_CMD_EN_SHIFT (7U) +/*! FA_ME_CMD_EN - FA Command fixed state + * 0b0..Disable + * 0b1..Enable + */ +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_FA_ME_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_FA_ME_CMD_EN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_FA_ME_CMD_EN_MASK) + +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_INVERSE_VALUE_MASK (0xFFFF0000U) +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_INVERSE_VALUE_SHIFT (16U) +/*! INVERSE_VALUE - inverse value of bits [15:0] + */ +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_INVERSE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_INVERSE_VALUE_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_INVERSE_VALUE_MASK) +/*! @} */ + +/*! @name ENABLE_FA_MODE - Enable FA mode. SET_FA_MODE Command should write 0xC33CA55A to this word to indicate boot ROM to enter FA mode. */ +/*! @{ */ + +#define FLASH_CFPA_ENABLE_FA_MODE_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CFPA_ENABLE_FA_MODE_FIELD_SHIFT (0U) +#define FLASH_CFPA_ENABLE_FA_MODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_ENABLE_FA_MODE_FIELD_SHIFT)) & FLASH_CFPA_ENABLE_FA_MODE_FIELD_MASK) +/*! @} */ + +/*! @name CMPA_PROG_IN_PROGRESS - CMPA Page programming on going. This field shall be set to 0x5CC55AA5 in the active CFPA page each time CMPA page programming is going on. It shall always be set to 0x00000000 in the CFPA scratch area. */ +/*! @{ */ + +#define FLASH_CFPA_CMPA_PROG_IN_PROGRESS_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CFPA_CMPA_PROG_IN_PROGRESS_FIELD_SHIFT (0U) +#define FLASH_CFPA_CMPA_PROG_IN_PROGRESS_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_CMPA_PROG_IN_PROGRESS_FIELD_SHIFT)) & FLASH_CFPA_CMPA_PROG_IN_PROGRESS_FIELD_MASK) +/*! @} */ + +/*! @name PRINCE_REGION0_IV_CODE - */ +/*! @{ */ + +#define FLASH_CFPA_PRINCE_REGION0_IV_CODE_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CFPA_PRINCE_REGION0_IV_CODE_FIELD_SHIFT (0U) +#define FLASH_CFPA_PRINCE_REGION0_IV_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION0_IV_CODE_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION0_IV_CODE_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_CFPA_PRINCE_REGION0_IV_CODE */ +#define FLASH_CFPA_PRINCE_REGION0_IV_CODE_COUNT (14U) + +/*! @name PRINCE_REGION0_IV_HEADER0 - */ +/*! @{ */ + +#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER0_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER0_FIELD_SHIFT (0U) +#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION0_IV_HEADER0_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION0_IV_HEADER0_FIELD_MASK) +/*! @} */ + +/*! @name PRINCE_REGION0_IV_HEADER1 - */ +/*! @{ */ + +#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_TYPE_MASK (0x3U) +#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_TYPE_SHIFT (0U) +#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_TYPE_SHIFT)) & FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_TYPE_MASK) + +#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_INDEX_MASK (0xF00U) +#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_INDEX_SHIFT (8U) +#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_INDEX_SHIFT)) & FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_INDEX_MASK) + +#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_SIZE_MASK (0x3F000000U) +#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_SIZE_SHIFT (24U) +#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_SIZE_SHIFT)) & FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_SIZE_MASK) +/*! @} */ + +/*! @name PRINCE_REGION0_IV_BODY - */ +/*! @{ */ + +#define FLASH_CFPA_PRINCE_REGION0_IV_BODY_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CFPA_PRINCE_REGION0_IV_BODY_FIELD_SHIFT (0U) +#define FLASH_CFPA_PRINCE_REGION0_IV_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION0_IV_BODY_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION0_IV_BODY_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_CFPA_PRINCE_REGION0_IV_BODY */ +#define FLASH_CFPA_PRINCE_REGION0_IV_BODY_COUNT (12U) + +/*! @name PRINCE_REGION1_IV_CODE - */ +/*! @{ */ + +#define FLASH_CFPA_PRINCE_REGION1_IV_CODE_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CFPA_PRINCE_REGION1_IV_CODE_FIELD_SHIFT (0U) +#define FLASH_CFPA_PRINCE_REGION1_IV_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION1_IV_CODE_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION1_IV_CODE_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_CFPA_PRINCE_REGION1_IV_CODE */ +#define FLASH_CFPA_PRINCE_REGION1_IV_CODE_COUNT (14U) + +/*! @name PRINCE_REGION1_IV_HEADER0 - */ +/*! @{ */ + +#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER0_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER0_FIELD_SHIFT (0U) +#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION1_IV_HEADER0_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION1_IV_HEADER0_FIELD_MASK) +/*! @} */ + +/*! @name PRINCE_REGION1_IV_HEADER1 - */ +/*! @{ */ + +#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_TYPE_MASK (0x3U) +#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_TYPE_SHIFT (0U) +#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_TYPE_SHIFT)) & FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_TYPE_MASK) + +#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_INDEX_MASK (0xF00U) +#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_INDEX_SHIFT (8U) +#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_INDEX_SHIFT)) & FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_INDEX_MASK) + +#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_SIZE_MASK (0x3F000000U) +#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_SIZE_SHIFT (24U) +#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_SIZE_SHIFT)) & FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_SIZE_MASK) +/*! @} */ + +/*! @name PRINCE_REGION1_IV_BODY - */ +/*! @{ */ + +#define FLASH_CFPA_PRINCE_REGION1_IV_BODY_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CFPA_PRINCE_REGION1_IV_BODY_FIELD_SHIFT (0U) +#define FLASH_CFPA_PRINCE_REGION1_IV_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION1_IV_BODY_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION1_IV_BODY_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_CFPA_PRINCE_REGION1_IV_BODY */ +#define FLASH_CFPA_PRINCE_REGION1_IV_BODY_COUNT (12U) + +/*! @name PRINCE_REGION2_IV_CODE - */ +/*! @{ */ + +#define FLASH_CFPA_PRINCE_REGION2_IV_CODE_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CFPA_PRINCE_REGION2_IV_CODE_FIELD_SHIFT (0U) +#define FLASH_CFPA_PRINCE_REGION2_IV_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION2_IV_CODE_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION2_IV_CODE_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_CFPA_PRINCE_REGION2_IV_CODE */ +#define FLASH_CFPA_PRINCE_REGION2_IV_CODE_COUNT (14U) + +/*! @name PRINCE_REGION2_IV_HEADER0 - */ +/*! @{ */ + +#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER0_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER0_FIELD_SHIFT (0U) +#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION2_IV_HEADER0_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION2_IV_HEADER0_FIELD_MASK) +/*! @} */ + +/*! @name PRINCE_REGION2_IV_HEADER1 - */ +/*! @{ */ + +#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_TYPE_MASK (0x3U) +#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_TYPE_SHIFT (0U) +#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_TYPE_SHIFT)) & FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_TYPE_MASK) + +#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_INDEX_MASK (0xF00U) +#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_INDEX_SHIFT (8U) +#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_INDEX_SHIFT)) & FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_INDEX_MASK) + +#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_SIZE_MASK (0x3F000000U) +#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_SIZE_SHIFT (24U) +#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_SIZE_SHIFT)) & FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_SIZE_MASK) +/*! @} */ + +/*! @name PRINCE_REGION2_IV_BODY - */ +/*! @{ */ + +#define FLASH_CFPA_PRINCE_REGION2_IV_BODY_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CFPA_PRINCE_REGION2_IV_BODY_FIELD_SHIFT (0U) +#define FLASH_CFPA_PRINCE_REGION2_IV_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION2_IV_BODY_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION2_IV_BODY_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_CFPA_PRINCE_REGION2_IV_BODY */ +#define FLASH_CFPA_PRINCE_REGION2_IV_BODY_COUNT (12U) + +/*! @name CUSTOMER_DEFINED - Customer Defined (Programable through ROM API) */ +/*! @{ */ + +#define FLASH_CFPA_CUSTOMER_DEFINED_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CFPA_CUSTOMER_DEFINED_FIELD_SHIFT (0U) +#define FLASH_CFPA_CUSTOMER_DEFINED_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_CUSTOMER_DEFINED_FIELD_SHIFT)) & FLASH_CFPA_CUSTOMER_DEFINED_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_CFPA_CUSTOMER_DEFINED */ +#define FLASH_CFPA_CUSTOMER_DEFINED_COUNT (56U) + +/*! @name SHA256_DIGEST - SHA256_DIGEST0 for DIGEST[31:0]..SHA256_DIGEST7 for DIGEST[255:224] */ +/*! @{ */ + +#define FLASH_CFPA_SHA256_DIGEST_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CFPA_SHA256_DIGEST_FIELD_SHIFT (0U) +#define FLASH_CFPA_SHA256_DIGEST_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_SHA256_DIGEST_FIELD_SHIFT)) & FLASH_CFPA_SHA256_DIGEST_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_CFPA_SHA256_DIGEST */ +#define FLASH_CFPA_SHA256_DIGEST_COUNT (8U) + + +/*! + * @} + */ /* end of group FLASH_CFPA_Register_Masks */ + + +/* FLASH_CFPA - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral FLASH_CFPA0 base address */ + #define FLASH_CFPA0_BASE (0x1003E000u) + /** Peripheral FLASH_CFPA0 base address */ + #define FLASH_CFPA0_BASE_NS (0x3E000u) + /** Peripheral FLASH_CFPA0 base pointer */ + #define FLASH_CFPA0 ((FLASH_CFPA_Type *)FLASH_CFPA0_BASE) + /** Peripheral FLASH_CFPA0 base pointer */ + #define FLASH_CFPA0_NS ((FLASH_CFPA_Type *)FLASH_CFPA0_BASE_NS) + /** Peripheral FLASH_CFPA1 base address */ + #define FLASH_CFPA1_BASE (0x1003E200u) + /** Peripheral FLASH_CFPA1 base address */ + #define FLASH_CFPA1_BASE_NS (0x3E200u) + /** Peripheral FLASH_CFPA1 base pointer */ + #define FLASH_CFPA1 ((FLASH_CFPA_Type *)FLASH_CFPA1_BASE) + /** Peripheral FLASH_CFPA1 base pointer */ + #define FLASH_CFPA1_NS ((FLASH_CFPA_Type *)FLASH_CFPA1_BASE_NS) + /** Peripheral FLASH_CFPA_SCRATCH base address */ + #define FLASH_CFPA_SCRATCH_BASE (0x1003DE00u) + /** Peripheral FLASH_CFPA_SCRATCH base address */ + #define FLASH_CFPA_SCRATCH_BASE_NS (0x3DE00u) + /** Peripheral FLASH_CFPA_SCRATCH base pointer */ + #define FLASH_CFPA_SCRATCH ((FLASH_CFPA_Type *)FLASH_CFPA_SCRATCH_BASE) + /** Peripheral FLASH_CFPA_SCRATCH base pointer */ + #define FLASH_CFPA_SCRATCH_NS ((FLASH_CFPA_Type *)FLASH_CFPA_SCRATCH_BASE_NS) + /** Array initializer of FLASH_CFPA peripheral base addresses */ + #define FLASH_CFPA_BASE_ADDRS { FLASH_CFPA0_BASE, FLASH_CFPA1_BASE, FLASH_CFPA_SCRATCH_BASE } + /** Array initializer of FLASH_CFPA peripheral base pointers */ + #define FLASH_CFPA_BASE_PTRS { FLASH_CFPA0, FLASH_CFPA1, FLASH_CFPA_SCRATCH } + /** Array initializer of FLASH_CFPA peripheral base addresses */ + #define FLASH_CFPA_BASE_ADDRS_NS { FLASH_CFPA0_BASE_NS, FLASH_CFPA1_BASE_NS, FLASH_CFPA_SCRATCH_BASE_NS } + /** Array initializer of FLASH_CFPA peripheral base pointers */ + #define FLASH_CFPA_BASE_PTRS_NS { FLASH_CFPA0_NS, FLASH_CFPA1_NS, FLASH_CFPA_SCRATCH_NS } +#else + /** Peripheral FLASH_CFPA0 base address */ + #define FLASH_CFPA0_BASE (0x3E000u) + /** Peripheral FLASH_CFPA0 base pointer */ + #define FLASH_CFPA0 ((FLASH_CFPA_Type *)FLASH_CFPA0_BASE) + /** Peripheral FLASH_CFPA1 base address */ + #define FLASH_CFPA1_BASE (0x3E200u) + /** Peripheral FLASH_CFPA1 base pointer */ + #define FLASH_CFPA1 ((FLASH_CFPA_Type *)FLASH_CFPA1_BASE) + /** Peripheral FLASH_CFPA_SCRATCH base address */ + #define FLASH_CFPA_SCRATCH_BASE (0x3DE00u) + /** Peripheral FLASH_CFPA_SCRATCH base pointer */ + #define FLASH_CFPA_SCRATCH ((FLASH_CFPA_Type *)FLASH_CFPA_SCRATCH_BASE) + /** Array initializer of FLASH_CFPA peripheral base addresses */ + #define FLASH_CFPA_BASE_ADDRS { FLASH_CFPA0_BASE, FLASH_CFPA1_BASE, FLASH_CFPA_SCRATCH_BASE } + /** Array initializer of FLASH_CFPA peripheral base pointers */ + #define FLASH_CFPA_BASE_PTRS { FLASH_CFPA0, FLASH_CFPA1, FLASH_CFPA_SCRATCH } +#endif + +/*! + * @} + */ /* end of group FLASH_CFPA_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- FLASH_CMPA Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FLASH_CMPA_Peripheral_Access_Layer FLASH_CMPA Peripheral Access Layer + * @{ + */ + +/** FLASH_CMPA - Register Layout Typedef */ +typedef struct { + __IO uint32_t BOOT_CFG; /**< , offset: 0x0 */ + __IO uint32_t SPI_FLASH_CFG; /**< , offset: 0x4 */ + __IO uint32_t USB_ID; /**< , offset: 0x8 */ + __IO uint32_t SDIO_CFG; /**< , offset: 0xC */ + __IO uint32_t CC_SOCU_PIN; /**< , offset: 0x10 */ + __IO uint32_t CC_SOCU_DFLT; /**< , offset: 0x14 */ + __IO uint32_t VENDOR_USAGE; /**< , offset: 0x18 */ + __IO uint32_t SECURE_BOOT_CFG; /**< Secure boot configuration flags., offset: 0x1C */ + __IO uint32_t PRINCE_BASE_ADDR; /**< , offset: 0x20 */ + __IO uint32_t PRINCE_SR_0; /**< Region 0, sub-region enable, offset: 0x24 */ + __IO uint32_t PRINCE_SR_1; /**< Region 1, sub-region enable, offset: 0x28 */ + __IO uint32_t PRINCE_SR_2; /**< Region 2, sub-region enable, offset: 0x2C */ + __IO uint32_t XTAL_32KHZ_CAPABANK_TRIM; /**< Xtal 32kHz capabank triming., offset: 0x30 */ + __IO uint32_t XTAL_16MHZ_CAPABANK_TRIM; /**< Xtal 16MHz capabank triming., offset: 0x34 */ + __IO uint32_t FLASH_REMAP_SIZE; /**< This 32-bit register contains the size of the image to remap, in bytes. The 12 LSBs are ignored, so the size granularity is 4KB., offset: 0x38 */ + __IO uint32_t FLASH_REMAP_OFFSET; /**< This 32-bit register contains the offset by which the image is to be remapped. The 12 LSBs are ignored, so the remap granularity is 4KB., offset: 0x3C */ + uint8_t RESERVED_0[16]; + __IO uint32_t ROTKH[8]; /**< ROTKH0 for Root of Trust Keys Table hash[255:224]..ROTKH7 for Root of Trust Keys Table hash[31:0], array offset: 0x50, array step: 0x4 */ + uint8_t RESERVED_1[144]; + __IO uint32_t CUSTOMER_DEFINED[56]; /**< Customer Defined (Programable through ROM API), array offset: 0x100, array step: 0x4 */ + __IO uint32_t SHA256_DIGEST[8]; /**< SHA256_DIGEST0 for DIGEST[31:0]..SHA256_DIGEST7 for DIGEST[255:224], array offset: 0x1E0, array step: 0x4 */ +} FLASH_CMPA_Type; + +/* ---------------------------------------------------------------------------- + -- FLASH_CMPA Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FLASH_CMPA_Register_Masks FLASH_CMPA Register Masks + * @{ + */ + +/*! @name BOOT_CFG - */ +/*! @{ */ + +#define FLASH_CMPA_BOOT_CFG_DEFAULT_ISP_MODE_MASK (0x70U) +#define FLASH_CMPA_BOOT_CFG_DEFAULT_ISP_MODE_SHIFT (4U) +/*! DEFAULT_ISP_MODE - Default ISP mode: + * 0b000..Auto ISP + * 0b001..USB_HID_ISP + * 0b010..UART ISP + * 0b011..SPI Slave ISP + * 0b100..I2C Slave ISP + * 0b111..Disable ISP fall through + */ +#define FLASH_CMPA_BOOT_CFG_DEFAULT_ISP_MODE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_BOOT_CFG_DEFAULT_ISP_MODE_SHIFT)) & FLASH_CMPA_BOOT_CFG_DEFAULT_ISP_MODE_MASK) + +#define FLASH_CMPA_BOOT_CFG_BOOT_SPEED_MASK (0x180U) +#define FLASH_CMPA_BOOT_CFG_BOOT_SPEED_SHIFT (7U) +/*! BOOT_SPEED - Core clock: + * 0b00..Defined by NMPA.SYSTEM_SPEED_CODE + * 0b10..48MHz FRO + */ +#define FLASH_CMPA_BOOT_CFG_BOOT_SPEED(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_BOOT_CFG_BOOT_SPEED_SHIFT)) & FLASH_CMPA_BOOT_CFG_BOOT_SPEED_MASK) + +#define FLASH_CMPA_BOOT_CFG_BOOT_FAILURE_PIN_MASK (0xFF000000U) +#define FLASH_CMPA_BOOT_CFG_BOOT_FAILURE_PIN_SHIFT (24U) +/*! BOOT_FAILURE_PIN - GPIO port and pin number to use for indicating failure reason. The toggle + * rate of the pin is used to decode the error type. [2:0] - Defines GPIO port [7:3] - Defines GPIO + * pin + */ +#define FLASH_CMPA_BOOT_CFG_BOOT_FAILURE_PIN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_BOOT_CFG_BOOT_FAILURE_PIN_SHIFT)) & FLASH_CMPA_BOOT_CFG_BOOT_FAILURE_PIN_MASK) +/*! @} */ + +/*! @name SPI_FLASH_CFG - */ +/*! @{ */ + +#define FLASH_CMPA_SPI_FLASH_CFG_SPI_RECOVERY_BOOT_EN_MASK (0x1FU) +#define FLASH_CMPA_SPI_FLASH_CFG_SPI_RECOVERY_BOOT_EN_SHIFT (0U) +/*! SPI_RECOVERY_BOOT_EN - SPI flash recovery boot is enabled, if non-zero value is written to this field. + */ +#define FLASH_CMPA_SPI_FLASH_CFG_SPI_RECOVERY_BOOT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SPI_FLASH_CFG_SPI_RECOVERY_BOOT_EN_SHIFT)) & FLASH_CMPA_SPI_FLASH_CFG_SPI_RECOVERY_BOOT_EN_MASK) +/*! @} */ + +/*! @name USB_ID - */ +/*! @{ */ + +#define FLASH_CMPA_USB_ID_USB_VENDOR_ID_MASK (0xFFFFU) +#define FLASH_CMPA_USB_ID_USB_VENDOR_ID_SHIFT (0U) +#define FLASH_CMPA_USB_ID_USB_VENDOR_ID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_USB_ID_USB_VENDOR_ID_SHIFT)) & FLASH_CMPA_USB_ID_USB_VENDOR_ID_MASK) + +#define FLASH_CMPA_USB_ID_USB_PRODUCT_ID_MASK (0xFFFF0000U) +#define FLASH_CMPA_USB_ID_USB_PRODUCT_ID_SHIFT (16U) +#define FLASH_CMPA_USB_ID_USB_PRODUCT_ID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_USB_ID_USB_PRODUCT_ID_SHIFT)) & FLASH_CMPA_USB_ID_USB_PRODUCT_ID_MASK) +/*! @} */ + +/*! @name SDIO_CFG - */ +/*! @{ */ + +#define FLASH_CMPA_SDIO_CFG_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CMPA_SDIO_CFG_FIELD_SHIFT (0U) +#define FLASH_CMPA_SDIO_CFG_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SDIO_CFG_FIELD_SHIFT)) & FLASH_CMPA_SDIO_CFG_FIELD_MASK) +/*! @} */ + +/*! @name CC_SOCU_PIN - */ +/*! @{ */ + +#define FLASH_CMPA_CC_SOCU_PIN_NIDEN_MASK (0x1U) +#define FLASH_CMPA_CC_SOCU_PIN_NIDEN_SHIFT (0U) +/*! NIDEN - Non Secure non-invasive debug enable + * 0b0..Use DAP to enable + * 0b1..Fixed state + */ +#define FLASH_CMPA_CC_SOCU_PIN_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_NIDEN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_NIDEN_MASK) + +#define FLASH_CMPA_CC_SOCU_PIN_DBGEN_MASK (0x2U) +#define FLASH_CMPA_CC_SOCU_PIN_DBGEN_SHIFT (1U) +/*! DBGEN - Non Secure debug enable + * 0b0..Use DAP to enable + * 0b1..Fixed state + */ +#define FLASH_CMPA_CC_SOCU_PIN_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_DBGEN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_DBGEN_MASK) + +#define FLASH_CMPA_CC_SOCU_PIN_SPNIDEN_MASK (0x4U) +#define FLASH_CMPA_CC_SOCU_PIN_SPNIDEN_SHIFT (2U) +/*! SPNIDEN - Secure non-invasive debug enable + * 0b0..Use DAP to enable + * 0b1..Fixed state + */ +#define FLASH_CMPA_CC_SOCU_PIN_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_SPNIDEN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_SPNIDEN_MASK) + +#define FLASH_CMPA_CC_SOCU_PIN_SPIDEN_MASK (0x8U) +#define FLASH_CMPA_CC_SOCU_PIN_SPIDEN_SHIFT (3U) +/*! SPIDEN - Secure invasive debug enable + * 0b0..Use DAP to enable + * 0b1..Fixed state + */ +#define FLASH_CMPA_CC_SOCU_PIN_SPIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_SPIDEN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_SPIDEN_MASK) + +#define FLASH_CMPA_CC_SOCU_PIN_TAPEN_MASK (0x10U) +#define FLASH_CMPA_CC_SOCU_PIN_TAPEN_SHIFT (4U) +/*! TAPEN - JTAG TAP enable + * 0b0..Use DAP to enable + * 0b1..Fixed state + */ +#define FLASH_CMPA_CC_SOCU_PIN_TAPEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_TAPEN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_TAPEN_MASK) + +#define FLASH_CMPA_CC_SOCU_PIN_ISP_CMD_EN_MASK (0x40U) +#define FLASH_CMPA_CC_SOCU_PIN_ISP_CMD_EN_SHIFT (6U) +/*! ISP_CMD_EN - ISP Boot Command enable + * 0b0..Use DAP to enable + * 0b1..Fixed state + */ +#define FLASH_CMPA_CC_SOCU_PIN_ISP_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_ISP_CMD_EN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_ISP_CMD_EN_MASK) + +#define FLASH_CMPA_CC_SOCU_PIN_FA_ME_CMD_EN_MASK (0x80U) +#define FLASH_CMPA_CC_SOCU_PIN_FA_ME_CMD_EN_SHIFT (7U) +/*! FA_ME_CMD_EN - FA Command enable + * 0b0..Use DAP to enable + * 0b1..Fixed state + */ +#define FLASH_CMPA_CC_SOCU_PIN_FA_ME_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_FA_ME_CMD_EN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_FA_ME_CMD_EN_MASK) + +#define FLASH_CMPA_CC_SOCU_PIN_UUID_CHECK_MASK (0x8000U) +#define FLASH_CMPA_CC_SOCU_PIN_UUID_CHECK_SHIFT (15U) +/*! UUID_CHECK - Enforce UUID match during Debug authentication. + */ +#define FLASH_CMPA_CC_SOCU_PIN_UUID_CHECK(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_UUID_CHECK_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_UUID_CHECK_MASK) + +#define FLASH_CMPA_CC_SOCU_PIN_INVERSE_VALUE_MASK (0xFFFF0000U) +#define FLASH_CMPA_CC_SOCU_PIN_INVERSE_VALUE_SHIFT (16U) +/*! INVERSE_VALUE - inverse value of bits [15:0] + */ +#define FLASH_CMPA_CC_SOCU_PIN_INVERSE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_INVERSE_VALUE_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_INVERSE_VALUE_MASK) +/*! @} */ + +/*! @name CC_SOCU_DFLT - */ +/*! @{ */ + +#define FLASH_CMPA_CC_SOCU_DFLT_NIDEN_MASK (0x1U) +#define FLASH_CMPA_CC_SOCU_DFLT_NIDEN_SHIFT (0U) +/*! NIDEN - Non Secure non-invasive debug fixed state + * 0b0..Disable + * 0b1..Enable + */ +#define FLASH_CMPA_CC_SOCU_DFLT_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_NIDEN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_NIDEN_MASK) + +#define FLASH_CMPA_CC_SOCU_DFLT_DBGEN_MASK (0x2U) +#define FLASH_CMPA_CC_SOCU_DFLT_DBGEN_SHIFT (1U) +/*! DBGEN - Non Secure debug fixed state + * 0b0..Disable + * 0b1..Enable + */ +#define FLASH_CMPA_CC_SOCU_DFLT_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_DBGEN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_DBGEN_MASK) + +#define FLASH_CMPA_CC_SOCU_DFLT_SPNIDEN_MASK (0x4U) +#define FLASH_CMPA_CC_SOCU_DFLT_SPNIDEN_SHIFT (2U) +/*! SPNIDEN - Secure non-invasive debug fixed state + * 0b0..Disable + * 0b1..Enable + */ +#define FLASH_CMPA_CC_SOCU_DFLT_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_SPNIDEN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_SPNIDEN_MASK) + +#define FLASH_CMPA_CC_SOCU_DFLT_SPIDEN_MASK (0x8U) +#define FLASH_CMPA_CC_SOCU_DFLT_SPIDEN_SHIFT (3U) +/*! SPIDEN - Secure invasive debug fixed state + * 0b0..Disable + * 0b1..Enable + */ +#define FLASH_CMPA_CC_SOCU_DFLT_SPIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_SPIDEN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_SPIDEN_MASK) + +#define FLASH_CMPA_CC_SOCU_DFLT_TAPEN_MASK (0x10U) +#define FLASH_CMPA_CC_SOCU_DFLT_TAPEN_SHIFT (4U) +/*! TAPEN - JTAG TAP fixed state + * 0b0..Disable + * 0b1..Enable + */ +#define FLASH_CMPA_CC_SOCU_DFLT_TAPEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_TAPEN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_TAPEN_MASK) + +#define FLASH_CMPA_CC_SOCU_DFLT_ISP_CMD_EN_MASK (0x40U) +#define FLASH_CMPA_CC_SOCU_DFLT_ISP_CMD_EN_SHIFT (6U) +/*! ISP_CMD_EN - ISP Boot Command fixed state + * 0b0..Disable + * 0b1..Enable + */ +#define FLASH_CMPA_CC_SOCU_DFLT_ISP_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_ISP_CMD_EN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_ISP_CMD_EN_MASK) + +#define FLASH_CMPA_CC_SOCU_DFLT_FA_ME_CMD_EN_MASK (0x80U) +#define FLASH_CMPA_CC_SOCU_DFLT_FA_ME_CMD_EN_SHIFT (7U) +/*! FA_ME_CMD_EN - FA Command fixed state + * 0b0..Disable + * 0b1..Enable + */ +#define FLASH_CMPA_CC_SOCU_DFLT_FA_ME_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_FA_ME_CMD_EN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_FA_ME_CMD_EN_MASK) + +#define FLASH_CMPA_CC_SOCU_DFLT_INVERSE_VALUE_MASK (0xFFFF0000U) +#define FLASH_CMPA_CC_SOCU_DFLT_INVERSE_VALUE_SHIFT (16U) +/*! INVERSE_VALUE - inverse value of bits [15:0] + */ +#define FLASH_CMPA_CC_SOCU_DFLT_INVERSE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_INVERSE_VALUE_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_INVERSE_VALUE_MASK) +/*! @} */ + +/*! @name VENDOR_USAGE - */ +/*! @{ */ + +#define FLASH_CMPA_VENDOR_USAGE_VENDOR_USAGE_MASK (0xFFFF0000U) +#define FLASH_CMPA_VENDOR_USAGE_VENDOR_USAGE_SHIFT (16U) +/*! VENDOR_USAGE - Upper 16 bits of vendor usage field defined in DAP. Lower 16-bits come from customer field area. + */ +#define FLASH_CMPA_VENDOR_USAGE_VENDOR_USAGE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_VENDOR_USAGE_VENDOR_USAGE_SHIFT)) & FLASH_CMPA_VENDOR_USAGE_VENDOR_USAGE_MASK) +/*! @} */ + +/*! @name SECURE_BOOT_CFG - Secure boot configuration flags. */ +/*! @{ */ + +#define FLASH_CMPA_SECURE_BOOT_CFG_RSA4K_MASK (0x3U) +#define FLASH_CMPA_SECURE_BOOT_CFG_RSA4K_SHIFT (0U) +/*! RSA4K - Use RSA4096 keys only. + * 0b00..Allow RSA2048 and higher + * 0b01..RSA4096 only + * 0b10..RSA4096 only + * 0b11..RSA4096 only + */ +#define FLASH_CMPA_SECURE_BOOT_CFG_RSA4K(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_RSA4K_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_RSA4K_MASK) + +#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_INC_NXP_CFG_MASK (0xCU) +#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_INC_NXP_CFG_SHIFT (2U) +/*! DICE_INC_NXP_CFG - Include NXP area in DICE computation. + * 0b00..not included + * 0b01..included + * 0b10..included + * 0b11..included + */ +#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_INC_NXP_CFG(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_DICE_INC_NXP_CFG_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_DICE_INC_NXP_CFG_MASK) + +#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_CUST_CFG_MASK (0x30U) +#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_CUST_CFG_SHIFT (4U) +/*! DICE_CUST_CFG - Include Customer factory area (including keys) in DICE computation. + * 0b00..not included + * 0b01..included + * 0b10..included + * 0b11..included + */ +#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_CUST_CFG(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_DICE_CUST_CFG_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_DICE_CUST_CFG_MASK) + +#define FLASH_CMPA_SECURE_BOOT_CFG_SKIP_DICE_MASK (0xC0U) +#define FLASH_CMPA_SECURE_BOOT_CFG_SKIP_DICE_SHIFT (6U) +/*! SKIP_DICE - Skip DICE computation + * 0b00..Enable DICE + * 0b01..Disable DICE + * 0b10..Disable DICE + * 0b11..Disable DICE + */ +#define FLASH_CMPA_SECURE_BOOT_CFG_SKIP_DICE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_SKIP_DICE_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_SKIP_DICE_MASK) + +#define FLASH_CMPA_SECURE_BOOT_CFG_TZM_IMAGE_TYPE_MASK (0x300U) +#define FLASH_CMPA_SECURE_BOOT_CFG_TZM_IMAGE_TYPE_SHIFT (8U) +/*! TZM_IMAGE_TYPE - TrustZone-M mode + * 0b00..TZ-M image mode is taken from application image header + * 0b01..TZ-M disabled image, boots to non-secure mode + * 0b10..TZ-M enabled image, boots to secure mode + * 0b11..TZ-M enabled image with TZ-M preset, boot to secure mode TZ-M pre-configured by data from application image header + */ +#define FLASH_CMPA_SECURE_BOOT_CFG_TZM_IMAGE_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_TZM_IMAGE_TYPE_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_TZM_IMAGE_TYPE_MASK) + +#define FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_SET_KEY_MASK (0xC00U) +#define FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_SET_KEY_SHIFT (10U) +/*! BLOCK_SET_KEY - Block PUF key code generation + * 0b00..Allow PUF Key Code generation + * 0b01..Disable PUF Key Code generation + * 0b10..Disable PUF Key Code generation + * 0b11..Disable PUF Key Code generation + */ +#define FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_SET_KEY(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_SET_KEY_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_SET_KEY_MASK) + +#define FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_ENROLL_MASK (0x3000U) +#define FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_ENROLL_SHIFT (12U) +/*! BLOCK_ENROLL - Block PUF enrollement + * 0b00..Allow PUF enroll operation + * 0b01..Disable PUF enroll operation + * 0b10..Disable PUF enroll operation + * 0b11..Disable PUF enroll operation + */ +#define FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_ENROLL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_ENROLL_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_ENROLL_MASK) + +#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_INC_SEC_EPOCH_MASK (0xC000U) +#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_INC_SEC_EPOCH_SHIFT (14U) +/*! DICE_INC_SEC_EPOCH - Include security EPOCH in DICE + * 0b00..not included + * 0b01..included + * 0b10..included + * 0b11..included + */ +#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_INC_SEC_EPOCH(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_DICE_INC_SEC_EPOCH_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_DICE_INC_SEC_EPOCH_MASK) + +#define FLASH_CMPA_SECURE_BOOT_CFG_SKIP_BOOT_SEED_MASK (0x30000U) +#define FLASH_CMPA_SECURE_BOOT_CFG_SKIP_BOOT_SEED_SHIFT (16U) +/*! SKIP_BOOT_SEED - Skip boot seed computation + * 0b00..Enable BOOT_SEED + * 0b01..Disable BOOT_SEED + * 0b10..Disable BOOT_SEED + * 0b11..Disable BOOT_SEED + */ +#define FLASH_CMPA_SECURE_BOOT_CFG_SKIP_BOOT_SEED(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_SKIP_BOOT_SEED_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_SKIP_BOOT_SEED_MASK) + +#define FLASH_CMPA_SECURE_BOOT_CFG_BOOT_SEED_INC_NXP_CFG_MASK (0xC0000U) +#define FLASH_CMPA_SECURE_BOOT_CFG_BOOT_SEED_INC_NXP_CFG_SHIFT (18U) +/*! BOOT_SEED_INC_NXP_CFG - Include NXP area in BOOT SEED computation + * 0b00..not included + * 0b01..included + * 0b10..included + * 0b11..included + */ +#define FLASH_CMPA_SECURE_BOOT_CFG_BOOT_SEED_INC_NXP_CFG(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_BOOT_SEED_INC_NXP_CFG_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_BOOT_SEED_INC_NXP_CFG_MASK) + +#define FLASH_CMPA_SECURE_BOOT_CFG_BOOT_SEED_CUST_CFG_MASK (0x300000U) +#define FLASH_CMPA_SECURE_BOOT_CFG_BOOT_SEED_CUST_CFG_SHIFT (20U) +/*! BOOT_SEED_CUST_CFG - Include CMPA area in BOOT SEED computation + * 0b00..not included + * 0b01..included + * 0b10..included + * 0b11..included + */ +#define FLASH_CMPA_SECURE_BOOT_CFG_BOOT_SEED_CUST_CFG(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_BOOT_SEED_CUST_CFG_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_BOOT_SEED_CUST_CFG_MASK) + +#define FLASH_CMPA_SECURE_BOOT_CFG_BOOT_SEED_INC_EPOCH_MASK (0xC00000U) +#define FLASH_CMPA_SECURE_BOOT_CFG_BOOT_SEED_INC_EPOCH_SHIFT (22U) +/*! BOOT_SEED_INC_EPOCH - Include security epoch area in BOOT_SEED computation. + * 0b00..not included + * 0b01..included + * 0b10..included + * 0b11..included + */ +#define FLASH_CMPA_SECURE_BOOT_CFG_BOOT_SEED_INC_EPOCH(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_BOOT_SEED_INC_EPOCH_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_BOOT_SEED_INC_EPOCH_MASK) + +#define FLASH_CMPA_SECURE_BOOT_CFG_SEC_BOOT_EN_MASK (0xC0000000U) +#define FLASH_CMPA_SECURE_BOOT_CFG_SEC_BOOT_EN_SHIFT (30U) +/*! SEC_BOOT_EN - Secure boot enable + * 0b00..Plain image (internal flash with or without CRC) + * 0b01..Boot signed images. (internal flash, RSA signed) + * 0b10..Boot signed images. (internal flash, RSA signed) + * 0b11..Boot signed images. (internal flash, RSA signed) + */ +#define FLASH_CMPA_SECURE_BOOT_CFG_SEC_BOOT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_SEC_BOOT_EN_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_SEC_BOOT_EN_MASK) +/*! @} */ + +/*! @name PRINCE_BASE_ADDR - */ +/*! @{ */ + +#define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR0_PRG_MASK (0xFU) +#define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR0_PRG_SHIFT (0U) +/*! ADDR0_PRG - Programmable portion of the base address of region 0 + */ +#define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR0_PRG(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_ADDR0_PRG_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_ADDR0_PRG_MASK) + +#define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR1_PRG_MASK (0xF0U) +#define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR1_PRG_SHIFT (4U) +/*! ADDR1_PRG - Programmable portion of the base address of region 1 + */ +#define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR1_PRG(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_ADDR1_PRG_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_ADDR1_PRG_MASK) + +#define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR2_PRG_MASK (0xF00U) +#define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR2_PRG_SHIFT (8U) +/*! ADDR2_PRG - Programmable portion of the base address of region 2 + */ +#define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR2_PRG(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_ADDR2_PRG_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_ADDR2_PRG_MASK) + +#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG0_MASK (0xC0000U) +#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG0_SHIFT (18U) +/*! LOCK_REG0 - Lock PRINCE region0 settings + * 0b00..Region is not locked + * 0b01..Region is locked + * 0b10..Region is locked + * 0b11..Region is locked + */ +#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG0(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG0_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG0_MASK) + +#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG1_MASK (0x300000U) +#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG1_SHIFT (20U) +/*! LOCK_REG1 - Lock PRINCE region1 settings + * 0b00..Region is not locked + * 0b01..Region is locked + * 0b10..Region is locked + * 0b11..Region is locked + */ +#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG1(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG1_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG1_MASK) + +#define FLASH_CMPA_PRINCE_BASE_ADDR_REG0_ERASE_CHECK_EN_MASK (0x3000000U) +#define FLASH_CMPA_PRINCE_BASE_ADDR_REG0_ERASE_CHECK_EN_SHIFT (24U) +/*! REG0_ERASE_CHECK_EN - For PRINCE region0 enable checking whether all encrypted pages are erased together + * 0b00..Region is disabled + * 0b01..Region is enabled + * 0b10..Region is enabled + * 0b11..Region is enabled + */ +#define FLASH_CMPA_PRINCE_BASE_ADDR_REG0_ERASE_CHECK_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_REG0_ERASE_CHECK_EN_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_REG0_ERASE_CHECK_EN_MASK) + +#define FLASH_CMPA_PRINCE_BASE_ADDR_REG1_ERASE_CHECK_EN_MASK (0xC000000U) +#define FLASH_CMPA_PRINCE_BASE_ADDR_REG1_ERASE_CHECK_EN_SHIFT (26U) +/*! REG1_ERASE_CHECK_EN - For PRINCE region1 enable checking whether all encrypted pages are erased together + * 0b00..Region is disabled + * 0b01..Region is enabled + * 0b10..Region is enabled + * 0b11..Region is enabled + */ +#define FLASH_CMPA_PRINCE_BASE_ADDR_REG1_ERASE_CHECK_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_REG1_ERASE_CHECK_EN_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_REG1_ERASE_CHECK_EN_MASK) + +#define FLASH_CMPA_PRINCE_BASE_ADDR_REG2_ERASE_CHECK_EN_MASK (0x30000000U) +#define FLASH_CMPA_PRINCE_BASE_ADDR_REG2_ERASE_CHECK_EN_SHIFT (28U) +/*! REG2_ERASE_CHECK_EN - For PRINCE region2 enable checking whether all encrypted pages are erased together + * 0b00..Region is disabled + * 0b01..Region is enabled + * 0b10..Region is enabled + * 0b11..Region is enabled + */ +#define FLASH_CMPA_PRINCE_BASE_ADDR_REG2_ERASE_CHECK_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_REG2_ERASE_CHECK_EN_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_REG2_ERASE_CHECK_EN_MASK) +/*! @} */ + +/*! @name PRINCE_SR_0 - Region 0, sub-region enable */ +/*! @{ */ + +#define FLASH_CMPA_PRINCE_SR_0_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CMPA_PRINCE_SR_0_FIELD_SHIFT (0U) +#define FLASH_CMPA_PRINCE_SR_0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_SR_0_FIELD_SHIFT)) & FLASH_CMPA_PRINCE_SR_0_FIELD_MASK) +/*! @} */ + +/*! @name PRINCE_SR_1 - Region 1, sub-region enable */ +/*! @{ */ + +#define FLASH_CMPA_PRINCE_SR_1_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CMPA_PRINCE_SR_1_FIELD_SHIFT (0U) +#define FLASH_CMPA_PRINCE_SR_1_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_SR_1_FIELD_SHIFT)) & FLASH_CMPA_PRINCE_SR_1_FIELD_MASK) +/*! @} */ + +/*! @name PRINCE_SR_2 - Region 2, sub-region enable */ +/*! @{ */ + +#define FLASH_CMPA_PRINCE_SR_2_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CMPA_PRINCE_SR_2_FIELD_SHIFT (0U) +#define FLASH_CMPA_PRINCE_SR_2_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_SR_2_FIELD_SHIFT)) & FLASH_CMPA_PRINCE_SR_2_FIELD_MASK) +/*! @} */ + +/*! @name XTAL_32KHZ_CAPABANK_TRIM - Xtal 32kHz capabank triming. */ +/*! @{ */ + +#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_TRIM_VALID_MASK (0x1U) +#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_TRIM_VALID_SHIFT (0U) +/*! TRIM_VALID - XTAL 32kHz capa bank trimmings + * 0b0..Capa Bank trimmings not valid. Default trimmings value are used + * 0b1..Capa Bank trimmings valid + */ +#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_TRIM_VALID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_TRIM_VALID_SHIFT)) & FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_TRIM_VALID_MASK) + +#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100_MASK (0x7FEU) +#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100_SHIFT (1U) +/*! XTAL_LOAD_CAP_IEC_PF_X100 - Load capacitance, pF x 100. For example, 6pF becomes 600. + */ +#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100_SHIFT)) & FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100_MASK) + +#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100_MASK (0x1FF800U) +#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100_SHIFT (11U) +/*! PCB_XIN_PARA_CAP_PF_X100 - PCB XIN parasitic capacitance, pF x 100. For example, 6pF becomes 600. + */ +#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100_SHIFT)) & FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100_MASK) + +#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100_MASK (0x7FE00000U) +#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100_SHIFT (21U) +/*! PCB_XOUT_PARA_CAP_PF_X100 - PCB XOUT parasitic capacitance, pF x 100. For example, 6pF becomes 600. + */ +#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100_SHIFT)) & FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100_MASK) +/*! @} */ + +/*! @name XTAL_16MHZ_CAPABANK_TRIM - Xtal 16MHz capabank triming. */ +/*! @{ */ + +#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_TRIM_VALID_MASK (0x1U) +#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_TRIM_VALID_SHIFT (0U) +/*! TRIM_VALID - XTAL 16MHz capa bank trimmings + * 0b0..Capa Bank trimmings not valid. Default trimmings value are used + * 0b1..Capa Bank trimmings valid + */ +#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_TRIM_VALID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_TRIM_VALID_SHIFT)) & FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_TRIM_VALID_MASK) + +#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100_MASK (0x7FEU) +#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100_SHIFT (1U) +/*! XTAL_LOAD_CAP_IEC_PF_X100 - Load capacitance, pF x 100. For example, 6pF becomes 600. + */ +#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100_SHIFT)) & FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100_MASK) + +#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100_MASK (0x1FF800U) +#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100_SHIFT (11U) +/*! PCB_XIN_PARA_CAP_PF_X100 - PCB XIN parasitic capacitance, pF x 100. For example, 6pF becomes 600. + */ +#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100_SHIFT)) & FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100_MASK) + +#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100_MASK (0x7FE00000U) +#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100_SHIFT (21U) +/*! PCB_XOUT_PARA_CAP_PF_X100 - PCB XOUT parasitic capacitance, pF x 100. For example, 6pF becomes 600. + */ +#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100_SHIFT)) & FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100_MASK) +/*! @} */ + +/*! @name FLASH_REMAP_SIZE - This 32-bit register contains the size of the image to remap, in bytes. The 12 LSBs are ignored, so the size granularity is 4KB. */ +/*! @{ */ + +#define FLASH_CMPA_FLASH_REMAP_SIZE_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CMPA_FLASH_REMAP_SIZE_FIELD_SHIFT (0U) +#define FLASH_CMPA_FLASH_REMAP_SIZE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_FLASH_REMAP_SIZE_FIELD_SHIFT)) & FLASH_CMPA_FLASH_REMAP_SIZE_FIELD_MASK) +/*! @} */ + +/*! @name FLASH_REMAP_OFFSET - This 32-bit register contains the offset by which the image is to be remapped. The 12 LSBs are ignored, so the remap granularity is 4KB. */ +/*! @{ */ + +#define FLASH_CMPA_FLASH_REMAP_OFFSET_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CMPA_FLASH_REMAP_OFFSET_FIELD_SHIFT (0U) +#define FLASH_CMPA_FLASH_REMAP_OFFSET_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_FLASH_REMAP_OFFSET_FIELD_SHIFT)) & FLASH_CMPA_FLASH_REMAP_OFFSET_FIELD_MASK) +/*! @} */ + +/*! @name ROTKH - ROTKH0 for Root of Trust Keys Table hash[255:224]..ROTKH7 for Root of Trust Keys Table hash[31:0] */ +/*! @{ */ + +#define FLASH_CMPA_ROTKH_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CMPA_ROTKH_FIELD_SHIFT (0U) +#define FLASH_CMPA_ROTKH_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_ROTKH_FIELD_SHIFT)) & FLASH_CMPA_ROTKH_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_CMPA_ROTKH */ +#define FLASH_CMPA_ROTKH_COUNT (8U) + +/*! @name CUSTOMER_DEFINED - Customer Defined (Programable through ROM API) */ +/*! @{ */ + +#define FLASH_CMPA_CUSTOMER_DEFINED_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CMPA_CUSTOMER_DEFINED_FIELD_SHIFT (0U) +#define FLASH_CMPA_CUSTOMER_DEFINED_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CUSTOMER_DEFINED_FIELD_SHIFT)) & FLASH_CMPA_CUSTOMER_DEFINED_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_CMPA_CUSTOMER_DEFINED */ +#define FLASH_CMPA_CUSTOMER_DEFINED_COUNT (56U) + +/*! @name SHA256_DIGEST - SHA256_DIGEST0 for DIGEST[31:0]..SHA256_DIGEST7 for DIGEST[255:224] */ +/*! @{ */ + +#define FLASH_CMPA_SHA256_DIGEST_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CMPA_SHA256_DIGEST_FIELD_SHIFT (0U) +#define FLASH_CMPA_SHA256_DIGEST_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SHA256_DIGEST_FIELD_SHIFT)) & FLASH_CMPA_SHA256_DIGEST_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_CMPA_SHA256_DIGEST */ +#define FLASH_CMPA_SHA256_DIGEST_COUNT (8U) + + +/*! + * @} + */ /* end of group FLASH_CMPA_Register_Masks */ + + +/* FLASH_CMPA - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral FLASH_CMPA base address */ + #define FLASH_CMPA_BASE (0x1003E400u) + /** Peripheral FLASH_CMPA base address */ + #define FLASH_CMPA_BASE_NS (0x3E400u) + /** Peripheral FLASH_CMPA base pointer */ + #define FLASH_CMPA ((FLASH_CMPA_Type *)FLASH_CMPA_BASE) + /** Peripheral FLASH_CMPA base pointer */ + #define FLASH_CMPA_NS ((FLASH_CMPA_Type *)FLASH_CMPA_BASE_NS) + /** Array initializer of FLASH_CMPA peripheral base addresses */ + #define FLASH_CMPA_BASE_ADDRS { FLASH_CMPA_BASE } + /** Array initializer of FLASH_CMPA peripheral base pointers */ + #define FLASH_CMPA_BASE_PTRS { FLASH_CMPA } + /** Array initializer of FLASH_CMPA peripheral base addresses */ + #define FLASH_CMPA_BASE_ADDRS_NS { FLASH_CMPA_BASE_NS } + /** Array initializer of FLASH_CMPA peripheral base pointers */ + #define FLASH_CMPA_BASE_PTRS_NS { FLASH_CMPA_NS } +#else + /** Peripheral FLASH_CMPA base address */ + #define FLASH_CMPA_BASE (0x3E400u) + /** Peripheral FLASH_CMPA base pointer */ + #define FLASH_CMPA ((FLASH_CMPA_Type *)FLASH_CMPA_BASE) + /** Array initializer of FLASH_CMPA peripheral base addresses */ + #define FLASH_CMPA_BASE_ADDRS { FLASH_CMPA_BASE } + /** Array initializer of FLASH_CMPA peripheral base pointers */ + #define FLASH_CMPA_BASE_PTRS { FLASH_CMPA } +#endif + +/*! + * @} + */ /* end of group FLASH_CMPA_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- FLASH_KEY_STORE Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FLASH_KEY_STORE_Peripheral_Access_Layer FLASH_KEY_STORE Peripheral Access Layer + * @{ + */ + +/** FLASH_KEY_STORE - Register Layout Typedef */ +typedef struct { + struct { /* offset: 0x0 */ + __IO uint32_t HEADER; /**< Valid Key Sore Header : 0x95959595, offset: 0x0 */ + __IO uint32_t PUF_DISCHARGE_TIME_IN_MS; /**< puf discharge time in ms., offset: 0x4 */ + } KEY_STORE_HEADER; + __IO uint32_t ACTIVATION_CODE[298]; /**< ., array offset: 0x8, array step: 0x4 */ + union { /* offset: 0x4B0 */ + __IO uint32_t SBKEY_KEY_CODE[14]; /**< ., array offset: 0x4B0, array step: 0x4 */ + struct { /* offset: 0x4B0 */ + __IO uint32_t SBKEY_HEADER0; /**< ., offset: 0x4B0 */ + __IO uint32_t SBKEY_HEADER1; /**< ., offset: 0x4B4 */ + __IO uint32_t SBKEY_BODY[12]; /**< ., array offset: 0x4B8, array step: 0x4 */ + } SBKEY_KEY_CODE_CORE; + }; + union { /* offset: 0x4E8 */ + __IO uint32_t USER_KEK_KEY_CODE[14]; /**< ., array offset: 0x4E8, array step: 0x4 */ + struct { /* offset: 0x4E8 */ + __IO uint32_t USER_KEK_HEADER0; /**< ., offset: 0x4E8 */ + __IO uint32_t USER_KEK_HEADER1; /**< ., offset: 0x4EC */ + __IO uint32_t USER_KEK_BODY[12]; /**< ., array offset: 0x4F0, array step: 0x4 */ + } USER_KEK_KEY_CODE_CORE; + }; + union { /* offset: 0x520 */ + __IO uint32_t UDS_KEY_CODE[14]; /**< ., array offset: 0x520, array step: 0x4 */ + struct { /* offset: 0x520 */ + __IO uint32_t UDS_HEADER0; /**< ., offset: 0x520 */ + __IO uint32_t UDS_HEADER1; /**< ., offset: 0x524 */ + __IO uint32_t UDS_BODY[12]; /**< ., array offset: 0x528, array step: 0x4 */ + } UDS_KEY_CODE_CORE; + }; + union { /* offset: 0x558 */ + __IO uint32_t PRINCE_REGION0_KEY_CODE[14]; /**< ., array offset: 0x558, array step: 0x4 */ + struct { /* offset: 0x558 */ + __IO uint32_t PRINCE_REGION0_HEADER0; /**< ., offset: 0x558 */ + __IO uint32_t PRINCE_REGION0_HEADER1; /**< ., offset: 0x55C */ + __IO uint32_t PRINCE_REGION0_BODY[12]; /**< ., array offset: 0x560, array step: 0x4 */ + } PRINCE_REGION0_KEY_CODE_CORE; + }; + union { /* offset: 0x590 */ + __IO uint32_t PRINCE_REGION1_KEY_CODE[14]; /**< ., array offset: 0x590, array step: 0x4 */ + struct { /* offset: 0x590 */ + __IO uint32_t PRINCE_REGION1_HEADER0; /**< ., offset: 0x590 */ + __IO uint32_t PRINCE_REGION1_HEADER1; /**< ., offset: 0x594 */ + __IO uint32_t PRINCE_REGION1_BODY[12]; /**< ., array offset: 0x598, array step: 0x4 */ + } PRINCE_REGION1_KEY_CODE_CORE; + }; + union { /* offset: 0x5C8 */ + __IO uint32_t PRINCE_REGION2_KEY_CODE[14]; /**< ., array offset: 0x5C8, array step: 0x4 */ + struct { /* offset: 0x5C8 */ + __IO uint32_t PRINCE_REGION2_HEADER0; /**< ., offset: 0x5C8 */ + __IO uint32_t PRINCE_REGION2_HEADER1; /**< ., offset: 0x5CC */ + __IO uint32_t PRINCE_REGION2_BODY[12]; /**< ., array offset: 0x5D0, array step: 0x4 */ + } PRINCE_REGION2_KEY_CODE_CORE; + }; +} FLASH_KEY_STORE_Type; + +/* ---------------------------------------------------------------------------- + -- FLASH_KEY_STORE Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FLASH_KEY_STORE_Register_Masks FLASH_KEY_STORE Register Masks + * @{ + */ + +/*! @name HEADER - Valid Key Sore Header : 0x95959595 */ +/*! @{ */ + +#define FLASH_KEY_STORE_HEADER_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_KEY_STORE_HEADER_FIELD_SHIFT (0U) +/*! FIELD - . + */ +#define FLASH_KEY_STORE_HEADER_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_HEADER_FIELD_SHIFT)) & FLASH_KEY_STORE_HEADER_FIELD_MASK) +/*! @} */ + +/*! @name PUF_DISCHARGE_TIME_IN_MS - puf discharge time in ms. */ +/*! @{ */ + +#define FLASH_KEY_STORE_PUF_DISCHARGE_TIME_IN_MS_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_KEY_STORE_PUF_DISCHARGE_TIME_IN_MS_FIELD_SHIFT (0U) +/*! FIELD - . + */ +#define FLASH_KEY_STORE_PUF_DISCHARGE_TIME_IN_MS_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PUF_DISCHARGE_TIME_IN_MS_FIELD_SHIFT)) & FLASH_KEY_STORE_PUF_DISCHARGE_TIME_IN_MS_FIELD_MASK) +/*! @} */ + +/*! @name ACTIVATION_CODE - . */ +/*! @{ */ + +#define FLASH_KEY_STORE_ACTIVATION_CODE_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_KEY_STORE_ACTIVATION_CODE_FIELD_SHIFT (0U) +/*! FIELD - . + */ +#define FLASH_KEY_STORE_ACTIVATION_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_ACTIVATION_CODE_FIELD_SHIFT)) & FLASH_KEY_STORE_ACTIVATION_CODE_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_KEY_STORE_ACTIVATION_CODE */ +#define FLASH_KEY_STORE_ACTIVATION_CODE_COUNT (298U) + +/*! @name SBKEY_KEY_CODE - . */ +/*! @{ */ + +#define FLASH_KEY_STORE_SBKEY_KEY_CODE_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_KEY_STORE_SBKEY_KEY_CODE_FIELD_SHIFT (0U) +/*! FIELD - . + */ +#define FLASH_KEY_STORE_SBKEY_KEY_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_SBKEY_KEY_CODE_FIELD_SHIFT)) & FLASH_KEY_STORE_SBKEY_KEY_CODE_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_KEY_STORE_SBKEY_KEY_CODE */ +#define FLASH_KEY_STORE_SBKEY_KEY_CODE_COUNT (14U) + +/*! @name SBKEY_HEADER0 - . */ +/*! @{ */ + +#define FLASH_KEY_STORE_SBKEY_HEADER0_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_KEY_STORE_SBKEY_HEADER0_FIELD_SHIFT (0U) +/*! FIELD - . + */ +#define FLASH_KEY_STORE_SBKEY_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_SBKEY_HEADER0_FIELD_SHIFT)) & FLASH_KEY_STORE_SBKEY_HEADER0_FIELD_MASK) +/*! @} */ + +/*! @name SBKEY_HEADER1 - . */ +/*! @{ */ + +#define FLASH_KEY_STORE_SBKEY_HEADER1_TYPE_MASK (0x3U) +#define FLASH_KEY_STORE_SBKEY_HEADER1_TYPE_SHIFT (0U) +/*! TYPE - . + */ +#define FLASH_KEY_STORE_SBKEY_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_SBKEY_HEADER1_TYPE_SHIFT)) & FLASH_KEY_STORE_SBKEY_HEADER1_TYPE_MASK) + +#define FLASH_KEY_STORE_SBKEY_HEADER1_INDEX_MASK (0xF00U) +#define FLASH_KEY_STORE_SBKEY_HEADER1_INDEX_SHIFT (8U) +/*! INDEX - . + */ +#define FLASH_KEY_STORE_SBKEY_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_SBKEY_HEADER1_INDEX_SHIFT)) & FLASH_KEY_STORE_SBKEY_HEADER1_INDEX_MASK) + +#define FLASH_KEY_STORE_SBKEY_HEADER1_SIZE_MASK (0x3F000000U) +#define FLASH_KEY_STORE_SBKEY_HEADER1_SIZE_SHIFT (24U) +/*! SIZE - . + */ +#define FLASH_KEY_STORE_SBKEY_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_SBKEY_HEADER1_SIZE_SHIFT)) & FLASH_KEY_STORE_SBKEY_HEADER1_SIZE_MASK) +/*! @} */ + +/*! @name SBKEY_BODY - . */ +/*! @{ */ + +#define FLASH_KEY_STORE_SBKEY_BODY_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_KEY_STORE_SBKEY_BODY_FIELD_SHIFT (0U) +/*! FIELD - . + */ +#define FLASH_KEY_STORE_SBKEY_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_SBKEY_BODY_FIELD_SHIFT)) & FLASH_KEY_STORE_SBKEY_BODY_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_KEY_STORE_SBKEY_BODY */ +#define FLASH_KEY_STORE_SBKEY_BODY_COUNT (12U) + +/*! @name USER_KEK_KEY_CODE - . */ +/*! @{ */ + +#define FLASH_KEY_STORE_USER_KEK_KEY_CODE_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_KEY_STORE_USER_KEK_KEY_CODE_FIELD_SHIFT (0U) +/*! FIELD - . + */ +#define FLASH_KEY_STORE_USER_KEK_KEY_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_USER_KEK_KEY_CODE_FIELD_SHIFT)) & FLASH_KEY_STORE_USER_KEK_KEY_CODE_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_KEY_STORE_USER_KEK_KEY_CODE */ +#define FLASH_KEY_STORE_USER_KEK_KEY_CODE_COUNT (14U) + +/*! @name USER_KEK_HEADER0 - . */ +/*! @{ */ + +#define FLASH_KEY_STORE_USER_KEK_HEADER0_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_KEY_STORE_USER_KEK_HEADER0_FIELD_SHIFT (0U) +/*! FIELD - . + */ +#define FLASH_KEY_STORE_USER_KEK_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_USER_KEK_HEADER0_FIELD_SHIFT)) & FLASH_KEY_STORE_USER_KEK_HEADER0_FIELD_MASK) +/*! @} */ + +/*! @name USER_KEK_HEADER1 - . */ +/*! @{ */ + +#define FLASH_KEY_STORE_USER_KEK_HEADER1_TYPE_MASK (0x3U) +#define FLASH_KEY_STORE_USER_KEK_HEADER1_TYPE_SHIFT (0U) +/*! TYPE - . + */ +#define FLASH_KEY_STORE_USER_KEK_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_USER_KEK_HEADER1_TYPE_SHIFT)) & FLASH_KEY_STORE_USER_KEK_HEADER1_TYPE_MASK) + +#define FLASH_KEY_STORE_USER_KEK_HEADER1_INDEX_MASK (0xF00U) +#define FLASH_KEY_STORE_USER_KEK_HEADER1_INDEX_SHIFT (8U) +/*! INDEX - . + */ +#define FLASH_KEY_STORE_USER_KEK_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_USER_KEK_HEADER1_INDEX_SHIFT)) & FLASH_KEY_STORE_USER_KEK_HEADER1_INDEX_MASK) + +#define FLASH_KEY_STORE_USER_KEK_HEADER1_SIZE_MASK (0x3F000000U) +#define FLASH_KEY_STORE_USER_KEK_HEADER1_SIZE_SHIFT (24U) +/*! SIZE - . + */ +#define FLASH_KEY_STORE_USER_KEK_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_USER_KEK_HEADER1_SIZE_SHIFT)) & FLASH_KEY_STORE_USER_KEK_HEADER1_SIZE_MASK) +/*! @} */ + +/*! @name USER_KEK_BODY - . */ +/*! @{ */ + +#define FLASH_KEY_STORE_USER_KEK_BODY_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_KEY_STORE_USER_KEK_BODY_FIELD_SHIFT (0U) +/*! FIELD - . + */ +#define FLASH_KEY_STORE_USER_KEK_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_USER_KEK_BODY_FIELD_SHIFT)) & FLASH_KEY_STORE_USER_KEK_BODY_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_KEY_STORE_USER_KEK_BODY */ +#define FLASH_KEY_STORE_USER_KEK_BODY_COUNT (12U) + +/*! @name UDS_KEY_CODE - . */ +/*! @{ */ + +#define FLASH_KEY_STORE_UDS_KEY_CODE_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_KEY_STORE_UDS_KEY_CODE_FIELD_SHIFT (0U) +/*! FIELD - . + */ +#define FLASH_KEY_STORE_UDS_KEY_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_UDS_KEY_CODE_FIELD_SHIFT)) & FLASH_KEY_STORE_UDS_KEY_CODE_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_KEY_STORE_UDS_KEY_CODE */ +#define FLASH_KEY_STORE_UDS_KEY_CODE_COUNT (14U) + +/*! @name UDS_HEADER0 - . */ +/*! @{ */ + +#define FLASH_KEY_STORE_UDS_HEADER0_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_KEY_STORE_UDS_HEADER0_FIELD_SHIFT (0U) +/*! FIELD - . + */ +#define FLASH_KEY_STORE_UDS_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_UDS_HEADER0_FIELD_SHIFT)) & FLASH_KEY_STORE_UDS_HEADER0_FIELD_MASK) +/*! @} */ + +/*! @name UDS_HEADER1 - . */ +/*! @{ */ + +#define FLASH_KEY_STORE_UDS_HEADER1_TYPE_MASK (0x3U) +#define FLASH_KEY_STORE_UDS_HEADER1_TYPE_SHIFT (0U) +/*! TYPE - . + */ +#define FLASH_KEY_STORE_UDS_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_UDS_HEADER1_TYPE_SHIFT)) & FLASH_KEY_STORE_UDS_HEADER1_TYPE_MASK) + +#define FLASH_KEY_STORE_UDS_HEADER1_INDEX_MASK (0xF00U) +#define FLASH_KEY_STORE_UDS_HEADER1_INDEX_SHIFT (8U) +/*! INDEX - . + */ +#define FLASH_KEY_STORE_UDS_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_UDS_HEADER1_INDEX_SHIFT)) & FLASH_KEY_STORE_UDS_HEADER1_INDEX_MASK) + +#define FLASH_KEY_STORE_UDS_HEADER1_SIZE_MASK (0x3F000000U) +#define FLASH_KEY_STORE_UDS_HEADER1_SIZE_SHIFT (24U) +/*! SIZE - . + */ +#define FLASH_KEY_STORE_UDS_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_UDS_HEADER1_SIZE_SHIFT)) & FLASH_KEY_STORE_UDS_HEADER1_SIZE_MASK) +/*! @} */ + +/*! @name UDS_BODY - . */ +/*! @{ */ + +#define FLASH_KEY_STORE_UDS_BODY_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_KEY_STORE_UDS_BODY_FIELD_SHIFT (0U) +/*! FIELD - . + */ +#define FLASH_KEY_STORE_UDS_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_UDS_BODY_FIELD_SHIFT)) & FLASH_KEY_STORE_UDS_BODY_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_KEY_STORE_UDS_BODY */ +#define FLASH_KEY_STORE_UDS_BODY_COUNT (12U) + +/*! @name PRINCE_REGION0_KEY_CODE - . */ +/*! @{ */ + +#define FLASH_KEY_STORE_PRINCE_REGION0_KEY_CODE_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_KEY_STORE_PRINCE_REGION0_KEY_CODE_FIELD_SHIFT (0U) +/*! FIELD - . + */ +#define FLASH_KEY_STORE_PRINCE_REGION0_KEY_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION0_KEY_CODE_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION0_KEY_CODE_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_KEY_STORE_PRINCE_REGION0_KEY_CODE */ +#define FLASH_KEY_STORE_PRINCE_REGION0_KEY_CODE_COUNT (14U) + +/*! @name PRINCE_REGION0_HEADER0 - . */ +/*! @{ */ + +#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER0_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER0_FIELD_SHIFT (0U) +/*! FIELD - . + */ +#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION0_HEADER0_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION0_HEADER0_FIELD_MASK) +/*! @} */ + +/*! @name PRINCE_REGION0_HEADER1 - . */ +/*! @{ */ + +#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_TYPE_MASK (0x3U) +#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_TYPE_SHIFT (0U) +/*! TYPE - . + */ +#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_TYPE_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_TYPE_MASK) + +#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_INDEX_MASK (0xF00U) +#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_INDEX_SHIFT (8U) +/*! INDEX - . + */ +#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_INDEX_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_INDEX_MASK) + +#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_SIZE_MASK (0x3F000000U) +#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_SIZE_SHIFT (24U) +/*! SIZE - . + */ +#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_SIZE_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_SIZE_MASK) +/*! @} */ + +/*! @name PRINCE_REGION0_BODY - . */ +/*! @{ */ + +#define FLASH_KEY_STORE_PRINCE_REGION0_BODY_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_KEY_STORE_PRINCE_REGION0_BODY_FIELD_SHIFT (0U) +/*! FIELD - . + */ +#define FLASH_KEY_STORE_PRINCE_REGION0_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION0_BODY_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION0_BODY_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_KEY_STORE_PRINCE_REGION0_BODY */ +#define FLASH_KEY_STORE_PRINCE_REGION0_BODY_COUNT (12U) + +/*! @name PRINCE_REGION1_KEY_CODE - . */ +/*! @{ */ + +#define FLASH_KEY_STORE_PRINCE_REGION1_KEY_CODE_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_KEY_STORE_PRINCE_REGION1_KEY_CODE_FIELD_SHIFT (0U) +/*! FIELD - . + */ +#define FLASH_KEY_STORE_PRINCE_REGION1_KEY_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION1_KEY_CODE_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION1_KEY_CODE_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_KEY_STORE_PRINCE_REGION1_KEY_CODE */ +#define FLASH_KEY_STORE_PRINCE_REGION1_KEY_CODE_COUNT (14U) + +/*! @name PRINCE_REGION1_HEADER0 - . */ +/*! @{ */ + +#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER0_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER0_FIELD_SHIFT (0U) +/*! FIELD - . + */ +#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION1_HEADER0_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION1_HEADER0_FIELD_MASK) +/*! @} */ + +/*! @name PRINCE_REGION1_HEADER1 - . */ +/*! @{ */ + +#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_TYPE_MASK (0x3U) +#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_TYPE_SHIFT (0U) +/*! TYPE - . + */ +#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_TYPE_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_TYPE_MASK) + +#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_INDEX_MASK (0xF00U) +#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_INDEX_SHIFT (8U) +/*! INDEX - . + */ +#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_INDEX_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_INDEX_MASK) + +#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_SIZE_MASK (0x3F000000U) +#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_SIZE_SHIFT (24U) +/*! SIZE - . + */ +#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_SIZE_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_SIZE_MASK) +/*! @} */ + +/*! @name PRINCE_REGION1_BODY - . */ +/*! @{ */ + +#define FLASH_KEY_STORE_PRINCE_REGION1_BODY_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_KEY_STORE_PRINCE_REGION1_BODY_FIELD_SHIFT (0U) +/*! FIELD - . + */ +#define FLASH_KEY_STORE_PRINCE_REGION1_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION1_BODY_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION1_BODY_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_KEY_STORE_PRINCE_REGION1_BODY */ +#define FLASH_KEY_STORE_PRINCE_REGION1_BODY_COUNT (12U) + +/*! @name PRINCE_REGION2_KEY_CODE - . */ +/*! @{ */ + +#define FLASH_KEY_STORE_PRINCE_REGION2_KEY_CODE_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_KEY_STORE_PRINCE_REGION2_KEY_CODE_FIELD_SHIFT (0U) +/*! FIELD - . + */ +#define FLASH_KEY_STORE_PRINCE_REGION2_KEY_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION2_KEY_CODE_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION2_KEY_CODE_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_KEY_STORE_PRINCE_REGION2_KEY_CODE */ +#define FLASH_KEY_STORE_PRINCE_REGION2_KEY_CODE_COUNT (14U) + +/*! @name PRINCE_REGION2_HEADER0 - . */ +/*! @{ */ + +#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER0_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER0_FIELD_SHIFT (0U) +/*! FIELD - . + */ +#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION2_HEADER0_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION2_HEADER0_FIELD_MASK) +/*! @} */ + +/*! @name PRINCE_REGION2_HEADER1 - . */ +/*! @{ */ + +#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_TYPE_MASK (0x3U) +#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_TYPE_SHIFT (0U) +/*! TYPE - . + */ +#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_TYPE_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_TYPE_MASK) + +#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_INDEX_MASK (0xF00U) +#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_INDEX_SHIFT (8U) +/*! INDEX - . + */ +#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_INDEX_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_INDEX_MASK) + +#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_SIZE_MASK (0x3F000000U) +#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_SIZE_SHIFT (24U) +/*! SIZE - . + */ +#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_SIZE_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_SIZE_MASK) +/*! @} */ + +/*! @name PRINCE_REGION2_BODY - . */ +/*! @{ */ + +#define FLASH_KEY_STORE_PRINCE_REGION2_BODY_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_KEY_STORE_PRINCE_REGION2_BODY_FIELD_SHIFT (0U) +/*! FIELD - . + */ +#define FLASH_KEY_STORE_PRINCE_REGION2_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION2_BODY_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION2_BODY_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_KEY_STORE_PRINCE_REGION2_BODY */ +#define FLASH_KEY_STORE_PRINCE_REGION2_BODY_COUNT (12U) + + +/*! + * @} + */ /* end of group FLASH_KEY_STORE_Register_Masks */ + + +/* FLASH_KEY_STORE - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral FLASH_KEY_STORE base address */ + #define FLASH_KEY_STORE_BASE (0x1003E600u) + /** Peripheral FLASH_KEY_STORE base address */ + #define FLASH_KEY_STORE_BASE_NS (0x3E600u) + /** Peripheral FLASH_KEY_STORE base pointer */ + #define FLASH_KEY_STORE ((FLASH_KEY_STORE_Type *)FLASH_KEY_STORE_BASE) + /** Peripheral FLASH_KEY_STORE base pointer */ + #define FLASH_KEY_STORE_NS ((FLASH_KEY_STORE_Type *)FLASH_KEY_STORE_BASE_NS) + /** Array initializer of FLASH_KEY_STORE peripheral base addresses */ + #define FLASH_KEY_STORE_BASE_ADDRS { FLASH_KEY_STORE_BASE } + /** Array initializer of FLASH_KEY_STORE peripheral base pointers */ + #define FLASH_KEY_STORE_BASE_PTRS { FLASH_KEY_STORE } + /** Array initializer of FLASH_KEY_STORE peripheral base addresses */ + #define FLASH_KEY_STORE_BASE_ADDRS_NS { FLASH_KEY_STORE_BASE_NS } + /** Array initializer of FLASH_KEY_STORE peripheral base pointers */ + #define FLASH_KEY_STORE_BASE_PTRS_NS { FLASH_KEY_STORE_NS } +#else + /** Peripheral FLASH_KEY_STORE base address */ + #define FLASH_KEY_STORE_BASE (0x3E600u) + /** Peripheral FLASH_KEY_STORE base pointer */ + #define FLASH_KEY_STORE ((FLASH_KEY_STORE_Type *)FLASH_KEY_STORE_BASE) + /** Array initializer of FLASH_KEY_STORE peripheral base addresses */ + #define FLASH_KEY_STORE_BASE_ADDRS { FLASH_KEY_STORE_BASE } + /** Array initializer of FLASH_KEY_STORE peripheral base pointers */ + #define FLASH_KEY_STORE_BASE_PTRS { FLASH_KEY_STORE } +#endif + +/*! + * @} + */ /* end of group FLASH_KEY_STORE_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- FLASH_NMPA Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FLASH_NMPA_Peripheral_Access_Layer FLASH_NMPA Peripheral Access Layer + * @{ + */ + +/** FLASH_NMPA - Register Layout Typedef */ +typedef struct { + union { /* offset: 0x0 */ + struct { /* offset: 0x0 */ + __IO uint32_t GPO0_0; /**< GPO0 register 0 description, offset: 0x0 */ + __IO uint32_t GPO0_1; /**< GPO0 register 1 description, offset: 0x4 */ + __IO uint32_t GPO0_2; /**< GPO0 register 2 description, offset: 0x8 */ + __IO uint32_t GPO0_3; /**< GPO0 register 3 description, offset: 0xC */ + } GPO0; + __IO uint32_t GPO0_ARRAY[4]; /**< GPO0 array description, array offset: 0x0, array step: 0x4 */ + }; + union { /* offset: 0x10 */ + struct { /* offset: 0x10 */ + __IO uint32_t GPO1_0; /**< GPO1 register 0 description, offset: 0x10 */ + __IO uint32_t GPO1_1; /**< GPO1 register 1 description, offset: 0x14 */ + __IO uint32_t GPO1_2; /**< GPO1 register 2 description, offset: 0x18 */ + __IO uint32_t GPO1_3; /**< GPO1 register 3 description, offset: 0x1C */ + } GPO1; + __IO uint32_t GPO1_ARRAY[4]; /**< GPO1 array description, array offset: 0x10, array step: 0x4 */ + }; + union { /* offset: 0x20 */ + struct { /* offset: 0x20 */ + __IO uint32_t GPO2_0; /**< GPO2 register 0 description, offset: 0x20 */ + __IO uint32_t GPO2_1; /**< GPO2 register 1 description, offset: 0x24 */ + __IO uint32_t GPO2_2; /**< GPO2 register 2 description, offset: 0x28 */ + __IO uint32_t GPO2_3; /**< GPO2 register 3 description, offset: 0x2C */ + } GPO2; + __IO uint32_t GPO2_ARRAY[4]; /**< GPO2 array description, array offset: 0x20, array step: 0x4 */ + }; + union { /* offset: 0x30 */ + struct { /* offset: 0x30 */ + __IO uint32_t GPO3_0; /**< GPO3 register 0 description, offset: 0x30 */ + __IO uint32_t GPO3_1; /**< GPO3 register 1 description, offset: 0x34 */ + __IO uint32_t GPO3_2; /**< GPO3 register 2 description, offset: 0x38 */ + __IO uint32_t GPO3_3; /**< GPO3 register 3 description, offset: 0x3C */ + } GPO3; + __IO uint32_t GPO3_ARRAY[4]; /**< GPO3 array description, array offset: 0x30, array step: 0x4 */ + }; + union { /* offset: 0x40 */ + struct { /* offset: 0x40 */ + __IO uint32_t GPO_CHECKSUM_0; /**< checksum of the GPO data in words 0, offset: 0x40 */ + __IO uint32_t GPO_CHECKSUM_1; /**< checksum of the GPO data in words 1, offset: 0x44 */ + __IO uint32_t GPO_CHECKSUM_2; /**< checksum of the GPO data in words 2, offset: 0x48 */ + __IO uint32_t GPO_CHECKSUM_3; /**< checksum of the GPO data in words 3, offset: 0x4C */ + } GPO_CHECKSUM; + __IO uint32_t GPO_CHECKSUM_ARRAY[4]; /**< checksum of the GPO data in words [3:0], array offset: 0x40, array step: 0x4 */ + }; + union { /* offset: 0x50 */ + struct { /* offset: 0x50 */ + __IO uint32_t FINAL_TEST_BATCH_ID_0; /**< , offset: 0x50 */ + __IO uint32_t FINAL_TEST_BATCH_ID_1; /**< , offset: 0x54 */ + __IO uint32_t FINAL_TEST_BATCH_ID_2; /**< , offset: 0x58 */ + __IO uint32_t FINAL_TEST_BATCH_ID_3; /**< , offset: 0x5C */ + } FINAL_TEST_BATCH_ID; + __IO uint32_t FINAL_TEST_BATCH_ID_ARRAY[4]; /**< , array offset: 0x50, array step: 0x4 */ + }; + __IO uint32_t DEVICE_TYPE; /**< , offset: 0x60 */ + __IO uint32_t FINAL_TEST_PROGRAM_VERSION; /**< , offset: 0x64 */ + __IO uint32_t FINAL_TEST_DATE; /**< , offset: 0x68 */ + __IO uint32_t FINAL_TEST_TIME; /**< , offset: 0x6C */ + union { /* offset: 0x70 */ + struct { /* offset: 0x70 */ + __IO uint32_t UUID_0; /**< , offset: 0x70 */ + __IO uint32_t UUID_1; /**< , offset: 0x74 */ + __IO uint32_t UUID_2; /**< , offset: 0x78 */ + __IO uint32_t UUID_3; /**< , offset: 0x7C */ + } UUID; + __IO uint32_t UUID_ARRAY[4]; /**< , array offset: 0x70, array step: 0x4 */ + }; + __IO uint32_t WAFER_TEST1_PROGRAM_VERSION; /**< , offset: 0x80 */ + __IO uint32_t WAFER_TEST1_DATE; /**< , offset: 0x84 */ + __IO uint32_t WAFER_TEST1_TIME; /**< , offset: 0x88 */ + uint8_t RESERVED_0[4]; + __IO uint32_t WAFER_TEST2_PROGRAM_VERSION; /**< , offset: 0x90 */ + __IO uint32_t WAFER_TEST2_DATE; /**< , offset: 0x94 */ + __IO uint32_t WAFER_TEST2_TIME; /**< , offset: 0x98 */ + __IO uint32_t USBCFG; /**< , offset: 0x9C */ + __IO uint32_t PERIPHENCFG; /**< , offset: 0xA0 */ + __IO uint32_t RAMSIZECFG; /**< , offset: 0xA4 */ + __IO uint32_t FLASHSIZECFG; /**< , offset: 0xA8 */ + uint8_t RESERVED_1[4]; + __IO uint32_t RINGO_0; /**< , offset: 0xB0 */ + __IO uint32_t RINGO_1; /**< , offset: 0xB4 */ + __IO uint32_t RINGO_2; /**< , offset: 0xB8 */ + uint8_t RESERVED_2[4]; + __IO uint32_t FRO_192MHZ; /**< , offset: 0xC0 */ + uint8_t RESERVED_3[4]; + __IO uint32_t XO_32MHZ; /**< , offset: 0xC8 */ + __IO uint32_t XO_32KHZ; /**< , offset: 0xCC */ + __IO uint32_t FRO_1MHZ; /**< , offset: 0xD0 */ + uint8_t RESERVED_4[4]; + union { /* offset: 0xD8 */ + struct { /* offset: 0xD8 */ + __IO uint32_t DCDC_POWER_PROFILE_HIGH_0; /**< , offset: 0xD8 */ + __IO uint32_t DCDC_POWER_PROFILE_HIGH_1; /**< , offset: 0xDC */ + } DCDC_POWER_PROFILE_HIGH; + __IO uint32_t DCDC_POWER_PROFILE_HIGH_ARRAY[2]; /**< , array offset: 0xD8, array step: 0x4 */ + }; + union { /* offset: 0xE0 */ + struct { /* offset: 0xE0 */ + __IO uint32_t DCDC_POWER_PROFILE_LOW_0; /**< , offset: 0xE0 */ + __IO uint32_t DCDC_POWER_PROFILE_LOW_1; /**< , offset: 0xE4 */ + } DCDC_POWER_PROFILE_LOW; + __IO uint32_t DCDC_POWER_PROFILE_LOW_ARRAY[2]; /**< , array offset: 0xE0, array step: 0x4 */ + }; + union { /* offset: 0xE8 */ + struct { /* offset: 0xE8 */ + __IO uint32_t DCDC_POWER_PROFILE_MEDIUM_0; /**< , offset: 0xE8 */ + __IO uint32_t DCDC_POWER_PROFILE_MEDIUM_1; /**< , offset: 0xEC */ + } DCDC_POWER_PROFILE_MEDIUM; + __IO uint32_t DCDC_POWER_PROFILE_MEDIUM_ARRAY[2]; /**< , array offset: 0xE8, array step: 0x4 */ + }; + __IO uint32_t BOD; /**< , offset: 0xF0 */ + __IO uint32_t LDO_AO; /**< , offset: 0xF4 */ + __IO uint32_t SDIO_DELAY; /**< , offset: 0xF8 */ + uint8_t RESERVED_5[4]; + union { /* offset: 0x100 */ + struct { /* offset: 0x100 */ + __IO uint32_t AUX_BIAS_CURVE_AMBIENT_0; /**< , offset: 0x100 */ + __IO uint32_t AUX_BIAS_CURVE_AMBIENT_1; /**< , offset: 0x104 */ + __IO uint32_t AUX_BIAS_CURVE_AMBIENT_2; /**< , offset: 0x108 */ + __IO uint32_t AUX_BIAS_CURVE_AMBIENT_3; /**< , offset: 0x10C */ + } AUX_BIAS_CURVE_AMBIENT; + __IO uint32_t AUX_BIAS_CURVE_AMBIENT_ARRAY[4]; /**< Aux Bias Curve Ambient (30degC), array offset: 0x100, array step: 0x4 */ + }; + union { /* offset: 0x110 */ + struct { /* offset: 0x110 */ + __IO uint32_t AUX_BIAS_CURVE_TEMP_0; /**< , offset: 0x110 */ + __IO uint32_t AUX_BIAS_CURVE_TEMP_1; /**< , offset: 0x114 */ + __IO uint32_t AUX_BIAS_CURVE_TEMP_2; /**< , offset: 0x118 */ + __IO uint32_t AUX_BIAS_CURVE_TEMP_3; /**< , offset: 0x11C */ + } AUX_BIAS_CURVE_TEMP; + __IO uint32_t AUX_BIAS_CURVE_TEMP_ARRAY[4]; /**< Aux Bias Curve TEMP (105degC), array offset: 0x110, array step: 0x4 */ + }; + __IO uint32_t TEMP_SENS_VBE1VBE8_REF_1; /**< , offset: 0x120 */ + __IO uint32_t TEMP_SENS_VBE1VBE8_REF_2; /**< , offset: 0x124 */ + __IO uint32_t TEMP_SENS_SLOPE; /**< , offset: 0x128 */ + __IO uint32_t TEMP_SENS_OFFSET; /**< , offset: 0x12C */ + union { /* offset: 0x130 */ + struct { /* offset: 0x130 */ + __IO uint32_t PVT_MONITOR_0_RINGO; /**< , offset: 0x130 */ + __IO uint32_t PVT_MONITOR_0_DELAYS_LSB; /**< , offset: 0x134 */ + __IO uint32_t PVT_MONITOR_0_DELAYS_MSB; /**< , offset: 0x138 */ + } PVT_MONITOR_0; + __IO uint32_t PVT_MONITOR_0_ARRAY[3]; /**< , array offset: 0x130, array step: 0x4 */ + }; + uint8_t RESERVED_6[4]; + union { /* offset: 0x140 */ + struct { /* offset: 0x140 */ + __IO uint32_t PVT_MONITOR_1_RINGO; /**< , offset: 0x140 */ + __IO uint32_t PVT_MONITOR_1_DELAYS_LSB; /**< , offset: 0x144 */ + __IO uint32_t PVT_MONITOR_1_DELAYS_MSB; /**< , offset: 0x148 */ + } PVT_MONITOR_1; + __IO uint32_t PVT_MONITOR_1_ARRAY[3]; /**< , array offset: 0x140, array step: 0x4 */ + }; + __IO uint32_t NXP_DEVICE_PRIVATE_KEY[13]; /**< , array offset: 0x14C, array step: 0x4 */ + __IO uint32_t NXP_DEVICE_CERTIFICATE_0[4]; /**< NXP Device Certificate (ECDSA_sign - r[255:128]), array offset: 0x180, array step: 0x4 */ + __IO uint32_t NXP_DEVICE_CERTIFICATE_1[4]; /**< NXP Device Certificate (ECDSA_sign - r[127:0]), array offset: 0x190, array step: 0x4 */ + __IO uint32_t NXP_DEVICE_CERTIFICATE_2[4]; /**< NXP Device Certificate (ECDSA_sign - s[255:128]), array offset: 0x1A0, array step: 0x4 */ + __IO uint32_t NXP_DEVICE_CERTIFICATE_3[4]; /**< NXP Device Certificate (ECDSA_sign - s[127:0]), array offset: 0x1B0, array step: 0x4 */ + __IO uint32_t SHA256_DIGEST[8]; /**< SHA-256 DIGEST (9EC00 - 9FDBC) ROM Patch Area + NXP Area (IMPORTANT NOTE: Pages used for Repair (N-8 to N-3) are excluded from the computation) SHA256_DIGEST0 for DIGEST[31:0]..SHA-256 DIGEST (9EC00 - 9FDBC) ROM Patch Area + NXP Area (IMPORTANT NOTE: Pages used for Repair (N-8 to N-3) are excluded from the computation) SHA256_DIGEST7 for DIGEST[255:224], array offset: 0x1C0, array step: 0x4 */ + union { /* offset: 0x1E0 */ + struct { /* offset: 0x1E0 */ + __IO uint32_t ECID_BACKUP_0; /**< , offset: 0x1E0 */ + __IO uint32_t ECID_BACKUP_1; /**< , offset: 0x1E4 */ + __IO uint32_t ECID_BACKUP_2; /**< , offset: 0x1E8 */ + __IO uint32_t ECID_BACKUP_3; /**< , offset: 0x1EC */ + } ECID_BACKUP; + __IO uint32_t ECID_BACKUP_ARRAY[4]; /**< ECID backup (the original is in page n-1), array offset: 0x1E0, array step: 0x4 */ + }; + uint32_t CHECKSUM[4]; /**< Checksum of the whole page, array offset: 0x1F0, array step: 0x4 */ + uint8_t RESERVED_7[2732]; + __IO uint32_t DIS_ROM_HIDING; /**< , offset: 0xCAC */ + uint8_t RESERVED_8[12]; + __IO uint32_t PUF_SRAM; /**< , offset: 0xCBC */ +} FLASH_NMPA_Type; + +/* ---------------------------------------------------------------------------- + -- FLASH_NMPA Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FLASH_NMPA_Register_Masks FLASH_NMPA Register Masks + * @{ + */ + +/*! @name GPO0_0 - GPO0 register 0 description */ +/*! @{ */ + +#define FLASH_NMPA_GPO0_0_FRO_TRIM_VALID_MASK (0x1U) +#define FLASH_NMPA_GPO0_0_FRO_TRIM_VALID_SHIFT (0U) +#define FLASH_NMPA_GPO0_0_FRO_TRIM_VALID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO0_0_FRO_TRIM_VALID_SHIFT)) & FLASH_NMPA_GPO0_0_FRO_TRIM_VALID_MASK) + +#define FLASH_NMPA_GPO0_0_FRO32K_NTAT_MASK (0xEU) +#define FLASH_NMPA_GPO0_0_FRO32K_NTAT_SHIFT (1U) +#define FLASH_NMPA_GPO0_0_FRO32K_NTAT(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO0_0_FRO32K_NTAT_SHIFT)) & FLASH_NMPA_GPO0_0_FRO32K_NTAT_MASK) + +#define FLASH_NMPA_GPO0_0_FRO32K_PTAT_MASK (0x70U) +#define FLASH_NMPA_GPO0_0_FRO32K_PTAT_SHIFT (4U) +#define FLASH_NMPA_GPO0_0_FRO32K_PTAT(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO0_0_FRO32K_PTAT_SHIFT)) & FLASH_NMPA_GPO0_0_FRO32K_PTAT_MASK) + +#define FLASH_NMPA_GPO0_0_FRO32K_CAPCAL_MASK (0xFF80U) +#define FLASH_NMPA_GPO0_0_FRO32K_CAPCAL_SHIFT (7U) +#define FLASH_NMPA_GPO0_0_FRO32K_CAPCAL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO0_0_FRO32K_CAPCAL_SHIFT)) & FLASH_NMPA_GPO0_0_FRO32K_CAPCAL_MASK) + +#define FLASH_NMPA_GPO0_0_FIELD_MASK (0xFFFF0000U) +#define FLASH_NMPA_GPO0_0_FIELD_SHIFT (16U) +#define FLASH_NMPA_GPO0_0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO0_0_FIELD_SHIFT)) & FLASH_NMPA_GPO0_0_FIELD_MASK) +/*! @} */ + +/*! @name GPO0_1 - GPO0 register 1 description */ +/*! @{ */ + +#define FLASH_NMPA_GPO0_1_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_NMPA_GPO0_1_FIELD_SHIFT (0U) +#define FLASH_NMPA_GPO0_1_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO0_1_FIELD_SHIFT)) & FLASH_NMPA_GPO0_1_FIELD_MASK) +/*! @} */ + +/*! @name GPO0_2 - GPO0 register 2 description */ +/*! @{ */ + +#define FLASH_NMPA_GPO0_2_SYSTEM_SPEED_CODE_MASK (0x3U) +#define FLASH_NMPA_GPO0_2_SYSTEM_SPEED_CODE_SHIFT (0U) +/*! SYSTEM_SPEED_CODE - 00 : FRO12MHz 01 : FRO24MHz 10 : FRO48MHz 11 : FRO96MHz + */ +#define FLASH_NMPA_GPO0_2_SYSTEM_SPEED_CODE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO0_2_SYSTEM_SPEED_CODE_SHIFT)) & FLASH_NMPA_GPO0_2_SYSTEM_SPEED_CODE_MASK) + +#define FLASH_NMPA_GPO0_2_FLASH_CTRL_OPMODE_MASK (0xCU) +#define FLASH_NMPA_GPO0_2_FLASH_CTRL_OPMODE_SHIFT (2U) +/*! FLASH_CTRL_OPMODE - 00 : Delay Line 01 : RCLK (back up clock) 10 : PCLK (back up clock) + */ +#define FLASH_NMPA_GPO0_2_FLASH_CTRL_OPMODE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO0_2_FLASH_CTRL_OPMODE_SHIFT)) & FLASH_NMPA_GPO0_2_FLASH_CTRL_OPMODE_MASK) + +#define FLASH_NMPA_GPO0_2_FIELD_MASK (0xFFFFFFF0U) +#define FLASH_NMPA_GPO0_2_FIELD_SHIFT (4U) +#define FLASH_NMPA_GPO0_2_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO0_2_FIELD_SHIFT)) & FLASH_NMPA_GPO0_2_FIELD_MASK) +/*! @} */ + +/*! @name GPO0_3 - GPO0 register 3 description */ +/*! @{ */ + +#define FLASH_NMPA_GPO0_3_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_NMPA_GPO0_3_FIELD_SHIFT (0U) +#define FLASH_NMPA_GPO0_3_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO0_3_FIELD_SHIFT)) & FLASH_NMPA_GPO0_3_FIELD_MASK) +/*! @} */ + +/*! @name GPO0_ARRAY - GPO0 array description */ +/*! @{ */ + +#define FLASH_NMPA_GPO0_ARRAY_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_NMPA_GPO0_ARRAY_FIELD_SHIFT (0U) +#define FLASH_NMPA_GPO0_ARRAY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO0_ARRAY_FIELD_SHIFT)) & FLASH_NMPA_GPO0_ARRAY_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_NMPA_GPO0_ARRAY */ +#define FLASH_NMPA_GPO0_ARRAY_COUNT (4U) + +/*! @name GPO1_0 - GPO1 register 0 description */ +/*! @{ */ + +#define FLASH_NMPA_GPO1_0_FINAL_TEST_NOT_DONE_MASK (0xFU) +#define FLASH_NMPA_GPO1_0_FINAL_TEST_NOT_DONE_SHIFT (0U) +/*! FINAL_TEST_NOT_DONE - FINAL_TEST_NOT_DONE[3:0]: 1010 : Final Test Not Done. All Other values: Final Test Done. + */ +#define FLASH_NMPA_GPO1_0_FINAL_TEST_NOT_DONE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO1_0_FINAL_TEST_NOT_DONE_SHIFT)) & FLASH_NMPA_GPO1_0_FINAL_TEST_NOT_DONE_MASK) + +#define FLASH_NMPA_GPO1_0_PARTCONFIG_MASK (0x7F0U) +#define FLASH_NMPA_GPO1_0_PARTCONFIG_SHIFT (4U) +/*! PARTCONFIG - Device type number. (E.g : LPC5569 stored as 69 decimal) + */ +#define FLASH_NMPA_GPO1_0_PARTCONFIG(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO1_0_PARTCONFIG_SHIFT)) & FLASH_NMPA_GPO1_0_PARTCONFIG_MASK) + +#define FLASH_NMPA_GPO1_0_DEVICE_TYPE_SEC_MASK (0x800U) +#define FLASH_NMPA_GPO1_0_DEVICE_TYPE_SEC_SHIFT (11U) +/*! DEVICE_TYPE_SEC - Security device type: 0: LPC55xxx (Non Secure Familly) 1: LPC55Sxxx (Secure Familly) + */ +#define FLASH_NMPA_GPO1_0_DEVICE_TYPE_SEC(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO1_0_DEVICE_TYPE_SEC_SHIFT)) & FLASH_NMPA_GPO1_0_DEVICE_TYPE_SEC_MASK) + +#define FLASH_NMPA_GPO1_0_SRAM_SIZE_MASK (0xF000U) +#define FLASH_NMPA_GPO1_0_SRAM_SIZE_SHIFT (12U) +/*! SRAM_SIZE - SRAM_SIZE[3:0]: (For Niobe4) 0000 : 320 KB 0001 : 256 KB 0010 : 144 KB 0011 : 80 KB + * (For Niobe4 Mini) 0100 : 96 KB 0101 : 80 KB 0110 : 64 KB 0111 : 48 KB All others : RESERVED + */ +#define FLASH_NMPA_GPO1_0_SRAM_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO1_0_SRAM_SIZE_SHIFT)) & FLASH_NMPA_GPO1_0_SRAM_SIZE_MASK) + +#define FLASH_NMPA_GPO1_0_CPU0_SECURITY_EXTENSION_DISABLE_MASK (0xF0000U) +#define FLASH_NMPA_GPO1_0_CPU0_SECURITY_EXTENSION_DISABLE_SHIFT (16U) +/*! CPU0_SECURITY_EXTENSION_DISABLE - CPU0_SECURITY_EXTENSION_DISABLE[3:0]: 1010 : CPU0 Security + * Extension is disabled. All Other values: CPU0 Security Extension is enabled. + */ +#define FLASH_NMPA_GPO1_0_CPU0_SECURITY_EXTENSION_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO1_0_CPU0_SECURITY_EXTENSION_DISABLE_SHIFT)) & FLASH_NMPA_GPO1_0_CPU0_SECURITY_EXTENSION_DISABLE_MASK) + +#define FLASH_NMPA_GPO1_0_FIELD_MASK (0xF00000U) +#define FLASH_NMPA_GPO1_0_FIELD_SHIFT (20U) +#define FLASH_NMPA_GPO1_0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO1_0_FIELD_SHIFT)) & FLASH_NMPA_GPO1_0_FIELD_MASK) + +#define FLASH_NMPA_GPO1_0_ROM_REVISION_MINOR_MASK (0xF000000U) +#define FLASH_NMPA_GPO1_0_ROM_REVISION_MINOR_SHIFT (24U) +/*! ROM_REVISION_MINOR - ROM Revision-Minor [3:0] + */ +#define FLASH_NMPA_GPO1_0_ROM_REVISION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO1_0_ROM_REVISION_MINOR_SHIFT)) & FLASH_NMPA_GPO1_0_ROM_REVISION_MINOR_MASK) + +#define FLASH_NMPA_GPO1_0_METAL_REVISION_ID_MASK (0xF0000000U) +#define FLASH_NMPA_GPO1_0_METAL_REVISION_ID_SHIFT (28U) +/*! METAL_REVISION_ID - METAL REVISION ID[3:0] + */ +#define FLASH_NMPA_GPO1_0_METAL_REVISION_ID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO1_0_METAL_REVISION_ID_SHIFT)) & FLASH_NMPA_GPO1_0_METAL_REVISION_ID_MASK) +/*! @} */ + +/*! @name GPO1_1 - GPO1 register 1 description */ +/*! @{ */ + +#define FLASH_NMPA_GPO1_1_ROM_PATCH_VERSION_MASK (0xFU) +#define FLASH_NMPA_GPO1_1_ROM_PATCH_VERSION_SHIFT (0U) +/*! ROM_PATCH_VERSION - ROM Patch Version [3:0] + */ +#define FLASH_NMPA_GPO1_1_ROM_PATCH_VERSION(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO1_1_ROM_PATCH_VERSION_SHIFT)) & FLASH_NMPA_GPO1_1_ROM_PATCH_VERSION_MASK) + +#define FLASH_NMPA_GPO1_1_CUSTOMER_REVISION_ID_MASK (0xF0U) +#define FLASH_NMPA_GPO1_1_CUSTOMER_REVISION_ID_SHIFT (4U) +/*! CUSTOMER_REVISION_ID - CUSTOMER REVISION ID[3:0] + */ +#define FLASH_NMPA_GPO1_1_CUSTOMER_REVISION_ID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO1_1_CUSTOMER_REVISION_ID_SHIFT)) & FLASH_NMPA_GPO1_1_CUSTOMER_REVISION_ID_MASK) + +#define FLASH_NMPA_GPO1_1_FIELD_MASK (0xFFFFFF00U) +#define FLASH_NMPA_GPO1_1_FIELD_SHIFT (8U) +#define FLASH_NMPA_GPO1_1_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO1_1_FIELD_SHIFT)) & FLASH_NMPA_GPO1_1_FIELD_MASK) +/*! @} */ + +/*! @name GPO1_2 - GPO1 register 2 description */ +/*! @{ */ + +#define FLASH_NMPA_GPO1_2_HVST_MASK (0x1U) +#define FLASH_NMPA_GPO1_2_HVST_SHIFT (0U) +/*! HVST - High Voltage Stress: 0=not done; 1=done. + */ +#define FLASH_NMPA_GPO1_2_HVST(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO1_2_HVST_SHIFT)) & FLASH_NMPA_GPO1_2_HVST_MASK) + +#define FLASH_NMPA_GPO1_2_FIELD_MASK (0xFFFFFFFEU) +#define FLASH_NMPA_GPO1_2_FIELD_SHIFT (1U) +#define FLASH_NMPA_GPO1_2_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO1_2_FIELD_SHIFT)) & FLASH_NMPA_GPO1_2_FIELD_MASK) +/*! @} */ + +/*! @name GPO1_3 - GPO1 register 3 description */ +/*! @{ */ + +#define FLASH_NMPA_GPO1_3_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_NMPA_GPO1_3_FIELD_SHIFT (0U) +#define FLASH_NMPA_GPO1_3_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO1_3_FIELD_SHIFT)) & FLASH_NMPA_GPO1_3_FIELD_MASK) +/*! @} */ + +/*! @name GPO1_ARRAY - GPO1 array description */ +/*! @{ */ + +#define FLASH_NMPA_GPO1_ARRAY_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_NMPA_GPO1_ARRAY_FIELD_SHIFT (0U) +#define FLASH_NMPA_GPO1_ARRAY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO1_ARRAY_FIELD_SHIFT)) & FLASH_NMPA_GPO1_ARRAY_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_NMPA_GPO1_ARRAY */ +#define FLASH_NMPA_GPO1_ARRAY_COUNT (4U) + +/*! @name GPO2_0 - GPO2 register 0 description */ +/*! @{ */ + +#define FLASH_NMPA_GPO2_0_USBHS_PHY_TRIM_VALID_MASK (0x1U) +#define FLASH_NMPA_GPO2_0_USBHS_PHY_TRIM_VALID_SHIFT (0U) +#define FLASH_NMPA_GPO2_0_USBHS_PHY_TRIM_VALID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO2_0_USBHS_PHY_TRIM_VALID_SHIFT)) & FLASH_NMPA_GPO2_0_USBHS_PHY_TRIM_VALID_MASK) + +#define FLASH_NMPA_GPO2_0_TRIM_USB_REG_ENV_TAIL_ADJ_VD_MASK (0x6U) +#define FLASH_NMPA_GPO2_0_TRIM_USB_REG_ENV_TAIL_ADJ_VD_SHIFT (1U) +#define FLASH_NMPA_GPO2_0_TRIM_USB_REG_ENV_TAIL_ADJ_VD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO2_0_TRIM_USB_REG_ENV_TAIL_ADJ_VD_SHIFT)) & FLASH_NMPA_GPO2_0_TRIM_USB_REG_ENV_TAIL_ADJ_VD_MASK) + +#define FLASH_NMPA_GPO2_0_TRIM_USBPHY_TX_D_CAL_MASK (0x78U) +#define FLASH_NMPA_GPO2_0_TRIM_USBPHY_TX_D_CAL_SHIFT (3U) +#define FLASH_NMPA_GPO2_0_TRIM_USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO2_0_TRIM_USBPHY_TX_D_CAL_SHIFT)) & FLASH_NMPA_GPO2_0_TRIM_USBPHY_TX_D_CAL_MASK) + +#define FLASH_NMPA_GPO2_0_TRIM_USBPHY_TX_CAL45DP_MASK (0xF80U) +#define FLASH_NMPA_GPO2_0_TRIM_USBPHY_TX_CAL45DP_SHIFT (7U) +#define FLASH_NMPA_GPO2_0_TRIM_USBPHY_TX_CAL45DP(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO2_0_TRIM_USBPHY_TX_CAL45DP_SHIFT)) & FLASH_NMPA_GPO2_0_TRIM_USBPHY_TX_CAL45DP_MASK) + +#define FLASH_NMPA_GPO2_0_TRIM_USBPHY_TX_CAL45DN_MASK (0x1F000U) +#define FLASH_NMPA_GPO2_0_TRIM_USBPHY_TX_CAL45DN_SHIFT (12U) +#define FLASH_NMPA_GPO2_0_TRIM_USBPHY_TX_CAL45DN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO2_0_TRIM_USBPHY_TX_CAL45DN_SHIFT)) & FLASH_NMPA_GPO2_0_TRIM_USBPHY_TX_CAL45DN_MASK) + +#define FLASH_NMPA_GPO2_0_TRIM_USB2_REFBIAS_TST_MASK (0x60000U) +#define FLASH_NMPA_GPO2_0_TRIM_USB2_REFBIAS_TST_SHIFT (17U) +#define FLASH_NMPA_GPO2_0_TRIM_USB2_REFBIAS_TST(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO2_0_TRIM_USB2_REFBIAS_TST_SHIFT)) & FLASH_NMPA_GPO2_0_TRIM_USB2_REFBIAS_TST_MASK) + +#define FLASH_NMPA_GPO2_0_TRIM_USB2_REFBIAS_VBGADJ_MASK (0x380000U) +#define FLASH_NMPA_GPO2_0_TRIM_USB2_REFBIAS_VBGADJ_SHIFT (19U) +#define FLASH_NMPA_GPO2_0_TRIM_USB2_REFBIAS_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO2_0_TRIM_USB2_REFBIAS_VBGADJ_SHIFT)) & FLASH_NMPA_GPO2_0_TRIM_USB2_REFBIAS_VBGADJ_MASK) + +#define FLASH_NMPA_GPO2_0_TRIM_PLL_CTRL0_DIV_SEL_MASK (0x1C00000U) +#define FLASH_NMPA_GPO2_0_TRIM_PLL_CTRL0_DIV_SEL_SHIFT (22U) +#define FLASH_NMPA_GPO2_0_TRIM_PLL_CTRL0_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO2_0_TRIM_PLL_CTRL0_DIV_SEL_SHIFT)) & FLASH_NMPA_GPO2_0_TRIM_PLL_CTRL0_DIV_SEL_MASK) + +#define FLASH_NMPA_GPO2_0_FLASH_SIZE_MASK (0xE000000U) +#define FLASH_NMPA_GPO2_0_FLASH_SIZE_SHIFT (25U) +/*! FLASH_SIZE - (For Niobe4) 000 : 640 KB 001 : 512 KB 010 : 256 KB 011 : 128 KB 100 : 0 KB All + * others : RESERVED (For Niobe4 Mini) FLASH_SIZE[2:0] 000 : 256 KB 001 : 128 KB 010 : 80 KB + * (reserved) 011 : 64 KB 100 : 0 kB (reserved) All others : RESERVED + */ +#define FLASH_NMPA_GPO2_0_FLASH_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO2_0_FLASH_SIZE_SHIFT)) & FLASH_NMPA_GPO2_0_FLASH_SIZE_MASK) + +#define FLASH_NMPA_GPO2_0_CPU0_SECURITY_EXTENSION_DISABLE_MASK (0xF0000000U) +#define FLASH_NMPA_GPO2_0_CPU0_SECURITY_EXTENSION_DISABLE_SHIFT (28U) +/*! CPU0_SECURITY_EXTENSION_DISABLE - CPU0_SECURITY_EXTENSION_DISABLE[3:0]: 1010 : CPU0 Security + * Extension is disabled. All Other values: CPU0 Security Extension is enabled. + */ +#define FLASH_NMPA_GPO2_0_CPU0_SECURITY_EXTENSION_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO2_0_CPU0_SECURITY_EXTENSION_DISABLE_SHIFT)) & FLASH_NMPA_GPO2_0_CPU0_SECURITY_EXTENSION_DISABLE_MASK) +/*! @} */ + +/*! @name GPO2_1 - GPO2 register 1 description */ +/*! @{ */ + +#define FLASH_NMPA_GPO2_1_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_NMPA_GPO2_1_FIELD_SHIFT (0U) +#define FLASH_NMPA_GPO2_1_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO2_1_FIELD_SHIFT)) & FLASH_NMPA_GPO2_1_FIELD_MASK) +/*! @} */ + +/*! @name GPO2_2 - GPO2 register 2 description */ +/*! @{ */ + +#define FLASH_NMPA_GPO2_2_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_NMPA_GPO2_2_FIELD_SHIFT (0U) +#define FLASH_NMPA_GPO2_2_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO2_2_FIELD_SHIFT)) & FLASH_NMPA_GPO2_2_FIELD_MASK) +/*! @} */ + +/*! @name GPO2_3 - GPO2 register 3 description */ +/*! @{ */ + +#define FLASH_NMPA_GPO2_3_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_NMPA_GPO2_3_FIELD_SHIFT (0U) +#define FLASH_NMPA_GPO2_3_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO2_3_FIELD_SHIFT)) & FLASH_NMPA_GPO2_3_FIELD_MASK) +/*! @} */ + +/*! @name GPO2_ARRAY - GPO2 array description */ +/*! @{ */ + +#define FLASH_NMPA_GPO2_ARRAY_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_NMPA_GPO2_ARRAY_FIELD_SHIFT (0U) +#define FLASH_NMPA_GPO2_ARRAY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO2_ARRAY_FIELD_SHIFT)) & FLASH_NMPA_GPO2_ARRAY_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_NMPA_GPO2_ARRAY */ +#define FLASH_NMPA_GPO2_ARRAY_COUNT (4U) + +/*! @name GPO3_0 - GPO3 register 0 description */ +/*! @{ */ + +#define FLASH_NMPA_GPO3_0_AUX_BIAS_TRIM_VALID_MASK (0x1U) +#define FLASH_NMPA_GPO3_0_AUX_BIAS_TRIM_VALID_SHIFT (0U) +#define FLASH_NMPA_GPO3_0_AUX_BIAS_TRIM_VALID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO3_0_AUX_BIAS_TRIM_VALID_SHIFT)) & FLASH_NMPA_GPO3_0_AUX_BIAS_TRIM_VALID_MASK) + +#define FLASH_NMPA_GPO3_0_AUX_BIAS_ITRIM_MASK (0x3EU) +#define FLASH_NMPA_GPO3_0_AUX_BIAS_ITRIM_SHIFT (1U) +#define FLASH_NMPA_GPO3_0_AUX_BIAS_ITRIM(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO3_0_AUX_BIAS_ITRIM_SHIFT)) & FLASH_NMPA_GPO3_0_AUX_BIAS_ITRIM_MASK) + +#define FLASH_NMPA_GPO3_0_AUX_BIAS_PTAT_ITRIM_MASK (0x7C0U) +#define FLASH_NMPA_GPO3_0_AUX_BIAS_PTAT_ITRIM_SHIFT (6U) +#define FLASH_NMPA_GPO3_0_AUX_BIAS_PTAT_ITRIM(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO3_0_AUX_BIAS_PTAT_ITRIM_SHIFT)) & FLASH_NMPA_GPO3_0_AUX_BIAS_PTAT_ITRIM_MASK) + +#define FLASH_NMPA_GPO3_0_AUX_BIAS_VREF1_VTRIM_MASK (0xF800U) +#define FLASH_NMPA_GPO3_0_AUX_BIAS_VREF1_VTRIM_SHIFT (11U) +#define FLASH_NMPA_GPO3_0_AUX_BIAS_VREF1_VTRIM(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO3_0_AUX_BIAS_VREF1_VTRIM_SHIFT)) & FLASH_NMPA_GPO3_0_AUX_BIAS_VREF1_VTRIM_MASK) + +#define FLASH_NMPA_GPO3_0_AUX_BIAS_VREF1_VCURVE_TRIM_MASK (0x70000U) +#define FLASH_NMPA_GPO3_0_AUX_BIAS_VREF1_VCURVE_TRIM_SHIFT (16U) +#define FLASH_NMPA_GPO3_0_AUX_BIAS_VREF1_VCURVE_TRIM(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO3_0_AUX_BIAS_VREF1_VCURVE_TRIM_SHIFT)) & FLASH_NMPA_GPO3_0_AUX_BIAS_VREF1_VCURVE_TRIM_MASK) + +#define FLASH_NMPA_GPO3_0_FIELD_MASK (0x1F80000U) +#define FLASH_NMPA_GPO3_0_FIELD_SHIFT (19U) +#define FLASH_NMPA_GPO3_0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO3_0_FIELD_SHIFT)) & FLASH_NMPA_GPO3_0_FIELD_MASK) + +#define FLASH_NMPA_GPO3_0_MODELNUM_EXTENSION_MASK (0xE000000U) +#define FLASH_NMPA_GPO3_0_MODELNUM_EXTENSION_SHIFT (25U) +/*! MODELNUM_EXTENSION - ModelNumber extension[2:0] + */ +#define FLASH_NMPA_GPO3_0_MODELNUM_EXTENSION(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO3_0_MODELNUM_EXTENSION_SHIFT)) & FLASH_NMPA_GPO3_0_MODELNUM_EXTENSION_MASK) + +#define FLASH_NMPA_GPO3_0_FINAL_TEST_NOT_DONE_MASK (0xF0000000U) +#define FLASH_NMPA_GPO3_0_FINAL_TEST_NOT_DONE_SHIFT (28U) +/*! FINAL_TEST_NOT_DONE - FINAL_TEST_NOT_DONE[3:0]: 1010 : Final Test Not Done. All Other values: Final Test Done. + */ +#define FLASH_NMPA_GPO3_0_FINAL_TEST_NOT_DONE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO3_0_FINAL_TEST_NOT_DONE_SHIFT)) & FLASH_NMPA_GPO3_0_FINAL_TEST_NOT_DONE_MASK) +/*! @} */ + +/*! @name GPO3_1 - GPO3 register 1 description */ +/*! @{ */ + +#define FLASH_NMPA_GPO3_1_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_NMPA_GPO3_1_FIELD_SHIFT (0U) +#define FLASH_NMPA_GPO3_1_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO3_1_FIELD_SHIFT)) & FLASH_NMPA_GPO3_1_FIELD_MASK) +/*! @} */ + +/*! @name GPO3_2 - GPO3 register 2 description */ +/*! @{ */ + +#define FLASH_NMPA_GPO3_2_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_NMPA_GPO3_2_FIELD_SHIFT (0U) +#define FLASH_NMPA_GPO3_2_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO3_2_FIELD_SHIFT)) & FLASH_NMPA_GPO3_2_FIELD_MASK) +/*! @} */ + +/*! @name GPO3_3 - GPO3 register 3 description */ +/*! @{ */ + +#define FLASH_NMPA_GPO3_3_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_NMPA_GPO3_3_FIELD_SHIFT (0U) +#define FLASH_NMPA_GPO3_3_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO3_3_FIELD_SHIFT)) & FLASH_NMPA_GPO3_3_FIELD_MASK) +/*! @} */ + +/*! @name GPO3_ARRAY - GPO3 array description */ +/*! @{ */ + +#define FLASH_NMPA_GPO3_ARRAY_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_NMPA_GPO3_ARRAY_FIELD_SHIFT (0U) +#define FLASH_NMPA_GPO3_ARRAY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO3_ARRAY_FIELD_SHIFT)) & FLASH_NMPA_GPO3_ARRAY_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_NMPA_GPO3_ARRAY */ +#define FLASH_NMPA_GPO3_ARRAY_COUNT (4U) + +/*! @name GPO_CHECKSUM_0 - checksum of the GPO data in words 0 */ +/*! @{ */ + +#define FLASH_NMPA_GPO_CHECKSUM_0_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_NMPA_GPO_CHECKSUM_0_FIELD_SHIFT (0U) +#define FLASH_NMPA_GPO_CHECKSUM_0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO_CHECKSUM_0_FIELD_SHIFT)) & FLASH_NMPA_GPO_CHECKSUM_0_FIELD_MASK) +/*! @} */ + +/*! @name GPO_CHECKSUM_1 - checksum of the GPO data in words 1 */ +/*! @{ */ + +#define FLASH_NMPA_GPO_CHECKSUM_1_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_NMPA_GPO_CHECKSUM_1_FIELD_SHIFT (0U) +#define FLASH_NMPA_GPO_CHECKSUM_1_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO_CHECKSUM_1_FIELD_SHIFT)) & FLASH_NMPA_GPO_CHECKSUM_1_FIELD_MASK) +/*! @} */ + +/*! @name GPO_CHECKSUM_2 - checksum of the GPO data in words 2 */ +/*! @{ */ + +#define FLASH_NMPA_GPO_CHECKSUM_2_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_NMPA_GPO_CHECKSUM_2_FIELD_SHIFT (0U) +#define FLASH_NMPA_GPO_CHECKSUM_2_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO_CHECKSUM_2_FIELD_SHIFT)) & FLASH_NMPA_GPO_CHECKSUM_2_FIELD_MASK) +/*! @} */ + +/*! @name GPO_CHECKSUM_3 - checksum of the GPO data in words 3 */ +/*! @{ */ + +#define FLASH_NMPA_GPO_CHECKSUM_3_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_NMPA_GPO_CHECKSUM_3_FIELD_SHIFT (0U) +#define FLASH_NMPA_GPO_CHECKSUM_3_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO_CHECKSUM_3_FIELD_SHIFT)) & FLASH_NMPA_GPO_CHECKSUM_3_FIELD_MASK) +/*! @} */ + +/*! @name GPO_CHECKSUM_ARRAY - checksum of the GPO data in words [3:0] */ +/*! @{ */ + +#define FLASH_NMPA_GPO_CHECKSUM_ARRAY_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_NMPA_GPO_CHECKSUM_ARRAY_FIELD_SHIFT (0U) +#define FLASH_NMPA_GPO_CHECKSUM_ARRAY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_GPO_CHECKSUM_ARRAY_FIELD_SHIFT)) & FLASH_NMPA_GPO_CHECKSUM_ARRAY_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_NMPA_GPO_CHECKSUM_ARRAY */ +#define FLASH_NMPA_GPO_CHECKSUM_ARRAY_COUNT (4U) + +/*! @name FINAL_TEST_BATCH_ID_0 - */ +/*! @{ */ + +#define FLASH_NMPA_FINAL_TEST_BATCH_ID_0_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_NMPA_FINAL_TEST_BATCH_ID_0_FIELD_SHIFT (0U) +#define FLASH_NMPA_FINAL_TEST_BATCH_ID_0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_FINAL_TEST_BATCH_ID_0_FIELD_SHIFT)) & FLASH_NMPA_FINAL_TEST_BATCH_ID_0_FIELD_MASK) +/*! @} */ + +/*! @name FINAL_TEST_BATCH_ID_1 - */ +/*! @{ */ + +#define FLASH_NMPA_FINAL_TEST_BATCH_ID_1_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_NMPA_FINAL_TEST_BATCH_ID_1_FIELD_SHIFT (0U) +#define FLASH_NMPA_FINAL_TEST_BATCH_ID_1_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_FINAL_TEST_BATCH_ID_1_FIELD_SHIFT)) & FLASH_NMPA_FINAL_TEST_BATCH_ID_1_FIELD_MASK) +/*! @} */ + +/*! @name FINAL_TEST_BATCH_ID_2 - */ +/*! @{ */ + +#define FLASH_NMPA_FINAL_TEST_BATCH_ID_2_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_NMPA_FINAL_TEST_BATCH_ID_2_FIELD_SHIFT (0U) +#define FLASH_NMPA_FINAL_TEST_BATCH_ID_2_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_FINAL_TEST_BATCH_ID_2_FIELD_SHIFT)) & FLASH_NMPA_FINAL_TEST_BATCH_ID_2_FIELD_MASK) +/*! @} */ + +/*! @name FINAL_TEST_BATCH_ID_3 - */ +/*! @{ */ + +#define FLASH_NMPA_FINAL_TEST_BATCH_ID_3_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_NMPA_FINAL_TEST_BATCH_ID_3_FIELD_SHIFT (0U) +#define FLASH_NMPA_FINAL_TEST_BATCH_ID_3_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_FINAL_TEST_BATCH_ID_3_FIELD_SHIFT)) & FLASH_NMPA_FINAL_TEST_BATCH_ID_3_FIELD_MASK) +/*! @} */ + +/*! @name FINAL_TEST_BATCH_ID_ARRAY - */ +/*! @{ */ + +#define FLASH_NMPA_FINAL_TEST_BATCH_ID_ARRAY_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_NMPA_FINAL_TEST_BATCH_ID_ARRAY_FIELD_SHIFT (0U) +#define FLASH_NMPA_FINAL_TEST_BATCH_ID_ARRAY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_FINAL_TEST_BATCH_ID_ARRAY_FIELD_SHIFT)) & FLASH_NMPA_FINAL_TEST_BATCH_ID_ARRAY_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_NMPA_FINAL_TEST_BATCH_ID_ARRAY */ +#define FLASH_NMPA_FINAL_TEST_BATCH_ID_ARRAY_COUNT (4U) + +/*! @name DEVICE_TYPE - */ +/*! @{ */ + +#define FLASH_NMPA_DEVICE_TYPE_DEVICE_TYPE_NUM_MASK (0xFFFFU) +#define FLASH_NMPA_DEVICE_TYPE_DEVICE_TYPE_NUM_SHIFT (0U) +/*! DEVICE_TYPE_NUM - Device type number. (E.g : LPC5569 stored as 5569 decimal) + */ +#define FLASH_NMPA_DEVICE_TYPE_DEVICE_TYPE_NUM(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DEVICE_TYPE_DEVICE_TYPE_NUM_SHIFT)) & FLASH_NMPA_DEVICE_TYPE_DEVICE_TYPE_NUM_MASK) + +#define FLASH_NMPA_DEVICE_TYPE_DEVICE_TYPE_SEC_MASK (0x10000U) +#define FLASH_NMPA_DEVICE_TYPE_DEVICE_TYPE_SEC_SHIFT (16U) +/*! DEVICE_TYPE_SEC - Security device type: 0: LPC55xxx (Non Secure Familly) 1: LPC55Sxxx (Secure Familly) + */ +#define FLASH_NMPA_DEVICE_TYPE_DEVICE_TYPE_SEC(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DEVICE_TYPE_DEVICE_TYPE_SEC_SHIFT)) & FLASH_NMPA_DEVICE_TYPE_DEVICE_TYPE_SEC_MASK) + +#define FLASH_NMPA_DEVICE_TYPE_DEVICE_TYPE_PKG_MASK (0xF00000U) +#define FLASH_NMPA_DEVICE_TYPE_DEVICE_TYPE_PKG_SHIFT (20U) +/*! DEVICE_TYPE_PKG - Device package type: 0000 : HLQFP 0001 : HTQFP 0010 : HVQFN 0100 : VFBGA 1000 : WLCSP + */ +#define FLASH_NMPA_DEVICE_TYPE_DEVICE_TYPE_PKG(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DEVICE_TYPE_DEVICE_TYPE_PKG_SHIFT)) & FLASH_NMPA_DEVICE_TYPE_DEVICE_TYPE_PKG_MASK) + +#define FLASH_NMPA_DEVICE_TYPE_DEVICE_TYPE_PIN_MASK (0xFF000000U) +#define FLASH_NMPA_DEVICE_TYPE_DEVICE_TYPE_PIN_SHIFT (24U) +/*! DEVICE_TYPE_PIN - Number of pins on the package. + */ +#define FLASH_NMPA_DEVICE_TYPE_DEVICE_TYPE_PIN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DEVICE_TYPE_DEVICE_TYPE_PIN_SHIFT)) & FLASH_NMPA_DEVICE_TYPE_DEVICE_TYPE_PIN_MASK) +/*! @} */ + +/*! @name FINAL_TEST_PROGRAM_VERSION - */ +/*! @{ */ + +#define FLASH_NMPA_FINAL_TEST_PROGRAM_VERSION_PROGRAM_VERSION_MASK (0xFFFFFFFFU) +#define FLASH_NMPA_FINAL_TEST_PROGRAM_VERSION_PROGRAM_VERSION_SHIFT (0U) +/*! PROGRAM_VERSION - PROGRAM_VERSION [xx.yy stored as : 100*x+y] + */ +#define FLASH_NMPA_FINAL_TEST_PROGRAM_VERSION_PROGRAM_VERSION(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_FINAL_TEST_PROGRAM_VERSION_PROGRAM_VERSION_SHIFT)) & FLASH_NMPA_FINAL_TEST_PROGRAM_VERSION_PROGRAM_VERSION_MASK) +/*! @} */ + +/*! @name FINAL_TEST_DATE - */ +/*! @{ */ + +#define FLASH_NMPA_FINAL_TEST_DATE_DATE_MASK (0xFFFFFFFFU) +#define FLASH_NMPA_FINAL_TEST_DATE_DATE_SHIFT (0U) +/*! DATE - DATE [stored as : year*10000+month*100+day] + */ +#define FLASH_NMPA_FINAL_TEST_DATE_DATE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_FINAL_TEST_DATE_DATE_SHIFT)) & FLASH_NMPA_FINAL_TEST_DATE_DATE_MASK) +/*! @} */ + +/*! @name FINAL_TEST_TIME - */ +/*! @{ */ + +#define FLASH_NMPA_FINAL_TEST_TIME_TIME_MASK (0xFFFFFFFFU) +#define FLASH_NMPA_FINAL_TEST_TIME_TIME_SHIFT (0U) +/*! TIME - TIME [stored as : hour*10000+minute*100+seconde] + */ +#define FLASH_NMPA_FINAL_TEST_TIME_TIME(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_FINAL_TEST_TIME_TIME_SHIFT)) & FLASH_NMPA_FINAL_TEST_TIME_TIME_MASK) +/*! @} */ + +/*! @name UUID_0 - */ +/*! @{ */ + +#define FLASH_NMPA_UUID_0_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_NMPA_UUID_0_FIELD_SHIFT (0U) +#define FLASH_NMPA_UUID_0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_UUID_0_FIELD_SHIFT)) & FLASH_NMPA_UUID_0_FIELD_MASK) +/*! @} */ + +/*! @name UUID_1 - */ +/*! @{ */ + +#define FLASH_NMPA_UUID_1_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_NMPA_UUID_1_FIELD_SHIFT (0U) +#define FLASH_NMPA_UUID_1_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_UUID_1_FIELD_SHIFT)) & FLASH_NMPA_UUID_1_FIELD_MASK) +/*! @} */ + +/*! @name UUID_2 - */ +/*! @{ */ + +#define FLASH_NMPA_UUID_2_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_NMPA_UUID_2_FIELD_SHIFT (0U) +#define FLASH_NMPA_UUID_2_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_UUID_2_FIELD_SHIFT)) & FLASH_NMPA_UUID_2_FIELD_MASK) +/*! @} */ + +/*! @name UUID_3 - */ +/*! @{ */ + +#define FLASH_NMPA_UUID_3_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_NMPA_UUID_3_FIELD_SHIFT (0U) +#define FLASH_NMPA_UUID_3_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_UUID_3_FIELD_SHIFT)) & FLASH_NMPA_UUID_3_FIELD_MASK) +/*! @} */ + +/*! @name UUID_ARRAY - */ +/*! @{ */ + +#define FLASH_NMPA_UUID_ARRAY_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_NMPA_UUID_ARRAY_FIELD_SHIFT (0U) +#define FLASH_NMPA_UUID_ARRAY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_UUID_ARRAY_FIELD_SHIFT)) & FLASH_NMPA_UUID_ARRAY_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_NMPA_UUID_ARRAY */ +#define FLASH_NMPA_UUID_ARRAY_COUNT (4U) + +/*! @name WAFER_TEST1_PROGRAM_VERSION - */ +/*! @{ */ + +#define FLASH_NMPA_WAFER_TEST1_PROGRAM_VERSION_WT1_PROGRAM_VERSION_MASK (0xFFFFFFFFU) +#define FLASH_NMPA_WAFER_TEST1_PROGRAM_VERSION_WT1_PROGRAM_VERSION_SHIFT (0U) +/*! WT1_PROGRAM_VERSION - WT1_PROGRAM_VERSION [xx.yy stored as : 100*x+y] + */ +#define FLASH_NMPA_WAFER_TEST1_PROGRAM_VERSION_WT1_PROGRAM_VERSION(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_WAFER_TEST1_PROGRAM_VERSION_WT1_PROGRAM_VERSION_SHIFT)) & FLASH_NMPA_WAFER_TEST1_PROGRAM_VERSION_WT1_PROGRAM_VERSION_MASK) +/*! @} */ + +/*! @name WAFER_TEST1_DATE - */ +/*! @{ */ + +#define FLASH_NMPA_WAFER_TEST1_DATE_WT1_DATE_MASK (0xFFFFFFFFU) +#define FLASH_NMPA_WAFER_TEST1_DATE_WT1_DATE_SHIFT (0U) +/*! WT1_DATE - WT1_DATE [stored as : year*10000+month*100+day] + */ +#define FLASH_NMPA_WAFER_TEST1_DATE_WT1_DATE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_WAFER_TEST1_DATE_WT1_DATE_SHIFT)) & FLASH_NMPA_WAFER_TEST1_DATE_WT1_DATE_MASK) +/*! @} */ + +/*! @name WAFER_TEST1_TIME - */ +/*! @{ */ + +#define FLASH_NMPA_WAFER_TEST1_TIME_WT1_TIME_MASK (0xFFFFFFFFU) +#define FLASH_NMPA_WAFER_TEST1_TIME_WT1_TIME_SHIFT (0U) +/*! WT1_TIME - WT1_TIME [stored as : hour*10000+minute*100+seconde] + */ +#define FLASH_NMPA_WAFER_TEST1_TIME_WT1_TIME(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_WAFER_TEST1_TIME_WT1_TIME_SHIFT)) & FLASH_NMPA_WAFER_TEST1_TIME_WT1_TIME_MASK) +/*! @} */ + +/*! @name WAFER_TEST2_PROGRAM_VERSION - */ +/*! @{ */ + +#define FLASH_NMPA_WAFER_TEST2_PROGRAM_VERSION_WT2_PROGRAM_VERSION_MASK (0xFFFFFFFFU) +#define FLASH_NMPA_WAFER_TEST2_PROGRAM_VERSION_WT2_PROGRAM_VERSION_SHIFT (0U) +/*! WT2_PROGRAM_VERSION - WT2_PROGRAM_VERSION [xx.yy stored as : 100*x+y] + */ +#define FLASH_NMPA_WAFER_TEST2_PROGRAM_VERSION_WT2_PROGRAM_VERSION(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_WAFER_TEST2_PROGRAM_VERSION_WT2_PROGRAM_VERSION_SHIFT)) & FLASH_NMPA_WAFER_TEST2_PROGRAM_VERSION_WT2_PROGRAM_VERSION_MASK) +/*! @} */ + +/*! @name WAFER_TEST2_DATE - */ +/*! @{ */ + +#define FLASH_NMPA_WAFER_TEST2_DATE_WT2_DATE_MASK (0xFFFFFFFFU) +#define FLASH_NMPA_WAFER_TEST2_DATE_WT2_DATE_SHIFT (0U) +/*! WT2_DATE - WT2_DATE [stored as : year*10000+month*100+day] + */ +#define FLASH_NMPA_WAFER_TEST2_DATE_WT2_DATE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_WAFER_TEST2_DATE_WT2_DATE_SHIFT)) & FLASH_NMPA_WAFER_TEST2_DATE_WT2_DATE_MASK) +/*! @} */ + +/*! @name WAFER_TEST2_TIME - */ +/*! @{ */ + +#define FLASH_NMPA_WAFER_TEST2_TIME_WT2_TIME_MASK (0xFFFFFFFFU) +#define FLASH_NMPA_WAFER_TEST2_TIME_WT2_TIME_SHIFT (0U) +/*! WT2_TIME - WT2_TIME [stored as : hour*10000+minute*100+seconde] + */ +#define FLASH_NMPA_WAFER_TEST2_TIME_WT2_TIME(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_WAFER_TEST2_TIME_WT2_TIME_SHIFT)) & FLASH_NMPA_WAFER_TEST2_TIME_WT2_TIME_MASK) +/*! @} */ + +/*! @name USBCFG - */ +/*! @{ */ + +#define FLASH_NMPA_USBCFG_XO32M_READY_TIME_OUT_MS_MASK (0xFFU) +#define FLASH_NMPA_USBCFG_XO32M_READY_TIME_OUT_MS_SHIFT (0U) +#define FLASH_NMPA_USBCFG_XO32M_READY_TIME_OUT_MS(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_USBCFG_XO32M_READY_TIME_OUT_MS_SHIFT)) & FLASH_NMPA_USBCFG_XO32M_READY_TIME_OUT_MS_MASK) + +#define FLASH_NMPA_USBCFG_USB_SPEED_MASK (0xFF00U) +#define FLASH_NMPA_USBCFG_USB_SPEED_SHIFT (8U) +/*! USB_SPEED - USB_SPEED[7:0]= 0x00 : USB High Speed Module used for ISP 0x01 : USB Full SPeed + * Module used for ISP 0x02 : Neither USB High Speed module nor USB Full Speed module used for ISP + * 0x03 - 0xFF : RESERVED + */ +#define FLASH_NMPA_USBCFG_USB_SPEED(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_USBCFG_USB_SPEED_SHIFT)) & FLASH_NMPA_USBCFG_USB_SPEED_MASK) + +#define FLASH_NMPA_USBCFG_USB_USE_XO32M_CAPA_BANKS_MASK (0x10000U) +#define FLASH_NMPA_USBCFG_USB_USE_XO32M_CAPA_BANKS_SHIFT (16U) +/*! USB_USE_XO32M_CAPA_BANKS - Enable the use of Crystal 32 MHz internal Capa Banks during the + * configuration of the High Speed USB for ISP: 0: Disable Crystal 32 MHz CapaBanks. 1: Enable Crystal + * 32 MHz CapaBanks. + */ +#define FLASH_NMPA_USBCFG_USB_USE_XO32M_CAPA_BANKS(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_USBCFG_USB_USE_XO32M_CAPA_BANKS_SHIFT)) & FLASH_NMPA_USBCFG_USB_USE_XO32M_CAPA_BANKS_MASK) +/*! @} */ + +/*! @name PERIPHENCFG - */ +/*! @{ */ + +#define FLASH_NMPA_PERIPHENCFG_PERIPHERAL_CONFIGURATION_MASK (0xFFFFU) +#define FLASH_NMPA_PERIPHENCFG_PERIPHERAL_CONFIGURATION_SHIFT (0U) +#define FLASH_NMPA_PERIPHENCFG_PERIPHERAL_CONFIGURATION(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_PERIPHENCFG_PERIPHERAL_CONFIGURATION_SHIFT)) & FLASH_NMPA_PERIPHENCFG_PERIPHERAL_CONFIGURATION_MASK) + +#define FLASH_NMPA_PERIPHENCFG_CPU1_ENABLE_MASK (0x80000000U) +#define FLASH_NMPA_PERIPHENCFG_CPU1_ENABLE_SHIFT (31U) +#define FLASH_NMPA_PERIPHENCFG_CPU1_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_PERIPHENCFG_CPU1_ENABLE_SHIFT)) & FLASH_NMPA_PERIPHENCFG_CPU1_ENABLE_MASK) +/*! @} */ + +/*! @name RAMSIZECFG - */ +/*! @{ */ + +#define FLASH_NMPA_RAMSIZECFG_SRAM_CONFIGURATION_MASK (0xFFFFFFFFU) +#define FLASH_NMPA_RAMSIZECFG_SRAM_CONFIGURATION_SHIFT (0U) +#define FLASH_NMPA_RAMSIZECFG_SRAM_CONFIGURATION(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_RAMSIZECFG_SRAM_CONFIGURATION_SHIFT)) & FLASH_NMPA_RAMSIZECFG_SRAM_CONFIGURATION_MASK) +/*! @} */ + +/*! @name FLASHSIZECFG - */ +/*! @{ */ + +#define FLASH_NMPA_FLASHSIZECFG_FLASH_CONFIGURATION_MASK (0xFFFFFFFFU) +#define FLASH_NMPA_FLASHSIZECFG_FLASH_CONFIGURATION_SHIFT (0U) +#define FLASH_NMPA_FLASHSIZECFG_FLASH_CONFIGURATION(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_FLASHSIZECFG_FLASH_CONFIGURATION_SHIFT)) & FLASH_NMPA_FLASHSIZECFG_FLASH_CONFIGURATION_MASK) +/*! @} */ + +/*! @name RINGO_0 - */ +/*! @{ */ + +#define FLASH_NMPA_RINGO_0_RINGO_0_CTRL_VALID_MASK (0x1U) +#define FLASH_NMPA_RINGO_0_RINGO_0_CTRL_VALID_SHIFT (0U) +/*! RINGO_0_CTRL_VALID - 1: RINGO_0_CTRL is valid. + */ +#define FLASH_NMPA_RINGO_0_RINGO_0_CTRL_VALID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_RINGO_0_RINGO_0_CTRL_VALID_SHIFT)) & FLASH_NMPA_RINGO_0_RINGO_0_CTRL_VALID_MASK) + +#define FLASH_NMPA_RINGO_0_RINGO_0_CTRL_MASK (0xFFFFFFFEU) +#define FLASH_NMPA_RINGO_0_RINGO_0_CTRL_SHIFT (1U) +/*! RINGO_0_CTRL - To copy RINGO_0_CTRL = ANACTRL->RINGO0_CTRL[30:0] + */ +#define FLASH_NMPA_RINGO_0_RINGO_0_CTRL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_RINGO_0_RINGO_0_CTRL_SHIFT)) & FLASH_NMPA_RINGO_0_RINGO_0_CTRL_MASK) +/*! @} */ + +/*! @name RINGO_1 - */ +/*! @{ */ + +#define FLASH_NMPA_RINGO_1_RINGO_1_CTRL_VALID_MASK (0x1U) +#define FLASH_NMPA_RINGO_1_RINGO_1_CTRL_VALID_SHIFT (0U) +/*! RINGO_1_CTRL_VALID - 1: RINGO_1_CTRL is valid. + */ +#define FLASH_NMPA_RINGO_1_RINGO_1_CTRL_VALID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_RINGO_1_RINGO_1_CTRL_VALID_SHIFT)) & FLASH_NMPA_RINGO_1_RINGO_1_CTRL_VALID_MASK) + +#define FLASH_NMPA_RINGO_1_RINGO_1_CTRL_MASK (0xFFFFFFFEU) +#define FLASH_NMPA_RINGO_1_RINGO_1_CTRL_SHIFT (1U) +/*! RINGO_1_CTRL - To copy RINGO_1_CTRL = ANACTRL->RINGO1_CTRL[30:0] + */ +#define FLASH_NMPA_RINGO_1_RINGO_1_CTRL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_RINGO_1_RINGO_1_CTRL_SHIFT)) & FLASH_NMPA_RINGO_1_RINGO_1_CTRL_MASK) +/*! @} */ + +/*! @name RINGO_2 - */ +/*! @{ */ + +#define FLASH_NMPA_RINGO_2_RINGO_2_CTRL_VALID_MASK (0x1U) +#define FLASH_NMPA_RINGO_2_RINGO_2_CTRL_VALID_SHIFT (0U) +/*! RINGO_2_CTRL_VALID - 1: RINGO_2_CTRL is valid. + */ +#define FLASH_NMPA_RINGO_2_RINGO_2_CTRL_VALID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_RINGO_2_RINGO_2_CTRL_VALID_SHIFT)) & FLASH_NMPA_RINGO_2_RINGO_2_CTRL_VALID_MASK) + +#define FLASH_NMPA_RINGO_2_RINGO_2_CTRL_MASK (0xFFFFFFFEU) +#define FLASH_NMPA_RINGO_2_RINGO_2_CTRL_SHIFT (1U) +/*! RINGO_2_CTRL - To copy RINGO_2_CTRL = ANACTRL->RINGO2_CTRL[30:0] + */ +#define FLASH_NMPA_RINGO_2_RINGO_2_CTRL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_RINGO_2_RINGO_2_CTRL_SHIFT)) & FLASH_NMPA_RINGO_2_RINGO_2_CTRL_MASK) +/*! @} */ + +/*! @name FRO_192MHZ - */ +/*! @{ */ + +#define FLASH_NMPA_FRO_192MHZ_FRO192M_TRIM_VALID_MASK (0x1U) +#define FLASH_NMPA_FRO_192MHZ_FRO192M_TRIM_VALID_SHIFT (0U) +#define FLASH_NMPA_FRO_192MHZ_FRO192M_TRIM_VALID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_FRO_192MHZ_FRO192M_TRIM_VALID_SHIFT)) & FLASH_NMPA_FRO_192MHZ_FRO192M_TRIM_VALID_MASK) + +#define FLASH_NMPA_FRO_192MHZ_FRO192M_BIASTRIM_MASK (0x7EU) +#define FLASH_NMPA_FRO_192MHZ_FRO192M_BIASTRIM_SHIFT (1U) +/*! FRO192M_BIASTRIM - FRO192M_BIASTRIM[5:0]. + */ +#define FLASH_NMPA_FRO_192MHZ_FRO192M_BIASTRIM(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_FRO_192MHZ_FRO192M_BIASTRIM_SHIFT)) & FLASH_NMPA_FRO_192MHZ_FRO192M_BIASTRIM_MASK) + +#define FLASH_NMPA_FRO_192MHZ_FRO192M_TEMPTRIM_MASK (0x7F00U) +#define FLASH_NMPA_FRO_192MHZ_FRO192M_TEMPTRIM_SHIFT (8U) +/*! FRO192M_TEMPTRIM - FRO192M_TEMPTRIM[6:0]. + */ +#define FLASH_NMPA_FRO_192MHZ_FRO192M_TEMPTRIM(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_FRO_192MHZ_FRO192M_TEMPTRIM_SHIFT)) & FLASH_NMPA_FRO_192MHZ_FRO192M_TEMPTRIM_MASK) + +#define FLASH_NMPA_FRO_192MHZ_FRO192M_DACTRIM_MASK (0x1FE0000U) +#define FLASH_NMPA_FRO_192MHZ_FRO192M_DACTRIM_SHIFT (17U) +/*! FRO192M_DACTRIM - FRO192M_DACTRIM[7:0]. + */ +#define FLASH_NMPA_FRO_192MHZ_FRO192M_DACTRIM(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_FRO_192MHZ_FRO192M_DACTRIM_SHIFT)) & FLASH_NMPA_FRO_192MHZ_FRO192M_DACTRIM_MASK) +/*! @} */ + +/*! @name XO_32MHZ - */ +/*! @{ */ + +#define FLASH_NMPA_XO_32MHZ_XO32M_XIN_TRIM_VALID_MASK (0x1U) +#define FLASH_NMPA_XO_32MHZ_XO32M_XIN_TRIM_VALID_SHIFT (0U) +#define FLASH_NMPA_XO_32MHZ_XO32M_XIN_TRIM_VALID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_XO_32MHZ_XO32M_XIN_TRIM_VALID_SHIFT)) & FLASH_NMPA_XO_32MHZ_XO32M_XIN_TRIM_VALID_MASK) + +#define FLASH_NMPA_XO_32MHZ_XO32M_XIN_CAPCAL_6PF_MASK (0xFEU) +#define FLASH_NMPA_XO_32MHZ_XO32M_XIN_CAPCAL_6PF_SHIFT (1U) +#define FLASH_NMPA_XO_32MHZ_XO32M_XIN_CAPCAL_6PF(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_XO_32MHZ_XO32M_XIN_CAPCAL_6PF_SHIFT)) & FLASH_NMPA_XO_32MHZ_XO32M_XIN_CAPCAL_6PF_MASK) + +#define FLASH_NMPA_XO_32MHZ_XO32M_XIN_CAPCAL_8PF_MASK (0x7F00U) +#define FLASH_NMPA_XO_32MHZ_XO32M_XIN_CAPCAL_8PF_SHIFT (8U) +#define FLASH_NMPA_XO_32MHZ_XO32M_XIN_CAPCAL_8PF(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_XO_32MHZ_XO32M_XIN_CAPCAL_8PF_SHIFT)) & FLASH_NMPA_XO_32MHZ_XO32M_XIN_CAPCAL_8PF_MASK) + +#define FLASH_NMPA_XO_32MHZ_XO32M_XOUT_TRIM_VALID_MASK (0x8000U) +#define FLASH_NMPA_XO_32MHZ_XO32M_XOUT_TRIM_VALID_SHIFT (15U) +#define FLASH_NMPA_XO_32MHZ_XO32M_XOUT_TRIM_VALID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_XO_32MHZ_XO32M_XOUT_TRIM_VALID_SHIFT)) & FLASH_NMPA_XO_32MHZ_XO32M_XOUT_TRIM_VALID_MASK) + +#define FLASH_NMPA_XO_32MHZ_XO32M_XOUT_CAPCAL_6PF_MASK (0x7F0000U) +#define FLASH_NMPA_XO_32MHZ_XO32M_XOUT_CAPCAL_6PF_SHIFT (16U) +#define FLASH_NMPA_XO_32MHZ_XO32M_XOUT_CAPCAL_6PF(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_XO_32MHZ_XO32M_XOUT_CAPCAL_6PF_SHIFT)) & FLASH_NMPA_XO_32MHZ_XO32M_XOUT_CAPCAL_6PF_MASK) + +#define FLASH_NMPA_XO_32MHZ_XO32M_XOUT_CAPCAL_8PF_MASK (0x3F800000U) +#define FLASH_NMPA_XO_32MHZ_XO32M_XOUT_CAPCAL_8PF_SHIFT (23U) +#define FLASH_NMPA_XO_32MHZ_XO32M_XOUT_CAPCAL_8PF(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_XO_32MHZ_XO32M_XOUT_CAPCAL_8PF_SHIFT)) & FLASH_NMPA_XO_32MHZ_XO32M_XOUT_CAPCAL_8PF_MASK) + +#define FLASH_NMPA_XO_32MHZ_XO32M_XO_SLAVE_STATUS_MASK (0x40000000U) +#define FLASH_NMPA_XO_32MHZ_XO32M_XO_SLAVE_STATUS_SHIFT (30U) +#define FLASH_NMPA_XO_32MHZ_XO32M_XO_SLAVE_STATUS(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_XO_32MHZ_XO32M_XO_SLAVE_STATUS_SHIFT)) & FLASH_NMPA_XO_32MHZ_XO32M_XO_SLAVE_STATUS_MASK) + +#define FLASH_NMPA_XO_32MHZ_XO32M_XO_AC_BUF_STATUS_MASK (0x80000000U) +#define FLASH_NMPA_XO_32MHZ_XO32M_XO_AC_BUF_STATUS_SHIFT (31U) +#define FLASH_NMPA_XO_32MHZ_XO32M_XO_AC_BUF_STATUS(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_XO_32MHZ_XO32M_XO_AC_BUF_STATUS_SHIFT)) & FLASH_NMPA_XO_32MHZ_XO32M_XO_AC_BUF_STATUS_MASK) +/*! @} */ + +/*! @name XO_32KHZ - */ +/*! @{ */ + +#define FLASH_NMPA_XO_32KHZ_XO32K_XIN_TRIM_VALID_MASK (0x1U) +#define FLASH_NMPA_XO_32KHZ_XO32K_XIN_TRIM_VALID_SHIFT (0U) +#define FLASH_NMPA_XO_32KHZ_XO32K_XIN_TRIM_VALID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_XO_32KHZ_XO32K_XIN_TRIM_VALID_SHIFT)) & FLASH_NMPA_XO_32KHZ_XO32K_XIN_TRIM_VALID_MASK) + +#define FLASH_NMPA_XO_32KHZ_XO32K_XIN_CAPCAL_6PF_MASK (0xFEU) +#define FLASH_NMPA_XO_32KHZ_XO32K_XIN_CAPCAL_6PF_SHIFT (1U) +#define FLASH_NMPA_XO_32KHZ_XO32K_XIN_CAPCAL_6PF(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_XO_32KHZ_XO32K_XIN_CAPCAL_6PF_SHIFT)) & FLASH_NMPA_XO_32KHZ_XO32K_XIN_CAPCAL_6PF_MASK) + +#define FLASH_NMPA_XO_32KHZ_XO32K_XIN_CAPCAL_8PF_MASK (0x7F00U) +#define FLASH_NMPA_XO_32KHZ_XO32K_XIN_CAPCAL_8PF_SHIFT (8U) +#define FLASH_NMPA_XO_32KHZ_XO32K_XIN_CAPCAL_8PF(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_XO_32KHZ_XO32K_XIN_CAPCAL_8PF_SHIFT)) & FLASH_NMPA_XO_32KHZ_XO32K_XIN_CAPCAL_8PF_MASK) + +#define FLASH_NMPA_XO_32KHZ_XO32K_XOUT_TRIM_VALID_MASK (0x8000U) +#define FLASH_NMPA_XO_32KHZ_XO32K_XOUT_TRIM_VALID_SHIFT (15U) +#define FLASH_NMPA_XO_32KHZ_XO32K_XOUT_TRIM_VALID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_XO_32KHZ_XO32K_XOUT_TRIM_VALID_SHIFT)) & FLASH_NMPA_XO_32KHZ_XO32K_XOUT_TRIM_VALID_MASK) + +#define FLASH_NMPA_XO_32KHZ_XO32K_XOUT_CAPCAL_6PF_MASK (0x7F0000U) +#define FLASH_NMPA_XO_32KHZ_XO32K_XOUT_CAPCAL_6PF_SHIFT (16U) +#define FLASH_NMPA_XO_32KHZ_XO32K_XOUT_CAPCAL_6PF(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_XO_32KHZ_XO32K_XOUT_CAPCAL_6PF_SHIFT)) & FLASH_NMPA_XO_32KHZ_XO32K_XOUT_CAPCAL_6PF_MASK) + +#define FLASH_NMPA_XO_32KHZ_XO32K_XOUT_CAPCAL_8PF_MASK (0x3F800000U) +#define FLASH_NMPA_XO_32KHZ_XO32K_XOUT_CAPCAL_8PF_SHIFT (23U) +#define FLASH_NMPA_XO_32KHZ_XO32K_XOUT_CAPCAL_8PF(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_XO_32KHZ_XO32K_XOUT_CAPCAL_8PF_SHIFT)) & FLASH_NMPA_XO_32KHZ_XO32K_XOUT_CAPCAL_8PF_MASK) +/*! @} */ + +/*! @name FRO_1MHZ - */ +/*! @{ */ + +#define FLASH_NMPA_FRO_1MHZ_FRO1M_TRIM_VALID_MASK (0x1U) +#define FLASH_NMPA_FRO_1MHZ_FRO1M_TRIM_VALID_SHIFT (0U) +#define FLASH_NMPA_FRO_1MHZ_FRO1M_TRIM_VALID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_FRO_1MHZ_FRO1M_TRIM_VALID_SHIFT)) & FLASH_NMPA_FRO_1MHZ_FRO1M_TRIM_VALID_MASK) + +#define FLASH_NMPA_FRO_1MHZ_FRO1M_FREQSEL_MASK (0xFEU) +#define FLASH_NMPA_FRO_1MHZ_FRO1M_FREQSEL_SHIFT (1U) +/*! FRO1M_FREQSEL - Frequency trimming bits. + */ +#define FLASH_NMPA_FRO_1MHZ_FRO1M_FREQSEL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_FRO_1MHZ_FRO1M_FREQSEL_SHIFT)) & FLASH_NMPA_FRO_1MHZ_FRO1M_FREQSEL_MASK) +/*! @} */ + +/*! @name DCDC_POWER_PROFILE_HIGH_0 - */ +/*! @{ */ + +#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_DCDC_TRIM_VALID_MASK (0x1U) +#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_DCDC_TRIM_VALID_SHIFT (0U) +/*! DCDC_TRIM_VALID - DCDC is trimed. + */ +#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_DCDC_TRIM_VALID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_DCDC_TRIM_VALID_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_DCDC_TRIM_VALID_MASK) + +#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_RC_MASK (0x7EU) +#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_RC_SHIFT (1U) +/*! RC - Constant On-Time calibration. + */ +#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_RC(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_RC_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_RC_MASK) + +#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_ICOMP_MASK (0x180U) +#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_ICOMP_SHIFT (7U) +/*! ICOMP - Select the type of ZCD comparator. + */ +#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_ICOMP(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_ICOMP_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_ICOMP_MASK) + +#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_ISEL_MASK (0x600U) +#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_ISEL_SHIFT (9U) +/*! ISEL - Alter Internal biasing currents. + */ +#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_ISEL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_ISEL_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_ISEL_MASK) + +#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_ICENABLE_MASK (0x800U) +#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_ICENABLE_SHIFT (11U) +/*! ICENABLE - Selection of auto scaling of COT period with variations in VDD. + */ +#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_ICENABLE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_ICENABLE_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_ICENABLE_MASK) + +#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_TMOS_MASK (0x1F000U) +#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_TMOS_SHIFT (12U) +/*! TMOS - One-shot generator reference current trimming signal. + */ +#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_TMOS(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_TMOS_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_TMOS_MASK) + +#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_DISABLEISENSE_MASK (0x20000U) +#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_DISABLEISENSE_SHIFT (17U) +/*! DISABLEISENSE - Disable Current sensing. + */ +#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_DISABLEISENSE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_DISABLEISENSE_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_DISABLEISENSE_MASK) + +#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_VOUT_MASK (0x3C0000U) +#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_VOUT_SHIFT (18U) +/*! VOUT - Set output regulation voltage. + */ +#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_VOUT(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_VOUT_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_VOUT_MASK) + +#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_SLICINGENABLE_MASK (0x400000U) +#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_SLICINGENABLE_SHIFT (22U) +/*! SLICINGENABLE - Enable staggered switching of power switches. + */ +#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_SLICINGENABLE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_SLICINGENABLE_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_SLICINGENABLE_MASK) + +#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_INDUCTORCLAMPENABLE_MASK (0x800000U) +#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_INDUCTORCLAMPENABLE_SHIFT (23U) +/*! INDUCTORCLAMPENABLE - Enable shorting of Inductor during PFM idle time. + */ +#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_INDUCTORCLAMPENABLE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_INDUCTORCLAMPENABLE_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_INDUCTORCLAMPENABLE_MASK) + +#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_VOUT_PWD_MASK (0xF000000U) +#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_VOUT_PWD_SHIFT (24U) +/*! VOUT_PWD - Set output regulation voltage during Deep Sleep. + */ +#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_VOUT_PWD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_VOUT_PWD_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_VOUT_PWD_MASK) +/*! @} */ + +/*! @name DCDC_POWER_PROFILE_HIGH_1 - */ +/*! @{ */ + +#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_RTRIMOFFET_MASK (0xFU) +#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_RTRIMOFFET_SHIFT (0U) +/*! RTRIMOFFET - Adjust the offset voltage of BJT based comparator. + */ +#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_RTRIMOFFET(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_RTRIMOFFET_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_RTRIMOFFET_MASK) + +#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_RSENSETRIM_MASK (0xF0U) +#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_RSENSETRIM_SHIFT (4U) +/*! RSENSETRIM - Adjust Max inductor peak current limiting. + */ +#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_RSENSETRIM(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_RSENSETRIM_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_RSENSETRIM_MASK) + +#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_DTESTENABLE_MASK (0x100U) +#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_DTESTENABLE_SHIFT (8U) +/*! DTESTENABLE - Enable Digital test signals. + */ +#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_DTESTENABLE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_DTESTENABLE_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_DTESTENABLE_MASK) + +#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_SETCURVE_MASK (0x600U) +#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_SETCURVE_SHIFT (9U) +/*! SETCURVE - Bandgap calibration parameter. + */ +#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_SETCURVE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_SETCURVE_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_SETCURVE_MASK) + +#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_SETDC_MASK (0x7800U) +#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_SETDC_SHIFT (11U) +/*! SETDC - Bandgap calibration parameter. + */ +#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_SETDC(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_SETDC_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_SETDC_MASK) + +#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_DTESTSEL_MASK (0x38000U) +#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_DTESTSEL_SHIFT (15U) +/*! DTESTSEL - Select the output signal for test. + */ +#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_DTESTSEL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_DTESTSEL_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_DTESTSEL_MASK) + +#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_ISCALEENABLE_MASK (0x40000U) +#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_ISCALEENABLE_SHIFT (18U) +/*! ISCALEENABLE - Modify COT behavior. + */ +#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_ISCALEENABLE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_ISCALEENABLE_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_ISCALEENABLE_MASK) + +#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_FORCEBYPASS_MASK (0x80000U) +#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_FORCEBYPASS_SHIFT (19U) +/*! FORCEBYPASS - Force bypass mode. + */ +#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_FORCEBYPASS(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_FORCEBYPASS_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_FORCEBYPASS_MASK) + +#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_TRIMAUTOCOT_MASK (0xF00000U) +#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_TRIMAUTOCOT_SHIFT (20U) +/*! TRIMAUTOCOT - Change the scaling ratio of the feedforward compensation. + */ +#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_TRIMAUTOCOT(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_TRIMAUTOCOT_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_TRIMAUTOCOT_MASK) + +#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_FORCEFULLCYCLE_MASK (0x1000000U) +#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_FORCEFULLCYCLE_SHIFT (24U) +/*! FORCEFULLCYCLE - Force full PFM PMOS and NMOS cycle. + */ +#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_FORCEFULLCYCLE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_FORCEFULLCYCLE_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_FORCEFULLCYCLE_MASK) + +#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_LCENABLE_MASK (0x2000000U) +#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_LCENABLE_SHIFT (25U) +/*! LCENABLE - Change the range of the peak detector of current inside the inductor. + */ +#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_LCENABLE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_LCENABLE_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_LCENABLE_MASK) + +#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_TOFF_MASK (0x7C000000U) +#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_TOFF_SHIFT (26U) +/*! TOFF - Constant Off-Time calibration input. + */ +#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_TOFF(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_TOFF_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_TOFF_MASK) + +#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_TOFFENABLE_MASK (0x80000000U) +#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_TOFFENABLE_SHIFT (31U) +/*! TOFFENABLE - Enable Constant Off-Time feature. + */ +#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_TOFFENABLE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_TOFFENABLE_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_TOFFENABLE_MASK) +/*! @} */ + +/*! @name DCDC_POWER_PROFILE_HIGH_ARRAY - */ +/*! @{ */ + +#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_ARRAY_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_ARRAY_FIELD_SHIFT (0U) +#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_ARRAY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_ARRAY_FIELD_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_ARRAY_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_ARRAY */ +#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_ARRAY_COUNT (2U) + +/*! @name DCDC_POWER_PROFILE_LOW_0 - */ +/*! @{ */ + +#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_DCDC_TRIM_VALID_MASK (0x1U) +#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_DCDC_TRIM_VALID_SHIFT (0U) +/*! DCDC_TRIM_VALID - DCDC is trimed. + */ +#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_DCDC_TRIM_VALID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_DCDC_TRIM_VALID_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_DCDC_TRIM_VALID_MASK) + +#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_RC_MASK (0x7EU) +#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_RC_SHIFT (1U) +/*! RC - Constant On-Time calibration. + */ +#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_RC(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_RC_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_RC_MASK) + +#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_ICOMP_MASK (0x180U) +#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_ICOMP_SHIFT (7U) +/*! ICOMP - Select the type of ZCD comparator. + */ +#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_ICOMP(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_ICOMP_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_ICOMP_MASK) + +#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_ISEL_MASK (0x600U) +#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_ISEL_SHIFT (9U) +/*! ISEL - Alter Internal biasing currents. + */ +#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_ISEL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_ISEL_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_ISEL_MASK) + +#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_ICENABLE_MASK (0x800U) +#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_ICENABLE_SHIFT (11U) +/*! ICENABLE - Selection of auto scaling of COT period with variations in VDD. + */ +#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_ICENABLE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_ICENABLE_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_ICENABLE_MASK) + +#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_TMOS_MASK (0x1F000U) +#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_TMOS_SHIFT (12U) +/*! TMOS - One-shot generator reference current trimming signal. + */ +#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_TMOS(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_TMOS_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_TMOS_MASK) + +#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_DISABLEISENSE_MASK (0x20000U) +#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_DISABLEISENSE_SHIFT (17U) +/*! DISABLEISENSE - Disable Current sensing. + */ +#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_DISABLEISENSE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_DISABLEISENSE_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_DISABLEISENSE_MASK) + +#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_VOUT_MASK (0x3C0000U) +#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_VOUT_SHIFT (18U) +/*! VOUT - Set output regulation voltage. + */ +#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_VOUT(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_VOUT_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_VOUT_MASK) + +#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_SLICINGENABLE_MASK (0x400000U) +#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_SLICINGENABLE_SHIFT (22U) +/*! SLICINGENABLE - Enable staggered switching of power switches. + */ +#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_SLICINGENABLE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_SLICINGENABLE_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_SLICINGENABLE_MASK) + +#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_INDUCTORCLAMPENABLE_MASK (0x800000U) +#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_INDUCTORCLAMPENABLE_SHIFT (23U) +/*! INDUCTORCLAMPENABLE - Enable shorting of Inductor during PFM idle time. + */ +#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_INDUCTORCLAMPENABLE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_INDUCTORCLAMPENABLE_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_INDUCTORCLAMPENABLE_MASK) + +#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_VOUT_PWD_MASK (0xF000000U) +#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_VOUT_PWD_SHIFT (24U) +/*! VOUT_PWD - Set output regulation voltage during Deep Sleep. + */ +#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_VOUT_PWD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_VOUT_PWD_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_VOUT_PWD_MASK) +/*! @} */ + +/*! @name DCDC_POWER_PROFILE_LOW_1 - */ +/*! @{ */ + +#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_RTRIMOFFET_MASK (0xFU) +#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_RTRIMOFFET_SHIFT (0U) +/*! RTRIMOFFET - Adjust the offset voltage of BJT based comparator. + */ +#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_RTRIMOFFET(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_RTRIMOFFET_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_RTRIMOFFET_MASK) + +#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_RSENSETRIM_MASK (0xF0U) +#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_RSENSETRIM_SHIFT (4U) +/*! RSENSETRIM - Adjust Max inductor peak current limiting. + */ +#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_RSENSETRIM(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_RSENSETRIM_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_RSENSETRIM_MASK) + +#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_DTESTENABLE_MASK (0x100U) +#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_DTESTENABLE_SHIFT (8U) +/*! DTESTENABLE - Enable Digital test signals. + */ +#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_DTESTENABLE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_DTESTENABLE_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_DTESTENABLE_MASK) + +#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_SETCURVE_MASK (0x600U) +#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_SETCURVE_SHIFT (9U) +/*! SETCURVE - Bandgap calibration parameter. + */ +#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_SETCURVE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_SETCURVE_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_SETCURVE_MASK) + +#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_SETDC_MASK (0x7800U) +#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_SETDC_SHIFT (11U) +/*! SETDC - Bandgap calibration parameter. + */ +#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_SETDC(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_SETDC_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_SETDC_MASK) + +#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_DTESTSEL_MASK (0x38000U) +#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_DTESTSEL_SHIFT (15U) +/*! DTESTSEL - Select the output signal for test. + */ +#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_DTESTSEL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_DTESTSEL_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_DTESTSEL_MASK) + +#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_ISCALEENABLE_MASK (0x40000U) +#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_ISCALEENABLE_SHIFT (18U) +/*! ISCALEENABLE - Modify COT behavior. + */ +#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_ISCALEENABLE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_ISCALEENABLE_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_ISCALEENABLE_MASK) + +#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_FORCEBYPASS_MASK (0x80000U) +#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_FORCEBYPASS_SHIFT (19U) +/*! FORCEBYPASS - Force bypass mode. + */ +#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_FORCEBYPASS(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_FORCEBYPASS_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_FORCEBYPASS_MASK) + +#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_TRIMAUTOCOT_MASK (0xF00000U) +#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_TRIMAUTOCOT_SHIFT (20U) +/*! TRIMAUTOCOT - Change the scaling ratio of the feedforward compensation. + */ +#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_TRIMAUTOCOT(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_TRIMAUTOCOT_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_TRIMAUTOCOT_MASK) + +#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_FORCEFULLCYCLE_MASK (0x1000000U) +#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_FORCEFULLCYCLE_SHIFT (24U) +/*! FORCEFULLCYCLE - Force full PFM PMOS and NMOS cycle. + */ +#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_FORCEFULLCYCLE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_FORCEFULLCYCLE_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_FORCEFULLCYCLE_MASK) + +#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_LCENABLE_MASK (0x2000000U) +#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_LCENABLE_SHIFT (25U) +/*! LCENABLE - Change the range of the peak detector of current inside the inductor. + */ +#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_LCENABLE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_LCENABLE_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_LCENABLE_MASK) + +#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_TOFF_MASK (0x7C000000U) +#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_TOFF_SHIFT (26U) +/*! TOFF - Constant Off-Time calibration input. + */ +#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_TOFF(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_TOFF_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_TOFF_MASK) + +#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_TOFFENABLE_MASK (0x80000000U) +#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_TOFFENABLE_SHIFT (31U) +/*! TOFFENABLE - Enable Constant Off-Time feature. + */ +#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_TOFFENABLE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_TOFFENABLE_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_TOFFENABLE_MASK) +/*! @} */ + +/*! @name DCDC_POWER_PROFILE_LOW_ARRAY - */ +/*! @{ */ + +#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_ARRAY_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_ARRAY_FIELD_SHIFT (0U) +#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_ARRAY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_LOW_ARRAY_FIELD_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_LOW_ARRAY_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_NMPA_DCDC_POWER_PROFILE_LOW_ARRAY */ +#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_ARRAY_COUNT (2U) + +/*! @name DCDC_POWER_PROFILE_MEDIUM_0 - */ +/*! @{ */ + +#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_DCDC_TRIM_VALID_MASK (0x1U) +#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_DCDC_TRIM_VALID_SHIFT (0U) +/*! DCDC_TRIM_VALID - DCDC is trimed. + */ +#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_DCDC_TRIM_VALID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_DCDC_TRIM_VALID_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_DCDC_TRIM_VALID_MASK) + +#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_RC_MASK (0x7EU) +#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_RC_SHIFT (1U) +/*! RC - Constant On-Time calibration. + */ +#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_RC(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_RC_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_RC_MASK) + +#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_ICOMP_MASK (0x180U) +#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_ICOMP_SHIFT (7U) +/*! ICOMP - Select the type of ZCD comparator. + */ +#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_ICOMP(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_ICOMP_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_ICOMP_MASK) + +#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_ISEL_MASK (0x600U) +#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_ISEL_SHIFT (9U) +/*! ISEL - Alter Internal biasing currents. + */ +#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_ISEL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_ISEL_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_ISEL_MASK) + +#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_ICENABLE_MASK (0x800U) +#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_ICENABLE_SHIFT (11U) +/*! ICENABLE - Selection of auto scaling of COT period with variations in VDD. + */ +#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_ICENABLE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_ICENABLE_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_ICENABLE_MASK) + +#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_TMOS_MASK (0x1F000U) +#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_TMOS_SHIFT (12U) +/*! TMOS - One-shot generator reference current trimming signal. + */ +#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_TMOS(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_TMOS_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_TMOS_MASK) + +#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_DISABLEISENSE_MASK (0x20000U) +#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_DISABLEISENSE_SHIFT (17U) +/*! DISABLEISENSE - Disable Current sensing. + */ +#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_DISABLEISENSE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_DISABLEISENSE_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_DISABLEISENSE_MASK) + +#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_VOUT_MASK (0x3C0000U) +#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_VOUT_SHIFT (18U) +/*! VOUT - Set output regulation voltage. + */ +#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_VOUT(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_VOUT_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_VOUT_MASK) + +#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_SLICINGENABLE_MASK (0x400000U) +#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_SLICINGENABLE_SHIFT (22U) +/*! SLICINGENABLE - Enable staggered switching of power switches. + */ +#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_SLICINGENABLE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_SLICINGENABLE_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_SLICINGENABLE_MASK) + +#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_INDUCTORCLAMPENABLE_MASK (0x800000U) +#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_INDUCTORCLAMPENABLE_SHIFT (23U) +/*! INDUCTORCLAMPENABLE - Enable shorting of Inductor during PFM idle time. + */ +#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_INDUCTORCLAMPENABLE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_INDUCTORCLAMPENABLE_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_INDUCTORCLAMPENABLE_MASK) + +#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_VOUT_PWD_MASK (0xF000000U) +#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_VOUT_PWD_SHIFT (24U) +/*! VOUT_PWD - Set output regulation voltage during Deep Sleep. + */ +#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_VOUT_PWD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_VOUT_PWD_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_VOUT_PWD_MASK) +/*! @} */ + +/*! @name DCDC_POWER_PROFILE_MEDIUM_1 - */ +/*! @{ */ + +#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_RTRIMOFFET_MASK (0xFU) +#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_RTRIMOFFET_SHIFT (0U) +/*! RTRIMOFFET - Adjust the offset voltage of BJT based comparator. + */ +#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_RTRIMOFFET(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_RTRIMOFFET_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_RTRIMOFFET_MASK) + +#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_RSENSETRIM_MASK (0xF0U) +#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_RSENSETRIM_SHIFT (4U) +/*! RSENSETRIM - Adjust Max inductor peak current limiting. + */ +#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_RSENSETRIM(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_RSENSETRIM_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_RSENSETRIM_MASK) + +#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_DTESTENABLE_MASK (0x100U) +#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_DTESTENABLE_SHIFT (8U) +/*! DTESTENABLE - Enable Digital test signals. + */ +#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_DTESTENABLE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_DTESTENABLE_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_DTESTENABLE_MASK) + +#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_SETCURVE_MASK (0x600U) +#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_SETCURVE_SHIFT (9U) +/*! SETCURVE - Bandgap calibration parameter. + */ +#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_SETCURVE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_SETCURVE_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_SETCURVE_MASK) + +#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_SETDC_MASK (0x7800U) +#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_SETDC_SHIFT (11U) +/*! SETDC - Bandgap calibration parameter. + */ +#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_SETDC(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_SETDC_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_SETDC_MASK) + +#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_DTESTSEL_MASK (0x38000U) +#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_DTESTSEL_SHIFT (15U) +/*! DTESTSEL - Select the output signal for test. + */ +#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_DTESTSEL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_DTESTSEL_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_DTESTSEL_MASK) + +#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_ISCALEENABLE_MASK (0x40000U) +#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_ISCALEENABLE_SHIFT (18U) +/*! ISCALEENABLE - Modify COT behavior. + */ +#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_ISCALEENABLE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_ISCALEENABLE_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_ISCALEENABLE_MASK) + +#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_FORCEBYPASS_MASK (0x80000U) +#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_FORCEBYPASS_SHIFT (19U) +/*! FORCEBYPASS - Force bypass mode. + */ +#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_FORCEBYPASS(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_FORCEBYPASS_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_FORCEBYPASS_MASK) + +#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_TRIMAUTOCOT_MASK (0xF00000U) +#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_TRIMAUTOCOT_SHIFT (20U) +/*! TRIMAUTOCOT - Change the scaling ratio of the feedforward compensation. + */ +#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_TRIMAUTOCOT(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_TRIMAUTOCOT_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_TRIMAUTOCOT_MASK) + +#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_FORCEFULLCYCLE_MASK (0x1000000U) +#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_FORCEFULLCYCLE_SHIFT (24U) +/*! FORCEFULLCYCLE - Force full PFM PMOS and NMOS cycle. + */ +#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_FORCEFULLCYCLE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_FORCEFULLCYCLE_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_FORCEFULLCYCLE_MASK) + +#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_LCENABLE_MASK (0x2000000U) +#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_LCENABLE_SHIFT (25U) +/*! LCENABLE - Change the range of the peak detector of current inside the inductor. + */ +#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_LCENABLE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_LCENABLE_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_LCENABLE_MASK) + +#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_TOFF_MASK (0x7C000000U) +#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_TOFF_SHIFT (26U) +/*! TOFF - Constant Off-Time calibration input. + */ +#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_TOFF(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_TOFF_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_TOFF_MASK) + +#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_TOFFENABLE_MASK (0x80000000U) +#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_TOFFENABLE_SHIFT (31U) +/*! TOFFENABLE - Enable Constant Off-Time feature. + */ +#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_TOFFENABLE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_TOFFENABLE_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_TOFFENABLE_MASK) +/*! @} */ + +/*! @name DCDC_POWER_PROFILE_MEDIUM_ARRAY - */ +/*! @{ */ + +#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_ARRAY_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_ARRAY_FIELD_SHIFT (0U) +#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_ARRAY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_ARRAY_FIELD_SHIFT)) & FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_ARRAY_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_ARRAY */ +#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_ARRAY_COUNT (2U) + +/*! @name BOD - */ +/*! @{ */ + +#define FLASH_NMPA_BOD_BOD_VBAT_TRIM_VALID_MASK (0x1U) +#define FLASH_NMPA_BOD_BOD_VBAT_TRIM_VALID_SHIFT (0U) +#define FLASH_NMPA_BOD_BOD_VBAT_TRIM_VALID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_BOD_BOD_VBAT_TRIM_VALID_SHIFT)) & FLASH_NMPA_BOD_BOD_VBAT_TRIM_VALID_MASK) + +#define FLASH_NMPA_BOD_BOD_VBAT_TRIGLVL_MASK (0x3EU) +#define FLASH_NMPA_BOD_BOD_VBAT_TRIGLVL_SHIFT (1U) +#define FLASH_NMPA_BOD_BOD_VBAT_TRIGLVL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_BOD_BOD_VBAT_TRIGLVL_SHIFT)) & FLASH_NMPA_BOD_BOD_VBAT_TRIGLVL_MASK) + +#define FLASH_NMPA_BOD_BOD_VBAT_HYST_MASK (0xC0U) +#define FLASH_NMPA_BOD_BOD_VBAT_HYST_SHIFT (6U) +#define FLASH_NMPA_BOD_BOD_VBAT_HYST(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_BOD_BOD_VBAT_HYST_SHIFT)) & FLASH_NMPA_BOD_BOD_VBAT_HYST_MASK) + +#define FLASH_NMPA_BOD_BOD_CORE_TRIM_VALID_MASK (0x10000U) +#define FLASH_NMPA_BOD_BOD_CORE_TRIM_VALID_SHIFT (16U) +#define FLASH_NMPA_BOD_BOD_CORE_TRIM_VALID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_BOD_BOD_CORE_TRIM_VALID_SHIFT)) & FLASH_NMPA_BOD_BOD_CORE_TRIM_VALID_MASK) + +#define FLASH_NMPA_BOD_BOD_CORE_TRIGLVL_MASK (0xE0000U) +#define FLASH_NMPA_BOD_BOD_CORE_TRIGLVL_SHIFT (17U) +#define FLASH_NMPA_BOD_BOD_CORE_TRIGLVL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_BOD_BOD_CORE_TRIGLVL_SHIFT)) & FLASH_NMPA_BOD_BOD_CORE_TRIGLVL_MASK) + +#define FLASH_NMPA_BOD_BOD_CORE_HYST_MASK (0x600000U) +#define FLASH_NMPA_BOD_BOD_CORE_HYST_SHIFT (21U) +#define FLASH_NMPA_BOD_BOD_CORE_HYST(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_BOD_BOD_CORE_HYST_SHIFT)) & FLASH_NMPA_BOD_BOD_CORE_HYST_MASK) +/*! @} */ + +/*! @name LDO_AO - */ +/*! @{ */ + +#define FLASH_NMPA_LDO_AO_ACTIVE_TRIM_VALID_MASK (0x1U) +#define FLASH_NMPA_LDO_AO_ACTIVE_TRIM_VALID_SHIFT (0U) +#define FLASH_NMPA_LDO_AO_ACTIVE_TRIM_VALID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_LDO_AO_ACTIVE_TRIM_VALID_SHIFT)) & FLASH_NMPA_LDO_AO_ACTIVE_TRIM_VALID_MASK) + +#define FLASH_NMPA_LDO_AO_ACTIVE_TRIM_MASK (0x3EU) +#define FLASH_NMPA_LDO_AO_ACTIVE_TRIM_SHIFT (1U) +#define FLASH_NMPA_LDO_AO_ACTIVE_TRIM(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_LDO_AO_ACTIVE_TRIM_SHIFT)) & FLASH_NMPA_LDO_AO_ACTIVE_TRIM_MASK) + +#define FLASH_NMPA_LDO_AO_DSLP_TRIM_VALID_MASK (0x100U) +#define FLASH_NMPA_LDO_AO_DSLP_TRIM_VALID_SHIFT (8U) +#define FLASH_NMPA_LDO_AO_DSLP_TRIM_VALID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_LDO_AO_DSLP_TRIM_VALID_SHIFT)) & FLASH_NMPA_LDO_AO_DSLP_TRIM_VALID_MASK) + +#define FLASH_NMPA_LDO_AO_DSLP_TRIM_MASK (0x3E00U) +#define FLASH_NMPA_LDO_AO_DSLP_TRIM_SHIFT (9U) +#define FLASH_NMPA_LDO_AO_DSLP_TRIM(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_LDO_AO_DSLP_TRIM_SHIFT)) & FLASH_NMPA_LDO_AO_DSLP_TRIM_MASK) + +#define FLASH_NMPA_LDO_AO_PDWN_TRIM_VALID_MASK (0x10000U) +#define FLASH_NMPA_LDO_AO_PDWN_TRIM_VALID_SHIFT (16U) +#define FLASH_NMPA_LDO_AO_PDWN_TRIM_VALID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_LDO_AO_PDWN_TRIM_VALID_SHIFT)) & FLASH_NMPA_LDO_AO_PDWN_TRIM_VALID_MASK) + +#define FLASH_NMPA_LDO_AO_PDWN_TRIM_MASK (0x3E0000U) +#define FLASH_NMPA_LDO_AO_PDWN_TRIM_SHIFT (17U) +#define FLASH_NMPA_LDO_AO_PDWN_TRIM(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_LDO_AO_PDWN_TRIM_SHIFT)) & FLASH_NMPA_LDO_AO_PDWN_TRIM_MASK) + +#define FLASH_NMPA_LDO_AO_DPDW_TRIM_VALID_MASK (0x1000000U) +#define FLASH_NMPA_LDO_AO_DPDW_TRIM_VALID_SHIFT (24U) +#define FLASH_NMPA_LDO_AO_DPDW_TRIM_VALID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_LDO_AO_DPDW_TRIM_VALID_SHIFT)) & FLASH_NMPA_LDO_AO_DPDW_TRIM_VALID_MASK) + +#define FLASH_NMPA_LDO_AO_DPDW_TRIM_MASK (0x3E000000U) +#define FLASH_NMPA_LDO_AO_DPDW_TRIM_SHIFT (25U) +#define FLASH_NMPA_LDO_AO_DPDW_TRIM(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_LDO_AO_DPDW_TRIM_SHIFT)) & FLASH_NMPA_LDO_AO_DPDW_TRIM_MASK) +/*! @} */ + +/*! @name SDIO_DELAY - */ +/*! @{ */ + +#define FLASH_NMPA_SDIO_DELAY_SDIO_0_VALID_MASK (0x1U) +#define FLASH_NMPA_SDIO_DELAY_SDIO_0_VALID_SHIFT (0U) +#define FLASH_NMPA_SDIO_DELAY_SDIO_0_VALID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_SDIO_DELAY_SDIO_0_VALID_SHIFT)) & FLASH_NMPA_SDIO_DELAY_SDIO_0_VALID_MASK) + +#define FLASH_NMPA_SDIO_DELAY_SDIO_0_DELAY_MASK (0x7FEU) +#define FLASH_NMPA_SDIO_DELAY_SDIO_0_DELAY_SHIFT (1U) +/*! SDIO_0_DELAY - SDIO_0_DELAY (unit: 100 ps). + */ +#define FLASH_NMPA_SDIO_DELAY_SDIO_0_DELAY(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_SDIO_DELAY_SDIO_0_DELAY_SHIFT)) & FLASH_NMPA_SDIO_DELAY_SDIO_0_DELAY_MASK) +/*! @} */ + +/*! @name AUX_BIAS_CURVE_AMBIENT_0 - */ +/*! @{ */ + +#define FLASH_NMPA_AUX_BIAS_CURVE_AMBIENT_0_VREF1VCURVETRIM_0_MASK (0xFFFFU) +#define FLASH_NMPA_AUX_BIAS_CURVE_AMBIENT_0_VREF1VCURVETRIM_0_SHIFT (0U) +/*! VREF1VCURVETRIM_0 - VREF1VCURVETRIM_0 (unit: 100uV) + */ +#define FLASH_NMPA_AUX_BIAS_CURVE_AMBIENT_0_VREF1VCURVETRIM_0(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_AUX_BIAS_CURVE_AMBIENT_0_VREF1VCURVETRIM_0_SHIFT)) & FLASH_NMPA_AUX_BIAS_CURVE_AMBIENT_0_VREF1VCURVETRIM_0_MASK) + +#define FLASH_NMPA_AUX_BIAS_CURVE_AMBIENT_0_VREF1VCURVETRIM_1_MASK (0xFFFF0000U) +#define FLASH_NMPA_AUX_BIAS_CURVE_AMBIENT_0_VREF1VCURVETRIM_1_SHIFT (16U) +/*! VREF1VCURVETRIM_1 - VREF1VCURVETRIM_1 (unit: 100uV) + */ +#define FLASH_NMPA_AUX_BIAS_CURVE_AMBIENT_0_VREF1VCURVETRIM_1(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_AUX_BIAS_CURVE_AMBIENT_0_VREF1VCURVETRIM_1_SHIFT)) & FLASH_NMPA_AUX_BIAS_CURVE_AMBIENT_0_VREF1VCURVETRIM_1_MASK) +/*! @} */ + +/*! @name AUX_BIAS_CURVE_AMBIENT_1 - */ +/*! @{ */ + +#define FLASH_NMPA_AUX_BIAS_CURVE_AMBIENT_1_VREF1VCURVETRIM_2_MASK (0xFFFFU) +#define FLASH_NMPA_AUX_BIAS_CURVE_AMBIENT_1_VREF1VCURVETRIM_2_SHIFT (0U) +/*! VREF1VCURVETRIM_2 - VREF1VCURVETRIM_2 (unit: 100uV) + */ +#define FLASH_NMPA_AUX_BIAS_CURVE_AMBIENT_1_VREF1VCURVETRIM_2(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_AUX_BIAS_CURVE_AMBIENT_1_VREF1VCURVETRIM_2_SHIFT)) & FLASH_NMPA_AUX_BIAS_CURVE_AMBIENT_1_VREF1VCURVETRIM_2_MASK) + +#define FLASH_NMPA_AUX_BIAS_CURVE_AMBIENT_1_VREF1VCURVETRIM_3_MASK (0xFFFF0000U) +#define FLASH_NMPA_AUX_BIAS_CURVE_AMBIENT_1_VREF1VCURVETRIM_3_SHIFT (16U) +/*! VREF1VCURVETRIM_3 - VREF1VCURVETRIM_3 (unit: 100uV) + */ +#define FLASH_NMPA_AUX_BIAS_CURVE_AMBIENT_1_VREF1VCURVETRIM_3(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_AUX_BIAS_CURVE_AMBIENT_1_VREF1VCURVETRIM_3_SHIFT)) & FLASH_NMPA_AUX_BIAS_CURVE_AMBIENT_1_VREF1VCURVETRIM_3_MASK) +/*! @} */ + +/*! @name AUX_BIAS_CURVE_AMBIENT_2 - */ +/*! @{ */ + +#define FLASH_NMPA_AUX_BIAS_CURVE_AMBIENT_2_VREF1VCURVETRIM_4_MASK (0xFFFFU) +#define FLASH_NMPA_AUX_BIAS_CURVE_AMBIENT_2_VREF1VCURVETRIM_4_SHIFT (0U) +/*! VREF1VCURVETRIM_4 - VREF1VCURVETRIM_4 (unit: 100uV) + */ +#define FLASH_NMPA_AUX_BIAS_CURVE_AMBIENT_2_VREF1VCURVETRIM_4(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_AUX_BIAS_CURVE_AMBIENT_2_VREF1VCURVETRIM_4_SHIFT)) & FLASH_NMPA_AUX_BIAS_CURVE_AMBIENT_2_VREF1VCURVETRIM_4_MASK) + +#define FLASH_NMPA_AUX_BIAS_CURVE_AMBIENT_2_VREF1VCURVETRIM_5_MASK (0xFFFF0000U) +#define FLASH_NMPA_AUX_BIAS_CURVE_AMBIENT_2_VREF1VCURVETRIM_5_SHIFT (16U) +/*! VREF1VCURVETRIM_5 - VREF1VCURVETRIM_5 (unit: 100uV) + */ +#define FLASH_NMPA_AUX_BIAS_CURVE_AMBIENT_2_VREF1VCURVETRIM_5(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_AUX_BIAS_CURVE_AMBIENT_2_VREF1VCURVETRIM_5_SHIFT)) & FLASH_NMPA_AUX_BIAS_CURVE_AMBIENT_2_VREF1VCURVETRIM_5_MASK) +/*! @} */ + +/*! @name AUX_BIAS_CURVE_AMBIENT_3 - */ +/*! @{ */ + +#define FLASH_NMPA_AUX_BIAS_CURVE_AMBIENT_3_VREF1VCURVETRIM_6_MASK (0xFFFFU) +#define FLASH_NMPA_AUX_BIAS_CURVE_AMBIENT_3_VREF1VCURVETRIM_6_SHIFT (0U) +/*! VREF1VCURVETRIM_6 - VREF1VCURVETRIM_6 (unit: 100uV) + */ +#define FLASH_NMPA_AUX_BIAS_CURVE_AMBIENT_3_VREF1VCURVETRIM_6(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_AUX_BIAS_CURVE_AMBIENT_3_VREF1VCURVETRIM_6_SHIFT)) & FLASH_NMPA_AUX_BIAS_CURVE_AMBIENT_3_VREF1VCURVETRIM_6_MASK) + +#define FLASH_NMPA_AUX_BIAS_CURVE_AMBIENT_3_VREF1VCURVETRIM_7_MASK (0xFFFF0000U) +#define FLASH_NMPA_AUX_BIAS_CURVE_AMBIENT_3_VREF1VCURVETRIM_7_SHIFT (16U) +/*! VREF1VCURVETRIM_7 - VREF1VCURVETRIM_7 (unit: 100uV) + */ +#define FLASH_NMPA_AUX_BIAS_CURVE_AMBIENT_3_VREF1VCURVETRIM_7(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_AUX_BIAS_CURVE_AMBIENT_3_VREF1VCURVETRIM_7_SHIFT)) & FLASH_NMPA_AUX_BIAS_CURVE_AMBIENT_3_VREF1VCURVETRIM_7_MASK) +/*! @} */ + +/*! @name AUX_BIAS_CURVE_AMBIENT_ARRAY - Aux Bias Curve Ambient (30degC) */ +/*! @{ */ + +#define FLASH_NMPA_AUX_BIAS_CURVE_AMBIENT_ARRAY_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_NMPA_AUX_BIAS_CURVE_AMBIENT_ARRAY_FIELD_SHIFT (0U) +#define FLASH_NMPA_AUX_BIAS_CURVE_AMBIENT_ARRAY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_AUX_BIAS_CURVE_AMBIENT_ARRAY_FIELD_SHIFT)) & FLASH_NMPA_AUX_BIAS_CURVE_AMBIENT_ARRAY_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_NMPA_AUX_BIAS_CURVE_AMBIENT_ARRAY */ +#define FLASH_NMPA_AUX_BIAS_CURVE_AMBIENT_ARRAY_COUNT (4U) + +/*! @name AUX_BIAS_CURVE_TEMP_0 - */ +/*! @{ */ + +#define FLASH_NMPA_AUX_BIAS_CURVE_TEMP_0_VREF1VCURVETRIM_0_MASK (0xFFFFU) +#define FLASH_NMPA_AUX_BIAS_CURVE_TEMP_0_VREF1VCURVETRIM_0_SHIFT (0U) +/*! VREF1VCURVETRIM_0 - VREF1VCURVETRIM_0 (unit: 100uV) + */ +#define FLASH_NMPA_AUX_BIAS_CURVE_TEMP_0_VREF1VCURVETRIM_0(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_AUX_BIAS_CURVE_TEMP_0_VREF1VCURVETRIM_0_SHIFT)) & FLASH_NMPA_AUX_BIAS_CURVE_TEMP_0_VREF1VCURVETRIM_0_MASK) + +#define FLASH_NMPA_AUX_BIAS_CURVE_TEMP_0_VREF1VCURVETRIM_1_MASK (0xFFFF0000U) +#define FLASH_NMPA_AUX_BIAS_CURVE_TEMP_0_VREF1VCURVETRIM_1_SHIFT (16U) +/*! VREF1VCURVETRIM_1 - VREF1VCURVETRIM_1 (unit: 100uV) + */ +#define FLASH_NMPA_AUX_BIAS_CURVE_TEMP_0_VREF1VCURVETRIM_1(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_AUX_BIAS_CURVE_TEMP_0_VREF1VCURVETRIM_1_SHIFT)) & FLASH_NMPA_AUX_BIAS_CURVE_TEMP_0_VREF1VCURVETRIM_1_MASK) +/*! @} */ + +/*! @name AUX_BIAS_CURVE_TEMP_1 - */ +/*! @{ */ + +#define FLASH_NMPA_AUX_BIAS_CURVE_TEMP_1_VREF1VCURVETRIM_2_MASK (0xFFFFU) +#define FLASH_NMPA_AUX_BIAS_CURVE_TEMP_1_VREF1VCURVETRIM_2_SHIFT (0U) +/*! VREF1VCURVETRIM_2 - VREF1VCURVETRIM_2 (unit: 100uV) + */ +#define FLASH_NMPA_AUX_BIAS_CURVE_TEMP_1_VREF1VCURVETRIM_2(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_AUX_BIAS_CURVE_TEMP_1_VREF1VCURVETRIM_2_SHIFT)) & FLASH_NMPA_AUX_BIAS_CURVE_TEMP_1_VREF1VCURVETRIM_2_MASK) + +#define FLASH_NMPA_AUX_BIAS_CURVE_TEMP_1_VREF1VCURVETRIM_3_MASK (0xFFFF0000U) +#define FLASH_NMPA_AUX_BIAS_CURVE_TEMP_1_VREF1VCURVETRIM_3_SHIFT (16U) +/*! VREF1VCURVETRIM_3 - VREF1VCURVETRIM_3 (unit: 100uV) + */ +#define FLASH_NMPA_AUX_BIAS_CURVE_TEMP_1_VREF1VCURVETRIM_3(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_AUX_BIAS_CURVE_TEMP_1_VREF1VCURVETRIM_3_SHIFT)) & FLASH_NMPA_AUX_BIAS_CURVE_TEMP_1_VREF1VCURVETRIM_3_MASK) +/*! @} */ + +/*! @name AUX_BIAS_CURVE_TEMP_2 - */ +/*! @{ */ + +#define FLASH_NMPA_AUX_BIAS_CURVE_TEMP_2_VREF1VCURVETRIM_4_MASK (0xFFFFU) +#define FLASH_NMPA_AUX_BIAS_CURVE_TEMP_2_VREF1VCURVETRIM_4_SHIFT (0U) +/*! VREF1VCURVETRIM_4 - VREF1VCURVETRIM_4 (unit: 100uV) + */ +#define FLASH_NMPA_AUX_BIAS_CURVE_TEMP_2_VREF1VCURVETRIM_4(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_AUX_BIAS_CURVE_TEMP_2_VREF1VCURVETRIM_4_SHIFT)) & FLASH_NMPA_AUX_BIAS_CURVE_TEMP_2_VREF1VCURVETRIM_4_MASK) + +#define FLASH_NMPA_AUX_BIAS_CURVE_TEMP_2_VREF1VCURVETRIM_5_MASK (0xFFFF0000U) +#define FLASH_NMPA_AUX_BIAS_CURVE_TEMP_2_VREF1VCURVETRIM_5_SHIFT (16U) +/*! VREF1VCURVETRIM_5 - VREF1VCURVETRIM_5 (unit: 100uV) + */ +#define FLASH_NMPA_AUX_BIAS_CURVE_TEMP_2_VREF1VCURVETRIM_5(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_AUX_BIAS_CURVE_TEMP_2_VREF1VCURVETRIM_5_SHIFT)) & FLASH_NMPA_AUX_BIAS_CURVE_TEMP_2_VREF1VCURVETRIM_5_MASK) +/*! @} */ + +/*! @name AUX_BIAS_CURVE_TEMP_3 - */ +/*! @{ */ + +#define FLASH_NMPA_AUX_BIAS_CURVE_TEMP_3_VREF1VCURVETRIM_6_MASK (0xFFFFU) +#define FLASH_NMPA_AUX_BIAS_CURVE_TEMP_3_VREF1VCURVETRIM_6_SHIFT (0U) +/*! VREF1VCURVETRIM_6 - VREF1VCURVETRIM_6 (unit: 100uV) + */ +#define FLASH_NMPA_AUX_BIAS_CURVE_TEMP_3_VREF1VCURVETRIM_6(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_AUX_BIAS_CURVE_TEMP_3_VREF1VCURVETRIM_6_SHIFT)) & FLASH_NMPA_AUX_BIAS_CURVE_TEMP_3_VREF1VCURVETRIM_6_MASK) + +#define FLASH_NMPA_AUX_BIAS_CURVE_TEMP_3_VREF1VCURVETRIM_7_MASK (0xFFFF0000U) +#define FLASH_NMPA_AUX_BIAS_CURVE_TEMP_3_VREF1VCURVETRIM_7_SHIFT (16U) +/*! VREF1VCURVETRIM_7 - VREF1VCURVETRIM_7 (unit: 100uV) + */ +#define FLASH_NMPA_AUX_BIAS_CURVE_TEMP_3_VREF1VCURVETRIM_7(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_AUX_BIAS_CURVE_TEMP_3_VREF1VCURVETRIM_7_SHIFT)) & FLASH_NMPA_AUX_BIAS_CURVE_TEMP_3_VREF1VCURVETRIM_7_MASK) +/*! @} */ + +/*! @name AUX_BIAS_CURVE_TEMP_ARRAY - Aux Bias Curve TEMP (105degC) */ +/*! @{ */ + +#define FLASH_NMPA_AUX_BIAS_CURVE_TEMP_ARRAY_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_NMPA_AUX_BIAS_CURVE_TEMP_ARRAY_FIELD_SHIFT (0U) +#define FLASH_NMPA_AUX_BIAS_CURVE_TEMP_ARRAY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_AUX_BIAS_CURVE_TEMP_ARRAY_FIELD_SHIFT)) & FLASH_NMPA_AUX_BIAS_CURVE_TEMP_ARRAY_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_NMPA_AUX_BIAS_CURVE_TEMP_ARRAY */ +#define FLASH_NMPA_AUX_BIAS_CURVE_TEMP_ARRAY_COUNT (4U) + +/*! @name TEMP_SENS_VBE1VBE8_REF_1 - */ +/*! @{ */ + +#define FLASH_NMPA_TEMP_SENS_VBE1VBE8_REF_1_VBE1_MASK (0xFFFFU) +#define FLASH_NMPA_TEMP_SENS_VBE1VBE8_REF_1_VBE1_SHIFT (0U) +#define FLASH_NMPA_TEMP_SENS_VBE1VBE8_REF_1_VBE1(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_TEMP_SENS_VBE1VBE8_REF_1_VBE1_SHIFT)) & FLASH_NMPA_TEMP_SENS_VBE1VBE8_REF_1_VBE1_MASK) + +#define FLASH_NMPA_TEMP_SENS_VBE1VBE8_REF_1_VBE8_MASK (0xFFFF0000U) +#define FLASH_NMPA_TEMP_SENS_VBE1VBE8_REF_1_VBE8_SHIFT (16U) +#define FLASH_NMPA_TEMP_SENS_VBE1VBE8_REF_1_VBE8(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_TEMP_SENS_VBE1VBE8_REF_1_VBE8_SHIFT)) & FLASH_NMPA_TEMP_SENS_VBE1VBE8_REF_1_VBE8_MASK) +/*! @} */ + +/*! @name TEMP_SENS_VBE1VBE8_REF_2 - */ +/*! @{ */ + +#define FLASH_NMPA_TEMP_SENS_VBE1VBE8_REF_2_VBE1_MASK (0xFFFFU) +#define FLASH_NMPA_TEMP_SENS_VBE1VBE8_REF_2_VBE1_SHIFT (0U) +#define FLASH_NMPA_TEMP_SENS_VBE1VBE8_REF_2_VBE1(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_TEMP_SENS_VBE1VBE8_REF_2_VBE1_SHIFT)) & FLASH_NMPA_TEMP_SENS_VBE1VBE8_REF_2_VBE1_MASK) + +#define FLASH_NMPA_TEMP_SENS_VBE1VBE8_REF_2_VBE8_MASK (0xFFFF0000U) +#define FLASH_NMPA_TEMP_SENS_VBE1VBE8_REF_2_VBE8_SHIFT (16U) +#define FLASH_NMPA_TEMP_SENS_VBE1VBE8_REF_2_VBE8(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_TEMP_SENS_VBE1VBE8_REF_2_VBE8_SHIFT)) & FLASH_NMPA_TEMP_SENS_VBE1VBE8_REF_2_VBE8_MASK) +/*! @} */ + +/*! @name TEMP_SENS_SLOPE - */ +/*! @{ */ + +#define FLASH_NMPA_TEMP_SENS_SLOPE_VALID_MASK (0x1U) +#define FLASH_NMPA_TEMP_SENS_SLOPE_VALID_SHIFT (0U) +#define FLASH_NMPA_TEMP_SENS_SLOPE_VALID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_TEMP_SENS_SLOPE_VALID_SHIFT)) & FLASH_NMPA_TEMP_SENS_SLOPE_VALID_MASK) + +#define FLASH_NMPA_TEMP_SENS_SLOPE_SLOPE_x1024_MASK (0xFFFFFFFEU) +#define FLASH_NMPA_TEMP_SENS_SLOPE_SLOPE_x1024_SHIFT (1U) +/*! SLOPE_x1024 - SLOPE_x1024[30:0] + */ +#define FLASH_NMPA_TEMP_SENS_SLOPE_SLOPE_x1024(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_TEMP_SENS_SLOPE_SLOPE_x1024_SHIFT)) & FLASH_NMPA_TEMP_SENS_SLOPE_SLOPE_x1024_MASK) +/*! @} */ + +/*! @name TEMP_SENS_OFFSET - */ +/*! @{ */ + +#define FLASH_NMPA_TEMP_SENS_OFFSET_VALID_MASK (0x1U) +#define FLASH_NMPA_TEMP_SENS_OFFSET_VALID_SHIFT (0U) +#define FLASH_NMPA_TEMP_SENS_OFFSET_VALID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_TEMP_SENS_OFFSET_VALID_SHIFT)) & FLASH_NMPA_TEMP_SENS_OFFSET_VALID_MASK) + +#define FLASH_NMPA_TEMP_SENS_OFFSET_OFFSET_x1024_MASK (0xFFFFFFFEU) +#define FLASH_NMPA_TEMP_SENS_OFFSET_OFFSET_x1024_SHIFT (1U) +/*! OFFSET_x1024 - OFFSET_x1024[30:0] + */ +#define FLASH_NMPA_TEMP_SENS_OFFSET_OFFSET_x1024(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_TEMP_SENS_OFFSET_OFFSET_x1024_SHIFT)) & FLASH_NMPA_TEMP_SENS_OFFSET_OFFSET_x1024_MASK) +/*! @} */ + +/*! @name PVT_MONITOR_0_RINGO - */ +/*! @{ */ + +#define FLASH_NMPA_PVT_MONITOR_0_RINGO_RINGO_VALID_MASK (0x1U) +#define FLASH_NMPA_PVT_MONITOR_0_RINGO_RINGO_VALID_SHIFT (0U) +#define FLASH_NMPA_PVT_MONITOR_0_RINGO_RINGO_VALID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_PVT_MONITOR_0_RINGO_RINGO_VALID_SHIFT)) & FLASH_NMPA_PVT_MONITOR_0_RINGO_RINGO_VALID_MASK) + +#define FLASH_NMPA_PVT_MONITOR_0_RINGO_RINGO_FREQ_HZ_MASK (0xFFFFFFFEU) +#define FLASH_NMPA_PVT_MONITOR_0_RINGO_RINGO_FREQ_HZ_SHIFT (1U) +#define FLASH_NMPA_PVT_MONITOR_0_RINGO_RINGO_FREQ_HZ(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_PVT_MONITOR_0_RINGO_RINGO_FREQ_HZ_SHIFT)) & FLASH_NMPA_PVT_MONITOR_0_RINGO_RINGO_FREQ_HZ_MASK) +/*! @} */ + +/*! @name PVT_MONITOR_0_DELAYS_LSB - */ +/*! @{ */ + +#define FLASH_NMPA_PVT_MONITOR_0_DELAYS_LSB_DELAY_VALID_MASK (0x1U) +#define FLASH_NMPA_PVT_MONITOR_0_DELAYS_LSB_DELAY_VALID_SHIFT (0U) +#define FLASH_NMPA_PVT_MONITOR_0_DELAYS_LSB_DELAY_VALID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_PVT_MONITOR_0_DELAYS_LSB_DELAY_VALID_SHIFT)) & FLASH_NMPA_PVT_MONITOR_0_DELAYS_LSB_DELAY_VALID_MASK) + +#define FLASH_NMPA_PVT_MONITOR_0_DELAYS_LSB_DELAY_0_MASK (0x7FEU) +#define FLASH_NMPA_PVT_MONITOR_0_DELAYS_LSB_DELAY_0_SHIFT (1U) +/*! DELAY_0 - Delay in us. + */ +#define FLASH_NMPA_PVT_MONITOR_0_DELAYS_LSB_DELAY_0(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_PVT_MONITOR_0_DELAYS_LSB_DELAY_0_SHIFT)) & FLASH_NMPA_PVT_MONITOR_0_DELAYS_LSB_DELAY_0_MASK) + +#define FLASH_NMPA_PVT_MONITOR_0_DELAYS_LSB_DELAY_1_MASK (0x1FF800U) +#define FLASH_NMPA_PVT_MONITOR_0_DELAYS_LSB_DELAY_1_SHIFT (11U) +/*! DELAY_1 - Delay in us. + */ +#define FLASH_NMPA_PVT_MONITOR_0_DELAYS_LSB_DELAY_1(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_PVT_MONITOR_0_DELAYS_LSB_DELAY_1_SHIFT)) & FLASH_NMPA_PVT_MONITOR_0_DELAYS_LSB_DELAY_1_MASK) + +#define FLASH_NMPA_PVT_MONITOR_0_DELAYS_LSB_DELAY_2_MASK (0x7FE00000U) +#define FLASH_NMPA_PVT_MONITOR_0_DELAYS_LSB_DELAY_2_SHIFT (21U) +/*! DELAY_2 - Delay in us. + */ +#define FLASH_NMPA_PVT_MONITOR_0_DELAYS_LSB_DELAY_2(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_PVT_MONITOR_0_DELAYS_LSB_DELAY_2_SHIFT)) & FLASH_NMPA_PVT_MONITOR_0_DELAYS_LSB_DELAY_2_MASK) +/*! @} */ + +/*! @name PVT_MONITOR_0_DELAYS_MSB - */ +/*! @{ */ + +#define FLASH_NMPA_PVT_MONITOR_0_DELAYS_MSB_DELAY_3_MASK (0x3FFU) +#define FLASH_NMPA_PVT_MONITOR_0_DELAYS_MSB_DELAY_3_SHIFT (0U) +/*! DELAY_3 - Delay in us. + */ +#define FLASH_NMPA_PVT_MONITOR_0_DELAYS_MSB_DELAY_3(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_PVT_MONITOR_0_DELAYS_MSB_DELAY_3_SHIFT)) & FLASH_NMPA_PVT_MONITOR_0_DELAYS_MSB_DELAY_3_MASK) + +#define FLASH_NMPA_PVT_MONITOR_0_DELAYS_MSB_DELAY_4_MASK (0xFFC00U) +#define FLASH_NMPA_PVT_MONITOR_0_DELAYS_MSB_DELAY_4_SHIFT (10U) +/*! DELAY_4 - Delay in us. + */ +#define FLASH_NMPA_PVT_MONITOR_0_DELAYS_MSB_DELAY_4(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_PVT_MONITOR_0_DELAYS_MSB_DELAY_4_SHIFT)) & FLASH_NMPA_PVT_MONITOR_0_DELAYS_MSB_DELAY_4_MASK) + +#define FLASH_NMPA_PVT_MONITOR_0_DELAYS_MSB_DELAY_5_MASK (0x3FF00000U) +#define FLASH_NMPA_PVT_MONITOR_0_DELAYS_MSB_DELAY_5_SHIFT (20U) +/*! DELAY_5 - Delay in us. + */ +#define FLASH_NMPA_PVT_MONITOR_0_DELAYS_MSB_DELAY_5(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_PVT_MONITOR_0_DELAYS_MSB_DELAY_5_SHIFT)) & FLASH_NMPA_PVT_MONITOR_0_DELAYS_MSB_DELAY_5_MASK) +/*! @} */ + +/*! @name PVT_MONITOR_0_ARRAY - */ +/*! @{ */ + +#define FLASH_NMPA_PVT_MONITOR_0_ARRAY_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_NMPA_PVT_MONITOR_0_ARRAY_FIELD_SHIFT (0U) +#define FLASH_NMPA_PVT_MONITOR_0_ARRAY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_PVT_MONITOR_0_ARRAY_FIELD_SHIFT)) & FLASH_NMPA_PVT_MONITOR_0_ARRAY_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_NMPA_PVT_MONITOR_0_ARRAY */ +#define FLASH_NMPA_PVT_MONITOR_0_ARRAY_COUNT (3U) + +/*! @name PVT_MONITOR_1_RINGO - */ +/*! @{ */ + +#define FLASH_NMPA_PVT_MONITOR_1_RINGO_RINGO_VALID_MASK (0x1U) +#define FLASH_NMPA_PVT_MONITOR_1_RINGO_RINGO_VALID_SHIFT (0U) +#define FLASH_NMPA_PVT_MONITOR_1_RINGO_RINGO_VALID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_PVT_MONITOR_1_RINGO_RINGO_VALID_SHIFT)) & FLASH_NMPA_PVT_MONITOR_1_RINGO_RINGO_VALID_MASK) + +#define FLASH_NMPA_PVT_MONITOR_1_RINGO_RINGO_FREQ_HZ_MASK (0xFFFFFFFEU) +#define FLASH_NMPA_PVT_MONITOR_1_RINGO_RINGO_FREQ_HZ_SHIFT (1U) +#define FLASH_NMPA_PVT_MONITOR_1_RINGO_RINGO_FREQ_HZ(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_PVT_MONITOR_1_RINGO_RINGO_FREQ_HZ_SHIFT)) & FLASH_NMPA_PVT_MONITOR_1_RINGO_RINGO_FREQ_HZ_MASK) +/*! @} */ + +/*! @name PVT_MONITOR_1_DELAYS_LSB - */ +/*! @{ */ + +#define FLASH_NMPA_PVT_MONITOR_1_DELAYS_LSB_DELAY_VALID_MASK (0x1U) +#define FLASH_NMPA_PVT_MONITOR_1_DELAYS_LSB_DELAY_VALID_SHIFT (0U) +#define FLASH_NMPA_PVT_MONITOR_1_DELAYS_LSB_DELAY_VALID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_PVT_MONITOR_1_DELAYS_LSB_DELAY_VALID_SHIFT)) & FLASH_NMPA_PVT_MONITOR_1_DELAYS_LSB_DELAY_VALID_MASK) + +#define FLASH_NMPA_PVT_MONITOR_1_DELAYS_LSB_DELAY_0_MASK (0x7FEU) +#define FLASH_NMPA_PVT_MONITOR_1_DELAYS_LSB_DELAY_0_SHIFT (1U) +/*! DELAY_0 - Delay in us. + */ +#define FLASH_NMPA_PVT_MONITOR_1_DELAYS_LSB_DELAY_0(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_PVT_MONITOR_1_DELAYS_LSB_DELAY_0_SHIFT)) & FLASH_NMPA_PVT_MONITOR_1_DELAYS_LSB_DELAY_0_MASK) + +#define FLASH_NMPA_PVT_MONITOR_1_DELAYS_LSB_DELAY_1_MASK (0x1FF800U) +#define FLASH_NMPA_PVT_MONITOR_1_DELAYS_LSB_DELAY_1_SHIFT (11U) +/*! DELAY_1 - Delay in us. + */ +#define FLASH_NMPA_PVT_MONITOR_1_DELAYS_LSB_DELAY_1(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_PVT_MONITOR_1_DELAYS_LSB_DELAY_1_SHIFT)) & FLASH_NMPA_PVT_MONITOR_1_DELAYS_LSB_DELAY_1_MASK) + +#define FLASH_NMPA_PVT_MONITOR_1_DELAYS_LSB_DELAY_2_MASK (0x7FE00000U) +#define FLASH_NMPA_PVT_MONITOR_1_DELAYS_LSB_DELAY_2_SHIFT (21U) +/*! DELAY_2 - Delay in us. + */ +#define FLASH_NMPA_PVT_MONITOR_1_DELAYS_LSB_DELAY_2(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_PVT_MONITOR_1_DELAYS_LSB_DELAY_2_SHIFT)) & FLASH_NMPA_PVT_MONITOR_1_DELAYS_LSB_DELAY_2_MASK) +/*! @} */ + +/*! @name PVT_MONITOR_1_DELAYS_MSB - */ +/*! @{ */ + +#define FLASH_NMPA_PVT_MONITOR_1_DELAYS_MSB_DELAY_3_MASK (0x3FFU) +#define FLASH_NMPA_PVT_MONITOR_1_DELAYS_MSB_DELAY_3_SHIFT (0U) +/*! DELAY_3 - Delay in us. + */ +#define FLASH_NMPA_PVT_MONITOR_1_DELAYS_MSB_DELAY_3(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_PVT_MONITOR_1_DELAYS_MSB_DELAY_3_SHIFT)) & FLASH_NMPA_PVT_MONITOR_1_DELAYS_MSB_DELAY_3_MASK) + +#define FLASH_NMPA_PVT_MONITOR_1_DELAYS_MSB_DELAY_4_MASK (0xFFC00U) +#define FLASH_NMPA_PVT_MONITOR_1_DELAYS_MSB_DELAY_4_SHIFT (10U) +/*! DELAY_4 - Delay in us. + */ +#define FLASH_NMPA_PVT_MONITOR_1_DELAYS_MSB_DELAY_4(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_PVT_MONITOR_1_DELAYS_MSB_DELAY_4_SHIFT)) & FLASH_NMPA_PVT_MONITOR_1_DELAYS_MSB_DELAY_4_MASK) + +#define FLASH_NMPA_PVT_MONITOR_1_DELAYS_MSB_DELAY_5_MASK (0x3FF00000U) +#define FLASH_NMPA_PVT_MONITOR_1_DELAYS_MSB_DELAY_5_SHIFT (20U) +/*! DELAY_5 - Delay in us. + */ +#define FLASH_NMPA_PVT_MONITOR_1_DELAYS_MSB_DELAY_5(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_PVT_MONITOR_1_DELAYS_MSB_DELAY_5_SHIFT)) & FLASH_NMPA_PVT_MONITOR_1_DELAYS_MSB_DELAY_5_MASK) +/*! @} */ + +/*! @name PVT_MONITOR_1_ARRAY - */ +/*! @{ */ + +#define FLASH_NMPA_PVT_MONITOR_1_ARRAY_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_NMPA_PVT_MONITOR_1_ARRAY_FIELD_SHIFT (0U) +#define FLASH_NMPA_PVT_MONITOR_1_ARRAY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_PVT_MONITOR_1_ARRAY_FIELD_SHIFT)) & FLASH_NMPA_PVT_MONITOR_1_ARRAY_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_NMPA_PVT_MONITOR_1_ARRAY */ +#define FLASH_NMPA_PVT_MONITOR_1_ARRAY_COUNT (3U) + +/*! @name NXP_DEVICE_PRIVATE_KEY - */ +/*! @{ */ + +#define FLASH_NMPA_NXP_DEVICE_PRIVATE_KEY_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_NMPA_NXP_DEVICE_PRIVATE_KEY_FIELD_SHIFT (0U) +#define FLASH_NMPA_NXP_DEVICE_PRIVATE_KEY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_NXP_DEVICE_PRIVATE_KEY_FIELD_SHIFT)) & FLASH_NMPA_NXP_DEVICE_PRIVATE_KEY_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_NMPA_NXP_DEVICE_PRIVATE_KEY */ +#define FLASH_NMPA_NXP_DEVICE_PRIVATE_KEY_COUNT (13U) + +/*! @name NXP_DEVICE_CERTIFICATE_0 - NXP Device Certificate (ECDSA_sign - r[255:128]) */ +/*! @{ */ + +#define FLASH_NMPA_NXP_DEVICE_CERTIFICATE_0_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_NMPA_NXP_DEVICE_CERTIFICATE_0_FIELD_SHIFT (0U) +#define FLASH_NMPA_NXP_DEVICE_CERTIFICATE_0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_NXP_DEVICE_CERTIFICATE_0_FIELD_SHIFT)) & FLASH_NMPA_NXP_DEVICE_CERTIFICATE_0_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_NMPA_NXP_DEVICE_CERTIFICATE_0 */ +#define FLASH_NMPA_NXP_DEVICE_CERTIFICATE_0_COUNT (4U) + +/*! @name NXP_DEVICE_CERTIFICATE_1 - NXP Device Certificate (ECDSA_sign - r[127:0]) */ +/*! @{ */ + +#define FLASH_NMPA_NXP_DEVICE_CERTIFICATE_1_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_NMPA_NXP_DEVICE_CERTIFICATE_1_FIELD_SHIFT (0U) +#define FLASH_NMPA_NXP_DEVICE_CERTIFICATE_1_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_NXP_DEVICE_CERTIFICATE_1_FIELD_SHIFT)) & FLASH_NMPA_NXP_DEVICE_CERTIFICATE_1_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_NMPA_NXP_DEVICE_CERTIFICATE_1 */ +#define FLASH_NMPA_NXP_DEVICE_CERTIFICATE_1_COUNT (4U) + +/*! @name NXP_DEVICE_CERTIFICATE_2 - NXP Device Certificate (ECDSA_sign - s[255:128]) */ +/*! @{ */ + +#define FLASH_NMPA_NXP_DEVICE_CERTIFICATE_2_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_NMPA_NXP_DEVICE_CERTIFICATE_2_FIELD_SHIFT (0U) +#define FLASH_NMPA_NXP_DEVICE_CERTIFICATE_2_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_NXP_DEVICE_CERTIFICATE_2_FIELD_SHIFT)) & FLASH_NMPA_NXP_DEVICE_CERTIFICATE_2_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_NMPA_NXP_DEVICE_CERTIFICATE_2 */ +#define FLASH_NMPA_NXP_DEVICE_CERTIFICATE_2_COUNT (4U) + +/*! @name NXP_DEVICE_CERTIFICATE_3 - NXP Device Certificate (ECDSA_sign - s[127:0]) */ +/*! @{ */ + +#define FLASH_NMPA_NXP_DEVICE_CERTIFICATE_3_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_NMPA_NXP_DEVICE_CERTIFICATE_3_FIELD_SHIFT (0U) +#define FLASH_NMPA_NXP_DEVICE_CERTIFICATE_3_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_NXP_DEVICE_CERTIFICATE_3_FIELD_SHIFT)) & FLASH_NMPA_NXP_DEVICE_CERTIFICATE_3_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_NMPA_NXP_DEVICE_CERTIFICATE_3 */ +#define FLASH_NMPA_NXP_DEVICE_CERTIFICATE_3_COUNT (4U) + +/*! @name SHA256_DIGEST - SHA-256 DIGEST (9EC00 - 9FDBC) ROM Patch Area + NXP Area (IMPORTANT NOTE: Pages used for Repair (N-8 to N-3) are excluded from the computation) SHA256_DIGEST0 for DIGEST[31:0]..SHA-256 DIGEST (9EC00 - 9FDBC) ROM Patch Area + NXP Area (IMPORTANT NOTE: Pages used for Repair (N-8 to N-3) are excluded from the computation) SHA256_DIGEST7 for DIGEST[255:224] */ +/*! @{ */ + +#define FLASH_NMPA_SHA256_DIGEST_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_NMPA_SHA256_DIGEST_FIELD_SHIFT (0U) +#define FLASH_NMPA_SHA256_DIGEST_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_SHA256_DIGEST_FIELD_SHIFT)) & FLASH_NMPA_SHA256_DIGEST_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_NMPA_SHA256_DIGEST */ +#define FLASH_NMPA_SHA256_DIGEST_COUNT (8U) + +/*! @name ECID_BACKUP_0 - */ +/*! @{ */ + +#define FLASH_NMPA_ECID_BACKUP_0_COORD_Y_MASK (0xFFFFU) +#define FLASH_NMPA_ECID_BACKUP_0_COORD_Y_SHIFT (0U) +#define FLASH_NMPA_ECID_BACKUP_0_COORD_Y(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_ECID_BACKUP_0_COORD_Y_SHIFT)) & FLASH_NMPA_ECID_BACKUP_0_COORD_Y_MASK) + +#define FLASH_NMPA_ECID_BACKUP_0_COORD_X_MASK (0xFFFF0000U) +#define FLASH_NMPA_ECID_BACKUP_0_COORD_X_SHIFT (16U) +#define FLASH_NMPA_ECID_BACKUP_0_COORD_X(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_ECID_BACKUP_0_COORD_X_SHIFT)) & FLASH_NMPA_ECID_BACKUP_0_COORD_X_MASK) +/*! @} */ + +/*! @name ECID_BACKUP_1 - */ +/*! @{ */ + +#define FLASH_NMPA_ECID_BACKUP_1_WAFER_MASK (0xFFU) +#define FLASH_NMPA_ECID_BACKUP_1_WAFER_SHIFT (0U) +#define FLASH_NMPA_ECID_BACKUP_1_WAFER(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_ECID_BACKUP_1_WAFER_SHIFT)) & FLASH_NMPA_ECID_BACKUP_1_WAFER_MASK) +/*! @} */ + +/*! @name ECID_BACKUP_2 - */ +/*! @{ */ + +#define FLASH_NMPA_ECID_BACKUP_2_LOTID_LSB_MASK (0xFFFFFFFFU) +#define FLASH_NMPA_ECID_BACKUP_2_LOTID_LSB_SHIFT (0U) +#define FLASH_NMPA_ECID_BACKUP_2_LOTID_LSB(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_ECID_BACKUP_2_LOTID_LSB_SHIFT)) & FLASH_NMPA_ECID_BACKUP_2_LOTID_LSB_MASK) +/*! @} */ + +/*! @name ECID_BACKUP_3 - */ +/*! @{ */ + +#define FLASH_NMPA_ECID_BACKUP_3_LOTID_MSB_MASK (0xFFFFFFFFU) +#define FLASH_NMPA_ECID_BACKUP_3_LOTID_MSB_SHIFT (0U) +#define FLASH_NMPA_ECID_BACKUP_3_LOTID_MSB(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_ECID_BACKUP_3_LOTID_MSB_SHIFT)) & FLASH_NMPA_ECID_BACKUP_3_LOTID_MSB_MASK) +/*! @} */ + +/*! @name ECID_BACKUP_ARRAY - ECID backup (the original is in page n-1) */ +/*! @{ */ + +#define FLASH_NMPA_ECID_BACKUP_ARRAY_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_NMPA_ECID_BACKUP_ARRAY_FIELD_SHIFT (0U) +#define FLASH_NMPA_ECID_BACKUP_ARRAY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_ECID_BACKUP_ARRAY_FIELD_SHIFT)) & FLASH_NMPA_ECID_BACKUP_ARRAY_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_NMPA_ECID_BACKUP_ARRAY */ +#define FLASH_NMPA_ECID_BACKUP_ARRAY_COUNT (4U) + +/* The count of FLASH_NMPA_CHECKSUM */ +#define FLASH_NMPA_CHECKSUM_COUNT (4U) + +/*! @name DIS_ROM_HIDING - */ +/*! @{ */ + +#define FLASH_NMPA_DIS_ROM_HIDING_DIS_ROM_HIDING_MASK (0xFFFFFFFFU) +#define FLASH_NMPA_DIS_ROM_HIDING_DIS_ROM_HIDING_SHIFT (0U) +/*! DIS_ROM_HIDING - When 0x3CC35AA5 ROM hiding feture is disabled. All other values critical ROM is hidden. + */ +#define FLASH_NMPA_DIS_ROM_HIDING_DIS_ROM_HIDING(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_DIS_ROM_HIDING_DIS_ROM_HIDING_SHIFT)) & FLASH_NMPA_DIS_ROM_HIDING_DIS_ROM_HIDING_MASK) +/*! @} */ + +/*! @name PUF_SRAM - */ +/*! @{ */ + +#define FLASH_NMPA_PUF_SRAM_PUF_SRAM_VALID_MASK (0x1U) +#define FLASH_NMPA_PUF_SRAM_PUF_SRAM_VALID_SHIFT (0U) +/*! PUF_SRAM_VALID - 1: PUF_SRAM is valid. + */ +#define FLASH_NMPA_PUF_SRAM_PUF_SRAM_VALID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_PUF_SRAM_PUF_SRAM_VALID_SHIFT)) & FLASH_NMPA_PUF_SRAM_PUF_SRAM_VALID_MASK) + +#define FLASH_NMPA_PUF_SRAM_mode_MASK (0x2U) +#define FLASH_NMPA_PUF_SRAM_mode_SHIFT (1U) +/*! mode - PUF SRAM Controller operating mode + */ +#define FLASH_NMPA_PUF_SRAM_mode(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_PUF_SRAM_mode_SHIFT)) & FLASH_NMPA_PUF_SRAM_mode_MASK) + +#define FLASH_NMPA_PUF_SRAM_ckgating_MASK (0x4U) +#define FLASH_NMPA_PUF_SRAM_ckgating_SHIFT (2U) +/*! ckgating - PUF SRAM Clock Gating control + */ +#define FLASH_NMPA_PUF_SRAM_ckgating(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_PUF_SRAM_ckgating_SHIFT)) & FLASH_NMPA_PUF_SRAM_ckgating_MASK) + +#define FLASH_NMPA_PUF_SRAM_SMB_MASK (0x300U) +#define FLASH_NMPA_PUF_SRAM_SMB_SHIFT (8U) +/*! SMB - Source Biasing voltage. + * 0b00..Low leakage. + * 0b01..Medium leakage. + * 0b10..Highest leakage. + * 0b11..Disable. + */ +#define FLASH_NMPA_PUF_SRAM_SMB(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_PUF_SRAM_SMB_SHIFT)) & FLASH_NMPA_PUF_SRAM_SMB_MASK) + +#define FLASH_NMPA_PUF_SRAM_RM_MASK (0x1C00U) +#define FLASH_NMPA_PUF_SRAM_RM_SHIFT (10U) +/*! RM - Read Margin control settings. + */ +#define FLASH_NMPA_PUF_SRAM_RM(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_PUF_SRAM_RM_SHIFT)) & FLASH_NMPA_PUF_SRAM_RM_MASK) + +#define FLASH_NMPA_PUF_SRAM_WM_MASK (0xE000U) +#define FLASH_NMPA_PUF_SRAM_WM_SHIFT (13U) +/*! WM - Write Margin control settings. + */ +#define FLASH_NMPA_PUF_SRAM_WM(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_PUF_SRAM_WM_SHIFT)) & FLASH_NMPA_PUF_SRAM_WM_MASK) + +#define FLASH_NMPA_PUF_SRAM_WRME_MASK (0x10000U) +#define FLASH_NMPA_PUF_SRAM_WRME_SHIFT (16U) +/*! WRME - Write read margin enable. + */ +#define FLASH_NMPA_PUF_SRAM_WRME(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_PUF_SRAM_WRME_SHIFT)) & FLASH_NMPA_PUF_SRAM_WRME_MASK) + +#define FLASH_NMPA_PUF_SRAM_RAEN_MASK (0x20000U) +#define FLASH_NMPA_PUF_SRAM_RAEN_SHIFT (17U) +/*! RAEN - SRAM Read Assist Enable + */ +#define FLASH_NMPA_PUF_SRAM_RAEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_PUF_SRAM_RAEN_SHIFT)) & FLASH_NMPA_PUF_SRAM_RAEN_MASK) + +#define FLASH_NMPA_PUF_SRAM_RAM_MASK (0x3C0000U) +#define FLASH_NMPA_PUF_SRAM_RAM_SHIFT (18U) +/*! RAM - SRAM Read Assist settings + */ +#define FLASH_NMPA_PUF_SRAM_RAM(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_PUF_SRAM_RAM_SHIFT)) & FLASH_NMPA_PUF_SRAM_RAM_MASK) + +#define FLASH_NMPA_PUF_SRAM_WAEN_MASK (0x400000U) +#define FLASH_NMPA_PUF_SRAM_WAEN_SHIFT (22U) +/*! WAEN - SRAM Write Assist Enable + */ +#define FLASH_NMPA_PUF_SRAM_WAEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_PUF_SRAM_WAEN_SHIFT)) & FLASH_NMPA_PUF_SRAM_WAEN_MASK) + +#define FLASH_NMPA_PUF_SRAM_WAM_MASK (0x1800000U) +#define FLASH_NMPA_PUF_SRAM_WAM_SHIFT (23U) +/*! WAM - SRAM Write Assist settings + */ +#define FLASH_NMPA_PUF_SRAM_WAM(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_PUF_SRAM_WAM_SHIFT)) & FLASH_NMPA_PUF_SRAM_WAM_MASK) + +#define FLASH_NMPA_PUF_SRAM_STBP_MASK (0x2000000U) +#define FLASH_NMPA_PUF_SRAM_STBP_SHIFT (25U) +/*! STBP - STBP + */ +#define FLASH_NMPA_PUF_SRAM_STBP(x) (((uint32_t)(((uint32_t)(x)) << FLASH_NMPA_PUF_SRAM_STBP_SHIFT)) & FLASH_NMPA_PUF_SRAM_STBP_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group FLASH_NMPA_Register_Masks */ + + +/* FLASH_NMPA - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral FLASH_NMPA base address */ + #define FLASH_NMPA_BASE (0x1003FC00u) + /** Peripheral FLASH_NMPA base address */ + #define FLASH_NMPA_BASE_NS (0x3FC00u) + /** Peripheral FLASH_NMPA base pointer */ + #define FLASH_NMPA ((FLASH_NMPA_Type *)FLASH_NMPA_BASE) + /** Peripheral FLASH_NMPA base pointer */ + #define FLASH_NMPA_NS ((FLASH_NMPA_Type *)FLASH_NMPA_BASE_NS) + /** Array initializer of FLASH_NMPA peripheral base addresses */ + #define FLASH_NMPA_BASE_ADDRS { FLASH_NMPA_BASE } + /** Array initializer of FLASH_NMPA peripheral base pointers */ + #define FLASH_NMPA_BASE_PTRS { FLASH_NMPA } + /** Array initializer of FLASH_NMPA peripheral base addresses */ + #define FLASH_NMPA_BASE_ADDRS_NS { FLASH_NMPA_BASE_NS } + /** Array initializer of FLASH_NMPA peripheral base pointers */ + #define FLASH_NMPA_BASE_PTRS_NS { FLASH_NMPA_NS } +#else + /** Peripheral FLASH_NMPA base address */ + #define FLASH_NMPA_BASE (0x3FC00u) + /** Peripheral FLASH_NMPA base pointer */ + #define FLASH_NMPA ((FLASH_NMPA_Type *)FLASH_NMPA_BASE) + /** Array initializer of FLASH_NMPA peripheral base addresses */ + #define FLASH_NMPA_BASE_ADDRS { FLASH_NMPA_BASE } + /** Array initializer of FLASH_NMPA peripheral base pointers */ + #define FLASH_NMPA_BASE_PTRS { FLASH_NMPA } +#endif + +/*! + * @} + */ /* end of group FLASH_NMPA_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- FLASH_ROMPATCH Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FLASH_ROMPATCH_Peripheral_Access_Layer FLASH_ROMPATCH Peripheral Access Layer + * @{ + */ + +/** FLASH_ROMPATCH - Register Layout Typedef */ +typedef struct { + __IO uint32_t HEADER; /**< ., offset: 0x0 */ + __IO uint32_t PATCH[255]; /**< ., array offset: 0x4, array step: 0x4 */ +} FLASH_ROMPATCH_Type; + +/* ---------------------------------------------------------------------------- + -- FLASH_ROMPATCH Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FLASH_ROMPATCH_Register_Masks FLASH_ROMPATCH Register Masks + * @{ + */ + +/*! @name HEADER - . */ +/*! @{ */ + +#define FLASH_ROMPATCH_HEADER_ENTRIES_MASK (0xFFU) +#define FLASH_ROMPATCH_HEADER_ENTRIES_SHIFT (0U) +/*! ENTRIES - . + */ +#define FLASH_ROMPATCH_HEADER_ENTRIES(x) (((uint32_t)(((uint32_t)(x)) << FLASH_ROMPATCH_HEADER_ENTRIES_SHIFT)) & FLASH_ROMPATCH_HEADER_ENTRIES_MASK) + +#define FLASH_ROMPATCH_HEADER_SUB_TYPE_MASK (0xFF00U) +#define FLASH_ROMPATCH_HEADER_SUB_TYPE_SHIFT (8U) +/*! SUB_TYPE - . + */ +#define FLASH_ROMPATCH_HEADER_SUB_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_ROMPATCH_HEADER_SUB_TYPE_SHIFT)) & FLASH_ROMPATCH_HEADER_SUB_TYPE_MASK) + +#define FLASH_ROMPATCH_HEADER_TYPE_MASK (0xFF0000U) +#define FLASH_ROMPATCH_HEADER_TYPE_SHIFT (16U) +/*! TYPE - . + */ +#define FLASH_ROMPATCH_HEADER_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_ROMPATCH_HEADER_TYPE_SHIFT)) & FLASH_ROMPATCH_HEADER_TYPE_MASK) + +#define FLASH_ROMPATCH_HEADER_IDENTIFIER_MASK (0xFF000000U) +#define FLASH_ROMPATCH_HEADER_IDENTIFIER_SHIFT (24U) +/*! IDENTIFIER - . + */ +#define FLASH_ROMPATCH_HEADER_IDENTIFIER(x) (((uint32_t)(((uint32_t)(x)) << FLASH_ROMPATCH_HEADER_IDENTIFIER_SHIFT)) & FLASH_ROMPATCH_HEADER_IDENTIFIER_MASK) +/*! @} */ + +/*! @name PATCH - . */ +/*! @{ */ + +#define FLASH_ROMPATCH_PATCH_PATCH_MASK (0xFFFFFFFFU) +#define FLASH_ROMPATCH_PATCH_PATCH_SHIFT (0U) +/*! PATCH - . + */ +#define FLASH_ROMPATCH_PATCH_PATCH(x) (((uint32_t)(((uint32_t)(x)) << FLASH_ROMPATCH_PATCH_PATCH_SHIFT)) & FLASH_ROMPATCH_PATCH_PATCH_MASK) +/*! @} */ + +/* The count of FLASH_ROMPATCH_PATCH */ +#define FLASH_ROMPATCH_PATCH_COUNT (255U) + + +/*! + * @} + */ /* end of group FLASH_ROMPATCH_Register_Masks */ + + +/* FLASH_ROMPATCH - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral FLASH_ROMPATCH base address */ + #define FLASH_ROMPATCH_BASE (0x1003EC00u) + /** Peripheral FLASH_ROMPATCH base address */ + #define FLASH_ROMPATCH_BASE_NS (0x3EC00u) + /** Peripheral FLASH_ROMPATCH base pointer */ + #define FLASH_ROMPATCH ((FLASH_ROMPATCH_Type *)FLASH_ROMPATCH_BASE) + /** Peripheral FLASH_ROMPATCH base pointer */ + #define FLASH_ROMPATCH_NS ((FLASH_ROMPATCH_Type *)FLASH_ROMPATCH_BASE_NS) + /** Array initializer of FLASH_ROMPATCH peripheral base addresses */ + #define FLASH_ROMPATCH_BASE_ADDRS { FLASH_ROMPATCH_BASE } + /** Array initializer of FLASH_ROMPATCH peripheral base pointers */ + #define FLASH_ROMPATCH_BASE_PTRS { FLASH_ROMPATCH } + /** Array initializer of FLASH_ROMPATCH peripheral base addresses */ + #define FLASH_ROMPATCH_BASE_ADDRS_NS { FLASH_ROMPATCH_BASE_NS } + /** Array initializer of FLASH_ROMPATCH peripheral base pointers */ + #define FLASH_ROMPATCH_BASE_PTRS_NS { FLASH_ROMPATCH_NS } +#else + /** Peripheral FLASH_ROMPATCH base address */ + #define FLASH_ROMPATCH_BASE (0x3EC00u) + /** Peripheral FLASH_ROMPATCH base pointer */ + #define FLASH_ROMPATCH ((FLASH_ROMPATCH_Type *)FLASH_ROMPATCH_BASE) + /** Array initializer of FLASH_ROMPATCH peripheral base addresses */ + #define FLASH_ROMPATCH_BASE_ADDRS { FLASH_ROMPATCH_BASE } + /** Array initializer of FLASH_ROMPATCH peripheral base pointers */ + #define FLASH_ROMPATCH_BASE_PTRS { FLASH_ROMPATCH } +#endif + +/*! + * @} + */ /* end of group FLASH_ROMPATCH_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- FLEXCOMM Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FLEXCOMM_Peripheral_Access_Layer FLEXCOMM Peripheral Access Layer + * @{ + */ + +/** FLEXCOMM - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[4088]; + __IO uint32_t PSELID; /**< Peripheral Select and Flexcomm ID register., offset: 0xFF8 */ + __I uint32_t PID; /**< Peripheral identification register., offset: 0xFFC */ +} FLEXCOMM_Type; + +/* ---------------------------------------------------------------------------- + -- FLEXCOMM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FLEXCOMM_Register_Masks FLEXCOMM Register Masks + * @{ + */ + +/*! @name PSELID - Peripheral Select and Flexcomm ID register. */ +/*! @{ */ + +#define FLEXCOMM_PSELID_PERSEL_MASK (0x7U) +#define FLEXCOMM_PSELID_PERSEL_SHIFT (0U) +/*! PERSEL - Peripheral Select. This field is writable by software. + * 0b000..No peripheral selected. + * 0b001..USART function selected. + * 0b010..SPI function selected. + * 0b011..I2C function selected. + * 0b100..I2S transmit function selected. + * 0b101..I2S receive function selected. + * 0b110..Reserved + * 0b111..Reserved + */ +#define FLEXCOMM_PSELID_PERSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_PERSEL_SHIFT)) & FLEXCOMM_PSELID_PERSEL_MASK) + +#define FLEXCOMM_PSELID_LOCK_MASK (0x8U) +#define FLEXCOMM_PSELID_LOCK_SHIFT (3U) +/*! LOCK - Lock the peripheral select. This field is writable by software. + * 0b0..Peripheral select can be changed by software. + * 0b1..Peripheral select is locked and cannot be changed until this Flexcomm or the entire device is reset. + */ +#define FLEXCOMM_PSELID_LOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_LOCK_SHIFT)) & FLEXCOMM_PSELID_LOCK_MASK) + +#define FLEXCOMM_PSELID_USARTPRESENT_MASK (0x10U) +#define FLEXCOMM_PSELID_USARTPRESENT_SHIFT (4U) +/*! USARTPRESENT - USART present indicator. This field is Read-only. + * 0b0..This Flexcomm does not include the USART function. + * 0b1..This Flexcomm includes the USART function. + */ +#define FLEXCOMM_PSELID_USARTPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_USARTPRESENT_SHIFT)) & FLEXCOMM_PSELID_USARTPRESENT_MASK) + +#define FLEXCOMM_PSELID_SPIPRESENT_MASK (0x20U) +#define FLEXCOMM_PSELID_SPIPRESENT_SHIFT (5U) +/*! SPIPRESENT - SPI present indicator. This field is Read-only. + * 0b0..This Flexcomm does not include the SPI function. + * 0b1..This Flexcomm includes the SPI function. + */ +#define FLEXCOMM_PSELID_SPIPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_SPIPRESENT_SHIFT)) & FLEXCOMM_PSELID_SPIPRESENT_MASK) + +#define FLEXCOMM_PSELID_I2CPRESENT_MASK (0x40U) +#define FLEXCOMM_PSELID_I2CPRESENT_SHIFT (6U) +/*! I2CPRESENT - I2C present indicator. This field is Read-only. + * 0b0..This Flexcomm does not include the I2C function. + * 0b1..This Flexcomm includes the I2C function. + */ +#define FLEXCOMM_PSELID_I2CPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_I2CPRESENT_SHIFT)) & FLEXCOMM_PSELID_I2CPRESENT_MASK) + +#define FLEXCOMM_PSELID_I2SPRESENT_MASK (0x80U) +#define FLEXCOMM_PSELID_I2SPRESENT_SHIFT (7U) +/*! I2SPRESENT - I 2S present indicator. This field is Read-only. + * 0b0..This Flexcomm does not include the I2S function. + * 0b1..This Flexcomm includes the I2S function. + */ +#define FLEXCOMM_PSELID_I2SPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_I2SPRESENT_SHIFT)) & FLEXCOMM_PSELID_I2SPRESENT_MASK) + +#define FLEXCOMM_PSELID_ID_MASK (0xFFFFF000U) +#define FLEXCOMM_PSELID_ID_SHIFT (12U) +/*! ID - Flexcomm ID. + */ +#define FLEXCOMM_PSELID_ID(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_ID_SHIFT)) & FLEXCOMM_PSELID_ID_MASK) +/*! @} */ + +/*! @name PID - Peripheral identification register. */ +/*! @{ */ + +#define FLEXCOMM_PID_APERTURE_MASK (0xFFU) +#define FLEXCOMM_PID_APERTURE_SHIFT (0U) +/*! APERTURE - size aperture for the register port on the bus (APB or AHB). + */ +#define FLEXCOMM_PID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_APERTURE_SHIFT)) & FLEXCOMM_PID_APERTURE_MASK) + +#define FLEXCOMM_PID_MINOR_REV_MASK (0xF00U) +#define FLEXCOMM_PID_MINOR_REV_SHIFT (8U) +/*! MINOR_REV - Minor revision of module implementation. + */ +#define FLEXCOMM_PID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_MINOR_REV_SHIFT)) & FLEXCOMM_PID_MINOR_REV_MASK) + +#define FLEXCOMM_PID_MAJOR_REV_MASK (0xF000U) +#define FLEXCOMM_PID_MAJOR_REV_SHIFT (12U) +/*! MAJOR_REV - Major revision of module implementation. + */ +#define FLEXCOMM_PID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_MAJOR_REV_SHIFT)) & FLEXCOMM_PID_MAJOR_REV_MASK) + +#define FLEXCOMM_PID_ID_MASK (0xFFFF0000U) +#define FLEXCOMM_PID_ID_SHIFT (16U) +/*! ID - Module identifier for the selected function. + */ +#define FLEXCOMM_PID_ID(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_ID_SHIFT)) & FLEXCOMM_PID_ID_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group FLEXCOMM_Register_Masks */ + + +/* FLEXCOMM - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral FLEXCOMM0 base address */ + #define FLEXCOMM0_BASE (0x50086000u) + /** Peripheral FLEXCOMM0 base address */ + #define FLEXCOMM0_BASE_NS (0x40086000u) + /** Peripheral FLEXCOMM0 base pointer */ + #define FLEXCOMM0 ((FLEXCOMM_Type *)FLEXCOMM0_BASE) + /** Peripheral FLEXCOMM0 base pointer */ + #define FLEXCOMM0_NS ((FLEXCOMM_Type *)FLEXCOMM0_BASE_NS) + /** Peripheral FLEXCOMM1 base address */ + #define FLEXCOMM1_BASE (0x50087000u) + /** Peripheral FLEXCOMM1 base address */ + #define FLEXCOMM1_BASE_NS (0x40087000u) + /** Peripheral FLEXCOMM1 base pointer */ + #define FLEXCOMM1 ((FLEXCOMM_Type *)FLEXCOMM1_BASE) + /** Peripheral FLEXCOMM1 base pointer */ + #define FLEXCOMM1_NS ((FLEXCOMM_Type *)FLEXCOMM1_BASE_NS) + /** Peripheral FLEXCOMM2 base address */ + #define FLEXCOMM2_BASE (0x50088000u) + /** Peripheral FLEXCOMM2 base address */ + #define FLEXCOMM2_BASE_NS (0x40088000u) + /** Peripheral FLEXCOMM2 base pointer */ + #define FLEXCOMM2 ((FLEXCOMM_Type *)FLEXCOMM2_BASE) + /** Peripheral FLEXCOMM2 base pointer */ + #define FLEXCOMM2_NS ((FLEXCOMM_Type *)FLEXCOMM2_BASE_NS) + /** Peripheral FLEXCOMM3 base address */ + #define FLEXCOMM3_BASE (0x50089000u) + /** Peripheral FLEXCOMM3 base address */ + #define FLEXCOMM3_BASE_NS (0x40089000u) + /** Peripheral FLEXCOMM3 base pointer */ + #define FLEXCOMM3 ((FLEXCOMM_Type *)FLEXCOMM3_BASE) + /** Peripheral FLEXCOMM3 base pointer */ + #define FLEXCOMM3_NS ((FLEXCOMM_Type *)FLEXCOMM3_BASE_NS) + /** Peripheral FLEXCOMM4 base address */ + #define FLEXCOMM4_BASE (0x5008A000u) + /** Peripheral FLEXCOMM4 base address */ + #define FLEXCOMM4_BASE_NS (0x4008A000u) + /** Peripheral FLEXCOMM4 base pointer */ + #define FLEXCOMM4 ((FLEXCOMM_Type *)FLEXCOMM4_BASE) + /** Peripheral FLEXCOMM4 base pointer */ + #define FLEXCOMM4_NS ((FLEXCOMM_Type *)FLEXCOMM4_BASE_NS) + /** Peripheral FLEXCOMM5 base address */ + #define FLEXCOMM5_BASE (0x50096000u) + /** Peripheral FLEXCOMM5 base address */ + #define FLEXCOMM5_BASE_NS (0x40096000u) + /** Peripheral FLEXCOMM5 base pointer */ + #define FLEXCOMM5 ((FLEXCOMM_Type *)FLEXCOMM5_BASE) + /** Peripheral FLEXCOMM5 base pointer */ + #define FLEXCOMM5_NS ((FLEXCOMM_Type *)FLEXCOMM5_BASE_NS) + /** Peripheral FLEXCOMM6 base address */ + #define FLEXCOMM6_BASE (0x50097000u) + /** Peripheral FLEXCOMM6 base address */ + #define FLEXCOMM6_BASE_NS (0x40097000u) + /** Peripheral FLEXCOMM6 base pointer */ + #define FLEXCOMM6 ((FLEXCOMM_Type *)FLEXCOMM6_BASE) + /** Peripheral FLEXCOMM6 base pointer */ + #define FLEXCOMM6_NS ((FLEXCOMM_Type *)FLEXCOMM6_BASE_NS) + /** Peripheral FLEXCOMM7 base address */ + #define FLEXCOMM7_BASE (0x50098000u) + /** Peripheral FLEXCOMM7 base address */ + #define FLEXCOMM7_BASE_NS (0x40098000u) + /** Peripheral FLEXCOMM7 base pointer */ + #define FLEXCOMM7 ((FLEXCOMM_Type *)FLEXCOMM7_BASE) + /** Peripheral FLEXCOMM7 base pointer */ + #define FLEXCOMM7_NS ((FLEXCOMM_Type *)FLEXCOMM7_BASE_NS) + /** Peripheral FLEXCOMM8 base address */ + #define FLEXCOMM8_BASE (0x5009F000u) + /** Peripheral FLEXCOMM8 base address */ + #define FLEXCOMM8_BASE_NS (0x4009F000u) + /** Peripheral FLEXCOMM8 base pointer */ + #define FLEXCOMM8 ((FLEXCOMM_Type *)FLEXCOMM8_BASE) + /** Peripheral FLEXCOMM8 base pointer */ + #define FLEXCOMM8_NS ((FLEXCOMM_Type *)FLEXCOMM8_BASE_NS) + /** Array initializer of FLEXCOMM peripheral base addresses */ + #define FLEXCOMM_BASE_ADDRS { FLEXCOMM0_BASE, FLEXCOMM1_BASE, FLEXCOMM2_BASE, FLEXCOMM3_BASE, FLEXCOMM4_BASE, FLEXCOMM5_BASE, FLEXCOMM6_BASE, FLEXCOMM7_BASE, FLEXCOMM8_BASE } + /** Array initializer of FLEXCOMM peripheral base pointers */ + #define FLEXCOMM_BASE_PTRS { FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8 } + /** Array initializer of FLEXCOMM peripheral base addresses */ + #define FLEXCOMM_BASE_ADDRS_NS { FLEXCOMM0_BASE_NS, FLEXCOMM1_BASE_NS, FLEXCOMM2_BASE_NS, FLEXCOMM3_BASE_NS, FLEXCOMM4_BASE_NS, FLEXCOMM5_BASE_NS, FLEXCOMM6_BASE_NS, FLEXCOMM7_BASE_NS, FLEXCOMM8_BASE_NS } + /** Array initializer of FLEXCOMM peripheral base pointers */ + #define FLEXCOMM_BASE_PTRS_NS { FLEXCOMM0_NS, FLEXCOMM1_NS, FLEXCOMM2_NS, FLEXCOMM3_NS, FLEXCOMM4_NS, FLEXCOMM5_NS, FLEXCOMM6_NS, FLEXCOMM7_NS, FLEXCOMM8_NS } +#else + /** Peripheral FLEXCOMM0 base address */ + #define FLEXCOMM0_BASE (0x40086000u) + /** Peripheral FLEXCOMM0 base pointer */ + #define FLEXCOMM0 ((FLEXCOMM_Type *)FLEXCOMM0_BASE) + /** Peripheral FLEXCOMM1 base address */ + #define FLEXCOMM1_BASE (0x40087000u) + /** Peripheral FLEXCOMM1 base pointer */ + #define FLEXCOMM1 ((FLEXCOMM_Type *)FLEXCOMM1_BASE) + /** Peripheral FLEXCOMM2 base address */ + #define FLEXCOMM2_BASE (0x40088000u) + /** Peripheral FLEXCOMM2 base pointer */ + #define FLEXCOMM2 ((FLEXCOMM_Type *)FLEXCOMM2_BASE) + /** Peripheral FLEXCOMM3 base address */ + #define FLEXCOMM3_BASE (0x40089000u) + /** Peripheral FLEXCOMM3 base pointer */ + #define FLEXCOMM3 ((FLEXCOMM_Type *)FLEXCOMM3_BASE) + /** Peripheral FLEXCOMM4 base address */ + #define FLEXCOMM4_BASE (0x4008A000u) + /** Peripheral FLEXCOMM4 base pointer */ + #define FLEXCOMM4 ((FLEXCOMM_Type *)FLEXCOMM4_BASE) + /** Peripheral FLEXCOMM5 base address */ + #define FLEXCOMM5_BASE (0x40096000u) + /** Peripheral FLEXCOMM5 base pointer */ + #define FLEXCOMM5 ((FLEXCOMM_Type *)FLEXCOMM5_BASE) + /** Peripheral FLEXCOMM6 base address */ + #define FLEXCOMM6_BASE (0x40097000u) + /** Peripheral FLEXCOMM6 base pointer */ + #define FLEXCOMM6 ((FLEXCOMM_Type *)FLEXCOMM6_BASE) + /** Peripheral FLEXCOMM7 base address */ + #define FLEXCOMM7_BASE (0x40098000u) + /** Peripheral FLEXCOMM7 base pointer */ + #define FLEXCOMM7 ((FLEXCOMM_Type *)FLEXCOMM7_BASE) + /** Peripheral FLEXCOMM8 base address */ + #define FLEXCOMM8_BASE (0x4009F000u) + /** Peripheral FLEXCOMM8 base pointer */ + #define FLEXCOMM8 ((FLEXCOMM_Type *)FLEXCOMM8_BASE) + /** Array initializer of FLEXCOMM peripheral base addresses */ + #define FLEXCOMM_BASE_ADDRS { FLEXCOMM0_BASE, FLEXCOMM1_BASE, FLEXCOMM2_BASE, FLEXCOMM3_BASE, FLEXCOMM4_BASE, FLEXCOMM5_BASE, FLEXCOMM6_BASE, FLEXCOMM7_BASE, FLEXCOMM8_BASE } + /** Array initializer of FLEXCOMM peripheral base pointers */ + #define FLEXCOMM_BASE_PTRS { FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8 } +#endif +/** Interrupt vectors for the FLEXCOMM peripheral type */ +#define FLEXCOMM_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn, FLEXCOMM8_IRQn } + +/*! + * @} + */ /* end of group FLEXCOMM_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- GINT Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GINT_Peripheral_Access_Layer GINT Peripheral Access Layer + * @{ + */ + +/** GINT - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL; /**< GPIO grouped interrupt control register, offset: 0x0 */ + uint8_t RESERVED_0[28]; + __IO uint32_t PORT_POL[2]; /**< GPIO grouped interrupt port 0 polarity register, array offset: 0x20, array step: 0x4 */ + uint8_t RESERVED_1[24]; + __IO uint32_t PORT_ENA[2]; /**< GPIO grouped interrupt port 0 enable register, array offset: 0x40, array step: 0x4 */ +} GINT_Type; + +/* ---------------------------------------------------------------------------- + -- GINT Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GINT_Register_Masks GINT Register Masks + * @{ + */ + +/*! @name CTRL - GPIO grouped interrupt control register */ +/*! @{ */ + +#define GINT_CTRL_INT_MASK (0x1U) +#define GINT_CTRL_INT_SHIFT (0U) +/*! INT - Group interrupt status. This bit is cleared by writing a one to it. Writing zero has no effect. + * 0b0..No request. No interrupt request is pending. + * 0b1..Request active. Interrupt request is active. + */ +#define GINT_CTRL_INT(x) (((uint32_t)(((uint32_t)(x)) << GINT_CTRL_INT_SHIFT)) & GINT_CTRL_INT_MASK) + +#define GINT_CTRL_COMB_MASK (0x2U) +#define GINT_CTRL_COMB_SHIFT (1U) +/*! COMB - Combine enabled inputs for group interrupt + * 0b0..Or. OR functionality: A grouped interrupt is generated when any one of the enabled inputs is active (based on its programmed polarity). + * 0b1..And. AND functionality: An interrupt is generated when all enabled bits are active (based on their programmed polarity). + */ +#define GINT_CTRL_COMB(x) (((uint32_t)(((uint32_t)(x)) << GINT_CTRL_COMB_SHIFT)) & GINT_CTRL_COMB_MASK) + +#define GINT_CTRL_TRIG_MASK (0x4U) +#define GINT_CTRL_TRIG_SHIFT (2U) +/*! TRIG - Group interrupt trigger + * 0b0..Edge-triggered. + * 0b1..Level-triggered. + */ +#define GINT_CTRL_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GINT_CTRL_TRIG_SHIFT)) & GINT_CTRL_TRIG_MASK) +/*! @} */ + +/*! @name PORT_POL - GPIO grouped interrupt port 0 polarity register */ +/*! @{ */ + +#define GINT_PORT_POL_POL_MASK (0xFFFFFFFFU) +#define GINT_PORT_POL_POL_SHIFT (0U) +/*! POL - Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n + * of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to + * the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin + * contributes to the group interrupt. + */ +#define GINT_PORT_POL_POL(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_POL_POL_SHIFT)) & GINT_PORT_POL_POL_MASK) +/*! @} */ + +/* The count of GINT_PORT_POL */ +#define GINT_PORT_POL_COUNT (2U) + +/*! @name PORT_ENA - GPIO grouped interrupt port 0 enable register */ +/*! @{ */ + +#define GINT_PORT_ENA_ENA_MASK (0xFFFFFFFFU) +#define GINT_PORT_ENA_ENA_SHIFT (0U) +/*! ENA - Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the + * port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is + * enabled and contributes to the grouped interrupt. + */ +#define GINT_PORT_ENA_ENA(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_ENA_ENA_SHIFT)) & GINT_PORT_ENA_ENA_MASK) +/*! @} */ + +/* The count of GINT_PORT_ENA */ +#define GINT_PORT_ENA_COUNT (2U) + + +/*! + * @} + */ /* end of group GINT_Register_Masks */ + + +/* GINT - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral GINT0 base address */ + #define GINT0_BASE (0x50002000u) + /** Peripheral GINT0 base address */ + #define GINT0_BASE_NS (0x40002000u) + /** Peripheral GINT0 base pointer */ + #define GINT0 ((GINT_Type *)GINT0_BASE) + /** Peripheral GINT0 base pointer */ + #define GINT0_NS ((GINT_Type *)GINT0_BASE_NS) + /** Peripheral GINT1 base address */ + #define GINT1_BASE (0x50003000u) + /** Peripheral GINT1 base address */ + #define GINT1_BASE_NS (0x40003000u) + /** Peripheral GINT1 base pointer */ + #define GINT1 ((GINT_Type *)GINT1_BASE) + /** Peripheral GINT1 base pointer */ + #define GINT1_NS ((GINT_Type *)GINT1_BASE_NS) + /** Array initializer of GINT peripheral base addresses */ + #define GINT_BASE_ADDRS { GINT0_BASE, GINT1_BASE } + /** Array initializer of GINT peripheral base pointers */ + #define GINT_BASE_PTRS { GINT0, GINT1 } + /** Array initializer of GINT peripheral base addresses */ + #define GINT_BASE_ADDRS_NS { GINT0_BASE_NS, GINT1_BASE_NS } + /** Array initializer of GINT peripheral base pointers */ + #define GINT_BASE_PTRS_NS { GINT0_NS, GINT1_NS } +#else + /** Peripheral GINT0 base address */ + #define GINT0_BASE (0x40002000u) + /** Peripheral GINT0 base pointer */ + #define GINT0 ((GINT_Type *)GINT0_BASE) + /** Peripheral GINT1 base address */ + #define GINT1_BASE (0x40003000u) + /** Peripheral GINT1 base pointer */ + #define GINT1 ((GINT_Type *)GINT1_BASE) + /** Array initializer of GINT peripheral base addresses */ + #define GINT_BASE_ADDRS { GINT0_BASE, GINT1_BASE } + /** Array initializer of GINT peripheral base pointers */ + #define GINT_BASE_PTRS { GINT0, GINT1 } +#endif +/** Interrupt vectors for the GINT peripheral type */ +#define GINT_IRQS { GINT0_IRQn, GINT1_IRQn } + +/*! + * @} + */ /* end of group GINT_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- GPIO Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer + * @{ + */ + +/** GPIO - Register Layout Typedef */ +typedef struct { + __IO uint8_t B[2][32]; /**< Byte pin registers for all port GPIO pins, array offset: 0x0, array step: index*0x20, index2*0x1 */ + uint8_t RESERVED_0[4032]; + __IO uint32_t W[2][32]; /**< Word pin registers for all port GPIO pins, array offset: 0x1000, array step: index*0x80, index2*0x4 */ + uint8_t RESERVED_1[3840]; + __IO uint32_t DIR[2]; /**< Direction registers for all port GPIO pins, array offset: 0x2000, array step: 0x4 */ + uint8_t RESERVED_2[120]; + __IO uint32_t MASK[2]; /**< Mask register for all port GPIO pins, array offset: 0x2080, array step: 0x4 */ + uint8_t RESERVED_3[120]; + __IO uint32_t PIN[2]; /**< Port pin register for all port GPIO pins, array offset: 0x2100, array step: 0x4 */ + uint8_t RESERVED_4[120]; + __IO uint32_t MPIN[2]; /**< Masked port register for all port GPIO pins, array offset: 0x2180, array step: 0x4 */ + uint8_t RESERVED_5[120]; + __IO uint32_t SET[2]; /**< Write: Set register for port. Read: output bits for port, array offset: 0x2200, array step: 0x4 */ + uint8_t RESERVED_6[120]; + __O uint32_t CLR[2]; /**< Clear port for all port GPIO pins, array offset: 0x2280, array step: 0x4 */ + uint8_t RESERVED_7[120]; + __O uint32_t NOT[2]; /**< Toggle port for all port GPIO pins, array offset: 0x2300, array step: 0x4 */ + uint8_t RESERVED_8[120]; + __O uint32_t DIRSET[2]; /**< Set pin direction bits for port, array offset: 0x2380, array step: 0x4 */ + uint8_t RESERVED_9[120]; + __O uint32_t DIRCLR[2]; /**< Clear pin direction bits for port, array offset: 0x2400, array step: 0x4 */ + uint8_t RESERVED_10[120]; + __O uint32_t DIRNOT[2]; /**< Toggle pin direction bits for port, array offset: 0x2480, array step: 0x4 */ +} GPIO_Type; + +/* ---------------------------------------------------------------------------- + -- GPIO Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPIO_Register_Masks GPIO Register Masks + * @{ + */ + +/*! @name B - Byte pin registers for all port GPIO pins */ +/*! @{ */ + +#define GPIO_B_PBYTE_MASK (0x1U) +#define GPIO_B_PBYTE_SHIFT (0U) +/*! PBYTE - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, + * except that pins configured as analog I/O always read as 0. One register for each port pin. + * Supported pins depends on the specific device and package. Write: loads the pin's output bit. + * One register for each port pin. Supported pins depends on the specific device and package. + */ +#define GPIO_B_PBYTE(x) (((uint8_t)(((uint8_t)(x)) << GPIO_B_PBYTE_SHIFT)) & GPIO_B_PBYTE_MASK) +/*! @} */ + +/* The count of GPIO_B */ +#define GPIO_B_COUNT (2U) + +/* The count of GPIO_B */ +#define GPIO_B_COUNT2 (32U) + +/*! @name W - Word pin registers for all port GPIO pins */ +/*! @{ */ + +#define GPIO_W_PWORD_MASK (0xFFFFFFFFU) +#define GPIO_W_PWORD_SHIFT (0U) +/*! PWORD - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is + * HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be + * read. Writing any value other than 0 will set the output bit. One register for each port pin. + * Supported pins depends on the specific device and package. + */ +#define GPIO_W_PWORD(x) (((uint32_t)(((uint32_t)(x)) << GPIO_W_PWORD_SHIFT)) & GPIO_W_PWORD_MASK) +/*! @} */ + +/* The count of GPIO_W */ +#define GPIO_W_COUNT (2U) + +/* The count of GPIO_W */ +#define GPIO_W_COUNT2 (32U) + +/*! @name DIR - Direction registers for all port GPIO pins */ +/*! @{ */ + +#define GPIO_DIR_DIRP_MASK (0xFFFFFFFFU) +#define GPIO_DIR_DIRP_SHIFT (0U) +/*! DIRP - Selects pin direction for pin PIOm_n (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported + * pins depends on the specific device and package. 0 = input. 1 = output. + */ +#define GPIO_DIR_DIRP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP_SHIFT)) & GPIO_DIR_DIRP_MASK) +/*! @} */ + +/* The count of GPIO_DIR */ +#define GPIO_DIR_COUNT (2U) + +/*! @name MASK - Mask register for all port GPIO pins */ +/*! @{ */ + +#define GPIO_MASK_MASKP_MASK (0xFFFFFFFFU) +#define GPIO_MASK_MASKP_SHIFT (0U) +/*! MASKP - Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = + * PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package.0 = + * Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit + * not affected. + */ +#define GPIO_MASK_MASKP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP_SHIFT)) & GPIO_MASK_MASKP_MASK) +/*! @} */ + +/* The count of GPIO_MASK */ +#define GPIO_MASK_COUNT (2U) + +/*! @name PIN - Port pin register for all port GPIO pins */ +/*! @{ */ + +#define GPIO_PIN_PORT_MASK (0xFFFFFFFFU) +#define GPIO_PIN_PORT_SHIFT (0U) +/*! PORT - Reads pin states or loads output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported + * pins depends on the specific device and package. 0 = Read: pin is low; write: clear output bit. + * 1 = Read: pin is high; write: set output bit. + */ +#define GPIO_PIN_PORT(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT_SHIFT)) & GPIO_PIN_PORT_MASK) +/*! @} */ + +/* The count of GPIO_PIN */ +#define GPIO_PIN_COUNT (2U) + +/*! @name MPIN - Masked port register for all port GPIO pins */ +/*! @{ */ + +#define GPIO_MPIN_MPORTP_MASK (0xFFFFFFFFU) +#define GPIO_MPIN_MPORTP_SHIFT (0U) +/*! MPORTP - Masked port register (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on + * the specific device and package. 0 = Read: pin is LOW and/or the corresponding bit in the MASK + * register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 + * = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit + * if the corresponding bit in the MASK register is 0. + */ +#define GPIO_MPIN_MPORTP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP_SHIFT)) & GPIO_MPIN_MPORTP_MASK) +/*! @} */ + +/* The count of GPIO_MPIN */ +#define GPIO_MPIN_COUNT (2U) + +/*! @name SET - Write: Set register for port. Read: output bits for port */ +/*! @{ */ + +#define GPIO_SET_SETP_MASK (0xFFFFFFFFU) +#define GPIO_SET_SETP_SHIFT (0U) +/*! SETP - Read or set output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on + * the specific device and package. 0 = Read: output bit: write: no operation. 1 = Read: output + * bit; write: set output bit. + */ +#define GPIO_SET_SETP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_SET_SETP_SHIFT)) & GPIO_SET_SETP_MASK) +/*! @} */ + +/* The count of GPIO_SET */ +#define GPIO_SET_COUNT (2U) + +/*! @name CLR - Clear port for all port GPIO pins */ +/*! @{ */ + +#define GPIO_CLR_CLRP_MASK (0xFFFFFFFFU) +#define GPIO_CLR_CLRP_SHIFT (0U) +/*! CLRP - Clear output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the + * specific device and package. 0 = No operation. 1 = Clear output bit. + */ +#define GPIO_CLR_CLRP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP_SHIFT)) & GPIO_CLR_CLRP_MASK) +/*! @} */ + +/* The count of GPIO_CLR */ +#define GPIO_CLR_COUNT (2U) + +/*! @name NOT - Toggle port for all port GPIO pins */ +/*! @{ */ + +#define GPIO_NOT_NOTP_MASK (0xFFFFFFFFU) +#define GPIO_NOT_NOTP_SHIFT (0U) +/*! NOTP - Toggle output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the + * specific device and package. 0 = no operation. 1 = Toggle output bit. + */ +#define GPIO_NOT_NOTP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP_SHIFT)) & GPIO_NOT_NOTP_MASK) +/*! @} */ + +/* The count of GPIO_NOT */ +#define GPIO_NOT_COUNT (2U) + +/*! @name DIRSET - Set pin direction bits for port */ +/*! @{ */ + +#define GPIO_DIRSET_DIRSETP_MASK (0xFFFFFFFFU) +#define GPIO_DIRSET_DIRSETP_SHIFT (0U) +/*! DIRSETP - Set direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on + * the specific device and package. 0 = No operation. 1 = Set direction bit. + */ +#define GPIO_DIRSET_DIRSETP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP_SHIFT)) & GPIO_DIRSET_DIRSETP_MASK) +/*! @} */ + +/* The count of GPIO_DIRSET */ +#define GPIO_DIRSET_COUNT (2U) + +/*! @name DIRCLR - Clear pin direction bits for port */ +/*! @{ */ + +#define GPIO_DIRCLR_DIRCLRP_MASK (0xFFFFFFFFU) +#define GPIO_DIRCLR_DIRCLRP_SHIFT (0U) +/*! DIRCLRP - Clear direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on + * the specific device and package. 0 = No operation. 1 = Clear direction bit. + */ +#define GPIO_DIRCLR_DIRCLRP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP_SHIFT)) & GPIO_DIRCLR_DIRCLRP_MASK) +/*! @} */ + +/* The count of GPIO_DIRCLR */ +#define GPIO_DIRCLR_COUNT (2U) + +/*! @name DIRNOT - Toggle pin direction bits for port */ +/*! @{ */ + +#define GPIO_DIRNOT_DIRNOTP_MASK (0xFFFFFFFFU) +#define GPIO_DIRNOT_DIRNOTP_SHIFT (0U) +/*! DIRNOTP - Toggle direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends + * on the specific device and package. 0 = no operation. 1 = Toggle direction bit. + */ +#define GPIO_DIRNOT_DIRNOTP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRNOT_DIRNOTP_SHIFT)) & GPIO_DIRNOT_DIRNOTP_MASK) +/*! @} */ + +/* The count of GPIO_DIRNOT */ +#define GPIO_DIRNOT_COUNT (2U) + + +/*! + * @} + */ /* end of group GPIO_Register_Masks */ + + +/* GPIO - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral GPIO base address */ + #define GPIO_BASE (0x5008C000u) + /** Peripheral GPIO base address */ + #define GPIO_BASE_NS (0x4008C000u) + /** Peripheral GPIO base pointer */ + #define GPIO ((GPIO_Type *)GPIO_BASE) + /** Peripheral GPIO base pointer */ + #define GPIO_NS ((GPIO_Type *)GPIO_BASE_NS) + /** Peripheral SECGPIO base address */ + #define SECGPIO_BASE (0x500A8000u) + /** Peripheral SECGPIO base address */ + #define SECGPIO_BASE_NS (0x400A8000u) + /** Peripheral SECGPIO base pointer */ + #define SECGPIO ((GPIO_Type *)SECGPIO_BASE) + /** Peripheral SECGPIO base pointer */ + #define SECGPIO_NS ((GPIO_Type *)SECGPIO_BASE_NS) + /** Array initializer of GPIO peripheral base addresses */ + #define GPIO_BASE_ADDRS { GPIO_BASE, SECGPIO_BASE } + /** Array initializer of GPIO peripheral base pointers */ + #define GPIO_BASE_PTRS { GPIO, SECGPIO } + /** Array initializer of GPIO peripheral base addresses */ + #define GPIO_BASE_ADDRS_NS { GPIO_BASE_NS, SECGPIO_BASE_NS } + /** Array initializer of GPIO peripheral base pointers */ + #define GPIO_BASE_PTRS_NS { GPIO_NS, SECGPIO_NS } +#else + /** Peripheral GPIO base address */ + #define GPIO_BASE (0x4008C000u) + /** Peripheral GPIO base pointer */ + #define GPIO ((GPIO_Type *)GPIO_BASE) + /** Peripheral SECGPIO base address */ + #define SECGPIO_BASE (0x400A8000u) + /** Peripheral SECGPIO base pointer */ + #define SECGPIO ((GPIO_Type *)SECGPIO_BASE) + /** Array initializer of GPIO peripheral base addresses */ + #define GPIO_BASE_ADDRS { GPIO_BASE, SECGPIO_BASE } + /** Array initializer of GPIO peripheral base pointers */ + #define GPIO_BASE_PTRS { GPIO, SECGPIO } +#endif + +/*! + * @} + */ /* end of group GPIO_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- HASHCRYPT Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup HASHCRYPT_Peripheral_Access_Layer HASHCRYPT Peripheral Access Layer + * @{ + */ + +/** HASHCRYPT - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL; /**< Control register to enable and operate Hash and Crypto, offset: 0x0 */ + __IO uint32_t STATUS; /**< Indicates status of Hash peripheral., offset: 0x4 */ + __IO uint32_t INTENSET; /**< Write 1 to enable interrupts; reads back with which are set., offset: 0x8 */ + __IO uint32_t INTENCLR; /**< Write 1 to clear interrupts., offset: 0xC */ + __IO uint32_t MEMCTRL; /**< Setup Master to access memory (if available), offset: 0x10 */ + __IO uint32_t MEMADDR; /**< Address to start memory access from (if available)., offset: 0x14 */ + uint8_t RESERVED_0[8]; + __O uint32_t INDATA; /**< Input of 16 words at a time to load up buffer., offset: 0x20 */ + __O uint32_t ALIAS[7]; /**< Aliases to allow writing words in a burst., array offset: 0x24, array step: 0x4 */ + __I uint32_t DIGEST0[8]; /**< Result digest (when status says so): • Is 1st 5 words if SHA1 used • Is all 8 words if SHA2 used • Is all 8 words if crypto or SHA512, array offset: 0x40, array step: 0x4 */ + uint8_t RESERVED_1[32]; + __IO uint32_t CRYPTCFG; /**< Crypto settings for AES and Salsa and ChaCha, offset: 0x80 */ + __I uint32_t CONFIG; /**< Returns the configuration of this block in this chip - indicates what services are available., offset: 0x84 */ + uint8_t RESERVED_2[4]; + __IO uint32_t LOCK; /**< Lock register allows locking to the current security level or unlocking by the lock holding level., offset: 0x8C */ + __O uint32_t MASK[4]; /**< Allows Application to write a random mask for ICB use. Normally only a new one on each system reset (including power up)., array offset: 0x90, array step: 0x4 */ + __O uint32_t RELOAD[8]; /**< The WO digest-reload registers may be written with a saved Hash digest, to allow continuation from where left off. These registers may only be written if the Reload field in CTRL is 1. If SHA1, only the 1st 5 are used., array offset: 0xA0, array step: 0x4 */ + uint8_t RESERVED_3[16]; + __O uint32_t PRNG_SEED; /**< PRNG random input value used as an entropy source, offset: 0xD0 */ + uint8_t RESERVED_4[4]; + __I uint32_t PRNG_OUT; /**< Provide random number., offset: 0xD8 */ +} HASHCRYPT_Type; + +/* ---------------------------------------------------------------------------- + -- HASHCRYPT Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup HASHCRYPT_Register_Masks HASHCRYPT Register Masks + * @{ + */ + +/*! @name CTRL - Control register to enable and operate Hash and Crypto */ +/*! @{ */ + +#define HASHCRYPT_CTRL_MODE_MASK (0x7U) +#define HASHCRYPT_CTRL_MODE_SHIFT (0U) +/*! Mode - The operational mode to use, or 0 if none. Note that the CONFIG register will indicate if + * specific modes beyond SHA1 and SHA2-256 are available. + * 0b000..Disabled + * 0b001..SHA1 is enabled + * 0b010..SHA2-256 is enabled + * 0b100..AES if available (see also CRYPTCFG register for more controls) + * 0b101..Reserved + */ +#define HASHCRYPT_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CTRL_MODE_SHIFT)) & HASHCRYPT_CTRL_MODE_MASK) + +#define HASHCRYPT_CTRL_NEW_HASH_MASK (0x10U) +#define HASHCRYPT_CTRL_NEW_HASH_SHIFT (4U) +/*! New_Hash - Written with 1 when starting a new Hash/Crypto. It self clears. Note that the WAITING + * Status bit will clear for a cycle during the initialization from New=1. + * 0b1..Starts a new Hash/Crypto and initializes the Digest/Result. + */ +#define HASHCRYPT_CTRL_NEW_HASH(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CTRL_NEW_HASH_SHIFT)) & HASHCRYPT_CTRL_NEW_HASH_MASK) + +#define HASHCRYPT_CTRL_RELOAD_MASK (0x20U) +#define HASHCRYPT_CTRL_RELOAD_SHIFT (5U) +/*! Reload - If 1, allows the SHA RELOAD registers to be used. This is used to save a partial Hash + * Digest (e.g. when need to run AES) and then reload it later for continuation. + * 0b1..Allow RELOAD registers to be used. + */ +#define HASHCRYPT_CTRL_RELOAD(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CTRL_RELOAD_SHIFT)) & HASHCRYPT_CTRL_RELOAD_MASK) + +#define HASHCRYPT_CTRL_DMA_I_MASK (0x100U) +#define HASHCRYPT_CTRL_DMA_I_SHIFT (8U) +/*! DMA_I - Written with 1 to use DMA to fill INDATA. If Hash, will request from DMA for 16 words + * and then will process the Hash. If Cryptographic, it will load as many words as needed, + * including key if not already loaded. It will then request again. Normal model is that the DMA + * interrupts the processor when its length expires. Note that if the processor will write the key and + * optionally IV, it should not enable this until it has done so. Otherwise, the DMA will be + * expected to load those for the 1st block (when needed). + * 0b0..DMA is not used. Processor writes the necessary words when WAITING is set (interrupts), unless AHB Master is used. + * 0b1..DMA will push in the data. + */ +#define HASHCRYPT_CTRL_DMA_I(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CTRL_DMA_I_SHIFT)) & HASHCRYPT_CTRL_DMA_I_MASK) + +#define HASHCRYPT_CTRL_DMA_O_MASK (0x200U) +#define HASHCRYPT_CTRL_DMA_O_SHIFT (9U) +/*! DMA_O - Written to 1 to use DMA to drain the digest/output. If both DMA_I and DMA_O are set, the + * DMA has to know to switch direction and the locations. This can be used for crypto uses. + * 0b0..DMA is not used. Processor reads the digest/output in response to DIGEST interrupt. + */ +#define HASHCRYPT_CTRL_DMA_O(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CTRL_DMA_O_SHIFT)) & HASHCRYPT_CTRL_DMA_O_MASK) + +#define HASHCRYPT_CTRL_HASHSWPB_MASK (0x1000U) +#define HASHCRYPT_CTRL_HASHSWPB_SHIFT (12U) +/*! HASHSWPB - If 1, will swap bytes in the word for SHA hashing. The default is byte order (so LSB + * is 1st byte) but this allows swapping to MSB is 1st such as is shown in SHS spec. For + * cryptographic swapping, see the CRYPTCFG register. + */ +#define HASHCRYPT_CTRL_HASHSWPB(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CTRL_HASHSWPB_SHIFT)) & HASHCRYPT_CTRL_HASHSWPB_MASK) + +#define HASHCRYPT_CTRL_AESFLUSH_MASK (0x2000U) +#define HASHCRYPT_CTRL_AESFLUSH_SHIFT (13U) +/*! AESFLUSH - Flushes the AES engine registers. This bit self clears. + * 0b1..Flush the AES engine registers. + * 0b0..Do not flush the AES engine registers. + */ +#define HASHCRYPT_CTRL_AESFLUSH(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CTRL_AESFLUSH_SHIFT)) & HASHCRYPT_CTRL_AESFLUSH_MASK) +/*! @} */ + +/*! @name STATUS - Indicates status of Hash peripheral. */ +/*! @{ */ + +#define HASHCRYPT_STATUS_WAITING_MASK (0x1U) +#define HASHCRYPT_STATUS_WAITING_SHIFT (0U) +/*! WAITING - If 1, the block is waiting for more data to process. + * 0b0..Not waiting for data - may be disabled or may be busy. Note that for cryptographic uses, this is not set + * if IsLast is set nor will it set until at least 1 word is read of the output. + * 0b1..Waiting for data to be written in (16 words) + */ +#define HASHCRYPT_STATUS_WAITING(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_STATUS_WAITING_SHIFT)) & HASHCRYPT_STATUS_WAITING_MASK) + +#define HASHCRYPT_STATUS_DIGEST_MASK (0x2U) +#define HASHCRYPT_STATUS_DIGEST_SHIFT (1U) +/*! DIGEST - For Hash, if 1 then a DIGEST is ready and waiting and there is no active next block + * already started. For Cryptographic uses, this will be set for each block processed, indicating + * OUTDATA (and OUTDATA2 if larger output) contains the next value to read out. This is cleared + * when any data is written, when New is written, for Cryptographic uses when the last word is read + * out, or when the block is disabled. + * 0b0..No Digest is ready + * 0b1..Digest is ready. Application may read it or may write more data + */ +#define HASHCRYPT_STATUS_DIGEST(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_STATUS_DIGEST_SHIFT)) & HASHCRYPT_STATUS_DIGEST_MASK) + +#define HASHCRYPT_STATUS_ERROR_MASK (0x4U) +#define HASHCRYPT_STATUS_ERROR_SHIFT (2U) +/*! ERROR - If 1, an error occurred. For normal uses, this is due to an attempted overrun: INDATA + * was written when it was not appropriate. For Master cases, this is an AHB bus error; the COUNT + * field will indicate which block it was on. + * 0b0..No error. + * 0b1..An error occurred since last cleared (written 1 to clear). + */ +#define HASHCRYPT_STATUS_ERROR(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_STATUS_ERROR_SHIFT)) & HASHCRYPT_STATUS_ERROR_MASK) + +#define HASHCRYPT_STATUS_FAULT_MASK (0x8U) +#define HASHCRYPT_STATUS_FAULT_SHIFT (3U) +/*! FAULT - Indicates if an AES or PRNG fault has occurred + * 0b0..No AES or PRNG fault has occurred. + * 0b1..An AES or PRNG fault has occurred. + */ +#define HASHCRYPT_STATUS_FAULT(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_STATUS_FAULT_SHIFT)) & HASHCRYPT_STATUS_FAULT_MASK) + +#define HASHCRYPT_STATUS_NEEDKEY_MASK (0x10U) +#define HASHCRYPT_STATUS_NEEDKEY_SHIFT (4U) +/*! NEEDKEY - Indicates the block wants the key to be written in (set along with WAITING) + * 0b0..No Key is needed and writes will not be treated as Key + * 0b1..Key is needed and INDATA/ALIAS will be accepted as Key. Will also set WAITING. + */ +#define HASHCRYPT_STATUS_NEEDKEY(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_STATUS_NEEDKEY_SHIFT)) & HASHCRYPT_STATUS_NEEDKEY_MASK) + +#define HASHCRYPT_STATUS_NEEDIV_MASK (0x20U) +#define HASHCRYPT_STATUS_NEEDIV_SHIFT (5U) +/*! NEEDIV - Indicates the block wants an IV/NONE to be written in (set along with WAITING) + * 0b0..No IV/Nonce is needed, either because written already or because not needed. + * 0b1..IV/Nonce is needed and INDATA/ALIAS will be accepted as IV/Nonce. Will also set WAITING. + */ +#define HASHCRYPT_STATUS_NEEDIV(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_STATUS_NEEDIV_SHIFT)) & HASHCRYPT_STATUS_NEEDIV_MASK) + +#define HASHCRYPT_STATUS_AESFAULT_MASK (0x100U) +#define HASHCRYPT_STATUS_AESFAULT_SHIFT (8U) +/*! AESFAULT - AES fault status + * 0b0..No AES fault has occurred. + * 0b1..An AES fault has occurred. + */ +#define HASHCRYPT_STATUS_AESFAULT(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_STATUS_AESFAULT_SHIFT)) & HASHCRYPT_STATUS_AESFAULT_MASK) + +#define HASHCRYPT_STATUS_PRNGFAULT_MASK (0x200U) +#define HASHCRYPT_STATUS_PRNGFAULT_SHIFT (9U) +/*! PRNGFAULT - PRNG fault status + * 0b0..No PRNG fault has occurred. + * 0b1..A PRNG fault has occurred. + */ +#define HASHCRYPT_STATUS_PRNGFAULT(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_STATUS_PRNGFAULT_SHIFT)) & HASHCRYPT_STATUS_PRNGFAULT_MASK) +/*! @} */ + +/*! @name INTENSET - Write 1 to enable interrupts; reads back with which are set. */ +/*! @{ */ + +#define HASHCRYPT_INTENSET_WAITING_MASK (0x1U) +#define HASHCRYPT_INTENSET_WAITING_SHIFT (0U) +/*! WAITING - Indicates if should interrupt when waiting for data input. + * 0b0..Will not interrupt when waiting. + * 0b1..Will interrupt when waiting + */ +#define HASHCRYPT_INTENSET_WAITING(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INTENSET_WAITING_SHIFT)) & HASHCRYPT_INTENSET_WAITING_MASK) + +#define HASHCRYPT_INTENSET_DIGEST_MASK (0x2U) +#define HASHCRYPT_INTENSET_DIGEST_SHIFT (1U) +/*! DIGEST - Indicates if should interrupt when Digest (or Outdata) is ready (completed a hash/crypto or completed a full sequence). + * 0b0..Will not interrupt when Digest is ready + * 0b1..Will interrupt when Digest is ready. Interrupt cleared by writing more data, starting a new Hash, or disabling (done). + */ +#define HASHCRYPT_INTENSET_DIGEST(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INTENSET_DIGEST_SHIFT)) & HASHCRYPT_INTENSET_DIGEST_MASK) + +#define HASHCRYPT_INTENSET_ERROR_MASK (0x4U) +#define HASHCRYPT_INTENSET_ERROR_SHIFT (2U) +/*! ERROR - Indicates if should interrupt on an ERROR (as defined in Status) + * 0b0..Will not interrupt on Error. + * 0b1..Will interrupt on Error (until cleared). + */ +#define HASHCRYPT_INTENSET_ERROR(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INTENSET_ERROR_SHIFT)) & HASHCRYPT_INTENSET_ERROR_MASK) + +#define HASHCRYPT_INTENSET_FAULT_MASK (0x8U) +#define HASHCRYPT_INTENSET_FAULT_SHIFT (3U) +/*! FAULT - Indicates if should interrupt on an AES or PRNG fault as indicated in the STATUS register + * 0b0..No interrupt on an AES or PRNG fault + * 0b1..Interrupt on an AES or PRNG fault + */ +#define HASHCRYPT_INTENSET_FAULT(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INTENSET_FAULT_SHIFT)) & HASHCRYPT_INTENSET_FAULT_MASK) +/*! @} */ + +/*! @name INTENCLR - Write 1 to clear interrupts. */ +/*! @{ */ + +#define HASHCRYPT_INTENCLR_WAITING_MASK (0x1U) +#define HASHCRYPT_INTENCLR_WAITING_SHIFT (0U) +/*! WAITING - Write 1 to clear mask. + */ +#define HASHCRYPT_INTENCLR_WAITING(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INTENCLR_WAITING_SHIFT)) & HASHCRYPT_INTENCLR_WAITING_MASK) + +#define HASHCRYPT_INTENCLR_DIGEST_MASK (0x2U) +#define HASHCRYPT_INTENCLR_DIGEST_SHIFT (1U) +/*! DIGEST - Write 1 to clear mask. + */ +#define HASHCRYPT_INTENCLR_DIGEST(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INTENCLR_DIGEST_SHIFT)) & HASHCRYPT_INTENCLR_DIGEST_MASK) + +#define HASHCRYPT_INTENCLR_ERROR_MASK (0x4U) +#define HASHCRYPT_INTENCLR_ERROR_SHIFT (2U) +/*! ERROR - Write 1 to clear mask. + */ +#define HASHCRYPT_INTENCLR_ERROR(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INTENCLR_ERROR_SHIFT)) & HASHCRYPT_INTENCLR_ERROR_MASK) + +#define HASHCRYPT_INTENCLR_FAULT_MASK (0x8U) +#define HASHCRYPT_INTENCLR_FAULT_SHIFT (3U) +/*! FAULT - Write 1 to clear mask. + */ +#define HASHCRYPT_INTENCLR_FAULT(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INTENCLR_FAULT_SHIFT)) & HASHCRYPT_INTENCLR_FAULT_MASK) +/*! @} */ + +/*! @name MEMCTRL - Setup Master to access memory (if available) */ +/*! @{ */ + +#define HASHCRYPT_MEMCTRL_MASTER_MASK (0x1U) +#define HASHCRYPT_MEMCTRL_MASTER_SHIFT (0U) +/*! MASTER - Enables mastering. + * 0b0..Mastering is not used and the normal DMA or Interrupt based model is used with INDATA. + * 0b1..Mastering is enabled and DMA and INDATA should not be used. + */ +#define HASHCRYPT_MEMCTRL_MASTER(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_MEMCTRL_MASTER_SHIFT)) & HASHCRYPT_MEMCTRL_MASTER_MASK) + +#define HASHCRYPT_MEMCTRL_COUNT_MASK (0x7FF0000U) +#define HASHCRYPT_MEMCTRL_COUNT_SHIFT (16U) +/*! COUNT - Number of 512-bit (128-bit if AES, except 1st block which may include key and IV) blocks + * to copy starting at MEMADDR. This register will decrement after each block is copied, ending + * in 0. For Hash, the DIGEST interrupt will occur when it reaches 0. Fro AES, the DIGEST/OUTDATA + * interrupt will occur on ever block. If a bus error occurs, it will stop with this field set + * to the block that failed. 0:Done - nothing to process. 1 to 2K: Number of 512-bit (or 128bit) + * blocks to hash. + */ +#define HASHCRYPT_MEMCTRL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_MEMCTRL_COUNT_SHIFT)) & HASHCRYPT_MEMCTRL_COUNT_MASK) +/*! @} */ + +/*! @name MEMADDR - Address to start memory access from (if available). */ +/*! @{ */ + +#define HASHCRYPT_MEMADDR_BASE_MASK (0xFFFFFFFFU) +#define HASHCRYPT_MEMADDR_BASE_SHIFT (0U) +/*! BASE - Address base to start copying from, word aligned (so bits 1:0 must be 0). This field will + * advance as it processes the words. If it fails with a bus error, the register will contain + * the failing word. N:Address in Flash or RAM space; RAM only as mapped in this part. May also be + * able to address SPIFI. + */ +#define HASHCRYPT_MEMADDR_BASE(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_MEMADDR_BASE_SHIFT)) & HASHCRYPT_MEMADDR_BASE_MASK) +/*! @} */ + +/*! @name INDATA - Input of 16 words at a time to load up buffer. */ +/*! @{ */ + +#define HASHCRYPT_INDATA_DATA_MASK (0xFFFFFFFFU) +#define HASHCRYPT_INDATA_DATA_SHIFT (0U) +/*! DATA - Write next word in little-endian form. The hash requires big endian word data, but this + * block swaps the bytes automatically. That is, SHA assumes the data coming in is treated as + * bytes (e.g. "abcd") and since the ARM core will treat "abcd" as a word as 0x64636261, the block + * will swap the word to restore into big endian. + */ +#define HASHCRYPT_INDATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INDATA_DATA_SHIFT)) & HASHCRYPT_INDATA_DATA_MASK) +/*! @} */ + +/*! @name ALIAS - Aliases to allow writing words in a burst. */ +/*! @{ */ + +#define HASHCRYPT_ALIAS_DATA_MASK (0xFFFFFFFFU) +#define HASHCRYPT_ALIAS_DATA_SHIFT (0U) +/*! DATA - Write next word in little-endian form. The hash requires big endian word data, but this + * block swaps the bytes automatically. That is, SHA assumes the data coming in is treated as + * bytes (e.g. "abcd") and since the ARM core will treat "abcd" as a word as 0x64636261, the block + * will swap the word to restore into big endian. + */ +#define HASHCRYPT_ALIAS_DATA(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_ALIAS_DATA_SHIFT)) & HASHCRYPT_ALIAS_DATA_MASK) +/*! @} */ + +/* The count of HASHCRYPT_ALIAS */ +#define HASHCRYPT_ALIAS_COUNT (7U) + +/*! @name DIGEST0 - Result digest (when status says so): • Is 1st 5 words if SHA1 used • Is all 8 words if SHA2 used • Is all 8 words if crypto or SHA512 */ +/*! @{ */ + +#define HASHCRYPT_DIGEST0_DIGEST_MASK (0xFFFFFFFFU) +#define HASHCRYPT_DIGEST0_DIGEST_SHIFT (0U) +/*! DIGEST - One word of the Digest or output. Note that only 1st 4 are populated for AES and 1st 5 are populated for SHA1. + */ +#define HASHCRYPT_DIGEST0_DIGEST(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_DIGEST0_DIGEST_SHIFT)) & HASHCRYPT_DIGEST0_DIGEST_MASK) +/*! @} */ + +/* The count of HASHCRYPT_DIGEST0 */ +#define HASHCRYPT_DIGEST0_COUNT (8U) + +/*! @name CRYPTCFG - Crypto settings for AES and Salsa and ChaCha */ +/*! @{ */ + +#define HASHCRYPT_CRYPTCFG_MSW1ST_OUT_MASK (0x1U) +#define HASHCRYPT_CRYPTCFG_MSW1ST_OUT_SHIFT (0U) +/*! MSW1ST_OUT - If 1, OUTDATA0 will be read Most significant word 1st for AES. Else it will be read + * in normal little endian - Least significant word 1st. Note: only if allowed by configuration. + */ +#define HASHCRYPT_CRYPTCFG_MSW1ST_OUT(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_MSW1ST_OUT_SHIFT)) & HASHCRYPT_CRYPTCFG_MSW1ST_OUT_MASK) + +#define HASHCRYPT_CRYPTCFG_SWAPKEY_MASK (0x2U) +#define HASHCRYPT_CRYPTCFG_SWAPKEY_SHIFT (1U) +/*! SWAPKEY - If 1, will Swap the key input (bytes in each word). + */ +#define HASHCRYPT_CRYPTCFG_SWAPKEY(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_SWAPKEY_SHIFT)) & HASHCRYPT_CRYPTCFG_SWAPKEY_MASK) + +#define HASHCRYPT_CRYPTCFG_SWAPDAT_MASK (0x4U) +#define HASHCRYPT_CRYPTCFG_SWAPDAT_SHIFT (2U) +/*! SWAPDAT - If 1, will SWAP the data and IV inputs (bytes in each word). + */ +#define HASHCRYPT_CRYPTCFG_SWAPDAT(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_SWAPDAT_SHIFT)) & HASHCRYPT_CRYPTCFG_SWAPDAT_MASK) + +#define HASHCRYPT_CRYPTCFG_MSW1ST_MASK (0x8U) +#define HASHCRYPT_CRYPTCFG_MSW1ST_SHIFT (3U) +/*! MSW1ST - If 1, load of key, IV, and data is MSW 1st for AES. Else, the words are little endian. + * Note: only if allowed by configuration. + */ +#define HASHCRYPT_CRYPTCFG_MSW1ST(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_MSW1ST_SHIFT)) & HASHCRYPT_CRYPTCFG_MSW1ST_MASK) + +#define HASHCRYPT_CRYPTCFG_AESMODE_MASK (0x30U) +#define HASHCRYPT_CRYPTCFG_AESMODE_SHIFT (4U) +/*! AESMODE - AES Cipher mode to use if plain AES + * 0b00..ECB - used as is + * 0b01..CBC mode (see details on IV/nonce) + * 0b10..CTR mode (see details on IV/nonce). See also AESCTRPOS. + * 0b11..reserved + */ +#define HASHCRYPT_CRYPTCFG_AESMODE(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_AESMODE_SHIFT)) & HASHCRYPT_CRYPTCFG_AESMODE_MASK) + +#define HASHCRYPT_CRYPTCFG_AESDECRYPT_MASK (0x40U) +#define HASHCRYPT_CRYPTCFG_AESDECRYPT_SHIFT (6U) +/*! AESDECRYPT - AES ECB direction. Only encryption used if CTR mode or manual modes such as CFB + * 0b0..Encrypt + * 0b1..Decrypt + */ +#define HASHCRYPT_CRYPTCFG_AESDECRYPT(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_AESDECRYPT_SHIFT)) & HASHCRYPT_CRYPTCFG_AESDECRYPT_MASK) + +#define HASHCRYPT_CRYPTCFG_AESSECRET_MASK (0x80U) +#define HASHCRYPT_CRYPTCFG_AESSECRET_SHIFT (7U) +/*! AESSECRET - Selects the Hidden Secret key vs. User key, if provided. If security levels are + * used, only the highest level is permitted to select this. + * 0b0..User key provided in normal way + * 0b1..Secret key provided in hidden way by HW + */ +#define HASHCRYPT_CRYPTCFG_AESSECRET(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_AESSECRET_SHIFT)) & HASHCRYPT_CRYPTCFG_AESSECRET_MASK) + +#define HASHCRYPT_CRYPTCFG_AESKEYSZ_MASK (0x300U) +#define HASHCRYPT_CRYPTCFG_AESKEYSZ_SHIFT (8U) +/*! AESKEYSZ - Sets the AES key size + * 0b00..128 bit key + * 0b01..192 bit key + * 0b10..256 bit key + * 0b11..reserved + */ +#define HASHCRYPT_CRYPTCFG_AESKEYSZ(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_AESKEYSZ_SHIFT)) & HASHCRYPT_CRYPTCFG_AESKEYSZ_MASK) + +#define HASHCRYPT_CRYPTCFG_AESCTRPOS_MASK (0x1C00U) +#define HASHCRYPT_CRYPTCFG_AESCTRPOS_SHIFT (10U) +/*! AESCTRPOS - Halfword position of 16b counter in IV if AESMODE is CTR (position is fixed for + * Salsa and ChaCha). Only supports 16b counter, so application must control any additional bytes if + * using more. The 16-bit counter is read from the IV and incremented by 1 each time. Any other + * use CTR should use ECB directly and do its own XOR and so on. + */ +#define HASHCRYPT_CRYPTCFG_AESCTRPOS(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_AESCTRPOS_SHIFT)) & HASHCRYPT_CRYPTCFG_AESCTRPOS_MASK) + +#define HASHCRYPT_CRYPTCFG_STREAMLAST_MASK (0x10000U) +#define HASHCRYPT_CRYPTCFG_STREAMLAST_SHIFT (16U) +/*! STREAMLAST - Is 1 if last stream block. If not 1, then the engine will compute the next "hash". + */ +#define HASHCRYPT_CRYPTCFG_STREAMLAST(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_STREAMLAST_SHIFT)) & HASHCRYPT_CRYPTCFG_STREAMLAST_MASK) +/*! @} */ + +/*! @name CONFIG - Returns the configuration of this block in this chip - indicates what services are available. */ +/*! @{ */ + +#define HASHCRYPT_CONFIG_DUAL_MASK (0x1U) +#define HASHCRYPT_CONFIG_DUAL_SHIFT (0U) +/*! DUAL - 1 if 2 x 512 bit buffers, 0 if only 1 x 512 bit + */ +#define HASHCRYPT_CONFIG_DUAL(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_DUAL_SHIFT)) & HASHCRYPT_CONFIG_DUAL_MASK) + +#define HASHCRYPT_CONFIG_DMA_MASK (0x2U) +#define HASHCRYPT_CONFIG_DMA_SHIFT (1U) +/*! DMA - 1 if DMA is connected + */ +#define HASHCRYPT_CONFIG_DMA(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_DMA_SHIFT)) & HASHCRYPT_CONFIG_DMA_MASK) + +#define HASHCRYPT_CONFIG_AHB_MASK (0x8U) +#define HASHCRYPT_CONFIG_AHB_SHIFT (3U) +/*! AHB - 1 if AHB Master is enabled + */ +#define HASHCRYPT_CONFIG_AHB(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_AHB_SHIFT)) & HASHCRYPT_CONFIG_AHB_MASK) + +#define HASHCRYPT_CONFIG_AES_MASK (0x40U) +#define HASHCRYPT_CONFIG_AES_SHIFT (6U) +/*! AES - 1 if AES 128 included + */ +#define HASHCRYPT_CONFIG_AES(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_AES_SHIFT)) & HASHCRYPT_CONFIG_AES_MASK) + +#define HASHCRYPT_CONFIG_AESKEY_MASK (0x80U) +#define HASHCRYPT_CONFIG_AESKEY_SHIFT (7U) +/*! AESKEY - 1 if AES 192 and 256 also included + */ +#define HASHCRYPT_CONFIG_AESKEY(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_AESKEY_SHIFT)) & HASHCRYPT_CONFIG_AESKEY_MASK) + +#define HASHCRYPT_CONFIG_SECRET_MASK (0x100U) +#define HASHCRYPT_CONFIG_SECRET_SHIFT (8U) +/*! SECRET - 1 if AES Secret key available + */ +#define HASHCRYPT_CONFIG_SECRET(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_SECRET_SHIFT)) & HASHCRYPT_CONFIG_SECRET_MASK) +/*! @} */ + +/*! @name LOCK - Lock register allows locking to the current security level or unlocking by the lock holding level. */ +/*! @{ */ + +#define HASHCRYPT_LOCK_SECLOCK_MASK (0x3U) +#define HASHCRYPT_LOCK_SECLOCK_SHIFT (0U) +/*! SECLOCK - Write 1 to secure-lock this block (if running in a security state). Write 0 to unlock. + * If locked already, may only write if at same or higher security level as lock. Reads as: 0 if + * unlocked, else 1, 2, 3 to indicate security level it is locked at. NOTE: this and ID are the + * only readable registers if locked and current state is lower than lock level. + * 0b00..Unlocks, so block is open to all. But, AHB Master will only issue non-secure requests. + * 0b01..Locks to the current security level. AHB Master will issue requests at this level. + */ +#define HASHCRYPT_LOCK_SECLOCK(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_LOCK_SECLOCK_SHIFT)) & HASHCRYPT_LOCK_SECLOCK_MASK) + +#define HASHCRYPT_LOCK_PATTERN_MASK (0xFFF0U) +#define HASHCRYPT_LOCK_PATTERN_SHIFT (4U) +/*! PATTERN - Must write 0xA75 to change lock state. A75:Pattern needed to change bits 1:0 + */ +#define HASHCRYPT_LOCK_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_LOCK_PATTERN_SHIFT)) & HASHCRYPT_LOCK_PATTERN_MASK) +/*! @} */ + +/*! @name MASK - Allows Application to write a random mask for ICB use. Normally only a new one on each system reset (including power up). */ +/*! @{ */ + +#define HASHCRYPT_MASK_MASK_MASK (0xFFFFFFFFU) +#define HASHCRYPT_MASK_MASK_SHIFT (0U) +/*! MASK - A random word. + */ +#define HASHCRYPT_MASK_MASK(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_MASK_MASK_SHIFT)) & HASHCRYPT_MASK_MASK_MASK) +/*! @} */ + +/* The count of HASHCRYPT_MASK */ +#define HASHCRYPT_MASK_COUNT (4U) + +/*! @name RELOAD - The WO digest-reload registers may be written with a saved Hash digest, to allow continuation from where left off. These registers may only be written if the Reload field in CTRL is 1. If SHA1, only the 1st 5 are used. */ +/*! @{ */ + +#define HASHCRYPT_RELOAD_DIGEST_MASK (0xFFFFFFFFU) +#define HASHCRYPT_RELOAD_DIGEST_SHIFT (0U) +/*! DIGEST - SHA Digest word to reload. + */ +#define HASHCRYPT_RELOAD_DIGEST(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_RELOAD_DIGEST_SHIFT)) & HASHCRYPT_RELOAD_DIGEST_MASK) +/*! @} */ + +/* The count of HASHCRYPT_RELOAD */ +#define HASHCRYPT_RELOAD_COUNT (8U) + +/*! @name PRNG_SEED - PRNG random input value used as an entropy source */ +/*! @{ */ + +#define HASHCRYPT_PRNG_SEED_PRNG_SEED_MASK (0xFFFFFFFFU) +#define HASHCRYPT_PRNG_SEED_PRNG_SEED_SHIFT (0U) +/*! PRNG_SEED - Random input value used as an entropy source + */ +#define HASHCRYPT_PRNG_SEED_PRNG_SEED(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_PRNG_SEED_PRNG_SEED_SHIFT)) & HASHCRYPT_PRNG_SEED_PRNG_SEED_MASK) +/*! @} */ + +/*! @name PRNG_OUT - Provide random number. */ +/*! @{ */ + +#define HASHCRYPT_PRNG_OUT_PRNG_OUT_MASK (0xFFFFFFFFU) +#define HASHCRYPT_PRNG_OUT_PRNG_OUT_SHIFT (0U) +/*! PRNG_OUT - Provide random number. + */ +#define HASHCRYPT_PRNG_OUT_PRNG_OUT(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_PRNG_OUT_PRNG_OUT_SHIFT)) & HASHCRYPT_PRNG_OUT_PRNG_OUT_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group HASHCRYPT_Register_Masks */ + + +/* HASHCRYPT - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral HASHCRYPT base address */ + #define HASHCRYPT_BASE (0x500A4000u) + /** Peripheral HASHCRYPT base address */ + #define HASHCRYPT_BASE_NS (0x400A4000u) + /** Peripheral HASHCRYPT base pointer */ + #define HASHCRYPT ((HASHCRYPT_Type *)HASHCRYPT_BASE) + /** Peripheral HASHCRYPT base pointer */ + #define HASHCRYPT_NS ((HASHCRYPT_Type *)HASHCRYPT_BASE_NS) + /** Array initializer of HASHCRYPT peripheral base addresses */ + #define HASHCRYPT_BASE_ADDRS { HASHCRYPT_BASE } + /** Array initializer of HASHCRYPT peripheral base pointers */ + #define HASHCRYPT_BASE_PTRS { HASHCRYPT } + /** Array initializer of HASHCRYPT peripheral base addresses */ + #define HASHCRYPT_BASE_ADDRS_NS { HASHCRYPT_BASE_NS } + /** Array initializer of HASHCRYPT peripheral base pointers */ + #define HASHCRYPT_BASE_PTRS_NS { HASHCRYPT_NS } +#else + /** Peripheral HASHCRYPT base address */ + #define HASHCRYPT_BASE (0x400A4000u) + /** Peripheral HASHCRYPT base pointer */ + #define HASHCRYPT ((HASHCRYPT_Type *)HASHCRYPT_BASE) + /** Array initializer of HASHCRYPT peripheral base addresses */ + #define HASHCRYPT_BASE_ADDRS { HASHCRYPT_BASE } + /** Array initializer of HASHCRYPT peripheral base pointers */ + #define HASHCRYPT_BASE_PTRS { HASHCRYPT } +#endif + +/*! + * @} + */ /* end of group HASHCRYPT_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- I2C Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer + * @{ + */ + +/** I2C - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[2048]; + __IO uint32_t CFG; /**< Configuration for shared functions., offset: 0x800 */ + __IO uint32_t STAT; /**< Status register for Master, Slave, and Monitor functions., offset: 0x804 */ + __IO uint32_t INTENSET; /**< Interrupt Enable Set and read register., offset: 0x808 */ + __O uint32_t INTENCLR; /**< Interrupt Enable Clear register., offset: 0x80C */ + __IO uint32_t TIMEOUT; /**< Time-out value register., offset: 0x810 */ + __IO uint32_t CLKDIV; /**< Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register, and controls some timing of the Slave function., offset: 0x814 */ + __I uint32_t INTSTAT; /**< Interrupt Status register for Master, Slave, and Monitor functions., offset: 0x818 */ + uint8_t RESERVED_1[4]; + __IO uint32_t MSTCTL; /**< Master control register., offset: 0x820 */ + __IO uint32_t MSTTIME; /**< Master timing configuration., offset: 0x824 */ + __IO uint32_t MSTDAT; /**< Combined Master receiver and transmitter data register., offset: 0x828 */ + uint8_t RESERVED_2[20]; + __IO uint32_t SLVCTL; /**< Slave control register., offset: 0x840 */ + __IO uint32_t SLVDAT; /**< Combined Slave receiver and transmitter data register., offset: 0x844 */ + __IO uint32_t SLVADR[4]; /**< Slave address register., array offset: 0x848, array step: 0x4 */ + __IO uint32_t SLVQUAL0; /**< Slave Qualification for address 0., offset: 0x858 */ + uint8_t RESERVED_3[36]; + __I uint32_t MONRXDAT; /**< Monitor receiver data register., offset: 0x880 */ + uint8_t RESERVED_4[1912]; + __I uint32_t ID; /**< Peripheral identification register., offset: 0xFFC */ +} I2C_Type; + +/* ---------------------------------------------------------------------------- + -- I2C Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup I2C_Register_Masks I2C Register Masks + * @{ + */ + +/*! @name CFG - Configuration for shared functions. */ +/*! @{ */ + +#define I2C_CFG_MSTEN_MASK (0x1U) +#define I2C_CFG_MSTEN_SHIFT (0U) +/*! MSTEN - Master Enable. When disabled, configurations settings for the Master function are not + * changed, but the Master function is internally reset. + * 0b0..Disabled. The I2C Master function is disabled. + * 0b1..Enabled. The I2C Master function is enabled. + */ +#define I2C_CFG_MSTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MSTEN_SHIFT)) & I2C_CFG_MSTEN_MASK) + +#define I2C_CFG_SLVEN_MASK (0x2U) +#define I2C_CFG_SLVEN_SHIFT (1U) +/*! SLVEN - Slave Enable. When disabled, configurations settings for the Slave function are not + * changed, but the Slave function is internally reset. + * 0b0..Disabled. The I2C slave function is disabled. + * 0b1..Enabled. The I2C slave function is enabled. + */ +#define I2C_CFG_SLVEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_SLVEN_SHIFT)) & I2C_CFG_SLVEN_MASK) + +#define I2C_CFG_MONEN_MASK (0x4U) +#define I2C_CFG_MONEN_SHIFT (2U) +/*! MONEN - Monitor Enable. When disabled, configurations settings for the Monitor function are not + * changed, but the Monitor function is internally reset. + * 0b0..Disabled. The I2C Monitor function is disabled. + * 0b1..Enabled. The I2C Monitor function is enabled. + */ +#define I2C_CFG_MONEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MONEN_SHIFT)) & I2C_CFG_MONEN_MASK) + +#define I2C_CFG_TIMEOUTEN_MASK (0x8U) +#define I2C_CFG_TIMEOUTEN_SHIFT (3U) +/*! TIMEOUTEN - I2C bus Time-out Enable. When disabled, the time-out function is internally reset. + * 0b0..Disabled. Time-out function is disabled. + * 0b1..Enabled. Time-out function is enabled. Both types of time-out flags will be generated and will cause + * interrupts if they are enabled. Typically, only one time-out will be used in a system. + */ +#define I2C_CFG_TIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_TIMEOUTEN_SHIFT)) & I2C_CFG_TIMEOUTEN_MASK) + +#define I2C_CFG_MONCLKSTR_MASK (0x10U) +#define I2C_CFG_MONCLKSTR_SHIFT (4U) +/*! MONCLKSTR - Monitor function Clock Stretching. + * 0b0..Disabled. The Monitor function will not perform clock stretching. Software or DMA may not always be able + * to read data provided by the Monitor function before it is overwritten. This mode may be used when + * non-invasive monitoring is critical. + * 0b1..Enabled. The Monitor function will perform clock stretching in order to ensure that software or DMA can + * read all incoming data supplied by the Monitor function. + */ +#define I2C_CFG_MONCLKSTR(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MONCLKSTR_SHIFT)) & I2C_CFG_MONCLKSTR_MASK) + +#define I2C_CFG_HSCAPABLE_MASK (0x20U) +#define I2C_CFG_HSCAPABLE_SHIFT (5U) +/*! HSCAPABLE - High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive + * and filter, as well as the timing for certain I2C signalling, enabling High-speed mode applies + * to all functions: Master, Slave, and Monitor. + * 0b0..Fast-mode plus. The I 2C interface will support Standard-mode, Fast-mode, and Fast-mode Plus, to the + * extent that the pin electronics support these modes. Any changes that need to be made to the pin controls, + * such as changing the drive strength or filtering, must be made by software via the IOCON register associated + * with each I2C pin, + * 0b1..High-speed. In addition to Standard-mode, Fast-mode, and Fast-mode Plus, the I 2C interface will support + * High-speed mode to the extent that the pin electronics support these modes. See Section 25.7.2.2 for more + * information. + */ +#define I2C_CFG_HSCAPABLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_HSCAPABLE_SHIFT)) & I2C_CFG_HSCAPABLE_MASK) +/*! @} */ + +/*! @name STAT - Status register for Master, Slave, and Monitor functions. */ +/*! @{ */ + +#define I2C_STAT_MSTPENDING_MASK (0x1U) +#define I2C_STAT_MSTPENDING_SHIFT (0U) +/*! MSTPENDING - Master Pending. Indicates that the Master is waiting to continue communication on + * the I2C-bus (pending) or is idle. When the master is pending, the MSTSTATE bits indicate what + * type of software service if any the master expects. This flag will cause an interrupt when set + * if, enabled via the INTENSET register. The MSTPENDING flag is not set when the DMA is handling + * an event (if the MSTDMA bit in the MSTCTL register is set). If the master is in the idle + * state, and no communication is needed, mask this interrupt. + * 0b0..In progress. Communication is in progress and the Master function is busy and cannot currently accept a command. + * 0b1..Pending. The Master function needs software service or is in the idle state. If the master is not in the + * idle state, it is waiting to receive or transmit data or the NACK bit. + */ +#define I2C_STAT_MSTPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTPENDING_SHIFT)) & I2C_STAT_MSTPENDING_MASK) + +#define I2C_STAT_MSTSTATE_MASK (0xEU) +#define I2C_STAT_MSTSTATE_SHIFT (1U) +/*! MSTSTATE - Master State code. The master state code reflects the master state when the + * MSTPENDING bit is set, that is the master is pending or in the idle state. Each value of this field + * indicates a specific required service for the Master function. All other values are reserved. See + * Table 400 for details of state values and appropriate responses. + * 0b000..Idle. The Master function is available to be used for a new transaction. + * 0b001..Receive ready. Received data available (Master Receiver mode). Address plus Read was previously sent and Acknowledged by slave. + * 0b010..Transmit ready. Data can be transmitted (Master Transmitter mode). Address plus Write was previously sent and Acknowledged by slave. + * 0b011..NACK Address. Slave NACKed address. + * 0b100..NACK Data. Slave NACKed transmitted data. + */ +#define I2C_STAT_MSTSTATE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTSTATE_SHIFT)) & I2C_STAT_MSTSTATE_MASK) + +#define I2C_STAT_MSTARBLOSS_MASK (0x10U) +#define I2C_STAT_MSTARBLOSS_SHIFT (4U) +/*! MSTARBLOSS - Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to + * this bit. It is also cleared automatically a 1 is written to MSTCONTINUE. + * 0b0..No Arbitration Loss has occurred. + * 0b1..Arbitration loss. The Master function has experienced an Arbitration Loss. At this point, the Master + * function has already stopped driving the bus and gone to an idle state. Software can respond by doing nothing, + * or by sending a Start in order to attempt to gain control of the bus when it next becomes idle. + */ +#define I2C_STAT_MSTARBLOSS(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTARBLOSS_SHIFT)) & I2C_STAT_MSTARBLOSS_MASK) + +#define I2C_STAT_MSTSTSTPERR_MASK (0x40U) +#define I2C_STAT_MSTSTSTPERR_SHIFT (6U) +/*! MSTSTSTPERR - Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to + * this bit. It is also cleared automatically a 1 is written to MSTCONTINUE. + * 0b0..No Start/Stop Error has occurred. + * 0b1..The Master function has experienced a Start/Stop Error. A Start or Stop was detected at a time when it is + * not allowed by the I2C specification. The Master interface has stopped driving the bus and gone to an + * idle state, no action is required. A request for a Start could be made, or software could attempt to insure + * that the bus has not stalled. + */ +#define I2C_STAT_MSTSTSTPERR(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTSTSTPERR_SHIFT)) & I2C_STAT_MSTSTSTPERR_MASK) + +#define I2C_STAT_SLVPENDING_MASK (0x100U) +#define I2C_STAT_SLVPENDING_SHIFT (8U) +/*! SLVPENDING - Slave Pending. Indicates that the Slave function is waiting to continue + * communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if + * enabled via INTENSET. The SLVPENDING flag is not set when the DMA is handling an event (if the + * SLVDMA bit in the SLVCTL register is set). The SLVPENDING flag is read-only and is + * automatically cleared when a 1 is written to the SLVCONTINUE bit in the SLVCTL register. The point in time + * when SlvPending is set depends on whether the I2C interface is in HSCAPABLE mode. See Section + * 25.7.2.2.2. When the I2C interface is configured to be HSCAPABLE, HS master codes are + * detected automatically. Due to the requirements of the HS I2C specification, slave addresses must + * also be detected automatically, since the address must be acknowledged before the clock can be + * stretched. + * 0b0..In progress. The Slave function does not currently need service. + * 0b1..Pending. The Slave function needs service. Information on what is needed can be found in the adjacent SLVSTATE field. + */ +#define I2C_STAT_SLVPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVPENDING_SHIFT)) & I2C_STAT_SLVPENDING_MASK) + +#define I2C_STAT_SLVSTATE_MASK (0x600U) +#define I2C_STAT_SLVSTATE_SHIFT (9U) +/*! SLVSTATE - Slave State code. Each value of this field indicates a specific required service for + * the Slave function. All other values are reserved. See Table 401 for state values and actions. + * note that the occurrence of some states and how they are handled are affected by DMA mode and + * Automatic Operation modes. + * 0b00..Slave address. Address plus R/W received. At least one of the four slave addresses has been matched by hardware. + * 0b01..Slave receive. Received data is available (Slave Receiver mode). + * 0b10..Slave transmit. Data can be transmitted (Slave Transmitter mode). + */ +#define I2C_STAT_SLVSTATE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVSTATE_SHIFT)) & I2C_STAT_SLVSTATE_MASK) + +#define I2C_STAT_SLVNOTSTR_MASK (0x800U) +#define I2C_STAT_SLVNOTSTR_SHIFT (11U) +/*! SLVNOTSTR - Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. + * This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave + * operation. This read-only flag reflects the slave function status in real time. + * 0b0..Stretching. The slave function is currently stretching the I2C bus clock. Deep-Sleep or Power-down mode cannot be entered at this time. + * 0b1..Not stretching. The slave function is not currently stretching the I 2C bus clock. Deep-sleep or + * Power-down mode could be entered at this time. + */ +#define I2C_STAT_SLVNOTSTR(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVNOTSTR_SHIFT)) & I2C_STAT_SLVNOTSTR_MASK) + +#define I2C_STAT_SLVIDX_MASK (0x3000U) +#define I2C_STAT_SLVIDX_SHIFT (12U) +/*! SLVIDX - Slave address match Index. This field is valid when the I2C slave function has been + * selected by receiving an address that matches one of the slave addresses defined by any enabled + * slave address registers, and provides an identification of the address that was matched. It is + * possible that more than one address could be matched, but only one match can be reported here. + * 0b00..Address 0. Slave address 0 was matched. + * 0b01..Address 1. Slave address 1 was matched. + * 0b10..Address 2. Slave address 2 was matched. + * 0b11..Address 3. Slave address 3 was matched. + */ +#define I2C_STAT_SLVIDX(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVIDX_SHIFT)) & I2C_STAT_SLVIDX_MASK) + +#define I2C_STAT_SLVSEL_MASK (0x4000U) +#define I2C_STAT_SLVSEL_SHIFT (14U) +/*! SLVSEL - Slave selected flag. SLVSEL is set after an address match when software tells the Slave + * function to acknowledge the address, or when the address has been automatically acknowledged. + * It is cleared when another address cycle presents an address that does not match an enabled + * address on the Slave function, when slave software decides to NACK a matched address, when + * there is a Stop detected on the bus, when the master NACKs slave data, and in some combinations of + * Automatic Operation. SLVSEL is not cleared if software NACKs data. + * 0b0..Not selected. The Slave function is not currently selected. + * 0b1..Selected. The Slave function is currently selected. + */ +#define I2C_STAT_SLVSEL(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVSEL_SHIFT)) & I2C_STAT_SLVSEL_MASK) + +#define I2C_STAT_SLVDESEL_MASK (0x8000U) +#define I2C_STAT_SLVDESEL_SHIFT (15U) +/*! SLVDESEL - Slave Deselected flag. This flag will cause an interrupt when set if enabled via + * INTENSET. This flag can be cleared by writing a 1 to this bit. + * 0b0..Not deselected. The Slave function has not become deselected. This does not mean that it is currently + * selected. That information can be found in the SLVSEL flag. + * 0b1..Deselected. The Slave function has become deselected. This is specifically caused by the SLVSEL flag + * changing from 1 to 0. See the description of SLVSEL for details on when that event occurs. + */ +#define I2C_STAT_SLVDESEL(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVDESEL_SHIFT)) & I2C_STAT_SLVDESEL_MASK) + +#define I2C_STAT_MONRDY_MASK (0x10000U) +#define I2C_STAT_MONRDY_SHIFT (16U) +/*! MONRDY - Monitor Ready. This flag is cleared when the MONRXDAT register is read. + * 0b0..No data. The Monitor function does not currently have data available. + * 0b1..Data waiting. The Monitor function has data waiting to be read. + */ +#define I2C_STAT_MONRDY(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONRDY_SHIFT)) & I2C_STAT_MONRDY_MASK) + +#define I2C_STAT_MONOV_MASK (0x20000U) +#define I2C_STAT_MONOV_SHIFT (17U) +/*! MONOV - Monitor Overflow flag. + * 0b0..No overrun. Monitor data has not overrun. + * 0b1..Overrun. A Monitor data overrun has occurred. This can only happen when Monitor clock stretching not + * enabled via the MONCLKSTR bit in the CFG register. Writing 1 to this bit clears the flag. + */ +#define I2C_STAT_MONOV(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONOV_SHIFT)) & I2C_STAT_MONOV_MASK) + +#define I2C_STAT_MONACTIVE_MASK (0x40000U) +#define I2C_STAT_MONACTIVE_SHIFT (18U) +/*! MONACTIVE - Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to + * be active. Active is defined here as when some Master is on the bus: a bus Start has occurred + * more recently than a bus Stop. + * 0b0..Inactive. The Monitor function considers the I2C bus to be inactive. + * 0b1..Active. The Monitor function considers the I2C bus to be active. + */ +#define I2C_STAT_MONACTIVE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONACTIVE_SHIFT)) & I2C_STAT_MONACTIVE_MASK) + +#define I2C_STAT_MONIDLE_MASK (0x80000U) +#define I2C_STAT_MONIDLE_SHIFT (19U) +/*! MONIDLE - Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change + * from active to inactive. This can be used by software to decide when to process data + * accumulated by the Monitor function. This flag will cause an interrupt when set if enabled via the + * INTENSET register. The flag can be cleared by writing a 1 to this bit. + * 0b0..Not idle. The I2C bus is not idle, or this flag has been cleared by software. + * 0b1..Idle. The I2C bus has gone idle at least once since the last time this flag was cleared by software. + */ +#define I2C_STAT_MONIDLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONIDLE_SHIFT)) & I2C_STAT_MONIDLE_MASK) + +#define I2C_STAT_EVENTTIMEOUT_MASK (0x1000000U) +#define I2C_STAT_EVENTTIMEOUT_SHIFT (24U) +/*! EVENTTIMEOUT - Event Time-out Interrupt flag. Indicates when the time between events has been + * longer than the time specified by the TIMEOUT register. Events include Start, Stop, and clock + * edges. The flag is cleared by writing a 1 to this bit. No time-out is created when the I2C-bus + * is idle. + * 0b0..No time-out. I2C bus events have not caused a time-out. + * 0b1..Event time-out. The time between I2C bus events has been longer than the time specified by the TIMEOUT register. + */ +#define I2C_STAT_EVENTTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_EVENTTIMEOUT_SHIFT)) & I2C_STAT_EVENTTIMEOUT_MASK) + +#define I2C_STAT_SCLTIMEOUT_MASK (0x2000000U) +#define I2C_STAT_SCLTIMEOUT_SHIFT (25U) +/*! SCLTIMEOUT - SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the + * time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit. + * 0b0..No time-out. SCL low time has not caused a time-out. + * 0b1..Time-out. SCL low time has caused a time-out. + */ +#define I2C_STAT_SCLTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SCLTIMEOUT_SHIFT)) & I2C_STAT_SCLTIMEOUT_MASK) +/*! @} */ + +/*! @name INTENSET - Interrupt Enable Set and read register. */ +/*! @{ */ + +#define I2C_INTENSET_MSTPENDINGEN_MASK (0x1U) +#define I2C_INTENSET_MSTPENDINGEN_SHIFT (0U) +/*! MSTPENDINGEN - Master Pending interrupt Enable. + * 0b0..Disabled. The MstPending interrupt is disabled. + * 0b1..Enabled. The MstPending interrupt is enabled. + */ +#define I2C_INTENSET_MSTPENDINGEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTPENDINGEN_SHIFT)) & I2C_INTENSET_MSTPENDINGEN_MASK) + +#define I2C_INTENSET_MSTARBLOSSEN_MASK (0x10U) +#define I2C_INTENSET_MSTARBLOSSEN_SHIFT (4U) +/*! MSTARBLOSSEN - Master Arbitration Loss interrupt Enable. + * 0b0..Disabled. The MstArbLoss interrupt is disabled. + * 0b1..Enabled. The MstArbLoss interrupt is enabled. + */ +#define I2C_INTENSET_MSTARBLOSSEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTARBLOSSEN_SHIFT)) & I2C_INTENSET_MSTARBLOSSEN_MASK) + +#define I2C_INTENSET_MSTSTSTPERREN_MASK (0x40U) +#define I2C_INTENSET_MSTSTSTPERREN_SHIFT (6U) +/*! MSTSTSTPERREN - Master Start/Stop Error interrupt Enable. + * 0b0..Disabled. The MstStStpErr interrupt is disabled. + * 0b1..Enabled. The MstStStpErr interrupt is enabled. + */ +#define I2C_INTENSET_MSTSTSTPERREN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTSTSTPERREN_SHIFT)) & I2C_INTENSET_MSTSTSTPERREN_MASK) + +#define I2C_INTENSET_SLVPENDINGEN_MASK (0x100U) +#define I2C_INTENSET_SLVPENDINGEN_SHIFT (8U) +/*! SLVPENDINGEN - Slave Pending interrupt Enable. + * 0b0..Disabled. The SlvPending interrupt is disabled. + * 0b1..Enabled. The SlvPending interrupt is enabled. + */ +#define I2C_INTENSET_SLVPENDINGEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVPENDINGEN_SHIFT)) & I2C_INTENSET_SLVPENDINGEN_MASK) + +#define I2C_INTENSET_SLVNOTSTREN_MASK (0x800U) +#define I2C_INTENSET_SLVNOTSTREN_SHIFT (11U) +/*! SLVNOTSTREN - Slave Not Stretching interrupt Enable. + * 0b0..Disabled. The SlvNotStr interrupt is disabled. + * 0b1..Enabled. The SlvNotStr interrupt is enabled. + */ +#define I2C_INTENSET_SLVNOTSTREN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVNOTSTREN_SHIFT)) & I2C_INTENSET_SLVNOTSTREN_MASK) + +#define I2C_INTENSET_SLVDESELEN_MASK (0x8000U) +#define I2C_INTENSET_SLVDESELEN_SHIFT (15U) +/*! SLVDESELEN - Slave Deselect interrupt Enable. + * 0b0..Disabled. The SlvDeSel interrupt is disabled. + * 0b1..Enabled. The SlvDeSel interrupt is enabled. + */ +#define I2C_INTENSET_SLVDESELEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVDESELEN_SHIFT)) & I2C_INTENSET_SLVDESELEN_MASK) + +#define I2C_INTENSET_MONRDYEN_MASK (0x10000U) +#define I2C_INTENSET_MONRDYEN_SHIFT (16U) +/*! MONRDYEN - Monitor data Ready interrupt Enable. + * 0b0..Disabled. The MonRdy interrupt is disabled. + * 0b1..Enabled. The MonRdy interrupt is enabled. + */ +#define I2C_INTENSET_MONRDYEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONRDYEN_SHIFT)) & I2C_INTENSET_MONRDYEN_MASK) + +#define I2C_INTENSET_MONOVEN_MASK (0x20000U) +#define I2C_INTENSET_MONOVEN_SHIFT (17U) +/*! MONOVEN - Monitor Overrun interrupt Enable. + * 0b0..Disabled. The MonOv interrupt is disabled. + * 0b1..Enabled. The MonOv interrupt is enabled. + */ +#define I2C_INTENSET_MONOVEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONOVEN_SHIFT)) & I2C_INTENSET_MONOVEN_MASK) + +#define I2C_INTENSET_MONIDLEEN_MASK (0x80000U) +#define I2C_INTENSET_MONIDLEEN_SHIFT (19U) +/*! MONIDLEEN - Monitor Idle interrupt Enable. + * 0b0..Disabled. The MonIdle interrupt is disabled. + * 0b1..Enabled. The MonIdle interrupt is enabled. + */ +#define I2C_INTENSET_MONIDLEEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONIDLEEN_SHIFT)) & I2C_INTENSET_MONIDLEEN_MASK) + +#define I2C_INTENSET_EVENTTIMEOUTEN_MASK (0x1000000U) +#define I2C_INTENSET_EVENTTIMEOUTEN_SHIFT (24U) +/*! EVENTTIMEOUTEN - Event time-out interrupt Enable. + * 0b0..Disabled. The Event time-out interrupt is disabled. + * 0b1..Enabled. The Event time-out interrupt is enabled. + */ +#define I2C_INTENSET_EVENTTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_EVENTTIMEOUTEN_SHIFT)) & I2C_INTENSET_EVENTTIMEOUTEN_MASK) + +#define I2C_INTENSET_SCLTIMEOUTEN_MASK (0x2000000U) +#define I2C_INTENSET_SCLTIMEOUTEN_SHIFT (25U) +/*! SCLTIMEOUTEN - SCL time-out interrupt Enable. + * 0b0..Disabled. The SCL time-out interrupt is disabled. + * 0b1..Enabled. The SCL time-out interrupt is enabled. + */ +#define I2C_INTENSET_SCLTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SCLTIMEOUTEN_SHIFT)) & I2C_INTENSET_SCLTIMEOUTEN_MASK) +/*! @} */ + +/*! @name INTENCLR - Interrupt Enable Clear register. */ +/*! @{ */ + +#define I2C_INTENCLR_MSTPENDINGCLR_MASK (0x1U) +#define I2C_INTENCLR_MSTPENDINGCLR_SHIFT (0U) +/*! MSTPENDINGCLR - Master Pending interrupt clear. Writing 1 to this bit clears the corresponding + * bit in the INTENSET register if implemented. + */ +#define I2C_INTENCLR_MSTPENDINGCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTPENDINGCLR_SHIFT)) & I2C_INTENCLR_MSTPENDINGCLR_MASK) + +#define I2C_INTENCLR_MSTARBLOSSCLR_MASK (0x10U) +#define I2C_INTENCLR_MSTARBLOSSCLR_SHIFT (4U) +/*! MSTARBLOSSCLR - Master Arbitration Loss interrupt clear. + */ +#define I2C_INTENCLR_MSTARBLOSSCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTARBLOSSCLR_SHIFT)) & I2C_INTENCLR_MSTARBLOSSCLR_MASK) + +#define I2C_INTENCLR_MSTSTSTPERRCLR_MASK (0x40U) +#define I2C_INTENCLR_MSTSTSTPERRCLR_SHIFT (6U) +/*! MSTSTSTPERRCLR - Master Start/Stop Error interrupt clear. + */ +#define I2C_INTENCLR_MSTSTSTPERRCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTSTSTPERRCLR_SHIFT)) & I2C_INTENCLR_MSTSTSTPERRCLR_MASK) + +#define I2C_INTENCLR_SLVPENDINGCLR_MASK (0x100U) +#define I2C_INTENCLR_SLVPENDINGCLR_SHIFT (8U) +/*! SLVPENDINGCLR - Slave Pending interrupt clear. + */ +#define I2C_INTENCLR_SLVPENDINGCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVPENDINGCLR_SHIFT)) & I2C_INTENCLR_SLVPENDINGCLR_MASK) + +#define I2C_INTENCLR_SLVNOTSTRCLR_MASK (0x800U) +#define I2C_INTENCLR_SLVNOTSTRCLR_SHIFT (11U) +/*! SLVNOTSTRCLR - Slave Not Stretching interrupt clear. + */ +#define I2C_INTENCLR_SLVNOTSTRCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVNOTSTRCLR_SHIFT)) & I2C_INTENCLR_SLVNOTSTRCLR_MASK) + +#define I2C_INTENCLR_SLVDESELCLR_MASK (0x8000U) +#define I2C_INTENCLR_SLVDESELCLR_SHIFT (15U) +/*! SLVDESELCLR - Slave Deselect interrupt clear. + */ +#define I2C_INTENCLR_SLVDESELCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVDESELCLR_SHIFT)) & I2C_INTENCLR_SLVDESELCLR_MASK) + +#define I2C_INTENCLR_MONRDYCLR_MASK (0x10000U) +#define I2C_INTENCLR_MONRDYCLR_SHIFT (16U) +/*! MONRDYCLR - Monitor data Ready interrupt clear. + */ +#define I2C_INTENCLR_MONRDYCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONRDYCLR_SHIFT)) & I2C_INTENCLR_MONRDYCLR_MASK) + +#define I2C_INTENCLR_MONOVCLR_MASK (0x20000U) +#define I2C_INTENCLR_MONOVCLR_SHIFT (17U) +/*! MONOVCLR - Monitor Overrun interrupt clear. + */ +#define I2C_INTENCLR_MONOVCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONOVCLR_SHIFT)) & I2C_INTENCLR_MONOVCLR_MASK) + +#define I2C_INTENCLR_MONIDLECLR_MASK (0x80000U) +#define I2C_INTENCLR_MONIDLECLR_SHIFT (19U) +/*! MONIDLECLR - Monitor Idle interrupt clear. + */ +#define I2C_INTENCLR_MONIDLECLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONIDLECLR_SHIFT)) & I2C_INTENCLR_MONIDLECLR_MASK) + +#define I2C_INTENCLR_EVENTTIMEOUTCLR_MASK (0x1000000U) +#define I2C_INTENCLR_EVENTTIMEOUTCLR_SHIFT (24U) +/*! EVENTTIMEOUTCLR - Event time-out interrupt clear. + */ +#define I2C_INTENCLR_EVENTTIMEOUTCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_EVENTTIMEOUTCLR_SHIFT)) & I2C_INTENCLR_EVENTTIMEOUTCLR_MASK) + +#define I2C_INTENCLR_SCLTIMEOUTCLR_MASK (0x2000000U) +#define I2C_INTENCLR_SCLTIMEOUTCLR_SHIFT (25U) +/*! SCLTIMEOUTCLR - SCL time-out interrupt clear. + */ +#define I2C_INTENCLR_SCLTIMEOUTCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SCLTIMEOUTCLR_SHIFT)) & I2C_INTENCLR_SCLTIMEOUTCLR_MASK) +/*! @} */ + +/*! @name TIMEOUT - Time-out value register. */ +/*! @{ */ + +#define I2C_TIMEOUT_TOMIN_MASK (0xFU) +#define I2C_TIMEOUT_TOMIN_SHIFT (0U) +/*! TOMIN - Time-out time value, bottom four bits. These are hard-wired to 0xF. This gives a minimum + * time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks. + */ +#define I2C_TIMEOUT_TOMIN(x) (((uint32_t)(((uint32_t)(x)) << I2C_TIMEOUT_TOMIN_SHIFT)) & I2C_TIMEOUT_TOMIN_MASK) + +#define I2C_TIMEOUT_TO_MASK (0xFFF0U) +#define I2C_TIMEOUT_TO_SHIFT (4U) +/*! TO - Time-out time value. Specifies the time-out interval value in increments of 16 I 2C + * function clocks, as defined by the CLKDIV register. To change this value while I2C is in operation, + * disable all time-outs, write a new value to TIMEOUT, then re-enable time-outs. 0x000 = A + * time-out will occur after 16 counts of the I2C function clock. 0x001 = A time-out will occur after + * 32 counts of the I2C function clock. 0xFFF = A time-out will occur after 65,536 counts of the + * I2C function clock. + */ +#define I2C_TIMEOUT_TO(x) (((uint32_t)(((uint32_t)(x)) << I2C_TIMEOUT_TO_SHIFT)) & I2C_TIMEOUT_TO_MASK) +/*! @} */ + +/*! @name CLKDIV - Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register, and controls some timing of the Slave function. */ +/*! @{ */ + +#define I2C_CLKDIV_DIVVAL_MASK (0xFFFFU) +#define I2C_CLKDIV_DIVVAL_SHIFT (0U) +/*! DIVVAL - This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that + * need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 = + * FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3 before use. 0xFFFF = FCLK is + * divided by 65,536 before use. + */ +#define I2C_CLKDIV_DIVVAL(x) (((uint32_t)(((uint32_t)(x)) << I2C_CLKDIV_DIVVAL_SHIFT)) & I2C_CLKDIV_DIVVAL_MASK) +/*! @} */ + +/*! @name INTSTAT - Interrupt Status register for Master, Slave, and Monitor functions. */ +/*! @{ */ + +#define I2C_INTSTAT_MSTPENDING_MASK (0x1U) +#define I2C_INTSTAT_MSTPENDING_SHIFT (0U) +/*! MSTPENDING - Master Pending. + */ +#define I2C_INTSTAT_MSTPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTPENDING_SHIFT)) & I2C_INTSTAT_MSTPENDING_MASK) + +#define I2C_INTSTAT_MSTARBLOSS_MASK (0x10U) +#define I2C_INTSTAT_MSTARBLOSS_SHIFT (4U) +/*! MSTARBLOSS - Master Arbitration Loss flag. + */ +#define I2C_INTSTAT_MSTARBLOSS(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTARBLOSS_SHIFT)) & I2C_INTSTAT_MSTARBLOSS_MASK) + +#define I2C_INTSTAT_MSTSTSTPERR_MASK (0x40U) +#define I2C_INTSTAT_MSTSTSTPERR_SHIFT (6U) +/*! MSTSTSTPERR - Master Start/Stop Error flag. + */ +#define I2C_INTSTAT_MSTSTSTPERR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTSTSTPERR_SHIFT)) & I2C_INTSTAT_MSTSTSTPERR_MASK) + +#define I2C_INTSTAT_SLVPENDING_MASK (0x100U) +#define I2C_INTSTAT_SLVPENDING_SHIFT (8U) +/*! SLVPENDING - Slave Pending. + */ +#define I2C_INTSTAT_SLVPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVPENDING_SHIFT)) & I2C_INTSTAT_SLVPENDING_MASK) + +#define I2C_INTSTAT_SLVNOTSTR_MASK (0x800U) +#define I2C_INTSTAT_SLVNOTSTR_SHIFT (11U) +/*! SLVNOTSTR - Slave Not Stretching status. + */ +#define I2C_INTSTAT_SLVNOTSTR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVNOTSTR_SHIFT)) & I2C_INTSTAT_SLVNOTSTR_MASK) + +#define I2C_INTSTAT_SLVDESEL_MASK (0x8000U) +#define I2C_INTSTAT_SLVDESEL_SHIFT (15U) +/*! SLVDESEL - Slave Deselected flag. + */ +#define I2C_INTSTAT_SLVDESEL(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVDESEL_SHIFT)) & I2C_INTSTAT_SLVDESEL_MASK) + +#define I2C_INTSTAT_MONRDY_MASK (0x10000U) +#define I2C_INTSTAT_MONRDY_SHIFT (16U) +/*! MONRDY - Monitor Ready. + */ +#define I2C_INTSTAT_MONRDY(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONRDY_SHIFT)) & I2C_INTSTAT_MONRDY_MASK) + +#define I2C_INTSTAT_MONOV_MASK (0x20000U) +#define I2C_INTSTAT_MONOV_SHIFT (17U) +/*! MONOV - Monitor Overflow flag. + */ +#define I2C_INTSTAT_MONOV(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONOV_SHIFT)) & I2C_INTSTAT_MONOV_MASK) + +#define I2C_INTSTAT_MONIDLE_MASK (0x80000U) +#define I2C_INTSTAT_MONIDLE_SHIFT (19U) +/*! MONIDLE - Monitor Idle flag. + */ +#define I2C_INTSTAT_MONIDLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONIDLE_SHIFT)) & I2C_INTSTAT_MONIDLE_MASK) + +#define I2C_INTSTAT_EVENTTIMEOUT_MASK (0x1000000U) +#define I2C_INTSTAT_EVENTTIMEOUT_SHIFT (24U) +/*! EVENTTIMEOUT - Event time-out Interrupt flag. + */ +#define I2C_INTSTAT_EVENTTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_EVENTTIMEOUT_SHIFT)) & I2C_INTSTAT_EVENTTIMEOUT_MASK) + +#define I2C_INTSTAT_SCLTIMEOUT_MASK (0x2000000U) +#define I2C_INTSTAT_SCLTIMEOUT_SHIFT (25U) +/*! SCLTIMEOUT - SCL time-out Interrupt flag. + */ +#define I2C_INTSTAT_SCLTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SCLTIMEOUT_SHIFT)) & I2C_INTSTAT_SCLTIMEOUT_MASK) +/*! @} */ + +/*! @name MSTCTL - Master control register. */ +/*! @{ */ + +#define I2C_MSTCTL_MSTCONTINUE_MASK (0x1U) +#define I2C_MSTCTL_MSTCONTINUE_SHIFT (0U) +/*! MSTCONTINUE - Master Continue. This bit is write-only. + * 0b0..No effect. + * 0b1..Continue. Informs the Master function to continue to the next operation. This must done after writing + * transmit data, reading received data, or any other housekeeping related to the next bus operation. + */ +#define I2C_MSTCTL_MSTCONTINUE(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTCONTINUE_SHIFT)) & I2C_MSTCTL_MSTCONTINUE_MASK) + +#define I2C_MSTCTL_MSTSTART_MASK (0x2U) +#define I2C_MSTCTL_MSTSTART_SHIFT (1U) +/*! MSTSTART - Master Start control. This bit is write-only. + * 0b0..No effect. + * 0b1..Start. A Start will be generated on the I2C bus at the next allowed time. + */ +#define I2C_MSTCTL_MSTSTART(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTSTART_SHIFT)) & I2C_MSTCTL_MSTSTART_MASK) + +#define I2C_MSTCTL_MSTSTOP_MASK (0x4U) +#define I2C_MSTCTL_MSTSTOP_SHIFT (2U) +/*! MSTSTOP - Master Stop control. This bit is write-only. + * 0b0..No effect. + * 0b1..Stop. A Stop will be generated on the I2C bus at the next allowed time, preceded by a NACK to the slave + * if the master is receiving data from the slave (Master Receiver mode). + */ +#define I2C_MSTCTL_MSTSTOP(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTSTOP_SHIFT)) & I2C_MSTCTL_MSTSTOP_MASK) + +#define I2C_MSTCTL_MSTDMA_MASK (0x8U) +#define I2C_MSTCTL_MSTDMA_SHIFT (3U) +/*! MSTDMA - Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type + * operations such as Start, address, Stop, and address match must always be done with software, + * typically via an interrupt. Address acknowledgement must also be done by software except when + * the I2C is configured to be HSCAPABLE (and address acknowledgement is handled entirely by + * hardware) or when Automatic Operation is enabled. When a DMA data transfer is complete, MSTDMA + * must be cleared prior to beginning the next operation, typically a Start or Stop.This bit is + * read/write. + * 0b0..Disable. No DMA requests are generated for master operation. + * 0b1..Enable. A DMA request is generated for I2C master data operations. When this I2C master is generating + * Acknowledge bits in Master Receiver mode, the acknowledge is generated automatically. + */ +#define I2C_MSTCTL_MSTDMA(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTDMA_SHIFT)) & I2C_MSTCTL_MSTDMA_MASK) +/*! @} */ + +/*! @name MSTTIME - Master timing configuration. */ +/*! @{ */ + +#define I2C_MSTTIME_MSTSCLLOW_MASK (0x7U) +#define I2C_MSTTIME_MSTSCLLOW_SHIFT (0U) +/*! MSTSCLLOW - Master SCL Low time. Specifies the minimum low time that will be asserted by this + * master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This + * corresponds to the parameter t LOW in the I2C bus specification. I2C bus specification parameters + * tBUF and tSU;STA have the same values and are also controlled by MSTSCLLOW. + * 0b000..2 clocks. Minimum SCL low time is 2 clocks of the I2C clock pre-divider. + * 0b001..3 clocks. Minimum SCL low time is 3 clocks of the I2C clock pre-divider. + * 0b010..4 clocks. Minimum SCL low time is 4 clocks of the I2C clock pre-divider. + * 0b011..5 clocks. Minimum SCL low time is 5 clocks of the I2C clock pre-divider. + * 0b100..6 clocks. Minimum SCL low time is 6 clocks of the I2C clock pre-divider. + * 0b101..7 clocks. Minimum SCL low time is 7 clocks of the I2C clock pre-divider. + * 0b110..8 clocks. Minimum SCL low time is 8 clocks of the I2C clock pre-divider. + * 0b111..9 clocks. Minimum SCL low time is 9 clocks of the I2C clock pre-divider. + */ +#define I2C_MSTTIME_MSTSCLLOW(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTTIME_MSTSCLLOW_SHIFT)) & I2C_MSTTIME_MSTSCLLOW_MASK) + +#define I2C_MSTTIME_MSTSCLHIGH_MASK (0x70U) +#define I2C_MSTTIME_MSTSCLHIGH_SHIFT (4U) +/*! MSTSCLHIGH - Master SCL High time. Specifies the minimum high time that will be asserted by this + * master on SCL. Other masters in a multi-master system could shorten this time. This + * corresponds to the parameter tHIGH in the I2C bus specification. I2C bus specification parameters + * tSU;STO and tHD;STA have the same values and are also controlled by MSTSCLHIGH. + * 0b000..2 clocks. Minimum SCL high time is 2 clock of the I2C clock pre-divider. + * 0b001..3 clocks. Minimum SCL high time is 3 clocks of the I2C clock pre-divider . + * 0b010..4 clocks. Minimum SCL high time is 4 clock of the I2C clock pre-divider. + * 0b011..5 clocks. Minimum SCL high time is 5 clock of the I2C clock pre-divider. + * 0b100..6 clocks. Minimum SCL high time is 6 clock of the I2C clock pre-divider. + * 0b101..7 clocks. Minimum SCL high time is 7 clock of the I2C clock pre-divider. + * 0b110..8 clocks. Minimum SCL high time is 8 clock of the I2C clock pre-divider. + * 0b111..9 clocks. Minimum SCL high time is 9 clocks of the I2C clock pre-divider. + */ +#define I2C_MSTTIME_MSTSCLHIGH(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTTIME_MSTSCLHIGH_SHIFT)) & I2C_MSTTIME_MSTSCLHIGH_MASK) +/*! @} */ + +/*! @name MSTDAT - Combined Master receiver and transmitter data register. */ +/*! @{ */ + +#define I2C_MSTDAT_DATA_MASK (0xFFU) +#define I2C_MSTDAT_DATA_SHIFT (0U) +/*! DATA - Master function data register. Read: read the most recently received data for the Master + * function. Write: transmit data using the Master function. + */ +#define I2C_MSTDAT_DATA(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTDAT_DATA_SHIFT)) & I2C_MSTDAT_DATA_MASK) +/*! @} */ + +/*! @name SLVCTL - Slave control register. */ +/*! @{ */ + +#define I2C_SLVCTL_SLVCONTINUE_MASK (0x1U) +#define I2C_SLVCTL_SLVCONTINUE_SHIFT (0U) +/*! SLVCONTINUE - Slave Continue. + * 0b0..No effect. + * 0b1..Continue. Informs the Slave function to continue to the next operation, by clearing the SLVPENDING flag + * in the STAT register. This must be done after writing transmit data, reading received data, or any other + * housekeeping related to the next bus operation. Automatic Operation has different requirements. SLVCONTINUE + * should not be set unless SLVPENDING = 1. + */ +#define I2C_SLVCTL_SLVCONTINUE(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVCONTINUE_SHIFT)) & I2C_SLVCTL_SLVCONTINUE_MASK) + +#define I2C_SLVCTL_SLVNACK_MASK (0x2U) +#define I2C_SLVCTL_SLVNACK_SHIFT (1U) +/*! SLVNACK - Slave NACK. + * 0b0..No effect. + * 0b1..NACK. Causes the Slave function to NACK the master when the slave is receiving data from the master (Slave Receiver mode). + */ +#define I2C_SLVCTL_SLVNACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVNACK_SHIFT)) & I2C_SLVCTL_SLVNACK_MASK) + +#define I2C_SLVCTL_SLVDMA_MASK (0x8U) +#define I2C_SLVCTL_SLVDMA_SHIFT (3U) +/*! SLVDMA - Slave DMA enable. + * 0b0..Disabled. No DMA requests are issued for Slave mode operation. + * 0b1..Enabled. DMA requests are issued for I2C slave data transmission and reception. + */ +#define I2C_SLVCTL_SLVDMA(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVDMA_SHIFT)) & I2C_SLVCTL_SLVDMA_MASK) + +#define I2C_SLVCTL_AUTOACK_MASK (0x100U) +#define I2C_SLVCTL_AUTOACK_SHIFT (8U) +/*! AUTOACK - Automatic Acknowledge.When this bit is set, it will cause an I2C header which matches + * SLVADR0 and the direction set by AUTOMATCHREAD to be ACKed immediately; this is used with DMA + * to allow processing of the data without intervention. If this bit is clear and a header + * matches SLVADR0, the behavior is controlled by AUTONACK in the SLVADR0 register: allowing NACK or + * interrupt. + * 0b0..Normal, non-automatic operation. If AUTONACK = 0, an SlvPending interrupt is generated when a matching + * address is received. If AUTONACK = 1, received addresses are NACKed (ignored). + * 0b1..A header with matching SLVADR0 and matching direction as set by AUTOMATCHREAD will be ACKed immediately, + * allowing the master to move on to the data bytes. If the address matches SLVADR0, but the direction does + * not match AUTOMATCHREAD, the behavior will depend on the AUTONACK bit in the SLVADR0 register: if AUTONACK + * is set, then it will be Nacked; else if AUTONACK is clear, then a SlvPending interrupt is generated. + */ +#define I2C_SLVCTL_AUTOACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_AUTOACK_SHIFT)) & I2C_SLVCTL_AUTOACK_MASK) + +#define I2C_SLVCTL_AUTOMATCHREAD_MASK (0x200U) +#define I2C_SLVCTL_AUTOMATCHREAD_SHIFT (9U) +/*! AUTOMATCHREAD - When AUTOACK is set, this bit controls whether it matches a read or write + * request on the next header with an address matching SLVADR0. Since DMA needs to be configured to + * match the transfer direction, the direction needs to be specified. This bit allows a direction to + * be chosen for the next operation. + * 0b0..The expected next operation in Automatic Mode is an I2C write. + * 0b1..The expected next operation in Automatic Mode is an I2C read. + */ +#define I2C_SLVCTL_AUTOMATCHREAD(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_AUTOMATCHREAD_SHIFT)) & I2C_SLVCTL_AUTOMATCHREAD_MASK) +/*! @} */ + +/*! @name SLVDAT - Combined Slave receiver and transmitter data register. */ +/*! @{ */ + +#define I2C_SLVDAT_DATA_MASK (0xFFU) +#define I2C_SLVDAT_DATA_SHIFT (0U) +/*! DATA - Slave function data register. Read: read the most recently received data for the Slave + * function. Write: transmit data using the Slave function. + */ +#define I2C_SLVDAT_DATA(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVDAT_DATA_SHIFT)) & I2C_SLVDAT_DATA_MASK) +/*! @} */ + +/*! @name SLVADR - Slave address register. */ +/*! @{ */ + +#define I2C_SLVADR_SADISABLE_MASK (0x1U) +#define I2C_SLVADR_SADISABLE_SHIFT (0U) +/*! SADISABLE - Slave Address n Disable. + * 0b0..Enabled. Slave Address n is enabled. + * 0b1..Ignored Slave Address n is ignored. + */ +#define I2C_SLVADR_SADISABLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_SADISABLE_SHIFT)) & I2C_SLVADR_SADISABLE_MASK) + +#define I2C_SLVADR_SLVADR_MASK (0xFEU) +#define I2C_SLVADR_SLVADR_SHIFT (1U) +/*! SLVADR - Slave Address. Seven bit slave address that is compared to received addresses if enabled. + */ +#define I2C_SLVADR_SLVADR(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_SLVADR_SHIFT)) & I2C_SLVADR_SLVADR_MASK) + +#define I2C_SLVADR_AUTONACK_MASK (0x8000U) +#define I2C_SLVADR_AUTONACK_SHIFT (15U) +/*! AUTONACK - Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD, allows + * software to ignore I2C traffic while handling previous I2C data or other operations. + * 0b0..Normal operation, matching I2C addresses are not ignored. + * 0b1..Automatic-only mode. All incoming addresses are ignored (NACKed), unless AUTOACK is set, it matches + * SLVADRn, and AUTOMATCHREAD matches the direction. + */ +#define I2C_SLVADR_AUTONACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_AUTONACK_SHIFT)) & I2C_SLVADR_AUTONACK_MASK) +/*! @} */ + +/* The count of I2C_SLVADR */ +#define I2C_SLVADR_COUNT (4U) + +/*! @name SLVQUAL0 - Slave Qualification for address 0. */ +/*! @{ */ + +#define I2C_SLVQUAL0_QUALMODE0_MASK (0x1U) +#define I2C_SLVQUAL0_QUALMODE0_SHIFT (0U) +/*! QUALMODE0 - Qualify mode for slave address 0. + * 0b0..Mask. The SLVQUAL0 field is used as a logical mask for matching address 0. + * 0b1..Extend. The SLVQUAL0 field is used to extend address 0 matching in a range of addresses. + */ +#define I2C_SLVQUAL0_QUALMODE0(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVQUAL0_QUALMODE0_SHIFT)) & I2C_SLVQUAL0_QUALMODE0_MASK) + +#define I2C_SLVQUAL0_SLVQUAL0_MASK (0xFEU) +#define I2C_SLVQUAL0_SLVQUAL0_SHIFT (1U) +/*! SLVQUAL0 - Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to + * be used as-is, assuming that it is enabled. If QUALMODE0 = 0, any bit in this field which is + * set to 1 will cause an automatic match of the corresponding bit of the received address when it + * is compared to the SLVADR0 register. If QUALMODE0 = 1, an address range is matched for + * address 0. This range extends from the value defined by SLVADR0 to the address defined by SLVQUAL0 + * (address matches when SLVADR0[7:1] <= received address <= SLVQUAL0[7:1]). + */ +#define I2C_SLVQUAL0_SLVQUAL0(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVQUAL0_SLVQUAL0_SHIFT)) & I2C_SLVQUAL0_SLVQUAL0_MASK) +/*! @} */ + +/*! @name MONRXDAT - Monitor receiver data register. */ +/*! @{ */ + +#define I2C_MONRXDAT_MONRXDAT_MASK (0xFFU) +#define I2C_MONRXDAT_MONRXDAT_SHIFT (0U) +/*! MONRXDAT - Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins. + */ +#define I2C_MONRXDAT_MONRXDAT(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONRXDAT_SHIFT)) & I2C_MONRXDAT_MONRXDAT_MASK) + +#define I2C_MONRXDAT_MONSTART_MASK (0x100U) +#define I2C_MONRXDAT_MONSTART_SHIFT (8U) +/*! MONSTART - Monitor Received Start. + * 0b0..No start detected. The Monitor function has not detected a Start event on the I2C bus. + * 0b1..Start detected. The Monitor function has detected a Start event on the I2C bus. + */ +#define I2C_MONRXDAT_MONSTART(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONSTART_SHIFT)) & I2C_MONRXDAT_MONSTART_MASK) + +#define I2C_MONRXDAT_MONRESTART_MASK (0x200U) +#define I2C_MONRXDAT_MONRESTART_SHIFT (9U) +/*! MONRESTART - Monitor Received Repeated Start. + * 0b0..No repeated start detected. The Monitor function has not detected a Repeated Start event on the I2C bus. + * 0b1..Repeated start detected. The Monitor function has detected a Repeated Start event on the I2C bus. + */ +#define I2C_MONRXDAT_MONRESTART(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONRESTART_SHIFT)) & I2C_MONRXDAT_MONRESTART_MASK) + +#define I2C_MONRXDAT_MONNACK_MASK (0x400U) +#define I2C_MONRXDAT_MONNACK_SHIFT (10U) +/*! MONNACK - Monitor Received NACK. + * 0b0..Acknowledged. The data currently being provided by the Monitor function was acknowledged by at least one master or slave receiver. + * 0b1..Not acknowledged. The data currently being provided by the Monitor function was not acknowledged by any receiver. + */ +#define I2C_MONRXDAT_MONNACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONNACK_SHIFT)) & I2C_MONRXDAT_MONNACK_MASK) +/*! @} */ + +/*! @name ID - Peripheral identification register. */ +/*! @{ */ + +#define I2C_ID_APERTURE_MASK (0xFFU) +#define I2C_ID_APERTURE_SHIFT (0U) +/*! APERTURE - Aperture: encoded as (aperture size/4K) -1, so 0x00 means a 4K aperture. + */ +#define I2C_ID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << I2C_ID_APERTURE_SHIFT)) & I2C_ID_APERTURE_MASK) + +#define I2C_ID_MINOR_REV_MASK (0xF00U) +#define I2C_ID_MINOR_REV_SHIFT (8U) +/*! MINOR_REV - Minor revision of module implementation. + */ +#define I2C_ID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << I2C_ID_MINOR_REV_SHIFT)) & I2C_ID_MINOR_REV_MASK) + +#define I2C_ID_MAJOR_REV_MASK (0xF000U) +#define I2C_ID_MAJOR_REV_SHIFT (12U) +/*! MAJOR_REV - Major revision of module implementation. + */ +#define I2C_ID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << I2C_ID_MAJOR_REV_SHIFT)) & I2C_ID_MAJOR_REV_MASK) + +#define I2C_ID_ID_MASK (0xFFFF0000U) +#define I2C_ID_ID_SHIFT (16U) +/*! ID - Module identifier for the selected function. + */ +#define I2C_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << I2C_ID_ID_SHIFT)) & I2C_ID_ID_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group I2C_Register_Masks */ + + +/* I2C - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral I2C0 base address */ + #define I2C0_BASE (0x50086000u) + /** Peripheral I2C0 base address */ + #define I2C0_BASE_NS (0x40086000u) + /** Peripheral I2C0 base pointer */ + #define I2C0 ((I2C_Type *)I2C0_BASE) + /** Peripheral I2C0 base pointer */ + #define I2C0_NS ((I2C_Type *)I2C0_BASE_NS) + /** Peripheral I2C1 base address */ + #define I2C1_BASE (0x50087000u) + /** Peripheral I2C1 base address */ + #define I2C1_BASE_NS (0x40087000u) + /** Peripheral I2C1 base pointer */ + #define I2C1 ((I2C_Type *)I2C1_BASE) + /** Peripheral I2C1 base pointer */ + #define I2C1_NS ((I2C_Type *)I2C1_BASE_NS) + /** Peripheral I2C2 base address */ + #define I2C2_BASE (0x50088000u) + /** Peripheral I2C2 base address */ + #define I2C2_BASE_NS (0x40088000u) + /** Peripheral I2C2 base pointer */ + #define I2C2 ((I2C_Type *)I2C2_BASE) + /** Peripheral I2C2 base pointer */ + #define I2C2_NS ((I2C_Type *)I2C2_BASE_NS) + /** Peripheral I2C3 base address */ + #define I2C3_BASE (0x50089000u) + /** Peripheral I2C3 base address */ + #define I2C3_BASE_NS (0x40089000u) + /** Peripheral I2C3 base pointer */ + #define I2C3 ((I2C_Type *)I2C3_BASE) + /** Peripheral I2C3 base pointer */ + #define I2C3_NS ((I2C_Type *)I2C3_BASE_NS) + /** Peripheral I2C4 base address */ + #define I2C4_BASE (0x5008A000u) + /** Peripheral I2C4 base address */ + #define I2C4_BASE_NS (0x4008A000u) + /** Peripheral I2C4 base pointer */ + #define I2C4 ((I2C_Type *)I2C4_BASE) + /** Peripheral I2C4 base pointer */ + #define I2C4_NS ((I2C_Type *)I2C4_BASE_NS) + /** Peripheral I2C5 base address */ + #define I2C5_BASE (0x50096000u) + /** Peripheral I2C5 base address */ + #define I2C5_BASE_NS (0x40096000u) + /** Peripheral I2C5 base pointer */ + #define I2C5 ((I2C_Type *)I2C5_BASE) + /** Peripheral I2C5 base pointer */ + #define I2C5_NS ((I2C_Type *)I2C5_BASE_NS) + /** Peripheral I2C6 base address */ + #define I2C6_BASE (0x50097000u) + /** Peripheral I2C6 base address */ + #define I2C6_BASE_NS (0x40097000u) + /** Peripheral I2C6 base pointer */ + #define I2C6 ((I2C_Type *)I2C6_BASE) + /** Peripheral I2C6 base pointer */ + #define I2C6_NS ((I2C_Type *)I2C6_BASE_NS) + /** Peripheral I2C7 base address */ + #define I2C7_BASE (0x50098000u) + /** Peripheral I2C7 base address */ + #define I2C7_BASE_NS (0x40098000u) + /** Peripheral I2C7 base pointer */ + #define I2C7 ((I2C_Type *)I2C7_BASE) + /** Peripheral I2C7 base pointer */ + #define I2C7_NS ((I2C_Type *)I2C7_BASE_NS) + /** Array initializer of I2C peripheral base addresses */ + #define I2C_BASE_ADDRS { I2C0_BASE, I2C1_BASE, I2C2_BASE, I2C3_BASE, I2C4_BASE, I2C5_BASE, I2C6_BASE, I2C7_BASE } + /** Array initializer of I2C peripheral base pointers */ + #define I2C_BASE_PTRS { I2C0, I2C1, I2C2, I2C3, I2C4, I2C5, I2C6, I2C7 } + /** Array initializer of I2C peripheral base addresses */ + #define I2C_BASE_ADDRS_NS { I2C0_BASE_NS, I2C1_BASE_NS, I2C2_BASE_NS, I2C3_BASE_NS, I2C4_BASE_NS, I2C5_BASE_NS, I2C6_BASE_NS, I2C7_BASE_NS } + /** Array initializer of I2C peripheral base pointers */ + #define I2C_BASE_PTRS_NS { I2C0_NS, I2C1_NS, I2C2_NS, I2C3_NS, I2C4_NS, I2C5_NS, I2C6_NS, I2C7_NS } +#else + /** Peripheral I2C0 base address */ + #define I2C0_BASE (0x40086000u) + /** Peripheral I2C0 base pointer */ + #define I2C0 ((I2C_Type *)I2C0_BASE) + /** Peripheral I2C1 base address */ + #define I2C1_BASE (0x40087000u) + /** Peripheral I2C1 base pointer */ + #define I2C1 ((I2C_Type *)I2C1_BASE) + /** Peripheral I2C2 base address */ + #define I2C2_BASE (0x40088000u) + /** Peripheral I2C2 base pointer */ + #define I2C2 ((I2C_Type *)I2C2_BASE) + /** Peripheral I2C3 base address */ + #define I2C3_BASE (0x40089000u) + /** Peripheral I2C3 base pointer */ + #define I2C3 ((I2C_Type *)I2C3_BASE) + /** Peripheral I2C4 base address */ + #define I2C4_BASE (0x4008A000u) + /** Peripheral I2C4 base pointer */ + #define I2C4 ((I2C_Type *)I2C4_BASE) + /** Peripheral I2C5 base address */ + #define I2C5_BASE (0x40096000u) + /** Peripheral I2C5 base pointer */ + #define I2C5 ((I2C_Type *)I2C5_BASE) + /** Peripheral I2C6 base address */ + #define I2C6_BASE (0x40097000u) + /** Peripheral I2C6 base pointer */ + #define I2C6 ((I2C_Type *)I2C6_BASE) + /** Peripheral I2C7 base address */ + #define I2C7_BASE (0x40098000u) + /** Peripheral I2C7 base pointer */ + #define I2C7 ((I2C_Type *)I2C7_BASE) + /** Array initializer of I2C peripheral base addresses */ + #define I2C_BASE_ADDRS { I2C0_BASE, I2C1_BASE, I2C2_BASE, I2C3_BASE, I2C4_BASE, I2C5_BASE, I2C6_BASE, I2C7_BASE } + /** Array initializer of I2C peripheral base pointers */ + #define I2C_BASE_PTRS { I2C0, I2C1, I2C2, I2C3, I2C4, I2C5, I2C6, I2C7 } +#endif +/** Interrupt vectors for the I2C peripheral type */ +#define I2C_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn } + +/*! + * @} + */ /* end of group I2C_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- I2S Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer + * @{ + */ + +/** I2S - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[3072]; + __IO uint32_t CFG1; /**< Configuration register 1 for the primary channel pair., offset: 0xC00 */ + __IO uint32_t CFG2; /**< Configuration register 2 for the primary channel pair., offset: 0xC04 */ + __IO uint32_t STAT; /**< Status register for the primary channel pair., offset: 0xC08 */ + uint8_t RESERVED_1[16]; + __IO uint32_t DIV; /**< Clock divider, used by all channel pairs., offset: 0xC1C */ + struct { /* offset: 0xC20, array step: 0x20 */ + __IO uint32_t PCFG1; /**< Configuration register 1 for channel pair, array offset: 0xC20, array step: 0x20 */ + __IO uint32_t PCFG2; /**< Configuration register 2 for channel pair, array offset: 0xC24, array step: 0x20 */ + __IO uint32_t PSTAT; /**< Status register for channel pair, array offset: 0xC28, array step: 0x20 */ + uint8_t RESERVED_0[20]; + } SECCHANNEL[3]; + uint8_t RESERVED_2[384]; + __IO uint32_t FIFOCFG; /**< FIFO configuration and enable register., offset: 0xE00 */ + __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */ + __IO uint32_t FIFOTRIG; /**< FIFO trigger settings for interrupt and DMA request., offset: 0xE08 */ + uint8_t RESERVED_3[4]; + __IO uint32_t FIFOINTENSET; /**< FIFO interrupt enable set (enable) and read register., offset: 0xE10 */ + __IO uint32_t FIFOINTENCLR; /**< FIFO interrupt enable clear (disable) and read register., offset: 0xE14 */ + __I uint32_t FIFOINTSTAT; /**< FIFO interrupt status register., offset: 0xE18 */ + uint8_t RESERVED_4[4]; + __O uint32_t FIFOWR; /**< FIFO write data., offset: 0xE20 */ + __O uint32_t FIFOWR48H; /**< FIFO write data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA., offset: 0xE24 */ + uint8_t RESERVED_5[8]; + __I uint32_t FIFORD; /**< FIFO read data., offset: 0xE30 */ + __I uint32_t FIFORD48H; /**< FIFO read data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA., offset: 0xE34 */ + uint8_t RESERVED_6[8]; + __I uint32_t FIFORDNOPOP; /**< FIFO data read with no FIFO pop., offset: 0xE40 */ + __I uint32_t FIFORD48HNOPOP; /**< FIFO data read for upper data bits with no FIFO pop. May only be used if the I2S is configured for 2x 24-bit data and not using DMA., offset: 0xE44 */ + __I uint32_t FIFOSIZE; /**< FIFO size register, offset: 0xE48 */ + uint8_t RESERVED_7[432]; + __I uint32_t ID; /**< I2S Module identification, offset: 0xFFC */ +} I2S_Type; + +/* ---------------------------------------------------------------------------- + -- I2S Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup I2S_Register_Masks I2S Register Masks + * @{ + */ + +/*! @name CFG1 - Configuration register 1 for the primary channel pair. */ +/*! @{ */ + +#define I2S_CFG1_MAINENABLE_MASK (0x1U) +#define I2S_CFG1_MAINENABLE_SHIFT (0U) +/*! MAINENABLE - Main enable for I 2S function in this Flexcomm + * 0b0..All I 2S channel pairs in this Flexcomm are disabled and the internal state machines, counters, and flags + * are reset. No other channel pairs can be enabled. + * 0b1..This I 2S channel pair is enabled. Other channel pairs in this Flexcomm may be enabled in their individual PAIRENABLE bits. + */ +#define I2S_CFG1_MAINENABLE(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_MAINENABLE_SHIFT)) & I2S_CFG1_MAINENABLE_MASK) + +#define I2S_CFG1_DATAPAUSE_MASK (0x2U) +#define I2S_CFG1_DATAPAUSE_SHIFT (1U) +/*! DATAPAUSE - Data flow Pause. Allows pausing data flow between the I2S serializer/deserializer + * and the FIFO. This could be done in order to change streams, or while restarting after a data + * underflow or overflow. When paused, FIFO operations can be done without corrupting data that is + * in the process of being sent or received. Once a data pause has been requested, the interface + * may need to complete sending data that was in progress before interrupting the flow of data. + * Software must check that the pause is actually in effect before taking action. This is done by + * monitoring the DATAPAUSED flag in the STAT register. When DATAPAUSE is cleared, data transfer + * will resume at the beginning of the next frame. + * 0b0..Normal operation, or resuming normal operation at the next frame if the I2S has already been paused. + * 0b1..A pause in the data flow is being requested. It is in effect when DATAPAUSED in STAT = 1. + */ +#define I2S_CFG1_DATAPAUSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_DATAPAUSE_SHIFT)) & I2S_CFG1_DATAPAUSE_MASK) + +#define I2S_CFG1_PAIRCOUNT_MASK (0xCU) +#define I2S_CFG1_PAIRCOUNT_SHIFT (2U) +/*! PAIRCOUNT - Provides the number of I2S channel pairs in this Flexcomm This is a read-only field + * whose value may be different in other Flexcomms. 00 = there is 1 I2S channel pair in this + * Flexcomm. 01 = there are 2 I2S channel pairs in this Flexcomm. 10 = there are 3 I2S channel pairs + * in this Flexcomm. 11 = there are 4 I2S channel pairs in this Flexcomm. + * 0b00..1 I2S channel pairs in this flexcomm + * 0b01..2 I2S channel pairs in this flexcomm + * 0b10..3 I2S channel pairs in this flexcomm + * 0b11..4 I2S channel pairs in this flexcomm + */ +#define I2S_CFG1_PAIRCOUNT(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_PAIRCOUNT_SHIFT)) & I2S_CFG1_PAIRCOUNT_MASK) + +#define I2S_CFG1_MSTSLVCFG_MASK (0x30U) +#define I2S_CFG1_MSTSLVCFG_SHIFT (4U) +/*! MSTSLVCFG - Master / slave configuration selection, determining how SCK and WS are used by all channel pairs in this Flexcomm. + * 0b00..Normal slave mode, the default mode. SCK and WS are received from a master and used to transmit or receive data. + * 0b01..WS synchronized master. WS is received from another master and used to synchronize the generation of + * SCK, when divided from the Flexcomm function clock. + * 0b10..Master using an existing SCK. SCK is received and used directly to generate WS, as well as transmitting or receiving data. + * 0b11..Normal master mode. SCK and WS are generated so they can be sent to one or more slave devices. + */ +#define I2S_CFG1_MSTSLVCFG(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_MSTSLVCFG_SHIFT)) & I2S_CFG1_MSTSLVCFG_MASK) + +#define I2S_CFG1_MODE_MASK (0xC0U) +#define I2S_CFG1_MODE_SHIFT (6U) +/*! MODE - Selects the basic I2S operating mode. Other configurations modify this to obtain all + * supported cases. See Formats and modes for examples. + * 0b00..I2S mode a.k.a. 'classic' mode. WS has a 50% duty cycle, with (for each enabled channel pair) one piece + * of left channel data occurring during the first phase, and one pieces of right channel data occurring + * during the second phase. In this mode, the data region begins one clock after the leading WS edge for the + * frame. For a 50% WS duty cycle, FRAMELEN must define an even number of I2S clocks for the frame. If + * FRAMELEN defines an odd number of clocks per frame, the extra clock will occur on the right. + * 0b01..DSP mode where WS has a 50% duty cycle. See remark for mode 0. + * 0b10..DSP mode where WS has a one clock long pulse at the beginning of each data frame. + * 0b11..DSP mode where WS has a one data slot long pulse at the beginning of each data frame. + */ +#define I2S_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_MODE_SHIFT)) & I2S_CFG1_MODE_MASK) + +#define I2S_CFG1_RIGHTLOW_MASK (0x100U) +#define I2S_CFG1_RIGHTLOW_SHIFT (8U) +/*! RIGHTLOW - Right channel data is in the Low portion of FIFO data. Essentially, this swaps left + * and right channel data as it is transferred to or from the FIFO. This bit is not used if the + * data width is greater than 24 bits or if PDMDATA = 1. Note that if the ONECHANNEL field (bit 10 + * of this register) = 1, the one channel to be used is the nominally the left channel. POSITION + * can still place that data in the frame where right channel data is normally located. if all + * enabled channel pairs have ONECHANNEL = 1, then RIGHTLOW = 1 is not allowed. + * 0b0..The right channel is taken from the high part of the FIFO data. For example, when data is 16 bits, FIFO + * bits 31:16 are used for the right channel. + * 0b1..The right channel is taken from the low part of the FIFO data. For example, when data is 16 bits, FIFO + * bits 15:0 are used for the right channel. + */ +#define I2S_CFG1_RIGHTLOW(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_RIGHTLOW_SHIFT)) & I2S_CFG1_RIGHTLOW_MASK) + +#define I2S_CFG1_LEFTJUST_MASK (0x200U) +#define I2S_CFG1_LEFTJUST_SHIFT (9U) +/*! LEFTJUST - Left Justify data. + * 0b0..Data is transferred between the FIFO and the I2S serializer/deserializer right justified, i.e. starting + * from bit 0 and continuing to the position defined by DATALEN. This would correspond to right justified data + * in the stream on the data bus. + * 0b1..Data is transferred between the FIFO and the I2S serializer/deserializer left justified, i.e. starting + * from the MSB of the FIFO entry and continuing for the number of bits defined by DATALEN. This would + * correspond to left justified data in the stream on the data bus. + */ +#define I2S_CFG1_LEFTJUST(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_LEFTJUST_SHIFT)) & I2S_CFG1_LEFTJUST_MASK) + +#define I2S_CFG1_ONECHANNEL_MASK (0x400U) +#define I2S_CFG1_ONECHANNEL_SHIFT (10U) +/*! ONECHANNEL - Single channel mode. Applies to both transmit and receive. This configuration bit + * applies only to the first I2S channel pair. Other channel pairs may select this mode + * independently in their separate CFG1 registers. + * 0b0..I2S data for this channel pair is treated as left and right channels. + * 0b1..I2S data for this channel pair is treated as a single channel, functionally the left channel for this + * pair. In mode 0 only, the right side of the frame begins at POSITION = 0x100. This is because mode 0 makes a + * clear distinction between the left and right sides of the frame. When ONECHANNEL = 1, the single channel + * of data may be placed on the right by setting POSITION to 0x100 + the data position within the right side + * (e.g. 0x108 would place data starting at the 8th clock after the middle of the frame). In other modes, data + * for the single channel of data is placed at the clock defined by POSITION. + */ +#define I2S_CFG1_ONECHANNEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_ONECHANNEL_SHIFT)) & I2S_CFG1_ONECHANNEL_MASK) + +#define I2S_CFG1_SCK_POL_MASK (0x1000U) +#define I2S_CFG1_SCK_POL_SHIFT (12U) +/*! SCK_POL - SCK polarity. + * 0b0..Data is launched on SCK falling edges and sampled on SCK rising edges (standard for I2S). + * 0b1..Data is launched on SCK rising edges and sampled on SCK falling edges. + */ +#define I2S_CFG1_SCK_POL(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_SCK_POL_SHIFT)) & I2S_CFG1_SCK_POL_MASK) + +#define I2S_CFG1_WS_POL_MASK (0x2000U) +#define I2S_CFG1_WS_POL_SHIFT (13U) +/*! WS_POL - WS polarity. + * 0b0..Data frames begin at a falling edge of WS (standard for classic I2S). + * 0b1..WS is inverted, resulting in a data frame beginning at a rising edge of WS (standard for most 'non-classic' variations of I2S). + */ +#define I2S_CFG1_WS_POL(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_WS_POL_SHIFT)) & I2S_CFG1_WS_POL_MASK) + +#define I2S_CFG1_DATALEN_MASK (0x1F0000U) +#define I2S_CFG1_DATALEN_SHIFT (16U) +/*! DATALEN - Data Length, minus 1 encoded, defines the number of data bits to be transmitted or + * received for all I2S channel pairs in this Flexcomm. Note that data is only driven to or received + * from SDA for the number of bits defined by DATALEN. DATALEN is also used in these ways by the + * I2S: Determines the size of data transfers between the FIFO and the I2S + * serializer/deserializer. See FIFO buffer configurations and usage In mode 1, 2, and 3, determines the location of + * right data following left data in the frame. In mode 3 (where WS has a one data slot long pulse + * at the beginning of each data frame) determines the duration of the WS pulse. Values: 0x00 to + * 0x02 = not supported 0x03 = data is 4 bits in length 0x04 = data is 5 bits in length 0x1F = + * data is 32 bits in length + */ +#define I2S_CFG1_DATALEN(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_DATALEN_SHIFT)) & I2S_CFG1_DATALEN_MASK) +/*! @} */ + +/*! @name CFG2 - Configuration register 2 for the primary channel pair. */ +/*! @{ */ + +#define I2S_CFG2_FRAMELEN_MASK (0x7FFU) +#define I2S_CFG2_FRAMELEN_SHIFT (0U) +/*! FRAMELEN - Frame Length, minus 1 encoded, defines the number of clocks and data bits in the + * frames that this channel pair participates in. See Frame format. 0x000 to 0x002 = not supported + * 0x003 = frame is 4 bits in total length 0x004 = frame is 5 bits in total length 0x7FF = frame is + * 2048 bits in total length if FRAMELEN is an defines an odd length frame (e.g. 33 clocks) in + * mode 0 or 1, the extra clock appears in the right half. When MODE = 3, FRAMELEN must be larger + * than DATALEN in order for the WS pulse to be generated correctly. + */ +#define I2S_CFG2_FRAMELEN(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG2_FRAMELEN_SHIFT)) & I2S_CFG2_FRAMELEN_MASK) + +#define I2S_CFG2_POSITION_MASK (0x1FF0000U) +#define I2S_CFG2_POSITION_SHIFT (16U) +/*! POSITION - Data Position. Defines the location within the frame of the data for this channel + * pair. POSITION + DATALEN must be less than FRAMELEN. See Frame format. When MODE = 0, POSITION + * defines the location of data in both the left phase and right phase, starting one clock after + * the WS edge. In other modes, POSITION defines the location of data within the entire frame. + * ONECHANNEL = 1 while MODE = 0 is a special case, see the description of ONECHANNEL. The + * combination of DATALEN and the POSITION fields of all channel pairs must be made such that the channels + * do not overlap within the frame. 0x000 = data begins at bit position 0 (the first bit + * position) within the frame or WS phase. 0x001 = data begins at bit position 1 within the frame or WS + * phase. 0x002 = data begins at bit position 2 within the frame or WS phase. + */ +#define I2S_CFG2_POSITION(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG2_POSITION_SHIFT)) & I2S_CFG2_POSITION_MASK) +/*! @} */ + +/*! @name STAT - Status register for the primary channel pair. */ +/*! @{ */ + +#define I2S_STAT_BUSY_MASK (0x1U) +#define I2S_STAT_BUSY_SHIFT (0U) +/*! BUSY - Busy status for the primary channel pair. Other BUSY flags may be found in the STAT register for each channel pair. + * 0b0..The transmitter/receiver for channel pair is currently idle. + * 0b1..The transmitter/receiver for channel pair is currently processing data. + */ +#define I2S_STAT_BUSY(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_BUSY_SHIFT)) & I2S_STAT_BUSY_MASK) + +#define I2S_STAT_SLVFRMERR_MASK (0x2U) +#define I2S_STAT_SLVFRMERR_SHIFT (1U) +/*! SLVFRMERR - Slave Frame Error flag. This applies when at least one channel pair is operating as + * a slave. An error indicates that the incoming WS signal did not transition as expected due to + * a mismatch between FRAMELEN and the actual incoming I2S stream. + * 0b0..No error has been recorded. + * 0b1..An error has been recorded for some channel pair that is operating in slave mode. ERROR is cleared by writing a 1 to this bit position. + */ +#define I2S_STAT_SLVFRMERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_SLVFRMERR_SHIFT)) & I2S_STAT_SLVFRMERR_MASK) + +#define I2S_STAT_LR_MASK (0x4U) +#define I2S_STAT_LR_SHIFT (2U) +/*! LR - Left/Right indication. This flag is considered to be a debugging aid and is not expected to + * be used by an I2S driver. Valid when one channel pair is busy. Indicates left or right data + * being processed for the currently busy channel pair. + * 0b0..Left channel. + * 0b1..Right channel. + */ +#define I2S_STAT_LR(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_LR_SHIFT)) & I2S_STAT_LR_MASK) + +#define I2S_STAT_DATAPAUSED_MASK (0x8U) +#define I2S_STAT_DATAPAUSED_SHIFT (3U) +/*! DATAPAUSED - Data Paused status flag. Applies to all I2S channels + * 0b0..Data is not currently paused. A data pause may have been requested but is not yet in force, waiting for + * an allowed pause point. Refer to the description of the DATAPAUSE control bit in the CFG1 register. + * 0b1..A data pause has been requested and is now in force. + */ +#define I2S_STAT_DATAPAUSED(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_DATAPAUSED_SHIFT)) & I2S_STAT_DATAPAUSED_MASK) +/*! @} */ + +/*! @name DIV - Clock divider, used by all channel pairs. */ +/*! @{ */ + +#define I2S_DIV_DIV_MASK (0xFFFU) +#define I2S_DIV_DIV_SHIFT (0U) +/*! DIV - This field controls how this I2S block uses the Flexcomm function clock. 0x000 = The + * Flexcomm function clock is used directly. 0x001 = The Flexcomm function clock is divided by 2. + * 0x002 = The Flexcomm function clock is divided by 3. 0xFFF = The Flexcomm function clock is + * divided by 4,096. + */ +#define I2S_DIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_DIV_DIV_SHIFT)) & I2S_DIV_DIV_MASK) +/*! @} */ + +/*! @name SECCHANNEL_PCFG1 - Configuration register 1 for channel pair */ +/*! @{ */ + +#define I2S_SECCHANNEL_PCFG1_PAIRENABLE_MASK (0x1U) +#define I2S_SECCHANNEL_PCFG1_PAIRENABLE_SHIFT (0U) +/*! PAIRENABLE - Enable for this channel pair. + * 0b0..This I2S channel pair is disabled. + * 0b1..This I2S channel pair is enabled. + */ +#define I2S_SECCHANNEL_PCFG1_PAIRENABLE(x) (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PCFG1_PAIRENABLE_SHIFT)) & I2S_SECCHANNEL_PCFG1_PAIRENABLE_MASK) + +#define I2S_SECCHANNEL_PCFG1_ONECHANNEL_MASK (0x400U) +#define I2S_SECCHANNEL_PCFG1_ONECHANNEL_SHIFT (10U) +/*! ONECHANNEL - Single channel mode. + * 0b0..I2S data for this channel pair is treated as left and right channels. + * 0b1..I2S data for this channel pair is treated as a single channel, functionally the left channel for this pair. + */ +#define I2S_SECCHANNEL_PCFG1_ONECHANNEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PCFG1_ONECHANNEL_SHIFT)) & I2S_SECCHANNEL_PCFG1_ONECHANNEL_MASK) +/*! @} */ + +/* The count of I2S_SECCHANNEL_PCFG1 */ +#define I2S_SECCHANNEL_PCFG1_COUNT (3U) + +/*! @name SECCHANNEL_PCFG2 - Configuration register 2 for channel pair */ +/*! @{ */ + +#define I2S_SECCHANNEL_PCFG2_POSITION_MASK (0x1FF0000U) +#define I2S_SECCHANNEL_PCFG2_POSITION_SHIFT (16U) +/*! POSITION - Data Position. + */ +#define I2S_SECCHANNEL_PCFG2_POSITION(x) (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PCFG2_POSITION_SHIFT)) & I2S_SECCHANNEL_PCFG2_POSITION_MASK) +/*! @} */ + +/* The count of I2S_SECCHANNEL_PCFG2 */ +#define I2S_SECCHANNEL_PCFG2_COUNT (3U) + +/*! @name SECCHANNEL_PSTAT - Status register for channel pair */ +/*! @{ */ + +#define I2S_SECCHANNEL_PSTAT_BUSY_MASK (0x1U) +#define I2S_SECCHANNEL_PSTAT_BUSY_SHIFT (0U) +/*! BUSY - Busy status for this channel pair. + * 0b0..The transmitter/receiver for this channel pair is currently idle. + * 0b1..The transmitter/receiver for this channel pair is currently processing data. + */ +#define I2S_SECCHANNEL_PSTAT_BUSY(x) (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PSTAT_BUSY_SHIFT)) & I2S_SECCHANNEL_PSTAT_BUSY_MASK) + +#define I2S_SECCHANNEL_PSTAT_SLVFRMERR_MASK (0x2U) +#define I2S_SECCHANNEL_PSTAT_SLVFRMERR_SHIFT (1U) +/*! SLVFRMERR - Save Frame Error flag. + */ +#define I2S_SECCHANNEL_PSTAT_SLVFRMERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PSTAT_SLVFRMERR_SHIFT)) & I2S_SECCHANNEL_PSTAT_SLVFRMERR_MASK) + +#define I2S_SECCHANNEL_PSTAT_LR_MASK (0x4U) +#define I2S_SECCHANNEL_PSTAT_LR_SHIFT (2U) +/*! LR - Left/Right indication. + */ +#define I2S_SECCHANNEL_PSTAT_LR(x) (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PSTAT_LR_SHIFT)) & I2S_SECCHANNEL_PSTAT_LR_MASK) + +#define I2S_SECCHANNEL_PSTAT_DATAPAUSED_MASK (0x8U) +#define I2S_SECCHANNEL_PSTAT_DATAPAUSED_SHIFT (3U) +/*! DATAPAUSED - Data Paused status flag. + * 0b0..Data is not currently paused. + * 0b1..A data pause has been requested and is now in force. + */ +#define I2S_SECCHANNEL_PSTAT_DATAPAUSED(x) (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PSTAT_DATAPAUSED_SHIFT)) & I2S_SECCHANNEL_PSTAT_DATAPAUSED_MASK) +/*! @} */ + +/* The count of I2S_SECCHANNEL_PSTAT */ +#define I2S_SECCHANNEL_PSTAT_COUNT (3U) + +/*! @name FIFOCFG - FIFO configuration and enable register. */ +/*! @{ */ + +#define I2S_FIFOCFG_ENABLETX_MASK (0x1U) +#define I2S_FIFOCFG_ENABLETX_SHIFT (0U) +/*! ENABLETX - Enable the transmit FIFO. + * 0b0..The transmit FIFO is not enabled. + * 0b1..The transmit FIFO is enabled. + */ +#define I2S_FIFOCFG_ENABLETX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_ENABLETX_SHIFT)) & I2S_FIFOCFG_ENABLETX_MASK) + +#define I2S_FIFOCFG_ENABLERX_MASK (0x2U) +#define I2S_FIFOCFG_ENABLERX_SHIFT (1U) +/*! ENABLERX - Enable the receive FIFO. + * 0b0..The receive FIFO is not enabled. + * 0b1..The receive FIFO is enabled. + */ +#define I2S_FIFOCFG_ENABLERX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_ENABLERX_SHIFT)) & I2S_FIFOCFG_ENABLERX_MASK) + +#define I2S_FIFOCFG_TXI2SE0_MASK (0x4U) +#define I2S_FIFOCFG_TXI2SE0_SHIFT (2U) +/*! TXI2SE0 - Transmit I2S empty 0. Determines the value sent by the I2S in transmit mode if the TX + * FIFO becomes empty. This value is sent repeatedly until the I2S is paused, the error is + * cleared, new data is provided, and the I2S is un-paused. + * 0b0..If the TX FIFO becomes empty, the last value is sent. This setting may be used when the data length is 24 + * bits or less, or when MONO = 1 for this channel pair. + * 0b1..If the TX FIFO becomes empty, 0 is sent. Use if the data length is greater than 24 bits or if zero fill is preferred. + */ +#define I2S_FIFOCFG_TXI2SE0(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_TXI2SE0_SHIFT)) & I2S_FIFOCFG_TXI2SE0_MASK) + +#define I2S_FIFOCFG_PACK48_MASK (0x8U) +#define I2S_FIFOCFG_PACK48_SHIFT (3U) +/*! PACK48 - Packing format for 48-bit data. This relates to how data is entered into or taken from the FIFO by software or DMA. + * 0b0..48-bit I2S FIFO entries are handled as all 24-bit values. + * 0b1..48-bit I2S FIFO entries are handled as alternating 32-bit and 16-bit values. + */ +#define I2S_FIFOCFG_PACK48(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_PACK48_SHIFT)) & I2S_FIFOCFG_PACK48_MASK) + +#define I2S_FIFOCFG_SIZE_MASK (0x30U) +#define I2S_FIFOCFG_SIZE_SHIFT (4U) +/*! SIZE - FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 + * entries of 8 bits. 0x1, 0x2, 0x3 = not applicable to USART. + */ +#define I2S_FIFOCFG_SIZE(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_SIZE_SHIFT)) & I2S_FIFOCFG_SIZE_MASK) + +#define I2S_FIFOCFG_DMATX_MASK (0x1000U) +#define I2S_FIFOCFG_DMATX_SHIFT (12U) +/*! DMATX - DMA configuration for transmit. + * 0b0..DMA is not used for the transmit function. + * 0b1..Trigger DMA for the transmit function if the FIFO is not full. Generally, data interrupts would be disabled if DMA is enabled. + */ +#define I2S_FIFOCFG_DMATX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_DMATX_SHIFT)) & I2S_FIFOCFG_DMATX_MASK) + +#define I2S_FIFOCFG_DMARX_MASK (0x2000U) +#define I2S_FIFOCFG_DMARX_SHIFT (13U) +/*! DMARX - DMA configuration for receive. + * 0b0..DMA is not used for the receive function. + * 0b1..Trigger DMA for the receive function if the FIFO is not empty. Generally, data interrupts would be disabled if DMA is enabled. + */ +#define I2S_FIFOCFG_DMARX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_DMARX_SHIFT)) & I2S_FIFOCFG_DMARX_MASK) + +#define I2S_FIFOCFG_WAKETX_MASK (0x4000U) +#define I2S_FIFOCFG_WAKETX_SHIFT (14U) +/*! WAKETX - Wake-up for transmit FIFO level. This allows the device to be woken from reduced power + * modes (up to power-down, as long as the peripheral function works in that power mode) without + * enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The + * CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware + * Wake-up control register. + * 0b0..Only enabled interrupts will wake up the device form reduced power modes. + * 0b1..A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by TXLVL in + * FIFOTRIG, even when the TXLVL interrupt is not enabled. + */ +#define I2S_FIFOCFG_WAKETX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_WAKETX_SHIFT)) & I2S_FIFOCFG_WAKETX_MASK) + +#define I2S_FIFOCFG_WAKERX_MASK (0x8000U) +#define I2S_FIFOCFG_WAKERX_SHIFT (15U) +/*! WAKERX - Wake-up for receive FIFO level. This allows the device to be woken from reduced power + * modes (up to power-down, as long as the peripheral function works in that power mode) without + * enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The + * CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware + * Wake-up control register. + * 0b0..Only enabled interrupts will wake up the device form reduced power modes. + * 0b1..A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by RXLVL in + * FIFOTRIG, even when the RXLVL interrupt is not enabled. + */ +#define I2S_FIFOCFG_WAKERX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_WAKERX_SHIFT)) & I2S_FIFOCFG_WAKERX_MASK) + +#define I2S_FIFOCFG_EMPTYTX_MASK (0x10000U) +#define I2S_FIFOCFG_EMPTYTX_SHIFT (16U) +/*! EMPTYTX - Empty command for the transmit FIFO. When a 1 is written to this bit, the TX FIFO is emptied. + */ +#define I2S_FIFOCFG_EMPTYTX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_EMPTYTX_SHIFT)) & I2S_FIFOCFG_EMPTYTX_MASK) + +#define I2S_FIFOCFG_EMPTYRX_MASK (0x20000U) +#define I2S_FIFOCFG_EMPTYRX_SHIFT (17U) +/*! EMPTYRX - Empty command for the receive FIFO. When a 1 is written to this bit, the RX FIFO is emptied. + */ +#define I2S_FIFOCFG_EMPTYRX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_EMPTYRX_SHIFT)) & I2S_FIFOCFG_EMPTYRX_MASK) +/*! @} */ + +/*! @name FIFOSTAT - FIFO status register. */ +/*! @{ */ + +#define I2S_FIFOSTAT_TXERR_MASK (0x1U) +#define I2S_FIFOSTAT_TXERR_SHIFT (0U) +/*! TXERR - TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow + * caused by pushing data into a full FIFO, or by an underflow if the FIFO is empty when data is + * needed. Cleared by writing a 1 to this bit. + */ +#define I2S_FIFOSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXERR_SHIFT)) & I2S_FIFOSTAT_TXERR_MASK) + +#define I2S_FIFOSTAT_RXERR_MASK (0x2U) +#define I2S_FIFOSTAT_RXERR_SHIFT (1U) +/*! RXERR - RX FIFO error. Will be set if a receive FIFO overflow occurs, caused by software or DMA + * not emptying the FIFO fast enough. Cleared by writing a 1 to this bit. + */ +#define I2S_FIFOSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXERR_SHIFT)) & I2S_FIFOSTAT_RXERR_MASK) + +#define I2S_FIFOSTAT_PERINT_MASK (0x8U) +#define I2S_FIFOSTAT_PERINT_SHIFT (3U) +/*! PERINT - Peripheral interrupt. When 1, this indicates that the peripheral function has asserted + * an interrupt. The details can be found by reading the peripheral's STAT register. + */ +#define I2S_FIFOSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_PERINT_SHIFT)) & I2S_FIFOSTAT_PERINT_MASK) + +#define I2S_FIFOSTAT_TXEMPTY_MASK (0x10U) +#define I2S_FIFOSTAT_TXEMPTY_SHIFT (4U) +/*! TXEMPTY - Transmit FIFO empty. When 1, the transmit FIFO is empty. The peripheral may still be processing the last piece of data. + */ +#define I2S_FIFOSTAT_TXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXEMPTY_SHIFT)) & I2S_FIFOSTAT_TXEMPTY_MASK) + +#define I2S_FIFOSTAT_TXNOTFULL_MASK (0x20U) +#define I2S_FIFOSTAT_TXNOTFULL_SHIFT (5U) +/*! TXNOTFULL - Transmit FIFO not full. When 1, the transmit FIFO is not full, so more data can be + * written. When 0, the transmit FIFO is full and another write would cause it to overflow. + */ +#define I2S_FIFOSTAT_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXNOTFULL_SHIFT)) & I2S_FIFOSTAT_TXNOTFULL_MASK) + +#define I2S_FIFOSTAT_RXNOTEMPTY_MASK (0x40U) +#define I2S_FIFOSTAT_RXNOTEMPTY_SHIFT (6U) +/*! RXNOTEMPTY - Receive FIFO not empty. When 1, the receive FIFO is not empty, so data can be read. When 0, the receive FIFO is empty. + */ +#define I2S_FIFOSTAT_RXNOTEMPTY(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXNOTEMPTY_SHIFT)) & I2S_FIFOSTAT_RXNOTEMPTY_MASK) + +#define I2S_FIFOSTAT_RXFULL_MASK (0x80U) +#define I2S_FIFOSTAT_RXFULL_SHIFT (7U) +/*! RXFULL - Receive FIFO full. When 1, the receive FIFO is full. Data needs to be read out to + * prevent the peripheral from causing an overflow. + */ +#define I2S_FIFOSTAT_RXFULL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXFULL_SHIFT)) & I2S_FIFOSTAT_RXFULL_MASK) + +#define I2S_FIFOSTAT_TXLVL_MASK (0x1F00U) +#define I2S_FIFOSTAT_TXLVL_SHIFT (8U) +/*! TXLVL - Transmit FIFO current level. A 0 means the TX FIFO is currently empty, and the TXEMPTY + * and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at + * the point where the read occurs. If the TX FIFO is full, the TXEMPTY and TXNOTFULL flags will be + * 0. + */ +#define I2S_FIFOSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXLVL_SHIFT)) & I2S_FIFOSTAT_TXLVL_MASK) + +#define I2S_FIFOSTAT_RXLVL_MASK (0x1F0000U) +#define I2S_FIFOSTAT_RXLVL_SHIFT (16U) +/*! RXLVL - Receive FIFO current level. A 0 means the RX FIFO is currently empty, and the RXFULL and + * RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the + * point where the read occurs. If the RX FIFO is full, the RXFULL and RXNOTEMPTY flags will be + * 1. + */ +#define I2S_FIFOSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXLVL_SHIFT)) & I2S_FIFOSTAT_RXLVL_MASK) +/*! @} */ + +/*! @name FIFOTRIG - FIFO trigger settings for interrupt and DMA request. */ +/*! @{ */ + +#define I2S_FIFOTRIG_TXLVLENA_MASK (0x1U) +#define I2S_FIFOTRIG_TXLVLENA_SHIFT (0U) +/*! TXLVLENA - Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled + * in FIFOINTENSET, or a DMA trigger if DMATX in FIFOCFG is set. + * 0b0..Transmit FIFO level does not generate a FIFO level trigger. + * 0b1..An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL field in this register. + */ +#define I2S_FIFOTRIG_TXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_TXLVLENA_SHIFT)) & I2S_FIFOTRIG_TXLVLENA_MASK) + +#define I2S_FIFOTRIG_RXLVLENA_MASK (0x2U) +#define I2S_FIFOTRIG_RXLVLENA_SHIFT (1U) +/*! RXLVLENA - Receive FIFO level trigger enable. This trigger will become an interrupt if enabled + * in FIFOINTENSET, or a DMA trigger if DMARX in FIFOCFG is set. + * 0b0..Receive FIFO level does not generate a FIFO level trigger. + * 0b1..An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL field in this register. + */ +#define I2S_FIFOTRIG_RXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_RXLVLENA_SHIFT)) & I2S_FIFOTRIG_RXLVLENA_MASK) + +#define I2S_FIFOTRIG_TXLVL_MASK (0xF00U) +#define I2S_FIFOTRIG_TXLVL_SHIFT (8U) +/*! TXLVL - Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled + * to do so, the FIFO level can wake up the device just enough to perform DMA, then return to + * the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the TX FIFO + * becomes empty. 1 = trigger when the TX FIFO level decreases to one entry. 15 = trigger when the TX + * FIFO level decreases to 15 entries (is no longer full). + */ +#define I2S_FIFOTRIG_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_TXLVL_SHIFT)) & I2S_FIFOTRIG_TXLVL_MASK) + +#define I2S_FIFOTRIG_RXLVL_MASK (0xF0000U) +#define I2S_FIFOTRIG_RXLVL_SHIFT (16U) +/*! RXLVL - Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data + * is received. This field is used only when RXLVLENA = 1. If enabled to do so, the FIFO level + * can wake up the device just enough to perform DMA, then return to the reduced power mode. See + * Hardware Wake-up control register. 0 = trigger when the RX FIFO has received one entry (is no + * longer empty). 1 = trigger when the RX FIFO has received two entries. 15 = trigger when the RX + * FIFO has received 16 entries (has become full). + */ +#define I2S_FIFOTRIG_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_RXLVL_SHIFT)) & I2S_FIFOTRIG_RXLVL_MASK) +/*! @} */ + +/*! @name FIFOINTENSET - FIFO interrupt enable set (enable) and read register. */ +/*! @{ */ + +#define I2S_FIFOINTENSET_TXERR_MASK (0x1U) +#define I2S_FIFOINTENSET_TXERR_SHIFT (0U) +/*! TXERR - Determines whether an interrupt occurs when a transmit error occurs, based on the TXERR flag in the FIFOSTAT register. + * 0b0..No interrupt will be generated for a transmit error. + * 0b1..An interrupt will be generated when a transmit error occurs. + */ +#define I2S_FIFOINTENSET_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_TXERR_SHIFT)) & I2S_FIFOINTENSET_TXERR_MASK) + +#define I2S_FIFOINTENSET_RXERR_MASK (0x2U) +#define I2S_FIFOINTENSET_RXERR_SHIFT (1U) +/*! RXERR - Determines whether an interrupt occurs when a receive error occurs, based on the RXERR flag in the FIFOSTAT register. + * 0b0..No interrupt will be generated for a receive error. + * 0b1..An interrupt will be generated when a receive error occurs. + */ +#define I2S_FIFOINTENSET_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_RXERR_SHIFT)) & I2S_FIFOINTENSET_RXERR_MASK) + +#define I2S_FIFOINTENSET_TXLVL_MASK (0x4U) +#define I2S_FIFOINTENSET_TXLVL_SHIFT (2U) +/*! TXLVL - Determines whether an interrupt occurs when a the transmit FIFO reaches the level + * specified by the TXLVL field in the FIFOTRIG register. + * 0b0..No interrupt will be generated based on the TX FIFO level. + * 0b1..If TXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the TX FIFO level decreases + * to the level specified by TXLVL in the FIFOTRIG register. + */ +#define I2S_FIFOINTENSET_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_TXLVL_SHIFT)) & I2S_FIFOINTENSET_TXLVL_MASK) + +#define I2S_FIFOINTENSET_RXLVL_MASK (0x8U) +#define I2S_FIFOINTENSET_RXLVL_SHIFT (3U) +/*! RXLVL - Determines whether an interrupt occurs when a the receive FIFO reaches the level + * specified by the TXLVL field in the FIFOTRIG register. + * 0b0..No interrupt will be generated based on the RX FIFO level. + * 0b1..If RXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the when the RX FIFO level + * increases to the level specified by RXLVL in the FIFOTRIG register. + */ +#define I2S_FIFOINTENSET_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_RXLVL_SHIFT)) & I2S_FIFOINTENSET_RXLVL_MASK) +/*! @} */ + +/*! @name FIFOINTENCLR - FIFO interrupt enable clear (disable) and read register. */ +/*! @{ */ + +#define I2S_FIFOINTENCLR_TXERR_MASK (0x1U) +#define I2S_FIFOINTENCLR_TXERR_SHIFT (0U) +/*! TXERR - Writing one clears the corresponding bits in the FIFOINTENSET register. + */ +#define I2S_FIFOINTENCLR_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_TXERR_SHIFT)) & I2S_FIFOINTENCLR_TXERR_MASK) + +#define I2S_FIFOINTENCLR_RXERR_MASK (0x2U) +#define I2S_FIFOINTENCLR_RXERR_SHIFT (1U) +/*! RXERR - Writing one clears the corresponding bits in the FIFOINTENSET register. + */ +#define I2S_FIFOINTENCLR_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_RXERR_SHIFT)) & I2S_FIFOINTENCLR_RXERR_MASK) + +#define I2S_FIFOINTENCLR_TXLVL_MASK (0x4U) +#define I2S_FIFOINTENCLR_TXLVL_SHIFT (2U) +/*! TXLVL - Writing one clears the corresponding bits in the FIFOINTENSET register. + */ +#define I2S_FIFOINTENCLR_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_TXLVL_SHIFT)) & I2S_FIFOINTENCLR_TXLVL_MASK) + +#define I2S_FIFOINTENCLR_RXLVL_MASK (0x8U) +#define I2S_FIFOINTENCLR_RXLVL_SHIFT (3U) +/*! RXLVL - Writing one clears the corresponding bits in the FIFOINTENSET register. + */ +#define I2S_FIFOINTENCLR_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_RXLVL_SHIFT)) & I2S_FIFOINTENCLR_RXLVL_MASK) +/*! @} */ + +/*! @name FIFOINTSTAT - FIFO interrupt status register. */ +/*! @{ */ + +#define I2S_FIFOINTSTAT_TXERR_MASK (0x1U) +#define I2S_FIFOINTSTAT_TXERR_SHIFT (0U) +/*! TXERR - TX FIFO error. + */ +#define I2S_FIFOINTSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_TXERR_SHIFT)) & I2S_FIFOINTSTAT_TXERR_MASK) + +#define I2S_FIFOINTSTAT_RXERR_MASK (0x2U) +#define I2S_FIFOINTSTAT_RXERR_SHIFT (1U) +/*! RXERR - RX FIFO error. + */ +#define I2S_FIFOINTSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_RXERR_SHIFT)) & I2S_FIFOINTSTAT_RXERR_MASK) + +#define I2S_FIFOINTSTAT_TXLVL_MASK (0x4U) +#define I2S_FIFOINTSTAT_TXLVL_SHIFT (2U) +/*! TXLVL - Transmit FIFO level interrupt. + */ +#define I2S_FIFOINTSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_TXLVL_SHIFT)) & I2S_FIFOINTSTAT_TXLVL_MASK) + +#define I2S_FIFOINTSTAT_RXLVL_MASK (0x8U) +#define I2S_FIFOINTSTAT_RXLVL_SHIFT (3U) +/*! RXLVL - Receive FIFO level interrupt. + */ +#define I2S_FIFOINTSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_RXLVL_SHIFT)) & I2S_FIFOINTSTAT_RXLVL_MASK) + +#define I2S_FIFOINTSTAT_PERINT_MASK (0x10U) +#define I2S_FIFOINTSTAT_PERINT_SHIFT (4U) +/*! PERINT - Peripheral interrupt. + */ +#define I2S_FIFOINTSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_PERINT_SHIFT)) & I2S_FIFOINTSTAT_PERINT_MASK) +/*! @} */ + +/*! @name FIFOWR - FIFO write data. */ +/*! @{ */ + +#define I2S_FIFOWR_TXDATA_MASK (0xFFFFFFFFU) +#define I2S_FIFOWR_TXDATA_SHIFT (0U) +/*! TXDATA - Transmit data to the FIFO. The number of bits used depends on configuration details. + */ +#define I2S_FIFOWR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOWR_TXDATA_SHIFT)) & I2S_FIFOWR_TXDATA_MASK) +/*! @} */ + +/*! @name FIFOWR48H - FIFO write data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA. */ +/*! @{ */ + +#define I2S_FIFOWR48H_TXDATA_MASK (0xFFFFFFU) +#define I2S_FIFOWR48H_TXDATA_SHIFT (0U) +/*! TXDATA - Transmit data to the FIFO. Whether this register is used and the number of bits used depends on configuration details. + */ +#define I2S_FIFOWR48H_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOWR48H_TXDATA_SHIFT)) & I2S_FIFOWR48H_TXDATA_MASK) +/*! @} */ + +/*! @name FIFORD - FIFO read data. */ +/*! @{ */ + +#define I2S_FIFORD_RXDATA_MASK (0xFFFFFFFFU) +#define I2S_FIFORD_RXDATA_SHIFT (0U) +/*! RXDATA - Received data from the FIFO. The number of bits used depends on configuration details. + */ +#define I2S_FIFORD_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORD_RXDATA_SHIFT)) & I2S_FIFORD_RXDATA_MASK) +/*! @} */ + +/*! @name FIFORD48H - FIFO read data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA. */ +/*! @{ */ + +#define I2S_FIFORD48H_RXDATA_MASK (0xFFFFFFU) +#define I2S_FIFORD48H_RXDATA_SHIFT (0U) +/*! RXDATA - Received data from the FIFO. Whether this register is used and the number of bits used depends on configuration details. + */ +#define I2S_FIFORD48H_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORD48H_RXDATA_SHIFT)) & I2S_FIFORD48H_RXDATA_MASK) +/*! @} */ + +/*! @name FIFORDNOPOP - FIFO data read with no FIFO pop. */ +/*! @{ */ + +#define I2S_FIFORDNOPOP_RXDATA_MASK (0xFFFFFFFFU) +#define I2S_FIFORDNOPOP_RXDATA_SHIFT (0U) +/*! RXDATA - Received data from the FIFO. + */ +#define I2S_FIFORDNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORDNOPOP_RXDATA_SHIFT)) & I2S_FIFORDNOPOP_RXDATA_MASK) +/*! @} */ + +/*! @name FIFORD48HNOPOP - FIFO data read for upper data bits with no FIFO pop. May only be used if the I2S is configured for 2x 24-bit data and not using DMA. */ +/*! @{ */ + +#define I2S_FIFORD48HNOPOP_RXDATA_MASK (0xFFFFFFU) +#define I2S_FIFORD48HNOPOP_RXDATA_SHIFT (0U) +/*! RXDATA - Received data from the FIFO. Whether this register is used and the number of bits used depends on configuration details. + */ +#define I2S_FIFORD48HNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORD48HNOPOP_RXDATA_SHIFT)) & I2S_FIFORD48HNOPOP_RXDATA_MASK) +/*! @} */ + +/*! @name FIFOSIZE - FIFO size register */ +/*! @{ */ + +#define I2S_FIFOSIZE_FIFOSIZE_MASK (0x1FU) +#define I2S_FIFOSIZE_FIFOSIZE_SHIFT (0U) +/*! FIFOSIZE - Provides the size of the FIFO for software. The size of the SPI FIFO is 8 entries. + */ +#define I2S_FIFOSIZE_FIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSIZE_FIFOSIZE_SHIFT)) & I2S_FIFOSIZE_FIFOSIZE_MASK) +/*! @} */ + +/*! @name ID - I2S Module identification */ +/*! @{ */ + +#define I2S_ID_APERTURE_MASK (0xFFU) +#define I2S_ID_APERTURE_SHIFT (0U) +/*! APERTURE - Aperture: encoded as (aperture size/4K) -1, so 0x00 means a 4K aperture. + */ +#define I2S_ID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << I2S_ID_APERTURE_SHIFT)) & I2S_ID_APERTURE_MASK) + +#define I2S_ID_MINOR_REV_MASK (0xF00U) +#define I2S_ID_MINOR_REV_SHIFT (8U) +/*! MINOR_REV - Minor revision of module implementation, starting at 0. + */ +#define I2S_ID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << I2S_ID_MINOR_REV_SHIFT)) & I2S_ID_MINOR_REV_MASK) + +#define I2S_ID_MAJOR_REV_MASK (0xF000U) +#define I2S_ID_MAJOR_REV_SHIFT (12U) +/*! MAJOR_REV - Major revision of module implementation, starting at 0. + */ +#define I2S_ID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << I2S_ID_MAJOR_REV_SHIFT)) & I2S_ID_MAJOR_REV_MASK) + +#define I2S_ID_ID_MASK (0xFFFF0000U) +#define I2S_ID_ID_SHIFT (16U) +/*! ID - Unique module identifier for this IP block. + */ +#define I2S_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << I2S_ID_ID_SHIFT)) & I2S_ID_ID_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group I2S_Register_Masks */ + + +/* I2S - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral I2S0 base address */ + #define I2S0_BASE (0x50086000u) + /** Peripheral I2S0 base address */ + #define I2S0_BASE_NS (0x40086000u) + /** Peripheral I2S0 base pointer */ + #define I2S0 ((I2S_Type *)I2S0_BASE) + /** Peripheral I2S0 base pointer */ + #define I2S0_NS ((I2S_Type *)I2S0_BASE_NS) + /** Peripheral I2S1 base address */ + #define I2S1_BASE (0x50087000u) + /** Peripheral I2S1 base address */ + #define I2S1_BASE_NS (0x40087000u) + /** Peripheral I2S1 base pointer */ + #define I2S1 ((I2S_Type *)I2S1_BASE) + /** Peripheral I2S1 base pointer */ + #define I2S1_NS ((I2S_Type *)I2S1_BASE_NS) + /** Peripheral I2S2 base address */ + #define I2S2_BASE (0x50088000u) + /** Peripheral I2S2 base address */ + #define I2S2_BASE_NS (0x40088000u) + /** Peripheral I2S2 base pointer */ + #define I2S2 ((I2S_Type *)I2S2_BASE) + /** Peripheral I2S2 base pointer */ + #define I2S2_NS ((I2S_Type *)I2S2_BASE_NS) + /** Peripheral I2S3 base address */ + #define I2S3_BASE (0x50089000u) + /** Peripheral I2S3 base address */ + #define I2S3_BASE_NS (0x40089000u) + /** Peripheral I2S3 base pointer */ + #define I2S3 ((I2S_Type *)I2S3_BASE) + /** Peripheral I2S3 base pointer */ + #define I2S3_NS ((I2S_Type *)I2S3_BASE_NS) + /** Peripheral I2S4 base address */ + #define I2S4_BASE (0x5008A000u) + /** Peripheral I2S4 base address */ + #define I2S4_BASE_NS (0x4008A000u) + /** Peripheral I2S4 base pointer */ + #define I2S4 ((I2S_Type *)I2S4_BASE) + /** Peripheral I2S4 base pointer */ + #define I2S4_NS ((I2S_Type *)I2S4_BASE_NS) + /** Peripheral I2S5 base address */ + #define I2S5_BASE (0x50096000u) + /** Peripheral I2S5 base address */ + #define I2S5_BASE_NS (0x40096000u) + /** Peripheral I2S5 base pointer */ + #define I2S5 ((I2S_Type *)I2S5_BASE) + /** Peripheral I2S5 base pointer */ + #define I2S5_NS ((I2S_Type *)I2S5_BASE_NS) + /** Peripheral I2S6 base address */ + #define I2S6_BASE (0x50097000u) + /** Peripheral I2S6 base address */ + #define I2S6_BASE_NS (0x40097000u) + /** Peripheral I2S6 base pointer */ + #define I2S6 ((I2S_Type *)I2S6_BASE) + /** Peripheral I2S6 base pointer */ + #define I2S6_NS ((I2S_Type *)I2S6_BASE_NS) + /** Peripheral I2S7 base address */ + #define I2S7_BASE (0x50098000u) + /** Peripheral I2S7 base address */ + #define I2S7_BASE_NS (0x40098000u) + /** Peripheral I2S7 base pointer */ + #define I2S7 ((I2S_Type *)I2S7_BASE) + /** Peripheral I2S7 base pointer */ + #define I2S7_NS ((I2S_Type *)I2S7_BASE_NS) + /** Array initializer of I2S peripheral base addresses */ + #define I2S_BASE_ADDRS { I2S0_BASE, I2S1_BASE, I2S2_BASE, I2S3_BASE, I2S4_BASE, I2S5_BASE, I2S6_BASE, I2S7_BASE } + /** Array initializer of I2S peripheral base pointers */ + #define I2S_BASE_PTRS { I2S0, I2S1, I2S2, I2S3, I2S4, I2S5, I2S6, I2S7 } + /** Array initializer of I2S peripheral base addresses */ + #define I2S_BASE_ADDRS_NS { I2S0_BASE_NS, I2S1_BASE_NS, I2S2_BASE_NS, I2S3_BASE_NS, I2S4_BASE_NS, I2S5_BASE_NS, I2S6_BASE_NS, I2S7_BASE_NS } + /** Array initializer of I2S peripheral base pointers */ + #define I2S_BASE_PTRS_NS { I2S0_NS, I2S1_NS, I2S2_NS, I2S3_NS, I2S4_NS, I2S5_NS, I2S6_NS, I2S7_NS } +#else + /** Peripheral I2S0 base address */ + #define I2S0_BASE (0x40086000u) + /** Peripheral I2S0 base pointer */ + #define I2S0 ((I2S_Type *)I2S0_BASE) + /** Peripheral I2S1 base address */ + #define I2S1_BASE (0x40087000u) + /** Peripheral I2S1 base pointer */ + #define I2S1 ((I2S_Type *)I2S1_BASE) + /** Peripheral I2S2 base address */ + #define I2S2_BASE (0x40088000u) + /** Peripheral I2S2 base pointer */ + #define I2S2 ((I2S_Type *)I2S2_BASE) + /** Peripheral I2S3 base address */ + #define I2S3_BASE (0x40089000u) + /** Peripheral I2S3 base pointer */ + #define I2S3 ((I2S_Type *)I2S3_BASE) + /** Peripheral I2S4 base address */ + #define I2S4_BASE (0x4008A000u) + /** Peripheral I2S4 base pointer */ + #define I2S4 ((I2S_Type *)I2S4_BASE) + /** Peripheral I2S5 base address */ + #define I2S5_BASE (0x40096000u) + /** Peripheral I2S5 base pointer */ + #define I2S5 ((I2S_Type *)I2S5_BASE) + /** Peripheral I2S6 base address */ + #define I2S6_BASE (0x40097000u) + /** Peripheral I2S6 base pointer */ + #define I2S6 ((I2S_Type *)I2S6_BASE) + /** Peripheral I2S7 base address */ + #define I2S7_BASE (0x40098000u) + /** Peripheral I2S7 base pointer */ + #define I2S7 ((I2S_Type *)I2S7_BASE) + /** Array initializer of I2S peripheral base addresses */ + #define I2S_BASE_ADDRS { I2S0_BASE, I2S1_BASE, I2S2_BASE, I2S3_BASE, I2S4_BASE, I2S5_BASE, I2S6_BASE, I2S7_BASE } + /** Array initializer of I2S peripheral base pointers */ + #define I2S_BASE_PTRS { I2S0, I2S1, I2S2, I2S3, I2S4, I2S5, I2S6, I2S7 } +#endif +/** Interrupt vectors for the I2S peripheral type */ +#define I2S_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn } + +/*! + * @} + */ /* end of group I2S_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- INPUTMUX Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup INPUTMUX_Peripheral_Access_Layer INPUTMUX Peripheral Access Layer + * @{ + */ + +/** INPUTMUX - Register Layout Typedef */ +typedef struct { + __IO uint32_t SCT0_INMUX[7]; /**< Input mux register for SCT0 input, array offset: 0x0, array step: 0x4 */ + uint8_t RESERVED_0[4]; + __IO uint32_t TIMER0CAPTSEL[4]; /**< Capture select registers for TIMER0 inputs, array offset: 0x20, array step: 0x4 */ + uint8_t RESERVED_1[16]; + __IO uint32_t TIMER1CAPTSEL[4]; /**< Capture select registers for TIMER1 inputs, array offset: 0x40, array step: 0x4 */ + uint8_t RESERVED_2[16]; + __IO uint32_t TIMER2CAPTSEL[4]; /**< Capture select registers for TIMER2 inputs, array offset: 0x60, array step: 0x4 */ + uint8_t RESERVED_3[80]; + __IO uint32_t PINTSEL[8]; /**< Pin interrupt select register, array offset: 0xC0, array step: 0x4 */ + __IO uint32_t DMA0_ITRIG_INMUX[23]; /**< Trigger select register for DMA0 channel, array offset: 0xE0, array step: 0x4 */ + uint8_t RESERVED_4[36]; + __IO uint32_t DMA0_OTRIG_INMUX[4]; /**< DMA0 output trigger selection to become DMA0 trigger, array offset: 0x160, array step: 0x4 */ + uint8_t RESERVED_5[16]; + __IO uint32_t FREQMEAS_REF; /**< Selection for frequency measurement reference clock, offset: 0x180 */ + __IO uint32_t FREQMEAS_TARGET; /**< Selection for frequency measurement target clock, offset: 0x184 */ + uint8_t RESERVED_6[24]; + __IO uint32_t TIMER3CAPTSEL[4]; /**< Capture select registers for TIMER3 inputs, array offset: 0x1A0, array step: 0x4 */ + uint8_t RESERVED_7[16]; + __IO uint32_t TIMER4CAPTSEL[4]; /**< Capture select registers for TIMER4 inputs, array offset: 0x1C0, array step: 0x4 */ + uint8_t RESERVED_8[16]; + __IO uint32_t PINTSECSEL[2]; /**< Pin interrupt secure select register, array offset: 0x1E0, array step: 0x4 */ + uint8_t RESERVED_9[24]; + __IO uint32_t DMA1_ITRIG_INMUX[10]; /**< Trigger select register for DMA1 channel, array offset: 0x200, array step: 0x4 */ + uint8_t RESERVED_10[24]; + __IO uint32_t DMA1_OTRIG_INMUX[4]; /**< DMA1 output trigger selection to become DMA1 trigger, array offset: 0x240, array step: 0x4 */ + uint8_t RESERVED_11[1264]; + __IO uint32_t DMA0_REQ_ENA; /**< Enable DMA0 requests, offset: 0x740 */ + uint8_t RESERVED_12[4]; + __O uint32_t DMA0_REQ_ENA_SET; /**< Set one or several bits in DMA0_REQ_ENA register, offset: 0x748 */ + uint8_t RESERVED_13[4]; + __O uint32_t DMA0_REQ_ENA_CLR; /**< Clear one or several bits in DMA0_REQ_ENA register, offset: 0x750 */ + uint8_t RESERVED_14[12]; + __IO uint32_t DMA1_REQ_ENA; /**< Enable DMA1 requests, offset: 0x760 */ + uint8_t RESERVED_15[4]; + __O uint32_t DMA1_REQ_ENA_SET; /**< Set one or several bits in DMA1_REQ_ENA register, offset: 0x768 */ + uint8_t RESERVED_16[4]; + __O uint32_t DMA1_REQ_ENA_CLR; /**< Clear one or several bits in DMA1_REQ_ENA register, offset: 0x770 */ + uint8_t RESERVED_17[12]; + __IO uint32_t DMA0_ITRIG_ENA; /**< Enable DMA0 triggers, offset: 0x780 */ + uint8_t RESERVED_18[4]; + __O uint32_t DMA0_ITRIG_ENA_SET; /**< Set one or several bits in DMA0_ITRIG_ENA register, offset: 0x788 */ + uint8_t RESERVED_19[4]; + __O uint32_t DMA0_ITRIG_ENA_CLR; /**< Clear one or several bits in DMA0_ITRIG_ENA register, offset: 0x790 */ + uint8_t RESERVED_20[12]; + __IO uint32_t DMA1_ITRIG_ENA; /**< Enable DMA1 triggers, offset: 0x7A0 */ + uint8_t RESERVED_21[4]; + __O uint32_t DMA1_ITRIG_ENA_SET; /**< Set one or several bits in DMA1_ITRIG_ENA register, offset: 0x7A8 */ + uint8_t RESERVED_22[4]; + __O uint32_t DMA1_ITRIG_ENA_CLR; /**< Clear one or several bits in DMA1_ITRIG_ENA register, offset: 0x7B0 */ +} INPUTMUX_Type; + +/* ---------------------------------------------------------------------------- + -- INPUTMUX Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup INPUTMUX_Register_Masks INPUTMUX Register Masks + * @{ + */ + +/*! @name SCT0_INMUX - Input mux register for SCT0 input */ +/*! @{ */ + +#define INPUTMUX_SCT0_INMUX_INP_N_MASK (0x1FU) +#define INPUTMUX_SCT0_INMUX_INP_N_SHIFT (0U) +/*! INP_N - Input number to SCT0 inputs 0 to 6.. + * 0b00000..SCT_GPI0 function selected from IOCON register + * 0b00001..SCT_GPI1 function selected from IOCON register + * 0b00010..SCT_GPI2 function selected from IOCON register + * 0b00011..SCT_GPI3 function selected from IOCON register + * 0b00100..SCT_GPI4 function selected from IOCON register + * 0b00101..SCT_GPI5 function selected from IOCON register + * 0b00110..SCT_GPI6 function selected from IOCON register + * 0b00111..SCT_GPI7 function selected from IOCON register + * 0b01000..T0_OUT0 ctimer 0 match[0] output + * 0b01001..T1_OUT0 ctimer 1 match[0] output + * 0b01010..T2_OUT0 ctimer 2 match[0] output + * 0b01011..T3_OUT0 ctimer 3 match[0] output + * 0b01100..T4_OUT0 ctimer 4 match[0] output + * 0b01101..ADC_IRQ interrupt request from ADC + * 0b01110..GPIOINT_BMATCH + * 0b01111..USB0_FRAME_TOGGLE + * 0b10000..USB1_FRAME_TOGGLE + * 0b10001..COMP_OUTPUT output from analog comparator + * 0b10010..I2S_SHARED_SCK[0] output from I2S pin sharing + * 0b10011..I2S_SHARED_SCK[1] output from I2S pin sharing + * 0b10100..I2S_SHARED_WS[0] output from I2S pin sharing + * 0b10101..I2S_SHARED_WS[1] output from I2S pin sharing + * 0b10110..ARM_TXEV interrupt event from cpu0 or cpu1 + * 0b10111..DEBUG_HALTED from cpu0 or cpu1 + * 0b11000-0b11111..None + */ +#define INPUTMUX_SCT0_INMUX_INP_N(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_SCT0_INMUX_INP_N_SHIFT)) & INPUTMUX_SCT0_INMUX_INP_N_MASK) +/*! @} */ + +/* The count of INPUTMUX_SCT0_INMUX */ +#define INPUTMUX_SCT0_INMUX_COUNT (7U) + +/*! @name TIMER0CAPTSEL - Capture select registers for TIMER0 inputs */ +/*! @{ */ + +#define INPUTMUX_TIMER0CAPTSEL_CAPTSEL_MASK (0x1FU) +#define INPUTMUX_TIMER0CAPTSEL_CAPTSEL_SHIFT (0U) +/*! CAPTSEL - Input number to TIMER0 capture inputs 0 to 4 + * 0b00000..CT_INP0 function selected from IOCON register + * 0b00001..CT_INP1 function selected from IOCON register + * 0b00010..CT_INP2 function selected from IOCON register + * 0b00011..CT_INP3 function selected from IOCON register + * 0b00100..CT_INP4 function selected from IOCON register + * 0b00101..CT_INP5 function selected from IOCON register + * 0b00110..CT_INP6 function selected from IOCON register + * 0b00111..CT_INP7 function selected from IOCON register + * 0b01000..CT_INP8 function selected from IOCON register + * 0b01001..CT_INP9 function selected from IOCON register + * 0b01010..CT_INP10 function selected from IOCON register + * 0b01011..CT_INP11 function selected from IOCON register + * 0b01100..CT_INP12 function selected from IOCON register + * 0b01101..CT_INP13 function selected from IOCON register + * 0b01110..CT_INP14 function selected from IOCON register + * 0b01111..CT_INP15 function selected from IOCON register + * 0b10000..CT_INP16 function selected from IOCON register + * 0b10001..None + * 0b10010..None + * 0b10011..None + * 0b10100..USB0_FRAME_TOGGLE + * 0b10101..USB1_FRAME_TOGGLE + * 0b10110..COMP_OUTPUT output from analog comparator + * 0b10111..I2S_SHARED_WS[0] output from I2S pin sharing + * 0b11000..I2S_SHARED_WS[1] output from I2S pin sharing + * 0b11001-0b11111..None + */ +#define INPUTMUX_TIMER0CAPTSEL_CAPTSEL(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER0CAPTSEL_CAPTSEL_SHIFT)) & INPUTMUX_TIMER0CAPTSEL_CAPTSEL_MASK) +/*! @} */ + +/* The count of INPUTMUX_TIMER0CAPTSEL */ +#define INPUTMUX_TIMER0CAPTSEL_COUNT (4U) + +/*! @name TIMER1CAPTSEL - Capture select registers for TIMER1 inputs */ +/*! @{ */ + +#define INPUTMUX_TIMER1CAPTSEL_CAPTSEL_MASK (0x1FU) +#define INPUTMUX_TIMER1CAPTSEL_CAPTSEL_SHIFT (0U) +/*! CAPTSEL - Input number to TIMER1 capture inputs 0 to 4 + * 0b00000..CT_INP0 function selected from IOCON register + * 0b00001..CT_INP1 function selected from IOCON register + * 0b00010..CT_INP2 function selected from IOCON register + * 0b00011..CT_INP3 function selected from IOCON register + * 0b00100..CT_INP4 function selected from IOCON register + * 0b00101..CT_INP5 function selected from IOCON register + * 0b00110..CT_INP6 function selected from IOCON register + * 0b00111..CT_INP7 function selected from IOCON register + * 0b01000..CT_INP8 function selected from IOCON register + * 0b01001..CT_INP9 function selected from IOCON register + * 0b01010..CT_INP10 function selected from IOCON register + * 0b01011..CT_INP11 function selected from IOCON register + * 0b01100..CT_INP12 function selected from IOCON register + * 0b01101..CT_INP13 function selected from IOCON register + * 0b01110..CT_INP14 function selected from IOCON register + * 0b01111..CT_INP15 function selected from IOCON register + * 0b10000..CT_INP16 function selected from IOCON register + * 0b10001..None + * 0b10010..None + * 0b10011..None + * 0b10100..USB0_FRAME_TOGGLE + * 0b10101..USB1_FRAME_TOGGLE + * 0b10110..COMP_OUTPUT output from analog comparator + * 0b10111..I2S_SHARED_WS[0] output from I2S pin sharing + * 0b11000..I2S_SHARED_WS[1] output from I2S pin sharing + * 0b11001-0b11111..None + */ +#define INPUTMUX_TIMER1CAPTSEL_CAPTSEL(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER1CAPTSEL_CAPTSEL_SHIFT)) & INPUTMUX_TIMER1CAPTSEL_CAPTSEL_MASK) +/*! @} */ + +/* The count of INPUTMUX_TIMER1CAPTSEL */ +#define INPUTMUX_TIMER1CAPTSEL_COUNT (4U) + +/*! @name TIMER2CAPTSEL - Capture select registers for TIMER2 inputs */ +/*! @{ */ + +#define INPUTMUX_TIMER2CAPTSEL_CAPTSEL_MASK (0x1FU) +#define INPUTMUX_TIMER2CAPTSEL_CAPTSEL_SHIFT (0U) +/*! CAPTSEL - Input number to TIMER2 capture inputs 0 to 4 + * 0b00000..CT_INP0 function selected from IOCON register + * 0b00001..CT_INP1 function selected from IOCON register + * 0b00010..CT_INP2 function selected from IOCON register + * 0b00011..CT_INP3 function selected from IOCON register + * 0b00100..CT_INP4 function selected from IOCON register + * 0b00101..CT_INP5 function selected from IOCON register + * 0b00110..CT_INP6 function selected from IOCON register + * 0b00111..CT_INP7 function selected from IOCON register + * 0b01000..CT_INP8 function selected from IOCON register + * 0b01001..CT_INP9 function selected from IOCON register + * 0b01010..CT_INP10 function selected from IOCON register + * 0b01011..CT_INP11 function selected from IOCON register + * 0b01100..CT_INP12 function selected from IOCON register + * 0b01101..CT_INP13 function selected from IOCON register + * 0b01110..CT_INP14 function selected from IOCON register + * 0b01111..CT_INP15 function selected from IOCON register + * 0b10000..CT_INP16 function selected from IOCON register + * 0b10001..None + * 0b10010..None + * 0b10011..None + * 0b10100..USB0_FRAME_TOGGLE + * 0b10101..USB1_FRAME_TOGGLE + * 0b10110..COMP_OUTPUT output from analog comparator + * 0b10111..I2S_SHARED_WS[0] output from I2S pin sharing + * 0b11000..I2S_SHARED_WS[1] output from I2S pin sharing + * 0b11001-0b11111..None + */ +#define INPUTMUX_TIMER2CAPTSEL_CAPTSEL(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER2CAPTSEL_CAPTSEL_SHIFT)) & INPUTMUX_TIMER2CAPTSEL_CAPTSEL_MASK) +/*! @} */ + +/* The count of INPUTMUX_TIMER2CAPTSEL */ +#define INPUTMUX_TIMER2CAPTSEL_COUNT (4U) + +/*! @name PINTSEL - Pin interrupt select register */ +/*! @{ */ + +#define INPUTMUX_PINTSEL_INTPIN_MASK (0x7FU) +#define INPUTMUX_PINTSEL_INTPIN_SHIFT (0U) +/*! INTPIN - Pin number select for pin interrupt or pattern match engine input. For PIOx_y: INTPIN = + * (x * 32) + y. PIO0_0 to PIO1_31 correspond to numbers 0 to 63. + */ +#define INPUTMUX_PINTSEL_INTPIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_PINTSEL_INTPIN_SHIFT)) & INPUTMUX_PINTSEL_INTPIN_MASK) +/*! @} */ + +/* The count of INPUTMUX_PINTSEL */ +#define INPUTMUX_PINTSEL_COUNT (8U) + +/*! @name DMA0_ITRIG_INMUX - Trigger select register for DMA0 channel */ +/*! @{ */ + +#define INPUTMUX_DMA0_ITRIG_INMUX_INP_MASK (0x1FU) +#define INPUTMUX_DMA0_ITRIG_INMUX_INP_SHIFT (0U) +/*! INP - Trigger input number (decimal value) for DMA channel n (n = 0 to 22). + * 0b00000..Pin interrupt 0 + * 0b00001..Pin interrupt 1 + * 0b00010..Pin interrupt 2 + * 0b00011..Pin interrupt 3 + * 0b00100..Timer CTIMER0 Match 0 + * 0b00101..Timer CTIMER0 Match 1 + * 0b00110..Timer CTIMER1 Match 0 + * 0b00111..Timer CTIMER1 Match 1 + * 0b01000..Timer CTIMER2 Match 0 + * 0b01001..Timer CTIMER2 Match 1 + * 0b01010..Timer CTIMER3 Match 0 + * 0b01011..Timer CTIMER3 Match 1 + * 0b01100..Timer CTIMER4 Match 0 + * 0b01101..Timer CTIMER4 Match 1 + * 0b01110..COMP_OUTPUT + * 0b01111..DMA0 output trigger mux 0 + * 0b10000..DMA0 output trigger mux 1 + * 0b10001..DMA0 output trigger mux 1 + * 0b10010..DMA0 output trigger mux 3 + * 0b10011..SCT0 DMA request 0 + * 0b10100..SCT0 DMA request 1 + * 0b10101..HASH DMA RX trigger + * 0b10110-0b11111..None + */ +#define INPUTMUX_DMA0_ITRIG_INMUX_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIG_INMUX_INP_SHIFT)) & INPUTMUX_DMA0_ITRIG_INMUX_INP_MASK) +/*! @} */ + +/* The count of INPUTMUX_DMA0_ITRIG_INMUX */ +#define INPUTMUX_DMA0_ITRIG_INMUX_COUNT (23U) + +/*! @name DMA0_OTRIG_INMUX - DMA0 output trigger selection to become DMA0 trigger */ +/*! @{ */ + +#define INPUTMUX_DMA0_OTRIG_INMUX_INP_MASK (0x1FU) +#define INPUTMUX_DMA0_OTRIG_INMUX_INP_SHIFT (0U) +/*! INP - DMA trigger output number (decimal value) for DMA channel n (n = 0 to 22). + */ +#define INPUTMUX_DMA0_OTRIG_INMUX_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_OTRIG_INMUX_INP_SHIFT)) & INPUTMUX_DMA0_OTRIG_INMUX_INP_MASK) +/*! @} */ + +/* The count of INPUTMUX_DMA0_OTRIG_INMUX */ +#define INPUTMUX_DMA0_OTRIG_INMUX_COUNT (4U) + +/*! @name FREQMEAS_REF - Selection for frequency measurement reference clock */ +/*! @{ */ + +#define INPUTMUX_FREQMEAS_REF_CLKIN_MASK (0x1FU) +#define INPUTMUX_FREQMEAS_REF_CLKIN_SHIFT (0U) +/*! CLKIN - Clock source number (decimal value) for frequency measure function reference clock: + * 0b00000..External main crystal oscilator (Clock_in). + * 0b00001..FRO 12MHz clock. + * 0b00010..FRO 96MHz clock. + * 0b00011..Watchdog oscillator / FRO1MHz clock. + * 0b00100..32 kHz oscillator (32k_clk) clock. + * 0b00101..main clock (main_clock). + * 0b00110..FREQME_GPIO_CLK_A. + * 0b00111..FREQME_GPIO_CLK_B. + */ +#define INPUTMUX_FREQMEAS_REF_CLKIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FREQMEAS_REF_CLKIN_SHIFT)) & INPUTMUX_FREQMEAS_REF_CLKIN_MASK) +/*! @} */ + +/*! @name FREQMEAS_TARGET - Selection for frequency measurement target clock */ +/*! @{ */ + +#define INPUTMUX_FREQMEAS_TARGET_CLKIN_MASK (0x1FU) +#define INPUTMUX_FREQMEAS_TARGET_CLKIN_SHIFT (0U) +/*! CLKIN - Clock source number (decimal value) for frequency measure function target clock: + * 0b00000..External main crystal oscilator (Clock_in). + * 0b00001..FRO 12MHz clock. + * 0b00010..FRO 96MHz clock. + * 0b00011..Watchdog oscillator / FRO1MHz clock. + * 0b00100..32 kHz oscillator (32k_clk) clock. + * 0b00101..main clock (main_clock). + * 0b00110..FREQME_GPIO_CLK_A. + * 0b00111..FREQME_GPIO_CLK_B. + */ +#define INPUTMUX_FREQMEAS_TARGET_CLKIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FREQMEAS_TARGET_CLKIN_SHIFT)) & INPUTMUX_FREQMEAS_TARGET_CLKIN_MASK) +/*! @} */ + +/*! @name TIMER3CAPTSEL - Capture select registers for TIMER3 inputs */ +/*! @{ */ + +#define INPUTMUX_TIMER3CAPTSEL_CAPTSEL_MASK (0x1FU) +#define INPUTMUX_TIMER3CAPTSEL_CAPTSEL_SHIFT (0U) +/*! CAPTSEL - Input number to TIMER3 capture inputs 0 to 4 + * 0b00000..CT_INP0 function selected from IOCON register + * 0b00001..CT_INP1 function selected from IOCON register + * 0b00010..CT_INP2 function selected from IOCON register + * 0b00011..CT_INP3 function selected from IOCON register + * 0b00100..CT_INP4 function selected from IOCON register + * 0b00101..CT_INP5 function selected from IOCON register + * 0b00110..CT_INP6 function selected from IOCON register + * 0b00111..CT_INP7 function selected from IOCON register + * 0b01000..CT_INP8 function selected from IOCON register + * 0b01001..CT_INP9 function selected from IOCON register + * 0b01010..CT_INP10 function selected from IOCON register + * 0b01011..CT_INP11 function selected from IOCON register + * 0b01100..CT_INP12 function selected from IOCON register + * 0b01101..CT_INP13 function selected from IOCON register + * 0b01110..CT_INP14 function selected from IOCON register + * 0b01111..CT_INP15 function selected from IOCON register + * 0b10000..CT_INP16 function selected from IOCON register + * 0b10001..None + * 0b10010..None + * 0b10011..None + * 0b10100..USB0_FRAME_TOGGLE + * 0b10101..USB1_FRAME_TOGGLE + * 0b10110..COMP_OUTPUT output from analog comparator + * 0b10111..I2S_SHARED_WS[0] output from I2S pin sharing + * 0b11000..I2S_SHARED_WS[1] output from I2S pin sharing + * 0b11001-0b11111..None + */ +#define INPUTMUX_TIMER3CAPTSEL_CAPTSEL(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER3CAPTSEL_CAPTSEL_SHIFT)) & INPUTMUX_TIMER3CAPTSEL_CAPTSEL_MASK) +/*! @} */ + +/* The count of INPUTMUX_TIMER3CAPTSEL */ +#define INPUTMUX_TIMER3CAPTSEL_COUNT (4U) + +/*! @name TIMER4CAPTSEL - Capture select registers for TIMER4 inputs */ +/*! @{ */ + +#define INPUTMUX_TIMER4CAPTSEL_CAPTSEL_MASK (0x1FU) +#define INPUTMUX_TIMER4CAPTSEL_CAPTSEL_SHIFT (0U) +/*! CAPTSEL - Input number to TIMER4 capture inputs 0 to 4 + * 0b00000..CT_INP0 function selected from IOCON register + * 0b00001..CT_INP1 function selected from IOCON register + * 0b00010..CT_INP2 function selected from IOCON register + * 0b00011..CT_INP3 function selected from IOCON register + * 0b00100..CT_INP4 function selected from IOCON register + * 0b00101..CT_INP5 function selected from IOCON register + * 0b00110..CT_INP6 function selected from IOCON register + * 0b00111..CT_INP7 function selected from IOCON register + * 0b01000..CT_INP8 function selected from IOCON register + * 0b01001..CT_INP9 function selected from IOCON register + * 0b01010..CT_INP10 function selected from IOCON register + * 0b01011..CT_INP11 function selected from IOCON register + * 0b01100..CT_INP12 function selected from IOCON register + * 0b01101..CT_INP13 function selected from IOCON register + * 0b01110..CT_INP14 function selected from IOCON register + * 0b01111..CT_INP15 function selected from IOCON register + * 0b10000..CT_INP16 function selected from IOCON register + * 0b10001..None + * 0b10010..None + * 0b10011..None + * 0b10100..USB0_FRAME_TOGGLE + * 0b10101..USB1_FRAME_TOGGLE + * 0b10110..COMP_OUTPUT output from analog comparator + * 0b10111..I2S_SHARED_WS[0] output from I2S pin sharing + * 0b11000..I2S_SHARED_WS[1] output from I2S pin sharing + * 0b11001-0b11111..None + */ +#define INPUTMUX_TIMER4CAPTSEL_CAPTSEL(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER4CAPTSEL_CAPTSEL_SHIFT)) & INPUTMUX_TIMER4CAPTSEL_CAPTSEL_MASK) +/*! @} */ + +/* The count of INPUTMUX_TIMER4CAPTSEL */ +#define INPUTMUX_TIMER4CAPTSEL_COUNT (4U) + +/*! @name PINTSECSEL - Pin interrupt secure select register */ +/*! @{ */ + +#define INPUTMUX_PINTSECSEL_INTPIN_MASK (0x3FU) +#define INPUTMUX_PINTSECSEL_INTPIN_SHIFT (0U) +/*! INTPIN - Pin number select for pin interrupt secure or pattern match engine input. For PIO0_x: + * INTPIN = x. PIO0_0 to PIO0_31 correspond to numbers 0 to 31. + */ +#define INPUTMUX_PINTSECSEL_INTPIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_PINTSECSEL_INTPIN_SHIFT)) & INPUTMUX_PINTSECSEL_INTPIN_MASK) +/*! @} */ + +/* The count of INPUTMUX_PINTSECSEL */ +#define INPUTMUX_PINTSECSEL_COUNT (2U) + +/*! @name DMA1_ITRIG_INMUX - Trigger select register for DMA1 channel */ +/*! @{ */ + +#define INPUTMUX_DMA1_ITRIG_INMUX_INP_MASK (0xFU) +#define INPUTMUX_DMA1_ITRIG_INMUX_INP_SHIFT (0U) +/*! INP - Trigger input number (decimal value) for DMA channel n (n = 0 to 9). + * 0b0000..Pin interrupt 0 + * 0b0001..Pin interrupt 1 + * 0b0010..Pin interrupt 2 + * 0b0011..Pin interrupt 3 + * 0b0100..Timer CTIMER0 Match 0 + * 0b0101..Timer CTIMER0 Match 1 + * 0b0110..Timer CTIMER2 Match 0 + * 0b0111..Timer CTIMER4 Match 0 + * 0b1000..DMA1 output trigger mux 0 + * 0b1001..DMA1 output trigger mux 1 + * 0b1010..DMA1 output trigger mux 2 + * 0b1011..DMA1 output trigger mux 3 + * 0b1100..SCT0 DMA request 0 + * 0b1101..SCT0 DMA request 1 + * 0b1110..HASH DMA RX trigger + * 0b1111..None + */ +#define INPUTMUX_DMA1_ITRIG_INMUX_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIG_INMUX_INP_SHIFT)) & INPUTMUX_DMA1_ITRIG_INMUX_INP_MASK) +/*! @} */ + +/* The count of INPUTMUX_DMA1_ITRIG_INMUX */ +#define INPUTMUX_DMA1_ITRIG_INMUX_COUNT (10U) + +/*! @name DMA1_OTRIG_INMUX - DMA1 output trigger selection to become DMA1 trigger */ +/*! @{ */ + +#define INPUTMUX_DMA1_OTRIG_INMUX_INP_MASK (0xFU) +#define INPUTMUX_DMA1_OTRIG_INMUX_INP_SHIFT (0U) +/*! INP - DMA trigger output number (decimal value) for DMA channel n (n = 0 to 9). + */ +#define INPUTMUX_DMA1_OTRIG_INMUX_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_OTRIG_INMUX_INP_SHIFT)) & INPUTMUX_DMA1_OTRIG_INMUX_INP_MASK) +/*! @} */ + +/* The count of INPUTMUX_DMA1_OTRIG_INMUX */ +#define INPUTMUX_DMA1_OTRIG_INMUX_COUNT (4U) + +/*! @name DMA0_REQ_ENA - Enable DMA0 requests */ +/*! @{ */ + +#define INPUTMUX_DMA0_REQ_ENA_REQ_ENA_MASK (0x7FFFFFU) +#define INPUTMUX_DMA0_REQ_ENA_REQ_ENA_SHIFT (0U) +/*! REQ_ENA - Controls the 23 request inputs of DMA0. If bit i is '1' the DMA request input #i is enabled. + */ +#define INPUTMUX_DMA0_REQ_ENA_REQ_ENA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENA_REQ_ENA_SHIFT)) & INPUTMUX_DMA0_REQ_ENA_REQ_ENA_MASK) +/*! @} */ + +/*! @name DMA0_REQ_ENA_SET - Set one or several bits in DMA0_REQ_ENA register */ +/*! @{ */ + +#define INPUTMUX_DMA0_REQ_ENA_SET_SET_MASK (0x7FFFFFU) +#define INPUTMUX_DMA0_REQ_ENA_SET_SET_SHIFT (0U) +/*! SET - Write : If bit #i = 1, bit #i in DMA0_REQ_ENA register is set to 1; if bit #i = 0 , no change in DMA0_REQ_ENA register + */ +#define INPUTMUX_DMA0_REQ_ENA_SET_SET(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENA_SET_SET_SHIFT)) & INPUTMUX_DMA0_REQ_ENA_SET_SET_MASK) +/*! @} */ + +/*! @name DMA0_REQ_ENA_CLR - Clear one or several bits in DMA0_REQ_ENA register */ +/*! @{ */ + +#define INPUTMUX_DMA0_REQ_ENA_CLR_CLR_MASK (0x7FFFFFU) +#define INPUTMUX_DMA0_REQ_ENA_CLR_CLR_SHIFT (0U) +/*! CLR - Write : If bit #i = 1, bit #i in DMA0_REQ_ENA register is reset to 0; if bit #i = 0 , no change in DMA0_REQ_ENA register + */ +#define INPUTMUX_DMA0_REQ_ENA_CLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENA_CLR_CLR_SHIFT)) & INPUTMUX_DMA0_REQ_ENA_CLR_CLR_MASK) +/*! @} */ + +/*! @name DMA1_REQ_ENA - Enable DMA1 requests */ +/*! @{ */ + +#define INPUTMUX_DMA1_REQ_ENA_REQ_ENA_MASK (0x3FFU) +#define INPUTMUX_DMA1_REQ_ENA_REQ_ENA_SHIFT (0U) +/*! REQ_ENA - Controls the 10 request inputs of DMA1. If bit i is '1' the DMA request input #i is enabled. + */ +#define INPUTMUX_DMA1_REQ_ENA_REQ_ENA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENA_REQ_ENA_SHIFT)) & INPUTMUX_DMA1_REQ_ENA_REQ_ENA_MASK) +/*! @} */ + +/*! @name DMA1_REQ_ENA_SET - Set one or several bits in DMA1_REQ_ENA register */ +/*! @{ */ + +#define INPUTMUX_DMA1_REQ_ENA_SET_SET_MASK (0x3FFU) +#define INPUTMUX_DMA1_REQ_ENA_SET_SET_SHIFT (0U) +/*! SET - Write : If bit #i = 1, bit #i in DMA1_REQ_ENA register is set to 1; if bit #i = 0 , no change in DMA1_REQ_ENA register + */ +#define INPUTMUX_DMA1_REQ_ENA_SET_SET(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENA_SET_SET_SHIFT)) & INPUTMUX_DMA1_REQ_ENA_SET_SET_MASK) +/*! @} */ + +/*! @name DMA1_REQ_ENA_CLR - Clear one or several bits in DMA1_REQ_ENA register */ +/*! @{ */ + +#define INPUTMUX_DMA1_REQ_ENA_CLR_CLR_MASK (0x3FFU) +#define INPUTMUX_DMA1_REQ_ENA_CLR_CLR_SHIFT (0U) +/*! CLR - Write : If bit #i = 1, bit #i in DMA1_REQ_ENA register is reset to 0; if bit #i = 0 , no change in DMA1_REQ_ENA register + */ +#define INPUTMUX_DMA1_REQ_ENA_CLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENA_CLR_CLR_SHIFT)) & INPUTMUX_DMA1_REQ_ENA_CLR_CLR_MASK) +/*! @} */ + +/*! @name DMA0_ITRIG_ENA - Enable DMA0 triggers */ +/*! @{ */ + +#define INPUTMUX_DMA0_ITRIG_ENA_ITRIG_ENA_MASK (0x3FFFFFU) +#define INPUTMUX_DMA0_ITRIG_ENA_ITRIG_ENA_SHIFT (0U) +/*! ITRIG_ENA - Controls the 22 trigger inputs of DMA0. If bit i is '1' the DMA trigger input #i is enabled. + */ +#define INPUTMUX_DMA0_ITRIG_ENA_ITRIG_ENA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIG_ENA_ITRIG_ENA_SHIFT)) & INPUTMUX_DMA0_ITRIG_ENA_ITRIG_ENA_MASK) +/*! @} */ + +/*! @name DMA0_ITRIG_ENA_SET - Set one or several bits in DMA0_ITRIG_ENA register */ +/*! @{ */ + +#define INPUTMUX_DMA0_ITRIG_ENA_SET_SET_MASK (0x3FFFFFU) +#define INPUTMUX_DMA0_ITRIG_ENA_SET_SET_SHIFT (0U) +/*! SET - Write : If bit #i = 1, bit #i in DMA0_ITRIG_ENA register is set to 1; if bit #i = 0 , no + * change in DMA0_ITRIG_ENA register + */ +#define INPUTMUX_DMA0_ITRIG_ENA_SET_SET(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIG_ENA_SET_SET_SHIFT)) & INPUTMUX_DMA0_ITRIG_ENA_SET_SET_MASK) +/*! @} */ + +/*! @name DMA0_ITRIG_ENA_CLR - Clear one or several bits in DMA0_ITRIG_ENA register */ +/*! @{ */ + +#define INPUTMUX_DMA0_ITRIG_ENA_CLR_CLR_MASK (0x3FFFFFU) +#define INPUTMUX_DMA0_ITRIG_ENA_CLR_CLR_SHIFT (0U) +/*! CLR - Write : If bit #i = 1, bit #i in DMA0_ITRIG_ENA register is reset to 0; if bit #i = 0 , no + * change in DMA0_ITRIG_ENA register + */ +#define INPUTMUX_DMA0_ITRIG_ENA_CLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIG_ENA_CLR_CLR_SHIFT)) & INPUTMUX_DMA0_ITRIG_ENA_CLR_CLR_MASK) +/*! @} */ + +/*! @name DMA1_ITRIG_ENA - Enable DMA1 triggers */ +/*! @{ */ + +#define INPUTMUX_DMA1_ITRIG_ENA_ITRIG_ENA_MASK (0x7FFFU) +#define INPUTMUX_DMA1_ITRIG_ENA_ITRIG_ENA_SHIFT (0U) +/*! ITRIG_ENA - Controls the 15 trigger inputs of DMA1. If bit i is '1' the DMA trigger input #i is enabled. + */ +#define INPUTMUX_DMA1_ITRIG_ENA_ITRIG_ENA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIG_ENA_ITRIG_ENA_SHIFT)) & INPUTMUX_DMA1_ITRIG_ENA_ITRIG_ENA_MASK) +/*! @} */ + +/*! @name DMA1_ITRIG_ENA_SET - Set one or several bits in DMA1_ITRIG_ENA register */ +/*! @{ */ + +#define INPUTMUX_DMA1_ITRIG_ENA_SET_SET_MASK (0x7FFFU) +#define INPUTMUX_DMA1_ITRIG_ENA_SET_SET_SHIFT (0U) +/*! SET - Write : If bit #i = 1, bit #i in DMA1_ITRIG_ENA register is set to 1; if bit #i = 0 , no + * change in DMA1_ITRIG_ENA register + */ +#define INPUTMUX_DMA1_ITRIG_ENA_SET_SET(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIG_ENA_SET_SET_SHIFT)) & INPUTMUX_DMA1_ITRIG_ENA_SET_SET_MASK) +/*! @} */ + +/*! @name DMA1_ITRIG_ENA_CLR - Clear one or several bits in DMA1_ITRIG_ENA register */ +/*! @{ */ + +#define INPUTMUX_DMA1_ITRIG_ENA_CLR_CLR_MASK (0x7FFFU) +#define INPUTMUX_DMA1_ITRIG_ENA_CLR_CLR_SHIFT (0U) +/*! CLR - Write : If bit #i = 1, bit #i in DMA1_ITRIG_ENA register is reset to 0; if bit #i = 0 , no + * change in DMA1_ITRIG_ENA register + */ +#define INPUTMUX_DMA1_ITRIG_ENA_CLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIG_ENA_CLR_CLR_SHIFT)) & INPUTMUX_DMA1_ITRIG_ENA_CLR_CLR_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group INPUTMUX_Register_Masks */ + + +/* INPUTMUX - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral INPUTMUX base address */ + #define INPUTMUX_BASE (0x50006000u) + /** Peripheral INPUTMUX base address */ + #define INPUTMUX_BASE_NS (0x40006000u) + /** Peripheral INPUTMUX base pointer */ + #define INPUTMUX ((INPUTMUX_Type *)INPUTMUX_BASE) + /** Peripheral INPUTMUX base pointer */ + #define INPUTMUX_NS ((INPUTMUX_Type *)INPUTMUX_BASE_NS) + /** Array initializer of INPUTMUX peripheral base addresses */ + #define INPUTMUX_BASE_ADDRS { INPUTMUX_BASE } + /** Array initializer of INPUTMUX peripheral base pointers */ + #define INPUTMUX_BASE_PTRS { INPUTMUX } + /** Array initializer of INPUTMUX peripheral base addresses */ + #define INPUTMUX_BASE_ADDRS_NS { INPUTMUX_BASE_NS } + /** Array initializer of INPUTMUX peripheral base pointers */ + #define INPUTMUX_BASE_PTRS_NS { INPUTMUX_NS } +#else + /** Peripheral INPUTMUX base address */ + #define INPUTMUX_BASE (0x40006000u) + /** Peripheral INPUTMUX base pointer */ + #define INPUTMUX ((INPUTMUX_Type *)INPUTMUX_BASE) + /** Array initializer of INPUTMUX peripheral base addresses */ + #define INPUTMUX_BASE_ADDRS { INPUTMUX_BASE } + /** Array initializer of INPUTMUX peripheral base pointers */ + #define INPUTMUX_BASE_PTRS { INPUTMUX } +#endif + +/*! + * @} + */ /* end of group INPUTMUX_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- IOCON Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup IOCON_Peripheral_Access_Layer IOCON Peripheral Access Layer + * @{ + */ + +/** IOCON - Register Layout Typedef */ +typedef struct { + __IO uint32_t PIO[2][32]; /**< Digital I/O control for port 0 pins PIO0_0..Digital I/O control for port 1 pins PIO1_31, array offset: 0x0, array step: index*0x80, index2*0x4 */ +} IOCON_Type; + +/* ---------------------------------------------------------------------------- + -- IOCON Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup IOCON_Register_Masks IOCON Register Masks + * @{ + */ + +/*! @name PIO - Digital I/O control for port 0 pins PIO0_0..Digital I/O control for port 1 pins PIO1_31 */ +/*! @{ */ + +#define IOCON_PIO_FUNC_MASK (0xFU) +#define IOCON_PIO_FUNC_SHIFT (0U) +/*! FUNC - Selects pin function. + * 0b0000..Alternative connection 0. + * 0b0001..Alternative connection 1. + * 0b0010..Alternative connection 2. + * 0b0011..Alternative connection 3. + * 0b0100..Alternative connection 4. + * 0b0101..Alternative connection 5. + * 0b0110..Alternative connection 6. + * 0b0111..Alternative connection 7. + */ +#define IOCON_PIO_FUNC(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_FUNC_SHIFT)) & IOCON_PIO_FUNC_MASK) + +#define IOCON_PIO_MODE_MASK (0x30U) +#define IOCON_PIO_MODE_SHIFT (4U) +/*! MODE - Selects function mode (on-chip pull-up/pull-down resistor control). + * 0b00..Inactive. Inactive (no pull-down/pull-up resistor enabled). + * 0b01..Pull-down. Pull-down resistor enabled. + * 0b10..Pull-up. Pull-up resistor enabled. + * 0b11..Repeater. Repeater mode. + */ +#define IOCON_PIO_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_MODE_SHIFT)) & IOCON_PIO_MODE_MASK) + +#define IOCON_PIO_SLEW_MASK (0x40U) +#define IOCON_PIO_SLEW_SHIFT (6U) +/*! SLEW - Driver slew rate. + * 0b0..Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. + * 0b1..Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. + */ +#define IOCON_PIO_SLEW(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_SLEW_SHIFT)) & IOCON_PIO_SLEW_MASK) + +#define IOCON_PIO_INVERT_MASK (0x80U) +#define IOCON_PIO_INVERT_SHIFT (7U) +/*! INVERT - Input polarity. + * 0b0..Disabled. Input function is not inverted. + * 0b1..Enabled. Input is function inverted. + */ +#define IOCON_PIO_INVERT(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_INVERT_SHIFT)) & IOCON_PIO_INVERT_MASK) + +#define IOCON_PIO_DIGIMODE_MASK (0x100U) +#define IOCON_PIO_DIGIMODE_SHIFT (8U) +/*! DIGIMODE - Select Digital mode. + * 0b0..Disable digital mode. Digital input set to 0. + * 0b1..Enable Digital mode. Digital input is enabled. + */ +#define IOCON_PIO_DIGIMODE(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_DIGIMODE_SHIFT)) & IOCON_PIO_DIGIMODE_MASK) + +#define IOCON_PIO_OD_MASK (0x200U) +#define IOCON_PIO_OD_SHIFT (9U) +/*! OD - Controls open-drain mode in standard GPIO mode (EGP = 1). This bit has no effect in I2C mode (EGP=0). + * 0b0..Normal. Normal push-pull output + * 0b1..Open-drain. Simulated open-drain output (high drive disabled). + */ +#define IOCON_PIO_OD(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_OD_SHIFT)) & IOCON_PIO_OD_MASK) + +#define IOCON_PIO_ASW_MASK (0x400U) +#define IOCON_PIO_ASW_SHIFT (10U) +/*! ASW - Analog switch input control. + * 0b0..Analog switch is open. (disable) + * 0b1..Analog switch is closed. (enable) + */ +#define IOCON_PIO_ASW(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_ASW_SHIFT)) & IOCON_PIO_ASW_MASK) + +#define IOCON_PIO_SSEL_MASK (0x800U) +#define IOCON_PIO_SSEL_SHIFT (11U) +/*! SSEL - Supply Selection bit. + * 0b0..3V3 Signaling in I2C Mode. + * 0b1..1V8 Signaling in I2C Mode. + */ +#define IOCON_PIO_SSEL(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_SSEL_SHIFT)) & IOCON_PIO_SSEL_MASK) + +#define IOCON_PIO_FILTEROFF_MASK (0x1000U) +#define IOCON_PIO_FILTEROFF_SHIFT (12U) +/*! FILTEROFF - Controls input glitch filter. + * 0b0..Filter enabled. + * 0b1..Filter disabled. + */ +#define IOCON_PIO_FILTEROFF(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_FILTEROFF_SHIFT)) & IOCON_PIO_FILTEROFF_MASK) + +#define IOCON_PIO_ECS_MASK (0x2000U) +#define IOCON_PIO_ECS_SHIFT (13U) +/*! ECS - Pull-up current source enable in I2C mode. + * 0b1..Enabled. Pull resistor is conencted. + * 0b0..Disabled. IO is in open drain cell. + */ +#define IOCON_PIO_ECS(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_ECS_SHIFT)) & IOCON_PIO_ECS_MASK) + +#define IOCON_PIO_EGP_MASK (0x4000U) +#define IOCON_PIO_EGP_SHIFT (14U) +/*! EGP - Switch between GPIO mode and I2C mode. + * 0b0..I2C mode. + * 0b1..GPIO mode. + */ +#define IOCON_PIO_EGP(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_EGP_SHIFT)) & IOCON_PIO_EGP_MASK) + +#define IOCON_PIO_I2CFILTER_MASK (0x8000U) +#define IOCON_PIO_I2CFILTER_SHIFT (15U) +/*! I2CFILTER - Configures I2C features for standard mode, fast mode, and Fast Mode Plus operation and High-Speed mode operation. + * 0b0..I2C 50 ns glitch filter enabled. Typically used for Standard-mode, Fast-mode and Fast-mode Plus I2C. + * 0b1..I2C 10 ns glitch filter enabled. Typically used for High-speed mode I2C. + */ +#define IOCON_PIO_I2CFILTER(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_I2CFILTER_SHIFT)) & IOCON_PIO_I2CFILTER_MASK) +/*! @} */ + +/* The count of IOCON_PIO */ +#define IOCON_PIO_COUNT (2U) + +/* The count of IOCON_PIO */ +#define IOCON_PIO_COUNT2 (32U) + + +/*! + * @} + */ /* end of group IOCON_Register_Masks */ + + +/* IOCON - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral IOCON base address */ + #define IOCON_BASE (0x50001000u) + /** Peripheral IOCON base address */ + #define IOCON_BASE_NS (0x40001000u) + /** Peripheral IOCON base pointer */ + #define IOCON ((IOCON_Type *)IOCON_BASE) + /** Peripheral IOCON base pointer */ + #define IOCON_NS ((IOCON_Type *)IOCON_BASE_NS) + /** Array initializer of IOCON peripheral base addresses */ + #define IOCON_BASE_ADDRS { IOCON_BASE } + /** Array initializer of IOCON peripheral base pointers */ + #define IOCON_BASE_PTRS { IOCON } + /** Array initializer of IOCON peripheral base addresses */ + #define IOCON_BASE_ADDRS_NS { IOCON_BASE_NS } + /** Array initializer of IOCON peripheral base pointers */ + #define IOCON_BASE_PTRS_NS { IOCON_NS } +#else + /** Peripheral IOCON base address */ + #define IOCON_BASE (0x40001000u) + /** Peripheral IOCON base pointer */ + #define IOCON ((IOCON_Type *)IOCON_BASE) + /** Array initializer of IOCON peripheral base addresses */ + #define IOCON_BASE_ADDRS { IOCON_BASE } + /** Array initializer of IOCON peripheral base pointers */ + #define IOCON_BASE_PTRS { IOCON } +#endif + +/*! + * @} + */ /* end of group IOCON_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- MRT Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup MRT_Peripheral_Access_Layer MRT Peripheral Access Layer + * @{ + */ + +/** MRT - Register Layout Typedef */ +typedef struct { + struct { /* offset: 0x0, array step: 0x10 */ + __IO uint32_t INTVAL; /**< MRT Time interval value register. This value is loaded into the TIMER register., array offset: 0x0, array step: 0x10 */ + __I uint32_t TIMER; /**< MRT Timer register. This register reads the value of the down-counter., array offset: 0x4, array step: 0x10 */ + __IO uint32_t CTRL; /**< MRT Control register. This register controls the MRT modes., array offset: 0x8, array step: 0x10 */ + __IO uint32_t STAT; /**< MRT Status register., array offset: 0xC, array step: 0x10 */ + } CHANNEL[4]; + uint8_t RESERVED_0[176]; + __IO uint32_t MODCFG; /**< Module Configuration register. This register provides information about this particular MRT instance, and allows choosing an overall mode for the idle channel feature., offset: 0xF0 */ + __I uint32_t IDLE_CH; /**< Idle channel register. This register returns the number of the first idle channel., offset: 0xF4 */ + __IO uint32_t IRQ_FLAG; /**< Global interrupt flag register, offset: 0xF8 */ +} MRT_Type; + +/* ---------------------------------------------------------------------------- + -- MRT Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup MRT_Register_Masks MRT Register Masks + * @{ + */ + +/*! @name CHANNEL_INTVAL - MRT Time interval value register. This value is loaded into the TIMER register. */ +/*! @{ */ + +#define MRT_CHANNEL_INTVAL_IVALUE_MASK (0xFFFFFFU) +#define MRT_CHANNEL_INTVAL_IVALUE_SHIFT (0U) +/*! IVALUE - Time interval load value. This value is loaded into the TIMERn register and the MRT + * channel n starts counting down from IVALUE -1. If the timer is idle, writing a non-zero value to + * this bit field starts the timer immediately. If the timer is running, writing a zero to this + * bit field does the following: If LOAD = 1, the timer stops immediately. If LOAD = 0, the timer + * stops at the end of the time interval. + */ +#define MRT_CHANNEL_INTVAL_IVALUE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_INTVAL_IVALUE_SHIFT)) & MRT_CHANNEL_INTVAL_IVALUE_MASK) + +#define MRT_CHANNEL_INTVAL_LOAD_MASK (0x80000000U) +#define MRT_CHANNEL_INTVAL_LOAD_SHIFT (31U) +/*! LOAD - Determines how the timer interval value IVALUE -1 is loaded into the TIMERn register. + * This bit is write-only. Reading this bit always returns 0. + * 0b0..No force load. The load from the INTVALn register to the TIMERn register is processed at the end of the + * time interval if the repeat mode is selected. + * 0b1..Force load. The INTVALn interval value IVALUE -1 is immediately loaded into the TIMERn register while TIMERn is running. + */ +#define MRT_CHANNEL_INTVAL_LOAD(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_INTVAL_LOAD_SHIFT)) & MRT_CHANNEL_INTVAL_LOAD_MASK) +/*! @} */ + +/* The count of MRT_CHANNEL_INTVAL */ +#define MRT_CHANNEL_INTVAL_COUNT (4U) + +/*! @name CHANNEL_TIMER - MRT Timer register. This register reads the value of the down-counter. */ +/*! @{ */ + +#define MRT_CHANNEL_TIMER_VALUE_MASK (0xFFFFFFU) +#define MRT_CHANNEL_TIMER_VALUE_SHIFT (0U) +/*! VALUE - Holds the current timer value of the down-counter. The initial value of the TIMERn + * register is loaded as IVALUE - 1 from the INTVALn register either at the end of the time interval + * or immediately in the following cases: INTVALn register is updated in the idle state. INTVALn + * register is updated with LOAD = 1. When the timer is in idle state, reading this bit fields + * returns -1 (0x00FF FFFF). + */ +#define MRT_CHANNEL_TIMER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_TIMER_VALUE_SHIFT)) & MRT_CHANNEL_TIMER_VALUE_MASK) +/*! @} */ + +/* The count of MRT_CHANNEL_TIMER */ +#define MRT_CHANNEL_TIMER_COUNT (4U) + +/*! @name CHANNEL_CTRL - MRT Control register. This register controls the MRT modes. */ +/*! @{ */ + +#define MRT_CHANNEL_CTRL_INTEN_MASK (0x1U) +#define MRT_CHANNEL_CTRL_INTEN_SHIFT (0U) +/*! INTEN - Enable the TIMERn interrupt. + * 0b0..Disabled. TIMERn interrupt is disabled. + * 0b1..Enabled. TIMERn interrupt is enabled. + */ +#define MRT_CHANNEL_CTRL_INTEN(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_CTRL_INTEN_SHIFT)) & MRT_CHANNEL_CTRL_INTEN_MASK) + +#define MRT_CHANNEL_CTRL_MODE_MASK (0x6U) +#define MRT_CHANNEL_CTRL_MODE_SHIFT (1U) +/*! MODE - Selects timer mode. + * 0b00..Repeat interrupt mode. + * 0b01..One-shot interrupt mode. + * 0b10..One-shot stall mode. + * 0b11..Reserved. + */ +#define MRT_CHANNEL_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_CTRL_MODE_SHIFT)) & MRT_CHANNEL_CTRL_MODE_MASK) +/*! @} */ + +/* The count of MRT_CHANNEL_CTRL */ +#define MRT_CHANNEL_CTRL_COUNT (4U) + +/*! @name CHANNEL_STAT - MRT Status register. */ +/*! @{ */ + +#define MRT_CHANNEL_STAT_INTFLAG_MASK (0x1U) +#define MRT_CHANNEL_STAT_INTFLAG_SHIFT (0U) +/*! INTFLAG - Monitors the interrupt flag. + * 0b0..No pending interrupt. Writing a zero is equivalent to no operation. + * 0b1..Pending interrupt. The interrupt is pending because TIMERn has reached the end of the time interval. If + * the INTEN bit in the CONTROLn is also set to 1, the interrupt for timer channel n and the global interrupt + * are raised. Writing a 1 to this bit clears the interrupt request. + */ +#define MRT_CHANNEL_STAT_INTFLAG(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_INTFLAG_SHIFT)) & MRT_CHANNEL_STAT_INTFLAG_MASK) + +#define MRT_CHANNEL_STAT_RUN_MASK (0x2U) +#define MRT_CHANNEL_STAT_RUN_SHIFT (1U) +/*! RUN - Indicates the state of TIMERn. This bit is read-only. + * 0b0..Idle state. TIMERn is stopped. + * 0b1..Running. TIMERn is running. + */ +#define MRT_CHANNEL_STAT_RUN(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_RUN_SHIFT)) & MRT_CHANNEL_STAT_RUN_MASK) + +#define MRT_CHANNEL_STAT_INUSE_MASK (0x4U) +#define MRT_CHANNEL_STAT_INUSE_SHIFT (2U) +/*! INUSE - Channel In Use flag. Operating details depend on the MULTITASK bit in the MODCFG + * register, and affects the use of IDLE_CH. See Idle channel register for details of the two operating + * modes. + * 0b0..This channel is not in use. + * 0b1..This channel is in use. + */ +#define MRT_CHANNEL_STAT_INUSE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_INUSE_SHIFT)) & MRT_CHANNEL_STAT_INUSE_MASK) +/*! @} */ + +/* The count of MRT_CHANNEL_STAT */ +#define MRT_CHANNEL_STAT_COUNT (4U) + +/*! @name MODCFG - Module Configuration register. This register provides information about this particular MRT instance, and allows choosing an overall mode for the idle channel feature. */ +/*! @{ */ + +#define MRT_MODCFG_NOC_MASK (0xFU) +#define MRT_MODCFG_NOC_SHIFT (0U) +/*! NOC - Identifies the number of channels in this MRT.(4 channels on this device.) + */ +#define MRT_MODCFG_NOC(x) (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_NOC_SHIFT)) & MRT_MODCFG_NOC_MASK) + +#define MRT_MODCFG_NOB_MASK (0x1F0U) +#define MRT_MODCFG_NOB_SHIFT (4U) +/*! NOB - Identifies the number of timer bits in this MRT. (24 bits wide on this device.) + */ +#define MRT_MODCFG_NOB(x) (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_NOB_SHIFT)) & MRT_MODCFG_NOB_MASK) + +#define MRT_MODCFG_MULTITASK_MASK (0x80000000U) +#define MRT_MODCFG_MULTITASK_SHIFT (31U) +/*! MULTITASK - Selects the operating mode for the INUSE flags and the IDLE_CH register. + * 0b0..Hardware status mode. In this mode, the INUSE(n) flags for all channels are reset. + * 0b1..Multi-task mode. + */ +#define MRT_MODCFG_MULTITASK(x) (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_MULTITASK_SHIFT)) & MRT_MODCFG_MULTITASK_MASK) +/*! @} */ + +/*! @name IDLE_CH - Idle channel register. This register returns the number of the first idle channel. */ +/*! @{ */ + +#define MRT_IDLE_CH_CHAN_MASK (0xF0U) +#define MRT_IDLE_CH_CHAN_SHIFT (4U) +/*! CHAN - Idle channel. Reading the CHAN bits, returns the lowest idle timer channel. The number is + * positioned such that it can be used as an offset from the MRT base address in order to access + * the registers for the allocated channel. If all timer channels are running, CHAN = 0xF. See + * text above for more details. + */ +#define MRT_IDLE_CH_CHAN(x) (((uint32_t)(((uint32_t)(x)) << MRT_IDLE_CH_CHAN_SHIFT)) & MRT_IDLE_CH_CHAN_MASK) +/*! @} */ + +/*! @name IRQ_FLAG - Global interrupt flag register */ +/*! @{ */ + +#define MRT_IRQ_FLAG_GFLAG0_MASK (0x1U) +#define MRT_IRQ_FLAG_GFLAG0_SHIFT (0U) +/*! GFLAG0 - Monitors the interrupt flag of TIMER0. + * 0b0..No pending interrupt. Writing a zero is equivalent to no operation. + * 0b1..Pending interrupt. The interrupt is pending because TIMER0 has reached the end of the time interval. If + * the INTEN bit in the CONTROL0 register is also set to 1, the interrupt for timer channel 0 and the global + * interrupt are raised. Writing a 1 to this bit clears the interrupt request. + */ +#define MRT_IRQ_FLAG_GFLAG0(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG0_SHIFT)) & MRT_IRQ_FLAG_GFLAG0_MASK) + +#define MRT_IRQ_FLAG_GFLAG1_MASK (0x2U) +#define MRT_IRQ_FLAG_GFLAG1_SHIFT (1U) +/*! GFLAG1 - Monitors the interrupt flag of TIMER1. See description of channel 0. + */ +#define MRT_IRQ_FLAG_GFLAG1(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG1_SHIFT)) & MRT_IRQ_FLAG_GFLAG1_MASK) + +#define MRT_IRQ_FLAG_GFLAG2_MASK (0x4U) +#define MRT_IRQ_FLAG_GFLAG2_SHIFT (2U) +/*! GFLAG2 - Monitors the interrupt flag of TIMER2. See description of channel 0. + */ +#define MRT_IRQ_FLAG_GFLAG2(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG2_SHIFT)) & MRT_IRQ_FLAG_GFLAG2_MASK) + +#define MRT_IRQ_FLAG_GFLAG3_MASK (0x8U) +#define MRT_IRQ_FLAG_GFLAG3_SHIFT (3U) +/*! GFLAG3 - Monitors the interrupt flag of TIMER3. See description of channel 0. + */ +#define MRT_IRQ_FLAG_GFLAG3(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG3_SHIFT)) & MRT_IRQ_FLAG_GFLAG3_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group MRT_Register_Masks */ + + +/* MRT - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral MRT0 base address */ + #define MRT0_BASE (0x5000D000u) + /** Peripheral MRT0 base address */ + #define MRT0_BASE_NS (0x4000D000u) + /** Peripheral MRT0 base pointer */ + #define MRT0 ((MRT_Type *)MRT0_BASE) + /** Peripheral MRT0 base pointer */ + #define MRT0_NS ((MRT_Type *)MRT0_BASE_NS) + /** Array initializer of MRT peripheral base addresses */ + #define MRT_BASE_ADDRS { MRT0_BASE } + /** Array initializer of MRT peripheral base pointers */ + #define MRT_BASE_PTRS { MRT0 } + /** Array initializer of MRT peripheral base addresses */ + #define MRT_BASE_ADDRS_NS { MRT0_BASE_NS } + /** Array initializer of MRT peripheral base pointers */ + #define MRT_BASE_PTRS_NS { MRT0_NS } +#else + /** Peripheral MRT0 base address */ + #define MRT0_BASE (0x4000D000u) + /** Peripheral MRT0 base pointer */ + #define MRT0 ((MRT_Type *)MRT0_BASE) + /** Array initializer of MRT peripheral base addresses */ + #define MRT_BASE_ADDRS { MRT0_BASE } + /** Array initializer of MRT peripheral base pointers */ + #define MRT_BASE_PTRS { MRT0 } +#endif +/** Interrupt vectors for the MRT peripheral type */ +#define MRT_IRQS { MRT0_IRQn } + +/*! + * @} + */ /* end of group MRT_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- OSTIMER Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup OSTIMER_Peripheral_Access_Layer OSTIMER Peripheral Access Layer + * @{ + */ + +/** OSTIMER - Register Layout Typedef */ +typedef struct { + __I uint32_t EVTIMERL; /**< EVTIMER Low Register, offset: 0x0 */ + __I uint32_t EVTIMERH; /**< EVTIMER High Register, offset: 0x4 */ + __I uint32_t CAPTURE_L; /**< Capture Low Register, offset: 0x8 */ + __I uint32_t CAPTURE_H; /**< Capture High Register, offset: 0xC */ + __IO uint32_t MATCH_L; /**< Match Low Register, offset: 0x10 */ + __IO uint32_t MATCH_H; /**< Match High Register, offset: 0x14 */ + uint8_t RESERVED_0[4]; + __IO uint32_t OSEVENT_CTRL; /**< OS_EVENT TIMER Control Register, offset: 0x1C */ +} OSTIMER_Type; + +/* ---------------------------------------------------------------------------- + -- OSTIMER Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup OSTIMER_Register_Masks OSTIMER Register Masks + * @{ + */ + +/*! @name EVTIMERL - EVTIMER Low Register */ +/*! @{ */ + +#define OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE_MASK (0xFFFFFFFFU) +#define OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE_SHIFT (0U) +/*! EVTIMER_COUNT_VALUE - A read reflects the current value of the lower 32 bits of the 42-bits + * EVTIMER. Note there is only one EVTIMER, readable from all domains. + */ +#define OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE_SHIFT)) & OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE_MASK) +/*! @} */ + +/*! @name EVTIMERH - EVTIMER High Register */ +/*! @{ */ + +#define OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE_MASK (0x3FFU) +#define OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE_SHIFT (0U) +/*! EVTIMER_COUNT_VALUE - A read reflects the current value of the upper 10 bits of the 42-bits + * EVTIMER. Note there is only one EVTIMER, readable from all domains. + */ +#define OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE_SHIFT)) & OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE_MASK) +/*! @} */ + +/*! @name CAPTURE_L - Capture Low Register */ +/*! @{ */ + +#define OSTIMER_CAPTURE_L_CAPTURE_VALUE_MASK (0xFFFFFFFFU) +#define OSTIMER_CAPTURE_L_CAPTURE_VALUE_SHIFT (0U) +/*! CAPTURE_VALUE - A read reflects the value of the lower 32 bits of the central 42-bits EVTIMER at + * the time the last capture signal was generated by the CPU (using CMSIS C function "__SEV();"). + */ +#define OSTIMER_CAPTURE_L_CAPTURE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_CAPTURE_L_CAPTURE_VALUE_SHIFT)) & OSTIMER_CAPTURE_L_CAPTURE_VALUE_MASK) +/*! @} */ + +/*! @name CAPTURE_H - Capture High Register */ +/*! @{ */ + +#define OSTIMER_CAPTURE_H_CAPTURE_VALUE_MASK (0x3FFU) +#define OSTIMER_CAPTURE_H_CAPTURE_VALUE_SHIFT (0U) +/*! CAPTURE_VALUE - A read reflects the value of the upper 10 bits of the central 42-bits EVTIMER at + * the time the last capture signal was generated by the CPU (using CMSIS C function "__SEV();"). + */ +#define OSTIMER_CAPTURE_H_CAPTURE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_CAPTURE_H_CAPTURE_VALUE_SHIFT)) & OSTIMER_CAPTURE_H_CAPTURE_VALUE_MASK) +/*! @} */ + +/*! @name MATCH_L - Match Low Register */ +/*! @{ */ + +#define OSTIMER_MATCH_L_MATCH_VALUE_MASK (0xFFFFFFFFU) +#define OSTIMER_MATCH_L_MATCH_VALUE_SHIFT (0U) +/*! MATCH_VALUE - The value written to the MATCH (L/H) register pair is compared against the central + * EVTIMER. When a match occurs, an interrupt request is generated if enabled. + */ +#define OSTIMER_MATCH_L_MATCH_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_MATCH_L_MATCH_VALUE_SHIFT)) & OSTIMER_MATCH_L_MATCH_VALUE_MASK) +/*! @} */ + +/*! @name MATCH_H - Match High Register */ +/*! @{ */ + +#define OSTIMER_MATCH_H_MATCH_VALUE_MASK (0x3FFU) +#define OSTIMER_MATCH_H_MATCH_VALUE_SHIFT (0U) +/*! MATCH_VALUE - The value written (upper 10 bits) to the MATCH (L/H) register pair is compared + * against the central EVTIMER. When a match occurs, an interrupt request is generated if enabled. + */ +#define OSTIMER_MATCH_H_MATCH_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_MATCH_H_MATCH_VALUE_SHIFT)) & OSTIMER_MATCH_H_MATCH_VALUE_MASK) +/*! @} */ + +/*! @name OSEVENT_CTRL - OS_EVENT TIMER Control Register */ +/*! @{ */ + +#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_MASK (0x1U) +#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_SHIFT (0U) +/*! OSTIMER_INTRFLAG - This bit is set when a match occurs between the central 42-bits EVTIMER and + * the value programmed in the match-register pair. This bit is cleared by writing a '1'. Writes + * to clear this bit are asynchronous. It should be done before a new match value is written into + * the MATCH_L/H registers. + */ +#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_SHIFT)) & OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_MASK) + +#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_MASK (0x2U) +#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_SHIFT (1U) +/*! OSTIMER_INTENA - When this bit is '1' an interrupt/wakeup request to the domain processor will + * be asserted when the OSTIMER_INTR flag is set. When this bit is '0', interrupt/wakeup requests + * due to the OSTIMER_INTR flag are blocked. + */ +#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_SHIFT)) & OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_MASK) + +#define OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_MASK (0x4U) +#define OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_SHIFT (2U) +/*! MATCH_WR_RDY - This bit will be low when it is safe to write to reload the Match Registers. In + * typical applications it should not be necessary to test this bit. [1] + */ +#define OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_SHIFT)) & OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group OSTIMER_Register_Masks */ + + +/* OSTIMER - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral OSTIMER base address */ + #define OSTIMER_BASE (0x5002D000u) + /** Peripheral OSTIMER base address */ + #define OSTIMER_BASE_NS (0x4002D000u) + /** Peripheral OSTIMER base pointer */ + #define OSTIMER ((OSTIMER_Type *)OSTIMER_BASE) + /** Peripheral OSTIMER base pointer */ + #define OSTIMER_NS ((OSTIMER_Type *)OSTIMER_BASE_NS) + /** Array initializer of OSTIMER peripheral base addresses */ + #define OSTIMER_BASE_ADDRS { OSTIMER_BASE } + /** Array initializer of OSTIMER peripheral base pointers */ + #define OSTIMER_BASE_PTRS { OSTIMER } + /** Array initializer of OSTIMER peripheral base addresses */ + #define OSTIMER_BASE_ADDRS_NS { OSTIMER_BASE_NS } + /** Array initializer of OSTIMER peripheral base pointers */ + #define OSTIMER_BASE_PTRS_NS { OSTIMER_NS } +#else + /** Peripheral OSTIMER base address */ + #define OSTIMER_BASE (0x4002D000u) + /** Peripheral OSTIMER base pointer */ + #define OSTIMER ((OSTIMER_Type *)OSTIMER_BASE) + /** Array initializer of OSTIMER peripheral base addresses */ + #define OSTIMER_BASE_ADDRS { OSTIMER_BASE } + /** Array initializer of OSTIMER peripheral base pointers */ + #define OSTIMER_BASE_PTRS { OSTIMER } +#endif +/** Interrupt vectors for the OSTIMER peripheral type */ +#define OSTIMER_IRQS { OS_EVENT_IRQn } + +/*! + * @} + */ /* end of group OSTIMER_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- PINT Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PINT_Peripheral_Access_Layer PINT Peripheral Access Layer + * @{ + */ + +/** PINT - Register Layout Typedef */ +typedef struct { + __IO uint32_t ISEL; /**< Pin Interrupt Mode register, offset: 0x0 */ + __IO uint32_t IENR; /**< Pin interrupt level or rising edge interrupt enable register, offset: 0x4 */ + __O uint32_t SIENR; /**< Pin interrupt level or rising edge interrupt set register, offset: 0x8 */ + __O uint32_t CIENR; /**< Pin interrupt level (rising edge interrupt) clear register, offset: 0xC */ + __IO uint32_t IENF; /**< Pin interrupt active level or falling edge interrupt enable register, offset: 0x10 */ + __O uint32_t SIENF; /**< Pin interrupt active level or falling edge interrupt set register, offset: 0x14 */ + __O uint32_t CIENF; /**< Pin interrupt active level or falling edge interrupt clear register, offset: 0x18 */ + __IO uint32_t RISE; /**< Pin interrupt rising edge register, offset: 0x1C */ + __IO uint32_t FALL; /**< Pin interrupt falling edge register, offset: 0x20 */ + __IO uint32_t IST; /**< Pin interrupt status register, offset: 0x24 */ + __IO uint32_t PMCTRL; /**< Pattern match interrupt control register, offset: 0x28 */ + __IO uint32_t PMSRC; /**< Pattern match interrupt bit-slice source register, offset: 0x2C */ + __IO uint32_t PMCFG; /**< Pattern match interrupt bit slice configuration register, offset: 0x30 */ +} PINT_Type; + +/* ---------------------------------------------------------------------------- + -- PINT Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PINT_Register_Masks PINT Register Masks + * @{ + */ + +/*! @name ISEL - Pin Interrupt Mode register */ +/*! @{ */ + +#define PINT_ISEL_PMODE_MASK (0xFFU) +#define PINT_ISEL_PMODE_SHIFT (0U) +/*! PMODE - Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt + * selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive + */ +#define PINT_ISEL_PMODE(x) (((uint32_t)(((uint32_t)(x)) << PINT_ISEL_PMODE_SHIFT)) & PINT_ISEL_PMODE_MASK) +/*! @} */ + +/*! @name IENR - Pin interrupt level or rising edge interrupt enable register */ +/*! @{ */ + +#define PINT_IENR_ENRL_MASK (0xFFU) +#define PINT_IENR_ENRL_SHIFT (0U) +/*! ENRL - Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the + * pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable + * rising edge or level interrupt. + */ +#define PINT_IENR_ENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_IENR_ENRL_SHIFT)) & PINT_IENR_ENRL_MASK) +/*! @} */ + +/*! @name SIENR - Pin interrupt level or rising edge interrupt set register */ +/*! @{ */ + +#define PINT_SIENR_SETENRL_MASK (0xFFU) +#define PINT_SIENR_SETENRL_SHIFT (0U) +/*! SETENRL - Ones written to this address set bits in the IENR, thus enabling interrupts. Bit n + * sets bit n in the IENR register. 0 = No operation. 1 = Enable rising edge or level interrupt. + */ +#define PINT_SIENR_SETENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_SIENR_SETENRL_SHIFT)) & PINT_SIENR_SETENRL_MASK) +/*! @} */ + +/*! @name CIENR - Pin interrupt level (rising edge interrupt) clear register */ +/*! @{ */ + +#define PINT_CIENR_CENRL_MASK (0xFFU) +#define PINT_CIENR_CENRL_SHIFT (0U) +/*! CENRL - Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit + * n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level + * interrupt. + */ +#define PINT_CIENR_CENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_CIENR_CENRL_SHIFT)) & PINT_CIENR_CENRL_MASK) +/*! @} */ + +/*! @name IENF - Pin interrupt active level or falling edge interrupt enable register */ +/*! @{ */ + +#define PINT_IENF_ENAF_MASK (0xFFU) +#define PINT_IENF_ENAF_SHIFT (0U) +/*! ENAF - Enables the falling edge or configures the active level interrupt for each pin interrupt. + * Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt + * or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active + * interrupt level HIGH. + */ +#define PINT_IENF_ENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_IENF_ENAF_SHIFT)) & PINT_IENF_ENAF_MASK) +/*! @} */ + +/*! @name SIENF - Pin interrupt active level or falling edge interrupt set register */ +/*! @{ */ + +#define PINT_SIENF_SETENAF_MASK (0xFFU) +#define PINT_SIENF_SETENAF_SHIFT (0U) +/*! SETENAF - Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n + * sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable + * falling edge interrupt. + */ +#define PINT_SIENF_SETENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_SIENF_SETENAF_SHIFT)) & PINT_SIENF_SETENAF_MASK) +/*! @} */ + +/*! @name CIENF - Pin interrupt active level or falling edge interrupt clear register */ +/*! @{ */ + +#define PINT_CIENF_CENAF_MASK (0xFFU) +#define PINT_CIENF_CENAF_SHIFT (0U) +/*! CENAF - Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n + * clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or + * falling edge interrupt disabled. + */ +#define PINT_CIENF_CENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_CIENF_CENAF_SHIFT)) & PINT_CIENF_CENAF_MASK) +/*! @} */ + +/*! @name RISE - Pin interrupt rising edge register */ +/*! @{ */ + +#define PINT_RISE_RDET_MASK (0xFFU) +#define PINT_RISE_RDET_SHIFT (0U) +/*! RDET - Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read + * 0: No rising edge has been detected on this pin since Reset or the last time a one was written + * to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the + * last time a one was written to this bit. Write 1: clear rising edge detection for this pin. + */ +#define PINT_RISE_RDET(x) (((uint32_t)(((uint32_t)(x)) << PINT_RISE_RDET_SHIFT)) & PINT_RISE_RDET_MASK) +/*! @} */ + +/*! @name FALL - Pin interrupt falling edge register */ +/*! @{ */ + +#define PINT_FALL_FDET_MASK (0xFFU) +#define PINT_FALL_FDET_SHIFT (0U) +/*! FDET - Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read + * 0: No falling edge has been detected on this pin since Reset or the last time a one was + * written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or + * the last time a one was written to this bit. Write 1: clear falling edge detection for this + * pin. + */ +#define PINT_FALL_FDET(x) (((uint32_t)(((uint32_t)(x)) << PINT_FALL_FDET_SHIFT)) & PINT_FALL_FDET_MASK) +/*! @} */ + +/*! @name IST - Pin interrupt status register */ +/*! @{ */ + +#define PINT_IST_PSTAT_MASK (0xFFU) +#define PINT_IST_PSTAT_SHIFT (0U) +/*! PSTAT - Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts + * the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for + * this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this + * interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. + * Write 1 (level-sensitive): switch the active level for this pin (in the IENF register). + */ +#define PINT_IST_PSTAT(x) (((uint32_t)(((uint32_t)(x)) << PINT_IST_PSTAT_SHIFT)) & PINT_IST_PSTAT_MASK) +/*! @} */ + +/*! @name PMCTRL - Pattern match interrupt control register */ +/*! @{ */ + +#define PINT_PMCTRL_SEL_PMATCH_MASK (0x1U) +#define PINT_PMCTRL_SEL_PMATCH_SHIFT (0U) +/*! SEL_PMATCH - Specifies whether the 8 pin interrupts are controlled by the pin interrupt function or by the pattern match function. + * 0b0..Pin interrupt. Interrupts are driven in response to the standard pin interrupt function. + * 0b1..Pattern match. Interrupts are driven in response to pattern matches. + */ +#define PINT_PMCTRL_SEL_PMATCH(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_SEL_PMATCH_SHIFT)) & PINT_PMCTRL_SEL_PMATCH_MASK) + +#define PINT_PMCTRL_ENA_RXEV_MASK (0x2U) +#define PINT_PMCTRL_ENA_RXEV_SHIFT (1U) +/*! ENA_RXEV - Enables the RXEV output to the CPU and/or to a GPIO output when the specified boolean expression evaluates to true. + * 0b0..Disabled. RXEV output to the CPU is disabled. + * 0b1..Enabled. RXEV output to the CPU is enabled. + */ +#define PINT_PMCTRL_ENA_RXEV(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_ENA_RXEV_SHIFT)) & PINT_PMCTRL_ENA_RXEV_MASK) + +#define PINT_PMCTRL_PMAT_MASK (0xFF000000U) +#define PINT_PMCTRL_PMAT_SHIFT (24U) +/*! PMAT - This field displays the current state of pattern matches. A 1 in any bit of this field + * indicates that the corresponding product term is matched by the current state of the appropriate + * inputs. + */ +#define PINT_PMCTRL_PMAT(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_PMAT_SHIFT)) & PINT_PMCTRL_PMAT_MASK) +/*! @} */ + +/*! @name PMSRC - Pattern match interrupt bit-slice source register */ +/*! @{ */ + +#define PINT_PMSRC_SRC0_MASK (0x700U) +#define PINT_PMSRC_SRC0_SHIFT (8U) +/*! SRC0 - Selects the input source for bit slice 0 + * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 0. + * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 0. + * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 0. + * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 0. + * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 0. + * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 0. + * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 0. + * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 0. + */ +#define PINT_PMSRC_SRC0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC0_SHIFT)) & PINT_PMSRC_SRC0_MASK) + +#define PINT_PMSRC_SRC1_MASK (0x3800U) +#define PINT_PMSRC_SRC1_SHIFT (11U) +/*! SRC1 - Selects the input source for bit slice 1 + * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 1. + * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 1. + * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 1. + * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 1. + * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 1. + * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 1. + * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 1. + * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 1. + */ +#define PINT_PMSRC_SRC1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC1_SHIFT)) & PINT_PMSRC_SRC1_MASK) + +#define PINT_PMSRC_SRC2_MASK (0x1C000U) +#define PINT_PMSRC_SRC2_SHIFT (14U) +/*! SRC2 - Selects the input source for bit slice 2 + * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 2. + * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 2. + * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 2. + * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 2. + * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 2. + * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 2. + * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 2. + * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 2. + */ +#define PINT_PMSRC_SRC2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC2_SHIFT)) & PINT_PMSRC_SRC2_MASK) + +#define PINT_PMSRC_SRC3_MASK (0xE0000U) +#define PINT_PMSRC_SRC3_SHIFT (17U) +/*! SRC3 - Selects the input source for bit slice 3 + * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 3. + * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 3. + * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 3. + * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 3. + * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 3. + * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 3. + * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 3. + * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 3. + */ +#define PINT_PMSRC_SRC3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC3_SHIFT)) & PINT_PMSRC_SRC3_MASK) + +#define PINT_PMSRC_SRC4_MASK (0x700000U) +#define PINT_PMSRC_SRC4_SHIFT (20U) +/*! SRC4 - Selects the input source for bit slice 4 + * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 4. + * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 4. + * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 4. + * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 4. + * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 4. + * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 4. + * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 4. + * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 4. + */ +#define PINT_PMSRC_SRC4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC4_SHIFT)) & PINT_PMSRC_SRC4_MASK) + +#define PINT_PMSRC_SRC5_MASK (0x3800000U) +#define PINT_PMSRC_SRC5_SHIFT (23U) +/*! SRC5 - Selects the input source for bit slice 5 + * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 5. + * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 5. + * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 5. + * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 5. + * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 5. + * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 5. + * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 5. + * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 5. + */ +#define PINT_PMSRC_SRC5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC5_SHIFT)) & PINT_PMSRC_SRC5_MASK) + +#define PINT_PMSRC_SRC6_MASK (0x1C000000U) +#define PINT_PMSRC_SRC6_SHIFT (26U) +/*! SRC6 - Selects the input source for bit slice 6 + * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 6. + * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 6. + * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 6. + * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 6. + * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 6. + * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 6. + * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 6. + * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 6. + */ +#define PINT_PMSRC_SRC6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC6_SHIFT)) & PINT_PMSRC_SRC6_MASK) + +#define PINT_PMSRC_SRC7_MASK (0xE0000000U) +#define PINT_PMSRC_SRC7_SHIFT (29U) +/*! SRC7 - Selects the input source for bit slice 7 + * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 7. + * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 7. + * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 7. + * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 7. + * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 7. + * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 7. + * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 7. + * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 7. + */ +#define PINT_PMSRC_SRC7(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC7_SHIFT)) & PINT_PMSRC_SRC7_MASK) +/*! @} */ + +/*! @name PMCFG - Pattern match interrupt bit slice configuration register */ +/*! @{ */ + +#define PINT_PMCFG_PROD_ENDPTS0_MASK (0x1U) +#define PINT_PMCFG_PROD_ENDPTS0_SHIFT (0U) +/*! PROD_ENDPTS0 - Determines whether slice 0 is an endpoint. + * 0b0..No effect. Slice 0 is not an endpoint. + * 0b1..endpoint. Slice 0 is the endpoint of a product term (minterm). Pin interrupt 0 in the NVIC is raised if the minterm evaluates as true. + */ +#define PINT_PMCFG_PROD_ENDPTS0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS0_SHIFT)) & PINT_PMCFG_PROD_ENDPTS0_MASK) + +#define PINT_PMCFG_PROD_ENDPTS1_MASK (0x2U) +#define PINT_PMCFG_PROD_ENDPTS1_SHIFT (1U) +/*! PROD_ENDPTS1 - Determines whether slice 1 is an endpoint. + * 0b0..No effect. Slice 1 is not an endpoint. + * 0b1..endpoint. Slice 1 is the endpoint of a product term (minterm). Pin interrupt 1 in the NVIC is raised if the minterm evaluates as true. + */ +#define PINT_PMCFG_PROD_ENDPTS1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS1_SHIFT)) & PINT_PMCFG_PROD_ENDPTS1_MASK) + +#define PINT_PMCFG_PROD_ENDPTS2_MASK (0x4U) +#define PINT_PMCFG_PROD_ENDPTS2_SHIFT (2U) +/*! PROD_ENDPTS2 - Determines whether slice 2 is an endpoint. + * 0b0..No effect. Slice 2 is not an endpoint. + * 0b1..endpoint. Slice 2 is the endpoint of a product term (minterm). Pin interrupt 2 in the NVIC is raised if the minterm evaluates as true. + */ +#define PINT_PMCFG_PROD_ENDPTS2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS2_SHIFT)) & PINT_PMCFG_PROD_ENDPTS2_MASK) + +#define PINT_PMCFG_PROD_ENDPTS3_MASK (0x8U) +#define PINT_PMCFG_PROD_ENDPTS3_SHIFT (3U) +/*! PROD_ENDPTS3 - Determines whether slice 3 is an endpoint. + * 0b0..No effect. Slice 3 is not an endpoint. + * 0b1..endpoint. Slice 3 is the endpoint of a product term (minterm). Pin interrupt 3 in the NVIC is raised if the minterm evaluates as true. + */ +#define PINT_PMCFG_PROD_ENDPTS3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS3_SHIFT)) & PINT_PMCFG_PROD_ENDPTS3_MASK) + +#define PINT_PMCFG_PROD_ENDPTS4_MASK (0x10U) +#define PINT_PMCFG_PROD_ENDPTS4_SHIFT (4U) +/*! PROD_ENDPTS4 - Determines whether slice 4 is an endpoint. + * 0b0..No effect. Slice 4 is not an endpoint. + * 0b1..endpoint. Slice 4 is the endpoint of a product term (minterm). Pin interrupt 4 in the NVIC is raised if the minterm evaluates as true. + */ +#define PINT_PMCFG_PROD_ENDPTS4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS4_SHIFT)) & PINT_PMCFG_PROD_ENDPTS4_MASK) + +#define PINT_PMCFG_PROD_ENDPTS5_MASK (0x20U) +#define PINT_PMCFG_PROD_ENDPTS5_SHIFT (5U) +/*! PROD_ENDPTS5 - Determines whether slice 5 is an endpoint. + * 0b0..No effect. Slice 5 is not an endpoint. + * 0b1..endpoint. Slice 5 is the endpoint of a product term (minterm). Pin interrupt 5 in the NVIC is raised if the minterm evaluates as true. + */ +#define PINT_PMCFG_PROD_ENDPTS5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS5_SHIFT)) & PINT_PMCFG_PROD_ENDPTS5_MASK) + +#define PINT_PMCFG_PROD_ENDPTS6_MASK (0x40U) +#define PINT_PMCFG_PROD_ENDPTS6_SHIFT (6U) +/*! PROD_ENDPTS6 - Determines whether slice 6 is an endpoint. + * 0b0..No effect. Slice 6 is not an endpoint. + * 0b1..endpoint. Slice 6 is the endpoint of a product term (minterm). Pin interrupt 6 in the NVIC is raised if the minterm evaluates as true. + */ +#define PINT_PMCFG_PROD_ENDPTS6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS6_SHIFT)) & PINT_PMCFG_PROD_ENDPTS6_MASK) + +#define PINT_PMCFG_CFG0_MASK (0x700U) +#define PINT_PMCFG_CFG0_SHIFT (8U) +/*! CFG0 - Specifies the match contribution condition for bit slice 0. + * 0b000..Constant HIGH. This bit slice always contributes to a product term match. + * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last + * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the + * PMSRC registers are written to. + * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last + * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the + * PMSRC registers are written to. + * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input + * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only + * cleared when the PMCFG or the PMSRC registers are written to. + * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. + * 0b101..Low level. Match occurs when there is a low level on the specified input. + * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). + * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or + * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit + * is cleared after one clock cycle. + */ +#define PINT_PMCFG_CFG0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG0_SHIFT)) & PINT_PMCFG_CFG0_MASK) + +#define PINT_PMCFG_CFG1_MASK (0x3800U) +#define PINT_PMCFG_CFG1_SHIFT (11U) +/*! CFG1 - Specifies the match contribution condition for bit slice 1. + * 0b000..Constant HIGH. This bit slice always contributes to a product term match. + * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last + * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the + * PMSRC registers are written to. + * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last + * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the + * PMSRC registers are written to. + * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input + * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only + * cleared when the PMCFG or the PMSRC registers are written to. + * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. + * 0b101..Low level. Match occurs when there is a low level on the specified input. + * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). + * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or + * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit + * is cleared after one clock cycle. + */ +#define PINT_PMCFG_CFG1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG1_SHIFT)) & PINT_PMCFG_CFG1_MASK) + +#define PINT_PMCFG_CFG2_MASK (0x1C000U) +#define PINT_PMCFG_CFG2_SHIFT (14U) +/*! CFG2 - Specifies the match contribution condition for bit slice 2. + * 0b000..Constant HIGH. This bit slice always contributes to a product term match. + * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last + * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the + * PMSRC registers are written to. + * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last + * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the + * PMSRC registers are written to. + * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input + * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only + * cleared when the PMCFG or the PMSRC registers are written to. + * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. + * 0b101..Low level. Match occurs when there is a low level on the specified input. + * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). + * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or + * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit + * is cleared after one clock cycle. + */ +#define PINT_PMCFG_CFG2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG2_SHIFT)) & PINT_PMCFG_CFG2_MASK) + +#define PINT_PMCFG_CFG3_MASK (0xE0000U) +#define PINT_PMCFG_CFG3_SHIFT (17U) +/*! CFG3 - Specifies the match contribution condition for bit slice 3. + * 0b000..Constant HIGH. This bit slice always contributes to a product term match. + * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last + * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the + * PMSRC registers are written to. + * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last + * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the + * PMSRC registers are written to. + * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input + * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only + * cleared when the PMCFG or the PMSRC registers are written to. + * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. + * 0b101..Low level. Match occurs when there is a low level on the specified input. + * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). + * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or + * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit + * is cleared after one clock cycle. + */ +#define PINT_PMCFG_CFG3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG3_SHIFT)) & PINT_PMCFG_CFG3_MASK) + +#define PINT_PMCFG_CFG4_MASK (0x700000U) +#define PINT_PMCFG_CFG4_SHIFT (20U) +/*! CFG4 - Specifies the match contribution condition for bit slice 4. + * 0b000..Constant HIGH. This bit slice always contributes to a product term match. + * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last + * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the + * PMSRC registers are written to. + * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last + * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the + * PMSRC registers are written to. + * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input + * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only + * cleared when the PMCFG or the PMSRC registers are written to. + * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. + * 0b101..Low level. Match occurs when there is a low level on the specified input. + * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). + * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or + * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit + * is cleared after one clock cycle. + */ +#define PINT_PMCFG_CFG4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG4_SHIFT)) & PINT_PMCFG_CFG4_MASK) + +#define PINT_PMCFG_CFG5_MASK (0x3800000U) +#define PINT_PMCFG_CFG5_SHIFT (23U) +/*! CFG5 - Specifies the match contribution condition for bit slice 5. + * 0b000..Constant HIGH. This bit slice always contributes to a product term match. + * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last + * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the + * PMSRC registers are written to. + * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last + * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the + * PMSRC registers are written to. + * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input + * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only + * cleared when the PMCFG or the PMSRC registers are written to. + * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. + * 0b101..Low level. Match occurs when there is a low level on the specified input. + * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). + * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or + * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit + * is cleared after one clock cycle. + */ +#define PINT_PMCFG_CFG5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG5_SHIFT)) & PINT_PMCFG_CFG5_MASK) + +#define PINT_PMCFG_CFG6_MASK (0x1C000000U) +#define PINT_PMCFG_CFG6_SHIFT (26U) +/*! CFG6 - Specifies the match contribution condition for bit slice 6. + * 0b000..Constant HIGH. This bit slice always contributes to a product term match. + * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last + * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the + * PMSRC registers are written to. + * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last + * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the + * PMSRC registers are written to. + * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input + * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only + * cleared when the PMCFG or the PMSRC registers are written to. + * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. + * 0b101..Low level. Match occurs when there is a low level on the specified input. + * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). + * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or + * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit + * is cleared after one clock cycle. + */ +#define PINT_PMCFG_CFG6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG6_SHIFT)) & PINT_PMCFG_CFG6_MASK) + +#define PINT_PMCFG_CFG7_MASK (0xE0000000U) +#define PINT_PMCFG_CFG7_SHIFT (29U) +/*! CFG7 - Specifies the match contribution condition for bit slice 7. + * 0b000..Constant HIGH. This bit slice always contributes to a product term match. + * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last + * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the + * PMSRC registers are written to. + * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last + * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the + * PMSRC registers are written to. + * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input + * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only + * cleared when the PMCFG or the PMSRC registers are written to. + * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. + * 0b101..Low level. Match occurs when there is a low level on the specified input. + * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). + * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or + * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit + * is cleared after one clock cycle. + */ +#define PINT_PMCFG_CFG7(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG7_SHIFT)) & PINT_PMCFG_CFG7_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group PINT_Register_Masks */ + + +/* PINT - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral PINT base address */ + #define PINT_BASE (0x50004000u) + /** Peripheral PINT base address */ + #define PINT_BASE_NS (0x40004000u) + /** Peripheral PINT base pointer */ + #define PINT ((PINT_Type *)PINT_BASE) + /** Peripheral PINT base pointer */ + #define PINT_NS ((PINT_Type *)PINT_BASE_NS) + /** Peripheral SECPINT base address */ + #define SECPINT_BASE (0x50005000u) + /** Peripheral SECPINT base address */ + #define SECPINT_BASE_NS (0x40005000u) + /** Peripheral SECPINT base pointer */ + #define SECPINT ((PINT_Type *)SECPINT_BASE) + /** Peripheral SECPINT base pointer */ + #define SECPINT_NS ((PINT_Type *)SECPINT_BASE_NS) + /** Array initializer of PINT peripheral base addresses */ + #define PINT_BASE_ADDRS { PINT_BASE, SECPINT_BASE } + /** Array initializer of PINT peripheral base pointers */ + #define PINT_BASE_PTRS { PINT, SECPINT } + /** Array initializer of PINT peripheral base addresses */ + #define PINT_BASE_ADDRS_NS { PINT_BASE_NS, SECPINT_BASE_NS } + /** Array initializer of PINT peripheral base pointers */ + #define PINT_BASE_PTRS_NS { PINT_NS, SECPINT_NS } +#else + /** Peripheral PINT base address */ + #define PINT_BASE (0x40004000u) + /** Peripheral PINT base pointer */ + #define PINT ((PINT_Type *)PINT_BASE) + /** Peripheral SECPINT base address */ + #define SECPINT_BASE (0x40005000u) + /** Peripheral SECPINT base pointer */ + #define SECPINT ((PINT_Type *)SECPINT_BASE) + /** Array initializer of PINT peripheral base addresses */ + #define PINT_BASE_ADDRS { PINT_BASE, SECPINT_BASE } + /** Array initializer of PINT peripheral base pointers */ + #define PINT_BASE_PTRS { PINT, SECPINT } +#endif +/** Interrupt vectors for the PINT peripheral type */ +#define PINT_IRQS { PIN_INT0_IRQn, PIN_INT1_IRQn, PIN_INT2_IRQn, PIN_INT3_IRQn, PIN_INT4_IRQn, PIN_INT5_IRQn, PIN_INT6_IRQn, PIN_INT7_IRQn, SEC_GPIO_INT0_IRQ0_IRQn, SEC_GPIO_INT0_IRQ1_IRQn } + +/*! + * @} + */ /* end of group PINT_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- PLU Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PLU_Peripheral_Access_Layer PLU Peripheral Access Layer + * @{ + */ + +/** PLU - Register Layout Typedef */ +typedef struct { + struct { /* offset: 0x0, array step: 0x20 */ + __IO uint32_t INP_MUX[5]; /**< LUTn input x MUX, array offset: 0x0, array step: index*0x20, index2*0x4 */ + uint8_t RESERVED_0[12]; + } LUT[26]; + uint8_t RESERVED_0[1216]; + __IO uint32_t LUT_TRUTH[26]; /**< Specifies the Truth Table contents for LUT0..Specifies the Truth Table contents for LUT25, array offset: 0x800, array step: 0x4 */ + uint8_t RESERVED_1[152]; + __I uint32_t OUTPUTS; /**< Provides the current state of the 8 designated PLU Outputs., offset: 0x900 */ + __IO uint32_t WAKEINT_CTRL; /**< Wakeup interrupt control for PLU, offset: 0x904 */ + uint8_t RESERVED_2[760]; + __IO uint32_t OUTPUT_MUX[8]; /**< Selects the source to be connected to PLU Output 0..Selects the source to be connected to PLU Output 7, array offset: 0xC00, array step: 0x4 */ +} PLU_Type; + +/* ---------------------------------------------------------------------------- + -- PLU Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PLU_Register_Masks PLU Register Masks + * @{ + */ + +/*! @name LUT_INP_MUX - LUTn input x MUX */ +/*! @{ */ + +#define PLU_LUT_INP_MUX_LUTn_INPx_MASK (0x3FU) +#define PLU_LUT_INP_MUX_LUTn_INPx_SHIFT (0U) +/*! LUTn_INPx - Selects the input source to be connected to LUT25 input4. For each LUT, the slot + * associated with the output from LUTn itself is tied low. + * 0b000000..The PLU primary inputs 0. + * 0b000001..The PLU primary inputs 1. + * 0b000010..The PLU primary inputs 2. + * 0b000011..The PLU primary inputs 3. + * 0b000100..The PLU primary inputs 4. + * 0b000101..The PLU primary inputs 5. + * 0b000110..The output of LUT0. + * 0b000111..The output of LUT1. + * 0b001000..The output of LUT2. + * 0b001001..The output of LUT3. + * 0b001010..The output of LUT4. + * 0b001011..The output of LUT5. + * 0b001100..The output of LUT6. + * 0b001101..The output of LUT7. + * 0b001110..The output of LUT8. + * 0b001111..The output of LUT9. + * 0b010000..The output of LUT10. + * 0b010001..The output of LUT11. + * 0b010010..The output of LUT12. + * 0b010011..The output of LUT13. + * 0b010100..The output of LUT14. + * 0b010101..The output of LUT15. + * 0b010110..The output of LUT16. + * 0b010111..The output of LUT17. + * 0b011000..The output of LUT18. + * 0b011001..The output of LUT19. + * 0b011010..The output of LUT20. + * 0b011011..The output of LUT21. + * 0b011100..The output of LUT22. + * 0b011101..The output of LUT23. + * 0b011110..The output of LUT24. + * 0b011111..The output of LUT25. + * 0b100000..state(0). + * 0b100001..state(1). + * 0b100010..state(2). + * 0b100011..state(3). + */ +#define PLU_LUT_INP_MUX_LUTn_INPx(x) (((uint32_t)(((uint32_t)(x)) << PLU_LUT_INP_MUX_LUTn_INPx_SHIFT)) & PLU_LUT_INP_MUX_LUTn_INPx_MASK) +/*! @} */ + +/* The count of PLU_LUT_INP_MUX */ +#define PLU_LUT_INP_MUX_COUNT (26U) + +/* The count of PLU_LUT_INP_MUX */ +#define PLU_LUT_INP_MUX_COUNT2 (5U) + +/*! @name LUT_TRUTH - Specifies the Truth Table contents for LUT0..Specifies the Truth Table contents for LUT25 */ +/*! @{ */ + +#define PLU_LUT_TRUTH_LUTn_TRUTH_MASK (0xFFFFFFFFU) +#define PLU_LUT_TRUTH_LUTn_TRUTH_SHIFT (0U) +/*! LUTn_TRUTH - Specifies the Truth Table contents for LUT25.. + */ +#define PLU_LUT_TRUTH_LUTn_TRUTH(x) (((uint32_t)(((uint32_t)(x)) << PLU_LUT_TRUTH_LUTn_TRUTH_SHIFT)) & PLU_LUT_TRUTH_LUTn_TRUTH_MASK) +/*! @} */ + +/* The count of PLU_LUT_TRUTH */ +#define PLU_LUT_TRUTH_COUNT (26U) + +/*! @name OUTPUTS - Provides the current state of the 8 designated PLU Outputs. */ +/*! @{ */ + +#define PLU_OUTPUTS_OUTPUT_STATE_MASK (0xFFU) +#define PLU_OUTPUTS_OUTPUT_STATE_SHIFT (0U) +/*! OUTPUT_STATE - Provides the current state of the 8 designated PLU Outputs.. + */ +#define PLU_OUTPUTS_OUTPUT_STATE(x) (((uint32_t)(((uint32_t)(x)) << PLU_OUTPUTS_OUTPUT_STATE_SHIFT)) & PLU_OUTPUTS_OUTPUT_STATE_MASK) +/*! @} */ + +/*! @name WAKEINT_CTRL - Wakeup interrupt control for PLU */ +/*! @{ */ + +#define PLU_WAKEINT_CTRL_MASK_MASK (0xFFU) +#define PLU_WAKEINT_CTRL_MASK_SHIFT (0U) +/*! MASK - Interrupt mask (which of the 8 PLU Outputs contribute to interrupt) + */ +#define PLU_WAKEINT_CTRL_MASK(x) (((uint32_t)(((uint32_t)(x)) << PLU_WAKEINT_CTRL_MASK_SHIFT)) & PLU_WAKEINT_CTRL_MASK_MASK) + +#define PLU_WAKEINT_CTRL_FILTER_MODE_MASK (0x300U) +#define PLU_WAKEINT_CTRL_FILTER_MODE_SHIFT (8U) +/*! FILTER_MODE - control input of the PLU, add filtering for glitch. + * 0b00..Bypass mode. + * 0b01..Filter 1 clock period. + * 0b10..Filter 2 clock period. + * 0b11..Filter 3 clock period. + */ +#define PLU_WAKEINT_CTRL_FILTER_MODE(x) (((uint32_t)(((uint32_t)(x)) << PLU_WAKEINT_CTRL_FILTER_MODE_SHIFT)) & PLU_WAKEINT_CTRL_FILTER_MODE_MASK) + +#define PLU_WAKEINT_CTRL_FILTER_CLKSEL_MASK (0xC00U) +#define PLU_WAKEINT_CTRL_FILTER_CLKSEL_SHIFT (10U) +/*! FILTER_CLKSEL - hclk is divided by 2**filter_clksel. + * 0b00..Selects the 1 MHz low-power oscillator as the filter clock. + * 0b01..Selects the 12 Mhz FRO as the filter clock. + * 0b10..Selects a third filter clock source, if provided. + * 0b11..Reserved. + */ +#define PLU_WAKEINT_CTRL_FILTER_CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << PLU_WAKEINT_CTRL_FILTER_CLKSEL_SHIFT)) & PLU_WAKEINT_CTRL_FILTER_CLKSEL_MASK) + +#define PLU_WAKEINT_CTRL_LATCH_ENABLE_MASK (0x1000U) +#define PLU_WAKEINT_CTRL_LATCH_ENABLE_SHIFT (12U) +/*! LATCH_ENABLE - latch the interrupt , then can be cleared with next bit INTR_CLEAR + */ +#define PLU_WAKEINT_CTRL_LATCH_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PLU_WAKEINT_CTRL_LATCH_ENABLE_SHIFT)) & PLU_WAKEINT_CTRL_LATCH_ENABLE_MASK) + +#define PLU_WAKEINT_CTRL_INTR_CLEAR_MASK (0x2000U) +#define PLU_WAKEINT_CTRL_INTR_CLEAR_SHIFT (13U) +/*! INTR_CLEAR - Write to clear wakeint_latched + */ +#define PLU_WAKEINT_CTRL_INTR_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << PLU_WAKEINT_CTRL_INTR_CLEAR_SHIFT)) & PLU_WAKEINT_CTRL_INTR_CLEAR_MASK) +/*! @} */ + +/*! @name OUTPUT_MUX - Selects the source to be connected to PLU Output 0..Selects the source to be connected to PLU Output 7 */ +/*! @{ */ + +#define PLU_OUTPUT_MUX_OUTPUTn_MASK (0x1FU) +#define PLU_OUTPUT_MUX_OUTPUTn_SHIFT (0U) +/*! OUTPUTn - Selects the source to be connected to PLU Output 7. + * 0b00000..The PLU output 0. + * 0b00001..The PLU output 1. + * 0b00010..The PLU output 2. + * 0b00011..The PLU output 3. + * 0b00100..The PLU output 4. + * 0b00101..The PLU output 5. + * 0b00110..The PLU output 6. + * 0b00111..The PLU output 7. + * 0b01000..The PLU output 8. + * 0b01001..The PLU output 9. + * 0b01010..The PLU output 10. + * 0b01011..The PLU output 11. + * 0b01100..The PLU output 12. + * 0b01101..The PLU output 13. + * 0b01110..The PLU output 14. + * 0b01111..The PLU output 15. + * 0b10000..The PLU output 16. + * 0b10001..The PLU output 17. + * 0b10010..The PLU output 18. + * 0b10011..The PLU output 19. + * 0b10100..The PLU output 20. + * 0b10101..The PLU output 21. + * 0b10110..The PLU output 22. + * 0b10111..The PLU output 23. + * 0b11000..The PLU output 24. + * 0b11001..The PLU output 25. + * 0b11010..state(0). + * 0b11011..state(1). + * 0b11100..state(2). + * 0b11101..state(3). + */ +#define PLU_OUTPUT_MUX_OUTPUTn(x) (((uint32_t)(((uint32_t)(x)) << PLU_OUTPUT_MUX_OUTPUTn_SHIFT)) & PLU_OUTPUT_MUX_OUTPUTn_MASK) +/*! @} */ + +/* The count of PLU_OUTPUT_MUX */ +#define PLU_OUTPUT_MUX_COUNT (8U) + + +/*! + * @} + */ /* end of group PLU_Register_Masks */ + + +/* PLU - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral PLU base address */ + #define PLU_BASE (0x5003D000u) + /** Peripheral PLU base address */ + #define PLU_BASE_NS (0x4003D000u) + /** Peripheral PLU base pointer */ + #define PLU ((PLU_Type *)PLU_BASE) + /** Peripheral PLU base pointer */ + #define PLU_NS ((PLU_Type *)PLU_BASE_NS) + /** Array initializer of PLU peripheral base addresses */ + #define PLU_BASE_ADDRS { PLU_BASE } + /** Array initializer of PLU peripheral base pointers */ + #define PLU_BASE_PTRS { PLU } + /** Array initializer of PLU peripheral base addresses */ + #define PLU_BASE_ADDRS_NS { PLU_BASE_NS } + /** Array initializer of PLU peripheral base pointers */ + #define PLU_BASE_PTRS_NS { PLU_NS } +#else + /** Peripheral PLU base address */ + #define PLU_BASE (0x4003D000u) + /** Peripheral PLU base pointer */ + #define PLU ((PLU_Type *)PLU_BASE) + /** Array initializer of PLU peripheral base addresses */ + #define PLU_BASE_ADDRS { PLU_BASE } + /** Array initializer of PLU peripheral base pointers */ + #define PLU_BASE_PTRS { PLU } +#endif + +/*! + * @} + */ /* end of group PLU_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- PMC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer + * @{ + */ + +/** PMC - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[4]; + __I uint32_t STATUS; /**< Power Management Controller FSM (Finite State Machines) status, offset: 0x4 */ + __IO uint32_t RESETCTRL; /**< Reset Control [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0x8 */ + uint8_t RESERVED_1[4]; + __IO uint32_t DCDC0; /**< DCDC (first) control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0x10 */ + __IO uint32_t DCDC1; /**< DCDC (second) control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0x14 */ + uint8_t RESERVED_2[4]; + __IO uint32_t LDOPMU; /**< Power Management Unit (PMU) and Always-On domains LDO control [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0x1C */ + uint8_t RESERVED_3[16]; + __IO uint32_t BODVBAT; /**< VBAT Brown Out Dectector (BoD) control register [Reset by: PoR, Pin Reset, Software Reset], offset: 0x30 */ + uint8_t RESERVED_4[12]; + __IO uint32_t REFFASTWKUP; /**< Analog References fast wake-up Control register [Reset by: PoR], offset: 0x40 */ + uint8_t RESERVED_5[8]; + __IO uint32_t XTAL32K; /**< 32 KHz Crystal oscillator (XTAL) control register [Reset by: PoR, Brown Out Detectors Reset], offset: 0x4C */ + __IO uint32_t COMP; /**< Analog Comparator control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0x50 */ + uint8_t RESERVED_6[16]; + __IO uint32_t WAKEUPIOCTRL; /**< Deep Power Down wake-up source [Reset by: PoR, Pin Reset, Software Reset], offset: 0x64 */ + __IO uint32_t WAKEIOCAUSE; /**< Allows to identify the Wake-up I/O source from Deep Power Down mode, offset: 0x68 */ + uint8_t RESERVED_7[8]; + __IO uint32_t STATUSCLK; /**< FRO and XTAL status register [Reset by: PoR, Brown Out Detectors Reset], offset: 0x74 */ + uint8_t RESERVED_8[12]; + __IO uint32_t AOREG1; /**< General purpose always on domain data storage [Reset by: PoR, Brown Out Detectors Reset], offset: 0x84 */ + uint8_t RESERVED_9[8]; + __IO uint32_t MISCCTRL; /**< Dummy Control bus to PMU [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0x90 */ + uint8_t RESERVED_10[4]; + __IO uint32_t RTCOSC32K; /**< RTC 1 KHZ and 1 Hz clocks source control register [Reset by: PoR, Brown Out Detectors Reset], offset: 0x98 */ + __IO uint32_t OSTIMERr; /**< OS Timer control register [Reset by: PoR, Brown Out Detectors Reset], offset: 0x9C */ + uint8_t RESERVED_11[24]; + __IO uint32_t PDRUNCFG0; /**< Controls the power to various analog blocks [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0xB8 */ + uint8_t RESERVED_12[4]; + __O uint32_t PDRUNCFGSET0; /**< Controls the power to various analog blocks [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0xC0 */ + uint8_t RESERVED_13[4]; + __O uint32_t PDRUNCFGCLR0; /**< Controls the power to various analog blocks [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0xC8 */ + uint8_t RESERVED_14[8]; + __IO uint32_t SRAMCTRL; /**< All SRAMs common control signals [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Software Reset], offset: 0xD4 */ +} PMC_Type; + +/* ---------------------------------------------------------------------------- + -- PMC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PMC_Register_Masks PMC Register Masks + * @{ + */ + +/*! @name STATUS - Power Management Controller FSM (Finite State Machines) status */ +/*! @{ */ + +#define PMC_STATUS_FSMMAIN_MASK (0x7U) +#define PMC_STATUS_FSMMAIN_SHIFT (0U) +/*! FSMMAIN - Power Management Controller Main Finite State Machine (FSM) status. + * 0b000..POWER UP : The IC is powering up. + * 0b001..ACTIVE : Power up is completed. The IC is in normal functional operation mode. + * 0b010..POWER DOWN : the IC has entered POWER DOWN mode. + * 0b011..DEEP SLEEP: The IC has entered DEEP SLEEP mode. + * 0b110..DEEP POWER DOWN : The IC entred DEEP POWER DOWN mode. + * 0b111..IC Structural TEST Mode : The IC has entered in IC Test mode. + */ +#define PMC_STATUS_FSMMAIN(x) (((uint32_t)(((uint32_t)(x)) << PMC_STATUS_FSMMAIN_SHIFT)) & PMC_STATUS_FSMMAIN_MASK) + +#define PMC_STATUS_FSMPWUP_MASK (0x78U) +#define PMC_STATUS_FSMPWUP_SHIFT (3U) +/*! FSMPWUP - POWER UP Finite State Machine (FSM) status. + */ +#define PMC_STATUS_FSMPWUP(x) (((uint32_t)(((uint32_t)(x)) << PMC_STATUS_FSMPWUP_SHIFT)) & PMC_STATUS_FSMPWUP_MASK) + +#define PMC_STATUS_FSMDSLP_MASK (0x780U) +#define PMC_STATUS_FSMDSLP_SHIFT (7U) +/*! FSMDSLP - DEEP SLEEP Finite State Machine (FSM) status. + */ +#define PMC_STATUS_FSMDSLP(x) (((uint32_t)(((uint32_t)(x)) << PMC_STATUS_FSMDSLP_SHIFT)) & PMC_STATUS_FSMDSLP_MASK) + +#define PMC_STATUS_FSMPWDN_MASK (0x7800U) +#define PMC_STATUS_FSMPWDN_SHIFT (11U) +/*! FSMPWDN - POWER DOWN Finite State Machine (FSM) status. + */ +#define PMC_STATUS_FSMPWDN(x) (((uint32_t)(((uint32_t)(x)) << PMC_STATUS_FSMPWDN_SHIFT)) & PMC_STATUS_FSMPWDN_MASK) + +#define PMC_STATUS_FSMDPWD_MASK (0x38000U) +#define PMC_STATUS_FSMDPWD_SHIFT (15U) +/*! FSMDPWD - DEEP POWER DOWN Finite State Machine (FSM) status. + */ +#define PMC_STATUS_FSMDPWD(x) (((uint32_t)(((uint32_t)(x)) << PMC_STATUS_FSMDPWD_SHIFT)) & PMC_STATUS_FSMDPWD_MASK) + +#define PMC_STATUS_BOOTMODE_MASK (0xC0000U) +#define PMC_STATUS_BOOTMODE_SHIFT (18U) +/*! BOOTMODE - Latest IC Boot cause:. + * 0b00..Latest IC boot was a Full power cycle boot sequence (PoR, Pin Reset, Brown Out Detectors Reset, Software Reset). + * 0b01..Latest IC boot was from DEEP SLEEP low power mode.. + * 0b10..Latest IC boot was from POWER DOWN low power mode.. + * 0b11..Latest IC boot was from DEEP POWER DOWN low power mode.. + */ +#define PMC_STATUS_BOOTMODE(x) (((uint32_t)(((uint32_t)(x)) << PMC_STATUS_BOOTMODE_SHIFT)) & PMC_STATUS_BOOTMODE_MASK) + +#define PMC_STATUS_WAFERTESTDONEVECT_MASK (0xF0000000U) +#define PMC_STATUS_WAFERTESTDONEVECT_SHIFT (28U) +/*! WAFERTESTDONEVECT - Indicates cuurent status of wafer test level. + */ +#define PMC_STATUS_WAFERTESTDONEVECT(x) (((uint32_t)(((uint32_t)(x)) << PMC_STATUS_WAFERTESTDONEVECT_SHIFT)) & PMC_STATUS_WAFERTESTDONEVECT_MASK) +/*! @} */ + +/*! @name RESETCTRL - Reset Control [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */ +/*! @{ */ + +#define PMC_RESETCTRL_DPDWAKEUPRESETENABLE_MASK (0x1U) +#define PMC_RESETCTRL_DPDWAKEUPRESETENABLE_SHIFT (0U) +/*! DPDWAKEUPRESETENABLE - Wake-up from DEEP POWER DOWN reset event (either from wake up I/O or RTC or OS Event Timer). + * 0b0..Reset event from DEEP POWER DOWN mode is disable. + * 0b1..Reset event from DEEP POWER DOWN mode is enable. + */ +#define PMC_RESETCTRL_DPDWAKEUPRESETENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCTRL_DPDWAKEUPRESETENABLE_SHIFT)) & PMC_RESETCTRL_DPDWAKEUPRESETENABLE_MASK) + +#define PMC_RESETCTRL_SWRRESETENABLE_MASK (0x8U) +#define PMC_RESETCTRL_SWRRESETENABLE_SHIFT (3U) +/*! SWRRESETENABLE - Software reset enable. + * 0b0..Software reset is disable. + * 0b1..Software reset is enable. + */ +#define PMC_RESETCTRL_SWRRESETENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCTRL_SWRRESETENABLE_SHIFT)) & PMC_RESETCTRL_SWRRESETENABLE_MASK) + +#define PMC_RESETCTRL_BODVBATRESETENA_SECURE_MASK (0x30U) +#define PMC_RESETCTRL_BODVBATRESETENA_SECURE_SHIFT (4U) +/*! BODVBATRESETENA_SECURE - BOD VBAT reset enable. + * 0b10..BOD VBAT reset is disable. + * 0b01..Any other value than b10, BOD VBAT reset is enable. + */ +#define PMC_RESETCTRL_BODVBATRESETENA_SECURE(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCTRL_BODVBATRESETENA_SECURE_SHIFT)) & PMC_RESETCTRL_BODVBATRESETENA_SECURE_MASK) + +#define PMC_RESETCTRL_BODCORERESETENA_SECURE_MASK (0xC0U) +#define PMC_RESETCTRL_BODCORERESETENA_SECURE_SHIFT (6U) +/*! BODCORERESETENA_SECURE - BOD Core reset enable. + * 0b10..BOD Core reset is disable. + * 0b01..Any other value than b10, BOD Core reset is enable. + */ +#define PMC_RESETCTRL_BODCORERESETENA_SECURE(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCTRL_BODCORERESETENA_SECURE_SHIFT)) & PMC_RESETCTRL_BODCORERESETENA_SECURE_MASK) + +#define PMC_RESETCTRL_BODVBATRESETENA_SECURE_DP_MASK (0x30000000U) +#define PMC_RESETCTRL_BODVBATRESETENA_SECURE_DP_SHIFT (28U) +/*! BODVBATRESETENA_SECURE_DP - BOD VBAT reset enable. + * 0b10..BOD VBAT reset is disable. + * 0b01..Any other value than b10, BOD VBAT reset is enable. + */ +#define PMC_RESETCTRL_BODVBATRESETENA_SECURE_DP(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCTRL_BODVBATRESETENA_SECURE_DP_SHIFT)) & PMC_RESETCTRL_BODVBATRESETENA_SECURE_DP_MASK) + +#define PMC_RESETCTRL_BODCORERESETENA_SECURE_DP_MASK (0xC0000000U) +#define PMC_RESETCTRL_BODCORERESETENA_SECURE_DP_SHIFT (30U) +/*! BODCORERESETENA_SECURE_DP - BOD Core reset enable. + * 0b10..BOD Core reset is disable. + * 0b01..Any other value than b10, BOD Core reset is enable. + */ +#define PMC_RESETCTRL_BODCORERESETENA_SECURE_DP(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCTRL_BODCORERESETENA_SECURE_DP_SHIFT)) & PMC_RESETCTRL_BODCORERESETENA_SECURE_DP_MASK) +/*! @} */ + +/*! @name DCDC0 - DCDC (first) control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */ +/*! @{ */ + +#define PMC_DCDC0_RC_MASK (0x3FU) +#define PMC_DCDC0_RC_SHIFT (0U) +/*! RC - Constant On-Time calibration. + */ +#define PMC_DCDC0_RC(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC0_RC_SHIFT)) & PMC_DCDC0_RC_MASK) + +#define PMC_DCDC0_ICOMP_MASK (0xC0U) +#define PMC_DCDC0_ICOMP_SHIFT (6U) +/*! ICOMP - Select the type of ZCD comparator. + */ +#define PMC_DCDC0_ICOMP(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC0_ICOMP_SHIFT)) & PMC_DCDC0_ICOMP_MASK) + +#define PMC_DCDC0_ISEL_MASK (0x300U) +#define PMC_DCDC0_ISEL_SHIFT (8U) +/*! ISEL - Alter Internal biasing currents. + */ +#define PMC_DCDC0_ISEL(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC0_ISEL_SHIFT)) & PMC_DCDC0_ISEL_MASK) + +#define PMC_DCDC0_ICENABLE_MASK (0x400U) +#define PMC_DCDC0_ICENABLE_SHIFT (10U) +/*! ICENABLE - Selection of auto scaling of COT period with variations in VDD. + */ +#define PMC_DCDC0_ICENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC0_ICENABLE_SHIFT)) & PMC_DCDC0_ICENABLE_MASK) + +#define PMC_DCDC0_TMOS_MASK (0xF800U) +#define PMC_DCDC0_TMOS_SHIFT (11U) +/*! TMOS - One-shot generator reference current trimming signal. + */ +#define PMC_DCDC0_TMOS(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC0_TMOS_SHIFT)) & PMC_DCDC0_TMOS_MASK) + +#define PMC_DCDC0_DISABLEISENSE_MASK (0x10000U) +#define PMC_DCDC0_DISABLEISENSE_SHIFT (16U) +/*! DISABLEISENSE - Disable Current sensing. + */ +#define PMC_DCDC0_DISABLEISENSE(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC0_DISABLEISENSE_SHIFT)) & PMC_DCDC0_DISABLEISENSE_MASK) + +#define PMC_DCDC0_VOUT_MASK (0x1E0000U) +#define PMC_DCDC0_VOUT_SHIFT (17U) +/*! VOUT - Set output regulation voltage. + * 0b0000..0.95 V. + * 0b0001..0.975 V. + * 0b0010..1 V. + * 0b0011..1.025 V. + * 0b0100..1.05 V. + * 0b0101..1.075 V. + * 0b0110..1.1 V. + * 0b0111..1.125 V. + * 0b1000..1.15 V. + * 0b1001..1.175 V. + * 0b1010..1.2 V. + */ +#define PMC_DCDC0_VOUT(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC0_VOUT_SHIFT)) & PMC_DCDC0_VOUT_MASK) + +#define PMC_DCDC0_SLICINGENABLE_MASK (0x200000U) +#define PMC_DCDC0_SLICINGENABLE_SHIFT (21U) +/*! SLICINGENABLE - Enable staggered switching of power switches. + */ +#define PMC_DCDC0_SLICINGENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC0_SLICINGENABLE_SHIFT)) & PMC_DCDC0_SLICINGENABLE_MASK) + +#define PMC_DCDC0_INDUCTORCLAMPENABLE_MASK (0x400000U) +#define PMC_DCDC0_INDUCTORCLAMPENABLE_SHIFT (22U) +/*! INDUCTORCLAMPENABLE - Enable shorting of Inductor during PFM idle time. + */ +#define PMC_DCDC0_INDUCTORCLAMPENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC0_INDUCTORCLAMPENABLE_SHIFT)) & PMC_DCDC0_INDUCTORCLAMPENABLE_MASK) + +#define PMC_DCDC0_VOUT_PWD_MASK (0x7800000U) +#define PMC_DCDC0_VOUT_PWD_SHIFT (23U) +/*! VOUT_PWD - Set output regulation voltage during Deep Sleep. + */ +#define PMC_DCDC0_VOUT_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC0_VOUT_PWD_SHIFT)) & PMC_DCDC0_VOUT_PWD_MASK) +/*! @} */ + +/*! @name DCDC1 - DCDC (second) control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */ +/*! @{ */ + +#define PMC_DCDC1_RTRIMOFFET_MASK (0xFU) +#define PMC_DCDC1_RTRIMOFFET_SHIFT (0U) +/*! RTRIMOFFET - Adjust the offset voltage of BJT based comparator. + */ +#define PMC_DCDC1_RTRIMOFFET(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_RTRIMOFFET_SHIFT)) & PMC_DCDC1_RTRIMOFFET_MASK) + +#define PMC_DCDC1_RSENSETRIM_MASK (0xF0U) +#define PMC_DCDC1_RSENSETRIM_SHIFT (4U) +/*! RSENSETRIM - Adjust Max inductor peak current limiting. + */ +#define PMC_DCDC1_RSENSETRIM(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_RSENSETRIM_SHIFT)) & PMC_DCDC1_RSENSETRIM_MASK) + +#define PMC_DCDC1_DTESTENABLE_MASK (0x100U) +#define PMC_DCDC1_DTESTENABLE_SHIFT (8U) +/*! DTESTENABLE - Enable Digital test signals. + */ +#define PMC_DCDC1_DTESTENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_DTESTENABLE_SHIFT)) & PMC_DCDC1_DTESTENABLE_MASK) + +#define PMC_DCDC1_SETCURVE_MASK (0x600U) +#define PMC_DCDC1_SETCURVE_SHIFT (9U) +/*! SETCURVE - Bandgap calibration parameter. + */ +#define PMC_DCDC1_SETCURVE(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_SETCURVE_SHIFT)) & PMC_DCDC1_SETCURVE_MASK) + +#define PMC_DCDC1_SETDC_MASK (0x7800U) +#define PMC_DCDC1_SETDC_SHIFT (11U) +/*! SETDC - Bandgap calibration parameter. + */ +#define PMC_DCDC1_SETDC(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_SETDC_SHIFT)) & PMC_DCDC1_SETDC_MASK) + +#define PMC_DCDC1_DTESTSEL_MASK (0x38000U) +#define PMC_DCDC1_DTESTSEL_SHIFT (15U) +/*! DTESTSEL - Select the output signal for test. + */ +#define PMC_DCDC1_DTESTSEL(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_DTESTSEL_SHIFT)) & PMC_DCDC1_DTESTSEL_MASK) + +#define PMC_DCDC1_ISCALEENABLE_MASK (0x40000U) +#define PMC_DCDC1_ISCALEENABLE_SHIFT (18U) +/*! ISCALEENABLE - Modify COT behavior. + */ +#define PMC_DCDC1_ISCALEENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_ISCALEENABLE_SHIFT)) & PMC_DCDC1_ISCALEENABLE_MASK) + +#define PMC_DCDC1_FORCEBYPASS_MASK (0x80000U) +#define PMC_DCDC1_FORCEBYPASS_SHIFT (19U) +/*! FORCEBYPASS - Force bypass mode. + */ +#define PMC_DCDC1_FORCEBYPASS(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_FORCEBYPASS_SHIFT)) & PMC_DCDC1_FORCEBYPASS_MASK) + +#define PMC_DCDC1_TRIMAUTOCOT_MASK (0xF00000U) +#define PMC_DCDC1_TRIMAUTOCOT_SHIFT (20U) +/*! TRIMAUTOCOT - Change the scaling ratio of the feedforward compensation. + */ +#define PMC_DCDC1_TRIMAUTOCOT(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_TRIMAUTOCOT_SHIFT)) & PMC_DCDC1_TRIMAUTOCOT_MASK) + +#define PMC_DCDC1_FORCEFULLCYCLE_MASK (0x1000000U) +#define PMC_DCDC1_FORCEFULLCYCLE_SHIFT (24U) +/*! FORCEFULLCYCLE - Force full PFM PMOS and NMOS cycle. + */ +#define PMC_DCDC1_FORCEFULLCYCLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_FORCEFULLCYCLE_SHIFT)) & PMC_DCDC1_FORCEFULLCYCLE_MASK) + +#define PMC_DCDC1_LCENABLE_MASK (0x2000000U) +#define PMC_DCDC1_LCENABLE_SHIFT (25U) +/*! LCENABLE - Change the range of the peak detector of current inside the inductor. + */ +#define PMC_DCDC1_LCENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_LCENABLE_SHIFT)) & PMC_DCDC1_LCENABLE_MASK) + +#define PMC_DCDC1_TOFF_MASK (0x7C000000U) +#define PMC_DCDC1_TOFF_SHIFT (26U) +/*! TOFF - Constant Off-Time calibration input. + */ +#define PMC_DCDC1_TOFF(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_TOFF_SHIFT)) & PMC_DCDC1_TOFF_MASK) + +#define PMC_DCDC1_TOFFENABLE_MASK (0x80000000U) +#define PMC_DCDC1_TOFFENABLE_SHIFT (31U) +/*! TOFFENABLE - Enable Constant Off-Time feature. + */ +#define PMC_DCDC1_TOFFENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_TOFFENABLE_SHIFT)) & PMC_DCDC1_TOFFENABLE_MASK) +/*! @} */ + +/*! @name LDOPMU - Power Management Unit (PMU) and Always-On domains LDO control [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */ +/*! @{ */ + +#define PMC_LDOPMU_VADJ_MASK (0x1FU) +#define PMC_LDOPMU_VADJ_SHIFT (0U) +/*! VADJ - Sets the Always-On domain LDO output level. + * 0b00000..1.22 V. + * 0b00001..0.7 V. + * 0b00010..0.725 V. + * 0b00011..0.75 V. + * 0b00100..0.775 V. + * 0b00101..0.8 V. + * 0b00110..0.825 V. + * 0b00111..0.85 V. + * 0b01000..0.875 V. + * 0b01001..0.9 V. + * 0b01010..0.96 V. + * 0b01011..0.97 V. + * 0b01100..0.98 V. + * 0b01101..0.99 V. + * 0b01110..1 V. + * 0b01111..1.01 V. + * 0b10000..1.02 V. + * 0b10001..1.03 V. + * 0b10010..1.04 V. + * 0b10011..1.05 V. + * 0b10100..1.06 V. + * 0b10101..1.07 V. + * 0b10110..1.08 V. + * 0b10111..1.09 V. + * 0b11000..1.1 V. + * 0b11001..1.11 V. + * 0b11010..1.12 V. + * 0b11011..1.13 V. + * 0b11100..1.14 V. + * 0b11101..1.15 V. + * 0b11110..1.16 V. + * 0b11111..1.22 V. + */ +#define PMC_LDOPMU_VADJ(x) (((uint32_t)(((uint32_t)(x)) << PMC_LDOPMU_VADJ_SHIFT)) & PMC_LDOPMU_VADJ_MASK) + +#define PMC_LDOPMU_VADJ_PWD_MASK (0x3E0U) +#define PMC_LDOPMU_VADJ_PWD_SHIFT (5U) +/*! VADJ_PWD - Sets the Always-On domain LDO output level in all power down modes. + */ +#define PMC_LDOPMU_VADJ_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMC_LDOPMU_VADJ_PWD_SHIFT)) & PMC_LDOPMU_VADJ_PWD_MASK) + +#define PMC_LDOPMU_VADJ_BOOST_MASK (0x7C00U) +#define PMC_LDOPMU_VADJ_BOOST_SHIFT (10U) +/*! VADJ_BOOST - Sets the Always-On domain LDO Boost output level. + */ +#define PMC_LDOPMU_VADJ_BOOST(x) (((uint32_t)(((uint32_t)(x)) << PMC_LDOPMU_VADJ_BOOST_SHIFT)) & PMC_LDOPMU_VADJ_BOOST_MASK) + +#define PMC_LDOPMU_VADJ_BOOST_PWD_MASK (0xF8000U) +#define PMC_LDOPMU_VADJ_BOOST_PWD_SHIFT (15U) +/*! VADJ_BOOST_PWD - Sets the Always-On domain LDO Boost output level in all power down modes. + */ +#define PMC_LDOPMU_VADJ_BOOST_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMC_LDOPMU_VADJ_BOOST_PWD_SHIFT)) & PMC_LDOPMU_VADJ_BOOST_PWD_MASK) + +#define PMC_LDOPMU_BLEED_MASK (0x100000U) +#define PMC_LDOPMU_BLEED_SHIFT (20U) +/*! BLEED - Controls LDOMEM bleed current. + * 0b0..Bleed current is disable. + * 0b1..Bleed current is enable. + */ +#define PMC_LDOPMU_BLEED(x) (((uint32_t)(((uint32_t)(x)) << PMC_LDOPMU_BLEED_SHIFT)) & PMC_LDOPMU_BLEED_MASK) + +#define PMC_LDOPMU_BOOST_ENA_MASK (0x1000000U) +#define PMC_LDOPMU_BOOST_ENA_SHIFT (24U) +/*! BOOST_ENA - Control the LDO AO boost mode in ACTIVE mode. + * 0b0..LDO AO Boost Mode is disable. + * 0b1..LDO AO Boost Mode is enable. + */ +#define PMC_LDOPMU_BOOST_ENA(x) (((uint32_t)(((uint32_t)(x)) << PMC_LDOPMU_BOOST_ENA_SHIFT)) & PMC_LDOPMU_BOOST_ENA_MASK) + +#define PMC_LDOPMU_BOOST_ENA_PWD_MASK (0x2000000U) +#define PMC_LDOPMU_BOOST_ENA_PWD_SHIFT (25U) +/*! BOOST_ENA_PWD - Control the LDO AO boost mode in the different low power modes (DEEP SLEEP, POWERDOWN, and DEEP POWER DOWN). + * 0b0..LDO AO Boost Mode is disable. + * 0b1..LDO AO Boost Mode is enable. + */ +#define PMC_LDOPMU_BOOST_ENA_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMC_LDOPMU_BOOST_ENA_PWD_SHIFT)) & PMC_LDOPMU_BOOST_ENA_PWD_MASK) +/*! @} */ + +/*! @name BODVBAT - VBAT Brown Out Dectector (BoD) control register [Reset by: PoR, Pin Reset, Software Reset] */ +/*! @{ */ + +#define PMC_BODVBAT_TRIGLVL_MASK (0x1FU) +#define PMC_BODVBAT_TRIGLVL_SHIFT (0U) +/*! TRIGLVL - BoD trigger level. + * 0b00000..1.00 V. + * 0b00001..1.10 V. + * 0b00010..1.20 V. + * 0b00011..1.30 V. + * 0b00100..1.40 V. + * 0b00101..1.50 V. + * 0b00110..1.60 V. + * 0b00111..1.65 V. + * 0b01000..1.70 V. + * 0b01001..1.75 V. + * 0b01010..1.80 V. + * 0b01011..1.90 V. + * 0b01100..2.00 V. + * 0b01101..2.10 V. + * 0b01110..2.20 V. + * 0b01111..2.30 V. + * 0b10000..2.40 V. + * 0b10001..2.50 V. + * 0b10010..2.60 V. + * 0b10011..2.70 V. + * 0b10100..2.806 V. + * 0b10101..2.90 V. + * 0b10110..3.00 V. + * 0b10111..3.10 V. + * 0b11000..3.20 V. + * 0b11001..3.30 V. + * 0b11010..3.30 V. + * 0b11011..3.30 V. + * 0b11100..3.30 V. + * 0b11101..3.30 V. + * 0b11110..3.30 V. + * 0b11111..3.30 V. + */ +#define PMC_BODVBAT_TRIGLVL(x) (((uint32_t)(((uint32_t)(x)) << PMC_BODVBAT_TRIGLVL_SHIFT)) & PMC_BODVBAT_TRIGLVL_MASK) + +#define PMC_BODVBAT_HYST_MASK (0x60U) +#define PMC_BODVBAT_HYST_SHIFT (5U) +/*! HYST - BoD Hysteresis control. + * 0b00..25 mV. + * 0b01..50 mV. + * 0b10..75 mV. + * 0b11..100 mV. + */ +#define PMC_BODVBAT_HYST(x) (((uint32_t)(((uint32_t)(x)) << PMC_BODVBAT_HYST_SHIFT)) & PMC_BODVBAT_HYST_MASK) +/*! @} */ + +/*! @name REFFASTWKUP - Analog References fast wake-up Control register [Reset by: PoR] */ +/*! @{ */ + +#define PMC_REFFASTWKUP_LPWKUP_MASK (0x1U) +#define PMC_REFFASTWKUP_LPWKUP_SHIFT (0U) +/*! LPWKUP - Analog References fast wake-up in case of wake-up from a low power mode (DEEP SLEEP, POWER DOWN and DEEP POWER DOWN): . + * 0b0..Analog References fast wake-up feature is disabled in case of wake-up from any Low power mode. + * 0b1..Analog References fast wake-up feature is enabled in case of wake-up from any Low power mode. + */ +#define PMC_REFFASTWKUP_LPWKUP(x) (((uint32_t)(((uint32_t)(x)) << PMC_REFFASTWKUP_LPWKUP_SHIFT)) & PMC_REFFASTWKUP_LPWKUP_MASK) + +#define PMC_REFFASTWKUP_HWWKUP_MASK (0x2U) +#define PMC_REFFASTWKUP_HWWKUP_SHIFT (1U) +/*! HWWKUP - Analog References fast wake-up in case of Hardware Pin reset: . + * 0b0..Analog References fast wake-up feature is disabled in case of Hardware Pin reset. + * 0b1..Analog References fast wake-up feature is enabled in case of Hardware Pin reset. + */ +#define PMC_REFFASTWKUP_HWWKUP(x) (((uint32_t)(((uint32_t)(x)) << PMC_REFFASTWKUP_HWWKUP_SHIFT)) & PMC_REFFASTWKUP_HWWKUP_MASK) +/*! @} */ + +/*! @name XTAL32K - 32 KHz Crystal oscillator (XTAL) control register [Reset by: PoR, Brown Out Detectors Reset] */ +/*! @{ */ + +#define PMC_XTAL32K_IREF_MASK (0x6U) +#define PMC_XTAL32K_IREF_SHIFT (1U) +/*! IREF - reference output current selection inputs. + */ +#define PMC_XTAL32K_IREF(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_IREF_SHIFT)) & PMC_XTAL32K_IREF_MASK) + +#define PMC_XTAL32K_TEST_MASK (0x8U) +#define PMC_XTAL32K_TEST_SHIFT (3U) +/*! TEST - Oscillator Test Mode. + */ +#define PMC_XTAL32K_TEST(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_TEST_SHIFT)) & PMC_XTAL32K_TEST_MASK) + +#define PMC_XTAL32K_IBIAS_MASK (0x30U) +#define PMC_XTAL32K_IBIAS_SHIFT (4U) +/*! IBIAS - bias current selection inputs. + */ +#define PMC_XTAL32K_IBIAS(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_IBIAS_SHIFT)) & PMC_XTAL32K_IBIAS_MASK) + +#define PMC_XTAL32K_AMPL_MASK (0xC0U) +#define PMC_XTAL32K_AMPL_SHIFT (6U) +/*! AMPL - oscillator amplitude selection inputs. + */ +#define PMC_XTAL32K_AMPL(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_AMPL_SHIFT)) & PMC_XTAL32K_AMPL_MASK) + +#define PMC_XTAL32K_CAPBANKIN_MASK (0x7F00U) +#define PMC_XTAL32K_CAPBANKIN_SHIFT (8U) +/*! CAPBANKIN - Capa bank setting input. + */ +#define PMC_XTAL32K_CAPBANKIN(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_CAPBANKIN_SHIFT)) & PMC_XTAL32K_CAPBANKIN_MASK) + +#define PMC_XTAL32K_CAPBANKOUT_MASK (0x3F8000U) +#define PMC_XTAL32K_CAPBANKOUT_SHIFT (15U) +/*! CAPBANKOUT - Capa bank setting output. + */ +#define PMC_XTAL32K_CAPBANKOUT(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_CAPBANKOUT_SHIFT)) & PMC_XTAL32K_CAPBANKOUT_MASK) + +#define PMC_XTAL32K_CAPTESTSTARTSRCSEL_MASK (0x400000U) +#define PMC_XTAL32K_CAPTESTSTARTSRCSEL_SHIFT (22U) +/*! CAPTESTSTARTSRCSEL - Source selection for xo32k_captest_start_ao_set. + * 0b0..Sourced from CAPTESTSTART. + * 0b1..Sourced from calibration. + */ +#define PMC_XTAL32K_CAPTESTSTARTSRCSEL(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_CAPTESTSTARTSRCSEL_SHIFT)) & PMC_XTAL32K_CAPTESTSTARTSRCSEL_MASK) + +#define PMC_XTAL32K_CAPTESTSTART_MASK (0x800000U) +#define PMC_XTAL32K_CAPTESTSTART_SHIFT (23U) +/*! CAPTESTSTART - Start test. + */ +#define PMC_XTAL32K_CAPTESTSTART(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_CAPTESTSTART_SHIFT)) & PMC_XTAL32K_CAPTESTSTART_MASK) + +#define PMC_XTAL32K_CAPTESTENABLE_MASK (0x1000000U) +#define PMC_XTAL32K_CAPTESTENABLE_SHIFT (24U) +/*! CAPTESTENABLE - Enable signal for cap test. + */ +#define PMC_XTAL32K_CAPTESTENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_CAPTESTENABLE_SHIFT)) & PMC_XTAL32K_CAPTESTENABLE_MASK) + +#define PMC_XTAL32K_CAPTESTOSCINSEL_MASK (0x2000000U) +#define PMC_XTAL32K_CAPTESTOSCINSEL_SHIFT (25U) +/*! CAPTESTOSCINSEL - Select the input for test. + * 0b0..Oscillator output pin (osc_out). + * 0b1..Oscillator input pin (osc_in). + */ +#define PMC_XTAL32K_CAPTESTOSCINSEL(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_CAPTESTOSCINSEL_SHIFT)) & PMC_XTAL32K_CAPTESTOSCINSEL_MASK) +/*! @} */ + +/*! @name COMP - Analog Comparator control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */ +/*! @{ */ + +#define PMC_COMP_HYST_MASK (0x2U) +#define PMC_COMP_HYST_SHIFT (1U) +/*! HYST - Hysteris when hyst = '1'. + * 0b0..Hysteresis is disable. + * 0b1..Hysteresis is enable. + */ +#define PMC_COMP_HYST(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_HYST_SHIFT)) & PMC_COMP_HYST_MASK) + +#define PMC_COMP_VREFINPUT_MASK (0x4U) +#define PMC_COMP_VREFINPUT_SHIFT (2U) +/*! VREFINPUT - Dedicated control bit to select between internal VREF and VDDA (for the resistive ladder). + * 0b0..Select internal VREF. + * 0b1..Select VDDA. + */ +#define PMC_COMP_VREFINPUT(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_VREFINPUT_SHIFT)) & PMC_COMP_VREFINPUT_MASK) + +#define PMC_COMP_LOWPOWER_MASK (0x8U) +#define PMC_COMP_LOWPOWER_SHIFT (3U) +/*! LOWPOWER - Low power mode. + * 0b0..High speed mode. + * 0b1..Low power mode (Low speed). + */ +#define PMC_COMP_LOWPOWER(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_LOWPOWER_SHIFT)) & PMC_COMP_LOWPOWER_MASK) + +#define PMC_COMP_PMUX_MASK (0x70U) +#define PMC_COMP_PMUX_SHIFT (4U) +/*! PMUX - Control word for P multiplexer:. + * 0b000..VREF (See fiedl VREFINPUT). + * 0b001..Pin P0_0. + * 0b010..Pin P0_9. + * 0b011..Pin P0_18. + * 0b100..Pin P1_14. + * 0b101..Pin P2_23. + */ +#define PMC_COMP_PMUX(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_PMUX_SHIFT)) & PMC_COMP_PMUX_MASK) + +#define PMC_COMP_NMUX_MASK (0x380U) +#define PMC_COMP_NMUX_SHIFT (7U) +/*! NMUX - Control word for N multiplexer:. + * 0b000..VREF (See field VREFINPUT). + * 0b001..Pin P0_0. + * 0b010..Pin P0_9. + * 0b011..Pin P0_18. + * 0b100..Pin P1_14. + * 0b101..Pin P2_23. + */ +#define PMC_COMP_NMUX(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_NMUX_SHIFT)) & PMC_COMP_NMUX_MASK) + +#define PMC_COMP_VREF_MASK (0x7C00U) +#define PMC_COMP_VREF_SHIFT (10U) +/*! VREF - Control reference voltage step, per steps of (VREFINPUT/31). + */ +#define PMC_COMP_VREF(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_VREF_SHIFT)) & PMC_COMP_VREF_MASK) + +#define PMC_COMP_FILTERCGF_SAMPLEMODE_MASK (0x30000U) +#define PMC_COMP_FILTERCGF_SAMPLEMODE_SHIFT (16U) +/*! FILTERCGF_SAMPLEMODE - Control the filtering of the Analog Comparator output. + * 0b00..Bypass mode. + * 0b01..Filter 1 clock period. + * 0b10..Filter 2 clock period. + * 0b11..Filter 3 clock period. + */ +#define PMC_COMP_FILTERCGF_SAMPLEMODE(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_FILTERCGF_SAMPLEMODE_SHIFT)) & PMC_COMP_FILTERCGF_SAMPLEMODE_MASK) + +#define PMC_COMP_FILTERCGF_CLKDIV_MASK (0x1C0000U) +#define PMC_COMP_FILTERCGF_CLKDIV_SHIFT (18U) +/*! FILTERCGF_CLKDIV - Filter Clock divider. + * 0b000..Filter clock period duration equals 1 Analog Comparator clock period. + * 0b001..Filter clock period duration equals 2 Analog Comparator clock period. + * 0b010..Filter clock period duration equals 4 Analog Comparator clock period. + * 0b011..Filter clock period duration equals 8 Analog Comparator clock period. + * 0b100..Filter clock period duration equals 16 Analog Comparator clock period. + * 0b101..Filter clock period duration equals 32 Analog Comparator clock period. + * 0b110..Filter clock period duration equals 64 Analog Comparator clock period. + * 0b111..Filter clock period duration equals 128 Analog Comparator clock period. + */ +#define PMC_COMP_FILTERCGF_CLKDIV(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_FILTERCGF_CLKDIV_SHIFT)) & PMC_COMP_FILTERCGF_CLKDIV_MASK) +/*! @} */ + +/*! @name WAKEUPIOCTRL - Deep Power Down wake-up source [Reset by: PoR, Pin Reset, Software Reset] */ +/*! @{ */ + +#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP0_MASK (0x1U) +#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP0_SHIFT (0U) +/*! RISINGEDGEWAKEUP0 - Enable / disable detection of rising edge events on Wake Up 0 pin in Deep Power Down modes:. + * 0b0..Rising edge detection is disable. + * 0b1..Rising edge detection is enable. + */ +#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP0(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP0_SHIFT)) & PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP0_MASK) + +#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP0_MASK (0x2U) +#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP0_SHIFT (1U) +/*! FALLINGEDGEWAKEUP0 - Enable / disable detection of falling edge events on Wake Up 0 pin in Deep Power Down modes:. + * 0b0..Falling edge detection is disable. + * 0b1..Falling edge detection is enable. + */ +#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP0(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP0_SHIFT)) & PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP0_MASK) + +#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP1_MASK (0x4U) +#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP1_SHIFT (2U) +/*! RISINGEDGEWAKEUP1 - Enable / disable detection of rising edge events on Wake Up 1 pin in Deep Power Down modes:. + * 0b0..Rising edge detection is disable. + * 0b1..Rising edge detection is enable. + */ +#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP1(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP1_SHIFT)) & PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP1_MASK) + +#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP1_MASK (0x8U) +#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP1_SHIFT (3U) +/*! FALLINGEDGEWAKEUP1 - Enable / disable detection of falling edge events on Wake Up 1 pin in Deep Power Down modes:. + * 0b0..Falling edge detection is disable. + * 0b1..Falling edge detection is enable. + */ +#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP1(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP1_SHIFT)) & PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP1_MASK) + +#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP2_MASK (0x10U) +#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP2_SHIFT (4U) +/*! RISINGEDGEWAKEUP2 - Enable / disable detection of rising edge events on Wake Up 2 pin in Deep Power Down modes:. + * 0b0..Rising edge detection is disable. + * 0b1..Rising edge detection is enable. + */ +#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP2(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP2_SHIFT)) & PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP2_MASK) + +#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP2_MASK (0x20U) +#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP2_SHIFT (5U) +/*! FALLINGEDGEWAKEUP2 - Enable / disable detection of falling edge events on Wake Up 2 pin in Deep Power Down modes:. + * 0b0..Falling edge detection is disable. + * 0b1..Falling edge detection is enable. + */ +#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP2(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP2_SHIFT)) & PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP2_MASK) + +#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP3_MASK (0x40U) +#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP3_SHIFT (6U) +/*! RISINGEDGEWAKEUP3 - Enable / disable detection of rising edge events on Wake Up 3 pin in Deep Power Down modes:. + * 0b0..Rising edge detection is disable. + * 0b1..Rising edge detection is enable. + */ +#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP3(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP3_SHIFT)) & PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP3_MASK) + +#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP3_MASK (0x80U) +#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP3_SHIFT (7U) +/*! FALLINGEDGEWAKEUP3 - Enable / disable detection of falling edge events on Wake Up 3 pin in Deep Power Down modes:. + * 0b0..Falling edge detection is disable. + * 0b1..Falling edge detection is enable. + */ +#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP3(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP3_SHIFT)) & PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP3_MASK) + +#define PMC_WAKEUPIOCTRL_MODEWAKEUPIOPAD0_MASK (0x3000U) +#define PMC_WAKEUPIOCTRL_MODEWAKEUPIOPAD0_SHIFT (12U) +/*! MODEWAKEUPIOPAD0 - Selects function mode (on-chip pull-up/pull-down resistor control). + * 0b00..Inactive. Inactive (no pull-down/pull-up resistor enabled). + * 0b01..Pull-down. Pull-down resistor enabled. + * 0b10..Pull-up. Pull-up resistor enabled. + * 0b11..Repeater. Repeater mode. + */ +#define PMC_WAKEUPIOCTRL_MODEWAKEUPIOPAD0(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_MODEWAKEUPIOPAD0_SHIFT)) & PMC_WAKEUPIOCTRL_MODEWAKEUPIOPAD0_MASK) + +#define PMC_WAKEUPIOCTRL_MODEWAKEUPIOPAD1_MASK (0xC000U) +#define PMC_WAKEUPIOCTRL_MODEWAKEUPIOPAD1_SHIFT (14U) +/*! MODEWAKEUPIOPAD1 - Selects function mode (on-chip pull-up/pull-down resistor control). + * 0b00..Inactive. Inactive (no pull-down/pull-up resistor enabled). + * 0b01..Pull-down. Pull-down resistor enabled. + * 0b10..Pull-up. Pull-up resistor enabled. + * 0b11..Repeater. Repeater mode. + */ +#define PMC_WAKEUPIOCTRL_MODEWAKEUPIOPAD1(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_MODEWAKEUPIOPAD1_SHIFT)) & PMC_WAKEUPIOCTRL_MODEWAKEUPIOPAD1_MASK) + +#define PMC_WAKEUPIOCTRL_MODEWAKEUPIOPAD2_MASK (0x30000U) +#define PMC_WAKEUPIOCTRL_MODEWAKEUPIOPAD2_SHIFT (16U) +/*! MODEWAKEUPIOPAD2 - Selects function mode (on-chip pull-up/pull-down resistor control). + * 0b00..Inactive. Inactive (no pull-down/pull-up resistor enabled). + * 0b01..Pull-down. Pull-down resistor enabled. + * 0b10..Pull-up. Pull-up resistor enabled. + * 0b11..Repeater. Repeater mode. + */ +#define PMC_WAKEUPIOCTRL_MODEWAKEUPIOPAD2(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_MODEWAKEUPIOPAD2_SHIFT)) & PMC_WAKEUPIOCTRL_MODEWAKEUPIOPAD2_MASK) + +#define PMC_WAKEUPIOCTRL_MODEWAKEUPIOPAD3_MASK (0xC0000U) +#define PMC_WAKEUPIOCTRL_MODEWAKEUPIOPAD3_SHIFT (18U) +/*! MODEWAKEUPIOPAD3 - Selects function mode (on-chip pull-up/pull-down resistor control). + * 0b00..Inactive. Inactive (no pull-down/pull-up resistor enabled). + * 0b01..Pull-down. Pull-down resistor enabled. + * 0b10..Pull-up. Pull-up resistor enabled. + * 0b11..Repeater. Repeater mode. + */ +#define PMC_WAKEUPIOCTRL_MODEWAKEUPIOPAD3(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_MODEWAKEUPIOPAD3_SHIFT)) & PMC_WAKEUPIOCTRL_MODEWAKEUPIOPAD3_MASK) + +#define PMC_WAKEUPIOCTRL_WAKEUPIO_ENABLE_CTRL_MASK (0x100000U) +#define PMC_WAKEUPIOCTRL_WAKEUPIO_ENABLE_CTRL_SHIFT (20U) +/*! WAKEUPIO_ENABLE_CTRL - Enable WAKEUP IO PAD control from MODEWAKEUPIOPAD (bits 12 to 19). + * 0b0..WAKEUP IO PAD mode control comes from IOCON. + * 0b1..WAKEUP IO PAD mode control comes from MODEWAKEUPIOPAD (bits 12 to 19). + */ +#define PMC_WAKEUPIOCTRL_WAKEUPIO_ENABLE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_WAKEUPIO_ENABLE_CTRL_SHIFT)) & PMC_WAKEUPIOCTRL_WAKEUPIO_ENABLE_CTRL_MASK) + +#define PMC_WAKEUPIOCTRL_WAKEUPIO_RSTN_MASK (0x200000U) +#define PMC_WAKEUPIOCTRL_WAKEUPIO_RSTN_SHIFT (21U) +/*! WAKEUPIO_RSTN - WAKEUP IO event detector reset control. + * 0b0..Bloc is reset. + * 0b1..Bloc is not reset. + */ +#define PMC_WAKEUPIOCTRL_WAKEUPIO_RSTN(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_WAKEUPIO_RSTN_SHIFT)) & PMC_WAKEUPIOCTRL_WAKEUPIO_RSTN_MASK) +/*! @} */ + +/*! @name WAKEIOCAUSE - Allows to identify the Wake-up I/O source from Deep Power Down mode */ +/*! @{ */ + +#define PMC_WAKEIOCAUSE_WAKEUP0_MASK (0x1U) +#define PMC_WAKEIOCAUSE_WAKEUP0_SHIFT (0U) +/*! WAKEUP0 - Allows to identify Wake up I/O 0 as the wake-up source from Deep Power Down mode. + * 0b0..Last wake up from Deep Power down mode was NOT triggred by wake up I/O 0. + * 0b1..Last wake up from Deep Power down mode was triggred by wake up I/O 0. + */ +#define PMC_WAKEIOCAUSE_WAKEUP0(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEIOCAUSE_WAKEUP0_SHIFT)) & PMC_WAKEIOCAUSE_WAKEUP0_MASK) + +#define PMC_WAKEIOCAUSE_WAKEUP1_MASK (0x2U) +#define PMC_WAKEIOCAUSE_WAKEUP1_SHIFT (1U) +/*! WAKEUP1 - Allows to identify Wake up I/O 1 as the wake-up source from Deep Power Down mode. + * 0b0..Last wake up from Deep Power down mode was NOT triggred by wake up I/O 1. + * 0b1..Last wake up from Deep Power down mode was triggred by wake up I/O 1. + */ +#define PMC_WAKEIOCAUSE_WAKEUP1(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEIOCAUSE_WAKEUP1_SHIFT)) & PMC_WAKEIOCAUSE_WAKEUP1_MASK) + +#define PMC_WAKEIOCAUSE_WAKEUP2_MASK (0x4U) +#define PMC_WAKEIOCAUSE_WAKEUP2_SHIFT (2U) +/*! WAKEUP2 - Allows to identify Wake up I/O 2 as the wake-up source from Deep Power Down mode. + * 0b0..Last wake up from Deep Power down mode was NOT triggred by wake up I/O 2. + * 0b1..Last wake up from Deep Power down mode was triggred by wake up I/O 2. + */ +#define PMC_WAKEIOCAUSE_WAKEUP2(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEIOCAUSE_WAKEUP2_SHIFT)) & PMC_WAKEIOCAUSE_WAKEUP2_MASK) + +#define PMC_WAKEIOCAUSE_WAKEUP3_MASK (0x8U) +#define PMC_WAKEIOCAUSE_WAKEUP3_SHIFT (3U) +/*! WAKEUP3 - Allows to identify Wake up I/O 3 as the wake-up source from Deep Power Down mode. + * 0b0..Last wake up from Deep Power down mode was NOT triggred by wake up I/O 3. + * 0b1..Last wake up from Deep Power down mode was triggred by wake up I/O 3. + */ +#define PMC_WAKEIOCAUSE_WAKEUP3(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEIOCAUSE_WAKEUP3_SHIFT)) & PMC_WAKEIOCAUSE_WAKEUP3_MASK) +/*! @} */ + +/*! @name STATUSCLK - FRO and XTAL status register [Reset by: PoR, Brown Out Detectors Reset] */ +/*! @{ */ + +#define PMC_STATUSCLK_XTAL32KOK_MASK (0x1U) +#define PMC_STATUSCLK_XTAL32KOK_SHIFT (0U) +/*! XTAL32KOK - XTAL oscillator 32 K OK signal. + */ +#define PMC_STATUSCLK_XTAL32KOK(x) (((uint32_t)(((uint32_t)(x)) << PMC_STATUSCLK_XTAL32KOK_SHIFT)) & PMC_STATUSCLK_XTAL32KOK_MASK) + +#define PMC_STATUSCLK_XTAL32KOSCFAILURE_MASK (0x4U) +#define PMC_STATUSCLK_XTAL32KOSCFAILURE_SHIFT (2U) +/*! XTAL32KOSCFAILURE - XTAL32 KHZ oscillator oscillation failure detection indicator. + * 0b0..No oscillation failure has been detetced since the last time this bit has been cleared. + * 0b1..At least one oscillation failure has been detetced since the last time this bit has been cleared. + */ +#define PMC_STATUSCLK_XTAL32KOSCFAILURE(x) (((uint32_t)(((uint32_t)(x)) << PMC_STATUSCLK_XTAL32KOSCFAILURE_SHIFT)) & PMC_STATUSCLK_XTAL32KOSCFAILURE_MASK) +/*! @} */ + +/*! @name AOREG1 - General purpose always on domain data storage [Reset by: PoR, Brown Out Detectors Reset] */ +/*! @{ */ + +#define PMC_AOREG1_POR_MASK (0x10U) +#define PMC_AOREG1_POR_SHIFT (4U) +/*! POR - The last chip reset was caused by a Power On Reset. + */ +#define PMC_AOREG1_POR(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_POR_SHIFT)) & PMC_AOREG1_POR_MASK) + +#define PMC_AOREG1_PADRESET_MASK (0x20U) +#define PMC_AOREG1_PADRESET_SHIFT (5U) +/*! PADRESET - The last chip reset was caused by a Pin Reset. + */ +#define PMC_AOREG1_PADRESET(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_PADRESET_SHIFT)) & PMC_AOREG1_PADRESET_MASK) + +#define PMC_AOREG1_BODRESET_MASK (0x40U) +#define PMC_AOREG1_BODRESET_SHIFT (6U) +/*! BODRESET - The last chip reset was caused by a Brown Out Detector (BoD), either VBAT BoD or Core Logic BoD. + */ +#define PMC_AOREG1_BODRESET(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_BODRESET_SHIFT)) & PMC_AOREG1_BODRESET_MASK) + +#define PMC_AOREG1_SYSTEMRESET_MASK (0x80U) +#define PMC_AOREG1_SYSTEMRESET_SHIFT (7U) +/*! SYSTEMRESET - The last chip reset was caused by a System Reset requested by the ARM CPU. + */ +#define PMC_AOREG1_SYSTEMRESET(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_SYSTEMRESET_SHIFT)) & PMC_AOREG1_SYSTEMRESET_MASK) + +#define PMC_AOREG1_WDTRESET_MASK (0x100U) +#define PMC_AOREG1_WDTRESET_SHIFT (8U) +/*! WDTRESET - The last chip reset was caused by the Watchdog Timer. + */ +#define PMC_AOREG1_WDTRESET(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_WDTRESET_SHIFT)) & PMC_AOREG1_WDTRESET_MASK) + +#define PMC_AOREG1_SWRRESET_MASK (0x200U) +#define PMC_AOREG1_SWRRESET_SHIFT (9U) +/*! SWRRESET - The last chip reset was caused by a Software event. + */ +#define PMC_AOREG1_SWRRESET(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_SWRRESET_SHIFT)) & PMC_AOREG1_SWRRESET_MASK) + +#define PMC_AOREG1_DPDRESET_WAKEUPIO_MASK (0x400U) +#define PMC_AOREG1_DPDRESET_WAKEUPIO_SHIFT (10U) +/*! DPDRESET_WAKEUPIO - The last chip reset was caused by a Wake-up I/O reset event during a Deep Power-Down mode. + */ +#define PMC_AOREG1_DPDRESET_WAKEUPIO(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_DPDRESET_WAKEUPIO_SHIFT)) & PMC_AOREG1_DPDRESET_WAKEUPIO_MASK) + +#define PMC_AOREG1_DPDRESET_RTC_MASK (0x800U) +#define PMC_AOREG1_DPDRESET_RTC_SHIFT (11U) +/*! DPDRESET_RTC - The last chip reset was caused by an RTC (either RTC Alarm or RTC wake up) reset event during a Deep Power-Down mode. + */ +#define PMC_AOREG1_DPDRESET_RTC(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_DPDRESET_RTC_SHIFT)) & PMC_AOREG1_DPDRESET_RTC_MASK) + +#define PMC_AOREG1_DPDRESET_OSTIMER_MASK (0x1000U) +#define PMC_AOREG1_DPDRESET_OSTIMER_SHIFT (12U) +/*! DPDRESET_OSTIMER - The last chip reset was caused by an OS Event Timer reset event during a Deep Power-Down mode. + */ +#define PMC_AOREG1_DPDRESET_OSTIMER(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_DPDRESET_OSTIMER_SHIFT)) & PMC_AOREG1_DPDRESET_OSTIMER_MASK) + +#define PMC_AOREG1_CDOGRESET_MASK (0x2000U) +#define PMC_AOREG1_CDOGRESET_SHIFT (13U) +/*! CDOGRESET - The last chip reset was caused by the code Watchdog. + */ +#define PMC_AOREG1_CDOGRESET(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_CDOGRESET_SHIFT)) & PMC_AOREG1_CDOGRESET_MASK) + +#define PMC_AOREG1_BOOTERRORCOUNTER_MASK (0xF0000U) +#define PMC_AOREG1_BOOTERRORCOUNTER_SHIFT (16U) +/*! BOOTERRORCOUNTER - ROM Boot Fatal Error Counter. + */ +#define PMC_AOREG1_BOOTERRORCOUNTER(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_BOOTERRORCOUNTER_SHIFT)) & PMC_AOREG1_BOOTERRORCOUNTER_MASK) +/*! @} */ + +/*! @name MISCCTRL - Dummy Control bus to PMU [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */ +/*! @{ */ + +#define PMC_MISCCTRL_LDODEEPSLEEPREF_MASK (0x1U) +#define PMC_MISCCTRL_LDODEEPSLEEPREF_SHIFT (0U) +/*! LDODEEPSLEEPREF - Select LDO Deep Sleep reference source. + * 0b0..LDO DEEP Sleep uses Flash buffer biasing as reference. + * 0b1..LDO DEEP Sleep uses Band Gap 0.8V as reference. + */ +#define PMC_MISCCTRL_LDODEEPSLEEPREF(x) (((uint32_t)(((uint32_t)(x)) << PMC_MISCCTRL_LDODEEPSLEEPREF_SHIFT)) & PMC_MISCCTRL_LDODEEPSLEEPREF_MASK) + +#define PMC_MISCCTRL_LDOMEMHIGHZMODE_MASK (0x2U) +#define PMC_MISCCTRL_LDOMEMHIGHZMODE_SHIFT (1U) +/*! LDOMEMHIGHZMODE - Control the activation of LDO MEM High Z mode. + * 0b0..LDO MEM High Z mode is disabled. + * 0b1..LDO MEM High Z mode is enabled. + */ +#define PMC_MISCCTRL_LDOMEMHIGHZMODE(x) (((uint32_t)(((uint32_t)(x)) << PMC_MISCCTRL_LDOMEMHIGHZMODE_SHIFT)) & PMC_MISCCTRL_LDOMEMHIGHZMODE_MASK) + +#define PMC_MISCCTRL_LOWPWR_FLASH_BUF_MASK (0x4U) +#define PMC_MISCCTRL_LOWPWR_FLASH_BUF_SHIFT (2U) +#define PMC_MISCCTRL_LOWPWR_FLASH_BUF(x) (((uint32_t)(((uint32_t)(x)) << PMC_MISCCTRL_LOWPWR_FLASH_BUF_SHIFT)) & PMC_MISCCTRL_LOWPWR_FLASH_BUF_MASK) + +#define PMC_MISCCTRL_MISCCTRL_3_11_MASK (0xFF8U) +#define PMC_MISCCTRL_MISCCTRL_3_11_SHIFT (3U) +/*! MISCCTRL_3_11 - Reserved. + */ +#define PMC_MISCCTRL_MISCCTRL_3_11(x) (((uint32_t)(((uint32_t)(x)) << PMC_MISCCTRL_MISCCTRL_3_11_SHIFT)) & PMC_MISCCTRL_MISCCTRL_3_11_MASK) + +#define PMC_MISCCTRL_DISABLE_BLEED_MASK (0x1000U) +#define PMC_MISCCTRL_DISABLE_BLEED_SHIFT (12U) +/*! DISABLE_BLEED - Controls LDO MEM bleed current. This field is expected to be controlled by the + * Low Power Software only in DEEP SLEEP low power mode. + * 0b0..LDO_MEM bleed current is enabled. + * 0b1..LDO_MEM bleed current is disabled. Should be set before entering in Deep Sleep low power mode and cleared + * after wake up from Deep SLeep low power mode. + */ +#define PMC_MISCCTRL_DISABLE_BLEED(x) (((uint32_t)(((uint32_t)(x)) << PMC_MISCCTRL_DISABLE_BLEED_SHIFT)) & PMC_MISCCTRL_DISABLE_BLEED_MASK) + +#define PMC_MISCCTRL_MISCCTRL_13_15_MASK (0xE000U) +#define PMC_MISCCTRL_MISCCTRL_13_15_SHIFT (13U) +/*! MISCCTRL_13_15 - Reserved. + */ +#define PMC_MISCCTRL_MISCCTRL_13_15(x) (((uint32_t)(((uint32_t)(x)) << PMC_MISCCTRL_MISCCTRL_13_15_SHIFT)) & PMC_MISCCTRL_MISCCTRL_13_15_MASK) +/*! @} */ + +/*! @name RTCOSC32K - RTC 1 KHZ and 1 Hz clocks source control register [Reset by: PoR, Brown Out Detectors Reset] */ +/*! @{ */ + +#define PMC_RTCOSC32K_SEL_MASK (0x1U) +#define PMC_RTCOSC32K_SEL_SHIFT (0U) +/*! SEL - Select the 32K oscillator to be used in Deep Power Down Mode for the RTC (either XTAL32KHz or FRO32KHz) . + * 0b0..FRO 32 KHz. + * 0b1..XTAL 32KHz. + */ +#define PMC_RTCOSC32K_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMC_RTCOSC32K_SEL_SHIFT)) & PMC_RTCOSC32K_SEL_MASK) + +#define PMC_RTCOSC32K_CLK1KHZDIV_MASK (0xEU) +#define PMC_RTCOSC32K_CLK1KHZDIV_SHIFT (1U) +/*! CLK1KHZDIV - Actual division ratio is : 28 + CLK1KHZDIV. + */ +#define PMC_RTCOSC32K_CLK1KHZDIV(x) (((uint32_t)(((uint32_t)(x)) << PMC_RTCOSC32K_CLK1KHZDIV_SHIFT)) & PMC_RTCOSC32K_CLK1KHZDIV_MASK) + +#define PMC_RTCOSC32K_CLK1KHZDIVUPDATEREQ_MASK (0x8000U) +#define PMC_RTCOSC32K_CLK1KHZDIVUPDATEREQ_SHIFT (15U) +/*! CLK1KHZDIVUPDATEREQ - RTC 1KHz clock Divider status flag. + */ +#define PMC_RTCOSC32K_CLK1KHZDIVUPDATEREQ(x) (((uint32_t)(((uint32_t)(x)) << PMC_RTCOSC32K_CLK1KHZDIVUPDATEREQ_SHIFT)) & PMC_RTCOSC32K_CLK1KHZDIVUPDATEREQ_MASK) + +#define PMC_RTCOSC32K_CLK1HZDIV_MASK (0x7FF0000U) +#define PMC_RTCOSC32K_CLK1HZDIV_SHIFT (16U) +/*! CLK1HZDIV - Actual division ratio is : 31744 + CLK1HZDIV. + */ +#define PMC_RTCOSC32K_CLK1HZDIV(x) (((uint32_t)(((uint32_t)(x)) << PMC_RTCOSC32K_CLK1HZDIV_SHIFT)) & PMC_RTCOSC32K_CLK1HZDIV_MASK) + +#define PMC_RTCOSC32K_CLK1HZDIVHALT_MASK (0x40000000U) +#define PMC_RTCOSC32K_CLK1HZDIVHALT_SHIFT (30U) +/*! CLK1HZDIVHALT - Halts the divider counter. + */ +#define PMC_RTCOSC32K_CLK1HZDIVHALT(x) (((uint32_t)(((uint32_t)(x)) << PMC_RTCOSC32K_CLK1HZDIVHALT_SHIFT)) & PMC_RTCOSC32K_CLK1HZDIVHALT_MASK) + +#define PMC_RTCOSC32K_CLK1HZDIVUPDATEREQ_MASK (0x80000000U) +#define PMC_RTCOSC32K_CLK1HZDIVUPDATEREQ_SHIFT (31U) +/*! CLK1HZDIVUPDATEREQ - RTC 1Hz Divider status flag. + */ +#define PMC_RTCOSC32K_CLK1HZDIVUPDATEREQ(x) (((uint32_t)(((uint32_t)(x)) << PMC_RTCOSC32K_CLK1HZDIVUPDATEREQ_SHIFT)) & PMC_RTCOSC32K_CLK1HZDIVUPDATEREQ_MASK) +/*! @} */ + +/*! @name OSTIMER - OS Timer control register [Reset by: PoR, Brown Out Detectors Reset] */ +/*! @{ */ + +#define PMC_OSTIMER_SOFTRESET_MASK (0x1U) +#define PMC_OSTIMER_SOFTRESET_SHIFT (0U) +/*! SOFTRESET - Active high reset. + */ +#define PMC_OSTIMER_SOFTRESET(x) (((uint32_t)(((uint32_t)(x)) << PMC_OSTIMER_SOFTRESET_SHIFT)) & PMC_OSTIMER_SOFTRESET_MASK) + +#define PMC_OSTIMER_CLOCKENABLE_MASK (0x2U) +#define PMC_OSTIMER_CLOCKENABLE_SHIFT (1U) +/*! CLOCKENABLE - Enable OS event timer clock. + */ +#define PMC_OSTIMER_CLOCKENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_OSTIMER_CLOCKENABLE_SHIFT)) & PMC_OSTIMER_CLOCKENABLE_MASK) + +#define PMC_OSTIMER_DPDWAKEUPENABLE_MASK (0x4U) +#define PMC_OSTIMER_DPDWAKEUPENABLE_SHIFT (2U) +/*! DPDWAKEUPENABLE - Wake up enable in Deep Power Down mode (To be used in Enable Deep Power Down mode). + */ +#define PMC_OSTIMER_DPDWAKEUPENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_OSTIMER_DPDWAKEUPENABLE_SHIFT)) & PMC_OSTIMER_DPDWAKEUPENABLE_MASK) + +#define PMC_OSTIMER_OSC32KPD_MASK (0x8U) +#define PMC_OSTIMER_OSC32KPD_SHIFT (3U) +/*! OSC32KPD - Oscilator 32KHz (either FRO32KHz or XTAL32KHz according to RTCOSC32K. + */ +#define PMC_OSTIMER_OSC32KPD(x) (((uint32_t)(((uint32_t)(x)) << PMC_OSTIMER_OSC32KPD_SHIFT)) & PMC_OSTIMER_OSC32KPD_MASK) + +#define PMC_OSTIMER_OSTIMERCLKSEL_MASK (0x30U) +#define PMC_OSTIMER_OSTIMERCLKSEL_SHIFT (4U) +/*! OSTIMERCLKSEL - OS event timer clock select. + * 0b00..Oscillator 32 kHz clock. + * 0b01..FRO 1MHz clock. + * 0b10..Main clock for OS timer. + * 0b11..No clock. + */ +#define PMC_OSTIMER_OSTIMERCLKSEL(x) (((uint32_t)(((uint32_t)(x)) << PMC_OSTIMER_OSTIMERCLKSEL_SHIFT)) & PMC_OSTIMER_OSTIMERCLKSEL_MASK) +/*! @} */ + +/*! @name PDRUNCFG0 - Controls the power to various analog blocks [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */ +/*! @{ */ + +#define PMC_PDRUNCFG0_PDEN_BODVBAT_MASK (0x8U) +#define PMC_PDRUNCFG0_PDEN_BODVBAT_SHIFT (3U) +/*! PDEN_BODVBAT - Controls power to VBAT Brown Out Detector (BOD). + * 0b0..BOD VBAT is powered. + * 0b1..BOD VBAT is powered down. + */ +#define PMC_PDRUNCFG0_PDEN_BODVBAT(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_BODVBAT_SHIFT)) & PMC_PDRUNCFG0_PDEN_BODVBAT_MASK) + +#define PMC_PDRUNCFG0_PDEN_FRO32K_MASK (0x40U) +#define PMC_PDRUNCFG0_PDEN_FRO32K_SHIFT (6U) +/*! PDEN_FRO32K - Controls power to the Free Running Oscillator (FRO) 32 KHz. + * 0b0..FRO32KHz is powered. + * 0b1..FRO32KHz is powered down. + */ +#define PMC_PDRUNCFG0_PDEN_FRO32K(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_FRO32K_SHIFT)) & PMC_PDRUNCFG0_PDEN_FRO32K_MASK) + +#define PMC_PDRUNCFG0_PDEN_XTAL32K_MASK (0x80U) +#define PMC_PDRUNCFG0_PDEN_XTAL32K_SHIFT (7U) +/*! PDEN_XTAL32K - Controls power to crystal 32 KHz. + * 0b0..Crystal 32KHz is powered. + * 0b1..Crystal 32KHz is powered down. + */ +#define PMC_PDRUNCFG0_PDEN_XTAL32K(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_XTAL32K_SHIFT)) & PMC_PDRUNCFG0_PDEN_XTAL32K_MASK) + +#define PMC_PDRUNCFG0_PDEN_XTAL32M_MASK (0x100U) +#define PMC_PDRUNCFG0_PDEN_XTAL32M_SHIFT (8U) +/*! PDEN_XTAL32M - Controls power to high speed crystal. + * 0b0..High speed crystal is powered. + * 0b1..High speed crystal is powered down. + */ +#define PMC_PDRUNCFG0_PDEN_XTAL32M(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_XTAL32M_SHIFT)) & PMC_PDRUNCFG0_PDEN_XTAL32M_MASK) + +#define PMC_PDRUNCFG0_PDEN_PLL0_MASK (0x200U) +#define PMC_PDRUNCFG0_PDEN_PLL0_SHIFT (9U) +/*! PDEN_PLL0 - Controls power to System PLL (also refered as PLL0). + * 0b0..PLL0 is powered. + * 0b1..PLL0 is powered down. + */ +#define PMC_PDRUNCFG0_PDEN_PLL0(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_PLL0_SHIFT)) & PMC_PDRUNCFG0_PDEN_PLL0_MASK) + +#define PMC_PDRUNCFG0_PDEN_PLL1_MASK (0x400U) +#define PMC_PDRUNCFG0_PDEN_PLL1_SHIFT (10U) +/*! PDEN_PLL1 - Controls power to USB PLL (also refered as PLL1). + * 0b0..PLL1 is powered. + * 0b1..PLL1 is powered down. + */ +#define PMC_PDRUNCFG0_PDEN_PLL1(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_PLL1_SHIFT)) & PMC_PDRUNCFG0_PDEN_PLL1_MASK) + +#define PMC_PDRUNCFG0_PDEN_USBFSPHY_MASK (0x800U) +#define PMC_PDRUNCFG0_PDEN_USBFSPHY_SHIFT (11U) +/*! PDEN_USBFSPHY - Controls power to USB Full Speed phy. + * 0b0..USB Full Speed phy is powered. + * 0b1..USB Full Speed phy is powered down. + */ +#define PMC_PDRUNCFG0_PDEN_USBFSPHY(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_USBFSPHY_SHIFT)) & PMC_PDRUNCFG0_PDEN_USBFSPHY_MASK) + +#define PMC_PDRUNCFG0_PDEN_USBHSPHY_MASK (0x1000U) +#define PMC_PDRUNCFG0_PDEN_USBHSPHY_SHIFT (12U) +/*! PDEN_USBHSPHY - Controls power to USB High Speed Phy. + * 0b0..USB HS phy is powered. + * 0b1..USB HS phy is powered down. + */ +#define PMC_PDRUNCFG0_PDEN_USBHSPHY(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_USBHSPHY_SHIFT)) & PMC_PDRUNCFG0_PDEN_USBHSPHY_MASK) + +#define PMC_PDRUNCFG0_PDEN_COMP_MASK (0x2000U) +#define PMC_PDRUNCFG0_PDEN_COMP_SHIFT (13U) +/*! PDEN_COMP - Controls power to Analog Comparator. + * 0b0..Analog Comparator is powered. + * 0b1..Analog Comparator is powered down. + */ +#define PMC_PDRUNCFG0_PDEN_COMP(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_COMP_SHIFT)) & PMC_PDRUNCFG0_PDEN_COMP_MASK) + +#define PMC_PDRUNCFG0_PDEN_LDOUSBHS_MASK (0x40000U) +#define PMC_PDRUNCFG0_PDEN_LDOUSBHS_SHIFT (18U) +/*! PDEN_LDOUSBHS - Controls power to USB high speed LDO. + * 0b0..USB high speed LDO is powered. + * 0b1..USB high speed LDO is powered down. + */ +#define PMC_PDRUNCFG0_PDEN_LDOUSBHS(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_LDOUSBHS_SHIFT)) & PMC_PDRUNCFG0_PDEN_LDOUSBHS_MASK) + +#define PMC_PDRUNCFG0_PDEN_AUXBIAS_MASK (0x80000U) +#define PMC_PDRUNCFG0_PDEN_AUXBIAS_SHIFT (19U) +/*! PDEN_AUXBIAS - Controls power to auxiliary biasing (AUXBIAS) + * 0b0..auxiliary biasing is powered. + * 0b1..auxiliary biasing is powered down. + */ +#define PMC_PDRUNCFG0_PDEN_AUXBIAS(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_AUXBIAS_SHIFT)) & PMC_PDRUNCFG0_PDEN_AUXBIAS_MASK) + +#define PMC_PDRUNCFG0_PDEN_LDOXO32M_MASK (0x100000U) +#define PMC_PDRUNCFG0_PDEN_LDOXO32M_SHIFT (20U) +/*! PDEN_LDOXO32M - Controls power to high speed crystal LDO. + * 0b0..High speed crystal LDO is powered. + * 0b1..High speed crystal LDO is powered down. + */ +#define PMC_PDRUNCFG0_PDEN_LDOXO32M(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_LDOXO32M_SHIFT)) & PMC_PDRUNCFG0_PDEN_LDOXO32M_MASK) + +#define PMC_PDRUNCFG0_PDEN_RNG_MASK (0x400000U) +#define PMC_PDRUNCFG0_PDEN_RNG_SHIFT (22U) +/*! PDEN_RNG - Controls power to all True Random Number Genetaor (TRNG) clock sources. + * 0b0..TRNG clocks are powered. + * 0b1..TRNG clocks are powered down. + */ +#define PMC_PDRUNCFG0_PDEN_RNG(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_RNG_SHIFT)) & PMC_PDRUNCFG0_PDEN_RNG_MASK) + +#define PMC_PDRUNCFG0_PDEN_PLL0_SSCG_MASK (0x800000U) +#define PMC_PDRUNCFG0_PDEN_PLL0_SSCG_SHIFT (23U) +/*! PDEN_PLL0_SSCG - Controls power to System PLL (PLL0) Spread Spectrum module. + * 0b0..PLL0 Sread spectrum module is powered. + * 0b1..PLL0 Sread spectrum module is powered down. + */ +#define PMC_PDRUNCFG0_PDEN_PLL0_SSCG(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_PLL0_SSCG_SHIFT)) & PMC_PDRUNCFG0_PDEN_PLL0_SSCG_MASK) +/*! @} */ + +/*! @name PDRUNCFGSET0 - Controls the power to various analog blocks [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */ +/*! @{ */ + +#define PMC_PDRUNCFGSET0_PDRUNCFGSET0_MASK (0xFFFFFFFFU) +#define PMC_PDRUNCFGSET0_PDRUNCFGSET0_SHIFT (0U) +/*! PDRUNCFGSET0 - Writing ones to this register sets the corresponding bit or bits in the PDRUNCFG0 register, if they are implemented. + */ +#define PMC_PDRUNCFGSET0_PDRUNCFGSET0(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFGSET0_PDRUNCFGSET0_SHIFT)) & PMC_PDRUNCFGSET0_PDRUNCFGSET0_MASK) +/*! @} */ + +/*! @name PDRUNCFGCLR0 - Controls the power to various analog blocks [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */ +/*! @{ */ + +#define PMC_PDRUNCFGCLR0_PDRUNCFGCLR0_MASK (0xFFFFFFFFU) +#define PMC_PDRUNCFGCLR0_PDRUNCFGCLR0_SHIFT (0U) +/*! PDRUNCFGCLR0 - Writing ones to this register clears the corresponding bit or bits in the PDRUNCFG0 register, if they are implemented. + */ +#define PMC_PDRUNCFGCLR0_PDRUNCFGCLR0(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFGCLR0_PDRUNCFGCLR0_SHIFT)) & PMC_PDRUNCFGCLR0_PDRUNCFGCLR0_MASK) +/*! @} */ + +/*! @name SRAMCTRL - All SRAMs common control signals [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Software Reset] */ +/*! @{ */ + +#define PMC_SRAMCTRL_SMB_MASK (0x3U) +#define PMC_SRAMCTRL_SMB_SHIFT (0U) +/*! SMB - Source Biasing voltage. + * 0b00..Low leakage. + * 0b01..Medium leakage. + * 0b10..Highest leakage. + * 0b11..Disable. + */ +#define PMC_SRAMCTRL_SMB(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL_SMB_SHIFT)) & PMC_SRAMCTRL_SMB_MASK) + +#define PMC_SRAMCTRL_RM_MASK (0x1CU) +#define PMC_SRAMCTRL_RM_SHIFT (2U) +/*! RM - Read Margin control settings. + */ +#define PMC_SRAMCTRL_RM(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL_RM_SHIFT)) & PMC_SRAMCTRL_RM_MASK) + +#define PMC_SRAMCTRL_WM_MASK (0xE0U) +#define PMC_SRAMCTRL_WM_SHIFT (5U) +/*! WM - Write Margin control settings. + */ +#define PMC_SRAMCTRL_WM(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL_WM_SHIFT)) & PMC_SRAMCTRL_WM_MASK) + +#define PMC_SRAMCTRL_WRME_MASK (0x100U) +#define PMC_SRAMCTRL_WRME_SHIFT (8U) +/*! WRME - Write read margin enable. + */ +#define PMC_SRAMCTRL_WRME(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL_WRME_SHIFT)) & PMC_SRAMCTRL_WRME_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group PMC_Register_Masks */ + + +/* PMC - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral PMC base address */ + #define PMC_BASE (0x50020000u) + /** Peripheral PMC base address */ + #define PMC_BASE_NS (0x40020000u) + /** Peripheral PMC base pointer */ + #define PMC ((PMC_Type *)PMC_BASE) + /** Peripheral PMC base pointer */ + #define PMC_NS ((PMC_Type *)PMC_BASE_NS) + /** Array initializer of PMC peripheral base addresses */ + #define PMC_BASE_ADDRS { PMC_BASE } + /** Array initializer of PMC peripheral base pointers */ + #define PMC_BASE_PTRS { PMC } + /** Array initializer of PMC peripheral base addresses */ + #define PMC_BASE_ADDRS_NS { PMC_BASE_NS } + /** Array initializer of PMC peripheral base pointers */ + #define PMC_BASE_PTRS_NS { PMC_NS } +#else + /** Peripheral PMC base address */ + #define PMC_BASE (0x40020000u) + /** Peripheral PMC base pointer */ + #define PMC ((PMC_Type *)PMC_BASE) + /** Array initializer of PMC peripheral base addresses */ + #define PMC_BASE_ADDRS { PMC_BASE } + /** Array initializer of PMC peripheral base pointers */ + #define PMC_BASE_PTRS { PMC } +#endif + +/*! + * @} + */ /* end of group PMC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- PRINCE Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PRINCE_Peripheral_Access_Layer PRINCE Peripheral Access Layer + * @{ + */ + +/** PRINCE - Register Layout Typedef */ +typedef struct { + __IO uint32_t ENC_ENABLE; /**< Encryption Enable register, offset: 0x0 */ + __O uint32_t MASK_LSB; /**< Data Mask register, 32 Least Significant Bits, offset: 0x4 */ + __O uint32_t MASK_MSB; /**< Data Mask register, 32 Most Significant Bits, offset: 0x8 */ + __IO uint32_t LOCK; /**< Lock register, offset: 0xC */ + __O uint32_t IV_LSB0; /**< Initial Vector register for region 0, Least Significant Bits, offset: 0x10 */ + __O uint32_t IV_MSB0; /**< Initial Vector register for region 0, Most Significant Bits, offset: 0x14 */ + __IO uint32_t BASE_ADDR0; /**< Base Address for region 0 register, offset: 0x18 */ + __IO uint32_t SR_ENABLE0; /**< Sub-Region Enable register for region 0, offset: 0x1C */ + __O uint32_t IV_LSB1; /**< Initial Vector register for region 1, Least Significant Bits, offset: 0x20 */ + __O uint32_t IV_MSB1; /**< Initial Vector register for region 1, Most Significant Bits, offset: 0x24 */ + __IO uint32_t BASE_ADDR1; /**< Base Address for region 1 register, offset: 0x28 */ + __IO uint32_t SR_ENABLE1; /**< Sub-Region Enable register for region 1, offset: 0x2C */ + __O uint32_t IV_LSB2; /**< Initial Vector register for region 2, Least Significant Bits, offset: 0x30 */ + __O uint32_t IV_MSB2; /**< Initial Vector register for region 2, Most Significant Bits, offset: 0x34 */ + __IO uint32_t BASE_ADDR2; /**< Base Address for region 2 register, offset: 0x38 */ + __IO uint32_t SR_ENABLE2; /**< Sub-Region Enable register for region 2, offset: 0x3C */ + uint8_t RESERVED_0[80]; + __IO uint32_t ERR; /**< Error status register, offset: 0x90 */ +} PRINCE_Type; + +/* ---------------------------------------------------------------------------- + -- PRINCE Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PRINCE_Register_Masks PRINCE Register Masks + * @{ + */ + +/*! @name ENC_ENABLE - Encryption Enable register */ +/*! @{ */ + +#define PRINCE_ENC_ENABLE_EN_MASK (0x1U) +#define PRINCE_ENC_ENABLE_EN_SHIFT (0U) +/*! EN - Enables PRINCE encryption for flash programming. + * 0b0..Encryption of writes to the flash controller DATAW* registers is disabled. + * 0b1..Encryption of writes to the flash controller DATAW* registers is enabled. Reading of PRINCE-encrypted flash regions is disabled. + */ +#define PRINCE_ENC_ENABLE_EN(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_ENC_ENABLE_EN_SHIFT)) & PRINCE_ENC_ENABLE_EN_MASK) +/*! @} */ + +/*! @name MASK_LSB - Data Mask register, 32 Least Significant Bits */ +/*! @{ */ + +#define PRINCE_MASK_LSB_MASKVAL_MASK (0xFFFFFFFFU) +#define PRINCE_MASK_LSB_MASKVAL_SHIFT (0U) +/*! MASKVAL - Value of the 32 Least Significant Bits of the 64-bit data mask. + */ +#define PRINCE_MASK_LSB_MASKVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_MASK_LSB_MASKVAL_SHIFT)) & PRINCE_MASK_LSB_MASKVAL_MASK) +/*! @} */ + +/*! @name MASK_MSB - Data Mask register, 32 Most Significant Bits */ +/*! @{ */ + +#define PRINCE_MASK_MSB_MASKVAL_MASK (0xFFFFFFFFU) +#define PRINCE_MASK_MSB_MASKVAL_SHIFT (0U) +/*! MASKVAL - Value of the 32 Most Significant Bits of the 64-bit data mask. + */ +#define PRINCE_MASK_MSB_MASKVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_MASK_MSB_MASKVAL_SHIFT)) & PRINCE_MASK_MSB_MASKVAL_MASK) +/*! @} */ + +/*! @name LOCK - Lock register */ +/*! @{ */ + +#define PRINCE_LOCK_LOCKREG0_MASK (0x1U) +#define PRINCE_LOCK_LOCKREG0_SHIFT (0U) +/*! LOCKREG0 - Lock Region 0 registers. + * 0b0..Disabled. IV_LSB0, IV_MSB0, BASE_ADDR0, and SR_ENABLE0 are writable.. + * 0b1..Enabled. IV_LSB0, IV_MSB0, BASE_ADDR0, and SR_ENABLE0 are not writable.. + */ +#define PRINCE_LOCK_LOCKREG0(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_LOCK_LOCKREG0_SHIFT)) & PRINCE_LOCK_LOCKREG0_MASK) + +#define PRINCE_LOCK_LOCKREG1_MASK (0x2U) +#define PRINCE_LOCK_LOCKREG1_SHIFT (1U) +/*! LOCKREG1 - Lock Region 1 registers. + * 0b0..Disabled. IV_LSB1, IV_MSB1, BASE_ADDR1, and SR_ENABLE1 are writable.. + * 0b1..Enabled. IV_LSB1, IV_MSB1, BASE_ADDR1, and SR_ENABLE1 are not writable.. + */ +#define PRINCE_LOCK_LOCKREG1(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_LOCK_LOCKREG1_SHIFT)) & PRINCE_LOCK_LOCKREG1_MASK) + +#define PRINCE_LOCK_LOCKREG2_MASK (0x4U) +#define PRINCE_LOCK_LOCKREG2_SHIFT (2U) +/*! LOCKREG2 - Lock Region 2 registers. + * 0b0..Disabled. IV_LSB2, IV_MSB2, BASE_ADDR2, and SR_ENABLE2 are writable.. + * 0b1..Enabled. IV_LSB2, IV_MSB2, BASE_ADDR2, and SR_ENABLE2 are not writable.. + */ +#define PRINCE_LOCK_LOCKREG2(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_LOCK_LOCKREG2_SHIFT)) & PRINCE_LOCK_LOCKREG2_MASK) + +#define PRINCE_LOCK_LOCKMASK_MASK (0x100U) +#define PRINCE_LOCK_LOCKMASK_SHIFT (8U) +/*! LOCKMASK - Lock the Mask registers. + * 0b0..Disabled. MASK_LSB, and MASK_MSB are writable.. + * 0b1..Enabled. MASK_LSB, and MASK_MSB are not writable.. + */ +#define PRINCE_LOCK_LOCKMASK(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_LOCK_LOCKMASK_SHIFT)) & PRINCE_LOCK_LOCKMASK_MASK) +/*! @} */ + +/*! @name IV_LSB0 - Initial Vector register for region 0, Least Significant Bits */ +/*! @{ */ + +#define PRINCE_IV_LSB0_IVVAL_MASK (0xFFFFFFFFU) +#define PRINCE_IV_LSB0_IVVAL_SHIFT (0U) +/*! IVVAL - Initial Vector value for the 32 Least Significant Bits of the 64-bit Initial Vector. + */ +#define PRINCE_IV_LSB0_IVVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_IV_LSB0_IVVAL_SHIFT)) & PRINCE_IV_LSB0_IVVAL_MASK) +/*! @} */ + +/*! @name IV_MSB0 - Initial Vector register for region 0, Most Significant Bits */ +/*! @{ */ + +#define PRINCE_IV_MSB0_IVVAL_MASK (0xFFFFFFFFU) +#define PRINCE_IV_MSB0_IVVAL_SHIFT (0U) +/*! IVVAL - Initial Vector value for the 32 Most Significant Bits of the 64-bit Initial Vector. + */ +#define PRINCE_IV_MSB0_IVVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_IV_MSB0_IVVAL_SHIFT)) & PRINCE_IV_MSB0_IVVAL_MASK) +/*! @} */ + +/*! @name BASE_ADDR0 - Base Address for region 0 register */ +/*! @{ */ + +#define PRINCE_BASE_ADDR0_ADDR_FIXED_MASK (0x3FFFFU) +#define PRINCE_BASE_ADDR0_ADDR_FIXED_SHIFT (0U) +/*! ADDR_FIXED - Fixed portion of the base address of region 0. + */ +#define PRINCE_BASE_ADDR0_ADDR_FIXED(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_BASE_ADDR0_ADDR_FIXED_SHIFT)) & PRINCE_BASE_ADDR0_ADDR_FIXED_MASK) + +#define PRINCE_BASE_ADDR0_ADDR_PRG_MASK (0xC0000U) +#define PRINCE_BASE_ADDR0_ADDR_PRG_SHIFT (18U) +/*! ADDR_PRG - Programmable portion of the base address of region 0. + */ +#define PRINCE_BASE_ADDR0_ADDR_PRG(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_BASE_ADDR0_ADDR_PRG_SHIFT)) & PRINCE_BASE_ADDR0_ADDR_PRG_MASK) +/*! @} */ + +/*! @name SR_ENABLE0 - Sub-Region Enable register for region 0 */ +/*! @{ */ + +#define PRINCE_SR_ENABLE0_EN_MASK (0xFFFFFFFFU) +#define PRINCE_SR_ENABLE0_EN_SHIFT (0U) +/*! EN - Each bit in this field enables an 8KB subregion for encryption at offset 8KB*bitnum of region 0. + */ +#define PRINCE_SR_ENABLE0_EN(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_SR_ENABLE0_EN_SHIFT)) & PRINCE_SR_ENABLE0_EN_MASK) +/*! @} */ + +/*! @name IV_LSB1 - Initial Vector register for region 1, Least Significant Bits */ +/*! @{ */ + +#define PRINCE_IV_LSB1_IVVAL_MASK (0xFFFFFFFFU) +#define PRINCE_IV_LSB1_IVVAL_SHIFT (0U) +/*! IVVAL - Initial Vector value for the 32 Least Significant Bits of the 64-bit Initial Vector. + */ +#define PRINCE_IV_LSB1_IVVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_IV_LSB1_IVVAL_SHIFT)) & PRINCE_IV_LSB1_IVVAL_MASK) +/*! @} */ + +/*! @name IV_MSB1 - Initial Vector register for region 1, Most Significant Bits */ +/*! @{ */ + +#define PRINCE_IV_MSB1_IVVAL_MASK (0xFFFFFFFFU) +#define PRINCE_IV_MSB1_IVVAL_SHIFT (0U) +/*! IVVAL - Initial Vector value for the 32 Most Significant Bits of the 64-bit Initial Vector. + */ +#define PRINCE_IV_MSB1_IVVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_IV_MSB1_IVVAL_SHIFT)) & PRINCE_IV_MSB1_IVVAL_MASK) +/*! @} */ + +/*! @name BASE_ADDR1 - Base Address for region 1 register */ +/*! @{ */ + +#define PRINCE_BASE_ADDR1_ADDR_FIXED_MASK (0x3FFFFU) +#define PRINCE_BASE_ADDR1_ADDR_FIXED_SHIFT (0U) +/*! ADDR_FIXED - Fixed portion of the base address of region 1. + */ +#define PRINCE_BASE_ADDR1_ADDR_FIXED(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_BASE_ADDR1_ADDR_FIXED_SHIFT)) & PRINCE_BASE_ADDR1_ADDR_FIXED_MASK) + +#define PRINCE_BASE_ADDR1_ADDR_PRG_MASK (0xC0000U) +#define PRINCE_BASE_ADDR1_ADDR_PRG_SHIFT (18U) +/*! ADDR_PRG - Programmable portion of the base address of region 1. + */ +#define PRINCE_BASE_ADDR1_ADDR_PRG(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_BASE_ADDR1_ADDR_PRG_SHIFT)) & PRINCE_BASE_ADDR1_ADDR_PRG_MASK) +/*! @} */ + +/*! @name SR_ENABLE1 - Sub-Region Enable register for region 1 */ +/*! @{ */ + +#define PRINCE_SR_ENABLE1_EN_MASK (0xFFFFFFFFU) +#define PRINCE_SR_ENABLE1_EN_SHIFT (0U) +/*! EN - Each bit in this field enables an 8KB subregion for encryption at offset 8KB*bitnum of region 1. + */ +#define PRINCE_SR_ENABLE1_EN(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_SR_ENABLE1_EN_SHIFT)) & PRINCE_SR_ENABLE1_EN_MASK) +/*! @} */ + +/*! @name IV_LSB2 - Initial Vector register for region 2, Least Significant Bits */ +/*! @{ */ + +#define PRINCE_IV_LSB2_IVVAL_MASK (0xFFFFFFFFU) +#define PRINCE_IV_LSB2_IVVAL_SHIFT (0U) +/*! IVVAL - Initial Vector value for the 32 Least Significant Bits of the 64-bit Initial Vector. + */ +#define PRINCE_IV_LSB2_IVVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_IV_LSB2_IVVAL_SHIFT)) & PRINCE_IV_LSB2_IVVAL_MASK) +/*! @} */ + +/*! @name IV_MSB2 - Initial Vector register for region 2, Most Significant Bits */ +/*! @{ */ + +#define PRINCE_IV_MSB2_IVVAL_MASK (0xFFFFFFFFU) +#define PRINCE_IV_MSB2_IVVAL_SHIFT (0U) +/*! IVVAL - Initial Vector value for the 32 Most Significant Bits of the 64-bit Initial Vector. + */ +#define PRINCE_IV_MSB2_IVVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_IV_MSB2_IVVAL_SHIFT)) & PRINCE_IV_MSB2_IVVAL_MASK) +/*! @} */ + +/*! @name BASE_ADDR2 - Base Address for region 2 register */ +/*! @{ */ + +#define PRINCE_BASE_ADDR2_ADDR_FIXED_MASK (0x3FFFFU) +#define PRINCE_BASE_ADDR2_ADDR_FIXED_SHIFT (0U) +/*! ADDR_FIXED - Fixed portion of the base address of region 2. + */ +#define PRINCE_BASE_ADDR2_ADDR_FIXED(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_BASE_ADDR2_ADDR_FIXED_SHIFT)) & PRINCE_BASE_ADDR2_ADDR_FIXED_MASK) + +#define PRINCE_BASE_ADDR2_ADDR_PRG_MASK (0xC0000U) +#define PRINCE_BASE_ADDR2_ADDR_PRG_SHIFT (18U) +/*! ADDR_PRG - Programmable portion of the base address of region 2. + */ +#define PRINCE_BASE_ADDR2_ADDR_PRG(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_BASE_ADDR2_ADDR_PRG_SHIFT)) & PRINCE_BASE_ADDR2_ADDR_PRG_MASK) +/*! @} */ + +/*! @name SR_ENABLE2 - Sub-Region Enable register for region 2 */ +/*! @{ */ + +#define PRINCE_SR_ENABLE2_EN_MASK (0xFFFFFFFFU) +#define PRINCE_SR_ENABLE2_EN_SHIFT (0U) +/*! EN - Each bit in this field enables an 8KB subregion for encryption at offset 8KB*bitnum of region 2. + */ +#define PRINCE_SR_ENABLE2_EN(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_SR_ENABLE2_EN_SHIFT)) & PRINCE_SR_ENABLE2_EN_MASK) +/*! @} */ + +/*! @name ERR - Error status register */ +/*! @{ */ + +#define PRINCE_ERR_ERRSTAT_MASK (0x1U) +#define PRINCE_ERR_ERRSTAT_SHIFT (0U) +/*! ERRSTAT - PRINCE Error Status. This bit is write-1 to clear. + * 0b0..No PRINCE error. + * 0b1..Error. A read of a PRINCE-encrypted region was attempted while ENC_ENABLE.EN=1. + */ +#define PRINCE_ERR_ERRSTAT(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_ERR_ERRSTAT_SHIFT)) & PRINCE_ERR_ERRSTAT_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group PRINCE_Register_Masks */ + + +/* PRINCE - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral PRINCE base address */ + #define PRINCE_BASE (0x50035000u) + /** Peripheral PRINCE base address */ + #define PRINCE_BASE_NS (0x40035000u) + /** Peripheral PRINCE base pointer */ + #define PRINCE ((PRINCE_Type *)PRINCE_BASE) + /** Peripheral PRINCE base pointer */ + #define PRINCE_NS ((PRINCE_Type *)PRINCE_BASE_NS) + /** Array initializer of PRINCE peripheral base addresses */ + #define PRINCE_BASE_ADDRS { PRINCE_BASE } + /** Array initializer of PRINCE peripheral base pointers */ + #define PRINCE_BASE_PTRS { PRINCE } + /** Array initializer of PRINCE peripheral base addresses */ + #define PRINCE_BASE_ADDRS_NS { PRINCE_BASE_NS } + /** Array initializer of PRINCE peripheral base pointers */ + #define PRINCE_BASE_PTRS_NS { PRINCE_NS } +#else + /** Peripheral PRINCE base address */ + #define PRINCE_BASE (0x40035000u) + /** Peripheral PRINCE base pointer */ + #define PRINCE ((PRINCE_Type *)PRINCE_BASE) + /** Array initializer of PRINCE peripheral base addresses */ + #define PRINCE_BASE_ADDRS { PRINCE_BASE } + /** Array initializer of PRINCE peripheral base pointers */ + #define PRINCE_BASE_PTRS { PRINCE } +#endif + +/*! + * @} + */ /* end of group PRINCE_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- PUF Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PUF_Peripheral_Access_Layer PUF Peripheral Access Layer + * @{ + */ + +/** PUF - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL; /**< PUF Control register, offset: 0x0 */ + __IO uint32_t KEYINDEX; /**< PUF Key Index register, offset: 0x4 */ + __IO uint32_t KEYSIZE; /**< PUF Key Size register, offset: 0x8 */ + uint8_t RESERVED_0[20]; + __I uint32_t STAT; /**< PUF Status register, offset: 0x20 */ + uint8_t RESERVED_1[4]; + __I uint32_t ALLOW; /**< PUF Allow register, offset: 0x28 */ + uint8_t RESERVED_2[20]; + __O uint32_t KEYINPUT; /**< PUF Key Input register, offset: 0x40 */ + __O uint32_t CODEINPUT; /**< PUF Code Input register, offset: 0x44 */ + __I uint32_t CODEOUTPUT; /**< PUF Code Output register, offset: 0x48 */ + uint8_t RESERVED_3[20]; + __I uint32_t KEYOUTINDEX; /**< PUF Key Output Index register, offset: 0x60 */ + __I uint32_t KEYOUTPUT; /**< PUF Key Output register, offset: 0x64 */ + uint8_t RESERVED_4[116]; + __IO uint32_t IFSTAT; /**< PUF Interface Status and clear register, offset: 0xDC */ + uint8_t RESERVED_5[32]; + __IO uint32_t INTEN; /**< PUF Interrupt Enable, offset: 0x100 */ + __IO uint32_t INTSTAT; /**< PUF interrupt status, offset: 0x104 */ + uint8_t RESERVED_6[4]; + __IO uint32_t CFG; /**< PUF config register for block bits, offset: 0x10C */ + uint8_t RESERVED_7[240]; + __IO uint32_t KEYLOCK; /**< Only reset in case of full IC reset, offset: 0x200 */ + __IO uint32_t KEYENABLE; /**< , offset: 0x204 */ + __O uint32_t KEYRESET; /**< Reinitialize Keys shift registers counters, offset: 0x208 */ + __O uint32_t IDXBLK; /**< , offset: 0x20C */ + __O uint32_t IDXBLK_DP; /**< , offset: 0x210 */ + __O uint32_t KEYMASK[4]; /**< Only reset in case of full IC reset, array offset: 0x214, array step: 0x4 */ + uint8_t RESERVED_8[48]; + __I uint32_t IDXBLK_STATUS; /**< Index block status, offset: 0x254 */ + __I uint32_t SHIFT_STATUS; /**< , offset: 0x258 */ +} PUF_Type; + +/* ---------------------------------------------------------------------------- + -- PUF Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PUF_Register_Masks PUF Register Masks + * @{ + */ + +/*! @name CTRL - PUF Control register */ +/*! @{ */ + +#define PUF_CTRL_ZEROIZE_MASK (0x1U) +#define PUF_CTRL_ZEROIZE_SHIFT (0U) +/*! zeroize - Begin Zeroize operation for PUF and go to Error state + */ +#define PUF_CTRL_ZEROIZE(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_ZEROIZE_SHIFT)) & PUF_CTRL_ZEROIZE_MASK) + +#define PUF_CTRL_ENROLL_MASK (0x2U) +#define PUF_CTRL_ENROLL_SHIFT (1U) +/*! enroll - Begin Enroll operation + */ +#define PUF_CTRL_ENROLL(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_ENROLL_SHIFT)) & PUF_CTRL_ENROLL_MASK) + +#define PUF_CTRL_START_MASK (0x4U) +#define PUF_CTRL_START_SHIFT (2U) +/*! start - Begin Start operation + */ +#define PUF_CTRL_START(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_START_SHIFT)) & PUF_CTRL_START_MASK) + +#define PUF_CTRL_GENERATEKEY_MASK (0x8U) +#define PUF_CTRL_GENERATEKEY_SHIFT (3U) +/*! GENERATEKEY - Begin Set Intrinsic Key operation + */ +#define PUF_CTRL_GENERATEKEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_GENERATEKEY_SHIFT)) & PUF_CTRL_GENERATEKEY_MASK) + +#define PUF_CTRL_SETKEY_MASK (0x10U) +#define PUF_CTRL_SETKEY_SHIFT (4U) +/*! SETKEY - Begin Set User Key operation + */ +#define PUF_CTRL_SETKEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_SETKEY_SHIFT)) & PUF_CTRL_SETKEY_MASK) + +#define PUF_CTRL_GETKEY_MASK (0x40U) +#define PUF_CTRL_GETKEY_SHIFT (6U) +/*! GETKEY - Begin Get Key operation + */ +#define PUF_CTRL_GETKEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_GETKEY_SHIFT)) & PUF_CTRL_GETKEY_MASK) +/*! @} */ + +/*! @name KEYINDEX - PUF Key Index register */ +/*! @{ */ + +#define PUF_KEYINDEX_KEYIDX_MASK (0xFU) +#define PUF_KEYINDEX_KEYIDX_SHIFT (0U) +/*! KEYIDX - Key index for Set Key operations + */ +#define PUF_KEYINDEX_KEYIDX(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYINDEX_KEYIDX_SHIFT)) & PUF_KEYINDEX_KEYIDX_MASK) +/*! @} */ + +/*! @name KEYSIZE - PUF Key Size register */ +/*! @{ */ + +#define PUF_KEYSIZE_KEYSIZE_MASK (0x3FU) +#define PUF_KEYSIZE_KEYSIZE_SHIFT (0U) +/*! KEYSIZE - Key size for Set Key operations + */ +#define PUF_KEYSIZE_KEYSIZE(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYSIZE_KEYSIZE_SHIFT)) & PUF_KEYSIZE_KEYSIZE_MASK) +/*! @} */ + +/*! @name STAT - PUF Status register */ +/*! @{ */ + +#define PUF_STAT_BUSY_MASK (0x1U) +#define PUF_STAT_BUSY_SHIFT (0U) +/*! busy - Indicates that operation is in progress + */ +#define PUF_STAT_BUSY(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_BUSY_SHIFT)) & PUF_STAT_BUSY_MASK) + +#define PUF_STAT_SUCCESS_MASK (0x2U) +#define PUF_STAT_SUCCESS_SHIFT (1U) +/*! SUCCESS - Last operation was successful + */ +#define PUF_STAT_SUCCESS(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_SUCCESS_SHIFT)) & PUF_STAT_SUCCESS_MASK) + +#define PUF_STAT_ERROR_MASK (0x4U) +#define PUF_STAT_ERROR_SHIFT (2U) +/*! error - PUF is in the Error state and no operations can be performed + */ +#define PUF_STAT_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_ERROR_SHIFT)) & PUF_STAT_ERROR_MASK) + +#define PUF_STAT_KEYINREQ_MASK (0x10U) +#define PUF_STAT_KEYINREQ_SHIFT (4U) +/*! KEYINREQ - Request for next part of key + */ +#define PUF_STAT_KEYINREQ(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_KEYINREQ_SHIFT)) & PUF_STAT_KEYINREQ_MASK) + +#define PUF_STAT_KEYOUTAVAIL_MASK (0x20U) +#define PUF_STAT_KEYOUTAVAIL_SHIFT (5U) +/*! KEYOUTAVAIL - Next part of key is available + */ +#define PUF_STAT_KEYOUTAVAIL(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_KEYOUTAVAIL_SHIFT)) & PUF_STAT_KEYOUTAVAIL_MASK) + +#define PUF_STAT_CODEINREQ_MASK (0x40U) +#define PUF_STAT_CODEINREQ_SHIFT (6U) +/*! CODEINREQ - Request for next part of AC/KC + */ +#define PUF_STAT_CODEINREQ(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_CODEINREQ_SHIFT)) & PUF_STAT_CODEINREQ_MASK) + +#define PUF_STAT_CODEOUTAVAIL_MASK (0x80U) +#define PUF_STAT_CODEOUTAVAIL_SHIFT (7U) +/*! CODEOUTAVAIL - Next part of AC/KC is available + */ +#define PUF_STAT_CODEOUTAVAIL(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_CODEOUTAVAIL_SHIFT)) & PUF_STAT_CODEOUTAVAIL_MASK) +/*! @} */ + +/*! @name ALLOW - PUF Allow register */ +/*! @{ */ + +#define PUF_ALLOW_ALLOWENROLL_MASK (0x1U) +#define PUF_ALLOW_ALLOWENROLL_SHIFT (0U) +/*! ALLOWENROLL - Enroll operation is allowed + */ +#define PUF_ALLOW_ALLOWENROLL(x) (((uint32_t)(((uint32_t)(x)) << PUF_ALLOW_ALLOWENROLL_SHIFT)) & PUF_ALLOW_ALLOWENROLL_MASK) + +#define PUF_ALLOW_ALLOWSTART_MASK (0x2U) +#define PUF_ALLOW_ALLOWSTART_SHIFT (1U) +/*! ALLOWSTART - Start operation is allowed + */ +#define PUF_ALLOW_ALLOWSTART(x) (((uint32_t)(((uint32_t)(x)) << PUF_ALLOW_ALLOWSTART_SHIFT)) & PUF_ALLOW_ALLOWSTART_MASK) + +#define PUF_ALLOW_ALLOWSETKEY_MASK (0x4U) +#define PUF_ALLOW_ALLOWSETKEY_SHIFT (2U) +/*! ALLOWSETKEY - Set Key operations are allowed + */ +#define PUF_ALLOW_ALLOWSETKEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_ALLOW_ALLOWSETKEY_SHIFT)) & PUF_ALLOW_ALLOWSETKEY_MASK) + +#define PUF_ALLOW_ALLOWGETKEY_MASK (0x8U) +#define PUF_ALLOW_ALLOWGETKEY_SHIFT (3U) +/*! ALLOWGETKEY - Get Key operation is allowed + */ +#define PUF_ALLOW_ALLOWGETKEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_ALLOW_ALLOWGETKEY_SHIFT)) & PUF_ALLOW_ALLOWGETKEY_MASK) +/*! @} */ + +/*! @name KEYINPUT - PUF Key Input register */ +/*! @{ */ + +#define PUF_KEYINPUT_KEYIN_MASK (0xFFFFFFFFU) +#define PUF_KEYINPUT_KEYIN_SHIFT (0U) +/*! KEYIN - Key input data + */ +#define PUF_KEYINPUT_KEYIN(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYINPUT_KEYIN_SHIFT)) & PUF_KEYINPUT_KEYIN_MASK) +/*! @} */ + +/*! @name CODEINPUT - PUF Code Input register */ +/*! @{ */ + +#define PUF_CODEINPUT_CODEIN_MASK (0xFFFFFFFFU) +#define PUF_CODEINPUT_CODEIN_SHIFT (0U) +/*! CODEIN - AC/KC input data + */ +#define PUF_CODEINPUT_CODEIN(x) (((uint32_t)(((uint32_t)(x)) << PUF_CODEINPUT_CODEIN_SHIFT)) & PUF_CODEINPUT_CODEIN_MASK) +/*! @} */ + +/*! @name CODEOUTPUT - PUF Code Output register */ +/*! @{ */ + +#define PUF_CODEOUTPUT_CODEOUT_MASK (0xFFFFFFFFU) +#define PUF_CODEOUTPUT_CODEOUT_SHIFT (0U) +/*! CODEOUT - AC/KC output data + */ +#define PUF_CODEOUTPUT_CODEOUT(x) (((uint32_t)(((uint32_t)(x)) << PUF_CODEOUTPUT_CODEOUT_SHIFT)) & PUF_CODEOUTPUT_CODEOUT_MASK) +/*! @} */ + +/*! @name KEYOUTINDEX - PUF Key Output Index register */ +/*! @{ */ + +#define PUF_KEYOUTINDEX_KEYOUTIDX_MASK (0xFU) +#define PUF_KEYOUTINDEX_KEYOUTIDX_SHIFT (0U) +/*! KEYOUTIDX - Key index for the key that is currently output via the Key Output register + */ +#define PUF_KEYOUTINDEX_KEYOUTIDX(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYOUTINDEX_KEYOUTIDX_SHIFT)) & PUF_KEYOUTINDEX_KEYOUTIDX_MASK) +/*! @} */ + +/*! @name KEYOUTPUT - PUF Key Output register */ +/*! @{ */ + +#define PUF_KEYOUTPUT_KEYOUT_MASK (0xFFFFFFFFU) +#define PUF_KEYOUTPUT_KEYOUT_SHIFT (0U) +/*! KEYOUT - Key output data + */ +#define PUF_KEYOUTPUT_KEYOUT(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYOUTPUT_KEYOUT_SHIFT)) & PUF_KEYOUTPUT_KEYOUT_MASK) +/*! @} */ + +/*! @name IFSTAT - PUF Interface Status and clear register */ +/*! @{ */ + +#define PUF_IFSTAT_ERROR_MASK (0x1U) +#define PUF_IFSTAT_ERROR_SHIFT (0U) +/*! ERROR - Indicates that an APB error has occurred,Writing logic1 clears the if_error bit + */ +#define PUF_IFSTAT_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PUF_IFSTAT_ERROR_SHIFT)) & PUF_IFSTAT_ERROR_MASK) +/*! @} */ + +/*! @name INTEN - PUF Interrupt Enable */ +/*! @{ */ + +#define PUF_INTEN_READYEN_MASK (0x1U) +#define PUF_INTEN_READYEN_SHIFT (0U) +/*! READYEN - Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status Register) + */ +#define PUF_INTEN_READYEN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_READYEN_SHIFT)) & PUF_INTEN_READYEN_MASK) + +#define PUF_INTEN_SUCCESEN_MASK (0x2U) +#define PUF_INTEN_SUCCESEN_SHIFT (1U) +/*! SUCCESEN - Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status Register) + */ +#define PUF_INTEN_SUCCESEN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_SUCCESEN_SHIFT)) & PUF_INTEN_SUCCESEN_MASK) + +#define PUF_INTEN_ERROREN_MASK (0x4U) +#define PUF_INTEN_ERROREN_SHIFT (2U) +/*! ERROREN - Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status Register) + */ +#define PUF_INTEN_ERROREN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_ERROREN_SHIFT)) & PUF_INTEN_ERROREN_MASK) + +#define PUF_INTEN_KEYINREQEN_MASK (0x10U) +#define PUF_INTEN_KEYINREQEN_SHIFT (4U) +/*! KEYINREQEN - Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status Register) + */ +#define PUF_INTEN_KEYINREQEN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_KEYINREQEN_SHIFT)) & PUF_INTEN_KEYINREQEN_MASK) + +#define PUF_INTEN_KEYOUTAVAILEN_MASK (0x20U) +#define PUF_INTEN_KEYOUTAVAILEN_SHIFT (5U) +/*! KEYOUTAVAILEN - Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status Register) + */ +#define PUF_INTEN_KEYOUTAVAILEN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_KEYOUTAVAILEN_SHIFT)) & PUF_INTEN_KEYOUTAVAILEN_MASK) + +#define PUF_INTEN_CODEINREQEN_MASK (0x40U) +#define PUF_INTEN_CODEINREQEN_SHIFT (6U) +/*! CODEINREQEN - Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status Register) + */ +#define PUF_INTEN_CODEINREQEN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_CODEINREQEN_SHIFT)) & PUF_INTEN_CODEINREQEN_MASK) + +#define PUF_INTEN_CODEOUTAVAILEN_MASK (0x80U) +#define PUF_INTEN_CODEOUTAVAILEN_SHIFT (7U) +/*! CODEOUTAVAILEN - Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status Register) + */ +#define PUF_INTEN_CODEOUTAVAILEN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_CODEOUTAVAILEN_SHIFT)) & PUF_INTEN_CODEOUTAVAILEN_MASK) +/*! @} */ + +/*! @name INTSTAT - PUF interrupt status */ +/*! @{ */ + +#define PUF_INTSTAT_READY_MASK (0x1U) +#define PUF_INTSTAT_READY_SHIFT (0U) +/*! READY - Triggers on falling edge of busy, write 1 to clear + */ +#define PUF_INTSTAT_READY(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_READY_SHIFT)) & PUF_INTSTAT_READY_MASK) + +#define PUF_INTSTAT_SUCCESS_MASK (0x2U) +#define PUF_INTSTAT_SUCCESS_SHIFT (1U) +/*! SUCCESS - Level sensitive interrupt, cleared when interrupt source clears + */ +#define PUF_INTSTAT_SUCCESS(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_SUCCESS_SHIFT)) & PUF_INTSTAT_SUCCESS_MASK) + +#define PUF_INTSTAT_ERROR_MASK (0x4U) +#define PUF_INTSTAT_ERROR_SHIFT (2U) +/*! ERROR - Level sensitive interrupt, cleared when interrupt source clears + */ +#define PUF_INTSTAT_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_ERROR_SHIFT)) & PUF_INTSTAT_ERROR_MASK) + +#define PUF_INTSTAT_KEYINREQ_MASK (0x10U) +#define PUF_INTSTAT_KEYINREQ_SHIFT (4U) +/*! KEYINREQ - Level sensitive interrupt, cleared when interrupt source clears + */ +#define PUF_INTSTAT_KEYINREQ(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_KEYINREQ_SHIFT)) & PUF_INTSTAT_KEYINREQ_MASK) + +#define PUF_INTSTAT_KEYOUTAVAIL_MASK (0x20U) +#define PUF_INTSTAT_KEYOUTAVAIL_SHIFT (5U) +/*! KEYOUTAVAIL - Level sensitive interrupt, cleared when interrupt source clears + */ +#define PUF_INTSTAT_KEYOUTAVAIL(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_KEYOUTAVAIL_SHIFT)) & PUF_INTSTAT_KEYOUTAVAIL_MASK) + +#define PUF_INTSTAT_CODEINREQ_MASK (0x40U) +#define PUF_INTSTAT_CODEINREQ_SHIFT (6U) +/*! CODEINREQ - Level sensitive interrupt, cleared when interrupt source clears + */ +#define PUF_INTSTAT_CODEINREQ(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_CODEINREQ_SHIFT)) & PUF_INTSTAT_CODEINREQ_MASK) + +#define PUF_INTSTAT_CODEOUTAVAIL_MASK (0x80U) +#define PUF_INTSTAT_CODEOUTAVAIL_SHIFT (7U) +/*! CODEOUTAVAIL - Level sensitive interrupt, cleared when interrupt source clears + */ +#define PUF_INTSTAT_CODEOUTAVAIL(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_CODEOUTAVAIL_SHIFT)) & PUF_INTSTAT_CODEOUTAVAIL_MASK) +/*! @} */ + +/*! @name CFG - PUF config register for block bits */ +/*! @{ */ + +#define PUF_CFG_BLOCKENROLL_SETKEY_MASK (0x1U) +#define PUF_CFG_BLOCKENROLL_SETKEY_SHIFT (0U) +/*! BLOCKENROLL_SETKEY - Block enroll operation. Write 1 to set, cleared on reset. + */ +#define PUF_CFG_BLOCKENROLL_SETKEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_CFG_BLOCKENROLL_SETKEY_SHIFT)) & PUF_CFG_BLOCKENROLL_SETKEY_MASK) + +#define PUF_CFG_BLOCKKEYOUTPUT_MASK (0x2U) +#define PUF_CFG_BLOCKKEYOUTPUT_SHIFT (1U) +/*! BLOCKKEYOUTPUT - Block set key operation. Write 1 to set, cleared on reset. + */ +#define PUF_CFG_BLOCKKEYOUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PUF_CFG_BLOCKKEYOUTPUT_SHIFT)) & PUF_CFG_BLOCKKEYOUTPUT_MASK) +/*! @} */ + +/*! @name KEYLOCK - Only reset in case of full IC reset */ +/*! @{ */ + +#define PUF_KEYLOCK_KEY0_MASK (0x3U) +#define PUF_KEYLOCK_KEY0_SHIFT (0U) +/*! KEY0 - "10:Write access to KEY0MASK, KEYENABLE.KEY0 and KEYRESET.KEY0 is allowed. 00, 01, + * 11:Write access to KEY0MASK, KEYENABLE.KEY0 and KEYRESET.KEY0 is NOT allowed. Important Note : Once + * this field is written with a value different from '10', its value can no longer be modified + * until un Power On Reset occurs." + */ +#define PUF_KEYLOCK_KEY0(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYLOCK_KEY0_SHIFT)) & PUF_KEYLOCK_KEY0_MASK) + +#define PUF_KEYLOCK_KEY1_MASK (0xCU) +#define PUF_KEYLOCK_KEY1_SHIFT (2U) +/*! KEY1 - "10:Write access to KEY1MASK, KEYENABLE.KEY1 and KEYRESET.KEY1 is allowed. 00, 01, + * 11:Write access to KEY1MASK, KEYENABLE.KEY1 and KEYRESET.KEY1 is NOT allowed. Important Note : Once + * this field is written with a value different from '10', its value can no longer be modified + * until un Power On Reset occurs." + */ +#define PUF_KEYLOCK_KEY1(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYLOCK_KEY1_SHIFT)) & PUF_KEYLOCK_KEY1_MASK) + +#define PUF_KEYLOCK_KEY2_MASK (0x30U) +#define PUF_KEYLOCK_KEY2_SHIFT (4U) +/*! KEY2 - "10:Write access to KEY2MASK, KEYENABLE.KEY2 and KEYRESET.KEY2 is allowed. 00, 01, + * 11:Write access to KEY2MASK, KEYENABLE.KEY2 and KEYRESET.KEY2 is NOT allowed. Important Note : Once + * this field is written with a value different from '10', its value can no longer be modified + * until un Power On Reset occurs." + */ +#define PUF_KEYLOCK_KEY2(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYLOCK_KEY2_SHIFT)) & PUF_KEYLOCK_KEY2_MASK) + +#define PUF_KEYLOCK_KEY3_MASK (0xC0U) +#define PUF_KEYLOCK_KEY3_SHIFT (6U) +/*! KEY3 - "10:Write access to KEY3MASK, KEYENABLE.KEY3 and KEYRESET.KEY3 is allowed. 00, 01, + * 11:Write access to KEY3MASK, KEYENABLE.KEY3 and KEYRESET.KEY3 is NOT allowed. Important Note : Once + * this field is written with a value different from '10', its value can no longer be modified + * until un Power On Reset occurs." + */ +#define PUF_KEYLOCK_KEY3(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYLOCK_KEY3_SHIFT)) & PUF_KEYLOCK_KEY3_MASK) +/*! @} */ + +/*! @name KEYENABLE - */ +/*! @{ */ + +#define PUF_KEYENABLE_KEY0_MASK (0x3U) +#define PUF_KEYENABLE_KEY0_SHIFT (0U) +/*! KEY0 - "10: Data coming out from PUF Index 0 interface are shifted in KEY0 register. 00, 01, 11 + * : Data coming out from PUF Index 0 interface are NOT shifted in KEY0 register." + */ +#define PUF_KEYENABLE_KEY0(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYENABLE_KEY0_SHIFT)) & PUF_KEYENABLE_KEY0_MASK) + +#define PUF_KEYENABLE_KEY1_MASK (0xCU) +#define PUF_KEYENABLE_KEY1_SHIFT (2U) +/*! KEY1 - "10: Data coming out from PUF Index 0 interface are shifted in KEY1 register. 00, 01, 11 + * : Data coming out from PUF Index 0 interface are NOT shifted in KEY1 register." + */ +#define PUF_KEYENABLE_KEY1(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYENABLE_KEY1_SHIFT)) & PUF_KEYENABLE_KEY1_MASK) + +#define PUF_KEYENABLE_KEY2_MASK (0x30U) +#define PUF_KEYENABLE_KEY2_SHIFT (4U) +/*! KEY2 - "10: Data coming out from PUF Index 0 interface are shifted in KEY2 register. 00, 01, 11 + * : Data coming out from PUF Index 0 interface are NOT shifted in KEY2 register." + */ +#define PUF_KEYENABLE_KEY2(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYENABLE_KEY2_SHIFT)) & PUF_KEYENABLE_KEY2_MASK) + +#define PUF_KEYENABLE_KEY3_MASK (0xC0U) +#define PUF_KEYENABLE_KEY3_SHIFT (6U) +/*! KEY3 - "10: Data coming out from PUF Index 0 interface are shifted in KEY3 register. 00, 01, 11 + * : Data coming out from PUF Index 0 interface are NOT shifted in KEY3 register." + */ +#define PUF_KEYENABLE_KEY3(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYENABLE_KEY3_SHIFT)) & PUF_KEYENABLE_KEY3_MASK) +/*! @} */ + +/*! @name KEYRESET - Reinitialize Keys shift registers counters */ +/*! @{ */ + +#define PUF_KEYRESET_KEY0_MASK (0x3U) +#define PUF_KEYRESET_KEY0_SHIFT (0U) +/*! KEY0 - 10: Reset KEY0 shift register. Self clearing. Must be done before loading any new key. + */ +#define PUF_KEYRESET_KEY0(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYRESET_KEY0_SHIFT)) & PUF_KEYRESET_KEY0_MASK) + +#define PUF_KEYRESET_KEY1_MASK (0xCU) +#define PUF_KEYRESET_KEY1_SHIFT (2U) +/*! KEY1 - 10: Reset KEY1 shift register. Self clearing. Must be done before loading any new key. + */ +#define PUF_KEYRESET_KEY1(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYRESET_KEY1_SHIFT)) & PUF_KEYRESET_KEY1_MASK) + +#define PUF_KEYRESET_KEY2_MASK (0x30U) +#define PUF_KEYRESET_KEY2_SHIFT (4U) +/*! KEY2 - 10: Reset KEY2 shift register. Self clearing. Must be done before loading any new key. + */ +#define PUF_KEYRESET_KEY2(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYRESET_KEY2_SHIFT)) & PUF_KEYRESET_KEY2_MASK) + +#define PUF_KEYRESET_KEY3_MASK (0xC0U) +#define PUF_KEYRESET_KEY3_SHIFT (6U) +/*! KEY3 - 10: Reset KEY3 shift register. Self clearing. Must be done before loading any new key. + */ +#define PUF_KEYRESET_KEY3(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYRESET_KEY3_SHIFT)) & PUF_KEYRESET_KEY3_MASK) +/*! @} */ + +/*! @name IDXBLK - */ +/*! @{ */ + +#define PUF_IDXBLK_IDX0_MASK (0x3U) +#define PUF_IDXBLK_IDX0_SHIFT (0U) +/*! IDX0 - Use to block PUF index 0 + */ +#define PUF_IDXBLK_IDX0(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDX0_SHIFT)) & PUF_IDXBLK_IDX0_MASK) + +#define PUF_IDXBLK_IDX1_MASK (0xCU) +#define PUF_IDXBLK_IDX1_SHIFT (2U) +/*! IDX1 - Use to block PUF index 1 + */ +#define PUF_IDXBLK_IDX1(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDX1_SHIFT)) & PUF_IDXBLK_IDX1_MASK) + +#define PUF_IDXBLK_IDX2_MASK (0x30U) +#define PUF_IDXBLK_IDX2_SHIFT (4U) +/*! IDX2 - Use to block PUF index 2 + */ +#define PUF_IDXBLK_IDX2(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDX2_SHIFT)) & PUF_IDXBLK_IDX2_MASK) + +#define PUF_IDXBLK_IDX3_MASK (0xC0U) +#define PUF_IDXBLK_IDX3_SHIFT (6U) +/*! IDX3 - Use to block PUF index 3 + */ +#define PUF_IDXBLK_IDX3(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDX3_SHIFT)) & PUF_IDXBLK_IDX3_MASK) + +#define PUF_IDXBLK_IDX4_MASK (0x300U) +#define PUF_IDXBLK_IDX4_SHIFT (8U) +/*! IDX4 - Use to block PUF index 4 + */ +#define PUF_IDXBLK_IDX4(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDX4_SHIFT)) & PUF_IDXBLK_IDX4_MASK) + +#define PUF_IDXBLK_IDX5_MASK (0xC00U) +#define PUF_IDXBLK_IDX5_SHIFT (10U) +/*! IDX5 - Use to block PUF index 5 + */ +#define PUF_IDXBLK_IDX5(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDX5_SHIFT)) & PUF_IDXBLK_IDX5_MASK) + +#define PUF_IDXBLK_IDX6_MASK (0x3000U) +#define PUF_IDXBLK_IDX6_SHIFT (12U) +/*! IDX6 - Use to block PUF index 6 + */ +#define PUF_IDXBLK_IDX6(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDX6_SHIFT)) & PUF_IDXBLK_IDX6_MASK) + +#define PUF_IDXBLK_IDX7_MASK (0xC000U) +#define PUF_IDXBLK_IDX7_SHIFT (14U) +/*! IDX7 - Use to block PUF index 7 + */ +#define PUF_IDXBLK_IDX7(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDX7_SHIFT)) & PUF_IDXBLK_IDX7_MASK) + +#define PUF_IDXBLK_IDX8_MASK (0x30000U) +#define PUF_IDXBLK_IDX8_SHIFT (16U) +/*! IDX8 - Use to block PUF index 8 + */ +#define PUF_IDXBLK_IDX8(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDX8_SHIFT)) & PUF_IDXBLK_IDX8_MASK) + +#define PUF_IDXBLK_IDX9_MASK (0xC0000U) +#define PUF_IDXBLK_IDX9_SHIFT (18U) +/*! IDX9 - Use to block PUF index 9 + */ +#define PUF_IDXBLK_IDX9(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDX9_SHIFT)) & PUF_IDXBLK_IDX9_MASK) + +#define PUF_IDXBLK_IDX10_MASK (0x300000U) +#define PUF_IDXBLK_IDX10_SHIFT (20U) +/*! IDX10 - Use to block PUF index 10 + */ +#define PUF_IDXBLK_IDX10(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDX10_SHIFT)) & PUF_IDXBLK_IDX10_MASK) + +#define PUF_IDXBLK_IDX11_MASK (0xC00000U) +#define PUF_IDXBLK_IDX11_SHIFT (22U) +/*! IDX11 - Use to block PUF index 11 + */ +#define PUF_IDXBLK_IDX11(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDX11_SHIFT)) & PUF_IDXBLK_IDX11_MASK) + +#define PUF_IDXBLK_IDX12_MASK (0x3000000U) +#define PUF_IDXBLK_IDX12_SHIFT (24U) +/*! IDX12 - Use to block PUF index 12 + */ +#define PUF_IDXBLK_IDX12(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDX12_SHIFT)) & PUF_IDXBLK_IDX12_MASK) + +#define PUF_IDXBLK_IDX13_MASK (0xC000000U) +#define PUF_IDXBLK_IDX13_SHIFT (26U) +/*! IDX13 - Use to block PUF index 13 + */ +#define PUF_IDXBLK_IDX13(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDX13_SHIFT)) & PUF_IDXBLK_IDX13_MASK) + +#define PUF_IDXBLK_IDX14_MASK (0x30000000U) +#define PUF_IDXBLK_IDX14_SHIFT (28U) +/*! IDX14 - Use to block PUF index 14 + */ +#define PUF_IDXBLK_IDX14(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDX14_SHIFT)) & PUF_IDXBLK_IDX14_MASK) + +#define PUF_IDXBLK_IDX15_MASK (0xC0000000U) +#define PUF_IDXBLK_IDX15_SHIFT (30U) +/*! IDX15 - Use to block PUF index 15 + */ +#define PUF_IDXBLK_IDX15(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDX15_SHIFT)) & PUF_IDXBLK_IDX15_MASK) +/*! @} */ + +/*! @name IDXBLK_DP - */ +/*! @{ */ + +#define PUF_IDXBLK_DP_IDX0_MASK (0x3U) +#define PUF_IDXBLK_DP_IDX0_SHIFT (0U) +/*! IDX0 - Use to block PUF index 0 + */ +#define PUF_IDXBLK_DP_IDX0(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDX0_SHIFT)) & PUF_IDXBLK_DP_IDX0_MASK) + +#define PUF_IDXBLK_DP_IDX1_MASK (0xCU) +#define PUF_IDXBLK_DP_IDX1_SHIFT (2U) +/*! IDX1 - Use to block PUF index 1 + */ +#define PUF_IDXBLK_DP_IDX1(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDX1_SHIFT)) & PUF_IDXBLK_DP_IDX1_MASK) + +#define PUF_IDXBLK_DP_IDX2_MASK (0x30U) +#define PUF_IDXBLK_DP_IDX2_SHIFT (4U) +/*! IDX2 - Use to block PUF index 2 + */ +#define PUF_IDXBLK_DP_IDX2(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDX2_SHIFT)) & PUF_IDXBLK_DP_IDX2_MASK) + +#define PUF_IDXBLK_DP_IDX3_MASK (0xC0U) +#define PUF_IDXBLK_DP_IDX3_SHIFT (6U) +/*! IDX3 - Use to block PUF index 3 + */ +#define PUF_IDXBLK_DP_IDX3(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDX3_SHIFT)) & PUF_IDXBLK_DP_IDX3_MASK) + +#define PUF_IDXBLK_DP_IDX4_MASK (0x300U) +#define PUF_IDXBLK_DP_IDX4_SHIFT (8U) +/*! IDX4 - Use to block PUF index 4 + */ +#define PUF_IDXBLK_DP_IDX4(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDX4_SHIFT)) & PUF_IDXBLK_DP_IDX4_MASK) + +#define PUF_IDXBLK_DP_IDX5_MASK (0xC00U) +#define PUF_IDXBLK_DP_IDX5_SHIFT (10U) +/*! IDX5 - Use to block PUF index 5 + */ +#define PUF_IDXBLK_DP_IDX5(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDX5_SHIFT)) & PUF_IDXBLK_DP_IDX5_MASK) + +#define PUF_IDXBLK_DP_IDX6_MASK (0x3000U) +#define PUF_IDXBLK_DP_IDX6_SHIFT (12U) +/*! IDX6 - Use to block PUF index 6 + */ +#define PUF_IDXBLK_DP_IDX6(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDX6_SHIFT)) & PUF_IDXBLK_DP_IDX6_MASK) + +#define PUF_IDXBLK_DP_IDX7_MASK (0xC000U) +#define PUF_IDXBLK_DP_IDX7_SHIFT (14U) +/*! IDX7 - Use to block PUF index 7 + */ +#define PUF_IDXBLK_DP_IDX7(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDX7_SHIFT)) & PUF_IDXBLK_DP_IDX7_MASK) + +#define PUF_IDXBLK_DP_IDX8_MASK (0x30000U) +#define PUF_IDXBLK_DP_IDX8_SHIFT (16U) +/*! IDX8 - Use to block PUF index 8 + */ +#define PUF_IDXBLK_DP_IDX8(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDX8_SHIFT)) & PUF_IDXBLK_DP_IDX8_MASK) + +#define PUF_IDXBLK_DP_IDX9_MASK (0xC0000U) +#define PUF_IDXBLK_DP_IDX9_SHIFT (18U) +/*! IDX9 - Use to block PUF index 9 + */ +#define PUF_IDXBLK_DP_IDX9(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDX9_SHIFT)) & PUF_IDXBLK_DP_IDX9_MASK) + +#define PUF_IDXBLK_DP_IDX10_MASK (0x300000U) +#define PUF_IDXBLK_DP_IDX10_SHIFT (20U) +/*! IDX10 - Use to block PUF index 10 + */ +#define PUF_IDXBLK_DP_IDX10(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDX10_SHIFT)) & PUF_IDXBLK_DP_IDX10_MASK) + +#define PUF_IDXBLK_DP_IDX11_MASK (0xC00000U) +#define PUF_IDXBLK_DP_IDX11_SHIFT (22U) +/*! IDX11 - Use to block PUF index 11 + */ +#define PUF_IDXBLK_DP_IDX11(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDX11_SHIFT)) & PUF_IDXBLK_DP_IDX11_MASK) + +#define PUF_IDXBLK_DP_IDX12_MASK (0x3000000U) +#define PUF_IDXBLK_DP_IDX12_SHIFT (24U) +/*! IDX12 - Use to block PUF index 12 + */ +#define PUF_IDXBLK_DP_IDX12(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDX12_SHIFT)) & PUF_IDXBLK_DP_IDX12_MASK) + +#define PUF_IDXBLK_DP_IDX13_MASK (0xC000000U) +#define PUF_IDXBLK_DP_IDX13_SHIFT (26U) +/*! IDX13 - Use to block PUF index 13 + */ +#define PUF_IDXBLK_DP_IDX13(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDX13_SHIFT)) & PUF_IDXBLK_DP_IDX13_MASK) + +#define PUF_IDXBLK_DP_IDX14_MASK (0x30000000U) +#define PUF_IDXBLK_DP_IDX14_SHIFT (28U) +/*! IDX14 - Use to block PUF index 14 + */ +#define PUF_IDXBLK_DP_IDX14(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDX14_SHIFT)) & PUF_IDXBLK_DP_IDX14_MASK) + +#define PUF_IDXBLK_DP_IDX15_MASK (0xC0000000U) +#define PUF_IDXBLK_DP_IDX15_SHIFT (30U) +/*! IDX15 - Use to block PUF index 15 + */ +#define PUF_IDXBLK_DP_IDX15(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDX15_SHIFT)) & PUF_IDXBLK_DP_IDX15_MASK) +/*! @} */ + +/*! @name KEYMASK - Only reset in case of full IC reset */ +/*! @{ */ + +#define PUF_KEYMASK_KEYMASK_MASK (0xFFFFFFFFU) +#define PUF_KEYMASK_KEYMASK_SHIFT (0U) +#define PUF_KEYMASK_KEYMASK(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYMASK_KEYMASK_SHIFT)) & PUF_KEYMASK_KEYMASK_MASK) +/*! @} */ + +/* The count of PUF_KEYMASK */ +#define PUF_KEYMASK_COUNT (4U) + +/*! @name IDXBLK_STATUS - Index block status */ +/*! @{ */ + +#define PUF_IDXBLK_STATUS_IDX0_MASK (0x3U) +#define PUF_IDXBLK_STATUS_IDX0_SHIFT (0U) +/*! IDX0 - Status block index 0 + */ +#define PUF_IDXBLK_STATUS_IDX0(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDX0_SHIFT)) & PUF_IDXBLK_STATUS_IDX0_MASK) + +#define PUF_IDXBLK_STATUS_IDX1_MASK (0xCU) +#define PUF_IDXBLK_STATUS_IDX1_SHIFT (2U) +/*! IDX1 - Status block index 1 + */ +#define PUF_IDXBLK_STATUS_IDX1(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDX1_SHIFT)) & PUF_IDXBLK_STATUS_IDX1_MASK) + +#define PUF_IDXBLK_STATUS_IDX2_MASK (0x30U) +#define PUF_IDXBLK_STATUS_IDX2_SHIFT (4U) +/*! IDX2 - Status block index 2 + */ +#define PUF_IDXBLK_STATUS_IDX2(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDX2_SHIFT)) & PUF_IDXBLK_STATUS_IDX2_MASK) + +#define PUF_IDXBLK_STATUS_IDX3_MASK (0xC0U) +#define PUF_IDXBLK_STATUS_IDX3_SHIFT (6U) +/*! IDX3 - Status block index 3 + */ +#define PUF_IDXBLK_STATUS_IDX3(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDX3_SHIFT)) & PUF_IDXBLK_STATUS_IDX3_MASK) + +#define PUF_IDXBLK_STATUS_IDX4_MASK (0x300U) +#define PUF_IDXBLK_STATUS_IDX4_SHIFT (8U) +/*! IDX4 - Status block index 4 + */ +#define PUF_IDXBLK_STATUS_IDX4(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDX4_SHIFT)) & PUF_IDXBLK_STATUS_IDX4_MASK) + +#define PUF_IDXBLK_STATUS_IDX5_MASK (0xC00U) +#define PUF_IDXBLK_STATUS_IDX5_SHIFT (10U) +/*! IDX5 - Status block index 5 + */ +#define PUF_IDXBLK_STATUS_IDX5(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDX5_SHIFT)) & PUF_IDXBLK_STATUS_IDX5_MASK) + +#define PUF_IDXBLK_STATUS_IDX6_MASK (0x3000U) +#define PUF_IDXBLK_STATUS_IDX6_SHIFT (12U) +/*! IDX6 - Status block index 6 + */ +#define PUF_IDXBLK_STATUS_IDX6(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDX6_SHIFT)) & PUF_IDXBLK_STATUS_IDX6_MASK) + +#define PUF_IDXBLK_STATUS_IDX7_MASK (0xC000U) +#define PUF_IDXBLK_STATUS_IDX7_SHIFT (14U) +/*! IDX7 - Status block index 7 + */ +#define PUF_IDXBLK_STATUS_IDX7(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDX7_SHIFT)) & PUF_IDXBLK_STATUS_IDX7_MASK) + +#define PUF_IDXBLK_STATUS_IDX8_MASK (0x30000U) +#define PUF_IDXBLK_STATUS_IDX8_SHIFT (16U) +/*! IDX8 - Status block index 8 + */ +#define PUF_IDXBLK_STATUS_IDX8(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDX8_SHIFT)) & PUF_IDXBLK_STATUS_IDX8_MASK) + +#define PUF_IDXBLK_STATUS_IDX9_MASK (0xC0000U) +#define PUF_IDXBLK_STATUS_IDX9_SHIFT (18U) +/*! IDX9 - Status block index 9 + */ +#define PUF_IDXBLK_STATUS_IDX9(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDX9_SHIFT)) & PUF_IDXBLK_STATUS_IDX9_MASK) + +#define PUF_IDXBLK_STATUS_IDX10_MASK (0x300000U) +#define PUF_IDXBLK_STATUS_IDX10_SHIFT (20U) +/*! IDX10 - Status block index 10 + */ +#define PUF_IDXBLK_STATUS_IDX10(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDX10_SHIFT)) & PUF_IDXBLK_STATUS_IDX10_MASK) + +#define PUF_IDXBLK_STATUS_IDX11_MASK (0xC00000U) +#define PUF_IDXBLK_STATUS_IDX11_SHIFT (22U) +/*! IDX11 - Status block index 11 + */ +#define PUF_IDXBLK_STATUS_IDX11(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDX11_SHIFT)) & PUF_IDXBLK_STATUS_IDX11_MASK) + +#define PUF_IDXBLK_STATUS_IDX12_MASK (0x3000000U) +#define PUF_IDXBLK_STATUS_IDX12_SHIFT (24U) +/*! IDX12 - Status block index 12 + */ +#define PUF_IDXBLK_STATUS_IDX12(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDX12_SHIFT)) & PUF_IDXBLK_STATUS_IDX12_MASK) + +#define PUF_IDXBLK_STATUS_IDX13_MASK (0xC000000U) +#define PUF_IDXBLK_STATUS_IDX13_SHIFT (26U) +/*! IDX13 - Status block index 13 + */ +#define PUF_IDXBLK_STATUS_IDX13(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDX13_SHIFT)) & PUF_IDXBLK_STATUS_IDX13_MASK) + +#define PUF_IDXBLK_STATUS_IDX14_MASK (0x30000000U) +#define PUF_IDXBLK_STATUS_IDX14_SHIFT (28U) +/*! IDX14 - Status block index 14 + */ +#define PUF_IDXBLK_STATUS_IDX14(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDX14_SHIFT)) & PUF_IDXBLK_STATUS_IDX14_MASK) + +#define PUF_IDXBLK_STATUS_IDX15_MASK (0xC0000000U) +#define PUF_IDXBLK_STATUS_IDX15_SHIFT (30U) +/*! IDX15 - Status block index 15 + */ +#define PUF_IDXBLK_STATUS_IDX15(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDX15_SHIFT)) & PUF_IDXBLK_STATUS_IDX15_MASK) +/*! @} */ + +/*! @name SHIFT_STATUS - */ +/*! @{ */ + +#define PUF_SHIFT_STATUS_KEY0_MASK (0xFU) +#define PUF_SHIFT_STATUS_KEY0_SHIFT (0U) +/*! KEY0 - Index counter from key 0 shift register + */ +#define PUF_SHIFT_STATUS_KEY0(x) (((uint32_t)(((uint32_t)(x)) << PUF_SHIFT_STATUS_KEY0_SHIFT)) & PUF_SHIFT_STATUS_KEY0_MASK) + +#define PUF_SHIFT_STATUS_KEY1_MASK (0xF0U) +#define PUF_SHIFT_STATUS_KEY1_SHIFT (4U) +/*! KEY1 - Index counter from key 1 shift register + */ +#define PUF_SHIFT_STATUS_KEY1(x) (((uint32_t)(((uint32_t)(x)) << PUF_SHIFT_STATUS_KEY1_SHIFT)) & PUF_SHIFT_STATUS_KEY1_MASK) + +#define PUF_SHIFT_STATUS_KEY2_MASK (0xF00U) +#define PUF_SHIFT_STATUS_KEY2_SHIFT (8U) +/*! KEY2 - Index counter from key 2 shift register + */ +#define PUF_SHIFT_STATUS_KEY2(x) (((uint32_t)(((uint32_t)(x)) << PUF_SHIFT_STATUS_KEY2_SHIFT)) & PUF_SHIFT_STATUS_KEY2_MASK) + +#define PUF_SHIFT_STATUS_KEY3_MASK (0xF000U) +#define PUF_SHIFT_STATUS_KEY3_SHIFT (12U) +/*! KEY3 - Index counter from key 3 shift register + */ +#define PUF_SHIFT_STATUS_KEY3(x) (((uint32_t)(((uint32_t)(x)) << PUF_SHIFT_STATUS_KEY3_SHIFT)) & PUF_SHIFT_STATUS_KEY3_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group PUF_Register_Masks */ + + +/* PUF - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral PUF base address */ + #define PUF_BASE (0x5003B000u) + /** Peripheral PUF base address */ + #define PUF_BASE_NS (0x4003B000u) + /** Peripheral PUF base pointer */ + #define PUF ((PUF_Type *)PUF_BASE) + /** Peripheral PUF base pointer */ + #define PUF_NS ((PUF_Type *)PUF_BASE_NS) + /** Array initializer of PUF peripheral base addresses */ + #define PUF_BASE_ADDRS { PUF_BASE } + /** Array initializer of PUF peripheral base pointers */ + #define PUF_BASE_PTRS { PUF } + /** Array initializer of PUF peripheral base addresses */ + #define PUF_BASE_ADDRS_NS { PUF_BASE_NS } + /** Array initializer of PUF peripheral base pointers */ + #define PUF_BASE_PTRS_NS { PUF_NS } +#else + /** Peripheral PUF base address */ + #define PUF_BASE (0x4003B000u) + /** Peripheral PUF base pointer */ + #define PUF ((PUF_Type *)PUF_BASE) + /** Array initializer of PUF peripheral base addresses */ + #define PUF_BASE_ADDRS { PUF_BASE } + /** Array initializer of PUF peripheral base pointers */ + #define PUF_BASE_PTRS { PUF } +#endif +/** Interrupt vectors for the PUF peripheral type */ +#define PUF_IRQS { PUF_IRQn } + +/*! + * @} + */ /* end of group PUF_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- PUF_SRAM_CTRL Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PUF_SRAM_CTRL_Peripheral_Access_Layer PUF_SRAM_CTRL Peripheral Access Layer + * @{ + */ + +/** PUF_SRAM_CTRL - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[768]; + __IO uint32_t CFG; /**< Configuration Register, offset: 0x300 */ + __I uint32_t STATUS; /**< Status Register, offset: 0x304 */ + uint8_t RESERVED_1[208]; + __O uint32_t INT_CLR_ENABLE; /**< Interrupt Enable Clear Register, offset: 0x3D8 */ + __O uint32_t INT_SET_ENABLE; /**< Interrupt Enable Set Register, offset: 0x3DC */ + __I uint32_t INT_STATUS; /**< Interrupt Status Register, offset: 0x3E0 */ + __I uint32_t INT_ENABLE; /**< Interrupt Enable Register, offset: 0x3E4 */ + __O uint32_t INT_CLR_STATUS; /**< Interrupt Status Clear Register, offset: 0x3E8 */ + __O uint32_t INT_SET_STATUS; /**< Interrupt Status set, offset: 0x3EC */ +} PUF_SRAM_CTRL_Type; + +/* ---------------------------------------------------------------------------- + -- PUF_SRAM_CTRL Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PUF_SRAM_CTRL_Register_Masks PUF_SRAM_CTRL Register Masks + * @{ + */ + +/*! @name CFG - Configuration Register */ +/*! @{ */ + +#define PUF_SRAM_CTRL_CFG_ENABLE_MASK (0x1U) +#define PUF_SRAM_CTRL_CFG_ENABLE_SHIFT (0U) +/*! enable - PUF SRAM Controller activation + */ +#define PUF_SRAM_CTRL_CFG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_CTRL_CFG_ENABLE_SHIFT)) & PUF_SRAM_CTRL_CFG_ENABLE_MASK) + +#define PUF_SRAM_CTRL_CFG_CKGATING_MASK (0x4U) +#define PUF_SRAM_CTRL_CFG_CKGATING_SHIFT (2U) +/*! ckgating - PUF SRAM Clock Gating control + */ +#define PUF_SRAM_CTRL_CFG_CKGATING(x) (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_CTRL_CFG_CKGATING_SHIFT)) & PUF_SRAM_CTRL_CFG_CKGATING_MASK) +/*! @} */ + +/*! @name STATUS - Status Register */ +/*! @{ */ + +#define PUF_SRAM_CTRL_STATUS_READY_MASK (0x1U) +#define PUF_SRAM_CTRL_STATUS_READY_SHIFT (0U) +/*! READY - PUF SRAM Controller State + */ +#define PUF_SRAM_CTRL_STATUS_READY(x) (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_CTRL_STATUS_READY_SHIFT)) & PUF_SRAM_CTRL_STATUS_READY_MASK) +/*! @} */ + +/*! @name INT_CLR_ENABLE - Interrupt Enable Clear Register */ +/*! @{ */ + +#define PUF_SRAM_CTRL_INT_CLR_ENABLE_READY_MASK (0x1U) +#define PUF_SRAM_CTRL_INT_CLR_ENABLE_READY_SHIFT (0U) +/*! READY - READY Interrupt Enable clear + */ +#define PUF_SRAM_CTRL_INT_CLR_ENABLE_READY(x) (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_CTRL_INT_CLR_ENABLE_READY_SHIFT)) & PUF_SRAM_CTRL_INT_CLR_ENABLE_READY_MASK) + +#define PUF_SRAM_CTRL_INT_CLR_ENABLE_APB_ERR_MASK (0x2U) +#define PUF_SRAM_CTRL_INT_CLR_ENABLE_APB_ERR_SHIFT (1U) +/*! APB_ERR - APB_ERR Interrupt Enable clear + */ +#define PUF_SRAM_CTRL_INT_CLR_ENABLE_APB_ERR(x) (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_CTRL_INT_CLR_ENABLE_APB_ERR_SHIFT)) & PUF_SRAM_CTRL_INT_CLR_ENABLE_APB_ERR_MASK) +/*! @} */ + +/*! @name INT_SET_ENABLE - Interrupt Enable Set Register */ +/*! @{ */ + +#define PUF_SRAM_CTRL_INT_SET_ENABLE_READY_MASK (0x1U) +#define PUF_SRAM_CTRL_INT_SET_ENABLE_READY_SHIFT (0U) +/*! READY - READY Interrupt Enable set + */ +#define PUF_SRAM_CTRL_INT_SET_ENABLE_READY(x) (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_CTRL_INT_SET_ENABLE_READY_SHIFT)) & PUF_SRAM_CTRL_INT_SET_ENABLE_READY_MASK) + +#define PUF_SRAM_CTRL_INT_SET_ENABLE_APB_ERR_MASK (0x2U) +#define PUF_SRAM_CTRL_INT_SET_ENABLE_APB_ERR_SHIFT (1U) +/*! APB_ERR - APB_ERR Interrupt Enable set + */ +#define PUF_SRAM_CTRL_INT_SET_ENABLE_APB_ERR(x) (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_CTRL_INT_SET_ENABLE_APB_ERR_SHIFT)) & PUF_SRAM_CTRL_INT_SET_ENABLE_APB_ERR_MASK) +/*! @} */ + +/*! @name INT_STATUS - Interrupt Status Register */ +/*! @{ */ + +#define PUF_SRAM_CTRL_INT_STATUS_READY_MASK (0x1U) +#define PUF_SRAM_CTRL_INT_STATUS_READY_SHIFT (0U) +/*! READY - READY Interrupt Status + */ +#define PUF_SRAM_CTRL_INT_STATUS_READY(x) (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_CTRL_INT_STATUS_READY_SHIFT)) & PUF_SRAM_CTRL_INT_STATUS_READY_MASK) + +#define PUF_SRAM_CTRL_INT_STATUS_APB_ERR_MASK (0x2U) +#define PUF_SRAM_CTRL_INT_STATUS_APB_ERR_SHIFT (1U) +/*! APB_ERR - APB_ERR Interrupt Status + */ +#define PUF_SRAM_CTRL_INT_STATUS_APB_ERR(x) (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_CTRL_INT_STATUS_APB_ERR_SHIFT)) & PUF_SRAM_CTRL_INT_STATUS_APB_ERR_MASK) +/*! @} */ + +/*! @name INT_ENABLE - Interrupt Enable Register */ +/*! @{ */ + +#define PUF_SRAM_CTRL_INT_ENABLE_READY_MASK (0x1U) +#define PUF_SRAM_CTRL_INT_ENABLE_READY_SHIFT (0U) +/*! READY - READY Interrupt Enable + */ +#define PUF_SRAM_CTRL_INT_ENABLE_READY(x) (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_CTRL_INT_ENABLE_READY_SHIFT)) & PUF_SRAM_CTRL_INT_ENABLE_READY_MASK) + +#define PUF_SRAM_CTRL_INT_ENABLE_APB_ERR_MASK (0x2U) +#define PUF_SRAM_CTRL_INT_ENABLE_APB_ERR_SHIFT (1U) +/*! APB_ERR - APB_ERR Interrupt Enable + */ +#define PUF_SRAM_CTRL_INT_ENABLE_APB_ERR(x) (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_CTRL_INT_ENABLE_APB_ERR_SHIFT)) & PUF_SRAM_CTRL_INT_ENABLE_APB_ERR_MASK) +/*! @} */ + +/*! @name INT_CLR_STATUS - Interrupt Status Clear Register */ +/*! @{ */ + +#define PUF_SRAM_CTRL_INT_CLR_STATUS_READY_MASK (0x1U) +#define PUF_SRAM_CTRL_INT_CLR_STATUS_READY_SHIFT (0U) +/*! READY - READY Interrupt Status clear + */ +#define PUF_SRAM_CTRL_INT_CLR_STATUS_READY(x) (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_CTRL_INT_CLR_STATUS_READY_SHIFT)) & PUF_SRAM_CTRL_INT_CLR_STATUS_READY_MASK) + +#define PUF_SRAM_CTRL_INT_CLR_STATUS_APB_ERR_MASK (0x2U) +#define PUF_SRAM_CTRL_INT_CLR_STATUS_APB_ERR_SHIFT (1U) +/*! APB_ERR - APB_ERR Interrupt Status Clear + */ +#define PUF_SRAM_CTRL_INT_CLR_STATUS_APB_ERR(x) (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_CTRL_INT_CLR_STATUS_APB_ERR_SHIFT)) & PUF_SRAM_CTRL_INT_CLR_STATUS_APB_ERR_MASK) +/*! @} */ + +/*! @name INT_SET_STATUS - Interrupt Status set */ +/*! @{ */ + +#define PUF_SRAM_CTRL_INT_SET_STATUS_READY_MASK (0x1U) +#define PUF_SRAM_CTRL_INT_SET_STATUS_READY_SHIFT (0U) +/*! READY - READY Interrupt Status set + */ +#define PUF_SRAM_CTRL_INT_SET_STATUS_READY(x) (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_CTRL_INT_SET_STATUS_READY_SHIFT)) & PUF_SRAM_CTRL_INT_SET_STATUS_READY_MASK) + +#define PUF_SRAM_CTRL_INT_SET_STATUS_APB_ERR_MASK (0x2U) +#define PUF_SRAM_CTRL_INT_SET_STATUS_APB_ERR_SHIFT (1U) +/*! APB_ERR - APB_ERR Interrupt Status Set + */ +#define PUF_SRAM_CTRL_INT_SET_STATUS_APB_ERR(x) (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_CTRL_INT_SET_STATUS_APB_ERR_SHIFT)) & PUF_SRAM_CTRL_INT_SET_STATUS_APB_ERR_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group PUF_SRAM_CTRL_Register_Masks */ + + +/* PUF_SRAM_CTRL - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral PUF_SRAM_CTRL base address */ + #define PUF_SRAM_CTRL_BASE (0x5003B000u) + /** Peripheral PUF_SRAM_CTRL base address */ + #define PUF_SRAM_CTRL_BASE_NS (0x4003B000u) + /** Peripheral PUF_SRAM_CTRL base pointer */ + #define PUF_SRAM_CTRL ((PUF_SRAM_CTRL_Type *)PUF_SRAM_CTRL_BASE) + /** Peripheral PUF_SRAM_CTRL base pointer */ + #define PUF_SRAM_CTRL_NS ((PUF_SRAM_CTRL_Type *)PUF_SRAM_CTRL_BASE_NS) + /** Array initializer of PUF_SRAM_CTRL peripheral base addresses */ + #define PUF_SRAM_CTRL_BASE_ADDRS { PUF_SRAM_CTRL_BASE } + /** Array initializer of PUF_SRAM_CTRL peripheral base pointers */ + #define PUF_SRAM_CTRL_BASE_PTRS { PUF_SRAM_CTRL } + /** Array initializer of PUF_SRAM_CTRL peripheral base addresses */ + #define PUF_SRAM_CTRL_BASE_ADDRS_NS { PUF_SRAM_CTRL_BASE_NS } + /** Array initializer of PUF_SRAM_CTRL peripheral base pointers */ + #define PUF_SRAM_CTRL_BASE_PTRS_NS { PUF_SRAM_CTRL_NS } +#else + /** Peripheral PUF_SRAM_CTRL base address */ + #define PUF_SRAM_CTRL_BASE (0x4003B000u) + /** Peripheral PUF_SRAM_CTRL base pointer */ + #define PUF_SRAM_CTRL ((PUF_SRAM_CTRL_Type *)PUF_SRAM_CTRL_BASE) + /** Array initializer of PUF_SRAM_CTRL peripheral base addresses */ + #define PUF_SRAM_CTRL_BASE_ADDRS { PUF_SRAM_CTRL_BASE } + /** Array initializer of PUF_SRAM_CTRL peripheral base pointers */ + #define PUF_SRAM_CTRL_BASE_PTRS { PUF_SRAM_CTRL } +#endif + +/*! + * @} + */ /* end of group PUF_SRAM_CTRL_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- RNG Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup RNG_Peripheral_Access_Layer RNG Peripheral Access Layer + * @{ + */ + +/** RNG - Register Layout Typedef */ +typedef struct { + __I uint32_t RANDOM_NUMBER; /**< This register contains a random 32 bit number which is computed on demand, at each time it is read, offset: 0x0 */ + __IO uint32_t ENCRYPTED_NUMBER; /**< This register contains a random 32 bit number which is pre-computed, offset: 0x4 */ + __I uint32_t COUNTER_VAL; /**< , offset: 0x8 */ + __IO uint32_t COUNTER_CFG; /**< , offset: 0xC */ + __IO uint32_t ONLINE_TEST_CFG; /**< , offset: 0x10 */ + __I uint32_t ONLINE_TEST_VAL; /**< , offset: 0x14 */ + __IO uint32_t ENTROPY_INJECT; /**< , offset: 0x18 */ + __IO uint32_t MISC_CFG; /**< , offset: 0x1C */ + uint8_t RESERVED_0[4052]; + __IO uint32_t POWERDOWN; /**< Powerdown mode (standard but certainly useless here), offset: 0xFF4 */ + uint8_t RESERVED_1[4]; + __I uint32_t MODULEID; /**< IP identifier, offset: 0xFFC */ +} RNG_Type; + +/* ---------------------------------------------------------------------------- + -- RNG Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup RNG_Register_Masks RNG Register Masks + * @{ + */ + +/*! @name RANDOM_NUMBER - This register contains a random 32 bit number which is computed on demand, at each time it is read */ +/*! @{ */ + +#define RNG_RANDOM_NUMBER_RANDOM_NUMBER_MASK (0xFFFFFFFFU) +#define RNG_RANDOM_NUMBER_RANDOM_NUMBER_SHIFT (0U) +/*! RANDOM_NUMBER - This register contains a random 32 bit number which is computed on demand, at each time it is read. + */ +#define RNG_RANDOM_NUMBER_RANDOM_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << RNG_RANDOM_NUMBER_RANDOM_NUMBER_SHIFT)) & RNG_RANDOM_NUMBER_RANDOM_NUMBER_MASK) +/*! @} */ + +/*! @name ENCRYPTED_NUMBER - This register contains a random 32 bit number which is pre-computed */ +/*! @{ */ + +#define RNG_ENCRYPTED_NUMBER_ENCRYPTED_NUMBER_MASK (0xFFFFFFFFU) +#define RNG_ENCRYPTED_NUMBER_ENCRYPTED_NUMBER_SHIFT (0U) +/*! ENCRYPTED_NUMBER - This register contains a random 32 bit number which is pre-computed. + */ +#define RNG_ENCRYPTED_NUMBER_ENCRYPTED_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << RNG_ENCRYPTED_NUMBER_ENCRYPTED_NUMBER_SHIFT)) & RNG_ENCRYPTED_NUMBER_ENCRYPTED_NUMBER_MASK) +/*! @} */ + +/*! @name COUNTER_VAL - */ +/*! @{ */ + +#define RNG_COUNTER_VAL_CLK_RATIO_MASK (0xFFU) +#define RNG_COUNTER_VAL_CLK_RATIO_SHIFT (0U) +/*! CLK_RATIO - Gives the ratio between the internal clocks frequencies and the register clock + * frequency for evaluation and certification purposes. + */ +#define RNG_COUNTER_VAL_CLK_RATIO(x) (((uint32_t)(((uint32_t)(x)) << RNG_COUNTER_VAL_CLK_RATIO_SHIFT)) & RNG_COUNTER_VAL_CLK_RATIO_MASK) + +#define RNG_COUNTER_VAL_REFRESH_CNT_MASK (0x3FFF00U) +#define RNG_COUNTER_VAL_REFRESH_CNT_SHIFT (8U) +/*! REFRESH_CNT - Incremented (till max possible value) each time COUNTER was updated since last reading to any *_NUMBER. + */ +#define RNG_COUNTER_VAL_REFRESH_CNT(x) (((uint32_t)(((uint32_t)(x)) << RNG_COUNTER_VAL_REFRESH_CNT_SHIFT)) & RNG_COUNTER_VAL_REFRESH_CNT_MASK) +/*! @} */ + +/*! @name COUNTER_CFG - */ +/*! @{ */ + +#define RNG_COUNTER_CFG_MODE_MASK (0x3U) +#define RNG_COUNTER_CFG_MODE_SHIFT (0U) +/*! MODE - 00: disabled 01: update once. + */ +#define RNG_COUNTER_CFG_MODE(x) (((uint32_t)(((uint32_t)(x)) << RNG_COUNTER_CFG_MODE_SHIFT)) & RNG_COUNTER_CFG_MODE_MASK) + +#define RNG_COUNTER_CFG_CLOCK_SEL_MASK (0x1CU) +#define RNG_COUNTER_CFG_CLOCK_SEL_SHIFT (2U) +/*! CLOCK_SEL - Selects the internal clock on which to compute statistics. + */ +#define RNG_COUNTER_CFG_CLOCK_SEL(x) (((uint32_t)(((uint32_t)(x)) << RNG_COUNTER_CFG_CLOCK_SEL_SHIFT)) & RNG_COUNTER_CFG_CLOCK_SEL_MASK) + +#define RNG_COUNTER_CFG_SHIFT4X_MASK (0xE0U) +#define RNG_COUNTER_CFG_SHIFT4X_SHIFT (5U) +/*! SHIFT4X - To be used to add precision to clock_ratio and determine 'entropy refill'. + */ +#define RNG_COUNTER_CFG_SHIFT4X(x) (((uint32_t)(((uint32_t)(x)) << RNG_COUNTER_CFG_SHIFT4X_SHIFT)) & RNG_COUNTER_CFG_SHIFT4X_MASK) +/*! @} */ + +/*! @name ONLINE_TEST_CFG - */ +/*! @{ */ + +#define RNG_ONLINE_TEST_CFG_ACTIVATE_MASK (0x1U) +#define RNG_ONLINE_TEST_CFG_ACTIVATE_SHIFT (0U) +/*! ACTIVATE - 0: disabled 1: activated Update rythm for VAL depends on COUNTER_CFG if data_sel is set to COUNTER. + */ +#define RNG_ONLINE_TEST_CFG_ACTIVATE(x) (((uint32_t)(((uint32_t)(x)) << RNG_ONLINE_TEST_CFG_ACTIVATE_SHIFT)) & RNG_ONLINE_TEST_CFG_ACTIVATE_MASK) + +#define RNG_ONLINE_TEST_CFG_DATA_SEL_MASK (0x6U) +#define RNG_ONLINE_TEST_CFG_DATA_SEL_SHIFT (1U) +/*! DATA_SEL - Selects source on which to apply online test: 00: LSB of COUNTER: raw data from one + * or all sources of entropy 01: MSB of COUNTER: raw data from one or all sources of entropy 10: + * RANDOM_NUMBER 11: ENCRYPTED_NUMBER 'activate' should be set to 'disabled' before changing this + * field. + */ +#define RNG_ONLINE_TEST_CFG_DATA_SEL(x) (((uint32_t)(((uint32_t)(x)) << RNG_ONLINE_TEST_CFG_DATA_SEL_SHIFT)) & RNG_ONLINE_TEST_CFG_DATA_SEL_MASK) +/*! @} */ + +/*! @name ONLINE_TEST_VAL - */ +/*! @{ */ + +#define RNG_ONLINE_TEST_VAL_LIVE_CHI_SQUARED_MASK (0xFU) +#define RNG_ONLINE_TEST_VAL_LIVE_CHI_SQUARED_SHIFT (0U) +/*! LIVE_CHI_SQUARED - This value is updated as described in field 'activate'. + */ +#define RNG_ONLINE_TEST_VAL_LIVE_CHI_SQUARED(x) (((uint32_t)(((uint32_t)(x)) << RNG_ONLINE_TEST_VAL_LIVE_CHI_SQUARED_SHIFT)) & RNG_ONLINE_TEST_VAL_LIVE_CHI_SQUARED_MASK) + +#define RNG_ONLINE_TEST_VAL_MIN_CHI_SQUARED_MASK (0xF0U) +#define RNG_ONLINE_TEST_VAL_MIN_CHI_SQUARED_SHIFT (4U) +/*! MIN_CHI_SQUARED - This field is reset when 'activate'==0. + */ +#define RNG_ONLINE_TEST_VAL_MIN_CHI_SQUARED(x) (((uint32_t)(((uint32_t)(x)) << RNG_ONLINE_TEST_VAL_MIN_CHI_SQUARED_SHIFT)) & RNG_ONLINE_TEST_VAL_MIN_CHI_SQUARED_MASK) + +#define RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED_MASK (0xF00U) +#define RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED_SHIFT (8U) +/*! MAX_CHI_SQUARED - This field is reset when 'activate'==0. + */ +#define RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED(x) (((uint32_t)(((uint32_t)(x)) << RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED_SHIFT)) & RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED_MASK) +/*! @} */ + +/*! @name ENTROPY_INJECT - */ +/*! @{ */ + +#define RNG_ENTROPY_INJECT_ENTROPY_MASK (0xFFFFFFFFU) +#define RNG_ENTROPY_INJECT_ENTROPY_SHIFT (0U) +/*! ENTROPY - Use this register to inject or restore entropy 32 bits at a time. Writing is blocking + * thus see to it to have analog clocks activated. Injection can be usefull to add contribution + * from an external source of entropy, like for example LSBs of an ADC or of a temperature sensor. + * Restore can be usefull to store N random numbers in central memory before going powerdown + * then restore this entropy to RNG IP after power-up. It is useless to inject or restore more than + * 1*(number of RNGs) 32b words consecutively. Recommendation is to inject 1*(number of RNGs) + * words, and possibly later (2*32 clock cycles of slowest analog clock) inject again 1*(number of + * RNGs) words. Then maximum capacity of restoration is reached: about 44 bits per RNG (not to be + * mistaken with maximum capacity of entropy accumulation which is about 100 bits per RNG). You + * can inject less than 32 bits words (let unused bits to 0). Injection cannot degrade overall + * performance due to the fact that some internal PRNGs are excluded on purpose from this external + * action. + */ +#define RNG_ENTROPY_INJECT_ENTROPY(x) (((uint32_t)(((uint32_t)(x)) << RNG_ENTROPY_INJECT_ENTROPY_SHIFT)) & RNG_ENTROPY_INJECT_ENTROPY_MASK) +/*! @} */ + +/*! @name MISC_CFG - */ +/*! @{ */ + +#define RNG_MISC_CFG_AES_RESEED_MASK (0x1U) +#define RNG_MISC_CFG_AES_RESEED_SHIFT (0U) +/*! AES_RESEED - If set, ENCRYPTED_NUMBER generation becomes predictable, provided all secrets and + * current internal state are known: independant from entropy source. + */ +#define RNG_MISC_CFG_AES_RESEED(x) (((uint32_t)(((uint32_t)(x)) << RNG_MISC_CFG_AES_RESEED_SHIFT)) & RNG_MISC_CFG_AES_RESEED_MASK) + +#define RNG_MISC_CFG_AES_DT_CFG_MASK (0x2U) +#define RNG_MISC_CFG_AES_DT_CFG_SHIFT (1U) +/*! AES_DT_CFG - Set this bit to re-seed AES. + */ +#define RNG_MISC_CFG_AES_DT_CFG(x) (((uint32_t)(((uint32_t)(x)) << RNG_MISC_CFG_AES_DT_CFG_SHIFT)) & RNG_MISC_CFG_AES_DT_CFG_MASK) +/*! @} */ + +/*! @name POWERDOWN - Powerdown mode (standard but certainly useless here) */ +/*! @{ */ + +#define RNG_POWERDOWN_SOFT_RESET_MASK (0x1U) +#define RNG_POWERDOWN_SOFT_RESET_SHIFT (0U) +/*! SOFT_RESET - Request softreset that will go low automaticaly after acknowledge from CORE. + */ +#define RNG_POWERDOWN_SOFT_RESET(x) (((uint32_t)(((uint32_t)(x)) << RNG_POWERDOWN_SOFT_RESET_SHIFT)) & RNG_POWERDOWN_SOFT_RESET_MASK) + +#define RNG_POWERDOWN_FORCE_SOFT_RESET_MASK (0x2U) +#define RNG_POWERDOWN_FORCE_SOFT_RESET_SHIFT (1U) +/*! FORCE_SOFT_RESET - When used with softreset it forces CORE_RESETN to low on acknowledge from CORE. + */ +#define RNG_POWERDOWN_FORCE_SOFT_RESET(x) (((uint32_t)(((uint32_t)(x)) << RNG_POWERDOWN_FORCE_SOFT_RESET_SHIFT)) & RNG_POWERDOWN_FORCE_SOFT_RESET_MASK) + +#define RNG_POWERDOWN_POWERDOWN_MASK (0x80000000U) +#define RNG_POWERDOWN_POWERDOWN_SHIFT (31U) +/*! POWERDOWN - When set all accesses to standard registers are blocked. + */ +#define RNG_POWERDOWN_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << RNG_POWERDOWN_POWERDOWN_SHIFT)) & RNG_POWERDOWN_POWERDOWN_MASK) +/*! @} */ + +/*! @name MODULEID - IP identifier */ +/*! @{ */ + +#define RNG_MODULEID_APERTURE_MASK (0xFFU) +#define RNG_MODULEID_APERTURE_SHIFT (0U) +/*! APERTURE - Aperture i. + */ +#define RNG_MODULEID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << RNG_MODULEID_APERTURE_SHIFT)) & RNG_MODULEID_APERTURE_MASK) + +#define RNG_MODULEID_MIN_REV_MASK (0xF00U) +#define RNG_MODULEID_MIN_REV_SHIFT (8U) +/*! MIN_REV - Minor revision i. + */ +#define RNG_MODULEID_MIN_REV(x) (((uint32_t)(((uint32_t)(x)) << RNG_MODULEID_MIN_REV_SHIFT)) & RNG_MODULEID_MIN_REV_MASK) + +#define RNG_MODULEID_MAJ_REV_MASK (0xF000U) +#define RNG_MODULEID_MAJ_REV_SHIFT (12U) +/*! MAJ_REV - Major revision i. + */ +#define RNG_MODULEID_MAJ_REV(x) (((uint32_t)(((uint32_t)(x)) << RNG_MODULEID_MAJ_REV_SHIFT)) & RNG_MODULEID_MAJ_REV_MASK) + +#define RNG_MODULEID_ID_MASK (0xFFFF0000U) +#define RNG_MODULEID_ID_SHIFT (16U) +/*! ID - Identifier. + */ +#define RNG_MODULEID_ID(x) (((uint32_t)(((uint32_t)(x)) << RNG_MODULEID_ID_SHIFT)) & RNG_MODULEID_ID_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group RNG_Register_Masks */ + + +/* RNG - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral RNG base address */ + #define RNG_BASE (0x5003A000u) + /** Peripheral RNG base address */ + #define RNG_BASE_NS (0x4003A000u) + /** Peripheral RNG base pointer */ + #define RNG ((RNG_Type *)RNG_BASE) + /** Peripheral RNG base pointer */ + #define RNG_NS ((RNG_Type *)RNG_BASE_NS) + /** Array initializer of RNG peripheral base addresses */ + #define RNG_BASE_ADDRS { RNG_BASE } + /** Array initializer of RNG peripheral base pointers */ + #define RNG_BASE_PTRS { RNG } + /** Array initializer of RNG peripheral base addresses */ + #define RNG_BASE_ADDRS_NS { RNG_BASE_NS } + /** Array initializer of RNG peripheral base pointers */ + #define RNG_BASE_PTRS_NS { RNG_NS } +#else + /** Peripheral RNG base address */ + #define RNG_BASE (0x4003A000u) + /** Peripheral RNG base pointer */ + #define RNG ((RNG_Type *)RNG_BASE) + /** Array initializer of RNG peripheral base addresses */ + #define RNG_BASE_ADDRS { RNG_BASE } + /** Array initializer of RNG peripheral base pointers */ + #define RNG_BASE_PTRS { RNG } +#endif + +/*! + * @} + */ /* end of group RNG_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- RTC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer + * @{ + */ + +/** RTC - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL; /**< RTC control register, offset: 0x0 */ + __IO uint32_t MATCH; /**< RTC match register, offset: 0x4 */ + __IO uint32_t COUNT; /**< RTC counter register, offset: 0x8 */ + __IO uint32_t WAKE; /**< High-resolution/wake-up timer control register, offset: 0xC */ + __I uint32_t SUBSEC; /**< Sub-second counter register, offset: 0x10 */ + uint8_t RESERVED_0[44]; + __IO uint32_t GPREG[8]; /**< General Purpose register, array offset: 0x40, array step: 0x4 */ +} RTC_Type; + +/* ---------------------------------------------------------------------------- + -- RTC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup RTC_Register_Masks RTC Register Masks + * @{ + */ + +/*! @name CTRL - RTC control register */ +/*! @{ */ + +#define RTC_CTRL_SWRESET_MASK (0x1U) +#define RTC_CTRL_SWRESET_SHIFT (0U) +/*! SWRESET - Software reset control + * 0b0..Not in reset. The RTC is not held in reset. This bit must be cleared prior to configuring or initiating any operation of the RTC. + * 0b1..In reset. The RTC is held in reset. All register bits within the RTC will be forced to their reset value + * except the OFD bit. This bit must be cleared before writing to any register in the RTC - including writes + * to set any of the other bits within this register. Do not attempt to write to any bits of this register at + * the same time that the reset bit is being cleared. + */ +#define RTC_CTRL_SWRESET(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_SWRESET_SHIFT)) & RTC_CTRL_SWRESET_MASK) + +#define RTC_CTRL_ALARM1HZ_MASK (0x4U) +#define RTC_CTRL_ALARM1HZ_SHIFT (2U) +/*! ALARM1HZ - RTC 1 Hz timer alarm flag status. + * 0b0..No match. No match has occurred on the 1 Hz RTC timer. Writing a 0 has no effect. + * 0b1..Match. A match condition has occurred on the 1 Hz RTC timer. This flag generates an RTC alarm interrupt + * request RTC_ALARM which can also wake up the part from any low power mode. Writing a 1 clears this bit. + */ +#define RTC_CTRL_ALARM1HZ(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_ALARM1HZ_SHIFT)) & RTC_CTRL_ALARM1HZ_MASK) + +#define RTC_CTRL_WAKE1KHZ_MASK (0x8U) +#define RTC_CTRL_WAKE1KHZ_SHIFT (3U) +/*! WAKE1KHZ - RTC 1 kHz timer wake-up flag status. + * 0b0..Run. The RTC 1 kHz timer is running. Writing a 0 has no effect. + * 0b1..Time-out. The 1 kHz high-resolution/wake-up timer has timed out. This flag generates an RTC wake-up + * interrupt request RTC-WAKE which can also wake up the part from any low power mode. Writing a 1 clears this bit. + */ +#define RTC_CTRL_WAKE1KHZ(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_WAKE1KHZ_SHIFT)) & RTC_CTRL_WAKE1KHZ_MASK) + +#define RTC_CTRL_ALARMDPD_EN_MASK (0x10U) +#define RTC_CTRL_ALARMDPD_EN_SHIFT (4U) +/*! ALARMDPD_EN - RTC 1 Hz timer alarm enable for Deep power-down. + * 0b0..Disable. A match on the 1 Hz RTC timer will not bring the part out of Deep power-down mode. + * 0b1..Enable. A match on the 1 Hz RTC timer bring the part out of Deep power-down mode. + */ +#define RTC_CTRL_ALARMDPD_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_ALARMDPD_EN_SHIFT)) & RTC_CTRL_ALARMDPD_EN_MASK) + +#define RTC_CTRL_WAKEDPD_EN_MASK (0x20U) +#define RTC_CTRL_WAKEDPD_EN_SHIFT (5U) +/*! WAKEDPD_EN - RTC 1 kHz timer wake-up enable for Deep power-down. + * 0b0..Disable. A match on the 1 kHz RTC timer will not bring the part out of Deep power-down mode. + * 0b1..Enable. A match on the 1 kHz RTC timer bring the part out of Deep power-down mode. + */ +#define RTC_CTRL_WAKEDPD_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_WAKEDPD_EN_SHIFT)) & RTC_CTRL_WAKEDPD_EN_MASK) + +#define RTC_CTRL_RTC1KHZ_EN_MASK (0x40U) +#define RTC_CTRL_RTC1KHZ_EN_SHIFT (6U) +/*! RTC1KHZ_EN - RTC 1 kHz clock enable. This bit can be set to 0 to conserve power if the 1 kHz + * timer is not used. This bit has no effect when the RTC is disabled (bit 7 of this register is 0). + * 0b0..Disable. A match on the 1 kHz RTC timer will not bring the part out of Deep power-down mode. + * 0b1..Enable. The 1 kHz RTC timer is enabled. + */ +#define RTC_CTRL_RTC1KHZ_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC1KHZ_EN_SHIFT)) & RTC_CTRL_RTC1KHZ_EN_MASK) + +#define RTC_CTRL_RTC_EN_MASK (0x80U) +#define RTC_CTRL_RTC_EN_SHIFT (7U) +/*! RTC_EN - RTC enable. + * 0b0..Disable. The RTC 1 Hz and 1 kHz clocks are shut down and the RTC operation is disabled. This bit should + * be 0 when writing to load a value in the RTC counter register. + * 0b1..Enable. The 1 Hz RTC clock is running and RTC operation is enabled. This bit must be set to initiate + * operation of the RTC. The first clock to the RTC counter occurs 1 s after this bit is set. To also enable the + * high-resolution, 1 kHz clock, set bit 6 in this register. + */ +#define RTC_CTRL_RTC_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC_EN_SHIFT)) & RTC_CTRL_RTC_EN_MASK) + +#define RTC_CTRL_RTC_OSC_PD_MASK (0x100U) +#define RTC_CTRL_RTC_OSC_PD_SHIFT (8U) +/*! RTC_OSC_PD - RTC oscillator power-down control. + * 0b0..See RTC_OSC_BYPASS + * 0b1..RTC oscillator is powered-down. + */ +#define RTC_CTRL_RTC_OSC_PD(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC_OSC_PD_SHIFT)) & RTC_CTRL_RTC_OSC_PD_MASK) + +#define RTC_CTRL_RTC_OSC_BYPASS_MASK (0x200U) +#define RTC_CTRL_RTC_OSC_BYPASS_SHIFT (9U) +/*! RTC_OSC_BYPASS - RTC oscillator bypass control. + * 0b0..The RTC Oscillator operates normally as a crystal oscillator with the crystal connected between the RTC_XTALIN and RTC_XTALOUT pins. + * 0b1..The RTC Oscillator is in bypass mode. In this mode a clock can be directly input into the RTC_XTALIN pin. + */ +#define RTC_CTRL_RTC_OSC_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC_OSC_BYPASS_SHIFT)) & RTC_CTRL_RTC_OSC_BYPASS_MASK) + +#define RTC_CTRL_RTC_SUBSEC_ENA_MASK (0x400U) +#define RTC_CTRL_RTC_SUBSEC_ENA_SHIFT (10U) +/*! RTC_SUBSEC_ENA - RTC Sub-second counter control. + * 0b0..The sub-second counter (if implemented) is disabled. This bit is cleared by a system-level POR or BOD + * reset as well as a by the RTC_ENA bit (bit 7 in this register). On modules not equipped with a sub-second + * counter, this bit will always read-back as a '0'. + * 0b1..The 32 KHz sub-second counter is enabled (if implemented). Counting commences on the start of the first + * one-second interval after this bit is set. Note: This bit can only be set after the RTC_ENA bit (bit 7) is + * set by a previous write operation. Note: The RTC sub-second counter must be re-enabled whenever the chip + * exits deep power-down mode. + */ +#define RTC_CTRL_RTC_SUBSEC_ENA(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC_SUBSEC_ENA_SHIFT)) & RTC_CTRL_RTC_SUBSEC_ENA_MASK) +/*! @} */ + +/*! @name MATCH - RTC match register */ +/*! @{ */ + +#define RTC_MATCH_MATVAL_MASK (0xFFFFFFFFU) +#define RTC_MATCH_MATVAL_SHIFT (0U) +/*! MATVAL - Contains the match value against which the 1 Hz RTC timer will be compared to set the + * alarm flag RTC_ALARM and generate an alarm interrupt/wake-up if enabled. + */ +#define RTC_MATCH_MATVAL(x) (((uint32_t)(((uint32_t)(x)) << RTC_MATCH_MATVAL_SHIFT)) & RTC_MATCH_MATVAL_MASK) +/*! @} */ + +/*! @name COUNT - RTC counter register */ +/*! @{ */ + +#define RTC_COUNT_VAL_MASK (0xFFFFFFFFU) +#define RTC_COUNT_VAL_SHIFT (0U) +/*! VAL - A read reflects the current value of the main, 1 Hz RTC timer. A write loads a new initial + * value into the timer. The RTC counter will count up continuously at a 1 Hz rate once the RTC + * Software Reset is removed (by clearing bit 0 of the CTRL register). Only write to this + * register when the RTC_EN bit in the RTC CTRL Register is 0. The counter increments one second after + * the RTC_EN bit is set. + */ +#define RTC_COUNT_VAL(x) (((uint32_t)(((uint32_t)(x)) << RTC_COUNT_VAL_SHIFT)) & RTC_COUNT_VAL_MASK) +/*! @} */ + +/*! @name WAKE - High-resolution/wake-up timer control register */ +/*! @{ */ + +#define RTC_WAKE_VAL_MASK (0xFFFFU) +#define RTC_WAKE_VAL_SHIFT (0U) +/*! VAL - A read reflects the current value of the high-resolution/wake-up timer. A write pre-loads + * a start count value into the wake-up timer and initializes a count-down sequence. Do not write + * to this register while counting is in progress. + */ +#define RTC_WAKE_VAL(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAKE_VAL_SHIFT)) & RTC_WAKE_VAL_MASK) +/*! @} */ + +/*! @name SUBSEC - Sub-second counter register */ +/*! @{ */ + +#define RTC_SUBSEC_SUBSEC_MASK (0x7FFFU) +#define RTC_SUBSEC_SUBSEC_SHIFT (0U) +/*! SUBSEC - A read reflects the current value of the 32KHz sub-second counter. This counter is + * cleared whenever the SUBSEC_ENA bit in the RTC_CONTROL register is low. Up-counting at a 32KHz + * rate commences at the start of the next one-second interval after the SUBSEC_ENA bit is set. This + * counter must be re-enabled after exiting deep power-down mode or after the main RTC module is + * disabled and re-enabled. On modules not equipped with a sub-second counter, this register + * will read-back as all zeroes. + */ +#define RTC_SUBSEC_SUBSEC(x) (((uint32_t)(((uint32_t)(x)) << RTC_SUBSEC_SUBSEC_SHIFT)) & RTC_SUBSEC_SUBSEC_MASK) +/*! @} */ + +/*! @name GPREG - General Purpose register */ +/*! @{ */ + +#define RTC_GPREG_GPDATA_MASK (0xFFFFFFFFU) +#define RTC_GPREG_GPDATA_SHIFT (0U) +/*! GPDATA - Data retained during Deep power-down mode or loss of main power as long as VBAT is supplied. + */ +#define RTC_GPREG_GPDATA(x) (((uint32_t)(((uint32_t)(x)) << RTC_GPREG_GPDATA_SHIFT)) & RTC_GPREG_GPDATA_MASK) +/*! @} */ + +/* The count of RTC_GPREG */ +#define RTC_GPREG_COUNT (8U) + + +/*! + * @} + */ /* end of group RTC_Register_Masks */ + + +/* RTC - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral RTC base address */ + #define RTC_BASE (0x5002C000u) + /** Peripheral RTC base address */ + #define RTC_BASE_NS (0x4002C000u) + /** Peripheral RTC base pointer */ + #define RTC ((RTC_Type *)RTC_BASE) + /** Peripheral RTC base pointer */ + #define RTC_NS ((RTC_Type *)RTC_BASE_NS) + /** Array initializer of RTC peripheral base addresses */ + #define RTC_BASE_ADDRS { RTC_BASE } + /** Array initializer of RTC peripheral base pointers */ + #define RTC_BASE_PTRS { RTC } + /** Array initializer of RTC peripheral base addresses */ + #define RTC_BASE_ADDRS_NS { RTC_BASE_NS } + /** Array initializer of RTC peripheral base pointers */ + #define RTC_BASE_PTRS_NS { RTC_NS } +#else + /** Peripheral RTC base address */ + #define RTC_BASE (0x4002C000u) + /** Peripheral RTC base pointer */ + #define RTC ((RTC_Type *)RTC_BASE) + /** Array initializer of RTC peripheral base addresses */ + #define RTC_BASE_ADDRS { RTC_BASE } + /** Array initializer of RTC peripheral base pointers */ + #define RTC_BASE_PTRS { RTC } +#endif +/** Interrupt vectors for the RTC peripheral type */ +#define RTC_IRQS { RTC_IRQn } + +/*! + * @} + */ /* end of group RTC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- SCT Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SCT_Peripheral_Access_Layer SCT Peripheral Access Layer + * @{ + */ + +/** SCT - Register Layout Typedef */ +typedef struct { + __IO uint32_t CONFIG; /**< SCT configuration register, offset: 0x0 */ + union { /* offset: 0x4 */ + struct { /* offset: 0x4 */ + __IO uint16_t CTRLL; /**< SCT_CTRLL register, offset: 0x4 */ + __IO uint16_t CTRLH; /**< SCT_CTRLH register, offset: 0x6 */ + } CTRL_ACCESS16BIT; + __IO uint32_t CTRL; /**< SCT control register, offset: 0x4 */ + }; + union { /* offset: 0x8 */ + struct { /* offset: 0x8 */ + __IO uint16_t LIMITL; /**< SCT_LIMITL register, offset: 0x8 */ + __IO uint16_t LIMITH; /**< SCT_LIMITH register, offset: 0xA */ + } LIMIT_ACCESS16BIT; + __IO uint32_t LIMIT; /**< SCT limit event select register, offset: 0x8 */ + }; + union { /* offset: 0xC */ + struct { /* offset: 0xC */ + __IO uint16_t HALTL; /**< SCT_HALTL register, offset: 0xC */ + __IO uint16_t HALTH; /**< SCT_HALTH register, offset: 0xE */ + } HALT_ACCESS16BIT; + __IO uint32_t HALT; /**< SCT halt event select register, offset: 0xC */ + }; + union { /* offset: 0x10 */ + struct { /* offset: 0x10 */ + __IO uint16_t STOPL; /**< SCT_STOPL register, offset: 0x10 */ + __IO uint16_t STOPH; /**< SCT_STOPH register, offset: 0x12 */ + } STOP_ACCESS16BIT; + __IO uint32_t STOP; /**< SCT stop event select register, offset: 0x10 */ + }; + union { /* offset: 0x14 */ + struct { /* offset: 0x14 */ + __IO uint16_t STARTL; /**< SCT_STARTL register, offset: 0x14 */ + __IO uint16_t STARTH; /**< SCT_STARTH register, offset: 0x16 */ + } START_ACCESS16BIT; + __IO uint32_t START; /**< SCT start event select register, offset: 0x14 */ + }; + uint8_t RESERVED_0[40]; + union { /* offset: 0x40 */ + struct { /* offset: 0x40 */ + __IO uint16_t COUNTL; /**< SCT_COUNTL register, offset: 0x40 */ + __IO uint16_t COUNTH; /**< SCT_COUNTH register, offset: 0x42 */ + } COUNT_ACCESS16BIT; + __IO uint32_t COUNT; /**< SCT counter register, offset: 0x40 */ + }; + union { /* offset: 0x44 */ + struct { /* offset: 0x44 */ + __IO uint16_t STATEL; /**< SCT_STATEL register, offset: 0x44 */ + __IO uint16_t STATEH; /**< SCT_STATEH register, offset: 0x46 */ + } STATE_ACCESS16BIT; + __IO uint32_t STATE; /**< SCT state register, offset: 0x44 */ + }; + __I uint32_t INPUT; /**< SCT input register, offset: 0x48 */ + union { /* offset: 0x4C */ + struct { /* offset: 0x4C */ + __IO uint16_t REGMODEL; /**< SCT_REGMODEL register, offset: 0x4C */ + __IO uint16_t REGMODEH; /**< SCT_REGMODEH register, offset: 0x4E */ + } REGMODE_ACCESS16BIT; + __IO uint32_t REGMODE; /**< SCT match/capture mode register, offset: 0x4C */ + }; + __IO uint32_t OUTPUT; /**< SCT output register, offset: 0x50 */ + __IO uint32_t OUTPUTDIRCTRL; /**< SCT output counter direction control register, offset: 0x54 */ + __IO uint32_t RES; /**< SCT conflict resolution register, offset: 0x58 */ + __IO uint32_t DMAREQ0; /**< SCT DMA request 0 register, offset: 0x5C */ + __IO uint32_t DMAREQ1; /**< SCT DMA request 1 register, offset: 0x60 */ + uint8_t RESERVED_1[140]; + __IO uint32_t EVEN; /**< SCT event interrupt enable register, offset: 0xF0 */ + __IO uint32_t EVFLAG; /**< SCT event flag register, offset: 0xF4 */ + __IO uint32_t CONEN; /**< SCT conflict interrupt enable register, offset: 0xF8 */ + __IO uint32_t CONFLAG; /**< SCT conflict flag register, offset: 0xFC */ + union { /* offset: 0x100 */ + union { /* offset: 0x100, array step: 0x4 */ + struct { /* offset: 0x100, array step: 0x4 */ + __IO uint16_t CAPL; /**< SCT_CAPL register, array offset: 0x100, array step: 0x4 */ + __IO uint16_t CAPH; /**< SCT_CAPH register, array offset: 0x102, array step: 0x4 */ + } CAP_ACCESS16BIT[16]; + __IO uint32_t CAP[16]; /**< SCT capture register of capture channel, array offset: 0x100, array step: 0x4 */ + }; + union { /* offset: 0x100, array step: 0x4 */ + struct { /* offset: 0x100, array step: 0x4 */ + __IO uint16_t MATCHL; /**< SCT_MATCHL register, array offset: 0x100, array step: 0x4 */ + __IO uint16_t MATCHH; /**< SCT_MATCHH register, array offset: 0x102, array step: 0x4 */ + } MATCH_ACCESS16BIT[16]; + __IO uint32_t MATCH[16]; /**< SCT match value register of match channels, array offset: 0x100, array step: 0x4 */ + }; + }; + uint8_t RESERVED_2[192]; + union { /* offset: 0x200 */ + union { /* offset: 0x200, array step: 0x4 */ + struct { /* offset: 0x200, array step: 0x4 */ + __IO uint16_t CAPCTRLL; /**< SCT_CAPCTRLL register, array offset: 0x200, array step: 0x4 */ + __IO uint16_t CAPCTRLH; /**< SCT_CAPCTRLH register, array offset: 0x202, array step: 0x4 */ + } CAPCTRL_ACCESS16BIT[16]; + __IO uint32_t CAPCTRL[16]; /**< SCT capture control register, array offset: 0x200, array step: 0x4 */ + }; + union { /* offset: 0x200, array step: 0x4 */ + struct { /* offset: 0x200, array step: 0x4 */ + __IO uint16_t MATCHRELL; /**< SCT_MATCHRELL register, array offset: 0x200, array step: 0x4 */ + __IO uint16_t MATCHRELH; /**< SCT_MATCHRELH register, array offset: 0x202, array step: 0x4 */ + } MATCHREL_ACCESS16BIT[16]; + __IO uint32_t MATCHREL[16]; /**< SCT match reload value register, array offset: 0x200, array step: 0x4 */ + }; + }; + uint8_t RESERVED_3[192]; + struct { /* offset: 0x300, array step: 0x8 */ + __IO uint32_t STATE; /**< SCT event state register 0, array offset: 0x300, array step: 0x8 */ + __IO uint32_t CTRL; /**< SCT event control register 0, array offset: 0x304, array step: 0x8 */ + } EV[16]; + uint8_t RESERVED_4[384]; + struct { /* offset: 0x500, array step: 0x8 */ + __IO uint32_t SET; /**< SCT output 0 set register, array offset: 0x500, array step: 0x8 */ + __IO uint32_t CLR; /**< SCT output 0 clear register, array offset: 0x504, array step: 0x8 */ + } OUT[10]; +} SCT_Type; + +/* ---------------------------------------------------------------------------- + -- SCT Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SCT_Register_Masks SCT Register Masks + * @{ + */ + +/*! @name CONFIG - SCT configuration register */ +/*! @{ */ + +#define SCT_CONFIG_UNIFY_MASK (0x1U) +#define SCT_CONFIG_UNIFY_SHIFT (0U) +/*! UNIFY - SCT operation + * 0b0..The SCT operates as two 16-bit counters named COUNTER_L and COUNTER_H. + * 0b1..The SCT operates as a unified 32-bit counter. + */ +#define SCT_CONFIG_UNIFY(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_UNIFY_SHIFT)) & SCT_CONFIG_UNIFY_MASK) + +#define SCT_CONFIG_CLKMODE_MASK (0x6U) +#define SCT_CONFIG_CLKMODE_SHIFT (1U) +/*! CLKMODE - SCT clock mode + * 0b00..System Clock Mode. The system clock clocks the entire SCT module including the counter(s) and counter prescalers. + * 0b01..Sampled System Clock Mode. The system clock clocks the SCT module, but the counter and prescalers are + * only enabled to count when the designated edge is detected on the input selected by the CKSEL field. The + * minimum pulse width on the selected clock-gate input is 1 bus clock period. This mode is the + * high-performance, sampled-clock mode. + * 0b10..SCT Input Clock Mode. The input/edge selected by the CKSEL field clocks the SCT module, including the + * counters and prescalers, after first being synchronized to the system clock. The minimum pulse width on the + * clock input is 1 bus clock period. This mode is the low-power, sampled-clock mode. + * 0b11..Asynchronous Mode. The entire SCT module is clocked directly by the input/edge selected by the CKSEL + * field. In this mode, the SCT outputs are switched synchronously to the SCT input clock - not the system + * clock. The input clock rate must be at least half the system clock rate and can be the same or faster than + * the system clock. + */ +#define SCT_CONFIG_CLKMODE(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_CLKMODE_SHIFT)) & SCT_CONFIG_CLKMODE_MASK) + +#define SCT_CONFIG_CKSEL_MASK (0x78U) +#define SCT_CONFIG_CKSEL_SHIFT (3U) +/*! CKSEL - SCT clock select. The specific functionality of the designated input/edge is dependent + * on the CLKMODE bit selection in this register. + * 0b0000..Rising edges on input 0. + * 0b0001..Falling edges on input 0. + * 0b0010..Rising edges on input 1. + * 0b0011..Falling edges on input 1. + * 0b0100..Rising edges on input 2. + * 0b0101..Falling edges on input 2. + * 0b0110..Rising edges on input 3. + * 0b0111..Falling edges on input 3. + * 0b1000..Rising edges on input 4. + * 0b1001..Falling edges on input 4. + * 0b1010..Rising edges on input 5. + * 0b1011..Falling edges on input 5. + * 0b1100..Rising edges on input 6. + * 0b1101..Falling edges on input 6. + * 0b1110..Rising edges on input 7. + * 0b1111..Falling edges on input 7. + */ +#define SCT_CONFIG_CKSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_CKSEL_SHIFT)) & SCT_CONFIG_CKSEL_MASK) + +#define SCT_CONFIG_NORELOAD_L_MASK (0x80U) +#define SCT_CONFIG_NORELOAD_L_SHIFT (7U) +/*! NORELOAD_L - A 1 in this bit prevents the lower match registers from being reloaded from their + * respective reload registers. Setting this bit eliminates the need to write to the reload + * registers MATCHREL if the match values are fixed. Software can write to set or clear this bit at any + * time. This bit applies to both the higher and lower registers when the UNIFY bit is set. + */ +#define SCT_CONFIG_NORELOAD_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_NORELOAD_L_SHIFT)) & SCT_CONFIG_NORELOAD_L_MASK) + +#define SCT_CONFIG_NORELOAD_H_MASK (0x100U) +#define SCT_CONFIG_NORELOAD_H_SHIFT (8U) +/*! NORELOAD_H - A 1 in this bit prevents the higher match registers from being reloaded from their + * respective reload registers. Setting this bit eliminates the need to write to the reload + * registers MATCHREL if the match values are fixed. Software can write to set or clear this bit at + * any time. This bit is not used when the UNIFY bit is set. + */ +#define SCT_CONFIG_NORELOAD_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_NORELOAD_H_SHIFT)) & SCT_CONFIG_NORELOAD_H_MASK) + +#define SCT_CONFIG_INSYNC_MASK (0x1E00U) +#define SCT_CONFIG_INSYNC_SHIFT (9U) +/*! INSYNC - Synchronization for input N (bit 9 = input 0, bit 10 = input 1,, bit 12 = input 3); all + * other bits are reserved. A 1 in one of these bits subjects the corresponding input to + * synchronization to the SCT clock, before it is used to create an event. If an input is known to + * already be synchronous to the SCT clock, this bit may be set to 0 for faster input response. (Note: + * The SCT clock is the system clock for CKMODEs 0-2. It is the selected, asynchronous SCT input + * clock for CKMODE3). Note that the INSYNC field only affects inputs used for event generation. + * It does not apply to the clock input specified in the CKSEL field. + */ +#define SCT_CONFIG_INSYNC(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_INSYNC_SHIFT)) & SCT_CONFIG_INSYNC_MASK) + +#define SCT_CONFIG_AUTOLIMIT_L_MASK (0x20000U) +#define SCT_CONFIG_AUTOLIMIT_L_SHIFT (17U) +/*! AUTOLIMIT_L - A one in this bit causes a match on match register 0 to be treated as a de-facto + * LIMIT condition without the need to define an associated event. As with any LIMIT event, this + * automatic limit causes the counter to be cleared to zero in unidirectional mode or to change + * the direction of count in bi-directional mode. Software can write to set or clear this bit at + * any time. This bit applies to both the higher and lower registers when the UNIFY bit is set. + */ +#define SCT_CONFIG_AUTOLIMIT_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_AUTOLIMIT_L_SHIFT)) & SCT_CONFIG_AUTOLIMIT_L_MASK) + +#define SCT_CONFIG_AUTOLIMIT_H_MASK (0x40000U) +#define SCT_CONFIG_AUTOLIMIT_H_SHIFT (18U) +/*! AUTOLIMIT_H - A one in this bit will cause a match on match register 0 to be treated as a + * de-facto LIMIT condition without the need to define an associated event. As with any LIMIT event, + * this automatic limit causes the counter to be cleared to zero in unidirectional mode or to + * change the direction of count in bi-directional mode. Software can write to set or clear this bit + * at any time. This bit is not used when the UNIFY bit is set. + */ +#define SCT_CONFIG_AUTOLIMIT_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_AUTOLIMIT_H_SHIFT)) & SCT_CONFIG_AUTOLIMIT_H_MASK) +/*! @} */ + +/*! @name CTRLL - SCT_CTRLL register */ +/*! @{ */ + +#define SCT_CTRLL_DOWN_L_MASK (0x1U) +#define SCT_CTRLL_DOWN_L_SHIFT (0U) +/*! DOWN_L - This bit is 1 when the L or unified counter is counting down. Hardware sets this bit + * when the counter is counting up, counter limit occurs, and BIDIR = 1.Hardware clears this bit + * when the counter is counting down and a limit condition occurs or when the counter reaches 0. + */ +#define SCT_CTRLL_DOWN_L(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_DOWN_L_SHIFT)) & SCT_CTRLL_DOWN_L_MASK) + +#define SCT_CTRLL_STOP_L_MASK (0x2U) +#define SCT_CTRLL_STOP_L_SHIFT (1U) +/*! STOP_L - When this bit is 1 and HALT is 0, the L or unified counter does not run, but I/O events + * related to the counter can occur. If a designated start event occurs, this bit is cleared and + * counting resumes. + */ +#define SCT_CTRLL_STOP_L(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_STOP_L_SHIFT)) & SCT_CTRLL_STOP_L_MASK) + +#define SCT_CTRLL_HALT_L_MASK (0x4U) +#define SCT_CTRLL_HALT_L_SHIFT (2U) +/*! HALT_L - When this bit is 1, the L or unified counter does not run and no events can occur. A + * reset sets this bit. When the HALT_L bit is one, the STOP_L bit is cleared. It is possible to + * remove the halt condition while keeping the SCT in the stop condition (not running) with a + * single write to this register to simultaneously clear the HALT bit and set the STOP bit. Once set, + * only software can clear this bit to restore counter operation. This bit is set on reset. + */ +#define SCT_CTRLL_HALT_L(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_HALT_L_SHIFT)) & SCT_CTRLL_HALT_L_MASK) + +#define SCT_CTRLL_CLRCTR_L_MASK (0x8U) +#define SCT_CTRLL_CLRCTR_L_SHIFT (3U) +/*! CLRCTR_L - Writing a 1 to this bit clears the L or unified counter. This bit always reads as 0. + */ +#define SCT_CTRLL_CLRCTR_L(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_CLRCTR_L_SHIFT)) & SCT_CTRLL_CLRCTR_L_MASK) + +#define SCT_CTRLL_BIDIR_L_MASK (0x10U) +#define SCT_CTRLL_BIDIR_L_SHIFT (4U) +/*! BIDIR_L - L or unified counter direction select + * 0b0..Up. The counter counts up to a limit condition, then is cleared to zero. + * 0b1..Up-down. The counter counts up to a limit, then counts down to a limit condition or to 0. + */ +#define SCT_CTRLL_BIDIR_L(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_BIDIR_L_SHIFT)) & SCT_CTRLL_BIDIR_L_MASK) + +#define SCT_CTRLL_PRE_L_MASK (0x1FE0U) +#define SCT_CTRLL_PRE_L_SHIFT (5U) +/*! PRE_L - Specifies the factor by which the SCT clock is prescaled to produce the L or unified + * counter clock. The counter clock is clocked at the rate of the SCT clock divided by PRE_L+1. + * Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value. + */ +#define SCT_CTRLL_PRE_L(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_PRE_L_SHIFT)) & SCT_CTRLL_PRE_L_MASK) +/*! @} */ + +/*! @name CTRLH - SCT_CTRLH register */ +/*! @{ */ + +#define SCT_CTRLH_DOWN_H_MASK (0x1U) +#define SCT_CTRLH_DOWN_H_SHIFT (0U) +/*! DOWN_H - This bit is 1 when the H counter is counting down. Hardware sets this bit when the + * counter is counting, a counter limit condition occurs, and BIDIR is 1. Hardware clears this bit + * when the counter is counting down and a limit condition occurs or when the counter reaches 0. + */ +#define SCT_CTRLH_DOWN_H(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_DOWN_H_SHIFT)) & SCT_CTRLH_DOWN_H_MASK) + +#define SCT_CTRLH_STOP_H_MASK (0x2U) +#define SCT_CTRLH_STOP_H_SHIFT (1U) +/*! STOP_H - When this bit is 1 and HALT is 0, the H counter does not, run but I/O events related to + * the counter can occur. If such an event matches the mask in the Start register, this bit is + * cleared and counting resumes. + */ +#define SCT_CTRLH_STOP_H(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_STOP_H_SHIFT)) & SCT_CTRLH_STOP_H_MASK) + +#define SCT_CTRLH_HALT_H_MASK (0x4U) +#define SCT_CTRLH_HALT_H_SHIFT (2U) +/*! HALT_H - When this bit is 1, the H counter does not run and no events can occur. A reset sets + * this bit. When the HALT_H bit is one, the STOP_H bit is cleared. It is possible to remove the + * halt condition while keeping the SCT in the stop condition (not running) with a single write to + * this register to simultaneously clear the HALT bit and set the STOP bit. Once set, this bit + * can only be cleared by software to restore counter operation. This bit is set on reset. + */ +#define SCT_CTRLH_HALT_H(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_HALT_H_SHIFT)) & SCT_CTRLH_HALT_H_MASK) + +#define SCT_CTRLH_CLRCTR_H_MASK (0x8U) +#define SCT_CTRLH_CLRCTR_H_SHIFT (3U) +/*! CLRCTR_H - Writing a 1 to this bit clears the H counter. This bit always reads as 0. + */ +#define SCT_CTRLH_CLRCTR_H(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_CLRCTR_H_SHIFT)) & SCT_CTRLH_CLRCTR_H_MASK) + +#define SCT_CTRLH_BIDIR_H_MASK (0x10U) +#define SCT_CTRLH_BIDIR_H_SHIFT (4U) +/*! BIDIR_H - Direction select + * 0b0..The H counter counts up to its limit condition, then is cleared to zero. + * 0b1..The H counter counts up to its limit, then counts down to a limit condition or to 0. + */ +#define SCT_CTRLH_BIDIR_H(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_BIDIR_H_SHIFT)) & SCT_CTRLH_BIDIR_H_MASK) + +#define SCT_CTRLH_PRE_H_MASK (0x1FE0U) +#define SCT_CTRLH_PRE_H_SHIFT (5U) +/*! PRE_H - Specifies the factor by which the SCT clock is prescaled to produce the H counter clock. + * The counter clock is clocked at the rate of the SCT clock divided by PRELH+1. Clear the + * counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value. + */ +#define SCT_CTRLH_PRE_H(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_PRE_H_SHIFT)) & SCT_CTRLH_PRE_H_MASK) +/*! @} */ + +/*! @name CTRL - SCT control register */ +/*! @{ */ + +#define SCT_CTRL_DOWN_L_MASK (0x1U) +#define SCT_CTRL_DOWN_L_SHIFT (0U) +/*! DOWN_L - This bit is 1 when the L or unified counter is counting down. Hardware sets this bit + * when the counter is counting up, counter limit occurs, and BIDIR = 1.Hardware clears this bit + * when the counter is counting down and a limit condition occurs or when the counter reaches 0. + */ +#define SCT_CTRL_DOWN_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_DOWN_L_SHIFT)) & SCT_CTRL_DOWN_L_MASK) + +#define SCT_CTRL_STOP_L_MASK (0x2U) +#define SCT_CTRL_STOP_L_SHIFT (1U) +/*! STOP_L - When this bit is 1 and HALT is 0, the L or unified counter does not run, but I/O events + * related to the counter can occur. If a designated start event occurs, this bit is cleared and + * counting resumes. + */ +#define SCT_CTRL_STOP_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_STOP_L_SHIFT)) & SCT_CTRL_STOP_L_MASK) + +#define SCT_CTRL_HALT_L_MASK (0x4U) +#define SCT_CTRL_HALT_L_SHIFT (2U) +/*! HALT_L - When this bit is 1, the L or unified counter does not run and no events can occur. A + * reset sets this bit. When the HALT_L bit is one, the STOP_L bit is cleared. It is possible to + * remove the halt condition while keeping the SCT in the stop condition (not running) with a + * single write to this register to simultaneously clear the HALT bit and set the STOP bit. Once set, + * only software can clear this bit to restore counter operation. This bit is set on reset. + */ +#define SCT_CTRL_HALT_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_HALT_L_SHIFT)) & SCT_CTRL_HALT_L_MASK) + +#define SCT_CTRL_CLRCTR_L_MASK (0x8U) +#define SCT_CTRL_CLRCTR_L_SHIFT (3U) +/*! CLRCTR_L - Writing a 1 to this bit clears the L or unified counter. This bit always reads as 0. + */ +#define SCT_CTRL_CLRCTR_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_CLRCTR_L_SHIFT)) & SCT_CTRL_CLRCTR_L_MASK) + +#define SCT_CTRL_BIDIR_L_MASK (0x10U) +#define SCT_CTRL_BIDIR_L_SHIFT (4U) +/*! BIDIR_L - L or unified counter direction select + * 0b0..Up. The counter counts up to a limit condition, then is cleared to zero. + * 0b1..Up-down. The counter counts up to a limit, then counts down to a limit condition or to 0. + */ +#define SCT_CTRL_BIDIR_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_BIDIR_L_SHIFT)) & SCT_CTRL_BIDIR_L_MASK) + +#define SCT_CTRL_PRE_L_MASK (0x1FE0U) +#define SCT_CTRL_PRE_L_SHIFT (5U) +/*! PRE_L - Specifies the factor by which the SCT clock is prescaled to produce the L or unified + * counter clock. The counter clock is clocked at the rate of the SCT clock divided by PRE_L+1. + * Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value. + */ +#define SCT_CTRL_PRE_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_PRE_L_SHIFT)) & SCT_CTRL_PRE_L_MASK) + +#define SCT_CTRL_DOWN_H_MASK (0x10000U) +#define SCT_CTRL_DOWN_H_SHIFT (16U) +/*! DOWN_H - This bit is 1 when the H counter is counting down. Hardware sets this bit when the + * counter is counting, a counter limit condition occurs, and BIDIR is 1. Hardware clears this bit + * when the counter is counting down and a limit condition occurs or when the counter reaches 0. + */ +#define SCT_CTRL_DOWN_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_DOWN_H_SHIFT)) & SCT_CTRL_DOWN_H_MASK) + +#define SCT_CTRL_STOP_H_MASK (0x20000U) +#define SCT_CTRL_STOP_H_SHIFT (17U) +/*! STOP_H - When this bit is 1 and HALT is 0, the H counter does not, run but I/O events related to + * the counter can occur. If such an event matches the mask in the Start register, this bit is + * cleared and counting resumes. + */ +#define SCT_CTRL_STOP_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_STOP_H_SHIFT)) & SCT_CTRL_STOP_H_MASK) + +#define SCT_CTRL_HALT_H_MASK (0x40000U) +#define SCT_CTRL_HALT_H_SHIFT (18U) +/*! HALT_H - When this bit is 1, the H counter does not run and no events can occur. A reset sets + * this bit. When the HALT_H bit is one, the STOP_H bit is cleared. It is possible to remove the + * halt condition while keeping the SCT in the stop condition (not running) with a single write to + * this register to simultaneously clear the HALT bit and set the STOP bit. Once set, this bit + * can only be cleared by software to restore counter operation. This bit is set on reset. + */ +#define SCT_CTRL_HALT_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_HALT_H_SHIFT)) & SCT_CTRL_HALT_H_MASK) + +#define SCT_CTRL_CLRCTR_H_MASK (0x80000U) +#define SCT_CTRL_CLRCTR_H_SHIFT (19U) +/*! CLRCTR_H - Writing a 1 to this bit clears the H counter. This bit always reads as 0. + */ +#define SCT_CTRL_CLRCTR_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_CLRCTR_H_SHIFT)) & SCT_CTRL_CLRCTR_H_MASK) + +#define SCT_CTRL_BIDIR_H_MASK (0x100000U) +#define SCT_CTRL_BIDIR_H_SHIFT (20U) +/*! BIDIR_H - Direction select + * 0b0..The H counter counts up to its limit condition, then is cleared to zero. + * 0b1..The H counter counts up to its limit, then counts down to a limit condition or to 0. + */ +#define SCT_CTRL_BIDIR_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_BIDIR_H_SHIFT)) & SCT_CTRL_BIDIR_H_MASK) + +#define SCT_CTRL_PRE_H_MASK (0x1FE00000U) +#define SCT_CTRL_PRE_H_SHIFT (21U) +/*! PRE_H - Specifies the factor by which the SCT clock is prescaled to produce the H counter clock. + * The counter clock is clocked at the rate of the SCT clock divided by PRELH+1. Clear the + * counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value. + */ +#define SCT_CTRL_PRE_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_PRE_H_SHIFT)) & SCT_CTRL_PRE_H_MASK) +/*! @} */ + +/*! @name LIMITL - SCT_LIMITL register */ +/*! @{ */ + +#define SCT_LIMITL_LIMITL_MASK (0xFFFFU) +#define SCT_LIMITL_LIMITL_SHIFT (0U) +#define SCT_LIMITL_LIMITL(x) (((uint16_t)(((uint16_t)(x)) << SCT_LIMITL_LIMITL_SHIFT)) & SCT_LIMITL_LIMITL_MASK) +/*! @} */ + +/*! @name LIMITH - SCT_LIMITH register */ +/*! @{ */ + +#define SCT_LIMITH_LIMITH_MASK (0xFFFFU) +#define SCT_LIMITH_LIMITH_SHIFT (0U) +#define SCT_LIMITH_LIMITH(x) (((uint16_t)(((uint16_t)(x)) << SCT_LIMITH_LIMITH_SHIFT)) & SCT_LIMITH_LIMITH_MASK) +/*! @} */ + +/*! @name LIMIT - SCT limit event select register */ +/*! @{ */ + +#define SCT_LIMIT_LIMMSK_L_MASK (0xFFFFU) +#define SCT_LIMIT_LIMMSK_L_SHIFT (0U) +/*! LIMMSK_L - If bit n is one, event n is used as a counter limit for the L or unified counter + * (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT. + */ +#define SCT_LIMIT_LIMMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_LIMIT_LIMMSK_L_SHIFT)) & SCT_LIMIT_LIMMSK_L_MASK) + +#define SCT_LIMIT_LIMMSK_H_MASK (0xFFFF0000U) +#define SCT_LIMIT_LIMMSK_H_SHIFT (16U) +/*! LIMMSK_H - If bit n is one, event n is used as a counter limit for the H counter (event 0 = bit + * 16, event 1 = bit 17, etc.). The number of bits = number of events in this SCT. + */ +#define SCT_LIMIT_LIMMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_LIMIT_LIMMSK_H_SHIFT)) & SCT_LIMIT_LIMMSK_H_MASK) +/*! @} */ + +/*! @name HALTL - SCT_HALTL register */ +/*! @{ */ + +#define SCT_HALTL_HALTL_MASK (0xFFFFU) +#define SCT_HALTL_HALTL_SHIFT (0U) +#define SCT_HALTL_HALTL(x) (((uint16_t)(((uint16_t)(x)) << SCT_HALTL_HALTL_SHIFT)) & SCT_HALTL_HALTL_MASK) +/*! @} */ + +/*! @name HALTH - SCT_HALTH register */ +/*! @{ */ + +#define SCT_HALTH_HALTH_MASK (0xFFFFU) +#define SCT_HALTH_HALTH_SHIFT (0U) +#define SCT_HALTH_HALTH(x) (((uint16_t)(((uint16_t)(x)) << SCT_HALTH_HALTH_SHIFT)) & SCT_HALTH_HALTH_MASK) +/*! @} */ + +/*! @name HALT - SCT halt event select register */ +/*! @{ */ + +#define SCT_HALT_HALTMSK_L_MASK (0xFFFFU) +#define SCT_HALT_HALTMSK_L_SHIFT (0U) +/*! HALTMSK_L - If bit n is one, event n sets the HALT_L bit in the CTRL register (event 0 = bit 0, + * event 1 = bit 1, etc.). The number of bits = number of events in this SCT. + */ +#define SCT_HALT_HALTMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_HALT_HALTMSK_L_SHIFT)) & SCT_HALT_HALTMSK_L_MASK) + +#define SCT_HALT_HALTMSK_H_MASK (0xFFFF0000U) +#define SCT_HALT_HALTMSK_H_SHIFT (16U) +/*! HALTMSK_H - If bit n is one, event n sets the HALT_H bit in the CTRL register (event 0 = bit 16, + * event 1 = bit 17, etc.). The number of bits = number of events in this SCT. + */ +#define SCT_HALT_HALTMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_HALT_HALTMSK_H_SHIFT)) & SCT_HALT_HALTMSK_H_MASK) +/*! @} */ + +/*! @name STOPL - SCT_STOPL register */ +/*! @{ */ + +#define SCT_STOPL_STOPL_MASK (0xFFFFU) +#define SCT_STOPL_STOPL_SHIFT (0U) +#define SCT_STOPL_STOPL(x) (((uint16_t)(((uint16_t)(x)) << SCT_STOPL_STOPL_SHIFT)) & SCT_STOPL_STOPL_MASK) +/*! @} */ + +/*! @name STOPH - SCT_STOPH register */ +/*! @{ */ + +#define SCT_STOPH_STOPH_MASK (0xFFFFU) +#define SCT_STOPH_STOPH_SHIFT (0U) +#define SCT_STOPH_STOPH(x) (((uint16_t)(((uint16_t)(x)) << SCT_STOPH_STOPH_SHIFT)) & SCT_STOPH_STOPH_MASK) +/*! @} */ + +/*! @name STOP - SCT stop event select register */ +/*! @{ */ + +#define SCT_STOP_STOPMSK_L_MASK (0xFFFFU) +#define SCT_STOP_STOPMSK_L_SHIFT (0U) +/*! STOPMSK_L - If bit n is one, event n sets the STOP_L bit in the CTRL register (event 0 = bit 0, + * event 1 = bit 1, etc.). The number of bits = number of events in this SCT. + */ +#define SCT_STOP_STOPMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_STOP_STOPMSK_L_SHIFT)) & SCT_STOP_STOPMSK_L_MASK) + +#define SCT_STOP_STOPMSK_H_MASK (0xFFFF0000U) +#define SCT_STOP_STOPMSK_H_SHIFT (16U) +/*! STOPMSK_H - If bit n is one, event n sets the STOP_H bit in the CTRL register (event 0 = bit 16, + * event 1 = bit 17, etc.). The number of bits = number of events in this SCT. + */ +#define SCT_STOP_STOPMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_STOP_STOPMSK_H_SHIFT)) & SCT_STOP_STOPMSK_H_MASK) +/*! @} */ + +/*! @name STARTL - SCT_STARTL register */ +/*! @{ */ + +#define SCT_STARTL_STARTL_MASK (0xFFFFU) +#define SCT_STARTL_STARTL_SHIFT (0U) +#define SCT_STARTL_STARTL(x) (((uint16_t)(((uint16_t)(x)) << SCT_STARTL_STARTL_SHIFT)) & SCT_STARTL_STARTL_MASK) +/*! @} */ + +/*! @name STARTH - SCT_STARTH register */ +/*! @{ */ + +#define SCT_STARTH_STARTH_MASK (0xFFFFU) +#define SCT_STARTH_STARTH_SHIFT (0U) +#define SCT_STARTH_STARTH(x) (((uint16_t)(((uint16_t)(x)) << SCT_STARTH_STARTH_SHIFT)) & SCT_STARTH_STARTH_MASK) +/*! @} */ + +/*! @name START - SCT start event select register */ +/*! @{ */ + +#define SCT_START_STARTMSK_L_MASK (0xFFFFU) +#define SCT_START_STARTMSK_L_SHIFT (0U) +/*! STARTMSK_L - If bit n is one, event n clears the STOP_L bit in the CTRL register (event 0 = bit + * 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT. + */ +#define SCT_START_STARTMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_START_STARTMSK_L_SHIFT)) & SCT_START_STARTMSK_L_MASK) + +#define SCT_START_STARTMSK_H_MASK (0xFFFF0000U) +#define SCT_START_STARTMSK_H_SHIFT (16U) +/*! STARTMSK_H - If bit n is one, event n clears the STOP_H bit in the CTRL register (event 0 = bit + * 16, event 1 = bit 17, etc.). The number of bits = number of events in this SCT. + */ +#define SCT_START_STARTMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_START_STARTMSK_H_SHIFT)) & SCT_START_STARTMSK_H_MASK) +/*! @} */ + +/*! @name COUNTL - SCT_COUNTL register */ +/*! @{ */ + +#define SCT_COUNTL_COUNTL_MASK (0xFFFFU) +#define SCT_COUNTL_COUNTL_SHIFT (0U) +#define SCT_COUNTL_COUNTL(x) (((uint16_t)(((uint16_t)(x)) << SCT_COUNTL_COUNTL_SHIFT)) & SCT_COUNTL_COUNTL_MASK) +/*! @} */ + +/*! @name COUNTH - SCT_COUNTH register */ +/*! @{ */ + +#define SCT_COUNTH_COUNTH_MASK (0xFFFFU) +#define SCT_COUNTH_COUNTH_SHIFT (0U) +#define SCT_COUNTH_COUNTH(x) (((uint16_t)(((uint16_t)(x)) << SCT_COUNTH_COUNTH_SHIFT)) & SCT_COUNTH_COUNTH_MASK) +/*! @} */ + +/*! @name COUNT - SCT counter register */ +/*! @{ */ + +#define SCT_COUNT_CTR_L_MASK (0xFFFFU) +#define SCT_COUNT_CTR_L_SHIFT (0U) +/*! CTR_L - When UNIFY = 0, read or write the 16-bit L counter value. When UNIFY = 1, read or write + * the lower 16 bits of the 32-bit unified counter. + */ +#define SCT_COUNT_CTR_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_COUNT_CTR_L_SHIFT)) & SCT_COUNT_CTR_L_MASK) + +#define SCT_COUNT_CTR_H_MASK (0xFFFF0000U) +#define SCT_COUNT_CTR_H_SHIFT (16U) +/*! CTR_H - When UNIFY = 0, read or write the 16-bit H counter value. When UNIFY = 1, read or write + * the upper 16 bits of the 32-bit unified counter. + */ +#define SCT_COUNT_CTR_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_COUNT_CTR_H_SHIFT)) & SCT_COUNT_CTR_H_MASK) +/*! @} */ + +/*! @name STATEL - SCT_STATEL register */ +/*! @{ */ + +#define SCT_STATEL_STATEL_MASK (0xFFFFU) +#define SCT_STATEL_STATEL_SHIFT (0U) +#define SCT_STATEL_STATEL(x) (((uint16_t)(((uint16_t)(x)) << SCT_STATEL_STATEL_SHIFT)) & SCT_STATEL_STATEL_MASK) +/*! @} */ + +/*! @name STATEH - SCT_STATEH register */ +/*! @{ */ + +#define SCT_STATEH_STATEH_MASK (0xFFFFU) +#define SCT_STATEH_STATEH_SHIFT (0U) +#define SCT_STATEH_STATEH(x) (((uint16_t)(((uint16_t)(x)) << SCT_STATEH_STATEH_SHIFT)) & SCT_STATEH_STATEH_MASK) +/*! @} */ + +/*! @name STATE - SCT state register */ +/*! @{ */ + +#define SCT_STATE_STATE_L_MASK (0x1FU) +#define SCT_STATE_STATE_L_SHIFT (0U) +/*! STATE_L - State variable. + */ +#define SCT_STATE_STATE_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_STATE_STATE_L_SHIFT)) & SCT_STATE_STATE_L_MASK) + +#define SCT_STATE_STATE_H_MASK (0x1F0000U) +#define SCT_STATE_STATE_H_SHIFT (16U) +/*! STATE_H - State variable. + */ +#define SCT_STATE_STATE_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_STATE_STATE_H_SHIFT)) & SCT_STATE_STATE_H_MASK) +/*! @} */ + +/*! @name INPUT - SCT input register */ +/*! @{ */ + +#define SCT_INPUT_AIN0_MASK (0x1U) +#define SCT_INPUT_AIN0_SHIFT (0U) +/*! AIN0 - Input 0 state. Input 0 state on the last SCT clock edge. + */ +#define SCT_INPUT_AIN0(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN0_SHIFT)) & SCT_INPUT_AIN0_MASK) + +#define SCT_INPUT_AIN1_MASK (0x2U) +#define SCT_INPUT_AIN1_SHIFT (1U) +/*! AIN1 - Input 1 state. Input 1 state on the last SCT clock edge. + */ +#define SCT_INPUT_AIN1(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN1_SHIFT)) & SCT_INPUT_AIN1_MASK) + +#define SCT_INPUT_AIN2_MASK (0x4U) +#define SCT_INPUT_AIN2_SHIFT (2U) +/*! AIN2 - Input 2 state. Input 2 state on the last SCT clock edge. + */ +#define SCT_INPUT_AIN2(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN2_SHIFT)) & SCT_INPUT_AIN2_MASK) + +#define SCT_INPUT_AIN3_MASK (0x8U) +#define SCT_INPUT_AIN3_SHIFT (3U) +/*! AIN3 - Input 3 state. Input 3 state on the last SCT clock edge. + */ +#define SCT_INPUT_AIN3(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN3_SHIFT)) & SCT_INPUT_AIN3_MASK) + +#define SCT_INPUT_AIN4_MASK (0x10U) +#define SCT_INPUT_AIN4_SHIFT (4U) +/*! AIN4 - Input 4 state. Input 4 state on the last SCT clock edge. + */ +#define SCT_INPUT_AIN4(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN4_SHIFT)) & SCT_INPUT_AIN4_MASK) + +#define SCT_INPUT_AIN5_MASK (0x20U) +#define SCT_INPUT_AIN5_SHIFT (5U) +/*! AIN5 - Input 5 state. Input 5 state on the last SCT clock edge. + */ +#define SCT_INPUT_AIN5(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN5_SHIFT)) & SCT_INPUT_AIN5_MASK) + +#define SCT_INPUT_AIN6_MASK (0x40U) +#define SCT_INPUT_AIN6_SHIFT (6U) +/*! AIN6 - Input 6 state. Input 6 state on the last SCT clock edge. + */ +#define SCT_INPUT_AIN6(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN6_SHIFT)) & SCT_INPUT_AIN6_MASK) + +#define SCT_INPUT_AIN7_MASK (0x80U) +#define SCT_INPUT_AIN7_SHIFT (7U) +/*! AIN7 - Input 7 state. Input 7 state on the last SCT clock edge. + */ +#define SCT_INPUT_AIN7(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN7_SHIFT)) & SCT_INPUT_AIN7_MASK) + +#define SCT_INPUT_AIN8_MASK (0x100U) +#define SCT_INPUT_AIN8_SHIFT (8U) +/*! AIN8 - Input 8 state. Input 8 state on the last SCT clock edge. + */ +#define SCT_INPUT_AIN8(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN8_SHIFT)) & SCT_INPUT_AIN8_MASK) + +#define SCT_INPUT_AIN9_MASK (0x200U) +#define SCT_INPUT_AIN9_SHIFT (9U) +/*! AIN9 - Input 9 state. Input 9 state on the last SCT clock edge. + */ +#define SCT_INPUT_AIN9(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN9_SHIFT)) & SCT_INPUT_AIN9_MASK) + +#define SCT_INPUT_AIN10_MASK (0x400U) +#define SCT_INPUT_AIN10_SHIFT (10U) +/*! AIN10 - Input 10 state. Input 10 state on the last SCT clock edge. + */ +#define SCT_INPUT_AIN10(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN10_SHIFT)) & SCT_INPUT_AIN10_MASK) + +#define SCT_INPUT_AIN11_MASK (0x800U) +#define SCT_INPUT_AIN11_SHIFT (11U) +/*! AIN11 - Input 11 state. Input 11 state on the last SCT clock edge. + */ +#define SCT_INPUT_AIN11(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN11_SHIFT)) & SCT_INPUT_AIN11_MASK) + +#define SCT_INPUT_AIN12_MASK (0x1000U) +#define SCT_INPUT_AIN12_SHIFT (12U) +/*! AIN12 - Input 12 state. Input 12 state on the last SCT clock edge. + */ +#define SCT_INPUT_AIN12(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN12_SHIFT)) & SCT_INPUT_AIN12_MASK) + +#define SCT_INPUT_AIN13_MASK (0x2000U) +#define SCT_INPUT_AIN13_SHIFT (13U) +/*! AIN13 - Input 13 state. Input 13 state on the last SCT clock edge. + */ +#define SCT_INPUT_AIN13(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN13_SHIFT)) & SCT_INPUT_AIN13_MASK) + +#define SCT_INPUT_AIN14_MASK (0x4000U) +#define SCT_INPUT_AIN14_SHIFT (14U) +/*! AIN14 - Input 14 state. Input 14 state on the last SCT clock edge. + */ +#define SCT_INPUT_AIN14(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN14_SHIFT)) & SCT_INPUT_AIN14_MASK) + +#define SCT_INPUT_AIN15_MASK (0x8000U) +#define SCT_INPUT_AIN15_SHIFT (15U) +/*! AIN15 - Input 15 state. Input 15 state on the last SCT clock edge. + */ +#define SCT_INPUT_AIN15(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN15_SHIFT)) & SCT_INPUT_AIN15_MASK) + +#define SCT_INPUT_SIN0_MASK (0x10000U) +#define SCT_INPUT_SIN0_SHIFT (16U) +/*! SIN0 - Input 0 state. Input 0 state following the synchronization specified by INSYNC. + */ +#define SCT_INPUT_SIN0(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN0_SHIFT)) & SCT_INPUT_SIN0_MASK) + +#define SCT_INPUT_SIN1_MASK (0x20000U) +#define SCT_INPUT_SIN1_SHIFT (17U) +/*! SIN1 - Input 1 state. Input 1 state following the synchronization specified by INSYNC. + */ +#define SCT_INPUT_SIN1(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN1_SHIFT)) & SCT_INPUT_SIN1_MASK) + +#define SCT_INPUT_SIN2_MASK (0x40000U) +#define SCT_INPUT_SIN2_SHIFT (18U) +/*! SIN2 - Input 2 state. Input 2 state following the synchronization specified by INSYNC. + */ +#define SCT_INPUT_SIN2(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN2_SHIFT)) & SCT_INPUT_SIN2_MASK) + +#define SCT_INPUT_SIN3_MASK (0x80000U) +#define SCT_INPUT_SIN3_SHIFT (19U) +/*! SIN3 - Input 3 state. Input 3 state following the synchronization specified by INSYNC. + */ +#define SCT_INPUT_SIN3(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN3_SHIFT)) & SCT_INPUT_SIN3_MASK) + +#define SCT_INPUT_SIN4_MASK (0x100000U) +#define SCT_INPUT_SIN4_SHIFT (20U) +/*! SIN4 - Input 4 state. Input 4 state following the synchronization specified by INSYNC. + */ +#define SCT_INPUT_SIN4(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN4_SHIFT)) & SCT_INPUT_SIN4_MASK) + +#define SCT_INPUT_SIN5_MASK (0x200000U) +#define SCT_INPUT_SIN5_SHIFT (21U) +/*! SIN5 - Input 5 state. Input 5 state following the synchronization specified by INSYNC. + */ +#define SCT_INPUT_SIN5(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN5_SHIFT)) & SCT_INPUT_SIN5_MASK) + +#define SCT_INPUT_SIN6_MASK (0x400000U) +#define SCT_INPUT_SIN6_SHIFT (22U) +/*! SIN6 - Input 6 state. Input 6 state following the synchronization specified by INSYNC. + */ +#define SCT_INPUT_SIN6(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN6_SHIFT)) & SCT_INPUT_SIN6_MASK) + +#define SCT_INPUT_SIN7_MASK (0x800000U) +#define SCT_INPUT_SIN7_SHIFT (23U) +/*! SIN7 - Input 7 state. Input 7 state following the synchronization specified by INSYNC. + */ +#define SCT_INPUT_SIN7(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN7_SHIFT)) & SCT_INPUT_SIN7_MASK) + +#define SCT_INPUT_SIN8_MASK (0x1000000U) +#define SCT_INPUT_SIN8_SHIFT (24U) +/*! SIN8 - Input 8 state. Input 8 state following the synchronization specified by INSYNC. + */ +#define SCT_INPUT_SIN8(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN8_SHIFT)) & SCT_INPUT_SIN8_MASK) + +#define SCT_INPUT_SIN9_MASK (0x2000000U) +#define SCT_INPUT_SIN9_SHIFT (25U) +/*! SIN9 - Input 9 state. Input 9 state following the synchronization specified by INSYNC. + */ +#define SCT_INPUT_SIN9(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN9_SHIFT)) & SCT_INPUT_SIN9_MASK) + +#define SCT_INPUT_SIN10_MASK (0x4000000U) +#define SCT_INPUT_SIN10_SHIFT (26U) +/*! SIN10 - Input 10 state. Input 10 state following the synchronization specified by INSYNC. + */ +#define SCT_INPUT_SIN10(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN10_SHIFT)) & SCT_INPUT_SIN10_MASK) + +#define SCT_INPUT_SIN11_MASK (0x8000000U) +#define SCT_INPUT_SIN11_SHIFT (27U) +/*! SIN11 - Input 11 state. Input 11 state following the synchronization specified by INSYNC. + */ +#define SCT_INPUT_SIN11(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN11_SHIFT)) & SCT_INPUT_SIN11_MASK) + +#define SCT_INPUT_SIN12_MASK (0x10000000U) +#define SCT_INPUT_SIN12_SHIFT (28U) +/*! SIN12 - Input 12 state. Input 12 state following the synchronization specified by INSYNC. + */ +#define SCT_INPUT_SIN12(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN12_SHIFT)) & SCT_INPUT_SIN12_MASK) + +#define SCT_INPUT_SIN13_MASK (0x20000000U) +#define SCT_INPUT_SIN13_SHIFT (29U) +/*! SIN13 - Input 13 state. Input 13 state following the synchronization specified by INSYNC. + */ +#define SCT_INPUT_SIN13(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN13_SHIFT)) & SCT_INPUT_SIN13_MASK) + +#define SCT_INPUT_SIN14_MASK (0x40000000U) +#define SCT_INPUT_SIN14_SHIFT (30U) +/*! SIN14 - Input 14 state. Input 14 state following the synchronization specified by INSYNC. + */ +#define SCT_INPUT_SIN14(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN14_SHIFT)) & SCT_INPUT_SIN14_MASK) + +#define SCT_INPUT_SIN15_MASK (0x80000000U) +#define SCT_INPUT_SIN15_SHIFT (31U) +/*! SIN15 - Input 15 state. Input 15 state following the synchronization specified by INSYNC. + */ +#define SCT_INPUT_SIN15(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN15_SHIFT)) & SCT_INPUT_SIN15_MASK) +/*! @} */ + +/*! @name REGMODEL - SCT_REGMODEL register */ +/*! @{ */ + +#define SCT_REGMODEL_REGMODEL_MASK (0xFFFFU) +#define SCT_REGMODEL_REGMODEL_SHIFT (0U) +#define SCT_REGMODEL_REGMODEL(x) (((uint16_t)(((uint16_t)(x)) << SCT_REGMODEL_REGMODEL_SHIFT)) & SCT_REGMODEL_REGMODEL_MASK) +/*! @} */ + +/*! @name REGMODEH - SCT_REGMODEH register */ +/*! @{ */ + +#define SCT_REGMODEH_REGMODEH_MASK (0xFFFFU) +#define SCT_REGMODEH_REGMODEH_SHIFT (0U) +#define SCT_REGMODEH_REGMODEH(x) (((uint16_t)(((uint16_t)(x)) << SCT_REGMODEH_REGMODEH_SHIFT)) & SCT_REGMODEH_REGMODEH_MASK) +/*! @} */ + +/*! @name REGMODE - SCT match/capture mode register */ +/*! @{ */ + +#define SCT_REGMODE_REGMOD_L_MASK (0xFFFFU) +#define SCT_REGMODE_REGMOD_L_SHIFT (0U) +/*! REGMOD_L - Each bit controls one match/capture register (register 0 = bit 0, register 1 = bit 1, + * etc.). The number of bits = number of match/captures in this SCT. 0 = register operates as + * match register. 1 = register operates as capture register. + */ +#define SCT_REGMODE_REGMOD_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L_SHIFT)) & SCT_REGMODE_REGMOD_L_MASK) + +#define SCT_REGMODE_REGMOD_H_MASK (0xFFFF0000U) +#define SCT_REGMODE_REGMOD_H_SHIFT (16U) +/*! REGMOD_H - Each bit controls one match/capture register (register 0 = bit 16, register 1 = bit + * 17, etc.). The number of bits = number of match/captures in this SCT. 0 = register operates as + * match registers. 1 = register operates as capture registers. + */ +#define SCT_REGMODE_REGMOD_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H_SHIFT)) & SCT_REGMODE_REGMOD_H_MASK) +/*! @} */ + +/*! @name OUTPUT - SCT output register */ +/*! @{ */ + +#define SCT_OUTPUT_OUT_MASK (0xFFFFU) +#define SCT_OUTPUT_OUT_SHIFT (0U) +/*! OUT - Writing a 1 to bit n forces the corresponding output HIGH. Writing a 0 forces the + * corresponding output LOW (output 0 = bit 0, output 1 = bit 1, etc.). The number of bits = number of + * outputs in this SCT. + */ +#define SCT_OUTPUT_OUT(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUT_OUT_SHIFT)) & SCT_OUTPUT_OUT_MASK) +/*! @} */ + +/*! @name OUTPUTDIRCTRL - SCT output counter direction control register */ +/*! @{ */ + +#define SCT_OUTPUTDIRCTRL_SETCLR0_MASK (0x3U) +#define SCT_OUTPUTDIRCTRL_SETCLR0_SHIFT (0U) +/*! SETCLR0 - Set/clear operation on output 0. Value 0x3 is reserved. Do not program this value. + * 0b00..Set and clear do not depend on the direction of any counter. + * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. + * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + */ +#define SCT_OUTPUTDIRCTRL_SETCLR0(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR0_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR0_MASK) + +#define SCT_OUTPUTDIRCTRL_SETCLR1_MASK (0xCU) +#define SCT_OUTPUTDIRCTRL_SETCLR1_SHIFT (2U) +/*! SETCLR1 - Set/clear operation on output 1. Value 0x3 is reserved. Do not program this value. + * 0b00..Set and clear do not depend on the direction of any counter. + * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. + * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + */ +#define SCT_OUTPUTDIRCTRL_SETCLR1(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR1_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR1_MASK) + +#define SCT_OUTPUTDIRCTRL_SETCLR2_MASK (0x30U) +#define SCT_OUTPUTDIRCTRL_SETCLR2_SHIFT (4U) +/*! SETCLR2 - Set/clear operation on output 2. Value 0x3 is reserved. Do not program this value. + * 0b00..Set and clear do not depend on the direction of any counter. + * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. + * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + */ +#define SCT_OUTPUTDIRCTRL_SETCLR2(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR2_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR2_MASK) + +#define SCT_OUTPUTDIRCTRL_SETCLR3_MASK (0xC0U) +#define SCT_OUTPUTDIRCTRL_SETCLR3_SHIFT (6U) +/*! SETCLR3 - Set/clear operation on output 3. Value 0x3 is reserved. Do not program this value. + * 0b00..Set and clear do not depend on the direction of any counter. + * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. + * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + */ +#define SCT_OUTPUTDIRCTRL_SETCLR3(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR3_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR3_MASK) + +#define SCT_OUTPUTDIRCTRL_SETCLR4_MASK (0x300U) +#define SCT_OUTPUTDIRCTRL_SETCLR4_SHIFT (8U) +/*! SETCLR4 - Set/clear operation on output 4. Value 0x3 is reserved. Do not program this value. + * 0b00..Set and clear do not depend on the direction of any counter. + * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. + * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + */ +#define SCT_OUTPUTDIRCTRL_SETCLR4(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR4_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR4_MASK) + +#define SCT_OUTPUTDIRCTRL_SETCLR5_MASK (0xC00U) +#define SCT_OUTPUTDIRCTRL_SETCLR5_SHIFT (10U) +/*! SETCLR5 - Set/clear operation on output 5. Value 0x3 is reserved. Do not program this value. + * 0b00..Set and clear do not depend on the direction of any counter. + * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. + * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + */ +#define SCT_OUTPUTDIRCTRL_SETCLR5(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR5_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR5_MASK) + +#define SCT_OUTPUTDIRCTRL_SETCLR6_MASK (0x3000U) +#define SCT_OUTPUTDIRCTRL_SETCLR6_SHIFT (12U) +/*! SETCLR6 - Set/clear operation on output 6. Value 0x3 is reserved. Do not program this value. + * 0b00..Set and clear do not depend on the direction of any counter. + * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. + * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + */ +#define SCT_OUTPUTDIRCTRL_SETCLR6(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR6_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR6_MASK) + +#define SCT_OUTPUTDIRCTRL_SETCLR7_MASK (0xC000U) +#define SCT_OUTPUTDIRCTRL_SETCLR7_SHIFT (14U) +/*! SETCLR7 - Set/clear operation on output 7. Value 0x3 is reserved. Do not program this value. + * 0b00..Set and clear do not depend on the direction of any counter. + * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. + * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + */ +#define SCT_OUTPUTDIRCTRL_SETCLR7(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR7_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR7_MASK) + +#define SCT_OUTPUTDIRCTRL_SETCLR8_MASK (0x30000U) +#define SCT_OUTPUTDIRCTRL_SETCLR8_SHIFT (16U) +/*! SETCLR8 - Set/clear operation on output 8. Value 0x3 is reserved. Do not program this value. + * 0b00..Set and clear do not depend on the direction of any counter. + * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. + * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + */ +#define SCT_OUTPUTDIRCTRL_SETCLR8(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR8_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR8_MASK) + +#define SCT_OUTPUTDIRCTRL_SETCLR9_MASK (0xC0000U) +#define SCT_OUTPUTDIRCTRL_SETCLR9_SHIFT (18U) +/*! SETCLR9 - Set/clear operation on output 9. Value 0x3 is reserved. Do not program this value. + * 0b00..Set and clear do not depend on the direction of any counter. + * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. + * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + */ +#define SCT_OUTPUTDIRCTRL_SETCLR9(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR9_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR9_MASK) + +#define SCT_OUTPUTDIRCTRL_SETCLR10_MASK (0x300000U) +#define SCT_OUTPUTDIRCTRL_SETCLR10_SHIFT (20U) +/*! SETCLR10 - Set/clear operation on output 10. Value 0x3 is reserved. Do not program this value. + * 0b00..Set and clear do not depend on the direction of any counter. + * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. + * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + */ +#define SCT_OUTPUTDIRCTRL_SETCLR10(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR10_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR10_MASK) + +#define SCT_OUTPUTDIRCTRL_SETCLR11_MASK (0xC00000U) +#define SCT_OUTPUTDIRCTRL_SETCLR11_SHIFT (22U) +/*! SETCLR11 - Set/clear operation on output 11. Value 0x3 is reserved. Do not program this value. + * 0b00..Set and clear do not depend on the direction of any counter. + * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. + * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + */ +#define SCT_OUTPUTDIRCTRL_SETCLR11(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR11_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR11_MASK) + +#define SCT_OUTPUTDIRCTRL_SETCLR12_MASK (0x3000000U) +#define SCT_OUTPUTDIRCTRL_SETCLR12_SHIFT (24U) +/*! SETCLR12 - Set/clear operation on output 12. Value 0x3 is reserved. Do not program this value. + * 0b00..Set and clear do not depend on the direction of any counter. + * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. + * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + */ +#define SCT_OUTPUTDIRCTRL_SETCLR12(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR12_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR12_MASK) + +#define SCT_OUTPUTDIRCTRL_SETCLR13_MASK (0xC000000U) +#define SCT_OUTPUTDIRCTRL_SETCLR13_SHIFT (26U) +/*! SETCLR13 - Set/clear operation on output 13. Value 0x3 is reserved. Do not program this value. + * 0b00..Set and clear do not depend on the direction of any counter. + * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. + * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + */ +#define SCT_OUTPUTDIRCTRL_SETCLR13(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR13_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR13_MASK) + +#define SCT_OUTPUTDIRCTRL_SETCLR14_MASK (0x30000000U) +#define SCT_OUTPUTDIRCTRL_SETCLR14_SHIFT (28U) +/*! SETCLR14 - Set/clear operation on output 14. Value 0x3 is reserved. Do not program this value. + * 0b00..Set and clear do not depend on the direction of any counter. + * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. + * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + */ +#define SCT_OUTPUTDIRCTRL_SETCLR14(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR14_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR14_MASK) + +#define SCT_OUTPUTDIRCTRL_SETCLR15_MASK (0xC0000000U) +#define SCT_OUTPUTDIRCTRL_SETCLR15_SHIFT (30U) +/*! SETCLR15 - Set/clear operation on output 15. Value 0x3 is reserved. Do not program this value. + * 0b00..Set and clear do not depend on the direction of any counter. + * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. + * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + */ +#define SCT_OUTPUTDIRCTRL_SETCLR15(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR15_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR15_MASK) +/*! @} */ + +/*! @name RES - SCT conflict resolution register */ +/*! @{ */ + +#define SCT_RES_O0RES_MASK (0x3U) +#define SCT_RES_O0RES_SHIFT (0U) +/*! O0RES - Effect of simultaneous set and clear on output 0. + * 0b00..No change. + * 0b01..Set output (or clear based on the SETCLR0 field in the OUTPUTDIRCTRL register). + * 0b10..Clear output (or set based on the SETCLR0 field). + * 0b11..Toggle output. + */ +#define SCT_RES_O0RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O0RES_SHIFT)) & SCT_RES_O0RES_MASK) + +#define SCT_RES_O1RES_MASK (0xCU) +#define SCT_RES_O1RES_SHIFT (2U) +/*! O1RES - Effect of simultaneous set and clear on output 1. + * 0b00..No change. + * 0b01..Set output (or clear based on the SETCLR1 field in the OUTPUTDIRCTRL register). + * 0b10..Clear output (or set based on the SETCLR1 field). + * 0b11..Toggle output. + */ +#define SCT_RES_O1RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O1RES_SHIFT)) & SCT_RES_O1RES_MASK) + +#define SCT_RES_O2RES_MASK (0x30U) +#define SCT_RES_O2RES_SHIFT (4U) +/*! O2RES - Effect of simultaneous set and clear on output 2. + * 0b00..No change. + * 0b01..Set output (or clear based on the SETCLR2 field in the OUTPUTDIRCTRL register). + * 0b10..Clear output n (or set based on the SETCLR2 field). + * 0b11..Toggle output. + */ +#define SCT_RES_O2RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O2RES_SHIFT)) & SCT_RES_O2RES_MASK) + +#define SCT_RES_O3RES_MASK (0xC0U) +#define SCT_RES_O3RES_SHIFT (6U) +/*! O3RES - Effect of simultaneous set and clear on output 3. + * 0b00..No change. + * 0b01..Set output (or clear based on the SETCLR3 field in the OUTPUTDIRCTRL register). + * 0b10..Clear output (or set based on the SETCLR3 field). + * 0b11..Toggle output. + */ +#define SCT_RES_O3RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O3RES_SHIFT)) & SCT_RES_O3RES_MASK) + +#define SCT_RES_O4RES_MASK (0x300U) +#define SCT_RES_O4RES_SHIFT (8U) +/*! O4RES - Effect of simultaneous set and clear on output 4. + * 0b00..No change. + * 0b01..Set output (or clear based on the SETCLR4 field in the OUTPUTDIRCTRL register). + * 0b10..Clear output (or set based on the SETCLR4 field). + * 0b11..Toggle output. + */ +#define SCT_RES_O4RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O4RES_SHIFT)) & SCT_RES_O4RES_MASK) + +#define SCT_RES_O5RES_MASK (0xC00U) +#define SCT_RES_O5RES_SHIFT (10U) +/*! O5RES - Effect of simultaneous set and clear on output 5. + * 0b00..No change. + * 0b01..Set output (or clear based on the SETCLR5 field in the OUTPUTDIRCTRL register). + * 0b10..Clear output (or set based on the SETCLR5 field). + * 0b11..Toggle output. + */ +#define SCT_RES_O5RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O5RES_SHIFT)) & SCT_RES_O5RES_MASK) + +#define SCT_RES_O6RES_MASK (0x3000U) +#define SCT_RES_O6RES_SHIFT (12U) +/*! O6RES - Effect of simultaneous set and clear on output 6. + * 0b00..No change. + * 0b01..Set output (or clear based on the SETCLR6 field in the OUTPUTDIRCTRL register). + * 0b10..Clear output (or set based on the SETCLR6 field). + * 0b11..Toggle output. + */ +#define SCT_RES_O6RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O6RES_SHIFT)) & SCT_RES_O6RES_MASK) + +#define SCT_RES_O7RES_MASK (0xC000U) +#define SCT_RES_O7RES_SHIFT (14U) +/*! O7RES - Effect of simultaneous set and clear on output 7. + * 0b00..No change. + * 0b01..Set output (or clear based on the SETCLR7 field in the OUTPUTDIRCTRL register). + * 0b10..Clear output n (or set based on the SETCLR7 field). + * 0b11..Toggle output. + */ +#define SCT_RES_O7RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O7RES_SHIFT)) & SCT_RES_O7RES_MASK) + +#define SCT_RES_O8RES_MASK (0x30000U) +#define SCT_RES_O8RES_SHIFT (16U) +/*! O8RES - Effect of simultaneous set and clear on output 8. + * 0b00..No change. + * 0b01..Set output (or clear based on the SETCLR8 field in the OUTPUTDIRCTRL register). + * 0b10..Clear output (or set based on the SETCLR8 field). + * 0b11..Toggle output. + */ +#define SCT_RES_O8RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O8RES_SHIFT)) & SCT_RES_O8RES_MASK) + +#define SCT_RES_O9RES_MASK (0xC0000U) +#define SCT_RES_O9RES_SHIFT (18U) +/*! O9RES - Effect of simultaneous set and clear on output 9. + * 0b00..No change. + * 0b01..Set output (or clear based on the SETCLR9 field in the OUTPUTDIRCTRL register). + * 0b10..Clear output (or set based on the SETCLR9 field). + * 0b11..Toggle output. + */ +#define SCT_RES_O9RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O9RES_SHIFT)) & SCT_RES_O9RES_MASK) + +#define SCT_RES_O10RES_MASK (0x300000U) +#define SCT_RES_O10RES_SHIFT (20U) +/*! O10RES - Effect of simultaneous set and clear on output 10. + * 0b00..No change. + * 0b01..Set output (or clear based on the SETCLR10 field in the OUTPUTDIRCTRL register). + * 0b10..Clear output (or set based on the SETCLR10 field). + * 0b11..Toggle output. + */ +#define SCT_RES_O10RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O10RES_SHIFT)) & SCT_RES_O10RES_MASK) + +#define SCT_RES_O11RES_MASK (0xC00000U) +#define SCT_RES_O11RES_SHIFT (22U) +/*! O11RES - Effect of simultaneous set and clear on output 11. + * 0b00..No change. + * 0b01..Set output (or clear based on the SETCLR11 field in the OUTPUTDIRCTRL register). + * 0b10..Clear output (or set based on the SETCLR11 field). + * 0b11..Toggle output. + */ +#define SCT_RES_O11RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O11RES_SHIFT)) & SCT_RES_O11RES_MASK) + +#define SCT_RES_O12RES_MASK (0x3000000U) +#define SCT_RES_O12RES_SHIFT (24U) +/*! O12RES - Effect of simultaneous set and clear on output 12. + * 0b00..No change. + * 0b01..Set output (or clear based on the SETCLR12 field in the OUTPUTDIRCTRL register). + * 0b10..Clear output (or set based on the SETCLR12 field). + * 0b11..Toggle output. + */ +#define SCT_RES_O12RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O12RES_SHIFT)) & SCT_RES_O12RES_MASK) + +#define SCT_RES_O13RES_MASK (0xC000000U) +#define SCT_RES_O13RES_SHIFT (26U) +/*! O13RES - Effect of simultaneous set and clear on output 13. + * 0b00..No change. + * 0b01..Set output (or clear based on the SETCLR13 field in the OUTPUTDIRCTRL register). + * 0b10..Clear output (or set based on the SETCLR13 field). + * 0b11..Toggle output. + */ +#define SCT_RES_O13RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O13RES_SHIFT)) & SCT_RES_O13RES_MASK) + +#define SCT_RES_O14RES_MASK (0x30000000U) +#define SCT_RES_O14RES_SHIFT (28U) +/*! O14RES - Effect of simultaneous set and clear on output 14. + * 0b00..No change. + * 0b01..Set output (or clear based on the SETCLR14 field in the OUTPUTDIRCTRL register). + * 0b10..Clear output (or set based on the SETCLR14 field). + * 0b11..Toggle output. + */ +#define SCT_RES_O14RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O14RES_SHIFT)) & SCT_RES_O14RES_MASK) + +#define SCT_RES_O15RES_MASK (0xC0000000U) +#define SCT_RES_O15RES_SHIFT (30U) +/*! O15RES - Effect of simultaneous set and clear on output 15. + * 0b00..No change. + * 0b01..Set output (or clear based on the SETCLR15 field in the OUTPUTDIRCTRL register). + * 0b10..Clear output (or set based on the SETCLR15 field). + * 0b11..Toggle output. + */ +#define SCT_RES_O15RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O15RES_SHIFT)) & SCT_RES_O15RES_MASK) +/*! @} */ + +/*! @name DMAREQ0 - SCT DMA request 0 register */ +/*! @{ */ + +#define SCT_DMAREQ0_DEV_0_MASK (0xFFFFU) +#define SCT_DMAREQ0_DEV_0_SHIFT (0U) +/*! DEV_0 - If bit n is one, event n triggers DMA request 0 (event 0 = bit 0, event 1 = bit 1, + * etc.). The number of bits = number of events in this SCT. + */ +#define SCT_DMAREQ0_DEV_0(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_0_SHIFT)) & SCT_DMAREQ0_DEV_0_MASK) + +#define SCT_DMAREQ0_DRL0_MASK (0x40000000U) +#define SCT_DMAREQ0_DRL0_SHIFT (30U) +/*! DRL0 - A 1 in this bit triggers DMA request 0 when it loads the MATCH_L/Unified registers from the RELOAD_L/Unified registers. + */ +#define SCT_DMAREQ0_DRL0(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DRL0_SHIFT)) & SCT_DMAREQ0_DRL0_MASK) + +#define SCT_DMAREQ0_DRQ0_MASK (0x80000000U) +#define SCT_DMAREQ0_DRQ0_SHIFT (31U) +/*! DRQ0 - This read-only bit indicates the state of DMA Request 0. Note that if the related DMA + * channel is enabled and properly set up, it is unlikely that software will see this flag, it will + * be cleared rapidly by the DMA service. The flag remaining set could point to an issue with DMA + * setup. + */ +#define SCT_DMAREQ0_DRQ0(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DRQ0_SHIFT)) & SCT_DMAREQ0_DRQ0_MASK) +/*! @} */ + +/*! @name DMAREQ1 - SCT DMA request 1 register */ +/*! @{ */ + +#define SCT_DMAREQ1_DEV_1_MASK (0xFFFFU) +#define SCT_DMAREQ1_DEV_1_SHIFT (0U) +/*! DEV_1 - If bit n is one, event n triggers DMA request 1 (event 0 = bit 0, event 1 = bit 1, + * etc.). The number of bits = number of events in this SCT. + */ +#define SCT_DMAREQ1_DEV_1(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_1_SHIFT)) & SCT_DMAREQ1_DEV_1_MASK) + +#define SCT_DMAREQ1_DRL1_MASK (0x40000000U) +#define SCT_DMAREQ1_DRL1_SHIFT (30U) +/*! DRL1 - A 1 in this bit triggers DMA request 1 when it loads the Match L/Unified registers from the Reload L/Unified registers. + */ +#define SCT_DMAREQ1_DRL1(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DRL1_SHIFT)) & SCT_DMAREQ1_DRL1_MASK) + +#define SCT_DMAREQ1_DRQ1_MASK (0x80000000U) +#define SCT_DMAREQ1_DRQ1_SHIFT (31U) +/*! DRQ1 - This read-only bit indicates the state of DMA Request 1. Note that if the related DMA + * channel is enabled and properly set up, it is unlikely that software will see this flag, it will + * be cleared rapidly by the DMA service. The flag remaining set could point to an issue with DMA + * setup. + */ +#define SCT_DMAREQ1_DRQ1(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DRQ1_SHIFT)) & SCT_DMAREQ1_DRQ1_MASK) +/*! @} */ + +/*! @name EVEN - SCT event interrupt enable register */ +/*! @{ */ + +#define SCT_EVEN_IEN_MASK (0xFFFFU) +#define SCT_EVEN_IEN_SHIFT (0U) +/*! IEN - The SCT requests an interrupt when bit n of this register and the event flag register are + * both one (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in + * this SCT. + */ +#define SCT_EVEN_IEN(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN_SHIFT)) & SCT_EVEN_IEN_MASK) +/*! @} */ + +/*! @name EVFLAG - SCT event flag register */ +/*! @{ */ + +#define SCT_EVFLAG_FLAG_MASK (0xFFFFU) +#define SCT_EVFLAG_FLAG_SHIFT (0U) +/*! FLAG - Bit n is one if event n has occurred since reset or a 1 was last written to this bit + * (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT. + */ +#define SCT_EVFLAG_FLAG(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG_SHIFT)) & SCT_EVFLAG_FLAG_MASK) +/*! @} */ + +/*! @name CONEN - SCT conflict interrupt enable register */ +/*! @{ */ + +#define SCT_CONEN_NCEN_MASK (0xFFFFU) +#define SCT_CONEN_NCEN_SHIFT (0U) +/*! NCEN - The SCT requests an interrupt when bit n of this register and the SCT conflict flag + * register are both one (output 0 = bit 0, output 1 = bit 1, etc.). The number of bits = number of + * outputs in this SCT. + */ +#define SCT_CONEN_NCEN(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONEN_NCEN_SHIFT)) & SCT_CONEN_NCEN_MASK) +/*! @} */ + +/*! @name CONFLAG - SCT conflict flag register */ +/*! @{ */ + +#define SCT_CONFLAG_NCFLAG_MASK (0xFFFFU) +#define SCT_CONFLAG_NCFLAG_SHIFT (0U) +/*! NCFLAG - Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was + * last written to this bit (output 0 = bit 0, output 1 = bit 1, etc.). The number of bits = + * number of outputs in this SCT. + */ +#define SCT_CONFLAG_NCFLAG(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_NCFLAG_SHIFT)) & SCT_CONFLAG_NCFLAG_MASK) + +#define SCT_CONFLAG_BUSERRL_MASK (0x40000000U) +#define SCT_CONFLAG_BUSERRL_SHIFT (30U) +/*! BUSERRL - The most recent bus error from this SCT involved writing CTR L/Unified, STATE + * L/Unified, MATCH L/Unified, or the Output register when the L/U counter was not halted. A word write + * to certain L and H registers can be half successful and half unsuccessful. + */ +#define SCT_CONFLAG_BUSERRL(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_BUSERRL_SHIFT)) & SCT_CONFLAG_BUSERRL_MASK) + +#define SCT_CONFLAG_BUSERRH_MASK (0x80000000U) +#define SCT_CONFLAG_BUSERRH_SHIFT (31U) +/*! BUSERRH - The most recent bus error from this SCT involved writing CTR H, STATE H, MATCH H, or + * the Output register when the H counter was not halted. + */ +#define SCT_CONFLAG_BUSERRH(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_BUSERRH_SHIFT)) & SCT_CONFLAG_BUSERRH_MASK) +/*! @} */ + +/*! @name CAPL - SCT_CAPL register */ +/*! @{ */ + +#define SCT_CAPL_CAPL_MASK (0xFFFFU) +#define SCT_CAPL_CAPL_SHIFT (0U) +#define SCT_CAPL_CAPL(x) (((uint16_t)(((uint16_t)(x)) << SCT_CAPL_CAPL_SHIFT)) & SCT_CAPL_CAPL_MASK) +/*! @} */ + +/* The count of SCT_CAPL */ +#define SCT_CAPL_COUNT (16U) + +/*! @name CAPH - SCT_CAPH register */ +/*! @{ */ + +#define SCT_CAPH_CAPH_MASK (0xFFFFU) +#define SCT_CAPH_CAPH_SHIFT (0U) +#define SCT_CAPH_CAPH(x) (((uint16_t)(((uint16_t)(x)) << SCT_CAPH_CAPH_SHIFT)) & SCT_CAPH_CAPH_MASK) +/*! @} */ + +/* The count of SCT_CAPH */ +#define SCT_CAPH_COUNT (16U) + +/*! @name CAP - SCT capture register of capture channel */ +/*! @{ */ + +#define SCT_CAP_CAPn_L_MASK (0xFFFFU) +#define SCT_CAP_CAPn_L_SHIFT (0U) +/*! CAPn_L - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. + * When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last + * captured. + */ +#define SCT_CAP_CAPn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CAP_CAPn_L_SHIFT)) & SCT_CAP_CAPn_L_MASK) + +#define SCT_CAP_CAPn_H_MASK (0xFFFF0000U) +#define SCT_CAP_CAPn_H_SHIFT (16U) +/*! CAPn_H - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. + * When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last + * captured. + */ +#define SCT_CAP_CAPn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CAP_CAPn_H_SHIFT)) & SCT_CAP_CAPn_H_MASK) +/*! @} */ + +/* The count of SCT_CAP */ +#define SCT_CAP_COUNT (16U) + +/*! @name MATCHL - SCT_MATCHL register */ +/*! @{ */ + +#define SCT_MATCHL_MATCHL_MASK (0xFFFFU) +#define SCT_MATCHL_MATCHL_SHIFT (0U) +#define SCT_MATCHL_MATCHL(x) (((uint16_t)(((uint16_t)(x)) << SCT_MATCHL_MATCHL_SHIFT)) & SCT_MATCHL_MATCHL_MASK) +/*! @} */ + +/* The count of SCT_MATCHL */ +#define SCT_MATCHL_COUNT (16U) + +/*! @name MATCHH - SCT_MATCHH register */ +/*! @{ */ + +#define SCT_MATCHH_MATCHH_MASK (0xFFFFU) +#define SCT_MATCHH_MATCHH_SHIFT (0U) +#define SCT_MATCHH_MATCHH(x) (((uint16_t)(((uint16_t)(x)) << SCT_MATCHH_MATCHH_SHIFT)) & SCT_MATCHH_MATCHH_MASK) +/*! @} */ + +/* The count of SCT_MATCHH */ +#define SCT_MATCHH_COUNT (16U) + +/*! @name MATCH - SCT match value register of match channels */ +/*! @{ */ + +#define SCT_MATCH_MATCHn_L_MASK (0xFFFFU) +#define SCT_MATCH_MATCHn_L_SHIFT (0U) +/*! MATCHn_L - When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When + * UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified + * counter. + */ +#define SCT_MATCH_MATCHn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_MATCH_MATCHn_L_SHIFT)) & SCT_MATCH_MATCHn_L_MASK) + +#define SCT_MATCH_MATCHn_H_MASK (0xFFFF0000U) +#define SCT_MATCH_MATCHn_H_SHIFT (16U) +/*! MATCHn_H - When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When + * UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified + * counter. + */ +#define SCT_MATCH_MATCHn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_MATCH_MATCHn_H_SHIFT)) & SCT_MATCH_MATCHn_H_MASK) +/*! @} */ + +/* The count of SCT_MATCH */ +#define SCT_MATCH_COUNT (16U) + +/*! @name CAPCTRLL - SCT_CAPCTRLL register */ +/*! @{ */ + +#define SCT_CAPCTRLL_CAPCTRLL_MASK (0xFFFFU) +#define SCT_CAPCTRLL_CAPCTRLL_SHIFT (0U) +#define SCT_CAPCTRLL_CAPCTRLL(x) (((uint16_t)(((uint16_t)(x)) << SCT_CAPCTRLL_CAPCTRLL_SHIFT)) & SCT_CAPCTRLL_CAPCTRLL_MASK) +/*! @} */ + +/* The count of SCT_CAPCTRLL */ +#define SCT_CAPCTRLL_COUNT (16U) + +/*! @name CAPCTRLH - SCT_CAPCTRLH register */ +/*! @{ */ + +#define SCT_CAPCTRLH_CAPCTRLH_MASK (0xFFFFU) +#define SCT_CAPCTRLH_CAPCTRLH_SHIFT (0U) +#define SCT_CAPCTRLH_CAPCTRLH(x) (((uint16_t)(((uint16_t)(x)) << SCT_CAPCTRLH_CAPCTRLH_SHIFT)) & SCT_CAPCTRLH_CAPCTRLH_MASK) +/*! @} */ + +/* The count of SCT_CAPCTRLH */ +#define SCT_CAPCTRLH_COUNT (16U) + +/*! @name CAPCTRL - SCT capture control register */ +/*! @{ */ + +#define SCT_CAPCTRL_CAPCONn_L_MASK (0xFFFFU) +#define SCT_CAPCTRL_CAPCONn_L_SHIFT (0U) +/*! CAPCONn_L - If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) + * register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of + * match/captures in this SCT. + */ +#define SCT_CAPCTRL_CAPCONn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CAPCTRL_CAPCONn_L_SHIFT)) & SCT_CAPCTRL_CAPCONn_L_MASK) + +#define SCT_CAPCTRL_CAPCONn_H_MASK (0xFFFF0000U) +#define SCT_CAPCTRL_CAPCONn_H_SHIFT (16U) +/*! CAPCONn_H - If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event + * 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. + */ +#define SCT_CAPCTRL_CAPCONn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CAPCTRL_CAPCONn_H_SHIFT)) & SCT_CAPCTRL_CAPCONn_H_MASK) +/*! @} */ + +/* The count of SCT_CAPCTRL */ +#define SCT_CAPCTRL_COUNT (16U) + +/*! @name MATCHRELL - SCT_MATCHRELL register */ +/*! @{ */ + +#define SCT_MATCHRELL_MATCHRELL_MASK (0xFFFFU) +#define SCT_MATCHRELL_MATCHRELL_SHIFT (0U) +#define SCT_MATCHRELL_MATCHRELL(x) (((uint16_t)(((uint16_t)(x)) << SCT_MATCHRELL_MATCHRELL_SHIFT)) & SCT_MATCHRELL_MATCHRELL_MASK) +/*! @} */ + +/* The count of SCT_MATCHRELL */ +#define SCT_MATCHRELL_COUNT (16U) + +/*! @name MATCHRELH - SCT_MATCHRELH register */ +/*! @{ */ + +#define SCT_MATCHRELH_MATCHRELH_MASK (0xFFFFU) +#define SCT_MATCHRELH_MATCHRELH_SHIFT (0U) +#define SCT_MATCHRELH_MATCHRELH(x) (((uint16_t)(((uint16_t)(x)) << SCT_MATCHRELH_MATCHRELH_SHIFT)) & SCT_MATCHRELH_MATCHRELH_MASK) +/*! @} */ + +/* The count of SCT_MATCHRELH */ +#define SCT_MATCHRELH_COUNT (16U) + +/*! @name MATCHREL - SCT match reload value register */ +/*! @{ */ + +#define SCT_MATCHREL_RELOADn_L_MASK (0xFFFFU) +#define SCT_MATCHREL_RELOADn_L_SHIFT (0U) +/*! RELOADn_L - When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. + * When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn + * register. + */ +#define SCT_MATCHREL_RELOADn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_MATCHREL_RELOADn_L_SHIFT)) & SCT_MATCHREL_RELOADn_L_MASK) + +#define SCT_MATCHREL_RELOADn_H_MASK (0xFFFF0000U) +#define SCT_MATCHREL_RELOADn_H_SHIFT (16U) +/*! RELOADn_H - When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When + * UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn + * register. + */ +#define SCT_MATCHREL_RELOADn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_MATCHREL_RELOADn_H_SHIFT)) & SCT_MATCHREL_RELOADn_H_MASK) +/*! @} */ + +/* The count of SCT_MATCHREL */ +#define SCT_MATCHREL_COUNT (16U) + +/*! @name EV_STATE - SCT event state register 0 */ +/*! @{ */ + +#define SCT_EV_STATE_STATEMSKn_MASK (0xFFFFU) +#define SCT_EV_STATE_STATEMSKn_SHIFT (0U) +/*! STATEMSKn - If bit m is one, event n happens in state m of the counter selected by the HEVENT + * bit (n = event number, m = state number; state 0 = bit 0, state 1= bit 1, etc.). The number of + * bits = number of states in this SCT. + */ +#define SCT_EV_STATE_STATEMSKn(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_STATE_STATEMSKn_SHIFT)) & SCT_EV_STATE_STATEMSKn_MASK) +/*! @} */ + +/* The count of SCT_EV_STATE */ +#define SCT_EV_STATE_COUNT (16U) + +/*! @name EV_CTRL - SCT event control register 0 */ +/*! @{ */ + +#define SCT_EV_CTRL_MATCHSEL_MASK (0xFU) +#define SCT_EV_CTRL_MATCHSEL_SHIFT (0U) +/*! MATCHSEL - Selects the Match register associated with this event (if any). A match can occur + * only when the counter selected by the HEVENT bit is running. + */ +#define SCT_EV_CTRL_MATCHSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_MATCHSEL_SHIFT)) & SCT_EV_CTRL_MATCHSEL_MASK) + +#define SCT_EV_CTRL_HEVENT_MASK (0x10U) +#define SCT_EV_CTRL_HEVENT_SHIFT (4U) +/*! HEVENT - Select L/H counter. Do not set this bit if UNIFY = 1. + * 0b0..Selects the L state and the L match register selected by MATCHSEL. + * 0b1..Selects the H state and the H match register selected by MATCHSEL. + */ +#define SCT_EV_CTRL_HEVENT(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_HEVENT_SHIFT)) & SCT_EV_CTRL_HEVENT_MASK) + +#define SCT_EV_CTRL_OUTSEL_MASK (0x20U) +#define SCT_EV_CTRL_OUTSEL_SHIFT (5U) +/*! OUTSEL - Input/output select + * 0b0..Selects the inputs selected by IOSEL. + * 0b1..Selects the outputs selected by IOSEL. + */ +#define SCT_EV_CTRL_OUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_OUTSEL_SHIFT)) & SCT_EV_CTRL_OUTSEL_MASK) + +#define SCT_EV_CTRL_IOSEL_MASK (0x3C0U) +#define SCT_EV_CTRL_IOSEL_SHIFT (6U) +/*! IOSEL - Selects the input or output signal number associated with this event (if any). Do not + * select an input in this register if CKMODE is 1x. In this case the clock input is an implicit + * ingredient of every event. + */ +#define SCT_EV_CTRL_IOSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_IOSEL_SHIFT)) & SCT_EV_CTRL_IOSEL_MASK) + +#define SCT_EV_CTRL_IOCOND_MASK (0xC00U) +#define SCT_EV_CTRL_IOCOND_SHIFT (10U) +/*! IOCOND - Selects the I/O condition for event n. (The detection of edges on outputs lag the + * conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state + * detection, an input must have a minimum pulse width of at least one SCT clock period . + * 0b00..LOW + * 0b01..Rise + * 0b10..Fall + * 0b11..HIGH + */ +#define SCT_EV_CTRL_IOCOND(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_IOCOND_SHIFT)) & SCT_EV_CTRL_IOCOND_MASK) + +#define SCT_EV_CTRL_COMBMODE_MASK (0x3000U) +#define SCT_EV_CTRL_COMBMODE_SHIFT (12U) +/*! COMBMODE - Selects how the specified match and I/O condition are used and combined. + * 0b00..OR. The event occurs when either the specified match or I/O condition occurs. + * 0b01..MATCH. Uses the specified match only. + * 0b10..IO. Uses the specified I/O condition only. + * 0b11..AND. The event occurs when the specified match and I/O condition occur simultaneously. + */ +#define SCT_EV_CTRL_COMBMODE(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_COMBMODE_SHIFT)) & SCT_EV_CTRL_COMBMODE_MASK) + +#define SCT_EV_CTRL_STATELD_MASK (0x4000U) +#define SCT_EV_CTRL_STATELD_SHIFT (14U) +/*! STATELD - This bit controls how the STATEV value modifies the state selected by HEVENT when this + * event is the highest-numbered event occurring for that state. + * 0b0..STATEV value is added into STATE (the carry-out is ignored). + * 0b1..STATEV value is loaded into STATE. + */ +#define SCT_EV_CTRL_STATELD(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_STATELD_SHIFT)) & SCT_EV_CTRL_STATELD_MASK) + +#define SCT_EV_CTRL_STATEV_MASK (0xF8000U) +#define SCT_EV_CTRL_STATEV_SHIFT (15U) +/*! STATEV - This value is loaded into or added to the state selected by HEVENT, depending on + * STATELD, when this event is the highest-numbered event occurring for that state. If STATELD and + * STATEV are both zero, there is no change to the STATE value. + */ +#define SCT_EV_CTRL_STATEV(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_STATEV_SHIFT)) & SCT_EV_CTRL_STATEV_MASK) + +#define SCT_EV_CTRL_MATCHMEM_MASK (0x100000U) +#define SCT_EV_CTRL_MATCHMEM_SHIFT (20U) +/*! MATCHMEM - If this bit is one and the COMBMODE field specifies a match component to the + * triggering of this event, then a match is considered to be active whenever the counter value is + * GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR + * EQUAL TO the match value when counting down. If this bit is zero, a match is only be active + * during the cycle when the counter is equal to the match value. + */ +#define SCT_EV_CTRL_MATCHMEM(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_MATCHMEM_SHIFT)) & SCT_EV_CTRL_MATCHMEM_MASK) + +#define SCT_EV_CTRL_DIRECTION_MASK (0x600000U) +#define SCT_EV_CTRL_DIRECTION_SHIFT (21U) +/*! DIRECTION - Direction qualifier for event generation. This field only applies when the counters + * are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved. + * 0b00..Direction independent. This event is triggered regardless of the count direction. + * 0b01..Counting up. This event is triggered only during up-counting when BIDIR = 1. + * 0b10..Counting down. This event is triggered only during down-counting when BIDIR = 1. + */ +#define SCT_EV_CTRL_DIRECTION(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_DIRECTION_SHIFT)) & SCT_EV_CTRL_DIRECTION_MASK) +/*! @} */ + +/* The count of SCT_EV_CTRL */ +#define SCT_EV_CTRL_COUNT (16U) + +/*! @name OUT_SET - SCT output 0 set register */ +/*! @{ */ + +#define SCT_OUT_SET_SET_MASK (0xFFFFU) +#define SCT_OUT_SET_SET_SHIFT (0U) +/*! SET - A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) output + * 0 = bit 0, output 1 = bit 1, etc. The number of bits = number of events in this SCT. When the + * counter is used in bi-directional mode, it is possible to reverse the action specified by the + * output set and clear registers when counting down, See the OUTPUTCTRL register. + */ +#define SCT_OUT_SET_SET(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUT_SET_SET_SHIFT)) & SCT_OUT_SET_SET_MASK) +/*! @} */ + +/* The count of SCT_OUT_SET */ +#define SCT_OUT_SET_COUNT (10U) + +/*! @name OUT_CLR - SCT output 0 clear register */ +/*! @{ */ + +#define SCT_OUT_CLR_CLR_MASK (0xFFFFU) +#define SCT_OUT_CLR_CLR_SHIFT (0U) +/*! CLR - A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 + * = bit 0, event 1 = bit 1, etc. The number of bits = number of events in this SCT. When the + * counter is used in bi-directional mode, it is possible to reverse the action specified by the + * output set and clear registers when counting down, See the OUTPUTCTRL register. + */ +#define SCT_OUT_CLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUT_CLR_CLR_SHIFT)) & SCT_OUT_CLR_CLR_MASK) +/*! @} */ + +/* The count of SCT_OUT_CLR */ +#define SCT_OUT_CLR_COUNT (10U) + + +/*! + * @} + */ /* end of group SCT_Register_Masks */ + + +/* SCT - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral SCT0 base address */ + #define SCT0_BASE (0x50085000u) + /** Peripheral SCT0 base address */ + #define SCT0_BASE_NS (0x40085000u) + /** Peripheral SCT0 base pointer */ + #define SCT0 ((SCT_Type *)SCT0_BASE) + /** Peripheral SCT0 base pointer */ + #define SCT0_NS ((SCT_Type *)SCT0_BASE_NS) + /** Array initializer of SCT peripheral base addresses */ + #define SCT_BASE_ADDRS { SCT0_BASE } + /** Array initializer of SCT peripheral base pointers */ + #define SCT_BASE_PTRS { SCT0 } + /** Array initializer of SCT peripheral base addresses */ + #define SCT_BASE_ADDRS_NS { SCT0_BASE_NS } + /** Array initializer of SCT peripheral base pointers */ + #define SCT_BASE_PTRS_NS { SCT0_NS } +#else + /** Peripheral SCT0 base address */ + #define SCT0_BASE (0x40085000u) + /** Peripheral SCT0 base pointer */ + #define SCT0 ((SCT_Type *)SCT0_BASE) + /** Array initializer of SCT peripheral base addresses */ + #define SCT_BASE_ADDRS { SCT0_BASE } + /** Array initializer of SCT peripheral base pointers */ + #define SCT_BASE_PTRS { SCT0 } +#endif +/** Interrupt vectors for the SCT peripheral type */ +#define SCT_IRQS { SCT0_IRQn } + +/*! + * @} + */ /* end of group SCT_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- SPI Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer + * @{ + */ + +/** SPI - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[1024]; + __IO uint32_t CFG; /**< SPI Configuration register, offset: 0x400 */ + __IO uint32_t DLY; /**< SPI Delay register, offset: 0x404 */ + __IO uint32_t STAT; /**< SPI Status. Some status flags can be cleared by writing a 1 to that bit position., offset: 0x408 */ + __IO uint32_t INTENSET; /**< SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set., offset: 0x40C */ + __O uint32_t INTENCLR; /**< SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared., offset: 0x410 */ + uint8_t RESERVED_1[16]; + __IO uint32_t DIV; /**< SPI clock Divider, offset: 0x424 */ + __I uint32_t INTSTAT; /**< SPI Interrupt Status, offset: 0x428 */ + uint8_t RESERVED_2[2516]; + __IO uint32_t FIFOCFG; /**< FIFO configuration and enable register., offset: 0xE00 */ + __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */ + __IO uint32_t FIFOTRIG; /**< FIFO trigger settings for interrupt and DMA request., offset: 0xE08 */ + uint8_t RESERVED_3[4]; + __IO uint32_t FIFOINTENSET; /**< FIFO interrupt enable set (enable) and read register., offset: 0xE10 */ + __IO uint32_t FIFOINTENCLR; /**< FIFO interrupt enable clear (disable) and read register., offset: 0xE14 */ + __I uint32_t FIFOINTSTAT; /**< FIFO interrupt status register., offset: 0xE18 */ + uint8_t RESERVED_4[4]; + __O uint32_t FIFOWR; /**< FIFO write data., offset: 0xE20 */ + uint8_t RESERVED_5[12]; + __I uint32_t FIFORD; /**< FIFO read data., offset: 0xE30 */ + uint8_t RESERVED_6[12]; + __I uint32_t FIFORDNOPOP; /**< FIFO data read with no FIFO pop., offset: 0xE40 */ + uint8_t RESERVED_7[4]; + __I uint32_t FIFOSIZE; /**< FIFO size register, offset: 0xE48 */ + uint8_t RESERVED_8[432]; + __I uint32_t ID; /**< Peripheral identification register., offset: 0xFFC */ +} SPI_Type; + +/* ---------------------------------------------------------------------------- + -- SPI Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SPI_Register_Masks SPI Register Masks + * @{ + */ + +/*! @name CFG - SPI Configuration register */ +/*! @{ */ + +#define SPI_CFG_ENABLE_MASK (0x1U) +#define SPI_CFG_ENABLE_SHIFT (0U) +/*! ENABLE - SPI enable. + * 0b0..Disabled. The SPI is disabled and the internal state machine and counters are reset. + * 0b1..Enabled. The SPI is enabled for operation. + */ +#define SPI_CFG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_ENABLE_SHIFT)) & SPI_CFG_ENABLE_MASK) + +#define SPI_CFG_MASTER_MASK (0x4U) +#define SPI_CFG_MASTER_SHIFT (2U) +/*! MASTER - Master mode select. + * 0b0..Slave mode. The SPI will operate in slave mode. SCK, MOSI, and the SSEL signals are inputs, MISO is an output. + * 0b1..Master mode. The SPI will operate in master mode. SCK, MOSI, and the SSEL signals are outputs, MISO is an input. + */ +#define SPI_CFG_MASTER(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_MASTER_SHIFT)) & SPI_CFG_MASTER_MASK) + +#define SPI_CFG_LSBF_MASK (0x8U) +#define SPI_CFG_LSBF_SHIFT (3U) +/*! LSBF - LSB First mode enable. + * 0b0..Standard. Data is transmitted and received in standard MSB first order. + * 0b1..Reverse. Data is transmitted and received in reverse order (LSB first). + */ +#define SPI_CFG_LSBF(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_LSBF_SHIFT)) & SPI_CFG_LSBF_MASK) + +#define SPI_CFG_CPHA_MASK (0x10U) +#define SPI_CFG_CPHA_SHIFT (4U) +/*! CPHA - Clock Phase select. + * 0b0..Change. The SPI captures serial data on the first clock transition of the transfer (when the clock + * changes away from the rest state). Data is changed on the following edge. + * 0b1..Capture. The SPI changes serial data on the first clock transition of the transfer (when the clock + * changes away from the rest state). Data is captured on the following edge. + */ +#define SPI_CFG_CPHA(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_CPHA_SHIFT)) & SPI_CFG_CPHA_MASK) + +#define SPI_CFG_CPOL_MASK (0x20U) +#define SPI_CFG_CPOL_SHIFT (5U) +/*! CPOL - Clock Polarity select. + * 0b0..Low. The rest state of the clock (between transfers) is low. + * 0b1..High. The rest state of the clock (between transfers) is high. + */ +#define SPI_CFG_CPOL(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_CPOL_SHIFT)) & SPI_CFG_CPOL_MASK) + +#define SPI_CFG_LOOP_MASK (0x80U) +#define SPI_CFG_LOOP_SHIFT (7U) +/*! LOOP - Loopback mode enable. Loopback mode applies only to Master mode, and connects transmit + * and receive data connected together to allow simple software testing. + * 0b0..Disabled. + * 0b1..Enabled. + */ +#define SPI_CFG_LOOP(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_LOOP_SHIFT)) & SPI_CFG_LOOP_MASK) + +#define SPI_CFG_SPOL0_MASK (0x100U) +#define SPI_CFG_SPOL0_SHIFT (8U) +/*! SPOL0 - SSEL0 Polarity select. + * 0b0..Low. The SSEL0 pin is active low. + * 0b1..High. The SSEL0 pin is active high. + */ +#define SPI_CFG_SPOL0(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL0_SHIFT)) & SPI_CFG_SPOL0_MASK) + +#define SPI_CFG_SPOL1_MASK (0x200U) +#define SPI_CFG_SPOL1_SHIFT (9U) +/*! SPOL1 - SSEL1 Polarity select. + * 0b0..Low. The SSEL1 pin is active low. + * 0b1..High. The SSEL1 pin is active high. + */ +#define SPI_CFG_SPOL1(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL1_SHIFT)) & SPI_CFG_SPOL1_MASK) + +#define SPI_CFG_SPOL2_MASK (0x400U) +#define SPI_CFG_SPOL2_SHIFT (10U) +/*! SPOL2 - SSEL2 Polarity select. + * 0b0..Low. The SSEL2 pin is active low. + * 0b1..High. The SSEL2 pin is active high. + */ +#define SPI_CFG_SPOL2(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL2_SHIFT)) & SPI_CFG_SPOL2_MASK) + +#define SPI_CFG_SPOL3_MASK (0x800U) +#define SPI_CFG_SPOL3_SHIFT (11U) +/*! SPOL3 - SSEL3 Polarity select. + * 0b0..Low. The SSEL3 pin is active low. + * 0b1..High. The SSEL3 pin is active high. + */ +#define SPI_CFG_SPOL3(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL3_SHIFT)) & SPI_CFG_SPOL3_MASK) +/*! @} */ + +/*! @name DLY - SPI Delay register */ +/*! @{ */ + +#define SPI_DLY_PRE_DELAY_MASK (0xFU) +#define SPI_DLY_PRE_DELAY_SHIFT (0U) +/*! PRE_DELAY - Controls the amount of time between SSEL assertion and the beginning of a data + * transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This + * is not considered part of the pre-delay. 0x0 = No additional time is inserted. 0x1 = 1 SPI + * clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are + * inserted. + */ +#define SPI_DLY_PRE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_PRE_DELAY_SHIFT)) & SPI_DLY_PRE_DELAY_MASK) + +#define SPI_DLY_POST_DELAY_MASK (0xF0U) +#define SPI_DLY_POST_DELAY_SHIFT (4U) +/*! POST_DELAY - Controls the amount of time between the end of a data transfer and SSEL + * deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock + * times are inserted. 0xF = 15 SPI clock times are inserted. + */ +#define SPI_DLY_POST_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_POST_DELAY_SHIFT)) & SPI_DLY_POST_DELAY_MASK) + +#define SPI_DLY_FRAME_DELAY_MASK (0xF00U) +#define SPI_DLY_FRAME_DELAY_SHIFT (8U) +/*! FRAME_DELAY - If the EOF flag is set, controls the minimum amount of time between the current + * frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 + * = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock + * times are inserted. + */ +#define SPI_DLY_FRAME_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_FRAME_DELAY_SHIFT)) & SPI_DLY_FRAME_DELAY_MASK) + +#define SPI_DLY_TRANSFER_DELAY_MASK (0xF000U) +#define SPI_DLY_TRANSFER_DELAY_SHIFT (12U) +/*! TRANSFER_DELAY - Controls the minimum amount of time that the SSEL is deasserted between + * transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 + * = The minimum time that SSEL is deasserted is 2 SPI clock times. 0x2 = The minimum time that + * SSEL is deasserted is 3 SPI clock times. 0xF = The minimum time that SSEL is deasserted is 16 + * SPI clock times. + */ +#define SPI_DLY_TRANSFER_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_TRANSFER_DELAY_SHIFT)) & SPI_DLY_TRANSFER_DELAY_MASK) +/*! @} */ + +/*! @name STAT - SPI Status. Some status flags can be cleared by writing a 1 to that bit position. */ +/*! @{ */ + +#define SPI_STAT_SSA_MASK (0x10U) +#define SPI_STAT_SSA_SHIFT (4U) +/*! SSA - Slave Select Assert. This flag is set whenever any slave select transitions from + * deasserted to asserted, in both master and slave modes. This allows determining when the SPI + * transmit/receive functions become busy, and allows waking up the device from reduced power modes when a + * slave mode access begins. This flag is cleared by software. + */ +#define SPI_STAT_SSA(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_SSA_SHIFT)) & SPI_STAT_SSA_MASK) + +#define SPI_STAT_SSD_MASK (0x20U) +#define SPI_STAT_SSD_SHIFT (5U) +/*! SSD - Slave Select Deassert. This flag is set whenever any asserted slave selects transition to + * deasserted, in both master and slave modes. This allows determining when the SPI + * transmit/receive functions become idle. This flag is cleared by software. + */ +#define SPI_STAT_SSD(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_SSD_SHIFT)) & SPI_STAT_SSD_MASK) + +#define SPI_STAT_STALLED_MASK (0x40U) +#define SPI_STAT_STALLED_SHIFT (6U) +/*! STALLED - Stalled status flag. This indicates whether the SPI is currently in a stall condition. + */ +#define SPI_STAT_STALLED(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_STALLED_SHIFT)) & SPI_STAT_STALLED_MASK) + +#define SPI_STAT_ENDTRANSFER_MASK (0x80U) +#define SPI_STAT_ENDTRANSFER_SHIFT (7U) +/*! ENDTRANSFER - End Transfer control bit. Software can set this bit to force an end to the current + * transfer when the transmitter finishes any activity already in progress, as if the EOT flag + * had been set prior to the last transmission. This capability is included to support cases where + * it is not known when transmit data is written that it will be the end of a transfer. The bit + * is cleared when the transmitter becomes idle as the transfer comes to an end. Forcing an end + * of transfer in this manner causes any specified FRAME_DELAY and TRANSFER_DELAY to be inserted. + */ +#define SPI_STAT_ENDTRANSFER(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_ENDTRANSFER_SHIFT)) & SPI_STAT_ENDTRANSFER_MASK) + +#define SPI_STAT_MSTIDLE_MASK (0x100U) +#define SPI_STAT_MSTIDLE_SHIFT (8U) +/*! MSTIDLE - Master idle status flag. This bit is 1 whenever the SPI master function is fully idle. + * This means that the transmit holding register is empty and the transmitter is not in the + * process of sending data. + */ +#define SPI_STAT_MSTIDLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_MSTIDLE_SHIFT)) & SPI_STAT_MSTIDLE_MASK) +/*! @} */ + +/*! @name INTENSET - SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set. */ +/*! @{ */ + +#define SPI_INTENSET_SSAEN_MASK (0x10U) +#define SPI_INTENSET_SSAEN_SHIFT (4U) +/*! SSAEN - Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted. + * 0b0..Disabled. No interrupt will be generated when any Slave Select transitions from deasserted to asserted. + * 0b1..Enabled. An interrupt will be generated when any Slave Select transitions from deasserted to asserted. + */ +#define SPI_INTENSET_SSAEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_SSAEN_SHIFT)) & SPI_INTENSET_SSAEN_MASK) + +#define SPI_INTENSET_SSDEN_MASK (0x20U) +#define SPI_INTENSET_SSDEN_SHIFT (5U) +/*! SSDEN - Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted. + * 0b0..Disabled. No interrupt will be generated when all asserted Slave Selects transition to deasserted. + * 0b1..Enabled. An interrupt will be generated when all asserted Slave Selects transition to deasserted. + */ +#define SPI_INTENSET_SSDEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_SSDEN_SHIFT)) & SPI_INTENSET_SSDEN_MASK) + +#define SPI_INTENSET_MSTIDLEEN_MASK (0x100U) +#define SPI_INTENSET_MSTIDLEEN_SHIFT (8U) +/*! MSTIDLEEN - Master idle interrupt enable. + * 0b0..No interrupt will be generated when the SPI master function is idle. + * 0b1..An interrupt will be generated when the SPI master function is fully idle. + */ +#define SPI_INTENSET_MSTIDLEEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_MSTIDLEEN_SHIFT)) & SPI_INTENSET_MSTIDLEEN_MASK) +/*! @} */ + +/*! @name INTENCLR - SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared. */ +/*! @{ */ + +#define SPI_INTENCLR_SSAEN_MASK (0x10U) +#define SPI_INTENCLR_SSAEN_SHIFT (4U) +/*! SSAEN - Writing 1 clears the corresponding bit in the INTENSET register. + */ +#define SPI_INTENCLR_SSAEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_SSAEN_SHIFT)) & SPI_INTENCLR_SSAEN_MASK) + +#define SPI_INTENCLR_SSDEN_MASK (0x20U) +#define SPI_INTENCLR_SSDEN_SHIFT (5U) +/*! SSDEN - Writing 1 clears the corresponding bit in the INTENSET register. + */ +#define SPI_INTENCLR_SSDEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_SSDEN_SHIFT)) & SPI_INTENCLR_SSDEN_MASK) + +#define SPI_INTENCLR_MSTIDLE_MASK (0x100U) +#define SPI_INTENCLR_MSTIDLE_SHIFT (8U) +/*! MSTIDLE - Writing 1 clears the corresponding bit in the INTENSET register. + */ +#define SPI_INTENCLR_MSTIDLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_MSTIDLE_SHIFT)) & SPI_INTENCLR_MSTIDLE_MASK) +/*! @} */ + +/*! @name DIV - SPI clock Divider */ +/*! @{ */ + +#define SPI_DIV_DIVVAL_MASK (0xFFFFU) +#define SPI_DIV_DIVVAL_SHIFT (0U) +/*! DIVVAL - Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the + * SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1, + * the value 1 results in FCLK/2, up to the maximum possible divide value of 0xFFFF, which results + * in FCLK/65536. + */ +#define SPI_DIV_DIVVAL(x) (((uint32_t)(((uint32_t)(x)) << SPI_DIV_DIVVAL_SHIFT)) & SPI_DIV_DIVVAL_MASK) +/*! @} */ + +/*! @name INTSTAT - SPI Interrupt Status */ +/*! @{ */ + +#define SPI_INTSTAT_SSA_MASK (0x10U) +#define SPI_INTSTAT_SSA_SHIFT (4U) +/*! SSA - Slave Select Assert. + */ +#define SPI_INTSTAT_SSA(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_SSA_SHIFT)) & SPI_INTSTAT_SSA_MASK) + +#define SPI_INTSTAT_SSD_MASK (0x20U) +#define SPI_INTSTAT_SSD_SHIFT (5U) +/*! SSD - Slave Select Deassert. + */ +#define SPI_INTSTAT_SSD(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_SSD_SHIFT)) & SPI_INTSTAT_SSD_MASK) + +#define SPI_INTSTAT_MSTIDLE_MASK (0x100U) +#define SPI_INTSTAT_MSTIDLE_SHIFT (8U) +/*! MSTIDLE - Master Idle status flag. + */ +#define SPI_INTSTAT_MSTIDLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_MSTIDLE_SHIFT)) & SPI_INTSTAT_MSTIDLE_MASK) +/*! @} */ + +/*! @name FIFOCFG - FIFO configuration and enable register. */ +/*! @{ */ + +#define SPI_FIFOCFG_ENABLETX_MASK (0x1U) +#define SPI_FIFOCFG_ENABLETX_SHIFT (0U) +/*! ENABLETX - Enable the transmit FIFO. + * 0b0..The transmit FIFO is not enabled. + * 0b1..The transmit FIFO is enabled. + */ +#define SPI_FIFOCFG_ENABLETX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_ENABLETX_SHIFT)) & SPI_FIFOCFG_ENABLETX_MASK) + +#define SPI_FIFOCFG_ENABLERX_MASK (0x2U) +#define SPI_FIFOCFG_ENABLERX_SHIFT (1U) +/*! ENABLERX - Enable the receive FIFO. + * 0b0..The receive FIFO is not enabled. + * 0b1..The receive FIFO is enabled. + */ +#define SPI_FIFOCFG_ENABLERX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_ENABLERX_SHIFT)) & SPI_FIFOCFG_ENABLERX_MASK) + +#define SPI_FIFOCFG_SIZE_MASK (0x30U) +#define SPI_FIFOCFG_SIZE_SHIFT (4U) +/*! SIZE - FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 + * entries of 8 bits. 0x1, 0x2, 0x3 = not applicable to USART. + */ +#define SPI_FIFOCFG_SIZE(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_SIZE_SHIFT)) & SPI_FIFOCFG_SIZE_MASK) + +#define SPI_FIFOCFG_DMATX_MASK (0x1000U) +#define SPI_FIFOCFG_DMATX_SHIFT (12U) +/*! DMATX - DMA configuration for transmit. + * 0b0..DMA is not used for the transmit function. + * 0b1..Trigger DMA for the transmit function if the FIFO is not full. Generally, data interrupts would be disabled if DMA is enabled. + */ +#define SPI_FIFOCFG_DMATX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_DMATX_SHIFT)) & SPI_FIFOCFG_DMATX_MASK) + +#define SPI_FIFOCFG_DMARX_MASK (0x2000U) +#define SPI_FIFOCFG_DMARX_SHIFT (13U) +/*! DMARX - DMA configuration for receive. + * 0b0..DMA is not used for the receive function. + * 0b1..Trigger DMA for the receive function if the FIFO is not empty. Generally, data interrupts would be disabled if DMA is enabled. + */ +#define SPI_FIFOCFG_DMARX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_DMARX_SHIFT)) & SPI_FIFOCFG_DMARX_MASK) + +#define SPI_FIFOCFG_WAKETX_MASK (0x4000U) +#define SPI_FIFOCFG_WAKETX_SHIFT (14U) +/*! WAKETX - Wake-up for transmit FIFO level. This allows the device to be woken from reduced power + * modes (up to power-down, as long as the peripheral function works in that power mode) without + * enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The + * CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware + * Wake-up control register. + * 0b0..Only enabled interrupts will wake up the device form reduced power modes. + * 0b1..A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by TXLVL in + * FIFOTRIG, even when the TXLVL interrupt is not enabled. + */ +#define SPI_FIFOCFG_WAKETX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_WAKETX_SHIFT)) & SPI_FIFOCFG_WAKETX_MASK) + +#define SPI_FIFOCFG_WAKERX_MASK (0x8000U) +#define SPI_FIFOCFG_WAKERX_SHIFT (15U) +/*! WAKERX - Wake-up for receive FIFO level. This allows the device to be woken from reduced power + * modes (up to power-down, as long as the peripheral function works in that power mode) without + * enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The + * CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware + * Wake-up control register. + * 0b0..Only enabled interrupts will wake up the device form reduced power modes. + * 0b1..A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by RXLVL in + * FIFOTRIG, even when the RXLVL interrupt is not enabled. + */ +#define SPI_FIFOCFG_WAKERX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_WAKERX_SHIFT)) & SPI_FIFOCFG_WAKERX_MASK) + +#define SPI_FIFOCFG_EMPTYTX_MASK (0x10000U) +#define SPI_FIFOCFG_EMPTYTX_SHIFT (16U) +/*! EMPTYTX - Empty command for the transmit FIFO. When a 1 is written to this bit, the TX FIFO is emptied. + */ +#define SPI_FIFOCFG_EMPTYTX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_EMPTYTX_SHIFT)) & SPI_FIFOCFG_EMPTYTX_MASK) + +#define SPI_FIFOCFG_EMPTYRX_MASK (0x20000U) +#define SPI_FIFOCFG_EMPTYRX_SHIFT (17U) +/*! EMPTYRX - Empty command for the receive FIFO. When a 1 is written to this bit, the RX FIFO is emptied. + */ +#define SPI_FIFOCFG_EMPTYRX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_EMPTYRX_SHIFT)) & SPI_FIFOCFG_EMPTYRX_MASK) +/*! @} */ + +/*! @name FIFOSTAT - FIFO status register. */ +/*! @{ */ + +#define SPI_FIFOSTAT_TXERR_MASK (0x1U) +#define SPI_FIFOSTAT_TXERR_SHIFT (0U) +/*! TXERR - TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow + * caused by pushing data into a full FIFO, or by an underflow if the FIFO is empty when data is + * needed. Cleared by writing a 1 to this bit. + */ +#define SPI_FIFOSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXERR_SHIFT)) & SPI_FIFOSTAT_TXERR_MASK) + +#define SPI_FIFOSTAT_RXERR_MASK (0x2U) +#define SPI_FIFOSTAT_RXERR_SHIFT (1U) +/*! RXERR - RX FIFO error. Will be set if a receive FIFO overflow occurs, caused by software or DMA + * not emptying the FIFO fast enough. Cleared by writing a 1 to this bit. + */ +#define SPI_FIFOSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXERR_SHIFT)) & SPI_FIFOSTAT_RXERR_MASK) + +#define SPI_FIFOSTAT_PERINT_MASK (0x8U) +#define SPI_FIFOSTAT_PERINT_SHIFT (3U) +/*! PERINT - Peripheral interrupt. When 1, this indicates that the peripheral function has asserted + * an interrupt. The details can be found by reading the peripheral's STAT register. + */ +#define SPI_FIFOSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_PERINT_SHIFT)) & SPI_FIFOSTAT_PERINT_MASK) + +#define SPI_FIFOSTAT_TXEMPTY_MASK (0x10U) +#define SPI_FIFOSTAT_TXEMPTY_SHIFT (4U) +/*! TXEMPTY - Transmit FIFO empty. When 1, the transmit FIFO is empty. The peripheral may still be processing the last piece of data. + */ +#define SPI_FIFOSTAT_TXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXEMPTY_SHIFT)) & SPI_FIFOSTAT_TXEMPTY_MASK) + +#define SPI_FIFOSTAT_TXNOTFULL_MASK (0x20U) +#define SPI_FIFOSTAT_TXNOTFULL_SHIFT (5U) +/*! TXNOTFULL - Transmit FIFO not full. When 1, the transmit FIFO is not full, so more data can be + * written. When 0, the transmit FIFO is full and another write would cause it to overflow. + */ +#define SPI_FIFOSTAT_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXNOTFULL_SHIFT)) & SPI_FIFOSTAT_TXNOTFULL_MASK) + +#define SPI_FIFOSTAT_RXNOTEMPTY_MASK (0x40U) +#define SPI_FIFOSTAT_RXNOTEMPTY_SHIFT (6U) +/*! RXNOTEMPTY - Receive FIFO not empty. When 1, the receive FIFO is not empty, so data can be read. When 0, the receive FIFO is empty. + */ +#define SPI_FIFOSTAT_RXNOTEMPTY(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXNOTEMPTY_SHIFT)) & SPI_FIFOSTAT_RXNOTEMPTY_MASK) + +#define SPI_FIFOSTAT_RXFULL_MASK (0x80U) +#define SPI_FIFOSTAT_RXFULL_SHIFT (7U) +/*! RXFULL - Receive FIFO full. When 1, the receive FIFO is full. Data needs to be read out to + * prevent the peripheral from causing an overflow. + */ +#define SPI_FIFOSTAT_RXFULL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXFULL_SHIFT)) & SPI_FIFOSTAT_RXFULL_MASK) + +#define SPI_FIFOSTAT_TXLVL_MASK (0x1F00U) +#define SPI_FIFOSTAT_TXLVL_SHIFT (8U) +/*! TXLVL - Transmit FIFO current level. A 0 means the TX FIFO is currently empty, and the TXEMPTY + * and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at + * the point where the read occurs. If the TX FIFO is full, the TXEMPTY and TXNOTFULL flags will be + * 0. + */ +#define SPI_FIFOSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXLVL_SHIFT)) & SPI_FIFOSTAT_TXLVL_MASK) + +#define SPI_FIFOSTAT_RXLVL_MASK (0x1F0000U) +#define SPI_FIFOSTAT_RXLVL_SHIFT (16U) +/*! RXLVL - Receive FIFO current level. A 0 means the RX FIFO is currently empty, and the RXFULL and + * RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the + * point where the read occurs. If the RX FIFO is full, the RXFULL and RXNOTEMPTY flags will be + * 1. + */ +#define SPI_FIFOSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXLVL_SHIFT)) & SPI_FIFOSTAT_RXLVL_MASK) +/*! @} */ + +/*! @name FIFOTRIG - FIFO trigger settings for interrupt and DMA request. */ +/*! @{ */ + +#define SPI_FIFOTRIG_TXLVLENA_MASK (0x1U) +#define SPI_FIFOTRIG_TXLVLENA_SHIFT (0U) +/*! TXLVLENA - Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled + * in FIFOINTENSET, or a DMA trigger if DMATX in FIFOCFG is set. + * 0b0..Transmit FIFO level does not generate a FIFO level trigger. + * 0b1..An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL field in this register. + */ +#define SPI_FIFOTRIG_TXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_TXLVLENA_SHIFT)) & SPI_FIFOTRIG_TXLVLENA_MASK) + +#define SPI_FIFOTRIG_RXLVLENA_MASK (0x2U) +#define SPI_FIFOTRIG_RXLVLENA_SHIFT (1U) +/*! RXLVLENA - Receive FIFO level trigger enable. This trigger will become an interrupt if enabled + * in FIFOINTENSET, or a DMA trigger if DMARX in FIFOCFG is set. + * 0b0..Receive FIFO level does not generate a FIFO level trigger. + * 0b1..An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL field in this register. + */ +#define SPI_FIFOTRIG_RXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_RXLVLENA_SHIFT)) & SPI_FIFOTRIG_RXLVLENA_MASK) + +#define SPI_FIFOTRIG_TXLVL_MASK (0xF00U) +#define SPI_FIFOTRIG_TXLVL_SHIFT (8U) +/*! TXLVL - Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled + * to do so, the FIFO level can wake up the device just enough to perform DMA, then return to + * the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the TX FIFO + * becomes empty. 1 = trigger when the TX FIFO level decreases to one entry. 15 = trigger when the TX + * FIFO level decreases to 15 entries (is no longer full). + */ +#define SPI_FIFOTRIG_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_TXLVL_SHIFT)) & SPI_FIFOTRIG_TXLVL_MASK) + +#define SPI_FIFOTRIG_RXLVL_MASK (0xF0000U) +#define SPI_FIFOTRIG_RXLVL_SHIFT (16U) +/*! RXLVL - Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data + * is received. This field is used only when RXLVLENA = 1. If enabled to do so, the FIFO level + * can wake up the device just enough to perform DMA, then return to the reduced power mode. See + * Hardware Wake-up control register. 0 = trigger when the RX FIFO has received one entry (is no + * longer empty). 1 = trigger when the RX FIFO has received two entries. 15 = trigger when the RX + * FIFO has received 16 entries (has become full). + */ +#define SPI_FIFOTRIG_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_RXLVL_SHIFT)) & SPI_FIFOTRIG_RXLVL_MASK) +/*! @} */ + +/*! @name FIFOINTENSET - FIFO interrupt enable set (enable) and read register. */ +/*! @{ */ + +#define SPI_FIFOINTENSET_TXERR_MASK (0x1U) +#define SPI_FIFOINTENSET_TXERR_SHIFT (0U) +/*! TXERR - Determines whether an interrupt occurs when a transmit error occurs, based on the TXERR flag in the FIFOSTAT register. + * 0b0..No interrupt will be generated for a transmit error. + * 0b1..An interrupt will be generated when a transmit error occurs. + */ +#define SPI_FIFOINTENSET_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_TXERR_SHIFT)) & SPI_FIFOINTENSET_TXERR_MASK) + +#define SPI_FIFOINTENSET_RXERR_MASK (0x2U) +#define SPI_FIFOINTENSET_RXERR_SHIFT (1U) +/*! RXERR - Determines whether an interrupt occurs when a receive error occurs, based on the RXERR flag in the FIFOSTAT register. + * 0b0..No interrupt will be generated for a receive error. + * 0b1..An interrupt will be generated when a receive error occurs. + */ +#define SPI_FIFOINTENSET_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_RXERR_SHIFT)) & SPI_FIFOINTENSET_RXERR_MASK) + +#define SPI_FIFOINTENSET_TXLVL_MASK (0x4U) +#define SPI_FIFOINTENSET_TXLVL_SHIFT (2U) +/*! TXLVL - Determines whether an interrupt occurs when a the transmit FIFO reaches the level + * specified by the TXLVL field in the FIFOTRIG register. + * 0b0..No interrupt will be generated based on the TX FIFO level. + * 0b1..If TXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the TX FIFO level decreases + * to the level specified by TXLVL in the FIFOTRIG register. + */ +#define SPI_FIFOINTENSET_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_TXLVL_SHIFT)) & SPI_FIFOINTENSET_TXLVL_MASK) + +#define SPI_FIFOINTENSET_RXLVL_MASK (0x8U) +#define SPI_FIFOINTENSET_RXLVL_SHIFT (3U) +/*! RXLVL - Determines whether an interrupt occurs when a the receive FIFO reaches the level + * specified by the TXLVL field in the FIFOTRIG register. + * 0b0..No interrupt will be generated based on the RX FIFO level. + * 0b1..If RXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the when the RX FIFO level + * increases to the level specified by RXLVL in the FIFOTRIG register. + */ +#define SPI_FIFOINTENSET_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_RXLVL_SHIFT)) & SPI_FIFOINTENSET_RXLVL_MASK) +/*! @} */ + +/*! @name FIFOINTENCLR - FIFO interrupt enable clear (disable) and read register. */ +/*! @{ */ + +#define SPI_FIFOINTENCLR_TXERR_MASK (0x1U) +#define SPI_FIFOINTENCLR_TXERR_SHIFT (0U) +/*! TXERR - Writing one clears the corresponding bits in the FIFOINTENSET register. + */ +#define SPI_FIFOINTENCLR_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_TXERR_SHIFT)) & SPI_FIFOINTENCLR_TXERR_MASK) + +#define SPI_FIFOINTENCLR_RXERR_MASK (0x2U) +#define SPI_FIFOINTENCLR_RXERR_SHIFT (1U) +/*! RXERR - Writing one clears the corresponding bits in the FIFOINTENSET register. + */ +#define SPI_FIFOINTENCLR_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_RXERR_SHIFT)) & SPI_FIFOINTENCLR_RXERR_MASK) + +#define SPI_FIFOINTENCLR_TXLVL_MASK (0x4U) +#define SPI_FIFOINTENCLR_TXLVL_SHIFT (2U) +/*! TXLVL - Writing one clears the corresponding bits in the FIFOINTENSET register. + */ +#define SPI_FIFOINTENCLR_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_TXLVL_SHIFT)) & SPI_FIFOINTENCLR_TXLVL_MASK) + +#define SPI_FIFOINTENCLR_RXLVL_MASK (0x8U) +#define SPI_FIFOINTENCLR_RXLVL_SHIFT (3U) +/*! RXLVL - Writing one clears the corresponding bits in the FIFOINTENSET register. + */ +#define SPI_FIFOINTENCLR_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_RXLVL_SHIFT)) & SPI_FIFOINTENCLR_RXLVL_MASK) +/*! @} */ + +/*! @name FIFOINTSTAT - FIFO interrupt status register. */ +/*! @{ */ + +#define SPI_FIFOINTSTAT_TXERR_MASK (0x1U) +#define SPI_FIFOINTSTAT_TXERR_SHIFT (0U) +/*! TXERR - TX FIFO error. + */ +#define SPI_FIFOINTSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_TXERR_SHIFT)) & SPI_FIFOINTSTAT_TXERR_MASK) + +#define SPI_FIFOINTSTAT_RXERR_MASK (0x2U) +#define SPI_FIFOINTSTAT_RXERR_SHIFT (1U) +/*! RXERR - RX FIFO error. + */ +#define SPI_FIFOINTSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_RXERR_SHIFT)) & SPI_FIFOINTSTAT_RXERR_MASK) + +#define SPI_FIFOINTSTAT_TXLVL_MASK (0x4U) +#define SPI_FIFOINTSTAT_TXLVL_SHIFT (2U) +/*! TXLVL - Transmit FIFO level interrupt. + */ +#define SPI_FIFOINTSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_TXLVL_SHIFT)) & SPI_FIFOINTSTAT_TXLVL_MASK) + +#define SPI_FIFOINTSTAT_RXLVL_MASK (0x8U) +#define SPI_FIFOINTSTAT_RXLVL_SHIFT (3U) +/*! RXLVL - Receive FIFO level interrupt. + */ +#define SPI_FIFOINTSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_RXLVL_SHIFT)) & SPI_FIFOINTSTAT_RXLVL_MASK) + +#define SPI_FIFOINTSTAT_PERINT_MASK (0x10U) +#define SPI_FIFOINTSTAT_PERINT_SHIFT (4U) +/*! PERINT - Peripheral interrupt. + */ +#define SPI_FIFOINTSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_PERINT_SHIFT)) & SPI_FIFOINTSTAT_PERINT_MASK) +/*! @} */ + +/*! @name FIFOWR - FIFO write data. */ +/*! @{ */ + +#define SPI_FIFOWR_TXDATA_MASK (0xFFFFU) +#define SPI_FIFOWR_TXDATA_SHIFT (0U) +/*! TXDATA - Transmit data to the FIFO. + */ +#define SPI_FIFOWR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXDATA_SHIFT)) & SPI_FIFOWR_TXDATA_MASK) + +#define SPI_FIFOWR_TXSSEL0_N_MASK (0x10000U) +#define SPI_FIFOWR_TXSSEL0_N_SHIFT (16U) +/*! TXSSEL0_N - Transmit slave select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default. + * 0b0..SSEL0 asserted. + * 0b1..SSEL0 not asserted. + */ +#define SPI_FIFOWR_TXSSEL0_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL0_N_SHIFT)) & SPI_FIFOWR_TXSSEL0_N_MASK) + +#define SPI_FIFOWR_TXSSEL1_N_MASK (0x20000U) +#define SPI_FIFOWR_TXSSEL1_N_SHIFT (17U) +/*! TXSSEL1_N - Transmit slave select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default. + * 0b0..SSEL1 asserted. + * 0b1..SSEL1 not asserted. + */ +#define SPI_FIFOWR_TXSSEL1_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL1_N_SHIFT)) & SPI_FIFOWR_TXSSEL1_N_MASK) + +#define SPI_FIFOWR_TXSSEL2_N_MASK (0x40000U) +#define SPI_FIFOWR_TXSSEL2_N_SHIFT (18U) +/*! TXSSEL2_N - Transmit slave select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default. + * 0b0..SSEL2 asserted. + * 0b1..SSEL2 not asserted. + */ +#define SPI_FIFOWR_TXSSEL2_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL2_N_SHIFT)) & SPI_FIFOWR_TXSSEL2_N_MASK) + +#define SPI_FIFOWR_TXSSEL3_N_MASK (0x80000U) +#define SPI_FIFOWR_TXSSEL3_N_SHIFT (19U) +/*! TXSSEL3_N - Transmit slave select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default. + * 0b0..SSEL3 asserted. + * 0b1..SSEL3 not asserted. + */ +#define SPI_FIFOWR_TXSSEL3_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL3_N_SHIFT)) & SPI_FIFOWR_TXSSEL3_N_MASK) + +#define SPI_FIFOWR_EOT_MASK (0x100000U) +#define SPI_FIFOWR_EOT_SHIFT (20U) +/*! EOT - End of transfer. The asserted SSEL will be deasserted at the end of a transfer and remain + * so far at least the time specified by the Transfer_delay value in the DLY register. + * 0b0..SSEL not deasserted. This piece of data is not treated as the end of a transfer. SSEL will not be deasserted at the end of this data. + * 0b1..SSEL deasserted. This piece of data is treated as the end of a transfer. SSEL will be deasserted at the end of this piece of data. + */ +#define SPI_FIFOWR_EOT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_EOT_SHIFT)) & SPI_FIFOWR_EOT_MASK) + +#define SPI_FIFOWR_EOF_MASK (0x200000U) +#define SPI_FIFOWR_EOF_SHIFT (21U) +/*! EOF - End of frame. Between frames, a delay may be inserted, as defined by the Frame_delay value + * in the DLY register. The end of a frame may not be particularly meaningful if the Frame_delay + * value = 0. This control can be used as part of the support for frame lengths greater than 16 + * bits. + * 0b0..Data not EOF. This piece of data transmitted is not treated as the end of a frame. + * 0b1..Data EOF. This piece of data is treated as the end of a frame, causing the Frame_delay time to be + * inserted before subsequent data is transmitted. + */ +#define SPI_FIFOWR_EOF(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_EOF_SHIFT)) & SPI_FIFOWR_EOF_MASK) + +#define SPI_FIFOWR_RXIGNORE_MASK (0x400000U) +#define SPI_FIFOWR_RXIGNORE_SHIFT (22U) +/*! RXIGNORE - Receive Ignore. This allows data to be transmitted using the SPI without the need to + * read unneeded data from the receiver. Setting this bit simplifies the transmit process and can + * be used with the DMA. + * 0b0..Read received data. Received data must be read in order to allow transmission to progress. SPI transmit + * will halt when the receive data FIFO is full. In slave mode, an overrun error will occur if received data + * is not read before new data is received. + * 0b1..Ignore received data. Received data is ignored, allowing transmission without reading unneeded received + * data. No receiver flags are generated. + */ +#define SPI_FIFOWR_RXIGNORE(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_RXIGNORE_SHIFT)) & SPI_FIFOWR_RXIGNORE_MASK) + +#define SPI_FIFOWR_TXIGNORE_MASK (0x800000U) +#define SPI_FIFOWR_TXIGNORE_SHIFT (23U) +/*! TXIGNORE - Transmit Ignore. This allows data to be received using the SPI without the need to + * read unneeded data from the receiver. Setting this bit simplifies the transmit process and can + * be used with the DMA.This bit can only be set by writing to the upper 16 bits only of FIFOWR, + * i.e., a half-word write to offset 0xE22. + * 0b0..Write transmit data. Transmit data must be written for each data exchange between master and slave. In + * slave mode, an underrun error occurs if transmit data is not provided before needed in a data frame. + * 0b1..Ignore transmit data. Data can be received without transmitting data (after FIFOWR has been initialized + * to set TXIGNORE). No transmitter flags are generated. When configured with TXIGNORE =1, the slave will set + * the data to always 0. + */ +#define SPI_FIFOWR_TXIGNORE(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXIGNORE_SHIFT)) & SPI_FIFOWR_TXIGNORE_MASK) + +#define SPI_FIFOWR_LEN_MASK (0xF000000U) +#define SPI_FIFOWR_LEN_SHIFT (24U) +/*! LEN - Data Length. Specifies the data length from 4 to 16 bits. Note that transfer lengths + * greater than 16 bits are supported by implementing multiple sequential transmits. 0x0-2 = Reserved. + * 0x3 = Data transfer is 4 bits in length. 0x4 = Data transfer is 5 bits in length. 0xF = Data + * transfer is 16 bits in length. + */ +#define SPI_FIFOWR_LEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_LEN_SHIFT)) & SPI_FIFOWR_LEN_MASK) +/*! @} */ + +/*! @name FIFORD - FIFO read data. */ +/*! @{ */ + +#define SPI_FIFORD_RXDATA_MASK (0xFFFFU) +#define SPI_FIFORD_RXDATA_SHIFT (0U) +/*! RXDATA - Received data from the FIFO. + */ +#define SPI_FIFORD_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXDATA_SHIFT)) & SPI_FIFORD_RXDATA_MASK) + +#define SPI_FIFORD_RXSSEL0_N_MASK (0x10000U) +#define SPI_FIFORD_RXSSEL0_N_SHIFT (16U) +/*! RXSSEL0_N - Slave Select for receive. This field allows the state of the SSEL0 pin to be saved + * along with received data. The value will reflect the SSEL0 pin for both master and slave + * operation. A zero indicates that a slave select is active. The actual polarity of each slave select + * pin is configured by the related SPOL bit in CFG. + */ +#define SPI_FIFORD_RXSSEL0_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL0_N_SHIFT)) & SPI_FIFORD_RXSSEL0_N_MASK) + +#define SPI_FIFORD_RXSSEL1_N_MASK (0x20000U) +#define SPI_FIFORD_RXSSEL1_N_SHIFT (17U) +/*! RXSSEL1_N - Slave Select for receive. This field allows the state of the SSEL1 pin to be saved + * along with received data. The value will reflect the SSEL1 pin for both master and slave + * operation. A zero indicates that a slave select is active. The actual polarity of each slave select + * pin is configured by the related SPOL bit in CFG. + */ +#define SPI_FIFORD_RXSSEL1_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL1_N_SHIFT)) & SPI_FIFORD_RXSSEL1_N_MASK) + +#define SPI_FIFORD_RXSSEL2_N_MASK (0x40000U) +#define SPI_FIFORD_RXSSEL2_N_SHIFT (18U) +/*! RXSSEL2_N - Slave Select for receive. This field allows the state of the SSEL2 pin to be saved + * along with received data. The value will reflect the SSEL2 pin for both master and slave + * operation. A zero indicates that a slave select is active. The actual polarity of each slave select + * pin is configured by the related SPOL bit in CFG. + */ +#define SPI_FIFORD_RXSSEL2_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL2_N_SHIFT)) & SPI_FIFORD_RXSSEL2_N_MASK) + +#define SPI_FIFORD_RXSSEL3_N_MASK (0x80000U) +#define SPI_FIFORD_RXSSEL3_N_SHIFT (19U) +/*! RXSSEL3_N - Slave Select for receive. This field allows the state of the SSEL3 pin to be saved + * along with received data. The value will reflect the SSEL3 pin for both master and slave + * operation. A zero indicates that a slave select is active. The actual polarity of each slave select + * pin is configured by the related SPOL bit in CFG. + */ +#define SPI_FIFORD_RXSSEL3_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL3_N_SHIFT)) & SPI_FIFORD_RXSSEL3_N_MASK) + +#define SPI_FIFORD_SOT_MASK (0x100000U) +#define SPI_FIFORD_SOT_SHIFT (20U) +/*! SOT - Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went + * from deasserted to asserted (i.e., any previous transfer has ended). This information can be + * used to identify the first piece of data in cases where the transfer length is greater than 16 + * bits. + */ +#define SPI_FIFORD_SOT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_SOT_SHIFT)) & SPI_FIFORD_SOT_MASK) +/*! @} */ + +/*! @name FIFORDNOPOP - FIFO data read with no FIFO pop. */ +/*! @{ */ + +#define SPI_FIFORDNOPOP_RXDATA_MASK (0xFFFFU) +#define SPI_FIFORDNOPOP_RXDATA_SHIFT (0U) +/*! RXDATA - Received data from the FIFO. + */ +#define SPI_FIFORDNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXDATA_SHIFT)) & SPI_FIFORDNOPOP_RXDATA_MASK) + +#define SPI_FIFORDNOPOP_RXSSEL0_N_MASK (0x10000U) +#define SPI_FIFORDNOPOP_RXSSEL0_N_SHIFT (16U) +/*! RXSSEL0_N - Slave Select for receive. + */ +#define SPI_FIFORDNOPOP_RXSSEL0_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL0_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL0_N_MASK) + +#define SPI_FIFORDNOPOP_RXSSEL1_N_MASK (0x20000U) +#define SPI_FIFORDNOPOP_RXSSEL1_N_SHIFT (17U) +/*! RXSSEL1_N - Slave Select for receive. + */ +#define SPI_FIFORDNOPOP_RXSSEL1_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL1_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL1_N_MASK) + +#define SPI_FIFORDNOPOP_RXSSEL2_N_MASK (0x40000U) +#define SPI_FIFORDNOPOP_RXSSEL2_N_SHIFT (18U) +/*! RXSSEL2_N - Slave Select for receive. + */ +#define SPI_FIFORDNOPOP_RXSSEL2_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL2_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL2_N_MASK) + +#define SPI_FIFORDNOPOP_RXSSEL3_N_MASK (0x80000U) +#define SPI_FIFORDNOPOP_RXSSEL3_N_SHIFT (19U) +/*! RXSSEL3_N - Slave Select for receive. + */ +#define SPI_FIFORDNOPOP_RXSSEL3_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL3_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL3_N_MASK) + +#define SPI_FIFORDNOPOP_SOT_MASK (0x100000U) +#define SPI_FIFORDNOPOP_SOT_SHIFT (20U) +/*! SOT - Start of transfer flag. + */ +#define SPI_FIFORDNOPOP_SOT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_SOT_SHIFT)) & SPI_FIFORDNOPOP_SOT_MASK) +/*! @} */ + +/*! @name FIFOSIZE - FIFO size register */ +/*! @{ */ + +#define SPI_FIFOSIZE_FIFOSIZE_MASK (0x1FU) +#define SPI_FIFOSIZE_FIFOSIZE_SHIFT (0U) +/*! FIFOSIZE - Provides the size of the FIFO for software. The size of the SPI FIFO is 8 entries. + */ +#define SPI_FIFOSIZE_FIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSIZE_FIFOSIZE_SHIFT)) & SPI_FIFOSIZE_FIFOSIZE_MASK) +/*! @} */ + +/*! @name ID - Peripheral identification register. */ +/*! @{ */ + +#define SPI_ID_APERTURE_MASK (0xFFU) +#define SPI_ID_APERTURE_SHIFT (0U) +/*! APERTURE - Aperture: encoded as (aperture size/4K) -1, so 0x00 means a 4K aperture. + */ +#define SPI_ID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << SPI_ID_APERTURE_SHIFT)) & SPI_ID_APERTURE_MASK) + +#define SPI_ID_MINOR_REV_MASK (0xF00U) +#define SPI_ID_MINOR_REV_SHIFT (8U) +/*! MINOR_REV - Minor revision of module implementation. + */ +#define SPI_ID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << SPI_ID_MINOR_REV_SHIFT)) & SPI_ID_MINOR_REV_MASK) + +#define SPI_ID_MAJOR_REV_MASK (0xF000U) +#define SPI_ID_MAJOR_REV_SHIFT (12U) +/*! MAJOR_REV - Major revision of module implementation. + */ +#define SPI_ID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << SPI_ID_MAJOR_REV_SHIFT)) & SPI_ID_MAJOR_REV_MASK) + +#define SPI_ID_ID_MASK (0xFFFF0000U) +#define SPI_ID_ID_SHIFT (16U) +/*! ID - Module identifier for the selected function. + */ +#define SPI_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << SPI_ID_ID_SHIFT)) & SPI_ID_ID_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group SPI_Register_Masks */ + + +/* SPI - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral SPI0 base address */ + #define SPI0_BASE (0x50086000u) + /** Peripheral SPI0 base address */ + #define SPI0_BASE_NS (0x40086000u) + /** Peripheral SPI0 base pointer */ + #define SPI0 ((SPI_Type *)SPI0_BASE) + /** Peripheral SPI0 base pointer */ + #define SPI0_NS ((SPI_Type *)SPI0_BASE_NS) + /** Peripheral SPI1 base address */ + #define SPI1_BASE (0x50087000u) + /** Peripheral SPI1 base address */ + #define SPI1_BASE_NS (0x40087000u) + /** Peripheral SPI1 base pointer */ + #define SPI1 ((SPI_Type *)SPI1_BASE) + /** Peripheral SPI1 base pointer */ + #define SPI1_NS ((SPI_Type *)SPI1_BASE_NS) + /** Peripheral SPI2 base address */ + #define SPI2_BASE (0x50088000u) + /** Peripheral SPI2 base address */ + #define SPI2_BASE_NS (0x40088000u) + /** Peripheral SPI2 base pointer */ + #define SPI2 ((SPI_Type *)SPI2_BASE) + /** Peripheral SPI2 base pointer */ + #define SPI2_NS ((SPI_Type *)SPI2_BASE_NS) + /** Peripheral SPI3 base address */ + #define SPI3_BASE (0x50089000u) + /** Peripheral SPI3 base address */ + #define SPI3_BASE_NS (0x40089000u) + /** Peripheral SPI3 base pointer */ + #define SPI3 ((SPI_Type *)SPI3_BASE) + /** Peripheral SPI3 base pointer */ + #define SPI3_NS ((SPI_Type *)SPI3_BASE_NS) + /** Peripheral SPI4 base address */ + #define SPI4_BASE (0x5008A000u) + /** Peripheral SPI4 base address */ + #define SPI4_BASE_NS (0x4008A000u) + /** Peripheral SPI4 base pointer */ + #define SPI4 ((SPI_Type *)SPI4_BASE) + /** Peripheral SPI4 base pointer */ + #define SPI4_NS ((SPI_Type *)SPI4_BASE_NS) + /** Peripheral SPI5 base address */ + #define SPI5_BASE (0x50096000u) + /** Peripheral SPI5 base address */ + #define SPI5_BASE_NS (0x40096000u) + /** Peripheral SPI5 base pointer */ + #define SPI5 ((SPI_Type *)SPI5_BASE) + /** Peripheral SPI5 base pointer */ + #define SPI5_NS ((SPI_Type *)SPI5_BASE_NS) + /** Peripheral SPI6 base address */ + #define SPI6_BASE (0x50097000u) + /** Peripheral SPI6 base address */ + #define SPI6_BASE_NS (0x40097000u) + /** Peripheral SPI6 base pointer */ + #define SPI6 ((SPI_Type *)SPI6_BASE) + /** Peripheral SPI6 base pointer */ + #define SPI6_NS ((SPI_Type *)SPI6_BASE_NS) + /** Peripheral SPI7 base address */ + #define SPI7_BASE (0x50098000u) + /** Peripheral SPI7 base address */ + #define SPI7_BASE_NS (0x40098000u) + /** Peripheral SPI7 base pointer */ + #define SPI7 ((SPI_Type *)SPI7_BASE) + /** Peripheral SPI7 base pointer */ + #define SPI7_NS ((SPI_Type *)SPI7_BASE_NS) + /** Peripheral SPI8 base address */ + #define SPI8_BASE (0x5009F000u) + /** Peripheral SPI8 base address */ + #define SPI8_BASE_NS (0x4009F000u) + /** Peripheral SPI8 base pointer */ + #define SPI8 ((SPI_Type *)SPI8_BASE) + /** Peripheral SPI8 base pointer */ + #define SPI8_NS ((SPI_Type *)SPI8_BASE_NS) + /** Array initializer of SPI peripheral base addresses */ + #define SPI_BASE_ADDRS { SPI0_BASE, SPI1_BASE, SPI2_BASE, SPI3_BASE, SPI4_BASE, SPI5_BASE, SPI6_BASE, SPI7_BASE, SPI8_BASE } + /** Array initializer of SPI peripheral base pointers */ + #define SPI_BASE_PTRS { SPI0, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SPI7, SPI8 } + /** Array initializer of SPI peripheral base addresses */ + #define SPI_BASE_ADDRS_NS { SPI0_BASE_NS, SPI1_BASE_NS, SPI2_BASE_NS, SPI3_BASE_NS, SPI4_BASE_NS, SPI5_BASE_NS, SPI6_BASE_NS, SPI7_BASE_NS, SPI8_BASE_NS } + /** Array initializer of SPI peripheral base pointers */ + #define SPI_BASE_PTRS_NS { SPI0_NS, SPI1_NS, SPI2_NS, SPI3_NS, SPI4_NS, SPI5_NS, SPI6_NS, SPI7_NS, SPI8_NS } +#else + /** Peripheral SPI0 base address */ + #define SPI0_BASE (0x40086000u) + /** Peripheral SPI0 base pointer */ + #define SPI0 ((SPI_Type *)SPI0_BASE) + /** Peripheral SPI1 base address */ + #define SPI1_BASE (0x40087000u) + /** Peripheral SPI1 base pointer */ + #define SPI1 ((SPI_Type *)SPI1_BASE) + /** Peripheral SPI2 base address */ + #define SPI2_BASE (0x40088000u) + /** Peripheral SPI2 base pointer */ + #define SPI2 ((SPI_Type *)SPI2_BASE) + /** Peripheral SPI3 base address */ + #define SPI3_BASE (0x40089000u) + /** Peripheral SPI3 base pointer */ + #define SPI3 ((SPI_Type *)SPI3_BASE) + /** Peripheral SPI4 base address */ + #define SPI4_BASE (0x4008A000u) + /** Peripheral SPI4 base pointer */ + #define SPI4 ((SPI_Type *)SPI4_BASE) + /** Peripheral SPI5 base address */ + #define SPI5_BASE (0x40096000u) + /** Peripheral SPI5 base pointer */ + #define SPI5 ((SPI_Type *)SPI5_BASE) + /** Peripheral SPI6 base address */ + #define SPI6_BASE (0x40097000u) + /** Peripheral SPI6 base pointer */ + #define SPI6 ((SPI_Type *)SPI6_BASE) + /** Peripheral SPI7 base address */ + #define SPI7_BASE (0x40098000u) + /** Peripheral SPI7 base pointer */ + #define SPI7 ((SPI_Type *)SPI7_BASE) + /** Peripheral SPI8 base address */ + #define SPI8_BASE (0x4009F000u) + /** Peripheral SPI8 base pointer */ + #define SPI8 ((SPI_Type *)SPI8_BASE) + /** Array initializer of SPI peripheral base addresses */ + #define SPI_BASE_ADDRS { SPI0_BASE, SPI1_BASE, SPI2_BASE, SPI3_BASE, SPI4_BASE, SPI5_BASE, SPI6_BASE, SPI7_BASE, SPI8_BASE } + /** Array initializer of SPI peripheral base pointers */ + #define SPI_BASE_PTRS { SPI0, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SPI7, SPI8 } +#endif +/** Interrupt vectors for the SPI peripheral type */ +#define SPI_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn, FLEXCOMM8_IRQn } + +/*! + * @} + */ /* end of group SPI_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- SYSCON Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SYSCON_Peripheral_Access_Layer SYSCON Peripheral Access Layer + * @{ + */ + +/** SYSCON - Register Layout Typedef */ +typedef struct { + __IO uint32_t MEMORYREMAP; /**< Memory Remap control register, offset: 0x0 */ + uint8_t RESERVED_0[12]; + __IO uint32_t AHBMATPRIO; /**< AHB Matrix priority control register Priority values are 3 = highest, 0 = lowest, offset: 0x10 */ + uint8_t RESERVED_1[36]; + __IO uint32_t CPU0STCKCAL; /**< System tick calibration for secure part of CPU0, offset: 0x38 */ + __IO uint32_t CPU0NSTCKCAL; /**< System tick calibration for non-secure part of CPU0, offset: 0x3C */ + uint8_t RESERVED_2[8]; + __IO uint32_t NMISRC; /**< NMI Source Select, offset: 0x48 */ + uint8_t RESERVED_3[180]; + union { /* offset: 0x100 */ + struct { /* offset: 0x100 */ + __IO uint32_t PRESETCTRL0; /**< Peripheral reset control 0, offset: 0x100 */ + __IO uint32_t PRESETCTRL1; /**< Peripheral reset control 1, offset: 0x104 */ + __IO uint32_t PRESETCTRL2; /**< Peripheral reset control 2, offset: 0x108 */ + } PRESETCTRL; + __IO uint32_t PRESETCTRLX[3]; /**< Peripheral reset control register, array offset: 0x100, array step: 0x4 */ + }; + uint8_t RESERVED_4[20]; + __IO uint32_t PRESETCTRLSET[3]; /**< Peripheral reset control set register, array offset: 0x120, array step: 0x4 */ + uint8_t RESERVED_5[20]; + __IO uint32_t PRESETCTRLCLR[3]; /**< Peripheral reset control clear register, array offset: 0x140, array step: 0x4 */ + uint8_t RESERVED_6[20]; + __O uint32_t SWR_RESET; /**< generate a software_reset, offset: 0x160 */ + uint8_t RESERVED_7[156]; + union { /* offset: 0x200 */ + struct { /* offset: 0x200 */ + __IO uint32_t AHBCLKCTRL0; /**< AHB Clock control 0, offset: 0x200 */ + __IO uint32_t AHBCLKCTRL1; /**< AHB Clock control 1, offset: 0x204 */ + __IO uint32_t AHBCLKCTRL2; /**< AHB Clock control 2, offset: 0x208 */ + } AHBCLKCTRL; + __IO uint32_t AHBCLKCTRLX[3]; /**< Peripheral reset control register, array offset: 0x200, array step: 0x4 */ + }; + uint8_t RESERVED_8[20]; + __IO uint32_t AHBCLKCTRLSET[3]; /**< Peripheral reset control register, array offset: 0x220, array step: 0x4 */ + uint8_t RESERVED_9[20]; + __IO uint32_t AHBCLKCTRLCLR[3]; /**< Peripheral reset control register, array offset: 0x240, array step: 0x4 */ + uint8_t RESERVED_10[20]; + union { /* offset: 0x260 */ + __IO uint32_t SYSTICKCLKSEL0; /**< System Tick Timer for CPU0 source select, offset: 0x260 */ + __IO uint32_t SYSTICKCLKSELX[1]; /**< Peripheral reset control register, array offset: 0x260, array step: 0x4 */ + }; + uint8_t RESERVED_11[4]; + __IO uint32_t TRACECLKSEL; /**< Trace clock source select, offset: 0x268 */ + union { /* offset: 0x26C */ + struct { /* offset: 0x26C */ + __IO uint32_t CTIMERCLKSEL0; /**< CTimer 0 clock source select, offset: 0x26C */ + __IO uint32_t CTIMERCLKSEL1; /**< CTimer 1 clock source select, offset: 0x270 */ + __IO uint32_t CTIMERCLKSEL2; /**< CTimer 2 clock source select, offset: 0x274 */ + __IO uint32_t CTIMERCLKSEL3; /**< CTimer 3 clock source select, offset: 0x278 */ + __IO uint32_t CTIMERCLKSEL4; /**< CTimer 4 clock source select, offset: 0x27C */ + } CTIMERCLKSEL; + __IO uint32_t CTIMERCLKSELX[5]; /**< Peripheral reset control register, array offset: 0x26C, array step: 0x4 */ + }; + __IO uint32_t MAINCLKSELA; /**< Main clock A source select, offset: 0x280 */ + __IO uint32_t MAINCLKSELB; /**< Main clock source select, offset: 0x284 */ + __IO uint32_t CLKOUTSEL; /**< CLKOUT clock source select, offset: 0x288 */ + uint8_t RESERVED_12[4]; + __IO uint32_t PLL0CLKSEL; /**< PLL0 clock source select, offset: 0x290 */ + __IO uint32_t PLL1CLKSEL; /**< PLL1 clock source select, offset: 0x294 */ + uint8_t RESERVED_13[8]; + __IO uint32_t CANCLKSEL; /**< CAN clock source select, offset: 0x2A0 */ + __IO uint32_t ADCCLKSEL; /**< ADC clock source select, offset: 0x2A4 */ + __IO uint32_t USB0CLKSEL; /**< FS USB clock source select, offset: 0x2A8 */ + __IO uint32_t CLK32KCLKSEL; /**< clock low speed source select for HS USB., offset: 0x2AC */ + union { /* offset: 0x2B0 */ + struct { /* offset: 0x2B0 */ + __IO uint32_t FCCLKSEL0; /**< Flexcomm Interface 0 clock source select for Fractional Rate Divider, offset: 0x2B0 */ + __IO uint32_t FCCLKSEL1; /**< Flexcomm Interface 1 clock source select for Fractional Rate Divider, offset: 0x2B4 */ + __IO uint32_t FCCLKSEL2; /**< Flexcomm Interface 2 clock source select for Fractional Rate Divider, offset: 0x2B8 */ + __IO uint32_t FCCLKSEL3; /**< Flexcomm Interface 3 clock source select for Fractional Rate Divider, offset: 0x2BC */ + __IO uint32_t FCCLKSEL4; /**< Flexcomm Interface 4 clock source select for Fractional Rate Divider, offset: 0x2C0 */ + __IO uint32_t FCCLKSEL5; /**< Flexcomm Interface 5 clock source select for Fractional Rate Divider, offset: 0x2C4 */ + __IO uint32_t FCCLKSEL6; /**< Flexcomm Interface 6 clock source select for Fractional Rate Divider, offset: 0x2C8 */ + __IO uint32_t FCCLKSEL7; /**< Flexcomm Interface 7 clock source select for Fractional Rate Divider, offset: 0x2CC */ + } FCCLKSEL; + __IO uint32_t FCCLKSELX[8]; /**< Peripheral reset control register, array offset: 0x2B0, array step: 0x4 */ + }; + __IO uint32_t HSLSPICLKSEL; /**< HS LSPI clock source select, offset: 0x2D0 */ + uint8_t RESERVED_14[12]; + __IO uint32_t MCLKCLKSEL; /**< MCLK clock source select, offset: 0x2E0 */ + uint8_t RESERVED_15[12]; + __IO uint32_t SCTCLKSEL; /**< SCTimer/PWM clock source select, offset: 0x2F0 */ + uint8_t RESERVED_16[12]; + __IO uint32_t SYSTICKCLKDIV0; /**< System Tick Timer divider for CPU0, offset: 0x300 */ + uint8_t RESERVED_17[4]; + __IO uint32_t TRACECLKDIV; /**< TRACE clock divider, offset: 0x308 */ + __IO uint32_t CANCLKDIV; /**< CAN clock divider, offset: 0x30C */ + uint8_t RESERVED_18[16]; + union { /* offset: 0x320 */ + struct { /* offset: 0x320 */ + __IO uint32_t FLEXFRG0CTRL; /**< Fractional rate divider for flexcomm 0, offset: 0x320 */ + __IO uint32_t FLEXFRG1CTRL; /**< Fractional rate divider for flexcomm 1, offset: 0x324 */ + __IO uint32_t FLEXFRG2CTRL; /**< Fractional rate divider for flexcomm 2, offset: 0x328 */ + __IO uint32_t FLEXFRG3CTRL; /**< Fractional rate divider for flexcomm 3, offset: 0x32C */ + __IO uint32_t FLEXFRG4CTRL; /**< Fractional rate divider for flexcomm 4, offset: 0x330 */ + __IO uint32_t FLEXFRG5CTRL; /**< Fractional rate divider for flexcomm 5, offset: 0x334 */ + __IO uint32_t FLEXFRG6CTRL; /**< Fractional rate divider for flexcomm 6, offset: 0x338 */ + __IO uint32_t FLEXFRG7CTRL; /**< Fractional rate divider for flexcomm 7, offset: 0x33C */ + } FLEXFRGCTRL; + __IO uint32_t FLEXFRGXCTRL[8]; /**< Peripheral reset control register, array offset: 0x320, array step: 0x4 */ + }; + uint8_t RESERVED_19[64]; + __IO uint32_t AHBCLKDIV; /**< System clock divider, offset: 0x380 */ + __IO uint32_t CLKOUTDIV; /**< CLKOUT clock divider, offset: 0x384 */ + __IO uint32_t FROHFDIV; /**< FRO_HF (96MHz) clock divider, offset: 0x388 */ + __IO uint32_t WDTCLKDIV; /**< WDT clock divider, offset: 0x38C */ + uint8_t RESERVED_20[4]; + __IO uint32_t ADCCLKDIV; /**< ADC clock divider, offset: 0x394 */ + __IO uint32_t USB0CLKDIV; /**< USB0-FS Clock divider, offset: 0x398 */ + uint8_t RESERVED_21[4]; + __IO uint32_t FRO1MCLKDIV; /**< FRO1MHz Clock divider (FRO1M_divided), offset: 0x3A0 */ + uint8_t RESERVED_22[8]; + __IO uint32_t MCLKDIV; /**< I2S MCLK clock divider, offset: 0x3AC */ + uint8_t RESERVED_23[4]; + __IO uint32_t SCTCLKDIV; /**< SCT/PWM clock divider, offset: 0x3B4 */ + uint8_t RESERVED_24[12]; + __IO uint32_t PLL0CLKDIV; /**< PLL0 clock divider, offset: 0x3C4 */ + uint8_t RESERVED_25[52]; + __IO uint32_t CLOCKGENUPDATELOCKOUT; /**< Control clock configuration registers access (like xxxDIV, xxxSEL), offset: 0x3FC */ + __IO uint32_t FMCCR; /**< FMC configuration register, offset: 0x400 */ + uint8_t RESERVED_26[8]; + __IO uint32_t USB0NEEDCLKCTRL; /**< USB0-FS need clock control, offset: 0x40C */ + __I uint32_t USB0NEEDCLKSTAT; /**< USB0-FS need clock status, offset: 0x410 */ + uint8_t RESERVED_27[8]; + __O uint32_t FMCFLUSH; /**< FMCflush control, offset: 0x41C */ + __IO uint32_t MCLKIO; /**< MCLK control, offset: 0x420 */ + __IO uint32_t USB1NEEDCLKCTRL; /**< USB1-HS need clock control, offset: 0x424 */ + __I uint32_t USB1NEEDCLKSTAT; /**< USB1-HS need clock status, offset: 0x428 */ + uint8_t RESERVED_28[20]; + __IO uint32_t FLASHREMAP_SIZE; /**< This 32-bit register contains the size of the image to remap, in bytes. The 12 LSBs are ignored, so the size granularity is 4KB., offset: 0x440 */ + __IO uint32_t FLASHREMAP_SIZE_DP; /**< This 32-bit register is a duplicate of FLASHREMAPSIZE for increased security., offset: 0x444 */ + __IO uint32_t FLASHREMAP_OFFSET; /**< This 32-bit register contains the offset by which the image is to be remapped. The 12 LSBs are ignored, so the remap granularity is 4KB., offset: 0x448 */ + __IO uint32_t FLASHREMAP_OFFSET_DP; /**< This 32-bit register is a duplicate of FLASHREMAPOFFSET for increased security., offset: 0x44C */ + uint8_t RESERVED_29[12]; + __IO uint32_t FLASHREMAP_LOCK; /**< Control write access to FLASHREMAP_SIZE and FLASHREMAP_OFFSET registers., offset: 0x45C */ + uint8_t RESERVED_30[16]; + __IO uint32_t CASPER_CTRL; /**< Control CASPER integration., offset: 0x470 */ + uint8_t RESERVED_31[236]; + __IO uint32_t PLL1CTRL; /**< PLL1 550m control, offset: 0x560 */ + __I uint32_t PLL1STAT; /**< PLL1 550m status, offset: 0x564 */ + __IO uint32_t PLL1NDEC; /**< PLL1 550m N divider, offset: 0x568 */ + __IO uint32_t PLL1MDEC; /**< PLL1 550m M divider, offset: 0x56C */ + __IO uint32_t PLL1PDEC; /**< PLL1 550m P divider, offset: 0x570 */ + uint8_t RESERVED_32[12]; + __IO uint32_t PLL0CTRL; /**< PLL0 550m control, offset: 0x580 */ + __I uint32_t PLL0STAT; /**< PLL0 550m status, offset: 0x584 */ + __IO uint32_t PLL0NDEC; /**< PLL0 550m N divider, offset: 0x588 */ + __IO uint32_t PLL0PDEC; /**< PLL0 550m P divider, offset: 0x58C */ + __IO uint32_t PLL0SSCG0; /**< PLL0 Spread Spectrum Wrapper control register 0, offset: 0x590 */ + __IO uint32_t PLL0SSCG1; /**< PLL0 Spread Spectrum Wrapper control register 1, offset: 0x594 */ + uint8_t RESERVED_33[364]; + __IO uint32_t FUNCRETENTIONCTRL; /**< Functional retention control register, offset: 0x704 */ + uint8_t RESERVED_34[260]; + __I uint32_t CPSTAT; /**< CPU Status, offset: 0x80C */ + uint8_t RESERVED_35[272]; + __IO uint32_t BOOT_SEED_REG0; /**< boot seed (256-bit random value), offset: 0x920 */ + __IO uint32_t BOOT_SEED_REG1; /**< boot seed (256-bit random value), offset: 0x924 */ + __IO uint32_t BOOT_SEED_REG2; /**< boot seed (256-bit random value), offset: 0x928 */ + __IO uint32_t BOOT_SEED_REG3; /**< boot seed (256-bit random value), offset: 0x92C */ + __IO uint32_t BOOT_SEED_REG4; /**< boot seed (256-bit random value), offset: 0x930 */ + __IO uint32_t BOOT_SEED_REG5; /**< boot seed (256-bit random value), offset: 0x934 */ + __IO uint32_t BOOT_SEED_REG6; /**< boot seed (256-bit random value), offset: 0x938 */ + __IO uint32_t BOOT_SEED_REG7; /**< boot seed (256-bit random value), offset: 0x93C */ + __IO uint32_t HMAC_REG0; /**< HMAC, offset: 0x940 */ + __IO uint32_t HMAC_REG1; /**< HMAC, offset: 0x944 */ + __IO uint32_t HMAC_REG2; /**< HMAC, offset: 0x948 */ + __IO uint32_t HMAC_REG3; /**< HMAC, offset: 0x94C */ + __IO uint32_t HMAC_REG4; /**< HMAC, offset: 0x950 */ + __IO uint32_t HMAC_REG5; /**< HMAC, offset: 0x954 */ + __IO uint32_t HMAC_REG6; /**< HMAC, offset: 0x958 */ + __IO uint32_t HMAC_REG7; /**< HMAC, offset: 0x95C */ + __IO uint32_t BOOT_LOCK; /**< Control write access to boot seed security registers., offset: 0x960 */ + uint8_t RESERVED_36[180]; + __IO uint32_t CLOCK_CTRL; /**< Various system clock controls : Flash clock (48 MHz) control, clocks to Frequency Measures, offset: 0xA18 */ + uint8_t RESERVED_37[244]; + __IO uint32_t COMP_INT_CTRL; /**< Comparator Interrupt control, offset: 0xB10 */ + __I uint32_t COMP_INT_STATUS; /**< Comparator Interrupt status, offset: 0xB14 */ + uint8_t RESERVED_38[748]; + __IO uint32_t AUTOCLKGATEOVERRIDE; /**< Control automatic clock gating, offset: 0xE04 */ + __IO uint32_t GPIOPSYNC; /**< Enable bypass of the first stage of synchonization inside GPIO_INT module, offset: 0xE08 */ + uint8_t RESERVED_39[380]; + __IO uint32_t HASHRESTHWKEY; /**< Controls whether the HASH AES hardware secret key is restricted to use by secure code, offset: 0xF88 */ + uint8_t RESERVED_40[20]; + __IO uint32_t DEBUG_LOCK_EN; /**< Control write access to security registers., offset: 0xFA0 */ + __IO uint32_t DEBUG_FEATURES; /**< Cortex debug features control., offset: 0xFA4 */ + __IO uint32_t DEBUG_FEATURES_DP; /**< Cortex debug features control. (duplicate), offset: 0xFA8 */ + uint8_t RESERVED_41[8]; + __IO uint32_t SWD_ACCESS_CPU0; /**< This register is used by ROM during DEBUG authentication mechanism to enable debug access port for CPU0., offset: 0xFB4 */ + uint8_t RESERVED_42[4]; + __O uint32_t KEY_BLOCK; /**< block quiddikey/PUF all index., offset: 0xFBC */ + __IO uint32_t DEBUG_AUTH_BEACON; /**< Debug authentication BEACON register, offset: 0xFC0 */ + uint8_t RESERVED_43[52]; + __I uint32_t DEVICE_ID0; /**< Device ID, offset: 0xFF8 */ + __I uint32_t DIEID; /**< Chip revision ID and Number, offset: 0xFFC */ +} SYSCON_Type; + +/* ---------------------------------------------------------------------------- + -- SYSCON Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SYSCON_Register_Masks SYSCON Register Masks + * @{ + */ + +/*! @name MEMORYREMAP - Memory Remap control register */ +/*! @{ */ + +#define SYSCON_MEMORYREMAP_MAP_MASK (0x3U) +#define SYSCON_MEMORYREMAP_MAP_SHIFT (0U) +/*! MAP - Select the location of the vector table :. + * 0b00..Vector Table in ROM. + * 0b01..Vector Table in RAM. + * 0b10..Vector Table in Flash. + * 0b11..Vector Table in Flash. + */ +#define SYSCON_MEMORYREMAP_MAP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MEMORYREMAP_MAP_SHIFT)) & SYSCON_MEMORYREMAP_MAP_MASK) +/*! @} */ + +/*! @name AHBMATPRIO - AHB Matrix priority control register Priority values are 3 = highest, 0 = lowest */ +/*! @{ */ + +#define SYSCON_AHBMATPRIO_PRI_CPU0_CBUS_MASK (0x3U) +#define SYSCON_AHBMATPRIO_PRI_CPU0_CBUS_SHIFT (0U) +/*! PRI_CPU0_CBUS - CPU0 C-AHB bus. + */ +#define SYSCON_AHBMATPRIO_PRI_CPU0_CBUS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_CPU0_CBUS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_CPU0_CBUS_MASK) + +#define SYSCON_AHBMATPRIO_PRI_CPU0_SBUS_MASK (0xCU) +#define SYSCON_AHBMATPRIO_PRI_CPU0_SBUS_SHIFT (2U) +/*! PRI_CPU0_SBUS - CPU0 S-AHB bus. + */ +#define SYSCON_AHBMATPRIO_PRI_CPU0_SBUS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_CPU0_SBUS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_CPU0_SBUS_MASK) + +#define SYSCON_AHBMATPRIO_PRI_SDMA0_MASK (0x30U) +#define SYSCON_AHBMATPRIO_PRI_SDMA0_SHIFT (4U) +/*! PRI_SDMA0 - DMA0 controller priority. + */ +#define SYSCON_AHBMATPRIO_PRI_SDMA0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_SDMA0_SHIFT)) & SYSCON_AHBMATPRIO_PRI_SDMA0_MASK) + +#define SYSCON_AHBMATPRIO_PRI_SDMA1_MASK (0xC0U) +#define SYSCON_AHBMATPRIO_PRI_SDMA1_SHIFT (6U) +/*! PRI_SDMA1 - DMA1 controller priority. + */ +#define SYSCON_AHBMATPRIO_PRI_SDMA1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_SDMA1_SHIFT)) & SYSCON_AHBMATPRIO_PRI_SDMA1_MASK) + +#define SYSCON_AHBMATPRIO_PRI_USB_FSD_MASK (0x300U) +#define SYSCON_AHBMATPRIO_PRI_USB_FSD_SHIFT (8U) +/*! PRI_USB_FSD - USB0-FS Device.(USB0) + */ +#define SYSCON_AHBMATPRIO_PRI_USB_FSD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_USB_FSD_SHIFT)) & SYSCON_AHBMATPRIO_PRI_USB_FSD_MASK) + +#define SYSCON_AHBMATPRIO_PRI_USB_FSH_MASK (0xC00U) +#define SYSCON_AHBMATPRIO_PRI_USB_FSH_SHIFT (10U) +/*! PRI_USB_FSH - USB0-FS host.(USB0) + */ +#define SYSCON_AHBMATPRIO_PRI_USB_FSH(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_USB_FSH_SHIFT)) & SYSCON_AHBMATPRIO_PRI_USB_FSH_MASK) + +#define SYSCON_AHBMATPRIO_PRI_HASH_AES_MASK (0x30000U) +#define SYSCON_AHBMATPRIO_PRI_HASH_AES_SHIFT (16U) +/*! PRI_HASH_AES - HASH_AES. + */ +#define SYSCON_AHBMATPRIO_PRI_HASH_AES(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_HASH_AES_SHIFT)) & SYSCON_AHBMATPRIO_PRI_HASH_AES_MASK) + +#define SYSCON_AHBMATPRIO_PRI_CANFD_MASK (0xC0000U) +#define SYSCON_AHBMATPRIO_PRI_CANFD_SHIFT (18U) +/*! PRI_CANFD - CANFD. + */ +#define SYSCON_AHBMATPRIO_PRI_CANFD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_CANFD_SHIFT)) & SYSCON_AHBMATPRIO_PRI_CANFD_MASK) +/*! @} */ + +/*! @name CPU0STCKCAL - System tick calibration for secure part of CPU0 */ +/*! @{ */ + +#define SYSCON_CPU0STCKCAL_TENMS_MASK (0xFFFFFFU) +#define SYSCON_CPU0STCKCAL_TENMS_SHIFT (0U) +/*! TENMS - Reload value for 10ms (100Hz) timing, subject to system clock skew errors. If the value + * reads as zero, the calibration value is not known. + */ +#define SYSCON_CPU0STCKCAL_TENMS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0STCKCAL_TENMS_SHIFT)) & SYSCON_CPU0STCKCAL_TENMS_MASK) + +#define SYSCON_CPU0STCKCAL_SKEW_MASK (0x1000000U) +#define SYSCON_CPU0STCKCAL_SKEW_SHIFT (24U) +/*! SKEW - Initial value for the Systick timer. + */ +#define SYSCON_CPU0STCKCAL_SKEW(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0STCKCAL_SKEW_SHIFT)) & SYSCON_CPU0STCKCAL_SKEW_MASK) + +#define SYSCON_CPU0STCKCAL_NOREF_MASK (0x2000000U) +#define SYSCON_CPU0STCKCAL_NOREF_SHIFT (25U) +/*! NOREF - Indicates whether the device provides a reference clock to the processor: 0 = reference + * clock provided; 1 = no reference clock provided. + */ +#define SYSCON_CPU0STCKCAL_NOREF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0STCKCAL_NOREF_SHIFT)) & SYSCON_CPU0STCKCAL_NOREF_MASK) +/*! @} */ + +/*! @name CPU0NSTCKCAL - System tick calibration for non-secure part of CPU0 */ +/*! @{ */ + +#define SYSCON_CPU0NSTCKCAL_TENMS_MASK (0xFFFFFFU) +#define SYSCON_CPU0NSTCKCAL_TENMS_SHIFT (0U) +/*! TENMS - Reload value for 10 ms (100 Hz) timing, subject to system clock skew errors. If the + * value reads as zero, the calibration value is not known. + */ +#define SYSCON_CPU0NSTCKCAL_TENMS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0NSTCKCAL_TENMS_SHIFT)) & SYSCON_CPU0NSTCKCAL_TENMS_MASK) + +#define SYSCON_CPU0NSTCKCAL_SKEW_MASK (0x1000000U) +#define SYSCON_CPU0NSTCKCAL_SKEW_SHIFT (24U) +/*! SKEW - Indicates whether the TENMS value is exact: 0 = TENMS value is exact; 1 = TENMS value is inexact, or not given. + */ +#define SYSCON_CPU0NSTCKCAL_SKEW(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0NSTCKCAL_SKEW_SHIFT)) & SYSCON_CPU0NSTCKCAL_SKEW_MASK) + +#define SYSCON_CPU0NSTCKCAL_NOREF_MASK (0x2000000U) +#define SYSCON_CPU0NSTCKCAL_NOREF_SHIFT (25U) +/*! NOREF - Initial value for the Systick timer. + */ +#define SYSCON_CPU0NSTCKCAL_NOREF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0NSTCKCAL_NOREF_SHIFT)) & SYSCON_CPU0NSTCKCAL_NOREF_MASK) +/*! @} */ + +/*! @name NMISRC - NMI Source Select */ +/*! @{ */ + +#define SYSCON_NMISRC_IRQCPU0_MASK (0x3FU) +#define SYSCON_NMISRC_IRQCPU0_SHIFT (0U) +/*! IRQCPU0 - The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) for the CPU0, if enabled by NMIENCPU0. + */ +#define SYSCON_NMISRC_IRQCPU0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_IRQCPU0_SHIFT)) & SYSCON_NMISRC_IRQCPU0_MASK) + +#define SYSCON_NMISRC_NMIENCPU0_MASK (0x80000000U) +#define SYSCON_NMISRC_NMIENCPU0_SHIFT (31U) +/*! NMIENCPU0 - Write a 1 to this bit to enable the Non-Maskable Interrupt (NMI) source selected by IRQCPU0. + */ +#define SYSCON_NMISRC_NMIENCPU0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_NMIENCPU0_SHIFT)) & SYSCON_NMISRC_NMIENCPU0_MASK) +/*! @} */ + +/*! @name PRESETCTRL0 - Peripheral reset control 0 */ +/*! @{ */ + +#define SYSCON_PRESETCTRL0_ROM_RST_MASK (0x2U) +#define SYSCON_PRESETCTRL0_ROM_RST_SHIFT (1U) +/*! ROM_RST - ROM reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL0_ROM_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_ROM_RST_SHIFT)) & SYSCON_PRESETCTRL0_ROM_RST_MASK) + +#define SYSCON_PRESETCTRL0_SRAM_CTRL1_RST_MASK (0x8U) +#define SYSCON_PRESETCTRL0_SRAM_CTRL1_RST_SHIFT (3U) +/*! SRAM_CTRL1_RST - SRAM Controller 1 reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL0_SRAM_CTRL1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_SRAM_CTRL1_RST_SHIFT)) & SYSCON_PRESETCTRL0_SRAM_CTRL1_RST_MASK) + +#define SYSCON_PRESETCTRL0_SRAM_CTRL2_RST_MASK (0x10U) +#define SYSCON_PRESETCTRL0_SRAM_CTRL2_RST_SHIFT (4U) +/*! SRAM_CTRL2_RST - SRAM Controller 2 reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL0_SRAM_CTRL2_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_SRAM_CTRL2_RST_SHIFT)) & SYSCON_PRESETCTRL0_SRAM_CTRL2_RST_MASK) + +#define SYSCON_PRESETCTRL0_FLASH_RST_MASK (0x80U) +#define SYSCON_PRESETCTRL0_FLASH_RST_SHIFT (7U) +/*! FLASH_RST - Flash controller reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL0_FLASH_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_FLASH_RST_SHIFT)) & SYSCON_PRESETCTRL0_FLASH_RST_MASK) + +#define SYSCON_PRESETCTRL0_FMC_RST_MASK (0x100U) +#define SYSCON_PRESETCTRL0_FMC_RST_SHIFT (8U) +/*! FMC_RST - FMC controller reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL0_FMC_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_FMC_RST_SHIFT)) & SYSCON_PRESETCTRL0_FMC_RST_MASK) + +#define SYSCON_PRESETCTRL0_MUX_RST_MASK (0x800U) +#define SYSCON_PRESETCTRL0_MUX_RST_SHIFT (11U) +/*! MUX_RST - Input Mux reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL0_MUX_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_MUX_RST_SHIFT)) & SYSCON_PRESETCTRL0_MUX_RST_MASK) + +#define SYSCON_PRESETCTRL0_IOCON_RST_MASK (0x2000U) +#define SYSCON_PRESETCTRL0_IOCON_RST_SHIFT (13U) +/*! IOCON_RST - I/O controller reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL0_IOCON_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_IOCON_RST_SHIFT)) & SYSCON_PRESETCTRL0_IOCON_RST_MASK) + +#define SYSCON_PRESETCTRL0_GPIO0_RST_MASK (0x4000U) +#define SYSCON_PRESETCTRL0_GPIO0_RST_SHIFT (14U) +/*! GPIO0_RST - GPIO0 reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL0_GPIO0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_GPIO0_RST_SHIFT)) & SYSCON_PRESETCTRL0_GPIO0_RST_MASK) + +#define SYSCON_PRESETCTRL0_GPIO1_RST_MASK (0x8000U) +#define SYSCON_PRESETCTRL0_GPIO1_RST_SHIFT (15U) +/*! GPIO1_RST - GPIO1 reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL0_GPIO1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_GPIO1_RST_SHIFT)) & SYSCON_PRESETCTRL0_GPIO1_RST_MASK) + +#define SYSCON_PRESETCTRL0_PINT_RST_MASK (0x40000U) +#define SYSCON_PRESETCTRL0_PINT_RST_SHIFT (18U) +/*! PINT_RST - Pin interrupt (PINT) reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL0_PINT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_PINT_RST_SHIFT)) & SYSCON_PRESETCTRL0_PINT_RST_MASK) + +#define SYSCON_PRESETCTRL0_GINT_RST_MASK (0x80000U) +#define SYSCON_PRESETCTRL0_GINT_RST_SHIFT (19U) +/*! GINT_RST - Group interrupt (GINT) reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL0_GINT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_GINT_RST_SHIFT)) & SYSCON_PRESETCTRL0_GINT_RST_MASK) + +#define SYSCON_PRESETCTRL0_DMA0_RST_MASK (0x100000U) +#define SYSCON_PRESETCTRL0_DMA0_RST_SHIFT (20U) +/*! DMA0_RST - DMA0 reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL0_DMA0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_DMA0_RST_SHIFT)) & SYSCON_PRESETCTRL0_DMA0_RST_MASK) + +#define SYSCON_PRESETCTRL0_CRCGEN_RST_MASK (0x200000U) +#define SYSCON_PRESETCTRL0_CRCGEN_RST_SHIFT (21U) +/*! CRCGEN_RST - CRCGEN reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL0_CRCGEN_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_CRCGEN_RST_SHIFT)) & SYSCON_PRESETCTRL0_CRCGEN_RST_MASK) + +#define SYSCON_PRESETCTRL0_WWDT_RST_MASK (0x400000U) +#define SYSCON_PRESETCTRL0_WWDT_RST_SHIFT (22U) +/*! WWDT_RST - Watchdog Timer reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL0_WWDT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_WWDT_RST_SHIFT)) & SYSCON_PRESETCTRL0_WWDT_RST_MASK) + +#define SYSCON_PRESETCTRL0_RTC_RST_MASK (0x800000U) +#define SYSCON_PRESETCTRL0_RTC_RST_SHIFT (23U) +/*! RTC_RST - Real Time Clock (RTC) reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL0_RTC_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_RTC_RST_SHIFT)) & SYSCON_PRESETCTRL0_RTC_RST_MASK) + +#define SYSCON_PRESETCTRL0_MAILBOX_RST_MASK (0x4000000U) +#define SYSCON_PRESETCTRL0_MAILBOX_RST_SHIFT (26U) +/*! MAILBOX_RST - Inter CPU communication Mailbox reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL0_MAILBOX_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_MAILBOX_RST_SHIFT)) & SYSCON_PRESETCTRL0_MAILBOX_RST_MASK) + +#define SYSCON_PRESETCTRL0_ADC_RST_MASK (0x8000000U) +#define SYSCON_PRESETCTRL0_ADC_RST_SHIFT (27U) +/*! ADC_RST - ADC reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL0_ADC_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_ADC_RST_SHIFT)) & SYSCON_PRESETCTRL0_ADC_RST_MASK) +/*! @} */ + +/*! @name PRESETCTRL1 - Peripheral reset control 1 */ +/*! @{ */ + +#define SYSCON_PRESETCTRL1_MRT_RST_MASK (0x1U) +#define SYSCON_PRESETCTRL1_MRT_RST_SHIFT (0U) +/*! MRT_RST - MRT reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL1_MRT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_MRT_RST_SHIFT)) & SYSCON_PRESETCTRL1_MRT_RST_MASK) + +#define SYSCON_PRESETCTRL1_OSTIMER_RST_MASK (0x2U) +#define SYSCON_PRESETCTRL1_OSTIMER_RST_SHIFT (1U) +/*! OSTIMER_RST - OS Event Timer reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL1_OSTIMER_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_OSTIMER_RST_SHIFT)) & SYSCON_PRESETCTRL1_OSTIMER_RST_MASK) + +#define SYSCON_PRESETCTRL1_SCT_RST_MASK (0x4U) +#define SYSCON_PRESETCTRL1_SCT_RST_SHIFT (2U) +/*! SCT_RST - SCT reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL1_SCT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_SCT_RST_SHIFT)) & SYSCON_PRESETCTRL1_SCT_RST_MASK) + +#define SYSCON_PRESETCTRL1_CAN_RST_MASK (0x80U) +#define SYSCON_PRESETCTRL1_CAN_RST_SHIFT (7U) +/*! CAN_RST - CAN reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL1_CAN_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_CAN_RST_SHIFT)) & SYSCON_PRESETCTRL1_CAN_RST_MASK) + +#define SYSCON_PRESETCTRL1_UTICK_RST_MASK (0x400U) +#define SYSCON_PRESETCTRL1_UTICK_RST_SHIFT (10U) +/*! UTICK_RST - UTICK reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL1_UTICK_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_UTICK_RST_SHIFT)) & SYSCON_PRESETCTRL1_UTICK_RST_MASK) + +#define SYSCON_PRESETCTRL1_FC0_RST_MASK (0x800U) +#define SYSCON_PRESETCTRL1_FC0_RST_SHIFT (11U) +/*! FC0_RST - FC0 reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL1_FC0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC0_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC0_RST_MASK) + +#define SYSCON_PRESETCTRL1_FC1_RST_MASK (0x1000U) +#define SYSCON_PRESETCTRL1_FC1_RST_SHIFT (12U) +/*! FC1_RST - FC1 reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL1_FC1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC1_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC1_RST_MASK) + +#define SYSCON_PRESETCTRL1_FC2_RST_MASK (0x2000U) +#define SYSCON_PRESETCTRL1_FC2_RST_SHIFT (13U) +/*! FC2_RST - FC2 reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL1_FC2_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC2_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC2_RST_MASK) + +#define SYSCON_PRESETCTRL1_FC3_RST_MASK (0x4000U) +#define SYSCON_PRESETCTRL1_FC3_RST_SHIFT (14U) +/*! FC3_RST - FC3 reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL1_FC3_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC3_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC3_RST_MASK) + +#define SYSCON_PRESETCTRL1_FC4_RST_MASK (0x8000U) +#define SYSCON_PRESETCTRL1_FC4_RST_SHIFT (15U) +/*! FC4_RST - FC4 reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL1_FC4_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC4_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC4_RST_MASK) + +#define SYSCON_PRESETCTRL1_FC5_RST_MASK (0x10000U) +#define SYSCON_PRESETCTRL1_FC5_RST_SHIFT (16U) +/*! FC5_RST - FC5 reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL1_FC5_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC5_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC5_RST_MASK) + +#define SYSCON_PRESETCTRL1_FC6_RST_MASK (0x20000U) +#define SYSCON_PRESETCTRL1_FC6_RST_SHIFT (17U) +/*! FC6_RST - FC6 reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL1_FC6_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC6_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC6_RST_MASK) + +#define SYSCON_PRESETCTRL1_FC7_RST_MASK (0x40000U) +#define SYSCON_PRESETCTRL1_FC7_RST_SHIFT (18U) +/*! FC7_RST - FC7 reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL1_FC7_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC7_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC7_RST_MASK) + +#define SYSCON_PRESETCTRL1_TIMER2_RST_MASK (0x400000U) +#define SYSCON_PRESETCTRL1_TIMER2_RST_SHIFT (22U) +/*! TIMER2_RST - Timer 2 reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL1_TIMER2_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_TIMER2_RST_SHIFT)) & SYSCON_PRESETCTRL1_TIMER2_RST_MASK) + +#define SYSCON_PRESETCTRL1_USB0_DEV_RST_MASK (0x2000000U) +#define SYSCON_PRESETCTRL1_USB0_DEV_RST_SHIFT (25U) +/*! USB0_DEV_RST - USB0-FS DEV reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL1_USB0_DEV_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_USB0_DEV_RST_SHIFT)) & SYSCON_PRESETCTRL1_USB0_DEV_RST_MASK) + +#define SYSCON_PRESETCTRL1_TIMER0_RST_MASK (0x4000000U) +#define SYSCON_PRESETCTRL1_TIMER0_RST_SHIFT (26U) +/*! TIMER0_RST - Timer 0 reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL1_TIMER0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_TIMER0_RST_SHIFT)) & SYSCON_PRESETCTRL1_TIMER0_RST_MASK) + +#define SYSCON_PRESETCTRL1_TIMER1_RST_MASK (0x8000000U) +#define SYSCON_PRESETCTRL1_TIMER1_RST_SHIFT (27U) +/*! TIMER1_RST - Timer 1 reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL1_TIMER1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_TIMER1_RST_SHIFT)) & SYSCON_PRESETCTRL1_TIMER1_RST_MASK) +/*! @} */ + +/*! @name PRESETCTRL2 - Peripheral reset control 2 */ +/*! @{ */ + +#define SYSCON_PRESETCTRL2_DMA1_RST_MASK (0x2U) +#define SYSCON_PRESETCTRL2_DMA1_RST_SHIFT (1U) +/*! DMA1_RST - DMA1 reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL2_DMA1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_DMA1_RST_SHIFT)) & SYSCON_PRESETCTRL2_DMA1_RST_MASK) + +#define SYSCON_PRESETCTRL2_COMP_RST_MASK (0x4U) +#define SYSCON_PRESETCTRL2_COMP_RST_SHIFT (2U) +/*! COMP_RST - Comparator reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL2_COMP_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_COMP_RST_SHIFT)) & SYSCON_PRESETCTRL2_COMP_RST_MASK) + +#define SYSCON_PRESETCTRL2_USB1_HOST_RST_MASK (0x10U) +#define SYSCON_PRESETCTRL2_USB1_HOST_RST_SHIFT (4U) +/*! USB1_HOST_RST - USB1-HS Host reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL2_USB1_HOST_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_USB1_HOST_RST_SHIFT)) & SYSCON_PRESETCTRL2_USB1_HOST_RST_MASK) + +#define SYSCON_PRESETCTRL2_USB1_DEV_RST_MASK (0x20U) +#define SYSCON_PRESETCTRL2_USB1_DEV_RST_SHIFT (5U) +/*! USB1_DEV_RST - USB1-HS dev reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL2_USB1_DEV_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_USB1_DEV_RST_SHIFT)) & SYSCON_PRESETCTRL2_USB1_DEV_RST_MASK) + +#define SYSCON_PRESETCTRL2_USB1_RAM_RST_MASK (0x40U) +#define SYSCON_PRESETCTRL2_USB1_RAM_RST_SHIFT (6U) +/*! USB1_RAM_RST - USB1-HS RAM reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL2_USB1_RAM_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_USB1_RAM_RST_SHIFT)) & SYSCON_PRESETCTRL2_USB1_RAM_RST_MASK) + +#define SYSCON_PRESETCTRL2_USB1_PHY_RST_MASK (0x80U) +#define SYSCON_PRESETCTRL2_USB1_PHY_RST_SHIFT (7U) +/*! USB1_PHY_RST - USB1-HS PHY reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL2_USB1_PHY_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_USB1_PHY_RST_SHIFT)) & SYSCON_PRESETCTRL2_USB1_PHY_RST_MASK) + +#define SYSCON_PRESETCTRL2_FREQME_RST_MASK (0x100U) +#define SYSCON_PRESETCTRL2_FREQME_RST_SHIFT (8U) +/*! FREQME_RST - Frequency meter reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL2_FREQME_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_FREQME_RST_SHIFT)) & SYSCON_PRESETCTRL2_FREQME_RST_MASK) + +#define SYSCON_PRESETCTRL2_CDOG_RST_MASK (0x800U) +#define SYSCON_PRESETCTRL2_CDOG_RST_SHIFT (11U) +/*! CDOG_RST - Code Watchdog reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL2_CDOG_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_CDOG_RST_SHIFT)) & SYSCON_PRESETCTRL2_CDOG_RST_MASK) + +#define SYSCON_PRESETCTRL2_RNG_RST_MASK (0x2000U) +#define SYSCON_PRESETCTRL2_RNG_RST_SHIFT (13U) +/*! RNG_RST - RNG reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL2_RNG_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_RNG_RST_SHIFT)) & SYSCON_PRESETCTRL2_RNG_RST_MASK) + +#define SYSCON_PRESETCTRL2_SYSCTL_RST_MASK (0x8000U) +#define SYSCON_PRESETCTRL2_SYSCTL_RST_SHIFT (15U) +/*! SYSCTL_RST - SYSCTL Block reset. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL2_SYSCTL_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_SYSCTL_RST_SHIFT)) & SYSCON_PRESETCTRL2_SYSCTL_RST_MASK) + +#define SYSCON_PRESETCTRL2_USB0_HOSTM_RST_MASK (0x10000U) +#define SYSCON_PRESETCTRL2_USB0_HOSTM_RST_SHIFT (16U) +/*! USB0_HOSTM_RST - USB0-FS Host Master reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL2_USB0_HOSTM_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_USB0_HOSTM_RST_SHIFT)) & SYSCON_PRESETCTRL2_USB0_HOSTM_RST_MASK) + +#define SYSCON_PRESETCTRL2_USB0_HOSTS_RST_MASK (0x20000U) +#define SYSCON_PRESETCTRL2_USB0_HOSTS_RST_SHIFT (17U) +/*! USB0_HOSTS_RST - USB0-FS Host Slave reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL2_USB0_HOSTS_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_USB0_HOSTS_RST_SHIFT)) & SYSCON_PRESETCTRL2_USB0_HOSTS_RST_MASK) + +#define SYSCON_PRESETCTRL2_HASH_AES_RST_MASK (0x40000U) +#define SYSCON_PRESETCTRL2_HASH_AES_RST_SHIFT (18U) +/*! HASH_AES_RST - HASH_AES reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL2_HASH_AES_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_HASH_AES_RST_SHIFT)) & SYSCON_PRESETCTRL2_HASH_AES_RST_MASK) + +#define SYSCON_PRESETCTRL2_PLULUT_RST_MASK (0x100000U) +#define SYSCON_PRESETCTRL2_PLULUT_RST_SHIFT (20U) +/*! PLULUT_RST - PLU LUT reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL2_PLULUT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_PLULUT_RST_SHIFT)) & SYSCON_PRESETCTRL2_PLULUT_RST_MASK) + +#define SYSCON_PRESETCTRL2_TIMER3_RST_MASK (0x200000U) +#define SYSCON_PRESETCTRL2_TIMER3_RST_SHIFT (21U) +/*! TIMER3_RST - Timer 3 reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL2_TIMER3_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_TIMER3_RST_SHIFT)) & SYSCON_PRESETCTRL2_TIMER3_RST_MASK) + +#define SYSCON_PRESETCTRL2_TIMER4_RST_MASK (0x400000U) +#define SYSCON_PRESETCTRL2_TIMER4_RST_SHIFT (22U) +/*! TIMER4_RST - Timer 4 reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL2_TIMER4_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_TIMER4_RST_SHIFT)) & SYSCON_PRESETCTRL2_TIMER4_RST_MASK) + +#define SYSCON_PRESETCTRL2_PUF_RST_MASK (0x800000U) +#define SYSCON_PRESETCTRL2_PUF_RST_SHIFT (23U) +/*! PUF_RST - PUF reset control reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL2_PUF_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_PUF_RST_SHIFT)) & SYSCON_PRESETCTRL2_PUF_RST_MASK) + +#define SYSCON_PRESETCTRL2_CASPER_RST_MASK (0x1000000U) +#define SYSCON_PRESETCTRL2_CASPER_RST_SHIFT (24U) +/*! CASPER_RST - Casper reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL2_CASPER_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_CASPER_RST_SHIFT)) & SYSCON_PRESETCTRL2_CASPER_RST_MASK) + +#define SYSCON_PRESETCTRL2_ANALOG_CTRL_RST_MASK (0x8000000U) +#define SYSCON_PRESETCTRL2_ANALOG_CTRL_RST_SHIFT (27U) +/*! ANALOG_CTRL_RST - analog control reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL2_ANALOG_CTRL_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_ANALOG_CTRL_RST_SHIFT)) & SYSCON_PRESETCTRL2_ANALOG_CTRL_RST_MASK) + +#define SYSCON_PRESETCTRL2_HS_LSPI_RST_MASK (0x10000000U) +#define SYSCON_PRESETCTRL2_HS_LSPI_RST_SHIFT (28U) +/*! HS_LSPI_RST - HS LSPI reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL2_HS_LSPI_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_HS_LSPI_RST_SHIFT)) & SYSCON_PRESETCTRL2_HS_LSPI_RST_MASK) + +#define SYSCON_PRESETCTRL2_GPIO_SEC_RST_MASK (0x20000000U) +#define SYSCON_PRESETCTRL2_GPIO_SEC_RST_SHIFT (29U) +/*! GPIO_SEC_RST - GPIO secure reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL2_GPIO_SEC_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_GPIO_SEC_RST_SHIFT)) & SYSCON_PRESETCTRL2_GPIO_SEC_RST_MASK) + +#define SYSCON_PRESETCTRL2_GPIO_SEC_INT_RST_MASK (0x40000000U) +#define SYSCON_PRESETCTRL2_GPIO_SEC_INT_RST_SHIFT (30U) +/*! GPIO_SEC_INT_RST - GPIO secure int reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL2_GPIO_SEC_INT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_GPIO_SEC_INT_RST_SHIFT)) & SYSCON_PRESETCTRL2_GPIO_SEC_INT_RST_MASK) +/*! @} */ + +/*! @name PRESETCTRLX - Peripheral reset control register */ +/*! @{ */ + +#define SYSCON_PRESETCTRLX_DATA_MASK (0xFFFFFFFFU) +#define SYSCON_PRESETCTRLX_DATA_SHIFT (0U) +/*! DATA - Data array value + */ +#define SYSCON_PRESETCTRLX_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLX_DATA_SHIFT)) & SYSCON_PRESETCTRLX_DATA_MASK) +/*! @} */ + +/* The count of SYSCON_PRESETCTRLX */ +#define SYSCON_PRESETCTRLX_COUNT (3U) + +/*! @name PRESETCTRLSET - Peripheral reset control set register */ +/*! @{ */ + +#define SYSCON_PRESETCTRLSET_DATA_MASK (0xFFFFFFFFU) +#define SYSCON_PRESETCTRLSET_DATA_SHIFT (0U) +/*! DATA - Data array value + */ +#define SYSCON_PRESETCTRLSET_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLSET_DATA_SHIFT)) & SYSCON_PRESETCTRLSET_DATA_MASK) +/*! @} */ + +/* The count of SYSCON_PRESETCTRLSET */ +#define SYSCON_PRESETCTRLSET_COUNT (3U) + +/*! @name PRESETCTRLCLR - Peripheral reset control clear register */ +/*! @{ */ + +#define SYSCON_PRESETCTRLCLR_DATA_MASK (0xFFFFFFFFU) +#define SYSCON_PRESETCTRLCLR_DATA_SHIFT (0U) +/*! DATA - Data array value + */ +#define SYSCON_PRESETCTRLCLR_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLCLR_DATA_SHIFT)) & SYSCON_PRESETCTRLCLR_DATA_MASK) +/*! @} */ + +/* The count of SYSCON_PRESETCTRLCLR */ +#define SYSCON_PRESETCTRLCLR_COUNT (3U) + +/*! @name SWR_RESET - generate a software_reset */ +/*! @{ */ + +#define SYSCON_SWR_RESET_SWR_RESET_MASK (0xFFFFFFFFU) +#define SYSCON_SWR_RESET_SWR_RESET_SHIFT (0U) +/*! SWR_RESET - Write 0x5A00_0001 to generate a software_reset. + * 0b01011010000000000000000000000001..Generate a software reset. + * 0b00000000000000000000000000000000..Bloc is not reset. + */ +#define SYSCON_SWR_RESET_SWR_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SWR_RESET_SWR_RESET_SHIFT)) & SYSCON_SWR_RESET_SWR_RESET_MASK) +/*! @} */ + +/*! @name AHBCLKCTRL0 - AHB Clock control 0 */ +/*! @{ */ + +#define SYSCON_AHBCLKCTRL0_ROM_MASK (0x2U) +#define SYSCON_AHBCLKCTRL0_ROM_SHIFT (1U) +/*! ROM - Enables the clock for the ROM. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL0_ROM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_ROM_SHIFT)) & SYSCON_AHBCLKCTRL0_ROM_MASK) + +#define SYSCON_AHBCLKCTRL0_SRAM_CTRL1_MASK (0x8U) +#define SYSCON_AHBCLKCTRL0_SRAM_CTRL1_SHIFT (3U) +/*! SRAM_CTRL1 - Enables the clock for the SRAM Controller 1. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL0_SRAM_CTRL1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_SRAM_CTRL1_SHIFT)) & SYSCON_AHBCLKCTRL0_SRAM_CTRL1_MASK) + +#define SYSCON_AHBCLKCTRL0_SRAM_CTRL2_MASK (0x10U) +#define SYSCON_AHBCLKCTRL0_SRAM_CTRL2_SHIFT (4U) +/*! SRAM_CTRL2 - Enables the clock for the SRAM Controller 2. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL0_SRAM_CTRL2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_SRAM_CTRL2_SHIFT)) & SYSCON_AHBCLKCTRL0_SRAM_CTRL2_MASK) + +#define SYSCON_AHBCLKCTRL0_FLASH_MASK (0x80U) +#define SYSCON_AHBCLKCTRL0_FLASH_SHIFT (7U) +/*! FLASH - Enables the clock for the Flash controller. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL0_FLASH(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_FLASH_SHIFT)) & SYSCON_AHBCLKCTRL0_FLASH_MASK) + +#define SYSCON_AHBCLKCTRL0_FMC_MASK (0x100U) +#define SYSCON_AHBCLKCTRL0_FMC_SHIFT (8U) +/*! FMC - Enables the clock for the FMC controller. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL0_FMC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_FMC_SHIFT)) & SYSCON_AHBCLKCTRL0_FMC_MASK) + +#define SYSCON_AHBCLKCTRL0_MUX_MASK (0x800U) +#define SYSCON_AHBCLKCTRL0_MUX_SHIFT (11U) +/*! MUX - Enables the clock for the Input Mux. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL0_MUX(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_MUX_SHIFT)) & SYSCON_AHBCLKCTRL0_MUX_MASK) + +#define SYSCON_AHBCLKCTRL0_IOCON_MASK (0x2000U) +#define SYSCON_AHBCLKCTRL0_IOCON_SHIFT (13U) +/*! IOCON - Enables the clock for the I/O controller. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL0_IOCON(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_IOCON_SHIFT)) & SYSCON_AHBCLKCTRL0_IOCON_MASK) + +#define SYSCON_AHBCLKCTRL0_GPIO0_MASK (0x4000U) +#define SYSCON_AHBCLKCTRL0_GPIO0_SHIFT (14U) +/*! GPIO0 - Enables the clock for the GPIO0. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL0_GPIO0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_GPIO0_SHIFT)) & SYSCON_AHBCLKCTRL0_GPIO0_MASK) + +#define SYSCON_AHBCLKCTRL0_GPIO1_MASK (0x8000U) +#define SYSCON_AHBCLKCTRL0_GPIO1_SHIFT (15U) +/*! GPIO1 - Enables the clock for the GPIO1. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL0_GPIO1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_GPIO1_SHIFT)) & SYSCON_AHBCLKCTRL0_GPIO1_MASK) + +#define SYSCON_AHBCLKCTRL0_PINT_MASK (0x40000U) +#define SYSCON_AHBCLKCTRL0_PINT_SHIFT (18U) +/*! PINT - Enables the clock for the Pin interrupt (PINT). + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL0_PINT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_PINT_SHIFT)) & SYSCON_AHBCLKCTRL0_PINT_MASK) + +#define SYSCON_AHBCLKCTRL0_GINT_MASK (0x80000U) +#define SYSCON_AHBCLKCTRL0_GINT_SHIFT (19U) +/*! GINT - Enables the clock for the Group interrupt (GINT). + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL0_GINT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_GINT_SHIFT)) & SYSCON_AHBCLKCTRL0_GINT_MASK) + +#define SYSCON_AHBCLKCTRL0_DMA0_MASK (0x100000U) +#define SYSCON_AHBCLKCTRL0_DMA0_SHIFT (20U) +/*! DMA0 - Enables the clock for the DMA0. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL0_DMA0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_DMA0_SHIFT)) & SYSCON_AHBCLKCTRL0_DMA0_MASK) + +#define SYSCON_AHBCLKCTRL0_CRCGEN_MASK (0x200000U) +#define SYSCON_AHBCLKCTRL0_CRCGEN_SHIFT (21U) +/*! CRCGEN - Enables the clock for the CRCGEN. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL0_CRCGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_CRCGEN_SHIFT)) & SYSCON_AHBCLKCTRL0_CRCGEN_MASK) + +#define SYSCON_AHBCLKCTRL0_WWDT_MASK (0x400000U) +#define SYSCON_AHBCLKCTRL0_WWDT_SHIFT (22U) +/*! WWDT - Enables the clock for the Watchdog Timer. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL0_WWDT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_WWDT_SHIFT)) & SYSCON_AHBCLKCTRL0_WWDT_MASK) + +#define SYSCON_AHBCLKCTRL0_RTC_MASK (0x800000U) +#define SYSCON_AHBCLKCTRL0_RTC_SHIFT (23U) +/*! RTC - Enables the clock for the Real Time Clock (RTC). + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL0_RTC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_RTC_SHIFT)) & SYSCON_AHBCLKCTRL0_RTC_MASK) + +#define SYSCON_AHBCLKCTRL0_MAILBOX_MASK (0x4000000U) +#define SYSCON_AHBCLKCTRL0_MAILBOX_SHIFT (26U) +/*! MAILBOX - Enables the clock for the Inter CPU communication Mailbox. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL0_MAILBOX(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_MAILBOX_SHIFT)) & SYSCON_AHBCLKCTRL0_MAILBOX_MASK) + +#define SYSCON_AHBCLKCTRL0_ADC_MASK (0x8000000U) +#define SYSCON_AHBCLKCTRL0_ADC_SHIFT (27U) +/*! ADC - Enables the clock for the ADC. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL0_ADC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_ADC_SHIFT)) & SYSCON_AHBCLKCTRL0_ADC_MASK) +/*! @} */ + +/*! @name AHBCLKCTRL1 - AHB Clock control 1 */ +/*! @{ */ + +#define SYSCON_AHBCLKCTRL1_MRT_MASK (0x1U) +#define SYSCON_AHBCLKCTRL1_MRT_SHIFT (0U) +/*! MRT - Enables the clock for the MRT. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL1_MRT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_MRT_SHIFT)) & SYSCON_AHBCLKCTRL1_MRT_MASK) + +#define SYSCON_AHBCLKCTRL1_OSTIMER_MASK (0x2U) +#define SYSCON_AHBCLKCTRL1_OSTIMER_SHIFT (1U) +/*! OSTIMER - Enables the clock for the OS Event Timer. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL1_OSTIMER(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_OSTIMER_SHIFT)) & SYSCON_AHBCLKCTRL1_OSTIMER_MASK) + +#define SYSCON_AHBCLKCTRL1_SCT_MASK (0x4U) +#define SYSCON_AHBCLKCTRL1_SCT_SHIFT (2U) +/*! SCT - Enables the clock for the SCT. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL1_SCT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_SCT_SHIFT)) & SYSCON_AHBCLKCTRL1_SCT_MASK) + +#define SYSCON_AHBCLKCTRL1_CAN_MASK (0x80U) +#define SYSCON_AHBCLKCTRL1_CAN_SHIFT (7U) +/*! CAN - Enables the clock for the CAN. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL1_CAN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_CAN_SHIFT)) & SYSCON_AHBCLKCTRL1_CAN_MASK) + +#define SYSCON_AHBCLKCTRL1_UTICK_MASK (0x400U) +#define SYSCON_AHBCLKCTRL1_UTICK_SHIFT (10U) +/*! UTICK - Enables the clock for the UTICK. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL1_UTICK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_UTICK_SHIFT)) & SYSCON_AHBCLKCTRL1_UTICK_MASK) + +#define SYSCON_AHBCLKCTRL1_FC0_MASK (0x800U) +#define SYSCON_AHBCLKCTRL1_FC0_SHIFT (11U) +/*! FC0 - Enables the clock for the FC0. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL1_FC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC0_SHIFT)) & SYSCON_AHBCLKCTRL1_FC0_MASK) + +#define SYSCON_AHBCLKCTRL1_FC1_MASK (0x1000U) +#define SYSCON_AHBCLKCTRL1_FC1_SHIFT (12U) +/*! FC1 - Enables the clock for the FC1. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL1_FC1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC1_SHIFT)) & SYSCON_AHBCLKCTRL1_FC1_MASK) + +#define SYSCON_AHBCLKCTRL1_FC2_MASK (0x2000U) +#define SYSCON_AHBCLKCTRL1_FC2_SHIFT (13U) +/*! FC2 - Enables the clock for the FC2. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL1_FC2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC2_SHIFT)) & SYSCON_AHBCLKCTRL1_FC2_MASK) + +#define SYSCON_AHBCLKCTRL1_FC3_MASK (0x4000U) +#define SYSCON_AHBCLKCTRL1_FC3_SHIFT (14U) +/*! FC3 - Enables the clock for the FC3. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL1_FC3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC3_SHIFT)) & SYSCON_AHBCLKCTRL1_FC3_MASK) + +#define SYSCON_AHBCLKCTRL1_FC4_MASK (0x8000U) +#define SYSCON_AHBCLKCTRL1_FC4_SHIFT (15U) +/*! FC4 - Enables the clock for the FC4. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL1_FC4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC4_SHIFT)) & SYSCON_AHBCLKCTRL1_FC4_MASK) + +#define SYSCON_AHBCLKCTRL1_FC5_MASK (0x10000U) +#define SYSCON_AHBCLKCTRL1_FC5_SHIFT (16U) +/*! FC5 - Enables the clock for the FC5. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL1_FC5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC5_SHIFT)) & SYSCON_AHBCLKCTRL1_FC5_MASK) + +#define SYSCON_AHBCLKCTRL1_FC6_MASK (0x20000U) +#define SYSCON_AHBCLKCTRL1_FC6_SHIFT (17U) +/*! FC6 - Enables the clock for the FC6. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL1_FC6(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC6_SHIFT)) & SYSCON_AHBCLKCTRL1_FC6_MASK) + +#define SYSCON_AHBCLKCTRL1_FC7_MASK (0x40000U) +#define SYSCON_AHBCLKCTRL1_FC7_SHIFT (18U) +/*! FC7 - Enables the clock for the FC7. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL1_FC7(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC7_SHIFT)) & SYSCON_AHBCLKCTRL1_FC7_MASK) + +#define SYSCON_AHBCLKCTRL1_TIMER2_MASK (0x400000U) +#define SYSCON_AHBCLKCTRL1_TIMER2_SHIFT (22U) +/*! TIMER2 - Enables the clock for the Timer 2. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL1_TIMER2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_TIMER2_SHIFT)) & SYSCON_AHBCLKCTRL1_TIMER2_MASK) + +#define SYSCON_AHBCLKCTRL1_USB0_DEV_MASK (0x2000000U) +#define SYSCON_AHBCLKCTRL1_USB0_DEV_SHIFT (25U) +/*! USB0_DEV - Enables the clock for the USB0-FS device. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL1_USB0_DEV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_USB0_DEV_SHIFT)) & SYSCON_AHBCLKCTRL1_USB0_DEV_MASK) + +#define SYSCON_AHBCLKCTRL1_TIMER0_MASK (0x4000000U) +#define SYSCON_AHBCLKCTRL1_TIMER0_SHIFT (26U) +/*! TIMER0 - Enables the clock for the Timer 0. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL1_TIMER0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_TIMER0_SHIFT)) & SYSCON_AHBCLKCTRL1_TIMER0_MASK) + +#define SYSCON_AHBCLKCTRL1_TIMER1_MASK (0x8000000U) +#define SYSCON_AHBCLKCTRL1_TIMER1_SHIFT (27U) +/*! TIMER1 - Enables the clock for the Timer 1. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL1_TIMER1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_TIMER1_SHIFT)) & SYSCON_AHBCLKCTRL1_TIMER1_MASK) +/*! @} */ + +/*! @name AHBCLKCTRL2 - AHB Clock control 2 */ +/*! @{ */ + +#define SYSCON_AHBCLKCTRL2_DMA1_MASK (0x2U) +#define SYSCON_AHBCLKCTRL2_DMA1_SHIFT (1U) +/*! DMA1 - Enables the clock for the DMA1. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_DMA1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_DMA1_SHIFT)) & SYSCON_AHBCLKCTRL2_DMA1_MASK) + +#define SYSCON_AHBCLKCTRL2_COMP_MASK (0x4U) +#define SYSCON_AHBCLKCTRL2_COMP_SHIFT (2U) +/*! COMP - Enables the clock for the Comparator. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_COMP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_COMP_SHIFT)) & SYSCON_AHBCLKCTRL2_COMP_MASK) + +#define SYSCON_AHBCLKCTRL2_USB1_HOST_MASK (0x10U) +#define SYSCON_AHBCLKCTRL2_USB1_HOST_SHIFT (4U) +/*! USB1_HOST - Enables the clock for the USB1-HS Host. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_USB1_HOST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_USB1_HOST_SHIFT)) & SYSCON_AHBCLKCTRL2_USB1_HOST_MASK) + +#define SYSCON_AHBCLKCTRL2_USB1_DEV_MASK (0x20U) +#define SYSCON_AHBCLKCTRL2_USB1_DEV_SHIFT (5U) +/*! USB1_DEV - Enables the clock for the USB1-HS device. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_USB1_DEV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_USB1_DEV_SHIFT)) & SYSCON_AHBCLKCTRL2_USB1_DEV_MASK) + +#define SYSCON_AHBCLKCTRL2_USB1_RAM_MASK (0x40U) +#define SYSCON_AHBCLKCTRL2_USB1_RAM_SHIFT (6U) +/*! USB1_RAM - Enables the clock for the USB1-HS RAM. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_USB1_RAM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_USB1_RAM_SHIFT)) & SYSCON_AHBCLKCTRL2_USB1_RAM_MASK) + +#define SYSCON_AHBCLKCTRL2_USB1_PHY_MASK (0x80U) +#define SYSCON_AHBCLKCTRL2_USB1_PHY_SHIFT (7U) +/*! USB1_PHY - Enables the clock for the USB1-HS PHY. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_USB1_PHY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_USB1_PHY_SHIFT)) & SYSCON_AHBCLKCTRL2_USB1_PHY_MASK) + +#define SYSCON_AHBCLKCTRL2_FREQME_MASK (0x100U) +#define SYSCON_AHBCLKCTRL2_FREQME_SHIFT (8U) +/*! FREQME - Enables the clock for the Frequency meter. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_FREQME(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_FREQME_SHIFT)) & SYSCON_AHBCLKCTRL2_FREQME_MASK) + +#define SYSCON_AHBCLKCTRL2_CDOG_MASK (0x800U) +#define SYSCON_AHBCLKCTRL2_CDOG_SHIFT (11U) +/*! CDOG - Enables the clock for the code watchdog. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_CDOG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_CDOG_SHIFT)) & SYSCON_AHBCLKCTRL2_CDOG_MASK) + +#define SYSCON_AHBCLKCTRL2_RNG_MASK (0x2000U) +#define SYSCON_AHBCLKCTRL2_RNG_SHIFT (13U) +/*! RNG - Enables the clock for the RNG. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_RNG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_RNG_SHIFT)) & SYSCON_AHBCLKCTRL2_RNG_MASK) + +#define SYSCON_AHBCLKCTRL2_SYSCTL_MASK (0x8000U) +#define SYSCON_AHBCLKCTRL2_SYSCTL_SHIFT (15U) +/*! SYSCTL - SYSCTL block clock. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_SYSCTL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_SYSCTL_SHIFT)) & SYSCON_AHBCLKCTRL2_SYSCTL_MASK) + +#define SYSCON_AHBCLKCTRL2_USB0_HOSTM_MASK (0x10000U) +#define SYSCON_AHBCLKCTRL2_USB0_HOSTM_SHIFT (16U) +/*! USB0_HOSTM - Enables the clock for the USB0-FS Host Master. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_USB0_HOSTM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_USB0_HOSTM_SHIFT)) & SYSCON_AHBCLKCTRL2_USB0_HOSTM_MASK) + +#define SYSCON_AHBCLKCTRL2_USB0_HOSTS_MASK (0x20000U) +#define SYSCON_AHBCLKCTRL2_USB0_HOSTS_SHIFT (17U) +/*! USB0_HOSTS - Enables the clock for the USB0-FS Host Slave. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_USB0_HOSTS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_USB0_HOSTS_SHIFT)) & SYSCON_AHBCLKCTRL2_USB0_HOSTS_MASK) + +#define SYSCON_AHBCLKCTRL2_HASH_AES_MASK (0x40000U) +#define SYSCON_AHBCLKCTRL2_HASH_AES_SHIFT (18U) +/*! HASH_AES - Enables the clock for the HASH_AES. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_HASH_AES(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_HASH_AES_SHIFT)) & SYSCON_AHBCLKCTRL2_HASH_AES_MASK) + +#define SYSCON_AHBCLKCTRL2_PLULUT_MASK (0x100000U) +#define SYSCON_AHBCLKCTRL2_PLULUT_SHIFT (20U) +/*! PLULUT - Enables the clock for the PLU LUT. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_PLULUT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_PLULUT_SHIFT)) & SYSCON_AHBCLKCTRL2_PLULUT_MASK) + +#define SYSCON_AHBCLKCTRL2_TIMER3_MASK (0x200000U) +#define SYSCON_AHBCLKCTRL2_TIMER3_SHIFT (21U) +/*! TIMER3 - Enables the clock for the Timer 3. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_TIMER3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_TIMER3_SHIFT)) & SYSCON_AHBCLKCTRL2_TIMER3_MASK) + +#define SYSCON_AHBCLKCTRL2_TIMER4_MASK (0x400000U) +#define SYSCON_AHBCLKCTRL2_TIMER4_SHIFT (22U) +/*! TIMER4 - Enables the clock for the Timer 4. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_TIMER4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_TIMER4_SHIFT)) & SYSCON_AHBCLKCTRL2_TIMER4_MASK) + +#define SYSCON_AHBCLKCTRL2_PUF_MASK (0x800000U) +#define SYSCON_AHBCLKCTRL2_PUF_SHIFT (23U) +/*! PUF - Enables the clock for the PUF reset control. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_PUF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_PUF_SHIFT)) & SYSCON_AHBCLKCTRL2_PUF_MASK) + +#define SYSCON_AHBCLKCTRL2_CASPER_MASK (0x1000000U) +#define SYSCON_AHBCLKCTRL2_CASPER_SHIFT (24U) +/*! CASPER - Enables the clock for the Casper. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_CASPER(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_CASPER_SHIFT)) & SYSCON_AHBCLKCTRL2_CASPER_MASK) + +#define SYSCON_AHBCLKCTRL2_ANALOG_CTRL_MASK (0x8000000U) +#define SYSCON_AHBCLKCTRL2_ANALOG_CTRL_SHIFT (27U) +/*! ANALOG_CTRL - Enables the clock for the analog control. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_ANALOG_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_ANALOG_CTRL_SHIFT)) & SYSCON_AHBCLKCTRL2_ANALOG_CTRL_MASK) + +#define SYSCON_AHBCLKCTRL2_HS_LSPI_MASK (0x10000000U) +#define SYSCON_AHBCLKCTRL2_HS_LSPI_SHIFT (28U) +/*! HS_LSPI - Enables the clock for the HS LSPI. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_HS_LSPI(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_HS_LSPI_SHIFT)) & SYSCON_AHBCLKCTRL2_HS_LSPI_MASK) + +#define SYSCON_AHBCLKCTRL2_GPIO_SEC_MASK (0x20000000U) +#define SYSCON_AHBCLKCTRL2_GPIO_SEC_SHIFT (29U) +/*! GPIO_SEC - Enables the clock for the GPIO secure. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_GPIO_SEC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_GPIO_SEC_SHIFT)) & SYSCON_AHBCLKCTRL2_GPIO_SEC_MASK) + +#define SYSCON_AHBCLKCTRL2_GPIO_SEC_INT_MASK (0x40000000U) +#define SYSCON_AHBCLKCTRL2_GPIO_SEC_INT_SHIFT (30U) +/*! GPIO_SEC_INT - Enables the clock for the GPIO secure int. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_GPIO_SEC_INT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_GPIO_SEC_INT_SHIFT)) & SYSCON_AHBCLKCTRL2_GPIO_SEC_INT_MASK) +/*! @} */ + +/*! @name AHBCLKCTRLX - Peripheral reset control register */ +/*! @{ */ + +#define SYSCON_AHBCLKCTRLX_DATA_MASK (0xFFFFFFFFU) +#define SYSCON_AHBCLKCTRLX_DATA_SHIFT (0U) +/*! DATA - Data array value + */ +#define SYSCON_AHBCLKCTRLX_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRLX_DATA_SHIFT)) & SYSCON_AHBCLKCTRLX_DATA_MASK) +/*! @} */ + +/* The count of SYSCON_AHBCLKCTRLX */ +#define SYSCON_AHBCLKCTRLX_COUNT (3U) + +/*! @name AHBCLKCTRLSET - Peripheral reset control register */ +/*! @{ */ + +#define SYSCON_AHBCLKCTRLSET_DATA_MASK (0xFFFFFFFFU) +#define SYSCON_AHBCLKCTRLSET_DATA_SHIFT (0U) +/*! DATA - Data array value + */ +#define SYSCON_AHBCLKCTRLSET_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRLSET_DATA_SHIFT)) & SYSCON_AHBCLKCTRLSET_DATA_MASK) +/*! @} */ + +/* The count of SYSCON_AHBCLKCTRLSET */ +#define SYSCON_AHBCLKCTRLSET_COUNT (3U) + +/*! @name AHBCLKCTRLCLR - Peripheral reset control register */ +/*! @{ */ + +#define SYSCON_AHBCLKCTRLCLR_DATA_MASK (0xFFFFFFFFU) +#define SYSCON_AHBCLKCTRLCLR_DATA_SHIFT (0U) +/*! DATA - Data array value + */ +#define SYSCON_AHBCLKCTRLCLR_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRLCLR_DATA_SHIFT)) & SYSCON_AHBCLKCTRLCLR_DATA_MASK) +/*! @} */ + +/* The count of SYSCON_AHBCLKCTRLCLR */ +#define SYSCON_AHBCLKCTRLCLR_COUNT (3U) + +/*! @name SYSTICKCLKSEL0 - System Tick Timer for CPU0 source select */ +/*! @{ */ + +#define SYSCON_SYSTICKCLKSEL0_SEL_MASK (0x7U) +#define SYSCON_SYSTICKCLKSEL0_SEL_SHIFT (0U) +/*! SEL - System Tick Timer for CPU0 source select. + * 0b000..System Tick 0 divided clock. + * 0b001..FRO 1MHz clock. + * 0b010..Oscillator 32 kHz clock. + * 0b011..No clock. + * 0b100..No clock. + * 0b101..No clock. + * 0b110..No clock. + * 0b111..No clock. + */ +#define SYSCON_SYSTICKCLKSEL0_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKSEL0_SEL_SHIFT)) & SYSCON_SYSTICKCLKSEL0_SEL_MASK) +/*! @} */ + +/*! @name SYSTICKCLKSELX - Peripheral reset control register */ +/*! @{ */ + +#define SYSCON_SYSTICKCLKSELX_DATA_MASK (0xFFFFFFFFU) +#define SYSCON_SYSTICKCLKSELX_DATA_SHIFT (0U) +/*! DATA - Data array value + */ +#define SYSCON_SYSTICKCLKSELX_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKSELX_DATA_SHIFT)) & SYSCON_SYSTICKCLKSELX_DATA_MASK) +/*! @} */ + +/* The count of SYSCON_SYSTICKCLKSELX */ +#define SYSCON_SYSTICKCLKSELX_COUNT (1U) + +/*! @name TRACECLKSEL - Trace clock source select */ +/*! @{ */ + +#define SYSCON_TRACECLKSEL_SEL_MASK (0x7U) +#define SYSCON_TRACECLKSEL_SEL_SHIFT (0U) +/*! SEL - Trace clock source select. + * 0b000..Trace divided clock. + * 0b001..FRO 1MHz clock. + * 0b010..Oscillator 32 kHz clock. + * 0b011..No clock. + * 0b100..No clock. + * 0b101..No clock. + * 0b110..No clock. + * 0b111..No clock. + */ +#define SYSCON_TRACECLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKSEL_SEL_SHIFT)) & SYSCON_TRACECLKSEL_SEL_MASK) +/*! @} */ + +/*! @name CTIMERCLKSEL0 - CTimer 0 clock source select */ +/*! @{ */ + +#define SYSCON_CTIMERCLKSEL0_SEL_MASK (0x7U) +#define SYSCON_CTIMERCLKSEL0_SEL_SHIFT (0U) +/*! SEL - CTimer 0 clock source select. + * 0b000..Main clock. + * 0b001..PLL0 clock. + * 0b010..No clock. + * 0b011..FRO 96 MHz clock. + * 0b100..FRO 1MHz clock. + * 0b101..MCLK clock. + * 0b110..Oscillator 32kHz clock. + * 0b111..No clock. + */ +#define SYSCON_CTIMERCLKSEL0_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERCLKSEL0_SEL_SHIFT)) & SYSCON_CTIMERCLKSEL0_SEL_MASK) +/*! @} */ + +/*! @name CTIMERCLKSEL1 - CTimer 1 clock source select */ +/*! @{ */ + +#define SYSCON_CTIMERCLKSEL1_SEL_MASK (0x7U) +#define SYSCON_CTIMERCLKSEL1_SEL_SHIFT (0U) +/*! SEL - CTimer 1 clock source select. + * 0b000..Main clock. + * 0b001..PLL0 clock. + * 0b010..No clock. + * 0b011..FRO 96 MHz clock. + * 0b100..FRO 1MHz clock. + * 0b101..MCLK clock. + * 0b110..Oscillator 32kHz clock. + * 0b111..No clock. + */ +#define SYSCON_CTIMERCLKSEL1_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERCLKSEL1_SEL_SHIFT)) & SYSCON_CTIMERCLKSEL1_SEL_MASK) +/*! @} */ + +/*! @name CTIMERCLKSEL2 - CTimer 2 clock source select */ +/*! @{ */ + +#define SYSCON_CTIMERCLKSEL2_SEL_MASK (0x7U) +#define SYSCON_CTIMERCLKSEL2_SEL_SHIFT (0U) +/*! SEL - CTimer 2 clock source select. + * 0b000..Main clock. + * 0b001..PLL0 clock. + * 0b010..No clock. + * 0b011..FRO 96 MHz clock. + * 0b100..FRO 1MHz clock. + * 0b101..MCLK clock. + * 0b110..Oscillator 32kHz clock. + * 0b111..No clock. + */ +#define SYSCON_CTIMERCLKSEL2_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERCLKSEL2_SEL_SHIFT)) & SYSCON_CTIMERCLKSEL2_SEL_MASK) +/*! @} */ + +/*! @name CTIMERCLKSEL3 - CTimer 3 clock source select */ +/*! @{ */ + +#define SYSCON_CTIMERCLKSEL3_SEL_MASK (0x7U) +#define SYSCON_CTIMERCLKSEL3_SEL_SHIFT (0U) +/*! SEL - CTimer 3 clock source select. + * 0b000..Main clock. + * 0b001..PLL0 clock. + * 0b010..No clock. + * 0b011..FRO 96 MHz clock. + * 0b100..FRO 1MHz clock. + * 0b101..MCLK clock. + * 0b110..Oscillator 32kHz clock. + * 0b111..No clock. + */ +#define SYSCON_CTIMERCLKSEL3_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERCLKSEL3_SEL_SHIFT)) & SYSCON_CTIMERCLKSEL3_SEL_MASK) +/*! @} */ + +/*! @name CTIMERCLKSEL4 - CTimer 4 clock source select */ +/*! @{ */ + +#define SYSCON_CTIMERCLKSEL4_SEL_MASK (0x7U) +#define SYSCON_CTIMERCLKSEL4_SEL_SHIFT (0U) +/*! SEL - CTimer 4 clock source select. + * 0b000..Main clock. + * 0b001..PLL0 clock. + * 0b010..No clock. + * 0b011..FRO 96 MHz clock. + * 0b100..FRO 1MHz clock. + * 0b101..MCLK clock. + * 0b110..Oscillator 32kHz clock. + * 0b111..No clock. + */ +#define SYSCON_CTIMERCLKSEL4_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERCLKSEL4_SEL_SHIFT)) & SYSCON_CTIMERCLKSEL4_SEL_MASK) +/*! @} */ + +/*! @name CTIMERCLKSELX - Peripheral reset control register */ +/*! @{ */ + +#define SYSCON_CTIMERCLKSELX_DATA_MASK (0xFFFFFFFFU) +#define SYSCON_CTIMERCLKSELX_DATA_SHIFT (0U) +/*! DATA - Data array value + */ +#define SYSCON_CTIMERCLKSELX_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERCLKSELX_DATA_SHIFT)) & SYSCON_CTIMERCLKSELX_DATA_MASK) +/*! @} */ + +/* The count of SYSCON_CTIMERCLKSELX */ +#define SYSCON_CTIMERCLKSELX_COUNT (5U) + +/*! @name MAINCLKSELA - Main clock A source select */ +/*! @{ */ + +#define SYSCON_MAINCLKSELA_SEL_MASK (0x7U) +#define SYSCON_MAINCLKSELA_SEL_SHIFT (0U) +/*! SEL - Main clock A source select. + * 0b000..FRO 12 MHz clock. + * 0b001..CLKIN clock. + * 0b010..FRO 1MHz clock. + * 0b011..FRO 96 MHz clock. + * 0b100..Reserved. + * 0b101..Reserved. + * 0b110..Reserved. + * 0b111..Reserved. + */ +#define SYSCON_MAINCLKSELA_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MAINCLKSELA_SEL_SHIFT)) & SYSCON_MAINCLKSELA_SEL_MASK) +/*! @} */ + +/*! @name MAINCLKSELB - Main clock source select */ +/*! @{ */ + +#define SYSCON_MAINCLKSELB_SEL_MASK (0x7U) +#define SYSCON_MAINCLKSELB_SEL_SHIFT (0U) +/*! SEL - Main clock source select. + * 0b000..Main Clock A. + * 0b001..PLL0 clock. + * 0b010..PLL1 clock. + * 0b011..Oscillator 32 kHz clock. + * 0b100..Reserved. + * 0b101..Reserved. + * 0b110..Reserved. + * 0b111..Reserved. + */ +#define SYSCON_MAINCLKSELB_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MAINCLKSELB_SEL_SHIFT)) & SYSCON_MAINCLKSELB_SEL_MASK) +/*! @} */ + +/*! @name CLKOUTSEL - CLKOUT clock source select */ +/*! @{ */ + +#define SYSCON_CLKOUTSEL_SEL_MASK (0xFU) +#define SYSCON_CLKOUTSEL_SEL_SHIFT (0U) +/*! SEL - CLKOUT clock source select. + * 0b0000..Main clock. + * 0b0001..PLL0 clock. + * 0b0010..CLKIN clock. + * 0b0011..FRO 96 MHz clock. + * 0b0100..FRO 1MHz clock. + * 0b0101..PLL1 clock. + * 0b0110..Oscillator 32kHz clock. + * 0b0111..No clock. + * 0b1000..Reserved. + * 0b1001..Reserved. + * 0b1010..Reserved. + * 0b1011..Reserved. + * 0b1100..No clock. + * 0b1101..No clock. + * 0b1110..No clock. + * 0b1111..No clock. + */ +#define SYSCON_CLKOUTSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTSEL_SEL_SHIFT)) & SYSCON_CLKOUTSEL_SEL_MASK) +/*! @} */ + +/*! @name PLL0CLKSEL - PLL0 clock source select */ +/*! @{ */ + +#define SYSCON_PLL0CLKSEL_SEL_MASK (0x7U) +#define SYSCON_PLL0CLKSEL_SEL_SHIFT (0U) +/*! SEL - PLL0 clock source select. + * 0b000..FRO 12 MHz clock. + * 0b001..CLKIN clock. + * 0b010..FRO 1MHz clock. + * 0b011..Oscillator 32kHz clock. + * 0b100..No clock. + * 0b101..No clock. + * 0b110..No clock. + * 0b111..No clock. + */ +#define SYSCON_PLL0CLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CLKSEL_SEL_SHIFT)) & SYSCON_PLL0CLKSEL_SEL_MASK) +/*! @} */ + +/*! @name PLL1CLKSEL - PLL1 clock source select */ +/*! @{ */ + +#define SYSCON_PLL1CLKSEL_SEL_MASK (0x7U) +#define SYSCON_PLL1CLKSEL_SEL_SHIFT (0U) +/*! SEL - PLL1 clock source select. + * 0b000..FRO 12 MHz clock. + * 0b001..CLKIN clock. + * 0b010..FRO 1MHz clock. + * 0b011..Oscillator 32kHz clock. + * 0b100..No clock. + * 0b101..No clock. + * 0b110..No clock. + * 0b111..No clock. + */ +#define SYSCON_PLL1CLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CLKSEL_SEL_SHIFT)) & SYSCON_PLL1CLKSEL_SEL_MASK) +/*! @} */ + +/*! @name CANCLKSEL - CAN clock source select */ +/*! @{ */ + +#define SYSCON_CANCLKSEL_SEL_MASK (0x7U) +#define SYSCON_CANCLKSEL_SEL_SHIFT (0U) +/*! SEL - CAN clock source select. + * 0b000..CAN divided clock. + * 0b001..FRO 1MHz clock. + * 0b010..Oscillator 32 kHz clock. + * 0b011..No clock. + * 0b100..No clock. + * 0b101..No clock. + * 0b110..No clock. + * 0b111..No clock. + */ +#define SYSCON_CANCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CANCLKSEL_SEL_SHIFT)) & SYSCON_CANCLKSEL_SEL_MASK) +/*! @} */ + +/*! @name ADCCLKSEL - ADC clock source select */ +/*! @{ */ + +#define SYSCON_ADCCLKSEL_SEL_MASK (0x7U) +#define SYSCON_ADCCLKSEL_SEL_SHIFT (0U) +/*! SEL - ADC clock source select. + * 0b000..Main clock. + * 0b001..PLL0 clock. + * 0b010..FRO 96 MHz clock. + * 0b011..Reserved. + * 0b100..Xtal clock coming directly. + * 0b101..No clock. + * 0b110..No clock. + * 0b111..No clock. + */ +#define SYSCON_ADCCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKSEL_SEL_SHIFT)) & SYSCON_ADCCLKSEL_SEL_MASK) +/*! @} */ + +/*! @name USB0CLKSEL - FS USB clock source select */ +/*! @{ */ + +#define SYSCON_USB0CLKSEL_SEL_MASK (0x7U) +#define SYSCON_USB0CLKSEL_SEL_SHIFT (0U) +/*! SEL - FS USB clock source select. + * 0b000..Main clock. + * 0b001..PLL0 clock. + * 0b010..No clock. + * 0b011..FRO 96 MHz clock. + * 0b100..No clock. + * 0b101..PLL1 clock. + * 0b110..No clock. + * 0b111..No clock. + */ +#define SYSCON_USB0CLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKSEL_SEL_SHIFT)) & SYSCON_USB0CLKSEL_SEL_MASK) +/*! @} */ + +/*! @name CLK32KCLKSEL - clock low speed source select for HS USB. */ +/*! @{ */ + +#define SYSCON_CLK32KCLKSEL_SEL_MASK (0x8U) +#define SYSCON_CLK32KCLKSEL_SEL_SHIFT (3U) +/*! SEL - clock low speed source select for HS USB. + * 0b0..Oscillator 32 kHz clock. + * 0b1..FRO1MHz_divided clock. + */ +#define SYSCON_CLK32KCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLK32KCLKSEL_SEL_SHIFT)) & SYSCON_CLK32KCLKSEL_SEL_MASK) +/*! @} */ + +/*! @name FCCLKSEL0 - Flexcomm Interface 0 clock source select for Fractional Rate Divider */ +/*! @{ */ + +#define SYSCON_FCCLKSEL0_SEL_MASK (0x7U) +#define SYSCON_FCCLKSEL0_SEL_SHIFT (0U) +/*! SEL - Flexcomm Interface 0 clock source select for Fractional Rate Divider. + * 0b000..Main clock. + * 0b001..system PLL divided clock. + * 0b010..FRO 12 MHz clock. + * 0b011..FRO 96 MHz clock. + * 0b100..FRO 1MHz clock. + * 0b101..MCLK clock. + * 0b110..Oscillator 32 kHz clock. + * 0b111..No clock. + */ +#define SYSCON_FCCLKSEL0_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL0_SEL_SHIFT)) & SYSCON_FCCLKSEL0_SEL_MASK) +/*! @} */ + +/*! @name FCCLKSEL1 - Flexcomm Interface 1 clock source select for Fractional Rate Divider */ +/*! @{ */ + +#define SYSCON_FCCLKSEL1_SEL_MASK (0x7U) +#define SYSCON_FCCLKSEL1_SEL_SHIFT (0U) +/*! SEL - Flexcomm Interface 1 clock source select for Fractional Rate Divider. + * 0b000..Main clock. + * 0b001..system PLL divided clock. + * 0b010..FRO 12 MHz clock. + * 0b011..FRO 96 MHz clock. + * 0b100..FRO 1MHz clock. + * 0b101..MCLK clock. + * 0b110..Oscillator 32 kHz clock. + * 0b111..No clock. + */ +#define SYSCON_FCCLKSEL1_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL1_SEL_SHIFT)) & SYSCON_FCCLKSEL1_SEL_MASK) +/*! @} */ + +/*! @name FCCLKSEL2 - Flexcomm Interface 2 clock source select for Fractional Rate Divider */ +/*! @{ */ + +#define SYSCON_FCCLKSEL2_SEL_MASK (0x7U) +#define SYSCON_FCCLKSEL2_SEL_SHIFT (0U) +/*! SEL - Flexcomm Interface 2 clock source select for Fractional Rate Divider. + * 0b000..Main clock. + * 0b001..system PLL divided clock. + * 0b010..FRO 12 MHz clock. + * 0b011..FRO 96 MHz clock. + * 0b100..FRO 1MHz clock. + * 0b101..MCLK clock. + * 0b110..Oscillator 32 kHz clock. + * 0b111..No clock. + */ +#define SYSCON_FCCLKSEL2_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL2_SEL_SHIFT)) & SYSCON_FCCLKSEL2_SEL_MASK) +/*! @} */ + +/*! @name FCCLKSEL3 - Flexcomm Interface 3 clock source select for Fractional Rate Divider */ +/*! @{ */ + +#define SYSCON_FCCLKSEL3_SEL_MASK (0x7U) +#define SYSCON_FCCLKSEL3_SEL_SHIFT (0U) +/*! SEL - Flexcomm Interface 3 clock source select for Fractional Rate Divider. + * 0b000..Main clock. + * 0b001..system PLL divided clock. + * 0b010..FRO 12 MHz clock. + * 0b011..FRO 96 MHz clock. + * 0b100..FRO 1MHz clock. + * 0b101..MCLK clock. + * 0b110..Oscillator 32 kHz clock. + * 0b111..No clock. + */ +#define SYSCON_FCCLKSEL3_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL3_SEL_SHIFT)) & SYSCON_FCCLKSEL3_SEL_MASK) +/*! @} */ + +/*! @name FCCLKSEL4 - Flexcomm Interface 4 clock source select for Fractional Rate Divider */ +/*! @{ */ + +#define SYSCON_FCCLKSEL4_SEL_MASK (0x7U) +#define SYSCON_FCCLKSEL4_SEL_SHIFT (0U) +/*! SEL - Flexcomm Interface 4 clock source select for Fractional Rate Divider. + * 0b000..Main clock. + * 0b001..system PLL divided clock. + * 0b010..FRO 12 MHz clock. + * 0b011..FRO 96 MHz clock. + * 0b100..FRO 1MHz clock. + * 0b101..MCLK clock. + * 0b110..Oscillator 32 kHz clock. + * 0b111..No clock. + */ +#define SYSCON_FCCLKSEL4_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL4_SEL_SHIFT)) & SYSCON_FCCLKSEL4_SEL_MASK) +/*! @} */ + +/*! @name FCCLKSEL5 - Flexcomm Interface 5 clock source select for Fractional Rate Divider */ +/*! @{ */ + +#define SYSCON_FCCLKSEL5_SEL_MASK (0x7U) +#define SYSCON_FCCLKSEL5_SEL_SHIFT (0U) +/*! SEL - Flexcomm Interface 5 clock source select for Fractional Rate Divider. + * 0b000..Main clock. + * 0b001..system PLL divided clock. + * 0b010..FRO 12 MHz clock. + * 0b011..FRO 96 MHz clock. + * 0b100..FRO 1MHz clock. + * 0b101..MCLK clock. + * 0b110..Oscillator 32 kHz clock. + * 0b111..No clock. + */ +#define SYSCON_FCCLKSEL5_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL5_SEL_SHIFT)) & SYSCON_FCCLKSEL5_SEL_MASK) +/*! @} */ + +/*! @name FCCLKSEL6 - Flexcomm Interface 6 clock source select for Fractional Rate Divider */ +/*! @{ */ + +#define SYSCON_FCCLKSEL6_SEL_MASK (0x7U) +#define SYSCON_FCCLKSEL6_SEL_SHIFT (0U) +/*! SEL - Flexcomm Interface 6 clock source select for Fractional Rate Divider. + * 0b000..Main clock. + * 0b001..system PLL divided clock. + * 0b010..FRO 12 MHz clock. + * 0b011..FRO 96 MHz clock. + * 0b100..FRO 1MHz clock. + * 0b101..MCLK clock. + * 0b110..Oscillator 32 kHz clock. + * 0b111..No clock. + */ +#define SYSCON_FCCLKSEL6_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL6_SEL_SHIFT)) & SYSCON_FCCLKSEL6_SEL_MASK) +/*! @} */ + +/*! @name FCCLKSEL7 - Flexcomm Interface 7 clock source select for Fractional Rate Divider */ +/*! @{ */ + +#define SYSCON_FCCLKSEL7_SEL_MASK (0x7U) +#define SYSCON_FCCLKSEL7_SEL_SHIFT (0U) +/*! SEL - Flexcomm Interface 7 clock source select for Fractional Rate Divider. + * 0b000..Main clock. + * 0b001..system PLL divided clock. + * 0b010..FRO 12 MHz clock. + * 0b011..FRO 96 MHz clock. + * 0b100..FRO 1MHz clock. + * 0b101..MCLK clock. + * 0b110..Oscillator 32 kHz clock. + * 0b111..No clock. + */ +#define SYSCON_FCCLKSEL7_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL7_SEL_SHIFT)) & SYSCON_FCCLKSEL7_SEL_MASK) +/*! @} */ + +/*! @name FCCLKSELX - Peripheral reset control register */ +/*! @{ */ + +#define SYSCON_FCCLKSELX_DATA_MASK (0xFFFFFFFFU) +#define SYSCON_FCCLKSELX_DATA_SHIFT (0U) +/*! DATA - Data array value + */ +#define SYSCON_FCCLKSELX_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSELX_DATA_SHIFT)) & SYSCON_FCCLKSELX_DATA_MASK) +/*! @} */ + +/* The count of SYSCON_FCCLKSELX */ +#define SYSCON_FCCLKSELX_COUNT (8U) + +/*! @name HSLSPICLKSEL - HS LSPI clock source select */ +/*! @{ */ + +#define SYSCON_HSLSPICLKSEL_SEL_MASK (0x7U) +#define SYSCON_HSLSPICLKSEL_SEL_SHIFT (0U) +/*! SEL - HS LSPI clock source select. + * 0b000..Main clock. + * 0b001..system PLL divided clock. + * 0b010..FRO 12 MHz clock. + * 0b011..FRO 96 MHz clock. + * 0b100..FRO 1MHz clock. + * 0b101..No clock. + * 0b110..Oscillator 32 kHz clock. + * 0b111..No clock. + */ +#define SYSCON_HSLSPICLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HSLSPICLKSEL_SEL_SHIFT)) & SYSCON_HSLSPICLKSEL_SEL_MASK) +/*! @} */ + +/*! @name MCLKCLKSEL - MCLK clock source select */ +/*! @{ */ + +#define SYSCON_MCLKCLKSEL_SEL_MASK (0x7U) +#define SYSCON_MCLKCLKSEL_SEL_SHIFT (0U) +/*! SEL - MCLK clock source select. + * 0b000..FRO 96 MHz clock. + * 0b001..PLL0 clock. + * 0b010..Reserved. + * 0b011..Reserved. + * 0b100..No clock. + * 0b101..No clock. + * 0b110..No clock. + * 0b111..No clock. + */ +#define SYSCON_MCLKCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKCLKSEL_SEL_SHIFT)) & SYSCON_MCLKCLKSEL_SEL_MASK) +/*! @} */ + +/*! @name SCTCLKSEL - SCTimer/PWM clock source select */ +/*! @{ */ + +#define SYSCON_SCTCLKSEL_SEL_MASK (0x7U) +#define SYSCON_SCTCLKSEL_SEL_SHIFT (0U) +/*! SEL - SCTimer/PWM clock source select. + * 0b000..Main clock. + * 0b001..PLL0 clock. + * 0b010..CLKIN clock. + * 0b011..FRO 96 MHz clock. + * 0b100..No clock. + * 0b101..MCLK clock. + * 0b110..No clock. + * 0b111..No clock. + */ +#define SYSCON_SCTCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKSEL_SEL_SHIFT)) & SYSCON_SCTCLKSEL_SEL_MASK) +/*! @} */ + +/*! @name SYSTICKCLKDIV0 - System Tick Timer divider for CPU0 */ +/*! @{ */ + +#define SYSCON_SYSTICKCLKDIV0_DIV_MASK (0xFFU) +#define SYSCON_SYSTICKCLKDIV0_DIV_SHIFT (0U) +/*! DIV - Clock divider value. + */ +#define SYSCON_SYSTICKCLKDIV0_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV0_DIV_SHIFT)) & SYSCON_SYSTICKCLKDIV0_DIV_MASK) + +#define SYSCON_SYSTICKCLKDIV0_RESET_MASK (0x20000000U) +#define SYSCON_SYSTICKCLKDIV0_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter. + * 0b1..Divider is reset. + * 0b0..Divider is not reset. + */ +#define SYSCON_SYSTICKCLKDIV0_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV0_RESET_SHIFT)) & SYSCON_SYSTICKCLKDIV0_RESET_MASK) + +#define SYSCON_SYSTICKCLKDIV0_HALT_MASK (0x40000000U) +#define SYSCON_SYSTICKCLKDIV0_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter. + * 0b1..Divider clock is stoped. + * 0b0..Divider clock is running. + */ +#define SYSCON_SYSTICKCLKDIV0_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV0_HALT_SHIFT)) & SYSCON_SYSTICKCLKDIV0_HALT_MASK) + +#define SYSCON_SYSTICKCLKDIV0_REQFLAG_MASK (0x80000000U) +#define SYSCON_SYSTICKCLKDIV0_REQFLAG_SHIFT (31U) +/*! REQFLAG - Divider status flag. + * 0b1..Clock frequency is not stable. + * 0b0..Divider clock is stable. + */ +#define SYSCON_SYSTICKCLKDIV0_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV0_REQFLAG_SHIFT)) & SYSCON_SYSTICKCLKDIV0_REQFLAG_MASK) +/*! @} */ + +/*! @name TRACECLKDIV - TRACE clock divider */ +/*! @{ */ + +#define SYSCON_TRACECLKDIV_DIV_MASK (0xFFU) +#define SYSCON_TRACECLKDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value. + */ +#define SYSCON_TRACECLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKDIV_DIV_SHIFT)) & SYSCON_TRACECLKDIV_DIV_MASK) + +#define SYSCON_TRACECLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_TRACECLKDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter. + * 0b1..Divider is reset. + * 0b0..Divider is not reset. + */ +#define SYSCON_TRACECLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKDIV_RESET_SHIFT)) & SYSCON_TRACECLKDIV_RESET_MASK) + +#define SYSCON_TRACECLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_TRACECLKDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter. + * 0b1..Divider clock is stoped. + * 0b0..Divider clock is running. + */ +#define SYSCON_TRACECLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKDIV_HALT_SHIFT)) & SYSCON_TRACECLKDIV_HALT_MASK) + +#define SYSCON_TRACECLKDIV_REQFLAG_MASK (0x80000000U) +#define SYSCON_TRACECLKDIV_REQFLAG_SHIFT (31U) +/*! REQFLAG - Divider status flag. + * 0b1..Clock frequency is not stable. + * 0b0..Divider clock is stable. + */ +#define SYSCON_TRACECLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKDIV_REQFLAG_SHIFT)) & SYSCON_TRACECLKDIV_REQFLAG_MASK) +/*! @} */ + +/*! @name CANCLKDIV - CAN clock divider */ +/*! @{ */ + +#define SYSCON_CANCLKDIV_DIV_MASK (0xFFU) +#define SYSCON_CANCLKDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value. + */ +#define SYSCON_CANCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CANCLKDIV_DIV_SHIFT)) & SYSCON_CANCLKDIV_DIV_MASK) + +#define SYSCON_CANCLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_CANCLKDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter. + * 0b1..Divider is reset. + * 0b0..Divider is not reset. + */ +#define SYSCON_CANCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CANCLKDIV_RESET_SHIFT)) & SYSCON_CANCLKDIV_RESET_MASK) + +#define SYSCON_CANCLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_CANCLKDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter. + * 0b1..Divider clock is stoped. + * 0b0..Divider clock is running. + */ +#define SYSCON_CANCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CANCLKDIV_HALT_SHIFT)) & SYSCON_CANCLKDIV_HALT_MASK) + +#define SYSCON_CANCLKDIV_REQFLAG_MASK (0x80000000U) +#define SYSCON_CANCLKDIV_REQFLAG_SHIFT (31U) +/*! REQFLAG - Divider status flag. + * 0b1..Clock frequency is not stable. + * 0b0..Divider clock is stable. + */ +#define SYSCON_CANCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CANCLKDIV_REQFLAG_SHIFT)) & SYSCON_CANCLKDIV_REQFLAG_MASK) +/*! @} */ + +/*! @name FLEXFRG0CTRL - Fractional rate divider for flexcomm 0 */ +/*! @{ */ + +#define SYSCON_FLEXFRG0CTRL_DIV_MASK (0xFFU) +#define SYSCON_FLEXFRG0CTRL_DIV_SHIFT (0U) +/*! DIV - Denominator of the fractional rate divider. + */ +#define SYSCON_FLEXFRG0CTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG0CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG0CTRL_DIV_MASK) + +#define SYSCON_FLEXFRG0CTRL_MULT_MASK (0xFF00U) +#define SYSCON_FLEXFRG0CTRL_MULT_SHIFT (8U) +/*! MULT - Numerator of the fractional rate divider. + */ +#define SYSCON_FLEXFRG0CTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG0CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG0CTRL_MULT_MASK) +/*! @} */ + +/*! @name FLEXFRG1CTRL - Fractional rate divider for flexcomm 1 */ +/*! @{ */ + +#define SYSCON_FLEXFRG1CTRL_DIV_MASK (0xFFU) +#define SYSCON_FLEXFRG1CTRL_DIV_SHIFT (0U) +/*! DIV - Denominator of the fractional rate divider. + */ +#define SYSCON_FLEXFRG1CTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG1CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG1CTRL_DIV_MASK) + +#define SYSCON_FLEXFRG1CTRL_MULT_MASK (0xFF00U) +#define SYSCON_FLEXFRG1CTRL_MULT_SHIFT (8U) +/*! MULT - Numerator of the fractional rate divider. + */ +#define SYSCON_FLEXFRG1CTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG1CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG1CTRL_MULT_MASK) +/*! @} */ + +/*! @name FLEXFRG2CTRL - Fractional rate divider for flexcomm 2 */ +/*! @{ */ + +#define SYSCON_FLEXFRG2CTRL_DIV_MASK (0xFFU) +#define SYSCON_FLEXFRG2CTRL_DIV_SHIFT (0U) +/*! DIV - Denominator of the fractional rate divider. + */ +#define SYSCON_FLEXFRG2CTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG2CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG2CTRL_DIV_MASK) + +#define SYSCON_FLEXFRG2CTRL_MULT_MASK (0xFF00U) +#define SYSCON_FLEXFRG2CTRL_MULT_SHIFT (8U) +/*! MULT - Numerator of the fractional rate divider. + */ +#define SYSCON_FLEXFRG2CTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG2CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG2CTRL_MULT_MASK) +/*! @} */ + +/*! @name FLEXFRG3CTRL - Fractional rate divider for flexcomm 3 */ +/*! @{ */ + +#define SYSCON_FLEXFRG3CTRL_DIV_MASK (0xFFU) +#define SYSCON_FLEXFRG3CTRL_DIV_SHIFT (0U) +/*! DIV - Denominator of the fractional rate divider. + */ +#define SYSCON_FLEXFRG3CTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG3CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG3CTRL_DIV_MASK) + +#define SYSCON_FLEXFRG3CTRL_MULT_MASK (0xFF00U) +#define SYSCON_FLEXFRG3CTRL_MULT_SHIFT (8U) +/*! MULT - Numerator of the fractional rate divider. + */ +#define SYSCON_FLEXFRG3CTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG3CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG3CTRL_MULT_MASK) +/*! @} */ + +/*! @name FLEXFRG4CTRL - Fractional rate divider for flexcomm 4 */ +/*! @{ */ + +#define SYSCON_FLEXFRG4CTRL_DIV_MASK (0xFFU) +#define SYSCON_FLEXFRG4CTRL_DIV_SHIFT (0U) +/*! DIV - Denominator of the fractional rate divider. + */ +#define SYSCON_FLEXFRG4CTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG4CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG4CTRL_DIV_MASK) + +#define SYSCON_FLEXFRG4CTRL_MULT_MASK (0xFF00U) +#define SYSCON_FLEXFRG4CTRL_MULT_SHIFT (8U) +/*! MULT - Numerator of the fractional rate divider. + */ +#define SYSCON_FLEXFRG4CTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG4CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG4CTRL_MULT_MASK) +/*! @} */ + +/*! @name FLEXFRG5CTRL - Fractional rate divider for flexcomm 5 */ +/*! @{ */ + +#define SYSCON_FLEXFRG5CTRL_DIV_MASK (0xFFU) +#define SYSCON_FLEXFRG5CTRL_DIV_SHIFT (0U) +/*! DIV - Denominator of the fractional rate divider. + */ +#define SYSCON_FLEXFRG5CTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG5CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG5CTRL_DIV_MASK) + +#define SYSCON_FLEXFRG5CTRL_MULT_MASK (0xFF00U) +#define SYSCON_FLEXFRG5CTRL_MULT_SHIFT (8U) +/*! MULT - Numerator of the fractional rate divider. + */ +#define SYSCON_FLEXFRG5CTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG5CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG5CTRL_MULT_MASK) +/*! @} */ + +/*! @name FLEXFRG6CTRL - Fractional rate divider for flexcomm 6 */ +/*! @{ */ + +#define SYSCON_FLEXFRG6CTRL_DIV_MASK (0xFFU) +#define SYSCON_FLEXFRG6CTRL_DIV_SHIFT (0U) +/*! DIV - Denominator of the fractional rate divider. + */ +#define SYSCON_FLEXFRG6CTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG6CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG6CTRL_DIV_MASK) + +#define SYSCON_FLEXFRG6CTRL_MULT_MASK (0xFF00U) +#define SYSCON_FLEXFRG6CTRL_MULT_SHIFT (8U) +/*! MULT - Numerator of the fractional rate divider. + */ +#define SYSCON_FLEXFRG6CTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG6CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG6CTRL_MULT_MASK) +/*! @} */ + +/*! @name FLEXFRG7CTRL - Fractional rate divider for flexcomm 7 */ +/*! @{ */ + +#define SYSCON_FLEXFRG7CTRL_DIV_MASK (0xFFU) +#define SYSCON_FLEXFRG7CTRL_DIV_SHIFT (0U) +/*! DIV - Denominator of the fractional rate divider. + */ +#define SYSCON_FLEXFRG7CTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG7CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG7CTRL_DIV_MASK) + +#define SYSCON_FLEXFRG7CTRL_MULT_MASK (0xFF00U) +#define SYSCON_FLEXFRG7CTRL_MULT_SHIFT (8U) +/*! MULT - Numerator of the fractional rate divider. + */ +#define SYSCON_FLEXFRG7CTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG7CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG7CTRL_MULT_MASK) +/*! @} */ + +/*! @name FLEXFRGXCTRL - Peripheral reset control register */ +/*! @{ */ + +#define SYSCON_FLEXFRGXCTRL_DATA_MASK (0xFFFFFFFFU) +#define SYSCON_FLEXFRGXCTRL_DATA_SHIFT (0U) +/*! DATA - Data array value + */ +#define SYSCON_FLEXFRGXCTRL_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRGXCTRL_DATA_SHIFT)) & SYSCON_FLEXFRGXCTRL_DATA_MASK) +/*! @} */ + +/* The count of SYSCON_FLEXFRGXCTRL */ +#define SYSCON_FLEXFRGXCTRL_COUNT (8U) + +/*! @name AHBCLKDIV - System clock divider */ +/*! @{ */ + +#define SYSCON_AHBCLKDIV_DIV_MASK (0xFFU) +#define SYSCON_AHBCLKDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value. + */ +#define SYSCON_AHBCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_DIV_SHIFT)) & SYSCON_AHBCLKDIV_DIV_MASK) + +#define SYSCON_AHBCLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_AHBCLKDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter. + * 0b1..Divider is reset. + * 0b0..Divider is not reset. + */ +#define SYSCON_AHBCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_RESET_SHIFT)) & SYSCON_AHBCLKDIV_RESET_MASK) + +#define SYSCON_AHBCLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_AHBCLKDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter. + * 0b1..Divider clock is stoped. + * 0b0..Divider clock is running. + */ +#define SYSCON_AHBCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_HALT_SHIFT)) & SYSCON_AHBCLKDIV_HALT_MASK) + +#define SYSCON_AHBCLKDIV_REQFLAG_MASK (0x80000000U) +#define SYSCON_AHBCLKDIV_REQFLAG_SHIFT (31U) +/*! REQFLAG - Divider status flag. + * 0b1..Clock frequency is not stable. + * 0b0..Divider clock is stable. + */ +#define SYSCON_AHBCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_REQFLAG_SHIFT)) & SYSCON_AHBCLKDIV_REQFLAG_MASK) +/*! @} */ + +/*! @name CLKOUTDIV - CLKOUT clock divider */ +/*! @{ */ + +#define SYSCON_CLKOUTDIV_DIV_MASK (0xFFU) +#define SYSCON_CLKOUTDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value. + */ +#define SYSCON_CLKOUTDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_DIV_SHIFT)) & SYSCON_CLKOUTDIV_DIV_MASK) + +#define SYSCON_CLKOUTDIV_RESET_MASK (0x20000000U) +#define SYSCON_CLKOUTDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter. + * 0b1..Divider is reset. + * 0b0..Divider is not reset. + */ +#define SYSCON_CLKOUTDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_RESET_SHIFT)) & SYSCON_CLKOUTDIV_RESET_MASK) + +#define SYSCON_CLKOUTDIV_HALT_MASK (0x40000000U) +#define SYSCON_CLKOUTDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter. + * 0b1..Divider clock is stoped. + * 0b0..Divider clock is running. + */ +#define SYSCON_CLKOUTDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_HALT_SHIFT)) & SYSCON_CLKOUTDIV_HALT_MASK) + +#define SYSCON_CLKOUTDIV_REQFLAG_MASK (0x80000000U) +#define SYSCON_CLKOUTDIV_REQFLAG_SHIFT (31U) +/*! REQFLAG - Divider status flag. + * 0b1..Clock frequency is not stable. + * 0b0..Divider clock is stable. + */ +#define SYSCON_CLKOUTDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_REQFLAG_SHIFT)) & SYSCON_CLKOUTDIV_REQFLAG_MASK) +/*! @} */ + +/*! @name FROHFDIV - FRO_HF (96MHz) clock divider */ +/*! @{ */ + +#define SYSCON_FROHFDIV_DIV_MASK (0xFFU) +#define SYSCON_FROHFDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value. + */ +#define SYSCON_FROHFDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFDIV_DIV_SHIFT)) & SYSCON_FROHFDIV_DIV_MASK) + +#define SYSCON_FROHFDIV_RESET_MASK (0x20000000U) +#define SYSCON_FROHFDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter. + * 0b1..Divider is reset. + * 0b0..Divider is not reset. + */ +#define SYSCON_FROHFDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFDIV_RESET_SHIFT)) & SYSCON_FROHFDIV_RESET_MASK) + +#define SYSCON_FROHFDIV_HALT_MASK (0x40000000U) +#define SYSCON_FROHFDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter. + * 0b1..Divider clock is stoped. + * 0b0..Divider clock is running. + */ +#define SYSCON_FROHFDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFDIV_HALT_SHIFT)) & SYSCON_FROHFDIV_HALT_MASK) + +#define SYSCON_FROHFDIV_REQFLAG_MASK (0x80000000U) +#define SYSCON_FROHFDIV_REQFLAG_SHIFT (31U) +/*! REQFLAG - Divider status flag. + * 0b1..Clock frequency is not stable. + * 0b0..Divider clock is stable. + */ +#define SYSCON_FROHFDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFDIV_REQFLAG_SHIFT)) & SYSCON_FROHFDIV_REQFLAG_MASK) +/*! @} */ + +/*! @name WDTCLKDIV - WDT clock divider */ +/*! @{ */ + +#define SYSCON_WDTCLKDIV_DIV_MASK (0x3FU) +#define SYSCON_WDTCLKDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value. + */ +#define SYSCON_WDTCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDTCLKDIV_DIV_SHIFT)) & SYSCON_WDTCLKDIV_DIV_MASK) + +#define SYSCON_WDTCLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_WDTCLKDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter. + * 0b1..Divider is reset. + * 0b0..Divider is not reset. + */ +#define SYSCON_WDTCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDTCLKDIV_RESET_SHIFT)) & SYSCON_WDTCLKDIV_RESET_MASK) + +#define SYSCON_WDTCLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_WDTCLKDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter. + * 0b1..Divider clock is stoped. + * 0b0..Divider clock is running. + */ +#define SYSCON_WDTCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDTCLKDIV_HALT_SHIFT)) & SYSCON_WDTCLKDIV_HALT_MASK) + +#define SYSCON_WDTCLKDIV_REQFLAG_MASK (0x80000000U) +#define SYSCON_WDTCLKDIV_REQFLAG_SHIFT (31U) +/*! REQFLAG - Divider status flag. + * 0b1..Clock frequency is not stable. + * 0b0..Divider clock is stable. + */ +#define SYSCON_WDTCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDTCLKDIV_REQFLAG_SHIFT)) & SYSCON_WDTCLKDIV_REQFLAG_MASK) +/*! @} */ + +/*! @name ADCCLKDIV - ADC clock divider */ +/*! @{ */ + +#define SYSCON_ADCCLKDIV_DIV_MASK (0x7U) +#define SYSCON_ADCCLKDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value. + */ +#define SYSCON_ADCCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_DIV_SHIFT)) & SYSCON_ADCCLKDIV_DIV_MASK) + +#define SYSCON_ADCCLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_ADCCLKDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter. + * 0b1..Divider is reset. + * 0b0..Divider is not reset. + */ +#define SYSCON_ADCCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_RESET_SHIFT)) & SYSCON_ADCCLKDIV_RESET_MASK) + +#define SYSCON_ADCCLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_ADCCLKDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter. + * 0b1..Divider clock is stoped. + * 0b0..Divider clock is running. + */ +#define SYSCON_ADCCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_HALT_SHIFT)) & SYSCON_ADCCLKDIV_HALT_MASK) + +#define SYSCON_ADCCLKDIV_REQFLAG_MASK (0x80000000U) +#define SYSCON_ADCCLKDIV_REQFLAG_SHIFT (31U) +/*! REQFLAG - Divider status flag. + * 0b1..Clock frequency is not stable. + * 0b0..Divider clock is stable. + */ +#define SYSCON_ADCCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_REQFLAG_SHIFT)) & SYSCON_ADCCLKDIV_REQFLAG_MASK) +/*! @} */ + +/*! @name USB0CLKDIV - USB0-FS Clock divider */ +/*! @{ */ + +#define SYSCON_USB0CLKDIV_DIV_MASK (0xFFU) +#define SYSCON_USB0CLKDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value. + */ +#define SYSCON_USB0CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKDIV_DIV_SHIFT)) & SYSCON_USB0CLKDIV_DIV_MASK) + +#define SYSCON_USB0CLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_USB0CLKDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter. + * 0b1..Divider is reset. + * 0b0..Divider is not reset. + */ +#define SYSCON_USB0CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKDIV_RESET_SHIFT)) & SYSCON_USB0CLKDIV_RESET_MASK) + +#define SYSCON_USB0CLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_USB0CLKDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter. + * 0b1..Divider clock is stoped. + * 0b0..Divider clock is running. + */ +#define SYSCON_USB0CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKDIV_HALT_SHIFT)) & SYSCON_USB0CLKDIV_HALT_MASK) + +#define SYSCON_USB0CLKDIV_REQFLAG_MASK (0x80000000U) +#define SYSCON_USB0CLKDIV_REQFLAG_SHIFT (31U) +/*! REQFLAG - Divider status flag. + * 0b1..Clock frequency is not stable. + * 0b0..Divider clock is stable. + */ +#define SYSCON_USB0CLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKDIV_REQFLAG_SHIFT)) & SYSCON_USB0CLKDIV_REQFLAG_MASK) +/*! @} */ + +/*! @name FRO1MCLKDIV - FRO1MHz Clock divider (FRO1M_divided) */ +/*! @{ */ + +#define SYSCON_FRO1MCLKDIV_DIV_MASK (0xFFU) +#define SYSCON_FRO1MCLKDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value. + */ +#define SYSCON_FRO1MCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FRO1MCLKDIV_DIV_SHIFT)) & SYSCON_FRO1MCLKDIV_DIV_MASK) + +#define SYSCON_FRO1MCLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_FRO1MCLKDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter. + * 0b1..Divider is reset. + * 0b0..Divider is not reset. + */ +#define SYSCON_FRO1MCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FRO1MCLKDIV_RESET_SHIFT)) & SYSCON_FRO1MCLKDIV_RESET_MASK) + +#define SYSCON_FRO1MCLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_FRO1MCLKDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter. + * 0b1..Divider clock is stoped. + * 0b0..Divider clock is running. + */ +#define SYSCON_FRO1MCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FRO1MCLKDIV_HALT_SHIFT)) & SYSCON_FRO1MCLKDIV_HALT_MASK) + +#define SYSCON_FRO1MCLKDIV_REQFLAG_MASK (0x80000000U) +#define SYSCON_FRO1MCLKDIV_REQFLAG_SHIFT (31U) +/*! REQFLAG - Divider status flag. + * 0b1..Clock frequency is not stable. + * 0b0..Divider clock is stable. + */ +#define SYSCON_FRO1MCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FRO1MCLKDIV_REQFLAG_SHIFT)) & SYSCON_FRO1MCLKDIV_REQFLAG_MASK) +/*! @} */ + +/*! @name MCLKDIV - I2S MCLK clock divider */ +/*! @{ */ + +#define SYSCON_MCLKDIV_DIV_MASK (0xFFU) +#define SYSCON_MCLKDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value. + */ +#define SYSCON_MCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_DIV_SHIFT)) & SYSCON_MCLKDIV_DIV_MASK) + +#define SYSCON_MCLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_MCLKDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter. + * 0b1..Divider is reset. + * 0b0..Divider is not reset. + */ +#define SYSCON_MCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_RESET_SHIFT)) & SYSCON_MCLKDIV_RESET_MASK) + +#define SYSCON_MCLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_MCLKDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter. + * 0b1..Divider clock is stoped. + * 0b0..Divider clock is running. + */ +#define SYSCON_MCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_HALT_SHIFT)) & SYSCON_MCLKDIV_HALT_MASK) + +#define SYSCON_MCLKDIV_REQFLAG_MASK (0x80000000U) +#define SYSCON_MCLKDIV_REQFLAG_SHIFT (31U) +/*! REQFLAG - Divider status flag. + * 0b1..Clock frequency is not stable. + * 0b0..Divider clock is stable. + */ +#define SYSCON_MCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_REQFLAG_SHIFT)) & SYSCON_MCLKDIV_REQFLAG_MASK) +/*! @} */ + +/*! @name SCTCLKDIV - SCT/PWM clock divider */ +/*! @{ */ + +#define SYSCON_SCTCLKDIV_DIV_MASK (0xFFU) +#define SYSCON_SCTCLKDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value. + */ +#define SYSCON_SCTCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKDIV_DIV_SHIFT)) & SYSCON_SCTCLKDIV_DIV_MASK) + +#define SYSCON_SCTCLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_SCTCLKDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter. + * 0b1..Divider is reset. + * 0b0..Divider is not reset. + */ +#define SYSCON_SCTCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKDIV_RESET_SHIFT)) & SYSCON_SCTCLKDIV_RESET_MASK) + +#define SYSCON_SCTCLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_SCTCLKDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter. + * 0b1..Divider clock is stoped. + * 0b0..Divider clock is running. + */ +#define SYSCON_SCTCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKDIV_HALT_SHIFT)) & SYSCON_SCTCLKDIV_HALT_MASK) + +#define SYSCON_SCTCLKDIV_REQFLAG_MASK (0x80000000U) +#define SYSCON_SCTCLKDIV_REQFLAG_SHIFT (31U) +/*! REQFLAG - Divider status flag. + * 0b1..Clock frequency is not stable. + * 0b0..Divider clock is stable. + */ +#define SYSCON_SCTCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKDIV_REQFLAG_SHIFT)) & SYSCON_SCTCLKDIV_REQFLAG_MASK) +/*! @} */ + +/*! @name PLL0CLKDIV - PLL0 clock divider */ +/*! @{ */ + +#define SYSCON_PLL0CLKDIV_DIV_MASK (0xFFU) +#define SYSCON_PLL0CLKDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value. + */ +#define SYSCON_PLL0CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CLKDIV_DIV_SHIFT)) & SYSCON_PLL0CLKDIV_DIV_MASK) + +#define SYSCON_PLL0CLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_PLL0CLKDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter. + * 0b1..Divider is reset. + * 0b0..Divider is not reset. + */ +#define SYSCON_PLL0CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CLKDIV_RESET_SHIFT)) & SYSCON_PLL0CLKDIV_RESET_MASK) + +#define SYSCON_PLL0CLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_PLL0CLKDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter. + * 0b1..Divider clock is stoped. + * 0b0..Divider clock is running. + */ +#define SYSCON_PLL0CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CLKDIV_HALT_SHIFT)) & SYSCON_PLL0CLKDIV_HALT_MASK) + +#define SYSCON_PLL0CLKDIV_REQFLAG_MASK (0x80000000U) +#define SYSCON_PLL0CLKDIV_REQFLAG_SHIFT (31U) +/*! REQFLAG - Divider status flag. + * 0b1..Clock frequency is not stable. + * 0b0..Divider clock is stable. + */ +#define SYSCON_PLL0CLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CLKDIV_REQFLAG_SHIFT)) & SYSCON_PLL0CLKDIV_REQFLAG_MASK) +/*! @} */ + +/*! @name CLOCKGENUPDATELOCKOUT - Control clock configuration registers access (like xxxDIV, xxxSEL) */ +/*! @{ */ + +#define SYSCON_CLOCKGENUPDATELOCKOUT_CLOCKGENUPDATELOCKOUT_MASK (0xFFFFFFFFU) +#define SYSCON_CLOCKGENUPDATELOCKOUT_CLOCKGENUPDATELOCKOUT_SHIFT (0U) +/*! CLOCKGENUPDATELOCKOUT - Control clock configuration registers access (for example, xxxDIV, xxxSEL). + * 0b00000000000000000000000000000001..update all clock configuration. + * 0b00000000000000000000000000000000..all hardware clock configruration are freeze. + */ +#define SYSCON_CLOCKGENUPDATELOCKOUT_CLOCKGENUPDATELOCKOUT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCKGENUPDATELOCKOUT_CLOCKGENUPDATELOCKOUT_SHIFT)) & SYSCON_CLOCKGENUPDATELOCKOUT_CLOCKGENUPDATELOCKOUT_MASK) +/*! @} */ + +/*! @name FMCCR - FMC configuration register */ +/*! @{ */ + +#define SYSCON_FMCCR_FETCHCFG_MASK (0x3U) +#define SYSCON_FMCCR_FETCHCFG_SHIFT (0U) +/*! FETCHCFG - Instruction fetch configuration. + * 0b00..Instruction fetches from flash are not buffered. + * 0b01..One buffer is used for all instruction fetches. + * 0b10..All buffers may be used for instruction fetches. + */ +#define SYSCON_FMCCR_FETCHCFG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_FETCHCFG_SHIFT)) & SYSCON_FMCCR_FETCHCFG_MASK) + +#define SYSCON_FMCCR_DATACFG_MASK (0xCU) +#define SYSCON_FMCCR_DATACFG_SHIFT (2U) +/*! DATACFG - Data read configuration. + * 0b00..Data accesses from flash are not buffered. + * 0b01..One buffer is used for all data accesses. + * 0b10..All buffers can be used for data accesses. + */ +#define SYSCON_FMCCR_DATACFG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_DATACFG_SHIFT)) & SYSCON_FMCCR_DATACFG_MASK) + +#define SYSCON_FMCCR_ACCEL_MASK (0x10U) +#define SYSCON_FMCCR_ACCEL_SHIFT (4U) +/*! ACCEL - Acceleration enable. + * 0b0..Flash acceleration is disabled. + * 0b1..Flash acceleration is enabled. + */ +#define SYSCON_FMCCR_ACCEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_ACCEL_SHIFT)) & SYSCON_FMCCR_ACCEL_MASK) + +#define SYSCON_FMCCR_PREFEN_MASK (0x20U) +#define SYSCON_FMCCR_PREFEN_SHIFT (5U) +/*! PREFEN - Prefetch enable. + * 0b0..No instruction prefetch is performed. + * 0b1..Instruction prefetch is enabled. + */ +#define SYSCON_FMCCR_PREFEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_PREFEN_SHIFT)) & SYSCON_FMCCR_PREFEN_MASK) + +#define SYSCON_FMCCR_PREFOVR_MASK (0x40U) +#define SYSCON_FMCCR_PREFOVR_SHIFT (6U) +/*! PREFOVR - Prefetch override. + * 0b0..Any previously initiated prefetch will be completed. + * 0b1..Any previously initiated prefetch will be aborted, and the next flash line following the current + * execution address will be prefetched if not already buffered. + */ +#define SYSCON_FMCCR_PREFOVR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_PREFOVR_SHIFT)) & SYSCON_FMCCR_PREFOVR_MASK) + +#define SYSCON_FMCCR_FLASHTIM_MASK (0xF000U) +#define SYSCON_FMCCR_FLASHTIM_SHIFT (12U) +/*! FLASHTIM - Flash memory access time. + * 0b0000..1 system clock flash access time (for system clock rates up to 11 MHz). + * 0b0001..2 system clocks flash access time (for system clock rates up to 22 MHz). + * 0b0010..3 system clocks flash access time (for system clock rates up to 33 MHz). + * 0b0011..4 system clocks flash access time (for system clock rates up to 44 MHz). + * 0b0100..5 system clocks flash access time (for system clock rates up to 55 MHz). + * 0b0101..6 system clocks flash access time (for system clock rates up to 66 MHz). + * 0b0110..7 system clocks flash access time (for system clock rates up to 84 MHz). + * 0b0111..8 system clocks flash access time (for system clock rates up to 104 MHz). + * 0b1000..9 system clocks flash access time (for system clock rates up to 119 MHz). + * 0b1001..10 system clocks flash access time (for system clock rates up to 129 MHz). + * 0b1010..11 system clocks flash access time (for system clock rates up to 144 MHz). + * 0b1011..12 system clocks flash access time (for system clock rates up to 150 MHz). + */ +#define SYSCON_FMCCR_FLASHTIM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_FLASHTIM_SHIFT)) & SYSCON_FMCCR_FLASHTIM_MASK) +/*! @} */ + +/*! @name USB0NEEDCLKCTRL - USB0-FS need clock control */ +/*! @{ */ + +#define SYSCON_USB0NEEDCLKCTRL_AP_FS_DEV_NEEDCLK_MASK (0x1U) +#define SYSCON_USB0NEEDCLKCTRL_AP_FS_DEV_NEEDCLK_SHIFT (0U) +/*! AP_FS_DEV_NEEDCLK - USB0-FS Device USB0_NEEDCLK signal control:. + * 0b0..Under hardware control. + * 0b1..Forced high. + */ +#define SYSCON_USB0NEEDCLKCTRL_AP_FS_DEV_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0NEEDCLKCTRL_AP_FS_DEV_NEEDCLK_SHIFT)) & SYSCON_USB0NEEDCLKCTRL_AP_FS_DEV_NEEDCLK_MASK) + +#define SYSCON_USB0NEEDCLKCTRL_POL_FS_DEV_NEEDCLK_MASK (0x2U) +#define SYSCON_USB0NEEDCLKCTRL_POL_FS_DEV_NEEDCLK_SHIFT (1U) +/*! POL_FS_DEV_NEEDCLK - USB0-FS Device USB0_NEEDCLK polarity for triggering the USB0-FS wake-up interrupt:. + * 0b0..Falling edge of device USB0_NEEDCLK triggers wake-up. + * 0b1..Rising edge of device USB0_NEEDCLK triggers wake-up. + */ +#define SYSCON_USB0NEEDCLKCTRL_POL_FS_DEV_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0NEEDCLKCTRL_POL_FS_DEV_NEEDCLK_SHIFT)) & SYSCON_USB0NEEDCLKCTRL_POL_FS_DEV_NEEDCLK_MASK) + +#define SYSCON_USB0NEEDCLKCTRL_AP_FS_HOST_NEEDCLK_MASK (0x4U) +#define SYSCON_USB0NEEDCLKCTRL_AP_FS_HOST_NEEDCLK_SHIFT (2U) +/*! AP_FS_HOST_NEEDCLK - USB0-FS Host USB0_NEEDCLK signal control:. + * 0b0..Under hardware control. + * 0b1..Forced high. + */ +#define SYSCON_USB0NEEDCLKCTRL_AP_FS_HOST_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0NEEDCLKCTRL_AP_FS_HOST_NEEDCLK_SHIFT)) & SYSCON_USB0NEEDCLKCTRL_AP_FS_HOST_NEEDCLK_MASK) + +#define SYSCON_USB0NEEDCLKCTRL_POL_FS_HOST_NEEDCLK_MASK (0x8U) +#define SYSCON_USB0NEEDCLKCTRL_POL_FS_HOST_NEEDCLK_SHIFT (3U) +/*! POL_FS_HOST_NEEDCLK - USB0-FS Host USB0_NEEDCLK polarity for triggering the USB0-FS wake-up interrupt:. + * 0b0..Falling edge of device USB0_NEEDCLK triggers wake-up. + * 0b1..Rising edge of device USB0_NEEDCLK triggers wake-up. + */ +#define SYSCON_USB0NEEDCLKCTRL_POL_FS_HOST_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0NEEDCLKCTRL_POL_FS_HOST_NEEDCLK_SHIFT)) & SYSCON_USB0NEEDCLKCTRL_POL_FS_HOST_NEEDCLK_MASK) +/*! @} */ + +/*! @name USB0NEEDCLKSTAT - USB0-FS need clock status */ +/*! @{ */ + +#define SYSCON_USB0NEEDCLKSTAT_DEV_NEEDCLK_MASK (0x1U) +#define SYSCON_USB0NEEDCLKSTAT_DEV_NEEDCLK_SHIFT (0U) +/*! DEV_NEEDCLK - USB0-FS Device USB0_NEEDCLK signal status:. + * 0b1..USB0-FS Device clock is high. + * 0b0..USB0-FS Device clock is low. + */ +#define SYSCON_USB0NEEDCLKSTAT_DEV_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0NEEDCLKSTAT_DEV_NEEDCLK_SHIFT)) & SYSCON_USB0NEEDCLKSTAT_DEV_NEEDCLK_MASK) + +#define SYSCON_USB0NEEDCLKSTAT_HOST_NEEDCLK_MASK (0x2U) +#define SYSCON_USB0NEEDCLKSTAT_HOST_NEEDCLK_SHIFT (1U) +/*! HOST_NEEDCLK - USB0-FS Host USB0_NEEDCLK signal status:. + * 0b1..USB0-FS Host clock is high. + * 0b0..USB0-FS Host clock is low. + */ +#define SYSCON_USB0NEEDCLKSTAT_HOST_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0NEEDCLKSTAT_HOST_NEEDCLK_SHIFT)) & SYSCON_USB0NEEDCLKSTAT_HOST_NEEDCLK_MASK) +/*! @} */ + +/*! @name FMCFLUSH - FMCflush control */ +/*! @{ */ + +#define SYSCON_FMCFLUSH_FLUSH_MASK (0x1U) +#define SYSCON_FMCFLUSH_FLUSH_SHIFT (0U) +/*! FLUSH - Flush control + * 0b1..Flush the FMC buffer contents. + * 0b0..No action is performed. + */ +#define SYSCON_FMCFLUSH_FLUSH(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCFLUSH_FLUSH_SHIFT)) & SYSCON_FMCFLUSH_FLUSH_MASK) +/*! @} */ + +/*! @name MCLKIO - MCLK control */ +/*! @{ */ + +#define SYSCON_MCLKIO_MCLKIO_MASK (0x1U) +#define SYSCON_MCLKIO_MCLKIO_SHIFT (0U) +/*! MCLKIO - MCLK control. + * 0b0..input mode. + * 0b1..output mode. + */ +#define SYSCON_MCLKIO_MCLKIO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKIO_MCLKIO_SHIFT)) & SYSCON_MCLKIO_MCLKIO_MASK) +/*! @} */ + +/*! @name USB1NEEDCLKCTRL - USB1-HS need clock control */ +/*! @{ */ + +#define SYSCON_USB1NEEDCLKCTRL_AP_HS_DEV_NEEDCLK_MASK (0x1U) +#define SYSCON_USB1NEEDCLKCTRL_AP_HS_DEV_NEEDCLK_SHIFT (0U) +/*! AP_HS_DEV_NEEDCLK - USB1-HS Device need_clock signal control: + * 0b0..HOST_NEEDCLK is under hardware control. + * 0b1..HOST_NEEDCLK is forced high. + */ +#define SYSCON_USB1NEEDCLKCTRL_AP_HS_DEV_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1NEEDCLKCTRL_AP_HS_DEV_NEEDCLK_SHIFT)) & SYSCON_USB1NEEDCLKCTRL_AP_HS_DEV_NEEDCLK_MASK) + +#define SYSCON_USB1NEEDCLKCTRL_POL_HS_DEV_NEEDCLK_MASK (0x2U) +#define SYSCON_USB1NEEDCLKCTRL_POL_HS_DEV_NEEDCLK_SHIFT (1U) +/*! POL_HS_DEV_NEEDCLK - USB1-HS device need clock polarity for triggering the USB1_NEEDCLK wake-up interrupt: + * 0b0..Falling edge of DEV_NEEDCLK triggers wake-up. + * 0b1..Rising edge of DEV_NEEDCLK triggers wake-up. + */ +#define SYSCON_USB1NEEDCLKCTRL_POL_HS_DEV_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1NEEDCLKCTRL_POL_HS_DEV_NEEDCLK_SHIFT)) & SYSCON_USB1NEEDCLKCTRL_POL_HS_DEV_NEEDCLK_MASK) + +#define SYSCON_USB1NEEDCLKCTRL_AP_HS_HOST_NEEDCLK_MASK (0x4U) +#define SYSCON_USB1NEEDCLKCTRL_AP_HS_HOST_NEEDCLK_SHIFT (2U) +/*! AP_HS_HOST_NEEDCLK - USB1-HS Host need clock signal control: + * 0b0..HOST_NEEDCLK is under hardware control. + * 0b1..HOST_NEEDCLK is forced high. + */ +#define SYSCON_USB1NEEDCLKCTRL_AP_HS_HOST_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1NEEDCLKCTRL_AP_HS_HOST_NEEDCLK_SHIFT)) & SYSCON_USB1NEEDCLKCTRL_AP_HS_HOST_NEEDCLK_MASK) + +#define SYSCON_USB1NEEDCLKCTRL_POL_HS_HOST_NEEDCLK_MASK (0x8U) +#define SYSCON_USB1NEEDCLKCTRL_POL_HS_HOST_NEEDCLK_SHIFT (3U) +/*! POL_HS_HOST_NEEDCLK - USB1-HS host need clock polarity for triggering the USB1_NEEDCLK wake-up interrupt. + * 0b0..Falling edge of HOST_NEEDCLK triggers wake-up. + * 0b1..Rising edge of HOST_NEEDCLK triggers wake-up. + */ +#define SYSCON_USB1NEEDCLKCTRL_POL_HS_HOST_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1NEEDCLKCTRL_POL_HS_HOST_NEEDCLK_SHIFT)) & SYSCON_USB1NEEDCLKCTRL_POL_HS_HOST_NEEDCLK_MASK) + +#define SYSCON_USB1NEEDCLKCTRL_HS_DEV_WAKEUP_N_MASK (0x10U) +#define SYSCON_USB1NEEDCLKCTRL_HS_DEV_WAKEUP_N_SHIFT (4U) +/*! HS_DEV_WAKEUP_N - Software override of device controller PHY wake up logic. + * 0b0..Forces USB1_PHY to wake-up. + * 0b1..Normal USB1_PHY behavior. + */ +#define SYSCON_USB1NEEDCLKCTRL_HS_DEV_WAKEUP_N(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1NEEDCLKCTRL_HS_DEV_WAKEUP_N_SHIFT)) & SYSCON_USB1NEEDCLKCTRL_HS_DEV_WAKEUP_N_MASK) +/*! @} */ + +/*! @name USB1NEEDCLKSTAT - USB1-HS need clock status */ +/*! @{ */ + +#define SYSCON_USB1NEEDCLKSTAT_DEV_NEEDCLK_MASK (0x1U) +#define SYSCON_USB1NEEDCLKSTAT_DEV_NEEDCLK_SHIFT (0U) +/*! DEV_NEEDCLK - USB1-HS Device need_clock signal status:. + * 0b1..DEV_NEEDCLK is high. + * 0b0..DEV_NEEDCLK is low. + */ +#define SYSCON_USB1NEEDCLKSTAT_DEV_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1NEEDCLKSTAT_DEV_NEEDCLK_SHIFT)) & SYSCON_USB1NEEDCLKSTAT_DEV_NEEDCLK_MASK) + +#define SYSCON_USB1NEEDCLKSTAT_HOST_NEEDCLK_MASK (0x2U) +#define SYSCON_USB1NEEDCLKSTAT_HOST_NEEDCLK_SHIFT (1U) +/*! HOST_NEEDCLK - USB1-HS Host need_clock signal status:. + * 0b1..HOST_NEEDCLK is high. + * 0b0..HOST_NEEDCLK is low. + */ +#define SYSCON_USB1NEEDCLKSTAT_HOST_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1NEEDCLKSTAT_HOST_NEEDCLK_SHIFT)) & SYSCON_USB1NEEDCLKSTAT_HOST_NEEDCLK_MASK) +/*! @} */ + +/*! @name FLASHREMAP_SIZE - This 32-bit register contains the size of the image to remap, in bytes. The 12 LSBs are ignored, so the size granularity is 4KB. */ +/*! @{ */ + +#define SYSCON_FLASHREMAP_SIZE_FLASHREMAP_SIZE_MASK (0xFFFFFFFFU) +#define SYSCON_FLASHREMAP_SIZE_FLASHREMAP_SIZE_SHIFT (0U) +#define SYSCON_FLASHREMAP_SIZE_FLASHREMAP_SIZE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASHREMAP_SIZE_FLASHREMAP_SIZE_SHIFT)) & SYSCON_FLASHREMAP_SIZE_FLASHREMAP_SIZE_MASK) +/*! @} */ + +/*! @name FLASHREMAP_SIZE_DP - This 32-bit register is a duplicate of FLASHREMAPSIZE for increased security. */ +/*! @{ */ + +#define SYSCON_FLASHREMAP_SIZE_DP_FLASHREMAP_SIZE_MASK (0xFFFFFFFFU) +#define SYSCON_FLASHREMAP_SIZE_DP_FLASHREMAP_SIZE_SHIFT (0U) +#define SYSCON_FLASHREMAP_SIZE_DP_FLASHREMAP_SIZE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASHREMAP_SIZE_DP_FLASHREMAP_SIZE_SHIFT)) & SYSCON_FLASHREMAP_SIZE_DP_FLASHREMAP_SIZE_MASK) +/*! @} */ + +/*! @name FLASHREMAP_OFFSET - This 32-bit register contains the offset by which the image is to be remapped. The 12 LSBs are ignored, so the remap granularity is 4KB. */ +/*! @{ */ + +#define SYSCON_FLASHREMAP_OFFSET_FLASHREMAP_OFFSET_MASK (0xFFFFFFFFU) +#define SYSCON_FLASHREMAP_OFFSET_FLASHREMAP_OFFSET_SHIFT (0U) +#define SYSCON_FLASHREMAP_OFFSET_FLASHREMAP_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASHREMAP_OFFSET_FLASHREMAP_OFFSET_SHIFT)) & SYSCON_FLASHREMAP_OFFSET_FLASHREMAP_OFFSET_MASK) +/*! @} */ + +/*! @name FLASHREMAP_OFFSET_DP - This 32-bit register is a duplicate of FLASHREMAPOFFSET for increased security. */ +/*! @{ */ + +#define SYSCON_FLASHREMAP_OFFSET_DP_FLASHREMAP_OFFSET_MASK (0xFFFFFFFFU) +#define SYSCON_FLASHREMAP_OFFSET_DP_FLASHREMAP_OFFSET_SHIFT (0U) +#define SYSCON_FLASHREMAP_OFFSET_DP_FLASHREMAP_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASHREMAP_OFFSET_DP_FLASHREMAP_OFFSET_SHIFT)) & SYSCON_FLASHREMAP_OFFSET_DP_FLASHREMAP_OFFSET_MASK) +/*! @} */ + +/*! @name FLASHREMAP_LOCK - Control write access to FLASHREMAP_SIZE and FLASHREMAP_OFFSET registers. */ +/*! @{ */ + +#define SYSCON_FLASHREMAP_LOCK_LOCK_MASK (0xFFFFFFFFU) +#define SYSCON_FLASHREMAP_LOCK_LOCK_SHIFT (0U) +/*! LOCK - Control write access to FLASHREMAP_SIZE and FLASHREMAP_OFFSET registers. Any value other + * than 0xC33CA55A and 0x3CC35AA5 does not modify the state. + * 0b00111100110000110101101010100101..Write access to 4 registers FLASHREMAP_SIZE* and FLASHREMAP_OFFSET* is unlocked. + * 0b11000011001111001010010101011010..Write access to 4 registers FLASHREMAP_SIZE* and FLASHREMAP_OFFSET* is locked. + */ +#define SYSCON_FLASHREMAP_LOCK_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASHREMAP_LOCK_LOCK_SHIFT)) & SYSCON_FLASHREMAP_LOCK_LOCK_MASK) +/*! @} */ + +/*! @name CASPER_CTRL - Control CASPER integration. */ +/*! @{ */ + +#define SYSCON_CASPER_CTRL_INTERLEAVE_MASK (0x1U) +#define SYSCON_CASPER_CTRL_INTERLEAVE_SHIFT (0U) +/*! INTERLEAVE - Control RAM access for RAMX0 and RAMX1. + * 0b1..RAM access to RAMX0 and RAMX1 is interleaved. + * 0b0..RAM access to RAMX0 and RAMX1 is consecutive. + */ +#define SYSCON_CASPER_CTRL_INTERLEAVE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CASPER_CTRL_INTERLEAVE_SHIFT)) & SYSCON_CASPER_CTRL_INTERLEAVE_MASK) +/*! @} */ + +/*! @name PLL1CTRL - PLL1 550m control */ +/*! @{ */ + +#define SYSCON_PLL1CTRL_SELR_MASK (0xFU) +#define SYSCON_PLL1CTRL_SELR_SHIFT (0U) +/*! SELR - Bandwidth select R value. + */ +#define SYSCON_PLL1CTRL_SELR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_SELR_SHIFT)) & SYSCON_PLL1CTRL_SELR_MASK) + +#define SYSCON_PLL1CTRL_SELI_MASK (0x3F0U) +#define SYSCON_PLL1CTRL_SELI_SHIFT (4U) +/*! SELI - Bandwidth select I value. + */ +#define SYSCON_PLL1CTRL_SELI(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_SELI_SHIFT)) & SYSCON_PLL1CTRL_SELI_MASK) + +#define SYSCON_PLL1CTRL_SELP_MASK (0x7C00U) +#define SYSCON_PLL1CTRL_SELP_SHIFT (10U) +/*! SELP - Bandwidth select P value. + */ +#define SYSCON_PLL1CTRL_SELP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_SELP_SHIFT)) & SYSCON_PLL1CTRL_SELP_MASK) + +#define SYSCON_PLL1CTRL_BYPASSPLL_MASK (0x8000U) +#define SYSCON_PLL1CTRL_BYPASSPLL_SHIFT (15U) +/*! BYPASSPLL - Bypass PLL input clock is sent directly to the PLL output (default). + * 0b1..PLL input clock is sent directly to the PLL output. + * 0b0..use PLL. + */ +#define SYSCON_PLL1CTRL_BYPASSPLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_BYPASSPLL_SHIFT)) & SYSCON_PLL1CTRL_BYPASSPLL_MASK) + +#define SYSCON_PLL1CTRL_BYPASSPOSTDIV2_MASK (0x10000U) +#define SYSCON_PLL1CTRL_BYPASSPOSTDIV2_SHIFT (16U) +/*! BYPASSPOSTDIV2 - bypass of the divide-by-2 divider in the post-divider. + * 0b1..bypass of the divide-by-2 divider in the post-divider. + * 0b0..use the divide-by-2 divider in the post-divider. + */ +#define SYSCON_PLL1CTRL_BYPASSPOSTDIV2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_BYPASSPOSTDIV2_SHIFT)) & SYSCON_PLL1CTRL_BYPASSPOSTDIV2_MASK) + +#define SYSCON_PLL1CTRL_LIMUPOFF_MASK (0x20000U) +#define SYSCON_PLL1CTRL_LIMUPOFF_SHIFT (17U) +/*! LIMUPOFF - limup_off = 1 in spread spectrum and fractional PLL applications. + */ +#define SYSCON_PLL1CTRL_LIMUPOFF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_LIMUPOFF_SHIFT)) & SYSCON_PLL1CTRL_LIMUPOFF_MASK) + +#define SYSCON_PLL1CTRL_BWDIRECT_MASK (0x40000U) +#define SYSCON_PLL1CTRL_BWDIRECT_SHIFT (18U) +/*! BWDIRECT - control of the bandwidth of the PLL. + * 0b1..modify the bandwidth of the PLL directly. + * 0b0..the bandwidth is changed synchronously with the feedback-divider. + */ +#define SYSCON_PLL1CTRL_BWDIRECT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_BWDIRECT_SHIFT)) & SYSCON_PLL1CTRL_BWDIRECT_MASK) + +#define SYSCON_PLL1CTRL_BYPASSPREDIV_MASK (0x80000U) +#define SYSCON_PLL1CTRL_BYPASSPREDIV_SHIFT (19U) +/*! BYPASSPREDIV - bypass of the pre-divider. + * 0b1..bypass of the pre-divider. + * 0b0..use the pre-divider. + */ +#define SYSCON_PLL1CTRL_BYPASSPREDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_BYPASSPREDIV_SHIFT)) & SYSCON_PLL1CTRL_BYPASSPREDIV_MASK) + +#define SYSCON_PLL1CTRL_BYPASSPOSTDIV_MASK (0x100000U) +#define SYSCON_PLL1CTRL_BYPASSPOSTDIV_SHIFT (20U) +/*! BYPASSPOSTDIV - bypass of the post-divider. + * 0b1..bypass of the post-divider. + * 0b0..use the post-divider. + */ +#define SYSCON_PLL1CTRL_BYPASSPOSTDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_BYPASSPOSTDIV_SHIFT)) & SYSCON_PLL1CTRL_BYPASSPOSTDIV_MASK) + +#define SYSCON_PLL1CTRL_CLKEN_MASK (0x200000U) +#define SYSCON_PLL1CTRL_CLKEN_SHIFT (21U) +/*! CLKEN - enable the output clock. + * 0b1..Enable the output clock. + * 0b0..Disable the output clock. + */ +#define SYSCON_PLL1CTRL_CLKEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_CLKEN_SHIFT)) & SYSCON_PLL1CTRL_CLKEN_MASK) + +#define SYSCON_PLL1CTRL_FRMEN_MASK (0x400000U) +#define SYSCON_PLL1CTRL_FRMEN_SHIFT (22U) +/*! FRMEN - 1: free running mode. + */ +#define SYSCON_PLL1CTRL_FRMEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_FRMEN_SHIFT)) & SYSCON_PLL1CTRL_FRMEN_MASK) + +#define SYSCON_PLL1CTRL_FRMCLKSTABLE_MASK (0x800000U) +#define SYSCON_PLL1CTRL_FRMCLKSTABLE_SHIFT (23U) +/*! FRMCLKSTABLE - free running mode clockstable: Warning: Only make frm_clockstable = 1 after the PLL output frequency is stable. + */ +#define SYSCON_PLL1CTRL_FRMCLKSTABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_FRMCLKSTABLE_SHIFT)) & SYSCON_PLL1CTRL_FRMCLKSTABLE_MASK) + +#define SYSCON_PLL1CTRL_SKEWEN_MASK (0x1000000U) +#define SYSCON_PLL1CTRL_SKEWEN_SHIFT (24U) +/*! SKEWEN - Skew mode. + * 0b1..skewmode is enable. + * 0b0..skewmode is disable. + */ +#define SYSCON_PLL1CTRL_SKEWEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_SKEWEN_SHIFT)) & SYSCON_PLL1CTRL_SKEWEN_MASK) +/*! @} */ + +/*! @name PLL1STAT - PLL1 550m status */ +/*! @{ */ + +#define SYSCON_PLL1STAT_LOCK_MASK (0x1U) +#define SYSCON_PLL1STAT_LOCK_SHIFT (0U) +/*! LOCK - lock detector output (active high) Warning: The lock signal is only reliable between fref[2] :100 kHz to 20 MHz. + */ +#define SYSCON_PLL1STAT_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1STAT_LOCK_SHIFT)) & SYSCON_PLL1STAT_LOCK_MASK) + +#define SYSCON_PLL1STAT_PREDIVACK_MASK (0x2U) +#define SYSCON_PLL1STAT_PREDIVACK_SHIFT (1U) +/*! PREDIVACK - pre-divider ratio change acknowledge. + */ +#define SYSCON_PLL1STAT_PREDIVACK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1STAT_PREDIVACK_SHIFT)) & SYSCON_PLL1STAT_PREDIVACK_MASK) + +#define SYSCON_PLL1STAT_FEEDDIVACK_MASK (0x4U) +#define SYSCON_PLL1STAT_FEEDDIVACK_SHIFT (2U) +/*! FEEDDIVACK - feedback divider ratio change acknowledge. + */ +#define SYSCON_PLL1STAT_FEEDDIVACK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1STAT_FEEDDIVACK_SHIFT)) & SYSCON_PLL1STAT_FEEDDIVACK_MASK) + +#define SYSCON_PLL1STAT_POSTDIVACK_MASK (0x8U) +#define SYSCON_PLL1STAT_POSTDIVACK_SHIFT (3U) +/*! POSTDIVACK - post-divider ratio change acknowledge. + */ +#define SYSCON_PLL1STAT_POSTDIVACK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1STAT_POSTDIVACK_SHIFT)) & SYSCON_PLL1STAT_POSTDIVACK_MASK) + +#define SYSCON_PLL1STAT_FRMDET_MASK (0x10U) +#define SYSCON_PLL1STAT_FRMDET_SHIFT (4U) +/*! FRMDET - free running detector output (active high). + */ +#define SYSCON_PLL1STAT_FRMDET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1STAT_FRMDET_SHIFT)) & SYSCON_PLL1STAT_FRMDET_MASK) +/*! @} */ + +/*! @name PLL1NDEC - PLL1 550m N divider */ +/*! @{ */ + +#define SYSCON_PLL1NDEC_NDIV_MASK (0xFFU) +#define SYSCON_PLL1NDEC_NDIV_SHIFT (0U) +/*! NDIV - pre-divider divider ratio (N-divider). + */ +#define SYSCON_PLL1NDEC_NDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1NDEC_NDIV_SHIFT)) & SYSCON_PLL1NDEC_NDIV_MASK) + +#define SYSCON_PLL1NDEC_NREQ_MASK (0x100U) +#define SYSCON_PLL1NDEC_NREQ_SHIFT (8U) +/*! NREQ - pre-divider ratio change request. + */ +#define SYSCON_PLL1NDEC_NREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1NDEC_NREQ_SHIFT)) & SYSCON_PLL1NDEC_NREQ_MASK) +/*! @} */ + +/*! @name PLL1MDEC - PLL1 550m M divider */ +/*! @{ */ + +#define SYSCON_PLL1MDEC_MDIV_MASK (0xFFFFU) +#define SYSCON_PLL1MDEC_MDIV_SHIFT (0U) +/*! MDIV - feedback divider divider ratio (M-divider). + */ +#define SYSCON_PLL1MDEC_MDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1MDEC_MDIV_SHIFT)) & SYSCON_PLL1MDEC_MDIV_MASK) + +#define SYSCON_PLL1MDEC_MREQ_MASK (0x10000U) +#define SYSCON_PLL1MDEC_MREQ_SHIFT (16U) +/*! MREQ - feedback ratio change request. + */ +#define SYSCON_PLL1MDEC_MREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1MDEC_MREQ_SHIFT)) & SYSCON_PLL1MDEC_MREQ_MASK) +/*! @} */ + +/*! @name PLL1PDEC - PLL1 550m P divider */ +/*! @{ */ + +#define SYSCON_PLL1PDEC_PDIV_MASK (0x1FU) +#define SYSCON_PLL1PDEC_PDIV_SHIFT (0U) +/*! PDIV - post-divider divider ratio (P-divider) + */ +#define SYSCON_PLL1PDEC_PDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1PDEC_PDIV_SHIFT)) & SYSCON_PLL1PDEC_PDIV_MASK) + +#define SYSCON_PLL1PDEC_PREQ_MASK (0x20U) +#define SYSCON_PLL1PDEC_PREQ_SHIFT (5U) +/*! PREQ - feedback ratio change request. + */ +#define SYSCON_PLL1PDEC_PREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1PDEC_PREQ_SHIFT)) & SYSCON_PLL1PDEC_PREQ_MASK) +/*! @} */ + +/*! @name PLL0CTRL - PLL0 550m control */ +/*! @{ */ + +#define SYSCON_PLL0CTRL_SELR_MASK (0xFU) +#define SYSCON_PLL0CTRL_SELR_SHIFT (0U) +/*! SELR - Bandwidth select R value. + */ +#define SYSCON_PLL0CTRL_SELR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_SELR_SHIFT)) & SYSCON_PLL0CTRL_SELR_MASK) + +#define SYSCON_PLL0CTRL_SELI_MASK (0x3F0U) +#define SYSCON_PLL0CTRL_SELI_SHIFT (4U) +/*! SELI - Bandwidth select I value. + */ +#define SYSCON_PLL0CTRL_SELI(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_SELI_SHIFT)) & SYSCON_PLL0CTRL_SELI_MASK) + +#define SYSCON_PLL0CTRL_SELP_MASK (0x7C00U) +#define SYSCON_PLL0CTRL_SELP_SHIFT (10U) +/*! SELP - Bandwidth select P value. + */ +#define SYSCON_PLL0CTRL_SELP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_SELP_SHIFT)) & SYSCON_PLL0CTRL_SELP_MASK) + +#define SYSCON_PLL0CTRL_BYPASSPLL_MASK (0x8000U) +#define SYSCON_PLL0CTRL_BYPASSPLL_SHIFT (15U) +/*! BYPASSPLL - Bypass PLL input clock is sent directly to the PLL output (default). + * 0b1..Bypass PLL input clock is sent directly to the PLL output. + * 0b0..use PLL. + */ +#define SYSCON_PLL0CTRL_BYPASSPLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_BYPASSPLL_SHIFT)) & SYSCON_PLL0CTRL_BYPASSPLL_MASK) + +#define SYSCON_PLL0CTRL_BYPASSPOSTDIV2_MASK (0x10000U) +#define SYSCON_PLL0CTRL_BYPASSPOSTDIV2_SHIFT (16U) +/*! BYPASSPOSTDIV2 - bypass of the divide-by-2 divider in the post-divider. + * 0b1..bypass of the divide-by-2 divider in the post-divider. + * 0b0..use the divide-by-2 divider in the post-divider. + */ +#define SYSCON_PLL0CTRL_BYPASSPOSTDIV2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_BYPASSPOSTDIV2_SHIFT)) & SYSCON_PLL0CTRL_BYPASSPOSTDIV2_MASK) + +#define SYSCON_PLL0CTRL_LIMUPOFF_MASK (0x20000U) +#define SYSCON_PLL0CTRL_LIMUPOFF_SHIFT (17U) +/*! LIMUPOFF - limup_off = 1 in spread spectrum and fractional PLL applications. + */ +#define SYSCON_PLL0CTRL_LIMUPOFF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_LIMUPOFF_SHIFT)) & SYSCON_PLL0CTRL_LIMUPOFF_MASK) + +#define SYSCON_PLL0CTRL_BWDIRECT_MASK (0x40000U) +#define SYSCON_PLL0CTRL_BWDIRECT_SHIFT (18U) +/*! BWDIRECT - Control of the bandwidth of the PLL. + * 0b1..modify the bandwidth of the PLL directly. + * 0b0..the bandwidth is changed synchronously with the feedback-divider. + */ +#define SYSCON_PLL0CTRL_BWDIRECT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_BWDIRECT_SHIFT)) & SYSCON_PLL0CTRL_BWDIRECT_MASK) + +#define SYSCON_PLL0CTRL_BYPASSPREDIV_MASK (0x80000U) +#define SYSCON_PLL0CTRL_BYPASSPREDIV_SHIFT (19U) +/*! BYPASSPREDIV - bypass of the pre-divider. + * 0b1..bypass of the pre-divider. + * 0b0..use the pre-divider. + */ +#define SYSCON_PLL0CTRL_BYPASSPREDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_BYPASSPREDIV_SHIFT)) & SYSCON_PLL0CTRL_BYPASSPREDIV_MASK) + +#define SYSCON_PLL0CTRL_BYPASSPOSTDIV_MASK (0x100000U) +#define SYSCON_PLL0CTRL_BYPASSPOSTDIV_SHIFT (20U) +/*! BYPASSPOSTDIV - bypass of the post-divider. + * 0b1..bypass of the post-divider. + * 0b0..use the post-divider. + */ +#define SYSCON_PLL0CTRL_BYPASSPOSTDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_BYPASSPOSTDIV_SHIFT)) & SYSCON_PLL0CTRL_BYPASSPOSTDIV_MASK) + +#define SYSCON_PLL0CTRL_CLKEN_MASK (0x200000U) +#define SYSCON_PLL0CTRL_CLKEN_SHIFT (21U) +/*! CLKEN - enable the output clock. + * 0b1..enable the output clock. + * 0b0..disable the output clock. + */ +#define SYSCON_PLL0CTRL_CLKEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_CLKEN_SHIFT)) & SYSCON_PLL0CTRL_CLKEN_MASK) + +#define SYSCON_PLL0CTRL_FRMEN_MASK (0x400000U) +#define SYSCON_PLL0CTRL_FRMEN_SHIFT (22U) +/*! FRMEN - free running mode. + * 0b1..free running mode is enable. + * 0b0..free running mode is disable. + */ +#define SYSCON_PLL0CTRL_FRMEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_FRMEN_SHIFT)) & SYSCON_PLL0CTRL_FRMEN_MASK) + +#define SYSCON_PLL0CTRL_FRMCLKSTABLE_MASK (0x800000U) +#define SYSCON_PLL0CTRL_FRMCLKSTABLE_SHIFT (23U) +/*! FRMCLKSTABLE - free running mode clockstable: Warning: Only make frm_clockstable =1 after the PLL output frequency is stable. + */ +#define SYSCON_PLL0CTRL_FRMCLKSTABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_FRMCLKSTABLE_SHIFT)) & SYSCON_PLL0CTRL_FRMCLKSTABLE_MASK) + +#define SYSCON_PLL0CTRL_SKEWEN_MASK (0x1000000U) +#define SYSCON_PLL0CTRL_SKEWEN_SHIFT (24U) +/*! SKEWEN - skew mode. + * 0b1..skew mode is enable. + * 0b0..skew mode is disable. + */ +#define SYSCON_PLL0CTRL_SKEWEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_SKEWEN_SHIFT)) & SYSCON_PLL0CTRL_SKEWEN_MASK) +/*! @} */ + +/*! @name PLL0STAT - PLL0 550m status */ +/*! @{ */ + +#define SYSCON_PLL0STAT_LOCK_MASK (0x1U) +#define SYSCON_PLL0STAT_LOCK_SHIFT (0U) +/*! LOCK - lock detector output (active high) Warning: The lock signal is only reliable between fref[2] :100 kHz to 20 MHz. + */ +#define SYSCON_PLL0STAT_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0STAT_LOCK_SHIFT)) & SYSCON_PLL0STAT_LOCK_MASK) + +#define SYSCON_PLL0STAT_PREDIVACK_MASK (0x2U) +#define SYSCON_PLL0STAT_PREDIVACK_SHIFT (1U) +/*! PREDIVACK - pre-divider ratio change acknowledge. + */ +#define SYSCON_PLL0STAT_PREDIVACK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0STAT_PREDIVACK_SHIFT)) & SYSCON_PLL0STAT_PREDIVACK_MASK) + +#define SYSCON_PLL0STAT_FEEDDIVACK_MASK (0x4U) +#define SYSCON_PLL0STAT_FEEDDIVACK_SHIFT (2U) +/*! FEEDDIVACK - feedback divider ratio change acknowledge. + */ +#define SYSCON_PLL0STAT_FEEDDIVACK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0STAT_FEEDDIVACK_SHIFT)) & SYSCON_PLL0STAT_FEEDDIVACK_MASK) + +#define SYSCON_PLL0STAT_POSTDIVACK_MASK (0x8U) +#define SYSCON_PLL0STAT_POSTDIVACK_SHIFT (3U) +/*! POSTDIVACK - post-divider ratio change acknowledge. + */ +#define SYSCON_PLL0STAT_POSTDIVACK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0STAT_POSTDIVACK_SHIFT)) & SYSCON_PLL0STAT_POSTDIVACK_MASK) + +#define SYSCON_PLL0STAT_FRMDET_MASK (0x10U) +#define SYSCON_PLL0STAT_FRMDET_SHIFT (4U) +/*! FRMDET - free running detector output (active high). + */ +#define SYSCON_PLL0STAT_FRMDET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0STAT_FRMDET_SHIFT)) & SYSCON_PLL0STAT_FRMDET_MASK) +/*! @} */ + +/*! @name PLL0NDEC - PLL0 550m N divider */ +/*! @{ */ + +#define SYSCON_PLL0NDEC_NDIV_MASK (0xFFU) +#define SYSCON_PLL0NDEC_NDIV_SHIFT (0U) +/*! NDIV - pre-divider divider ratio (N-divider). + */ +#define SYSCON_PLL0NDEC_NDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0NDEC_NDIV_SHIFT)) & SYSCON_PLL0NDEC_NDIV_MASK) + +#define SYSCON_PLL0NDEC_NREQ_MASK (0x100U) +#define SYSCON_PLL0NDEC_NREQ_SHIFT (8U) +/*! NREQ - pre-divider ratio change request. + */ +#define SYSCON_PLL0NDEC_NREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0NDEC_NREQ_SHIFT)) & SYSCON_PLL0NDEC_NREQ_MASK) +/*! @} */ + +/*! @name PLL0PDEC - PLL0 550m P divider */ +/*! @{ */ + +#define SYSCON_PLL0PDEC_PDIV_MASK (0x1FU) +#define SYSCON_PLL0PDEC_PDIV_SHIFT (0U) +/*! PDIV - post-divider divider ratio (P-divider) + */ +#define SYSCON_PLL0PDEC_PDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0PDEC_PDIV_SHIFT)) & SYSCON_PLL0PDEC_PDIV_MASK) + +#define SYSCON_PLL0PDEC_PREQ_MASK (0x20U) +#define SYSCON_PLL0PDEC_PREQ_SHIFT (5U) +/*! PREQ - feedback ratio change request. + */ +#define SYSCON_PLL0PDEC_PREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0PDEC_PREQ_SHIFT)) & SYSCON_PLL0PDEC_PREQ_MASK) +/*! @} */ + +/*! @name PLL0SSCG0 - PLL0 Spread Spectrum Wrapper control register 0 */ +/*! @{ */ + +#define SYSCON_PLL0SSCG0_MD_LBS_MASK (0xFFFFFFFFU) +#define SYSCON_PLL0SSCG0_MD_LBS_SHIFT (0U) +/*! MD_LBS - input word of the wrapper bit 31 to 0. + */ +#define SYSCON_PLL0SSCG0_MD_LBS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG0_MD_LBS_SHIFT)) & SYSCON_PLL0SSCG0_MD_LBS_MASK) +/*! @} */ + +/*! @name PLL0SSCG1 - PLL0 Spread Spectrum Wrapper control register 1 */ +/*! @{ */ + +#define SYSCON_PLL0SSCG1_MD_MBS_MASK (0x1U) +#define SYSCON_PLL0SSCG1_MD_MBS_SHIFT (0U) +/*! MD_MBS - input word of the wrapper bit 32. + */ +#define SYSCON_PLL0SSCG1_MD_MBS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MD_MBS_SHIFT)) & SYSCON_PLL0SSCG1_MD_MBS_MASK) + +#define SYSCON_PLL0SSCG1_MD_REQ_MASK (0x2U) +#define SYSCON_PLL0SSCG1_MD_REQ_SHIFT (1U) +/*! MD_REQ - md change request. + */ +#define SYSCON_PLL0SSCG1_MD_REQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MD_REQ_SHIFT)) & SYSCON_PLL0SSCG1_MD_REQ_MASK) + +#define SYSCON_PLL0SSCG1_MF_MASK (0x1CU) +#define SYSCON_PLL0SSCG1_MF_SHIFT (2U) +/*! MF - programmable modulation frequency fm = Fref/Nss mf[2:0] = 000 => Nss=512 (fm ~ 3. + */ +#define SYSCON_PLL0SSCG1_MF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MF_SHIFT)) & SYSCON_PLL0SSCG1_MF_MASK) + +#define SYSCON_PLL0SSCG1_MR_MASK (0xE0U) +#define SYSCON_PLL0SSCG1_MR_SHIFT (5U) +/*! MR - programmable frequency modulation depth Dfmodpk-pk = Fref*kss/Fcco = kss/(2*md[32:25]dec) + * mr[2:0] = 000 => kss = 0 (no spread spectrum) mr[2:0] = 001 => kss ~ 1 mr[2:0] = 010 => kss ~ 1. + */ +#define SYSCON_PLL0SSCG1_MR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MR_SHIFT)) & SYSCON_PLL0SSCG1_MR_MASK) + +#define SYSCON_PLL0SSCG1_MC_MASK (0x300U) +#define SYSCON_PLL0SSCG1_MC_SHIFT (8U) +/*! MC - modulation waveform control Compensation for low pass filtering of the PLL to get a + * triangular modulation at the output of the PLL, giving a flat frequency spectrum. + */ +#define SYSCON_PLL0SSCG1_MC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MC_SHIFT)) & SYSCON_PLL0SSCG1_MC_MASK) + +#define SYSCON_PLL0SSCG1_MDIV_EXT_MASK (0x3FFFC00U) +#define SYSCON_PLL0SSCG1_MDIV_EXT_SHIFT (10U) +/*! MDIV_EXT - to select an external mdiv value. + */ +#define SYSCON_PLL0SSCG1_MDIV_EXT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MDIV_EXT_SHIFT)) & SYSCON_PLL0SSCG1_MDIV_EXT_MASK) + +#define SYSCON_PLL0SSCG1_MREQ_MASK (0x4000000U) +#define SYSCON_PLL0SSCG1_MREQ_SHIFT (26U) +/*! MREQ - to select an external mreq value. + */ +#define SYSCON_PLL0SSCG1_MREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MREQ_SHIFT)) & SYSCON_PLL0SSCG1_MREQ_MASK) + +#define SYSCON_PLL0SSCG1_DITHER_MASK (0x8000000U) +#define SYSCON_PLL0SSCG1_DITHER_SHIFT (27U) +/*! DITHER - dithering between two modulation frequencies in a random way or in a pseudo random way + * (white noise), in order to decrease the probability that the modulated waveform will occur + * with the same phase on a particular point on the screen. + */ +#define SYSCON_PLL0SSCG1_DITHER(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_DITHER_SHIFT)) & SYSCON_PLL0SSCG1_DITHER_MASK) + +#define SYSCON_PLL0SSCG1_SEL_EXT_MASK (0x10000000U) +#define SYSCON_PLL0SSCG1_SEL_EXT_SHIFT (28U) +/*! SEL_EXT - to select mdiv_ext and mreq_ext sel_ext = 0: mdiv ~ md[32:0], mreq = 1 sel_ext = 1 : mdiv = mdiv_ext, mreq = mreq_ext. + */ +#define SYSCON_PLL0SSCG1_SEL_EXT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_SEL_EXT_SHIFT)) & SYSCON_PLL0SSCG1_SEL_EXT_MASK) +/*! @} */ + +/*! @name FUNCRETENTIONCTRL - Functional retention control register */ +/*! @{ */ + +#define SYSCON_FUNCRETENTIONCTRL_FUNCRETENA_MASK (0x1U) +#define SYSCON_FUNCRETENTIONCTRL_FUNCRETENA_SHIFT (0U) +/*! FUNCRETENA - functional retention in power down only. + * 0b1..enable functional retention. + * 0b0..disable functional retention. + */ +#define SYSCON_FUNCRETENTIONCTRL_FUNCRETENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FUNCRETENTIONCTRL_FUNCRETENA_SHIFT)) & SYSCON_FUNCRETENTIONCTRL_FUNCRETENA_MASK) + +#define SYSCON_FUNCRETENTIONCTRL_RET_START_MASK (0x3FFEU) +#define SYSCON_FUNCRETENTIONCTRL_RET_START_SHIFT (1U) +/*! RET_START - Start address divided by 4 inside SRAMX bank. + */ +#define SYSCON_FUNCRETENTIONCTRL_RET_START(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FUNCRETENTIONCTRL_RET_START_SHIFT)) & SYSCON_FUNCRETENTIONCTRL_RET_START_MASK) + +#define SYSCON_FUNCRETENTIONCTRL_RET_LENTH_MASK (0xFFC000U) +#define SYSCON_FUNCRETENTIONCTRL_RET_LENTH_SHIFT (14U) +/*! RET_LENTH - lenth of Scan chains to save. + */ +#define SYSCON_FUNCRETENTIONCTRL_RET_LENTH(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FUNCRETENTIONCTRL_RET_LENTH_SHIFT)) & SYSCON_FUNCRETENTIONCTRL_RET_LENTH_MASK) +/*! @} */ + +/*! @name CPSTAT - CPU Status */ +/*! @{ */ + +#define SYSCON_CPSTAT_CPU0SLEEPING_MASK (0x1U) +#define SYSCON_CPSTAT_CPU0SLEEPING_SHIFT (0U) +/*! CPU0SLEEPING - The CPU0 sleeping state. + * 0b1..the CPU is sleeping. + * 0b0..the CPU is not sleeping. + */ +#define SYSCON_CPSTAT_CPU0SLEEPING(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPSTAT_CPU0SLEEPING_SHIFT)) & SYSCON_CPSTAT_CPU0SLEEPING_MASK) + +#define SYSCON_CPSTAT_CPU0LOCKUP_MASK (0x4U) +#define SYSCON_CPSTAT_CPU0LOCKUP_SHIFT (2U) +/*! CPU0LOCKUP - The CPU0 lockup state. + * 0b1..the CPU is in lockup. + * 0b0..the CPU is not in lockup. + */ +#define SYSCON_CPSTAT_CPU0LOCKUP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPSTAT_CPU0LOCKUP_SHIFT)) & SYSCON_CPSTAT_CPU0LOCKUP_MASK) +/*! @} */ + +/*! @name BOOT_SEED_REG0 - boot seed (256-bit random value) */ +/*! @{ */ + +#define SYSCON_BOOT_SEED_REG0_BOOT_SEED_REG0_MASK (0xFFFFFFFFU) +#define SYSCON_BOOT_SEED_REG0_BOOT_SEED_REG0_SHIFT (0U) +#define SYSCON_BOOT_SEED_REG0_BOOT_SEED_REG0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BOOT_SEED_REG0_BOOT_SEED_REG0_SHIFT)) & SYSCON_BOOT_SEED_REG0_BOOT_SEED_REG0_MASK) +/*! @} */ + +/*! @name BOOT_SEED_REG1 - boot seed (256-bit random value) */ +/*! @{ */ + +#define SYSCON_BOOT_SEED_REG1_BOOT_SEED_REG1_MASK (0xFFFFFFFFU) +#define SYSCON_BOOT_SEED_REG1_BOOT_SEED_REG1_SHIFT (0U) +#define SYSCON_BOOT_SEED_REG1_BOOT_SEED_REG1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BOOT_SEED_REG1_BOOT_SEED_REG1_SHIFT)) & SYSCON_BOOT_SEED_REG1_BOOT_SEED_REG1_MASK) +/*! @} */ + +/*! @name BOOT_SEED_REG2 - boot seed (256-bit random value) */ +/*! @{ */ + +#define SYSCON_BOOT_SEED_REG2_BOOT_SEED_REG2_MASK (0xFFFFFFFFU) +#define SYSCON_BOOT_SEED_REG2_BOOT_SEED_REG2_SHIFT (0U) +#define SYSCON_BOOT_SEED_REG2_BOOT_SEED_REG2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BOOT_SEED_REG2_BOOT_SEED_REG2_SHIFT)) & SYSCON_BOOT_SEED_REG2_BOOT_SEED_REG2_MASK) +/*! @} */ + +/*! @name BOOT_SEED_REG3 - boot seed (256-bit random value) */ +/*! @{ */ + +#define SYSCON_BOOT_SEED_REG3_BOOT_SEED_REG3_MASK (0xFFFFFFFFU) +#define SYSCON_BOOT_SEED_REG3_BOOT_SEED_REG3_SHIFT (0U) +#define SYSCON_BOOT_SEED_REG3_BOOT_SEED_REG3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BOOT_SEED_REG3_BOOT_SEED_REG3_SHIFT)) & SYSCON_BOOT_SEED_REG3_BOOT_SEED_REG3_MASK) +/*! @} */ + +/*! @name BOOT_SEED_REG4 - boot seed (256-bit random value) */ +/*! @{ */ + +#define SYSCON_BOOT_SEED_REG4_BOOT_SEED_REG4_MASK (0xFFFFFFFFU) +#define SYSCON_BOOT_SEED_REG4_BOOT_SEED_REG4_SHIFT (0U) +#define SYSCON_BOOT_SEED_REG4_BOOT_SEED_REG4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BOOT_SEED_REG4_BOOT_SEED_REG4_SHIFT)) & SYSCON_BOOT_SEED_REG4_BOOT_SEED_REG4_MASK) +/*! @} */ + +/*! @name BOOT_SEED_REG5 - boot seed (256-bit random value) */ +/*! @{ */ + +#define SYSCON_BOOT_SEED_REG5_BOOT_SEED_REG5_MASK (0xFFFFFFFFU) +#define SYSCON_BOOT_SEED_REG5_BOOT_SEED_REG5_SHIFT (0U) +#define SYSCON_BOOT_SEED_REG5_BOOT_SEED_REG5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BOOT_SEED_REG5_BOOT_SEED_REG5_SHIFT)) & SYSCON_BOOT_SEED_REG5_BOOT_SEED_REG5_MASK) +/*! @} */ + +/*! @name BOOT_SEED_REG6 - boot seed (256-bit random value) */ +/*! @{ */ + +#define SYSCON_BOOT_SEED_REG6_BOOT_SEED_REG6_MASK (0xFFFFFFFFU) +#define SYSCON_BOOT_SEED_REG6_BOOT_SEED_REG6_SHIFT (0U) +#define SYSCON_BOOT_SEED_REG6_BOOT_SEED_REG6(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BOOT_SEED_REG6_BOOT_SEED_REG6_SHIFT)) & SYSCON_BOOT_SEED_REG6_BOOT_SEED_REG6_MASK) +/*! @} */ + +/*! @name BOOT_SEED_REG7 - boot seed (256-bit random value) */ +/*! @{ */ + +#define SYSCON_BOOT_SEED_REG7_BOOT_SEED_REG7_MASK (0xFFFFFFFFU) +#define SYSCON_BOOT_SEED_REG7_BOOT_SEED_REG7_SHIFT (0U) +#define SYSCON_BOOT_SEED_REG7_BOOT_SEED_REG7(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BOOT_SEED_REG7_BOOT_SEED_REG7_SHIFT)) & SYSCON_BOOT_SEED_REG7_BOOT_SEED_REG7_MASK) +/*! @} */ + +/*! @name HMAC_REG0 - HMAC */ +/*! @{ */ + +#define SYSCON_HMAC_REG0_HMAC_REG0_MASK (0xFFFFFFFFU) +#define SYSCON_HMAC_REG0_HMAC_REG0_SHIFT (0U) +#define SYSCON_HMAC_REG0_HMAC_REG0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HMAC_REG0_HMAC_REG0_SHIFT)) & SYSCON_HMAC_REG0_HMAC_REG0_MASK) +/*! @} */ + +/*! @name HMAC_REG1 - HMAC */ +/*! @{ */ + +#define SYSCON_HMAC_REG1_HMAC_REG1_MASK (0xFFFFFFFFU) +#define SYSCON_HMAC_REG1_HMAC_REG1_SHIFT (0U) +#define SYSCON_HMAC_REG1_HMAC_REG1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HMAC_REG1_HMAC_REG1_SHIFT)) & SYSCON_HMAC_REG1_HMAC_REG1_MASK) +/*! @} */ + +/*! @name HMAC_REG2 - HMAC */ +/*! @{ */ + +#define SYSCON_HMAC_REG2_HMAC_REG2_MASK (0xFFFFFFFFU) +#define SYSCON_HMAC_REG2_HMAC_REG2_SHIFT (0U) +#define SYSCON_HMAC_REG2_HMAC_REG2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HMAC_REG2_HMAC_REG2_SHIFT)) & SYSCON_HMAC_REG2_HMAC_REG2_MASK) +/*! @} */ + +/*! @name HMAC_REG3 - HMAC */ +/*! @{ */ + +#define SYSCON_HMAC_REG3_HMAC_REG3_MASK (0xFFFFFFFFU) +#define SYSCON_HMAC_REG3_HMAC_REG3_SHIFT (0U) +#define SYSCON_HMAC_REG3_HMAC_REG3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HMAC_REG3_HMAC_REG3_SHIFT)) & SYSCON_HMAC_REG3_HMAC_REG3_MASK) +/*! @} */ + +/*! @name HMAC_REG4 - HMAC */ +/*! @{ */ + +#define SYSCON_HMAC_REG4_HMAC_REG4_MASK (0xFFFFFFFFU) +#define SYSCON_HMAC_REG4_HMAC_REG4_SHIFT (0U) +#define SYSCON_HMAC_REG4_HMAC_REG4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HMAC_REG4_HMAC_REG4_SHIFT)) & SYSCON_HMAC_REG4_HMAC_REG4_MASK) +/*! @} */ + +/*! @name HMAC_REG5 - HMAC */ +/*! @{ */ + +#define SYSCON_HMAC_REG5_HMAC_REG5_MASK (0xFFFFFFFFU) +#define SYSCON_HMAC_REG5_HMAC_REG5_SHIFT (0U) +#define SYSCON_HMAC_REG5_HMAC_REG5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HMAC_REG5_HMAC_REG5_SHIFT)) & SYSCON_HMAC_REG5_HMAC_REG5_MASK) +/*! @} */ + +/*! @name HMAC_REG6 - HMAC */ +/*! @{ */ + +#define SYSCON_HMAC_REG6_HMAC_REG6_MASK (0xFFFFFFFFU) +#define SYSCON_HMAC_REG6_HMAC_REG6_SHIFT (0U) +#define SYSCON_HMAC_REG6_HMAC_REG6(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HMAC_REG6_HMAC_REG6_SHIFT)) & SYSCON_HMAC_REG6_HMAC_REG6_MASK) +/*! @} */ + +/*! @name HMAC_REG7 - HMAC */ +/*! @{ */ + +#define SYSCON_HMAC_REG7_HMAC_REG7_MASK (0xFFFFFFFFU) +#define SYSCON_HMAC_REG7_HMAC_REG7_SHIFT (0U) +#define SYSCON_HMAC_REG7_HMAC_REG7(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HMAC_REG7_HMAC_REG7_SHIFT)) & SYSCON_HMAC_REG7_HMAC_REG7_MASK) +/*! @} */ + +/*! @name BOOT_LOCK - Control write access to boot seed security registers. */ +/*! @{ */ + +#define SYSCON_BOOT_LOCK_LOCK_BOOT_SEED_MASK (0x1U) +#define SYSCON_BOOT_LOCK_LOCK_BOOT_SEED_SHIFT (0U) +/*! LOCK_BOOT_SEED - Control write access to BOOT_SEED_REG registers. + * 0b1..write access to all 8 registers BOOT_SEED_REG is locked. This register is write once. + */ +#define SYSCON_BOOT_LOCK_LOCK_BOOT_SEED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BOOT_LOCK_LOCK_BOOT_SEED_SHIFT)) & SYSCON_BOOT_LOCK_LOCK_BOOT_SEED_MASK) + +#define SYSCON_BOOT_LOCK_LOCK_HMAC_MASK (0x2U) +#define SYSCON_BOOT_LOCK_LOCK_HMAC_SHIFT (1U) +/*! LOCK_HMAC - Control write access to HMAC_REG registers. + * 0b1..write access to all 8 registers HMAC_REG is locked. This register is write once. + */ +#define SYSCON_BOOT_LOCK_LOCK_HMAC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BOOT_LOCK_LOCK_HMAC_SHIFT)) & SYSCON_BOOT_LOCK_LOCK_HMAC_MASK) +/*! @} */ + +/*! @name CLOCK_CTRL - Various system clock controls : Flash clock (48 MHz) control, clocks to Frequency Measures */ +/*! @{ */ + +#define SYSCON_CLOCK_CTRL_XTAL32MHZ_FREQM_ENA_MASK (0x2U) +#define SYSCON_CLOCK_CTRL_XTAL32MHZ_FREQM_ENA_SHIFT (1U) +/*! XTAL32MHZ_FREQM_ENA - Enable XTAL32MHz clock for Frequency Measure module. + * 0b1..The clock is enabled. + * 0b0..The clock is not enabled. + */ +#define SYSCON_CLOCK_CTRL_XTAL32MHZ_FREQM_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_XTAL32MHZ_FREQM_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_XTAL32MHZ_FREQM_ENA_MASK) + +#define SYSCON_CLOCK_CTRL_FRO1MHZ_UTICK_ENA_MASK (0x4U) +#define SYSCON_CLOCK_CTRL_FRO1MHZ_UTICK_ENA_SHIFT (2U) +/*! FRO1MHZ_UTICK_ENA - Enable FRO 1MHz clock for Frequency Measure module and for UTICK. + * 0b1..The clock is enabled. + * 0b0..The clock is not enabled. + */ +#define SYSCON_CLOCK_CTRL_FRO1MHZ_UTICK_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_FRO1MHZ_UTICK_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_FRO1MHZ_UTICK_ENA_MASK) + +#define SYSCON_CLOCK_CTRL_FRO12MHZ_FREQM_ENA_MASK (0x8U) +#define SYSCON_CLOCK_CTRL_FRO12MHZ_FREQM_ENA_SHIFT (3U) +/*! FRO12MHZ_FREQM_ENA - Enable FRO 12MHz clock for Frequency Measure module. + * 0b1..The clock is enabled. + * 0b0..The clock is not enabled. + */ +#define SYSCON_CLOCK_CTRL_FRO12MHZ_FREQM_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_FRO12MHZ_FREQM_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_FRO12MHZ_FREQM_ENA_MASK) + +#define SYSCON_CLOCK_CTRL_FRO_HF_FREQM_ENA_MASK (0x10U) +#define SYSCON_CLOCK_CTRL_FRO_HF_FREQM_ENA_SHIFT (4U) +/*! FRO_HF_FREQM_ENA - Enable FRO 96MHz clock for Frequency Measure module. + * 0b1..The clock is enabled. + * 0b0..The clock is not enabled. + */ +#define SYSCON_CLOCK_CTRL_FRO_HF_FREQM_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_FRO_HF_FREQM_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_FRO_HF_FREQM_ENA_MASK) + +#define SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK (0x20U) +#define SYSCON_CLOCK_CTRL_CLKIN_ENA_SHIFT (5U) +/*! CLKIN_ENA - Enable clock_in clock for clock module. + * 0b1..The clock is enabled. + * 0b0..The clock is not enabled. + */ +#define SYSCON_CLOCK_CTRL_CLKIN_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_CLKIN_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK) + +#define SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_MASK (0x40U) +#define SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_SHIFT (6U) +/*! FRO1MHZ_CLK_ENA - Enable FRO 1MHz clock for clock muxing in clock gen. + * 0b1..The clock is enabled. + * 0b0..The clock is not enabled. + */ +#define SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_MASK) + +#define SYSCON_CLOCK_CTRL_ANA_FRO12M_CLK_ENA_MASK (0x80U) +#define SYSCON_CLOCK_CTRL_ANA_FRO12M_CLK_ENA_SHIFT (7U) +/*! ANA_FRO12M_CLK_ENA - Enable FRO 12MHz clock for analog control of the FRO 192MHz. + * 0b1..The clock is enabled. + * 0b0..The clock is not enabled. + */ +#define SYSCON_CLOCK_CTRL_ANA_FRO12M_CLK_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_ANA_FRO12M_CLK_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_ANA_FRO12M_CLK_ENA_MASK) + +#define SYSCON_CLOCK_CTRL_XO_CAL_CLK_ENA_MASK (0x100U) +#define SYSCON_CLOCK_CTRL_XO_CAL_CLK_ENA_SHIFT (8U) +/*! XO_CAL_CLK_ENA - Enable clock for cristal oscilator calibration. + * 0b1..The clock is enabled. + * 0b0..The clock is not enabled. + */ +#define SYSCON_CLOCK_CTRL_XO_CAL_CLK_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_XO_CAL_CLK_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_XO_CAL_CLK_ENA_MASK) + +#define SYSCON_CLOCK_CTRL_PLU_DEGLITCH_CLK_ENA_MASK (0x200U) +#define SYSCON_CLOCK_CTRL_PLU_DEGLITCH_CLK_ENA_SHIFT (9U) +/*! PLU_DEGLITCH_CLK_ENA - Enable clocks FRO_1MHz and FRO_12MHz for PLU deglitching. + * 0b1..The clock is enabled. + * 0b0..The clock is not enabled. + */ +#define SYSCON_CLOCK_CTRL_PLU_DEGLITCH_CLK_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_PLU_DEGLITCH_CLK_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_PLU_DEGLITCH_CLK_ENA_MASK) +/*! @} */ + +/*! @name COMP_INT_CTRL - Comparator Interrupt control */ +/*! @{ */ + +#define SYSCON_COMP_INT_CTRL_INT_ENABLE_MASK (0x1U) +#define SYSCON_COMP_INT_CTRL_INT_ENABLE_SHIFT (0U) +/*! INT_ENABLE - Analog Comparator interrupt enable control:. + * 0b1..interrupt enable. + * 0b0..interrupt disable. + */ +#define SYSCON_COMP_INT_CTRL_INT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_CTRL_INT_ENABLE_SHIFT)) & SYSCON_COMP_INT_CTRL_INT_ENABLE_MASK) + +#define SYSCON_COMP_INT_CTRL_INT_CLEAR_MASK (0x2U) +#define SYSCON_COMP_INT_CTRL_INT_CLEAR_SHIFT (1U) +/*! INT_CLEAR - Analog Comparator interrupt clear. + * 0b0..No effect. + * 0b1..Clear the interrupt. Self-cleared bit. + */ +#define SYSCON_COMP_INT_CTRL_INT_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_CTRL_INT_CLEAR_SHIFT)) & SYSCON_COMP_INT_CTRL_INT_CLEAR_MASK) + +#define SYSCON_COMP_INT_CTRL_INT_CTRL_MASK (0x1CU) +#define SYSCON_COMP_INT_CTRL_INT_CTRL_SHIFT (2U) +/*! INT_CTRL - Comparator interrupt type selector:. + * 0b000..The analog comparator interrupt edge sensitive is disabled. + * 0b010..analog comparator interrupt is rising edge sensitive. + * 0b100..analog comparator interrupt is falling edge sensitive. + * 0b110..analog comparator interrupt is rising and falling edge sensitive. + * 0b001..The analog comparator interrupt level sensitive is disabled. + * 0b011..Analog Comparator interrupt is high level sensitive. + * 0b101..Analog Comparator interrupt is low level sensitive. + * 0b111..The analog comparator interrupt level sensitive is disabled. + */ +#define SYSCON_COMP_INT_CTRL_INT_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_CTRL_INT_CTRL_SHIFT)) & SYSCON_COMP_INT_CTRL_INT_CTRL_MASK) + +#define SYSCON_COMP_INT_CTRL_INT_SOURCE_MASK (0x20U) +#define SYSCON_COMP_INT_CTRL_INT_SOURCE_SHIFT (5U) +/*! INT_SOURCE - Select which Analog comparator output (filtered our un-filtered) is used for interrupt detection. + * 0b0..Select Analog Comparator filtered output as input for interrupt detection. + * 0b1..Select Analog Comparator raw output (unfiltered) as input for interrupt detection. Must be used when + * Analog comparator is used as wake up source in Power down mode. + */ +#define SYSCON_COMP_INT_CTRL_INT_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_CTRL_INT_SOURCE_SHIFT)) & SYSCON_COMP_INT_CTRL_INT_SOURCE_MASK) +/*! @} */ + +/*! @name COMP_INT_STATUS - Comparator Interrupt status */ +/*! @{ */ + +#define SYSCON_COMP_INT_STATUS_STATUS_MASK (0x1U) +#define SYSCON_COMP_INT_STATUS_STATUS_SHIFT (0U) +/*! STATUS - Interrupt status BEFORE Interrupt Enable. + * 0b0..no interrupt pending. + * 0b1..interrupt pending. + */ +#define SYSCON_COMP_INT_STATUS_STATUS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_STATUS_STATUS_SHIFT)) & SYSCON_COMP_INT_STATUS_STATUS_MASK) + +#define SYSCON_COMP_INT_STATUS_INT_STATUS_MASK (0x2U) +#define SYSCON_COMP_INT_STATUS_INT_STATUS_SHIFT (1U) +/*! INT_STATUS - Interrupt status AFTER Interrupt Enable. + * 0b0..no interrupt pending. + * 0b1..interrupt pending. + */ +#define SYSCON_COMP_INT_STATUS_INT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_STATUS_INT_STATUS_SHIFT)) & SYSCON_COMP_INT_STATUS_INT_STATUS_MASK) + +#define SYSCON_COMP_INT_STATUS_VAL_MASK (0x4U) +#define SYSCON_COMP_INT_STATUS_VAL_SHIFT (2U) +/*! VAL - comparator analog output. + * 0b1..P+ is greater than P-. + * 0b0..P+ is smaller than P-. + */ +#define SYSCON_COMP_INT_STATUS_VAL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_STATUS_VAL_SHIFT)) & SYSCON_COMP_INT_STATUS_VAL_MASK) +/*! @} */ + +/*! @name AUTOCLKGATEOVERRIDE - Control automatic clock gating */ +/*! @{ */ + +#define SYSCON_AUTOCLKGATEOVERRIDE_ROM_MASK (0x1U) +#define SYSCON_AUTOCLKGATEOVERRIDE_ROM_SHIFT (0U) +/*! ROM - Control automatic clock gating of ROM controller. + * 0b1..Automatic clock gating is overridden (Clock gating is disabled). + * 0b0..Automatic clock gating is not overridden. + */ +#define SYSCON_AUTOCLKGATEOVERRIDE_ROM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_ROM_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_ROM_MASK) + +#define SYSCON_AUTOCLKGATEOVERRIDE_RAMX_CTRL_MASK (0x2U) +#define SYSCON_AUTOCLKGATEOVERRIDE_RAMX_CTRL_SHIFT (1U) +/*! RAMX_CTRL - Control automatic clock gating of RAMX controller. + * 0b1..Automatic clock gating is overridden (Clock gating is disabled). + * 0b0..Automatic clock gating is not overridden. + */ +#define SYSCON_AUTOCLKGATEOVERRIDE_RAMX_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAMX_CTRL_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAMX_CTRL_MASK) + +#define SYSCON_AUTOCLKGATEOVERRIDE_RAM0_CTRL_MASK (0x4U) +#define SYSCON_AUTOCLKGATEOVERRIDE_RAM0_CTRL_SHIFT (2U) +/*! RAM0_CTRL - Control automatic clock gating of RAM0 controller. + * 0b1..Automatic clock gating is overridden (Clock gating is disabled). + * 0b0..Automatic clock gating is not overridden. + */ +#define SYSCON_AUTOCLKGATEOVERRIDE_RAM0_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAM0_CTRL_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAM0_CTRL_MASK) + +#define SYSCON_AUTOCLKGATEOVERRIDE_RAM1_CTRL_MASK (0x8U) +#define SYSCON_AUTOCLKGATEOVERRIDE_RAM1_CTRL_SHIFT (3U) +/*! RAM1_CTRL - Control automatic clock gating of RAM1 controller. + * 0b1..Automatic clock gating is overridden (Clock gating is disabled). + * 0b0..Automatic clock gating is not overridden. + */ +#define SYSCON_AUTOCLKGATEOVERRIDE_RAM1_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAM1_CTRL_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAM1_CTRL_MASK) + +#define SYSCON_AUTOCLKGATEOVERRIDE_RAM2_CTRL_MASK (0x10U) +#define SYSCON_AUTOCLKGATEOVERRIDE_RAM2_CTRL_SHIFT (4U) +/*! RAM2_CTRL - Control automatic clock gating of RAM2 controller. + * 0b1..Automatic clock gating is overridden (Clock gating is disabled). + * 0b0..Automatic clock gating is not overridden. + */ +#define SYSCON_AUTOCLKGATEOVERRIDE_RAM2_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAM2_CTRL_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAM2_CTRL_MASK) + +#define SYSCON_AUTOCLKGATEOVERRIDE_SYNC0_APB_MASK (0x80U) +#define SYSCON_AUTOCLKGATEOVERRIDE_SYNC0_APB_SHIFT (7U) +/*! SYNC0_APB - Control automatic clock gating of synchronous bridge controller 0. + * 0b1..Automatic clock gating is overridden (Clock gating is disabled). + * 0b0..Automatic clock gating is not overridden. + */ +#define SYSCON_AUTOCLKGATEOVERRIDE_SYNC0_APB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_SYNC0_APB_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_SYNC0_APB_MASK) + +#define SYSCON_AUTOCLKGATEOVERRIDE_SYNC1_APB_MASK (0x100U) +#define SYSCON_AUTOCLKGATEOVERRIDE_SYNC1_APB_SHIFT (8U) +/*! SYNC1_APB - Control automatic clock gating of synchronous bridge controller 1. + * 0b1..Automatic clock gating is overridden (Clock gating is disabled). + * 0b0..Automatic clock gating is not overridden. + */ +#define SYSCON_AUTOCLKGATEOVERRIDE_SYNC1_APB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_SYNC1_APB_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_SYNC1_APB_MASK) + +#define SYSCON_AUTOCLKGATEOVERRIDE_CRCGEN_MASK (0x800U) +#define SYSCON_AUTOCLKGATEOVERRIDE_CRCGEN_SHIFT (11U) +/*! CRCGEN - Control automatic clock gating of CRCGEN controller. + * 0b1..Automatic clock gating is overridden (Clock gating is disabled). + * 0b0..Automatic clock gating is not overridden. + */ +#define SYSCON_AUTOCLKGATEOVERRIDE_CRCGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_CRCGEN_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_CRCGEN_MASK) + +#define SYSCON_AUTOCLKGATEOVERRIDE_SDMA0_MASK (0x1000U) +#define SYSCON_AUTOCLKGATEOVERRIDE_SDMA0_SHIFT (12U) +/*! SDMA0 - Control automatic clock gating of DMA0 controller. + * 0b1..Automatic clock gating is overridden (Clock gating is disabled). + * 0b0..Automatic clock gating is not overridden. + */ +#define SYSCON_AUTOCLKGATEOVERRIDE_SDMA0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_SDMA0_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_SDMA0_MASK) + +#define SYSCON_AUTOCLKGATEOVERRIDE_SDMA1_MASK (0x2000U) +#define SYSCON_AUTOCLKGATEOVERRIDE_SDMA1_SHIFT (13U) +/*! SDMA1 - Control automatic clock gating of DMA1 controller. + * 0b1..Automatic clock gating is overridden (Clock gating is disabled). + * 0b0..Automatic clock gating is not overridden. + */ +#define SYSCON_AUTOCLKGATEOVERRIDE_SDMA1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_SDMA1_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_SDMA1_MASK) + +#define SYSCON_AUTOCLKGATEOVERRIDE_USB0_MASK (0x4000U) +#define SYSCON_AUTOCLKGATEOVERRIDE_USB0_SHIFT (14U) +/*! USB0 - Control automatic clock gating of USB controller. + * 0b1..Automatic clock gating is overridden (Clock gating is disabled). + * 0b0..Automatic clock gating is not overridden. + */ +#define SYSCON_AUTOCLKGATEOVERRIDE_USB0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_USB0_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_USB0_MASK) + +#define SYSCON_AUTOCLKGATEOVERRIDE_SYSCON_MASK (0x8000U) +#define SYSCON_AUTOCLKGATEOVERRIDE_SYSCON_SHIFT (15U) +/*! SYSCON - Control automatic clock gating of synchronous system controller registers bank. + * 0b1..Automatic clock gating is overridden (Clock gating is disabled). + * 0b0..Automatic clock gating is not overridden. + */ +#define SYSCON_AUTOCLKGATEOVERRIDE_SYSCON(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_SYSCON_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_SYSCON_MASK) + +#define SYSCON_AUTOCLKGATEOVERRIDE_ENABLEUPDATE_MASK (0xFFFF0000U) +#define SYSCON_AUTOCLKGATEOVERRIDE_ENABLEUPDATE_SHIFT (16U) +/*! ENABLEUPDATE - The value 0xC0DE must be written for AUTOCLKGATEOVERRIDE registers fields updates to have effect. + * 0b1100000011011110..Bit Fields 0 - 15 of this register are updated + * 0b0000000000000000..Bit Fields 0 - 15 of this register are not updated + */ +#define SYSCON_AUTOCLKGATEOVERRIDE_ENABLEUPDATE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_ENABLEUPDATE_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_ENABLEUPDATE_MASK) +/*! @} */ + +/*! @name GPIOPSYNC - Enable bypass of the first stage of synchonization inside GPIO_INT module */ +/*! @{ */ + +#define SYSCON_GPIOPSYNC_PSYNC_MASK (0x1U) +#define SYSCON_GPIOPSYNC_PSYNC_SHIFT (0U) +/*! PSYNC - Enable bypass of the first stage of synchonization inside GPIO_INT module. + * 0b1..bypass of the first stage of synchonization inside GPIO_INT module. + * 0b0..use the first stage of synchonization inside GPIO_INT module. + */ +#define SYSCON_GPIOPSYNC_PSYNC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_GPIOPSYNC_PSYNC_SHIFT)) & SYSCON_GPIOPSYNC_PSYNC_MASK) +/*! @} */ + +/*! @name HASHRESTHWKEY - Controls whether the HASH AES hardware secret key is restricted to use by secure code */ +/*! @{ */ + +#define SYSCON_HASHRESTHWKEY_UNLOCKCODE_MASK (0xFFFFFFFFU) +#define SYSCON_HASHRESTHWKEY_UNLOCKCODE_SHIFT (0U) +/*! UNLOCKCODE - Code value that controls whether HASH AES hardware secret key is unlocked + * 0b11000011001111001010010101011010..HASH AES hardware secret key is unlocked for use by non-secure code. Any + * other value means that the hardware secret key is restricted to use by + * secure code only. + */ +#define SYSCON_HASHRESTHWKEY_UNLOCKCODE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HASHRESTHWKEY_UNLOCKCODE_SHIFT)) & SYSCON_HASHRESTHWKEY_UNLOCKCODE_MASK) +/*! @} */ + +/*! @name DEBUG_LOCK_EN - Control write access to security registers. */ +/*! @{ */ + +#define SYSCON_DEBUG_LOCK_EN_LOCK_ALL_MASK (0xFU) +#define SYSCON_DEBUG_LOCK_EN_LOCK_ALL_SHIFT (0U) +/*! LOCK_ALL - Control write access to security registers. + * 0b1010..1010: Enable write access to all registers. + * 0b0000..Any other value than b1010: disable write access to all registers. + */ +#define SYSCON_DEBUG_LOCK_EN_LOCK_ALL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_LOCK_EN_LOCK_ALL_SHIFT)) & SYSCON_DEBUG_LOCK_EN_LOCK_ALL_MASK) +/*! @} */ + +/*! @name DEBUG_FEATURES - Cortex debug features control. */ +/*! @{ */ + +#define SYSCON_DEBUG_FEATURES_CPU0_DBGEN_MASK (0x3U) +#define SYSCON_DEBUG_FEATURES_CPU0_DBGEN_SHIFT (0U) +/*! CPU0_DBGEN - CPU0 Invasive debug control:. + * 0b10..10: Invasive debug is enabled. + * 0b01..Any other value than b10: invasive debug is disable. + */ +#define SYSCON_DEBUG_FEATURES_CPU0_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CPU0_DBGEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CPU0_DBGEN_MASK) + +#define SYSCON_DEBUG_FEATURES_CPU0_NIDEN_MASK (0xCU) +#define SYSCON_DEBUG_FEATURES_CPU0_NIDEN_SHIFT (2U) +/*! CPU0_NIDEN - CPU0 Non Invasive debug control:. + * 0b10..10: Invasive debug is enabled. + * 0b01..Any other value than b10: invasive debug is disable. + */ +#define SYSCON_DEBUG_FEATURES_CPU0_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CPU0_NIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CPU0_NIDEN_MASK) + +#define SYSCON_DEBUG_FEATURES_CPU0_SPIDEN_MASK (0x30U) +#define SYSCON_DEBUG_FEATURES_CPU0_SPIDEN_SHIFT (4U) +/*! CPU0_SPIDEN - CPU0 Secure Invasive debug control:. + * 0b10..10: Invasive debug is enabled. + * 0b01..Any other value than b10: invasive debug is disable. + */ +#define SYSCON_DEBUG_FEATURES_CPU0_SPIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CPU0_SPIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CPU0_SPIDEN_MASK) + +#define SYSCON_DEBUG_FEATURES_CPU0_SPNIDEN_MASK (0xC0U) +#define SYSCON_DEBUG_FEATURES_CPU0_SPNIDEN_SHIFT (6U) +/*! CPU0_SPNIDEN - CPU0 Secure Non Invasive debug control:. + * 0b10..10: Invasive debug is enabled. + * 0b01..Any other value than b10: invasive debug is disable. + */ +#define SYSCON_DEBUG_FEATURES_CPU0_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CPU0_SPNIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CPU0_SPNIDEN_MASK) +/*! @} */ + +/*! @name DEBUG_FEATURES_DP - Cortex debug features control. (duplicate) */ +/*! @{ */ + +#define SYSCON_DEBUG_FEATURES_DP_CPU0_DBGEN_MASK (0x3U) +#define SYSCON_DEBUG_FEATURES_DP_CPU0_DBGEN_SHIFT (0U) +/*! CPU0_DBGEN - CPU0 (CPU0) Invasive debug control:. + * 0b10..10: Invasive debug is enabled. + * 0b01..Any other value than b10: invasive debug is disable. + */ +#define SYSCON_DEBUG_FEATURES_DP_CPU0_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CPU0_DBGEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CPU0_DBGEN_MASK) + +#define SYSCON_DEBUG_FEATURES_DP_CPU0_NIDEN_MASK (0xCU) +#define SYSCON_DEBUG_FEATURES_DP_CPU0_NIDEN_SHIFT (2U) +/*! CPU0_NIDEN - CPU0 Non Invasive debug control:. + * 0b10..10: Invasive debug is enabled. + * 0b01..Any other value than b10: invasive debug is disable. + */ +#define SYSCON_DEBUG_FEATURES_DP_CPU0_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CPU0_NIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CPU0_NIDEN_MASK) + +#define SYSCON_DEBUG_FEATURES_DP_CPU0_SPIDEN_MASK (0x30U) +#define SYSCON_DEBUG_FEATURES_DP_CPU0_SPIDEN_SHIFT (4U) +/*! CPU0_SPIDEN - CPU0 Secure Invasive debug control:. + * 0b10..10: Invasive debug is enabled. + * 0b01..Any other value than b10: invasive debug is disable. + */ +#define SYSCON_DEBUG_FEATURES_DP_CPU0_SPIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CPU0_SPIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CPU0_SPIDEN_MASK) + +#define SYSCON_DEBUG_FEATURES_DP_CPU0_SPNIDEN_MASK (0xC0U) +#define SYSCON_DEBUG_FEATURES_DP_CPU0_SPNIDEN_SHIFT (6U) +/*! CPU0_SPNIDEN - CPU0 Secure Non Invasive debug control:. + * 0b10..10: Invasive debug is enabled. + * 0b01..Any other value than b10: invasive debug is disable. + */ +#define SYSCON_DEBUG_FEATURES_DP_CPU0_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CPU0_SPNIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CPU0_SPNIDEN_MASK) +/*! @} */ + +/*! @name SWD_ACCESS_CPU0 - This register is used by ROM during DEBUG authentication mechanism to enable debug access port for CPU0. */ +/*! @{ */ + +#define SYSCON_SWD_ACCESS_CPU0_SEC_CODE_MASK (0xFFFFFFFFU) +#define SYSCON_SWD_ACCESS_CPU0_SEC_CODE_SHIFT (0U) +/*! SEC_CODE - CPU0 SWD-AP: 0x12345678. + * 0b00010010001101000101011001111000..Value to write to enable CPU0 SWD access. Reading back register will be read as 0xA. + * 0b00000000000000000000000000000000..CPU0 DAP is not allowed. Reading back register will be read as 0x5. + */ +#define SYSCON_SWD_ACCESS_CPU0_SEC_CODE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SWD_ACCESS_CPU0_SEC_CODE_SHIFT)) & SYSCON_SWD_ACCESS_CPU0_SEC_CODE_MASK) +/*! @} */ + +/*! @name KEY_BLOCK - block quiddikey/PUF all index. */ +/*! @{ */ + +#define SYSCON_KEY_BLOCK_KEY_BLOCK_MASK (0xFFFFFFFFU) +#define SYSCON_KEY_BLOCK_KEY_BLOCK_SHIFT (0U) +/*! KEY_BLOCK - Write a value to block quiddikey/PUF all index. + */ +#define SYSCON_KEY_BLOCK_KEY_BLOCK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_KEY_BLOCK_KEY_BLOCK_SHIFT)) & SYSCON_KEY_BLOCK_KEY_BLOCK_MASK) +/*! @} */ + +/*! @name DEBUG_AUTH_BEACON - Debug authentication BEACON register */ +/*! @{ */ + +#define SYSCON_DEBUG_AUTH_BEACON_BEACON_MASK (0xFFFFFFFFU) +#define SYSCON_DEBUG_AUTH_BEACON_BEACON_SHIFT (0U) +/*! BEACON - Set by the debug authentication code in ROM to pass the debug beacons (Credential + * Beacon and Authentication Beacon) to application code. + */ +#define SYSCON_DEBUG_AUTH_BEACON_BEACON(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_AUTH_BEACON_BEACON_SHIFT)) & SYSCON_DEBUG_AUTH_BEACON_BEACON_MASK) +/*! @} */ + +/*! @name DEVICE_ID0 - Device ID */ +/*! @{ */ + +#define SYSCON_DEVICE_ID0_ROM_REV_MINOR_MASK (0xF00000U) +#define SYSCON_DEVICE_ID0_ROM_REV_MINOR_SHIFT (20U) +/*! ROM_REV_MINOR - ROM revision. + */ +#define SYSCON_DEVICE_ID0_ROM_REV_MINOR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEVICE_ID0_ROM_REV_MINOR_SHIFT)) & SYSCON_DEVICE_ID0_ROM_REV_MINOR_MASK) +/*! @} */ + +/*! @name DIEID - Chip revision ID and Number */ +/*! @{ */ + +#define SYSCON_DIEID_REV_ID_MASK (0xFU) +#define SYSCON_DIEID_REV_ID_SHIFT (0U) +/*! REV_ID - Chip Metal Revision ID. + */ +#define SYSCON_DIEID_REV_ID(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DIEID_REV_ID_SHIFT)) & SYSCON_DIEID_REV_ID_MASK) + +#define SYSCON_DIEID_MCO_NUM_IN_DIE_ID_MASK (0xFFFFF0U) +#define SYSCON_DIEID_MCO_NUM_IN_DIE_ID_SHIFT (4U) +/*! MCO_NUM_IN_DIE_ID - Chip Number 0x426B. + */ +#define SYSCON_DIEID_MCO_NUM_IN_DIE_ID(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DIEID_MCO_NUM_IN_DIE_ID_SHIFT)) & SYSCON_DIEID_MCO_NUM_IN_DIE_ID_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group SYSCON_Register_Masks */ + + +/* SYSCON - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral SYSCON base address */ + #define SYSCON_BASE (0x50000000u) + /** Peripheral SYSCON base address */ + #define SYSCON_BASE_NS (0x40000000u) + /** Peripheral SYSCON base pointer */ + #define SYSCON ((SYSCON_Type *)SYSCON_BASE) + /** Peripheral SYSCON base pointer */ + #define SYSCON_NS ((SYSCON_Type *)SYSCON_BASE_NS) + /** Array initializer of SYSCON peripheral base addresses */ + #define SYSCON_BASE_ADDRS { SYSCON_BASE } + /** Array initializer of SYSCON peripheral base pointers */ + #define SYSCON_BASE_PTRS { SYSCON } + /** Array initializer of SYSCON peripheral base addresses */ + #define SYSCON_BASE_ADDRS_NS { SYSCON_BASE_NS } + /** Array initializer of SYSCON peripheral base pointers */ + #define SYSCON_BASE_PTRS_NS { SYSCON_NS } +#else + /** Peripheral SYSCON base address */ + #define SYSCON_BASE (0x40000000u) + /** Peripheral SYSCON base pointer */ + #define SYSCON ((SYSCON_Type *)SYSCON_BASE) + /** Array initializer of SYSCON peripheral base addresses */ + #define SYSCON_BASE_ADDRS { SYSCON_BASE } + /** Array initializer of SYSCON peripheral base pointers */ + #define SYSCON_BASE_PTRS { SYSCON } +#endif + +/*! + * @} + */ /* end of group SYSCON_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- SYSCTL Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SYSCTL_Peripheral_Access_Layer SYSCTL Peripheral Access Layer + * @{ + */ + +/** SYSCTL - Register Layout Typedef */ +typedef struct { + __IO uint32_t UPDATELCKOUT; /**< update lock out control, offset: 0x0 */ + uint8_t RESERVED_0[60]; + __IO uint32_t FCCTRLSEL[8]; /**< Selects the source for SCK going into Flexcomm 0..Selects the source for SCK going into Flexcomm 7, array offset: 0x40, array step: 0x4 */ + uint8_t RESERVED_1[32]; + __IO uint32_t SHAREDCTRLSET[2]; /**< Selects sources and data combinations for shared signal set 0...Selects sources and data combinations for shared signal set 1., array offset: 0x80, array step: 0x4 */ + uint8_t RESERVED_2[120]; + __I uint32_t USB_HS_STATUS; /**< Status register for USB HS, offset: 0x100 */ + uint8_t RESERVED_3[124]; + __IO uint32_t CODE_GRAY_LSB; /**< CODE_GRAY LSB input Register, offset: 0x180 */ + __IO uint32_t CODE_GRAY_MSB; /**< CODE_GRAY MSB input Register, offset: 0x184 */ + __I uint32_t CODE_BIN_LSB; /**< CODE_BIN LSB output Register, offset: 0x188 */ + __I uint32_t CODE_BIN_MSB; /**< CODE_BIN MSB output Register, offset: 0x18C */ +} SYSCTL_Type; + +/* ---------------------------------------------------------------------------- + -- SYSCTL Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SYSCTL_Register_Masks SYSCTL Register Masks + * @{ + */ + +/*! @name UPDATELCKOUT - update lock out control */ +/*! @{ */ + +#define SYSCTL_UPDATELCKOUT_UPDATELCKOUT_MASK (0x1U) +#define SYSCTL_UPDATELCKOUT_UPDATELCKOUT_SHIFT (0U) +/*! UPDATELCKOUT - All Registers + * 0b0..Normal Mode. Can be written to. + * 0b1..Protected Mode. Cannot be written to. + */ +#define SYSCTL_UPDATELCKOUT_UPDATELCKOUT(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_UPDATELCKOUT_UPDATELCKOUT_SHIFT)) & SYSCTL_UPDATELCKOUT_UPDATELCKOUT_MASK) +/*! @} */ + +/*! @name FCCTRLSEL - Selects the source for SCK going into Flexcomm 0..Selects the source for SCK going into Flexcomm 7 */ +/*! @{ */ + +#define SYSCTL_FCCTRLSEL_SCKINSEL_MASK (0x3U) +#define SYSCTL_FCCTRLSEL_SCKINSEL_SHIFT (0U) +/*! SCKINSEL - Selects the source for SCK going into this Flexcomm. + * 0b00..Selects the dedicated FCn_SCK function for this Flexcomm. + * 0b01..SCK is taken from shared signal set 0 (defined by SHAREDCTRLSET0). + * 0b10..SCK is taken from shared signal set 1 (defined by SHAREDCTRLSET1). + * 0b11..Reserved. + */ +#define SYSCTL_FCCTRLSEL_SCKINSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_FCCTRLSEL_SCKINSEL_SHIFT)) & SYSCTL_FCCTRLSEL_SCKINSEL_MASK) + +#define SYSCTL_FCCTRLSEL_WSINSEL_MASK (0x300U) +#define SYSCTL_FCCTRLSEL_WSINSEL_SHIFT (8U) +/*! WSINSEL - Selects the source for WS going into this Flexcomm. + * 0b00..Selects the dedicated (FCn_TXD_SCL_MISO_WS) function for this Flexcomm. + * 0b01..WS is taken from shared signal set 0 (defined by SHAREDCTRLSET0). + * 0b10..WS is taken from shared signal set 1 (defined by SHAREDCTRLSET1). + * 0b11..Reserved. + */ +#define SYSCTL_FCCTRLSEL_WSINSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_FCCTRLSEL_WSINSEL_SHIFT)) & SYSCTL_FCCTRLSEL_WSINSEL_MASK) + +#define SYSCTL_FCCTRLSEL_DATAINSEL_MASK (0x30000U) +#define SYSCTL_FCCTRLSEL_DATAINSEL_SHIFT (16U) +/*! DATAINSEL - Selects the source for DATA input to this Flexcomm. + * 0b00..Selects the dedicated FCn_RXD_SDA_MOSI_DATA input for this Flexcomm. + * 0b01..Input data is taken from shared signal set 0 (defined by SHAREDCTRLSET0). + * 0b10..Input data is taken from shared signal set 1 (defined by SHAREDCTRLSET1). + * 0b11..Reserved. + */ +#define SYSCTL_FCCTRLSEL_DATAINSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_FCCTRLSEL_DATAINSEL_SHIFT)) & SYSCTL_FCCTRLSEL_DATAINSEL_MASK) + +#define SYSCTL_FCCTRLSEL_DATAOUTSEL_MASK (0x3000000U) +#define SYSCTL_FCCTRLSEL_DATAOUTSEL_SHIFT (24U) +/*! DATAOUTSEL - Selects the source for DATA output from this Flexcomm. + * 0b00..Selects the dedicated FCn_RXD_SDA_MOSI_DATA output from this Flexcomm. + * 0b01..Output data is taken from shared signal set 0 (defined by SHAREDCTRLSET0). + * 0b10..Output data is taken from shared signal set 1 (defined by SHAREDCTRLSET1). + * 0b11..Reserved. + */ +#define SYSCTL_FCCTRLSEL_DATAOUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_FCCTRLSEL_DATAOUTSEL_SHIFT)) & SYSCTL_FCCTRLSEL_DATAOUTSEL_MASK) +/*! @} */ + +/* The count of SYSCTL_FCCTRLSEL */ +#define SYSCTL_FCCTRLSEL_COUNT (8U) + +/*! @name SHAREDCTRLSET - Selects sources and data combinations for shared signal set 0...Selects sources and data combinations for shared signal set 1. */ +/*! @{ */ + +#define SYSCTL_SHAREDCTRLSET_SHAREDSCKSEL_MASK (0x7U) +#define SYSCTL_SHAREDCTRLSET_SHAREDSCKSEL_SHIFT (0U) +/*! SHAREDSCKSEL - Selects the source for SCK of this shared signal set. + * 0b000..SCK for this shared signal set comes from Flexcomm 0. + * 0b001..SCK for this shared signal set comes from Flexcomm 1. + * 0b010..SCK for this shared signal set comes from Flexcomm 2. + * 0b011..SCK for this shared signal set comes from Flexcomm 3. + * 0b100..SCK for this shared signal set comes from Flexcomm 4. + * 0b101..SCK for this shared signal set comes from Flexcomm 5. + * 0b110..SCK for this shared signal set comes from Flexcomm 6. + * 0b111..SCK for this shared signal set comes from Flexcomm 7. + */ +#define SYSCTL_SHAREDCTRLSET_SHAREDSCKSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_SHAREDSCKSEL_SHIFT)) & SYSCTL_SHAREDCTRLSET_SHAREDSCKSEL_MASK) + +#define SYSCTL_SHAREDCTRLSET_SHAREDWSSEL_MASK (0x70U) +#define SYSCTL_SHAREDCTRLSET_SHAREDWSSEL_SHIFT (4U) +/*! SHAREDWSSEL - Selects the source for WS of this shared signal set. + * 0b000..WS for this shared signal set comes from Flexcomm 0. + * 0b001..WS for this shared signal set comes from Flexcomm 1. + * 0b010..WS for this shared signal set comes from Flexcomm 2. + * 0b011..WS for this shared signal set comes from Flexcomm 3. + * 0b100..WS for this shared signal set comes from Flexcomm 4. + * 0b101..WS for this shared signal set comes from Flexcomm 5. + * 0b110..WS for this shared signal set comes from Flexcomm 6. + * 0b111..WS for this shared signal set comes from Flexcomm 7. + */ +#define SYSCTL_SHAREDCTRLSET_SHAREDWSSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_SHAREDWSSEL_SHIFT)) & SYSCTL_SHAREDCTRLSET_SHAREDWSSEL_MASK) + +#define SYSCTL_SHAREDCTRLSET_SHAREDDATASEL_MASK (0x700U) +#define SYSCTL_SHAREDCTRLSET_SHAREDDATASEL_SHIFT (8U) +/*! SHAREDDATASEL - Selects the source for DATA input for this shared signal set. + * 0b000..DATA input for this shared signal set comes from Flexcomm 0. + * 0b001..DATA input for this shared signal set comes from Flexcomm 1. + * 0b010..DATA input for this shared signal set comes from Flexcomm 2. + * 0b011..DATA input for this shared signal set comes from Flexcomm 3. + * 0b100..DATA input for this shared signal set comes from Flexcomm 4. + * 0b101..DATA input for this shared signal set comes from Flexcomm 5. + * 0b110..DATA input for this shared signal set comes from Flexcomm 6. + * 0b111..DATA input for this shared signal set comes from Flexcomm 7. + */ +#define SYSCTL_SHAREDCTRLSET_SHAREDDATASEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_SHAREDDATASEL_SHIFT)) & SYSCTL_SHAREDCTRLSET_SHAREDDATASEL_MASK) + +#define SYSCTL_SHAREDCTRLSET_FC0DATAOUTEN_MASK (0x10000U) +#define SYSCTL_SHAREDCTRLSET_FC0DATAOUTEN_SHIFT (16U) +/*! FC0DATAOUTEN - Controls FC0 contribution to SHAREDDATAOUT for this shared set. + * 0b0..Data output from FC0 does not contribute to this shared set. + * 0b1..Data output from FC0 does contribute to this shared set. + */ +#define SYSCTL_SHAREDCTRLSET_FC0DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_FC0DATAOUTEN_SHIFT)) & SYSCTL_SHAREDCTRLSET_FC0DATAOUTEN_MASK) + +#define SYSCTL_SHAREDCTRLSET_FC1DATAOUTEN_MASK (0x20000U) +#define SYSCTL_SHAREDCTRLSET_FC1DATAOUTEN_SHIFT (17U) +/*! FC1DATAOUTEN - Controls FC1 contribution to SHAREDDATAOUT for this shared set. + * 0b0..Data output from FC1 does not contribute to this shared set. + * 0b1..Data output from FC1 does contribute to this shared set. + */ +#define SYSCTL_SHAREDCTRLSET_FC1DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_FC1DATAOUTEN_SHIFT)) & SYSCTL_SHAREDCTRLSET_FC1DATAOUTEN_MASK) + +#define SYSCTL_SHAREDCTRLSET_FC2DATAOUTEN_MASK (0x40000U) +#define SYSCTL_SHAREDCTRLSET_FC2DATAOUTEN_SHIFT (18U) +/*! FC2DATAOUTEN - Controls FC2 contribution to SHAREDDATAOUT for this shared set. + * 0b0..Data output from FC2 does not contribute to this shared set. + * 0b1..Data output from FC2 does contribute to this shared set. + */ +#define SYSCTL_SHAREDCTRLSET_FC2DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_FC2DATAOUTEN_SHIFT)) & SYSCTL_SHAREDCTRLSET_FC2DATAOUTEN_MASK) + +#define SYSCTL_SHAREDCTRLSET_FC4DATAOUTEN_MASK (0x100000U) +#define SYSCTL_SHAREDCTRLSET_FC4DATAOUTEN_SHIFT (20U) +/*! FC4DATAOUTEN - Controls FC4 contribution to SHAREDDATAOUT for this shared set. + * 0b0..Data output from FC4 does not contribute to this shared set. + * 0b1..Data output from FC4 does contribute to this shared set. + */ +#define SYSCTL_SHAREDCTRLSET_FC4DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_FC4DATAOUTEN_SHIFT)) & SYSCTL_SHAREDCTRLSET_FC4DATAOUTEN_MASK) + +#define SYSCTL_SHAREDCTRLSET_FC5DATAOUTEN_MASK (0x200000U) +#define SYSCTL_SHAREDCTRLSET_FC5DATAOUTEN_SHIFT (21U) +/*! FC5DATAOUTEN - Controls FC5 contribution to SHAREDDATAOUT for this shared set. + * 0b0..Data output from FC5 does not contribute to this shared set. + * 0b1..Data output from FC5 does contribute to this shared set. + */ +#define SYSCTL_SHAREDCTRLSET_FC5DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_FC5DATAOUTEN_SHIFT)) & SYSCTL_SHAREDCTRLSET_FC5DATAOUTEN_MASK) + +#define SYSCTL_SHAREDCTRLSET_FC6DATAOUTEN_MASK (0x400000U) +#define SYSCTL_SHAREDCTRLSET_FC6DATAOUTEN_SHIFT (22U) +/*! FC6DATAOUTEN - Controls FC6 contribution to SHAREDDATAOUT for this shared set. + * 0b0..Data output from FC6 does not contribute to this shared set. + * 0b1..Data output from FC6 does contribute to this shared set. + */ +#define SYSCTL_SHAREDCTRLSET_FC6DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_FC6DATAOUTEN_SHIFT)) & SYSCTL_SHAREDCTRLSET_FC6DATAOUTEN_MASK) + +#define SYSCTL_SHAREDCTRLSET_FC7DATAOUTEN_MASK (0x800000U) +#define SYSCTL_SHAREDCTRLSET_FC7DATAOUTEN_SHIFT (23U) +/*! FC7DATAOUTEN - Controls FC7 contribution to SHAREDDATAOUT for this shared set. + * 0b0..Data output from FC7 does not contribute to this shared set. + * 0b1..Data output from FC7 does contribute to this shared set. + */ +#define SYSCTL_SHAREDCTRLSET_FC7DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_FC7DATAOUTEN_SHIFT)) & SYSCTL_SHAREDCTRLSET_FC7DATAOUTEN_MASK) +/*! @} */ + +/* The count of SYSCTL_SHAREDCTRLSET */ +#define SYSCTL_SHAREDCTRLSET_COUNT (2U) + +/*! @name USB_HS_STATUS - Status register for USB HS */ +/*! @{ */ + +#define SYSCTL_USB_HS_STATUS_USBHS_3V_NOK_MASK (0x1U) +#define SYSCTL_USB_HS_STATUS_USBHS_3V_NOK_SHIFT (0U) +/*! USBHS_3V_NOK - USB_HS: Low voltage detection on 3.3V supply. + * 0b0..3v3 supply is good. + * 0b1..3v3 supply is too low. + */ +#define SYSCTL_USB_HS_STATUS_USBHS_3V_NOK(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_USB_HS_STATUS_USBHS_3V_NOK_SHIFT)) & SYSCTL_USB_HS_STATUS_USBHS_3V_NOK_MASK) +/*! @} */ + +/*! @name CODE_GRAY_LSB - CODE_GRAY LSB input Register */ +/*! @{ */ + +#define SYSCTL_CODE_GRAY_LSB_CODE_GRAY_LSB_MASK (0xFFFFFFFFU) +#define SYSCTL_CODE_GRAY_LSB_CODE_GRAY_LSB_SHIFT (0U) +/*! CODE_GRAY_LSB - Gray code (42bits) to be converted back to binary + */ +#define SYSCTL_CODE_GRAY_LSB_CODE_GRAY_LSB(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_CODE_GRAY_LSB_CODE_GRAY_LSB_SHIFT)) & SYSCTL_CODE_GRAY_LSB_CODE_GRAY_LSB_MASK) +/*! @} */ + +/*! @name CODE_GRAY_MSB - CODE_GRAY MSB input Register */ +/*! @{ */ + +#define SYSCTL_CODE_GRAY_MSB_CODE_GRAY_MSB_MASK (0x3FFU) +#define SYSCTL_CODE_GRAY_MSB_CODE_GRAY_MSB_SHIFT (0U) +/*! CODE_GRAY_MSB - Gray code (42bits) to be converted back to binary + */ +#define SYSCTL_CODE_GRAY_MSB_CODE_GRAY_MSB(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_CODE_GRAY_MSB_CODE_GRAY_MSB_SHIFT)) & SYSCTL_CODE_GRAY_MSB_CODE_GRAY_MSB_MASK) +/*! @} */ + +/*! @name CODE_BIN_LSB - CODE_BIN LSB output Register */ +/*! @{ */ + +#define SYSCTL_CODE_BIN_LSB_CODE_BIN_LSB_MASK (0xFFFFFFFFU) +#define SYSCTL_CODE_BIN_LSB_CODE_BIN_LSB_SHIFT (0U) +/*! CODE_BIN_LSB - Binary converted code (42bits) + */ +#define SYSCTL_CODE_BIN_LSB_CODE_BIN_LSB(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_CODE_BIN_LSB_CODE_BIN_LSB_SHIFT)) & SYSCTL_CODE_BIN_LSB_CODE_BIN_LSB_MASK) +/*! @} */ + +/*! @name CODE_BIN_MSB - CODE_BIN MSB output Register */ +/*! @{ */ + +#define SYSCTL_CODE_BIN_MSB_CODE_BIN_MSB_MASK (0x3FFU) +#define SYSCTL_CODE_BIN_MSB_CODE_BIN_MSB_SHIFT (0U) +/*! CODE_BIN_MSB - Binary converted code (42bits) + */ +#define SYSCTL_CODE_BIN_MSB_CODE_BIN_MSB(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_CODE_BIN_MSB_CODE_BIN_MSB_SHIFT)) & SYSCTL_CODE_BIN_MSB_CODE_BIN_MSB_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group SYSCTL_Register_Masks */ + + +/* SYSCTL - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral SYSCTL base address */ + #define SYSCTL_BASE (0x50023000u) + /** Peripheral SYSCTL base address */ + #define SYSCTL_BASE_NS (0x40023000u) + /** Peripheral SYSCTL base pointer */ + #define SYSCTL ((SYSCTL_Type *)SYSCTL_BASE) + /** Peripheral SYSCTL base pointer */ + #define SYSCTL_NS ((SYSCTL_Type *)SYSCTL_BASE_NS) + /** Array initializer of SYSCTL peripheral base addresses */ + #define SYSCTL_BASE_ADDRS { SYSCTL_BASE } + /** Array initializer of SYSCTL peripheral base pointers */ + #define SYSCTL_BASE_PTRS { SYSCTL } + /** Array initializer of SYSCTL peripheral base addresses */ + #define SYSCTL_BASE_ADDRS_NS { SYSCTL_BASE_NS } + /** Array initializer of SYSCTL peripheral base pointers */ + #define SYSCTL_BASE_PTRS_NS { SYSCTL_NS } +#else + /** Peripheral SYSCTL base address */ + #define SYSCTL_BASE (0x40023000u) + /** Peripheral SYSCTL base pointer */ + #define SYSCTL ((SYSCTL_Type *)SYSCTL_BASE) + /** Array initializer of SYSCTL peripheral base addresses */ + #define SYSCTL_BASE_ADDRS { SYSCTL_BASE } + /** Array initializer of SYSCTL peripheral base pointers */ + #define SYSCTL_BASE_PTRS { SYSCTL } +#endif + +/*! + * @} + */ /* end of group SYSCTL_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- USART Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USART_Peripheral_Access_Layer USART Peripheral Access Layer + * @{ + */ + +/** USART - Register Layout Typedef */ +typedef struct { + __IO uint32_t CFG; /**< USART Configuration register. Basic USART configuration settings that typically are not changed during operation., offset: 0x0 */ + __IO uint32_t CTL; /**< USART Control register. USART control settings that are more likely to change during operation., offset: 0x4 */ + __IO uint32_t STAT; /**< USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them., offset: 0x8 */ + __IO uint32_t INTENSET; /**< Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set., offset: 0xC */ + __O uint32_t INTENCLR; /**< Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared., offset: 0x10 */ + uint8_t RESERVED_0[12]; + __IO uint32_t BRG; /**< Baud Rate Generator register. 16-bit integer baud rate divisor value., offset: 0x20 */ + __I uint32_t INTSTAT; /**< Interrupt status register. Reflects interrupts that are currently enabled., offset: 0x24 */ + __IO uint32_t OSR; /**< Oversample selection register for asynchronous communication., offset: 0x28 */ + __IO uint32_t ADDR; /**< Address register for automatic address matching., offset: 0x2C */ + uint8_t RESERVED_1[3536]; + __IO uint32_t FIFOCFG; /**< FIFO configuration and enable register., offset: 0xE00 */ + __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */ + __IO uint32_t FIFOTRIG; /**< FIFO trigger settings for interrupt and DMA request., offset: 0xE08 */ + uint8_t RESERVED_2[4]; + __IO uint32_t FIFOINTENSET; /**< FIFO interrupt enable set (enable) and read register., offset: 0xE10 */ + __IO uint32_t FIFOINTENCLR; /**< FIFO interrupt enable clear (disable) and read register., offset: 0xE14 */ + __I uint32_t FIFOINTSTAT; /**< FIFO interrupt status register., offset: 0xE18 */ + uint8_t RESERVED_3[4]; + __O uint32_t FIFOWR; /**< FIFO write data., offset: 0xE20 */ + uint8_t RESERVED_4[12]; + __I uint32_t FIFORD; /**< FIFO read data., offset: 0xE30 */ + uint8_t RESERVED_5[12]; + __I uint32_t FIFORDNOPOP; /**< FIFO data read with no FIFO pop., offset: 0xE40 */ + uint8_t RESERVED_6[4]; + __I uint32_t FIFOSIZE; /**< FIFO size register, offset: 0xE48 */ + uint8_t RESERVED_7[432]; + __I uint32_t ID; /**< Peripheral identification register., offset: 0xFFC */ +} USART_Type; + +/* ---------------------------------------------------------------------------- + -- USART Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USART_Register_Masks USART Register Masks + * @{ + */ + +/*! @name CFG - USART Configuration register. Basic USART configuration settings that typically are not changed during operation. */ +/*! @{ */ + +#define USART_CFG_ENABLE_MASK (0x1U) +#define USART_CFG_ENABLE_SHIFT (0U) +/*! ENABLE - USART Enable. + * 0b0..Disabled. The USART is disabled and the internal state machine and counters are reset. While Enable = 0, + * all USART interrupts and DMA transfers are disabled. When Enable is set again, CFG and most other control + * bits remain unchanged. When re-enabled, the USART will immediately be ready to transmit because the + * transmitter has been reset and is therefore available. + * 0b1..Enabled. The USART is enabled for operation. + */ +#define USART_CFG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_ENABLE_SHIFT)) & USART_CFG_ENABLE_MASK) + +#define USART_CFG_DATALEN_MASK (0xCU) +#define USART_CFG_DATALEN_SHIFT (2U) +/*! DATALEN - Selects the data size for the USART. + * 0b00..7 bit Data length. + * 0b01..8 bit Data length. + * 0b10..9 bit data length. The 9th bit is commonly used for addressing in multidrop mode. See the ADDRDET bit in the CTL register. + * 0b11..Reserved. + */ +#define USART_CFG_DATALEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_DATALEN_SHIFT)) & USART_CFG_DATALEN_MASK) + +#define USART_CFG_PARITYSEL_MASK (0x30U) +#define USART_CFG_PARITYSEL_SHIFT (4U) +/*! PARITYSEL - Selects what type of parity is used by the USART. + * 0b00..No parity. + * 0b01..Reserved. + * 0b10..Even parity. Adds a bit to each character such that the number of 1s in a transmitted character is even, + * and the number of 1s in a received character is expected to be even. + * 0b11..Odd parity. Adds a bit to each character such that the number of 1s in a transmitted character is odd, + * and the number of 1s in a received character is expected to be odd. + */ +#define USART_CFG_PARITYSEL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_PARITYSEL_SHIFT)) & USART_CFG_PARITYSEL_MASK) + +#define USART_CFG_STOPLEN_MASK (0x40U) +#define USART_CFG_STOPLEN_SHIFT (6U) +/*! STOPLEN - Number of stop bits appended to transmitted data. Only a single stop bit is required for received data. + * 0b0..1 stop bit. + * 0b1..2 stop bits. This setting should only be used for asynchronous communication. + */ +#define USART_CFG_STOPLEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_STOPLEN_SHIFT)) & USART_CFG_STOPLEN_MASK) + +#define USART_CFG_MODE32K_MASK (0x80U) +#define USART_CFG_MODE32K_SHIFT (7U) +/*! MODE32K - Selects standard or 32 kHz clocking mode. + * 0b0..Disabled. USART uses standard clocking. + * 0b1..Enabled. USART uses the 32 kHz clock from the RTC oscillator as the clock source to the BRG, and uses a special bit clocking scheme. + */ +#define USART_CFG_MODE32K(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_MODE32K_SHIFT)) & USART_CFG_MODE32K_MASK) + +#define USART_CFG_LINMODE_MASK (0x100U) +#define USART_CFG_LINMODE_SHIFT (8U) +/*! LINMODE - LIN break mode enable. + * 0b0..Disabled. Break detect and generate is configured for normal operation. + * 0b1..Enabled. Break detect and generate is configured for LIN bus operation. + */ +#define USART_CFG_LINMODE(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_LINMODE_SHIFT)) & USART_CFG_LINMODE_MASK) + +#define USART_CFG_CTSEN_MASK (0x200U) +#define USART_CFG_CTSEN_SHIFT (9U) +/*! CTSEN - CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input + * pin, or from the USART's own RTS if loopback mode is enabled. + * 0b0..No flow control. The transmitter does not receive any automatic flow control signal. + * 0b1..Flow control enabled. The transmitter uses the CTS input (or RTS output in loopback mode) for flow control purposes. + */ +#define USART_CFG_CTSEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_CTSEN_SHIFT)) & USART_CFG_CTSEN_MASK) + +#define USART_CFG_SYNCEN_MASK (0x800U) +#define USART_CFG_SYNCEN_SHIFT (11U) +/*! SYNCEN - Selects synchronous or asynchronous operation. + * 0b0..Asynchronous mode. + * 0b1..Synchronous mode. + */ +#define USART_CFG_SYNCEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_SYNCEN_SHIFT)) & USART_CFG_SYNCEN_MASK) + +#define USART_CFG_CLKPOL_MASK (0x1000U) +#define USART_CFG_CLKPOL_SHIFT (12U) +/*! CLKPOL - Selects the clock polarity and sampling edge of received data in synchronous mode. + * 0b0..Falling edge. Un_RXD is sampled on the falling edge of SCLK. + * 0b1..Rising edge. Un_RXD is sampled on the rising edge of SCLK. + */ +#define USART_CFG_CLKPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_CLKPOL_SHIFT)) & USART_CFG_CLKPOL_MASK) + +#define USART_CFG_SYNCMST_MASK (0x4000U) +#define USART_CFG_SYNCMST_SHIFT (14U) +/*! SYNCMST - Synchronous mode Master select. + * 0b0..Slave. When synchronous mode is enabled, the USART is a slave. + * 0b1..Master. When synchronous mode is enabled, the USART is a master. + */ +#define USART_CFG_SYNCMST(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_SYNCMST_SHIFT)) & USART_CFG_SYNCMST_MASK) + +#define USART_CFG_LOOP_MASK (0x8000U) +#define USART_CFG_LOOP_SHIFT (15U) +/*! LOOP - Selects data loopback mode. + * 0b0..Normal operation. + * 0b1..Loopback mode. This provides a mechanism to perform diagnostic loopback testing for USART data. Serial + * data from the transmitter (Un_TXD) is connected internally to serial input of the receive (Un_RXD). Un_TXD + * and Un_RTS activity will also appear on external pins if these functions are configured to appear on device + * pins. The receiver RTS signal is also looped back to CTS and performs flow control if enabled by CTSEN. + */ +#define USART_CFG_LOOP(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_LOOP_SHIFT)) & USART_CFG_LOOP_MASK) + +#define USART_CFG_OETA_MASK (0x40000U) +#define USART_CFG_OETA_SHIFT (18U) +/*! OETA - Output Enable Turnaround time enable for RS-485 operation. + * 0b0..Disabled. If selected by OESEL, the Output Enable signal deasserted at the end of the last stop bit of a transmission. + * 0b1..Enabled. If selected by OESEL, the Output Enable signal remains asserted for one character time after the + * end of the last stop bit of a transmission. OE will also remain asserted if another transmit begins + * before it is deasserted. + */ +#define USART_CFG_OETA(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_OETA_SHIFT)) & USART_CFG_OETA_MASK) + +#define USART_CFG_AUTOADDR_MASK (0x80000U) +#define USART_CFG_AUTOADDR_SHIFT (19U) +/*! AUTOADDR - Automatic Address matching enable. + * 0b0..Disabled. When addressing is enabled by ADDRDET, address matching is done by software. This provides the + * possibility of versatile addressing (e.g. respond to more than one address). + * 0b1..Enabled. When addressing is enabled by ADDRDET, address matching is done by hardware, using the value in + * the ADDR register as the address to match. + */ +#define USART_CFG_AUTOADDR(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_AUTOADDR_SHIFT)) & USART_CFG_AUTOADDR_MASK) + +#define USART_CFG_OESEL_MASK (0x100000U) +#define USART_CFG_OESEL_SHIFT (20U) +/*! OESEL - Output Enable Select. + * 0b0..Standard. The RTS signal is used as the standard flow control function. + * 0b1..RS-485. The RTS signal configured to provide an output enable signal to control an RS-485 transceiver. + */ +#define USART_CFG_OESEL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_OESEL_SHIFT)) & USART_CFG_OESEL_MASK) + +#define USART_CFG_OEPOL_MASK (0x200000U) +#define USART_CFG_OEPOL_SHIFT (21U) +/*! OEPOL - Output Enable Polarity. + * 0b0..Low. If selected by OESEL, the output enable is active low. + * 0b1..High. If selected by OESEL, the output enable is active high. + */ +#define USART_CFG_OEPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_OEPOL_SHIFT)) & USART_CFG_OEPOL_MASK) + +#define USART_CFG_RXPOL_MASK (0x400000U) +#define USART_CFG_RXPOL_SHIFT (22U) +/*! RXPOL - Receive data polarity. + * 0b0..Standard. The RX signal is used as it arrives from the pin. This means that the RX rest value is 1, start + * bit is 0, data is not inverted, and the stop bit is 1. + * 0b1..Inverted. The RX signal is inverted before being used by the USART. This means that the RX rest value is + * 0, start bit is 1, data is inverted, and the stop bit is 0. + */ +#define USART_CFG_RXPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_RXPOL_SHIFT)) & USART_CFG_RXPOL_MASK) + +#define USART_CFG_TXPOL_MASK (0x800000U) +#define USART_CFG_TXPOL_SHIFT (23U) +/*! TXPOL - Transmit data polarity. + * 0b0..Standard. The TX signal is sent out without change. This means that the TX rest value is 1, start bit is + * 0, data is not inverted, and the stop bit is 1. + * 0b1..Inverted. The TX signal is inverted by the USART before being sent out. This means that the TX rest value + * is 0, start bit is 1, data is inverted, and the stop bit is 0. + */ +#define USART_CFG_TXPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_TXPOL_SHIFT)) & USART_CFG_TXPOL_MASK) +/*! @} */ + +/*! @name CTL - USART Control register. USART control settings that are more likely to change during operation. */ +/*! @{ */ + +#define USART_CTL_TXBRKEN_MASK (0x2U) +#define USART_CTL_TXBRKEN_SHIFT (1U) +/*! TXBRKEN - Break Enable. + * 0b0..Normal operation. + * 0b1..Continuous break. Continuous break is sent immediately when this bit is set, and remains until this bit + * is cleared. A break may be sent without danger of corrupting any currently transmitting character if the + * transmitter is first disabled (TXDIS in CTL is set) and then waiting for the transmitter to be disabled + * (TXDISINT in STAT = 1) before writing 1 to TXBRKEN. + */ +#define USART_CTL_TXBRKEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_TXBRKEN_SHIFT)) & USART_CTL_TXBRKEN_MASK) + +#define USART_CTL_ADDRDET_MASK (0x4U) +#define USART_CTL_ADDRDET_SHIFT (2U) +/*! ADDRDET - Enable address detect mode. + * 0b0..Disabled. The USART presents all incoming data. + * 0b1..Enabled. The USART receiver ignores incoming data that does not have the most significant bit of the data + * (typically the 9th bit) = 1. When the data MSB bit = 1, the receiver treats the incoming data normally, + * generating a received data interrupt. Software can then check the data to see if this is an address that + * should be handled. If it is, the ADDRDET bit is cleared by software and further incoming data is handled + * normally. + */ +#define USART_CTL_ADDRDET(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_ADDRDET_SHIFT)) & USART_CTL_ADDRDET_MASK) + +#define USART_CTL_TXDIS_MASK (0x40U) +#define USART_CTL_TXDIS_SHIFT (6U) +/*! TXDIS - Transmit Disable. + * 0b0..Not disabled. USART transmitter is not disabled. + * 0b1..Disabled. USART transmitter is disabled after any character currently being transmitted is complete. This + * feature can be used to facilitate software flow control. + */ +#define USART_CTL_TXDIS(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_TXDIS_SHIFT)) & USART_CTL_TXDIS_MASK) + +#define USART_CTL_CC_MASK (0x100U) +#define USART_CTL_CC_SHIFT (8U) +/*! CC - Continuous Clock generation. By default, SCLK is only output while data is being transmitted in synchronous mode. + * 0b0..Clock on character. In synchronous mode, SCLK cycles only when characters are being sent on Un_TXD or to + * complete a character that is being received. + * 0b1..Continuous clock. SCLK runs continuously in synchronous mode, allowing characters to be received on + * Un_RxD independently from transmission on Un_TXD). + */ +#define USART_CTL_CC(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_CC_SHIFT)) & USART_CTL_CC_MASK) + +#define USART_CTL_CLRCCONRX_MASK (0x200U) +#define USART_CTL_CLRCCONRX_SHIFT (9U) +/*! CLRCCONRX - Clear Continuous Clock. + * 0b0..No effect. No effect on the CC bit. + * 0b1..Auto-clear. The CC bit is automatically cleared when a complete character has been received. This bit is cleared at the same time. + */ +#define USART_CTL_CLRCCONRX(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_CLRCCONRX_SHIFT)) & USART_CTL_CLRCCONRX_MASK) + +#define USART_CTL_AUTOBAUD_MASK (0x10000U) +#define USART_CTL_AUTOBAUD_SHIFT (16U) +/*! AUTOBAUD - Autobaud enable. + * 0b0..Disabled. USART is in normal operating mode. + * 0b1..Enabled. USART is in autobaud mode. This bit should only be set when the USART receiver is idle. The + * first start bit of RX is measured and used the update the BRG register to match the received data rate. + * AUTOBAUD is cleared once this process is complete, or if there is an AERR. + */ +#define USART_CTL_AUTOBAUD(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_AUTOBAUD_SHIFT)) & USART_CTL_AUTOBAUD_MASK) +/*! @} */ + +/*! @name STAT - USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them. */ +/*! @{ */ + +#define USART_STAT_RXIDLE_MASK (0x2U) +#define USART_STAT_RXIDLE_SHIFT (1U) +/*! RXIDLE - Receiver Idle. When 0, indicates that the receiver is currently in the process of + * receiving data. When 1, indicates that the receiver is not currently in the process of receiving + * data. + */ +#define USART_STAT_RXIDLE(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXIDLE_SHIFT)) & USART_STAT_RXIDLE_MASK) + +#define USART_STAT_TXIDLE_MASK (0x8U) +#define USART_STAT_TXIDLE_SHIFT (3U) +/*! TXIDLE - Transmitter Idle. When 0, indicates that the transmitter is currently in the process of + * sending data.When 1, indicate that the transmitter is not currently in the process of sending + * data. + */ +#define USART_STAT_TXIDLE(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_TXIDLE_SHIFT)) & USART_STAT_TXIDLE_MASK) + +#define USART_STAT_CTS_MASK (0x10U) +#define USART_STAT_CTS_SHIFT (4U) +/*! CTS - This bit reflects the current state of the CTS signal, regardless of the setting of the + * CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode + * is enabled. + */ +#define USART_STAT_CTS(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_CTS_SHIFT)) & USART_STAT_CTS_MASK) + +#define USART_STAT_DELTACTS_MASK (0x20U) +#define USART_STAT_DELTACTS_SHIFT (5U) +/*! DELTACTS - This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software. + */ +#define USART_STAT_DELTACTS(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_DELTACTS_SHIFT)) & USART_STAT_DELTACTS_MASK) + +#define USART_STAT_TXDISSTAT_MASK (0x40U) +#define USART_STAT_TXDISSTAT_SHIFT (6U) +/*! TXDISSTAT - Transmitter Disabled Status flag. When 1, this bit indicates that the USART + * transmitter is fully idle after being disabled via the TXDIS bit in the CFG register (TXDIS = 1). + */ +#define USART_STAT_TXDISSTAT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_TXDISSTAT_SHIFT)) & USART_STAT_TXDISSTAT_MASK) + +#define USART_STAT_RXBRK_MASK (0x400U) +#define USART_STAT_RXBRK_SHIFT (10U) +/*! RXBRK - Received Break. This bit reflects the current state of the receiver break detection + * logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also + * be set when this condition occurs because the stop bit(s) for the character would be missing. + * RXBRK is cleared when the Un_RXD pin goes high. + */ +#define USART_STAT_RXBRK(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXBRK_SHIFT)) & USART_STAT_RXBRK_MASK) + +#define USART_STAT_DELTARXBRK_MASK (0x800U) +#define USART_STAT_DELTARXBRK_SHIFT (11U) +/*! DELTARXBRK - This bit is set when a change in the state of receiver break detection occurs. Cleared by software. + */ +#define USART_STAT_DELTARXBRK(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_DELTARXBRK_SHIFT)) & USART_STAT_DELTARXBRK_MASK) + +#define USART_STAT_START_MASK (0x1000U) +#define USART_STAT_START_SHIFT (12U) +/*! START - This bit is set when a start is detected on the receiver input. Its purpose is primarily + * to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. + * Cleared by software. + */ +#define USART_STAT_START(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_START_SHIFT)) & USART_STAT_START_MASK) + +#define USART_STAT_FRAMERRINT_MASK (0x2000U) +#define USART_STAT_FRAMERRINT_SHIFT (13U) +/*! FRAMERRINT - Framing Error interrupt flag. This flag is set when a character is received with a + * missing stop bit at the expected location. This could be an indication of a baud rate or + * configuration mismatch with the transmitting source. + */ +#define USART_STAT_FRAMERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_FRAMERRINT_SHIFT)) & USART_STAT_FRAMERRINT_MASK) + +#define USART_STAT_PARITYERRINT_MASK (0x4000U) +#define USART_STAT_PARITYERRINT_SHIFT (14U) +/*! PARITYERRINT - Parity Error interrupt flag. This flag is set when a parity error is detected in a received character. + */ +#define USART_STAT_PARITYERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_PARITYERRINT_SHIFT)) & USART_STAT_PARITYERRINT_MASK) + +#define USART_STAT_RXNOISEINT_MASK (0x8000U) +#define USART_STAT_RXNOISEINT_SHIFT (15U) +/*! RXNOISEINT - Received Noise interrupt flag. Three samples of received data are taken in order to + * determine the value of each received data bit, except in synchronous mode. This acts as a + * noise filter if one sample disagrees. This flag is set when a received data bit contains one + * disagreeing sample. This could indicate line noise, a baud rate or character format mismatch, or + * loss of synchronization during data reception. + */ +#define USART_STAT_RXNOISEINT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXNOISEINT_SHIFT)) & USART_STAT_RXNOISEINT_MASK) + +#define USART_STAT_ABERR_MASK (0x10000U) +#define USART_STAT_ABERR_SHIFT (16U) +/*! ABERR - Auto baud Error. An auto baud error can occur if the BRG counts to its limit before the + * end of the start bit that is being measured, essentially an auto baud time-out. + */ +#define USART_STAT_ABERR(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_ABERR_SHIFT)) & USART_STAT_ABERR_MASK) +/*! @} */ + +/*! @name INTENSET - Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set. */ +/*! @{ */ + +#define USART_INTENSET_TXIDLEEN_MASK (0x8U) +#define USART_INTENSET_TXIDLEEN_SHIFT (3U) +/*! TXIDLEEN - When 1, enables an interrupt when the transmitter becomes idle (TXIDLE = 1). + */ +#define USART_INTENSET_TXIDLEEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_TXIDLEEN_SHIFT)) & USART_INTENSET_TXIDLEEN_MASK) + +#define USART_INTENSET_DELTACTSEN_MASK (0x20U) +#define USART_INTENSET_DELTACTSEN_SHIFT (5U) +/*! DELTACTSEN - When 1, enables an interrupt when there is a change in the state of the CTS input. + */ +#define USART_INTENSET_DELTACTSEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_DELTACTSEN_SHIFT)) & USART_INTENSET_DELTACTSEN_MASK) + +#define USART_INTENSET_TXDISEN_MASK (0x40U) +#define USART_INTENSET_TXDISEN_SHIFT (6U) +/*! TXDISEN - When 1, enables an interrupt when the transmitter is fully disabled as indicated by + * the TXDISINT flag in STAT. See description of the TXDISINT bit for details. + */ +#define USART_INTENSET_TXDISEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_TXDISEN_SHIFT)) & USART_INTENSET_TXDISEN_MASK) + +#define USART_INTENSET_DELTARXBRKEN_MASK (0x800U) +#define USART_INTENSET_DELTARXBRKEN_SHIFT (11U) +/*! DELTARXBRKEN - When 1, enables an interrupt when a change of state has occurred in the detection + * of a received break condition (break condition asserted or deasserted). + */ +#define USART_INTENSET_DELTARXBRKEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_DELTARXBRKEN_SHIFT)) & USART_INTENSET_DELTARXBRKEN_MASK) + +#define USART_INTENSET_STARTEN_MASK (0x1000U) +#define USART_INTENSET_STARTEN_SHIFT (12U) +/*! STARTEN - When 1, enables an interrupt when a received start bit has been detected. + */ +#define USART_INTENSET_STARTEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_STARTEN_SHIFT)) & USART_INTENSET_STARTEN_MASK) + +#define USART_INTENSET_FRAMERREN_MASK (0x2000U) +#define USART_INTENSET_FRAMERREN_SHIFT (13U) +/*! FRAMERREN - When 1, enables an interrupt when a framing error has been detected. + */ +#define USART_INTENSET_FRAMERREN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_FRAMERREN_SHIFT)) & USART_INTENSET_FRAMERREN_MASK) + +#define USART_INTENSET_PARITYERREN_MASK (0x4000U) +#define USART_INTENSET_PARITYERREN_SHIFT (14U) +/*! PARITYERREN - When 1, enables an interrupt when a parity error has been detected. + */ +#define USART_INTENSET_PARITYERREN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_PARITYERREN_SHIFT)) & USART_INTENSET_PARITYERREN_MASK) + +#define USART_INTENSET_RXNOISEEN_MASK (0x8000U) +#define USART_INTENSET_RXNOISEEN_SHIFT (15U) +/*! RXNOISEEN - When 1, enables an interrupt when noise is detected. See description of the RXNOISEINT bit in Table 354. + */ +#define USART_INTENSET_RXNOISEEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_RXNOISEEN_SHIFT)) & USART_INTENSET_RXNOISEEN_MASK) + +#define USART_INTENSET_ABERREN_MASK (0x10000U) +#define USART_INTENSET_ABERREN_SHIFT (16U) +/*! ABERREN - When 1, enables an interrupt when an auto baud error occurs. + */ +#define USART_INTENSET_ABERREN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_ABERREN_SHIFT)) & USART_INTENSET_ABERREN_MASK) +/*! @} */ + +/*! @name INTENCLR - Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared. */ +/*! @{ */ + +#define USART_INTENCLR_TXIDLECLR_MASK (0x8U) +#define USART_INTENCLR_TXIDLECLR_SHIFT (3U) +/*! TXIDLECLR - Writing 1 clears the corresponding bit in the INTENSET register. + */ +#define USART_INTENCLR_TXIDLECLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_TXIDLECLR_SHIFT)) & USART_INTENCLR_TXIDLECLR_MASK) + +#define USART_INTENCLR_DELTACTSCLR_MASK (0x20U) +#define USART_INTENCLR_DELTACTSCLR_SHIFT (5U) +/*! DELTACTSCLR - Writing 1 clears the corresponding bit in the INTENSET register. + */ +#define USART_INTENCLR_DELTACTSCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_DELTACTSCLR_SHIFT)) & USART_INTENCLR_DELTACTSCLR_MASK) + +#define USART_INTENCLR_TXDISCLR_MASK (0x40U) +#define USART_INTENCLR_TXDISCLR_SHIFT (6U) +/*! TXDISCLR - Writing 1 clears the corresponding bit in the INTENSET register. + */ +#define USART_INTENCLR_TXDISCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_TXDISCLR_SHIFT)) & USART_INTENCLR_TXDISCLR_MASK) + +#define USART_INTENCLR_DELTARXBRKCLR_MASK (0x800U) +#define USART_INTENCLR_DELTARXBRKCLR_SHIFT (11U) +/*! DELTARXBRKCLR - Writing 1 clears the corresponding bit in the INTENSET register. + */ +#define USART_INTENCLR_DELTARXBRKCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_DELTARXBRKCLR_SHIFT)) & USART_INTENCLR_DELTARXBRKCLR_MASK) + +#define USART_INTENCLR_STARTCLR_MASK (0x1000U) +#define USART_INTENCLR_STARTCLR_SHIFT (12U) +/*! STARTCLR - Writing 1 clears the corresponding bit in the INTENSET register. + */ +#define USART_INTENCLR_STARTCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_STARTCLR_SHIFT)) & USART_INTENCLR_STARTCLR_MASK) + +#define USART_INTENCLR_FRAMERRCLR_MASK (0x2000U) +#define USART_INTENCLR_FRAMERRCLR_SHIFT (13U) +/*! FRAMERRCLR - Writing 1 clears the corresponding bit in the INTENSET register. + */ +#define USART_INTENCLR_FRAMERRCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_FRAMERRCLR_SHIFT)) & USART_INTENCLR_FRAMERRCLR_MASK) + +#define USART_INTENCLR_PARITYERRCLR_MASK (0x4000U) +#define USART_INTENCLR_PARITYERRCLR_SHIFT (14U) +/*! PARITYERRCLR - Writing 1 clears the corresponding bit in the INTENSET register. + */ +#define USART_INTENCLR_PARITYERRCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_PARITYERRCLR_SHIFT)) & USART_INTENCLR_PARITYERRCLR_MASK) + +#define USART_INTENCLR_RXNOISECLR_MASK (0x8000U) +#define USART_INTENCLR_RXNOISECLR_SHIFT (15U) +/*! RXNOISECLR - Writing 1 clears the corresponding bit in the INTENSET register. + */ +#define USART_INTENCLR_RXNOISECLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_RXNOISECLR_SHIFT)) & USART_INTENCLR_RXNOISECLR_MASK) + +#define USART_INTENCLR_ABERRCLR_MASK (0x10000U) +#define USART_INTENCLR_ABERRCLR_SHIFT (16U) +/*! ABERRCLR - Writing 1 clears the corresponding bit in the INTENSET register. + */ +#define USART_INTENCLR_ABERRCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_ABERRCLR_SHIFT)) & USART_INTENCLR_ABERRCLR_MASK) +/*! @} */ + +/*! @name BRG - Baud Rate Generator register. 16-bit integer baud rate divisor value. */ +/*! @{ */ + +#define USART_BRG_BRGVAL_MASK (0xFFFFU) +#define USART_BRG_BRGVAL_SHIFT (0U) +/*! BRGVAL - This value is used to divide the USART input clock to determine the baud rate, based on + * the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is + * divided by 2 before use by the USART function. 2 = FCLK is divided by 3 before use by the USART + * function. 0xFFFF = FCLK is divided by 65,536 before use by the USART function. + */ +#define USART_BRG_BRGVAL(x) (((uint32_t)(((uint32_t)(x)) << USART_BRG_BRGVAL_SHIFT)) & USART_BRG_BRGVAL_MASK) +/*! @} */ + +/*! @name INTSTAT - Interrupt status register. Reflects interrupts that are currently enabled. */ +/*! @{ */ + +#define USART_INTSTAT_TXIDLE_MASK (0x8U) +#define USART_INTSTAT_TXIDLE_SHIFT (3U) +/*! TXIDLE - Transmitter Idle status. + */ +#define USART_INTSTAT_TXIDLE(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_TXIDLE_SHIFT)) & USART_INTSTAT_TXIDLE_MASK) + +#define USART_INTSTAT_DELTACTS_MASK (0x20U) +#define USART_INTSTAT_DELTACTS_SHIFT (5U) +/*! DELTACTS - This bit is set when a change in the state of the CTS input is detected. + */ +#define USART_INTSTAT_DELTACTS(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_DELTACTS_SHIFT)) & USART_INTSTAT_DELTACTS_MASK) + +#define USART_INTSTAT_TXDISINT_MASK (0x40U) +#define USART_INTSTAT_TXDISINT_SHIFT (6U) +/*! TXDISINT - Transmitter Disabled Interrupt flag. + */ +#define USART_INTSTAT_TXDISINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_TXDISINT_SHIFT)) & USART_INTSTAT_TXDISINT_MASK) + +#define USART_INTSTAT_DELTARXBRK_MASK (0x800U) +#define USART_INTSTAT_DELTARXBRK_SHIFT (11U) +/*! DELTARXBRK - This bit is set when a change in the state of receiver break detection occurs. + */ +#define USART_INTSTAT_DELTARXBRK(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_DELTARXBRK_SHIFT)) & USART_INTSTAT_DELTARXBRK_MASK) + +#define USART_INTSTAT_START_MASK (0x1000U) +#define USART_INTSTAT_START_SHIFT (12U) +/*! START - This bit is set when a start is detected on the receiver input. + */ +#define USART_INTSTAT_START(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_START_SHIFT)) & USART_INTSTAT_START_MASK) + +#define USART_INTSTAT_FRAMERRINT_MASK (0x2000U) +#define USART_INTSTAT_FRAMERRINT_SHIFT (13U) +/*! FRAMERRINT - Framing Error interrupt flag. + */ +#define USART_INTSTAT_FRAMERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_FRAMERRINT_SHIFT)) & USART_INTSTAT_FRAMERRINT_MASK) + +#define USART_INTSTAT_PARITYERRINT_MASK (0x4000U) +#define USART_INTSTAT_PARITYERRINT_SHIFT (14U) +/*! PARITYERRINT - Parity Error interrupt flag. + */ +#define USART_INTSTAT_PARITYERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_PARITYERRINT_SHIFT)) & USART_INTSTAT_PARITYERRINT_MASK) + +#define USART_INTSTAT_RXNOISEINT_MASK (0x8000U) +#define USART_INTSTAT_RXNOISEINT_SHIFT (15U) +/*! RXNOISEINT - Received Noise interrupt flag. + */ +#define USART_INTSTAT_RXNOISEINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_RXNOISEINT_SHIFT)) & USART_INTSTAT_RXNOISEINT_MASK) + +#define USART_INTSTAT_ABERRINT_MASK (0x10000U) +#define USART_INTSTAT_ABERRINT_SHIFT (16U) +/*! ABERRINT - Auto baud Error Interrupt flag. + */ +#define USART_INTSTAT_ABERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_ABERRINT_SHIFT)) & USART_INTSTAT_ABERRINT_MASK) +/*! @} */ + +/*! @name OSR - Oversample selection register for asynchronous communication. */ +/*! @{ */ + +#define USART_OSR_OSRVAL_MASK (0xFU) +#define USART_OSR_OSRVAL_SHIFT (0U) +/*! OSRVAL - Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 function clocks are used to + * transmit and receive each data bit. 0x5 = 6 function clocks are used to transmit and receive + * each data bit. 0xF= 16 function clocks are used to transmit and receive each data bit. + */ +#define USART_OSR_OSRVAL(x) (((uint32_t)(((uint32_t)(x)) << USART_OSR_OSRVAL_SHIFT)) & USART_OSR_OSRVAL_MASK) +/*! @} */ + +/*! @name ADDR - Address register for automatic address matching. */ +/*! @{ */ + +#define USART_ADDR_ADDRESS_MASK (0xFFU) +#define USART_ADDR_ADDRESS_SHIFT (0U) +/*! ADDRESS - 8-bit address used with automatic address matching. Used when address detection is + * enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1). + */ +#define USART_ADDR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << USART_ADDR_ADDRESS_SHIFT)) & USART_ADDR_ADDRESS_MASK) +/*! @} */ + +/*! @name FIFOCFG - FIFO configuration and enable register. */ +/*! @{ */ + +#define USART_FIFOCFG_ENABLETX_MASK (0x1U) +#define USART_FIFOCFG_ENABLETX_SHIFT (0U) +/*! ENABLETX - Enable the transmit FIFO. + * 0b0..The transmit FIFO is not enabled. + * 0b1..The transmit FIFO is enabled. + */ +#define USART_FIFOCFG_ENABLETX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_ENABLETX_SHIFT)) & USART_FIFOCFG_ENABLETX_MASK) + +#define USART_FIFOCFG_ENABLERX_MASK (0x2U) +#define USART_FIFOCFG_ENABLERX_SHIFT (1U) +/*! ENABLERX - Enable the receive FIFO. + * 0b0..The receive FIFO is not enabled. + * 0b1..The receive FIFO is enabled. + */ +#define USART_FIFOCFG_ENABLERX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_ENABLERX_SHIFT)) & USART_FIFOCFG_ENABLERX_MASK) + +#define USART_FIFOCFG_SIZE_MASK (0x30U) +#define USART_FIFOCFG_SIZE_SHIFT (4U) +/*! SIZE - FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 + * entries of 8 bits. 0x1, 0x2, 0x3 = not applicable to USART. + */ +#define USART_FIFOCFG_SIZE(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_SIZE_SHIFT)) & USART_FIFOCFG_SIZE_MASK) + +#define USART_FIFOCFG_DMATX_MASK (0x1000U) +#define USART_FIFOCFG_DMATX_SHIFT (12U) +/*! DMATX - DMA configuration for transmit. + * 0b0..DMA is not used for the transmit function. + * 0b1..Trigger DMA for the transmit function if the FIFO is not full. Generally, data interrupts would be disabled if DMA is enabled. + */ +#define USART_FIFOCFG_DMATX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_DMATX_SHIFT)) & USART_FIFOCFG_DMATX_MASK) + +#define USART_FIFOCFG_DMARX_MASK (0x2000U) +#define USART_FIFOCFG_DMARX_SHIFT (13U) +/*! DMARX - DMA configuration for receive. + * 0b0..DMA is not used for the receive function. + * 0b1..Trigger DMA for the receive function if the FIFO is not empty. Generally, data interrupts would be disabled if DMA is enabled. + */ +#define USART_FIFOCFG_DMARX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_DMARX_SHIFT)) & USART_FIFOCFG_DMARX_MASK) + +#define USART_FIFOCFG_WAKETX_MASK (0x4000U) +#define USART_FIFOCFG_WAKETX_SHIFT (14U) +/*! WAKETX - Wake-up for transmit FIFO level. This allows the device to be woken from reduced power + * modes (up to power-down, as long as the peripheral function works in that power mode) without + * enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The + * CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware + * Wake-up control register. + * 0b0..Only enabled interrupts will wake up the device form reduced power modes. + * 0b1..A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by TXLVL in + * FIFOTRIG, even when the TXLVL interrupt is not enabled. + */ +#define USART_FIFOCFG_WAKETX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_WAKETX_SHIFT)) & USART_FIFOCFG_WAKETX_MASK) + +#define USART_FIFOCFG_WAKERX_MASK (0x8000U) +#define USART_FIFOCFG_WAKERX_SHIFT (15U) +/*! WAKERX - Wake-up for receive FIFO level. This allows the device to be woken from reduced power + * modes (up to power-down, as long as the peripheral function works in that power mode) without + * enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The + * CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware + * Wake-up control register. + * 0b0..Only enabled interrupts will wake up the device form reduced power modes. + * 0b1..A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by RXLVL in + * FIFOTRIG, even when the RXLVL interrupt is not enabled. + */ +#define USART_FIFOCFG_WAKERX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_WAKERX_SHIFT)) & USART_FIFOCFG_WAKERX_MASK) + +#define USART_FIFOCFG_EMPTYTX_MASK (0x10000U) +#define USART_FIFOCFG_EMPTYTX_SHIFT (16U) +/*! EMPTYTX - Empty command for the transmit FIFO. When a 1 is written to this bit, the TX FIFO is emptied. + */ +#define USART_FIFOCFG_EMPTYTX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_EMPTYTX_SHIFT)) & USART_FIFOCFG_EMPTYTX_MASK) + +#define USART_FIFOCFG_EMPTYRX_MASK (0x20000U) +#define USART_FIFOCFG_EMPTYRX_SHIFT (17U) +/*! EMPTYRX - Empty command for the receive FIFO. When a 1 is written to this bit, the RX FIFO is emptied. + */ +#define USART_FIFOCFG_EMPTYRX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_EMPTYRX_SHIFT)) & USART_FIFOCFG_EMPTYRX_MASK) +/*! @} */ + +/*! @name FIFOSTAT - FIFO status register. */ +/*! @{ */ + +#define USART_FIFOSTAT_TXERR_MASK (0x1U) +#define USART_FIFOSTAT_TXERR_SHIFT (0U) +/*! TXERR - TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow + * caused by pushing data into a full FIFO, or by an underflow if the FIFO is empty when data is + * needed. Cleared by writing a 1 to this bit. + */ +#define USART_FIFOSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXERR_SHIFT)) & USART_FIFOSTAT_TXERR_MASK) + +#define USART_FIFOSTAT_RXERR_MASK (0x2U) +#define USART_FIFOSTAT_RXERR_SHIFT (1U) +/*! RXERR - RX FIFO error. Will be set if a receive FIFO overflow occurs, caused by software or DMA + * not emptying the FIFO fast enough. Cleared by writing a 1 to this bit. + */ +#define USART_FIFOSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXERR_SHIFT)) & USART_FIFOSTAT_RXERR_MASK) + +#define USART_FIFOSTAT_PERINT_MASK (0x8U) +#define USART_FIFOSTAT_PERINT_SHIFT (3U) +/*! PERINT - Peripheral interrupt. When 1, this indicates that the peripheral function has asserted + * an interrupt. The details can be found by reading the peripheral's STAT register. + */ +#define USART_FIFOSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_PERINT_SHIFT)) & USART_FIFOSTAT_PERINT_MASK) + +#define USART_FIFOSTAT_TXEMPTY_MASK (0x10U) +#define USART_FIFOSTAT_TXEMPTY_SHIFT (4U) +/*! TXEMPTY - Transmit FIFO empty. When 1, the transmit FIFO is empty. The peripheral may still be processing the last piece of data. + */ +#define USART_FIFOSTAT_TXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXEMPTY_SHIFT)) & USART_FIFOSTAT_TXEMPTY_MASK) + +#define USART_FIFOSTAT_TXNOTFULL_MASK (0x20U) +#define USART_FIFOSTAT_TXNOTFULL_SHIFT (5U) +/*! TXNOTFULL - Transmit FIFO not full. When 1, the transmit FIFO is not full, so more data can be + * written. When 0, the transmit FIFO is full and another write would cause it to overflow. + */ +#define USART_FIFOSTAT_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXNOTFULL_SHIFT)) & USART_FIFOSTAT_TXNOTFULL_MASK) + +#define USART_FIFOSTAT_RXNOTEMPTY_MASK (0x40U) +#define USART_FIFOSTAT_RXNOTEMPTY_SHIFT (6U) +/*! RXNOTEMPTY - Receive FIFO not empty. When 1, the receive FIFO is not empty, so data can be read. When 0, the receive FIFO is empty. + */ +#define USART_FIFOSTAT_RXNOTEMPTY(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXNOTEMPTY_SHIFT)) & USART_FIFOSTAT_RXNOTEMPTY_MASK) + +#define USART_FIFOSTAT_RXFULL_MASK (0x80U) +#define USART_FIFOSTAT_RXFULL_SHIFT (7U) +/*! RXFULL - Receive FIFO full. When 1, the receive FIFO is full. Data needs to be read out to + * prevent the peripheral from causing an overflow. + */ +#define USART_FIFOSTAT_RXFULL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXFULL_SHIFT)) & USART_FIFOSTAT_RXFULL_MASK) + +#define USART_FIFOSTAT_TXLVL_MASK (0x1F00U) +#define USART_FIFOSTAT_TXLVL_SHIFT (8U) +/*! TXLVL - Transmit FIFO current level. A 0 means the TX FIFO is currently empty, and the TXEMPTY + * and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at + * the point where the read occurs. If the TX FIFO is full, the TXEMPTY and TXNOTFULL flags will be + * 0. + */ +#define USART_FIFOSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXLVL_SHIFT)) & USART_FIFOSTAT_TXLVL_MASK) + +#define USART_FIFOSTAT_RXLVL_MASK (0x1F0000U) +#define USART_FIFOSTAT_RXLVL_SHIFT (16U) +/*! RXLVL - Receive FIFO current level. A 0 means the RX FIFO is currently empty, and the RXFULL and + * RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the + * point where the read occurs. If the RX FIFO is full, the RXFULL and RXNOTEMPTY flags will be + * 1. + */ +#define USART_FIFOSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXLVL_SHIFT)) & USART_FIFOSTAT_RXLVL_MASK) +/*! @} */ + +/*! @name FIFOTRIG - FIFO trigger settings for interrupt and DMA request. */ +/*! @{ */ + +#define USART_FIFOTRIG_TXLVLENA_MASK (0x1U) +#define USART_FIFOTRIG_TXLVLENA_SHIFT (0U) +/*! TXLVLENA - Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled + * in FIFOINTENSET, or a DMA trigger if DMATX in FIFOCFG is set. + * 0b0..Transmit FIFO level does not generate a FIFO level trigger. + * 0b1..An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL field in this register. + */ +#define USART_FIFOTRIG_TXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_TXLVLENA_SHIFT)) & USART_FIFOTRIG_TXLVLENA_MASK) + +#define USART_FIFOTRIG_RXLVLENA_MASK (0x2U) +#define USART_FIFOTRIG_RXLVLENA_SHIFT (1U) +/*! RXLVLENA - Receive FIFO level trigger enable. This trigger will become an interrupt if enabled + * in FIFOINTENSET, or a DMA trigger if DMARX in FIFOCFG is set. + * 0b0..Receive FIFO level does not generate a FIFO level trigger. + * 0b1..An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL field in this register. + */ +#define USART_FIFOTRIG_RXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_RXLVLENA_SHIFT)) & USART_FIFOTRIG_RXLVLENA_MASK) + +#define USART_FIFOTRIG_TXLVL_MASK (0xF00U) +#define USART_FIFOTRIG_TXLVL_SHIFT (8U) +/*! TXLVL - Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled + * to do so, the FIFO level can wake up the device just enough to perform DMA, then return to + * the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the TX FIFO + * becomes empty. 1 = trigger when the TX FIFO level decreases to one entry. 15 = trigger when the TX + * FIFO level decreases to 15 entries (is no longer full). + */ +#define USART_FIFOTRIG_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_TXLVL_SHIFT)) & USART_FIFOTRIG_TXLVL_MASK) + +#define USART_FIFOTRIG_RXLVL_MASK (0xF0000U) +#define USART_FIFOTRIG_RXLVL_SHIFT (16U) +/*! RXLVL - Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data + * is received. This field is used only when RXLVLENA = 1. If enabled to do so, the FIFO level + * can wake up the device just enough to perform DMA, then return to the reduced power mode. See + * Hardware Wake-up control register. 0 = trigger when the RX FIFO has received one entry (is no + * longer empty). 1 = trigger when the RX FIFO has received two entries. 15 = trigger when the RX + * FIFO has received 16 entries (has become full). + */ +#define USART_FIFOTRIG_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_RXLVL_SHIFT)) & USART_FIFOTRIG_RXLVL_MASK) +/*! @} */ + +/*! @name FIFOINTENSET - FIFO interrupt enable set (enable) and read register. */ +/*! @{ */ + +#define USART_FIFOINTENSET_TXERR_MASK (0x1U) +#define USART_FIFOINTENSET_TXERR_SHIFT (0U) +/*! TXERR - Determines whether an interrupt occurs when a transmit error occurs, based on the TXERR flag in the FIFOSTAT register. + * 0b0..No interrupt will be generated for a transmit error. + * 0b1..An interrupt will be generated when a transmit error occurs. + */ +#define USART_FIFOINTENSET_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_TXERR_SHIFT)) & USART_FIFOINTENSET_TXERR_MASK) + +#define USART_FIFOINTENSET_RXERR_MASK (0x2U) +#define USART_FIFOINTENSET_RXERR_SHIFT (1U) +/*! RXERR - Determines whether an interrupt occurs when a receive error occurs, based on the RXERR flag in the FIFOSTAT register. + * 0b0..No interrupt will be generated for a receive error. + * 0b1..An interrupt will be generated when a receive error occurs. + */ +#define USART_FIFOINTENSET_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_RXERR_SHIFT)) & USART_FIFOINTENSET_RXERR_MASK) + +#define USART_FIFOINTENSET_TXLVL_MASK (0x4U) +#define USART_FIFOINTENSET_TXLVL_SHIFT (2U) +/*! TXLVL - Determines whether an interrupt occurs when a the transmit FIFO reaches the level + * specified by the TXLVL field in the FIFOTRIG register. + * 0b0..No interrupt will be generated based on the TX FIFO level. + * 0b1..If TXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the TX FIFO level decreases + * to the level specified by TXLVL in the FIFOTRIG register. + */ +#define USART_FIFOINTENSET_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_TXLVL_SHIFT)) & USART_FIFOINTENSET_TXLVL_MASK) + +#define USART_FIFOINTENSET_RXLVL_MASK (0x8U) +#define USART_FIFOINTENSET_RXLVL_SHIFT (3U) +/*! RXLVL - Determines whether an interrupt occurs when a the receive FIFO reaches the level + * specified by the TXLVL field in the FIFOTRIG register. + * 0b0..No interrupt will be generated based on the RX FIFO level. + * 0b1..If RXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the when the RX FIFO level + * increases to the level specified by RXLVL in the FIFOTRIG register. + */ +#define USART_FIFOINTENSET_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_RXLVL_SHIFT)) & USART_FIFOINTENSET_RXLVL_MASK) +/*! @} */ + +/*! @name FIFOINTENCLR - FIFO interrupt enable clear (disable) and read register. */ +/*! @{ */ + +#define USART_FIFOINTENCLR_TXERR_MASK (0x1U) +#define USART_FIFOINTENCLR_TXERR_SHIFT (0U) +/*! TXERR - Writing one clears the corresponding bits in the FIFOINTENSET register. + */ +#define USART_FIFOINTENCLR_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_TXERR_SHIFT)) & USART_FIFOINTENCLR_TXERR_MASK) + +#define USART_FIFOINTENCLR_RXERR_MASK (0x2U) +#define USART_FIFOINTENCLR_RXERR_SHIFT (1U) +/*! RXERR - Writing one clears the corresponding bits in the FIFOINTENSET register. + */ +#define USART_FIFOINTENCLR_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_RXERR_SHIFT)) & USART_FIFOINTENCLR_RXERR_MASK) + +#define USART_FIFOINTENCLR_TXLVL_MASK (0x4U) +#define USART_FIFOINTENCLR_TXLVL_SHIFT (2U) +/*! TXLVL - Writing one clears the corresponding bits in the FIFOINTENSET register. + */ +#define USART_FIFOINTENCLR_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_TXLVL_SHIFT)) & USART_FIFOINTENCLR_TXLVL_MASK) + +#define USART_FIFOINTENCLR_RXLVL_MASK (0x8U) +#define USART_FIFOINTENCLR_RXLVL_SHIFT (3U) +/*! RXLVL - Writing one clears the corresponding bits in the FIFOINTENSET register. + */ +#define USART_FIFOINTENCLR_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_RXLVL_SHIFT)) & USART_FIFOINTENCLR_RXLVL_MASK) +/*! @} */ + +/*! @name FIFOINTSTAT - FIFO interrupt status register. */ +/*! @{ */ + +#define USART_FIFOINTSTAT_TXERR_MASK (0x1U) +#define USART_FIFOINTSTAT_TXERR_SHIFT (0U) +/*! TXERR - TX FIFO error. + */ +#define USART_FIFOINTSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_TXERR_SHIFT)) & USART_FIFOINTSTAT_TXERR_MASK) + +#define USART_FIFOINTSTAT_RXERR_MASK (0x2U) +#define USART_FIFOINTSTAT_RXERR_SHIFT (1U) +/*! RXERR - RX FIFO error. + */ +#define USART_FIFOINTSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_RXERR_SHIFT)) & USART_FIFOINTSTAT_RXERR_MASK) + +#define USART_FIFOINTSTAT_TXLVL_MASK (0x4U) +#define USART_FIFOINTSTAT_TXLVL_SHIFT (2U) +/*! TXLVL - Transmit FIFO level interrupt. + */ +#define USART_FIFOINTSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_TXLVL_SHIFT)) & USART_FIFOINTSTAT_TXLVL_MASK) + +#define USART_FIFOINTSTAT_RXLVL_MASK (0x8U) +#define USART_FIFOINTSTAT_RXLVL_SHIFT (3U) +/*! RXLVL - Receive FIFO level interrupt. + */ +#define USART_FIFOINTSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_RXLVL_SHIFT)) & USART_FIFOINTSTAT_RXLVL_MASK) + +#define USART_FIFOINTSTAT_PERINT_MASK (0x10U) +#define USART_FIFOINTSTAT_PERINT_SHIFT (4U) +/*! PERINT - Peripheral interrupt. + */ +#define USART_FIFOINTSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_PERINT_SHIFT)) & USART_FIFOINTSTAT_PERINT_MASK) +/*! @} */ + +/*! @name FIFOWR - FIFO write data. */ +/*! @{ */ + +#define USART_FIFOWR_TXDATA_MASK (0x1FFU) +#define USART_FIFOWR_TXDATA_SHIFT (0U) +/*! TXDATA - Transmit data to the FIFO. + */ +#define USART_FIFOWR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOWR_TXDATA_SHIFT)) & USART_FIFOWR_TXDATA_MASK) +/*! @} */ + +/*! @name FIFORD - FIFO read data. */ +/*! @{ */ + +#define USART_FIFORD_RXDATA_MASK (0x1FFU) +#define USART_FIFORD_RXDATA_SHIFT (0U) +/*! RXDATA - Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings. + */ +#define USART_FIFORD_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_RXDATA_SHIFT)) & USART_FIFORD_RXDATA_MASK) + +#define USART_FIFORD_FRAMERR_MASK (0x2000U) +#define USART_FIFORD_FRAMERR_SHIFT (13U) +/*! FRAMERR - Framing Error status flag. This bit reflects the status for the data it is read along + * with from the FIFO, and indicates that the character was received with a missing stop bit at + * the expected location. This could be an indication of a baud rate or configuration mismatch + * with the transmitting source. + */ +#define USART_FIFORD_FRAMERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_FRAMERR_SHIFT)) & USART_FIFORD_FRAMERR_MASK) + +#define USART_FIFORD_PARITYERR_MASK (0x4000U) +#define USART_FIFORD_PARITYERR_SHIFT (14U) +/*! PARITYERR - Parity Error status flag. This bit reflects the status for the data it is read along + * with from the FIFO. This bit will be set when a parity error is detected in a received + * character. + */ +#define USART_FIFORD_PARITYERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_PARITYERR_SHIFT)) & USART_FIFORD_PARITYERR_MASK) + +#define USART_FIFORD_RXNOISE_MASK (0x8000U) +#define USART_FIFORD_RXNOISE_SHIFT (15U) +/*! RXNOISE - Received Noise flag. See description of the RxNoiseInt bit in Table 354. + */ +#define USART_FIFORD_RXNOISE(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_RXNOISE_SHIFT)) & USART_FIFORD_RXNOISE_MASK) +/*! @} */ + +/*! @name FIFORDNOPOP - FIFO data read with no FIFO pop. */ +/*! @{ */ + +#define USART_FIFORDNOPOP_RXDATA_MASK (0x1FFU) +#define USART_FIFORDNOPOP_RXDATA_SHIFT (0U) +/*! RXDATA - Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings. + */ +#define USART_FIFORDNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_RXDATA_SHIFT)) & USART_FIFORDNOPOP_RXDATA_MASK) + +#define USART_FIFORDNOPOP_FRAMERR_MASK (0x2000U) +#define USART_FIFORDNOPOP_FRAMERR_SHIFT (13U) +/*! FRAMERR - Framing Error status flag. This bit reflects the status for the data it is read along + * with from the FIFO, and indicates that the character was received with a missing stop bit at + * the expected location. This could be an indication of a baud rate or configuration mismatch + * with the transmitting source. + */ +#define USART_FIFORDNOPOP_FRAMERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_FRAMERR_SHIFT)) & USART_FIFORDNOPOP_FRAMERR_MASK) + +#define USART_FIFORDNOPOP_PARITYERR_MASK (0x4000U) +#define USART_FIFORDNOPOP_PARITYERR_SHIFT (14U) +/*! PARITYERR - Parity Error status flag. This bit reflects the status for the data it is read along + * with from the FIFO. This bit will be set when a parity error is detected in a received + * character. + */ +#define USART_FIFORDNOPOP_PARITYERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_PARITYERR_SHIFT)) & USART_FIFORDNOPOP_PARITYERR_MASK) + +#define USART_FIFORDNOPOP_RXNOISE_MASK (0x8000U) +#define USART_FIFORDNOPOP_RXNOISE_SHIFT (15U) +/*! RXNOISE - Received Noise flag. See description of the RxNoiseInt bit in Table 354. + */ +#define USART_FIFORDNOPOP_RXNOISE(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_RXNOISE_SHIFT)) & USART_FIFORDNOPOP_RXNOISE_MASK) +/*! @} */ + +/*! @name FIFOSIZE - FIFO size register */ +/*! @{ */ + +#define USART_FIFOSIZE_FIFOSIZE_MASK (0x1FU) +#define USART_FIFOSIZE_FIFOSIZE_SHIFT (0U) +/*! FIFOSIZE - Provides the size of the FIFO for software. The size of the SPI FIFO is 8 entries. + */ +#define USART_FIFOSIZE_FIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSIZE_FIFOSIZE_SHIFT)) & USART_FIFOSIZE_FIFOSIZE_MASK) +/*! @} */ + +/*! @name ID - Peripheral identification register. */ +/*! @{ */ + +#define USART_ID_APERTURE_MASK (0xFFU) +#define USART_ID_APERTURE_SHIFT (0U) +/*! APERTURE - Aperture: encoded as (aperture size/4K) -1, so 0x00 means a 4K aperture. + */ +#define USART_ID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << USART_ID_APERTURE_SHIFT)) & USART_ID_APERTURE_MASK) + +#define USART_ID_MINOR_REV_MASK (0xF00U) +#define USART_ID_MINOR_REV_SHIFT (8U) +/*! MINOR_REV - Minor revision of module implementation. + */ +#define USART_ID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << USART_ID_MINOR_REV_SHIFT)) & USART_ID_MINOR_REV_MASK) + +#define USART_ID_MAJOR_REV_MASK (0xF000U) +#define USART_ID_MAJOR_REV_SHIFT (12U) +/*! MAJOR_REV - Major revision of module implementation. + */ +#define USART_ID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << USART_ID_MAJOR_REV_SHIFT)) & USART_ID_MAJOR_REV_MASK) + +#define USART_ID_ID_MASK (0xFFFF0000U) +#define USART_ID_ID_SHIFT (16U) +/*! ID - Module identifier for the selected function. + */ +#define USART_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << USART_ID_ID_SHIFT)) & USART_ID_ID_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group USART_Register_Masks */ + + +/* USART - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral USART0 base address */ + #define USART0_BASE (0x50086000u) + /** Peripheral USART0 base address */ + #define USART0_BASE_NS (0x40086000u) + /** Peripheral USART0 base pointer */ + #define USART0 ((USART_Type *)USART0_BASE) + /** Peripheral USART0 base pointer */ + #define USART0_NS ((USART_Type *)USART0_BASE_NS) + /** Peripheral USART1 base address */ + #define USART1_BASE (0x50087000u) + /** Peripheral USART1 base address */ + #define USART1_BASE_NS (0x40087000u) + /** Peripheral USART1 base pointer */ + #define USART1 ((USART_Type *)USART1_BASE) + /** Peripheral USART1 base pointer */ + #define USART1_NS ((USART_Type *)USART1_BASE_NS) + /** Peripheral USART2 base address */ + #define USART2_BASE (0x50088000u) + /** Peripheral USART2 base address */ + #define USART2_BASE_NS (0x40088000u) + /** Peripheral USART2 base pointer */ + #define USART2 ((USART_Type *)USART2_BASE) + /** Peripheral USART2 base pointer */ + #define USART2_NS ((USART_Type *)USART2_BASE_NS) + /** Peripheral USART3 base address */ + #define USART3_BASE (0x50089000u) + /** Peripheral USART3 base address */ + #define USART3_BASE_NS (0x40089000u) + /** Peripheral USART3 base pointer */ + #define USART3 ((USART_Type *)USART3_BASE) + /** Peripheral USART3 base pointer */ + #define USART3_NS ((USART_Type *)USART3_BASE_NS) + /** Peripheral USART4 base address */ + #define USART4_BASE (0x5008A000u) + /** Peripheral USART4 base address */ + #define USART4_BASE_NS (0x4008A000u) + /** Peripheral USART4 base pointer */ + #define USART4 ((USART_Type *)USART4_BASE) + /** Peripheral USART4 base pointer */ + #define USART4_NS ((USART_Type *)USART4_BASE_NS) + /** Peripheral USART5 base address */ + #define USART5_BASE (0x50096000u) + /** Peripheral USART5 base address */ + #define USART5_BASE_NS (0x40096000u) + /** Peripheral USART5 base pointer */ + #define USART5 ((USART_Type *)USART5_BASE) + /** Peripheral USART5 base pointer */ + #define USART5_NS ((USART_Type *)USART5_BASE_NS) + /** Peripheral USART6 base address */ + #define USART6_BASE (0x50097000u) + /** Peripheral USART6 base address */ + #define USART6_BASE_NS (0x40097000u) + /** Peripheral USART6 base pointer */ + #define USART6 ((USART_Type *)USART6_BASE) + /** Peripheral USART6 base pointer */ + #define USART6_NS ((USART_Type *)USART6_BASE_NS) + /** Peripheral USART7 base address */ + #define USART7_BASE (0x50098000u) + /** Peripheral USART7 base address */ + #define USART7_BASE_NS (0x40098000u) + /** Peripheral USART7 base pointer */ + #define USART7 ((USART_Type *)USART7_BASE) + /** Peripheral USART7 base pointer */ + #define USART7_NS ((USART_Type *)USART7_BASE_NS) + /** Array initializer of USART peripheral base addresses */ + #define USART_BASE_ADDRS { USART0_BASE, USART1_BASE, USART2_BASE, USART3_BASE, USART4_BASE, USART5_BASE, USART6_BASE, USART7_BASE } + /** Array initializer of USART peripheral base pointers */ + #define USART_BASE_PTRS { USART0, USART1, USART2, USART3, USART4, USART5, USART6, USART7 } + /** Array initializer of USART peripheral base addresses */ + #define USART_BASE_ADDRS_NS { USART0_BASE_NS, USART1_BASE_NS, USART2_BASE_NS, USART3_BASE_NS, USART4_BASE_NS, USART5_BASE_NS, USART6_BASE_NS, USART7_BASE_NS } + /** Array initializer of USART peripheral base pointers */ + #define USART_BASE_PTRS_NS { USART0_NS, USART1_NS, USART2_NS, USART3_NS, USART4_NS, USART5_NS, USART6_NS, USART7_NS } +#else + /** Peripheral USART0 base address */ + #define USART0_BASE (0x40086000u) + /** Peripheral USART0 base pointer */ + #define USART0 ((USART_Type *)USART0_BASE) + /** Peripheral USART1 base address */ + #define USART1_BASE (0x40087000u) + /** Peripheral USART1 base pointer */ + #define USART1 ((USART_Type *)USART1_BASE) + /** Peripheral USART2 base address */ + #define USART2_BASE (0x40088000u) + /** Peripheral USART2 base pointer */ + #define USART2 ((USART_Type *)USART2_BASE) + /** Peripheral USART3 base address */ + #define USART3_BASE (0x40089000u) + /** Peripheral USART3 base pointer */ + #define USART3 ((USART_Type *)USART3_BASE) + /** Peripheral USART4 base address */ + #define USART4_BASE (0x4008A000u) + /** Peripheral USART4 base pointer */ + #define USART4 ((USART_Type *)USART4_BASE) + /** Peripheral USART5 base address */ + #define USART5_BASE (0x40096000u) + /** Peripheral USART5 base pointer */ + #define USART5 ((USART_Type *)USART5_BASE) + /** Peripheral USART6 base address */ + #define USART6_BASE (0x40097000u) + /** Peripheral USART6 base pointer */ + #define USART6 ((USART_Type *)USART6_BASE) + /** Peripheral USART7 base address */ + #define USART7_BASE (0x40098000u) + /** Peripheral USART7 base pointer */ + #define USART7 ((USART_Type *)USART7_BASE) + /** Array initializer of USART peripheral base addresses */ + #define USART_BASE_ADDRS { USART0_BASE, USART1_BASE, USART2_BASE, USART3_BASE, USART4_BASE, USART5_BASE, USART6_BASE, USART7_BASE } + /** Array initializer of USART peripheral base pointers */ + #define USART_BASE_PTRS { USART0, USART1, USART2, USART3, USART4, USART5, USART6, USART7 } +#endif +/** Interrupt vectors for the USART peripheral type */ +#define USART_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn } + +/*! + * @} + */ /* end of group USART_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- USB Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer + * @{ + */ + +/** USB - Register Layout Typedef */ +typedef struct { + __IO uint32_t DEVCMDSTAT; /**< USB Device Command/Status register, offset: 0x0 */ + __IO uint32_t INFO; /**< USB Info register, offset: 0x4 */ + __IO uint32_t EPLISTSTART; /**< USB EP Command/Status List start address, offset: 0x8 */ + __IO uint32_t DATABUFSTART; /**< USB Data buffer start address, offset: 0xC */ + __IO uint32_t LPM; /**< USB Link Power Management register, offset: 0x10 */ + __IO uint32_t EPSKIP; /**< USB Endpoint skip, offset: 0x14 */ + __IO uint32_t EPINUSE; /**< USB Endpoint Buffer in use, offset: 0x18 */ + __IO uint32_t EPBUFCFG; /**< USB Endpoint Buffer Configuration register, offset: 0x1C */ + __IO uint32_t INTSTAT; /**< USB interrupt status register, offset: 0x20 */ + __IO uint32_t INTEN; /**< USB interrupt enable register, offset: 0x24 */ + __IO uint32_t INTSETSTAT; /**< USB set interrupt status register, offset: 0x28 */ + uint8_t RESERVED_0[8]; + __IO uint32_t EPTOGGLE; /**< USB Endpoint toggle register, offset: 0x34 */ +} USB_Type; + +/* ---------------------------------------------------------------------------- + -- USB Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USB_Register_Masks USB Register Masks + * @{ + */ + +/*! @name DEVCMDSTAT - USB Device Command/Status register */ +/*! @{ */ + +#define USB_DEVCMDSTAT_DEV_ADDR_MASK (0x7FU) +#define USB_DEVCMDSTAT_DEV_ADDR_SHIFT (0U) +/*! DEV_ADDR - USB device address. After bus reset, the address is reset to 0x00. If the enable bit + * is set, the device will respond on packets for function address DEV_ADDR. When receiving a + * SetAddress Control Request from the USB host, software must program the new address before + * completing the status phase of the SetAddress Control Request. + */ +#define USB_DEVCMDSTAT_DEV_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DEV_ADDR_SHIFT)) & USB_DEVCMDSTAT_DEV_ADDR_MASK) + +#define USB_DEVCMDSTAT_DEV_EN_MASK (0x80U) +#define USB_DEVCMDSTAT_DEV_EN_SHIFT (7U) +/*! DEV_EN - USB device enable. If this bit is set, the HW will start responding on packets for function address DEV_ADDR. + */ +#define USB_DEVCMDSTAT_DEV_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DEV_EN_SHIFT)) & USB_DEVCMDSTAT_DEV_EN_MASK) + +#define USB_DEVCMDSTAT_SETUP_MASK (0x100U) +#define USB_DEVCMDSTAT_SETUP_SHIFT (8U) +/*! SETUP - SETUP token received. If a SETUP token is received and acknowledged by the device, this + * bit is set. As long as this bit is set all received IN and OUT tokens will be NAKed by HW. SW + * must clear this bit by writing a one. If this bit is zero, HW will handle the tokens to the + * CTRL EP0 as indicated by the CTRL EP0 IN and OUT data information programmed by SW. + */ +#define USB_DEVCMDSTAT_SETUP(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_SETUP_SHIFT)) & USB_DEVCMDSTAT_SETUP_MASK) + +#define USB_DEVCMDSTAT_FORCE_NEEDCLK_MASK (0x200U) +#define USB_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT (9U) +/*! FORCE_NEEDCLK - Forces the NEEDCLK output to always be on: + * 0b0..USB_NEEDCLK has normal function. + * 0b1..USB_NEEDCLK always 1. Clock will not be stopped in case of suspend. + */ +#define USB_DEVCMDSTAT_FORCE_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT)) & USB_DEVCMDSTAT_FORCE_NEEDCLK_MASK) + +#define USB_DEVCMDSTAT_LPM_SUP_MASK (0x800U) +#define USB_DEVCMDSTAT_LPM_SUP_SHIFT (11U) +/*! LPM_SUP - LPM Supported: + * 0b0..LPM not supported. + * 0b1..LPM supported. + */ +#define USB_DEVCMDSTAT_LPM_SUP(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_LPM_SUP_SHIFT)) & USB_DEVCMDSTAT_LPM_SUP_MASK) + +#define USB_DEVCMDSTAT_INTONNAK_AO_MASK (0x1000U) +#define USB_DEVCMDSTAT_INTONNAK_AO_SHIFT (12U) +/*! INTONNAK_AO - Interrupt on NAK for interrupt and bulk OUT EP + * 0b0..Only acknowledged packets generate an interrupt + * 0b1..Both acknowledged and NAKed packets generate interrupts. + */ +#define USB_DEVCMDSTAT_INTONNAK_AO(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_AO_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_AO_MASK) + +#define USB_DEVCMDSTAT_INTONNAK_AI_MASK (0x2000U) +#define USB_DEVCMDSTAT_INTONNAK_AI_SHIFT (13U) +/*! INTONNAK_AI - Interrupt on NAK for interrupt and bulk IN EP + * 0b0..Only acknowledged packets generate an interrupt + * 0b1..Both acknowledged and NAKed packets generate interrupts. + */ +#define USB_DEVCMDSTAT_INTONNAK_AI(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_AI_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_AI_MASK) + +#define USB_DEVCMDSTAT_INTONNAK_CO_MASK (0x4000U) +#define USB_DEVCMDSTAT_INTONNAK_CO_SHIFT (14U) +/*! INTONNAK_CO - Interrupt on NAK for control OUT EP + * 0b0..Only acknowledged packets generate an interrupt + * 0b1..Both acknowledged and NAKed packets generate interrupts. + */ +#define USB_DEVCMDSTAT_INTONNAK_CO(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_CO_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_CO_MASK) + +#define USB_DEVCMDSTAT_INTONNAK_CI_MASK (0x8000U) +#define USB_DEVCMDSTAT_INTONNAK_CI_SHIFT (15U) +/*! INTONNAK_CI - Interrupt on NAK for control IN EP + * 0b0..Only acknowledged packets generate an interrupt + * 0b1..Both acknowledged and NAKed packets generate interrupts. + */ +#define USB_DEVCMDSTAT_INTONNAK_CI(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_CI_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_CI_MASK) + +#define USB_DEVCMDSTAT_DCON_MASK (0x10000U) +#define USB_DEVCMDSTAT_DCON_SHIFT (16U) +/*! DCON - Device status - connect. The connect bit must be set by SW to indicate that the device + * must signal a connect. The pull-up resistor on USB_DP will be enabled when this bit is set and + * the VBUSDEBOUNCED bit is one. + */ +#define USB_DEVCMDSTAT_DCON(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DCON_SHIFT)) & USB_DEVCMDSTAT_DCON_MASK) + +#define USB_DEVCMDSTAT_DSUS_MASK (0x20000U) +#define USB_DEVCMDSTAT_DSUS_SHIFT (17U) +/*! DSUS - Device status - suspend. The suspend bit indicates the current suspend state. It is set + * to 1 when the device hasn't seen any activity on its upstream port for more than 3 + * milliseconds. It is reset to 0 on any activity. When the device is suspended (Suspend bit DSUS = 1) and + * the software writes a 0 to it, the device will generate a remote wake-up. This will only happen + * when the device is connected (Connect bit = 1). When the device is not connected or not + * suspended, a writing a 0 has no effect. Writing a 1 never has an effect. + */ +#define USB_DEVCMDSTAT_DSUS(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DSUS_SHIFT)) & USB_DEVCMDSTAT_DSUS_MASK) + +#define USB_DEVCMDSTAT_LPM_SUS_MASK (0x80000U) +#define USB_DEVCMDSTAT_LPM_SUS_SHIFT (19U) +/*! LPM_SUS - Device status - LPM Suspend. This bit represents the current LPM suspend state. It is + * set to 1 by HW when the device has acknowledged the LPM request from the USB host and the + * Token Retry Time of 10 ms has elapsed. When the device is in the LPM suspended state (LPM suspend + * bit = 1) and the software writes a zero to this bit, the device will generate a remote + * walk-up. Software can only write a zero to this bit when the LPM_REWP bit is set to 1. HW resets this + * bit when it receives a host initiated resume. HW only updates the LPM_SUS bit when the + * LPM_SUPP bit is equal to one. + */ +#define USB_DEVCMDSTAT_LPM_SUS(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_LPM_SUS_SHIFT)) & USB_DEVCMDSTAT_LPM_SUS_MASK) + +#define USB_DEVCMDSTAT_LPM_REWP_MASK (0x100000U) +#define USB_DEVCMDSTAT_LPM_REWP_SHIFT (20U) +/*! LPM_REWP - LPM Remote Wake-up Enabled by USB host. HW sets this bit to one when the bRemoteWake + * bit in the LPM extended token is set to 1. HW will reset this bit to 0 when it receives the + * host initiated LPM resume, when a remote wake-up is sent by the device or when a USB bus reset + * is received. Software can use this bit to check if the remote wake-up feature is enabled by the + * host for the LPM transaction. + */ +#define USB_DEVCMDSTAT_LPM_REWP(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_LPM_REWP_SHIFT)) & USB_DEVCMDSTAT_LPM_REWP_MASK) + +#define USB_DEVCMDSTAT_DCON_C_MASK (0x1000000U) +#define USB_DEVCMDSTAT_DCON_C_SHIFT (24U) +/*! DCON_C - Device status - connect change. The Connect Change bit is set when the device's pull-up + * resistor is disconnected because VBus disappeared. The bit is reset by writing a one to it. + */ +#define USB_DEVCMDSTAT_DCON_C(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DCON_C_SHIFT)) & USB_DEVCMDSTAT_DCON_C_MASK) + +#define USB_DEVCMDSTAT_DSUS_C_MASK (0x2000000U) +#define USB_DEVCMDSTAT_DSUS_C_SHIFT (25U) +/*! DSUS_C - Device status - suspend change. The suspend change bit is set to 1 when the suspend bit + * toggles. The suspend bit can toggle because: - The device goes in the suspended state - The + * device is disconnected - The device receives resume signaling on its upstream port. The bit is + * reset by writing a one to it. + */ +#define USB_DEVCMDSTAT_DSUS_C(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DSUS_C_SHIFT)) & USB_DEVCMDSTAT_DSUS_C_MASK) + +#define USB_DEVCMDSTAT_DRES_C_MASK (0x4000000U) +#define USB_DEVCMDSTAT_DRES_C_SHIFT (26U) +/*! DRES_C - Device status - reset change. This bit is set when the device received a bus reset. On + * a bus reset the device will automatically go to the default state (unconfigured and responding + * to address 0). The bit is reset by writing a one to it. + */ +#define USB_DEVCMDSTAT_DRES_C(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DRES_C_SHIFT)) & USB_DEVCMDSTAT_DRES_C_MASK) + +#define USB_DEVCMDSTAT_VBUSDEBOUNCED_MASK (0x10000000U) +#define USB_DEVCMDSTAT_VBUSDEBOUNCED_SHIFT (28U) +/*! VBUSDEBOUNCED - This bit indicates if Vbus is detected or not. The bit raises immediately when + * Vbus becomes high. It drops to zero if Vbus is low for at least 3 ms. If this bit is high and + * the DCon bit is set, the HW will enable the pull-up resistor to signal a connect. + */ +#define USB_DEVCMDSTAT_VBUSDEBOUNCED(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_VBUSDEBOUNCED_SHIFT)) & USB_DEVCMDSTAT_VBUSDEBOUNCED_MASK) +/*! @} */ + +/*! @name INFO - USB Info register */ +/*! @{ */ + +#define USB_INFO_FRAME_NR_MASK (0x7FFU) +#define USB_INFO_FRAME_NR_SHIFT (0U) +/*! FRAME_NR - Frame number. This contains the frame number of the last successfully received SOF. + * In case no SOF was received by the device at the beginning of a frame, the frame number + * returned is that of the last successfully received SOF. In case the SOF frame number contained a CRC + * error, the frame number returned will be the corrupted frame number as received by the device. + */ +#define USB_INFO_FRAME_NR(x) (((uint32_t)(((uint32_t)(x)) << USB_INFO_FRAME_NR_SHIFT)) & USB_INFO_FRAME_NR_MASK) + +#define USB_INFO_ERR_CODE_MASK (0x7800U) +#define USB_INFO_ERR_CODE_SHIFT (11U) +/*! ERR_CODE - The error code which last occurred: + * 0b0000..No error + * 0b0001..PID encoding error + * 0b0010..PID unknown + * 0b0011..Packet unexpected + * 0b0100..Token CRC error + * 0b0101..Data CRC error + * 0b0110..Time out + * 0b0111..Babble + * 0b1000..Truncated EOP + * 0b1001..Sent/Received NAK + * 0b1010..Sent Stall + * 0b1011..Overrun + * 0b1100..Sent empty packet + * 0b1101..Bitstuff error + * 0b1110..Sync error + * 0b1111..Wrong data toggle + */ +#define USB_INFO_ERR_CODE(x) (((uint32_t)(((uint32_t)(x)) << USB_INFO_ERR_CODE_SHIFT)) & USB_INFO_ERR_CODE_MASK) + +#define USB_INFO_MINREV_MASK (0xFF0000U) +#define USB_INFO_MINREV_SHIFT (16U) +/*! MINREV - Minor Revision. + */ +#define USB_INFO_MINREV(x) (((uint32_t)(((uint32_t)(x)) << USB_INFO_MINREV_SHIFT)) & USB_INFO_MINREV_MASK) + +#define USB_INFO_MAJREV_MASK (0xFF000000U) +#define USB_INFO_MAJREV_SHIFT (24U) +/*! MAJREV - Major Revision. + */ +#define USB_INFO_MAJREV(x) (((uint32_t)(((uint32_t)(x)) << USB_INFO_MAJREV_SHIFT)) & USB_INFO_MAJREV_MASK) +/*! @} */ + +/*! @name EPLISTSTART - USB EP Command/Status List start address */ +/*! @{ */ + +#define USB_EPLISTSTART_EP_LIST_MASK (0xFFFFFF00U) +#define USB_EPLISTSTART_EP_LIST_SHIFT (8U) +/*! EP_LIST - Start address of the USB EP Command/Status List. + */ +#define USB_EPLISTSTART_EP_LIST(x) (((uint32_t)(((uint32_t)(x)) << USB_EPLISTSTART_EP_LIST_SHIFT)) & USB_EPLISTSTART_EP_LIST_MASK) +/*! @} */ + +/*! @name DATABUFSTART - USB Data buffer start address */ +/*! @{ */ + +#define USB_DATABUFSTART_DA_BUF_MASK (0xFFC00000U) +#define USB_DATABUFSTART_DA_BUF_SHIFT (22U) +/*! DA_BUF - Start address of the buffer pointer page where all endpoint data buffers are located. + */ +#define USB_DATABUFSTART_DA_BUF(x) (((uint32_t)(((uint32_t)(x)) << USB_DATABUFSTART_DA_BUF_SHIFT)) & USB_DATABUFSTART_DA_BUF_MASK) +/*! @} */ + +/*! @name LPM - USB Link Power Management register */ +/*! @{ */ + +#define USB_LPM_HIRD_HW_MASK (0xFU) +#define USB_LPM_HIRD_HW_SHIFT (0U) +/*! HIRD_HW - Host Initiated Resume Duration - HW. This is the HIRD value from the last received LPM token + */ +#define USB_LPM_HIRD_HW(x) (((uint32_t)(((uint32_t)(x)) << USB_LPM_HIRD_HW_SHIFT)) & USB_LPM_HIRD_HW_MASK) + +#define USB_LPM_HIRD_SW_MASK (0xF0U) +#define USB_LPM_HIRD_SW_SHIFT (4U) +/*! HIRD_SW - Host Initiated Resume Duration - SW. This is the time duration required by the USB + * device system to come out of LPM initiated suspend after receiving the host initiated LPM resume. + */ +#define USB_LPM_HIRD_SW(x) (((uint32_t)(((uint32_t)(x)) << USB_LPM_HIRD_SW_SHIFT)) & USB_LPM_HIRD_SW_MASK) + +#define USB_LPM_DATA_PENDING_MASK (0x100U) +#define USB_LPM_DATA_PENDING_SHIFT (8U) +/*! DATA_PENDING - As long as this bit is set to one and LPM supported bit is set to one, HW will + * return a NYET handshake on every LPM token it receives. If LPM supported bit is set to one and + * this bit is zero, HW will return an ACK handshake on every LPM token it receives. If SW has + * still data pending and LPM is supported, it must set this bit to 1. + */ +#define USB_LPM_DATA_PENDING(x) (((uint32_t)(((uint32_t)(x)) << USB_LPM_DATA_PENDING_SHIFT)) & USB_LPM_DATA_PENDING_MASK) +/*! @} */ + +/*! @name EPSKIP - USB Endpoint skip */ +/*! @{ */ + +#define USB_EPSKIP_SKIP_MASK (0x3FFU) +#define USB_EPSKIP_SKIP_SHIFT (0U) +/*! SKIP - Endpoint skip: Writing 1 to one of these bits, will indicate to HW that it must + * deactivate the buffer assigned to this endpoint and return control back to software. When HW has + * deactivated the endpoint, it will clear this bit, but it will not modify the EPINUSE bit. An + * interrupt will be generated when the Active bit goes from 1 to 0. Note: In case of double-buffering, + * HW will only clear the Active bit of the buffer indicated by the EPINUSE bit. + */ +#define USB_EPSKIP_SKIP(x) (((uint32_t)(((uint32_t)(x)) << USB_EPSKIP_SKIP_SHIFT)) & USB_EPSKIP_SKIP_MASK) +/*! @} */ + +/*! @name EPINUSE - USB Endpoint Buffer in use */ +/*! @{ */ + +#define USB_EPINUSE_BUF_MASK (0x3FCU) +#define USB_EPINUSE_BUF_SHIFT (2U) +/*! BUF - Buffer in use: This register has one bit per physical endpoint. 0: HW is accessing buffer + * 0. 1: HW is accessing buffer 1. + */ +#define USB_EPINUSE_BUF(x) (((uint32_t)(((uint32_t)(x)) << USB_EPINUSE_BUF_SHIFT)) & USB_EPINUSE_BUF_MASK) +/*! @} */ + +/*! @name EPBUFCFG - USB Endpoint Buffer Configuration register */ +/*! @{ */ + +#define USB_EPBUFCFG_BUF_SB_MASK (0x3FCU) +#define USB_EPBUFCFG_BUF_SB_SHIFT (2U) +/*! BUF_SB - Buffer usage: This register has one bit per physical endpoint. 0: Single-buffer. 1: + * Double-buffer. If the bit is set to single-buffer (0), it will not toggle the corresponding + * EPINUSE bit when it clears the active bit. If the bit is set to double-buffer (1), HW will toggle + * the EPINUSE bit when it clears the Active bit for the buffer. + */ +#define USB_EPBUFCFG_BUF_SB(x) (((uint32_t)(((uint32_t)(x)) << USB_EPBUFCFG_BUF_SB_SHIFT)) & USB_EPBUFCFG_BUF_SB_MASK) +/*! @} */ + +/*! @name INTSTAT - USB interrupt status register */ +/*! @{ */ + +#define USB_INTSTAT_EP0OUT_MASK (0x1U) +#define USB_INTSTAT_EP0OUT_SHIFT (0U) +/*! EP0OUT - Interrupt status register bit for the Control EP0 OUT direction. This bit will be set + * if NBytes transitions to zero or the skip bit is set by software or a SETUP packet is + * successfully received for the control EP0. If the IntOnNAK_CO is set, this bit will also be set when a + * NAK is transmitted for the Control EP0 OUT direction. Software can clear this bit by writing a + * one to it. + */ +#define USB_INTSTAT_EP0OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP0OUT_SHIFT)) & USB_INTSTAT_EP0OUT_MASK) + +#define USB_INTSTAT_EP0IN_MASK (0x2U) +#define USB_INTSTAT_EP0IN_SHIFT (1U) +/*! EP0IN - Interrupt status register bit for the Control EP0 IN direction. This bit will be set if + * NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_CI is set, this + * bit will also be set when a NAK is transmitted for the Control EP0 IN direction. Software can + * clear this bit by writing a one to it. + */ +#define USB_INTSTAT_EP0IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP0IN_SHIFT)) & USB_INTSTAT_EP0IN_MASK) + +#define USB_INTSTAT_EP1OUT_MASK (0x4U) +#define USB_INTSTAT_EP1OUT_SHIFT (2U) +/*! EP1OUT - Interrupt status register bit for the EP1 OUT direction. This bit will be set if the + * corresponding Active bit is cleared by HW. This is done in case the programmed NBytes + * transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be + * set when a NAK is transmitted for the EP1 OUT direction. Software can clear this bit by + * writing a one to it. + */ +#define USB_INTSTAT_EP1OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP1OUT_SHIFT)) & USB_INTSTAT_EP1OUT_MASK) + +#define USB_INTSTAT_EP1IN_MASK (0x8U) +#define USB_INTSTAT_EP1IN_SHIFT (3U) +/*! EP1IN - Interrupt status register bit for the EP1 IN direction. This bit will be set if the + * corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions + * to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be + * set when a NAK is transmitted for the EP1 IN direction. Software can clear this bit by writing + * a one to it. + */ +#define USB_INTSTAT_EP1IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP1IN_SHIFT)) & USB_INTSTAT_EP1IN_MASK) + +#define USB_INTSTAT_EP2OUT_MASK (0x10U) +#define USB_INTSTAT_EP2OUT_SHIFT (4U) +/*! EP2OUT - Interrupt status register bit for the EP2 OUT direction. This bit will be set if the + * corresponding Active bit is cleared by HW. This is done in case the programmed NBytes + * transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be + * set when a NAK is transmitted for the EP2 OUT direction. Software can clear this bit by + * writing a one to it. + */ +#define USB_INTSTAT_EP2OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP2OUT_SHIFT)) & USB_INTSTAT_EP2OUT_MASK) + +#define USB_INTSTAT_EP2IN_MASK (0x20U) +#define USB_INTSTAT_EP2IN_SHIFT (5U) +/*! EP2IN - Interrupt status register bit for the EP2 IN direction. This bit will be set if the + * corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions + * to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be + * set when a NAK is transmitted for the EP2 IN direction. Software can clear this bit by writing + * a one to it. + */ +#define USB_INTSTAT_EP2IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP2IN_SHIFT)) & USB_INTSTAT_EP2IN_MASK) + +#define USB_INTSTAT_EP3OUT_MASK (0x40U) +#define USB_INTSTAT_EP3OUT_SHIFT (6U) +/*! EP3OUT - Interrupt status register bit for the EP3 OUT direction. This bit will be set if the + * corresponding Active bit is cleared by HW. This is done in case the programmed NBytes + * transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be + * set when a NAK is transmitted for the EP3 OUT direction. Software can clear this bit by + * writing a one to it. + */ +#define USB_INTSTAT_EP3OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP3OUT_SHIFT)) & USB_INTSTAT_EP3OUT_MASK) + +#define USB_INTSTAT_EP3IN_MASK (0x80U) +#define USB_INTSTAT_EP3IN_SHIFT (7U) +/*! EP3IN - Interrupt status register bit for the EP3 IN direction. This bit will be set if the + * corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions + * to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be + * set when a NAK is transmitted for the EP3 IN direction. Software can clear this bit by writing + * a one to it. + */ +#define USB_INTSTAT_EP3IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP3IN_SHIFT)) & USB_INTSTAT_EP3IN_MASK) + +#define USB_INTSTAT_EP4OUT_MASK (0x100U) +#define USB_INTSTAT_EP4OUT_SHIFT (8U) +/*! EP4OUT - Interrupt status register bit for the EP4 OUT direction. This bit will be set if the + * corresponding Active bit is cleared by HW. This is done in case the programmed NBytes + * transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be + * set when a NAK is transmitted for the EP4 OUT direction. Software can clear this bit by + * writing a one to it. + */ +#define USB_INTSTAT_EP4OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP4OUT_SHIFT)) & USB_INTSTAT_EP4OUT_MASK) + +#define USB_INTSTAT_EP4IN_MASK (0x200U) +#define USB_INTSTAT_EP4IN_SHIFT (9U) +/*! EP4IN - Interrupt status register bit for the EP4 IN direction. This bit will be set if the + * corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions + * to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be + * set when a NAK is transmitted for the EP4 IN direction. Software can clear this bit by writing + * a one to it. + */ +#define USB_INTSTAT_EP4IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP4IN_SHIFT)) & USB_INTSTAT_EP4IN_MASK) + +#define USB_INTSTAT_FRAME_INT_MASK (0x40000000U) +#define USB_INTSTAT_FRAME_INT_SHIFT (30U) +/*! FRAME_INT - Frame interrupt. This bit is set to one every millisecond when the VbusDebounced bit + * and the DCON bit are set. This bit can be used by software when handling isochronous + * endpoints. Software can clear this bit by writing a one to it. + */ +#define USB_INTSTAT_FRAME_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_FRAME_INT_SHIFT)) & USB_INTSTAT_FRAME_INT_MASK) + +#define USB_INTSTAT_DEV_INT_MASK (0x80000000U) +#define USB_INTSTAT_DEV_INT_SHIFT (31U) +/*! DEV_INT - Device status interrupt. This bit is set by HW when one of the bits in the Device + * Status Change register are set. Software can clear this bit by writing a one to it. + */ +#define USB_INTSTAT_DEV_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_DEV_INT_SHIFT)) & USB_INTSTAT_DEV_INT_MASK) +/*! @} */ + +/*! @name INTEN - USB interrupt enable register */ +/*! @{ */ + +#define USB_INTEN_EP_INT_EN_MASK (0x3FFU) +#define USB_INTEN_EP_INT_EN_SHIFT (0U) +/*! EP_INT_EN - If this bit is set and the corresponding USB interrupt status bit is set, a HW + * interrupt is generated on the interrupt line indicated by the corresponding USB interrupt routing + * bit. + */ +#define USB_INTEN_EP_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTEN_EP_INT_EN_SHIFT)) & USB_INTEN_EP_INT_EN_MASK) + +#define USB_INTEN_FRAME_INT_EN_MASK (0x40000000U) +#define USB_INTEN_FRAME_INT_EN_SHIFT (30U) +/*! FRAME_INT_EN - If this bit is set and the corresponding USB interrupt status bit is set, a HW + * interrupt is generated on the interrupt line indicated by the corresponding USB interrupt + * routing bit. + */ +#define USB_INTEN_FRAME_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTEN_FRAME_INT_EN_SHIFT)) & USB_INTEN_FRAME_INT_EN_MASK) + +#define USB_INTEN_DEV_INT_EN_MASK (0x80000000U) +#define USB_INTEN_DEV_INT_EN_SHIFT (31U) +/*! DEV_INT_EN - If this bit is set and the corresponding USB interrupt status bit is set, a HW + * interrupt is generated on the interrupt line indicated by the corresponding USB interrupt routing + * bit. + */ +#define USB_INTEN_DEV_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTEN_DEV_INT_EN_SHIFT)) & USB_INTEN_DEV_INT_EN_MASK) +/*! @} */ + +/*! @name INTSETSTAT - USB set interrupt status register */ +/*! @{ */ + +#define USB_INTSETSTAT_EP_SET_INT_MASK (0x3FFU) +#define USB_INTSETSTAT_EP_SET_INT_SHIFT (0U) +/*! EP_SET_INT - If software writes a one to one of these bits, the corresponding USB interrupt + * status bit is set. When this register is read, the same value as the USB interrupt status register + * is returned. + */ +#define USB_INTSETSTAT_EP_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSETSTAT_EP_SET_INT_SHIFT)) & USB_INTSETSTAT_EP_SET_INT_MASK) + +#define USB_INTSETSTAT_FRAME_SET_INT_MASK (0x40000000U) +#define USB_INTSETSTAT_FRAME_SET_INT_SHIFT (30U) +/*! FRAME_SET_INT - If software writes a one to one of these bits, the corresponding USB interrupt + * status bit is set. When this register is read, the same value as the USB interrupt status + * register is returned. + */ +#define USB_INTSETSTAT_FRAME_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSETSTAT_FRAME_SET_INT_SHIFT)) & USB_INTSETSTAT_FRAME_SET_INT_MASK) + +#define USB_INTSETSTAT_DEV_SET_INT_MASK (0x80000000U) +#define USB_INTSETSTAT_DEV_SET_INT_SHIFT (31U) +/*! DEV_SET_INT - If software writes a one to one of these bits, the corresponding USB interrupt + * status bit is set. When this register is read, the same value as the USB interrupt status + * register is returned. + */ +#define USB_INTSETSTAT_DEV_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSETSTAT_DEV_SET_INT_SHIFT)) & USB_INTSETSTAT_DEV_SET_INT_MASK) +/*! @} */ + +/*! @name EPTOGGLE - USB Endpoint toggle register */ +/*! @{ */ + +#define USB_EPTOGGLE_TOGGLE_MASK (0x3FFU) +#define USB_EPTOGGLE_TOGGLE_SHIFT (0U) +/*! TOGGLE - Endpoint data toggle: This field indicates the current value of the data toggle for the corresponding endpoint. + */ +#define USB_EPTOGGLE_TOGGLE(x) (((uint32_t)(((uint32_t)(x)) << USB_EPTOGGLE_TOGGLE_SHIFT)) & USB_EPTOGGLE_TOGGLE_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group USB_Register_Masks */ + + +/* USB - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral USB0 base address */ + #define USB0_BASE (0x50084000u) + /** Peripheral USB0 base address */ + #define USB0_BASE_NS (0x40084000u) + /** Peripheral USB0 base pointer */ + #define USB0 ((USB_Type *)USB0_BASE) + /** Peripheral USB0 base pointer */ + #define USB0_NS ((USB_Type *)USB0_BASE_NS) + /** Array initializer of USB peripheral base addresses */ + #define USB_BASE_ADDRS { USB0_BASE } + /** Array initializer of USB peripheral base pointers */ + #define USB_BASE_PTRS { USB0 } + /** Array initializer of USB peripheral base addresses */ + #define USB_BASE_ADDRS_NS { USB0_BASE_NS } + /** Array initializer of USB peripheral base pointers */ + #define USB_BASE_PTRS_NS { USB0_NS } +#else + /** Peripheral USB0 base address */ + #define USB0_BASE (0x40084000u) + /** Peripheral USB0 base pointer */ + #define USB0 ((USB_Type *)USB0_BASE) + /** Array initializer of USB peripheral base addresses */ + #define USB_BASE_ADDRS { USB0_BASE } + /** Array initializer of USB peripheral base pointers */ + #define USB_BASE_PTRS { USB0 } +#endif +/** Interrupt vectors for the USB peripheral type */ +#define USB_IRQS { USB0_IRQn } +#define USB_NEEDCLK_IRQS { USB0_NEEDCLK_IRQn } + +/*! + * @} + */ /* end of group USB_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- USBFSH Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USBFSH_Peripheral_Access_Layer USBFSH Peripheral Access Layer + * @{ + */ + +/** USBFSH - Register Layout Typedef */ +typedef struct { + __I uint32_t HCREVISION; /**< BCD representation of the version of the HCI specification that is implemented by the Host Controller (HC), offset: 0x0 */ + __IO uint32_t HCCONTROL; /**< Defines the operating modes of the HC, offset: 0x4 */ + __IO uint32_t HCCOMMANDSTATUS; /**< This register is used to receive the commands from the Host Controller Driver (HCD), offset: 0x8 */ + __IO uint32_t HCINTERRUPTSTATUS; /**< Indicates the status on various events that cause hardware interrupts by setting the appropriate bits, offset: 0xC */ + __IO uint32_t HCINTERRUPTENABLE; /**< Controls the bits in the HcInterruptStatus register and indicates which events will generate a hardware interrupt, offset: 0x10 */ + __IO uint32_t HCINTERRUPTDISABLE; /**< The bits in this register are used to disable corresponding bits in the HCInterruptStatus register and in turn disable that event leading to hardware interrupt, offset: 0x14 */ + __IO uint32_t HCHCCA; /**< Contains the physical address of the host controller communication area, offset: 0x18 */ + __I uint32_t HCPERIODCURRENTED; /**< Contains the physical address of the current isochronous or interrupt endpoint descriptor, offset: 0x1C */ + __IO uint32_t HCCONTROLHEADED; /**< Contains the physical address of the first endpoint descriptor of the control list, offset: 0x20 */ + __IO uint32_t HCCONTROLCURRENTED; /**< Contains the physical address of the current endpoint descriptor of the control list, offset: 0x24 */ + __IO uint32_t HCBULKHEADED; /**< Contains the physical address of the first endpoint descriptor of the bulk list, offset: 0x28 */ + __IO uint32_t HCBULKCURRENTED; /**< Contains the physical address of the current endpoint descriptor of the bulk list, offset: 0x2C */ + __I uint32_t HCDONEHEAD; /**< Contains the physical address of the last transfer descriptor added to the 'Done' queue, offset: 0x30 */ + __IO uint32_t HCFMINTERVAL; /**< Defines the bit time interval in a frame and the full speed maximum packet size which would not cause an overrun, offset: 0x34 */ + __I uint32_t HCFMREMAINING; /**< A 14-bit counter showing the bit time remaining in the current frame, offset: 0x38 */ + __I uint32_t HCFMNUMBER; /**< Contains a 16-bit counter and provides the timing reference among events happening in the HC and the HCD, offset: 0x3C */ + __IO uint32_t HCPERIODICSTART; /**< Contains a programmable 14-bit value which determines the earliest time HC should start processing a periodic list, offset: 0x40 */ + __IO uint32_t HCLSTHRESHOLD; /**< Contains 11-bit value which is used by the HC to determine whether to commit to transfer a maximum of 8-byte LS packet before EOF, offset: 0x44 */ + __IO uint32_t HCRHDESCRIPTORA; /**< First of the two registers which describes the characteristics of the root hub, offset: 0x48 */ + __IO uint32_t HCRHDESCRIPTORB; /**< Second of the two registers which describes the characteristics of the Root Hub, offset: 0x4C */ + __IO uint32_t HCRHSTATUS; /**< This register is divided into two parts, offset: 0x50 */ + __IO uint32_t HCRHPORTSTATUS; /**< Controls and reports the port events on a per-port basis, offset: 0x54 */ + uint8_t RESERVED_0[4]; + __IO uint32_t PORTMODE; /**< Controls the port if it is attached to the host block or the device block, offset: 0x5C */ +} USBFSH_Type; + +/* ---------------------------------------------------------------------------- + -- USBFSH Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USBFSH_Register_Masks USBFSH Register Masks + * @{ + */ + +/*! @name HCREVISION - BCD representation of the version of the HCI specification that is implemented by the Host Controller (HC) */ +/*! @{ */ + +#define USBFSH_HCREVISION_REV_MASK (0xFFU) +#define USBFSH_HCREVISION_REV_SHIFT (0U) +/*! REV - Revision. + */ +#define USBFSH_HCREVISION_REV(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCREVISION_REV_SHIFT)) & USBFSH_HCREVISION_REV_MASK) +/*! @} */ + +/*! @name HCCONTROL - Defines the operating modes of the HC */ +/*! @{ */ + +#define USBFSH_HCCONTROL_CBSR_MASK (0x3U) +#define USBFSH_HCCONTROL_CBSR_SHIFT (0U) +/*! CBSR - ControlBulkServiceRatio. + */ +#define USBFSH_HCCONTROL_CBSR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_CBSR_SHIFT)) & USBFSH_HCCONTROL_CBSR_MASK) + +#define USBFSH_HCCONTROL_PLE_MASK (0x4U) +#define USBFSH_HCCONTROL_PLE_SHIFT (2U) +/*! PLE - PeriodicListEnable. + */ +#define USBFSH_HCCONTROL_PLE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_PLE_SHIFT)) & USBFSH_HCCONTROL_PLE_MASK) + +#define USBFSH_HCCONTROL_IE_MASK (0x8U) +#define USBFSH_HCCONTROL_IE_SHIFT (3U) +/*! IE - IsochronousEnable. + */ +#define USBFSH_HCCONTROL_IE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_IE_SHIFT)) & USBFSH_HCCONTROL_IE_MASK) + +#define USBFSH_HCCONTROL_CLE_MASK (0x10U) +#define USBFSH_HCCONTROL_CLE_SHIFT (4U) +/*! CLE - ControlListEnable. + */ +#define USBFSH_HCCONTROL_CLE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_CLE_SHIFT)) & USBFSH_HCCONTROL_CLE_MASK) + +#define USBFSH_HCCONTROL_BLE_MASK (0x20U) +#define USBFSH_HCCONTROL_BLE_SHIFT (5U) +/*! BLE - BulkListEnable This bit is set to enable the processing of the Bulk list in the next Frame. + */ +#define USBFSH_HCCONTROL_BLE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_BLE_SHIFT)) & USBFSH_HCCONTROL_BLE_MASK) + +#define USBFSH_HCCONTROL_HCFS_MASK (0xC0U) +#define USBFSH_HCCONTROL_HCFS_SHIFT (6U) +/*! HCFS - HostControllerFunctionalState for USB 00b: USBRESET 01b: USBRESUME 10b: USBOPERATIONAL + * 11b: USBSUSPEND A transition to USBOPERATIONAL from another state causes SOFgeneration to begin + * 1 ms later. + */ +#define USBFSH_HCCONTROL_HCFS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_HCFS_SHIFT)) & USBFSH_HCCONTROL_HCFS_MASK) + +#define USBFSH_HCCONTROL_IR_MASK (0x100U) +#define USBFSH_HCCONTROL_IR_SHIFT (8U) +/*! IR - InterruptRouting This bit determines the routing of interrupts generated by events registered in HcInterruptStatus. + */ +#define USBFSH_HCCONTROL_IR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_IR_SHIFT)) & USBFSH_HCCONTROL_IR_MASK) + +#define USBFSH_HCCONTROL_RWC_MASK (0x200U) +#define USBFSH_HCCONTROL_RWC_SHIFT (9U) +/*! RWC - RemoteWakeupConnected This bit indicates whether HC supports remote wake-up signaling. + */ +#define USBFSH_HCCONTROL_RWC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_RWC_SHIFT)) & USBFSH_HCCONTROL_RWC_MASK) + +#define USBFSH_HCCONTROL_RWE_MASK (0x400U) +#define USBFSH_HCCONTROL_RWE_SHIFT (10U) +/*! RWE - RemoteWakeupEnable This bit is used by HCD to enable or disable the remote wake-up feature + * upon the detection of upstream resume signaling. + */ +#define USBFSH_HCCONTROL_RWE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_RWE_SHIFT)) & USBFSH_HCCONTROL_RWE_MASK) +/*! @} */ + +/*! @name HCCOMMANDSTATUS - This register is used to receive the commands from the Host Controller Driver (HCD) */ +/*! @{ */ + +#define USBFSH_HCCOMMANDSTATUS_HCR_MASK (0x1U) +#define USBFSH_HCCOMMANDSTATUS_HCR_SHIFT (0U) +/*! HCR - HostControllerReset This bit is set by HCD to initiate a software reset of HC. + */ +#define USBFSH_HCCOMMANDSTATUS_HCR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_HCR_SHIFT)) & USBFSH_HCCOMMANDSTATUS_HCR_MASK) + +#define USBFSH_HCCOMMANDSTATUS_CLF_MASK (0x2U) +#define USBFSH_HCCOMMANDSTATUS_CLF_SHIFT (1U) +/*! CLF - ControlListFilled This bit is used to indicate whether there are any TDs on the Control list. + */ +#define USBFSH_HCCOMMANDSTATUS_CLF(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_CLF_SHIFT)) & USBFSH_HCCOMMANDSTATUS_CLF_MASK) + +#define USBFSH_HCCOMMANDSTATUS_BLF_MASK (0x4U) +#define USBFSH_HCCOMMANDSTATUS_BLF_SHIFT (2U) +/*! BLF - BulkListFilled This bit is used to indicate whether there are any TDs on the Bulk list. + */ +#define USBFSH_HCCOMMANDSTATUS_BLF(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_BLF_SHIFT)) & USBFSH_HCCOMMANDSTATUS_BLF_MASK) + +#define USBFSH_HCCOMMANDSTATUS_OCR_MASK (0x8U) +#define USBFSH_HCCOMMANDSTATUS_OCR_SHIFT (3U) +/*! OCR - OwnershipChangeRequest This bit is set by an OS HCD to request a change of control of the HC. + */ +#define USBFSH_HCCOMMANDSTATUS_OCR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_OCR_SHIFT)) & USBFSH_HCCOMMANDSTATUS_OCR_MASK) + +#define USBFSH_HCCOMMANDSTATUS_SOC_MASK (0xC0U) +#define USBFSH_HCCOMMANDSTATUS_SOC_SHIFT (6U) +/*! SOC - SchedulingOverrunCount These bits are incremented on each scheduling overrun error. + */ +#define USBFSH_HCCOMMANDSTATUS_SOC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_SOC_SHIFT)) & USBFSH_HCCOMMANDSTATUS_SOC_MASK) +/*! @} */ + +/*! @name HCINTERRUPTSTATUS - Indicates the status on various events that cause hardware interrupts by setting the appropriate bits */ +/*! @{ */ + +#define USBFSH_HCINTERRUPTSTATUS_SO_MASK (0x1U) +#define USBFSH_HCINTERRUPTSTATUS_SO_SHIFT (0U) +/*! SO - SchedulingOverrun This bit is set when the USB schedule for the current Frame overruns and + * after the update of HccaFrameNumber. + */ +#define USBFSH_HCINTERRUPTSTATUS_SO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_SO_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_SO_MASK) + +#define USBFSH_HCINTERRUPTSTATUS_WDH_MASK (0x2U) +#define USBFSH_HCINTERRUPTSTATUS_WDH_SHIFT (1U) +/*! WDH - WritebackDoneHead This bit is set immediately after HC has written HcDoneHead to HccaDoneHead. + */ +#define USBFSH_HCINTERRUPTSTATUS_WDH(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_WDH_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_WDH_MASK) + +#define USBFSH_HCINTERRUPTSTATUS_SF_MASK (0x4U) +#define USBFSH_HCINTERRUPTSTATUS_SF_SHIFT (2U) +/*! SF - StartofFrame This bit is set by HC at each start of a frame and after the update of HccaFrameNumber. + */ +#define USBFSH_HCINTERRUPTSTATUS_SF(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_SF_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_SF_MASK) + +#define USBFSH_HCINTERRUPTSTATUS_RD_MASK (0x8U) +#define USBFSH_HCINTERRUPTSTATUS_RD_SHIFT (3U) +/*! RD - ResumeDetected This bit is set when HC detects that a device on the USB is asserting resume signaling. + */ +#define USBFSH_HCINTERRUPTSTATUS_RD(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_RD_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_RD_MASK) + +#define USBFSH_HCINTERRUPTSTATUS_UE_MASK (0x10U) +#define USBFSH_HCINTERRUPTSTATUS_UE_SHIFT (4U) +/*! UE - UnrecoverableError This bit is set when HC detects a system error not related to USB. + */ +#define USBFSH_HCINTERRUPTSTATUS_UE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_UE_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_UE_MASK) + +#define USBFSH_HCINTERRUPTSTATUS_FNO_MASK (0x20U) +#define USBFSH_HCINTERRUPTSTATUS_FNO_SHIFT (5U) +/*! FNO - FrameNumberOverflow This bit is set when the MSb of HcFmNumber (bit 15) changes value, + * from 0 to 1 or from 1 to 0, and after HccaFrameNumber has been updated. + */ +#define USBFSH_HCINTERRUPTSTATUS_FNO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_FNO_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_FNO_MASK) + +#define USBFSH_HCINTERRUPTSTATUS_RHSC_MASK (0x40U) +#define USBFSH_HCINTERRUPTSTATUS_RHSC_SHIFT (6U) +/*! RHSC - RootHubStatusChange This bit is set when the content of HcRhStatus or the content of any + * of HcRhPortStatus[NumberofDownstreamPort] has changed. + */ +#define USBFSH_HCINTERRUPTSTATUS_RHSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_RHSC_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_RHSC_MASK) + +#define USBFSH_HCINTERRUPTSTATUS_OC_MASK (0xFFFFFC00U) +#define USBFSH_HCINTERRUPTSTATUS_OC_SHIFT (10U) +/*! OC - OwnershipChange This bit is set by HC when HCD sets the OwnershipChangeRequest field in HcCommandStatus. + */ +#define USBFSH_HCINTERRUPTSTATUS_OC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_OC_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_OC_MASK) +/*! @} */ + +/*! @name HCINTERRUPTENABLE - Controls the bits in the HcInterruptStatus register and indicates which events will generate a hardware interrupt */ +/*! @{ */ + +#define USBFSH_HCINTERRUPTENABLE_SO_MASK (0x1U) +#define USBFSH_HCINTERRUPTENABLE_SO_SHIFT (0U) +/*! SO - Scheduling Overrun interrupt. + */ +#define USBFSH_HCINTERRUPTENABLE_SO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_SO_SHIFT)) & USBFSH_HCINTERRUPTENABLE_SO_MASK) + +#define USBFSH_HCINTERRUPTENABLE_WDH_MASK (0x2U) +#define USBFSH_HCINTERRUPTENABLE_WDH_SHIFT (1U) +/*! WDH - HcDoneHead Writeback interrupt. + */ +#define USBFSH_HCINTERRUPTENABLE_WDH(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_WDH_SHIFT)) & USBFSH_HCINTERRUPTENABLE_WDH_MASK) + +#define USBFSH_HCINTERRUPTENABLE_SF_MASK (0x4U) +#define USBFSH_HCINTERRUPTENABLE_SF_SHIFT (2U) +/*! SF - Start of Frame interrupt. + */ +#define USBFSH_HCINTERRUPTENABLE_SF(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_SF_SHIFT)) & USBFSH_HCINTERRUPTENABLE_SF_MASK) + +#define USBFSH_HCINTERRUPTENABLE_RD_MASK (0x8U) +#define USBFSH_HCINTERRUPTENABLE_RD_SHIFT (3U) +/*! RD - Resume Detect interrupt. + */ +#define USBFSH_HCINTERRUPTENABLE_RD(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_RD_SHIFT)) & USBFSH_HCINTERRUPTENABLE_RD_MASK) + +#define USBFSH_HCINTERRUPTENABLE_UE_MASK (0x10U) +#define USBFSH_HCINTERRUPTENABLE_UE_SHIFT (4U) +/*! UE - Unrecoverable Error interrupt. + */ +#define USBFSH_HCINTERRUPTENABLE_UE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_UE_SHIFT)) & USBFSH_HCINTERRUPTENABLE_UE_MASK) + +#define USBFSH_HCINTERRUPTENABLE_FNO_MASK (0x20U) +#define USBFSH_HCINTERRUPTENABLE_FNO_SHIFT (5U) +/*! FNO - Frame Number Overflow interrupt. + */ +#define USBFSH_HCINTERRUPTENABLE_FNO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_FNO_SHIFT)) & USBFSH_HCINTERRUPTENABLE_FNO_MASK) + +#define USBFSH_HCINTERRUPTENABLE_RHSC_MASK (0x40U) +#define USBFSH_HCINTERRUPTENABLE_RHSC_SHIFT (6U) +/*! RHSC - Root Hub Status Change interrupt. + */ +#define USBFSH_HCINTERRUPTENABLE_RHSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_RHSC_SHIFT)) & USBFSH_HCINTERRUPTENABLE_RHSC_MASK) + +#define USBFSH_HCINTERRUPTENABLE_OC_MASK (0x40000000U) +#define USBFSH_HCINTERRUPTENABLE_OC_SHIFT (30U) +/*! OC - Ownership Change interrupt. + */ +#define USBFSH_HCINTERRUPTENABLE_OC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_OC_SHIFT)) & USBFSH_HCINTERRUPTENABLE_OC_MASK) + +#define USBFSH_HCINTERRUPTENABLE_MIE_MASK (0x80000000U) +#define USBFSH_HCINTERRUPTENABLE_MIE_SHIFT (31U) +/*! MIE - Master Interrupt Enable. + */ +#define USBFSH_HCINTERRUPTENABLE_MIE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_MIE_SHIFT)) & USBFSH_HCINTERRUPTENABLE_MIE_MASK) +/*! @} */ + +/*! @name HCINTERRUPTDISABLE - The bits in this register are used to disable corresponding bits in the HCInterruptStatus register and in turn disable that event leading to hardware interrupt */ +/*! @{ */ + +#define USBFSH_HCINTERRUPTDISABLE_SO_MASK (0x1U) +#define USBFSH_HCINTERRUPTDISABLE_SO_SHIFT (0U) +/*! SO - Scheduling Overrun interrupt. + */ +#define USBFSH_HCINTERRUPTDISABLE_SO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_SO_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_SO_MASK) + +#define USBFSH_HCINTERRUPTDISABLE_WDH_MASK (0x2U) +#define USBFSH_HCINTERRUPTDISABLE_WDH_SHIFT (1U) +/*! WDH - HcDoneHead Writeback interrupt. + */ +#define USBFSH_HCINTERRUPTDISABLE_WDH(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_WDH_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_WDH_MASK) + +#define USBFSH_HCINTERRUPTDISABLE_SF_MASK (0x4U) +#define USBFSH_HCINTERRUPTDISABLE_SF_SHIFT (2U) +/*! SF - Start of Frame interrupt. + */ +#define USBFSH_HCINTERRUPTDISABLE_SF(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_SF_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_SF_MASK) + +#define USBFSH_HCINTERRUPTDISABLE_RD_MASK (0x8U) +#define USBFSH_HCINTERRUPTDISABLE_RD_SHIFT (3U) +/*! RD - Resume Detect interrupt. + */ +#define USBFSH_HCINTERRUPTDISABLE_RD(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_RD_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_RD_MASK) + +#define USBFSH_HCINTERRUPTDISABLE_UE_MASK (0x10U) +#define USBFSH_HCINTERRUPTDISABLE_UE_SHIFT (4U) +/*! UE - Unrecoverable Error interrupt. + */ +#define USBFSH_HCINTERRUPTDISABLE_UE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_UE_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_UE_MASK) + +#define USBFSH_HCINTERRUPTDISABLE_FNO_MASK (0x20U) +#define USBFSH_HCINTERRUPTDISABLE_FNO_SHIFT (5U) +/*! FNO - Frame Number Overflow interrupt. + */ +#define USBFSH_HCINTERRUPTDISABLE_FNO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_FNO_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_FNO_MASK) + +#define USBFSH_HCINTERRUPTDISABLE_RHSC_MASK (0x40U) +#define USBFSH_HCINTERRUPTDISABLE_RHSC_SHIFT (6U) +/*! RHSC - Root Hub Status Change interrupt. + */ +#define USBFSH_HCINTERRUPTDISABLE_RHSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_RHSC_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_RHSC_MASK) + +#define USBFSH_HCINTERRUPTDISABLE_OC_MASK (0x40000000U) +#define USBFSH_HCINTERRUPTDISABLE_OC_SHIFT (30U) +/*! OC - Ownership Change interrupt. + */ +#define USBFSH_HCINTERRUPTDISABLE_OC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_OC_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_OC_MASK) + +#define USBFSH_HCINTERRUPTDISABLE_MIE_MASK (0x80000000U) +#define USBFSH_HCINTERRUPTDISABLE_MIE_SHIFT (31U) +/*! MIE - A 0 written to this field is ignored by HC. + */ +#define USBFSH_HCINTERRUPTDISABLE_MIE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_MIE_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_MIE_MASK) +/*! @} */ + +/*! @name HCHCCA - Contains the physical address of the host controller communication area */ +/*! @{ */ + +#define USBFSH_HCHCCA_HCCA_MASK (0xFFFFFF00U) +#define USBFSH_HCHCCA_HCCA_SHIFT (8U) +/*! HCCA - Base address of the Host Controller Communication Area. + */ +#define USBFSH_HCHCCA_HCCA(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCHCCA_HCCA_SHIFT)) & USBFSH_HCHCCA_HCCA_MASK) +/*! @} */ + +/*! @name HCPERIODCURRENTED - Contains the physical address of the current isochronous or interrupt endpoint descriptor */ +/*! @{ */ + +#define USBFSH_HCPERIODCURRENTED_PCED_MASK (0xFFFFFFF0U) +#define USBFSH_HCPERIODCURRENTED_PCED_SHIFT (4U) +/*! PCED - The content of this register is updated by HC after a periodic ED is processed. + */ +#define USBFSH_HCPERIODCURRENTED_PCED(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCPERIODCURRENTED_PCED_SHIFT)) & USBFSH_HCPERIODCURRENTED_PCED_MASK) +/*! @} */ + +/*! @name HCCONTROLHEADED - Contains the physical address of the first endpoint descriptor of the control list */ +/*! @{ */ + +#define USBFSH_HCCONTROLHEADED_CHED_MASK (0xFFFFFFF0U) +#define USBFSH_HCCONTROLHEADED_CHED_SHIFT (4U) +/*! CHED - HC traverses the Control list starting with the HcControlHeadED pointer. + */ +#define USBFSH_HCCONTROLHEADED_CHED(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROLHEADED_CHED_SHIFT)) & USBFSH_HCCONTROLHEADED_CHED_MASK) +/*! @} */ + +/*! @name HCCONTROLCURRENTED - Contains the physical address of the current endpoint descriptor of the control list */ +/*! @{ */ + +#define USBFSH_HCCONTROLCURRENTED_CCED_MASK (0xFFFFFFF0U) +#define USBFSH_HCCONTROLCURRENTED_CCED_SHIFT (4U) +/*! CCED - ControlCurrentED. + */ +#define USBFSH_HCCONTROLCURRENTED_CCED(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROLCURRENTED_CCED_SHIFT)) & USBFSH_HCCONTROLCURRENTED_CCED_MASK) +/*! @} */ + +/*! @name HCBULKHEADED - Contains the physical address of the first endpoint descriptor of the bulk list */ +/*! @{ */ + +#define USBFSH_HCBULKHEADED_BHED_MASK (0xFFFFFFF0U) +#define USBFSH_HCBULKHEADED_BHED_SHIFT (4U) +/*! BHED - BulkHeadED HC traverses the bulk list starting with the HcBulkHeadED pointer. + */ +#define USBFSH_HCBULKHEADED_BHED(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCBULKHEADED_BHED_SHIFT)) & USBFSH_HCBULKHEADED_BHED_MASK) +/*! @} */ + +/*! @name HCBULKCURRENTED - Contains the physical address of the current endpoint descriptor of the bulk list */ +/*! @{ */ + +#define USBFSH_HCBULKCURRENTED_BCED_MASK (0xFFFFFFF0U) +#define USBFSH_HCBULKCURRENTED_BCED_SHIFT (4U) +/*! BCED - BulkCurrentED This is advanced to the next ED after the HC has served the current one. + */ +#define USBFSH_HCBULKCURRENTED_BCED(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCBULKCURRENTED_BCED_SHIFT)) & USBFSH_HCBULKCURRENTED_BCED_MASK) +/*! @} */ + +/*! @name HCDONEHEAD - Contains the physical address of the last transfer descriptor added to the 'Done' queue */ +/*! @{ */ + +#define USBFSH_HCDONEHEAD_DH_MASK (0xFFFFFFF0U) +#define USBFSH_HCDONEHEAD_DH_SHIFT (4U) +/*! DH - DoneHead When a TD is completed, HC writes the content of HcDoneHead to the NextTD field of the TD. + */ +#define USBFSH_HCDONEHEAD_DH(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCDONEHEAD_DH_SHIFT)) & USBFSH_HCDONEHEAD_DH_MASK) +/*! @} */ + +/*! @name HCFMINTERVAL - Defines the bit time interval in a frame and the full speed maximum packet size which would not cause an overrun */ +/*! @{ */ + +#define USBFSH_HCFMINTERVAL_FI_MASK (0x3FFFU) +#define USBFSH_HCFMINTERVAL_FI_SHIFT (0U) +/*! FI - FrameInterval This specifies the interval between two consecutive SOFs in bit times. + */ +#define USBFSH_HCFMINTERVAL_FI(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMINTERVAL_FI_SHIFT)) & USBFSH_HCFMINTERVAL_FI_MASK) + +#define USBFSH_HCFMINTERVAL_FSMPS_MASK (0x7FFF0000U) +#define USBFSH_HCFMINTERVAL_FSMPS_SHIFT (16U) +/*! FSMPS - FSLargestDataPacket This field specifies a value which is loaded into the Largest Data + * Packet Counter at the beginning of each frame. + */ +#define USBFSH_HCFMINTERVAL_FSMPS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMINTERVAL_FSMPS_SHIFT)) & USBFSH_HCFMINTERVAL_FSMPS_MASK) + +#define USBFSH_HCFMINTERVAL_FIT_MASK (0x80000000U) +#define USBFSH_HCFMINTERVAL_FIT_SHIFT (31U) +/*! FIT - FrameIntervalToggle HCD toggles this bit whenever it loads a new value to FrameInterval. + */ +#define USBFSH_HCFMINTERVAL_FIT(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMINTERVAL_FIT_SHIFT)) & USBFSH_HCFMINTERVAL_FIT_MASK) +/*! @} */ + +/*! @name HCFMREMAINING - A 14-bit counter showing the bit time remaining in the current frame */ +/*! @{ */ + +#define USBFSH_HCFMREMAINING_FR_MASK (0x3FFFU) +#define USBFSH_HCFMREMAINING_FR_SHIFT (0U) +/*! FR - FrameRemaining This counter is decremented at each bit time. + */ +#define USBFSH_HCFMREMAINING_FR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMREMAINING_FR_SHIFT)) & USBFSH_HCFMREMAINING_FR_MASK) + +#define USBFSH_HCFMREMAINING_FRT_MASK (0x80000000U) +#define USBFSH_HCFMREMAINING_FRT_SHIFT (31U) +/*! FRT - FrameRemainingToggle This bit is loaded from the FrameIntervalToggle field of HcFmInterval + * whenever FrameRemaining reaches 0. + */ +#define USBFSH_HCFMREMAINING_FRT(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMREMAINING_FRT_SHIFT)) & USBFSH_HCFMREMAINING_FRT_MASK) +/*! @} */ + +/*! @name HCFMNUMBER - Contains a 16-bit counter and provides the timing reference among events happening in the HC and the HCD */ +/*! @{ */ + +#define USBFSH_HCFMNUMBER_FN_MASK (0xFFFFU) +#define USBFSH_HCFMNUMBER_FN_SHIFT (0U) +/*! FN - FrameNumber This is incremented when HcFmRemaining is re-loaded. + */ +#define USBFSH_HCFMNUMBER_FN(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMNUMBER_FN_SHIFT)) & USBFSH_HCFMNUMBER_FN_MASK) +/*! @} */ + +/*! @name HCPERIODICSTART - Contains a programmable 14-bit value which determines the earliest time HC should start processing a periodic list */ +/*! @{ */ + +#define USBFSH_HCPERIODICSTART_PS_MASK (0x3FFFU) +#define USBFSH_HCPERIODICSTART_PS_SHIFT (0U) +/*! PS - PeriodicStart After a hardware reset, this field is cleared and then set by HCD during the HC initialization. + */ +#define USBFSH_HCPERIODICSTART_PS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCPERIODICSTART_PS_SHIFT)) & USBFSH_HCPERIODICSTART_PS_MASK) +/*! @} */ + +/*! @name HCLSTHRESHOLD - Contains 11-bit value which is used by the HC to determine whether to commit to transfer a maximum of 8-byte LS packet before EOF */ +/*! @{ */ + +#define USBFSH_HCLSTHRESHOLD_LST_MASK (0xFFFU) +#define USBFSH_HCLSTHRESHOLD_LST_SHIFT (0U) +/*! LST - LSThreshold This field contains a value which is compared to the FrameRemaining field + * prior to initiating a Low Speed transaction. + */ +#define USBFSH_HCLSTHRESHOLD_LST(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCLSTHRESHOLD_LST_SHIFT)) & USBFSH_HCLSTHRESHOLD_LST_MASK) +/*! @} */ + +/*! @name HCRHDESCRIPTORA - First of the two registers which describes the characteristics of the root hub */ +/*! @{ */ + +#define USBFSH_HCRHDESCRIPTORA_NDP_MASK (0xFFU) +#define USBFSH_HCRHDESCRIPTORA_NDP_SHIFT (0U) +/*! NDP - NumberDownstreamPorts These bits specify the number of downstream ports supported by the root hub. + */ +#define USBFSH_HCRHDESCRIPTORA_NDP(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_NDP_SHIFT)) & USBFSH_HCRHDESCRIPTORA_NDP_MASK) + +#define USBFSH_HCRHDESCRIPTORA_PSM_MASK (0x100U) +#define USBFSH_HCRHDESCRIPTORA_PSM_SHIFT (8U) +/*! PSM - PowerSwitchingMode This bit is used to specify how the power switching of the root hub ports is controlled. + */ +#define USBFSH_HCRHDESCRIPTORA_PSM(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_PSM_SHIFT)) & USBFSH_HCRHDESCRIPTORA_PSM_MASK) + +#define USBFSH_HCRHDESCRIPTORA_NPS_MASK (0x200U) +#define USBFSH_HCRHDESCRIPTORA_NPS_SHIFT (9U) +/*! NPS - NoPowerSwitching These bits are used to specify whether power switching is supported or port are always powered. + */ +#define USBFSH_HCRHDESCRIPTORA_NPS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_NPS_SHIFT)) & USBFSH_HCRHDESCRIPTORA_NPS_MASK) + +#define USBFSH_HCRHDESCRIPTORA_DT_MASK (0x400U) +#define USBFSH_HCRHDESCRIPTORA_DT_SHIFT (10U) +/*! DT - DeviceType This bit specifies that the root hub is not a compound device. + */ +#define USBFSH_HCRHDESCRIPTORA_DT(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_DT_SHIFT)) & USBFSH_HCRHDESCRIPTORA_DT_MASK) + +#define USBFSH_HCRHDESCRIPTORA_OCPM_MASK (0x800U) +#define USBFSH_HCRHDESCRIPTORA_OCPM_SHIFT (11U) +/*! OCPM - OverCurrentProtectionMode This bit describes how the overcurrent status for the root hub ports are reported. + */ +#define USBFSH_HCRHDESCRIPTORA_OCPM(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_OCPM_SHIFT)) & USBFSH_HCRHDESCRIPTORA_OCPM_MASK) + +#define USBFSH_HCRHDESCRIPTORA_NOCP_MASK (0x1000U) +#define USBFSH_HCRHDESCRIPTORA_NOCP_SHIFT (12U) +/*! NOCP - NoOverCurrentProtection This bit describes how the overcurrent status for the root hub ports are reported. + */ +#define USBFSH_HCRHDESCRIPTORA_NOCP(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_NOCP_SHIFT)) & USBFSH_HCRHDESCRIPTORA_NOCP_MASK) + +#define USBFSH_HCRHDESCRIPTORA_POTPGT_MASK (0xFF000000U) +#define USBFSH_HCRHDESCRIPTORA_POTPGT_SHIFT (24U) +/*! POTPGT - PowerOnToPowerGoodTime This byte specifies the duration the HCD has to wait before + * accessing a powered-on port of the root hub. + */ +#define USBFSH_HCRHDESCRIPTORA_POTPGT(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_POTPGT_SHIFT)) & USBFSH_HCRHDESCRIPTORA_POTPGT_MASK) +/*! @} */ + +/*! @name HCRHDESCRIPTORB - Second of the two registers which describes the characteristics of the Root Hub */ +/*! @{ */ + +#define USBFSH_HCRHDESCRIPTORB_DR_MASK (0xFFFFU) +#define USBFSH_HCRHDESCRIPTORB_DR_SHIFT (0U) +/*! DR - DeviceRemovable Each bit is dedicated to a port of the Root Hub. + */ +#define USBFSH_HCRHDESCRIPTORB_DR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORB_DR_SHIFT)) & USBFSH_HCRHDESCRIPTORB_DR_MASK) + +#define USBFSH_HCRHDESCRIPTORB_PPCM_MASK (0xFFFF0000U) +#define USBFSH_HCRHDESCRIPTORB_PPCM_SHIFT (16U) +/*! PPCM - PortPowerControlMask Each bit indicates if a port is affected by a global power control + * command when PowerSwitchingMode is set. + */ +#define USBFSH_HCRHDESCRIPTORB_PPCM(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORB_PPCM_SHIFT)) & USBFSH_HCRHDESCRIPTORB_PPCM_MASK) +/*! @} */ + +/*! @name HCRHSTATUS - This register is divided into two parts */ +/*! @{ */ + +#define USBFSH_HCRHSTATUS_LPS_MASK (0x1U) +#define USBFSH_HCRHSTATUS_LPS_SHIFT (0U) +/*! LPS - (read) LocalPowerStatus The Root Hub does not support the local power status feature; + * thus, this bit is always read as 0. + */ +#define USBFSH_HCRHSTATUS_LPS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_LPS_SHIFT)) & USBFSH_HCRHSTATUS_LPS_MASK) + +#define USBFSH_HCRHSTATUS_OCI_MASK (0x2U) +#define USBFSH_HCRHSTATUS_OCI_SHIFT (1U) +/*! OCI - OverCurrentIndicator This bit reports overcurrent conditions when the global reporting is implemented. + */ +#define USBFSH_HCRHSTATUS_OCI(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_OCI_SHIFT)) & USBFSH_HCRHSTATUS_OCI_MASK) + +#define USBFSH_HCRHSTATUS_DRWE_MASK (0x8000U) +#define USBFSH_HCRHSTATUS_DRWE_SHIFT (15U) +/*! DRWE - (read) DeviceRemoteWakeupEnable This bit enables a ConnectStatusChange bit as a resume + * event, causing a USBSUSPEND to USBRESUME state transition and setting the ResumeDetected + * interrupt. + */ +#define USBFSH_HCRHSTATUS_DRWE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_DRWE_SHIFT)) & USBFSH_HCRHSTATUS_DRWE_MASK) + +#define USBFSH_HCRHSTATUS_LPSC_MASK (0x10000U) +#define USBFSH_HCRHSTATUS_LPSC_SHIFT (16U) +/*! LPSC - (read) LocalPowerStatusChange The root hub does not support the local power status feature. + */ +#define USBFSH_HCRHSTATUS_LPSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_LPSC_SHIFT)) & USBFSH_HCRHSTATUS_LPSC_MASK) + +#define USBFSH_HCRHSTATUS_OCIC_MASK (0x20000U) +#define USBFSH_HCRHSTATUS_OCIC_SHIFT (17U) +/*! OCIC - OverCurrentIndicatorChange This bit is set by hardware when a change has occurred to the OCI field of this register. + */ +#define USBFSH_HCRHSTATUS_OCIC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_OCIC_SHIFT)) & USBFSH_HCRHSTATUS_OCIC_MASK) + +#define USBFSH_HCRHSTATUS_CRWE_MASK (0x80000000U) +#define USBFSH_HCRHSTATUS_CRWE_SHIFT (31U) +/*! CRWE - (write) ClearRemoteWakeupEnable Writing a 1 clears DeviceRemoveWakeupEnable. + */ +#define USBFSH_HCRHSTATUS_CRWE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_CRWE_SHIFT)) & USBFSH_HCRHSTATUS_CRWE_MASK) +/*! @} */ + +/*! @name HCRHPORTSTATUS - Controls and reports the port events on a per-port basis */ +/*! @{ */ + +#define USBFSH_HCRHPORTSTATUS_CCS_MASK (0x1U) +#define USBFSH_HCRHPORTSTATUS_CCS_SHIFT (0U) +/*! CCS - (read) CurrentConnectStatus This bit reflects the current state of the downstream port. + */ +#define USBFSH_HCRHPORTSTATUS_CCS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_CCS_SHIFT)) & USBFSH_HCRHPORTSTATUS_CCS_MASK) + +#define USBFSH_HCRHPORTSTATUS_PES_MASK (0x2U) +#define USBFSH_HCRHPORTSTATUS_PES_SHIFT (1U) +/*! PES - (read) PortEnableStatus This bit indicates whether the port is enabled or disabled. + */ +#define USBFSH_HCRHPORTSTATUS_PES(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PES_SHIFT)) & USBFSH_HCRHPORTSTATUS_PES_MASK) + +#define USBFSH_HCRHPORTSTATUS_PSS_MASK (0x4U) +#define USBFSH_HCRHPORTSTATUS_PSS_SHIFT (2U) +/*! PSS - (read) PortSuspendStatus This bit indicates the port is suspended or in the resume sequence. + */ +#define USBFSH_HCRHPORTSTATUS_PSS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PSS_SHIFT)) & USBFSH_HCRHPORTSTATUS_PSS_MASK) + +#define USBFSH_HCRHPORTSTATUS_POCI_MASK (0x8U) +#define USBFSH_HCRHPORTSTATUS_POCI_SHIFT (3U) +/*! POCI - (read) PortOverCurrentIndicator This bit is only valid when the Root Hub is configured in + * such a way that overcurrent conditions are reported on a per-port basis. + */ +#define USBFSH_HCRHPORTSTATUS_POCI(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_POCI_SHIFT)) & USBFSH_HCRHPORTSTATUS_POCI_MASK) + +#define USBFSH_HCRHPORTSTATUS_PRS_MASK (0x10U) +#define USBFSH_HCRHPORTSTATUS_PRS_SHIFT (4U) +/*! PRS - (read) PortResetStatus When this bit is set by a write to SetPortReset, port reset signaling is asserted. + */ +#define USBFSH_HCRHPORTSTATUS_PRS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PRS_SHIFT)) & USBFSH_HCRHPORTSTATUS_PRS_MASK) + +#define USBFSH_HCRHPORTSTATUS_PPS_MASK (0x100U) +#define USBFSH_HCRHPORTSTATUS_PPS_SHIFT (8U) +/*! PPS - (read) PortPowerStatus This bit reflects the porta's power status, regardless of the type + * of power switching implemented. + */ +#define USBFSH_HCRHPORTSTATUS_PPS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PPS_SHIFT)) & USBFSH_HCRHPORTSTATUS_PPS_MASK) + +#define USBFSH_HCRHPORTSTATUS_LSDA_MASK (0x200U) +#define USBFSH_HCRHPORTSTATUS_LSDA_SHIFT (9U) +/*! LSDA - (read) LowSpeedDeviceAttached This bit indicates the speed of the device attached to this port. + */ +#define USBFSH_HCRHPORTSTATUS_LSDA(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_LSDA_SHIFT)) & USBFSH_HCRHPORTSTATUS_LSDA_MASK) + +#define USBFSH_HCRHPORTSTATUS_CSC_MASK (0x10000U) +#define USBFSH_HCRHPORTSTATUS_CSC_SHIFT (16U) +/*! CSC - ConnectStatusChange This bit is set whenever a connect or disconnect event occurs. + */ +#define USBFSH_HCRHPORTSTATUS_CSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_CSC_SHIFT)) & USBFSH_HCRHPORTSTATUS_CSC_MASK) + +#define USBFSH_HCRHPORTSTATUS_PESC_MASK (0x20000U) +#define USBFSH_HCRHPORTSTATUS_PESC_SHIFT (17U) +/*! PESC - PortEnableStatusChange This bit is set when hardware events cause the PortEnableStatus bit to be cleared. + */ +#define USBFSH_HCRHPORTSTATUS_PESC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PESC_SHIFT)) & USBFSH_HCRHPORTSTATUS_PESC_MASK) + +#define USBFSH_HCRHPORTSTATUS_PSSC_MASK (0x40000U) +#define USBFSH_HCRHPORTSTATUS_PSSC_SHIFT (18U) +/*! PSSC - PortSuspendStatusChange This bit is set when the full resume sequence is completed. + */ +#define USBFSH_HCRHPORTSTATUS_PSSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PSSC_SHIFT)) & USBFSH_HCRHPORTSTATUS_PSSC_MASK) + +#define USBFSH_HCRHPORTSTATUS_OCIC_MASK (0x80000U) +#define USBFSH_HCRHPORTSTATUS_OCIC_SHIFT (19U) +/*! OCIC - PortOverCurrentIndicatorChange This bit is valid only if overcurrent conditions are reported on a per-port basis. + */ +#define USBFSH_HCRHPORTSTATUS_OCIC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_OCIC_SHIFT)) & USBFSH_HCRHPORTSTATUS_OCIC_MASK) + +#define USBFSH_HCRHPORTSTATUS_PRSC_MASK (0x100000U) +#define USBFSH_HCRHPORTSTATUS_PRSC_SHIFT (20U) +/*! PRSC - PortResetStatusChange This bit is set at the end of the 10 ms port reset signal. + */ +#define USBFSH_HCRHPORTSTATUS_PRSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PRSC_SHIFT)) & USBFSH_HCRHPORTSTATUS_PRSC_MASK) +/*! @} */ + +/*! @name PORTMODE - Controls the port if it is attached to the host block or the device block */ +/*! @{ */ + +#define USBFSH_PORTMODE_ID_MASK (0x1U) +#define USBFSH_PORTMODE_ID_SHIFT (0U) +/*! ID - Port ID pin value. + */ +#define USBFSH_PORTMODE_ID(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_PORTMODE_ID_SHIFT)) & USBFSH_PORTMODE_ID_MASK) + +#define USBFSH_PORTMODE_ID_EN_MASK (0x100U) +#define USBFSH_PORTMODE_ID_EN_SHIFT (8U) +/*! ID_EN - Port ID pin pull-up enable. + */ +#define USBFSH_PORTMODE_ID_EN(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_PORTMODE_ID_EN_SHIFT)) & USBFSH_PORTMODE_ID_EN_MASK) + +#define USBFSH_PORTMODE_DEV_ENABLE_MASK (0x10000U) +#define USBFSH_PORTMODE_DEV_ENABLE_SHIFT (16U) +/*! DEV_ENABLE - 1: device 0: host. + */ +#define USBFSH_PORTMODE_DEV_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_PORTMODE_DEV_ENABLE_SHIFT)) & USBFSH_PORTMODE_DEV_ENABLE_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group USBFSH_Register_Masks */ + + +/* USBFSH - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral USBFSH base address */ + #define USBFSH_BASE (0x500A2000u) + /** Peripheral USBFSH base address */ + #define USBFSH_BASE_NS (0x400A2000u) + /** Peripheral USBFSH base pointer */ + #define USBFSH ((USBFSH_Type *)USBFSH_BASE) + /** Peripheral USBFSH base pointer */ + #define USBFSH_NS ((USBFSH_Type *)USBFSH_BASE_NS) + /** Array initializer of USBFSH peripheral base addresses */ + #define USBFSH_BASE_ADDRS { USBFSH_BASE } + /** Array initializer of USBFSH peripheral base pointers */ + #define USBFSH_BASE_PTRS { USBFSH } + /** Array initializer of USBFSH peripheral base addresses */ + #define USBFSH_BASE_ADDRS_NS { USBFSH_BASE_NS } + /** Array initializer of USBFSH peripheral base pointers */ + #define USBFSH_BASE_PTRS_NS { USBFSH_NS } +#else + /** Peripheral USBFSH base address */ + #define USBFSH_BASE (0x400A2000u) + /** Peripheral USBFSH base pointer */ + #define USBFSH ((USBFSH_Type *)USBFSH_BASE) + /** Array initializer of USBFSH peripheral base addresses */ + #define USBFSH_BASE_ADDRS { USBFSH_BASE } + /** Array initializer of USBFSH peripheral base pointers */ + #define USBFSH_BASE_PTRS { USBFSH } +#endif +/** Interrupt vectors for the USBFSH peripheral type */ +#define USBFSH_IRQS { USB0_IRQn } +#define USBFSH_NEEDCLK_IRQS { USB0_NEEDCLK_IRQn } + +/*! + * @} + */ /* end of group USBFSH_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- USBHSD Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USBHSD_Peripheral_Access_Layer USBHSD Peripheral Access Layer + * @{ + */ + +/** USBHSD - Register Layout Typedef */ +typedef struct { + __IO uint32_t DEVCMDSTAT; /**< USB Device Command/Status register, offset: 0x0 */ + __I uint32_t INFO; /**< USB Info register, offset: 0x4 */ + __IO uint32_t EPLISTSTART; /**< USB EP Command/Status List start address, offset: 0x8 */ + __IO uint32_t DATABUFSTART; /**< USB Data buffer start address, offset: 0xC */ + __IO uint32_t LPM; /**< USB Link Power Management register, offset: 0x10 */ + __IO uint32_t EPSKIP; /**< USB Endpoint skip, offset: 0x14 */ + __IO uint32_t EPINUSE; /**< USB Endpoint Buffer in use, offset: 0x18 */ + __IO uint32_t EPBUFCFG; /**< USB Endpoint Buffer Configuration register, offset: 0x1C */ + __IO uint32_t INTSTAT; /**< USB interrupt status register, offset: 0x20 */ + __IO uint32_t INTEN; /**< USB interrupt enable register, offset: 0x24 */ + __IO uint32_t INTSETSTAT; /**< USB set interrupt status register, offset: 0x28 */ + uint8_t RESERVED_0[8]; + __I uint32_t EPTOGGLE; /**< USB Endpoint toggle register, offset: 0x34 */ +} USBHSD_Type; + +/* ---------------------------------------------------------------------------- + -- USBHSD Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USBHSD_Register_Masks USBHSD Register Masks + * @{ + */ + +/*! @name DEVCMDSTAT - USB Device Command/Status register */ +/*! @{ */ + +#define USBHSD_DEVCMDSTAT_DEV_ADDR_MASK (0x7FU) +#define USBHSD_DEVCMDSTAT_DEV_ADDR_SHIFT (0U) +/*! DEV_ADDR - USB device address. + */ +#define USBHSD_DEVCMDSTAT_DEV_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DEV_ADDR_SHIFT)) & USBHSD_DEVCMDSTAT_DEV_ADDR_MASK) + +#define USBHSD_DEVCMDSTAT_DEV_EN_MASK (0x80U) +#define USBHSD_DEVCMDSTAT_DEV_EN_SHIFT (7U) +/*! DEV_EN - USB device enable. + */ +#define USBHSD_DEVCMDSTAT_DEV_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DEV_EN_SHIFT)) & USBHSD_DEVCMDSTAT_DEV_EN_MASK) + +#define USBHSD_DEVCMDSTAT_SETUP_MASK (0x100U) +#define USBHSD_DEVCMDSTAT_SETUP_SHIFT (8U) +/*! SETUP - SETUP token received. + */ +#define USBHSD_DEVCMDSTAT_SETUP(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_SETUP_SHIFT)) & USBHSD_DEVCMDSTAT_SETUP_MASK) + +#define USBHSD_DEVCMDSTAT_FORCE_NEEDCLK_MASK (0x200U) +#define USBHSD_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT (9U) +/*! FORCE_NEEDCLK - Forces the NEEDCLK output to always be on:. + */ +#define USBHSD_DEVCMDSTAT_FORCE_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT)) & USBHSD_DEVCMDSTAT_FORCE_NEEDCLK_MASK) + +#define USBHSD_DEVCMDSTAT_LPM_SUP_MASK (0x800U) +#define USBHSD_DEVCMDSTAT_LPM_SUP_SHIFT (11U) +/*! LPM_SUP - LPM Supported:. + */ +#define USBHSD_DEVCMDSTAT_LPM_SUP(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_LPM_SUP_SHIFT)) & USBHSD_DEVCMDSTAT_LPM_SUP_MASK) + +#define USBHSD_DEVCMDSTAT_INTONNAK_AO_MASK (0x1000U) +#define USBHSD_DEVCMDSTAT_INTONNAK_AO_SHIFT (12U) +/*! INTONNAK_AO - Interrupt on NAK for interrupt and bulk OUT EP:. + */ +#define USBHSD_DEVCMDSTAT_INTONNAK_AO(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_INTONNAK_AO_SHIFT)) & USBHSD_DEVCMDSTAT_INTONNAK_AO_MASK) + +#define USBHSD_DEVCMDSTAT_INTONNAK_AI_MASK (0x2000U) +#define USBHSD_DEVCMDSTAT_INTONNAK_AI_SHIFT (13U) +/*! INTONNAK_AI - Interrupt on NAK for interrupt and bulk IN EP:. + */ +#define USBHSD_DEVCMDSTAT_INTONNAK_AI(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_INTONNAK_AI_SHIFT)) & USBHSD_DEVCMDSTAT_INTONNAK_AI_MASK) + +#define USBHSD_DEVCMDSTAT_INTONNAK_CO_MASK (0x4000U) +#define USBHSD_DEVCMDSTAT_INTONNAK_CO_SHIFT (14U) +/*! INTONNAK_CO - Interrupt on NAK for control OUT EP:. + */ +#define USBHSD_DEVCMDSTAT_INTONNAK_CO(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_INTONNAK_CO_SHIFT)) & USBHSD_DEVCMDSTAT_INTONNAK_CO_MASK) + +#define USBHSD_DEVCMDSTAT_INTONNAK_CI_MASK (0x8000U) +#define USBHSD_DEVCMDSTAT_INTONNAK_CI_SHIFT (15U) +/*! INTONNAK_CI - Interrupt on NAK for control IN EP:. + */ +#define USBHSD_DEVCMDSTAT_INTONNAK_CI(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_INTONNAK_CI_SHIFT)) & USBHSD_DEVCMDSTAT_INTONNAK_CI_MASK) + +#define USBHSD_DEVCMDSTAT_DCON_MASK (0x10000U) +#define USBHSD_DEVCMDSTAT_DCON_SHIFT (16U) +/*! DCON - Device status - connect. + */ +#define USBHSD_DEVCMDSTAT_DCON(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DCON_SHIFT)) & USBHSD_DEVCMDSTAT_DCON_MASK) + +#define USBHSD_DEVCMDSTAT_DSUS_MASK (0x20000U) +#define USBHSD_DEVCMDSTAT_DSUS_SHIFT (17U) +/*! DSUS - Device status - suspend. + */ +#define USBHSD_DEVCMDSTAT_DSUS(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DSUS_SHIFT)) & USBHSD_DEVCMDSTAT_DSUS_MASK) + +#define USBHSD_DEVCMDSTAT_LPM_SUS_MASK (0x80000U) +#define USBHSD_DEVCMDSTAT_LPM_SUS_SHIFT (19U) +/*! LPM_SUS - Device status - LPM Suspend. + */ +#define USBHSD_DEVCMDSTAT_LPM_SUS(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_LPM_SUS_SHIFT)) & USBHSD_DEVCMDSTAT_LPM_SUS_MASK) + +#define USBHSD_DEVCMDSTAT_LPM_REWP_MASK (0x100000U) +#define USBHSD_DEVCMDSTAT_LPM_REWP_SHIFT (20U) +/*! LPM_REWP - LPM Remote Wake-up Enabled by USB host. + */ +#define USBHSD_DEVCMDSTAT_LPM_REWP(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_LPM_REWP_SHIFT)) & USBHSD_DEVCMDSTAT_LPM_REWP_MASK) + +#define USBHSD_DEVCMDSTAT_Speed_MASK (0xC00000U) +#define USBHSD_DEVCMDSTAT_Speed_SHIFT (22U) +/*! Speed - This field indicates the speed at which the device operates: 00b: reserved 01b: + * full-speed 10b: high-speed 11b: super-speed (reserved for future use). + */ +#define USBHSD_DEVCMDSTAT_Speed(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_Speed_SHIFT)) & USBHSD_DEVCMDSTAT_Speed_MASK) + +#define USBHSD_DEVCMDSTAT_DCON_C_MASK (0x1000000U) +#define USBHSD_DEVCMDSTAT_DCON_C_SHIFT (24U) +/*! DCON_C - Device status - connect change. + */ +#define USBHSD_DEVCMDSTAT_DCON_C(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DCON_C_SHIFT)) & USBHSD_DEVCMDSTAT_DCON_C_MASK) + +#define USBHSD_DEVCMDSTAT_DSUS_C_MASK (0x2000000U) +#define USBHSD_DEVCMDSTAT_DSUS_C_SHIFT (25U) +/*! DSUS_C - Device status - suspend change. + */ +#define USBHSD_DEVCMDSTAT_DSUS_C(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DSUS_C_SHIFT)) & USBHSD_DEVCMDSTAT_DSUS_C_MASK) + +#define USBHSD_DEVCMDSTAT_DRES_C_MASK (0x4000000U) +#define USBHSD_DEVCMDSTAT_DRES_C_SHIFT (26U) +/*! DRES_C - Device status - reset change. + */ +#define USBHSD_DEVCMDSTAT_DRES_C(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DRES_C_SHIFT)) & USBHSD_DEVCMDSTAT_DRES_C_MASK) + +#define USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED_MASK (0x10000000U) +#define USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED_SHIFT (28U) +/*! VBUS_DEBOUNCED - This bit indicates if VBUS is detected or not. + */ +#define USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED_SHIFT)) & USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED_MASK) + +#define USBHSD_DEVCMDSTAT_PHY_TEST_MODE_MASK (0xE0000000U) +#define USBHSD_DEVCMDSTAT_PHY_TEST_MODE_SHIFT (29U) +/*! PHY_TEST_MODE - This field is written by firmware to put the PHY into a test mode as defined by the USB2.0 specification. + * 0b000..Test mode disabled. + * 0b001..Test_J. + * 0b010..Test_K. + * 0b011..Test_SE0_NAK. + * 0b100..Test_Packet. + * 0b101..Test_Force_Enable. + */ +#define USBHSD_DEVCMDSTAT_PHY_TEST_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_PHY_TEST_MODE_SHIFT)) & USBHSD_DEVCMDSTAT_PHY_TEST_MODE_MASK) +/*! @} */ + +/*! @name INFO - USB Info register */ +/*! @{ */ + +#define USBHSD_INFO_FRAME_NR_MASK (0x7FFU) +#define USBHSD_INFO_FRAME_NR_SHIFT (0U) +/*! FRAME_NR - Frame number. + */ +#define USBHSD_INFO_FRAME_NR(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INFO_FRAME_NR_SHIFT)) & USBHSD_INFO_FRAME_NR_MASK) + +#define USBHSD_INFO_ERR_CODE_MASK (0x7800U) +#define USBHSD_INFO_ERR_CODE_SHIFT (11U) +/*! ERR_CODE - The error code which last occurred:. + */ +#define USBHSD_INFO_ERR_CODE(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INFO_ERR_CODE_SHIFT)) & USBHSD_INFO_ERR_CODE_MASK) + +#define USBHSD_INFO_MINREV_MASK (0xFF0000U) +#define USBHSD_INFO_MINREV_SHIFT (16U) +/*! MINREV - Minor revision. + */ +#define USBHSD_INFO_MINREV(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INFO_MINREV_SHIFT)) & USBHSD_INFO_MINREV_MASK) + +#define USBHSD_INFO_MAJREV_MASK (0xFF000000U) +#define USBHSD_INFO_MAJREV_SHIFT (24U) +/*! MAJREV - Major revision. + */ +#define USBHSD_INFO_MAJREV(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INFO_MAJREV_SHIFT)) & USBHSD_INFO_MAJREV_MASK) +/*! @} */ + +/*! @name EPLISTSTART - USB EP Command/Status List start address */ +/*! @{ */ + +#define USBHSD_EPLISTSTART_EP_LIST_PRG_MASK (0xFFF00U) +#define USBHSD_EPLISTSTART_EP_LIST_PRG_SHIFT (8U) +/*! EP_LIST_PRG - Programmable portion of the USB EP Command/Status List address. + */ +#define USBHSD_EPLISTSTART_EP_LIST_PRG(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPLISTSTART_EP_LIST_PRG_SHIFT)) & USBHSD_EPLISTSTART_EP_LIST_PRG_MASK) + +#define USBHSD_EPLISTSTART_EP_LIST_FIXED_MASK (0xFFF00000U) +#define USBHSD_EPLISTSTART_EP_LIST_FIXED_SHIFT (20U) +/*! EP_LIST_FIXED - Fixed portion of USB EP Command/Status List address. + */ +#define USBHSD_EPLISTSTART_EP_LIST_FIXED(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPLISTSTART_EP_LIST_FIXED_SHIFT)) & USBHSD_EPLISTSTART_EP_LIST_FIXED_MASK) +/*! @} */ + +/*! @name DATABUFSTART - USB Data buffer start address */ +/*! @{ */ + +#define USBHSD_DATABUFSTART_DA_BUF_MASK (0xFFFFFFFFU) +#define USBHSD_DATABUFSTART_DA_BUF_SHIFT (0U) +/*! DA_BUF - Start address of the memory page where all endpoint data buffers are located. + */ +#define USBHSD_DATABUFSTART_DA_BUF(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DATABUFSTART_DA_BUF_SHIFT)) & USBHSD_DATABUFSTART_DA_BUF_MASK) +/*! @} */ + +/*! @name LPM - USB Link Power Management register */ +/*! @{ */ + +#define USBHSD_LPM_HIRD_HW_MASK (0xFU) +#define USBHSD_LPM_HIRD_HW_SHIFT (0U) +/*! HIRD_HW - Host Initiated Resume Duration - HW. + */ +#define USBHSD_LPM_HIRD_HW(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_LPM_HIRD_HW_SHIFT)) & USBHSD_LPM_HIRD_HW_MASK) + +#define USBHSD_LPM_HIRD_SW_MASK (0xF0U) +#define USBHSD_LPM_HIRD_SW_SHIFT (4U) +/*! HIRD_SW - Host Initiated Resume Duration - SW. + */ +#define USBHSD_LPM_HIRD_SW(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_LPM_HIRD_SW_SHIFT)) & USBHSD_LPM_HIRD_SW_MASK) + +#define USBHSD_LPM_DATA_PENDING_MASK (0x100U) +#define USBHSD_LPM_DATA_PENDING_SHIFT (8U) +/*! DATA_PENDING - As long as this bit is set to one and LPM supported bit is set to one, HW will + * return a NYET handshake on every LPM token it receives. + */ +#define USBHSD_LPM_DATA_PENDING(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_LPM_DATA_PENDING_SHIFT)) & USBHSD_LPM_DATA_PENDING_MASK) +/*! @} */ + +/*! @name EPSKIP - USB Endpoint skip */ +/*! @{ */ + +#define USBHSD_EPSKIP_SKIP_MASK (0xFFFU) +#define USBHSD_EPSKIP_SKIP_SHIFT (0U) +/*! SKIP - Endpoint skip: Writing 1 to one of these bits, will indicate to HW that it must + * deactivate the buffer assigned to this endpoint and return control back to software. + */ +#define USBHSD_EPSKIP_SKIP(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPSKIP_SKIP_SHIFT)) & USBHSD_EPSKIP_SKIP_MASK) +/*! @} */ + +/*! @name EPINUSE - USB Endpoint Buffer in use */ +/*! @{ */ + +#define USBHSD_EPINUSE_BUF_MASK (0xFFCU) +#define USBHSD_EPINUSE_BUF_SHIFT (2U) +/*! BUF - Buffer in use: This register has one bit per physical endpoint. + */ +#define USBHSD_EPINUSE_BUF(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPINUSE_BUF_SHIFT)) & USBHSD_EPINUSE_BUF_MASK) +/*! @} */ + +/*! @name EPBUFCFG - USB Endpoint Buffer Configuration register */ +/*! @{ */ + +#define USBHSD_EPBUFCFG_BUF_SB_MASK (0xFFCU) +#define USBHSD_EPBUFCFG_BUF_SB_SHIFT (2U) +/*! BUF_SB - Buffer usage: This register has one bit per physical endpoint. + */ +#define USBHSD_EPBUFCFG_BUF_SB(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPBUFCFG_BUF_SB_SHIFT)) & USBHSD_EPBUFCFG_BUF_SB_MASK) +/*! @} */ + +/*! @name INTSTAT - USB interrupt status register */ +/*! @{ */ + +#define USBHSD_INTSTAT_EP0OUT_MASK (0x1U) +#define USBHSD_INTSTAT_EP0OUT_SHIFT (0U) +/*! EP0OUT - Interrupt status register bit for the Control EP0 OUT direction. + */ +#define USBHSD_INTSTAT_EP0OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP0OUT_SHIFT)) & USBHSD_INTSTAT_EP0OUT_MASK) + +#define USBHSD_INTSTAT_EP0IN_MASK (0x2U) +#define USBHSD_INTSTAT_EP0IN_SHIFT (1U) +/*! EP0IN - Interrupt status register bit for the Control EP0 IN direction. + */ +#define USBHSD_INTSTAT_EP0IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP0IN_SHIFT)) & USBHSD_INTSTAT_EP0IN_MASK) + +#define USBHSD_INTSTAT_EP1OUT_MASK (0x4U) +#define USBHSD_INTSTAT_EP1OUT_SHIFT (2U) +/*! EP1OUT - Interrupt status register bit for the EP1 OUT direction. + */ +#define USBHSD_INTSTAT_EP1OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP1OUT_SHIFT)) & USBHSD_INTSTAT_EP1OUT_MASK) + +#define USBHSD_INTSTAT_EP1IN_MASK (0x8U) +#define USBHSD_INTSTAT_EP1IN_SHIFT (3U) +/*! EP1IN - Interrupt status register bit for the EP1 IN direction. + */ +#define USBHSD_INTSTAT_EP1IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP1IN_SHIFT)) & USBHSD_INTSTAT_EP1IN_MASK) + +#define USBHSD_INTSTAT_EP2OUT_MASK (0x10U) +#define USBHSD_INTSTAT_EP2OUT_SHIFT (4U) +/*! EP2OUT - Interrupt status register bit for the EP2 OUT direction. + */ +#define USBHSD_INTSTAT_EP2OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP2OUT_SHIFT)) & USBHSD_INTSTAT_EP2OUT_MASK) + +#define USBHSD_INTSTAT_EP2IN_MASK (0x20U) +#define USBHSD_INTSTAT_EP2IN_SHIFT (5U) +/*! EP2IN - Interrupt status register bit for the EP2 IN direction. + */ +#define USBHSD_INTSTAT_EP2IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP2IN_SHIFT)) & USBHSD_INTSTAT_EP2IN_MASK) + +#define USBHSD_INTSTAT_EP3OUT_MASK (0x40U) +#define USBHSD_INTSTAT_EP3OUT_SHIFT (6U) +/*! EP3OUT - Interrupt status register bit for the EP3 OUT direction. + */ +#define USBHSD_INTSTAT_EP3OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP3OUT_SHIFT)) & USBHSD_INTSTAT_EP3OUT_MASK) + +#define USBHSD_INTSTAT_EP3IN_MASK (0x80U) +#define USBHSD_INTSTAT_EP3IN_SHIFT (7U) +/*! EP3IN - Interrupt status register bit for the EP3 IN direction. + */ +#define USBHSD_INTSTAT_EP3IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP3IN_SHIFT)) & USBHSD_INTSTAT_EP3IN_MASK) + +#define USBHSD_INTSTAT_EP4OUT_MASK (0x100U) +#define USBHSD_INTSTAT_EP4OUT_SHIFT (8U) +/*! EP4OUT - Interrupt status register bit for the EP4 OUT direction. + */ +#define USBHSD_INTSTAT_EP4OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP4OUT_SHIFT)) & USBHSD_INTSTAT_EP4OUT_MASK) + +#define USBHSD_INTSTAT_EP4IN_MASK (0x200U) +#define USBHSD_INTSTAT_EP4IN_SHIFT (9U) +/*! EP4IN - Interrupt status register bit for the EP4 IN direction. + */ +#define USBHSD_INTSTAT_EP4IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP4IN_SHIFT)) & USBHSD_INTSTAT_EP4IN_MASK) + +#define USBHSD_INTSTAT_EP5OUT_MASK (0x400U) +#define USBHSD_INTSTAT_EP5OUT_SHIFT (10U) +/*! EP5OUT - Interrupt status register bit for the EP5 OUT direction. + */ +#define USBHSD_INTSTAT_EP5OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP5OUT_SHIFT)) & USBHSD_INTSTAT_EP5OUT_MASK) + +#define USBHSD_INTSTAT_EP5IN_MASK (0x800U) +#define USBHSD_INTSTAT_EP5IN_SHIFT (11U) +/*! EP5IN - Interrupt status register bit for the EP5 IN direction. + */ +#define USBHSD_INTSTAT_EP5IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP5IN_SHIFT)) & USBHSD_INTSTAT_EP5IN_MASK) + +#define USBHSD_INTSTAT_FRAME_INT_MASK (0x40000000U) +#define USBHSD_INTSTAT_FRAME_INT_SHIFT (30U) +/*! FRAME_INT - Frame interrupt. + */ +#define USBHSD_INTSTAT_FRAME_INT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_FRAME_INT_SHIFT)) & USBHSD_INTSTAT_FRAME_INT_MASK) + +#define USBHSD_INTSTAT_DEV_INT_MASK (0x80000000U) +#define USBHSD_INTSTAT_DEV_INT_SHIFT (31U) +/*! DEV_INT - Device status interrupt. + */ +#define USBHSD_INTSTAT_DEV_INT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_DEV_INT_SHIFT)) & USBHSD_INTSTAT_DEV_INT_MASK) +/*! @} */ + +/*! @name INTEN - USB interrupt enable register */ +/*! @{ */ + +#define USBHSD_INTEN_EP_INT_EN_MASK (0xFFFU) +#define USBHSD_INTEN_EP_INT_EN_SHIFT (0U) +/*! EP_INT_EN - If this bit is set and the corresponding USB interrupt status bit is set, a HW + * interrupt is generated on the interrupt line. + */ +#define USBHSD_INTEN_EP_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTEN_EP_INT_EN_SHIFT)) & USBHSD_INTEN_EP_INT_EN_MASK) + +#define USBHSD_INTEN_FRAME_INT_EN_MASK (0x40000000U) +#define USBHSD_INTEN_FRAME_INT_EN_SHIFT (30U) +/*! FRAME_INT_EN - If this bit is set and the corresponding USB interrupt status bit is set, a HW + * interrupt is generated on the interrupt line. + */ +#define USBHSD_INTEN_FRAME_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTEN_FRAME_INT_EN_SHIFT)) & USBHSD_INTEN_FRAME_INT_EN_MASK) + +#define USBHSD_INTEN_DEV_INT_EN_MASK (0x80000000U) +#define USBHSD_INTEN_DEV_INT_EN_SHIFT (31U) +/*! DEV_INT_EN - If this bit is set and the corresponding USB interrupt status bit is set, a HW + * interrupt is generated on the interrupt line. + */ +#define USBHSD_INTEN_DEV_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTEN_DEV_INT_EN_SHIFT)) & USBHSD_INTEN_DEV_INT_EN_MASK) +/*! @} */ + +/*! @name INTSETSTAT - USB set interrupt status register */ +/*! @{ */ + +#define USBHSD_INTSETSTAT_EP_SET_INT_MASK (0xFFFU) +#define USBHSD_INTSETSTAT_EP_SET_INT_SHIFT (0U) +/*! EP_SET_INT - If software writes a one to one of these bits, the corresponding USB interrupt status bit is set. + */ +#define USBHSD_INTSETSTAT_EP_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSETSTAT_EP_SET_INT_SHIFT)) & USBHSD_INTSETSTAT_EP_SET_INT_MASK) + +#define USBHSD_INTSETSTAT_FRAME_SET_INT_MASK (0x40000000U) +#define USBHSD_INTSETSTAT_FRAME_SET_INT_SHIFT (30U) +/*! FRAME_SET_INT - If software writes a one to one of these bits, the corresponding USB interrupt status bit is set. + */ +#define USBHSD_INTSETSTAT_FRAME_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSETSTAT_FRAME_SET_INT_SHIFT)) & USBHSD_INTSETSTAT_FRAME_SET_INT_MASK) + +#define USBHSD_INTSETSTAT_DEV_SET_INT_MASK (0x80000000U) +#define USBHSD_INTSETSTAT_DEV_SET_INT_SHIFT (31U) +/*! DEV_SET_INT - If software writes a one to one of these bits, the corresponding USB interrupt status bit is set. + */ +#define USBHSD_INTSETSTAT_DEV_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSETSTAT_DEV_SET_INT_SHIFT)) & USBHSD_INTSETSTAT_DEV_SET_INT_MASK) +/*! @} */ + +/*! @name EPTOGGLE - USB Endpoint toggle register */ +/*! @{ */ + +#define USBHSD_EPTOGGLE_TOGGLE_MASK (0x3FFFFFFFU) +#define USBHSD_EPTOGGLE_TOGGLE_SHIFT (0U) +/*! TOGGLE - Endpoint data toggle: This field indicates the current value of the data toggle for the corresponding endpoint. + */ +#define USBHSD_EPTOGGLE_TOGGLE(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPTOGGLE_TOGGLE_SHIFT)) & USBHSD_EPTOGGLE_TOGGLE_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group USBHSD_Register_Masks */ + + +/* USBHSD - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral USBHSD base address */ + #define USBHSD_BASE (0x50094000u) + /** Peripheral USBHSD base address */ + #define USBHSD_BASE_NS (0x40094000u) + /** Peripheral USBHSD base pointer */ + #define USBHSD ((USBHSD_Type *)USBHSD_BASE) + /** Peripheral USBHSD base pointer */ + #define USBHSD_NS ((USBHSD_Type *)USBHSD_BASE_NS) + /** Array initializer of USBHSD peripheral base addresses */ + #define USBHSD_BASE_ADDRS { USBHSD_BASE } + /** Array initializer of USBHSD peripheral base pointers */ + #define USBHSD_BASE_PTRS { USBHSD } + /** Array initializer of USBHSD peripheral base addresses */ + #define USBHSD_BASE_ADDRS_NS { USBHSD_BASE_NS } + /** Array initializer of USBHSD peripheral base pointers */ + #define USBHSD_BASE_PTRS_NS { USBHSD_NS } +#else + /** Peripheral USBHSD base address */ + #define USBHSD_BASE (0x40094000u) + /** Peripheral USBHSD base pointer */ + #define USBHSD ((USBHSD_Type *)USBHSD_BASE) + /** Array initializer of USBHSD peripheral base addresses */ + #define USBHSD_BASE_ADDRS { USBHSD_BASE } + /** Array initializer of USBHSD peripheral base pointers */ + #define USBHSD_BASE_PTRS { USBHSD } +#endif +/** Interrupt vectors for the USBHSD peripheral type */ +#define USBHSD_IRQS { USB1_IRQn } +#define USBHSD_NEEDCLK_IRQS { USB1_NEEDCLK_IRQn } + +/*! + * @} + */ /* end of group USBHSD_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- USBHSH Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USBHSH_Peripheral_Access_Layer USBHSH Peripheral Access Layer + * @{ + */ + +/** USBHSH - Register Layout Typedef */ +typedef struct { + __I uint32_t CAPLENGTH_CHIPID; /**< This register contains the offset value towards the start of the operational register space and the version number of the IP block, offset: 0x0 */ + __I uint32_t HCSPARAMS; /**< Host Controller Structural Parameters, offset: 0x4 */ + __I uint32_t HCCPARAMS; /**< Host Controller Capability Parameters, offset: 0x8 */ + __IO uint32_t FLADJ_FRINDEX; /**< Frame Length Adjustment, offset: 0xC */ + __IO uint32_t ATLPTD; /**< Memory base address where ATL PTD0 is stored, offset: 0x10 */ + __IO uint32_t ISOPTD; /**< Memory base address where ISO PTD0 is stored, offset: 0x14 */ + __IO uint32_t INTPTD; /**< Memory base address where INT PTD0 is stored, offset: 0x18 */ + __IO uint32_t DATAPAYLOAD; /**< Memory base address that indicates the start of the data payload buffers, offset: 0x1C */ + __IO uint32_t USBCMD; /**< USB Command register, offset: 0x20 */ + __IO uint32_t USBSTS; /**< USB Interrupt Status register, offset: 0x24 */ + __IO uint32_t USBINTR; /**< USB Interrupt Enable register, offset: 0x28 */ + __IO uint32_t PORTSC1; /**< Port Status and Control register, offset: 0x2C */ + __IO uint32_t ATLPTDD; /**< Done map for each ATL PTD, offset: 0x30 */ + __IO uint32_t ATLPTDS; /**< Skip map for each ATL PTD, offset: 0x34 */ + __IO uint32_t ISOPTDD; /**< Done map for each ISO PTD, offset: 0x38 */ + __IO uint32_t ISOPTDS; /**< Skip map for each ISO PTD, offset: 0x3C */ + __IO uint32_t INTPTDD; /**< Done map for each INT PTD, offset: 0x40 */ + __IO uint32_t INTPTDS; /**< Skip map for each INT PTD, offset: 0x44 */ + __IO uint32_t LASTPTD; /**< Marks the last PTD in the list for ISO, INT and ATL, offset: 0x48 */ + uint8_t RESERVED_0[4]; + __IO uint32_t PORTMODE; /**< Controls the port if it is attached to the host block or the device block, offset: 0x50 */ +} USBHSH_Type; + +/* ---------------------------------------------------------------------------- + -- USBHSH Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USBHSH_Register_Masks USBHSH Register Masks + * @{ + */ + +/*! @name CAPLENGTH_CHIPID - This register contains the offset value towards the start of the operational register space and the version number of the IP block */ +/*! @{ */ + +#define USBHSH_CAPLENGTH_CHIPID_CAPLENGTH_MASK (0xFFU) +#define USBHSH_CAPLENGTH_CHIPID_CAPLENGTH_SHIFT (0U) +/*! CAPLENGTH - Capability Length: This is used as an offset. + */ +#define USBHSH_CAPLENGTH_CHIPID_CAPLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_CAPLENGTH_CHIPID_CAPLENGTH_SHIFT)) & USBHSH_CAPLENGTH_CHIPID_CAPLENGTH_MASK) + +#define USBHSH_CAPLENGTH_CHIPID_CHIPID_MASK (0xFFFF0000U) +#define USBHSH_CAPLENGTH_CHIPID_CHIPID_SHIFT (16U) +/*! CHIPID - Chip identification: indicates major and minor revision of the IP: [31:24] = Major + * revision [23:16] = Minor revision Major revisions used: 0x01: USB2. + */ +#define USBHSH_CAPLENGTH_CHIPID_CHIPID(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_CAPLENGTH_CHIPID_CHIPID_SHIFT)) & USBHSH_CAPLENGTH_CHIPID_CHIPID_MASK) +/*! @} */ + +/*! @name HCSPARAMS - Host Controller Structural Parameters */ +/*! @{ */ + +#define USBHSH_HCSPARAMS_N_PORTS_MASK (0xFU) +#define USBHSH_HCSPARAMS_N_PORTS_SHIFT (0U) +/*! N_PORTS - This register specifies the number of physical downstream ports implemented on this host controller. + */ +#define USBHSH_HCSPARAMS_N_PORTS(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_HCSPARAMS_N_PORTS_SHIFT)) & USBHSH_HCSPARAMS_N_PORTS_MASK) + +#define USBHSH_HCSPARAMS_PPC_MASK (0x10U) +#define USBHSH_HCSPARAMS_PPC_SHIFT (4U) +/*! PPC - This field indicates whether the host controller implementation includes port power control. + */ +#define USBHSH_HCSPARAMS_PPC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_HCSPARAMS_PPC_SHIFT)) & USBHSH_HCSPARAMS_PPC_MASK) + +#define USBHSH_HCSPARAMS_P_INDICATOR_MASK (0x10000U) +#define USBHSH_HCSPARAMS_P_INDICATOR_SHIFT (16U) +/*! P_INDICATOR - This bit indicates whether the ports support port indicator control. + */ +#define USBHSH_HCSPARAMS_P_INDICATOR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_HCSPARAMS_P_INDICATOR_SHIFT)) & USBHSH_HCSPARAMS_P_INDICATOR_MASK) +/*! @} */ + +/*! @name HCCPARAMS - Host Controller Capability Parameters */ +/*! @{ */ + +#define USBHSH_HCCPARAMS_LPMC_MASK (0x20000U) +#define USBHSH_HCCPARAMS_LPMC_SHIFT (17U) +/*! LPMC - Link Power Management Capability. + */ +#define USBHSH_HCCPARAMS_LPMC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_HCCPARAMS_LPMC_SHIFT)) & USBHSH_HCCPARAMS_LPMC_MASK) +/*! @} */ + +/*! @name FLADJ_FRINDEX - Frame Length Adjustment */ +/*! @{ */ + +#define USBHSH_FLADJ_FRINDEX_FLADJ_MASK (0x3FU) +#define USBHSH_FLADJ_FRINDEX_FLADJ_SHIFT (0U) +/*! FLADJ - Frame Length Timing Value. + */ +#define USBHSH_FLADJ_FRINDEX_FLADJ(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_FLADJ_FRINDEX_FLADJ_SHIFT)) & USBHSH_FLADJ_FRINDEX_FLADJ_MASK) + +#define USBHSH_FLADJ_FRINDEX_FRINDEX_MASK (0x3FFF0000U) +#define USBHSH_FLADJ_FRINDEX_FRINDEX_SHIFT (16U) +/*! FRINDEX - Frame Index: Bits 29 to16 in this register are used for the frame number field in the SOF packet. + */ +#define USBHSH_FLADJ_FRINDEX_FRINDEX(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_FLADJ_FRINDEX_FRINDEX_SHIFT)) & USBHSH_FLADJ_FRINDEX_FRINDEX_MASK) +/*! @} */ + +/*! @name ATLPTD - Memory base address where ATL PTD0 is stored */ +/*! @{ */ + +#define USBHSH_ATLPTD_ATL_CUR_MASK (0x1F0U) +#define USBHSH_ATLPTD_ATL_CUR_SHIFT (4U) +/*! ATL_CUR - This indicates the current PTD that is used by the hardware when it is processing the ATL list. + */ +#define USBHSH_ATLPTD_ATL_CUR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ATLPTD_ATL_CUR_SHIFT)) & USBHSH_ATLPTD_ATL_CUR_MASK) + +#define USBHSH_ATLPTD_ATL_BASE_MASK (0xFFFFFE00U) +#define USBHSH_ATLPTD_ATL_BASE_SHIFT (9U) +/*! ATL_BASE - Base address to be used by the hardware to find the start of the ATL list. + */ +#define USBHSH_ATLPTD_ATL_BASE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ATLPTD_ATL_BASE_SHIFT)) & USBHSH_ATLPTD_ATL_BASE_MASK) +/*! @} */ + +/*! @name ISOPTD - Memory base address where ISO PTD0 is stored */ +/*! @{ */ + +#define USBHSH_ISOPTD_ISO_FIRST_MASK (0x3E0U) +#define USBHSH_ISOPTD_ISO_FIRST_SHIFT (5U) +/*! ISO_FIRST - This indicates the first PTD that is used by the hardware when it is processing the ISO list. + */ +#define USBHSH_ISOPTD_ISO_FIRST(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ISOPTD_ISO_FIRST_SHIFT)) & USBHSH_ISOPTD_ISO_FIRST_MASK) + +#define USBHSH_ISOPTD_ISO_BASE_MASK (0xFFFFFC00U) +#define USBHSH_ISOPTD_ISO_BASE_SHIFT (10U) +/*! ISO_BASE - Base address to be used by the hardware to find the start of the ISO list. + */ +#define USBHSH_ISOPTD_ISO_BASE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ISOPTD_ISO_BASE_SHIFT)) & USBHSH_ISOPTD_ISO_BASE_MASK) +/*! @} */ + +/*! @name INTPTD - Memory base address where INT PTD0 is stored */ +/*! @{ */ + +#define USBHSH_INTPTD_INT_FIRST_MASK (0x3E0U) +#define USBHSH_INTPTD_INT_FIRST_SHIFT (5U) +/*! INT_FIRST - This indicates the first PTD that is used by the hardware when it is processing the INT list. + */ +#define USBHSH_INTPTD_INT_FIRST(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_INTPTD_INT_FIRST_SHIFT)) & USBHSH_INTPTD_INT_FIRST_MASK) + +#define USBHSH_INTPTD_INT_BASE_MASK (0xFFFFFC00U) +#define USBHSH_INTPTD_INT_BASE_SHIFT (10U) +/*! INT_BASE - Base address to be used by the hardware to find the start of the INT list. + */ +#define USBHSH_INTPTD_INT_BASE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_INTPTD_INT_BASE_SHIFT)) & USBHSH_INTPTD_INT_BASE_MASK) +/*! @} */ + +/*! @name DATAPAYLOAD - Memory base address that indicates the start of the data payload buffers */ +/*! @{ */ + +#define USBHSH_DATAPAYLOAD_DAT_BASE_MASK (0xFFFF0000U) +#define USBHSH_DATAPAYLOAD_DAT_BASE_SHIFT (16U) +/*! DAT_BASE - Base address to be used by the hardware to find the start of the data payload section. + */ +#define USBHSH_DATAPAYLOAD_DAT_BASE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_DATAPAYLOAD_DAT_BASE_SHIFT)) & USBHSH_DATAPAYLOAD_DAT_BASE_MASK) +/*! @} */ + +/*! @name USBCMD - USB Command register */ +/*! @{ */ + +#define USBHSH_USBCMD_RS_MASK (0x1U) +#define USBHSH_USBCMD_RS_SHIFT (0U) +/*! RS - Run/Stop: 1b = Run. + */ +#define USBHSH_USBCMD_RS(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_RS_SHIFT)) & USBHSH_USBCMD_RS_MASK) + +#define USBHSH_USBCMD_HCRESET_MASK (0x2U) +#define USBHSH_USBCMD_HCRESET_SHIFT (1U) +/*! HCRESET - Host Controller Reset: This control bit is used by the software to reset the host controller. + */ +#define USBHSH_USBCMD_HCRESET(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_HCRESET_SHIFT)) & USBHSH_USBCMD_HCRESET_MASK) + +#define USBHSH_USBCMD_FLS_MASK (0xCU) +#define USBHSH_USBCMD_FLS_SHIFT (2U) +/*! FLS - Frame List Size: This field specifies the size of the frame list. + */ +#define USBHSH_USBCMD_FLS(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_FLS_SHIFT)) & USBHSH_USBCMD_FLS_MASK) + +#define USBHSH_USBCMD_LHCR_MASK (0x80U) +#define USBHSH_USBCMD_LHCR_SHIFT (7U) +/*! LHCR - Light Host Controller Reset: This bit allows the driver software to reset the host + * controller without affecting the state of the ports. + */ +#define USBHSH_USBCMD_LHCR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_LHCR_SHIFT)) & USBHSH_USBCMD_LHCR_MASK) + +#define USBHSH_USBCMD_ATL_EN_MASK (0x100U) +#define USBHSH_USBCMD_ATL_EN_SHIFT (8U) +/*! ATL_EN - ATL List enabled. + */ +#define USBHSH_USBCMD_ATL_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_ATL_EN_SHIFT)) & USBHSH_USBCMD_ATL_EN_MASK) + +#define USBHSH_USBCMD_ISO_EN_MASK (0x200U) +#define USBHSH_USBCMD_ISO_EN_SHIFT (9U) +/*! ISO_EN - ISO List enabled. + */ +#define USBHSH_USBCMD_ISO_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_ISO_EN_SHIFT)) & USBHSH_USBCMD_ISO_EN_MASK) + +#define USBHSH_USBCMD_INT_EN_MASK (0x400U) +#define USBHSH_USBCMD_INT_EN_SHIFT (10U) +/*! INT_EN - INT List enabled. + */ +#define USBHSH_USBCMD_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_INT_EN_SHIFT)) & USBHSH_USBCMD_INT_EN_MASK) + +#define USBHSH_USBCMD_HIRD_MASK (0xF000000U) +#define USBHSH_USBCMD_HIRD_SHIFT (24U) +/*! HIRD - Host-Initiated Resume Duration. + */ +#define USBHSH_USBCMD_HIRD(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_HIRD_SHIFT)) & USBHSH_USBCMD_HIRD_MASK) + +#define USBHSH_USBCMD_LPM_RWU_MASK (0x10000000U) +#define USBHSH_USBCMD_LPM_RWU_SHIFT (28U) +/*! LPM_RWU - bRemoteWake field. + */ +#define USBHSH_USBCMD_LPM_RWU(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_LPM_RWU_SHIFT)) & USBHSH_USBCMD_LPM_RWU_MASK) +/*! @} */ + +/*! @name USBSTS - USB Interrupt Status register */ +/*! @{ */ + +#define USBHSH_USBSTS_PCD_MASK (0x4U) +#define USBHSH_USBSTS_PCD_SHIFT (2U) +/*! PCD - Port Change Detect: The host controller sets this bit to logic 1 when any port has a + * change bit transition from a 0 to a one or a Force Port Resume bit transition from a 0 to a 1 as a + * result of a J-K transition detected on a suspended port. + */ +#define USBHSH_USBSTS_PCD(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_PCD_SHIFT)) & USBHSH_USBSTS_PCD_MASK) + +#define USBHSH_USBSTS_FLR_MASK (0x8U) +#define USBHSH_USBSTS_FLR_SHIFT (3U) +/*! FLR - Frame List Rollover: The host controller sets this bit to logic 1 when the frame list + * index rolls over its maximum value to 0. + */ +#define USBHSH_USBSTS_FLR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_FLR_SHIFT)) & USBHSH_USBSTS_FLR_MASK) + +#define USBHSH_USBSTS_ATL_IRQ_MASK (0x10000U) +#define USBHSH_USBSTS_ATL_IRQ_SHIFT (16U) +/*! ATL_IRQ - ATL IRQ: Indicates that an ATL PTD (with I-bit set) was completed. + */ +#define USBHSH_USBSTS_ATL_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_ATL_IRQ_SHIFT)) & USBHSH_USBSTS_ATL_IRQ_MASK) + +#define USBHSH_USBSTS_ISO_IRQ_MASK (0x20000U) +#define USBHSH_USBSTS_ISO_IRQ_SHIFT (17U) +/*! ISO_IRQ - ISO IRQ: Indicates that an ISO PTD (with I-bit set) was completed. + */ +#define USBHSH_USBSTS_ISO_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_ISO_IRQ_SHIFT)) & USBHSH_USBSTS_ISO_IRQ_MASK) + +#define USBHSH_USBSTS_INT_IRQ_MASK (0x40000U) +#define USBHSH_USBSTS_INT_IRQ_SHIFT (18U) +/*! INT_IRQ - INT IRQ: Indicates that an INT PTD (with I-bit set) was completed. + */ +#define USBHSH_USBSTS_INT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_INT_IRQ_SHIFT)) & USBHSH_USBSTS_INT_IRQ_MASK) + +#define USBHSH_USBSTS_SOF_IRQ_MASK (0x80000U) +#define USBHSH_USBSTS_SOF_IRQ_SHIFT (19U) +/*! SOF_IRQ - SOF interrupt: Every time when the host sends a Start of Frame token on the USB bus, this bit is set. + */ +#define USBHSH_USBSTS_SOF_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_SOF_IRQ_SHIFT)) & USBHSH_USBSTS_SOF_IRQ_MASK) +/*! @} */ + +/*! @name USBINTR - USB Interrupt Enable register */ +/*! @{ */ + +#define USBHSH_USBINTR_PCDE_MASK (0x4U) +#define USBHSH_USBINTR_PCDE_SHIFT (2U) +/*! PCDE - Port Change Detect Interrupt Enable: 1: enable 0: disable. + */ +#define USBHSH_USBINTR_PCDE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_PCDE_SHIFT)) & USBHSH_USBINTR_PCDE_MASK) + +#define USBHSH_USBINTR_FLRE_MASK (0x8U) +#define USBHSH_USBINTR_FLRE_SHIFT (3U) +/*! FLRE - Frame List Rollover Interrupt Enable: 1: enable 0: disable. + */ +#define USBHSH_USBINTR_FLRE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_FLRE_SHIFT)) & USBHSH_USBINTR_FLRE_MASK) + +#define USBHSH_USBINTR_ATL_IRQ_E_MASK (0x10000U) +#define USBHSH_USBINTR_ATL_IRQ_E_SHIFT (16U) +/*! ATL_IRQ_E - ATL IRQ Enable bit: 1: enable 0: disable. + */ +#define USBHSH_USBINTR_ATL_IRQ_E(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_ATL_IRQ_E_SHIFT)) & USBHSH_USBINTR_ATL_IRQ_E_MASK) + +#define USBHSH_USBINTR_ISO_IRQ_E_MASK (0x20000U) +#define USBHSH_USBINTR_ISO_IRQ_E_SHIFT (17U) +/*! ISO_IRQ_E - ISO IRQ Enable bit: 1: enable 0: disable. + */ +#define USBHSH_USBINTR_ISO_IRQ_E(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_ISO_IRQ_E_SHIFT)) & USBHSH_USBINTR_ISO_IRQ_E_MASK) + +#define USBHSH_USBINTR_INT_IRQ_E_MASK (0x40000U) +#define USBHSH_USBINTR_INT_IRQ_E_SHIFT (18U) +/*! INT_IRQ_E - INT IRQ Enable bit: 1: enable 0: disable. + */ +#define USBHSH_USBINTR_INT_IRQ_E(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_INT_IRQ_E_SHIFT)) & USBHSH_USBINTR_INT_IRQ_E_MASK) + +#define USBHSH_USBINTR_SOF_E_MASK (0x80000U) +#define USBHSH_USBINTR_SOF_E_SHIFT (19U) +/*! SOF_E - SOF Interrupt Enable bit: 1: enable 0: disable. + */ +#define USBHSH_USBINTR_SOF_E(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_SOF_E_SHIFT)) & USBHSH_USBINTR_SOF_E_MASK) +/*! @} */ + +/*! @name PORTSC1 - Port Status and Control register */ +/*! @{ */ + +#define USBHSH_PORTSC1_CCS_MASK (0x1U) +#define USBHSH_PORTSC1_CCS_SHIFT (0U) +/*! CCS - Current Connect Status: Logic 1 indicates a device is present on the port. + */ +#define USBHSH_PORTSC1_CCS(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_CCS_SHIFT)) & USBHSH_PORTSC1_CCS_MASK) + +#define USBHSH_PORTSC1_CSC_MASK (0x2U) +#define USBHSH_PORTSC1_CSC_SHIFT (1U) +/*! CSC - Connect Status Change: Logic 1 means that the value of CCS has changed. + */ +#define USBHSH_PORTSC1_CSC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_CSC_SHIFT)) & USBHSH_PORTSC1_CSC_MASK) + +#define USBHSH_PORTSC1_PED_MASK (0x4U) +#define USBHSH_PORTSC1_PED_SHIFT (2U) +/*! PED - Port Enabled/Disabled. + */ +#define USBHSH_PORTSC1_PED(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PED_SHIFT)) & USBHSH_PORTSC1_PED_MASK) + +#define USBHSH_PORTSC1_PEDC_MASK (0x8U) +#define USBHSH_PORTSC1_PEDC_SHIFT (3U) +/*! PEDC - Port Enabled/Disabled Change: Logic 1 means that the value of PED has changed. + */ +#define USBHSH_PORTSC1_PEDC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PEDC_SHIFT)) & USBHSH_PORTSC1_PEDC_MASK) + +#define USBHSH_PORTSC1_OCA_MASK (0x10U) +#define USBHSH_PORTSC1_OCA_SHIFT (4U) +/*! OCA - Over-current active: Logic 1 means that this port has an over-current condition. + */ +#define USBHSH_PORTSC1_OCA(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_OCA_SHIFT)) & USBHSH_PORTSC1_OCA_MASK) + +#define USBHSH_PORTSC1_OCC_MASK (0x20U) +#define USBHSH_PORTSC1_OCC_SHIFT (5U) +/*! OCC - Over-current change: Logic 1 means that the value of OCA has changed. + */ +#define USBHSH_PORTSC1_OCC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_OCC_SHIFT)) & USBHSH_PORTSC1_OCC_MASK) + +#define USBHSH_PORTSC1_FPR_MASK (0x40U) +#define USBHSH_PORTSC1_FPR_SHIFT (6U) +/*! FPR - Force Port Resume: Logic 1 means resume (K-state) detected or driven on the port. + */ +#define USBHSH_PORTSC1_FPR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_FPR_SHIFT)) & USBHSH_PORTSC1_FPR_MASK) + +#define USBHSH_PORTSC1_SUSP_MASK (0x80U) +#define USBHSH_PORTSC1_SUSP_SHIFT (7U) +/*! SUSP - Suspend: Logic 1 means port is in the suspend state. + */ +#define USBHSH_PORTSC1_SUSP(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_SUSP_SHIFT)) & USBHSH_PORTSC1_SUSP_MASK) + +#define USBHSH_PORTSC1_PR_MASK (0x100U) +#define USBHSH_PORTSC1_PR_SHIFT (8U) +/*! PR - Port Reset: Logic 1 means the port is in the reset state. + */ +#define USBHSH_PORTSC1_PR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PR_SHIFT)) & USBHSH_PORTSC1_PR_MASK) + +#define USBHSH_PORTSC1_SUS_L1_MASK (0x200U) +#define USBHSH_PORTSC1_SUS_L1_SHIFT (9U) +/*! SUS_L1 - Suspend using L1 0b = Suspend using L2 1b = Suspend using L1 When this bit is set to a + * 1 and a non-zero value is specified in the Device Address field, the host controller will + * generate an LPM Token to enter the L1 state whenever software writes a one to the Suspend bit, as + * well as L1 exit timing during any device or host-initiated resume. + */ +#define USBHSH_PORTSC1_SUS_L1(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_SUS_L1_SHIFT)) & USBHSH_PORTSC1_SUS_L1_MASK) + +#define USBHSH_PORTSC1_LS_MASK (0xC00U) +#define USBHSH_PORTSC1_LS_SHIFT (10U) +/*! LS - Line Status: This field reflects the current logical levels of the DP (bit 11) and DM (bit 10) signal lines. + */ +#define USBHSH_PORTSC1_LS(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_LS_SHIFT)) & USBHSH_PORTSC1_LS_MASK) + +#define USBHSH_PORTSC1_PP_MASK (0x1000U) +#define USBHSH_PORTSC1_PP_SHIFT (12U) +/*! PP - Port Power: The function of this bit depends on the value of the Port Power Control (PPC) bit in the HCSPARAMS register. + */ +#define USBHSH_PORTSC1_PP(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PP_SHIFT)) & USBHSH_PORTSC1_PP_MASK) + +#define USBHSH_PORTSC1_PIC_MASK (0xC000U) +#define USBHSH_PORTSC1_PIC_SHIFT (14U) +/*! PIC - Port Indicator Control : Writing to this field has no effect if the P_INDICATOR bit in the + * HCSPARAMS register is logic 0. + */ +#define USBHSH_PORTSC1_PIC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PIC_SHIFT)) & USBHSH_PORTSC1_PIC_MASK) + +#define USBHSH_PORTSC1_PTC_MASK (0xF0000U) +#define USBHSH_PORTSC1_PTC_SHIFT (16U) +/*! PTC - Port Test Control: A non-zero value indicates that the port is operating in the test mode as indicated by the value. + */ +#define USBHSH_PORTSC1_PTC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PTC_SHIFT)) & USBHSH_PORTSC1_PTC_MASK) + +#define USBHSH_PORTSC1_PSPD_MASK (0x300000U) +#define USBHSH_PORTSC1_PSPD_SHIFT (20U) +/*! PSPD - Port Speed: 00b: Low-speed 01b: Full-speed 10b: High-speed 11b: Reserved. + */ +#define USBHSH_PORTSC1_PSPD(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PSPD_SHIFT)) & USBHSH_PORTSC1_PSPD_MASK) + +#define USBHSH_PORTSC1_WOO_MASK (0x400000U) +#define USBHSH_PORTSC1_WOO_SHIFT (22U) +/*! WOO - Wake on overcurrent enable: Writing this bit to a one enables the port to be sensitive to + * overcurrent conditions as wake-up events. + */ +#define USBHSH_PORTSC1_WOO(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_WOO_SHIFT)) & USBHSH_PORTSC1_WOO_MASK) + +#define USBHSH_PORTSC1_SUS_STAT_MASK (0x1800000U) +#define USBHSH_PORTSC1_SUS_STAT_SHIFT (23U) +/*! SUS_STAT - These two bits are used by software to determine whether the most recent L1 suspend + * request was successful: 00b: Success-state transition was successful (ACK) 01b: Not Yet - + * Device was unable to enter the L1 state at this time (NYET) 10b: Not supported - Device does not + * support the L1 state (STALL) 11b: Timeout/Error - Device failed to respond or an error occurred. + */ +#define USBHSH_PORTSC1_SUS_STAT(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_SUS_STAT_SHIFT)) & USBHSH_PORTSC1_SUS_STAT_MASK) + +#define USBHSH_PORTSC1_DEV_ADD_MASK (0xFE000000U) +#define USBHSH_PORTSC1_DEV_ADD_SHIFT (25U) +/*! DEV_ADD - Device Address for LPM tokens. + */ +#define USBHSH_PORTSC1_DEV_ADD(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_DEV_ADD_SHIFT)) & USBHSH_PORTSC1_DEV_ADD_MASK) +/*! @} */ + +/*! @name ATLPTDD - Done map for each ATL PTD */ +/*! @{ */ + +#define USBHSH_ATLPTDD_ATL_DONE_MASK (0xFFFFFFFFU) +#define USBHSH_ATLPTDD_ATL_DONE_SHIFT (0U) +/*! ATL_DONE - The bit corresponding to a certain PTD will be set to logic 1 as soon as that PTD execution is completed. + */ +#define USBHSH_ATLPTDD_ATL_DONE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ATLPTDD_ATL_DONE_SHIFT)) & USBHSH_ATLPTDD_ATL_DONE_MASK) +/*! @} */ + +/*! @name ATLPTDS - Skip map for each ATL PTD */ +/*! @{ */ + +#define USBHSH_ATLPTDS_ATL_SKIP_MASK (0xFFFFFFFFU) +#define USBHSH_ATLPTDS_ATL_SKIP_SHIFT (0U) +/*! ATL_SKIP - When a bit in the PTD Skip Map is set to logic 1, the corresponding PTD will be + * skipped, independent of the V bit setting. + */ +#define USBHSH_ATLPTDS_ATL_SKIP(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ATLPTDS_ATL_SKIP_SHIFT)) & USBHSH_ATLPTDS_ATL_SKIP_MASK) +/*! @} */ + +/*! @name ISOPTDD - Done map for each ISO PTD */ +/*! @{ */ + +#define USBHSH_ISOPTDD_ISO_DONE_MASK (0xFFFFFFFFU) +#define USBHSH_ISOPTDD_ISO_DONE_SHIFT (0U) +/*! ISO_DONE - The bit corresponding to a certain PTD will be set to logic 1 as soon as that PTD execution is completed. + */ +#define USBHSH_ISOPTDD_ISO_DONE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ISOPTDD_ISO_DONE_SHIFT)) & USBHSH_ISOPTDD_ISO_DONE_MASK) +/*! @} */ + +/*! @name ISOPTDS - Skip map for each ISO PTD */ +/*! @{ */ + +#define USBHSH_ISOPTDS_ISO_SKIP_MASK (0xFFFFFFFFU) +#define USBHSH_ISOPTDS_ISO_SKIP_SHIFT (0U) +/*! ISO_SKIP - The bit corresponding to a certain PTD will be set to logic 1 as soon as that PTD execution is completed. + */ +#define USBHSH_ISOPTDS_ISO_SKIP(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ISOPTDS_ISO_SKIP_SHIFT)) & USBHSH_ISOPTDS_ISO_SKIP_MASK) +/*! @} */ + +/*! @name INTPTDD - Done map for each INT PTD */ +/*! @{ */ + +#define USBHSH_INTPTDD_INT_DONE_MASK (0xFFFFFFFFU) +#define USBHSH_INTPTDD_INT_DONE_SHIFT (0U) +/*! INT_DONE - The bit corresponding to a certain PTD will be set to logic 1 as soon as that PTD execution is completed. + */ +#define USBHSH_INTPTDD_INT_DONE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_INTPTDD_INT_DONE_SHIFT)) & USBHSH_INTPTDD_INT_DONE_MASK) +/*! @} */ + +/*! @name INTPTDS - Skip map for each INT PTD */ +/*! @{ */ + +#define USBHSH_INTPTDS_INT_SKIP_MASK (0xFFFFFFFFU) +#define USBHSH_INTPTDS_INT_SKIP_SHIFT (0U) +/*! INT_SKIP - When a bit in the PTD Skip Map is set to logic 1, the corresponding PTD will be + * skipped, independent of the V bit setting. + */ +#define USBHSH_INTPTDS_INT_SKIP(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_INTPTDS_INT_SKIP_SHIFT)) & USBHSH_INTPTDS_INT_SKIP_MASK) +/*! @} */ + +/*! @name LASTPTD - Marks the last PTD in the list for ISO, INT and ATL */ +/*! @{ */ + +#define USBHSH_LASTPTD_ATL_LAST_MASK (0x1FU) +#define USBHSH_LASTPTD_ATL_LAST_SHIFT (0U) +/*! ATL_LAST - If hardware has reached this PTD and the J bit is not set, it will go to PTD0 as the next PTD to be processed. + */ +#define USBHSH_LASTPTD_ATL_LAST(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_LASTPTD_ATL_LAST_SHIFT)) & USBHSH_LASTPTD_ATL_LAST_MASK) + +#define USBHSH_LASTPTD_ISO_LAST_MASK (0x1F00U) +#define USBHSH_LASTPTD_ISO_LAST_SHIFT (8U) +/*! ISO_LAST - This indicates the last PTD in the ISO list. + */ +#define USBHSH_LASTPTD_ISO_LAST(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_LASTPTD_ISO_LAST_SHIFT)) & USBHSH_LASTPTD_ISO_LAST_MASK) + +#define USBHSH_LASTPTD_INT_LAST_MASK (0x1F0000U) +#define USBHSH_LASTPTD_INT_LAST_SHIFT (16U) +/*! INT_LAST - This indicates the last PTD in the INT list. + */ +#define USBHSH_LASTPTD_INT_LAST(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_LASTPTD_INT_LAST_SHIFT)) & USBHSH_LASTPTD_INT_LAST_MASK) +/*! @} */ + +/*! @name PORTMODE - Controls the port if it is attached to the host block or the device block */ +/*! @{ */ + +#define USBHSH_PORTMODE_DEV_ENABLE_MASK (0x10000U) +#define USBHSH_PORTMODE_DEV_ENABLE_SHIFT (16U) +/*! DEV_ENABLE - If this bit is set to one, one of the ports will behave as a USB device. + */ +#define USBHSH_PORTMODE_DEV_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTMODE_DEV_ENABLE_SHIFT)) & USBHSH_PORTMODE_DEV_ENABLE_MASK) + +#define USBHSH_PORTMODE_SW_CTRL_PDCOM_MASK (0x40000U) +#define USBHSH_PORTMODE_SW_CTRL_PDCOM_SHIFT (18U) +/*! SW_CTRL_PDCOM - This bit indicates if the PHY power-down input is controlled by software or by hardware. + */ +#define USBHSH_PORTMODE_SW_CTRL_PDCOM(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTMODE_SW_CTRL_PDCOM_SHIFT)) & USBHSH_PORTMODE_SW_CTRL_PDCOM_MASK) + +#define USBHSH_PORTMODE_SW_PDCOM_MASK (0x80000U) +#define USBHSH_PORTMODE_SW_PDCOM_SHIFT (19U) +/*! SW_PDCOM - This bit is only used when SW_CTRL_PDCOM is set to 1b. + */ +#define USBHSH_PORTMODE_SW_PDCOM(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTMODE_SW_PDCOM_SHIFT)) & USBHSH_PORTMODE_SW_PDCOM_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group USBHSH_Register_Masks */ + + +/* USBHSH - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral USBHSH base address */ + #define USBHSH_BASE (0x500A3000u) + /** Peripheral USBHSH base address */ + #define USBHSH_BASE_NS (0x400A3000u) + /** Peripheral USBHSH base pointer */ + #define USBHSH ((USBHSH_Type *)USBHSH_BASE) + /** Peripheral USBHSH base pointer */ + #define USBHSH_NS ((USBHSH_Type *)USBHSH_BASE_NS) + /** Array initializer of USBHSH peripheral base addresses */ + #define USBHSH_BASE_ADDRS { USBHSH_BASE } + /** Array initializer of USBHSH peripheral base pointers */ + #define USBHSH_BASE_PTRS { USBHSH } + /** Array initializer of USBHSH peripheral base addresses */ + #define USBHSH_BASE_ADDRS_NS { USBHSH_BASE_NS } + /** Array initializer of USBHSH peripheral base pointers */ + #define USBHSH_BASE_PTRS_NS { USBHSH_NS } +#else + /** Peripheral USBHSH base address */ + #define USBHSH_BASE (0x400A3000u) + /** Peripheral USBHSH base pointer */ + #define USBHSH ((USBHSH_Type *)USBHSH_BASE) + /** Array initializer of USBHSH peripheral base addresses */ + #define USBHSH_BASE_ADDRS { USBHSH_BASE } + /** Array initializer of USBHSH peripheral base pointers */ + #define USBHSH_BASE_PTRS { USBHSH } +#endif +/** Interrupt vectors for the USBHSH peripheral type */ +#define USBHSH_IRQS { USB1_IRQn } +#define USBHSH_NEEDCLK_IRQS { USB1_NEEDCLK_IRQn } + +/*! + * @} + */ /* end of group USBHSH_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- USBPHY Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USBPHY_Peripheral_Access_Layer USBPHY Peripheral Access Layer + * @{ + */ + +/** USBPHY - Register Layout Typedef */ +typedef struct { + __IO uint32_t PWD; /**< USB PHY Power-Down Register, offset: 0x0 */ + __IO uint32_t PWD_SET; /**< USB PHY Power-Down Register, offset: 0x4 */ + __IO uint32_t PWD_CLR; /**< USB PHY Power-Down Register, offset: 0x8 */ + __IO uint32_t PWD_TOG; /**< USB PHY Power-Down Register, offset: 0xC */ + __IO uint32_t TX; /**< USB PHY Transmitter Control Register, offset: 0x10 */ + __IO uint32_t TX_SET; /**< USB PHY Transmitter Control Register, offset: 0x14 */ + __IO uint32_t TX_CLR; /**< USB PHY Transmitter Control Register, offset: 0x18 */ + __IO uint32_t TX_TOG; /**< USB PHY Transmitter Control Register, offset: 0x1C */ + __IO uint32_t RX; /**< USB PHY Receiver Control Register, offset: 0x20 */ + __IO uint32_t RX_SET; /**< USB PHY Receiver Control Register, offset: 0x24 */ + __IO uint32_t RX_CLR; /**< USB PHY Receiver Control Register, offset: 0x28 */ + __IO uint32_t RX_TOG; /**< USB PHY Receiver Control Register, offset: 0x2C */ + __IO uint32_t CTRL; /**< USB PHY General Control Register, offset: 0x30 */ + __IO uint32_t CTRL_SET; /**< USB PHY General Control Register, offset: 0x34 */ + __IO uint32_t CTRL_CLR; /**< USB PHY General Control Register, offset: 0x38 */ + __IO uint32_t CTRL_TOG; /**< USB PHY General Control Register, offset: 0x3C */ + __I uint32_t STATUS; /**< USB PHY Status Register, offset: 0x40 */ + uint8_t RESERVED_0[92]; + __IO uint32_t PLL_SIC; /**< USB PHY PLL Control/Status Register, offset: 0xA0 */ + __IO uint32_t PLL_SIC_SET; /**< USB PHY PLL Control/Status Register, offset: 0xA4 */ + __IO uint32_t PLL_SIC_CLR; /**< USB PHY PLL Control/Status Register, offset: 0xA8 */ + __IO uint32_t PLL_SIC_TOG; /**< USB PHY PLL Control/Status Register, offset: 0xAC */ + uint8_t RESERVED_1[16]; + __IO uint32_t USB1_VBUS_DETECT; /**< USB PHY VBUS Detect Control Register, offset: 0xC0 */ + __IO uint32_t USB1_VBUS_DETECT_SET; /**< USB PHY VBUS Detect Control Register, offset: 0xC4 */ + __IO uint32_t USB1_VBUS_DETECT_CLR; /**< USB PHY VBUS Detect Control Register, offset: 0xC8 */ + __IO uint32_t USB1_VBUS_DETECT_TOG; /**< USB PHY VBUS Detect Control Register, offset: 0xCC */ + __I uint32_t USB1_VBUS_DET_STAT; /**< USB PHY VBUS Detector Status Register, offset: 0xD0 */ + uint8_t RESERVED_2[44]; + __IO uint32_t ANACTRLr; /**< USB PHY Analog Control Register, offset: 0x100 */ + __IO uint32_t ANACTRL_SET; /**< USB PHY Analog Control Register, offset: 0x104 */ + __IO uint32_t ANACTRL_CLR; /**< USB PHY Analog Control Register, offset: 0x108 */ + __IO uint32_t ANACTRL_TOG; /**< USB PHY Analog Control Register, offset: 0x10C */ +} USBPHY_Type; + +/* ---------------------------------------------------------------------------- + -- USBPHY Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USBPHY_Register_Masks USBPHY Register Masks + * @{ + */ + +/*! @name PWD - USB PHY Power-Down Register */ +/*! @{ */ + +#define USBPHY_PWD_TXPWDFS_MASK (0x400U) +#define USBPHY_PWD_TXPWDFS_SHIFT (10U) +/*! TXPWDFS + * 0b0..Normal operation. + * 0b1..Power-down the USB full-speed drivers. This turns off the current starvation sources and puts the + */ +#define USBPHY_PWD_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDFS_SHIFT)) & USBPHY_PWD_TXPWDFS_MASK) + +#define USBPHY_PWD_TXPWDIBIAS_MASK (0x800U) +#define USBPHY_PWD_TXPWDIBIAS_SHIFT (11U) +/*! TXPWDIBIAS + * 0b0..Normal operation. + * 0b1..Power-down the USB PHY current bias block for the transmitter. This bit should be set only when the + */ +#define USBPHY_PWD_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_TXPWDIBIAS_MASK) + +#define USBPHY_PWD_TXPWDV2I_MASK (0x1000U) +#define USBPHY_PWD_TXPWDV2I_SHIFT (12U) +/*! TXPWDV2I + * 0b0..Normal operation. + * 0b1..Power-down the USB PHY transmit V-to-I converter and the current mirror + */ +#define USBPHY_PWD_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDV2I_SHIFT)) & USBPHY_PWD_TXPWDV2I_MASK) + +#define USBPHY_PWD_RXPWDENV_MASK (0x20000U) +#define USBPHY_PWD_RXPWDENV_SHIFT (17U) +/*! RXPWDENV + * 0b0..Normal operation. + * 0b1..Power-down the USB high-speed receiver envelope detector (squelch signal) + */ +#define USBPHY_PWD_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDENV_SHIFT)) & USBPHY_PWD_RXPWDENV_MASK) + +#define USBPHY_PWD_RXPWD1PT1_MASK (0x40000U) +#define USBPHY_PWD_RXPWD1PT1_SHIFT (18U) +/*! RXPWD1PT1 + * 0b0..Normal operation. + * 0b1..Power-down the USB full-speed differential receiver. + */ +#define USBPHY_PWD_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWD1PT1_SHIFT)) & USBPHY_PWD_RXPWD1PT1_MASK) + +#define USBPHY_PWD_RXPWDDIFF_MASK (0x80000U) +#define USBPHY_PWD_RXPWDDIFF_SHIFT (19U) +/*! RXPWDDIFF + * 0b0..Normal operation. + * 0b1..Power-down the USB high-speed differential receive + */ +#define USBPHY_PWD_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDDIFF_SHIFT)) & USBPHY_PWD_RXPWDDIFF_MASK) + +#define USBPHY_PWD_RXPWDRX_MASK (0x100000U) +#define USBPHY_PWD_RXPWDRX_SHIFT (20U) +/*! RXPWDRX + * 0b0..Normal operation. + * 0b1..Power-down the entire USB PHY receiver block except for the full-speed differential receiver + */ +#define USBPHY_PWD_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDRX_SHIFT)) & USBPHY_PWD_RXPWDRX_MASK) +/*! @} */ + +/*! @name PWD_SET - USB PHY Power-Down Register */ +/*! @{ */ + +#define USBPHY_PWD_SET_TXPWDFS_MASK (0x400U) +#define USBPHY_PWD_SET_TXPWDFS_SHIFT (10U) +/*! TXPWDFS + * 0b0..Normal operation. + * 0b1..Power-down the USB full-speed drivers. This turns off the current starvation sources and puts the + */ +#define USBPHY_PWD_SET_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDFS_SHIFT)) & USBPHY_PWD_SET_TXPWDFS_MASK) + +#define USBPHY_PWD_SET_TXPWDIBIAS_MASK (0x800U) +#define USBPHY_PWD_SET_TXPWDIBIAS_SHIFT (11U) +/*! TXPWDIBIAS + * 0b0..Normal operation. + * 0b1..Power-down the USB PHY current bias block for the transmitter. This bit should be set only when the + */ +#define USBPHY_PWD_SET_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_SET_TXPWDIBIAS_MASK) + +#define USBPHY_PWD_SET_TXPWDV2I_MASK (0x1000U) +#define USBPHY_PWD_SET_TXPWDV2I_SHIFT (12U) +/*! TXPWDV2I + * 0b0..Normal operation. + * 0b1..Power-down the USB PHY transmit V-to-I converter and the current mirror + */ +#define USBPHY_PWD_SET_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDV2I_SHIFT)) & USBPHY_PWD_SET_TXPWDV2I_MASK) + +#define USBPHY_PWD_SET_RXPWDENV_MASK (0x20000U) +#define USBPHY_PWD_SET_RXPWDENV_SHIFT (17U) +/*! RXPWDENV + * 0b0..Normal operation. + * 0b1..Power-down the USB high-speed receiver envelope detector (squelch signal) + */ +#define USBPHY_PWD_SET_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDENV_SHIFT)) & USBPHY_PWD_SET_RXPWDENV_MASK) + +#define USBPHY_PWD_SET_RXPWD1PT1_MASK (0x40000U) +#define USBPHY_PWD_SET_RXPWD1PT1_SHIFT (18U) +/*! RXPWD1PT1 + * 0b0..Normal operation. + * 0b1..Power-down the USB full-speed differential receiver. + */ +#define USBPHY_PWD_SET_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWD1PT1_SHIFT)) & USBPHY_PWD_SET_RXPWD1PT1_MASK) + +#define USBPHY_PWD_SET_RXPWDDIFF_MASK (0x80000U) +#define USBPHY_PWD_SET_RXPWDDIFF_SHIFT (19U) +/*! RXPWDDIFF + * 0b0..Normal operation. + * 0b1..Power-down the USB high-speed differential receive + */ +#define USBPHY_PWD_SET_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDDIFF_SHIFT)) & USBPHY_PWD_SET_RXPWDDIFF_MASK) + +#define USBPHY_PWD_SET_RXPWDRX_MASK (0x100000U) +#define USBPHY_PWD_SET_RXPWDRX_SHIFT (20U) +/*! RXPWDRX + * 0b0..Normal operation. + * 0b1..Power-down the entire USB PHY receiver block except for the full-speed differential receiver + */ +#define USBPHY_PWD_SET_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDRX_SHIFT)) & USBPHY_PWD_SET_RXPWDRX_MASK) +/*! @} */ + +/*! @name PWD_CLR - USB PHY Power-Down Register */ +/*! @{ */ + +#define USBPHY_PWD_CLR_TXPWDFS_MASK (0x400U) +#define USBPHY_PWD_CLR_TXPWDFS_SHIFT (10U) +/*! TXPWDFS + * 0b0..Normal operation. + * 0b1..Power-down the USB full-speed drivers. This turns off the current starvation sources and puts the + */ +#define USBPHY_PWD_CLR_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDFS_SHIFT)) & USBPHY_PWD_CLR_TXPWDFS_MASK) + +#define USBPHY_PWD_CLR_TXPWDIBIAS_MASK (0x800U) +#define USBPHY_PWD_CLR_TXPWDIBIAS_SHIFT (11U) +/*! TXPWDIBIAS + * 0b0..Normal operation. + * 0b1..Power-down the USB PHY current bias block for the transmitter. This bit should be set only when the + */ +#define USBPHY_PWD_CLR_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_CLR_TXPWDIBIAS_MASK) + +#define USBPHY_PWD_CLR_TXPWDV2I_MASK (0x1000U) +#define USBPHY_PWD_CLR_TXPWDV2I_SHIFT (12U) +/*! TXPWDV2I + * 0b0..Normal operation. + * 0b1..Power-down the USB PHY transmit V-to-I converter and the current mirror + */ +#define USBPHY_PWD_CLR_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDV2I_SHIFT)) & USBPHY_PWD_CLR_TXPWDV2I_MASK) + +#define USBPHY_PWD_CLR_RXPWDENV_MASK (0x20000U) +#define USBPHY_PWD_CLR_RXPWDENV_SHIFT (17U) +/*! RXPWDENV + * 0b0..Normal operation. + * 0b1..Power-down the USB high-speed receiver envelope detector (squelch signal) + */ +#define USBPHY_PWD_CLR_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDENV_SHIFT)) & USBPHY_PWD_CLR_RXPWDENV_MASK) + +#define USBPHY_PWD_CLR_RXPWD1PT1_MASK (0x40000U) +#define USBPHY_PWD_CLR_RXPWD1PT1_SHIFT (18U) +/*! RXPWD1PT1 + * 0b0..Normal operation. + * 0b1..Power-down the USB full-speed differential receiver. + */ +#define USBPHY_PWD_CLR_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWD1PT1_SHIFT)) & USBPHY_PWD_CLR_RXPWD1PT1_MASK) + +#define USBPHY_PWD_CLR_RXPWDDIFF_MASK (0x80000U) +#define USBPHY_PWD_CLR_RXPWDDIFF_SHIFT (19U) +/*! RXPWDDIFF + * 0b0..Normal operation. + * 0b1..Power-down the USB high-speed differential receive + */ +#define USBPHY_PWD_CLR_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDDIFF_SHIFT)) & USBPHY_PWD_CLR_RXPWDDIFF_MASK) + +#define USBPHY_PWD_CLR_RXPWDRX_MASK (0x100000U) +#define USBPHY_PWD_CLR_RXPWDRX_SHIFT (20U) +/*! RXPWDRX + * 0b0..Normal operation. + * 0b1..Power-down the entire USB PHY receiver block except for the full-speed differential receiver + */ +#define USBPHY_PWD_CLR_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDRX_SHIFT)) & USBPHY_PWD_CLR_RXPWDRX_MASK) +/*! @} */ + +/*! @name PWD_TOG - USB PHY Power-Down Register */ +/*! @{ */ + +#define USBPHY_PWD_TOG_TXPWDFS_MASK (0x400U) +#define USBPHY_PWD_TOG_TXPWDFS_SHIFT (10U) +/*! TXPWDFS + * 0b0..Normal operation. + * 0b1..Power-down the USB full-speed drivers. This turns off the current starvation sources and puts the + */ +#define USBPHY_PWD_TOG_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDFS_SHIFT)) & USBPHY_PWD_TOG_TXPWDFS_MASK) + +#define USBPHY_PWD_TOG_TXPWDIBIAS_MASK (0x800U) +#define USBPHY_PWD_TOG_TXPWDIBIAS_SHIFT (11U) +/*! TXPWDIBIAS + * 0b0..Normal operation. + * 0b1..Power-down the USB PHY current bias block for the transmitter. This bit should be set only when the + */ +#define USBPHY_PWD_TOG_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_TOG_TXPWDIBIAS_MASK) + +#define USBPHY_PWD_TOG_TXPWDV2I_MASK (0x1000U) +#define USBPHY_PWD_TOG_TXPWDV2I_SHIFT (12U) +/*! TXPWDV2I + * 0b0..Normal operation. + * 0b1..Power-down the USB PHY transmit V-to-I converter and the current mirror + */ +#define USBPHY_PWD_TOG_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDV2I_SHIFT)) & USBPHY_PWD_TOG_TXPWDV2I_MASK) + +#define USBPHY_PWD_TOG_RXPWDENV_MASK (0x20000U) +#define USBPHY_PWD_TOG_RXPWDENV_SHIFT (17U) +/*! RXPWDENV + * 0b0..Normal operation. + * 0b1..Power-down the USB high-speed receiver envelope detector (squelch signal) + */ +#define USBPHY_PWD_TOG_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDENV_SHIFT)) & USBPHY_PWD_TOG_RXPWDENV_MASK) + +#define USBPHY_PWD_TOG_RXPWD1PT1_MASK (0x40000U) +#define USBPHY_PWD_TOG_RXPWD1PT1_SHIFT (18U) +/*! RXPWD1PT1 + * 0b0..Normal operation. + * 0b1..Power-down the USB full-speed differential receiver. + */ +#define USBPHY_PWD_TOG_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWD1PT1_SHIFT)) & USBPHY_PWD_TOG_RXPWD1PT1_MASK) + +#define USBPHY_PWD_TOG_RXPWDDIFF_MASK (0x80000U) +#define USBPHY_PWD_TOG_RXPWDDIFF_SHIFT (19U) +/*! RXPWDDIFF + * 0b0..Normal operation. + * 0b1..Power-down the USB high-speed differential receive + */ +#define USBPHY_PWD_TOG_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDDIFF_SHIFT)) & USBPHY_PWD_TOG_RXPWDDIFF_MASK) + +#define USBPHY_PWD_TOG_RXPWDRX_MASK (0x100000U) +#define USBPHY_PWD_TOG_RXPWDRX_SHIFT (20U) +/*! RXPWDRX + * 0b0..Normal operation. + * 0b1..Power-down the entire USB PHY receiver block except for the full-speed differential receiver + */ +#define USBPHY_PWD_TOG_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDRX_SHIFT)) & USBPHY_PWD_TOG_RXPWDRX_MASK) +/*! @} */ + +/*! @name TX - USB PHY Transmitter Control Register */ +/*! @{ */ + +#define USBPHY_TX_D_CAL_MASK (0xFU) +#define USBPHY_TX_D_CAL_SHIFT (0U) +/*! D_CAL + * 0b0000..Maximum current, approximately 19% above nominal. + * 0b0111..Nominal + * 0b1111..Minimum current, approximately 19% below nominal. + */ +#define USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TX_D_CAL_MASK) + +#define USBPHY_TX_TXCAL45DM_MASK (0xF00U) +#define USBPHY_TX_TXCAL45DM_SHIFT (8U) +#define USBPHY_TX_TXCAL45DM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXCAL45DM_SHIFT)) & USBPHY_TX_TXCAL45DM_MASK) + +#define USBPHY_TX_TXENCAL45DN_MASK (0x2000U) +#define USBPHY_TX_TXENCAL45DN_SHIFT (13U) +#define USBPHY_TX_TXENCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXENCAL45DN_SHIFT)) & USBPHY_TX_TXENCAL45DN_MASK) + +#define USBPHY_TX_TXCAL45DP_MASK (0xF0000U) +#define USBPHY_TX_TXCAL45DP_SHIFT (16U) +#define USBPHY_TX_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXCAL45DP_SHIFT)) & USBPHY_TX_TXCAL45DP_MASK) + +#define USBPHY_TX_TXENCAL45DP_MASK (0x200000U) +#define USBPHY_TX_TXENCAL45DP_SHIFT (21U) +#define USBPHY_TX_TXENCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXENCAL45DP_SHIFT)) & USBPHY_TX_TXENCAL45DP_MASK) +/*! @} */ + +/*! @name TX_SET - USB PHY Transmitter Control Register */ +/*! @{ */ + +#define USBPHY_TX_SET_D_CAL_MASK (0xFU) +#define USBPHY_TX_SET_D_CAL_SHIFT (0U) +/*! D_CAL + * 0b0000..Maximum current, approximately 19% above nominal. + * 0b0111..Nominal + * 0b1111..Minimum current, approximately 19% below nominal. + */ +#define USBPHY_TX_SET_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_D_CAL_SHIFT)) & USBPHY_TX_SET_D_CAL_MASK) + +#define USBPHY_TX_SET_TXCAL45DM_MASK (0xF00U) +#define USBPHY_TX_SET_TXCAL45DM_SHIFT (8U) +#define USBPHY_TX_SET_TXCAL45DM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXCAL45DM_SHIFT)) & USBPHY_TX_SET_TXCAL45DM_MASK) + +#define USBPHY_TX_SET_TXENCAL45DN_MASK (0x2000U) +#define USBPHY_TX_SET_TXENCAL45DN_SHIFT (13U) +#define USBPHY_TX_SET_TXENCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXENCAL45DN_SHIFT)) & USBPHY_TX_SET_TXENCAL45DN_MASK) + +#define USBPHY_TX_SET_TXCAL45DP_MASK (0xF0000U) +#define USBPHY_TX_SET_TXCAL45DP_SHIFT (16U) +#define USBPHY_TX_SET_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXCAL45DP_SHIFT)) & USBPHY_TX_SET_TXCAL45DP_MASK) + +#define USBPHY_TX_SET_TXENCAL45DP_MASK (0x200000U) +#define USBPHY_TX_SET_TXENCAL45DP_SHIFT (21U) +#define USBPHY_TX_SET_TXENCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXENCAL45DP_SHIFT)) & USBPHY_TX_SET_TXENCAL45DP_MASK) +/*! @} */ + +/*! @name TX_CLR - USB PHY Transmitter Control Register */ +/*! @{ */ + +#define USBPHY_TX_CLR_D_CAL_MASK (0xFU) +#define USBPHY_TX_CLR_D_CAL_SHIFT (0U) +/*! D_CAL + * 0b0000..Maximum current, approximately 19% above nominal. + * 0b0111..Nominal + * 0b1111..Minimum current, approximately 19% below nominal. + */ +#define USBPHY_TX_CLR_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_D_CAL_SHIFT)) & USBPHY_TX_CLR_D_CAL_MASK) + +#define USBPHY_TX_CLR_TXCAL45DM_MASK (0xF00U) +#define USBPHY_TX_CLR_TXCAL45DM_SHIFT (8U) +#define USBPHY_TX_CLR_TXCAL45DM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXCAL45DM_SHIFT)) & USBPHY_TX_CLR_TXCAL45DM_MASK) + +#define USBPHY_TX_CLR_TXENCAL45DN_MASK (0x2000U) +#define USBPHY_TX_CLR_TXENCAL45DN_SHIFT (13U) +#define USBPHY_TX_CLR_TXENCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXENCAL45DN_SHIFT)) & USBPHY_TX_CLR_TXENCAL45DN_MASK) + +#define USBPHY_TX_CLR_TXCAL45DP_MASK (0xF0000U) +#define USBPHY_TX_CLR_TXCAL45DP_SHIFT (16U) +#define USBPHY_TX_CLR_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXCAL45DP_SHIFT)) & USBPHY_TX_CLR_TXCAL45DP_MASK) + +#define USBPHY_TX_CLR_TXENCAL45DP_MASK (0x200000U) +#define USBPHY_TX_CLR_TXENCAL45DP_SHIFT (21U) +#define USBPHY_TX_CLR_TXENCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXENCAL45DP_SHIFT)) & USBPHY_TX_CLR_TXENCAL45DP_MASK) +/*! @} */ + +/*! @name TX_TOG - USB PHY Transmitter Control Register */ +/*! @{ */ + +#define USBPHY_TX_TOG_D_CAL_MASK (0xFU) +#define USBPHY_TX_TOG_D_CAL_SHIFT (0U) +/*! D_CAL + * 0b0000..Maximum current, approximately 19% above nominal. + * 0b0111..Nominal + * 0b1111..Minimum current, approximately 19% below nominal. + */ +#define USBPHY_TX_TOG_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_D_CAL_SHIFT)) & USBPHY_TX_TOG_D_CAL_MASK) + +#define USBPHY_TX_TOG_TXCAL45DM_MASK (0xF00U) +#define USBPHY_TX_TOG_TXCAL45DM_SHIFT (8U) +#define USBPHY_TX_TOG_TXCAL45DM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXCAL45DM_SHIFT)) & USBPHY_TX_TOG_TXCAL45DM_MASK) + +#define USBPHY_TX_TOG_TXENCAL45DN_MASK (0x2000U) +#define USBPHY_TX_TOG_TXENCAL45DN_SHIFT (13U) +#define USBPHY_TX_TOG_TXENCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXENCAL45DN_SHIFT)) & USBPHY_TX_TOG_TXENCAL45DN_MASK) + +#define USBPHY_TX_TOG_TXCAL45DP_MASK (0xF0000U) +#define USBPHY_TX_TOG_TXCAL45DP_SHIFT (16U) +#define USBPHY_TX_TOG_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXCAL45DP_SHIFT)) & USBPHY_TX_TOG_TXCAL45DP_MASK) + +#define USBPHY_TX_TOG_TXENCAL45DP_MASK (0x200000U) +#define USBPHY_TX_TOG_TXENCAL45DP_SHIFT (21U) +#define USBPHY_TX_TOG_TXENCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXENCAL45DP_SHIFT)) & USBPHY_TX_TOG_TXENCAL45DP_MASK) +/*! @} */ + +/*! @name RX - USB PHY Receiver Control Register */ +/*! @{ */ + +#define USBPHY_RX_ENVADJ_MASK (0x7U) +#define USBPHY_RX_ENVADJ_SHIFT (0U) +/*! ENVADJ + * 0b000..Trip-Level Voltage is 0.1000 V + * 0b001..Trip-Level Voltage is 0.1125 V + * 0b010..Trip-Level Voltage is 0.1250 V + * 0b011..Trip-Level Voltage is 0.0875 V + * 0b100..reserved + * 0b101..reserved + * 0b110..reserved + * 0b111..reserved + */ +#define USBPHY_RX_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_ENVADJ_SHIFT)) & USBPHY_RX_ENVADJ_MASK) + +#define USBPHY_RX_DISCONADJ_MASK (0x70U) +#define USBPHY_RX_DISCONADJ_SHIFT (4U) +/*! DISCONADJ + * 0b000..Trip-Level Voltage is 0.56875 V + * 0b001..Trip-Level Voltage is 0.55000 V + * 0b010..Trip-Level Voltage is 0.58125 V + * 0b011..Trip-Level Voltage is 0.60000 V + * 0b100..reserved + * 0b101..reserved + * 0b110..reserved + * 0b111..reserved + */ +#define USBPHY_RX_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_DISCONADJ_SHIFT)) & USBPHY_RX_DISCONADJ_MASK) + +#define USBPHY_RX_RXDBYPASS_MASK (0x400000U) +#define USBPHY_RX_RXDBYPASS_SHIFT (22U) +/*! RXDBYPASS + * 0b0..Normal operation. + * 0b1..Use the output of the USB_DP single-ended receiver in place of the full-speed differential receiver + */ +#define USBPHY_RX_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_RXDBYPASS_SHIFT)) & USBPHY_RX_RXDBYPASS_MASK) +/*! @} */ + +/*! @name RX_SET - USB PHY Receiver Control Register */ +/*! @{ */ + +#define USBPHY_RX_SET_ENVADJ_MASK (0x7U) +#define USBPHY_RX_SET_ENVADJ_SHIFT (0U) +/*! ENVADJ + * 0b000..Trip-Level Voltage is 0.1000 V + * 0b001..Trip-Level Voltage is 0.1125 V + * 0b010..Trip-Level Voltage is 0.1250 V + * 0b011..Trip-Level Voltage is 0.0875 V + * 0b100..reserved + * 0b101..reserved + * 0b110..reserved + * 0b111..reserved + */ +#define USBPHY_RX_SET_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_ENVADJ_SHIFT)) & USBPHY_RX_SET_ENVADJ_MASK) + +#define USBPHY_RX_SET_DISCONADJ_MASK (0x70U) +#define USBPHY_RX_SET_DISCONADJ_SHIFT (4U) +/*! DISCONADJ + * 0b000..Trip-Level Voltage is 0.56875 V + * 0b001..Trip-Level Voltage is 0.55000 V + * 0b010..Trip-Level Voltage is 0.58125 V + * 0b011..Trip-Level Voltage is 0.60000 V + * 0b100..reserved + * 0b101..reserved + * 0b110..reserved + * 0b111..reserved + */ +#define USBPHY_RX_SET_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_DISCONADJ_SHIFT)) & USBPHY_RX_SET_DISCONADJ_MASK) + +#define USBPHY_RX_SET_RXDBYPASS_MASK (0x400000U) +#define USBPHY_RX_SET_RXDBYPASS_SHIFT (22U) +/*! RXDBYPASS + * 0b0..Normal operation. + * 0b1..Use the output of the USB_DP single-ended receiver in place of the full-speed differential receiver + */ +#define USBPHY_RX_SET_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_RXDBYPASS_SHIFT)) & USBPHY_RX_SET_RXDBYPASS_MASK) +/*! @} */ + +/*! @name RX_CLR - USB PHY Receiver Control Register */ +/*! @{ */ + +#define USBPHY_RX_CLR_ENVADJ_MASK (0x7U) +#define USBPHY_RX_CLR_ENVADJ_SHIFT (0U) +/*! ENVADJ + * 0b000..Trip-Level Voltage is 0.1000 V + * 0b001..Trip-Level Voltage is 0.1125 V + * 0b010..Trip-Level Voltage is 0.1250 V + * 0b011..Trip-Level Voltage is 0.0875 V + * 0b100..reserved + * 0b101..reserved + * 0b110..reserved + * 0b111..reserved + */ +#define USBPHY_RX_CLR_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_ENVADJ_SHIFT)) & USBPHY_RX_CLR_ENVADJ_MASK) + +#define USBPHY_RX_CLR_DISCONADJ_MASK (0x70U) +#define USBPHY_RX_CLR_DISCONADJ_SHIFT (4U) +/*! DISCONADJ + * 0b000..Trip-Level Voltage is 0.56875 V + * 0b001..Trip-Level Voltage is 0.55000 V + * 0b010..Trip-Level Voltage is 0.58125 V + * 0b011..Trip-Level Voltage is 0.60000 V + * 0b100..reserved + * 0b101..reserved + * 0b110..reserved + * 0b111..reserved + */ +#define USBPHY_RX_CLR_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_DISCONADJ_SHIFT)) & USBPHY_RX_CLR_DISCONADJ_MASK) + +#define USBPHY_RX_CLR_RXDBYPASS_MASK (0x400000U) +#define USBPHY_RX_CLR_RXDBYPASS_SHIFT (22U) +/*! RXDBYPASS + * 0b0..Normal operation. + * 0b1..Use the output of the USB_DP single-ended receiver in place of the full-speed differential receiver + */ +#define USBPHY_RX_CLR_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_RXDBYPASS_SHIFT)) & USBPHY_RX_CLR_RXDBYPASS_MASK) +/*! @} */ + +/*! @name RX_TOG - USB PHY Receiver Control Register */ +/*! @{ */ + +#define USBPHY_RX_TOG_ENVADJ_MASK (0x7U) +#define USBPHY_RX_TOG_ENVADJ_SHIFT (0U) +/*! ENVADJ + * 0b000..Trip-Level Voltage is 0.1000 V + * 0b001..Trip-Level Voltage is 0.1125 V + * 0b010..Trip-Level Voltage is 0.1250 V + * 0b011..Trip-Level Voltage is 0.0875 V + * 0b100..reserved + * 0b101..reserved + * 0b110..reserved + * 0b111..reserved + */ +#define USBPHY_RX_TOG_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_ENVADJ_SHIFT)) & USBPHY_RX_TOG_ENVADJ_MASK) + +#define USBPHY_RX_TOG_DISCONADJ_MASK (0x70U) +#define USBPHY_RX_TOG_DISCONADJ_SHIFT (4U) +/*! DISCONADJ + * 0b000..Trip-Level Voltage is 0.56875 V + * 0b001..Trip-Level Voltage is 0.55000 V + * 0b010..Trip-Level Voltage is 0.58125 V + * 0b011..Trip-Level Voltage is 0.60000 V + * 0b100..reserved + * 0b101..reserved + * 0b110..reserved + * 0b111..reserved + */ +#define USBPHY_RX_TOG_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_DISCONADJ_SHIFT)) & USBPHY_RX_TOG_DISCONADJ_MASK) + +#define USBPHY_RX_TOG_RXDBYPASS_MASK (0x400000U) +#define USBPHY_RX_TOG_RXDBYPASS_SHIFT (22U) +/*! RXDBYPASS + * 0b0..Normal operation. + * 0b1..Use the output of the USB_DP single-ended receiver in place of the full-speed differential receiver + */ +#define USBPHY_RX_TOG_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_RXDBYPASS_SHIFT)) & USBPHY_RX_TOG_RXDBYPASS_MASK) +/*! @} */ + +/*! @name CTRL - USB PHY General Control Register */ +/*! @{ */ + +#define USBPHY_CTRL_ENHOSTDISCONDETECT_MASK (0x2U) +#define USBPHY_CTRL_ENHOSTDISCONDETECT_SHIFT (1U) +#define USBPHY_CTRL_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_ENHOSTDISCONDETECT_MASK) + +#define USBPHY_CTRL_ENIRQHOSTDISCON_MASK (0x4U) +#define USBPHY_CTRL_ENIRQHOSTDISCON_SHIFT (2U) +#define USBPHY_CTRL_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_ENIRQHOSTDISCON_MASK) + +#define USBPHY_CTRL_HOSTDISCONDETECT_IRQ_MASK (0x8U) +#define USBPHY_CTRL_HOSTDISCONDETECT_IRQ_SHIFT (3U) +#define USBPHY_CTRL_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_HOSTDISCONDETECT_IRQ_MASK) + +#define USBPHY_CTRL_ENDEVPLUGINDET_MASK (0x10U) +#define USBPHY_CTRL_ENDEVPLUGINDET_SHIFT (4U) +/*! ENDEVPLUGINDET + * 0b0..Disables 200kohm pullup resistors on USB_DP and USB_DM pins (Default) + * 0b1..Enables 200kohm pullup resistors on USB_DP and USB_DM pins + */ +#define USBPHY_CTRL_ENDEVPLUGINDET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENDEVPLUGINDET_SHIFT)) & USBPHY_CTRL_ENDEVPLUGINDET_MASK) + +#define USBPHY_CTRL_DEVPLUGIN_POLARITY_MASK (0x20U) +#define USBPHY_CTRL_DEVPLUGIN_POLARITY_SHIFT (5U) +#define USBPHY_CTRL_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_DEVPLUGIN_POLARITY_MASK) + +#define USBPHY_CTRL_RESUMEIRQSTICKY_MASK (0x100U) +#define USBPHY_CTRL_RESUMEIRQSTICKY_SHIFT (8U) +#define USBPHY_CTRL_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_RESUMEIRQSTICKY_MASK) + +#define USBPHY_CTRL_ENIRQRESUMEDETECT_MASK (0x200U) +#define USBPHY_CTRL_ENIRQRESUMEDETECT_SHIFT (9U) +#define USBPHY_CTRL_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_ENIRQRESUMEDETECT_MASK) + +#define USBPHY_CTRL_RESUME_IRQ_MASK (0x400U) +#define USBPHY_CTRL_RESUME_IRQ_SHIFT (10U) +#define USBPHY_CTRL_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_RESUME_IRQ_MASK) + +#define USBPHY_CTRL_DEVPLUGIN_IRQ_MASK (0x1000U) +#define USBPHY_CTRL_DEVPLUGIN_IRQ_SHIFT (12U) +#define USBPHY_CTRL_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_DEVPLUGIN_IRQ_MASK) + +#define USBPHY_CTRL_ENUTMILEVEL2_MASK (0x4000U) +#define USBPHY_CTRL_ENUTMILEVEL2_SHIFT (14U) +#define USBPHY_CTRL_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_ENUTMILEVEL2_MASK) + +#define USBPHY_CTRL_ENUTMILEVEL3_MASK (0x8000U) +#define USBPHY_CTRL_ENUTMILEVEL3_SHIFT (15U) +#define USBPHY_CTRL_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_ENUTMILEVEL3_MASK) + +#define USBPHY_CTRL_ENIRQWAKEUP_MASK (0x10000U) +#define USBPHY_CTRL_ENIRQWAKEUP_SHIFT (16U) +#define USBPHY_CTRL_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_ENIRQWAKEUP_MASK) + +#define USBPHY_CTRL_WAKEUP_IRQ_MASK (0x20000U) +#define USBPHY_CTRL_WAKEUP_IRQ_SHIFT (17U) +#define USBPHY_CTRL_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_WAKEUP_IRQ_MASK) + +#define USBPHY_CTRL_AUTORESUME_EN_MASK (0x40000U) +#define USBPHY_CTRL_AUTORESUME_EN_SHIFT (18U) +#define USBPHY_CTRL_AUTORESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_AUTORESUME_EN_MASK) + +#define USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK (0x80000U) +#define USBPHY_CTRL_ENAUTOCLR_CLKGATE_SHIFT (19U) +#define USBPHY_CTRL_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK) + +#define USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK (0x100000U) +#define USBPHY_CTRL_ENAUTOCLR_PHY_PWD_SHIFT (20U) +#define USBPHY_CTRL_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK) + +#define USBPHY_CTRL_ENDPDMCHG_WKUP_MASK (0x200000U) +#define USBPHY_CTRL_ENDPDMCHG_WKUP_SHIFT (21U) +#define USBPHY_CTRL_ENDPDMCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_ENDPDMCHG_WKUP_MASK) + +#define USBPHY_CTRL_ENVBUSCHG_WKUP_MASK (0x800000U) +#define USBPHY_CTRL_ENVBUSCHG_WKUP_SHIFT (23U) +#define USBPHY_CTRL_ENVBUSCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_ENVBUSCHG_WKUP_MASK) + +#define USBPHY_CTRL_ENAUTOCLR_USBCLKGATE_MASK (0x2000000U) +#define USBPHY_CTRL_ENAUTOCLR_USBCLKGATE_SHIFT (25U) +#define USBPHY_CTRL_ENAUTOCLR_USBCLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOCLR_USBCLKGATE_SHIFT)) & USBPHY_CTRL_ENAUTOCLR_USBCLKGATE_MASK) + +#define USBPHY_CTRL_ENAUTOSET_USBCLKS_MASK (0x4000000U) +#define USBPHY_CTRL_ENAUTOSET_USBCLKS_SHIFT (26U) +#define USBPHY_CTRL_ENAUTOSET_USBCLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOSET_USBCLKS_SHIFT)) & USBPHY_CTRL_ENAUTOSET_USBCLKS_MASK) + +#define USBPHY_CTRL_HOST_FORCE_LS_SE0_MASK (0x10000000U) +#define USBPHY_CTRL_HOST_FORCE_LS_SE0_SHIFT (28U) +#define USBPHY_CTRL_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_HOST_FORCE_LS_SE0_MASK) + +#define USBPHY_CTRL_UTMI_SUSPENDM_MASK (0x20000000U) +#define USBPHY_CTRL_UTMI_SUSPENDM_SHIFT (29U) +#define USBPHY_CTRL_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_UTMI_SUSPENDM_MASK) + +#define USBPHY_CTRL_CLKGATE_MASK (0x40000000U) +#define USBPHY_CTRL_CLKGATE_SHIFT (30U) +#define USBPHY_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLKGATE_SHIFT)) & USBPHY_CTRL_CLKGATE_MASK) + +#define USBPHY_CTRL_SFTRST_MASK (0x80000000U) +#define USBPHY_CTRL_SFTRST_SHIFT (31U) +#define USBPHY_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SFTRST_SHIFT)) & USBPHY_CTRL_SFTRST_MASK) +/*! @} */ + +/*! @name CTRL_SET - USB PHY General Control Register */ +/*! @{ */ + +#define USBPHY_CTRL_SET_ENHOSTDISCONDETECT_MASK (0x2U) +#define USBPHY_CTRL_SET_ENHOSTDISCONDETECT_SHIFT (1U) +#define USBPHY_CTRL_SET_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_SET_ENHOSTDISCONDETECT_MASK) + +#define USBPHY_CTRL_SET_ENIRQHOSTDISCON_MASK (0x4U) +#define USBPHY_CTRL_SET_ENIRQHOSTDISCON_SHIFT (2U) +#define USBPHY_CTRL_SET_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_SET_ENIRQHOSTDISCON_MASK) + +#define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_MASK (0x8U) +#define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_SHIFT (3U) +#define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_MASK) + +#define USBPHY_CTRL_SET_ENDEVPLUGINDET_MASK (0x10U) +#define USBPHY_CTRL_SET_ENDEVPLUGINDET_SHIFT (4U) +/*! ENDEVPLUGINDET + * 0b0..Disables 200kohm pullup resistors on USB_DP and USB_DM pins (Default) + * 0b1..Enables 200kohm pullup resistors on USB_DP and USB_DM pins + */ +#define USBPHY_CTRL_SET_ENDEVPLUGINDET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENDEVPLUGINDET_SHIFT)) & USBPHY_CTRL_SET_ENDEVPLUGINDET_MASK) + +#define USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_MASK (0x20U) +#define USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_SHIFT (5U) +#define USBPHY_CTRL_SET_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_MASK) + +#define USBPHY_CTRL_SET_RESUMEIRQSTICKY_MASK (0x100U) +#define USBPHY_CTRL_SET_RESUMEIRQSTICKY_SHIFT (8U) +#define USBPHY_CTRL_SET_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_SET_RESUMEIRQSTICKY_MASK) + +#define USBPHY_CTRL_SET_ENIRQRESUMEDETECT_MASK (0x200U) +#define USBPHY_CTRL_SET_ENIRQRESUMEDETECT_SHIFT (9U) +#define USBPHY_CTRL_SET_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_SET_ENIRQRESUMEDETECT_MASK) + +#define USBPHY_CTRL_SET_RESUME_IRQ_MASK (0x400U) +#define USBPHY_CTRL_SET_RESUME_IRQ_SHIFT (10U) +#define USBPHY_CTRL_SET_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_SET_RESUME_IRQ_MASK) + +#define USBPHY_CTRL_SET_DEVPLUGIN_IRQ_MASK (0x1000U) +#define USBPHY_CTRL_SET_DEVPLUGIN_IRQ_SHIFT (12U) +#define USBPHY_CTRL_SET_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_SET_DEVPLUGIN_IRQ_MASK) + +#define USBPHY_CTRL_SET_ENUTMILEVEL2_MASK (0x4000U) +#define USBPHY_CTRL_SET_ENUTMILEVEL2_SHIFT (14U) +#define USBPHY_CTRL_SET_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_SET_ENUTMILEVEL2_MASK) + +#define USBPHY_CTRL_SET_ENUTMILEVEL3_MASK (0x8000U) +#define USBPHY_CTRL_SET_ENUTMILEVEL3_SHIFT (15U) +#define USBPHY_CTRL_SET_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_SET_ENUTMILEVEL3_MASK) + +#define USBPHY_CTRL_SET_ENIRQWAKEUP_MASK (0x10000U) +#define USBPHY_CTRL_SET_ENIRQWAKEUP_SHIFT (16U) +#define USBPHY_CTRL_SET_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_SET_ENIRQWAKEUP_MASK) + +#define USBPHY_CTRL_SET_WAKEUP_IRQ_MASK (0x20000U) +#define USBPHY_CTRL_SET_WAKEUP_IRQ_SHIFT (17U) +#define USBPHY_CTRL_SET_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_SET_WAKEUP_IRQ_MASK) + +#define USBPHY_CTRL_SET_AUTORESUME_EN_MASK (0x40000U) +#define USBPHY_CTRL_SET_AUTORESUME_EN_SHIFT (18U) +#define USBPHY_CTRL_SET_AUTORESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_SET_AUTORESUME_EN_MASK) + +#define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK (0x80000U) +#define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_SHIFT (19U) +#define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK) + +#define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK (0x100000U) +#define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_SHIFT (20U) +#define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK) + +#define USBPHY_CTRL_SET_ENDPDMCHG_WKUP_MASK (0x200000U) +#define USBPHY_CTRL_SET_ENDPDMCHG_WKUP_SHIFT (21U) +#define USBPHY_CTRL_SET_ENDPDMCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_SET_ENDPDMCHG_WKUP_MASK) + +#define USBPHY_CTRL_SET_ENVBUSCHG_WKUP_MASK (0x800000U) +#define USBPHY_CTRL_SET_ENVBUSCHG_WKUP_SHIFT (23U) +#define USBPHY_CTRL_SET_ENVBUSCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_SET_ENVBUSCHG_WKUP_MASK) + +#define USBPHY_CTRL_SET_ENAUTOCLR_USBCLKGATE_MASK (0x2000000U) +#define USBPHY_CTRL_SET_ENAUTOCLR_USBCLKGATE_SHIFT (25U) +#define USBPHY_CTRL_SET_ENAUTOCLR_USBCLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOCLR_USBCLKGATE_SHIFT)) & USBPHY_CTRL_SET_ENAUTOCLR_USBCLKGATE_MASK) + +#define USBPHY_CTRL_SET_ENAUTOSET_USBCLKS_MASK (0x4000000U) +#define USBPHY_CTRL_SET_ENAUTOSET_USBCLKS_SHIFT (26U) +#define USBPHY_CTRL_SET_ENAUTOSET_USBCLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOSET_USBCLKS_SHIFT)) & USBPHY_CTRL_SET_ENAUTOSET_USBCLKS_MASK) + +#define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_MASK (0x10000000U) +#define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_SHIFT (28U) +#define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_MASK) + +#define USBPHY_CTRL_SET_UTMI_SUSPENDM_MASK (0x20000000U) +#define USBPHY_CTRL_SET_UTMI_SUSPENDM_SHIFT (29U) +#define USBPHY_CTRL_SET_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_SET_UTMI_SUSPENDM_MASK) + +#define USBPHY_CTRL_SET_CLKGATE_MASK (0x40000000U) +#define USBPHY_CTRL_SET_CLKGATE_SHIFT (30U) +#define USBPHY_CTRL_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_CLKGATE_SHIFT)) & USBPHY_CTRL_SET_CLKGATE_MASK) + +#define USBPHY_CTRL_SET_SFTRST_MASK (0x80000000U) +#define USBPHY_CTRL_SET_SFTRST_SHIFT (31U) +#define USBPHY_CTRL_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_SFTRST_SHIFT)) & USBPHY_CTRL_SET_SFTRST_MASK) +/*! @} */ + +/*! @name CTRL_CLR - USB PHY General Control Register */ +/*! @{ */ + +#define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_MASK (0x2U) +#define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_SHIFT (1U) +#define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_MASK) + +#define USBPHY_CTRL_CLR_ENIRQHOSTDISCON_MASK (0x4U) +#define USBPHY_CTRL_CLR_ENIRQHOSTDISCON_SHIFT (2U) +#define USBPHY_CTRL_CLR_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_CLR_ENIRQHOSTDISCON_MASK) + +#define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_MASK (0x8U) +#define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_SHIFT (3U) +#define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_MASK) + +#define USBPHY_CTRL_CLR_ENDEVPLUGINDET_MASK (0x10U) +#define USBPHY_CTRL_CLR_ENDEVPLUGINDET_SHIFT (4U) +/*! ENDEVPLUGINDET + * 0b0..Disables 200kohm pullup resistors on USB_DP and USB_DM pins (Default) + * 0b1..Enables 200kohm pullup resistors on USB_DP and USB_DM pins + */ +#define USBPHY_CTRL_CLR_ENDEVPLUGINDET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENDEVPLUGINDET_SHIFT)) & USBPHY_CTRL_CLR_ENDEVPLUGINDET_MASK) + +#define USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_MASK (0x20U) +#define USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_SHIFT (5U) +#define USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_MASK) + +#define USBPHY_CTRL_CLR_RESUMEIRQSTICKY_MASK (0x100U) +#define USBPHY_CTRL_CLR_RESUMEIRQSTICKY_SHIFT (8U) +#define USBPHY_CTRL_CLR_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_CLR_RESUMEIRQSTICKY_MASK) + +#define USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_MASK (0x200U) +#define USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_SHIFT (9U) +#define USBPHY_CTRL_CLR_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_MASK) + +#define USBPHY_CTRL_CLR_RESUME_IRQ_MASK (0x400U) +#define USBPHY_CTRL_CLR_RESUME_IRQ_SHIFT (10U) +#define USBPHY_CTRL_CLR_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_CLR_RESUME_IRQ_MASK) + +#define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_MASK (0x1000U) +#define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_SHIFT (12U) +#define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_MASK) + +#define USBPHY_CTRL_CLR_ENUTMILEVEL2_MASK (0x4000U) +#define USBPHY_CTRL_CLR_ENUTMILEVEL2_SHIFT (14U) +#define USBPHY_CTRL_CLR_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_CLR_ENUTMILEVEL2_MASK) + +#define USBPHY_CTRL_CLR_ENUTMILEVEL3_MASK (0x8000U) +#define USBPHY_CTRL_CLR_ENUTMILEVEL3_SHIFT (15U) +#define USBPHY_CTRL_CLR_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_CLR_ENUTMILEVEL3_MASK) + +#define USBPHY_CTRL_CLR_ENIRQWAKEUP_MASK (0x10000U) +#define USBPHY_CTRL_CLR_ENIRQWAKEUP_SHIFT (16U) +#define USBPHY_CTRL_CLR_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_CLR_ENIRQWAKEUP_MASK) + +#define USBPHY_CTRL_CLR_WAKEUP_IRQ_MASK (0x20000U) +#define USBPHY_CTRL_CLR_WAKEUP_IRQ_SHIFT (17U) +#define USBPHY_CTRL_CLR_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_CLR_WAKEUP_IRQ_MASK) + +#define USBPHY_CTRL_CLR_AUTORESUME_EN_MASK (0x40000U) +#define USBPHY_CTRL_CLR_AUTORESUME_EN_SHIFT (18U) +#define USBPHY_CTRL_CLR_AUTORESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_CLR_AUTORESUME_EN_MASK) + +#define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_MASK (0x80000U) +#define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_SHIFT (19U) +#define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_MASK) + +#define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_MASK (0x100000U) +#define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_SHIFT (20U) +#define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_MASK) + +#define USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_MASK (0x200000U) +#define USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_SHIFT (21U) +#define USBPHY_CTRL_CLR_ENDPDMCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_MASK) + +#define USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_MASK (0x800000U) +#define USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_SHIFT (23U) +#define USBPHY_CTRL_CLR_ENVBUSCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_MASK) + +#define USBPHY_CTRL_CLR_ENAUTOCLR_USBCLKGATE_MASK (0x2000000U) +#define USBPHY_CTRL_CLR_ENAUTOCLR_USBCLKGATE_SHIFT (25U) +#define USBPHY_CTRL_CLR_ENAUTOCLR_USBCLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOCLR_USBCLKGATE_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOCLR_USBCLKGATE_MASK) + +#define USBPHY_CTRL_CLR_ENAUTOSET_USBCLKS_MASK (0x4000000U) +#define USBPHY_CTRL_CLR_ENAUTOSET_USBCLKS_SHIFT (26U) +#define USBPHY_CTRL_CLR_ENAUTOSET_USBCLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOSET_USBCLKS_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOSET_USBCLKS_MASK) + +#define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_MASK (0x10000000U) +#define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_SHIFT (28U) +#define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_MASK) + +#define USBPHY_CTRL_CLR_UTMI_SUSPENDM_MASK (0x20000000U) +#define USBPHY_CTRL_CLR_UTMI_SUSPENDM_SHIFT (29U) +#define USBPHY_CTRL_CLR_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_CLR_UTMI_SUSPENDM_MASK) + +#define USBPHY_CTRL_CLR_CLKGATE_MASK (0x40000000U) +#define USBPHY_CTRL_CLR_CLKGATE_SHIFT (30U) +#define USBPHY_CTRL_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_CLKGATE_SHIFT)) & USBPHY_CTRL_CLR_CLKGATE_MASK) + +#define USBPHY_CTRL_CLR_SFTRST_MASK (0x80000000U) +#define USBPHY_CTRL_CLR_SFTRST_SHIFT (31U) +#define USBPHY_CTRL_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_SFTRST_SHIFT)) & USBPHY_CTRL_CLR_SFTRST_MASK) +/*! @} */ + +/*! @name CTRL_TOG - USB PHY General Control Register */ +/*! @{ */ + +#define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_MASK (0x2U) +#define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_SHIFT (1U) +#define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_MASK) + +#define USBPHY_CTRL_TOG_ENIRQHOSTDISCON_MASK (0x4U) +#define USBPHY_CTRL_TOG_ENIRQHOSTDISCON_SHIFT (2U) +#define USBPHY_CTRL_TOG_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_TOG_ENIRQHOSTDISCON_MASK) + +#define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_MASK (0x8U) +#define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_SHIFT (3U) +#define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_MASK) + +#define USBPHY_CTRL_TOG_ENDEVPLUGINDET_MASK (0x10U) +#define USBPHY_CTRL_TOG_ENDEVPLUGINDET_SHIFT (4U) +/*! ENDEVPLUGINDET + * 0b0..Disables 200kohm pullup resistors on USB_DP and USB_DM pins (Default) + * 0b1..Enables 200kohm pullup resistors on USB_DP and USB_DM pins + */ +#define USBPHY_CTRL_TOG_ENDEVPLUGINDET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENDEVPLUGINDET_SHIFT)) & USBPHY_CTRL_TOG_ENDEVPLUGINDET_MASK) + +#define USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_MASK (0x20U) +#define USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_SHIFT (5U) +#define USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_MASK) + +#define USBPHY_CTRL_TOG_RESUMEIRQSTICKY_MASK (0x100U) +#define USBPHY_CTRL_TOG_RESUMEIRQSTICKY_SHIFT (8U) +#define USBPHY_CTRL_TOG_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_TOG_RESUMEIRQSTICKY_MASK) + +#define USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_MASK (0x200U) +#define USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_SHIFT (9U) +#define USBPHY_CTRL_TOG_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_MASK) + +#define USBPHY_CTRL_TOG_RESUME_IRQ_MASK (0x400U) +#define USBPHY_CTRL_TOG_RESUME_IRQ_SHIFT (10U) +#define USBPHY_CTRL_TOG_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_TOG_RESUME_IRQ_MASK) + +#define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_MASK (0x1000U) +#define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_SHIFT (12U) +#define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_MASK) + +#define USBPHY_CTRL_TOG_ENUTMILEVEL2_MASK (0x4000U) +#define USBPHY_CTRL_TOG_ENUTMILEVEL2_SHIFT (14U) +#define USBPHY_CTRL_TOG_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_TOG_ENUTMILEVEL2_MASK) + +#define USBPHY_CTRL_TOG_ENUTMILEVEL3_MASK (0x8000U) +#define USBPHY_CTRL_TOG_ENUTMILEVEL3_SHIFT (15U) +#define USBPHY_CTRL_TOG_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_TOG_ENUTMILEVEL3_MASK) + +#define USBPHY_CTRL_TOG_ENIRQWAKEUP_MASK (0x10000U) +#define USBPHY_CTRL_TOG_ENIRQWAKEUP_SHIFT (16U) +#define USBPHY_CTRL_TOG_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_TOG_ENIRQWAKEUP_MASK) + +#define USBPHY_CTRL_TOG_WAKEUP_IRQ_MASK (0x20000U) +#define USBPHY_CTRL_TOG_WAKEUP_IRQ_SHIFT (17U) +#define USBPHY_CTRL_TOG_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_TOG_WAKEUP_IRQ_MASK) + +#define USBPHY_CTRL_TOG_AUTORESUME_EN_MASK (0x40000U) +#define USBPHY_CTRL_TOG_AUTORESUME_EN_SHIFT (18U) +#define USBPHY_CTRL_TOG_AUTORESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_TOG_AUTORESUME_EN_MASK) + +#define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_MASK (0x80000U) +#define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_SHIFT (19U) +#define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_MASK) + +#define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_MASK (0x100000U) +#define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_SHIFT (20U) +#define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_MASK) + +#define USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_MASK (0x200000U) +#define USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_SHIFT (21U) +#define USBPHY_CTRL_TOG_ENDPDMCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_MASK) + +#define USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_MASK (0x800000U) +#define USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_SHIFT (23U) +#define USBPHY_CTRL_TOG_ENVBUSCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_MASK) + +#define USBPHY_CTRL_TOG_ENAUTOCLR_USBCLKGATE_MASK (0x2000000U) +#define USBPHY_CTRL_TOG_ENAUTOCLR_USBCLKGATE_SHIFT (25U) +#define USBPHY_CTRL_TOG_ENAUTOCLR_USBCLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOCLR_USBCLKGATE_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOCLR_USBCLKGATE_MASK) + +#define USBPHY_CTRL_TOG_ENAUTOSET_USBCLKS_MASK (0x4000000U) +#define USBPHY_CTRL_TOG_ENAUTOSET_USBCLKS_SHIFT (26U) +#define USBPHY_CTRL_TOG_ENAUTOSET_USBCLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOSET_USBCLKS_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOSET_USBCLKS_MASK) + +#define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_MASK (0x10000000U) +#define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_SHIFT (28U) +#define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_MASK) + +#define USBPHY_CTRL_TOG_UTMI_SUSPENDM_MASK (0x20000000U) +#define USBPHY_CTRL_TOG_UTMI_SUSPENDM_SHIFT (29U) +#define USBPHY_CTRL_TOG_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_TOG_UTMI_SUSPENDM_MASK) + +#define USBPHY_CTRL_TOG_CLKGATE_MASK (0x40000000U) +#define USBPHY_CTRL_TOG_CLKGATE_SHIFT (30U) +#define USBPHY_CTRL_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_CLKGATE_SHIFT)) & USBPHY_CTRL_TOG_CLKGATE_MASK) + +#define USBPHY_CTRL_TOG_SFTRST_MASK (0x80000000U) +#define USBPHY_CTRL_TOG_SFTRST_SHIFT (31U) +#define USBPHY_CTRL_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_SFTRST_SHIFT)) & USBPHY_CTRL_TOG_SFTRST_MASK) +/*! @} */ + +/*! @name STATUS - USB PHY Status Register */ +/*! @{ */ + +#define USBPHY_STATUS_OK_STATUS_3V_MASK (0x1U) +#define USBPHY_STATUS_OK_STATUS_3V_SHIFT (0U) +#define USBPHY_STATUS_OK_STATUS_3V(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_OK_STATUS_3V_SHIFT)) & USBPHY_STATUS_OK_STATUS_3V_MASK) + +#define USBPHY_STATUS_HOSTDISCONDETECT_STATUS_MASK (0x8U) +#define USBPHY_STATUS_HOSTDISCONDETECT_STATUS_SHIFT (3U) +/*! HOSTDISCONDETECT_STATUS + * 0b0..USB cable disconnect has not been detected at the local host + * 0b1..USB cable disconnect has been detected at the local host + */ +#define USBPHY_STATUS_HOSTDISCONDETECT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_HOSTDISCONDETECT_STATUS_SHIFT)) & USBPHY_STATUS_HOSTDISCONDETECT_STATUS_MASK) + +#define USBPHY_STATUS_DEVPLUGIN_STATUS_MASK (0x40U) +#define USBPHY_STATUS_DEVPLUGIN_STATUS_SHIFT (6U) +/*! DEVPLUGIN_STATUS + * 0b0..No attachment to a USB host is detected + * 0b1..Cable attachment to a USB host is detected + */ +#define USBPHY_STATUS_DEVPLUGIN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_DEVPLUGIN_STATUS_SHIFT)) & USBPHY_STATUS_DEVPLUGIN_STATUS_MASK) + +#define USBPHY_STATUS_RESUME_STATUS_MASK (0x400U) +#define USBPHY_STATUS_RESUME_STATUS_SHIFT (10U) +#define USBPHY_STATUS_RESUME_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RESUME_STATUS_SHIFT)) & USBPHY_STATUS_RESUME_STATUS_MASK) +/*! @} */ + +/*! @name PLL_SIC - USB PHY PLL Control/Status Register */ +/*! @{ */ + +#define USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK (0x40U) +#define USBPHY_PLL_SIC_PLL_EN_USB_CLKS_SHIFT (6U) +#define USBPHY_PLL_SIC_PLL_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK) + +#define USBPHY_PLL_SIC_PLL_POWER_MASK (0x1000U) +#define USBPHY_PLL_SIC_PLL_POWER_SHIFT (12U) +#define USBPHY_PLL_SIC_PLL_POWER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_PLL_POWER_MASK) + +#define USBPHY_PLL_SIC_PLL_ENABLE_MASK (0x2000U) +#define USBPHY_PLL_SIC_PLL_ENABLE_SHIFT (13U) +#define USBPHY_PLL_SIC_PLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_PLL_ENABLE_MASK) + +#define USBPHY_PLL_SIC_REFBIAS_PWD_SEL_MASK (0x80000U) +#define USBPHY_PLL_SIC_REFBIAS_PWD_SEL_SHIFT (19U) +/*! REFBIAS_PWD_SEL + * 0b0..Selects PLL_POWER to control the reference bias + * 0b1..Selects REFBIAS_PWD to control the reference bias + */ +#define USBPHY_PLL_SIC_REFBIAS_PWD_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_REFBIAS_PWD_SEL_SHIFT)) & USBPHY_PLL_SIC_REFBIAS_PWD_SEL_MASK) + +#define USBPHY_PLL_SIC_REFBIAS_PWD_MASK (0x100000U) +#define USBPHY_PLL_SIC_REFBIAS_PWD_SHIFT (20U) +#define USBPHY_PLL_SIC_REFBIAS_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_REFBIAS_PWD_SHIFT)) & USBPHY_PLL_SIC_REFBIAS_PWD_MASK) + +#define USBPHY_PLL_SIC_PLL_REG_ENABLE_MASK (0x200000U) +#define USBPHY_PLL_SIC_PLL_REG_ENABLE_SHIFT (21U) +#define USBPHY_PLL_SIC_PLL_REG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_REG_ENABLE_SHIFT)) & USBPHY_PLL_SIC_PLL_REG_ENABLE_MASK) + +#define USBPHY_PLL_SIC_PLL_DIV_SEL_MASK (0x1C00000U) +#define USBPHY_PLL_SIC_PLL_DIV_SEL_SHIFT (22U) +/*! PLL_DIV_SEL + * 0b000..Divide by 13 + * 0b001..Divide by 15 + * 0b010..Divide by 16 + * 0b011..Divide by 20 + * 0b100..Divide by 22 + * 0b101..Divide by 25 + * 0b110..Divide by 30 + * 0b111..Divide by 240 + */ +#define USBPHY_PLL_SIC_PLL_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_PLL_DIV_SEL_MASK) + +#define USBPHY_PLL_SIC_PLL_PREDIV_MASK (0x40000000U) +#define USBPHY_PLL_SIC_PLL_PREDIV_SHIFT (30U) +#define USBPHY_PLL_SIC_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_PREDIV_SHIFT)) & USBPHY_PLL_SIC_PLL_PREDIV_MASK) + +#define USBPHY_PLL_SIC_PLL_LOCK_MASK (0x80000000U) +#define USBPHY_PLL_SIC_PLL_LOCK_SHIFT (31U) +/*! PLL_LOCK + * 0b0..PLL is not currently locked + * 0b1..PLL is currently locked + */ +#define USBPHY_PLL_SIC_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_PLL_LOCK_MASK) +/*! @} */ + +/*! @name PLL_SIC_SET - USB PHY PLL Control/Status Register */ +/*! @{ */ + +#define USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_MASK (0x40U) +#define USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_SHIFT (6U) +#define USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_MASK) + +#define USBPHY_PLL_SIC_SET_PLL_POWER_MASK (0x1000U) +#define USBPHY_PLL_SIC_SET_PLL_POWER_SHIFT (12U) +#define USBPHY_PLL_SIC_SET_PLL_POWER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_POWER_MASK) + +#define USBPHY_PLL_SIC_SET_PLL_ENABLE_MASK (0x2000U) +#define USBPHY_PLL_SIC_SET_PLL_ENABLE_SHIFT (13U) +#define USBPHY_PLL_SIC_SET_PLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_ENABLE_MASK) + +#define USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL_MASK (0x80000U) +#define USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL_SHIFT (19U) +/*! REFBIAS_PWD_SEL + * 0b0..Selects PLL_POWER to control the reference bias + * 0b1..Selects REFBIAS_PWD to control the reference bias + */ +#define USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL_SHIFT)) & USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL_MASK) + +#define USBPHY_PLL_SIC_SET_REFBIAS_PWD_MASK (0x100000U) +#define USBPHY_PLL_SIC_SET_REFBIAS_PWD_SHIFT (20U) +#define USBPHY_PLL_SIC_SET_REFBIAS_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_REFBIAS_PWD_SHIFT)) & USBPHY_PLL_SIC_SET_REFBIAS_PWD_MASK) + +#define USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_MASK (0x200000U) +#define USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_SHIFT (21U) +#define USBPHY_PLL_SIC_SET_PLL_REG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_MASK) + +#define USBPHY_PLL_SIC_SET_PLL_DIV_SEL_MASK (0x1C00000U) +#define USBPHY_PLL_SIC_SET_PLL_DIV_SEL_SHIFT (22U) +/*! PLL_DIV_SEL + * 0b000..Divide by 13 + * 0b001..Divide by 15 + * 0b010..Divide by 16 + * 0b011..Divide by 20 + * 0b100..Divide by 22 + * 0b101..Divide by 25 + * 0b110..Divide by 30 + * 0b111..Divide by 240 + */ +#define USBPHY_PLL_SIC_SET_PLL_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_DIV_SEL_MASK) + +#define USBPHY_PLL_SIC_SET_PLL_PREDIV_MASK (0x40000000U) +#define USBPHY_PLL_SIC_SET_PLL_PREDIV_SHIFT (30U) +#define USBPHY_PLL_SIC_SET_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_PREDIV_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_PREDIV_MASK) + +#define USBPHY_PLL_SIC_SET_PLL_LOCK_MASK (0x80000000U) +#define USBPHY_PLL_SIC_SET_PLL_LOCK_SHIFT (31U) +/*! PLL_LOCK + * 0b0..PLL is not currently locked + * 0b1..PLL is currently locked + */ +#define USBPHY_PLL_SIC_SET_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_LOCK_MASK) +/*! @} */ + +/*! @name PLL_SIC_CLR - USB PHY PLL Control/Status Register */ +/*! @{ */ + +#define USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_MASK (0x40U) +#define USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_SHIFT (6U) +#define USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_MASK) + +#define USBPHY_PLL_SIC_CLR_PLL_POWER_MASK (0x1000U) +#define USBPHY_PLL_SIC_CLR_PLL_POWER_SHIFT (12U) +#define USBPHY_PLL_SIC_CLR_PLL_POWER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_POWER_MASK) + +#define USBPHY_PLL_SIC_CLR_PLL_ENABLE_MASK (0x2000U) +#define USBPHY_PLL_SIC_CLR_PLL_ENABLE_SHIFT (13U) +#define USBPHY_PLL_SIC_CLR_PLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_ENABLE_MASK) + +#define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL_MASK (0x80000U) +#define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL_SHIFT (19U) +/*! REFBIAS_PWD_SEL + * 0b0..Selects PLL_POWER to control the reference bias + * 0b1..Selects REFBIAS_PWD to control the reference bias + */ +#define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL_SHIFT)) & USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL_MASK) + +#define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_MASK (0x100000U) +#define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SHIFT (20U) +#define USBPHY_PLL_SIC_CLR_REFBIAS_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SHIFT)) & USBPHY_PLL_SIC_CLR_REFBIAS_PWD_MASK) + +#define USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_MASK (0x200000U) +#define USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_SHIFT (21U) +#define USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_MASK) + +#define USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_MASK (0x1C00000U) +#define USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_SHIFT (22U) +/*! PLL_DIV_SEL + * 0b000..Divide by 13 + * 0b001..Divide by 15 + * 0b010..Divide by 16 + * 0b011..Divide by 20 + * 0b100..Divide by 22 + * 0b101..Divide by 25 + * 0b110..Divide by 30 + * 0b111..Divide by 240 + */ +#define USBPHY_PLL_SIC_CLR_PLL_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_MASK) + +#define USBPHY_PLL_SIC_CLR_PLL_PREDIV_MASK (0x40000000U) +#define USBPHY_PLL_SIC_CLR_PLL_PREDIV_SHIFT (30U) +#define USBPHY_PLL_SIC_CLR_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_PREDIV_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_PREDIV_MASK) + +#define USBPHY_PLL_SIC_CLR_PLL_LOCK_MASK (0x80000000U) +#define USBPHY_PLL_SIC_CLR_PLL_LOCK_SHIFT (31U) +/*! PLL_LOCK + * 0b0..PLL is not currently locked + * 0b1..PLL is currently locked + */ +#define USBPHY_PLL_SIC_CLR_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_LOCK_MASK) +/*! @} */ + +/*! @name PLL_SIC_TOG - USB PHY PLL Control/Status Register */ +/*! @{ */ + +#define USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_MASK (0x40U) +#define USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_SHIFT (6U) +#define USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_MASK) + +#define USBPHY_PLL_SIC_TOG_PLL_POWER_MASK (0x1000U) +#define USBPHY_PLL_SIC_TOG_PLL_POWER_SHIFT (12U) +#define USBPHY_PLL_SIC_TOG_PLL_POWER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_POWER_MASK) + +#define USBPHY_PLL_SIC_TOG_PLL_ENABLE_MASK (0x2000U) +#define USBPHY_PLL_SIC_TOG_PLL_ENABLE_SHIFT (13U) +#define USBPHY_PLL_SIC_TOG_PLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_ENABLE_MASK) + +#define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL_MASK (0x80000U) +#define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL_SHIFT (19U) +/*! REFBIAS_PWD_SEL + * 0b0..Selects PLL_POWER to control the reference bias + * 0b1..Selects REFBIAS_PWD to control the reference bias + */ +#define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL_SHIFT)) & USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL_MASK) + +#define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_MASK (0x100000U) +#define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SHIFT (20U) +#define USBPHY_PLL_SIC_TOG_REFBIAS_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SHIFT)) & USBPHY_PLL_SIC_TOG_REFBIAS_PWD_MASK) + +#define USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_MASK (0x200000U) +#define USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_SHIFT (21U) +#define USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_MASK) + +#define USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_MASK (0x1C00000U) +#define USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_SHIFT (22U) +/*! PLL_DIV_SEL + * 0b000..Divide by 13 + * 0b001..Divide by 15 + * 0b010..Divide by 16 + * 0b011..Divide by 20 + * 0b100..Divide by 22 + * 0b101..Divide by 25 + * 0b110..Divide by 30 + * 0b111..Divide by 240 + */ +#define USBPHY_PLL_SIC_TOG_PLL_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_MASK) + +#define USBPHY_PLL_SIC_TOG_PLL_PREDIV_MASK (0x40000000U) +#define USBPHY_PLL_SIC_TOG_PLL_PREDIV_SHIFT (30U) +#define USBPHY_PLL_SIC_TOG_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_PREDIV_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_PREDIV_MASK) + +#define USBPHY_PLL_SIC_TOG_PLL_LOCK_MASK (0x80000000U) +#define USBPHY_PLL_SIC_TOG_PLL_LOCK_SHIFT (31U) +/*! PLL_LOCK + * 0b0..PLL is not currently locked + * 0b1..PLL is currently locked + */ +#define USBPHY_PLL_SIC_TOG_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_LOCK_MASK) +/*! @} */ + +/*! @name USB1_VBUS_DETECT - USB PHY VBUS Detect Control Register */ +/*! @{ */ + +#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_MASK (0x7U) +#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_SHIFT (0U) +/*! VBUSVALID_THRESH + * 0b000..4.0V + * 0b001..4.1V + * 0b010..4.2V + * 0b011..4.3V + * 0b100..4.4V(Default) + * 0b101..4.5V + * 0b110..4.6V + * 0b111..4.7V + */ +#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_MASK) + +#define USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_MASK (0x8U) +#define USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_SHIFT (3U) +/*! VBUS_OVERRIDE_EN + * 0b0..Use the results of the internal VBUS_VALID and Session Valid comparators for VBUS_VALID, AVALID, BVALID, and SESSEND (Default) + * 0b1..Use the override values for VBUS_VALID, AVALID, BVALID, and SESSEND + */ +#define USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_MASK) + +#define USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_MASK (0x10U) +#define USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_SHIFT (4U) +#define USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_MASK) + +#define USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_MASK (0x20U) +#define USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_SHIFT (5U) +#define USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_MASK) + +#define USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_MASK (0x40U) +#define USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_SHIFT (6U) +#define USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_MASK) + +#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_MASK (0x80U) +#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_SHIFT (7U) +#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_MASK) + +#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_MASK (0x100U) +#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_SHIFT (8U) +/*! VBUSVALID_SEL + * 0b0..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) + * 0b1..Use the VBUS_VALID_3V detector results for signal reported to the USB controller + */ +#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_MASK) + +#define USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_MASK (0x600U) +#define USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_SHIFT (9U) +/*! VBUS_SOURCE_SEL + * 0b00..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) + * 0b01..Use the Session Valid comparator results for signal reported to the USB controller + * 0b10..Use the Session Valid comparator results for signal reported to the USB controller + * 0b11..Reserved, do not use + */ +#define USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_MASK) + +#define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_EN_MASK (0x800U) +#define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_EN_SHIFT (11U) +#define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_EN_MASK) + +#define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_MASK (0x1000U) +#define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_SHIFT (12U) +#define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_MASK) + +#define USBPHY_USB1_VBUS_DETECT_EXT_ID_OVERRIDE_EN_MASK (0x2000U) +#define USBPHY_USB1_VBUS_DETECT_EXT_ID_OVERRIDE_EN_SHIFT (13U) +/*! EXT_ID_OVERRIDE_EN + * 0b0..Select the Muxed value chosen using ID_OVERRIDE_EN. + * 0b1..Select the external ID value. + */ +#define USBPHY_USB1_VBUS_DETECT_EXT_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_EXT_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_EXT_ID_OVERRIDE_EN_MASK) + +#define USBPHY_USB1_VBUS_DETECT_EXT_VBUS_OVERRIDE_EN_MASK (0x4000U) +#define USBPHY_USB1_VBUS_DETECT_EXT_VBUS_OVERRIDE_EN_SHIFT (14U) +/*! EXT_VBUS_OVERRIDE_EN + * 0b0..Select the Muxed value chosen using VBUS_OVERRIDE_EN. + * 0b1..Select the external VBUS VALID value. + */ +#define USBPHY_USB1_VBUS_DETECT_EXT_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_EXT_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_EXT_VBUS_OVERRIDE_EN_MASK) + +#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID_MASK (0x40000U) +#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID_SHIFT (18U) +/*! VBUSVALID_TO_SESSVALID + * 0b0..Use the VBUS_VALID comparator for VBUS_VALID results + * 0b1..Use the Session End comparator for VBUS_VALID results. The Session End threshold is >0.8V and <4.0V. + */ +#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID_MASK) + +#define USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_MASK (0x700000U) +#define USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_SHIFT (20U) +/*! PWRUP_CMPS + * 0b000..Powers down the VBUS_VALID comparator + * 0b111..Enables the VBUS_VALID comparator (default) + */ +#define USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_MASK) + +#define USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_MASK (0x4000000U) +#define USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_SHIFT (26U) +/*! DISCHARGE_VBUS + * 0b0..VBUS discharge resistor is disabled (Default) + * 0b1..VBUS discharge resistor is enabled + */ +#define USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_MASK) +/*! @} */ + +/*! @name USB1_VBUS_DETECT_SET - USB PHY VBUS Detect Control Register */ +/*! @{ */ + +#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK (0x7U) +#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT (0U) +/*! VBUSVALID_THRESH + * 0b000..4.0V + * 0b001..4.1V + * 0b010..4.2V + * 0b011..4.3V + * 0b100..4.4V(Default) + * 0b101..4.5V + * 0b110..4.6V + * 0b111..4.7V + */ +#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK) + +#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_MASK (0x8U) +#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_SHIFT (3U) +/*! VBUS_OVERRIDE_EN + * 0b0..Use the results of the internal VBUS_VALID and Session Valid comparators for VBUS_VALID, AVALID, BVALID, and SESSEND (Default) + * 0b1..Use the override values for VBUS_VALID, AVALID, BVALID, and SESSEND + */ +#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_MASK) + +#define USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_MASK (0x10U) +#define USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_SHIFT (4U) +#define USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_MASK) + +#define USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_MASK (0x20U) +#define USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_SHIFT (5U) +#define USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_MASK) + +#define USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_MASK (0x40U) +#define USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_SHIFT (6U) +#define USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_MASK) + +#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_MASK (0x80U) +#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_SHIFT (7U) +#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_MASK) + +#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_MASK (0x100U) +#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_SHIFT (8U) +/*! VBUSVALID_SEL + * 0b0..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) + * 0b1..Use the VBUS_VALID_3V detector results for signal reported to the USB controller + */ +#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_MASK) + +#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_MASK (0x600U) +#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_SHIFT (9U) +/*! VBUS_SOURCE_SEL + * 0b00..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) + * 0b01..Use the Session Valid comparator results for signal reported to the USB controller + * 0b10..Use the Session Valid comparator results for signal reported to the USB controller + * 0b11..Reserved, do not use + */ +#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_MASK) + +#define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_EN_MASK (0x800U) +#define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_EN_SHIFT (11U) +#define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_EN_MASK) + +#define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_MASK (0x1000U) +#define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_SHIFT (12U) +#define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_MASK) + +#define USBPHY_USB1_VBUS_DETECT_SET_EXT_ID_OVERRIDE_EN_MASK (0x2000U) +#define USBPHY_USB1_VBUS_DETECT_SET_EXT_ID_OVERRIDE_EN_SHIFT (13U) +/*! EXT_ID_OVERRIDE_EN + * 0b0..Select the Muxed value chosen using ID_OVERRIDE_EN. + * 0b1..Select the external ID value. + */ +#define USBPHY_USB1_VBUS_DETECT_SET_EXT_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_EXT_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_EXT_ID_OVERRIDE_EN_MASK) + +#define USBPHY_USB1_VBUS_DETECT_SET_EXT_VBUS_OVERRIDE_EN_MASK (0x4000U) +#define USBPHY_USB1_VBUS_DETECT_SET_EXT_VBUS_OVERRIDE_EN_SHIFT (14U) +/*! EXT_VBUS_OVERRIDE_EN + * 0b0..Select the Muxed value chosen using VBUS_OVERRIDE_EN. + * 0b1..Select the external VBUS VALID value. + */ +#define USBPHY_USB1_VBUS_DETECT_SET_EXT_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_EXT_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_EXT_VBUS_OVERRIDE_EN_MASK) + +#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID_MASK (0x40000U) +#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID_SHIFT (18U) +/*! VBUSVALID_TO_SESSVALID + * 0b0..Use the VBUS_VALID comparator for VBUS_VALID results + * 0b1..Use the Session End comparator for VBUS_VALID results. The Session End threshold is >0.8V and <4.0V. + */ +#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID_MASK) + +#define USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS_MASK (0x700000U) +#define USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS_SHIFT (20U) +/*! PWRUP_CMPS + * 0b000..Powers down the VBUS_VALID comparator + * 0b111..Enables the VBUS_VALID comparator (default) + */ +#define USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS_MASK) + +#define USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_MASK (0x4000000U) +#define USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_SHIFT (26U) +/*! DISCHARGE_VBUS + * 0b0..VBUS discharge resistor is disabled (Default) + * 0b1..VBUS discharge resistor is enabled + */ +#define USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_MASK) +/*! @} */ + +/*! @name USB1_VBUS_DETECT_CLR - USB PHY VBUS Detect Control Register */ +/*! @{ */ + +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK (0x7U) +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT (0U) +/*! VBUSVALID_THRESH + * 0b000..4.0V + * 0b001..4.1V + * 0b010..4.2V + * 0b011..4.3V + * 0b100..4.4V(Default) + * 0b101..4.5V + * 0b110..4.6V + * 0b111..4.7V + */ +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK) + +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_MASK (0x8U) +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_SHIFT (3U) +/*! VBUS_OVERRIDE_EN + * 0b0..Use the results of the internal VBUS_VALID and Session Valid comparators for VBUS_VALID, AVALID, BVALID, and SESSEND (Default) + * 0b1..Use the override values for VBUS_VALID, AVALID, BVALID, and SESSEND + */ +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_MASK) + +#define USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_MASK (0x10U) +#define USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_SHIFT (4U) +#define USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_MASK) + +#define USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_MASK (0x20U) +#define USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_SHIFT (5U) +#define USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_MASK) + +#define USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_MASK (0x40U) +#define USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_SHIFT (6U) +#define USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_MASK) + +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_MASK (0x80U) +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_SHIFT (7U) +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_MASK) + +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_MASK (0x100U) +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_SHIFT (8U) +/*! VBUSVALID_SEL + * 0b0..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) + * 0b1..Use the VBUS_VALID_3V detector results for signal reported to the USB controller + */ +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_MASK) + +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_MASK (0x600U) +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_SHIFT (9U) +/*! VBUS_SOURCE_SEL + * 0b00..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) + * 0b01..Use the Session Valid comparator results for signal reported to the USB controller + * 0b10..Use the Session Valid comparator results for signal reported to the USB controller + * 0b11..Reserved, do not use + */ +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_MASK) + +#define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_EN_MASK (0x800U) +#define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_EN_SHIFT (11U) +#define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_EN_MASK) + +#define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_MASK (0x1000U) +#define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_SHIFT (12U) +#define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_MASK) + +#define USBPHY_USB1_VBUS_DETECT_CLR_EXT_ID_OVERRIDE_EN_MASK (0x2000U) +#define USBPHY_USB1_VBUS_DETECT_CLR_EXT_ID_OVERRIDE_EN_SHIFT (13U) +/*! EXT_ID_OVERRIDE_EN + * 0b0..Select the Muxed value chosen using ID_OVERRIDE_EN. + * 0b1..Select the external ID value. + */ +#define USBPHY_USB1_VBUS_DETECT_CLR_EXT_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_EXT_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_EXT_ID_OVERRIDE_EN_MASK) + +#define USBPHY_USB1_VBUS_DETECT_CLR_EXT_VBUS_OVERRIDE_EN_MASK (0x4000U) +#define USBPHY_USB1_VBUS_DETECT_CLR_EXT_VBUS_OVERRIDE_EN_SHIFT (14U) +/*! EXT_VBUS_OVERRIDE_EN + * 0b0..Select the muxed value chosen using VBUS_OVERRIDE_EN. + * 0b1..Select the external VBUS VALID value. + */ +#define USBPHY_USB1_VBUS_DETECT_CLR_EXT_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_EXT_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_EXT_VBUS_OVERRIDE_EN_MASK) + +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID_MASK (0x40000U) +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID_SHIFT (18U) +/*! VBUSVALID_TO_SESSVALID + * 0b0..Use the VBUS_VALID comparator for VBUS_VALID results + * 0b1..Use the Session End comparator for VBUS_VALID results. The Session End threshold is >0.8V and <4.0V. + */ +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID_MASK) + +#define USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS_MASK (0x700000U) +#define USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS_SHIFT (20U) +/*! PWRUP_CMPS + * 0b000..Powers down the VBUS_VALID comparator + * 0b111..Enables the VBUS_VALID comparator (default) + */ +#define USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS_MASK) + +#define USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_MASK (0x4000000U) +#define USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_SHIFT (26U) +/*! DISCHARGE_VBUS + * 0b0..VBUS discharge resistor is disabled (Default) + * 0b1..VBUS discharge resistor is enabled + */ +#define USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_MASK) +/*! @} */ + +/*! @name USB1_VBUS_DETECT_TOG - USB PHY VBUS Detect Control Register */ +/*! @{ */ + +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK (0x7U) +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT (0U) +/*! VBUSVALID_THRESH + * 0b000..4.0V + * 0b001..4.1V + * 0b010..4.2V + * 0b011..4.3V + * 0b100..4.4V(Default) + * 0b101..4.5V + * 0b110..4.6V + * 0b111..4.7V + */ +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK) + +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_MASK (0x8U) +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_SHIFT (3U) +/*! VBUS_OVERRIDE_EN + * 0b0..Use the results of the internal VBUS_VALID and Session Valid comparators for VBUS_VALID, AVALID, BVALID, and SESSEND (Default) + * 0b1..Use the override values for VBUS_VALID, AVALID, BVALID, and SESSEND + */ +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_MASK) + +#define USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_MASK (0x10U) +#define USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_SHIFT (4U) +#define USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_MASK) + +#define USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_MASK (0x20U) +#define USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_SHIFT (5U) +#define USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_MASK) + +#define USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_MASK (0x40U) +#define USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_SHIFT (6U) +#define USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_MASK) + +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_MASK (0x80U) +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_SHIFT (7U) +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_MASK) + +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_MASK (0x100U) +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_SHIFT (8U) +/*! VBUSVALID_SEL + * 0b0..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) + * 0b1..Use the VBUS_VALID_3V detector results for signal reported to the USB controller + */ +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_MASK) + +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_MASK (0x600U) +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_SHIFT (9U) +/*! VBUS_SOURCE_SEL + * 0b00..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) + * 0b01..Use the Session Valid comparator results for signal reported to the USB controller + * 0b10..Use the Session Valid comparator results for signal reported to the USB controller + * 0b11..Reserved, do not use + */ +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_MASK) + +#define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_EN_MASK (0x800U) +#define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_EN_SHIFT (11U) +#define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_EN_MASK) + +#define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_MASK (0x1000U) +#define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_SHIFT (12U) +#define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_MASK) + +#define USBPHY_USB1_VBUS_DETECT_TOG_EXT_ID_OVERRIDE_EN_MASK (0x2000U) +#define USBPHY_USB1_VBUS_DETECT_TOG_EXT_ID_OVERRIDE_EN_SHIFT (13U) +/*! EXT_ID_OVERRIDE_EN + * 0b0..Select the muxed value chosen using ID_OVERRIDE_EN. + * 0b1..Select the external ID value. + */ +#define USBPHY_USB1_VBUS_DETECT_TOG_EXT_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_EXT_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_EXT_ID_OVERRIDE_EN_MASK) + +#define USBPHY_USB1_VBUS_DETECT_TOG_EXT_VBUS_OVERRIDE_EN_MASK (0x4000U) +#define USBPHY_USB1_VBUS_DETECT_TOG_EXT_VBUS_OVERRIDE_EN_SHIFT (14U) +/*! EXT_VBUS_OVERRIDE_EN + * 0b0..Select the Muxed value chosen using VBUS_OVERRIDE_EN. + * 0b1..Select the external VBUS VALID value. + */ +#define USBPHY_USB1_VBUS_DETECT_TOG_EXT_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_EXT_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_EXT_VBUS_OVERRIDE_EN_MASK) + +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID_MASK (0x40000U) +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID_SHIFT (18U) +/*! VBUSVALID_TO_SESSVALID + * 0b0..Use the VBUS_VALID comparator for VBUS_VALID results + * 0b1..Use the Session End comparator for VBUS_VALID results. The Session End threshold is >0.8V and <4.0V. + */ +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID_MASK) + +#define USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS_MASK (0x700000U) +#define USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS_SHIFT (20U) +/*! PWRUP_CMPS + * 0b000..Powers down the VBUS_VALID comparator + * 0b111..Enables the VBUS_VALID comparator (default) + */ +#define USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS_MASK) + +#define USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_MASK (0x4000000U) +#define USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_SHIFT (26U) +/*! DISCHARGE_VBUS + * 0b0..VBUS discharge resistor is disabled (Default) + * 0b1..VBUS discharge resistor is enabled + */ +#define USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_MASK) +/*! @} */ + +/*! @name USB1_VBUS_DET_STAT - USB PHY VBUS Detector Status Register */ +/*! @{ */ + +#define USBPHY_USB1_VBUS_DET_STAT_SESSEND_MASK (0x1U) +#define USBPHY_USB1_VBUS_DET_STAT_SESSEND_SHIFT (0U) +/*! SESSEND + * 0b0..The VBUS voltage is above the Session Valid threshold + * 0b1..The VBUS voltage is below the Session Valid threshold + */ +#define USBPHY_USB1_VBUS_DET_STAT_SESSEND(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_SESSEND_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_SESSEND_MASK) + +#define USBPHY_USB1_VBUS_DET_STAT_BVALID_MASK (0x2U) +#define USBPHY_USB1_VBUS_DET_STAT_BVALID_SHIFT (1U) +/*! BVALID + * 0b0..The VBUS voltage is below the Session Valid threshold + * 0b1..The VBUS voltage is above the Session Valid threshold + */ +#define USBPHY_USB1_VBUS_DET_STAT_BVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_BVALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_BVALID_MASK) + +#define USBPHY_USB1_VBUS_DET_STAT_AVALID_MASK (0x4U) +#define USBPHY_USB1_VBUS_DET_STAT_AVALID_SHIFT (2U) +/*! AVALID + * 0b0..The VBUS voltage is below the Session Valid threshold + * 0b1..The VBUS voltage is above the Session Valid threshold + */ +#define USBPHY_USB1_VBUS_DET_STAT_AVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_AVALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_AVALID_MASK) + +#define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_MASK (0x8U) +#define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_SHIFT (3U) +/*! VBUS_VALID + * 0b0..VBUS is below the comparator threshold + * 0b1..VBUS is above the comparator threshold + */ +#define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_MASK) + +#define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V_MASK (0x10U) +#define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V_SHIFT (4U) +/*! VBUS_VALID_3V + * 0b0..VBUS voltage is below VBUS_VALID_3V threshold + * 0b1..VBUS voltage is above VBUS_VALID_3V threshold + */ +#define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V_MASK) +/*! @} */ + +/*! @name ANACTRL - USB PHY Analog Control Register */ +/*! @{ */ + +#define USBPHY_ANACTRL_LVI_EN_MASK (0x2U) +#define USBPHY_ANACTRL_LVI_EN_SHIFT (1U) +#define USBPHY_ANACTRL_LVI_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_LVI_EN_SHIFT)) & USBPHY_ANACTRL_LVI_EN_MASK) + +#define USBPHY_ANACTRL_PFD_CLK_SEL_MASK (0xCU) +#define USBPHY_ANACTRL_PFD_CLK_SEL_SHIFT (2U) +#define USBPHY_ANACTRL_PFD_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_PFD_CLK_SEL_SHIFT)) & USBPHY_ANACTRL_PFD_CLK_SEL_MASK) + +#define USBPHY_ANACTRL_DEV_PULLDOWN_MASK (0x400U) +#define USBPHY_ANACTRL_DEV_PULLDOWN_SHIFT (10U) +/*! DEV_PULLDOWN + * 0b0..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare disabled in device mode. + * 0b1..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare enabled in device mode. + */ +#define USBPHY_ANACTRL_DEV_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_DEV_PULLDOWN_MASK) +/*! @} */ + +/*! @name ANACTRL_SET - USB PHY Analog Control Register */ +/*! @{ */ + +#define USBPHY_ANACTRL_SET_LVI_EN_MASK (0x2U) +#define USBPHY_ANACTRL_SET_LVI_EN_SHIFT (1U) +#define USBPHY_ANACTRL_SET_LVI_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_SET_LVI_EN_SHIFT)) & USBPHY_ANACTRL_SET_LVI_EN_MASK) + +#define USBPHY_ANACTRL_SET_PFD_CLK_SEL_MASK (0xCU) +#define USBPHY_ANACTRL_SET_PFD_CLK_SEL_SHIFT (2U) +#define USBPHY_ANACTRL_SET_PFD_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_SET_PFD_CLK_SEL_SHIFT)) & USBPHY_ANACTRL_SET_PFD_CLK_SEL_MASK) + +#define USBPHY_ANACTRL_SET_DEV_PULLDOWN_MASK (0x400U) +#define USBPHY_ANACTRL_SET_DEV_PULLDOWN_SHIFT (10U) +/*! DEV_PULLDOWN + * 0b0..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare disabled in device mode. + * 0b1..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare enabled in device mode. + */ +#define USBPHY_ANACTRL_SET_DEV_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_SET_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_SET_DEV_PULLDOWN_MASK) +/*! @} */ + +/*! @name ANACTRL_CLR - USB PHY Analog Control Register */ +/*! @{ */ + +#define USBPHY_ANACTRL_CLR_LVI_EN_MASK (0x2U) +#define USBPHY_ANACTRL_CLR_LVI_EN_SHIFT (1U) +#define USBPHY_ANACTRL_CLR_LVI_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_CLR_LVI_EN_SHIFT)) & USBPHY_ANACTRL_CLR_LVI_EN_MASK) + +#define USBPHY_ANACTRL_CLR_PFD_CLK_SEL_MASK (0xCU) +#define USBPHY_ANACTRL_CLR_PFD_CLK_SEL_SHIFT (2U) +#define USBPHY_ANACTRL_CLR_PFD_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_CLR_PFD_CLK_SEL_SHIFT)) & USBPHY_ANACTRL_CLR_PFD_CLK_SEL_MASK) + +#define USBPHY_ANACTRL_CLR_DEV_PULLDOWN_MASK (0x400U) +#define USBPHY_ANACTRL_CLR_DEV_PULLDOWN_SHIFT (10U) +/*! DEV_PULLDOWN + * 0b0..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare disabled in device mode. + * 0b1..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare enabled in device mode. + */ +#define USBPHY_ANACTRL_CLR_DEV_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_CLR_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_CLR_DEV_PULLDOWN_MASK) +/*! @} */ + +/*! @name ANACTRL_TOG - USB PHY Analog Control Register */ +/*! @{ */ + +#define USBPHY_ANACTRL_TOG_LVI_EN_MASK (0x2U) +#define USBPHY_ANACTRL_TOG_LVI_EN_SHIFT (1U) +#define USBPHY_ANACTRL_TOG_LVI_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TOG_LVI_EN_SHIFT)) & USBPHY_ANACTRL_TOG_LVI_EN_MASK) + +#define USBPHY_ANACTRL_TOG_PFD_CLK_SEL_MASK (0xCU) +#define USBPHY_ANACTRL_TOG_PFD_CLK_SEL_SHIFT (2U) +#define USBPHY_ANACTRL_TOG_PFD_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TOG_PFD_CLK_SEL_SHIFT)) & USBPHY_ANACTRL_TOG_PFD_CLK_SEL_MASK) + +#define USBPHY_ANACTRL_TOG_DEV_PULLDOWN_MASK (0x400U) +#define USBPHY_ANACTRL_TOG_DEV_PULLDOWN_SHIFT (10U) +/*! DEV_PULLDOWN + * 0b0..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare disabled in device mode. + * 0b1..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare enabled in device mode. + */ +#define USBPHY_ANACTRL_TOG_DEV_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TOG_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_TOG_DEV_PULLDOWN_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group USBPHY_Register_Masks */ + + +/* USBPHY - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral USBPHY base address */ + #define USBPHY_BASE (0x50038000u) + /** Peripheral USBPHY base address */ + #define USBPHY_BASE_NS (0x40038000u) + /** Peripheral USBPHY base pointer */ + #define USBPHY ((USBPHY_Type *)USBPHY_BASE) + /** Peripheral USBPHY base pointer */ + #define USBPHY_NS ((USBPHY_Type *)USBPHY_BASE_NS) + /** Array initializer of USBPHY peripheral base addresses */ + #define USBPHY_BASE_ADDRS { USBPHY_BASE } + /** Array initializer of USBPHY peripheral base pointers */ + #define USBPHY_BASE_PTRS { USBPHY } + /** Array initializer of USBPHY peripheral base addresses */ + #define USBPHY_BASE_ADDRS_NS { USBPHY_BASE_NS } + /** Array initializer of USBPHY peripheral base pointers */ + #define USBPHY_BASE_PTRS_NS { USBPHY_NS } +#else + /** Peripheral USBPHY base address */ + #define USBPHY_BASE (0x40038000u) + /** Peripheral USBPHY base pointer */ + #define USBPHY ((USBPHY_Type *)USBPHY_BASE) + /** Array initializer of USBPHY peripheral base addresses */ + #define USBPHY_BASE_ADDRS { USBPHY_BASE } + /** Array initializer of USBPHY peripheral base pointers */ + #define USBPHY_BASE_PTRS { USBPHY } +#endif +/** Interrupt vectors for the USBPHY peripheral type */ +#define USBPHY_IRQS { USB1_PHY_IRQn } + +/*! + * @} + */ /* end of group USBPHY_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- UTICK Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup UTICK_Peripheral_Access_Layer UTICK Peripheral Access Layer + * @{ + */ + +/** UTICK - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL; /**< Control register., offset: 0x0 */ + __IO uint32_t STAT; /**< Status register., offset: 0x4 */ + __IO uint32_t CFG; /**< Capture configuration register., offset: 0x8 */ + __O uint32_t CAPCLR; /**< Capture clear register., offset: 0xC */ + __I uint32_t CAP[4]; /**< Capture register ., array offset: 0x10, array step: 0x4 */ +} UTICK_Type; + +/* ---------------------------------------------------------------------------- + -- UTICK Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup UTICK_Register_Masks UTICK Register Masks + * @{ + */ + +/*! @name CTRL - Control register. */ +/*! @{ */ + +#define UTICK_CTRL_DELAYVAL_MASK (0x7FFFFFFFU) +#define UTICK_CTRL_DELAYVAL_SHIFT (0U) +/*! DELAYVAL - Tick interval value. The delay will be equal to DELAYVAL + 1 periods of the timer + * clock. The minimum usable value is 1, for a delay of 2 timer clocks. A value of 0 stops the timer. + */ +#define UTICK_CTRL_DELAYVAL(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CTRL_DELAYVAL_SHIFT)) & UTICK_CTRL_DELAYVAL_MASK) + +#define UTICK_CTRL_REPEAT_MASK (0x80000000U) +#define UTICK_CTRL_REPEAT_SHIFT (31U) +/*! REPEAT - Repeat delay. 0 = One-time delay. 1 = Delay repeats continuously. + */ +#define UTICK_CTRL_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CTRL_REPEAT_SHIFT)) & UTICK_CTRL_REPEAT_MASK) +/*! @} */ + +/*! @name STAT - Status register. */ +/*! @{ */ + +#define UTICK_STAT_INTR_MASK (0x1U) +#define UTICK_STAT_INTR_SHIFT (0U) +/*! INTR - Interrupt flag. 0 = No interrupt is pending. 1 = An interrupt is pending. A write of any + * value to this register clears this flag. + */ +#define UTICK_STAT_INTR(x) (((uint32_t)(((uint32_t)(x)) << UTICK_STAT_INTR_SHIFT)) & UTICK_STAT_INTR_MASK) + +#define UTICK_STAT_ACTIVE_MASK (0x2U) +#define UTICK_STAT_ACTIVE_SHIFT (1U) +/*! ACTIVE - Active flag. 0 = The Micro-Tick Timer is stopped. 1 = The Micro-Tick Timer is currently active. + */ +#define UTICK_STAT_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << UTICK_STAT_ACTIVE_SHIFT)) & UTICK_STAT_ACTIVE_MASK) +/*! @} */ + +/*! @name CFG - Capture configuration register. */ +/*! @{ */ + +#define UTICK_CFG_CAPEN0_MASK (0x1U) +#define UTICK_CFG_CAPEN0_SHIFT (0U) +/*! CAPEN0 - Enable Capture 0. 1 = Enabled, 0 = Disabled. + */ +#define UTICK_CFG_CAPEN0(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN0_SHIFT)) & UTICK_CFG_CAPEN0_MASK) + +#define UTICK_CFG_CAPEN1_MASK (0x2U) +#define UTICK_CFG_CAPEN1_SHIFT (1U) +/*! CAPEN1 - Enable Capture 1. 1 = Enabled, 0 = Disabled. + */ +#define UTICK_CFG_CAPEN1(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN1_SHIFT)) & UTICK_CFG_CAPEN1_MASK) + +#define UTICK_CFG_CAPEN2_MASK (0x4U) +#define UTICK_CFG_CAPEN2_SHIFT (2U) +/*! CAPEN2 - Enable Capture 2. 1 = Enabled, 0 = Disabled. + */ +#define UTICK_CFG_CAPEN2(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN2_SHIFT)) & UTICK_CFG_CAPEN2_MASK) + +#define UTICK_CFG_CAPEN3_MASK (0x8U) +#define UTICK_CFG_CAPEN3_SHIFT (3U) +/*! CAPEN3 - Enable Capture 3. 1 = Enabled, 0 = Disabled. + */ +#define UTICK_CFG_CAPEN3(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN3_SHIFT)) & UTICK_CFG_CAPEN3_MASK) + +#define UTICK_CFG_CAPPOL0_MASK (0x100U) +#define UTICK_CFG_CAPPOL0_SHIFT (8U) +/*! CAPPOL0 - Capture Polarity 0. 0 = Positive edge capture, 1 = Negative edge capture. + */ +#define UTICK_CFG_CAPPOL0(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL0_SHIFT)) & UTICK_CFG_CAPPOL0_MASK) + +#define UTICK_CFG_CAPPOL1_MASK (0x200U) +#define UTICK_CFG_CAPPOL1_SHIFT (9U) +/*! CAPPOL1 - Capture Polarity 1. 0 = Positive edge capture, 1 = Negative edge capture. + */ +#define UTICK_CFG_CAPPOL1(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL1_SHIFT)) & UTICK_CFG_CAPPOL1_MASK) + +#define UTICK_CFG_CAPPOL2_MASK (0x400U) +#define UTICK_CFG_CAPPOL2_SHIFT (10U) +/*! CAPPOL2 - Capture Polarity 2. 0 = Positive edge capture, 1 = Negative edge capture. + */ +#define UTICK_CFG_CAPPOL2(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL2_SHIFT)) & UTICK_CFG_CAPPOL2_MASK) + +#define UTICK_CFG_CAPPOL3_MASK (0x800U) +#define UTICK_CFG_CAPPOL3_SHIFT (11U) +/*! CAPPOL3 - Capture Polarity 3. 0 = Positive edge capture, 1 = Negative edge capture. + */ +#define UTICK_CFG_CAPPOL3(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL3_SHIFT)) & UTICK_CFG_CAPPOL3_MASK) +/*! @} */ + +/*! @name CAPCLR - Capture clear register. */ +/*! @{ */ + +#define UTICK_CAPCLR_CAPCLR0_MASK (0x1U) +#define UTICK_CAPCLR_CAPCLR0_SHIFT (0U) +/*! CAPCLR0 - Clear capture 0. Writing 1 to this bit clears the CAP0 register value. + */ +#define UTICK_CAPCLR_CAPCLR0(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR0_SHIFT)) & UTICK_CAPCLR_CAPCLR0_MASK) + +#define UTICK_CAPCLR_CAPCLR1_MASK (0x2U) +#define UTICK_CAPCLR_CAPCLR1_SHIFT (1U) +/*! CAPCLR1 - Clear capture 1. Writing 1 to this bit clears the CAP1 register value. + */ +#define UTICK_CAPCLR_CAPCLR1(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR1_SHIFT)) & UTICK_CAPCLR_CAPCLR1_MASK) + +#define UTICK_CAPCLR_CAPCLR2_MASK (0x4U) +#define UTICK_CAPCLR_CAPCLR2_SHIFT (2U) +/*! CAPCLR2 - Clear capture 2. Writing 1 to this bit clears the CAP2 register value. + */ +#define UTICK_CAPCLR_CAPCLR2(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR2_SHIFT)) & UTICK_CAPCLR_CAPCLR2_MASK) + +#define UTICK_CAPCLR_CAPCLR3_MASK (0x8U) +#define UTICK_CAPCLR_CAPCLR3_SHIFT (3U) +/*! CAPCLR3 - Clear capture 3. Writing 1 to this bit clears the CAP3 register value. + */ +#define UTICK_CAPCLR_CAPCLR3(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR3_SHIFT)) & UTICK_CAPCLR_CAPCLR3_MASK) +/*! @} */ + +/*! @name CAP - Capture register . */ +/*! @{ */ + +#define UTICK_CAP_CAP_VALUE_MASK (0x7FFFFFFFU) +#define UTICK_CAP_CAP_VALUE_SHIFT (0U) +/*! CAP_VALUE - Capture value for the related capture event (UTICK_CAPn. Note: the value is 1 lower + * than the actual value of the Micro-tick Timer at the moment of the capture event. + */ +#define UTICK_CAP_CAP_VALUE(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAP_CAP_VALUE_SHIFT)) & UTICK_CAP_CAP_VALUE_MASK) + +#define UTICK_CAP_VALID_MASK (0x80000000U) +#define UTICK_CAP_VALID_SHIFT (31U) +/*! VALID - Capture Valid. When 1, a value has been captured based on a transition of the related + * UTICK_CAPn pin. Cleared by writing to the related bit in the CAPCLR register. + */ +#define UTICK_CAP_VALID(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAP_VALID_SHIFT)) & UTICK_CAP_VALID_MASK) +/*! @} */ + +/* The count of UTICK_CAP */ +#define UTICK_CAP_COUNT (4U) + + +/*! + * @} + */ /* end of group UTICK_Register_Masks */ + + +/* UTICK - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral UTICK0 base address */ + #define UTICK0_BASE (0x5000E000u) + /** Peripheral UTICK0 base address */ + #define UTICK0_BASE_NS (0x4000E000u) + /** Peripheral UTICK0 base pointer */ + #define UTICK0 ((UTICK_Type *)UTICK0_BASE) + /** Peripheral UTICK0 base pointer */ + #define UTICK0_NS ((UTICK_Type *)UTICK0_BASE_NS) + /** Array initializer of UTICK peripheral base addresses */ + #define UTICK_BASE_ADDRS { UTICK0_BASE } + /** Array initializer of UTICK peripheral base pointers */ + #define UTICK_BASE_PTRS { UTICK0 } + /** Array initializer of UTICK peripheral base addresses */ + #define UTICK_BASE_ADDRS_NS { UTICK0_BASE_NS } + /** Array initializer of UTICK peripheral base pointers */ + #define UTICK_BASE_PTRS_NS { UTICK0_NS } +#else + /** Peripheral UTICK0 base address */ + #define UTICK0_BASE (0x4000E000u) + /** Peripheral UTICK0 base pointer */ + #define UTICK0 ((UTICK_Type *)UTICK0_BASE) + /** Array initializer of UTICK peripheral base addresses */ + #define UTICK_BASE_ADDRS { UTICK0_BASE } + /** Array initializer of UTICK peripheral base pointers */ + #define UTICK_BASE_PTRS { UTICK0 } +#endif +/** Interrupt vectors for the UTICK peripheral type */ +#define UTICK_IRQS { UTICK0_IRQn } + +/*! + * @} + */ /* end of group UTICK_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- WWDT Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup WWDT_Peripheral_Access_Layer WWDT Peripheral Access Layer + * @{ + */ + +/** WWDT - Register Layout Typedef */ +typedef struct { + __IO uint32_t MOD; /**< Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer., offset: 0x0 */ + __IO uint32_t TC; /**< Watchdog timer constant register. This 24-bit register determines the time-out value., offset: 0x4 */ + __O uint32_t FEED; /**< Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in TC., offset: 0x8 */ + __I uint32_t TV; /**< Watchdog timer value register. This 24-bit register reads out the current value of the Watchdog timer., offset: 0xC */ + uint8_t RESERVED_0[4]; + __IO uint32_t WARNINT; /**< Watchdog Warning Interrupt compare value., offset: 0x14 */ + __IO uint32_t WINDOW; /**< Watchdog Window compare value., offset: 0x18 */ +} WWDT_Type; + +/* ---------------------------------------------------------------------------- + -- WWDT Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup WWDT_Register_Masks WWDT Register Masks + * @{ + */ + +/*! @name MOD - Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer. */ +/*! @{ */ + +#define WWDT_MOD_WDEN_MASK (0x1U) +#define WWDT_MOD_WDEN_SHIFT (0U) +/*! WDEN - Watchdog enable bit. Once this bit is set to one and a watchdog feed is performed, the + * watchdog timer will run permanently. + * 0b0..Stop. The watchdog timer is stopped. + * 0b1..Run. The watchdog timer is running. + */ +#define WWDT_MOD_WDEN(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDEN_SHIFT)) & WWDT_MOD_WDEN_MASK) + +#define WWDT_MOD_WDRESET_MASK (0x2U) +#define WWDT_MOD_WDRESET_SHIFT (1U) +/*! WDRESET - Watchdog reset enable bit. Once this bit has been written with a 1 it cannot be re-written with a 0. + * 0b0..Interrupt. A watchdog time-out will not cause a chip reset. + * 0b1..Reset. A watchdog time-out will cause a chip reset. + */ +#define WWDT_MOD_WDRESET(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDRESET_SHIFT)) & WWDT_MOD_WDRESET_MASK) + +#define WWDT_MOD_WDTOF_MASK (0x4U) +#define WWDT_MOD_WDTOF_SHIFT (2U) +/*! WDTOF - Watchdog time-out flag. Set when the watchdog timer times out, by a feed error, or by + * events associated with WDPROTECT. Cleared by software writing a 0 to this bit position. Causes a + * chip reset if WDRESET = 1. + */ +#define WWDT_MOD_WDTOF(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDTOF_SHIFT)) & WWDT_MOD_WDTOF_MASK) + +#define WWDT_MOD_WDINT_MASK (0x8U) +#define WWDT_MOD_WDINT_SHIFT (3U) +/*! WDINT - Warning interrupt flag. Set when the timer is at or below the value in WDWARNINT. + * Cleared by software writing a 1 to this bit position. Note that this bit cannot be cleared while the + * WARNINT value is equal to the value of the TV register. This can occur if the value of + * WARNINT is 0 and the WDRESET bit is 0 when TV decrements to 0. + */ +#define WWDT_MOD_WDINT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDINT_SHIFT)) & WWDT_MOD_WDINT_MASK) + +#define WWDT_MOD_WDPROTECT_MASK (0x10U) +#define WWDT_MOD_WDPROTECT_SHIFT (4U) +/*! WDPROTECT - Watchdog update mode. This bit can be set once by software and is only cleared by a reset. + * 0b0..Flexible. The watchdog time-out value (TC) can be changed at any time. + * 0b1..Threshold. The watchdog time-out value (TC) can be changed only after the counter is below the value of WDWARNINT and WDWINDOW. + */ +#define WWDT_MOD_WDPROTECT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDPROTECT_SHIFT)) & WWDT_MOD_WDPROTECT_MASK) +/*! @} */ + +/*! @name TC - Watchdog timer constant register. This 24-bit register determines the time-out value. */ +/*! @{ */ + +#define WWDT_TC_COUNT_MASK (0xFFFFFFU) +#define WWDT_TC_COUNT_SHIFT (0U) +/*! COUNT - Watchdog time-out value. + */ +#define WWDT_TC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_TC_COUNT_SHIFT)) & WWDT_TC_COUNT_MASK) +/*! @} */ + +/*! @name FEED - Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in TC. */ +/*! @{ */ + +#define WWDT_FEED_FEED_MASK (0xFFU) +#define WWDT_FEED_FEED_SHIFT (0U) +/*! FEED - Feed value should be 0xAA followed by 0x55. + */ +#define WWDT_FEED_FEED(x) (((uint32_t)(((uint32_t)(x)) << WWDT_FEED_FEED_SHIFT)) & WWDT_FEED_FEED_MASK) +/*! @} */ + +/*! @name TV - Watchdog timer value register. This 24-bit register reads out the current value of the Watchdog timer. */ +/*! @{ */ + +#define WWDT_TV_COUNT_MASK (0xFFFFFFU) +#define WWDT_TV_COUNT_SHIFT (0U) +/*! COUNT - Counter timer value. + */ +#define WWDT_TV_COUNT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_TV_COUNT_SHIFT)) & WWDT_TV_COUNT_MASK) +/*! @} */ + +/*! @name WARNINT - Watchdog Warning Interrupt compare value. */ +/*! @{ */ + +#define WWDT_WARNINT_WARNINT_MASK (0x3FFU) +#define WWDT_WARNINT_WARNINT_SHIFT (0U) +/*! WARNINT - Watchdog warning interrupt compare value. + */ +#define WWDT_WARNINT_WARNINT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_WARNINT_WARNINT_SHIFT)) & WWDT_WARNINT_WARNINT_MASK) +/*! @} */ + +/*! @name WINDOW - Watchdog Window compare value. */ +/*! @{ */ + +#define WWDT_WINDOW_WINDOW_MASK (0xFFFFFFU) +#define WWDT_WINDOW_WINDOW_SHIFT (0U) +/*! WINDOW - Watchdog window value. + */ +#define WWDT_WINDOW_WINDOW(x) (((uint32_t)(((uint32_t)(x)) << WWDT_WINDOW_WINDOW_SHIFT)) & WWDT_WINDOW_WINDOW_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group WWDT_Register_Masks */ + + +/* WWDT - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral WWDT base address */ + #define WWDT_BASE (0x5000C000u) + /** Peripheral WWDT base address */ + #define WWDT_BASE_NS (0x4000C000u) + /** Peripheral WWDT base pointer */ + #define WWDT ((WWDT_Type *)WWDT_BASE) + /** Peripheral WWDT base pointer */ + #define WWDT_NS ((WWDT_Type *)WWDT_BASE_NS) + /** Array initializer of WWDT peripheral base addresses */ + #define WWDT_BASE_ADDRS { WWDT_BASE } + /** Array initializer of WWDT peripheral base pointers */ + #define WWDT_BASE_PTRS { WWDT } + /** Array initializer of WWDT peripheral base addresses */ + #define WWDT_BASE_ADDRS_NS { WWDT_BASE_NS } + /** Array initializer of WWDT peripheral base pointers */ + #define WWDT_BASE_PTRS_NS { WWDT_NS } +#else + /** Peripheral WWDT base address */ + #define WWDT_BASE (0x4000C000u) + /** Peripheral WWDT base pointer */ + #define WWDT ((WWDT_Type *)WWDT_BASE) + /** Array initializer of WWDT peripheral base addresses */ + #define WWDT_BASE_ADDRS { WWDT_BASE } + /** Array initializer of WWDT peripheral base pointers */ + #define WWDT_BASE_PTRS { WWDT } +#endif +/** Interrupt vectors for the WWDT peripheral type */ +#define WWDT_IRQS { WDT_BOD_IRQn } + +/*! + * @} + */ /* end of group WWDT_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +/* ---------------------------------------------------------------------------- + -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). + * @{ + */ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang system_header + #endif +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma system_include +#endif + +/** + * @brief Mask and left-shift a bit field value for use in a register bit range. + * @param field Name of the register bit field. + * @param value Value of the bit field. + * @return Masked and shifted value. + */ +#define NXP_VAL2FLD(field, value) (((value) << (field ## _SHIFT)) & (field ## _MASK)) +/** + * @brief Mask and right-shift a register value to extract a bit field value. + * @param field Name of the register bit field. + * @param value Value of the register. + * @return Masked and shifted bit field value. + */ +#define NXP_FLD2VAL(field, value) (((value) & (field ## _MASK)) >> (field ## _SHIFT)) + +/*! + * @} + */ /* end of group Bit_Field_Generic_Macros */ + + +/* ---------------------------------------------------------------------------- + -- SDK Compatibility + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SDK_Compatibility_Symbols SDK Compatibility + * @{ + */ + +/** High Speed SPI (Flexcomm 8) interrupt name */ +#define LSPI_HS_IRQn FLEXCOMM8_IRQn + + +/*! + * @} + */ /* end of group SDK_Compatibility_Symbols */ + + +#endif /* _LPC55S16_H_ */ + diff --git a/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/LPC55S16_features.h b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/LPC55S16_features.h new file mode 100644 index 0000000000..34d3df6c55 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/LPC55S16_features.h @@ -0,0 +1,451 @@ +/* +** ################################################################### +** Version: rev. 1.1, 2019-12-03 +** Build: b220303 +** +** Abstract: +** Chip specific module features. +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2022 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2018-08-22) +** Initial version based on v0.2UM +** - rev. 1.1 (2019-12-03) +** Initial version based on v0.6UM +** +** ################################################################### +*/ + +#ifndef _LPC55S16_FEATURES_H_ +#define _LPC55S16_FEATURES_H_ + +/* SOC module features */ + +/* @brief LPC_CAN availability on the SoC. */ +#define FSL_FEATURE_SOC_LPC_CAN_COUNT (1) +/* @brief CASPER availability on the SoC. */ +#define FSL_FEATURE_SOC_CASPER_COUNT (1) +/* @brief CRC availability on the SoC. */ +#define FSL_FEATURE_SOC_CRC_COUNT (1) +/* @brief CTIMER availability on the SoC. */ +#define FSL_FEATURE_SOC_CTIMER_COUNT (5) +/* @brief CDOG availability on the SoC. */ +#define FSL_FEATURE_SOC_CDOG_COUNT (1) +/* @brief DMA availability on the SoC. */ +#define FSL_FEATURE_SOC_DMA_COUNT (2) +/* @brief FLASH availability on the SoC. */ +#define FSL_FEATURE_SOC_FLASH_COUNT (1) +/* @brief FLEXCOMM availability on the SoC. */ +#define FSL_FEATURE_SOC_FLEXCOMM_COUNT (9) +/* @brief GINT availability on the SoC. */ +#define FSL_FEATURE_SOC_GINT_COUNT (2) +/* @brief GPIO availability on the SoC. */ +#define FSL_FEATURE_SOC_GPIO_COUNT (1) +/* @brief SECGPIO availability on the SoC. */ +#define FSL_FEATURE_SOC_SECGPIO_COUNT (1) +/* @brief HASHCRYPT availability on the SoC. */ +#define FSL_FEATURE_SOC_HASHCRYPT_COUNT (1) +/* @brief I2C availability on the SoC. */ +#define FSL_FEATURE_SOC_I2C_COUNT (8) +/* @brief I2S availability on the SoC. */ +#define FSL_FEATURE_SOC_I2S_COUNT (8) +/* @brief INPUTMUX availability on the SoC. */ +#define FSL_FEATURE_SOC_INPUTMUX_COUNT (1) +/* @brief IOCON availability on the SoC. */ +#define FSL_FEATURE_SOC_IOCON_COUNT (1) +/* @brief LPADC availability on the SoC. */ +#define FSL_FEATURE_SOC_LPADC_COUNT (1) +/* @brief MRT availability on the SoC. */ +#define FSL_FEATURE_SOC_MRT_COUNT (1) +/* @brief OSTIMER availability on the SoC. */ +#define FSL_FEATURE_SOC_OSTIMER_COUNT (1) +/* @brief PINT availability on the SoC. */ +#define FSL_FEATURE_SOC_PINT_COUNT (1) +/* @brief SECPINT availability on the SoC. */ +#define FSL_FEATURE_SOC_SECPINT_COUNT (1) +/* @brief PMC availability on the SoC. */ +#define FSL_FEATURE_SOC_PMC_COUNT (1) +/* @brief PUF availability on the SoC. */ +#define FSL_FEATURE_SOC_PUF_COUNT (1) +/* @brief PUF_SRAM_CTRL availability on the SoC. */ +#define FSL_FEATURE_SOC_PUF_SRAM_CTRL_COUNT (1) +/* @brief LPC_RNG1 availability on the SoC. */ +#define FSL_FEATURE_SOC_LPC_RNG1_COUNT (1) +/* @brief RTC availability on the SoC. */ +#define FSL_FEATURE_SOC_RTC_COUNT (1) +/* @brief SCT availability on the SoC. */ +#define FSL_FEATURE_SOC_SCT_COUNT (1) +/* @brief SPI availability on the SoC. */ +#define FSL_FEATURE_SOC_SPI_COUNT (9) +/* @brief SYSCON availability on the SoC. */ +#define FSL_FEATURE_SOC_SYSCON_COUNT (1) +/* @brief SYSCTL1 availability on the SoC. */ +#define FSL_FEATURE_SOC_SYSCTL1_COUNT (1) +/* @brief USART availability on the SoC. */ +#define FSL_FEATURE_SOC_USART_COUNT (8) +/* @brief USB availability on the SoC. */ +#define FSL_FEATURE_SOC_USB_COUNT (1) +/* @brief USBFSH availability on the SoC. */ +#define FSL_FEATURE_SOC_USBFSH_COUNT (1) +/* @brief USBHSD availability on the SoC. */ +#define FSL_FEATURE_SOC_USBHSD_COUNT (1) +/* @brief USBHSH availability on the SoC. */ +#define FSL_FEATURE_SOC_USBHSH_COUNT (1) +/* @brief USBPHY availability on the SoC. */ +#define FSL_FEATURE_SOC_USBPHY_COUNT (1) +/* @brief UTICK availability on the SoC. */ +#define FSL_FEATURE_SOC_UTICK_COUNT (1) +/* @brief WWDT availability on the SoC. */ +#define FSL_FEATURE_SOC_WWDT_COUNT (1) + +/* LPADC module features */ + +/* @brief FIFO availability on the SoC. */ +#define FSL_FEATURE_LPADC_FIFO_COUNT (2) +/* @brief Has subsequent trigger priority (bitfield CFG[TPRICTRL]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_SUBSEQUENT_PRIORITY (1) +/* @brief Has differential mode (bitfield CMDLn[DIFF]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_DIFF (0) +/* @brief Has channel scale (bitfield CMDLn[CSCALE]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_CSCALE (0) +/* @brief Has conversion type select (bitfield CMDLn[CTYPE]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_CTYPE (1) +/* @brief Has conversion resolution select (bitfield CMDLn[MODE]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_MODE (1) +/* @brief Has compare function enable (bitfield CMDHn[CMPEN]). */ +#define FSL_FEATURE_LPADC_HAS_CMDH_CMPEN (1) +/* @brief Has Wait for trigger assertion before execution (bitfield CMDHn[WAIT_TRIG]). */ +#define FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG (1) +/* @brief Has offset calibration (bitfield CTRL[CALOFS]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CALOFS (1) +/* @brief Has gain calibration (bitfield CTRL[CAL_REQ]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ (1) +/* @brief Has calibration average (bitfield CTRL[CAL_AVGS]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS (1) +/* @brief Has internal clock (bitfield CFG[ADCKEN]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_ADCKEN (0) +/* @brief Enable support for low voltage reference on option 1 reference (bitfield CFG[VREF1RNG]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG (0) +/* @brief Has calibration (bitfield CFG[CALOFS]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_CALOFS (0) +/* @brief Has offset trim (register OFSTRIM). */ +#define FSL_FEATURE_LPADC_HAS_OFSTRIM (1) +/* @brief Has Trigger status register. */ +#define FSL_FEATURE_LPADC_HAS_TSTAT (1) +/* @brief Has power select (bitfield CFG[PWRSEL]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_PWRSEL (1) +/* @brief Has alternate channel B scale (bitfield CMDLn[ALTB_CSCALE]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_ALTB_CSCALE (0) +/* @brief Has alternate channel B select enable (bitfield CMDLn[ALTBEN]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_ALTBEN (0) +/* @brief Has alternate channel input (bitfield CMDLn[ALTB_ADCH]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_ALTB_ADCH (0) +/* @brief Has offset calibration mode (bitfield CTRL[CALOFSMODE]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE (0) +/* @brief Conversion averaged bitfiled width. */ +#define FSL_FEATURE_LPADC_CONVERSIONS_AVERAGED_BITFIELD_WIDTH (3) +/* @brief Has internal temperature sensor. */ +#define FSL_FEATURE_LPADC_HAS_INTERNAL_TEMP_SENSOR (1) +/* @brief Temperature sensor parameter A (slope). */ +#define FSL_FEATURE_LPADC_TEMP_PARAMETER_A (799.0f) +/* @brief Temperature sensor parameter B (offset). */ +#define FSL_FEATURE_LPADC_TEMP_PARAMETER_B (280.0f) +/* @brief Temperature sensor parameter Alpha. */ +#define FSL_FEATURE_LPADC_TEMP_PARAMETER_ALPHA (8.5f) +/* @brief Temperature sensor need calibration. */ +#define FSL_FEATURE_LPADC_TEMP_NEED_CALIBRATION (1) +/* @brief the address of temperature sensor parameter A (slope) in Flash. */ +#define FSL_FEATURE_FLASH_NMPA_TEMP_SLOPE_ADDRS (0x3FD28U) +/* @brief the address of temperature sensor parameter B (offset) in Flash. */ +#define FSL_FEATURE_FLASH_NMPA_TEMP_OFFSET_ADDRS (0x3FD2CU) +/* @brief the buffer size of temperature sensor. */ +#define FSL_FEATURE_LPADC_TEMP_SENS_BUFFER_SIZE (2U) + +/* ANALOGCTRL module features */ + +/* @brief Has PLL_USB_OUT_BIT_FIELD bitfile in XO32M_CTRL reigster. */ +#define FSL_FEATURE_ANACTRL_HAS_NO_ENABLE_PLL_USB_OUT_BIT_FIELD (1) +/* @brief Has XO32M_ADC_CLK_MODE bitfile in DUMMY_CTRL reigster. */ +#define FSL_FEATURE_ANACTRL_HAS_XO32M_ADC_CLK_MODE_BIF_FIELD (1) +/* @brief Has auxiliary bias(register AUX_BIAS). */ +#define FSL_FEATURE_ANACTRL_HAS_AUX_BIAS_REG (1) + +/* CAN module features */ + +/* @brief Support CANFD or not */ +#define FSL_FEATURE_CAN_SUPPORT_CANFD (1) + +/* CASPER module features */ + +/* @brief Base address of the CASPER dedicated RAM */ +#define FSL_FEATURE_CASPER_RAM_BASE_ADDRESS (0x04000000) +/* @brief HW interleaving of the CASPER dedicated RAM */ +#define FSL_FEATURE_CASPER_RAM_HW_INTERLEAVE (1) + +/* CTIMER module features */ + +/* @brief CTIMER has no capture channel. */ +#define FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE (0) +/* @brief CTIMER has no capture 2 interrupt. */ +#define FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT (0) +/* @brief CTIMER capture 3 interrupt. */ +#define FSL_FEATURE_CTIMER_HAS_IR_CR3INT (1) +/* @brief Has CTIMER CCR_CAP2 (register bits CCR[CAP2RE][CAP2FE][CAP2I]. */ +#define FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2 (0) +/* @brief Has CTIMER CCR_CAP3 (register bits CCR[CAP3RE][CAP3FE][CAP3I]). */ +#define FSL_FEATURE_CTIMER_HAS_CCR_CAP3 (1) + +/* DMA module features */ + +/* @brief Number of channels */ +#define FSL_FEATURE_DMA_NUMBER_OF_CHANNELS (23) +/* @brief Align size of DMA descriptor */ +#define FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE (512) +/* @brief DMA head link descriptor table align size */ +#define FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE (16U) + +/* FLEXCOMM module features */ + +/* @brief FLEXCOMM0 USART INDEX 0 */ +#define FSL_FEATURE_FLEXCOMM0_USART_INDEX (0) +/* @brief FLEXCOMM0 SPI INDEX 0 */ +#define FSL_FEATURE_FLEXCOMM0_SPI_INDEX (0) +/* @brief FLEXCOMM0 I2C INDEX 0 */ +#define FSL_FEATURE_FLEXCOMM0_I2C_INDEX (0) +/* @brief FLEXCOMM0 I2S INDEX 0 */ +#define FSL_FEATURE_FLEXCOMM0_I2S_INDEX (0) +/* @brief FLEXCOMM1 USART INDEX 1 */ +#define FSL_FEATURE_FLEXCOMM1_USART_INDEX (1) +/* @brief FLEXCOMM1 SPI INDEX 1 */ +#define FSL_FEATURE_FLEXCOMM1_SPI_INDEX (1) +/* @brief FLEXCOMM1 I2C INDEX 1 */ +#define FSL_FEATURE_FLEXCOMM1_I2C_INDEX (1) +/* @brief FLEXCOMM1 I2S INDEX 1 */ +#define FSL_FEATURE_FLEXCOMM1_I2S_INDEX (1) +/* @brief FLEXCOMM2 USART INDEX 2 */ +#define FSL_FEATURE_FLEXCOMM2_USART_INDEX (2) +/* @brief FLEXCOMM2 SPI INDEX 2 */ +#define FSL_FEATURE_FLEXCOMM2_SPI_INDEX (2) +/* @brief FLEXCOMM2 I2C INDEX 2 */ +#define FSL_FEATURE_FLEXCOMM2_I2C_INDEX (2) +/* @brief FLEXCOMM2 I2S INDEX 2 */ +#define FSL_FEATURE_FLEXCOMM2_I2S_INDEX (2) +/* @brief FLEXCOMM3 USART INDEX 3 */ +#define FSL_FEATURE_FLEXCOMM3_USART_INDEX (3) +/* @brief FLEXCOMM3 SPI INDEX 3 */ +#define FSL_FEATURE_FLEXCOMM3_SPI_INDEX (3) +/* @brief FLEXCOMM3 I2C INDEX 3 */ +#define FSL_FEATURE_FLEXCOMM3_I2C_INDEX (3) +/* @brief FLEXCOMM3 I2S INDEX 3 */ +#define FSL_FEATURE_FLEXCOMM3_I2S_INDEX (3) +/* @brief FLEXCOMM4 USART INDEX 4 */ +#define FSL_FEATURE_FLEXCOMM4_USART_INDEX (4) +/* @brief FLEXCOMM4 SPI INDEX 4 */ +#define FSL_FEATURE_FLEXCOMM4_SPI_INDEX (4) +/* @brief FLEXCOMM4 I2C INDEX 4 */ +#define FSL_FEATURE_FLEXCOMM4_I2C_INDEX (4) +/* @brief FLEXCOMM4 I2S INDEX 4 */ +#define FSL_FEATURE_FLEXCOMM4_I2S_INDEX (4) +/* @brief FLEXCOMM5 USART INDEX 5 */ +#define FSL_FEATURE_FLEXCOMM5_USART_INDEX (5) +/* @brief FLEXCOMM5 SPI INDEX 5 */ +#define FSL_FEATURE_FLEXCOMM5_SPI_INDEX (5) +/* @brief FLEXCOMM5 I2C INDEX 5 */ +#define FSL_FEATURE_FLEXCOMM5_I2C_INDEX (5) +/* @brief FLEXCOMM5 I2S INDEX 5 */ +#define FSL_FEATURE_FLEXCOMM5_I2S_INDEX (5) +/* @brief FLEXCOMM6 USART INDEX 6 */ +#define FSL_FEATURE_FLEXCOMM6_USART_INDEX (6) +/* @brief FLEXCOMM6 SPI INDEX 6 */ +#define FSL_FEATURE_FLEXCOMM6_SPI_INDEX (6) +/* @brief FLEXCOMM6 I2C INDEX 6 */ +#define FSL_FEATURE_FLEXCOMM6_I2C_INDEX (6) +/* @brief FLEXCOMM6 I2S INDEX 6 */ +#define FSL_FEATURE_FLEXCOMM6_I2S_INDEX (6) +/* @brief FLEXCOMM7 USART INDEX 7 */ +#define FSL_FEATURE_FLEXCOMM7_USART_INDEX (7) +/* @brief FLEXCOMM7 SPI INDEX 7 */ +#define FSL_FEATURE_FLEXCOMM7_SPI_INDEX (7) +/* @brief FLEXCOMM7 I2C INDEX 7 */ +#define FSL_FEATURE_FLEXCOMM7_I2C_INDEX (7) +/* @brief FLEXCOMM7 I2S INDEX 7 */ +#define FSL_FEATURE_FLEXCOMM7_I2S_INDEX (7) +/* @brief FLEXCOMM8 SPI(HS_SPI) INDEX 8 */ +#define FSL_FEATURE_FLEXCOMM8_SPI_INDEX (8) +/* @brief I2S has DMIC interconnection */ +#define FSL_FEATURE_FLEXCOMM_INSTANCE_I2S_HAS_DMIC_INTERCONNECTIONn(x) (0) +/* @brief I2S support dual channel transfer */ +#define FSL_FEATURE_FLEXCOMM_INSTANCE_I2S_SUPPORT_SECONDARY_CHANNELn(x) \ + (((x) == FLEXCOMM0) ? (0) : \ + (((x) == FLEXCOMM1) ? (0) : \ + (((x) == FLEXCOMM2) ? (0) : \ + (((x) == FLEXCOMM3) ? (0) : \ + (((x) == FLEXCOMM4) ? (0) : \ + (((x) == FLEXCOMM5) ? (0) : \ + (((x) == FLEXCOMM6) ? (1) : \ + (((x) == FLEXCOMM7) ? (1) : \ + (((x) == FLEXCOMM8) ? (0) : (-1)))))))))) + +/* HASHCRYPT module features */ + +/* @brief the address of alias offset */ +#define FSL_FEATURE_HASHCRYPT_ALIAS_OFFSET (0x00000000) +/* @brief hashcrypt has reload feature */ +#define FSL_FEATURE_HASHCRYPT_HAS_RELOAD_FEATURE (1) + +/* I2S module features */ + +/* @brief I2S6 and I2S7 support dual channel transfer. */ +#define FSL_FEATURE_I2S_SUPPORT_SECONDARY_CHANNEL (1) +/* @brief I2S has DMIC interconnection */ +#define FSL_FEATURE_FLEXCOMM_I2S_HAS_DMIC_INTERCONNECTION (0) + +/* IOCON module features */ + +/* @brief Func bit field width */ +#define FSL_FEATURE_IOCON_FUNC_FIELD_WIDTH (4) + +/* MRT module features */ + +/* @brief number of channels. */ +#define FSL_FEATURE_MRT_NUMBER_OF_CHANNELS (4) + +/* PINT module features */ + +/* @brief Number of connected outputs */ +#define FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS (8) + +/* PLU module features */ + +/* @brief Has WAKEINT_CTRL register. */ +#define FSL_FEATURE_PLU_HAS_WAKEINT_CTRL_REG (1) + +/* PMC module features */ + +/* @brief UTICK does not support PD configure. */ +#define FSL_FEATURE_UTICK_HAS_NO_PDCFG (1) +/* @brief WDT OSC does not support PD configure. */ +#define FSL_FEATURE_WWDT_HAS_NO_PDCFG (1) + +/* POWERLIB module features */ + +/* @brief Powerlib API is different with other LPC series devices. */ +#define FSL_FEATURE_POWERLIB_EXTEND (1) + +/* PUF module features */ + +/* @brief Number of PUF key slots available on device. */ +#define FSL_FEATURE_PUF_HAS_KEYSLOTS (4) +/* @brief the shift status value */ +#define FSL_FEATURE_PUF_HAS_SHIFT_STATUS (1) +/* @brief PUF has dedicated SRAM control */ +#define FSL_FEATURE_PUF_HAS_SRAM_CTRL (1) + +/* RTC module features */ + +/* No feature definitions */ + +/* SCT module features */ + +/* @brief Number of events */ +#define FSL_FEATURE_SCT_NUMBER_OF_EVENTS (16) +/* @brief Number of states */ +#define FSL_FEATURE_SCT_NUMBER_OF_STATES (32) +/* @brief Number of match capture */ +#define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (16) +/* @brief Number of outputs */ +#define FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS (10) + +/* SECPINT module features */ + +/* @brief Number of connected outputs */ +#define FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS (2) + +/* SYSCON module features */ + +/* @brief Flash page size in bytes */ +#define FSL_FEATURE_SYSCON_FLASH_PAGE_SIZE_BYTES (512) +/* @brief Flash sector size in bytes */ +#define FSL_FEATURE_SYSCON_FLASH_SECTOR_SIZE_BYTES (32768) +/* @brief Flash size in bytes */ +#define FSL_FEATURE_SYSCON_FLASH_SIZE_BYTES (251904) +/* @brief Has Power Down mode */ +#define FSL_FEATURE_SYSCON_HAS_POWERDOWN_MODE (1) +/* @brief CCM_ANALOG availability on the SoC. */ +#define FSL_FEATURE_SOC_CCM_ANALOG_COUNT (1) +/* @brief Starter register discontinuous. */ +#define FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS (1) + +/* SYSCTL1 module features */ + +/* @brief SYSCTRL has Code Gray feature. */ +#define FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY (1) + +/* USB module features */ + +/* @brief Size of the USB dedicated RAM */ +#define FSL_FEATURE_USB_USB_RAM (0x00004000) +/* @brief Base address of the USB dedicated RAM */ +#define FSL_FEATURE_USB_USB_RAM_BASE_ADDRESS (0x20010000) +/* @brief USB version */ +#define FSL_FEATURE_USB_VERSION (200) +/* @brief Number of the endpoint in USB FS */ +#define FSL_FEATURE_USB_EP_NUM (5) + +/* USBFSH module features */ + +/* @brief Size of the USB dedicated RAM */ +#define FSL_FEATURE_USBFSH_USB_RAM (0x00004000) +/* @brief Base address of the USB dedicated RAM */ +#define FSL_FEATURE_USBFSH_USB_RAM_BASE_ADDRESS (0x20010000) +/* @brief USBFSH version */ +#define FSL_FEATURE_USBFSH_VERSION (200) + +/* USBHSD module features */ + +/* @brief Size of the USB dedicated RAM */ +#define FSL_FEATURE_USBHSD_USB_RAM (0x00004000) +/* @brief Base address of the USB dedicated RAM */ +#define FSL_FEATURE_USBHSD_USB_RAM_BASE_ADDRESS (0x20010000) +/* @brief USBHSD version */ +#define FSL_FEATURE_USBHSD_VERSION (300) +/* @brief Number of the endpoint in USB HS */ +#define FSL_FEATURE_USBHSD_EP_NUM (6) + +/* USBHSH module features */ + +/* @brief Size of the USB dedicated RAM */ +#define FSL_FEATURE_USBHSH_USB_RAM (0x00004000) +/* @brief Base address of the USB dedicated RAM */ +#define FSL_FEATURE_USBHSH_USB_RAM_BASE_ADDRESS (0x20010000) +/* @brief USBHSH version */ +#define FSL_FEATURE_USBHSH_VERSION (300) + +/* USBPHY module features */ + +/* @brief Size of the USB dedicated RAM */ +#define FSL_FEATURE_USBPHY_USB_RAM (0x00004000) +/* @brief Base address of the USB dedicated RAM */ +#define FSL_FEATURE_USBPHY_USB_RAM_BASE_ADDRESS (0x20010000) +/* @brief USBHSD version */ +#define FSL_FEATURE_USBPHY_VERSION (300) +/* @brief Number of the endpoint in USB HS */ +#define FSL_FEATURE_USBPHY_EP_NUM (6) + +/* WWDT module features */ + +/* @brief Has no RESET register. */ +#define FSL_FEATURE_WWDT_HAS_NO_RESET (1) +/* @brief WWDT does not support oscillator lock. */ +#define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (1) + +#endif /* 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Q!e;%gjNM8K<|F0)7b_=Y^8f$< literal 0 HcmV?d00001 diff --git a/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/arm/LPC55S16_flash.scf b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/arm/LPC55S16_flash.scf new file mode 100644 index 0000000000..99d6a233a2 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/arm/LPC55S16_flash.scf @@ -0,0 +1,86 @@ +#!armclang --target=arm-arm-none-eabi -march=armv8-m.main -E -x c +/* +** ################################################################### +** Processors: LPC55S16JBD100 +** LPC55S16JBD64 +** LPC55S16JEV59 +** LPC55S16JEV98 +** +** Compiler: Keil ARM C/C++ Compiler +** Reference manual: LPC55S1x/LPC551x User manual Rev.0.6 15 November 2019 +** Version: rev. 1.1, 2019-12-03 +** Build: b220622 +** +** Abstract: +** Linker file for the Keil ARM C/C++ Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2022 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + + +/* USB BDT size */ +#define usb_bdt_size 0x0 +/* Sizes */ +#if (defined(__stack_size__)) + #define Stack_Size __stack_size__ +#else + #define Stack_Size 0x0400 +#endif + +#if (defined(__heap_size__)) + #define Heap_Size __heap_size__ +#else + #define Heap_Size 0x0400 +#endif + +#define m_interrupts_start 0x00000000 +#define m_interrupts_size 0x00000200 + +#define m_text_start 0x00000200 +#define m_text_size 0x0003CE00 + +#define m_data_start 0x20000000 +#define m_data_size 0x00010000 + +#define m_sramx_start 0x04000000 +#define m_sramx_size 0x00004000 + +#define m_usb_sram_start 0x20010000 +#define m_usb_sram_size 0x00004000 + +LR_m_text m_interrupts_start m_interrupts_size+m_text_size { ; load region size_region + + VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address + * (.isr_vector,+FIRST) + } + + ER_m_text m_text_start FIXED m_text_size { ; load address = execution address + * (InRoot$$Sections) + .ANY (+RO) + } + + RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data + .ANY (+RW +ZI) + } + ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up + } + ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down + } + + RW_m_usb_bdt m_usb_sram_start UNINIT usb_bdt_size { + * (*m_usb_bdt) + } + + RW_m_usb_ram (m_usb_sram_start + usb_bdt_size) UNINIT (m_usb_sram_size - usb_bdt_size) { + * (*m_usb_global) + } +} diff --git a/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/arm/LPC55S16_ram.scf b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/arm/LPC55S16_ram.scf new file mode 100644 index 0000000000..1986299df7 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/arm/LPC55S16_ram.scf @@ -0,0 +1,83 @@ +#!armclang --target=arm-arm-none-eabi -march=armv8-m.main -E -x c +/* +** ################################################################### +** Processors: LPC55S16JBD100 +** LPC55S16JBD64 +** LPC55S16JEV59 +** LPC55S16JEV98 +** +** Compiler: Keil ARM C/C++ Compiler +** Reference manual: LPC55S1x/LPC551x User manual Rev.0.6 15 November 2019 +** Version: rev. 1.1, 2019-12-03 +** Build: b220622 +** +** Abstract: +** Linker file for the Keil ARM C/C++ Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2022 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + + +/* USB BDT size */ +#define usb_bdt_size 0x0 +/* Sizes */ +#if (defined(__stack_size__)) + #define Stack_Size __stack_size__ +#else + #define Stack_Size 0x0400 +#endif + +#if (defined(__heap_size__)) + #define Heap_Size __heap_size__ +#else + #define Heap_Size 0x0400 +#endif + +#define m_interrupts_start 0x20000000 +#define m_interrupts_size 0x00000200 + +#define m_text_start 0x20000200 +#define m_text_size 0x0000FE00 + +#define m_data_start 0x04000000 +#define m_data_size 0x00004000 + +#define m_usb_sram_start 0x20010000 +#define m_usb_sram_size 0x00004000 + +LR_m_text m_interrupts_start m_interrupts_size+m_text_size { ; load region size_region + + VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address + * (.isr_vector,+FIRST) + } + + ER_m_text m_text_start FIXED m_text_size { ; load address = execution address + * (InRoot$$Sections) + .ANY (+RO) + } + + RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data + .ANY (+RW +ZI) + } + ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up + } + ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down + } + + RW_m_usb_bdt m_usb_sram_start UNINIT usb_bdt_size { + * (*m_usb_bdt) + } + + RW_m_usb_ram (m_usb_sram_start + usb_bdt_size) UNINIT (m_usb_sram_size - usb_bdt_size) { + * (*m_usb_global) + } +} diff --git a/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/arm/LPC55S1xx.dbgconf b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/arm/LPC55S1xx.dbgconf new file mode 100644 index 0000000000..1cc3a2af84 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/arm/LPC55S1xx.dbgconf @@ -0,0 +1,18 @@ +// <<< Use Configuration Wizard in Context Menu >>> + +// SWO pin +// The SWO (Serial Wire Output) pin optionally provides data from the ITM +// for an external debug tool to evaluate. +// <0=> PIO0_10 +// <1=> PIO0_8 +SWO_Pin = 0; +// + +// Debug Configuration +// StopAfterBootloader Stop after Bootloader +// +Dbg_CR = 0x00000001; +// + + +// <<< end of configuration section >>> \ No newline at end of file diff --git a/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/arm/startup_LPC55S16.S b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/arm/startup_LPC55S16.S new file mode 100644 index 0000000000..134148bf5e --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/arm/startup_LPC55S16.S @@ -0,0 +1,812 @@ +/* --------------------------------------------------------------------------------------- + * @file: startup_LPC55S16.s + * @purpose: CMSIS Cortex-M33 Core Device Startup File for the LPC55S16 + * @version: 1.1 + * @date: 2019-12-3 + * ---------------------------------------------------------------------------------------*/ +/* + * Copyright 1997-2016 Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +/*****************************************************************************/ +/* Version: GCC for ARM Embedded Processors */ +/*****************************************************************************/ + + .syntax unified + .arch armv8-m.main + .eabi_attribute Tag_ABI_align_preserved, 1 /*8-byte alignment */ + + .section .isr_vector, "a" + .align 2 + .globl __Vectors + +__Vectors: + .long Image$$ARM_LIB_STACK$$ZI$$Limit /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long NMI_Handler /* NMI Handler*/ + .long HardFault_Handler /* Hard Fault Handler*/ + .long MemManage_Handler /* MPU Fault Handler*/ + .long BusFault_Handler /* Bus Fault Handler*/ + .long UsageFault_Handler /* Usage Fault Handler*/ + .long SecureFault_Handler /* Secure Fault Handler*/ + .long 0 /* Reserved*/ + .long 0 /* Reserved*/ + .long 0 /* Reserved*/ + .long SVC_Handler /* SVCall Handler*/ + .long DebugMon_Handler /* Debug Monitor Handler*/ + .long 0 /* Reserved*/ + .long PendSV_Handler /* PendSV Handler*/ + .long SysTick_Handler /* SysTick Handler*/ + + /* External Interrupts*/ + .long WDT_BOD_IRQHandler /* Windowed watchdog timer, Brownout detect, Flash interrupt */ + .long DMA0_IRQHandler /* DMA0 controller */ + .long GINT0_IRQHandler /* GPIO group 0 */ + .long GINT1_IRQHandler /* GPIO group 1 */ + .long PIN_INT0_IRQHandler /* Pin interrupt 0 or pattern match engine slice 0 */ + .long PIN_INT1_IRQHandler /* Pin interrupt 1or pattern match engine slice 1 */ + .long PIN_INT2_IRQHandler /* Pin interrupt 2 or pattern match engine slice 2 */ + .long PIN_INT3_IRQHandler /* Pin interrupt 3 or pattern match engine slice 3 */ + .long UTICK0_IRQHandler /* Micro-tick Timer */ + .long MRT0_IRQHandler /* Multi-rate timer */ + .long CTIMER0_IRQHandler /* Standard counter/timer CTIMER0 */ + .long CTIMER1_IRQHandler /* Standard counter/timer CTIMER1 */ + .long SCT0_IRQHandler /* SCTimer/PWM */ + .long CTIMER3_IRQHandler /* Standard counter/timer CTIMER3 */ + .long FLEXCOMM0_IRQHandler /* Flexcomm Interface 0 (USART, SPI, I2C, I2S, FLEXCOMM) */ + .long FLEXCOMM1_IRQHandler /* Flexcomm Interface 1 (USART, SPI, I2C, I2S, FLEXCOMM) */ + .long FLEXCOMM2_IRQHandler /* Flexcomm Interface 2 (USART, SPI, I2C, I2S, FLEXCOMM) */ + .long FLEXCOMM3_IRQHandler /* Flexcomm Interface 3 (USART, SPI, I2C, I2S, FLEXCOMM) */ + .long FLEXCOMM4_IRQHandler /* Flexcomm Interface 4 (USART, SPI, I2C, I2S, FLEXCOMM) */ + .long FLEXCOMM5_IRQHandler /* Flexcomm Interface 5 (USART, SPI, I2C, I2S, FLEXCOMM) */ + .long FLEXCOMM6_IRQHandler /* Flexcomm Interface 6 (USART, SPI, I2C, I2S, FLEXCOMM) */ + .long FLEXCOMM7_IRQHandler /* Flexcomm Interface 7 (USART, SPI, I2C, I2S, FLEXCOMM) */ + .long ADC0_IRQHandler /* ADC0 */ + .long Reserved39_IRQHandler /* Reserved interrupt */ + .long ACMP_IRQHandler /* ACMP interrupts */ + .long Reserved41_IRQHandler /* Reserved interrupt */ + .long Reserved42_IRQHandler /* Reserved interrupt */ + .long USB0_NEEDCLK_IRQHandler /* USB Activity Wake-up Interrupt */ + .long USB0_IRQHandler /* USB device */ + .long RTC_IRQHandler /* RTC alarm and wake-up interrupts */ + .long Reserved46_IRQHandler /* Reserved interrupt */ + .long Reserved47_IRQHandler /* Reserved interrupt */ + .long PIN_INT4_IRQHandler /* Pin interrupt 4 or pattern match engine slice 4 int */ + .long PIN_INT5_IRQHandler /* Pin interrupt 5 or pattern match engine slice 5 int */ + .long PIN_INT6_IRQHandler /* Pin interrupt 6 or pattern match engine slice 6 int */ + .long PIN_INT7_IRQHandler /* Pin interrupt 7 or pattern match engine slice 7 int */ + .long CTIMER2_IRQHandler /* Standard counter/timer CTIMER2 */ + .long CTIMER4_IRQHandler /* Standard counter/timer CTIMER4 */ + .long OS_EVENT_IRQHandler /* OS_EVENT_TIMER and OS_EVENT_WAKEUP interrupts */ + .long Reserved55_IRQHandler /* Reserved interrupt */ + .long Reserved56_IRQHandler /* Reserved interrupt */ + .long Reserved57_IRQHandler /* Reserved interrupt */ + .long Reserved58_IRQHandler /* Reserved interrupt */ + .long CAN0_IRQ0_IRQHandler /* CAN0 interrupt0 */ + .long CAN0_IRQ1_IRQHandler /* CAN0 interrupt1 */ + .long Reserved61_IRQHandler /* Reserved interrupt */ + .long USB1_PHY_IRQHandler /* USB1_PHY */ + .long USB1_IRQHandler /* USB1 interrupt */ + .long USB1_NEEDCLK_IRQHandler /* USB1 activity */ + .long SEC_HYPERVISOR_CALL_IRQHandler /* SEC_HYPERVISOR_CALL interrupt */ + .long SEC_GPIO_INT0_IRQ0_IRQHandler /* SEC_GPIO_INT0_IRQ0 interrupt */ + .long SEC_GPIO_INT0_IRQ1_IRQHandler /* SEC_GPIO_INT0_IRQ1 interrupt */ + .long PLU_IRQHandler /* PLU interrupt */ + .long SEC_VIO_IRQHandler /* SEC_VIO interrupt */ + .long HASHCRYPT_IRQHandler /* SHA interrupt */ + .long CASER_IRQHandler /* CASPER interrupt */ + .long PUF_IRQHandler /* PUF interrupt */ + .long Reserved73_IRQHandler /* Reserved interrupt */ + .long DMA1_IRQHandler /* DMA1 interrupt */ + .long FLEXCOMM8_IRQHandler /* Flexcomm Interface 8 (SPI, , FLEXCOMM) */ + .long CDOG_IRQHandler /* CDOG interrupt */ + .size __Vectors, . - __Vectors + + .text + .thumb + +/* Reset Handler */ + .thumb_func + .align 2 + .weak Reset_Handler + .type Reset_Handler, %function + +Reset_Handler: + cpsid i /* Mask interrupts */ + .equ VTOR, 0xE000ED08 + ldr r0, =VTOR + ldr r1, =__Vectors + str r1, [r0] + ldr r2, [r1] + msr msp, r2 + ldr R0, =Image$$ARM_LIB_STACK$$ZI$$Base + msr msplim, R0 + ldr r0,=SystemInit + blx r0 + cpsie i /* Unmask interrupts */ + ldr r0,=__main + bx r0 + + .pool + .size Reset_Handler, . - Reset_Handler + + .align 1 + .thumb_func + .weak DefaultISR + .type DefaultISR, %function +DefaultISR: + b DefaultISR + .size DefaultISR, . - DefaultISR + + .align 1 + .thumb_func + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + ldr r0,=NMI_Handler + bx r0 + .size NMI_Handler, . - NMI_Handler + + .align 1 + .thumb_func + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + ldr r0,=HardFault_Handler + bx r0 + .size HardFault_Handler, . - HardFault_Handler + + .align 1 + .thumb_func + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + ldr r0,=SVC_Handler + bx r0 + .size SVC_Handler, . - SVC_Handler + + .align 1 + .thumb_func + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + ldr r0,=PendSV_Handler + bx r0 + .size PendSV_Handler, . - PendSV_Handler + + .align 1 + .thumb_func + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + ldr r0,=SysTick_Handler + bx r0 + .size SysTick_Handler, . - SysTick_Handler + .align 1 + .thumb_func + .weak WDT_BOD_IRQHandler + .type WDT_BOD_IRQHandler, %function +WDT_BOD_IRQHandler: + ldr r0,=WDT_BOD_DriverIRQHandler + bx r0 + .size WDT_BOD_IRQHandler, . - WDT_BOD_IRQHandler + + .align 1 + .thumb_func + .weak DMA0_IRQHandler + .type DMA0_IRQHandler, %function +DMA0_IRQHandler: + ldr r0,=DMA0_DriverIRQHandler + bx r0 + .size DMA0_IRQHandler, . - DMA0_IRQHandler + + .align 1 + .thumb_func + .weak GINT0_IRQHandler + .type GINT0_IRQHandler, %function +GINT0_IRQHandler: + ldr r0,=GINT0_DriverIRQHandler + bx r0 + .size GINT0_IRQHandler, . - GINT0_IRQHandler + + .align 1 + .thumb_func + .weak GINT1_IRQHandler + .type GINT1_IRQHandler, %function +GINT1_IRQHandler: + ldr r0,=GINT1_DriverIRQHandler + bx r0 + .size GINT1_IRQHandler, . - GINT1_IRQHandler + + .align 1 + .thumb_func + .weak PIN_INT0_IRQHandler + .type PIN_INT0_IRQHandler, %function +PIN_INT0_IRQHandler: + ldr r0,=PIN_INT0_DriverIRQHandler + bx r0 + .size PIN_INT0_IRQHandler, . - PIN_INT0_IRQHandler + + .align 1 + .thumb_func + .weak PIN_INT1_IRQHandler + .type PIN_INT1_IRQHandler, %function +PIN_INT1_IRQHandler: + ldr r0,=PIN_INT1_DriverIRQHandler + bx r0 + .size PIN_INT1_IRQHandler, . - PIN_INT1_IRQHandler + + .align 1 + .thumb_func + .weak PIN_INT2_IRQHandler + .type PIN_INT2_IRQHandler, %function +PIN_INT2_IRQHandler: + ldr r0,=PIN_INT2_DriverIRQHandler + bx r0 + .size PIN_INT2_IRQHandler, . - PIN_INT2_IRQHandler + + .align 1 + .thumb_func + .weak PIN_INT3_IRQHandler + .type PIN_INT3_IRQHandler, %function +PIN_INT3_IRQHandler: + ldr r0,=PIN_INT3_DriverIRQHandler + bx r0 + .size PIN_INT3_IRQHandler, . - PIN_INT3_IRQHandler + + .align 1 + .thumb_func + .weak UTICK0_IRQHandler + .type UTICK0_IRQHandler, %function +UTICK0_IRQHandler: + ldr r0,=UTICK0_DriverIRQHandler + bx r0 + .size UTICK0_IRQHandler, . - UTICK0_IRQHandler + + .align 1 + .thumb_func + .weak MRT0_IRQHandler + .type MRT0_IRQHandler, %function +MRT0_IRQHandler: + ldr r0,=MRT0_DriverIRQHandler + bx r0 + .size MRT0_IRQHandler, . - MRT0_IRQHandler + + .align 1 + .thumb_func + .weak CTIMER0_IRQHandler + .type CTIMER0_IRQHandler, %function +CTIMER0_IRQHandler: + ldr r0,=CTIMER0_DriverIRQHandler + bx r0 + .size CTIMER0_IRQHandler, . - CTIMER0_IRQHandler + + .align 1 + .thumb_func + .weak CTIMER1_IRQHandler + .type CTIMER1_IRQHandler, %function +CTIMER1_IRQHandler: + ldr r0,=CTIMER1_DriverIRQHandler + bx r0 + .size CTIMER1_IRQHandler, . - CTIMER1_IRQHandler + + .align 1 + .thumb_func + .weak SCT0_IRQHandler + .type SCT0_IRQHandler, %function +SCT0_IRQHandler: + ldr r0,=SCT0_DriverIRQHandler + bx r0 + .size SCT0_IRQHandler, . - SCT0_IRQHandler + + .align 1 + .thumb_func + .weak CTIMER3_IRQHandler + .type CTIMER3_IRQHandler, %function +CTIMER3_IRQHandler: + ldr r0,=CTIMER3_DriverIRQHandler + bx r0 + .size CTIMER3_IRQHandler, . - CTIMER3_IRQHandler + + .align 1 + .thumb_func + .weak FLEXCOMM0_IRQHandler + .type FLEXCOMM0_IRQHandler, %function +FLEXCOMM0_IRQHandler: + ldr r0,=FLEXCOMM0_DriverIRQHandler + bx r0 + .size FLEXCOMM0_IRQHandler, . - FLEXCOMM0_IRQHandler + + .align 1 + .thumb_func + .weak FLEXCOMM1_IRQHandler + .type FLEXCOMM1_IRQHandler, %function +FLEXCOMM1_IRQHandler: + ldr r0,=FLEXCOMM1_DriverIRQHandler + bx r0 + .size FLEXCOMM1_IRQHandler, . - FLEXCOMM1_IRQHandler + + .align 1 + .thumb_func + .weak FLEXCOMM2_IRQHandler + .type FLEXCOMM2_IRQHandler, %function +FLEXCOMM2_IRQHandler: + ldr r0,=FLEXCOMM2_DriverIRQHandler + bx r0 + .size FLEXCOMM2_IRQHandler, . - FLEXCOMM2_IRQHandler + + .align 1 + .thumb_func + .weak FLEXCOMM3_IRQHandler + .type FLEXCOMM3_IRQHandler, %function +FLEXCOMM3_IRQHandler: + ldr r0,=FLEXCOMM3_DriverIRQHandler + bx r0 + .size FLEXCOMM3_IRQHandler, . - FLEXCOMM3_IRQHandler + + .align 1 + .thumb_func + .weak FLEXCOMM4_IRQHandler + .type FLEXCOMM4_IRQHandler, %function +FLEXCOMM4_IRQHandler: + ldr r0,=FLEXCOMM4_DriverIRQHandler + bx r0 + .size FLEXCOMM4_IRQHandler, . - FLEXCOMM4_IRQHandler + + .align 1 + .thumb_func + .weak FLEXCOMM5_IRQHandler + .type FLEXCOMM5_IRQHandler, %function +FLEXCOMM5_IRQHandler: + ldr r0,=FLEXCOMM5_DriverIRQHandler + bx r0 + .size FLEXCOMM5_IRQHandler, . - FLEXCOMM5_IRQHandler + + .align 1 + .thumb_func + .weak FLEXCOMM6_IRQHandler + .type FLEXCOMM6_IRQHandler, %function +FLEXCOMM6_IRQHandler: + ldr r0,=FLEXCOMM6_DriverIRQHandler + bx r0 + .size FLEXCOMM6_IRQHandler, . - FLEXCOMM6_IRQHandler + + .align 1 + .thumb_func + .weak FLEXCOMM7_IRQHandler + .type FLEXCOMM7_IRQHandler, %function +FLEXCOMM7_IRQHandler: + ldr r0,=FLEXCOMM7_DriverIRQHandler + bx r0 + .size FLEXCOMM7_IRQHandler, . - FLEXCOMM7_IRQHandler + + .align 1 + .thumb_func + .weak ADC0_IRQHandler + .type ADC0_IRQHandler, %function +ADC0_IRQHandler: + ldr r0,=ADC0_DriverIRQHandler + bx r0 + .size ADC0_IRQHandler, . - ADC0_IRQHandler + + .align 1 + .thumb_func + .weak Reserved39_IRQHandler + .type Reserved39_IRQHandler, %function +Reserved39_IRQHandler: + ldr r0,=Reserved39_DriverIRQHandler + bx r0 + .size Reserved39_IRQHandler, . - Reserved39_IRQHandler + + .align 1 + .thumb_func + .weak ACMP_IRQHandler + .type ACMP_IRQHandler, %function +ACMP_IRQHandler: + ldr r0,=ACMP_DriverIRQHandler + bx r0 + .size ACMP_IRQHandler, . - ACMP_IRQHandler + + .align 1 + .thumb_func + .weak Reserved41_IRQHandler + .type Reserved41_IRQHandler, %function +Reserved41_IRQHandler: + ldr r0,=Reserved41_DriverIRQHandler + bx r0 + .size Reserved41_IRQHandler, . - Reserved41_IRQHandler + + .align 1 + .thumb_func + .weak Reserved42_IRQHandler + .type Reserved42_IRQHandler, %function +Reserved42_IRQHandler: + ldr r0,=Reserved42_DriverIRQHandler + bx r0 + .size Reserved42_IRQHandler, . - Reserved42_IRQHandler + + .align 1 + .thumb_func + .weak USB0_NEEDCLK_IRQHandler + .type USB0_NEEDCLK_IRQHandler, %function +USB0_NEEDCLK_IRQHandler: + ldr r0,=USB0_NEEDCLK_DriverIRQHandler + bx r0 + .size USB0_NEEDCLK_IRQHandler, . - USB0_NEEDCLK_IRQHandler + + .align 1 + .thumb_func + .weak USB0_IRQHandler + .type USB0_IRQHandler, %function +USB0_IRQHandler: + ldr r0,=USB0_DriverIRQHandler + bx r0 + .size USB0_IRQHandler, . - USB0_IRQHandler + + .align 1 + .thumb_func + .weak RTC_IRQHandler + .type RTC_IRQHandler, %function +RTC_IRQHandler: + ldr r0,=RTC_DriverIRQHandler + bx r0 + .size RTC_IRQHandler, . - RTC_IRQHandler + + .align 1 + .thumb_func + .weak Reserved46_IRQHandler + .type Reserved46_IRQHandler, %function +Reserved46_IRQHandler: + ldr r0,=Reserved46_DriverIRQHandler + bx r0 + .size Reserved46_IRQHandler, . - Reserved46_IRQHandler + + .align 1 + .thumb_func + .weak Reserved47_IRQHandler + .type Reserved47_IRQHandler, %function +Reserved47_IRQHandler: + ldr r0,=Reserved47_DriverIRQHandler + bx r0 + .size Reserved47_IRQHandler, . - Reserved47_IRQHandler + + .align 1 + .thumb_func + .weak PIN_INT4_IRQHandler + .type PIN_INT4_IRQHandler, %function +PIN_INT4_IRQHandler: + ldr r0,=PIN_INT4_DriverIRQHandler + bx r0 + .size PIN_INT4_IRQHandler, . - PIN_INT4_IRQHandler + + .align 1 + .thumb_func + .weak PIN_INT5_IRQHandler + .type PIN_INT5_IRQHandler, %function +PIN_INT5_IRQHandler: + ldr r0,=PIN_INT5_DriverIRQHandler + bx r0 + .size PIN_INT5_IRQHandler, . - PIN_INT5_IRQHandler + + .align 1 + .thumb_func + .weak PIN_INT6_IRQHandler + .type PIN_INT6_IRQHandler, %function +PIN_INT6_IRQHandler: + ldr r0,=PIN_INT6_DriverIRQHandler + bx r0 + .size PIN_INT6_IRQHandler, . - PIN_INT6_IRQHandler + + .align 1 + .thumb_func + .weak PIN_INT7_IRQHandler + .type PIN_INT7_IRQHandler, %function +PIN_INT7_IRQHandler: + ldr r0,=PIN_INT7_DriverIRQHandler + bx r0 + .size PIN_INT7_IRQHandler, . - PIN_INT7_IRQHandler + + .align 1 + .thumb_func + .weak CTIMER2_IRQHandler + .type CTIMER2_IRQHandler, %function +CTIMER2_IRQHandler: + ldr r0,=CTIMER2_DriverIRQHandler + bx r0 + .size CTIMER2_IRQHandler, . - CTIMER2_IRQHandler + + .align 1 + .thumb_func + .weak CTIMER4_IRQHandler + .type CTIMER4_IRQHandler, %function +CTIMER4_IRQHandler: + ldr r0,=CTIMER4_DriverIRQHandler + bx r0 + .size CTIMER4_IRQHandler, . - CTIMER4_IRQHandler + + .align 1 + .thumb_func + .weak OS_EVENT_IRQHandler + .type OS_EVENT_IRQHandler, %function +OS_EVENT_IRQHandler: + ldr r0,=OS_EVENT_DriverIRQHandler + bx r0 + .size OS_EVENT_IRQHandler, . - OS_EVENT_IRQHandler + + .align 1 + .thumb_func + .weak Reserved55_IRQHandler + .type Reserved55_IRQHandler, %function +Reserved55_IRQHandler: + ldr r0,=Reserved55_DriverIRQHandler + bx r0 + .size Reserved55_IRQHandler, . - Reserved55_IRQHandler + + .align 1 + .thumb_func + .weak Reserved56_IRQHandler + .type Reserved56_IRQHandler, %function +Reserved56_IRQHandler: + ldr r0,=Reserved56_DriverIRQHandler + bx r0 + .size Reserved56_IRQHandler, . - Reserved56_IRQHandler + + .align 1 + .thumb_func + .weak Reserved57_IRQHandler + .type Reserved57_IRQHandler, %function +Reserved57_IRQHandler: + ldr r0,=Reserved57_DriverIRQHandler + bx r0 + .size Reserved57_IRQHandler, . - Reserved57_IRQHandler + + .align 1 + .thumb_func + .weak Reserved58_IRQHandler + .type Reserved58_IRQHandler, %function +Reserved58_IRQHandler: + ldr r0,=Reserved58_DriverIRQHandler + bx r0 + .size Reserved58_IRQHandler, . - Reserved58_IRQHandler + + .align 1 + .thumb_func + .weak CAN0_IRQ0_IRQHandler + .type CAN0_IRQ0_IRQHandler, %function +CAN0_IRQ0_IRQHandler: + ldr r0,=CAN0_IRQ0_DriverIRQHandler + bx r0 + .size CAN0_IRQ0_IRQHandler, . - CAN0_IRQ0_IRQHandler + + .align 1 + .thumb_func + .weak CAN0_IRQ1_IRQHandler + .type CAN0_IRQ1_IRQHandler, %function +CAN0_IRQ1_IRQHandler: + ldr r0,=CAN0_IRQ1_DriverIRQHandler + bx r0 + .size CAN0_IRQ1_IRQHandler, . - CAN0_IRQ1_IRQHandler + + .align 1 + .thumb_func + .weak Reserved61_IRQHandler + .type Reserved61_IRQHandler, %function +Reserved61_IRQHandler: + ldr r0,=Reserved61_DriverIRQHandler + bx r0 + .size Reserved61_IRQHandler, . - Reserved61_IRQHandler + + .align 1 + .thumb_func + .weak USB1_PHY_IRQHandler + .type USB1_PHY_IRQHandler, %function +USB1_PHY_IRQHandler: + ldr r0,=USB1_PHY_DriverIRQHandler + bx r0 + .size USB1_PHY_IRQHandler, . - USB1_PHY_IRQHandler + + .align 1 + .thumb_func + .weak USB1_IRQHandler + .type USB1_IRQHandler, %function +USB1_IRQHandler: + ldr r0,=USB1_DriverIRQHandler + bx r0 + .size USB1_IRQHandler, . - USB1_IRQHandler + + .align 1 + .thumb_func + .weak USB1_NEEDCLK_IRQHandler + .type USB1_NEEDCLK_IRQHandler, %function +USB1_NEEDCLK_IRQHandler: + ldr r0,=USB1_NEEDCLK_DriverIRQHandler + bx r0 + .size USB1_NEEDCLK_IRQHandler, . - USB1_NEEDCLK_IRQHandler + + .align 1 + .thumb_func + .weak SEC_HYPERVISOR_CALL_IRQHandler + .type SEC_HYPERVISOR_CALL_IRQHandler, %function +SEC_HYPERVISOR_CALL_IRQHandler: + ldr r0,=SEC_HYPERVISOR_CALL_DriverIRQHandler + bx r0 + .size SEC_HYPERVISOR_CALL_IRQHandler, . - SEC_HYPERVISOR_CALL_IRQHandler + + .align 1 + .thumb_func + .weak SEC_GPIO_INT0_IRQ0_IRQHandler + .type SEC_GPIO_INT0_IRQ0_IRQHandler, %function +SEC_GPIO_INT0_IRQ0_IRQHandler: + ldr r0,=SEC_GPIO_INT0_IRQ0_DriverIRQHandler + bx r0 + .size SEC_GPIO_INT0_IRQ0_IRQHandler, . - SEC_GPIO_INT0_IRQ0_IRQHandler + + .align 1 + .thumb_func + .weak SEC_GPIO_INT0_IRQ1_IRQHandler + .type SEC_GPIO_INT0_IRQ1_IRQHandler, %function +SEC_GPIO_INT0_IRQ1_IRQHandler: + ldr r0,=SEC_GPIO_INT0_IRQ1_DriverIRQHandler + bx r0 + .size SEC_GPIO_INT0_IRQ1_IRQHandler, . - SEC_GPIO_INT0_IRQ1_IRQHandler + + .align 1 + .thumb_func + .weak PLU_IRQHandler + .type PLU_IRQHandler, %function +PLU_IRQHandler: + ldr r0,=PLU_DriverIRQHandler + bx r0 + .size PLU_IRQHandler, . - PLU_IRQHandler + + .align 1 + .thumb_func + .weak SEC_VIO_IRQHandler + .type SEC_VIO_IRQHandler, %function +SEC_VIO_IRQHandler: + ldr r0,=SEC_VIO_DriverIRQHandler + bx r0 + .size SEC_VIO_IRQHandler, . - SEC_VIO_IRQHandler + + .align 1 + .thumb_func + .weak HASHCRYPT_IRQHandler + .type HASHCRYPT_IRQHandler, %function +HASHCRYPT_IRQHandler: + ldr r0,=HASHCRYPT_DriverIRQHandler + bx r0 + .size HASHCRYPT_IRQHandler, . - HASHCRYPT_IRQHandler + + .align 1 + .thumb_func + .weak CASER_IRQHandler + .type CASER_IRQHandler, %function +CASER_IRQHandler: + ldr r0,=CASER_DriverIRQHandler + bx r0 + .size CASER_IRQHandler, . - CASER_IRQHandler + + .align 1 + .thumb_func + .weak PUF_IRQHandler + .type PUF_IRQHandler, %function +PUF_IRQHandler: + ldr r0,=PUF_DriverIRQHandler + bx r0 + .size PUF_IRQHandler, . - PUF_IRQHandler + + .align 1 + .thumb_func + .weak Reserved73_IRQHandler + .type Reserved73_IRQHandler, %function +Reserved73_IRQHandler: + ldr r0,=Reserved73_DriverIRQHandler + bx r0 + .size Reserved73_IRQHandler, . - Reserved73_IRQHandler + + .align 1 + .thumb_func + .weak DMA1_IRQHandler + .type DMA1_IRQHandler, %function +DMA1_IRQHandler: + ldr r0,=DMA1_DriverIRQHandler + bx r0 + .size DMA1_IRQHandler, . - DMA1_IRQHandler + + .align 1 + .thumb_func + .weak FLEXCOMM8_IRQHandler + .type FLEXCOMM8_IRQHandler, %function +FLEXCOMM8_IRQHandler: + ldr r0,=FLEXCOMM8_DriverIRQHandler + bx r0 + .size FLEXCOMM8_IRQHandler, . - FLEXCOMM8_IRQHandler + + .align 1 + .thumb_func + .weak CDOG_IRQHandler + .type CDOG_IRQHandler, %function +CDOG_IRQHandler: + ldr r0,=CDOG_DriverIRQHandler + bx r0 + .size CDOG_IRQHandler, . - CDOG_IRQHandler + +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_irq_handler handler_name + .weak \handler_name + .set \handler_name, DefaultISR + .endm +/* Exception Handlers */ + def_irq_handler MemManage_Handler + def_irq_handler BusFault_Handler + def_irq_handler UsageFault_Handler + def_irq_handler SecureFault_Handler + def_irq_handler DebugMon_Handler + def_irq_handler WDT_BOD_DriverIRQHandler /* Windowed watchdog timer, Brownout detect, Flash interrupt */ + def_irq_handler DMA0_DriverIRQHandler /* DMA0 controller */ + def_irq_handler GINT0_DriverIRQHandler /* GPIO group 0 */ + def_irq_handler GINT1_DriverIRQHandler /* GPIO group 1 */ + def_irq_handler PIN_INT0_DriverIRQHandler /* Pin interrupt 0 or pattern match engine slice 0 */ + def_irq_handler PIN_INT1_DriverIRQHandler /* Pin interrupt 1or pattern match engine slice 1 */ + def_irq_handler PIN_INT2_DriverIRQHandler /* Pin interrupt 2 or pattern match engine slice 2 */ + def_irq_handler PIN_INT3_DriverIRQHandler /* Pin interrupt 3 or pattern match engine slice 3 */ + def_irq_handler UTICK0_DriverIRQHandler /* Micro-tick Timer */ + def_irq_handler MRT0_DriverIRQHandler /* Multi-rate timer */ + def_irq_handler CTIMER0_DriverIRQHandler /* Standard counter/timer CTIMER0 */ + def_irq_handler CTIMER1_DriverIRQHandler /* Standard counter/timer CTIMER1 */ + def_irq_handler SCT0_DriverIRQHandler /* SCTimer/PWM */ + def_irq_handler CTIMER3_DriverIRQHandler /* Standard counter/timer CTIMER3 */ + def_irq_handler FLEXCOMM0_DriverIRQHandler /* Flexcomm Interface 0 (USART, SPI, I2C, I2S, FLEXCOMM) */ + def_irq_handler FLEXCOMM1_DriverIRQHandler /* Flexcomm Interface 1 (USART, SPI, I2C, I2S, FLEXCOMM) */ + def_irq_handler FLEXCOMM2_DriverIRQHandler /* Flexcomm Interface 2 (USART, SPI, I2C, I2S, FLEXCOMM) */ + def_irq_handler FLEXCOMM3_DriverIRQHandler /* Flexcomm Interface 3 (USART, SPI, I2C, I2S, FLEXCOMM) */ + def_irq_handler FLEXCOMM4_DriverIRQHandler /* Flexcomm Interface 4 (USART, SPI, I2C, I2S, FLEXCOMM) */ + def_irq_handler FLEXCOMM5_DriverIRQHandler /* Flexcomm Interface 5 (USART, SPI, I2C, I2S, FLEXCOMM) */ + def_irq_handler FLEXCOMM6_DriverIRQHandler /* Flexcomm Interface 6 (USART, SPI, I2C, I2S, FLEXCOMM) */ + def_irq_handler FLEXCOMM7_DriverIRQHandler /* Flexcomm Interface 7 (USART, SPI, I2C, I2S, FLEXCOMM) */ + def_irq_handler ADC0_DriverIRQHandler /* ADC0 */ + def_irq_handler Reserved39_DriverIRQHandler /* Reserved interrupt */ + def_irq_handler ACMP_DriverIRQHandler /* ACMP interrupts */ + def_irq_handler Reserved41_DriverIRQHandler /* Reserved interrupt */ + def_irq_handler Reserved42_DriverIRQHandler /* Reserved interrupt */ + def_irq_handler USB0_NEEDCLK_DriverIRQHandler /* USB Activity Wake-up Interrupt */ + def_irq_handler USB0_DriverIRQHandler /* USB device */ + def_irq_handler RTC_DriverIRQHandler /* RTC alarm and wake-up interrupts */ + def_irq_handler Reserved46_DriverIRQHandler /* Reserved interrupt */ + def_irq_handler Reserved47_DriverIRQHandler /* Reserved interrupt */ + def_irq_handler PIN_INT4_DriverIRQHandler /* Pin interrupt 4 or pattern match engine slice 4 int */ + def_irq_handler PIN_INT5_DriverIRQHandler /* Pin interrupt 5 or pattern match engine slice 5 int */ + def_irq_handler PIN_INT6_DriverIRQHandler /* Pin interrupt 6 or pattern match engine slice 6 int */ + def_irq_handler PIN_INT7_DriverIRQHandler /* Pin interrupt 7 or pattern match engine slice 7 int */ + def_irq_handler CTIMER2_DriverIRQHandler /* Standard counter/timer CTIMER2 */ + def_irq_handler CTIMER4_DriverIRQHandler /* Standard counter/timer CTIMER4 */ + def_irq_handler OS_EVENT_DriverIRQHandler /* OS_EVENT_TIMER and OS_EVENT_WAKEUP interrupts */ + def_irq_handler Reserved55_DriverIRQHandler /* Reserved interrupt */ + def_irq_handler Reserved56_DriverIRQHandler /* Reserved interrupt */ + def_irq_handler Reserved57_DriverIRQHandler /* Reserved interrupt */ + def_irq_handler Reserved58_DriverIRQHandler /* Reserved interrupt */ + def_irq_handler CAN0_IRQ0_DriverIRQHandler /* CAN0 interrupt0 */ + def_irq_handler CAN0_IRQ1_DriverIRQHandler /* CAN0 interrupt1 */ + def_irq_handler Reserved61_DriverIRQHandler /* Reserved interrupt */ + def_irq_handler USB1_PHY_DriverIRQHandler /* USB1_PHY */ + def_irq_handler USB1_DriverIRQHandler /* USB1 interrupt */ + def_irq_handler USB1_NEEDCLK_DriverIRQHandler /* USB1 activity */ + def_irq_handler SEC_HYPERVISOR_CALL_DriverIRQHandler /* SEC_HYPERVISOR_CALL interrupt */ + def_irq_handler SEC_GPIO_INT0_IRQ0_DriverIRQHandler /* SEC_GPIO_INT0_IRQ0 interrupt */ + def_irq_handler SEC_GPIO_INT0_IRQ1_DriverIRQHandler /* SEC_GPIO_INT0_IRQ1 interrupt */ + def_irq_handler PLU_DriverIRQHandler /* PLU interrupt */ + def_irq_handler SEC_VIO_DriverIRQHandler /* SEC_VIO interrupt */ + def_irq_handler HASHCRYPT_DriverIRQHandler /* SHA interrupt */ + def_irq_handler CASER_DriverIRQHandler /* CASPER interrupt */ + def_irq_handler PUF_DriverIRQHandler /* PUF interrupt */ + def_irq_handler Reserved73_DriverIRQHandler /* Reserved interrupt */ + def_irq_handler DMA1_DriverIRQHandler /* DMA1 interrupt */ + def_irq_handler FLEXCOMM8_DriverIRQHandler /* Flexcomm Interface 8 (SPI, , FLEXCOMM) */ + def_irq_handler CDOG_DriverIRQHandler /* CDOG interrupt */ + + .end diff --git a/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_anactrl.c b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_anactrl.c new file mode 100644 index 0000000000..68175b880a --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_anactrl.c @@ -0,0 +1,251 @@ +/* + * Copyright 2018-2021, NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#include "fsl_anactrl.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.anactrl" +#endif + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Get instance number for ANACTRL module. + * + * @param base ANACTRL peripheral base address + */ +static uint32_t ANACTRL_GetInstance(ANACTRL_Type *base); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Pointers to ANACTRL bases for each instance. */ +static ANACTRL_Type *const s_anactrlBases[] = ANACTRL_BASE_PTRS; +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Pointers to ANACTRL clocks for each instance. */ +static const clock_ip_name_t s_anactrlClocks[] = ANALOGCTRL_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/******************************************************************************* + * Code + ******************************************************************************/ +/*! + * brief Get the ANACTRL instance from peripheral base address. + * + * param base ANACTRL peripheral base address. + * return ANACTRL instance. + */ +static uint32_t ANACTRL_GetInstance(ANACTRL_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_anactrlBases); instance++) + { + if (s_anactrlBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_anactrlBases)); + + return instance; +} + +/*! + * brief Initializes the ANACTRL mode, the module's clock will be enabled by invoking this function. + * + * param base ANACTRL peripheral base address. + */ +void ANACTRL_Init(ANACTRL_Type *base) +{ + assert(NULL != base); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable the clock for ANACTRL instance. */ + CLOCK_EnableClock(s_anactrlClocks[ANACTRL_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/*! + * brief De-initializes ANACTRL module, the module's clock will be disabled by invoking this function. + * + * param base ANACTRL peripheral base address. + */ +void ANACTRL_Deinit(ANACTRL_Type *base) +{ + assert(NULL != base); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Disable the clock for ANACTRL instance. */ + CLOCK_DisableClock(s_anactrlClocks[ANACTRL_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/*! + * brief Configs the on-chip high-speed Free Running Oscillator(FRO192M), such as enabling/disabling 12 MHZ clock output + * and enable/disable 96MHZ clock output. + * + * param base ANACTRL peripheral base address. + * param config Pointer to FRO192M configuration structure. Refer to anactrl_fro192M_config_t structure. + */ +void ANACTRL_SetFro192M(ANACTRL_Type *base, const anactrl_fro192M_config_t *config) +{ + assert(NULL != config); + + uint32_t tmp32 = base->FRO192M_CTRL; + + tmp32 &= ~(ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_MASK | ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK); + + if (config->enable12MHzClk) + { + tmp32 |= ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_MASK; + } + if (config->enable96MHzClk) + { + tmp32 |= ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK; + } + + base->FRO192M_CTRL |= tmp32; +} + +/*! + * brief Gets the default configuration of FRO192M. + * The default values are: + * code + config->enable12MHzClk = true; + config->enable96MHzClk = false; + endcode + * param config Pointer to FRO192M configuration structure. Refer to anactrl_fro192M_config_t structure. + */ +void ANACTRL_GetDefaultFro192MConfig(anactrl_fro192M_config_t *config) +{ + assert(NULL != config); + + /* Initializes the configure structure to zero. */ + (void)memset(config, 0, sizeof(*config)); + + config->enable12MHzClk = true; + config->enable96MHzClk = false; +} + +/*! + * brief Configs the 32 MHz Crystal oscillator(High-speed crystal oscillator), such as enable/disable output to CPU + * system, and so on. + * + * param base ANACTRL peripheral base address. + * param config Pointer to XO32M configuration structure. Refer to anactrl_xo32M_config_t structure. + */ +void ANACTRL_SetXo32M(ANACTRL_Type *base, const anactrl_xo32M_config_t *config) +{ + assert(NULL != config); + + uint32_t tmp32 = base->XO32M_CTRL; + + tmp32 &= ~(ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_MASK | ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK); + + /* Set XO32M CTRL. */ +#if !(defined(FSL_FEATURE_ANACTRL_HAS_NO_ENABLE_PLL_USB_OUT_BIT_FIELD) && \ + FSL_FEATURE_ANACTRL_HAS_NO_ENABLE_PLL_USB_OUT_BIT_FIELD) + tmp32 &= ~ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_MASK; + if (config->enablePllUsbOutput) + { + tmp32 |= ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_MASK; + } +#endif /* FSL_FEATURE_ANACTRL_HAS_NO_ENABLE_PLL_USB_OUT_BIT_FIELD */ + + if (config->enableACBufferBypass) + { + tmp32 |= ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_MASK; + } + + if (config->enableSysCLkOutput) + { + tmp32 |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK; + } + base->XO32M_CTRL = tmp32; + +#if (defined(FSL_FEATURE_ANACTRL_HAS_XO32M_ADC_CLK_MODE_BIF_FIELD) && \ + FSL_FEATURE_ANACTRL_HAS_XO32M_ADC_CLK_MODE_BIF_FIELD) + if (config->enableADCOutput) + { + base->DUMMY_CTRL |= ANACTRL_DUMMY_CTRL_XO32M_ADC_CLK_MODE_MASK; + } + else + { + base->DUMMY_CTRL &= ~ANACTRL_DUMMY_CTRL_XO32M_ADC_CLK_MODE_MASK; + } +#endif /* FSL_FEATURE_ANACTRL_HAS_XO32M_ADC_CLK_MODE_BIF_FIELD */ +} + +/*! + * brief Gets the default configuration of XO32M. + * The default values are: + * code + config->enableSysCLkOutput = false; + config->enableACBufferBypass = false; + endcode + * param config Pointer to XO32M configuration structure. Refer to anactrl_xo32M_config_t structure. + */ +void ANACTRL_GetDefaultXo32MConfig(anactrl_xo32M_config_t *config) +{ + assert(NULL != config); + + /* Initializes the configure structure to zero. */ + (void)memset(config, 0, sizeof(*config)); + +#if !(defined(FSL_FEATURE_ANACTRL_HAS_NO_ENABLE_PLL_USB_OUT_BIT_FIELD) && \ + FSL_FEATURE_ANACTRL_HAS_NO_ENABLE_PLL_USB_OUT_BIT_FIELD) + config->enablePllUsbOutput = false; +#endif /* FSL_FEATURE_ANACTRL_HAS_NO_ENABLE_PLL_USB_OUT_BIT_FIELD */ + config->enableSysCLkOutput = false; + config->enableACBufferBypass = false; +#if (defined(FSL_FEATURE_ANACTRL_HAS_XO32M_ADC_CLK_MODE_BIF_FIELD) && \ + FSL_FEATURE_ANACTRL_HAS_XO32M_ADC_CLK_MODE_BIF_FIELD) + config->enableADCOutput = true; +#endif /* FSL_FEATURE_ANACTRL_HAS_XO32M_ADC_CLK_MODE_BIF_FIELD */ +} + +#if !(defined(FSL_FEATURE_ANACTRL_HAS_NO_FREQ_ME_CTRL) && FSL_FEATURE_ANACTRL_HAS_NO_FREQ_ME_CTRL) +/*! + * brief Measures the frequency of the target clock source. + * + * This function measures target frequency according to a accurate reference frequency.The formula is: + * Ftarget = (CAPVAL * Freference) / ((1<= 2U); + + uint32_t targetClkFreq = 0U; + uint32_t capval = 0U; + + /* Init a measurement cycle. */ + base->FREQ_ME_CTRL = ANACTRL_FREQ_ME_CTRL_PROG_MASK + ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE(scale); + while (ANACTRL_FREQ_ME_CTRL_PROG_MASK == (base->FREQ_ME_CTRL & ANACTRL_FREQ_ME_CTRL_PROG_MASK)) + { + } + + /* Calculate the target clock frequency. */ + capval = (base->FREQ_ME_CTRL & ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE_MASK); + targetClkFreq = (capval * refClkFreq) / ((1UL << scale) - 1UL); + + return targetClkFreq; +} +#endif /* FSL_FEATURE_ANACTRL_HAS_NO_FREQ_ME_CTRL */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_anactrl.h b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_anactrl.h new file mode 100644 index 0000000000..4ca845b5a9 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_anactrl.h @@ -0,0 +1,377 @@ +/* + * Copyright 2018-2021, NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __FSL_ANACTRL_H__ +#define __FSL_ANACTRL_H__ + +#include "fsl_common.h" + +/*! + * @addtogroup anactrl + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @brief ANACTRL driver version. */ +#define FSL_ANACTRL_DRIVER_VERSION (MAKE_VERSION(2, 3, 0)) /*!< Version 2.3.0. */` + +/*! + * @brief ANACTRL interrupt flags + */ +enum _anactrl_interrupt_flags +{ +#if (defined(FSL_FEATURE_ANACTRL_CONTROL_VDD_MAIN) && FSL_FEATURE_ANACTRL_CONTROL_VDD_MAIN) + kANACTRL_BodVDDMainFlag = ANACTRL_BOD_DCDC_INT_STATUS_BODVDDMAIN_STATUS_MASK, /*!< BOD VDDMAIN Interrupt status + before Interrupt Enable. */ + kANACTRL_BodVDDMainInterruptFlag = + ANACTRL_BOD_DCDC_INT_STATUS_BODVDDMAIN_INT_STATUS_MASK, /*!< BOD VDDMAIN Interrupt status + after Interrupt Enable. */ + kANACTRL_BodVDDMainPowerFlag = ANACTRL_BOD_DCDC_INT_STATUS_BODVDDMAIN_VAL_MASK, /*!< Current value of BOD VDDMAIN + power status output. */ +#else + kANACTRL_BodVbatFlag = ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_STATUS_MASK, /*!< BOD VBAT Interrupt status before + Interrupt Enable. */ + kANACTRL_BodVbatInterruptFlag = ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_INT_STATUS_MASK, /*!< BOD VBAT Interrupt status + after Interrupt Enable. */ + kANACTRL_BodVbatPowerFlag = ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_VAL_MASK, /*!< Current value of BOD VBAT power + status output. */ +#endif /* defined(FSL_FEATURE_ANACTRL_CONTROL_VDD_MAIN) && FSL_FEATURE_ANACTRL_CONTROL_VDD_MAIN */ + kANACTRL_BodCoreFlag = ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS_MASK, /*!< BOD CORE Interrupt status before + Interrupt Enable. */ + kANACTRL_BodCoreInterruptFlag = ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS_MASK, /*!< BOD CORE Interrupt status + after Interrupt Enable. */ + kANACTRL_BodCorePowerFlag = ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL_MASK, /*!< Current value of BOD CORE power + status output. */ + kANACTRL_DcdcFlag = ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS_MASK, /*!< DCDC Interrupt status before + Interrupt Enable. */ + kANACTRL_DcdcInterruptFlag = ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS_MASK, /*!< DCDC Interrupt status after + Interrupt Enable. */ + kANACTRL_DcdcPowerFlag = ANACTRL_BOD_DCDC_INT_STATUS_DCDC_VAL_MASK, /*!< Current value of DCDC power + status output. */ +}; + +/*! + * @brief ANACTRL interrupt control + */ +enum _anactrl_interrupt +{ +#if (defined(FSL_FEATURE_ANACTRL_CONTROL_VDD_MAIN) && FSL_FEATURE_ANACTRL_CONTROL_VDD_MAIN) + kANACTRL_BodVDDMainInterruptEnable = ANACTRL_BOD_DCDC_INT_CTRL_BODVDDMAIN_INT_ENABLE_MASK, /*!< BOD VDDMAIN + interrupt control. */ +#else + kANACTRL_BodVbatInterruptEnable = ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_ENABLE_MASK, /*!< BOD VBAT interrupt + control. */ +#endif /* defined(FSL_FEATURE_ANACTRL_CONTROL_VDD_MAIN) && FSL_FEATURE_ANACTRL_CONTROL_VDD_MAIN */ + kANACTRL_BodCoreInterruptEnable = ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE_MASK, /*!< BOD CORE interrupt + control. */ + kANACTRL_DcdcInterruptEnable = ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE_MASK, /*!< DCDC interrupt control. */ +}; + +/*! + * @brief ANACTRL status flags + */ +enum _anactrl_flags +{ + kANACTRL_FlashPowerDownFlag = ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN_MASK, /*!< Flash power-down status. */ + kANACTRL_FlashInitErrorFlag = ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR_MASK, /*!< Flash initialization + error status. */ +}; + +/*! + * @brief ANACTRL FRO192M and XO32M status flags + */ +enum _anactrl_osc_flags +{ + kANACTRL_OutputClkValidFlag = ANACTRL_FRO192M_STATUS_CLK_VALID_MASK, /*!< Output clock valid signal. */ + kANACTRL_CCOThresholdVoltageFlag = ANACTRL_FRO192M_STATUS_ATB_VCTRL_MASK, /*!< CCO threshold voltage detector + output (signal vcco_ok). */ + kANACTRL_XO32MOutputReadyFlag = ANACTRL_XO32M_STATUS_XO_READY_MASK << 16U, /*!< Indicates XO out + frequency statibilty. */ +}; + +/*! + * @brief Configuration for FRO192M + * + * This structure holds the configuration settings for the on-chip high-speed Free Running Oscillator. To initialize + * this structure to reasonable defaults, call the ANACTRL_GetDefaultFro192MConfig() function and pass a + * pointer to your config structure instance. + */ +typedef struct _anactrl_fro192M_config +{ + bool enable12MHzClk; /*!< Enable 12MHz clock. */ + bool enable96MHzClk; /*!< Enable 96MHz clock. */ +} anactrl_fro192M_config_t; + +/*! + * @brief Configuration for XO32M + * + * This structure holds the configuration settings for the 32 MHz crystal oscillator. To initialize this + * structure to reasonable defaults, call the ANACTRL_GetDefaultXo32MConfig() function and pass a + * pointer to your config structure instance. + */ +typedef struct _anactrl_xo32M_config +{ + bool enableACBufferBypass; /*!< Enable XO AC buffer bypass in pll and top level. */ +#if !(defined(FSL_FEATURE_ANACTRL_HAS_NO_ENABLE_PLL_USB_OUT_BIT_FIELD) && \ + FSL_FEATURE_ANACTRL_HAS_NO_ENABLE_PLL_USB_OUT_BIT_FIELD) + bool enablePllUsbOutput; /*!< Enable XO 32 MHz output to USB HS PLL. */ +#endif /* FSL_FEATURE_ANACTRL_HAS_NO_ENABLE_PLL_USB_OUT_BIT_FIELD */ + bool enableSysCLkOutput; /*!< Enable XO 32 MHz output to CPU system, SCT, and CLKOUT */ +#if (defined(FSL_FEATURE_ANACTRL_HAS_XO32M_ADC_CLK_MODE_BIF_FIELD) && \ + FSL_FEATURE_ANACTRL_HAS_XO32M_ADC_CLK_MODE_BIF_FIELD) + bool enableADCOutput; /*!< Enable High speed crystal oscillator output to ADC. */ +#endif /* FSL_FEATURE_ANACTRL_HAS_XO32M_ADC_CLK_MODE_BIF_FIELD */ +} anactrl_xo32M_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Initializes the ANACTRL mode, the module's clock will be enabled by invoking this function. + * + * @param base ANACTRL peripheral base address. + */ +void ANACTRL_Init(ANACTRL_Type *base); + +/*! + * @brief De-initializes ANACTRL module, the module's clock will be disabled by invoking this function. + * + * @param base ANACTRL peripheral base address. + */ +void ANACTRL_Deinit(ANACTRL_Type *base); +/* @} */ + +/*! + * @name Set oscillators + * @{ + */ + +/*! + * @brief Configs the on-chip high-speed Free Running Oscillator(FRO192M), such as enabling/disabling 12 MHZ clock + * output and enable/disable 96MHZ clock output. + * + * @param base ANACTRL peripheral base address. + * @param config Pointer to FRO192M configuration structure. Refer to @ref anactrl_fro192M_config_t structure. + */ +void ANACTRL_SetFro192M(ANACTRL_Type *base, const anactrl_fro192M_config_t *config); + +/*! + * @brief Gets the default configuration of FRO192M. + * The default values are: + * @code + config->enable12MHzClk = true; + config->enable96MHzClk = false; + @endcode + * @param config Pointer to FRO192M configuration structure. Refer to @ref anactrl_fro192M_config_t structure. + */ +void ANACTRL_GetDefaultFro192MConfig(anactrl_fro192M_config_t *config); + +/*! + * @brief Configs the 32 MHz Crystal oscillator(High-speed crystal oscillator), such as enable/disable output to CPU + * system, and so on. + * + * @param base ANACTRL peripheral base address. + * @param config Pointer to XO32M configuration structure. Refer to @ref anactrl_xo32M_config_t structure. + */ +void ANACTRL_SetXo32M(ANACTRL_Type *base, const anactrl_xo32M_config_t *config); + +/*! + * @brief Gets the default configuration of XO32M. + * The default values are: + * @code + config->enableSysCLkOutput = false; + config->enableACBufferBypass = false; + @endcode + * @param config Pointer to XO32M configuration structure. Refer to @ref anactrl_xo32M_config_t structure. + */ +void ANACTRL_GetDefaultXo32MConfig(anactrl_xo32M_config_t *config); + +/* @} */ + +#if !(defined(FSL_FEATURE_ANACTRL_HAS_NO_FREQ_ME_CTRL) && FSL_FEATURE_ANACTRL_HAS_NO_FREQ_ME_CTRL) +/*! + * @name Measure Frequency + * @{ + */ + +/*! + * @brief Measures the frequency of the target clock source. + * + * This function measures target frequency according to a accurate reference frequency.The formula is: + * Ftarget = (CAPVAL * Freference) / ((1<BOD_DCDC_INT_CTRL |= (0x15U & mask); +} + +/*! + * @brief Disables the ANACTRL interrupts. + * + * @param base ANACTRL peripheral base address. + * @param mask The interrupt mask. Refer to "_anactrl_interrupt" enumeration. + */ +static inline void ANACTRL_DisableInterrupts(ANACTRL_Type *base, uint32_t mask) +{ + base->BOD_DCDC_INT_CTRL &= ~(0x15U & mask); +} + +/*! + * @brief Clears the ANACTRL interrupts. + * + * @param base ANACTRL peripheral base address. + * @param mask The interrupt mask. Refer to "_anactrl_interrupt" enumeration. + */ +static inline void ANACTRL_ClearInterrupts(ANACTRL_Type *base, uint32_t mask) +{ + base->BOD_DCDC_INT_CTRL |= (uint32_t)(mask << 1UL); +} +/* @} */ + +/*! + * @name Status Interface + * @{ + */ + +/*! + * @brief Gets ANACTRL status flags. + * + * This function gets Analog control status flags. The flags are returned as the logical + * OR value of the enumerators @ref _anactrl_flags. To check for a specific status, + * compare the return value with enumerators in the @ref _anactrl_flags. + * For example, to check whether the flash is in power down mode: + * @code + * if (kANACTRL_FlashPowerDownFlag & ANACTRL_ANACTRL_GetStatusFlags(ANACTRL)) + * { + * ... + * } + * @endcode + * + * @param base ANACTRL peripheral base address. + * @return ANACTRL status flags which are given in the enumerators in the @ref _anactrl_flags. + */ +static inline uint32_t ANACTRL_GetStatusFlags(ANACTRL_Type *base) +{ + return base->ANALOG_CTRL_STATUS; +} + +/*! + * @brief Gets ANACTRL oscillators status flags. + * + * This function gets Anactrl oscillators status flags. The flags are returned as the logical + * OR value of the enumerators @ref _anactrl_osc_flags. To check for a specific status, + * compare the return value with enumerators in the @ref _anactrl_osc_flags. + * For example, to check whether the FRO192M clock output is valid: + * @code + * if (kANACTRL_OutputClkValidFlag & ANACTRL_ANACTRL_GetOscStatusFlags(ANACTRL)) + * { + * ... + * } + * @endcode + * + * @param base ANACTRL peripheral base address. + * @return ANACTRL oscillators status flags which are given in the enumerators in the @ref _anactrl_osc_flags. + */ +static inline uint32_t ANACTRL_GetOscStatusFlags(ANACTRL_Type *base) +{ + return (base->FRO192M_STATUS & 0xFFU) | ((base->XO32M_STATUS & 0xFFU) << 16U); +} + +/*! + * @brief Gets ANACTRL interrupt status flags. + * + * This function gets Anactrl interrupt status flags. The flags are returned as the logical + * OR value of the enumerators @ref _anactrl_interrupt_flags. To check for a specific status, + * compare the return value with enumerators in the @ref _anactrl_interrupt_flags. + * For example, to check whether the VBAT voltage level is above the threshold: + * @code + * if (kANACTRL_BodVbatPowerFlag & ANACTRL_ANACTRL_GetInterruptStatusFlags(ANACTRL)) + * { + * ... + * } + * @endcode + * + * @param base ANACTRL peripheral base address. + * @return ANACTRL oscillators status flags which are given in the enumerators in the @ref _anactrl_osc_flags. + */ +static inline uint32_t ANACTRL_GetInterruptStatusFlags(ANACTRL_Type *base) +{ + return base->BOD_DCDC_INT_STATUS & 0x1FFU; +} +/* @} */ + +#if (defined(FSL_FEATURE_ANACTRL_HAS_AUX_BIAS_REG) && (FSL_FEATURE_ANACTRL_HAS_AUX_BIAS_REG == 1U)) +/*! + * @brief Aux_Bias Control Interfaces + * @{ + */ + +/*! + * @brief Enables/disabless 1V reference voltage buffer. + * + * @param base ANACTRL peripheral base address. + * @param enable Used to enable or disable 1V reference voltage buffer. + */ +static inline void ANACTRL_EnableVref1V(ANACTRL_Type *base, bool enable) +{ + if (enable) + { + base->AUX_BIAS |= ANACTRL_AUX_BIAS_VREF1VENABLE_MASK; + } + else + { + base->AUX_BIAS &= ~ANACTRL_AUX_BIAS_VREF1VENABLE_MASK; + } +} + +/* @} */ +#endif /* defined(FSL_FEATURE_ANACTRL_HAS_AUX_BIAS_REG) */ + +#if defined(__cplusplus) +} +#endif + +/* @}*/ + +#endif /* __FSL_ANACTRL_H__ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_casper.c b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_casper.c new file mode 100644 index 0000000000..97c2613fd1 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_casper.c @@ -0,0 +1,3433 @@ +/* + * Copyright 2018-2021 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_casper.h" +#include /* ceil TODO check if really need it */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.casper" +#endif + +/* Recoding length for the secure scalar multiplication: + * Use n=256 and w=4 --> compute ciel(384/3) = 86 + 1 digits + * Use n=384 and w=4 --> compute ciel(384/3) = 128 + 1 digits + * Use n=521 and w=4 --> compute ciel(521/3) = 174 + 1 digits + */ + +/*!< Recoding length for the secure scalar multiplication */ +enum _casper_ecc_recode_len +{ + kCASPER_ECC_P256_recode_len = 87u, + kCASPER_ECC_P384_recode_len = 129u, + kCASPER_ECC_P521_recode_len = 175u, +}; + +enum _casper_ecc_N_bitlen +{ + kCASPER_ECC_P256_N_bitlen = 256u, + kCASPER_ECC_P384_N_bitlen = 384u, + kCASPER_ECC_P521_N_bitlen = 576u, +}; + +enum _casper_ecc_N_wordlen +{ + kCASPER_ECC_P256_wordlen = 256U / 32U, + kCASPER_ECC_P384_wordlen = 384u / 32U, + kCASPER_ECC_P521_wordlen = 576u / 32U, +}; + +#if defined(__GNUC__) +/* Enforce O1 optimize level, specifically to remove strict-aliasing option. + (-fno-strict-aliasing is required for this driver). */ +#pragma GCC push_options +#pragma GCC optimize("-O1") +#endif + +#if (defined(__CC_ARM) || defined(__ARMCC_VERSION)) +/* Enforce optimization off for clang, specifically to remove strict-aliasing option. +(-fno-strict-aliasing is required for this driver). */ +#pragma clang optimize off +#endif + +/* CASPER driver allows usage of 256, 384 and 521 ECC */ +#define CASPER_MAX_ECC_SIZE_WORDLEN (576u / 32U) +#define CASPER_RECODE_LENGTH_MAX 175 + +#define CASPER_RAM_BASE_NS (FSL_FEATURE_CASPER_RAM_BASE_ADDRESS) + +#if defined(FSL_FEATURE_CASPER_RAM_IS_INTERLEAVED) && FSL_FEATURE_CASPER_RAM_IS_INTERLEAVED +#define CASPER_RAM_OFFSET (FSL_FEATURE_CASPER_RAM_OFFSET) +#define INTERLEAVE(addr) \ + (((((((addr) >> 2U) & 0x00000001U) << CASPER_RAM_OFFSET) + (((addr) >> 3U) << 2U) + ((addr)&0x00000003U)) & \ + 0xFFFFU) | \ + s_casperRamBase) +#define DEINTERLEAVE(addr) INTERLEAVE(addr) +#define GET_WORD(addr) (*((uint32_t *)DEINTERLEAVE((uint32_t)(addr)))) +#define GET_DWORD(addr) (((uint64_t)GET_WORD(addr)) | (((uint64_t)GET_WORD(((uint32_t)(addr)) + 4U)) << 32U)) +#define SET_WORD(addr, value) *((uint32_t *)INTERLEAVE((uint32_t)(addr))) = ((uint32_t)(value)) +#define SET_DWORD(addr, value) \ + do \ + { \ + SET_WORD(addr, (uint32_t)(value & 0xFFFFFFFFU)); \ + SET_WORD(((uint32_t)(addr)) + 4U, (uint32_t)((value & 0xFFFFFFFF00000000U) >> 32U)); \ + } while (false) + +/* memcopy is always word aligned */ +/* interleaved to interleaved + static void CASPER_MEMCPY_I2I(void *dst, const void *src, size_t siz) + */ +#define CASPER_MEMCPY_I2I(dst, src, siz) \ + \ + { \ + uint32_t *dst32 = (uint32_t *)(dst); \ + const uint32_t *src32 = (const uint32_t *)(const uint32_t *)(src); \ + uint32_t i; \ + for (i = 0U; i < (siz) / 4U; i++) \ + { \ + SET_WORD(&dst32[i], GET_WORD(&src32[i])); \ + } \ + } + +/* interleaved to non-interleaved + static void CASPER_MEMCPY_I2N(void *dst, const void *src, size_t siz) + */ +#define CASPER_MEMCPY_I2N(dst, src, siz) \ + \ + { \ + uint32_t *dst32 = (uint32_t *)(dst); \ + const uint32_t *src32 = (const uint32_t *)(const uint32_t *)(src); \ + uint32_t i; \ + for (i = 0U; i < (siz) / 4U; i++) \ + { \ + dst32[i] = GET_WORD(&src32[i]); \ + } \ + } + +/* non-interleaved to interleaved + static void CASPER_MEMCPY_N2I(void *dst, const void *src, size_t siz) + */ +#define CASPER_MEMCPY_N2I(dst, src, siz) \ + \ + { \ + volatile uint32_t *dst32 = (uint32_t *)(dst); \ + const uint32_t *src32 = (const uint32_t *)(const uint32_t *)(src); \ + uint32_t i; \ + for (i = 0U; i < (siz) / 4U; i++) \ + { \ + SET_WORD(&dst32[i], src32[i]); \ + } \ + } +#else +#define GET_WORD(addr) (*((uint32_t *)(uint32_t)(addr))) +#define GET_DWORD(addr) (*((uint64_t *)(addr))) +#define SET_WORD(addr, value) *((uint32_t *)(uint32_t)(addr)) = ((uint32_t)(value)) +#define SET_DWORD(addr, value) *((uint64_t *)(addr)) = ((uint64_t)(value)) + +#define CASPER_MEMCPY_I2I(dst, src, siz) (void)memcpy(dst, src, siz) +#define CASPER_MEMCPY_I2N(dst, src, siz) (void)memcpy(dst, src, siz) +#define CASPER_MEMCPY_N2I(dst, src, siz) (void)memcpy(dst, src, siz) +#endif + +#define WORK_BUFF_MUL4 (N_wordlen_max * 4 + 2) /* ! working buffer is 4xN_wordlen to allow in place math */ +#define N_bytelen (N_wordlen * 4U) /* for memory copy and the like */ +#define N_dwordlen (unsigned)(N_wordlen / 2U) + +#define PreZeroW(i, w_out) \ + for ((i) = 0U; (i) < N_wordlen; (i) += 4U) \ + { \ + SET_WORD(&(w_out)[(i) + 0U], 0U); \ + SET_WORD(&(w_out)[(i) + 1U], 0U); \ + SET_WORD(&(w_out)[(i) + 2U], 0U); \ + SET_WORD(&(w_out)[(i) + 3U], 0U); \ + } /* unrolled partly */ +#define PreZeroW2up(i, w_out) \ + for (i = N_wordlen; i <= N_wordlen * 2U; i += 4U) \ + { \ + SET_WORD(&w_out[i + 0U], 0U); \ + SET_WORD(&w_out[i + 1U], 0U); \ + SET_WORD(&w_out[i + 2U], 0U); \ + SET_WORD(&w_out[i + 3U], 0U); \ + } /* unrolled partly */ + +/* Macros for the ECC component in Casper */ + +/* CASPER memory layout for ECC */ + +#define CASPER_MEM ((uint32_t *)msg_ret) + +/* Currently these macros work on 32-bit platforms */ + +#define add(c1, c0, a, b) \ + \ + do \ + { \ + uint32_t _t; \ + _t = a + b; \ + c1 = (uint32_t)(_t < a); \ + c0 = _t; \ + \ + } while (false) + +#define add_cout(carry, c, a, b) add((carry), (c), (a), (b)) + +#define add_cout_cin(carryout, c, a, b, carryin) \ + do \ + { \ + uint64_t _t = (uint64_t)(a) + (b) + (carryin); \ + (c) = (uint32_t)_t; \ + (carryout) = (uint32_t)(_t >> 32); \ + } while (false) + +#define sub_borrowout(borrow, c, a, b) \ + do \ + { \ + uint32_t _b = (uint32_t)((b) > (a)); \ + (c) = (a) - (b); \ + (borrow) = _b; \ + } while (false) + +#define sub_borrowin_borrowout(borrowout, c, a, b, borrowin) \ + do \ + { \ + uint32_t _t, _borrow1, _borrow2; \ + sub_borrowout(_borrow1, _t, (a), (b)); \ + sub_borrowout(_borrow2, (c), _t, (borrowin)); \ + (borrowout) = _borrow1 + _borrow2; \ + } while (false) + +#define sub_borrowout_1(borrow, c, a) \ + do \ + { \ + uint32_t _b = 0; \ + c = a - b; \ + borrow = _b; \ + } while (false) + +#define sub_borrowin_borrowout_1(borrowout, c, a, borrowin) \ + do \ + { \ + uint32_t _t, _borrow1, _borrow2; \ + sub_borrowout_1(_borrow1, _t, a); \ + sub_borrowout(_borrow2, c, _t, borrowin); \ + borrowout = _borrow1 + _borrow2; \ + } while (false) + +/* 32 x 32 --> 64-bit multiplication + * (c1,c0) = a * b + */ +#define mul(c1, c0, a, b) \ + \ + do \ + { \ + uint64_t __m; \ + __m = (uint64_t)a * (uint64_t)b; \ + c0 = (uint32_t)__m; \ + c1 = (uint32_t)(__m >> (uint64_t)32); \ + \ + } while (false) + +/* Multiply-and-accumulate + * (c1,c0) = a*b+c0 + */ +#define muladd(c1, c0, a, b) \ + \ + do \ + { \ + uint32_t __ma = c0; \ + mul(c1, c0, a, b); \ + c0 = c0 + __ma; \ + c1 = c1 + (c0 < __ma); \ + \ + } while (0) + +/* Multiply-and-accumulate-accumulate + * (c1,c0) = a*b+c0+c1 + */ +#define muladdadd(c1, c0, a, b) \ + \ + do \ + { \ + uint32_t __maa0 = c0, __maa1 = c1; \ + mul(c1, c0, a, b); \ + c0 = c0 + __maa0; \ + c1 = c1 + (c0 < __maa0); \ + c0 = c0 + __maa1; \ + c1 = c1 + (c0 < __maa1); \ + \ + } while (0) + +#define square_casper(c, a) multiply_casper(c, a, a) +#define sub_casper(c, a, b) CASPER_montsub(c, a, b, &CASPER_MEM[(N_wordlen + 4U)]) +#define add_casper(c, a, b) CASPER_montadd(c, a, b, &CASPER_MEM[(N_wordlen + 4U)]) +#define mul2_casper(c, a) add_casper(c, a, a) +#define half(c, a, b) CASPER_half(c, a, b) +/******************************************************************************* + * Variables + ******************************************************************************/ + +/* The model for this algo is that it can be implemented for a fixed size RSA key */ +/* for max speed. If this is made into a variable (to allow varying size), then */ +/* it will be slower by a bit. */ +/* The file is compiled with N_bitlen passed in as number of bits of the RSA key */ +/* #define N_bitlen 2048 */ +static size_t N_wordlen = 0U; /* ! number of words (e.g. 4096/32 is 128 words) */ + +static uint32_t s_casperRamBase = CASPER_RAM_BASE_NS; +static uint32_t *msg_ret = (uint32_t *)CASPER_RAM_BASE_NS; + +/* NISTp-256 = 2^256-2^224+2^192+2^96-1 */ +static uint32_t NISTp256[256 / 32u] = {0xffffffffU, 0xffffffffU, 0xffffffffU, 0x00000000, + 0x00000000, 0x00000000, 0x00000001, 0xffffffffU}; + +/* The cardinality of the curve E(F_p) */ +static uint32_t NISTp256_q[256 / 32u] = {0xfc632551U, 0xf3b9cac2U, 0xa7179e84U, 0xbce6faadU, + 0xffffffffU, 0xffffffffU, 0x00000000, 0xffffffffU}; + +/* R = 2^256 mod p, the value "1" in Montgomery form. */ +static uint32_t NISTr256[256 / 32u] = {0x00000001, 0x00000000, 0x00000000, 0xffffffffU, + 0xffffffffU, 0xffffffffU, 0xfffffffeU, 0x00000000}; + +static uint32_t Np256[2] = {1, 0}; + +/* NISTp-384 = 2^384 - 2^128 - 2^96 + 2^32 - 1 */ +static uint32_t NISTp384[384 / 32u] = {0xffffffffU, 0x00000000, 0x00000000, 0xffffffffU, 0xfffffffeU, 0xffffffffU, + 0xffffffffU, 0xffffffffU, 0xffffffffU, 0xffffffffU, 0xffffffffU, 0xffffffffU}; + +/* The cardinality of the curve E(F_p) */ +static uint32_t NISTp384_q[384 / 32u] = {0xccc52973U, 0xecec196aU, 0x48b0a77aU, 0x581a0db2U, 0xf4372ddfU, 0xc7634d81U, + 0xffffffffU, 0xffffffffU, 0xffffffffU, 0xffffffffU, 0xffffffffU, 0xffffffffU}; + +/* R = 2^256 mod p, the value "1" in Montgomery form. */ +static uint32_t NISTr384[384 / 32u] = {0x00000001, 0xffffffffU, 0xffffffffU, 0x00000000, 0x1, 0, 0, 0, 0, 0, 0, 0}; + +// -p^-1 mod 2^64 = 0x100000001 +static uint32_t Np384[2] = {1, 1}; + +/* NISTp-521 = 2^521 - 1 */ +static uint32_t NISTp521[576 / 32U] = {0xffffffffU, 0xffffffffU, 0xffffffffU, 0xffffffffU, 0xffffffffU, 0xffffffffU, + 0xffffffffU, 0xffffffffU, 0xffffffffU, 0xffffffffU, 0xffffffffU, 0xffffffffU, + 0xffffffffU, 0xffffffffU, 0xffffffffU, 0xffffffffU, 0x1ffU, 0}; + +/* The cardinality of the curve E(F_p) */ +static uint32_t NISTp521_q[576 / 32U] = {0x91386409U, 0xbb6fb71eU, 0x899c47aeU, 0x3bb5c9b8U, 0xf709a5d0U, 0x7fcc0148U, + 0xbf2f966bU, 0x51868783U, 0xfffffffaU, 0xffffffffU, 0xffffffffU, 0xffffffffU, + 0xffffffffU, 0xffffffffU, 0xffffffffU, 0xffffffffU, 0x1ffU, 0}; + +/* R = 2^576 mod p, the value "1" in Montgomery form. */ +static uint32_t NISTr521[576 / 32U] = {0, 0x800000, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; + +/* -p^-1 mod 2^64 = 1 */ +static uint32_t Np521[2] = {1, 0}; + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/* Convert a projective point (X1 : Y1 : Z1) + * to the affine point (X3, Y3) = (X1/Z1^2,Y1/Z1^3) + * The memory of (X3, Y3) and (X1 : Y1 : Z1) should not overlap + */ +void Jac_toAffine(uint32_t *X3, uint32_t *Y3, uint32_t *X1, uint32_t *Y1, uint32_t *Z1); + +/* Compute (X3 : Y3: Z3) = (X1: Y1: Z1) + (X2 : Y2 : Z2) + * where (X1: Y1: Z1) != (X2 : Y2 : Z2) + * (X3 : Y3: Z3) may be the same as one of the inputs. + */ +void Jac_addition(uint32_t *X3, + uint32_t *Y3, + uint32_t *Z3, + uint32_t *X1, + uint32_t *Y1, + uint32_t *Z1, + uint32_t *X2, + uint32_t *Y2, + uint32_t *Z2); + +/* Compute (X3 : Y3: Z3) = (X1: Y1: Z1) + (X2, Y2) + * where (X1: Y1: Z1) != (X2, Y2) + * (X3 : Y3: Z3) may not overlap with (X1: Y1: Z1). + * Source: 2004 Hankerson?Menezes?Vanstone, page 91. + */ +void Jac_add_affine( + uint32_t *X3, uint32_t *Y3, uint32_t *Z3, uint32_t *X1, uint32_t *Y1, uint32_t *Z1, uint32_t *X2, uint32_t *Y2); + +/* Point doubling from: 2004 Hankerson?Menezes?Vanstone, page 91. + * Compute (X3 : Y3: Z3) = (X1: Y1: Z1) + (X1 : Y1 : Z1) + * (X3 : Y3: Z3) may be the same as the input. + */ +void Jac_double(uint32_t *X3, uint32_t *Y3, uint32_t *Z3, uint32_t *X1, uint32_t *Y1, uint32_t *Z1); + +/* Constant time elliptic curve scalar multiplication. + * Source: https://eprint.iacr.org/2014/130.pdf + * when using w = 4. + * Computes (X3 : Y3 : Z3) = k * (X1, Y1) \in E(F_p) + * p is the prime used to define the finite field F_p + * q is the (prime) order of the curve + */ +void Jac_scalar_multiplication( + uint32_t *X3, uint32_t *Y3, uint32_t *Z3, uint32_t *X1, uint32_t *Y1, uint32_t *k, uint32_t *p, uint32_t *q); + +/* Compute the double scalar multiplication + * (X3 : Y3 : Z3) = k1 * (X1, Y1) + k2 * (X2, Y2) + * Using Shamir's trick and precomputing 16 points. + * This code is *not* constant time since this is used + * for verification only. + */ +void double_scalar_multiplication(uint32_t *X3, + uint32_t *Y3, + uint32_t *Z3, + uint32_t *X1, + uint32_t *Y1, + uint32_t *k1, + uint32_t *X2, + uint32_t *Y2, + uint32_t *k2); + +/* Compute inversion modulo NIST-p384 using Fermats little theorem. + * Using c = a^(p-2) = a^(-1) mod p. + * This computes the modular inversion if all arithmetic is "regular" + * modular arithmetic or computes automatically the Montgomery inverse + * if all arithmetic is Montgomery arithmetic. + */ +static void invert_mod_p384(uint32_t *c, uint32_t *a); + +/* Modular inversion for NIST-P256 */ +static void invert_mod_p256(uint32_t *c, uint32_t *a); + +/* Modular inversion for NIST-P521 */ +static void invert_mod_p521(uint32_t *c, uint32_t *a); + +// A and C do not need to be in Casper memory +static void toMontgomery_ECC_P256(uint32_t *C, uint32_t *A); +static void toMontgomery_ECC_P384(uint32_t *C, uint32_t *A); +static void toMontgomery_ECC_P521(uint32_t *C, uint32_t *A); + +static void CASPER_montsub(uint32_t *C, uint32_t *A, uint32_t *B, uint32_t *mod); +static void CASPER_montadd(uint32_t *C, uint32_t *A, uint32_t *B, uint32_t *mod); + +/* Compute c = a/2 mod p where b is scratch space. */ +static void CASPER_half(uint32_t *c, uint32_t *a, uint32_t *b); + +void CASPER_MEMCPY(void *dst, const void *src, size_t siz); + +static void multiply_casper(uint32_t w_out[], const uint32_t a[], const uint32_t b[]); + +static uint8_t int8abs(int8_t v); + +/* Constant time select c = a if m = 0 or + * c = b if m = 1 + * a, b, c are n words + */ +static void casper_select(uint32_t *c, uint32_t *a, uint32_t *b, int m, int n); + +/* Dumb n-limb addition of c=a+b, return carry. */ +static uint32_t add_n_1(uint32_t *c, uint32_t *a, uint32_t b, int n); + +#if 0 +/* Dumb n-limb addition of c=a+b, return carry. */ +static uint32_t add_n(uint32_t *c, uint32_t *a, uint32_t *b, int n); + +/* Dumb n-limb subtraction of c=a-b, return borrow. */ +static uint32_t sub_n_1(uint32_t *c, uint32_t *a, uint32_t b, int n); +#endif + +/* Dumb n-limb subtraction of c=a-b, return borrow. */ +static uint32_t sub_n(uint32_t *c, uint32_t *a, uint32_t *b, int n); + +int RSA_SignatureToPlaintextFast(const unsigned signature[N_wordlen_max], + const unsigned exp_pubkey, + const unsigned pubkey[N_wordlen_max], + unsigned MsgRet[WORK_BUFF_MUL4]); + +int RSA_MontSignatureToPlaintextFast(const unsigned mont_signature[N_wordlen_max], + const unsigned exp_pubkey, + const unsigned pubkey[N_wordlen_max], + unsigned MsgRet[WORK_BUFF_MUL4]); + +void MultprecMultiply(unsigned w_out[], const unsigned u[], const unsigned v[]); + +void MultprecGenNp64(const unsigned *Nmod, unsigned *np64_ret); +void MultprecMontPrepareX(unsigned Xmont_out[], const unsigned x[], const unsigned Rp[], const unsigned Nmod[]); +void MultprecModulo(unsigned r_out[], const unsigned v[], int top); +void MultprecCiosMul( + unsigned w_out[], const unsigned a[], const unsigned b[], const unsigned Nmod[], const unsigned *Np); +void MultprecMontCalcRp(unsigned Rp[], const unsigned exp_pubkey, const unsigned Nmod[]); + +static void MultprecCiosMul_ct( + uint32_t w_out[], const uint32_t a[], const uint32_t b[], const uint32_t Nmod[], const uint32_t *Np); + +static void MultprecCiosMul521_ct( + uint32_t w_out[], const uint32_t a[], const uint32_t b[], const uint32_t Nmod[], const uint32_t *Np); + +static void shiftrightSysram(uint32_t *z, uint32_t *x, uint32_t c); +static void shiftright(uint32_t *z, uint32_t *x, uint32_t c); +static void shiftleft(uint32_t *z, uint32_t *x, uint32_t c); + +/******************************************************************************* + * Code + ******************************************************************************/ + +__STATIC_FORCEINLINE uint32_t CA_MK_OFF(const void *addr) +{ + return ((uint32_t)(const uint32_t *)addr - s_casperRamBase); +} + +#if 1 +__STATIC_FORCEINLINE void Accel_done(void) +{ + register uint32_t status; + do + { + status = CASPER->STATUS; + } while (0U == (status & CASPER_STATUS_DONE_MASK)); +} + +__STATIC_FORCEINLINE void Accel_SetABCD_Addr(uint32_t ab, uint32_t cd) +{ + CASPER->CTRL0 = ab | (cd << 16); /* CDoffset << 16 | ABoffset */ +} + +__STATIC_FORCEINLINE void Accel_crypto_mul(uint32_t ctrl1) +{ + CASPER->CTRL1 = ctrl1; +} +#else +#include "intrinsics.h" +#define Accel_done() \ + { \ + register uint32_t status; \ + do \ + { \ + status = CASPER_Rd32b(CASPER_CP_STATUS); \ + } while (0 == (status & CASPER_STATUS_DONE_MASK)); \ + } +#if 0 +__STATIC_FORCEINLINE void Accel_done(void) +{ + register uint32_t status; + do + { + status = CASPER->STATUS; + } while (0 == (status & CASPER_STATUS_DONE_MASK)); +} +#endif +#define Accel_SetABCD_Addr(ab, cd) CASPER_Wr32b((uint32_t)ab | ((uint32_t)cd << 16), CASPER_CP_CTRL0); +#define Accel_crypto_mul(ctrl1) CASPER_Wr32b((uint32_t)ctrl1, CASPER_CP_CTRL1); +#endif + +__STATIC_FORCEINLINE uint32_t Accel_IterOpcodeResaddr(uint32_t iter, uint32_t opcode, uint32_t resAddr) +{ + return CASPER_CTRL1_ITER(iter) | CASPER_CTRL1_MODE(opcode) | (resAddr << 16); +} + +void CASPER_MEMCPY(void *dst, const void *src, size_t siz) +{ + bool bdst = + ((((uint32_t)(uint32_t *)dst) | 0x10000000u) >= ((unsigned)FSL_FEATURE_CASPER_RAM_BASE_ADDRESS | 0x10000000u) && + (((uint32_t)(uint32_t *)dst) | 0x10000000u) < + ((unsigned)FSL_FEATURE_CASPER_RAM_BASE_ADDRESS | 0x10000000u) + 8u * 1024u); + + bool bsrc = ((((uint32_t)(const uint32_t *)src) | 0x10000000u) >= + ((unsigned)FSL_FEATURE_CASPER_RAM_BASE_ADDRESS | 0x10000000u) && + (((uint32_t)(const uint32_t *)src) | 0x10000000u) < + ((unsigned)FSL_FEATURE_CASPER_RAM_BASE_ADDRESS | 0x10000000u) + 8u * 1024u); + + if (bdst && bsrc) + { + CASPER_MEMCPY_I2I(dst, src, siz); + } + else if (bdst && !bsrc) + { + CASPER_MEMCPY_N2I(dst, src, siz); + } + else if (!bdst && bsrc) + { + CASPER_MEMCPY_I2N(dst, src, siz); + } + else + { + (void)memcpy(dst, src, siz); + } +} + +/* Constant time select c = a if m = 0 or + * c = b if m = 1 + * a, b, c are n words + */ +static void casper_select(uint32_t *c, uint32_t *a, uint32_t *b, int m, int n) +{ + uint32_t m1 = 0U - (uint32_t)m, m2 = ~m1; + int i; + + for (i = 0; i < n; i++) + { + SET_WORD(&c[i], (GET_WORD(&a[i]) & m2) | (GET_WORD(&b[i]) & m1)); + } +} + +/* Compute R`, which is R mod N. This is done using subtraction */ +/* R has 1 in N_wordlen, but we do not fill it in since borrowed. */ +/* Exp-pubkey only used to optimize for exp=3 */ +void MultprecMontCalcRp(unsigned Rp[], const unsigned exp_pubkey, const unsigned Nmod[]) +{ + uint32_t i; + + /* R is 2^n where n is 1 bit longer than Nmod, so 1 followed by 32 or 64 0 words for example */ + /* Note that Nmod's upper most bit has to be 1 by definition, so one subtract is enough. We */ + /* do not set the 1 since it is "borrowed" so no point */ + PreZeroW(i, Rp); + Accel_SetABCD_Addr(CA_MK_OFF(Nmod), 0); + Accel_crypto_mul(Accel_IterOpcodeResaddr(N_dwordlen - 1U, (uint32_t)kCASPER_OpSub64, CA_MK_OFF(Rp))); + Accel_done(); + /* final borrow cannot happen since we know we started with a larger number */ +} + +/* MultprecMultiply - multiple w=u*v (per Knuth) */ +/* w_out is 2x the size of u and v */ +void MultprecMultiply(unsigned w_out[], const unsigned u[], const unsigned v[]) +{ + uint32_t i, j; + + /* Knuth 4.3.1 - Algorithm M */ + /* Compute w = u * v */ + /* u and v are N bits long in 32 bit word form */ + /* w is 2*N bits long in 32 bit word form */ + /* Note: We just multiply in place */ + + /* Step 1. Fill w[t-1:0] with 0s, the upper half will be written as we go */ + PreZeroW(i, w_out); + + /* We do 1st pass NOSUM so we do not have to 0 output */ + Accel_SetABCD_Addr(CA_MK_OFF(&v[0]), CA_MK_OFF(u)); + Accel_crypto_mul( + Accel_IterOpcodeResaddr(N_wordlen / 2U - 1U, (uint32_t)kCASPER_OpMul6464NoSum, CA_MK_OFF(&w_out[0]))); + Accel_done(); + /* Step 2. iterate over N words of v using j */ + for (j = 2U; j < N_wordlen; j += 2U) + { + /* Step 2b. Check for 0 on v word - skip if so since we 0ed already */ + /* Step 3. Iterate over N words of u using i - perform Multiply-accumulate */ + if (0U != (GET_WORD(&v[j])) || 0U != (GET_WORD(&v[j + 1U]))) + { + Accel_SetABCD_Addr(CA_MK_OFF(&v[j]), CA_MK_OFF(u)); + Accel_crypto_mul( + Accel_IterOpcodeResaddr(N_wordlen / 2U - 1U, (uint32_t)kCASPER_OpMul6464Sum, CA_MK_OFF(&w_out[j]))); + Accel_done(); + } + } +} + +/* MultprecModulo performs divide to get remainer as needed for RSA */ +/* This performs (q,r) = u/v, but we do not keep q */ +/* r_out is module (remainder) and is 2*N */ +/* u is in r_out (1st N) at start (passed in) */ +/* v is N long */ +void MultprecModulo(unsigned r_out[], const unsigned v[], int top) +{ + uint64_t u64; /* use 64 bit math mixed with 32 bit */ + unsigned u32; /* allows us to work on U in 32 bit */ + unsigned u_n, ul16, uh16, *u_shft; /* u_shft is because r_out is u initially */ + unsigned vl16, vh16, v_Nm1; + unsigned q_hat, r_hat, q_over; + unsigned borrow, carry; + uint32_t i; + int j, tmp; + + /* Knuth 4.3.1 - Algorithm D */ + /* Compute q = u / v giving remainder r = u mod v */ + /* -- we only want r, so we build qhat but do not store the Qs */ + /* v is N long, with u,q,r 2N long because u is slowly replavced by r. */ + /* We normalize/unnormlize per Knuth in the buffer (not copied) */ + + /* Step 1. Normalize value so MSb is in v[n-1]. Remember that v is */ + /* the public key - to call it a 2048 bit number, they cannot have 0 */ + /* in the MSb (or it would be less than 2048 bits) and so we know we */ + /* are normalized already. Therefore, u is effectively shifted already. */ + /* For u, we have it in r_out. u[n] holds any overflow */ + /* Since divide on CM3/4 is 32/32=32, we break into 16 bit halves, but */ + /* multiply can be 32x32=64. */ + u_n = 0; + u_shft = r_out; /* u (shifted) is in r_out */ + + v_Nm1 = GET_WORD(&v[N_wordlen - 1U]); /* MSw of public key */ + vl16 = v_Nm1 & 0xFFFFU; /* lower 16 */ + vh16 = v_Nm1 >> 16; /* upper 16 */ + /* Step 2. Iterate j from m-n down to 0 (M selected per Knuth as 2*N) */ + for (j = top; j >= 0; j--) + { + /* Step 3. estimate q_hat as (U[j+n]*B + U[j+n-1]) / V[n-1] */ + /* Note: using subset of Knuth algo since v is 1/2 len of u (which is */ + /* from multiply or x^2 leading into this). */ + u32 = u_n; /* pickup u4u3u2, knowing u4 is 0 */ + u64 = ((uint64_t)u_n << 32) | GET_WORD(&u_shft[(uint32_t)j + N_wordlen - 1U]); + ul16 = (unsigned int)(u64 & 0xFFFFU); /* lower 16 */ + uh16 = (unsigned int)((u64 >> 16) & 0xFFFFU); /* upper 16 */ + + /* we see if even possible (u large enough relative to v) */ + if ((u32 - v_Nm1) <= u32) + { + u32 -= v_Nm1; + q_over = 1; /* overflow from the sub */ + } + else + { + q_over = 0; + } + /* q_hat = u32 / vh16 -- is the upper partial value */ + /* estimate; if too much, then back down by 1 or 2 */ + q_hat = u32 / vh16; + r_hat = u32 - (q_hat * vh16); + /* see if Q is more than 16 bits or remainder is too large (over div) */ + if ((q_hat == 0x10000U) || ((q_hat * vl16) > ((r_hat << 16) | uh16))) + { + /* too much - undo a division */ + q_hat--; + r_hat += vh16; + /* check if still too much */ + if ((r_hat < 0x10000U) && ((q_hat * vl16) > ((r_hat << 16) | uh16))) + { + q_hat--; /* yes, so undo a 2nd */ + } + } + + /* compose u3u2uh16, then sub q_hat*v if OK */ + u64 = (((uint64_t)u32 << 16) | uh16) - ((uint64_t)q_hat * v_Nm1); + if (0U != (u64 >> 48)) + { + /* no, so add v back */ + u32 = (unsigned)(u64 + v_Nm1); + q_hat--; + } + else + { + u32 = (unsigned)u64; + } + tmp = (int32_t)(uint32_t)(q_hat << 16); /* quotient upper part */ + + /* divide lower part: q = u2uh16ul16 / v. */ + /* estimate and add back if over divdied */ + q_hat = u32 / vh16; + r_hat = u32 - (q_hat * vh16); + if ((q_hat == 0x10000U) || ((q_hat * vl16) > ((r_hat << 16) | ul16))) + { + /* too much - undo a division */ + q_hat--; + r_hat += vh16; + /* check if still too much */ + if ((r_hat < 0x10000U) && ((q_hat * vl16) > ((r_hat << 16) | ul16))) + { + q_hat--; /* yes, so undo a 2nd */ + } + } + + /* compose u2uh16ul16, then sub q_hat*v if OK */ + u64 = (((uint64_t)u32 << 16) | ul16) - ((uint64_t)q_hat * v_Nm1); + if (0U != (u64 >> 48)) + { + /* no, so add v back */ + r_hat = (unsigned)(u64 + v_Nm1); + q_hat--; + } + else + { + r_hat = (unsigned)u64; + } + q_hat |= (unsigned)tmp; /* other half of the quotient */ + while ((q_over != 0U) || ((uint64_t)q_hat * GET_WORD(&v[N_wordlen - 2U])) > + ((1ULL << 32) * r_hat) + (uint64_t)GET_WORD(&u_shft[(uint32_t)j + N_wordlen - 2U])) + { /* if Qhat>b, then reduce to b-1, then adjust up Rhat */ + q_hat--; + r_hat += v_Nm1; + if (r_hat < v_Nm1) + { + break; /* no overflow */ + /* else repeat since Rhat >= b */ + } + } + + /* Step 4. Multiply and subtract. We know the amount, */ + /* so we do the schoolboy math. Have to do on */ + /* the large value. */ + if (q_hat != 0U) + { + borrow = 0; + for (i = 0; i < N_wordlen; i++) + { + u64 = (uint64_t)q_hat * GET_WORD(&v[i]) + borrow; + borrow = (unsigned)(u64 >> 32); + if (GET_WORD(&u_shft[i + (unsigned)j]) < (unsigned)u64) + { + borrow++; /* carry the overflow */ + } + SET_WORD(&u_shft[i + (unsigned)j], GET_WORD(&u_shft[i + (unsigned)j]) - (unsigned)u64); + } + u_n -= borrow; /* overflow from shift left does not fit otherwise */ + } + + /* Store 5. (update Q - we don't), and add back V to remainder if we over-subtracted */ + /* That restores remainder to correct (we could only be off by 1) */ + /* This should happen very rarely. */ + if (u_n != 0U) + { + carry = 0; + for (i = 0; i < N_wordlen; i++) + { + SET_WORD(&u_shft[i + (unsigned)j], GET_WORD(&u_shft[i + (unsigned)j]) + carry); + carry = (GET_WORD(&u_shft[i + (unsigned)j]) < carry) ? 1U : 0U; + SET_WORD(&u_shft[i + (unsigned)j], GET_WORD(&u_shft[i + (unsigned)j]) + GET_WORD(&v[i])); + if (GET_WORD(&u_shft[i + (unsigned)j]) < GET_WORD(&v[i])) + { + carry++; + } + } + } + u_n = GET_WORD( + &u_shft[(uint32_t)j + N_wordlen - 1U]); /* hold upper part of u to catch overflow (to borrow from) */ + } + /* low N bits of r are valid as remainder */ +} + +/* We convert X into a Mont form number. Note length of arrays: */ +/* x is N_wordlen, Nmod is N_wordlen */ +/* Rp is N_wordlen (it is R` which is R mod N) */ +/* Xmont_out is N_wordlen*2+1 */ +void MultprecMontPrepareX(unsigned Xmont_out[], const unsigned x[], const unsigned Rp[], const unsigned Nmod[]) +{ + MultprecMultiply(Xmont_out, x, Rp); + MultprecModulo(Xmont_out, Nmod, (int32_t)N_wordlen); +} + +void MultprecGenNp64(const unsigned *Nmod, unsigned *np64_ret) /* only pass the low order double word */ +{ + uint64_t nprime, Nmod_0; + Nmod_0 = GET_WORD(&Nmod[0]) | ((uint64_t)GET_WORD(&Nmod[1]) << 32); + +#define COMP_NPN_1 ((2U - Nmod_0 * nprime) * nprime) /* computes N`*N0=1 mod 2^P where P is the partial built up */ + nprime = (((2U + Nmod_0) & 4U) << 1) + Nmod_0; /* mod 2^4 */ + nprime = COMP_NPN_1; + nprime = COMP_NPN_1; + nprime = COMP_NPN_1; + nprime = COMP_NPN_1; + /* 8 multiplies of uint64_t */ + *((uint64_t *)(uintptr_t)np64_ret) = (~0ULL - nprime) + 1ULL; +} + +/* CIOS Multiply. This is the Coarse Integrated form where the values are */ +/* multiplied and reduced for each step of "i". This uses less memory and */ +/* is faster as a result. Note that this is used to square as well as mul, */ +/* so not as fast as pure squaring could be. */ +void MultprecCiosMul( + unsigned w_out[], const unsigned a[], const unsigned b[], const unsigned Nmod[], const unsigned *Np) +{ + int j; + uint32_t i; + uint64_t *m64 = (uint64_t *)(uintptr_t)&msg_ret[kCASPER_RamOffset_M64]; + uint64_t Np64; + uint64_t carry; + uint64_t *a64, *b64, *w64, *N64; + + Np64 = *(uint64_t *)(uintptr_t)Np; + + a64 = (uint64_t *)(uintptr_t)a; + b64 = (uint64_t *)(uintptr_t)b; + w64 = (uint64_t *)(uintptr_t)w_out; + N64 = (uint64_t *)(uintptr_t)Nmod; + + if (a != NULL) + { /* if !a, we are reducing only */ + PreZeroW(i, w_out); + } + SET_DWORD(&w64[N_dwordlen], 0ULL); + SET_DWORD(&w64[N_dwordlen + 1U], 0ULL); + /* with accelerator */ + + /* loop i and then reduce after each j round */ + for (i = 0; i < N_dwordlen; i++) + { + /* Step 3. Iterate over N words of u using i - perform Multiply-accumulate */ + /* push-pull: we do a*b and then separately m*n (reduce) */ + if (a != NULL) + { /* if mul&reduce vs. reduce only */ + carry = GET_DWORD(&w64[N_dwordlen]); + Accel_SetABCD_Addr(CA_MK_OFF(&b64[i]), CA_MK_OFF(a64)); + Accel_crypto_mul( + Accel_IterOpcodeResaddr(N_dwordlen - 1U, (uint32_t)kCASPER_OpMul6464FullSum, CA_MK_OFF(w64))); + Accel_done(); + /* max carry is contained since ~0*~0=0xFFFE0001+0xFFFF=0xFFFF0000, */ + /* so max carry is 0xFFFF and 0xFFFF0000+0xFFFF=0xFFFFFFFF */ + /* accel took care of w_out[N_wordlen] & +1, so we just take care of the next double word if carry=1 */ + /* w64[N_dwordlen+1] = g_carry; */ + carry = (uint64_t)(GET_DWORD(&w64[N_dwordlen]) < carry); + SET_DWORD(&w64[N_dwordlen + 1U], carry); + } + SET_DWORD(&m64[0], GET_DWORD(&w64[0]) * Np64); /* prime for 1st; modulo a double-word */ + + /* we are reducing, so the 1st [0th] 64 bit value product is tossed, but we */ + /* need its carry. We let the accel do this separately - really need a mode to */ + /* do this "reduce" since it is natural */ + carry = GET_DWORD(&w64[N_dwordlen]); + Accel_SetABCD_Addr(CA_MK_OFF(m64), CA_MK_OFF(&N64[0])); + Accel_crypto_mul( + Accel_IterOpcodeResaddr(N_dwordlen - 1U, (uint32_t)kCASPER_OpMul6464FullSum, CA_MK_OFF(&w64[0]))); + Accel_done(); + carry = (uint64_t)(GET_DWORD(&w64[N_dwordlen]) < carry); + + Accel_SetABCD_Addr(CA_MK_OFF(&w64[1]), 0); + Accel_crypto_mul(Accel_IterOpcodeResaddr(N_dwordlen - 1U, (uint32_t)kCASPER_OpCopy, CA_MK_OFF(&w64[0]))); + + Accel_done(); + SET_DWORD(&w64[N_dwordlen], (GET_DWORD(&w64[N_dwordlen + 1U]) + carry)); + } + + /* now check if need to subtract Nmod */ + if (0U != (GET_WORD(&w_out[N_wordlen]))) + { + j = 1; /* we have to subtract for sure if carry up */ + } + else + { + j = 0; + for (i = N_wordlen - 1U; i > 0U; i--) + { + if (GET_WORD(&w_out[i]) != GET_WORD(&Nmod[i])) + { + j = (int32_t)(GET_WORD(&w_out[i]) > GET_WORD(&Nmod[i])); /* if larger sub */ + break; /* we would remove the break if worrying about side channel */ + } + } + } + if (0 == j) + { + return; /* Is smaller than Nmod, so done. */ + } + Accel_SetABCD_Addr(CA_MK_OFF(Nmod), 0); + Accel_crypto_mul(Accel_IterOpcodeResaddr(N_dwordlen - 1U, (uint32_t)kCASPER_OpSub64, CA_MK_OFF(w_out))); + Accel_done(); + /* last borrow is OK since we know it could only be <2N and */ +} + +/* RSA_MontSignatureToPlaintextFast: */ +/* MsgRet[] = Message return buffer - must be large enough to hold input and output (4*N+2) */ +/* exp_pubkey = the "e" that the value is raised to. Usually 3 or 0x10001. */ +/* signature = N bitpos len long "message" to process in Montgomery form - so saving conversion (divide) */ +/* pubkey = N bitpos len long public key to process signature with */ +/* returns: 0 */ +/* */ +/* Algo: compute M = signaturen^e mod public_key */ +/* where M is original plaintext, signature is signed value */ +/* note: e is usually either 0x3 or 0x10001 */ +int RSA_MontSignatureToPlaintextFast(const unsigned mont_signature[N_wordlen_max], + const unsigned exp_pubkey, + const unsigned pubkey[N_wordlen_max], + unsigned MsgRet[WORK_BUFF_MUL4]) +{ + int bidx = 0; + int bitpos; + unsigned np64[2]; + + /* MsgRet working area: */ + /* 0..N = RESULT, starting with S` */ + /* N..N*2 = S` and then working BASE during math. */ + /* N*2..N*4+2 = temp working area for Mont mul */ + + /* 1. Copy sig into MsgRet so we have one working result buffer */ + CASPER_MEMCPY_I2I((uint32_t *)(uintptr_t)&MsgRet[kCASPER_RamOffset_Result], + (const uint32_t *)(uintptr_t)mont_signature, N_bytelen); + MultprecGenNp64(pubkey, np64); /* Generate N` from LSW of N (LSW being lowest 64b word) */ + bitpos = (int8_t)(uint8_t)(31U - __CLZ(exp_pubkey)); /* count of bits after the left most 1 */ + while (--bitpos >= 0) + { + /* This operates on: */ + /* result = 1; */ + /* base = signature */ + /* loop while exponent bits from MSb to LSb */ + /* if (exp bit is 1) */ + /* result = result * base */ + /* base = base^2 */ + /* Because the MSb of exp is always 1 by definition, we can invert this a bit: */ + /* base = signature` */ + /* result = base; equivalent to result = 1*base from 1st pass, but now square is needed 1st */ + /* loop while exponent bits from MSb-1 to LSb */ + /* base = base^2 */ + /* if (exp bit is 1) */ + /* result = result * base */ + /* This ends up doing the same thing but skips two wasteful steps of multiplying by 1 and */ + /* a final squaring never used. */ + /* */ + /* Next we have the problem that CIOS mul needs a separate dest buffer. So, we bounce */ + /* base between base and temp, and likewise for result. */ + MultprecCiosMul(&MsgRet[(bidx != 0) ? kCASPER_RamOffset_Base : kCASPER_RamOffset_TempBase], + &MsgRet[(bidx != 0) ? kCASPER_RamOffset_TempBase : kCASPER_RamOffset_Base], + &MsgRet[(bidx != 0) ? kCASPER_RamOffset_TempBase : kCASPER_RamOffset_Base], pubkey, np64); + if (0U != (exp_pubkey & (uint32_t)(uint8_t)(1U << (uint8_t)bitpos))) /* where e is 1 */ + { + /* result has result, so we need to work into other temp area */ + MultprecCiosMul(&MsgRet[(bidx != 0) ? kCASPER_RamOffset_TempBase : kCASPER_RamOffset_Base], + &MsgRet[kCASPER_RamOffset_Result], + &MsgRet[(bidx != 0) ? kCASPER_RamOffset_Base : kCASPER_RamOffset_TempBase], pubkey, np64); + /* we have to copy back to result */ + + // CASPER_MEMCPY_I2I(&MsgRet[kCASPER_RamOffset_Result], + // &MsgRet[bidx ? kCASPER_RamOffset_TempBase : kCASPER_RamOffset_Base], N_bytelen); + } + else + { + bidx = (int32_t)(uint32_t) ~(unsigned)bidx; + } + } + + CASPER_MEMCPY_I2I((uint32_t *)(uintptr_t)&MsgRet[kCASPER_RamOffset_Result], + (uint32_t *)(uintptr_t)&MsgRet[(bidx != 0) ? kCASPER_RamOffset_TempBase : kCASPER_RamOffset_Base], + N_bytelen); + + /* final step is one more reduction to get back to normal form (ie. divide R out) */ + MultprecCiosMul(&MsgRet[kCASPER_RamOffset_Result], NULL, NULL, pubkey, np64); + return (0); /* always 0 */ +} + +/* RSA_SignatureToPlaintextFast: */ +/* MsgRet[] = Message return buffer - must be large enough to hold input and output (4*N+2) */ +/* exp_pubkey = the "e" that the value is raised to. Usually 3 or 0x10001. */ +/* signature = N bitpos len long "message" to process in normal form - so converted to Mont form */ +/* pubkey = N bitpos len long public key to process signature with */ +/* returns: 0 */ +/* */ +/* Algo: compute M = signaturen^e mod public_key */ +/* where M is original plaintext, signature is signed value */ +/* note: e is usually either 0x3 or 0x10001 */ +int RSA_SignatureToPlaintextFast(const unsigned signature[N_wordlen_max], + const unsigned exp_pubkey, + const unsigned pubkey[N_wordlen_max], + unsigned MsgRet[WORK_BUFF_MUL4]) +{ + /* MsgRet working area: */ + /* 0..N = RESULT, starting with S`; it is used for R` just during creation of S` */ + /* N..N*2 = S` and then working BASE during math. Note overflow beyond N*2 when making S` */ + /* N*2..N*4+2 = temp working area for Mont mul */ + + MultprecMontCalcRp(&MsgRet[kCASPER_RamOffset_Result], exp_pubkey, pubkey); /* calculate R` (=R mod N) */ + MultprecMontPrepareX(&MsgRet[kCASPER_RamOffset_Base], signature, &MsgRet[kCASPER_RamOffset_Result], + pubkey); /* X*R1` mod N */ + return (RSA_MontSignatureToPlaintextFast(&MsgRet[kCASPER_RamOffset_Base], exp_pubkey, pubkey, MsgRet)); +} + +/*! + * brief Performs modular exponentiation - (A^E) mod N. + * + * This function performs modular exponentiation. + * + * param base CASPER base address + * param signature first addend (in little endian format) + * param pubN modulus (in little endian format) + * param wordLen Size of pubN in bytes + * param pubE exponent + * param[out] plaintext Output array to store result of operation (in little endian format) + */ +void CASPER_ModExp( + CASPER_Type *base, const uint8_t *signature, const uint8_t *pubN, size_t wordLen, uint32_t pubE, uint8_t *plaintext) +{ +#define PK_LOC &msg_ret[kCASPER_RamOffset_Modulus] +#define SIG_LOC &msg_ret[(unsigned)kCASPER_RamOffset_Modulus + N_wordlen_max] + + N_wordlen = wordLen; /* set global variable for key length - used by RSA_SignatureToPlaintextFast() */ + CASPER_MEMCPY_N2I(PK_LOC, (const uint32_t *)(uintptr_t)pubN, N_bytelen); + CASPER_MEMCPY_N2I(SIG_LOC, (const uint32_t *)(uintptr_t)signature, N_bytelen); + (void)RSA_SignatureToPlaintextFast((const unsigned *)(uintptr_t)(SIG_LOC), pubE, + (const unsigned *)(uintptr_t)(PK_LOC), (unsigned int *)(uintptr_t)msg_ret); + + CASPER_MEMCPY_I2N((uint32_t *)(uintptr_t)plaintext, msg_ret, N_bytelen); +} + +/*! + * brief Enables clock and disables reset for CASPER peripheral. + * + * Enable clock and disable reset for CASPER. + * + * param base CASPER base address + */ +void CASPER_Init(CASPER_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +#if defined(CASPER_CLOCKS) + CLOCK_EnableClock(kCLOCK_Casper); +#endif +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +#if defined(CASPER_RSTS) + RESET_PeripheralReset(kCASPER_RST_SHIFT_RSTn); +#endif +#if defined(FSL_FEATURE_CASPER_RAM_HW_INTERLEAVE) && (FSL_FEATURE_CASPER_RAM_HW_INTERLEAVE > 0) + /* Enable hardware interleaving to RAMX0 and RAMX1 for CASPER */ + SYSCON->CASPER_CTRL = SYSCON_CASPER_CTRL_INTERLEAVE(1); +#endif /* FSL_FEATURE_CASPER_RAM_HW_INTERLEAVE */ + /* If Casper init is called with secure address, use secure addres also for accessing Casper RAM. */ + s_casperRamBase = (unsigned)CASPER_RAM_BASE_NS | ((uint32_t)base & 0x10000000u); + msg_ret = (uint32_t *)s_casperRamBase; +} + +/*! + * brief Disables clock for CASPER peripheral. + * + * Disable clock and enable reset. + * + * param base CASPER base address + */ +void CASPER_Deinit(CASPER_Type *base) +{ +#if defined(CASPER_RSTS) + RESET_SetPeripheralReset(kCASPER_RST_SHIFT_RSTn); +#endif +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +#if defined(CASPER_CLOCKS) + CLOCK_DisableClock(kCLOCK_Casper); +#endif +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/* New ECC code which uses Casper. */ + +/* Set the prime modulus mod in Casper memory. + */ +void CASPER_ecc_init(casper_algo_t curve) +{ + uint32_t *mod; + + if (curve == kCASPER_ECC_P256) + { + N_wordlen = 256U / 32U; + mod = NISTp256; + } + + if (curve == kCASPER_ECC_P384) + { + N_wordlen = 384U / 32U; + mod = NISTp384; + } + + if (curve == kCASPER_ECC_P521) + { + N_wordlen = 576U / 32U; + mod = NISTp521; + } + + CASPER_MEMCPY(&CASPER_MEM[(N_wordlen + 4U)], mod, N_wordlen * sizeof(uint32_t)); + uint8_t a[((CASPER_MAX_ECC_SIZE_WORDLEN + 4U) - CASPER_MAX_ECC_SIZE_WORDLEN) * sizeof(uint32_t)] = {0}; + CASPER_MEMCPY(&CASPER_MEM[(N_wordlen + 4U) + N_wordlen], a, ((N_wordlen + 4U) - N_wordlen) * sizeof(uint32_t)); +} + +void CASPER_ECC_equal(int *res, uint32_t *op1, uint32_t *op2) +{ + uint32_t a[CASPER_MAX_ECC_SIZE_WORDLEN] = {0}; + uint32_t b[CASPER_MAX_ECC_SIZE_WORDLEN] = {0}; + uint32_t c = 0; + CASPER_MEMCPY(a, op1, N_wordlen * sizeof(uint32_t)); + CASPER_MEMCPY(b, op2, N_wordlen * sizeof(uint32_t)); + + do + { + uint32_t _i; + c = (a[0] ^ b[0]); + for (_i = 1; _i < N_wordlen; _i++) + { + c |= (a[_i] ^ b[_i]); + } + } while (false); + + *res = (int32_t)c; +} + +void CASPER_ECC_equal_to_zero(int *res, uint32_t *op1) +{ + uint32_t a[CASPER_MAX_ECC_SIZE_WORDLEN] = {0}; + uint32_t c = 0; + CASPER_MEMCPY(a, op1, N_wordlen * sizeof(uint32_t)); + + do + { + uint32_t _i; + c = a[0]; + for (_i = 1; _i < N_wordlen; _i++) + { + c |= a[_i]; + } + } while (false); + + *res = (int32_t)c; +} + +void CASPER_ECC_SECP256R1_Mul( + CASPER_Type *base, uint32_t resX[8], uint32_t resY[8], uint32_t X[8], uint32_t Y[8], uint32_t scalar[8]) +{ + uint32_t X1[8] = {0}; + uint32_t Y1[8] = {0}; + toMontgomery_ECC_P256(X1, X); + toMontgomery_ECC_P256(Y1, Y); + + CASPER_MEMCPY( + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 0U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], + X1, (uint32_t)kCASPER_ECC_P256_wordlen * sizeof(uint32_t)); + CASPER_MEMCPY( + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 1U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], + Y1, (uint32_t)kCASPER_ECC_P256_wordlen * sizeof(uint32_t)); + + Jac_scalar_multiplication( + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 6U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 7U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 8U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 0U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 1U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], + scalar, NISTp256, NISTp256_q); + + Jac_toAffine( + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 3U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 4U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 6U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 7U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 8U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)]); + + /* Montgomery to Normal */ + /* X_normal = 1 * X_montgomery; Y_normal = 1 * Y_montgomery */ + uint32_t one[(kCASPER_ECC_P256_wordlen + 4U)] = {0x0}; + one[0] = 0x1u; + CASPER_MEMCPY( + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 0U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], + one, ((uint32_t)kCASPER_ECC_P256_wordlen + 4U) * sizeof(uint32_t)); + multiply_casper( + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 5U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 3U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 0U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)]); + multiply_casper( + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 6U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 4U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 0U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)]); + + /* copy out to result */ + CASPER_MEMCPY( + resX, + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 5U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], + (uint32_t)kCASPER_ECC_P256_wordlen * sizeof(uint32_t)); + CASPER_MEMCPY( + resY, + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 6U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], + (uint32_t)kCASPER_ECC_P256_wordlen * sizeof(uint32_t)); +} + +void CASPER_ECC_SECP256R1_MulAdd(CASPER_Type *base, + uint32_t resX[8], + uint32_t resY[8], + uint32_t X1[8], + uint32_t Y1[8], + uint32_t scalar1[8], + uint32_t X2[8], + uint32_t Y2[8], + uint32_t scalar2[8]) +{ + uint32_t zeroes[(kCASPER_ECC_P256_wordlen + 4U)] = {0}; + + CASPER_MEMCPY( + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 0U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], + X1, (uint32_t)kCASPER_ECC_P256_wordlen * sizeof(uint32_t)); + CASPER_MEMCPY( + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 1U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], + Y1, (uint32_t)kCASPER_ECC_P256_wordlen * sizeof(uint32_t)); + + CASPER_MEMCPY( + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], + X2, (uint32_t)kCASPER_ECC_P256_wordlen * sizeof(uint32_t)); + CASPER_MEMCPY( + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 3U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], + Y2, (uint32_t)kCASPER_ECC_P256_wordlen * sizeof(uint32_t)); + + toMontgomery_ECC_P256( + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 0U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 0U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)]); + toMontgomery_ECC_P256( + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 1U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 1U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)]); + toMontgomery_ECC_P256( + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)]); + toMontgomery_ECC_P256( + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 3U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 3U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)]); + + CASPER_MEMCPY( + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 4U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], + zeroes, ((uint32_t)kCASPER_ECC_P256_wordlen + 4U) * sizeof(uint32_t)); + CASPER_MEMCPY( + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 5U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], + zeroes, ((uint32_t)kCASPER_ECC_P256_wordlen + 4U) * sizeof(uint32_t)); + CASPER_MEMCPY( + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 6U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], + zeroes, ((uint32_t)kCASPER_ECC_P256_wordlen + 4U) * sizeof(uint32_t)); + double_scalar_multiplication( + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 4U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 5U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 6U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 0U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 1U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], + scalar1, + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 3U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], + scalar2); + + Jac_toAffine( + &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P256_wordlen + 80U) + 0U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], + &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P256_wordlen + 80U) + 1U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 4U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 5U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 6U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)]); + + uint32_t one[(kCASPER_ECC_P256_wordlen + 4U)] = {0x0}; + one[0] = 0x1u; + CASPER_MEMCPY( + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 0U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], + one, ((uint32_t)kCASPER_ECC_P256_wordlen + 4U) * sizeof(uint32_t)); + multiply_casper( + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 1U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], + &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P256_wordlen + 80U) + 0U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 0U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)]); + multiply_casper( + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], + &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P256_wordlen + 80U) + 1U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 0U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)]); + + CASPER_MEMCPY(resX, + (&CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + + 1U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)]), + (uint32_t)kCASPER_ECC_P256_wordlen * sizeof(uint32_t)); + CASPER_MEMCPY(resY, + (&CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + + 2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)]), + (uint32_t)kCASPER_ECC_P256_wordlen * sizeof(uint32_t)); +} + +void CASPER_ECC_SECP384R1_Mul( + CASPER_Type *base, uint32_t resX[12], uint32_t resY[12], uint32_t X[12], uint32_t Y[12], uint32_t scalar[12]) +{ + uint32_t X1[12] = {0}; + uint32_t Y1[12] = {0}; + toMontgomery_ECC_P384(X1, X); + toMontgomery_ECC_P384(Y1, Y); + + CASPER_MEMCPY( + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 0U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], + X1, (uint32_t)kCASPER_ECC_P384_wordlen * sizeof(uint32_t)); + CASPER_MEMCPY( + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 1U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], + Y1, (uint32_t)kCASPER_ECC_P384_wordlen * sizeof(uint32_t)); + + Jac_scalar_multiplication( + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 6U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 7U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 8U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 0U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 1U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], + scalar, NISTp384, NISTp384_q); + + Jac_toAffine( + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 3U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 4U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 6U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 7U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 8U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)]); + + /* Montgomery to Normal */ + /* X_normal = 1 * X_montgomery; Y_normal = 1 * Y_montgomery */ + uint32_t one[12] = {0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}; + CASPER_MEMCPY( + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 0U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], + one, (uint32_t)kCASPER_ECC_P384_wordlen * sizeof(uint32_t)); + multiply_casper( + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 5U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 3U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 0U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)]); + multiply_casper( + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 6U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 4U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 0U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)]); + + /* copy out to result */ + CASPER_MEMCPY( + resX, + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 5U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], + (uint32_t)kCASPER_ECC_P384_wordlen * sizeof(uint32_t)); + CASPER_MEMCPY( + resY, + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 6U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], + (uint32_t)kCASPER_ECC_P384_wordlen * sizeof(uint32_t)); +} + +void CASPER_ECC_SECP384R1_MulAdd(CASPER_Type *base, + uint32_t resX[12], + uint32_t resY[12], + uint32_t X1[12], + uint32_t Y1[12], + uint32_t scalar1[12], + uint32_t X2[12], + uint32_t Y2[12], + uint32_t scalar2[12]) +{ + CASPER_MEMCPY( + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 0U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], + X1, (uint32_t)kCASPER_ECC_P384_wordlen * sizeof(uint32_t)); + CASPER_MEMCPY( + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 1U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], + Y1, (uint32_t)kCASPER_ECC_P384_wordlen * sizeof(uint32_t)); + + CASPER_MEMCPY( + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], + X2, (uint32_t)kCASPER_ECC_P384_wordlen * sizeof(uint32_t)); + CASPER_MEMCPY( + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 3U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], + Y2, (uint32_t)kCASPER_ECC_P384_wordlen * sizeof(uint32_t)); + + toMontgomery_ECC_P384( + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 0U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 0U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)]); + toMontgomery_ECC_P384( + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 1U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 1U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)]); + toMontgomery_ECC_P384( + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)]); + toMontgomery_ECC_P384( + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 3U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 3U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)]); + + double_scalar_multiplication( + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 4U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 5U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 6U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 0U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 1U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], + scalar1, + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 3U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], + scalar2); + + Jac_toAffine( + &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P384_wordlen + 80U) + 0U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], + &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P384_wordlen + 80U) + 1U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 4U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 5U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 6U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)]); + + uint32_t one[12] = {0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}; + CASPER_MEMCPY( + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 0U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], + one, (uint32_t)kCASPER_ECC_P384_wordlen * sizeof(uint32_t)); + multiply_casper( + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 1U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], + &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P384_wordlen + 80U) + 0U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 0U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)]); + multiply_casper( + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], + &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P384_wordlen + 80U) + 1U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 0U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)]); + + CASPER_MEMCPY(resX, + (&CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + + 1U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)]), + (uint32_t)kCASPER_ECC_P384_wordlen * sizeof(uint32_t)); + CASPER_MEMCPY(resY, + (&CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + + 2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)]), + (uint32_t)kCASPER_ECC_P384_wordlen * sizeof(uint32_t)); +} + +void CASPER_ECC_SECP521R1_Mul( + CASPER_Type *base, uint32_t resX[18], uint32_t resY[18], uint32_t X[18], uint32_t Y[18], uint32_t scalar[18]) +{ + uint32_t X1[18] = {0}; + uint32_t Y1[18] = {0}; + toMontgomery_ECC_P521(X1, X); + toMontgomery_ECC_P521(Y1, Y); + + CASPER_MEMCPY( + &CASPER_MEM[(((uint32_t)kCASPER_ECC_P521_wordlen + 4U) + (1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U))) + + 0U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], + X1, (uint32_t)kCASPER_ECC_P521_wordlen * sizeof(uint32_t)); + CASPER_MEMCPY( + &CASPER_MEM[(((uint32_t)kCASPER_ECC_P521_wordlen + 4U) + (1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U))) + + 1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], + Y1, (uint32_t)kCASPER_ECC_P521_wordlen * sizeof(uint32_t)); + + Jac_scalar_multiplication( + &CASPER_MEM[(((uint32_t)kCASPER_ECC_P521_wordlen + 4U) + (1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U))) + + 6U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], + &CASPER_MEM[(((uint32_t)kCASPER_ECC_P521_wordlen + 4U) + (1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U))) + + 7U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], + &CASPER_MEM[(((uint32_t)kCASPER_ECC_P521_wordlen + 4U) + (1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U))) + + 8U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], + &CASPER_MEM[(((uint32_t)kCASPER_ECC_P521_wordlen + 4U) + (1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U))) + + 0U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], + &CASPER_MEM[(((uint32_t)kCASPER_ECC_P521_wordlen + 4U) + (1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U))) + + 1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], + scalar, NISTp521, NISTp521_q); + + Jac_toAffine( + &CASPER_MEM[(((uint32_t)kCASPER_ECC_P521_wordlen + 4U) + (1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U))) + + 3U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], + &CASPER_MEM[(((uint32_t)kCASPER_ECC_P521_wordlen + 4U) + (1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U))) + + 4U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], + &CASPER_MEM[(((uint32_t)kCASPER_ECC_P521_wordlen + 4U) + (1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U))) + + 6U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], + &CASPER_MEM[(((uint32_t)kCASPER_ECC_P521_wordlen + 4U) + (1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U))) + + 7U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], + &CASPER_MEM[(((uint32_t)kCASPER_ECC_P521_wordlen + 4U) + (1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U))) + + 8U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)]); + + /* Montgomery to Normal */ + /* X_normal = 1 * X_montgomery; Y_normal = 1 * Y_montgomery */ + uint32_t one[18] = {0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}; + CASPER_MEMCPY( + &CASPER_MEM[(((uint32_t)kCASPER_ECC_P521_wordlen + 4U) + (1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U))) + + 0U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], + one, (uint32_t)kCASPER_ECC_P521_wordlen * sizeof(uint32_t)); + multiply_casper( + &CASPER_MEM[(((uint32_t)kCASPER_ECC_P521_wordlen + 4U) + (1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U))) + + 5U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], + &CASPER_MEM[(((uint32_t)kCASPER_ECC_P521_wordlen + 4U) + (1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U))) + + 3U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], + &CASPER_MEM[(((uint32_t)kCASPER_ECC_P521_wordlen + 4U) + (1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U))) + + 0U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)]); + multiply_casper( + &CASPER_MEM[(((uint32_t)kCASPER_ECC_P521_wordlen + 4U) + (1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U))) + + 6U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], + &CASPER_MEM[(((uint32_t)kCASPER_ECC_P521_wordlen + 4U) + (1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U))) + + 4U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], + &CASPER_MEM[(((uint32_t)kCASPER_ECC_P521_wordlen + 4U) + (1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U))) + + 0U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)]); + + /* copy out to result */ + CASPER_MEMCPY( + resX, + &CASPER_MEM[(((uint32_t)kCASPER_ECC_P521_wordlen + 4U) + (1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U))) + + 5U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], + (uint32_t)kCASPER_ECC_P521_wordlen * sizeof(uint32_t)); + CASPER_MEMCPY( + resY, + &CASPER_MEM[(((uint32_t)kCASPER_ECC_P521_wordlen + 4U) + (1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U))) + + 6U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], + (uint32_t)kCASPER_ECC_P521_wordlen * sizeof(uint32_t)); +} + +void CASPER_ECC_SECP521R1_MulAdd(CASPER_Type *base, + uint32_t resX[18], + uint32_t resY[18], + uint32_t X1[18], + uint32_t Y1[18], + uint32_t scalar1[18], + uint32_t X2[18], + uint32_t Y2[18], + uint32_t scalar2[18]) +{ + uint32_t zeroes[(kCASPER_ECC_P521_wordlen + 4U)] = {0}; + + CASPER_MEMCPY( + &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 0U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], + X1, (uint32_t)kCASPER_ECC_P521_wordlen * sizeof(uint32_t)); + CASPER_MEMCPY( + &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], + Y1, (uint32_t)kCASPER_ECC_P521_wordlen * sizeof(uint32_t)); + + CASPER_MEMCPY( + &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 2U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], + X2, (uint32_t)kCASPER_ECC_P521_wordlen * sizeof(uint32_t)); + CASPER_MEMCPY( + &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 3U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], + Y2, (uint32_t)kCASPER_ECC_P521_wordlen * sizeof(uint32_t)); + + toMontgomery_ECC_P521( + &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 0U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], + &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 0U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)]); + toMontgomery_ECC_P521( + &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], + &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)]); + toMontgomery_ECC_P521( + &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 2U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], + &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 2U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)]); + toMontgomery_ECC_P521( + &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 3U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], + &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 3U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)]); + + CASPER_MEMCPY( + &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 4U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], + zeroes, ((uint32_t)kCASPER_ECC_P521_wordlen + 4U) * sizeof(uint32_t)); + CASPER_MEMCPY( + &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 5U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], + zeroes, ((uint32_t)kCASPER_ECC_P521_wordlen + 4U) * sizeof(uint32_t)); + CASPER_MEMCPY( + &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 6U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], + zeroes, ((uint32_t)kCASPER_ECC_P521_wordlen + 4U) * sizeof(uint32_t)); + double_scalar_multiplication( + &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 4U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], + &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 5U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], + &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 6U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], + &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 0U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], + &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], + scalar1, + &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 2U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], + &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 3U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], + scalar2); + + Jac_toAffine( + &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P521_wordlen + 80U) + 0U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], + &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P521_wordlen + 80U) + 1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], + &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 4U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], + &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 5U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], + &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 6U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)]); + + uint32_t one[(kCASPER_ECC_P521_wordlen + 4U)] = {0x0}; + one[0] = 0x1u; + CASPER_MEMCPY( + &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 0U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], + one, ((uint32_t)kCASPER_ECC_P521_wordlen + 4U) * sizeof(uint32_t)); + multiply_casper( + &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], + &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P521_wordlen + 80U) + 0U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], + &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 0U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)]); + multiply_casper( + &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + + 2U * ((uint32_t)(uint32_t)kCASPER_ECC_P521_wordlen + 4U)], + &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P521_wordlen + 80U) + 1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], + &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 0U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)]); + + CASPER_MEMCPY( + resX, + (&CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)]), + (uint32_t)kCASPER_ECC_P521_wordlen * sizeof(uint32_t)); + CASPER_MEMCPY( + resY, + (&CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 2U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)]), + (uint32_t)kCASPER_ECC_P521_wordlen * sizeof(uint32_t)); +} + +// CIOS Multiply. This is the Coarse Integrated form where the values are +// multiplied and reduced for each step of "i". This uses less memory and +// is faster as a result. Note that this is used to square as well as mul, +// so not as fast as pure squaring could be. +static void MultprecCiosMul_ct( + uint32_t w_out[], const uint32_t a[], const uint32_t b[], const uint32_t Nmod[], const uint32_t *Np) +{ + uint32_t j; + uint64_t *m64 = (uint64_t *)(uintptr_t)&msg_ret[kCASPER_RamOffset_M64]; + uint64_t Np64; + uint64_t carry; + uint64_t *a64, *b64, *w64, *N64; + uint32_t *T1 = &CASPER_MEM[0], borrow; + + Np64 = *(uint64_t *)(uintptr_t)Np; + + a64 = (uint64_t *)(uintptr_t)a; + b64 = (uint64_t *)(uintptr_t)b; + w64 = (uint64_t *)(uintptr_t)w_out; + N64 = (uint64_t *)(uintptr_t)Nmod; + + if (a != NULL) + { /* if !a, we are reducing only */ + PreZeroW(j, w_out); + } + SET_DWORD(&w64[N_dwordlen], 0ULL); + SET_DWORD(&w64[N_dwordlen + 1U], 0ULL); + /* with accelerator */ + + /* loop j and then reduce after each j round */ + for (j = 0; j < N_dwordlen; j++) + { + /* Step 3. Iterate over N words of u using j - perform Multiply-accumulate */ + /* push-pull: we do a*b and then separately m*n (reduce) */ + if (a != NULL) + { /* if mul&reduce vs. reduce only */ + carry = GET_DWORD(&w64[N_dwordlen]); + Accel_SetABCD_Addr(CA_MK_OFF(&b64[j]), CA_MK_OFF(a64)); + Accel_crypto_mul( + Accel_IterOpcodeResaddr(N_dwordlen - 1U, (uint32_t)kCASPER_OpMul6464FullSum, CA_MK_OFF(w64))); + Accel_done(); + /* max carry is contained since ~0*~0=0xFFFE0001+0xFFFF=0xFFFF0000, */ + /* so max carry is 0xFFFF and 0xFFFF0000+0xFFFF=0xFFFFFFFF */ + /* accel took care of w_out[N_wordlen] & +1, so we just take care of the next double word if carry=1 */ + /* w64[N_dwordlen+1] = g_carry; */ + carry = (uint64_t)(GET_DWORD(&w64[N_dwordlen]) < carry); + SET_DWORD(&w64[N_dwordlen + 1U], carry); + } + SET_DWORD(&m64[0], GET_DWORD(&w64[0]) * Np64); /* prime for 1st; modulo a double-word */ + + /* we are reducing, so the 1st [0th] 64 bit value product is tossed, but we */ + /* need its carry. We let the accel do this separately - really need a mode to */ + /* do this "reduce" since it is natural */ + carry = GET_DWORD(&w64[N_dwordlen]); + Accel_SetABCD_Addr(CA_MK_OFF(m64), CA_MK_OFF(&N64[0])); + Accel_crypto_mul( + Accel_IterOpcodeResaddr(N_dwordlen - 1U, (uint32_t)kCASPER_OpMul6464FullSum, CA_MK_OFF(&w64[0]))); + Accel_done(); + carry = (uint64_t)(GET_DWORD(&w64[N_dwordlen]) < carry); + + Accel_SetABCD_Addr(CA_MK_OFF(&w64[1]), 0); + Accel_crypto_mul(Accel_IterOpcodeResaddr(N_dwordlen - 1U, (uint32_t)kCASPER_OpCopy, CA_MK_OFF(&w64[0]))); + + Accel_done(); + SET_DWORD(&w64[N_dwordlen], (GET_DWORD(&w64[N_dwordlen + 1U]) + carry)); + } + + /* now check if need to subtract Nmod */ + CASPER_MEMCPY_I2I(T1, w_out, (N_wordlen + 1U) * sizeof(uint32_t)); + + /* Compute w = w - N */ + Accel_SetABCD_Addr(CA_MK_OFF(Nmod), 0); + Accel_crypto_mul(Accel_IterOpcodeResaddr(N_dwordlen, (uint32_t)kCASPER_OpSub64, CA_MK_OFF(w_out))); + Accel_done(); + + // if w_out > T1 then there was a borrow + borrow = (uint32_t)(GET_WORD(&((uint32_t *)w_out)[N_wordlen]) > GET_WORD(&T1[N_wordlen])); + + SET_WORD(&w_out[N_wordlen + 1U], 0); + SET_WORD(&w_out[N_wordlen], 0); + casper_select(w_out, w_out, T1, (int32_t)borrow, (int16_t)(uint16_t)N_wordlen); +} + +/* Compute C = A - B % mod + * Assumes all operand have two extra limbs to store carry. + */ +static void CASPER_montsub(uint32_t *C, uint32_t *A, uint32_t *B, uint32_t *mod) +{ + uint64_t *b64, *c64, *m64, *tmp; + int borrow; + + b64 = (uint64_t *)(uintptr_t)B; + c64 = (uint64_t *)(uintptr_t)C; + m64 = (uint64_t *)(uintptr_t)mod; + + tmp = (uint64_t *)(uintptr_t)&CASPER_MEM[0]; + + CASPER_MEMCPY(tmp, A, N_wordlen * sizeof(uint32_t)); + + /* Compute tmp = A - B. */ + Accel_SetABCD_Addr(CA_MK_OFF(b64), 0); + + Accel_crypto_mul(Accel_IterOpcodeResaddr(N_wordlen / 2U - 1U, (uint32_t)kCASPER_OpSub64, CA_MK_OFF(tmp))); + Accel_done(); + + borrow = (int32_t)((GET_WORD(&((uint32_t *)(uintptr_t)tmp)[N_wordlen - 1U])) > GET_WORD(&A[N_wordlen - 1U])); + CASPER_MEMCPY(c64, tmp, N_wordlen * sizeof(uint32_t)); + + /* Compute C = Mod + tmp */ + Accel_SetABCD_Addr(CA_MK_OFF(m64), 0); + Accel_crypto_mul(Accel_IterOpcodeResaddr(N_wordlen / 2U - 1U, (uint32_t)kCASPER_OpAdd64, CA_MK_OFF(c64))); + Accel_done(); + + casper_select(C, (uint32_t *)(uintptr_t)tmp, C, borrow, (int16_t)(uint16_t)N_wordlen); +} + +/* Compute C = A + B % mod + * Assumes all operand have two extra limbs to store carry. + */ +static void CASPER_montadd(uint32_t *C, uint32_t *A, uint32_t *B, uint32_t *mod) +{ + uint64_t *b64, *c64, *m64, *tmp; + int borrow; + + b64 = (uint64_t *)(uintptr_t)B; + c64 = (uint64_t *)(uintptr_t)C; + m64 = (uint64_t *)(uintptr_t)mod; + + tmp = (uint64_t *)(uintptr_t)&CASPER_MEM[0]; + + CASPER_MEMCPY(tmp, A, N_wordlen * sizeof(uint32_t)); + SET_DWORD(&tmp[N_wordlen / 2U], 0ULL); + SET_DWORD(&b64[N_wordlen / 2U], 0ULL); + SET_DWORD(&m64[N_wordlen / 2U], 0ULL); + + /* Compute tmp = A + B using one additonal double-length limb. */ + Accel_SetABCD_Addr(CA_MK_OFF(b64), 0); + + Accel_crypto_mul(Accel_IterOpcodeResaddr(N_wordlen / 2U, (uint32_t)kCASPER_OpAdd64, CA_MK_OFF(tmp))); + Accel_done(); + + CASPER_MEMCPY(c64, tmp, (N_wordlen + 2U) * sizeof(uint32_t)); + + /* Compute C = Mod - tmp */ + Accel_SetABCD_Addr(CA_MK_OFF(m64), 0); + Accel_crypto_mul(Accel_IterOpcodeResaddr(N_wordlen / 2U, (uint32_t)kCASPER_OpSub64, CA_MK_OFF(c64))); + Accel_done(); + + // borrow = g_carry; + borrow = (int32_t)(GET_WORD(&C[N_wordlen]) > GET_WORD(&(((uint32_t *)(uintptr_t)tmp)[N_wordlen]))); + casper_select(C, C, (uint32_t *)(uintptr_t)tmp, borrow, (int16_t)(uint16_t)N_wordlen); +} + +/* Compute c = a/2 mod p where b is scratch space. */ +static void CASPER_half(uint32_t *c, uint32_t *a, uint32_t *b) +{ + shiftright(b, a, 1U); /* Compute a/2 and (a+p)/2 */ + + /* Compute tmp = a + p using one additonal double-length limb. */ + CASPER_MEMCPY(c, a, N_wordlen * sizeof(uint32_t)); + SET_WORD(&c[N_wordlen], 0); + SET_WORD(&c[N_wordlen + 1U], 0U); + + Accel_SetABCD_Addr(CA_MK_OFF(((uint64_t *)(uintptr_t)&CASPER_MEM[(N_wordlen + 4U)])), 0); + Accel_crypto_mul( + Accel_IterOpcodeResaddr(N_wordlen / 2U, (uint32_t)kCASPER_OpAdd64, CA_MK_OFF(((uint64_t *)(uintptr_t)c)))); + Accel_done(); + + shiftright(c, c, 1U); + SET_WORD(&c[N_wordlen - 1U], GET_WORD(&c[N_wordlen - 1U]) | (GET_WORD(&c[N_wordlen]) << 31)); + SET_WORD(&c[N_wordlen], 0U); + casper_select(c, b, c, (int32_t)(uint32_t)(GET_WORD(&a[0]) & 1U), (int16_t)(uint16_t)(N_wordlen)); +} + +static uint32_t casper_get_word(uint32_t *addr) +{ + return GET_WORD(addr); +} + +/* Shift right by 1 <= c <= 31. z[] and x[] in system RAM, no interleaving macros used. */ +static void shiftrightSysram(uint32_t *z, uint32_t *x, uint32_t c) +{ + z[0] = (x[1] << (32U - (c))) | (x[0] >> (c)); + z[1] = (x[2] << (32U - (c))) | (x[1] >> (c)); + z[2] = (x[3] << (32U - (c))) | (x[2] >> (c)); + z[3] = (x[4] << (32U - (c))) | (x[3] >> (c)); + z[4] = (x[5] << (32U - (c))) | (x[4] >> (c)); + z[5] = (x[6] << (32U - (c))) | (x[5] >> (c)); + z[6] = (x[7] << (32U - (c))) | (x[6] >> (c)); + + if (N_wordlen == 18U) + { + z[7] = (x[8] << (32U - (c))) | (x[7] >> (c)); + z[8] = (x[9] << (32U - (c))) | (x[8] >> (c)); + z[9] = (x[10] << (32U - (c))) | (x[9] >> (c)); + z[10] = (x[11] << (32U - (c))) | (x[10] >> (c)); + z[11] = (x[12] << (32U - (c))) | (x[11] >> (c)); + z[12] = (x[13] << (32U - (c))) | (x[12] >> (c)); + z[13] = (x[14] << (32U - (c))) | (x[13] >> (c)); + z[14] = (x[15] << (32U - (c))) | (x[14] >> (c)); + z[15] = (x[16] << (32U - (c))) | (x[15] >> (c)); + z[16] = (x[17] << (32U - (c))) | (x[16] >> (c)); + z[17] = (x[17] >> (c)); + } + + if (N_wordlen == 12U) + { + z[7] = (x[8] << (32U - (c))) | (x[7] >> (c)); + z[8] = (x[9] << (32U - (c))) | (x[8] >> (c)); + z[9] = (x[10] << (32U - (c))) | (x[9] >> (c)); + z[10] = (x[11] << (32U - (c))) | (x[10] >> (c)); + z[11] = (x[11] >> (c)); + } + if (N_wordlen == 8U) + { + z[7] = (x[7] >> (c)); + } +} +/* Shift right by 1 <= c <= 31. */ +static void shiftright(uint32_t *z, uint32_t *x, uint32_t c) +{ + SET_WORD(&z[0], (GET_WORD(&x[1]) << (32U - (c))) | (GET_WORD(&x[0]) >> (c))); + SET_WORD(&z[1], (GET_WORD(&x[2]) << (32U - (c))) | (GET_WORD(&x[1]) >> (c))); + SET_WORD(&z[2], (GET_WORD(&x[3]) << (32U - (c))) | (GET_WORD(&x[2]) >> (c))); + SET_WORD(&z[3], (GET_WORD(&x[4]) << (32U - (c))) | (GET_WORD(&x[3]) >> (c))); + SET_WORD(&z[4], (GET_WORD(&x[5]) << (32U - (c))) | (GET_WORD(&x[4]) >> (c))); + SET_WORD(&z[5], (GET_WORD(&x[6]) << (32U - (c))) | (GET_WORD(&x[5]) >> (c))); + SET_WORD(&z[6], (GET_WORD(&x[7]) << (32U - (c))) | (GET_WORD(&x[6]) >> (c))); + + if (N_wordlen == 18U) + { + SET_WORD(&z[7], (GET_WORD(&x[8]) << (32U - (c))) | (GET_WORD(&x[7]) >> (c))); + SET_WORD(&z[8], (GET_WORD(&x[9]) << (32U - (c))) | (GET_WORD(&x[8]) >> (c))); + SET_WORD(&z[9], (GET_WORD(&x[10]) << (32U - (c))) | (GET_WORD(&x[9]) >> (c))); + SET_WORD(&z[10], (GET_WORD(&x[11]) << (32U - (c))) | (GET_WORD(&x[10]) >> (c))); + SET_WORD(&z[11], (GET_WORD(&x[12]) << (32U - (c))) | (GET_WORD(&x[11]) >> (c))); + SET_WORD(&z[12], (GET_WORD(&x[13]) << (32U - (c))) | (GET_WORD(&x[12]) >> (c))); + SET_WORD(&z[13], (GET_WORD(&x[14]) << (32U - (c))) | (GET_WORD(&x[13]) >> (c))); + SET_WORD(&z[14], (GET_WORD(&x[15]) << (32U - (c))) | (GET_WORD(&x[14]) >> (c))); + SET_WORD(&z[15], (GET_WORD(&x[16]) << (32U - (c))) | (GET_WORD(&x[15]) >> (c))); + SET_WORD(&z[16], (GET_WORD(&x[17]) << (32U - (c))) | (GET_WORD(&x[16]) >> (c))); + SET_WORD(&z[17], (GET_WORD(&x[17]) >> (c))); + } + if (N_wordlen == 12U) + { + SET_WORD(&z[7], (GET_WORD(&x[8]) << (32U - (c))) | (GET_WORD(&x[7]) >> (c))); + SET_WORD(&z[8], (GET_WORD(&x[9]) << (32U - (c))) | (GET_WORD(&x[8]) >> (c))); + SET_WORD(&z[9], (GET_WORD(&x[10]) << (32U - (c))) | (GET_WORD(&x[9]) >> (c))); + SET_WORD(&z[10], (GET_WORD(&x[11]) << (32U - (c))) | (GET_WORD(&x[10]) >> (c))); + SET_WORD(&z[11], (GET_WORD(&x[11]) >> (c))); + } + if (N_wordlen == 8U) + { + SET_WORD((&z[7]), (GET_WORD(&x[7]) >> (c))); + } +} +/* Shift left by 1 <= c <= 31. */ +static void shiftleft(uint32_t *z, uint32_t *x, uint32_t c) +{ + if (N_wordlen == 18U) + { + SET_WORD(&z[17], (GET_WORD(&x[17]) << (c)) | GET_WORD(&z[16]) >> (32U - (c))); + SET_WORD(&z[16], (GET_WORD(&x[16]) << (c)) | GET_WORD(&z[15]) >> (32U - (c))); + SET_WORD(&z[15], (GET_WORD(&x[15]) << (c)) | GET_WORD(&z[14]) >> (32U - (c))); + SET_WORD(&z[14], (GET_WORD(&x[14]) << (c)) | GET_WORD(&z[13]) >> (32U - (c))); + SET_WORD(&z[13], (GET_WORD(&x[13]) << (c)) | GET_WORD(&z[12]) >> (32U - (c))); + SET_WORD(&z[12], (GET_WORD(&x[12]) << (c)) | GET_WORD(&z[11]) >> (32U - (c))); + SET_WORD(&z[11], (GET_WORD(&x[11]) << (c)) | GET_WORD(&z[10]) >> (32U - (c))); + SET_WORD(&z[10], (GET_WORD(&x[10]) << (c)) | GET_WORD(&z[9]) >> (32U - (c))); + SET_WORD(&z[9], (GET_WORD(&x[9]) << (c)) | GET_WORD(&z[8]) >> (32U - (c))); + SET_WORD(&z[8], (GET_WORD(&x[8]) << (c)) | GET_WORD(&z[7]) >> (32U - (c))); + } + if (N_wordlen == 12U) + { + SET_WORD(&z[11], (GET_WORD(&x[11]) << (c)) | GET_WORD(&z[10]) >> (32U - (c))); + SET_WORD(&z[10], (GET_WORD(&x[10]) << (c)) | GET_WORD(&z[9]) >> (32U - (c))); + SET_WORD(&z[9], (GET_WORD(&x[9]) << (c)) | GET_WORD(&z[8]) >> (32U - (c))); + SET_WORD(&z[8], (GET_WORD(&x[8]) << (c)) | GET_WORD(&z[7]) >> (32U - (c))); + } + SET_WORD(&z[7], (GET_WORD(&x[7]) << (c)) | GET_WORD(&z[6]) >> (32U - (c))); + SET_WORD(&z[6], (GET_WORD(&x[6]) << (c)) | GET_WORD(&z[5]) >> (32U - (c))); + SET_WORD(&z[5], (GET_WORD(&x[5]) << (c)) | GET_WORD(&z[4]) >> (32U - (c))); + SET_WORD(&z[4], (GET_WORD(&x[4]) << (c)) | GET_WORD(&z[3]) >> (32U - (c))); + SET_WORD(&z[3], (GET_WORD(&x[3]) << (c)) | GET_WORD(&z[2]) >> (32U - (c))); + SET_WORD(&z[2], (GET_WORD(&x[2]) << (c)) | GET_WORD(&z[1]) >> (32U - (c))); + SET_WORD(&z[1], (GET_WORD(&x[1]) << (c)) | GET_WORD(&z[0]) >> (32U - (c))); + SET_WORD(&z[0], (GET_WORD(&x[0]) << (c))); +} + +static void multiply_casper(uint32_t w_out[], const uint32_t a[], const uint32_t b[]) +{ + uint32_t *Np; + + if (N_wordlen == 8U) + { + Np = Np256; + MultprecCiosMul_ct(w_out, a, b, &CASPER_MEM[(N_wordlen + 4U)], Np); + } + if (N_wordlen == 12U) + { + Np = Np384; + MultprecCiosMul_ct(w_out, a, b, &CASPER_MEM[(N_wordlen + 4U)], Np); + } + + if (N_wordlen == 18U) + { + Np = Np521; + MultprecCiosMul521_ct(w_out, a, b, &CASPER_MEM[(N_wordlen + 4U)], Np); + } +} +/* Convert a projective point (X1 : Y1 : Z1) + * to the affine point (X3, Y3) = (X1/Z1^2,Y1/Z1^3) + * The memory of (X3, Y3) and (X1 : Y1 : Z1) should not overlap + */ +void Jac_toAffine(uint32_t *X3, uint32_t *Y3, uint32_t *X1, uint32_t *Y1, uint32_t *Z1) +{ + uint32_t *T1, *T2; + + T1 = &CASPER_MEM[((2U * (N_wordlen + 4U)) + (9U * (N_wordlen + 4U))) + 0U * (N_wordlen + 4U)]; + T2 = &CASPER_MEM[((2U * (N_wordlen + 4U)) + (9U * (N_wordlen + 4U))) + 1U * (N_wordlen + 4U)]; + + square_casper(T1, Z1); // Z^2 + multiply_casper(T2, T1, Z1); // Z^3 + + // Montgomery inverse + if (N_wordlen == 8U) + { + invert_mod_p256(T1, T2); + } + + if (N_wordlen == 12U) + { + invert_mod_p384(T1, T2); + } + + if (N_wordlen == 18U) + { + invert_mod_p521(T1, T2); + } + + multiply_casper(Y3, Y1, T1); // Y3 = Y/Z^3 + multiply_casper(T2, T1, Z1); // Z^-2 + multiply_casper(X3, X1, T2); // X3 = X/Z^2 +} + +/* Compute (X3 : Y3: Z3) = (X1: Y1: Z1) + (X2 : Y2 : Z2) + * where (X1: Y1: Z1) != (X2 : Y2 : Z2) + * (X3 : Y3: Z3) may be the same as one of the inputs. + */ +void Jac_addition(uint32_t *X3, + uint32_t *Y3, + uint32_t *Z3, + uint32_t *X1, + uint32_t *Y1, + uint32_t *Z1, + uint32_t *X2, + uint32_t *Y2, + uint32_t *Z2) +{ + uint32_t *Z1Z1, *Z2Z2, *U1, *S1, *J, *H, *V, *t0, *t1; + int m1, m2; + + Z1Z1 = &CASPER_MEM[((2U * (N_wordlen + 4U)) + (9U * (N_wordlen + 4U))) + 0U * (N_wordlen + 4U)]; + Z2Z2 = &CASPER_MEM[((2U * (N_wordlen + 4U)) + (9U * (N_wordlen + 4U))) + 1U * (N_wordlen + 4U)]; + U1 = &CASPER_MEM[((2U * (N_wordlen + 4U)) + (9U * (N_wordlen + 4U))) + 2U * (N_wordlen + 4U)]; + S1 = &CASPER_MEM[((2U * (N_wordlen + 4U)) + (9U * (N_wordlen + 4U))) + 3U * (N_wordlen + 4U)]; + J = &CASPER_MEM[((2U * (N_wordlen + 4U)) + (9U * (N_wordlen + 4U))) + 4U * (N_wordlen + 4U)]; + H = &CASPER_MEM[((2U * (N_wordlen + 4U)) + (9U * (N_wordlen + 4U))) + 5U * (N_wordlen + 4U)]; + V = &CASPER_MEM[((2U * (N_wordlen + 4U)) + (9U * (N_wordlen + 4U))) + 6U * (N_wordlen + 4U)]; + t0 = &CASPER_MEM[((2U * (N_wordlen + 4U)) + (9U * (N_wordlen + 4U))) + 7U * (N_wordlen + 4U)]; + t1 = &CASPER_MEM[((2U * (N_wordlen + 4U)) + (9U * (N_wordlen + 4U))) + 8U * (N_wordlen + 4U)]; + + CASPER_ECC_equal_to_zero(&m1, Z1); + CASPER_ECC_equal_to_zero(&m2, Z2); + if (m1 == 0) + { + CASPER_MEMCPY(X3, X2, N_wordlen * 4U); + CASPER_MEMCPY(Y3, Y2, N_wordlen * 4U); + CASPER_MEMCPY(Z3, Z2, N_wordlen * 4U); + return; + } + if (m2 == 0) + { + CASPER_MEMCPY(X3, X1, N_wordlen * 4U); + CASPER_MEMCPY(Y3, Y1, N_wordlen * 4U); + CASPER_MEMCPY(Z3, Z1, N_wordlen * 4U); + return; + } + + square_casper(Z1Z1, Z1); + square_casper(Z2Z2, Z2); + multiply_casper(U1, X1, Z2Z2); + multiply_casper(H, X2, Z1Z1); /* if H equals U1 then X's are the same */ + multiply_casper(t0, Z2, Z2Z2); + multiply_casper(S1, Y1, t0); + multiply_casper(t0, Z1, Z1Z1); + multiply_casper(J, Y2, t0); /* if (S1 == J) then Y's are the same */ + + CASPER_ECC_equal(&m1, H, U1); /* If H and U1 match then the X-coordinates are the same. */ + CASPER_ECC_equal(&m2, S1, J); /* If S1 and J match then the Y-coordinates are the same. */ + if (m1 == 0) + { + if (m2 == 0) + { + Jac_double(X3, Y3, Z3, X1, Y1, Z1); + return; + } + /* else { + We work with the point at infinity. + The Z-coordinate will be set to zero in this function. + } */ + } + + sub_casper(H, H, U1); + mul2_casper(t0, H); + square_casper(t1, t0); + sub_casper(t0, J, S1); + multiply_casper(J, H, t1); + multiply_casper(V, U1, t1); + mul2_casper(U1, t0); + square_casper(t0, U1); + mul2_casper(t1, V); + sub_casper(t0, t0, J); + sub_casper(X3, t0, t1); + sub_casper(t0, V, X3); + multiply_casper(t1, S1, J); + mul2_casper(t1, t1); + multiply_casper(V, U1, t0); + sub_casper(Y3, V, t1); + add_casper(V, Z1, Z2); + square_casper(t1, V); + sub_casper(t1, t1, Z1Z1); + sub_casper(t1, t1, Z2Z2); + multiply_casper(Z3, t1, H); +} + +/* Compute (X3 : Y3: Z3) = (X1: Y1: Z1) + (X2, Y2) + * where (X1: Y1: Z1) != (X2, Y2) + * (X3 : Y3: Z3) may not overlap with (X1: Y1: Z1). + * Source: 2004 Hankerson?Menezes?Vanstone, page 91. + */ +void Jac_add_affine( + uint32_t *X3, uint32_t *Y3, uint32_t *Z3, uint32_t *X1, uint32_t *Y1, uint32_t *Z1, uint32_t *X2, uint32_t *Y2) +{ + uint32_t *T1, *T2, *T3, *T4, *T5; + uint32_t *ONE = NULL; + int m1, m2; + + if (N_wordlen == 8U) + { + ONE = NISTr256; + } + if (N_wordlen == 12U) + { + ONE = NISTr384; + } + if (N_wordlen == 18U) + { + ONE = NISTr521; + } + + T1 = &CASPER_MEM[((2U * (N_wordlen + 4U)) + (9U * (N_wordlen + 4U))) + 0U * (N_wordlen + 4U)]; + T2 = &CASPER_MEM[((2U * (N_wordlen + 4U)) + (9U * (N_wordlen + 4U))) + 1U * (N_wordlen + 4U)]; + T3 = &CASPER_MEM[((2U * (N_wordlen + 4U)) + (9U * (N_wordlen + 4U))) + 2U * (N_wordlen + 4U)]; + T4 = &CASPER_MEM[((2U * (N_wordlen + 4U)) + (9U * (N_wordlen + 4U))) + 3U * (N_wordlen + 4U)]; + T5 = &CASPER_MEM[((2U * (N_wordlen + 4U)) + (9U * (N_wordlen + 4U))) + 4U * (N_wordlen + 4U)]; + + CASPER_ECC_equal_to_zero(&m1, Z1); + if (m1 == 0) + { + CASPER_MEMCPY(X3, X2, N_wordlen * 4U); + CASPER_MEMCPY(Y3, Y2, N_wordlen * 4U); + CASPER_MEMCPY(Z3, ONE, N_wordlen * 4U); + return; + } + + CASPER_MEMCPY(T5, Z1, N_wordlen * sizeof(uint32_t)); + square_casper(T3, Z1); + multiply_casper(T2, T3, Z1); + multiply_casper(T4, T3, X2); + multiply_casper(T3, T2, Y2); + + CASPER_ECC_equal(&m1, T4, X1); + CASPER_ECC_equal(&m2, T3, Y1); + if (m1 == 0) + { + if (m2 == 0) + { + Jac_double(X3, Y3, Z3, X1, Y1, Z1); + return; + } + /* else { + We work with the point at infinity. + The Z-coordinate will be set to zero in this function. + } */ + } + + sub_casper(T1, T4, X1); + sub_casper(T2, T3, Y1); + multiply_casper(Z3, T5, T1); + square_casper(T3, T1); + multiply_casper(T4, T3, T1); + multiply_casper(T5, T3, X1); + mul2_casper(T1, T5); + square_casper(X3, T2); + sub_casper(X3, X3, T1); + sub_casper(X3, X3, T4); + sub_casper(T3, T5, X3); + multiply_casper(T1, T3, T2); + multiply_casper(T2, T4, Y1); + sub_casper(Y3, T1, T2); +} + +static uint32_t casper_get_word(uint32_t *addr); + +/* Point doubling from: 2004 Hankerson?Menezes?Vanstone, page 91. + * Compute (X3 : Y3: Z3) = (X1: Y1: Z1) + (X1 : Y1 : Z1) + * (X3 : Y3: Z3) may be the same as the input. + */ +void Jac_double(uint32_t *X3, uint32_t *Y3, uint32_t *Z3, uint32_t *X1, uint32_t *Y1, uint32_t *Z1) +{ + uint32_t *T1, *T2, *T3, *T4, *T5; + + T1 = &CASPER_MEM[((2U * (N_wordlen + 4U)) + (9U * (N_wordlen + 4U))) + 0U * (N_wordlen + 4U)]; + T2 = &CASPER_MEM[((2U * (N_wordlen + 4U)) + (9U * (N_wordlen + 4U))) + 1U * (N_wordlen + 4U)]; + T3 = &CASPER_MEM[((2U * (N_wordlen + 4U)) + (9U * (N_wordlen + 4U))) + 2U * (N_wordlen + 4U)]; + T4 = &CASPER_MEM[((2U * (N_wordlen + 4U)) + (9U * (N_wordlen + 4U))) + 3U * (N_wordlen + 4U)]; + T5 = &CASPER_MEM[((2U * (N_wordlen + 4U)) + (9U * (N_wordlen + 4U))) + 4U * (N_wordlen + 4U)]; + + square_casper(T1, Z1); + sub_casper(T3, X1, T1); + add_casper(T1, X1, T1); + multiply_casper(T4, T3, T1); + + mul2_casper(T3, T4); + + add_casper(T2, T3, T4); + + mul2_casper(Y3, Y1); + + CASPER_MEMCPY(T5, Z1, N_wordlen * sizeof(uint32_t)); + multiply_casper(Z3, Y3, T5); + + square_casper(T5, Y3); + + multiply_casper(T3, T5, X1); + + square_casper(Y3, T5); + + half(T5, Y3, T4); + + square_casper(X3, T2); + + mul2_casper(T1, T3); + + sub_casper(X3, X3, T1); + + sub_casper(T1, T3, X3); + + multiply_casper(T3, T1, T2); + + sub_casper(Y3, T3, T5); +} + +/* Recoding for a signed fixed window. + * Source: https://eprint.iacr.org/2014/130.pdf, Algorithm 6 + * Recode the n-bit integer k into ciel(log2(n)/(w-1)) digits + * where each digit is in + * { +/- 1, +/- 3, ..., +/- 2^(w-1)-1 } + * and put the result in c. + */ +static void recode(int8_t *c, uint32_t *k, int n, int w) +{ + int i, t; + uint32_t K[CASPER_MAX_ECC_SIZE_WORDLEN] = {0}; + (void)memcpy(K, k, (size_t)ceil(((double)n / 8.))); + t = (n + (w - 2)) / (w - 1); + for (i = 0; i < t; i++) + { + c[i] = (int8_t)(uint8_t)((K[0] & ((uint32_t)(uint32_t)(1UL << (uint32_t)w) - 1UL)) - + (uint32_t)(uint32_t)(1UL << ((uint32_t)w - 1UL))); + shiftrightSysram(K, K, (unsigned)w - 1U); + (void)add_n_1(K, K, (uint32_t)c[i] >> 31, (int16_t)(uint16_t)N_wordlen); + } + c[t] = (int8_t)K[0]; +} + +static uint32_t sub_n(uint32_t *c, uint32_t *a, uint32_t *b, int n) +{ + int i; + uint32_t borrow; + sub_borrowout(borrow, GET_WORD(&c[0]), a[0], GET_WORD(&b[0])); + for (i = 1; i < n; i++) + { + sub_borrowin_borrowout(borrow, GET_WORD(&c[i]), a[i], GET_WORD(&b[i]), borrow); + } + return borrow; +} + +#if 0 +/* Dumb n-limb subtraction of c=a-b, return borrow. */ +static uint32_t sub_n_1(uint32_t *c, uint32_t *a, uint32_t b, int n) { + int i; + uint32_t borrow; + sub_borrowout(borrow, c[0], a[0], b); + for (i = 1; i < n; i++) { + sub_borrowin_borrowout_1(borrow, c[i], a[i], borrow); + } + return borrow; +} + +/* Dumb n-limb addition of c=a+b, return carry. */ +static uint32_t add_n(uint32_t *c, uint32_t *a, uint32_t *b, int n) { + int i; + uint32_t carry; + add_cout(carry, c[0], a[0], b[0]); + for (i = 1; i < n; i++) { + add_cout_cin(carry, c[i], a[i], b[i], carry); + } + return carry; +} +#endif + +/* Dumb n-limb addition of c=a+b, return carry. */ +static uint32_t add_n_1(uint32_t *c, uint32_t *a, uint32_t b, int n) +{ + int i; + uint32_t carry; + add_cout(carry, c[0], a[0], b); + for (i = 1; i < n; i++) + { + add_cout_cin(carry, c[i], a[i], 0U, carry); + } + return carry; +} + +static uint8_t int8abs(int8_t v) +{ + return ((v < 0) ? ((uint8_t)-v) : ((uint8_t)v)); +} + +/* Constant time elliptic curve scalar multiplication. + * Source: https://eprint.iacr.org/2014/130.pdf + * when using w = 4. + * Computes (X3 : Y3 : Z3) = k * (X1, Y1) \in E(F_p) + * p is the prime used to define the finite field F_p + * q is the (prime) order of the curve + */ +void Jac_scalar_multiplication( + uint32_t *X3, uint32_t *Y3, uint32_t *Z3, uint32_t *X1, uint32_t *Y1, uint32_t *k, uint32_t *p, uint32_t *q) +{ + uint32_t *scalar, *M, *X, *Y, *Z, *mem; + uint32_t *ONE = NULL; + int i, sign, odd; + uint8_t index; + size_t recodeLength = 175u; + size_t bitlen = 0u; + int8_t rec[CASPER_RECODE_LENGTH_MAX] = {0}; + + if (N_wordlen == 8U) + { + recodeLength = (size_t)kCASPER_ECC_P256_recode_len; + bitlen = (size_t)kCASPER_ECC_P256_N_bitlen; + ONE = NISTr256; + } + + if (N_wordlen == 12U) + { + recodeLength = (size_t)kCASPER_ECC_P384_recode_len; + bitlen = (size_t)kCASPER_ECC_P384_N_bitlen; + ONE = NISTr384; + } + + if (N_wordlen == 18U) + { + recodeLength = (size_t)kCASPER_ECC_P521_recode_len; + bitlen = (size_t)521U; + ONE = NISTr521; + } + + /* Point to the start of the LUT table space. */ + mem = &CASPER_MEM[(20U * N_wordlen + 80U)]; + + scalar = &CASPER_MEM[(20U * N_wordlen + 80U) + 12U * (N_wordlen + 4U)]; + X = &CASPER_MEM[(20U * N_wordlen + 80U) + 13U * (N_wordlen + 4U)]; + Y = &CASPER_MEM[(20U * N_wordlen + 80U) + 14U * (N_wordlen + 4U)]; + Z = &CASPER_MEM[(20U * N_wordlen + 80U) + 15U * (N_wordlen + 4U)]; + M = &CASPER_MEM[(20U * N_wordlen + 80U) + 16U * (N_wordlen + 4U)]; + + /* Point to memory the recoded scalar. + */ + CASPER_MEMCPY(scalar, k, sizeof(uint32_t) * N_wordlen); + +/* Precomputation: compute 1*P, 3*P, 5*P, and 7*P */ +#define FSL_CASPER_LUT(P, x) (mem + (3U * ((P)-1U) / 2U + (x)) * (N_wordlen + 4U)) + + /* Set 1*P */ + CASPER_MEMCPY(Z3, ONE, N_wordlen * sizeof(uint32_t)); + CASPER_MEMCPY(FSL_CASPER_LUT(1U, 0U), X1, N_wordlen * sizeof(uint32_t)); + CASPER_MEMCPY(FSL_CASPER_LUT(1U, 1U), Y1, N_wordlen * sizeof(uint32_t)); + CASPER_MEMCPY(FSL_CASPER_LUT(1U, 2U), Z3, N_wordlen * sizeof(uint32_t)); + + /* Compute 2*P */ + Jac_double(X3, Y3, Z3, X1, Y1, Z3); + + /* Compute 3*P = 2P + P */ + Jac_add_affine(FSL_CASPER_LUT(3U, 0U), FSL_CASPER_LUT(3U, 1U), FSL_CASPER_LUT(3U, 2U), X3, Y3, Z3, X1, Y1); + + /* Compute 5*P = 3P + 2P */ + Jac_addition(FSL_CASPER_LUT(5U, 0U), FSL_CASPER_LUT(5U, 1U), FSL_CASPER_LUT(5U, 2U), FSL_CASPER_LUT(3U, 0U), + FSL_CASPER_LUT(3U, 1U), FSL_CASPER_LUT(3U, 2U), X3, Y3, Z3); + + /* Compute 7*P = 5P + 2P */ + Jac_addition(FSL_CASPER_LUT(7U, 0U), FSL_CASPER_LUT(7U, 1U), FSL_CASPER_LUT(7U, 2U), FSL_CASPER_LUT(5U, 0U), + FSL_CASPER_LUT(5U, 1U), FSL_CASPER_LUT(5U, 2U), X3, Y3, Z3); + + /* Recode the scalar */ + odd = (int32_t)((uint32_t)(casper_get_word(&scalar[0]) & 1U)); + (void)sub_n(M, q, scalar, (int16_t)(uint16_t)N_wordlen); // todo!!! + casper_select(scalar, M, scalar, odd, (int16_t)(uint16_t)N_wordlen); + + /* Use n=384 and w=4 --> compute ciel(384/3) = 128 + 1 digits */ + uint32_t scalarSysram[CASPER_MAX_ECC_SIZE_WORDLEN]; + CASPER_MEMCPY(scalarSysram, scalar, /*CASPER_*/ N_wordlen * sizeof(uint32_t)); + recode(rec, scalarSysram, (int32_t)bitlen, 4); + + /* Set the first value. */ + index = int8abs(rec[recodeLength - 1U]); + sign = (int32_t)(uint32_t)(uint8_t)(((uint8_t)rec[recodeLength - 1U]) >> 7); + + CASPER_MEMCPY(X3, FSL_CASPER_LUT((uint32_t)index, 0U), N_wordlen * sizeof(uint32_t)); + CASPER_MEMCPY(Y3, FSL_CASPER_LUT((uint32_t)index, 1U), N_wordlen * sizeof(uint32_t)); + CASPER_MEMCPY(Z3, FSL_CASPER_LUT((uint32_t)index, 2U), N_wordlen * sizeof(uint32_t)); + + /* Get the correct LUT element in constant time by touching + * all elements and masking out the correct one. + */ + +#define GET_LUT(x, y, z, index) \ + do \ + { \ + int m; \ + CASPER_MEMCPY((x), FSL_CASPER_LUT(1U, 0U), N_wordlen * sizeof(uint32_t)); \ + CASPER_MEMCPY((y), FSL_CASPER_LUT(1U, 1U), N_wordlen * sizeof(uint32_t)); \ + CASPER_MEMCPY((z), FSL_CASPER_LUT(1U, 2U), N_wordlen * sizeof(uint32_t)); \ + m = (int32_t)((index) == 3U); \ + casper_select((x), (x), FSL_CASPER_LUT(3U, 0U), m, (int16_t)(uint16_t)N_wordlen); \ + casper_select((y), (y), FSL_CASPER_LUT(3U, 1U), m, (int16_t)(uint16_t)N_wordlen); \ + casper_select((z), (z), FSL_CASPER_LUT(3U, 2U), m, (int16_t)(uint16_t)N_wordlen); \ + m = (int32_t)((index) == 5U); \ + casper_select((x), (x), FSL_CASPER_LUT(5U, 0U), m, (int16_t)(uint16_t)N_wordlen); \ + casper_select((y), (y), FSL_CASPER_LUT(5U, 1U), m, (int16_t)(uint16_t)N_wordlen); \ + casper_select((z), (z), FSL_CASPER_LUT(5U, 2U), m, (int16_t)(uint16_t)N_wordlen); \ + m = (int32_t)((index) == 7U); \ + casper_select((x), (x), FSL_CASPER_LUT(7U, 0U), m, (int16_t)(uint16_t)N_wordlen); \ + casper_select((y), (y), FSL_CASPER_LUT(7U, 1U), m, (int16_t)(uint16_t)N_wordlen); \ + casper_select((z), (z), FSL_CASPER_LUT(7U, 2U), m, (int16_t)(uint16_t)N_wordlen); \ + } while (false) + + GET_LUT(X3, Y3, Z3, index); + + /* Compute -y and select the positive or negative point. */ + (void)sub_n(M, p, Y3, (int16_t)(uint16_t)N_wordlen); // todo!!! + casper_select(Y3, Y3, M, sign, (int16_t)(uint16_t)N_wordlen); + + for (i = (int)(uint32_t)(recodeLength - 2U); i >= 0; i--) + { + Jac_double(X3, Y3, Z3, X3, Y3, Z3); + Jac_double(X3, Y3, Z3, X3, Y3, Z3); + Jac_double(X3, Y3, Z3, X3, Y3, Z3); + + index = int8abs(rec[i]); + sign = (int32_t)(uint32_t)(uint8_t)(((uint8_t)rec[i]) >> 7); + + GET_LUT(X, Y, Z, index); + + /* Compute -y and select the positive or negative point. */ + (void)sub_n(scalar, p, Y, (int16_t)(uint16_t)N_wordlen); // todo!!! + casper_select(scalar, Y, scalar, sign, (int16_t)(uint16_t)N_wordlen); + + Jac_addition(X3, Y3, Z3, X3, Y3, Z3, X, scalar, Z); + } + + (void)sub_n(M, p, Y3, (int16_t)(uint16_t)N_wordlen); // todo!!! + + casper_select(Y3, M, Y3, odd, (int16_t)(uint16_t)N_wordlen); +} + +#undef FSL_CASPER_LUT +#undef GET_LUT + +/* + * Pre-compute the following 16 points: + * 00 00 = 0*P + 0*Q <-- Not needed when using sliding windows + * 00 01 = 0*P + 1*Q <-- Not needed when using sliding windows + * 00 10 = 0*P + 2*Q + * 00 11 = 0*P + 3*Q + * + * 01 00 = 1*P + 0*Q <-- Not needed when using sliding windows + * 01 01 = 1*P + 1*Q <-- Not needed when using sliding windows + * 01 10 = 1*P + 2*Q + * 01 11 = 1*P + 3*Q + * + * 10 00 = 2*P + 0*Q + * 10 01 = 2*P + 1*Q + * 10 10 = 2*P + 2*Q + * 10 11 = 2*P + 3*Q + * + * 11 00 = 3*P + 0*Q + * 11 01 = 3*P + 1*Q + * 11 10 = 3*P + 2*Q + * 11 11 = 3*P + 3*Q + * + * index = (bitsi||bitsj)-2 - (biti != 0)*2 + * + * Input: P = (X1 : Y1 : Z1) and + * Q = (X2 : Y2 : Z2) + * Output: mem, memory location for the LUT. + */ + +static void precompute_double_scalar_LUT16(uint32_t *Px, uint32_t *Py, uint32_t *Qx, uint32_t *Qy) +{ + uint32_t *Q2x, *Q2y, *Q2z, *P2x, *P2y, *P2z, *Z, *mem; + uint32_t *ONE = NULL; + uint32_t index = 0; + + if (N_wordlen == 8U) + { + ONE = NISTr256; + } + + if (N_wordlen == 12U) + { + ONE = NISTr384; + } + + Q2x = &CASPER_MEM[(20U * N_wordlen + 80U) + 48U * N_wordlen + 0U * (N_wordlen + 4U)]; + Q2y = &CASPER_MEM[(20U * N_wordlen + 80U) + 48U * N_wordlen + 1U * (N_wordlen + 4U)]; + Q2z = &CASPER_MEM[(20U * N_wordlen + 80U) + 48U * N_wordlen + 2U * (N_wordlen + 4U)]; + + /* Re-use memory from different scratch space since no + * projective point addition is used below. */ + P2x = &CASPER_MEM[((2U * (N_wordlen + 4U)) + (9U * (N_wordlen + 4U))) + 5U * (N_wordlen + 4U)]; + P2z = &CASPER_MEM[((2U * (N_wordlen + 4U)) + (9U * (N_wordlen + 4U))) + 6U * (N_wordlen + 4U)]; + P2y = &CASPER_MEM[((2U * (N_wordlen + 4U)) + (9U * (N_wordlen + 4U))) + 7U * (N_wordlen + 4U)]; + Z = &CASPER_MEM[((2U * (N_wordlen + 4U)) + (9U * (N_wordlen + 4U))) + 8U * (N_wordlen + 4U)]; + + mem = &CASPER_MEM[(20U * N_wordlen + 80U)]; + + CASPER_MEMCPY(Z, ONE, N_wordlen * sizeof(uint32_t)); + + // 00 10 = 0*P + 2*Q + Jac_double(Q2x, Q2y, Q2z, Qx, Qy, Z); + CASPER_MEMCPY(&mem[index], Q2x, N_wordlen * sizeof(uint32_t)); + index += N_wordlen; + CASPER_MEMCPY(&mem[index], Q2y, N_wordlen * sizeof(uint32_t)); + index += N_wordlen; + CASPER_MEMCPY(&mem[index], Q2z, N_wordlen * sizeof(uint32_t)); + index += N_wordlen; + + // 00 11 = 0*P + 3*Q + Jac_add_affine(P2x, P2y, P2z, Q2x, Q2y, Q2z, Qx, Qy); + CASPER_MEMCPY(&mem[index], P2x, N_wordlen * sizeof(uint32_t)); + index += N_wordlen; + CASPER_MEMCPY(&mem[index], P2y, N_wordlen * sizeof(uint32_t)); + index += N_wordlen; + CASPER_MEMCPY(&mem[index], P2z, N_wordlen * sizeof(uint32_t)); + index += N_wordlen; + + // 01 10 = 1*P + 2*Q + Jac_add_affine(P2x, P2y, P2z, Q2x, Q2y, Q2z, Px, Py); + CASPER_MEMCPY(&mem[index], P2x, N_wordlen * sizeof(uint32_t)); + index += N_wordlen; + CASPER_MEMCPY(&mem[index], P2y, N_wordlen * sizeof(uint32_t)); + index += N_wordlen; + CASPER_MEMCPY(&mem[index], P2z, N_wordlen * sizeof(uint32_t)); + index += N_wordlen; + + // 01 11 = 1*P + 3*Q + Jac_add_affine(P2x, P2y, P2z, P2x, P2y, P2z, Qx, Qy); + CASPER_MEMCPY(&mem[index], P2x, N_wordlen * sizeof(uint32_t)); + index += N_wordlen; + CASPER_MEMCPY(&mem[index], P2y, N_wordlen * sizeof(uint32_t)); + index += N_wordlen; + CASPER_MEMCPY(&mem[index], P2z, N_wordlen * sizeof(uint32_t)); + index += N_wordlen; + + // 10 00 = 2*P + 0*Q + Jac_double(P2x, P2y, P2z, Px, Py, Z); + CASPER_MEMCPY(&mem[index], P2x, N_wordlen * sizeof(uint32_t)); + index += N_wordlen; + CASPER_MEMCPY(&mem[index], P2y, N_wordlen * sizeof(uint32_t)); + index += N_wordlen; + CASPER_MEMCPY(&mem[index], P2z, N_wordlen * sizeof(uint32_t)); + index += N_wordlen; + + // 10 01 = 2*P + 1*Q + Jac_add_affine(Q2x, Q2y, Q2z, P2x, P2y, P2z, Qx, Qy); + CASPER_MEMCPY(&mem[index], Q2x, N_wordlen * sizeof(uint32_t)); + index += N_wordlen; + CASPER_MEMCPY(&mem[index], Q2y, N_wordlen * sizeof(uint32_t)); + index += N_wordlen; + CASPER_MEMCPY(&mem[index], Q2z, N_wordlen * sizeof(uint32_t)); + index += N_wordlen; + + // 10 10 = 2*P + 2*Q + Jac_add_affine(Q2x, Q2y, Q2z, Q2x, Q2y, Q2z, Qx, Qy); + CASPER_MEMCPY(&mem[index], Q2x, N_wordlen * sizeof(uint32_t)); + index += N_wordlen; + CASPER_MEMCPY(&mem[index], Q2y, N_wordlen * sizeof(uint32_t)); + index += N_wordlen; + CASPER_MEMCPY(&mem[index], Q2z, N_wordlen * sizeof(uint32_t)); + index += N_wordlen; + + // 10 11 = 2*P + 3*Q + Jac_add_affine(Q2x, Q2y, Q2z, Q2x, Q2y, Q2z, Qx, Qy); + CASPER_MEMCPY(&mem[index], Q2x, N_wordlen * sizeof(uint32_t)); + index += N_wordlen; + CASPER_MEMCPY(&mem[index], Q2y, N_wordlen * sizeof(uint32_t)); + index += N_wordlen; + CASPER_MEMCPY(&mem[index], Q2z, N_wordlen * sizeof(uint32_t)); + index += N_wordlen; + + // 11 00 = 3*P + 0*Q + Jac_add_affine(P2x, P2y, P2z, P2x, P2y, P2z, Px, Py); + CASPER_MEMCPY(&mem[index], P2x, N_wordlen * sizeof(uint32_t)); + index += N_wordlen; + CASPER_MEMCPY(&mem[index], P2y, N_wordlen * sizeof(uint32_t)); + index += N_wordlen; + CASPER_MEMCPY(&mem[index], P2z, N_wordlen * sizeof(uint32_t)); + index += N_wordlen; + + // 11 01 = 3*P + 1*Q + Jac_add_affine(Q2x, Q2y, Q2z, P2x, P2y, P2z, Qx, Qy); + CASPER_MEMCPY(&mem[index], Q2x, N_wordlen * sizeof(uint32_t)); + index += N_wordlen; + CASPER_MEMCPY(&mem[index], Q2y, N_wordlen * sizeof(uint32_t)); + index += N_wordlen; + CASPER_MEMCPY(&mem[index], Q2z, N_wordlen * sizeof(uint32_t)); + index += N_wordlen; + + // 11 10 = 3*P + 2*Q + Jac_add_affine(Q2x, Q2y, Q2z, Q2x, Q2y, Q2z, Qx, Qy); + CASPER_MEMCPY(&mem[index], Q2x, N_wordlen * sizeof(uint32_t)); + index += N_wordlen; + CASPER_MEMCPY(&mem[index], Q2y, N_wordlen * sizeof(uint32_t)); + index += N_wordlen; + CASPER_MEMCPY(&mem[index], Q2z, N_wordlen * sizeof(uint32_t)); + index += N_wordlen; + + // 11 11 = 3*P + 3*Q + Jac_add_affine(Q2x, Q2y, Q2z, Q2x, Q2y, Q2z, Qx, Qy); + CASPER_MEMCPY(&mem[index], Q2x, N_wordlen * sizeof(uint32_t)); + index += N_wordlen; + CASPER_MEMCPY(&mem[index], Q2y, N_wordlen * sizeof(uint32_t)); + index += N_wordlen; + CASPER_MEMCPY(&mem[index], Q2z, N_wordlen * sizeof(uint32_t)); + index += N_wordlen; +} + +/* + * Pre-compute the following 4 points: + * 0 0 = 0*P + 0*Q <-- Not needed when using sliding windows + * 0 1 = 0*P + 1*Q + * + * 1 0 = 1*P + 0*Q + * 1 1 = 1*P + 1*Q + * + * index = (bitsj+1) & (0-bitsi) + * + * Input: P = (X1 : Y1 : Z1) and + * Q = (X2 : Y2 : Z2) + * Output: mem, memory location for the LUT. + */ + +static void precompute_double_scalar_LUT4(uint32_t *Px, uint32_t *Py, uint32_t *Qx, uint32_t *Qy) +{ + uint32_t *Z, *mem, *ONE; + uint32_t index = 0; + + ONE = NISTr521; + + /* Re-use memory from different scratch space since no + * projective point addition is used below. */ + Z = &CASPER_MEM[(11U * N_wordlen + 4U) + 5U * (N_wordlen + 4U)]; + mem = &CASPER_MEM[(20U * N_wordlen + 80U)]; + + CASPER_MEMCPY(Z, ONE, N_wordlen * sizeof(uint32_t)); + + // 0*P + 1*Q + CASPER_MEMCPY(&mem[index], Qx, N_wordlen * sizeof(uint32_t)); + index += N_wordlen; + CASPER_MEMCPY(&mem[index], Qy, N_wordlen * sizeof(uint32_t)); + index += N_wordlen; + CASPER_MEMCPY(&mem[index], Z, N_wordlen * sizeof(uint32_t)); + index += N_wordlen; + + // 1*P + 0*Q + CASPER_MEMCPY(&mem[index], Px, N_wordlen * sizeof(uint32_t)); + index += N_wordlen; + CASPER_MEMCPY(&mem[index], Py, N_wordlen * sizeof(uint32_t)); + index += N_wordlen; + CASPER_MEMCPY(&mem[index], Z, N_wordlen * sizeof(uint32_t)); + index += N_wordlen; + + // 1*P + 1*Q + Jac_add_affine(&mem[index], &mem[index + N_wordlen], &mem[index + 2U * N_wordlen], Px, Py, Z, Qx, Qy); +} + +#define GETLUTX(x) (3U * (x)*N_wordlen) +#define GETLUTY(x) (3U * (x)*N_wordlen + 1U * N_wordlen) +#define GETLUTZ(x) (3U * (x)*N_wordlen + 2U * N_wordlen) + +/* Compute the double scalar multiplication + * (X3 : Y3 : Z3) = k1 * (X1, Y1) + k2 * (X2, Y2) + * Using Shamir's trick and precomputing 16 points. + * This code is *not* constant time since this is used + * for verification only. + */ +void double_scalar_multiplication(uint32_t *X3, + uint32_t *Y3, + uint32_t *Z3, + uint32_t *X1, + uint32_t *Y1, + uint32_t *k1, + uint32_t *X2, + uint32_t *Y2, + uint32_t *k2) +{ + uint32_t index = 0, c = 0; + uint32_t *p1 = NULL, *p2 = NULL, x1, x2, *lut, *Tx = NULL, *Ty = NULL, *Tz = NULL; + size_t bitlen, shiftr, shiftl = 0u; + + if (N_wordlen == 8U) + { + bitlen = (size_t)kCASPER_ECC_P256_N_bitlen; + precompute_double_scalar_LUT16(X1, Y1, X2, Y2); + shiftr = 30U; + shiftl = 2U; + } + + if (N_wordlen == 12U) + { + bitlen = (size_t)kCASPER_ECC_P384_N_bitlen; + precompute_double_scalar_LUT16(X1, Y1, X2, Y2); + shiftr = 30U; + shiftl = 2U; + } + + if (N_wordlen == 18U) + { + bitlen = (size_t)kCASPER_ECC_P521_N_bitlen; + precompute_double_scalar_LUT4(X1, Y1, X2, Y2); + shiftr = 31U; + shiftl = 1U; + } + + lut = &CASPER_MEM[(20U * N_wordlen + 80U)]; + + if (N_wordlen == 8U || N_wordlen == 12U) + { + p1 = &CASPER_MEM[(20U * N_wordlen + 80U) + 48U * N_wordlen]; + p2 = &CASPER_MEM[(20U * N_wordlen + 80U) + 48U * N_wordlen + 1U * (N_wordlen + 4U)]; + + Tx = &CASPER_MEM[(20U * N_wordlen + 80U) + 48U * N_wordlen + 2U * (N_wordlen + 4U)]; + Ty = &CASPER_MEM[(20U * N_wordlen + 80U) + 48U * N_wordlen + 3U * (N_wordlen + 4U)]; + Tz = &CASPER_MEM[(20U * N_wordlen + 80U) + 48U * N_wordlen + 4U * (N_wordlen + 4U)]; + } + + if (N_wordlen == 18U) + { + p1 = &CASPER_MEM[(20U * N_wordlen + 80U) + 12U * N_wordlen]; + p2 = &CASPER_MEM[(20U * N_wordlen + 80U) + 12U * N_wordlen + 1U * (N_wordlen + 4U)]; + + Tx = &CASPER_MEM[(20U * N_wordlen + 80U) + 12U * N_wordlen + 2U * (N_wordlen + 4U)]; + Ty = &CASPER_MEM[(20U * N_wordlen + 80U) + 12U * N_wordlen + 3U * (N_wordlen + 4U)]; + Tz = &CASPER_MEM[(20U * N_wordlen + 80U) + 12U * N_wordlen + 4U * (N_wordlen + 4U)]; + } + + CASPER_MEMCPY(p1, k1, sizeof(uint32_t) * N_wordlen); + CASPER_MEMCPY(p2, k2, sizeof(uint32_t) * N_wordlen); + + /* Check if we can slide. */ + while (((casper_get_word(&p1[N_wordlen - 1U]) | casper_get_word(&p2[N_wordlen - 1U])) >> 31) == 0U && c < bitlen) + { + shiftleft(p1, p1, 1U); + shiftleft(p2, p2, 1U); + c++; + /* No doubling needed. */ + } + + /* Set the first value. */ + x1 = casper_get_word(&p1[N_wordlen - 1U]) >> shiftr; + x2 = casper_get_word(&p2[N_wordlen - 1U]) >> shiftr; + if (N_wordlen == 8U || N_wordlen == 12U) + { + index = (x2 | (x1 << 2)) - 2U - (uint32_t)(x1 != 0U) * 2U; + } + + if (N_wordlen == 18U) + { + index = (((x2) + 1U) & (0U - (x1))); + } + shiftleft(p1, p1, shiftl); + shiftleft(p2, p2, shiftl); + + CASPER_MEMCPY(X3, &lut[GETLUTX(index)], N_wordlen * sizeof(uint32_t)); + CASPER_MEMCPY(Y3, &lut[GETLUTY(index)], N_wordlen * sizeof(uint32_t)); + CASPER_MEMCPY(Z3, &lut[GETLUTZ(index)], N_wordlen * sizeof(uint32_t)); + c += shiftl; + + // todo: create an is_zero function + + while ((casper_get_word(&p1[0]) | casper_get_word(&p1[1]) | casper_get_word(&p1[2]) | casper_get_word(&p1[3]) | + casper_get_word(&p1[4]) | casper_get_word(&p1[5]) | casper_get_word(&p1[6]) | casper_get_word(&p1[7]) | + casper_get_word(&p1[8]) | casper_get_word(&p1[9]) | casper_get_word(&p1[10]) | casper_get_word(&p1[11]) | + casper_get_word(&p1[12]) | casper_get_word(&p1[13]) | casper_get_word(&p1[14]) | casper_get_word(&p1[15]) | + casper_get_word(&p1[16]) | casper_get_word(&p1[17]) | casper_get_word(&p2[0]) | casper_get_word(&p2[1]) | + casper_get_word(&p2[2]) | casper_get_word(&p2[3]) | casper_get_word(&p2[4]) | casper_get_word(&p2[5]) | + casper_get_word(&p2[6]) | casper_get_word(&p2[7]) | casper_get_word(&p2[8]) | casper_get_word(&p2[9]) | + casper_get_word(&p2[10]) | casper_get_word(&p2[11]) | casper_get_word(&p2[12]) | casper_get_word(&p2[13]) | + casper_get_word(&p2[14]) | casper_get_word(&p2[15]) | casper_get_word(&p2[16]) | + casper_get_word(&p2[17])) != 0U) + { + /* Check if we can slide. */ + while (((casper_get_word(&p1[N_wordlen - 1U]) | casper_get_word(&p2[N_wordlen - 1U])) >> 31) == 0U && + c < bitlen) + { + shiftleft(p1, p1, 1U); + shiftleft(p2, p2, 1U); + Jac_double(X3, Y3, Z3, X3, Y3, Z3); + c++; + } + + if (c >= (bitlen - 1U)) + { + break; + } + + for (uint32_t i = 0; i < shiftl; i++) + { + Jac_double(X3, Y3, Z3, X3, Y3, Z3); + } + + x1 = casper_get_word(&p1[N_wordlen - 1U]) >> shiftr; + x2 = casper_get_word(&p2[N_wordlen - 1U]) >> shiftr; + + if (N_wordlen == 8U || N_wordlen == 12U) + { + index = (x2 | (x1 << 2)) - 2U - (uint32_t)(x1 != 0U) * 2U; + } + + if (N_wordlen == 18U) + { + index = (((x2) + 1U) & (0U - (x1))); + } + + shiftleft(p1, p1, shiftl); + shiftleft(p2, p2, shiftl); + + CASPER_MEMCPY(Tx, &lut[GETLUTX(index)], N_wordlen * sizeof(uint32_t)); + CASPER_MEMCPY(Ty, &lut[GETLUTY(index)], N_wordlen * sizeof(uint32_t)); + CASPER_MEMCPY(Tz, &lut[GETLUTZ(index)], N_wordlen * sizeof(uint32_t)); + + Jac_addition(X3, Y3, Z3, X3, Y3, Z3, Tx, Ty, + Tz); //&lut[GETLUTX(index)], &lut[GETLUTY(index)], &lut[GETLUTZ(index)]); + c += shiftl; + } + + /* Special case in the end. */ + if (c == (bitlen - 1U)) + { + Jac_double(X3, Y3, Z3, X3, Y3, Z3); + x1 = casper_get_word(&p1[N_wordlen - 1U]) >> 31; + x2 = casper_get_word(&p2[N_wordlen - 1U]) >> 31; + if (0U != x1) + { + Jac_add_affine(X3, Y3, Z3, X3, Y3, Z3, X1, Y1); + } + if (x2 != 0U) + { + Jac_add_affine(X3, Y3, Z3, X3, Y3, Z3, X2, Y2); + } + c++; + } + + while (c < bitlen) + { + Jac_double(X3, Y3, Z3, X3, Y3, Z3); + c++; + } +} + +static void invert_mod_p256(uint32_t *c, uint32_t *a) +{ + int i; + uint32_t *t, *t2, *s1, *s2, *s4, *s8, *tmp; + + /* Assuming it is safe to use the ECC scratch size. */ + t = &CASPER_MEM[((2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + + (9U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U))) + + 2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)]; + t2 = &CASPER_MEM[((2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + + (9U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U))) + + 3U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)]; + s1 = &CASPER_MEM[((2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + + (9U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U))) + + 4U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)]; + s2 = &CASPER_MEM[((2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + + (9U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U))) + + 5U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)]; + s4 = &CASPER_MEM[((2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + + (9U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U))) + + 6U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)]; + s8 = &CASPER_MEM[((2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + + (9U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U))) + + 7U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)]; + tmp = &CASPER_MEM[((2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + + (9U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U))) + + 8U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)]; + + // t2 = n^(2^1)*n # 11 + square_casper(tmp, a); + multiply_casper(t2, tmp, a); + + // s1 = t2^(2^2)*t2 # F + square_casper(s1, t2); + square_casper(tmp, s1); + multiply_casper(s1, tmp, t2); + + // s2 = s1^(2^4)*s1 # FF + square_casper(s2, s1); + // for (i = 1; i < 4; i++) square(s2, s2); + square_casper(tmp, s2); + square_casper(s2, tmp); + square_casper(tmp, s2); + multiply_casper(s2, tmp, s1); + + // s4 = s2^(2^8)*s2 # FFFF + square_casper(s4, s2); + for (i = 1; i < 7; i += 2) + { + square_casper(tmp, s4); + square_casper(s4, tmp); + } + square_casper(tmp, s4); + multiply_casper(s4, tmp, s2); + + // s8 = s4^(2^16)*s4 # FFFFFFFF + square_casper(s8, s4); + for (i = 1; i < 15; i += 2) + { + square_casper(tmp, s8); + square_casper(s8, tmp); + } + square_casper(tmp, s8); + multiply_casper(s8, tmp, s4); + + // t = s8^(2^32)*n # ffffffff00000001 + square_casper(tmp, s8); + for (i = 1; i < 31; i += 2) + { + square_casper(t, tmp); + square_casper(tmp, t); + } + square_casper(t, tmp); + multiply_casper(tmp, t, a); + + // t = t^(2^128)*s8 # ffffffff00000001000000000000000000000000ffffffff + for (i = 0; i < 128; i += 2) + { + square_casper(t, tmp); + square_casper(tmp, t); + } + multiply_casper(t, tmp, s8); + + // t = t^(2^32)*s8 # ffffffff00000001000000000000000000000000ffffffffffffffff + for (i = 0; i < 32; i += 2) + { + square_casper(tmp, t); + square_casper(t, tmp); + } + multiply_casper(tmp, t, s8); + + // t = t^(2^16)*s4 # ffffffff00000001000000000000000000000000ffffffffffffffffffff + for (i = 0; i < 16; i += 2) + { + square_casper(t, tmp); + square_casper(tmp, t); + } + multiply_casper(t, tmp, s4); + + // t = t^(2^8)*s2 # ffffffff00000001000000000000000000000000ffffffffffffffffffffff + for (i = 0; i < 8; i += 2) + { + square_casper(tmp, t); + square_casper(t, tmp); + } + multiply_casper(tmp, t, s2); + + // t = t^(2^4)*s1 # ffffffff00000001000000000000000000000000fffffffffffffffffffffff + for (i = 0; i < 4; i += 2) + { + square_casper(t, tmp); + square_casper(tmp, t); + } + multiply_casper(t, tmp, s1); + + // t = t^(2^2)*t2 + square_casper(tmp, t); + square_casper(t, tmp); + multiply_casper(tmp, t, t2); + + // t = t^(2^2)*n # ffffffff00000001000000000000000000000000fffffffffffffffffffffffd + square_casper(t, tmp); + square_casper(tmp, t); + multiply_casper(c, tmp, a); +} + +// A and C do not need to be in Casper memory +static void toMontgomery_ECC_P256(uint32_t *C, uint32_t *A) +{ + /* R^2 = 2^512 mod p, used to convert values to Montgomery form. */ + uint32_t R2[kCASPER_ECC_P256_wordlen] = {0x00000003, 0x00000000, 0xffffffffU, 0xfffffffbU, + 0xfffffffeU, 0xffffffffU, 0xfffffffdU, 0x4}; + uint32_t *T1, *T2, *T3; + T1 = &CASPER_MEM[((2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + + (9U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U))) + + 0U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)]; + T2 = &CASPER_MEM[((2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + + (9U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U))) + + 1U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)]; + T3 = &CASPER_MEM[((2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + + (9U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U))) + + 2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)]; + + CASPER_MEMCPY(T1, R2, (uint32_t)kCASPER_ECC_P256_wordlen * sizeof(uint32_t)); + CASPER_MEMCPY(T2, A, (uint32_t)kCASPER_ECC_P256_wordlen * sizeof(uint32_t)); + + multiply_casper(T3, T2, T1); + CASPER_MEMCPY(C, T3, (uint32_t)kCASPER_ECC_P256_wordlen * sizeof(uint32_t)); +} + +/* Compute inversion modulo NIST-p384 using Fermats little theorem. + * Using c = a^(p-2) = a^(-1) mod p. + * This computes the modular inversion if all arithmetic is "regular" + * modular arithmetic or computes automatically the Montgomery inverse + * if all arithmetic is Montgomery arithmetic. + */ + +static void invert_mod_p384(uint32_t *c, uint32_t *a) +{ + int i; + uint32_t *e, *d, *tmp, *t0, *t1, *t2, *t3, *t4, *t5, *t6; // 10 residues needed + + /* Assuming it is safe to use the LUT scratch size. + * Hence, do not invert while elements in the LUT are needed. + */ + e = &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P384_wordlen + 80U) + 0U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)]; + d = &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P384_wordlen + 80U) + 1U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)]; + tmp = + &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P384_wordlen + 80U) + 2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)]; + t0 = &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P384_wordlen + 80U) + 3U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)]; + t1 = &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P384_wordlen + 80U) + 4U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)]; + t2 = &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P384_wordlen + 80U) + 5U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)]; + t3 = &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P384_wordlen + 80U) + 6U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)]; + t4 = &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P384_wordlen + 80U) + 7U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)]; + t5 = &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P384_wordlen + 80U) + 8U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)]; + t6 = &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P384_wordlen + 80U) + 9U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)]; + + square_casper(tmp, a); // 2 + square_casper(t1, tmp); // 4 + square_casper(tmp, t1); // 8 + multiply_casper(t2, tmp, t1); // 12 + multiply_casper(d, a, t2); // 13 + multiply_casper(e, d, a); // 14 + multiply_casper(t0, e, a); // 15 + + // t1 = t0^(2^4)*t0 # ff + square_casper(tmp, t0); + square_casper(t1, tmp); + square_casper(tmp, t1); + square_casper(t2, tmp); + multiply_casper(t1, t2, t0); + + // t2 = t1^(2^8)*t1 # 4f + square_casper(tmp, t1); + for (i = 0; i < 3; i++) + { + square_casper(t3, tmp); + square_casper(tmp, t3); + } + square_casper(t3, tmp); + multiply_casper(t2, t3, t1); + + // t3 = t2^(2^16)*t2 # 8f + square_casper(tmp, t2); + for (i = 0; i < 7; i++) + { + square_casper(t4, tmp); + square_casper(tmp, t4); + } + square_casper(t4, tmp); + multiply_casper(t3, t4, t2); + + // t4 = t3^(2^32)*t3 # 16f + square_casper(tmp, t3); + for (i = 0; i < 15; i++) + { + square_casper(t5, tmp); + square_casper(tmp, t5); + } + square_casper(t5, tmp); + multiply_casper(t4, t5, t3); + + // t5 = t4^(2^64)*t4 # 32f + square_casper(tmp, t4); + for (i = 0; i < 31; i++) + { + square_casper(t6, tmp); + square_casper(tmp, t6); + } + square_casper(t6, tmp); + multiply_casper(t5, t6, t4); + + // t5 = t5^(2^64)*t4 # 48f + square_casper(tmp, t5); + for (i = 0; i < 31; i++) + { + square_casper(t6, tmp); + square_casper(tmp, t6); + } + square_casper(t6, tmp); + multiply_casper(t5, t6, t4); + + // t5 = t5^(2^32)*t3 # 56f + square_casper(tmp, t5); + for (i = 0; i < 15; i++) + { + square_casper(t6, tmp); + square_casper(tmp, t6); + } + square_casper(t6, tmp); + multiply_casper(t5, t6, t3); + + // t5 = t5^(2^16)*t2 # 60f + square_casper(tmp, t5); + for (i = 0; i < 7; i++) + { + square_casper(t6, tmp); + square_casper(tmp, t6); + } + square_casper(t6, tmp); + multiply_casper(t5, t6, t2); + + // t5 = t5^(2^8)*t1 # 62f + square_casper(tmp, t5); + for (i = 0; i < 3; i++) + { + square_casper(t6, tmp); + square_casper(tmp, t6); + } + square_casper(t6, tmp); + multiply_casper(t5, t6, t1); + + // n = t5^(2^4)*t0 # 63f + square_casper(tmp, t5); + for (i = 0; i < 1; i++) + { + square_casper(t6, tmp); + square_casper(tmp, t6); + } + square_casper(t6, tmp); + multiply_casper(t5, t6, t0); + + // n = n^(2^4)*e + square_casper(tmp, t5); + for (i = 0; i < 1; i++) + { + square_casper(t6, tmp); + square_casper(tmp, t6); + } + square_casper(t6, tmp); + multiply_casper(t5, t6, e); + + // n = n^(2^32)*t3 + square_casper(tmp, t5); + for (i = 0; i < 15; i++) + { + square_casper(t6, tmp); + square_casper(tmp, t6); + } + square_casper(t6, tmp); + multiply_casper(t5, t6, t3); + + // n = n^(2^64) + square_casper(tmp, t5); + for (i = 0; i < 31; i++) + { + square_casper(t6, tmp); + square_casper(tmp, t6); + } + square_casper(t5, tmp); + + // n = n^(2^16)*t2 + square_casper(tmp, t5); + for (i = 0; i < 7; i++) + { + square_casper(t6, tmp); + square_casper(tmp, t6); + } + square_casper(t6, tmp); + multiply_casper(t5, t6, t2); + + // n = n^(2^8)*t1 + square_casper(tmp, t5); + for (i = 0; i < 3; i++) + { + square_casper(t6, tmp); + square_casper(tmp, t6); + } + square_casper(t6, tmp); + multiply_casper(t5, t6, t1); + + // n = n^(2^4)*t0 + square_casper(tmp, t5); + for (i = 0; i < 1; i++) + { + square_casper(t6, tmp); + square_casper(tmp, t6); + } + square_casper(t6, tmp); + multiply_casper(t5, t6, t0); + + // n = n^(2^4)*d + square_casper(tmp, t5); + for (i = 0; i < 1; i++) + { + square_casper(t6, tmp); + square_casper(tmp, t6); + } + square_casper(t6, tmp); + multiply_casper(c, t6, d); +} + +// A and C do not need to be in Casper memory +static void toMontgomery_ECC_P384(uint32_t *C, uint32_t *A) +{ + /* R^2 = 2^768 mod p, used to convert values to Montgomery form. */ + uint32_t R2[kCASPER_ECC_P384_wordlen] = {0x00000001, 0xfffffffeU, 0x00000000, 0x00000002, 0x00000000, 0xfffffffeU, + 0x00000000, 0x00000002, 0x1, 0x0, 0x0, 0x0}; + uint32_t *T1, *T2, *T3; + T1 = &CASPER_MEM[((2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + + (9U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U))) + + 0U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)]; + T2 = &CASPER_MEM[((2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + + (9U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U))) + + 1U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)]; + T3 = &CASPER_MEM[((2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + + (9U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U))) + + 2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)]; + + CASPER_MEMCPY(T1, R2, (uint32_t)kCASPER_ECC_P384_wordlen * sizeof(uint32_t)); + CASPER_MEMCPY(T2, A, (uint32_t)kCASPER_ECC_P384_wordlen * sizeof(uint32_t)); + + multiply_casper(T3, T2, T1); + CASPER_MEMCPY(C, T3, (uint32_t)kCASPER_ECC_P384_wordlen * sizeof(uint32_t)); +} + +static void invert_mod_p521(uint32_t *c, uint32_t *a) +{ + int i; + uint32_t *e3, *d2, *d3, *d4, *T2, *T4; // 6 residues needed + + /* Assuming it is safe to use the LUT scratch size. + * Hence, do not invert while elements in the LUT are needed. + */ + e3 = &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P521_wordlen + 80U) + 0U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)]; + d2 = &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P521_wordlen + 80U) + 1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)]; + d3 = &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P521_wordlen + 80U) + 2U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)]; + d4 = &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P521_wordlen + 80U) + 3U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)]; + T2 = &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P521_wordlen + 80U) + 4U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)]; + T4 = &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P521_wordlen + 80U) + 5U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)]; + + square_casper(d2, a); + multiply_casper(T2, d2, a); + + // d3 = 2^2 * T2 + square_casper(d3, T2); + square_casper(e3, d3); + multiply_casper(T4, e3, T2); + + // d3 = 2^4 * T4 + square_casper(d3, T4); + square_casper(e3, d3); + square_casper(d3, e3); + square_casper(e3, d3); + multiply_casper(d2, e3, T4); + + // d3 = 2^8 * d2 + square_casper(d3, d2); + square_casper(e3, d3); + for (i = 0; i < 3; i++) + { + square_casper(d3, e3); + square_casper(e3, d3); + } + multiply_casper(d4, e3, d2); + + // d3 = 2^16 * d2 + square_casper(d3, d4); + square_casper(e3, d3); + for (i = 0; i < 7; i++) + { + square_casper(d3, e3); + square_casper(e3, d3); + } + multiply_casper(d2, e3, d4); + + // d3 = 2^32 * d2 + square_casper(d3, d2); + square_casper(e3, d3); + for (i = 0; i < 15; i++) + { + square_casper(d3, e3); + square_casper(e3, d3); + } + multiply_casper(d4, e3, d2); + + // d3 = 2^64 * d2 + square_casper(d3, d4); + square_casper(e3, d3); + for (i = 0; i < 31; i++) + { + square_casper(d3, e3); + square_casper(e3, d3); + } + multiply_casper(d2, e3, d4); + + // d3 = 2^128 * d2 + square_casper(d3, d2); + square_casper(e3, d3); + for (i = 0; i < 63; i++) + { + square_casper(d3, e3); + square_casper(e3, d3); + } + multiply_casper(d4, e3, d2); + + // d3 = 2^256 * d2 + square_casper(d3, d4); + square_casper(e3, d3); + for (i = 0; i < 127; i++) + { + square_casper(d3, e3); + square_casper(e3, d3); + } + multiply_casper(d2, e3, d4); + + // d3 = 2^2 * d2 + square_casper(d3, d2); + square_casper(e3, d3); + multiply_casper(d2, e3, T2); + + // d3 = 2^4 * d2 + square_casper(d3, d2); + square_casper(e3, d3); + square_casper(d3, e3); + square_casper(e3, d3); + multiply_casper(d2, e3, T4); + + square_casper(d3, d2); + multiply_casper(d2, d3, a); + + // d3 = 2 ^ 2 * d2 + square_casper(d3, d2); + square_casper(e3, d3); + multiply_casper(c, e3, a); +} + +static void toMontgomery_ECC_P521(uint32_t *C, uint32_t *A) +{ + /* R^2 = 2^1088 mod p, used to convert values to Montgomery form. */ + // uint32_t R2[NUM_LIMBS] = { 0x00000000, 0x4000, 0, 0, + // 0, 0, 0, 0, + // 0, 0, 0, 0, + // 0 }; + /* R^2 = 2^1152 mod p, used to convert values to Montgomery form. */ + uint32_t R2[kCASPER_ECC_P521_wordlen] = {0, 0, 0, 0x4000, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; + + uint32_t *T1, *T2, *T3; + T1 = &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P521_wordlen + 80U) + 0U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)]; + T2 = &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P521_wordlen + 80U) + 1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)]; + T3 = &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P521_wordlen + 80U) + 2U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)]; + + CASPER_MEMCPY(T1, R2, (uint32_t)kCASPER_ECC_P521_wordlen * sizeof(uint32_t)); + CASPER_MEMCPY(T2, A, (uint32_t)kCASPER_ECC_P521_wordlen * sizeof(uint32_t)); + + multiply_casper(T3, T2, T1); + CASPER_MEMCPY(C, T3, (uint32_t)kCASPER_ECC_P521_wordlen * sizeof(uint32_t)); +} + +static void MultprecCiosMul521_ct( + uint32_t w_out[], const uint32_t a[], const uint32_t b[], const uint32_t Nmod[], const uint32_t *Np) +{ + uint32_t j; + uint64_t carry; + uint64_t *a64, *b64, *w64; + + uint32_t *T1 = &CASPER_MEM[0], borrow; + + a64 = (uint64_t *)(uintptr_t)a; + b64 = (uint64_t *)(uintptr_t)b; + w64 = (uint64_t *)(uintptr_t)w_out; + + if (a != NULL) + { /* if !a, we are reducing only */ + PreZeroW(j, w_out); + } + SET_DWORD(&w64[N_dwordlen], 0ULL); + SET_DWORD(&w64[N_dwordlen + 1U], 0ULL); + /* with accelerator */ + + /* loop j and then reduce after each j round */ + for (j = 0; j < N_dwordlen; j++) + { + /* Step 3. Iterate over N words of u using j - perform Multiply-accumulate */ + /* push-pull: we do a*b and then separately m*n (reduce) */ + if (a != NULL) + { /* if mul&reduce vs. reduce only */ + carry = GET_DWORD(&w64[N_dwordlen]); + Accel_SetABCD_Addr(CA_MK_OFF(&b64[j]), CA_MK_OFF(a64)); + Accel_crypto_mul( + Accel_IterOpcodeResaddr(N_dwordlen - 1U, (uint32_t)kCASPER_OpMul6464FullSum, CA_MK_OFF(w64))); + Accel_done(); + /* max carry is contained since ~0*~0=0xFFFE0001+0xFFFF=0xFFFF0000, */ + /* so max carry is 0xFFFF and 0xFFFF0000+0xFFFF=0xFFFFFFFF */ + /* accel took care of w_out[N_wordlen] & +1, so we just take care of the next double word if carry=1 */ + /* w64[N_dwordlen+1] = g_carry; */ + carry = (uint64_t)(GET_DWORD(&w64[N_dwordlen]) < carry); + SET_DWORD(&w64[N_dwordlen + 1U], carry); + } + + /* Fast reduction using only shifts for this special shape: + * (c - (-p^-1*c mod 2^64) * p)/2^64 = + * (c - c_0 * p)/2^64 = + * (\sum_{j=0}^9 c_i*2^64 - c_0 * p)/2^64 = + * (\sum_{j=0}^9 c_i*2^64 - c_0 * (2^521-1))/2^64 = + * (\sum_{j=0}^9 c_i*2^64 - c_0 * 2^521 - c_0)/2^64 = + * c_1 + c_2*2^64 + c_3*2^128 + c_4*2^192 + c_5*2^256 + c_6*2^320 + c_7*2^384 + c_8*2^448 + c_9*2^512 + c_0 * + * 2^{448 + 9} so one only needs to compute this 128-bit addition: [c_8, c_9] + c_0 * 2^9 + */ + + uint64_t *p64 = (uint64_t *)(uintptr_t)T1; + + /* p64[0] = w64[0] << 9;*/ + SET_DWORD(&p64[0], GET_DWORD(&w64[0]) << 9U); + /* p64[1] = w64[0] >> (64 - 9); */ + SET_DWORD(&p64[1], GET_DWORD(&w64[0]) >> (64 - 9)); + /* w64[0] = w64[1]; */ + SET_DWORD(&w64[0], GET_DWORD(&w64[1])); + /* w64[1] = w64[2]; */ + SET_DWORD(&w64[1], GET_DWORD(&w64[2])); + /* w64[2] = w64[3]; */ + SET_DWORD(&w64[2], GET_DWORD(&w64[3])); + /* w64[3] = w64[4]; */ + SET_DWORD(&w64[3], GET_DWORD(&w64[4])); + /* w64[4] = w64[5]; */ + SET_DWORD(&w64[4], GET_DWORD(&w64[5])); + /* w64[5] = w64[6]; */ + SET_DWORD(&w64[5], GET_DWORD(&w64[6])); + /* w64[6] = w64[7]; */ + SET_DWORD(&w64[6], GET_DWORD(&w64[7])); + + /* Compute p64 = p64 + {w64[8], w64[9]} using one additonal double-length limb, + * where p64 = w64[0] * 2^9. + */ + Accel_SetABCD_Addr(CA_MK_OFF(&w64[8]), 0); + Accel_crypto_mul(Accel_IterOpcodeResaddr(2, (uint32_t)kCASPER_OpAdd64, /* kCASPER_OpAdd64, */ + CA_MK_OFF(p64))); + Accel_done(); + + /* w64[7] = p64[0]; */ + SET_DWORD(&w64[7], GET_DWORD(&p64[0])); + /* w64[8] = p64[1]; */ + SET_DWORD(&w64[8], GET_DWORD(&p64[1])); + /* w64[9] = 0; */ + SET_DWORD(&w64[9], (uint64_t)0U); + } + + /* memcpy(T1, w_out, (NUM_LIMBS + 1) * sizeof(uint32_t)); */ + /* now check if need to subtract Nmod */ + CASPER_MEMCPY_I2I(T1, w_out, (N_wordlen + 1U) * sizeof(uint32_t)); + + /* Compute w = w - N */ + Accel_SetABCD_Addr(CA_MK_OFF(Nmod), 0); + Accel_crypto_mul(Accel_IterOpcodeResaddr(N_dwordlen, (uint32_t)kCASPER_OpSub64, CA_MK_OFF(w_out))); + Accel_done(); + + /* if w_out > T1 then there was a borrow */ + /* borrow = (((uint32_t*)w_out)[NUM_LIMBS] > T1[NUM_LIMBS]); */ + borrow = (uint32_t)(GET_WORD(&((uint32_t *)w_out)[N_wordlen]) > GET_WORD(&T1[N_wordlen])); + SET_WORD(&w_out[N_wordlen + 1U], 0); + SET_WORD(&w_out[N_wordlen], 0); + /* w_out[NUM_LIMBS + 1] = 0; */ + /* w_out[NUM_LIMBS] = 0; */ + casper_select(w_out, w_out, T1, (int32_t)borrow, (int32_t)N_wordlen); +} + +#if defined(__GNUC__) +/* End of enforcing O1 optimize level for gcc*/ +#pragma GCC pop_options +#endif + +#if (defined(__CC_ARM) || defined(__ARMCC_VERSION)) +// End of enforcing optimize off for clang +#pragma clang optimize on +#endif diff --git a/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_casper.h b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_casper.h new file mode 100644 index 0000000000..328dc10111 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_casper.h @@ -0,0 +1,386 @@ +/* + * Copyright 2018-2021 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_CASPER_H_ +#define _FSL_CASPER_H_ + +#include "fsl_common.h" + +/*! @file */ + +/******************************************************************************* + * Definitions + *******************************************************************************/ + +/*! + * @addtogroup casper_driver + * @{ + */ +/*! @name Driver version */ +/*@{*/ +/*! @brief CASPER driver version. Version 2.2.3. + * + * Current version: 2.2.3 + * + * Change log: + * - Version 2.0.0 + * - Initial version + * - Version 2.0.1 + * - Bug fix KPSDK-24531 double_scalar_multiplication() result may be all zeroes for some specific input + * - Version 2.0.2 + * - Bug fix KPSDK-25015 CASPER_MEMCPY hard-fault on LPC55xx when both source and destination buffers are outside of + * CASPER_RAM + * - Version 2.0.3 + * - Bug fix KPSDK-28107 RSUB, FILL and ZERO operations not implemented in enum _casper_operation. + * - Version 2.0.4 + * - For GCC compiler, enforce O1 optimize level, specifically to remove strict-aliasing option. + * This driver is very specific and requires -fno-strict-aliasing. + * - Version 2.0.5 + * - Fix sign-compare warning. + * - Version 2.0.6 + * - Fix IAR Pa082 warning. + * - Version 2.0.7 + * - Fix MISRA-C 2012 issue. + * - Version 2.0.8 + * - Add feature macro for CASPER_RAM_OFFSET. + * - Version 2.0.9 + * - Remove unused function Jac_oncurve(). + * - Fix ECC384 build. + * - Version 2.0.10 + * - Fix MISRA-C 2012 issue. + * - Version 2.1.0 + * - Add ECC NIST P-521 elliptic curve. + * - Version 2.2.0 + * - Rework driver to support multiple curves at once. + * - Version 2.2.1 + * - Fix MISRA-C 2012 issue. + * - Version 2.2.2 + * - Enable hardware interleaving to RAMX0 and RAMX1 for CASPER by feature macro FSL_FEATURE_CASPER_RAM_HW_INTERLEAVE + * - Version 2.2.3 + * - Added macro into CASPER_Init and CASPER_Deinit to support devices without clock and reset control. + */ +#define FSL_CASPER_DRIVER_VERSION (MAKE_VERSION(2, 2, 3)) +/*@}*/ + +/*! @brief CASPER operation + * + */ +typedef enum _casper_operation +{ + kCASPER_OpMul6464NoSum = 0x01, /*! Walking 1 or more of J loop, doing r=a*b using 64x64=128*/ + kCASPER_OpMul6464Sum = + 0x02, /*! Walking 1 or more of J loop, doing c,r=r+a*b using 64x64=128, but assume inner j loop*/ + kCASPER_OpMul6464FullSum = + 0x03, /*! Walking 1 or more of J loop, doing c,r=r+a*b using 64x64=128, but sum all of w. */ + kCASPER_OpMul6464Reduce = + 0x04, /*! Walking 1 or more of J loop, doing c,r[-1]=r+a*b using 64x64=128, but skip 1st write*/ + kCASPER_OpAdd64 = 0x08, /*! Walking add with off_AB, and in/out off_RES doing c,r=r+a+c using 64+64=65*/ + kCASPER_OpSub64 = 0x09, /*! Walking subtract with off_AB, and in/out off_RES doing r=r-a using 64-64=64, with last + borrow implicit if any*/ + kCASPER_OpDouble64 = 0x0A, /*! Walking add to self with off_RES doing c,r=r+r+c using 64+64=65*/ + kCASPER_OpXor64 = 0x0B, /*! Walking XOR with off_AB, and in/out off_RES doing r=r^a using 64^64=64*/ + kCASPER_OpRSub64 = 0x0C, /*! Walking subtract with off_AB, and in/out off_RES using r=a-r */ + kCASPER_OpShiftLeft32 = + 0x10, /*! Walking shift left doing r1,r=(b*D)|r1, where D is 2^amt and is loaded by app (off_CD not used)*/ + kCASPER_OpShiftRight32 = 0x11, /*! Walking shift right doing r,r1=(b*D)|r1, where D is 2^(32-amt) and is loaded by + app (off_CD not used) and off_RES starts at MSW*/ + kCASPER_OpCopy = 0x14, /*! Copy from ABoff to resoff, 64b at a time*/ + kCASPER_OpRemask = 0x15, /*! Copy and mask from ABoff to resoff, 64b at a time*/ + kCASPER_OpFill = 0x16, /*! Fill RESOFF using 64 bits at a time with value in A and B */ + kCASPER_OpZero = 0x17, /*! Fill RESOFF using 64 bits at a time of 0s */ + kCASPER_OpCompare = 0x18, /*! Compare two arrays, running all the way to the end*/ + kCASPER_OpCompareFast = 0x19, /*! Compare two arrays, stopping on 1st !=*/ +} casper_operation_t; + +/*! @brief Algorithm used for CASPER operation */ +typedef enum _casper_algo_t +{ + kCASPER_ECC_P256 = 0x01, /*!< ECC_P256*/ + kCASPER_ECC_P384 = 0x02, /*!< ECC_P384 */ + kCASPER_ECC_P521 = 0x03, /*!< ECC_P521 */ +} casper_algo_t; + +#define CASPER_CP 1 +#define CASPER_CP_CTRL0 (0x0 >> 2) +#define CASPER_CP_CTRL1 (0x4 >> 2) +#define CASPER_CP_LOADER (0x8 >> 2) +#define CASPER_CP_STATUS (0xC >> 2) +#define CASPER_CP_INTENSET (0x10 >> 2) +#define CASPER_CP_INTENCLR (0x14 >> 2) +#define CASPER_CP_INTSTAT (0x18 >> 2) +#define CASPER_CP_AREG (0x20 >> 2) +#define CASPER_CP_BREG (0x24 >> 2) +#define CASPER_CP_CREG (0x28 >> 2) +#define CASPER_CP_DREG (0x2C >> 2) +#define CASPER_CP_RES0 (0x30 >> 2) +#define CASPER_CP_RES1 (0x34 >> 2) +#define CASPER_CP_RES2 (0x38 >> 2) +#define CASPER_CP_RES3 (0x3C >> 2) +#define CASPER_CP_MASK (0x60 >> 2) +#define CASPER_CP_REMASK (0x64 >> 2) +#define CASPER_CP_LOCK (0x80 >> 2) +#define CASPER_CP_ID (0xFFC >> 2) +/* mcr (cp, opc1, value, CRn, CRm, opc2) */ +#define CASPER_Wr32b(value, off) __arm_mcr(CASPER_CP, 0, value, ((off >> 4)), (off), 0) +/* mcrr(coproc, opc1, value, CRm) */ +#define CASPER_Wr64b(value, off) __arm_mcrr(CASPER_CP, 0, value, off) +/* mrc(coproc, opc1, CRn, CRm, opc2) */ +#define CASPER_Rd32b(off) __arm_mrc(CASPER_CP, 0, ((off >> 4)), (off), 0) + +/* The model for this algo is that it can be implemented for a fixed size RSA key */ +/* for max speed. If this is made into a variable (to allow varying size), then */ +/* it will be slower by a bit. */ +/* The file is compiled with N_bitlen passed in as number of bits of the RSA key */ +/* #define N_bitlen 2048 */ +#define N_wordlen_max (4096U / 32U) + +enum +{ + kCASPER_RamOffset_Result = 0x0u, + kCASPER_RamOffset_Base = (N_wordlen_max + 8u), + kCASPER_RamOffset_TempBase = (2u * N_wordlen_max + 16u), + kCASPER_RamOffset_Modulus = (kCASPER_RamOffset_TempBase + N_wordlen_max + 4u), + kCASPER_RamOffset_M64 = 1022U, +}; + +/*! @} */ + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @addtogroup casper_driver + * @{ + */ + +/*! + * @brief Enables clock and disables reset for CASPER peripheral. + * + * Enable clock and disable reset for CASPER. + * + * @param base CASPER base address + */ +void CASPER_Init(CASPER_Type *base); + +/*! + * @brief Disables clock for CASPER peripheral. + * + * Disable clock and enable reset. + * + * @param base CASPER base address + */ +void CASPER_Deinit(CASPER_Type *base); + +/*! + *@} + */ /* end of casper_driver */ + +/******************************************************************************* + * PKHA API + ******************************************************************************/ + +/*! + * @addtogroup casper_driver_pkha + * @{ + */ + +/*! + * @brief Performs modular exponentiation - (A^E) mod N. + * + * This function performs modular exponentiation. + * + * @param base CASPER base address + * @param signature first addend (in little endian format) + * @param pubN modulus (in little endian format) + * @param wordLen Size of pubN in bytes + * @param pubE exponent + * @param[out] plaintext Output array to store result of operation (in little endian format) + */ +void CASPER_ModExp(CASPER_Type *base, + const uint8_t *signature, + const uint8_t *pubN, + size_t wordLen, + uint32_t pubE, + uint8_t *plaintext); + +/*! + * @brief Initialize prime modulus mod in Casper memory . + * + * Set the prime modulus mod in Casper memory and set N_wordlen + * according to selected algorithm. + * + * @param curve elliptic curve algoritm + */ +void CASPER_ecc_init(casper_algo_t curve); + +/*! + * @brief Performs ECC secp256r1 point single scalar multiplication + * + * This function performs ECC secp256r1 point single scalar multiplication + * [resX; resY] = scalar * [X; Y] + * Coordinates are affine in normal form, little endian. + * Scalars are little endian. + * All arrays are little endian byte arrays, uint32_t type is used + * only to enforce the 32-bit alignment (0-mod-4 address). + * + * @param base CASPER base address + * @param[out] resX Output X affine coordinate in normal form, little endian. + * @param[out] resY Output Y affine coordinate in normal form, little endian. + * @param X Input X affine coordinate in normal form, little endian. + * @param Y Input Y affine coordinate in normal form, little endian. + * @param scalar Input scalar integer, in normal form, little endian. + */ +void CASPER_ECC_SECP256R1_Mul( + CASPER_Type *base, uint32_t resX[8], uint32_t resY[8], uint32_t X[8], uint32_t Y[8], uint32_t scalar[8]); + +/*! + * @brief Performs ECC secp256r1 point double scalar multiplication + * + * This function performs ECC secp256r1 point double scalar multiplication + * [resX; resY] = scalar1 * [X1; Y1] + scalar2 * [X2; Y2] + * Coordinates are affine in normal form, little endian. + * Scalars are little endian. + * All arrays are little endian byte arrays, uint32_t type is used + * only to enforce the 32-bit alignment (0-mod-4 address). + * + * @param base CASPER base address + * @param[out] resX Output X affine coordinate. + * @param[out] resY Output Y affine coordinate. + * @param X1 Input X1 affine coordinate. + * @param Y1 Input Y1 affine coordinate. + * @param scalar1 Input scalar1 integer. + * @param X2 Input X2 affine coordinate. + * @param Y2 Input Y2 affine coordinate. + * @param scalar2 Input scalar2 integer. + */ +void CASPER_ECC_SECP256R1_MulAdd(CASPER_Type *base, + uint32_t resX[8], + uint32_t resY[8], + uint32_t X1[8], + uint32_t Y1[8], + uint32_t scalar1[8], + uint32_t X2[8], + uint32_t Y2[8], + uint32_t scalar2[8]); + +/*! + * @brief Performs ECC secp384r1 point single scalar multiplication + * + * This function performs ECC secp384r1 point single scalar multiplication + * [resX; resY] = scalar * [X; Y] + * Coordinates are affine in normal form, little endian. + * Scalars are little endian. + * All arrays are little endian byte arrays, uint32_t type is used + * only to enforce the 32-bit alignment (0-mod-4 address). + * + * @param base CASPER base address + * @param[out] resX Output X affine coordinate in normal form, little endian. + * @param[out] resY Output Y affine coordinate in normal form, little endian. + * @param X Input X affine coordinate in normal form, little endian. + * @param Y Input Y affine coordinate in normal form, little endian. + * @param scalar Input scalar integer, in normal form, little endian. + */ +void CASPER_ECC_SECP384R1_Mul( + CASPER_Type *base, uint32_t resX[12], uint32_t resY[12], uint32_t X[12], uint32_t Y[12], uint32_t scalar[12]); + +/*! + * @brief Performs ECC secp384r1 point double scalar multiplication + * + * This function performs ECC secp384r1 point double scalar multiplication + * [resX; resY] = scalar1 * [X1; Y1] + scalar2 * [X2; Y2] + * Coordinates are affine in normal form, little endian. + * Scalars are little endian. + * All arrays are little endian byte arrays, uint32_t type is used + * only to enforce the 32-bit alignment (0-mod-4 address). + * + * @param base CASPER base address + * @param[out] resX Output X affine coordinate. + * @param[out] resY Output Y affine coordinate. + * @param X1 Input X1 affine coordinate. + * @param Y1 Input Y1 affine coordinate. + * @param scalar1 Input scalar1 integer. + * @param X2 Input X2 affine coordinate. + * @param Y2 Input Y2 affine coordinate. + * @param scalar2 Input scalar2 integer. + */ +void CASPER_ECC_SECP384R1_MulAdd(CASPER_Type *base, + uint32_t resX[12], + uint32_t resY[12], + uint32_t X1[12], + uint32_t Y1[12], + uint32_t scalar1[12], + uint32_t X2[12], + uint32_t Y2[12], + uint32_t scalar2[12]); + +/*! + * @brief Performs ECC secp521r1 point single scalar multiplication + * + * This function performs ECC secp521r1 point single scalar multiplication + * [resX; resY] = scalar * [X; Y] + * Coordinates are affine in normal form, little endian. + * Scalars are little endian. + * All arrays are little endian byte arrays, uint32_t type is used + * only to enforce the 32-bit alignment (0-mod-4 address). + * + * @param base CASPER base address + * @param[out] resX Output X affine coordinate in normal form, little endian. + * @param[out] resY Output Y affine coordinate in normal form, little endian. + * @param X Input X affine coordinate in normal form, little endian. + * @param Y Input Y affine coordinate in normal form, little endian. + * @param scalar Input scalar integer, in normal form, little endian. + */ +void CASPER_ECC_SECP521R1_Mul( + CASPER_Type *base, uint32_t resX[18], uint32_t resY[18], uint32_t X[18], uint32_t Y[18], uint32_t scalar[18]); + +/*! + * @brief Performs ECC secp521r1 point double scalar multiplication + * + * This function performs ECC secp521r1 point double scalar multiplication + * [resX; resY] = scalar1 * [X1; Y1] + scalar2 * [X2; Y2] + * Coordinates are affine in normal form, little endian. + * Scalars are little endian. + * All arrays are little endian byte arrays, uint32_t type is used + * only to enforce the 32-bit alignment (0-mod-4 address). + * + * @param base CASPER base address + * @param[out] resX Output X affine coordinate. + * @param[out] resY Output Y affine coordinate. + * @param X1 Input X1 affine coordinate. + * @param Y1 Input Y1 affine coordinate. + * @param scalar1 Input scalar1 integer. + * @param X2 Input X2 affine coordinate. + * @param Y2 Input Y2 affine coordinate. + * @param scalar2 Input scalar2 integer. + */ +void CASPER_ECC_SECP521R1_MulAdd(CASPER_Type *base, + uint32_t resX[18], + uint32_t resY[18], + uint32_t X1[18], + uint32_t Y1[18], + uint32_t scalar1[18], + uint32_t X2[18], + uint32_t Y2[18], + uint32_t scalar2[18]); + +void CASPER_ECC_equal(int *res, uint32_t *op1, uint32_t *op2); +void CASPER_ECC_equal_to_zero(int *res, uint32_t *op1); + +/*! + *@} + */ /* end of casper_driver_pkha */ + +#if defined(__cplusplus) +} +#endif + +#endif /* _FSL_CASPER_H_ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_cdog.c b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_cdog.c new file mode 100644 index 0000000000..9b985e1cbd --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_cdog.c @@ -0,0 +1,314 @@ +/* + * Copyright 2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_cdog.h" + +/******************************************************************************* + * Definitions + *******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.cdog" +#endif + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ + +/*! + * brief Sets the default configuration of CDOG + * + * This function initialize CDOG config structure to default values. + * + * param conf CDOG configuration structure + */ +void CDOG_GetDefaultConfig(cdog_config_t *conf) +{ + /* Default configuration after reset */ + conf->lock = (uint8_t)kCDOG_LockCtrl_Unlock; /* Lock control */ + conf->timeout = (uint8_t)kCDOG_FaultCtrl_NoAction; /* Timeout control */ + conf->miscompare = (uint8_t)kCDOG_FaultCtrl_NoAction; /* Miscompare control */ + conf->sequence = (uint8_t)kCDOG_FaultCtrl_NoAction; /* Sequence control */ + conf->state = (uint8_t)kCDOG_FaultCtrl_NoAction; /* State control */ + conf->address = (uint8_t)kCDOG_FaultCtrl_NoAction; /* Address control */ + conf->irq_pause = (uint8_t)kCDOG_IrqPauseCtrl_Run; /* IRQ pause control */ + conf->debug_halt = (uint8_t)kCDOG_DebugHaltCtrl_Run; /* Debug halt control */ + return; +} + +/*! + * brief Sets secure counter and instruction timer values + * + * This function sets value in RELOAD and START registers for instruction timer. + * + * param base CDOG peripheral base address + * param reload reload value + * param start start value + */ +void CDOG_Start(CDOG_Type *base, uint32_t reload, uint32_t start) +{ + base->RELOAD = reload; + base->START = start; +} + +/*! + * brief Stops secure counter and instruction timer + * + * This function stops instruction timer and secure counter. + * This also change state of CDOG to IDLE. + * + * param base CDOG peripheral base address + * param stop expected value which will be compared with value of secure counter + */ +void CDOG_Stop(CDOG_Type *base, uint32_t stop) +{ + base->STOP = stop; +} + +/*! + * brief Sets secure counter and instruction timer values + * + * This function sets value in STOP, RELOAD and START registers + * for instruction timer and secure counter. + * + * param base CDOG peripheral base address + * param stop expected value which will be compared with value of secure counter + * param reload reload value for instruction timer + * param start start value for secure timer + */ +void CDOG_Set(CDOG_Type *base, uint32_t stop, uint32_t reload, uint32_t start) +{ + base->STOP = stop; + base->RELOAD = reload; + base->START = start; +} + +/*! + * brief Add value to secure counter + * + * This function add specified value to secure counter. + * + * param base CDOG peripheral base address. + * param add Value to be added. + */ +void CDOG_Add(CDOG_Type *base, uint32_t add) +{ + base->ADD = (secure_counter_t)add; +} + +/*! + * brief Add 1 to secure counter + * + * This function add 1 to secure counter. + * + * param base CDOG peripheral base address. + * param add Value to be added. + */ +void CDOG_Add1(CDOG_Type *base) +{ + base->ADD1 = (secure_counter_t)0x1U; +} + +/*! + * brief Add 16 to secure counter + * + * This function add 16 to secure counter. + * + * param base CDOG peripheral base address. + * param add Value to be added. + */ +void CDOG_Add16(CDOG_Type *base) +{ + base->ADD16 = (secure_counter_t)0x1U; +} + +/*! + * brief Add 256 to secure counter + * + * This function add 256 to secure counter. + * + * param base CDOG peripheral base address. + * param add Value to be added. + */ +void CDOG_Add256(CDOG_Type *base) +{ + base->ADD256 = (secure_counter_t)0x1U; +} + +/*! + * brief Substract value to secure counter + * + * This function substract specified value to secure counter. + * + * param base CDOG peripheral base address. + * param sub Value to be substracted. + */ +void CDOG_Sub(CDOG_Type *base, uint32_t sub) +{ + base->SUB = (secure_counter_t)sub; +} + +/*! + * brief Substract 1 from secure counter + * + * This function substract specified 1 from secure counter. + * + * param base CDOG peripheral base address. + */ +void CDOG_Sub1(CDOG_Type *base) +{ + base->SUB1 = (secure_counter_t)0x1U; +} + +/*! + * brief Substract 16 from secure counter + * + * This function substract specified 16 from secure counter. + * + * param base CDOG peripheral base address. + */ +void CDOG_Sub16(CDOG_Type *base) +{ + base->SUB16 = (secure_counter_t)0x1U; +} + +/*! + * brief Substract 256 from secure counter + * + * This function substract specified 256 from secure counter. + * + * param base CDOG peripheral base address. + */ +void CDOG_Sub256(CDOG_Type *base) +{ + base->SUB256 = (secure_counter_t)0x1U; +} + +/*! + * brief Checks secure counter. + * + * This function compares stop value with secure counter value + * by writting to RELOAD refister. + * + * param base CDOG peripheral base address + * param check expected (stop) value. + */ +void CDOG_Check(CDOG_Type *base, uint32_t check) +{ + base->RESTART = check; +} + +/*! + * brief Set the CDOG persistent word. + * + * param base CDOG peripheral base address. + * param value The value to be written. + */ +void CDOG_WritePersistent(CDOG_Type *base, uint32_t value) +{ + base->PERSISTENT = value; +} + +/*! + * brief Get the CDOG persistent word. + * + * param base CDOG peripheral base address. + * return The persistent word. + */ +uint32_t CDOG_ReadPersistent(CDOG_Type *base) +{ + return base->PERSISTENT; +} + +/*! + * brief Initialize CDOG + * + * This function initializes CDOG block and setting. + * + * param base CDOG peripheral base address + * param conf CDOG configuration structure + * return Status of the init operation + */ +status_t CDOG_Init(CDOG_Type *base, cdog_config_t *conf) +{ + /* Ungate clock to CDOG engine and reset it */ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +#ifdef CDOG_CLOCKS + CLOCK_EnableClock(kCLOCK_Cdog); +#endif /* CDOG_CLOCKS */ +#endif /* !FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if !(defined(FSL_FEATURE_CDOG_HAS_NO_RESET) && FSL_FEATURE_CDOG_HAS_NO_RESET) + RESET_PeripheralReset(kCDOG_RST_SHIFT_RSTn); +#endif /* !FSL_FEATURE_CDOG_HAS_NO_RESET */ + + if (base->CONTROL == 0x0U) + { + /* CDOG is not in IDLE mode, which may be cause after SW reset. */ + /* Writing to CONTROL register will trigger fault. */ + return kStatus_Fail; + } + + /* Clear pending errors, otherwise the device will reset */ + /* itself immediately after enable Code Watchdog */ + if ((uint32_t)kCDOG_LockCtrl_Lock == + ((base->CONTROL & CDOG_CONTROL_LOCK_CTRL_MASK) >> CDOG_CONTROL_LOCK_CTRL_SHIFT)) + + { + CDOG->FLAGS = CDOG_FLAGS_TO_FLAG(1U) | CDOG_FLAGS_MISCOM_FLAG(1U) | CDOG_FLAGS_SEQ_FLAG(1U) | + CDOG_FLAGS_CNT_FLAG(1U) | CDOG_FLAGS_STATE_FLAG(1U) | CDOG_FLAGS_ADDR_FLAG(1U) | + CDOG_FLAGS_POR_FLAG(1U); + } + else + { + CDOG->FLAGS = CDOG_FLAGS_TO_FLAG(0U) | CDOG_FLAGS_MISCOM_FLAG(0U) | CDOG_FLAGS_SEQ_FLAG(0U) | + CDOG_FLAGS_CNT_FLAG(0U) | CDOG_FLAGS_STATE_FLAG(0U) | CDOG_FLAGS_ADDR_FLAG(0U) | + CDOG_FLAGS_POR_FLAG(0U); + } + + base->CONTROL = + CDOG_CONTROL_TIMEOUT_CTRL(conf->timeout) | /* Action if the timeout event is triggered */ + CDOG_CONTROL_MISCOMPARE_CTRL(conf->miscompare) | /* Action if the miscompare error event is triggered */ + CDOG_CONTROL_SEQUENCE_CTRL(conf->sequence) | /* Action if the sequence error event is triggered */ + CDOG_CONTROL_STATE_CTRL(conf->state) | /* Action if the state error event is triggered */ + CDOG_CONTROL_ADDRESS_CTRL(conf->address) | /* Action if the address error event is triggered */ + CDOG_CONTROL_IRQ_PAUSE(conf->irq_pause) | /* Pause running during interrupts setup */ + CDOG_CONTROL_DEBUG_HALT_CTRL( + conf->debug_halt) | /* Halt CDOG timer during debug so we have chance to debug code */ + CDOG_CONTROL_LOCK_CTRL(conf->lock); /* Lock control register */ + + NVIC_EnableIRQ(CDOG_IRQn); + + return kStatus_Success; +} + +/*! + * brief Deinitialize CDOG + * + * This function stops CDOG secure counter. + * + * param base CDOG peripheral base address + */ +void CDOG_Deinit(CDOG_Type *base) +{ + NVIC_DisableIRQ(CDOG_IRQn); + +#if !(defined(FSL_FEATURE_CDOG_HAS_NO_RESET) && FSL_FEATURE_CDOG_HAS_NO_RESET) + RESET_SetPeripheralReset(kCDOG_RST_SHIFT_RSTn); +#endif /* !FSL_FEATURE_CDOG_HAS_NO_RESET */ + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +#ifdef CDOG_CLOCKS + CLOCK_DisableClock(kCLOCK_Cdog); +#endif /* CDOG_CLOCKS */ +#endif /* !FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} diff --git a/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_cdog.h b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_cdog.h new file mode 100644 index 0000000000..b93c8dbdfe --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_cdog.h @@ -0,0 +1,325 @@ +/* + * Copyright 2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_CDOG_H_ +#define _FSL_CDOG_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup CDOG + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + *******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief Defines CDOG driver version 2.1.1. + * + * Change log: + * - Version 2.1.1 + * - Remove bit CONTROL[CONTROL_CTRL] + * - Version 2.1.0 + * - Rename CWT to CDOG + * - Version 2.0.2 + * - Fix MISRA-2012 issues + * - Version 2.0.1 + * - Fix doxygen issues + * - Version 2.0.0 + * - initial version + */ +#define FSL_CDOG_DRIVER_VERSION (MAKE_VERSION(2, 1, 1)) +/*@}*/ + +typedef struct +{ + uint8_t lock : 2; + uint8_t timeout : 3; + uint8_t miscompare : 3; + uint8_t sequence : 3; + uint8_t state : 3; + uint8_t address : 3; + uint8_t reserved : 8; + uint8_t irq_pause : 2; + uint8_t debug_halt : 2; +} cdog_config_t; + +enum __cdog_debug_Action_ctrl_enum +{ + kCDOG_DebugHaltCtrl_Run = 0x1, + kCDOG_DebugHaltCtrl_Pause = 0x2, +}; + +enum __cdog_irq_pause_ctrl_enum +{ + kCDOG_IrqPauseCtrl_Run = 0x1, + kCDOG_IrqPauseCtrl_Pause = 0x2, +}; + +enum __cdog_fault_ctrl_enum +{ + kCDOG_FaultCtrl_EnableReset = 0x1U, + kCDOG_FaultCtrl_EnableInterrupt = 0x2U, + kCDOG_FaultCtrl_NoAction = 0x4U, +}; + +enum __code_lock_ctrl_enum +{ + kCDOG_LockCtrl_Lock = 0x1, + kCDOG_LockCtrl_Unlock = 0x2, +}; + +typedef uint32_t secure_counter_t; + +#define SC_ADD(add) \ + do \ + { \ + CDOG->ADD = (secure_counter_t)(add); \ + } while (0) + +#define SC_ADD1 \ + do \ + { \ + CDOG->ADD1 = (secure_counter_t)0x1U; \ + } while (0) + +#define SC_ADD16 \ + do \ + { \ + CDOG->ADD16 = (secure_counter_t)0x1U; \ + } while (0) + +#define SC_ADD256 \ + do \ + { \ + CDOG->ADD256 = (secure_counter_t)0x1U; \ + } while (0) + +#define SC_SUB(sub) \ + do \ + { \ + CDOG->SUB = (secure_counter_t)(sub); \ + } while (0) + +#define SC_SUB1 \ + do \ + { \ + CDOG->SUB1 = (secure_counter_t)0x1U; \ + } while (0) + +#define SC_SUB16 \ + do \ + { \ + CDOG->SUB16 = (secure_counter_t)0x1U; \ + } while (0) + +#define SC_SUB256 \ + do \ + { \ + CDOG->SUB256 = (secure_counter_t)0x1U; \ + } while (0) + +#define SC_CHECK(val) \ + do \ + { \ + CDOG->RESTART = (secure_counter_t)val; \ + } while (0) + +/******************************************************************************* + * API + *******************************************************************************/ + +extern void CDOG_DriverIRQHandler(void); + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/*! + * @name CDOG Functional Operation + * @{ + */ + +/*! + * @brief Initialize CDOG + * + * This function initializes CDOG block and setting. + * + * @param base CDOG peripheral base address + * @param conf CDOG configuration structure + * @return Status of the init operation + */ +status_t CDOG_Init(CDOG_Type *base, cdog_config_t *conf); + +/*! + * @brief Deinitialize CDOG + * + * This function deinitializes CDOG secure counter. + * + * @param base CDOG peripheral base address + */ +void CDOG_Deinit(CDOG_Type *base); + +/*! + * @brief Sets the default configuration of CDOG + * + * This function initialize CDOG config structure to default values. + * + * @param conf CDOG configuration structure + */ +void CDOG_GetDefaultConfig(cdog_config_t *conf); + +/*! + * @brief Stops secure counter and instruction timer + * + * This function stops instruction timer and secure counter. + * This also change state od CDOG to IDLE. + * + * @param base CDOG peripheral base address + * @param stop expected value which will be compared with value of secure counter + */ +void CDOG_Stop(CDOG_Type *base, uint32_t stop); + +/*! + * @brief Sets secure counter and instruction timer values + * + * This function sets value in RELOAD and START registers + * for instruction timer and secure counter + * + * @param base CDOG peripheral base address + * @param reload reload value + * @param start start value + */ +void CDOG_Start(CDOG_Type *base, uint32_t reload, uint32_t start); + +/*! + * @brief Checks secure counter. + * + * This function compares stop value in handler with secure counter value + * by writting to RELOAD refister. + * + * @param base CDOG peripheral base address + * @param check expected (stop) value + */ +void CDOG_Check(CDOG_Type *base, uint32_t check); + +/*! + * @brief Sets secure counter and instruction timer values + * + * This function sets value in STOP, RELOAD and START registers + * for instruction timer and secure counter. + * + * @param base CDOG peripheral base address + * @param stop expected value which will be compared with value of secure counter + * @param reload reload value for instruction timer + * @param start start value for secure timer + */ +void CDOG_Set(CDOG_Type *base, uint32_t stop, uint32_t reload, uint32_t start); + +/*! + * @brief Add value to secure counter + * + * This function add specified value to secure counter. + * + * @param base CDOG peripheral base address. + * @param add Value to be added. + */ +void CDOG_Add(CDOG_Type *base, uint32_t add); + +/*! + * @brief Add 1 to secure counter + * + * This function add 1 to secure counter. + * + * @param base CDOG peripheral base address. + */ +void CDOG_Add1(CDOG_Type *base); + +/*! + * @brief Add 16 to secure counter + * + * This function add 16 to secure counter. + * + * @param base CDOG peripheral base address. + */ +void CDOG_Add16(CDOG_Type *base); + +/*! + * @brief Add 256 to secure counter + * + * This function add 256 to secure counter. + * + * @param base CDOG peripheral base address. + */ +void CDOG_Add256(CDOG_Type *base); + +/*! + * brief Substract value to secure counter + * + * This function substract specified value to secure counter. + * + * param base CDOG peripheral base address. + * param sub Value to be substracted. + */ +void CDOG_Sub(CDOG_Type *base, uint32_t sub); + +/*! + * @brief Substract 1 from secure counter + * + * This function substract specified 1 from secure counter. + * + * @param base CDOG peripheral base address. + */ +void CDOG_Sub1(CDOG_Type *base); + +/*! + * @brief Substract 16 from secure counter + * + * This function substract specified 16 from secure counter. + * + * @param base CDOG peripheral base address. + */ +void CDOG_Sub16(CDOG_Type *base); + +/*! + * @brief Substract 256 from secure counter + * + * This function substract specified 256 from secure counter. + * + * @param base CDOG peripheral base address. + */ +void CDOG_Sub256(CDOG_Type *base); + +/*! + * @brief Set the CDOG persistent word. + * + * @param base CDOG peripheral base address. + * @param value The value to be written. + */ +void CDOG_WritePersistent(CDOG_Type *base, uint32_t value); + +/*! + * @brief Get the CDOG persistent word. + * + * @param base CDOG peripheral base address. + * @return The persistent word. + */ +uint32_t CDOG_ReadPersistent(CDOG_Type *base); + +/*! @}*/ + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +/*! @}*/ /* end of group cdog */ + +#endif /* _FSL_CDOG_H_ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_clock.c b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_clock.c new file mode 100644 index 0000000000..8a3be03261 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_clock.c @@ -0,0 +1,2179 @@ +/* + * Copyright 2017 - 2021 , NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_clock.h" +#include "fsl_power.h" +/******************************************************************************* + * Definitions + ******************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.clock" +#endif +#define NVALMAX (0x100U) +#define PVALMAX (0x20U) +#define MVALMAX (0x10000U) + +#define PLL_MAX_N_DIV 0x100U + +/*-------------------------------------------------------------------------- +!!! If required these #defines can be moved to chip library file +----------------------------------------------------------------------------*/ + +#define PLL_SSCG1_MDEC_VAL_P (10U) /* MDEC is in bits 25 downto 10 */ +#define PLL_SSCG1_MDEC_VAL_M (0xFFFFULL << PLL_SSCG1_MDEC_VAL_P) +#define PLL_NDEC_VAL_P (0U) /* NDEC is in bits 9:0 */ +#define PLL_NDEC_VAL_M (0xFFUL << PLL_NDEC_VAL_P) +#define PLL_PDEC_VAL_P (0U) /*!< PDEC is in bits 6:0 */ +#define PLL_PDEC_VAL_M (0x1FUL << PLL_PDEC_VAL_P) + +#define PLL_MIN_CCO_FREQ_MHZ (275000000U) +#define PLL_MAX_CCO_FREQ_MHZ (550000000U) +#define PLL_LOWER_IN_LIMIT (2000U) /*!< Minimum PLL input rate */ +#define PLL_HIGHER_IN_LIMIT (150000000U) /*!< Maximum PLL input rate */ +#define PLL_MIN_IN_SSMODE (3000000U) +#define PLL_MAX_IN_SSMODE \ + (100000000U) /*!< Not find the value in UM, Just use the maximum frequency which device support */ + +/* PLL NDEC reg */ +#define PLL_NDEC_VAL_SET(value) (((unsigned long)(value) << PLL_NDEC_VAL_P) & PLL_NDEC_VAL_M) +/* PLL PDEC reg */ +#define PLL_PDEC_VAL_SET(value) (((unsigned long)(value) << PLL_PDEC_VAL_P) & PLL_PDEC_VAL_M) +/* SSCG control1 */ +#define PLL_SSCG1_MDEC_VAL_SET(value) (((uint64_t)(value) << PLL_SSCG1_MDEC_VAL_P) & PLL_SSCG1_MDEC_VAL_M) + +/* PLL0 SSCG control1 */ +#define PLL0_SSCG_MD_FRACT_P 0U +#define PLL0_SSCG_MD_INT_P 25U +#define PLL0_SSCG_MD_FRACT_M (0x1FFFFFFUL << PLL0_SSCG_MD_FRACT_P) +#define PLL0_SSCG_MD_INT_M ((uint64_t)0xFFUL << PLL0_SSCG_MD_INT_P) + +#define PLL0_SSCG_MD_FRACT_SET(value) (((uint64_t)(value) << PLL0_SSCG_MD_FRACT_P) & PLL0_SSCG_MD_FRACT_M) +#define PLL0_SSCG_MD_INT_SET(value) (((uint64_t)(value) << PLL0_SSCG_MD_INT_P) & PLL0_SSCG_MD_INT_M) + +/* Saved value of PLL output rate, computed whenever needed to save run-time + computation on each call to retrive the PLL rate. */ +static uint32_t s_Pll0_Freq; +static uint32_t s_Pll1_Freq; + +/** External clock rate on the CLKIN pin in Hz. If not used, + set this to 0. Otherwise, set it to the exact rate in Hz this pin is + being driven at. */ +static uint32_t s_Ext_Clk_Freq = 16000000U; +static uint32_t s_I2S_Mclk_Freq = 0U; +static uint32_t s_PLU_ClkIn_Freq = 0U; + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/* Find SELP, SELI, and SELR values for raw M value, max M = MVALMAX */ +static void pllFindSel(uint32_t M, uint32_t *pSelP, uint32_t *pSelI, uint32_t *pSelR); +/* Get predivider (N) from PLL0 NDEC setting */ +static uint32_t findPll0PreDiv(void); +/* Get predivider (N) from PLL1 NDEC setting */ +static uint32_t findPll1PreDiv(void); +/* Get postdivider (P) from PLL0 PDEC setting */ +static uint32_t findPll0PostDiv(void); +/* Get postdivider (P) from PLL1 PDEC setting. */ +static uint32_t findPll1PostDiv(void); +/* Get multiplier (M) from PLL0 MDEC and SSCG settings */ +static float findPll0MMult(void); +/* Get multiplier (M) from PLL1 MDEC. */ +static uint32_t findPll1MMult(void); +/* Get the greatest common divisor */ +static uint32_t FindGreatestCommonDivisor(uint32_t m, uint32_t n); +/* Set PLL output based on desired output rate */ +static pll_error_t CLOCK_GetPll0Config(uint32_t finHz, uint32_t foutHz, pll_setup_t *pSetup, bool useSS); +/* Update local PLL rate variable */ +static void CLOCK_GetPLL0OutFromSetupUpdate(pll_setup_t *pSetup); +/* Update local PLL1 rate variable */ +static void CLOCK_GetPLL1OutFromSetupUpdate(pll_setup_t *pSetup); + +/******************************************************************************* + * Code + ******************************************************************************/ + +/* Clock Selection for IP */ +/** + * brief Configure the clock selection muxes. + * param connection : Clock to be configured. + * return Nothing + */ +void CLOCK_AttachClk(clock_attach_id_t connection) +{ + uint8_t mux; + uint8_t sel; + uint16_t item; + uint32_t tmp32 = (uint32_t)connection; + uint32_t i; + volatile uint32_t *pClkSel; + + pClkSel = &(SYSCON->SYSTICKCLKSELX[0]); + + if (kNONE_to_NONE != connection) + { + for (i = 0U; i < 2U; i++) + { + if (tmp32 == 0U) + { + break; + } + item = (uint16_t)GET_ID_ITEM(tmp32); + if (item != 0U) + { + mux = (uint8_t)GET_ID_ITEM_MUX(item); + sel = (uint8_t)GET_ID_ITEM_SEL(item); + if (mux == CM_RTCOSC32KCLKSEL) + { + PMC->RTCOSC32K = (PMC->RTCOSC32K & ~PMC_RTCOSC32K_SEL_MASK) | PMC_RTCOSC32K_SEL(sel); + } + else if (mux == CM_OSTIMERCLKSEL) + { + PMC->OSTIMERr = (PMC->OSTIMERr & ~PMC_OSTIMER_OSTIMERCLKSEL_MASK) | PMC_OSTIMER_OSTIMERCLKSEL(sel); + } + else + { + pClkSel[mux] = sel; + } + } + tmp32 = GET_ID_NEXT_ITEM(tmp32); /* pick up next descriptor */ + } + } +} + +/* Return the actual clock attach id */ +/** + * brief Get the actual clock attach id. + * This fuction uses the offset in input attach id, then it reads the actual source value in + * the register and combine the offset to obtain an actual attach id. + * param attachId : Clock attach id to get. + * return Clock source value. + */ +clock_attach_id_t CLOCK_GetClockAttachId(clock_attach_id_t attachId) +{ + uint8_t mux; + uint32_t actualSel; + uint32_t tmp32 = (uint32_t)attachId; + uint32_t i; + uint32_t actualAttachId = 0U; + uint32_t selector = GET_ID_SELECTOR(tmp32); + volatile uint32_t *pClkSel; + + pClkSel = &(SYSCON->SYSTICKCLKSELX[0]); + + if (kNONE_to_NONE == attachId) + { + return kNONE_to_NONE; + } + + for (i = 0U; i < 2U; i++) + { + mux = (uint8_t)GET_ID_ITEM_MUX(tmp32); + if (tmp32 != 0UL) + { + if (mux == CM_RTCOSC32KCLKSEL) + { + actualSel = ((PMC->RTCOSC32K) & PMC_RTCOSC32K_SEL_MASK) >> PMC_RTCOSC32K_SEL_SHIFT; + } + else if (mux == CM_OSTIMERCLKSEL) + { + actualSel = ((PMC->OSTIMERr) & PMC_OSTIMER_OSTIMERCLKSEL_MASK) >> PMC_OSTIMER_OSTIMERCLKSEL_SHIFT; + } + else + { + actualSel = pClkSel[mux]; + } + + /* Consider the combination of two registers */ + actualAttachId |= CLK_ATTACH_ID(mux, actualSel, i); + } + tmp32 = GET_ID_NEXT_ITEM(tmp32); /*!< pick up next descriptor */ + } + + actualAttachId |= selector; + + return (clock_attach_id_t)actualAttachId; +} + +/* Set IP Clock Divider */ +/** + * brief Setup peripheral clock dividers. + * param div_name : Clock divider name + * param divided_by_value: Value to be divided + * param reset : Whether to reset the divider counter. + * return Nothing + */ +void CLOCK_SetClkDiv(clock_div_name_t div_name, uint32_t divided_by_value, bool reset) +{ + volatile uint32_t *pClkDiv; + + pClkDiv = &(SYSCON->SYSTICKCLKDIV0); + if ((div_name >= kCLOCK_DivFlexFrg0) && (div_name <= kCLOCK_DivFlexFrg7)) + { + /*!< Flexcomm Interface function clock = (clock selected via FCCLKSEL) / (1+ MULT /DIV), DIV = 0xFF */ + ((volatile uint32_t *)pClkDiv)[(uint8_t)div_name] = + SYSCON_FLEXFRG0CTRL_DIV_MASK | SYSCON_FLEXFRG0CTRL_MULT(divided_by_value); + } + else + { + if (reset) + { + ((volatile uint32_t *)pClkDiv)[(uint8_t)div_name] = 1UL << 29U; + } + if (divided_by_value == 0U) /*!< halt */ + { + ((volatile uint32_t *)pClkDiv)[(uint8_t)div_name] = 1UL << 30U; + } + else + { + ((volatile uint32_t *)pClkDiv)[(uint8_t)div_name] = (divided_by_value - 1U); + } + } +} + +/* Set RTC 1KHz Clock Divider */ +/** + * brief Setup rtc 1khz clock divider. + * param divided_by_value: Value to be divided + * return Nothing + */ +void CLOCK_SetRtc1khzClkDiv(uint32_t divided_by_value) +{ + PMC->RTCOSC32K = + (PMC->RTCOSC32K & ~PMC_RTCOSC32K_CLK1KHZDIV_MASK) | PMC_RTCOSC32K_CLK1KHZDIV(divided_by_value - 28U); +} + +/* Set RTC 1KHz Clock Divider */ +/** + * brief Setup rtc 1hz clock divider. + * param divided_by_value: Value to be divided + * return Nothing + */ +void CLOCK_SetRtc1hzClkDiv(uint32_t divided_by_value) +{ + if (divided_by_value == 0U) /*!< halt */ + { + PMC->RTCOSC32K |= (1UL << PMC_RTCOSC32K_CLK1HZDIVHALT_SHIFT); + } + else + { + PMC->RTCOSC32K = + (PMC->RTCOSC32K & ~PMC_RTCOSC32K_CLK1HZDIV_MASK) | PMC_RTCOSC32K_CLK1HZDIV(divided_by_value - 31744U); + } +} + +/* Set FRO Clocking */ +/** + * brief Initialize the Core clock to given frequency (12, 48 or 96 MHz). + * Turns on FRO and uses default CCO, if freq is 12000000, then high speed output is off, else high speed output is + * enabled. + * param iFreq : Desired frequency (must be one of #CLK_FRO_12MHZ or #CLK_FRO_48MHZ or #CLK_FRO_96MHZ) + * return returns success or fail status. + */ +status_t CLOCK_SetupFROClocking(uint32_t iFreq) +{ + if ((iFreq != 12000000U) && (iFreq != 96000000U)) + { + return kStatus_Fail; + } + /* Enable Analog Control module */ + SYSCON->PRESETCTRLCLR[2] = (1UL << SYSCON_PRESETCTRL2_ANALOG_CTRL_RST_SHIFT); + SYSCON->AHBCLKCTRLSET[2] = SYSCON_AHBCLKCTRL2_ANALOG_CTRL_MASK; + /* Power up the FRO192M */ + POWER_DisablePD(kPDRUNCFG_PD_FRO192M); + + if (iFreq == 96000000U) + { + ANACTRL->FRO192M_CTRL |= ANACTRL_FRO192M_CTRL_ENA_96MHZCLK(1); + } + /* always enable + else if (iFreq == 48000000U) + { + ANACTRL->FRO192M_CTRL |= ANACTRL_FRO192M_CTRL_ENA_48MHZCLK(1); + }*/ + else + { + ANACTRL->FRO192M_CTRL |= ANACTRL_FRO192M_CTRL_ENA_12MHZCLK(1); + } + return kStatus_Success; +} + +/* Set the FLASH wait states for the passed frequency */ +/** + * brief Set the flash wait states for the input freuqency. + * param iFreq: Input frequency + * return Nothing + */ +typedef struct +{ + uint32_t waitstate; + uint32_t freqMax; +} WaitStateInterval_t; + +/* clang-format off */ +/* Wait state if frequency is inferior to the one specified */ +static const WaitStateInterval_t IntervalList[] = { + {0, 11000000}, + {1, 22000000}, + {2, 33000000}, + {3, 44000000}, + {4, 55000000}, + {5, 66000000}, + {6, 84000000}, + {7, 104000000}, + {8, 119000000}, + {9, 129000000}, + {10, 144000000}, + {11, 150000000} /* Maximum allowed frequency (150 MHz) */ +}; +/* clang-format on */ + +void CLOCK_SetFLASHAccessCyclesForFreq(uint32_t system_freq_hz) +{ + /* Flash Controller & FMC internal number of Wait States (minus 1) */ + uint32_t num_wait_states = 15UL; /* Default to the maximum number of wait states */ + + for (size_t cnt = 0; cnt < (sizeof(IntervalList) / sizeof(WaitStateInterval_t)); cnt++) + { + if (system_freq_hz <= IntervalList[cnt].freqMax) + { + num_wait_states = IntervalList[cnt].waitstate; + break; + } + } + + FLASH->INT_CLR_STATUS = 0x1F; /* Clear all status flags */ + + FLASH->DATAW[0] = (FLASH->DATAW[0] & 0xFFFFFFF0UL) | + (num_wait_states & (SYSCON_FMCCR_FLASHTIM_MASK >> SYSCON_FMCCR_FLASHTIM_SHIFT)); + + FLASH->CMD = 0x2; /* CMD_SET_READ_MODE */ + + /* Wait until the cmd is completed (without error) */ + while ((FLASH->INT_STATUS & FLASH_INT_STATUS_DONE_MASK) == 0UL) + { + } + + /* Adjust FMC waiting time cycles (num_wait_states) */ + SYSCON->FMCCR = (SYSCON->FMCCR & ~SYSCON_FMCCR_FLASHTIM_MASK) | + ((num_wait_states << SYSCON_FMCCR_FLASHTIM_SHIFT) & SYSCON_FMCCR_FLASHTIM_MASK); +} + +/* Set EXT OSC Clk */ +/** + * brief Initialize the external osc clock to given frequency. + * Crystal oscillator with an operating frequency of 12 MHz to 32 MHz. + * Option for external clock input (bypass mode) for clock frequencies of up to 25 MHz. + * param iFreq : Desired frequency (must be equal to exact rate in Hz) + * return returns success or fail status. + */ +status_t CLOCK_SetupExtClocking(uint32_t iFreq) +{ + if (iFreq > 32000000U) + { + return kStatus_Fail; + } + /* Turn on power for crystal 32 MHz */ + POWER_DisablePD(kPDRUNCFG_PD_XTAL32M); + POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M); + /* Enable clock_in clock for clock module. */ + SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK; + + s_Ext_Clk_Freq = iFreq; + return kStatus_Success; +} + +/* Set I2S MCLK Clk */ +/** + * brief Initialize the I2S MCLK clock to given frequency. + * param iFreq : Desired frequency (must be equal to exact rate in Hz) + * return returns success or fail status. + */ +status_t CLOCK_SetupI2SMClkClocking(uint32_t iFreq) +{ + s_I2S_Mclk_Freq = iFreq; + return kStatus_Success; +} + +/* Set PLU CLKIN Clk */ +/** + * brief Initialize the PLU CLKIN clock to given frequency. + * param iFreq : Desired frequency (must be equal to exact rate in Hz) + * return returns success or fail status. + */ +status_t CLOCK_SetupPLUClkInClocking(uint32_t iFreq) +{ + s_PLU_ClkIn_Freq = iFreq; + return kStatus_Success; +} + +/* Get CLOCK OUT Clk */ +/*! brief Return Frequency of ClockOut + * return Frequency of ClockOut + */ +uint32_t CLOCK_GetClockOutClkFreq(void) +{ + uint32_t freq = 0U; + + switch (SYSCON->CLKOUTSEL) + { + case 0U: + freq = CLOCK_GetCoreSysClkFreq(); + break; + + case 1U: + freq = CLOCK_GetPll0OutFreq(); + break; + + case 2U: + freq = CLOCK_GetExtClkFreq(); + break; + + case 3U: + freq = CLOCK_GetFroHfFreq(); + break; + + case 4U: + freq = CLOCK_GetFro1MFreq(); + break; + + case 5U: + freq = CLOCK_GetPll1OutFreq(); + break; + + case 6U: + freq = CLOCK_GetOsc32KFreq(); + break; + + case 7U: + freq = 0U; + break; + + default: + freq = 0U; + break; + } + return freq / ((SYSCON->CLKOUTDIV & 0xffU) + 1U); +} + +/* Get CAN Clk */ +/*! brief Return Frequency of Can Clock + * return Frequency of Can. + */ +uint32_t CLOCK_GetMCanClkFreq(void) +{ + uint32_t freq = 0U; + + switch (SYSCON->CANCLKSEL) + { + case 0U: + freq = CLOCK_GetCoreSysClkFreq() / ((SYSCON->CANCLKDIV & SYSCON_CANCLKDIV_DIV_MASK) + 1U); + break; + case 1U: + freq = CLOCK_GetFro1MFreq(); + break; + case 2U: + freq = CLOCK_GetOsc32KFreq(); + break; + case 7U: + freq = 0U; + break; + + default: + freq = 0U; + break; + } + + return freq; +} + +/* Get ADC Clk */ +/*! brief Return Frequency of Adc Clock + * return Frequency of Adc. + */ +uint32_t CLOCK_GetAdcClkFreq(void) +{ + uint32_t freq = 0U; + + switch (SYSCON->ADCCLKSEL) + { + case 0U: + freq = CLOCK_GetCoreSysClkFreq(); + break; + case 1U: + freq = CLOCK_GetPll0OutFreq(); + break; + case 2U: + freq = CLOCK_GetFroHfFreq(); + break; + case 7U: + freq = 0U; + break; + + default: + freq = 0U; + break; + } + + return freq / ((SYSCON->ADCCLKDIV & SYSCON_ADCCLKDIV_DIV_MASK) + 1U); +} + +/* Get USB0 Clk */ +/*! brief Return Frequency of Usb0 Clock + * return Frequency of Usb0 Clock. + */ +uint32_t CLOCK_GetUsb0ClkFreq(void) +{ + uint32_t freq = 0U; + + switch (SYSCON->USB0CLKSEL) + { + case 0U: + freq = CLOCK_GetCoreSysClkFreq(); + break; + case 1U: + freq = CLOCK_GetPll0OutFreq(); + break; + case 3U: + freq = CLOCK_GetFroHfFreq(); + break; + case 5U: + freq = CLOCK_GetPll1OutFreq(); + break; + case 7U: + freq = 0U; + break; + + default: + freq = 0U; + break; + } + + return freq / ((SYSCON->USB0CLKDIV & 0xffU) + 1U); +} + +/* Get USB1 Clk */ +/*! brief Return Frequency of Usb1 Clock + * return Frequency of Usb1 Clock. + */ +uint32_t CLOCK_GetUsb1ClkFreq(void) +{ + return ((ANACTRL->XO32M_CTRL & ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_MASK) != 0UL) ? s_Ext_Clk_Freq : 0U; +} + +/* Get MCLK Clk */ +/*! brief Return Frequency of MClk Clock + * return Frequency of MClk Clock. + */ +uint32_t CLOCK_GetMclkClkFreq(void) +{ + uint32_t freq = 0U; + + switch (SYSCON->MCLKCLKSEL) + { + case 0U: + freq = CLOCK_GetFroHfFreq(); + break; + case 1U: + freq = CLOCK_GetPll0OutFreq(); + break; + case 7U: + freq = 0U; + break; + + default: + freq = 0U; + break; + } + + return freq / ((SYSCON->MCLKDIV & 0xffU) + 1U); +} + +/* Get SCTIMER Clk */ +/*! brief Return Frequency of SCTimer Clock + * return Frequency of SCTimer Clock. + */ +uint32_t CLOCK_GetSctClkFreq(void) +{ + uint32_t freq = 0U; + + switch (SYSCON->SCTCLKSEL) + { + case 0U: + freq = CLOCK_GetCoreSysClkFreq(); + break; + case 1U: + freq = CLOCK_GetPll0OutFreq(); + break; + case 2U: + freq = CLOCK_GetExtClkFreq(); + break; + case 3U: + freq = CLOCK_GetFroHfFreq(); + break; + case 5U: + freq = CLOCK_GetI2SMClkFreq(); + break; + case 7U: + freq = 0U; + break; + + default: + freq = 0U; + break; + } + + return freq / ((SYSCON->SCTCLKDIV & 0xffU) + 1U); +} + +/* Get FRO 12M Clk */ +/*! brief Return Frequency of FRO 12MHz + * return Frequency of FRO 12MHz + */ +uint32_t CLOCK_GetFro12MFreq(void) +{ + return ((ANACTRL->FRO192M_CTRL & ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_MASK) != 0UL) ? 12000000U : 0U; +} + +/* Get FRO 1M Clk */ +/*! brief Return Frequency of FRO 1MHz + * return Frequency of FRO 1MHz + */ +uint32_t CLOCK_GetFro1MFreq(void) +{ + return ((SYSCON->CLOCK_CTRL & SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_MASK) != 0UL) ? 1000000U : 0U; +} + +/* Get EXT OSC Clk */ +/*! brief Return Frequency of External Clock + * return Frequency of External Clock. If no external clock is used returns 0. + */ +uint32_t CLOCK_GetExtClkFreq(void) +{ + return ((ANACTRL->XO32M_CTRL & ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK) != 0UL) ? s_Ext_Clk_Freq : 0U; +} + +/* Get WATCH DOG Clk */ +/*! brief Return Frequency of Watchdog + * return Frequency of Watchdog + */ +uint32_t CLOCK_GetWdtClkFreq(void) +{ + return CLOCK_GetFro1MFreq() / ((SYSCON->WDTCLKDIV & SYSCON_WDTCLKDIV_DIV_MASK) + 1U); +} + +/* Get HF FRO Clk */ +/*! brief Return Frequency of High-Freq output of FRO + * return Frequency of High-Freq output of FRO + */ +uint32_t CLOCK_GetFroHfFreq(void) +{ + return ((ANACTRL->FRO192M_CTRL & ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK) != 0UL) ? 96000000U : 0U; +} + +/* Get SYSTEM PLL Clk */ +/*! brief Return Frequency of PLL + * return Frequency of PLL + */ +uint32_t CLOCK_GetPll0OutFreq(void) +{ + return s_Pll0_Freq; +} + +/* Get USB PLL Clk */ +/*! brief Return Frequency of USB PLL + * return Frequency of PLL + */ +uint32_t CLOCK_GetPll1OutFreq(void) +{ + return s_Pll1_Freq; +} + +/* Get RTC OSC Clk */ +/*! brief Return Frequency of 32kHz osc + * return Frequency of 32kHz osc + */ +uint32_t CLOCK_GetOsc32KFreq(void) +{ + return ((0UL == (PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_FRO32K_MASK)) && + (0UL == (PMC->RTCOSC32K & PMC_RTCOSC32K_SEL_MASK))) ? + CLK_RTC_32K_CLK : + ((0UL == (PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_XTAL32K_MASK)) && + ((PMC->RTCOSC32K & PMC_RTCOSC32K_SEL_MASK) != 0UL)) ? + CLK_RTC_32K_CLK : + 0UL; +} + +/* Get MAIN Clk */ +/*! brief Return Frequency of Core System + * return Frequency of Core System + */ +uint32_t CLOCK_GetCoreSysClkFreq(void) +{ + uint32_t freq = 0U; + + switch (SYSCON->MAINCLKSELB) + { + case 0U: + if (SYSCON->MAINCLKSELA == 0U) + { + freq = CLOCK_GetFro12MFreq(); + } + else if (SYSCON->MAINCLKSELA == 1U) + { + freq = CLOCK_GetExtClkFreq(); + } + else if (SYSCON->MAINCLKSELA == 2U) + { + freq = CLOCK_GetFro1MFreq(); + } + else if (SYSCON->MAINCLKSELA == 3U) + { + freq = CLOCK_GetFroHfFreq(); + } + else + { + /* Added comments to avoid the violation of MISRA C-2012 rule 15.7 */ + } + break; + case 1U: + freq = CLOCK_GetPll0OutFreq(); + break; + case 2U: + freq = CLOCK_GetPll1OutFreq(); + break; + + case 3U: + freq = CLOCK_GetOsc32KFreq(); + break; + + default: + freq = 0U; + break; + } + + return freq; +} + +/* Get I2S MCLK Clk */ +/*! brief Return Frequency of I2S MCLK Clock + * return Frequency of I2S MCLK Clock + */ +uint32_t CLOCK_GetI2SMClkFreq(void) +{ + return s_I2S_Mclk_Freq; +} + +/* Get PLU CLKIN Clk */ +/*! brief Return Frequency of PLU CLKIN Clock + * return Frequency of PLU CLKIN Clock + */ +uint32_t CLOCK_GetPLUClkInFreq(void) +{ + return s_PLU_ClkIn_Freq; +} + +/* Get FLEXCOMM input clock */ +/*! brief Return Frequency of flexcomm input clock + * param id : flexcomm instance id + * return Frequency value + */ +uint32_t CLOCK_GetFlexCommInputClock(uint32_t id) +{ + uint32_t freq = 0U; + + switch (SYSCON->FCCLKSELX[id]) + { + case 0U: + freq = CLOCK_GetCoreSysClkFreq(); + break; + case 1U: + freq = CLOCK_GetPll0OutFreq() / ((SYSCON->PLL0CLKDIV & 0xffU) + 1U); + break; + case 2U: + freq = CLOCK_GetFro12MFreq(); + break; + case 3U: + freq = CLOCK_GetFroHfFreq() / ((SYSCON->FROHFDIV & 0xffU) + 1U); + break; + case 4U: + freq = CLOCK_GetFro1MFreq(); + break; + case 5U: + freq = CLOCK_GetI2SMClkFreq(); + break; + case 6U: + freq = CLOCK_GetOsc32KFreq(); + break; + case 7U: + freq = 0U; + break; + + default: + freq = 0U; + break; + } + + return freq; +} + +/* Get FLEXCOMM Clk */ +uint32_t CLOCK_GetFlexCommClkFreq(uint32_t id) +{ + uint32_t freq = 0U; + uint32_t frgMul = 0U; + uint32_t frgDiv = 0U; + + freq = CLOCK_GetFlexCommInputClock(id); + frgMul = (SYSCON->FLEXFRGXCTRL[id] & SYSCON_FLEXFRG0CTRL_MULT_MASK) >> 8U; + frgDiv = SYSCON->FLEXFRGXCTRL[id] & SYSCON_FLEXFRG0CTRL_DIV_MASK; + return (uint32_t)(((uint64_t)freq * ((uint64_t)frgDiv + 1ULL)) / (frgMul + frgDiv + 1UL)); +} + +/* Get HS_LPSI Clk */ +uint32_t CLOCK_GetHsLspiClkFreq(void) +{ + uint32_t freq = 0U; + + switch (SYSCON->HSLSPICLKSEL) + { + case 0U: + freq = CLOCK_GetCoreSysClkFreq(); + break; + case 1U: + freq = CLOCK_GetPll0OutFreq() / ((SYSCON->PLL0CLKDIV & 0xffU) + 1U); + break; + case 2U: + freq = CLOCK_GetFro12MFreq(); + break; + case 3U: + freq = CLOCK_GetFroHfFreq() / ((SYSCON->FROHFDIV & 0xffU) + 1U); + break; + case 4U: + freq = CLOCK_GetFro1MFreq(); + break; + case 6U: + freq = CLOCK_GetOsc32KFreq(); + break; + case 7U: + freq = 0U; + break; + + default: + freq = 0U; + break; + } + + return freq; +} + +/* Get CTimer Clk */ +/*! brief Return Frequency of CTimer functional Clock + * return Frequency of CTimer functional Clock + */ +uint32_t CLOCK_GetCTimerClkFreq(uint32_t id) +{ + uint32_t freq = 0U; + + switch (SYSCON->CTIMERCLKSELX[id]) + { + case 0U: + freq = CLOCK_GetCoreSysClkFreq(); + break; + case 1U: + freq = CLOCK_GetPll0OutFreq(); + break; + case 3U: + freq = CLOCK_GetFroHfFreq(); + break; + case 4U: + freq = CLOCK_GetFro1MFreq(); + break; + case 5U: + freq = CLOCK_GetI2SMClkFreq(); + break; + case 6U: + freq = CLOCK_GetOsc32KFreq(); + break; + case 7U: + freq = 0U; + break; + + default: + freq = 0U; + break; + } + + return freq; +} + +/* Get Systick Clk */ +/*! brief Return Frequency of SystickClock + * return Frequency of Systick Clock + */ +uint32_t CLOCK_GetSystickClkFreq(uint32_t id) +{ + uint32_t freq = 0U; + + switch (SYSCON->SYSTICKCLKSELX[id]) + { + case 0U: + /*Niobe4mini just has one SYSTICKSEL and SYSTICKDIV register, Fix coverity problem in this way temporarily + */ + freq = CLOCK_GetCoreSysClkFreq() / (((SYSCON->SYSTICKCLKDIV0) & 0xffU) + 1U); + break; + case 1U: + freq = CLOCK_GetFro1MFreq(); + break; + case 2U: + freq = CLOCK_GetOsc32KFreq(); + break; + case 7U: + freq = 0U; + break; + + default: + freq = 0U; + break; + } + + return freq; +} + +/* Set FlexComm Clock */ +/** + * brief Set the flexcomm output frequency. + * param id : flexcomm instance id + * freq : output frequency + * return 0 : the frequency range is out of range. + * 1 : switch successfully. + */ +uint32_t CLOCK_SetFlexCommClock(uint32_t id, uint32_t freq) +{ + uint32_t input = CLOCK_GetFlexCommClkFreq(id); + uint32_t mul; + + if ((freq > 48000000UL) || (freq > input) || (input / freq >= 2UL)) + { + /* FRG output frequency should be less than equal to 48MHz */ + return 0UL; + } + else + { + mul = (uint32_t)((((uint64_t)input - freq) * 256ULL) / ((uint64_t)freq)); + SYSCON->FLEXFRGXCTRL[id] = (mul << 8U) | 0xFFU; + return 1UL; + } +} + +/* Get IP Clk */ +/*! brief Return Frequency of selected clock + * return Frequency of selected clock + */ +uint32_t CLOCK_GetFreq(clock_name_t clockName) +{ + uint32_t freq; + switch (clockName) + { + case kCLOCK_CoreSysClk: + freq = CLOCK_GetCoreSysClkFreq(); + break; + case kCLOCK_BusClk: + freq = CLOCK_GetCoreSysClkFreq() / ((SYSCON->AHBCLKDIV & 0xffU) + 1U); + break; + case kCLOCK_ClockOut: + freq = CLOCK_GetClockOutClkFreq(); + break; + case kCLOCK_Pll1Out: + freq = CLOCK_GetPll1OutFreq(); + break; + case kCLOCK_Mclk: + freq = CLOCK_GetMclkClkFreq(); + break; + case kCLOCK_FroHf: + freq = CLOCK_GetFroHfFreq(); + break; + case kCLOCK_Fro12M: + freq = CLOCK_GetFro12MFreq(); + break; + case kCLOCK_Fro1M: + freq = CLOCK_GetFro1MFreq(); + break; + case kCLOCK_ExtClk: + freq = CLOCK_GetExtClkFreq(); + break; + case kCLOCK_Pll0Out: + freq = CLOCK_GetPll0OutFreq(); + break; + case kCLOCK_FlexI2S: + freq = CLOCK_GetI2SMClkFreq(); + break; + default: + freq = 0U; + break; + } + return freq; +} + +/* Find SELP, SELI, and SELR values for raw M value, max M = MVALMAX */ +static void pllFindSel(uint32_t M, uint32_t *pSelP, uint32_t *pSelI, uint32_t *pSelR) +{ + uint32_t seli, selp; + /* bandwidth: compute selP from Multiplier */ + if ((SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_MDIV_EXT_MASK) != 0UL) /* normal mode */ + { + selp = (M >> 2U) + 1U; + if (selp >= 31U) + { + selp = 31U; + } + *pSelP = selp; + + if (M >= 8000UL) + { + seli = 1UL; + } + else if (M >= 122UL) + { + seli = (uint32_t)(8000UL / M); /*floor(8000/M) */ + } + else + { + seli = 2UL * ((uint32_t)(M / 4UL)) + 3UL; /* 2*floor(M/4) + 3 */ + } + + if (seli >= 63UL) + { + seli = 63UL; + } + *pSelI = seli; + + *pSelR = 0UL; + } + else + { + /* Note: If the spread spectrum mode, choose N to ensure 3 MHz < Fin/N < 5 MHz */ + *pSelP = 3U; + *pSelI = 4U; + *pSelR = 4U; + } +} + +/* Get predivider (N) from PLL0 NDEC setting */ +static uint32_t findPll0PreDiv(void) +{ + uint32_t preDiv = 1UL; + + /* Direct input is not used? */ + if ((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPREDIV_MASK) == 0UL) + { + preDiv = SYSCON->PLL0NDEC & SYSCON_PLL0NDEC_NDIV_MASK; + if (preDiv == 0UL) + { + preDiv = 1UL; + } + } + return preDiv; +} + +/* Get predivider (N) from PLL1 NDEC setting */ +static uint32_t findPll1PreDiv(void) +{ + uint32_t preDiv = 1UL; + + /* Direct input is not used? */ + if ((SYSCON->PLL1CTRL & SYSCON_PLL1CTRL_BYPASSPREDIV_MASK) == 0UL) + { + preDiv = SYSCON->PLL1NDEC & SYSCON_PLL1NDEC_NDIV_MASK; + if (preDiv == 0UL) + { + preDiv = 1UL; + } + } + return preDiv; +} + +/* Get postdivider (P) from PLL0 PDEC setting */ +static uint32_t findPll0PostDiv(void) +{ + uint32_t postDiv = 1UL; + + if ((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPOSTDIV_MASK) == 0UL) + { + if ((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPOSTDIV2_MASK) != 0UL) + { + postDiv = SYSCON->PLL0PDEC & SYSCON_PLL0PDEC_PDIV_MASK; + } + else + { + postDiv = 2UL * (SYSCON->PLL0PDEC & SYSCON_PLL0PDEC_PDIV_MASK); + } + if (postDiv == 0UL) + { + postDiv = 2UL; + } + } + return postDiv; +} + +/* Get postdivider (P) from PLL1 PDEC setting. */ +static uint32_t findPll1PostDiv(void) +{ + uint32_t postDiv = 1UL; + + if ((SYSCON->PLL1CTRL & SYSCON_PLL1CTRL_BYPASSPOSTDIV_MASK) == 0UL) + { + if ((SYSCON->PLL1CTRL & SYSCON_PLL1CTRL_BYPASSPOSTDIV2_MASK) != 0UL) + { + postDiv = SYSCON->PLL1PDEC & SYSCON_PLL1PDEC_PDIV_MASK; + } + else + { + postDiv = 2UL * (SYSCON->PLL1PDEC & SYSCON_PLL1PDEC_PDIV_MASK); + } + if (postDiv == 0UL) + { + postDiv = 2UL; + } + } + + return postDiv; +} + +/* Get multiplier (M) from PLL0 SSCG and SEL_EXT settings */ +static float findPll0MMult(void) +{ + float mMult = 1.0F; + float mMult_fract; + uint32_t mMult_int; + + if ((SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_SEL_EXT_MASK) != 0UL) + { + mMult = + (float)(uint32_t)((SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_MDIV_EXT_MASK) >> SYSCON_PLL0SSCG1_MDIV_EXT_SHIFT); + } + else + { + mMult_int = ((SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_MD_MBS_MASK) << 7U); + mMult_int = mMult_int | ((SYSCON->PLL0SSCG0) >> PLL0_SSCG_MD_INT_P); + mMult_fract = ((float)(uint32_t)((SYSCON->PLL0SSCG0) & PLL0_SSCG_MD_FRACT_M) / + (float)(uint32_t)(1UL << PLL0_SSCG_MD_INT_P)); + mMult = (float)mMult_int + mMult_fract; + } + if(0ULL == ((uint64_t)mMult)) + { + mMult = 1.0F; + } + return mMult; +} + +/* Get multiplier (M) from PLL1 MDEC. */ +static uint32_t findPll1MMult(void) +{ + uint32_t mMult = 1UL; + + mMult = SYSCON->PLL1MDEC & SYSCON_PLL1MDEC_MDIV_MASK; + + if (mMult == 0UL) + { + mMult = 1UL; + } + + return mMult; +} + +/* Find greatest common divisor between m and n */ +static uint32_t FindGreatestCommonDivisor(uint32_t m, uint32_t n) +{ + uint32_t tmp; + + while (n != 0U) + { + tmp = n; + n = m % n; + m = tmp; + } + + return m; +} + +/* + * Set PLL0 output based on desired output rate. + * In this function, the it calculates the PLL0 setting for output frequency from input clock + * frequency. The calculation would cost a few time. So it is not recommaned to use it frequently. + * the "pllctrl", "pllndec", "pllpdec", "pllmdec" would updated in this function. + */ +static pll_error_t CLOCK_GetPll0ConfigInternal(uint32_t finHz, uint32_t foutHz, pll_setup_t *pSetup, bool useSS) +{ + uint32_t nDivOutHz, fccoHz; + uint32_t pllPreDivider, pllMultiplier, pllPostDivider; + uint32_t pllDirectInput, pllDirectOutput; + uint32_t pllSelP, pllSelI, pllSelR, uplimoff; + + /* Baseline parameters (no input or output dividers) */ + pllPreDivider = 1U; /* 1 implies pre-divider will be disabled */ + pllPostDivider = 1U; /* 1 implies post-divider will be disabled */ + pllDirectOutput = 1U; + + /* Verify output rate parameter */ + if (foutHz > PLL_MAX_CCO_FREQ_MHZ) + { + /* Maximum PLL output with post divider=1 cannot go above this frequency */ + return kStatus_PLL_OutputTooHigh; + } + if (foutHz < (PLL_MIN_CCO_FREQ_MHZ / (PVALMAX << 1U))) + { + /* Minmum PLL output with maximum post divider cannot go below this frequency */ + return kStatus_PLL_OutputTooLow; + } + + /* If using SS mode, input clock needs to be between 3MHz and 20MHz */ + if (useSS) + { + /* Verify input rate parameter */ + if (finHz < PLL_MIN_IN_SSMODE) + { + /* Input clock into the PLL cannot be lower than this */ + return kStatus_PLL_InputTooLow; + } + /* PLL input in SS mode must be under 20MHz */ + if (finHz > (PLL_MAX_IN_SSMODE * NVALMAX)) + { + return kStatus_PLL_InputTooHigh; + } + } + else + { + /* Verify input rate parameter */ + if (finHz < PLL_LOWER_IN_LIMIT) + { + /* Input clock into the PLL cannot be lower than this */ + return kStatus_PLL_InputTooLow; + } + if (finHz > PLL_HIGHER_IN_LIMIT) + { + /* Input clock into the PLL cannot be higher than this */ + return kStatus_PLL_InputTooHigh; + } + } + + /* Find the optimal CCO frequency for the output and input that + will keep it inside the PLL CCO range. This may require + tweaking the post-divider for the PLL. */ + fccoHz = foutHz; + while (fccoHz < PLL_MIN_CCO_FREQ_MHZ) + { + /* CCO output is less than minimum CCO range, so the CCO output + needs to be bumped up and the post-divider is used to bring + the PLL output back down. */ + pllPostDivider++; + if (pllPostDivider > PVALMAX) + { + return kStatus_PLL_OutsideIntLimit; + } + + /* Target CCO goes up, PLL output goes down */ + /* divide-by-2 divider in the post-divider is always work*/ + fccoHz = foutHz * (pllPostDivider * 2U); + pllDirectOutput = 0U; + } + + /* Determine if a pre-divider is needed to get the best frequency */ + if ((finHz > PLL_LOWER_IN_LIMIT) && (fccoHz >= finHz) && (useSS == false)) + { + uint32_t a = FindGreatestCommonDivisor(fccoHz, finHz); + + if (a > PLL_LOWER_IN_LIMIT) + { + a = finHz / a; + if ((a != 0U) && (a < PLL_MAX_N_DIV)) + { + pllPreDivider = a; + } + } + } + + /* Bypass pre-divider hardware if pre-divider is 1 */ + if (pllPreDivider > 1U) + { + pllDirectInput = 0U; + } + else + { + pllDirectInput = 1U; + } + + /* Determine PLL multipler */ + nDivOutHz = (finHz / pllPreDivider); + pllMultiplier = (fccoHz / nDivOutHz); + + /* Find optimal values for filter */ + if (useSS == false) + { + /* Will bumping up M by 1 get us closer to the desired CCO frequency? */ + if ((nDivOutHz * ((pllMultiplier * 2U) + 1U)) < (fccoHz * 2U)) + { + pllMultiplier++; + } + + /* Setup filtering */ + pllFindSel(pllMultiplier, &pllSelP, &pllSelI, &pllSelR); + uplimoff = 0U; + + /* Get encoded value for M (mult) and use manual filter, disable SS mode */ + pSetup->pllsscg[1] = + (uint32_t)((PLL_SSCG1_MDEC_VAL_SET(pllMultiplier)) | (1UL << SYSCON_PLL0SSCG1_SEL_EXT_SHIFT)); + } + else + { + uint64_t fc; + + /* Filtering will be handled by SSC */ + pllSelR = 0UL; + pllSelI = 0UL; + pllSelP = 0UL; + uplimoff = 1U; + + /* The PLL multiplier will get very close and slightly under the + desired target frequency. A small fractional component can be + added to fine tune the frequency upwards to the target. */ + fc = ((uint64_t)(uint32_t)(fccoHz % nDivOutHz) << 25UL) / nDivOutHz; + + /* Set multiplier */ + pSetup->pllsscg[0] = (uint32_t)(PLL0_SSCG_MD_INT_SET(pllMultiplier) | PLL0_SSCG_MD_FRACT_SET((uint32_t)fc)); + pSetup->pllsscg[1] = (uint32_t)(PLL0_SSCG_MD_INT_SET(pllMultiplier) >> 32U); + } + + /* Get encoded values for N (prediv) and P (postdiv) */ + pSetup->pllndec = PLL_NDEC_VAL_SET(pllPreDivider); + pSetup->pllpdec = PLL_PDEC_VAL_SET(pllPostDivider); + + /* PLL control */ + pSetup->pllctrl = (pllSelR << SYSCON_PLL0CTRL_SELR_SHIFT) | /* Filter coefficient */ + (pllSelI << SYSCON_PLL0CTRL_SELI_SHIFT) | /* Filter coefficient */ + (pllSelP << SYSCON_PLL0CTRL_SELP_SHIFT) | /* Filter coefficient */ + (0UL << SYSCON_PLL0CTRL_BYPASSPLL_SHIFT) | /* PLL bypass mode disabled */ + (uplimoff << SYSCON_PLL0CTRL_LIMUPOFF_SHIFT) | /* SS/fractional mode disabled */ + (pllDirectInput << SYSCON_PLL0CTRL_BYPASSPREDIV_SHIFT) | /* Bypass pre-divider? */ + (pllDirectOutput << SYSCON_PLL0CTRL_BYPASSPOSTDIV_SHIFT) | /* Bypass post-divider? */ + (1UL << SYSCON_PLL0CTRL_CLKEN_SHIFT); /* Ensure the PLL clock output */ + + return kStatus_PLL_Success; +} + +#if (defined(CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) && CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) +/* Alloct the static buffer for cache. */ +static pll_setup_t s_PllSetupCacheStruct[CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT]; +static uint32_t s_FinHzCache[CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT] = {0}; +static uint32_t s_FoutHzCache[CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT] = {0}; +static bool s_UseSSCache[CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT] = {false}; +static uint32_t s_PllSetupCacheIdx = 0U; +#endif /* CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT */ + +/* + * Calculate the PLL setting values from input clock freq to output freq. + */ +static pll_error_t CLOCK_GetPll0Config(uint32_t finHz, uint32_t foutHz, pll_setup_t *pSetup, bool useSS) +{ + pll_error_t retErr; +#if (defined(CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) && CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) + uint32_t i; + + for (i = 0U; i < CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT; i++) + { + if ((finHz == s_FinHzCache[i]) && (foutHz == s_FoutHzCache[i]) && (useSS == s_UseSSCache[i])) + { + /* Hit the target in cache buffer. */ + pSetup->pllctrl = s_PllSetupCacheStruct[i].pllctrl; + pSetup->pllndec = s_PllSetupCacheStruct[i].pllndec; + pSetup->pllpdec = s_PllSetupCacheStruct[i].pllpdec; + pSetup->pllsscg[0] = s_PllSetupCacheStruct[i].pllsscg[0]; + pSetup->pllsscg[1] = s_PllSetupCacheStruct[i].pllsscg[1]; + retErr = kStatus_PLL_Success; + break; + } + } + + if (i < CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) + { + return retErr; + } +#endif /* CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT */ + + retErr = CLOCK_GetPll0ConfigInternal(finHz, foutHz, pSetup, useSS); + +#if (defined(CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) && CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) + /* Cache the most recent calulation result into buffer. */ + s_FinHzCache[s_PllSetupCacheIdx] = finHz; + s_FoutHzCache[s_PllSetupCacheIdx] = foutHz; + s_UseSSCache[s_PllSetupCacheIdx] = useSS; + + s_PllSetupCacheStruct[s_PllSetupCacheIdx].pllctrl = pSetup->pllctrl; + s_PllSetupCacheStruct[s_PllSetupCacheIdx].pllndec = pSetup->pllndec; + s_PllSetupCacheStruct[s_PllSetupCacheIdx].pllpdec = pSetup->pllpdec; + s_PllSetupCacheStruct[s_PllSetupCacheIdx].pllsscg[0] = pSetup->pllsscg[0]; + s_PllSetupCacheStruct[s_PllSetupCacheIdx].pllsscg[1] = pSetup->pllsscg[1]; + /* Update the index for next available buffer. */ + s_PllSetupCacheIdx = (s_PllSetupCacheIdx + 1U) % CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT; +#endif /* CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT */ + + return retErr; +} + +/* Update local PLL rate variable */ +static void CLOCK_GetPLL0OutFromSetupUpdate(pll_setup_t *pSetup) +{ + s_Pll0_Freq = CLOCK_GetPLL0OutFromSetup(pSetup); +} + +/* Update local PLL1 rate variable */ +static void CLOCK_GetPLL1OutFromSetupUpdate(pll_setup_t *pSetup) +{ + s_Pll1_Freq = CLOCK_GetPLL1OutFromSetup(pSetup); +} + +/* Return System PLL input clock rate */ +/*! brief Return PLL0 input clock rate + * return PLL0 input clock rate + */ +uint32_t CLOCK_GetPLL0InClockRate(void) +{ + uint32_t clkRate = 0U; + + switch ((SYSCON->PLL0CLKSEL & SYSCON_PLL0CLKSEL_SEL_MASK)) + { + case 0x00U: + clkRate = CLK_FRO_12MHZ; + break; + + case 0x01U: + clkRate = CLOCK_GetExtClkFreq(); + break; + + case 0x02U: + clkRate = CLOCK_GetFro1MFreq(); + break; + + case 0x03U: + clkRate = CLOCK_GetOsc32KFreq(); + break; + + default: + clkRate = 0U; + break; + } + + return clkRate; +} + +/* Return PLL1 input clock rate */ +uint32_t CLOCK_GetPLL1InClockRate(void) +{ + uint32_t clkRate = 0U; + + switch ((SYSCON->PLL1CLKSEL & SYSCON_PLL1CLKSEL_SEL_MASK)) + { + case 0x00U: + clkRate = CLK_FRO_12MHZ; + break; + + case 0x01U: + clkRate = CLOCK_GetExtClkFreq(); + break; + + case 0x02U: + clkRate = CLOCK_GetFro1MFreq(); + break; + + case 0x03U: + clkRate = CLOCK_GetOsc32KFreq(); + break; + + default: + clkRate = 0U; + break; + } + + return clkRate; +} + +/* Return PLL0 output clock rate from setup structure */ +/*! brief Return PLL0 output clock rate from setup structure + * param pSetup : Pointer to a PLL setup structure + * return PLL0 output clock rate the setup structure will generate + */ +uint32_t CLOCK_GetPLL0OutFromSetup(pll_setup_t *pSetup) +{ + uint32_t clkRate = 0; + uint32_t prediv, postdiv; + float workRate = 0.0F; + + /* Get the input clock frequency of PLL. */ + clkRate = CLOCK_GetPLL0InClockRate(); + + if (((pSetup->pllctrl & SYSCON_PLL0CTRL_BYPASSPLL_MASK) == 0UL) && + ((pSetup->pllctrl & SYSCON_PLL0CTRL_CLKEN_MASK) != 0UL) && + ((PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_PLL0_MASK) == 0UL) && + ((PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_PLL0_SSCG_MASK) == 0UL)) + { + prediv = findPll0PreDiv(); + postdiv = findPll0PostDiv(); + /* Adjust input clock */ + clkRate = clkRate / prediv; + /* MDEC used for rate */ + workRate = (float)clkRate * (float)findPll0MMult(); + workRate /= (float)postdiv; + } + + return (uint32_t)workRate; +} + +/* Return PLL1 output clock rate from setup structure */ +/*! brief Return PLL1 output clock rate from setup structure + * param pSetup : Pointer to a PLL setup structure + * return PLL0 output clock rate the setup structure will generate + */ +uint32_t CLOCK_GetPLL1OutFromSetup(pll_setup_t *pSetup) +{ + uint32_t clkRate = 0; + uint32_t prediv, postdiv; + uint32_t workRate = 0UL; + + /* Get the input clock frequency of PLL. */ + clkRate = CLOCK_GetPLL1InClockRate(); + + if (((pSetup->pllctrl & SYSCON_PLL1CTRL_BYPASSPLL_MASK) == 0UL) && + ((pSetup->pllctrl & SYSCON_PLL1CTRL_CLKEN_MASK) != 0UL) && + ((PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_PLL1_MASK) == 0UL)) + { + prediv = findPll1PreDiv(); + postdiv = findPll1PostDiv(); + /* Adjust input clock */ + clkRate = clkRate / prediv; + /* MDEC used for rate */ + workRate = clkRate * findPll1MMult(); + workRate /= postdiv; + } + + return workRate; +} + +/* Set the current PLL0 Rate */ +/*! brief Store the current PLL rate + * param rate: Current rate of the PLL + * return Nothing + **/ +void CLOCK_SetStoredPLL0ClockRate(uint32_t rate) +{ + s_Pll0_Freq = rate; +} + +/* Return PLL0 output clock rate */ +/*! brief Return PLL0 output clock rate + * param recompute : Forces a PLL rate recomputation if true + * return PLL0 output clock rate + * note The PLL rate is cached in the driver in a variable as + * the rate computation function can take some time to perform. It + * is recommended to use 'false' with the 'recompute' parameter. + */ +uint32_t CLOCK_GetPLL0OutClockRate(bool recompute) +{ + pll_setup_t Setup; + uint32_t rate; + + if ((recompute) || (s_Pll0_Freq == 0U)) + { + Setup.pllctrl = SYSCON->PLL0CTRL; + Setup.pllndec = SYSCON->PLL0NDEC; + Setup.pllpdec = SYSCON->PLL0PDEC; + Setup.pllsscg[0] = SYSCON->PLL0SSCG0; + Setup.pllsscg[1] = SYSCON->PLL0SSCG1; + + CLOCK_GetPLL0OutFromSetupUpdate(&Setup); + } + + rate = s_Pll0_Freq; + + return rate; +} + +/*! brief Return PLL1 output clock rate + * param recompute : Forces a PLL rate recomputation if true + * return PLL1 output clock rate + * note The PLL rate is cached in the driver in a variable as + * the rate computation function can take some time to perform. It + * is recommended to use 'false' with the 'recompute' parameter. + */ +uint32_t CLOCK_GetPLL1OutClockRate(bool recompute) +{ + pll_setup_t Setup; + uint32_t rate; + + if ((recompute) || (s_Pll1_Freq == 0U)) + { + Setup.pllctrl = SYSCON->PLL1CTRL; + Setup.pllndec = SYSCON->PLL1NDEC; + Setup.pllpdec = SYSCON->PLL1PDEC; + Setup.pllmdec = SYSCON->PLL1MDEC; + CLOCK_GetPLL1OutFromSetupUpdate(&Setup); + } + + rate = s_Pll1_Freq; + + return rate; +} + +/* Set PLL0 output based on the passed PLL setup data */ +/*! brief Set PLL output based on the passed PLL setup data + * param pControl : Pointer to populated PLL control structure to generate setup with + * param pSetup : Pointer to PLL setup structure to be filled + * return PLL_ERROR_SUCCESS on success, or PLL setup error code + * note Actual frequency for setup may vary from the desired frequency based on the + * accuracy of input clocks, rounding, non-fractional PLL mode, etc. + */ +pll_error_t CLOCK_SetupPLL0Data(pll_config_t *pControl, pll_setup_t *pSetup) +{ + uint32_t inRate; + bool useSS = (bool)((pControl->flags & PLL_CONFIGFLAG_FORCENOFRACT) == 0UL); + + pll_error_t pllError; + + /* Determine input rate for the PLL */ + if ((pControl->flags & PLL_CONFIGFLAG_USEINRATE) != 0UL) + { + inRate = pControl->inputRate; + } + else + { + inRate = CLOCK_GetPLL0InClockRate(); + } + + /* PLL flag options */ + pllError = CLOCK_GetPll0Config(inRate, pControl->desiredRate, pSetup, useSS); + if ((useSS) && (pllError == kStatus_PLL_Success)) + { + /* If using SS mode, then some tweaks are made to the generated setup */ + pSetup->pllsscg[1] |= (uint32_t)pControl->ss_mf | (uint32_t)pControl->ss_mr | (uint32_t)pControl->ss_mc; + if (pControl->mfDither) + { + pSetup->pllsscg[1] |= (1UL << SYSCON_PLL0SSCG1_DITHER_SHIFT); + } + } + + return pllError; +} + +/* Set PLL0 output from PLL setup structure */ +/*! brief Set PLL output from PLL setup structure (precise frequency) + * param pSetup : Pointer to populated PLL setup structure + * param flagcfg : Flag configuration for PLL config structure + * return PLL_ERROR_SUCCESS on success, or PLL setup error code + * note This function will power off the PLL, setup the PLL with the + * new setup data, and then optionally powerup the PLL, wait for PLL lock, + * and adjust system voltages to the new PLL rate. The function will not + * alter any source clocks (ie, main systen clock) that may use the PLL, + * so these should be setup prior to and after exiting the function. + */ +pll_error_t CLOCK_SetupPLL0Prec(pll_setup_t *pSetup, uint32_t flagcfg) +{ + uint32_t inRate, clkRate, prediv; + + /* Power off PLL during setup changes */ + POWER_EnablePD(kPDRUNCFG_PD_PLL0); + POWER_EnablePD(kPDRUNCFG_PD_PLL0_SSCG); + + pSetup->flags = flagcfg; + + /* Write PLL setup data */ + SYSCON->PLL0CTRL = pSetup->pllctrl; + SYSCON->PLL0NDEC = pSetup->pllndec; + SYSCON->PLL0NDEC = pSetup->pllndec | (1UL << SYSCON_PLL0NDEC_NREQ_SHIFT); /* latch */ + SYSCON->PLL0PDEC = pSetup->pllpdec; + SYSCON->PLL0PDEC = pSetup->pllpdec | (1UL << SYSCON_PLL0PDEC_PREQ_SHIFT); /* latch */ + SYSCON->PLL0SSCG0 = pSetup->pllsscg[0]; + SYSCON->PLL0SSCG1 = pSetup->pllsscg[1]; + SYSCON->PLL0SSCG1 = + pSetup->pllsscg[1] | (1UL << SYSCON_PLL0SSCG1_MREQ_SHIFT) | (1UL << SYSCON_PLL0SSCG1_MD_REQ_SHIFT); /* latch */ + + POWER_DisablePD(kPDRUNCFG_PD_PLL0); + POWER_DisablePD(kPDRUNCFG_PD_PLL0_SSCG); + + if ((pSetup->flags & PLL_SETUPFLAG_WAITLOCK) != 0UL) + { + if ((SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_MDIV_EXT_MASK) != 0UL) /* normal mode */ + { + inRate = CLOCK_GetPLL0InClockRate(); + prediv = findPll0PreDiv(); + /* Adjust input clock */ + clkRate = inRate / prediv; + /* The lock signal is only reliable between fref[2] :100 kHz to 20 MHz. */ + if ((clkRate >= 100000UL) && (clkRate <= 20000000UL)) + { + while (CLOCK_IsPLL0Locked() == false) + { + } + } + else + { + SDK_DelayAtLeastUs(6000U, + SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); /* software should use a 6 ms time interval + to insure the PLL will be stable */ + } + } + else /* spread spectrum mode */ + { + SDK_DelayAtLeastUs(6000U, + SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); /* software should use a 6 ms time interval to + insure the PLL will be stable */ + } + } + + /* Update current programmed PLL rate var */ + CLOCK_GetPLL0OutFromSetupUpdate(pSetup); + + /* System voltage adjustment, occurs prior to setting main system clock */ + if ((pSetup->flags & PLL_SETUPFLAG_ADGVOLT) != 0UL) + { + POWER_SetVoltageForFreq(s_Pll0_Freq); + } + + return kStatus_PLL_Success; +} + +/* Setup PLL Frequency from pre-calculated value */ +/** + * brief Set PLL0 output from PLL setup structure (precise frequency) + * param pSetup : Pointer to populated PLL setup structure + * return kStatus_PLL_Success on success, or PLL setup error code + * note This function will power off the PLL, setup the PLL with the + * new setup data, and then optionally powerup the PLL, wait for PLL lock, + * and adjust system voltages to the new PLL rate. The function will not + * alter any source clocks (ie, main systen clock) that may use the PLL, + * so these should be setup prior to and after exiting the function. + */ +pll_error_t CLOCK_SetPLL0Freq(const pll_setup_t *pSetup) +{ + uint32_t inRate, clkRate, prediv; + /* Power off PLL during setup changes */ + POWER_EnablePD(kPDRUNCFG_PD_PLL0); + POWER_EnablePD(kPDRUNCFG_PD_PLL0_SSCG); + + /* Write PLL setup data */ + SYSCON->PLL0CTRL = pSetup->pllctrl; + SYSCON->PLL0NDEC = pSetup->pllndec; + SYSCON->PLL0NDEC = pSetup->pllndec | (1UL << SYSCON_PLL0NDEC_NREQ_SHIFT); /* latch */ + SYSCON->PLL0PDEC = pSetup->pllpdec; + SYSCON->PLL0PDEC = pSetup->pllpdec | (1UL << SYSCON_PLL0PDEC_PREQ_SHIFT); /* latch */ + SYSCON->PLL0SSCG0 = pSetup->pllsscg[0]; + SYSCON->PLL0SSCG1 = pSetup->pllsscg[1]; + SYSCON->PLL0SSCG1 = + pSetup->pllsscg[1] | (1UL << SYSCON_PLL0SSCG1_MD_REQ_SHIFT) | (1UL << SYSCON_PLL0SSCG1_MREQ_SHIFT); /* latch */ + + POWER_DisablePD(kPDRUNCFG_PD_PLL0); + POWER_DisablePD(kPDRUNCFG_PD_PLL0_SSCG); + + if ((pSetup->flags & PLL_SETUPFLAG_WAITLOCK) != 0UL) + { + if ((SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_MDIV_EXT_MASK) != 0UL) /* normal mode */ + { + inRate = CLOCK_GetPLL0InClockRate(); + prediv = findPll0PreDiv(); + /* Adjust input clock */ + clkRate = inRate / prediv; + /* The lock signal is only reliable between fref[2] :100 kHz to 20 MHz. */ + if ((clkRate >= 100000UL) && (clkRate <= 20000000UL)) + { + while (CLOCK_IsPLL0Locked() == false) + { + } + } + else + { + SDK_DelayAtLeastUs(6000U, + SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); /* software should use a 6 ms time interval + to insure the PLL will be stable */ + } + } + else /* spread spectrum mode */ + { + SDK_DelayAtLeastUs(6000U, + SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); /* software should use a 6 ms time interval to + insure the PLL will be stable */ + } + } + + /* Update current programmed PLL rate var */ + s_Pll0_Freq = pSetup->pllRate; + + return kStatus_PLL_Success; +} + +/* Setup PLL1 Frequency from pre-calculated value */ +/** + * brief Set PLL1 output from PLL setup structure (precise frequency) + * param pSetup : Pointer to populated PLL setup structure + * return kStatus_PLL_Success on success, or PLL setup error code + * note This function will power off the PLL, setup the PLL with the + * new setup data, and then optionally powerup the PLL, wait for PLL lock, + * and adjust system voltages to the new PLL rate. The function will not + * alter any source clocks (ie, main systen clock) that may use the PLL, + * so these should be setup prior to and after exiting the function. + */ +pll_error_t CLOCK_SetPLL1Freq(const pll_setup_t *pSetup) +{ + uint32_t inRate, clkRate, prediv; + /* Power off PLL during setup changes */ + POWER_EnablePD(kPDRUNCFG_PD_PLL1); + + /* Write PLL setup data */ + SYSCON->PLL1CTRL = pSetup->pllctrl; + SYSCON->PLL1NDEC = pSetup->pllndec; + SYSCON->PLL1NDEC = pSetup->pllndec | (1UL << SYSCON_PLL1NDEC_NREQ_SHIFT); /* latch */ + SYSCON->PLL1PDEC = pSetup->pllpdec; + SYSCON->PLL1PDEC = pSetup->pllpdec | (1UL << SYSCON_PLL1PDEC_PREQ_SHIFT); /* latch */ + SYSCON->PLL1MDEC = pSetup->pllmdec; + SYSCON->PLL1MDEC = pSetup->pllmdec | (1UL << SYSCON_PLL1MDEC_MREQ_SHIFT); /* latch */ + + POWER_DisablePD(kPDRUNCFG_PD_PLL1); + + if ((pSetup->flags & PLL_SETUPFLAG_WAITLOCK) != 0UL) + { + inRate = CLOCK_GetPLL1InClockRate(); + prediv = findPll1PreDiv(); + /* Adjust input clock */ + clkRate = inRate / prediv; + /* The lock signal is only reliable between fref[2] :100 kHz to 20 MHz. */ + if ((clkRate >= 100000UL) && (clkRate <= 20000000UL)) + { + while (CLOCK_IsPLL1Locked() == false) + { + } + } + else + { + SDK_DelayAtLeastUs(6000U, + SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); /* software should use a 6 ms time interval to + insure the PLL will be stable */ + } + } + + /* Update current programmed PLL rate var */ + s_Pll1_Freq = pSetup->pllRate; + + return kStatus_PLL_Success; +} + +/* Set PLL0 clock based on the input frequency and multiplier */ +/*! brief Set PLL0 output based on the multiplier and input frequency + * param multiply_by : multiplier + * param input_freq : Clock input frequency of the PLL + * return Nothing + * note Unlike the Chip_Clock_SetupSystemPLLPrec() function, this + * function does not disable or enable PLL power, wait for PLL lock, + * or adjust system voltages. These must be done in the application. + * The function will not alter any source clocks (ie, main systen clock) + * that may use the PLL, so these should be setup prior to and after + * exiting the function. + */ +void CLOCK_SetupPLL0Mult(uint32_t multiply_by, uint32_t input_freq) +{ + uint32_t cco_freq = input_freq * multiply_by; + uint32_t pdec = 1U; + uint32_t selr; + uint32_t seli; + uint32_t selp; + uint32_t mdec, ndec; + + while (cco_freq < 275000000U) + { + multiply_by <<= 1U; /* double value in each iteration */ + pdec <<= 1U; /* correspondingly double pdec to cancel effect of double msel */ + cco_freq = input_freq * multiply_by; + } + + selr = 0U; + + if (multiply_by >= 8000UL) + { + seli = 1UL; + } + else if (multiply_by >= 122UL) + { + seli = (uint32_t)(8000UL / multiply_by); /*floor(8000/M) */ + } + else + { + seli = 2UL * ((uint32_t)(multiply_by / 4UL)) + 3UL; /* 2*floor(M/4) + 3 */ + } + + if (seli >= 63U) + { + seli = 63U; + } + + { + selp = 31U; + } + + if (pdec > 1U) + { + pdec = pdec / 2U; /* Account for minus 1 encoding */ + /* Translate P value */ + } + + mdec = (uint32_t)PLL_SSCG1_MDEC_VAL_SET(multiply_by); + ndec = 0x1U; /* pre divide by 1 (hardcoded) */ + + SYSCON->PLL0CTRL = SYSCON_PLL0CTRL_CLKEN_MASK | SYSCON_PLL0CTRL_BYPASSPOSTDIV(0) | + SYSCON_PLL0CTRL_BYPASSPOSTDIV2(0) | (selr << SYSCON_PLL0CTRL_SELR_SHIFT) | + (seli << SYSCON_PLL0CTRL_SELI_SHIFT) | (selp << SYSCON_PLL0CTRL_SELP_SHIFT); + SYSCON->PLL0PDEC = pdec | (1UL << SYSCON_PLL0PDEC_PREQ_SHIFT); /* set Pdec value and assert preq */ + SYSCON->PLL0NDEC = ndec | (1UL << SYSCON_PLL0NDEC_NREQ_SHIFT); /* set Pdec value and assert preq */ + SYSCON->PLL0SSCG1 = + mdec | (1UL << SYSCON_PLL0SSCG1_MREQ_SHIFT); /* select non sscg MDEC value, assert mreq and select mdec value */ +} + +/* Enable USB DEVICE FULL SPEED clock */ +/*! brief Enable USB Device FS clock. + * param src : clock source + * param freq: clock frequency + * Enable USB Device Full Speed clock. + */ +bool CLOCK_EnableUsbfs0DeviceClock(clock_usbfs_src_t src, uint32_t freq) +{ + bool ret = true; + + CLOCK_DisableClock(kCLOCK_Usbd0); + + if (kCLOCK_UsbfsSrcFro == src) + { + switch (freq) + { + case 96000000U: + CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 2, false); /*!< Div by 2 to get 48MHz, no divider reset */ + break; + + default: + ret = false; + break; + } + /* Turn ON FRO HF */ + POWER_DisablePD(kPDRUNCFG_PD_FRO192M); + /* Enable FRO 96MHz output */ + ANACTRL->FRO192M_CTRL = + ANACTRL->FRO192M_CTRL | ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK | ANACTRL_FRO192M_CTRL_USBCLKADJ_MASK; + /* Select FRO 96 or 48 MHz */ + CLOCK_AttachClk(kFRO_HF_to_USB0_CLK); + } + else + { + /*!< Configure XTAL32M */ + POWER_DisablePD(kPDRUNCFG_PD_XTAL32M); /* Ensure XTAL32M is powered */ + POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M); /* Ensure XTAL32M is powered */ + (void)CLOCK_SetupExtClocking(16000000U); /* Enable clk_in clock */ + SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK; /* Enable clk_in from XTAL32M clock */ + ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK; /* Enable clk_in to system */ + + /*!< Set up PLL1 */ + POWER_DisablePD(kPDRUNCFG_PD_PLL1); + CLOCK_AttachClk(kEXT_CLK_to_PLL1); /*!< Switch PLL1CLKSEL to EXT_CLK */ + const pll_setup_t pll1Setup = { + .pllctrl = SYSCON_PLL1CTRL_CLKEN_MASK | SYSCON_PLL1CTRL_SELI(19U) | SYSCON_PLL1CTRL_SELP(9U), + .pllndec = SYSCON_PLL1NDEC_NDIV(1U), + .pllpdec = SYSCON_PLL1PDEC_PDIV(5U), + .pllmdec = SYSCON_PLL1MDEC_MDIV(30U), + .pllRate = 48000000U, + .flags = PLL_SETUPFLAG_WAITLOCK}; + (void)CLOCK_SetPLL1Freq(&pll1Setup); + + CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1U, false); + CLOCK_AttachClk(kPLL1_to_USB0_CLK); + SDK_DelayAtLeastUs(50U, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); + } + CLOCK_EnableClock(kCLOCK_Usbd0); + CLOCK_EnableClock(kCLOCK_UsbRam1); + + return ret; +} + +/* Enable USB HOST FULL SPEED clock */ +/*! brief Enable USB HOST FS clock. + * param src : clock source + * param freq: clock frequency + * Enable USB HOST Full Speed clock. + */ +bool CLOCK_EnableUsbfs0HostClock(clock_usbfs_src_t src, uint32_t freq) +{ + bool ret = true; + + CLOCK_DisableClock(kCLOCK_Usbhmr0); + CLOCK_DisableClock(kCLOCK_Usbhsl0); + + if (kCLOCK_UsbfsSrcFro == src) + { + switch (freq) + { + case 96000000U: + CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 2, false); /*!< Div by 2 to get 48MHz, no divider reset */ + break; + + default: + ret = false; + break; + } + /* Turn ON FRO HF */ + POWER_DisablePD(kPDRUNCFG_PD_FRO192M); + /* Enable FRO 96MHz output */ + ANACTRL->FRO192M_CTRL = ANACTRL->FRO192M_CTRL | ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK; + /* Select FRO 96 MHz */ + CLOCK_AttachClk(kFRO_HF_to_USB0_CLK); + } + else + { + /*!< Configure XTAL32M */ + POWER_DisablePD(kPDRUNCFG_PD_XTAL32M); /* Ensure XTAL32M is powered */ + POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M); /* Ensure XTAL32M is powered */ + (void)CLOCK_SetupExtClocking(16000000U); /* Enable clk_in clock */ + SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK; /* Enable clk_in from XTAL32M clock */ + ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK; /* Enable clk_in to system */ + + /*!< Set up PLL1 */ + POWER_DisablePD(kPDRUNCFG_PD_PLL1); + CLOCK_AttachClk(kEXT_CLK_to_PLL1); /*!< Switch PLL1CLKSEL to EXT_CLK */ + const pll_setup_t pll1Setup = { + .pllctrl = SYSCON_PLL1CTRL_CLKEN_MASK | SYSCON_PLL1CTRL_SELI(19U) | SYSCON_PLL1CTRL_SELP(9U), + .pllndec = SYSCON_PLL1NDEC_NDIV(1U), + .pllpdec = SYSCON_PLL1PDEC_PDIV(5U), + .pllmdec = SYSCON_PLL1MDEC_MDIV(30U), + .pllRate = 48000000U, + .flags = PLL_SETUPFLAG_WAITLOCK}; + (void)CLOCK_SetPLL1Freq(&pll1Setup); + + CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1U, false); + CLOCK_AttachClk(kPLL1_to_USB0_CLK); + SDK_DelayAtLeastUs(50U, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); + } + CLOCK_EnableClock(kCLOCK_Usbhmr0); + CLOCK_EnableClock(kCLOCK_Usbhsl0); + CLOCK_EnableClock(kCLOCK_UsbRam1); + + return ret; +} + +/* Enable USB PHY clock */ +bool CLOCK_EnableUsbhs0PhyPllClock(clock_usb_phy_src_t src, uint32_t freq) +{ + volatile uint32_t i; + uint32_t phyPllDiv = 0U; + uint16_t multiplier = 0U; + + POWER_DisablePD(kPDRUNCFG_PD_XTAL32M); + POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M); + POWER_DisablePD(kPDRUNCFG_PD_FRO32K); /*!< Ensure FRO32k is on */ + POWER_DisablePD(kPDRUNCFG_PD_XTAL32K); /*!< Ensure xtal32k is on */ + POWER_DisablePD(kPDRUNCFG_PD_USB1_PHY); /*!< Ensure xtal32k is on */ + POWER_DisablePD(kPDRUNCFG_PD_LDOUSBHS); /*!< Ensure xtal32k is on */ + + /* wait to make sure PHY power is fully up */ + i = 100000U; + while ((i--) != 0U) + { + __ASM("nop"); + } + + SYSCON->AHBCLKCTRLSET[2] = SYSCON_AHBCLKCTRL2_ANALOG_CTRL(1); + SYSCON->AHBCLKCTRLSET[2] = SYSCON_AHBCLKCTRL2_USB1_PHY(1); + + USBPHY->CTRL_CLR = USBPHY_CTRL_SFTRST_MASK; + + multiplier = 480000000 / freq; + + switch (multiplier) + { + case 15: + { + phyPllDiv = USBPHY_PLL_SIC_PLL_DIV_SEL(0U); + break; + } + case 16: + { + phyPllDiv = USBPHY_PLL_SIC_PLL_DIV_SEL(1U); + break; + } + case 20: + { + phyPllDiv = USBPHY_PLL_SIC_PLL_DIV_SEL(2U); + break; + } + case 24: + { + phyPllDiv = USBPHY_PLL_SIC_PLL_DIV_SEL(4U); + break; + } + case 25: + { + phyPllDiv = USBPHY_PLL_SIC_PLL_DIV_SEL(5U); + break; + } + case 30: + { + phyPllDiv = USBPHY_PLL_SIC_PLL_DIV_SEL(6U); + break; + } + default: + { + return false; + } + } + USBPHY->PLL_SIC = (USBPHY->PLL_SIC & ~USBPHY_PLL_SIC_PLL_DIV_SEL(0x7)) | phyPllDiv; + USBPHY->PLL_SIC_SET = USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_MASK; + USBPHY->PLL_SIC_CLR = (1UL << 16U); // Reserved. User must set this bit to 0x0 + USBPHY->PLL_SIC_SET = USBPHY_PLL_SIC_SET_PLL_POWER_MASK; + USBPHY->PLL_SIC_SET = USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_MASK; + + USBPHY->CTRL_CLR = USBPHY_CTRL_CLR_CLKGATE_MASK; + USBPHY->PWD_SET = 0x0; + + return true; +} + +/* Enable USB DEVICE HIGH SPEED clock */ +bool CLOCK_EnableUsbhs0DeviceClock(clock_usbhs_src_t src, uint32_t freq) +{ + SYSCON->AHBCLKCTRLSET[2] = SYSCON_AHBCLKCTRL2_USB1_RAM(1); + SYSCON->AHBCLKCTRLSET[2] = SYSCON_AHBCLKCTRL2_USB1_DEV(1); + + /* 16 MHz will be driven by the tb on the xtal1 pin of XTAL32M */ + SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK; /* Enable clock_in clock for clock module. */ + ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT(1); + return true; +} + +/* Enable USB HOST HIGH SPEED clock */ +bool CLOCK_EnableUsbhs0HostClock(clock_usbhs_src_t src, uint32_t freq) +{ + SYSCON->AHBCLKCTRLSET[2] = SYSCON_AHBCLKCTRL2_USB1_RAM(1); + SYSCON->AHBCLKCTRLSET[2] = SYSCON_AHBCLKCTRL2_USB1_HOST(1); + + /* 16 MHz will be driven by the tb on the xtal1 pin of XTAL32M */ + SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK; /* Enable clock_in clock for clock module. */ + ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT(1); + + return true; +} + +/*! @brief Enable the OSTIMER 32k clock. + * @return Nothing + */ +void CLOCK_EnableOstimer32kClock(void) +{ + PMC->OSTIMERr |= PMC_OSTIMER_CLOCKENABLE_MASK; +} diff --git a/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_clock.h b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_clock.h new file mode 100644 index 0000000000..d28d8b21a3 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_clock.h @@ -0,0 +1,1525 @@ +/* + * Copyright 2017 - 2021 , NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_CLOCK_H_ +#define _FSL_CLOCK_H_ + +#include "fsl_common.h" + +/*! @addtogroup clock */ +/*! @{ */ + +/*! @file */ + +/******************************************************************************* + * Definitions + *****************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief CLOCK driver version 2.3.7. */ +#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 3, 7)) +/*@}*/ + +/*! @brief Configure whether driver controls clock + * + * When set to 0, peripheral drivers will enable clock in initialize function + * and disable clock in de-initialize function. When set to 1, peripheral + * driver will not control the clock, application could control the clock out of + * the driver. + * + * @note All drivers share this feature switcher. If it is set to 1, application + * should handle clock enable and disable for all drivers. + */ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)) +#define FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL 0 +#endif + +/*! + * @brief User-defined the size of cache for CLOCK_PllGetConfig() function. + * + * Once define this MACRO to be non-zero value, CLOCK_PllGetConfig() function + * would cache the recent calulation and accelerate the execution to get the + * right settings. + */ +#ifndef CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT +#define CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT 2U +#endif + +/* Definition for delay API in clock driver, users can redefine it to the real application. */ +#ifndef SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY +#define SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY (100000000UL) +#endif + +/*! @brief Clock ip name array for ROM. */ +#define ROM_CLOCKS \ + { \ + kCLOCK_Rom \ + } +/*! @brief Clock ip name array for SRAM. */ +#define SRAM_CLOCKS \ + { \ + kCLOCK_Sram1, kCLOCK_Sram2 \ + } +/*! @brief Clock ip name array for FLASH. */ +#define FLASH_CLOCKS \ + { \ + kCLOCK_Flash \ + } +/*! @brief Clock ip name array for FMC. */ +#define FMC_CLOCKS \ + { \ + kCLOCK_Fmc \ + } +/*! @brief Clock ip name array for INPUTMUX. */ +#define INPUTMUX_CLOCKS \ + { \ + kCLOCK_InputMux0 \ + } +/*! @brief Clock ip name array for IOCON. */ +#define IOCON_CLOCKS \ + { \ + kCLOCK_Iocon \ + } +/*! @brief Clock ip name array for GPIO. */ +#define GPIO_CLOCKS \ + { \ + kCLOCK_Gpio0, kCLOCK_Gpio1 \ + } +/*! @brief Clock ip name array for PINT. */ +#define PINT_CLOCKS \ + { \ + kCLOCK_Pint \ + } +/*! @brief Clock ip name array for GINT. */ +#define GINT_CLOCKS \ + { \ + kCLOCK_Gint, kCLOCK_Gint \ + } +/*! @brief Clock ip name array for DMA. */ +#define DMA_CLOCKS \ + { \ + kCLOCK_Dma0, kCLOCK_Dma1 \ + } +/*! @brief Clock ip name array for CRC. */ +#define CRC_CLOCKS \ + { \ + kCLOCK_Crc \ + } +/*! @brief Clock ip name array for WWDT. */ +#define WWDT_CLOCKS \ + { \ + kCLOCK_Wwdt \ + } +/*! @brief Clock ip name array for RTC. */ +#define RTC_CLOCKS \ + { \ + kCLOCK_Rtc \ + } +/*! @brief Clock ip name array for Mailbox. */ +#define MAILBOX_CLOCKS \ + { \ + kCLOCK_Mailbox \ + } +/*! @brief Clock ip name array for LPADC. */ +#define LPADC_CLOCKS \ + { \ + kCLOCK_Adc0 \ + } +/*! @brief Clock ip name array for MRT. */ +#define MRT_CLOCKS \ + { \ + kCLOCK_Mrt \ + } +/*! @brief Clock ip name array for OSTIMER. */ +#define OSTIMER_CLOCKS \ + { \ + kCLOCK_OsTimer0 \ + } +/*! @brief Clock ip name array for SCT0. */ +#define SCT_CLOCKS \ + { \ + kCLOCK_Sct0 \ + } +/*! @brief Clock ip name array for MCAN. */ +#define MCAN_CLOCKS \ + { \ + kCLOCK_Mcan \ + } +/*! @brief Clock ip name array for UTICK. */ +#define UTICK_CLOCKS \ + { \ + kCLOCK_Utick0 \ + } +/*! @brief Clock ip name array for FLEXCOMM. */ +#define FLEXCOMM_CLOCKS \ + { \ + kCLOCK_FlexComm0, kCLOCK_FlexComm1, kCLOCK_FlexComm2, kCLOCK_FlexComm3, kCLOCK_FlexComm4, kCLOCK_FlexComm5, \ + kCLOCK_FlexComm6, kCLOCK_FlexComm7, kCLOCK_Hs_Lspi \ + } +/*! @brief Clock ip name array for LPUART. */ +#define LPUART_CLOCKS \ + { \ + kCLOCK_MinUart0, kCLOCK_MinUart1, kCLOCK_MinUart2, kCLOCK_MinUart3, kCLOCK_MinUart4, kCLOCK_MinUart5, \ + kCLOCK_MinUart6, kCLOCK_MinUart7 \ + } + +/*! @brief Clock ip name array for BI2C. */ +#define BI2C_CLOCKS \ + { \ + kCLOCK_BI2c0, kCLOCK_BI2c1, kCLOCK_BI2c2, kCLOCK_BI2c3, kCLOCK_BI2c4, kCLOCK_BI2c5, kCLOCK_BI2c6, kCLOCK_BI2c7 \ + } +/*! @brief Clock ip name array for LSPI. */ +#define LPSPI_CLOCKS \ + { \ + kCLOCK_LSpi0, kCLOCK_LSpi1, kCLOCK_LSpi2, kCLOCK_LSpi3, kCLOCK_LSpi4, kCLOCK_LSpi5, kCLOCK_LSpi6, kCLOCK_LSpi7 \ + } +/*! @brief Clock ip name array for FLEXI2S. */ +#define FLEXI2S_CLOCKS \ + { \ + kCLOCK_FlexI2s0, kCLOCK_FlexI2s1, kCLOCK_FlexI2s2, kCLOCK_FlexI2s3, kCLOCK_FlexI2s4, kCLOCK_FlexI2s5, \ + kCLOCK_FlexI2s6, kCLOCK_FlexI2s7 \ + } +/*! @brief Clock ip name array for CTIMER. */ +#define CTIMER_CLOCKS \ + { \ + kCLOCK_Timer0, kCLOCK_Timer1, kCLOCK_Timer2, kCLOCK_Timer3, kCLOCK_Timer4 \ + } +/*! @brief Clock ip name array for EZHA */ +#define EZHA_CLOCKS \ + { \ + kCLOCK_Ezha \ + } +/*! @brief Clock ip name array for EZHB */ +#define EZHB_CLOCKS \ + { \ + kCLOCK_Ezhb \ + } +/*! @brief Clock ip name array for COMP */ +#define COMP_CLOCKS \ + { \ + kCLOCK_Comp \ + } +/*! @brief Clock ip name array for USB1CLK. */ +#define USB1CLK_CLOCKS \ + { \ + kCLOCK_Usb1Clk \ + } +/*! @brief Clock ip name array for FREQME. */ +#define FREQME_CLOCKS \ + { \ + kCLOCK_Freqme \ + } +/*! @brief Clock ip name array for USBRAM. */ +#define USBRAM_CLOCKS \ + { \ + kCLOCK_UsbRam1 \ + } +/*! @brief Clock ip name array for CDOG. */ +#define CDOG_CLOCKS \ + { \ + kCLOCK_Cdog \ + } +/*! @brief Clock ip name array for RNG. */ +#define RNG_CLOCKS \ + { \ + kCLOCK_Rng \ + } +/*! @brief Clock ip name array for USBHMR0. */ +#define USBHMR0_CLOCKS \ + { \ + kCLOCK_Usbhmr0 \ + } +/*! @brief Clock ip name array for USBHSL0. */ +#define USBHSL0_CLOCKS \ + { \ + kCLOCK_Usbhsl0 \ + } +/*! @brief Clock ip name array for HashCrypt. */ +#define HASHCRYPT_CLOCKS \ + { \ + kCLOCK_HashCrypt \ + } +/*! @brief Clock ip name array for PLULUT. */ +#define PLULUT_CLOCKS \ + { \ + kCLOCK_PluLut \ + } +/*! @brief Clock ip name array for PUF. */ +#define PUF_CLOCKS \ + { \ + kCLOCK_Puf \ + } +/*! @brief Clock ip name array for CASPER. */ +#define CASPER_CLOCKS \ + { \ + kCLOCK_Casper \ + } +/*! @brief Clock ip name array for ANALOGCTRL. */ +#define ANALOGCTRL_CLOCKS \ + { \ + kCLOCK_AnalogCtrl \ + } +/*! @brief Clock ip name array for HS_LSPI. */ +#define HS_LSPI_CLOCKS \ + { \ + kCLOCK_Hs_Lspi \ + } +/*! @brief Clock ip name array for GPIO_SEC. */ +#define GPIO_SEC_CLOCKS \ + { \ + kCLOCK_Gpio_Sec \ + } +/*! @brief Clock ip name array for GPIO_SEC_INT. */ +#define GPIO_SEC_INT_CLOCKS \ + { \ + kCLOCK_Gpio_Sec_Int \ + } +/*! @brief Clock ip name array for USBD. */ +#define USBD_CLOCKS \ + { \ + kCLOCK_Usbd0, kCLOCK_Usbh1, kCLOCK_Usbd1 \ + } +/*! @brief Clock ip name array for USBH. */ +#define USBH_CLOCKS \ + { \ + kCLOCK_Usbh1 \ + } +#define PLU_CLOCKS \ + { \ + kCLOCK_PluLut \ + } +#define SYSCTL_CLOCKS \ + { \ + kCLOCK_Sysctl \ + } +/*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */ +/*------------------------------------------------------------------------------ + clock_ip_name_t definition: +------------------------------------------------------------------------------*/ + +#define CLK_GATE_REG_OFFSET_SHIFT 8U +#define CLK_GATE_REG_OFFSET_MASK 0xFFFFFF00U +#define CLK_GATE_BIT_SHIFT_SHIFT 0U +#define CLK_GATE_BIT_SHIFT_MASK 0x000000FFU + +#define CLK_GATE_DEFINE(reg_offset, bit_shift) \ + ((((reg_offset) << CLK_GATE_REG_OFFSET_SHIFT) & CLK_GATE_REG_OFFSET_MASK) | \ + (((bit_shift) << CLK_GATE_BIT_SHIFT_SHIFT) & CLK_GATE_BIT_SHIFT_MASK)) + +#define CLK_GATE_ABSTRACT_REG_OFFSET(x) (((uint32_t)(x)&CLK_GATE_REG_OFFSET_MASK) >> CLK_GATE_REG_OFFSET_SHIFT) +#define CLK_GATE_ABSTRACT_BITS_SHIFT(x) (((uint32_t)(x)&CLK_GATE_BIT_SHIFT_MASK) >> CLK_GATE_BIT_SHIFT_SHIFT) + +#define AHB_CLK_CTRL0 0 +#define AHB_CLK_CTRL1 1 +#define AHB_CLK_CTRL2 2 + +/*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */ +typedef enum _clock_ip_name +{ + kCLOCK_IpInvalid = 0U, /*!< Invalid Ip Name. */ + kCLOCK_Rom = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 1), /*!< Clock gate name: Rom. */ + + kCLOCK_Sram1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 3), /*!< Clock gate name: Sram1. */ + + kCLOCK_Sram2 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 4), /*!< Clock gate name: Sram2. */ + + kCLOCK_Flash = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 7), /*!< Clock gate name: Flash. */ + + kCLOCK_Fmc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 8), /*!< Clock gate name: Fmc. */ + + kCLOCK_InputMux = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 11), /*!< Clock gate name: InputMux. */ + + kCLOCK_Iocon = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 13), /*!< Clock gate name: Iocon. */ + + kCLOCK_Gpio0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 14), /*!< Clock gate name: Gpio0. */ + + kCLOCK_Gpio1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 15), /*!< Clock gate name: Gpio1. */ + + kCLOCK_Pint = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 18), /*!< Clock gate name: Pint. */ + + kCLOCK_Gint = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 19), /*!< Clock gate name: Gint. */ + + kCLOCK_Dma0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 20), /*!< Clock gate name: Dma0. */ + + kCLOCK_Crc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 21), /*!< Clock gate name: Crc. */ + + kCLOCK_Wwdt = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 22), /*!< Clock gate name: Wwdt. */ + + kCLOCK_Rtc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 23), /*!< Clock gate name: Rtc. */ + + kCLOCK_Mailbox = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 26), /*!< Clock gate name: Mailbox. */ + + kCLOCK_Adc0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 27), /*!< Clock gate name: Adc0. */ + + kCLOCK_Mrt = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 0), /*!< Clock gate name: Mrt. */ + + kCLOCK_OsTimer0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 1), /*!< Clock gate name: OsTimer0. */ + + kCLOCK_Sct0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 2), /*!< Clock gate name: Sct0. */ + + kCLOCK_Mcan = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 7), /*!< Clock gate name: Mcan. */ + + kCLOCK_Utick0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 10), /*!< Clock gate name: Utick0. */ + + kCLOCK_FlexComm0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), /*!< Clock gate name: FlexComm0. */ + + kCLOCK_FlexComm1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), /*!< Clock gate name: FlexComm1. */ + + kCLOCK_FlexComm2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), /*!< Clock gate name: FlexComm2. */ + + kCLOCK_FlexComm3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), /*!< Clock gate name: FlexComm3. */ + + kCLOCK_FlexComm4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), /*!< Clock gate name: FlexComm4. */ + + kCLOCK_FlexComm5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), /*!< Clock gate name: FlexComm5. */ + + kCLOCK_FlexComm6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), /*!< Clock gate name: FlexComm6. */ + + kCLOCK_FlexComm7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), /*!< Clock gate name: FlexComm7. */ + + kCLOCK_MinUart0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), /*!< Clock gate name: MinUart0. */ + + kCLOCK_MinUart1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), /*!< Clock gate name: MinUart1. */ + + kCLOCK_MinUart2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), /*!< Clock gate name: MinUart2. */ + + kCLOCK_MinUart3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), /*!< Clock gate name: MinUart3. */ + + kCLOCK_MinUart4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), /*!< Clock gate name: MinUart4. */ + + kCLOCK_MinUart5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), /*!< Clock gate name: MinUart5. */ + + kCLOCK_MinUart6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), /*!< Clock gate name: MinUart6. */ + + kCLOCK_MinUart7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), /*!< Clock gate name: MinUart7. */ + + kCLOCK_LSpi0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), /*!< Clock gate name: LSpi0. */ + + kCLOCK_LSpi1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), /*!< Clock gate name: LSpi1. */ + + kCLOCK_LSpi2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), /*!< Clock gate name: LSpi2. */ + + kCLOCK_LSpi3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), /*!< Clock gate name: LSpi3. */ + + kCLOCK_LSpi4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), /*!< Clock gate name: LSpi4. */ + + kCLOCK_LSpi5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), /*!< Clock gate name: LSpi5. */ + + kCLOCK_LSpi6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), /*!< Clock gate name: LSpi6. */ + + kCLOCK_LSpi7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), /*!< Clock gate name: LSpi7. */ + + kCLOCK_BI2c0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), /*!< Clock gate name: BI2c0. */ + + kCLOCK_BI2c1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), /*!< Clock gate name: BI2c1. */ + + kCLOCK_BI2c2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), /*!< Clock gate name: BI2c2. */ + + kCLOCK_BI2c3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), /*!< Clock gate name: BI2c3. */ + + kCLOCK_BI2c4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), /*!< Clock gate name: BI2c4. */ + + kCLOCK_BI2c5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), /*!< Clock gate name: BI2c5. */ + + kCLOCK_BI2c6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), /*!< Clock gate name: BI2c6. */ + + kCLOCK_BI2c7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), /*!< Clock gate name: BI2c7. */ + + kCLOCK_FlexI2s0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), /*!< Clock gate name: FlexI2s0. */ + + kCLOCK_FlexI2s1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), /*!< Clock gate name: FlexI2s1. */ + + kCLOCK_FlexI2s2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), /*!< Clock gate name: FlexI2s2. */ + + kCLOCK_FlexI2s3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), /*!< Clock gate name: FlexI2s3. */ + + kCLOCK_FlexI2s4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), /*!< Clock gate name: FlexI2s4. */ + + kCLOCK_FlexI2s5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), /*!< Clock gate name: FlexI2s5. */ + + kCLOCK_FlexI2s6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), /*!< Clock gate name: FlexI2s6. */ + + kCLOCK_FlexI2s7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), /*!< Clock gate name: FlexI2s7. */ + + kCLOCK_Timer2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 22), /*!< Clock gate name: Timer2. */ + + kCLOCK_Usbd0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 25), /*!< Clock gate name: Usbd0. */ + + kCLOCK_Timer0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 26), /*!< Clock gate name: Timer0. */ + + kCLOCK_Timer1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 27), /*!< Clock gate name: Timer1. */ + + kCLOCK_Ezha = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 30), /*!< Clock gate name: Ezha. */ + + kCLOCK_Ezhb = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 31), /*!< Clock gate name: Ezhb. */ + + kCLOCK_Dma1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 1), /*!< Clock gate name: Dma1. */ + + kCLOCK_Comp = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 2), /*!< Clock gate name: Comp. */ + + kCLOCK_Usbh1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 4), /*!< Clock gate name: Usbh1. */ + + kCLOCK_Usbd1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 5), /*!< Clock gate name: Usbd1. */ + + kCLOCK_UsbRam1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 6), /*!< Clock gate name: UsbRam1. */ + + kCLOCK_Usb1Clk = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 7), /*!< Clock gate name: Usb1Clk. */ + + kCLOCK_Freqme = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 8), /*!< Clock gate name: Freqme. */ + + kCLOCK_Cdog = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 11), /*!< Clock gate name: Cdog. */ + + kCLOCK_Rng = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 13), /*!< Clock gate name: Rng. */ + + kCLOCK_Sysctl = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 15), /*!< Clock gate name: Sysctl. */ + + kCLOCK_Usbhmr0 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 16), /*!< Clock gate name: Usbhmr0. */ + + kCLOCK_Usbhsl0 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 17), /*!< Clock gate name: Usbhsl0. */ + + kCLOCK_HashCrypt = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 18), /*!< Clock gate name: HashCrypt. */ + + kCLOCK_PluLut = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 20), /*!< Clock gate name: PluLut. */ + + kCLOCK_Timer3 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 21), /*!< Clock gate name: Timer3. */ + + kCLOCK_Timer4 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 22), /*!< Clock gate name: Timer4. */ + + kCLOCK_Puf = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 23), /*!< Clock gate name: Puf. */ + + kCLOCK_Casper = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 24), /*!< Clock gate name: Casper. */ + + kCLOCK_AnalogCtrl = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 27), /*!< Clock gate name: AnalogCtrl. */ + + kCLOCK_Hs_Lspi = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 28), /*!< Clock gate name: Lspi. */ + + kCLOCK_Gpio_Sec = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 29), /*!< Clock gate name: GPIO Sec. */ + + kCLOCK_Gpio_Sec_Int = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 30) /*!< Clock gate name: GPIO SEC Int. */ +} clock_ip_name_t; + +/*! @brief Peripherals clock source definition. */ +#define BUS_CLK kCLOCK_BusClk + +#define I2C0_CLK_SRC BUS_CLK + +/*! @brief Clock name used to get clock frequency. */ +typedef enum _clock_name +{ + kCLOCK_CoreSysClk, /*!< Core/system clock (aka MAIN_CLK) */ + kCLOCK_BusClk, /*!< Bus clock (AHB clock) */ + kCLOCK_ClockOut, /*!< CLOCKOUT */ + kCLOCK_FroHf, /*!< FRO48/96 */ + kCLOCK_Pll1Out, /*!< PLL1 Output */ + kCLOCK_Mclk, /*!< MCLK */ + kCLOCK_Fro12M, /*!< FRO12M */ + kCLOCK_Fro1M, /*!< FRO1M */ + kCLOCK_ExtClk, /*!< External Clock */ + kCLOCK_Pll0Out, /*!< PLL0 Output */ + kCLOCK_FlexI2S, /*!< FlexI2S clock */ + +} clock_name_t; + +/*! @brief Clock Mux Switches + * The encoding is as follows each connection identified is 32bits wide while 24bits are valuable + * starting from LSB upwards + * + * [4 bits for choice, 0 means invalid choice] [8 bits mux ID]* + * + */ + +#define CLK_ATTACH_ID(mux, sel, pos) \ + ((((uint32_t)(mux) << 0U) | (((uint32_t)(sel) + 1U) & 0xFU) << 8U) << ((uint32_t)(pos)*12U)) +#define MUX_A(mux, sel) CLK_ATTACH_ID((mux), (sel), 0U) +#define MUX_B(mux, sel, selector) (CLK_ATTACH_ID((mux), (sel), 1U) | ((selector) << 24U)) + +#define GET_ID_ITEM(connection) ((connection)&0xFFFU) +#define GET_ID_NEXT_ITEM(connection) ((connection) >> 12U) +#define GET_ID_ITEM_MUX(connection) (((uint8_t)connection) & 0xFFU) +#define GET_ID_ITEM_SEL(connection) ((uint8_t)((((uint32_t)(connection)&0xF00U) >> 8U) - 1U)) +#define GET_ID_SELECTOR(connection) ((connection)&0xF000000U) + +#define CM_SYSTICKCLKSEL0 0 +#define CM_TRACECLKSEL 2 +#define CM_CTIMERCLKSEL0 3 +#define CM_CTIMERCLKSEL1 4 +#define CM_CTIMERCLKSEL2 5 +#define CM_CTIMERCLKSEL3 6 +#define CM_CTIMERCLKSEL4 7 +#define CM_MAINCLKSELA 8 +#define CM_MAINCLKSELB 9 +#define CM_CLKOUTCLKSEL 10 +#define CM_PLL0CLKSEL 12 +#define CM_PLL1CLKSEL 13 +#define CM_MCANCLKSEL 16 +#define CM_ADCASYNCCLKSEL 17 +#define CM_USB0CLKSEL 18 +#define CM_CLK32KCLKSEL 19 +#define CM_FXCOMCLKSEL0 20 +#define CM_FXCOMCLKSEL1 21 +#define CM_FXCOMCLKSEL2 22 +#define CM_FXCOMCLKSEL3 23 +#define CM_FXCOMCLKSEL4 24 +#define CM_FXCOMCLKSEL5 25 +#define CM_FXCOMCLKSEL6 26 +#define CM_FXCOMCLKSEL7 27 +#define CM_HSLSPICLKSEL 28 +#define CM_MCLKCLKSEL 32 +#define CM_SCTCLKSEL 36 + +#define CM_OSTIMERCLKSEL (62U) +#define CM_RTCOSC32KCLKSEL 63U + +/*! + * @brief The enumerator of clock attach Id. + */ +typedef enum _clock_attach_id +{ + + kFRO12M_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 0, 0), /*!< Attach FRO12M to MAIN_CLK. */ + + kEXT_CLK_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 1) | MUX_B(CM_MAINCLKSELB, 0, 0), /*!< Attach EXT_CLK to MAIN_CLK. */ + + kFRO1M_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 2) | MUX_B(CM_MAINCLKSELB, 0, 0), /*!< Attach FRO1M to MAIN_CLK. */ + + kFRO_HF_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 3) | MUX_B(CM_MAINCLKSELB, 0, 0), /*!< Attach FRO_HF to MAIN_CLK. */ + + kPLL0_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 1, 0), /*!< Attach PLL0 to MAIN_CLK. */ + + kPLL1_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 2, 0), /*!< Attach PLL1 to MAIN_CLK. */ + + kOSC32K_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 3, 0), /*!< Attach OSC32K to MAIN_CLK. */ + + kMAIN_CLK_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 0), /*!< Attach MAIN_CLK to CLKOUT. */ + + kPLL0_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 1), /*!< Attach PLL0 to CLKOUT. */ + + kEXT_CLK_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 2), /*!< Attach EXT_CLK to CLKOUT. */ + + kFRO_HF_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 3), /*!< Attach FRO_HF to CLKOUT. */ + + kFRO1M_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 4), /*!< Attach FRO1M to CLKOUT. */ + + kPLL1_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 5), /*!< Attach PLL1 to CLKOUT. */ + + kOSC32K_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 6), /*!< Attach OSC32K to CLKOUT. */ + + kNONE_to_SYS_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 7), /*!< Attach NONE to SYS_CLKOUT. */ + + kFRO12M_to_PLL0 = MUX_A(CM_PLL0CLKSEL, 0), /*!< Attach FRO12M to PLL0. */ + + kEXT_CLK_to_PLL0 = MUX_A(CM_PLL0CLKSEL, 1), /*!< Attach EXT_CLK to PLL0. */ + + kFRO1M_to_PLL0 = MUX_A(CM_PLL0CLKSEL, 2), /*!< Attach FRO1M to PLL0. */ + + kOSC32K_to_PLL0 = MUX_A(CM_PLL0CLKSEL, 3), /*!< Attach OSC32K to PLL0. */ + + kNONE_to_PLL0 = MUX_A(CM_PLL0CLKSEL, 7), /*!< Attach NONE to PLL0. */ + + kMCAN_DIV_to_MCAN = MUX_A(CM_MCANCLKSEL, 0), /*!< Attach MCAN_DIV to MCAN. */ + + kFRO1M_to_MCAN = MUX_A(CM_MCANCLKSEL, 1), /*!< Attach FRO1M to MCAN. */ + + kOSC32K_to_MCAN = MUX_A(CM_MCANCLKSEL, 2), /*!< Attach OSC32K to MCAN. */ + + kNONE_to_MCAN = MUX_A(CM_MCANCLKSEL, 7), /*!< Attach NONE to MCAN. */ + + kMAIN_CLK_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 0), /*!< Attach MAIN_CLK to ADC_CLK. */ + + kPLL0_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 1), /*!< Attach PLL0 to ADC_CLK. */ + + kFRO_HF_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 2), /*!< Attach FRO_HF to ADC_CLK. */ + + kEXT_CLK_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 4), /*!< Attach EXT_CLK to ADC_CLK. */ + + kNONE_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 7), /*!< Attach NONE to ADC_CLK. */ + + kMAIN_CLK_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 0), /*!< Attach MAIN_CLK to USB0_CLK. */ + + kPLL0_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 1), /*!< Attach PLL0 to USB0_CLK. */ + + kFRO_HF_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 3), /*!< Attach FRO_HF to USB0_CLK. */ + + kPLL1_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 5), /*!< Attach PLL1 to USB0_CLK. */ + + kNONE_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 7), /*!< Attach NONE to USB0_CLK. */ + + kOSC32K_to_CLK32K = MUX_A(CM_CLK32KCLKSEL, 0), /*!< Attach OSC32K to CLK32K. */ + + kFRO1MDIV_to_CLK32K = MUX_A(CM_CLK32KCLKSEL, 1), /*!< Attach FRO1MDIV to CLK32K. */ + + kNONE_to_CLK32K = MUX_A(CM_CLK32KCLKSEL, 7), /*!< Attach NONE to CLK32K. */ + + kMAIN_CLK_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 0), /*!< Attach MAIN_CLK to FLEXCOMM0. */ + + kPLL0_DIV_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 1), /*!< Attach PLL0_DIV to FLEXCOMM0. */ + + kFRO12M_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 2), /*!< Attach FRO12M to FLEXCOMM0. */ + + kFRO_HF_DIV_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM0. */ + + kFRO1M_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 4), /*!< Attach FRO1M to FLEXCOMM0. */ + + kMCLK_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 5), /*!< Attach MCLK to FLEXCOMM0. */ + + kOSC32K_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 6), /*!< Attach OSC32K to FLEXCOMM0. */ + + kNONE_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 7), /*!< Attach NONE to FLEXCOMM0. */ + + kMAIN_CLK_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 0), /*!< Attach MAIN_CLK to FLEXCOMM1. */ + + kPLL0_DIV_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 1), /*!< Attach PLL0_DIV to FLEXCOMM1. */ + + kFRO12M_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 2), /*!< Attach FRO12M to FLEXCOMM1. */ + + kFRO_HF_DIV_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM1. */ + + kFRO1M_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 4), /*!< Attach FRO1M to FLEXCOMM1. */ + + kMCLK_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 5), /*!< Attach MCLK to FLEXCOMM1. */ + + kOSC32K_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 6), /*!< Attach OSC32K to FLEXCOMM1. */ + + kNONE_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 7), /*!< Attach NONE to FLEXCOMM1. */ + + kMAIN_CLK_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 0), /*!< Attach MAIN_CLK to FLEXCOMM2. */ + + kPLL0_DIV_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 1), /*!< Attach PLL0_DIV to FLEXCOMM2. */ + + kFRO12M_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 2), /*!< Attach FRO12M to FLEXCOMM2. */ + + kFRO_HF_DIV_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM2. */ + + kFRO1M_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 4), /*!< Attach FRO1M to FLEXCOMM2. */ + + kMCLK_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 5), /*!< Attach MCLK to FLEXCOMM2. */ + + kOSC32K_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 6), /*!< Attach OSC32K to FLEXCOMM2. */ + + kNONE_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 7), /*!< Attach NONE to FLEXCOMM2. */ + + kMAIN_CLK_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 0), /*!< Attach MAIN_CLK to FLEXCOMM3. */ + + kPLL0_DIV_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 1), /*!< Attach PLL0_DIV to FLEXCOMM3. */ + + kFRO12M_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 2), /*!< Attach FRO12M to FLEXCOMM3. */ + + kFRO_HF_DIV_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM3. */ + + kFRO1M_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 4), /*!< Attach FRO1M to FLEXCOMM3. */ + + kMCLK_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 5), /*!< Attach MCLK to FLEXCOMM3. */ + + kOSC32K_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 6), /*!< Attach OSC32K to FLEXCOMM3. */ + + kNONE_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 7), /*!< Attach NONE to FLEXCOMM3. */ + + kMAIN_CLK_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 0), /*!< Attach MAIN_CLK to FLEXCOMM4. */ + + kPLL0_DIV_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 1), /*!< Attach PLL0_DIV to FLEXCOMM4. */ + + kFRO12M_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 2), /*!< Attach FRO12M to FLEXCOMM4. */ + + kFRO_HF_DIV_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM4. */ + + kFRO1M_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 4), /*!< Attach FRO1M to FLEXCOMM4. */ + + kMCLK_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 5), /*!< Attach MCLK to FLEXCOMM4. */ + + kOSC32K_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 6), /*!< Attach OSC32K to FLEXCOMM4. */ + + kNONE_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 7), /*!< Attach NONE to FLEXCOMM4. */ + + kMAIN_CLK_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 0), /*!< Attach MAIN_CLK to FLEXCOMM5. */ + + kPLL0_DIV_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 1), /*!< Attach PLL0_DIV to FLEXCOMM5. */ + + kFRO12M_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 2), /*!< Attach FRO12M to FLEXCOMM5. */ + + kFRO_HF_DIV_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM5. */ + + kFRO1M_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 4), /*!< Attach FRO1M to FLEXCOMM5. */ + + kMCLK_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 5), /*!< Attach MCLK to FLEXCOMM5. */ + + kOSC32K_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 6), /*!< Attach OSC32K to FLEXCOMM5. */ + + kNONE_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 7), /*!< Attach NONE to FLEXCOMM5. */ + + kMAIN_CLK_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 0), /*!< Attach MAIN_CLK to FLEXCOMM6. */ + + kPLL0_DIV_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 1), /*!< Attach PLL0_DIV to FLEXCOMM6. */ + + kFRO12M_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 2), /*!< Attach FRO12M to FLEXCOMM6. */ + + kFRO_HF_DIV_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM6. */ + + kFRO1M_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 4), /*!< Attach FRO1M to FLEXCOMM6. */ + + kMCLK_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 5), /*!< Attach MCLK to FLEXCOMM6. */ + + kOSC32K_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 6), /*!< Attach OSC32K to FLEXCOMM6. */ + + kNONE_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 7), /*!< Attach NONE to FLEXCOMM6. */ + + kMAIN_CLK_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 0), /*!< Attach MAIN_CLK to FLEXCOMM7. */ + + kPLL0_DIV_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 1), /*!< Attach PLL0_DIV to FLEXCOMM7. */ + + kFRO12M_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 2), /*!< Attach FRO12M to FLEXCOMM7. */ + + kFRO_HF_DIV_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM7. */ + + kFRO1M_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 4), /*!< Attach FRO1M to FLEXCOMM7. */ + + kMCLK_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 5), /*!< Attach MCLK to FLEXCOMM7. */ + + kOSC32K_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 6), /*!< Attach OSC32K to FLEXCOMM7. */ + + kNONE_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 7), /*!< Attach NONE to FLEXCOMM7. */ + + kMAIN_CLK_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 0), /*!< Attach MAIN_CLK to HSLSPI. */ + + kPLL0_DIV_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 1), /*!< Attach PLL0_DIV to HSLSPI. */ + + kFRO12M_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 2), /*!< Attach FRO12M to HSLSPI. */ + + kFRO_HF_DIV_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 3), /*!< Attach FRO_HF_DIV to HSLSPI. */ + + kFRO1M_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 4), /*!< Attach FRO1M to HSLSPI. */ + + kOSC32K_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 6), /*!< Attach OSC32K to HSLSPI. */ + + kNONE_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 7), /*!< Attach NONE to HSLSPI. */ + + kFRO_HF_to_MCLK = MUX_A(CM_MCLKCLKSEL, 0), /*!< Attach FRO_HF to MCLK. */ + + kPLL0_to_MCLK = MUX_A(CM_MCLKCLKSEL, 1), /*!< Attach PLL0 to MCLK. */ + + kNONE_to_MCLK = MUX_A(CM_MCLKCLKSEL, 7), /*!< Attach NONE to MCLK. */ + + kMAIN_CLK_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 0), /*!< Attach MAIN_CLK to SCT_CLK. */ + + kPLL0_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 1), /*!< Attach PLL0 to SCT_CLK. */ + + kEXT_CLK_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 2), /*!< Attach EXT_CLK to SCT_CLK. */ + + kFRO_HF_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 3), /*!< Attach FRO_HF to SCT_CLK. */ + + kMCLK_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 5), /*!< Attach MCLK to SCT_CLK. */ + + kNONE_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 7), /*!< Attach NONE to SCT_CLK. */ + + kFRO32K_to_OSC32K = MUX_A(CM_RTCOSC32KCLKSEL, 0), /*!< Attach FRO32K to OSC32K. */ + + kXTAL32K_to_OSC32K = MUX_A(CM_RTCOSC32KCLKSEL, 1), /*!< Attach XTAL32K to OSC32K. */ + + kOSC32K_to_OSTIMER = MUX_A(CM_OSTIMERCLKSEL, 0), /*!< Attach OSC32K to OSTIMER. */ + + kFRO1M_to_OSTIMER = MUX_A(CM_OSTIMERCLKSEL, 1), /*!< Attach FRO1M to OSTIMER. */ + + kMAIN_CLK_to_OSTIMER = MUX_A(CM_OSTIMERCLKSEL, 2), /*!< Attach MAIN_CLK to OSTIMER. */ + + kTRACE_DIV_to_TRACE = MUX_A(CM_TRACECLKSEL, 0), /*!< Attach TRACE_DIV to TRACE. */ + + kFRO1M_to_TRACE = MUX_A(CM_TRACECLKSEL, 1), /*!< Attach FRO1M to TRACE. */ + + kOSC32K_to_TRACE = MUX_A(CM_TRACECLKSEL, 2), /*!< Attach OSC32K to TRACE. */ + + kNONE_to_TRACE = MUX_A(CM_TRACECLKSEL, 7), /*!< Attach NONE to TRACE. */ + + kSYSTICK_DIV0_to_SYSTICK0 = MUX_A(CM_SYSTICKCLKSEL0, 0), /*!< Attach SYSTICK_DIV0 to SYSTICK0. */ + + kFRO1M_to_SYSTICK0 = MUX_A(CM_SYSTICKCLKSEL0, 1), /*!< Attach FRO1M to SYSTICK0. */ + + kOSC32K_to_SYSTICK0 = MUX_A(CM_SYSTICKCLKSEL0, 2), /*!< Attach OSC32K to SYSTICK0. */ + + kNONE_to_SYSTICK0 = MUX_A(CM_SYSTICKCLKSEL0, 7), /*!< Attach NONE to SYSTICK0. */ + + kFRO12M_to_PLL1 = MUX_A(CM_PLL1CLKSEL, 0), /*!< Attach FRO12M to PLL1. */ + + kEXT_CLK_to_PLL1 = MUX_A(CM_PLL1CLKSEL, 1), /*!< Attach EXT_CLK to PLL1. */ + + kFRO1M_to_PLL1 = MUX_A(CM_PLL1CLKSEL, 2), /*!< Attach FRO1M to PLL1. */ + + kOSC32K_to_PLL1 = MUX_A(CM_PLL1CLKSEL, 3), /*!< Attach OSC32K to PLL1. */ + + kNONE_to_PLL1 = MUX_A(CM_PLL1CLKSEL, 7), /*!< Attach NONE to PLL1. */ + + kMAIN_CLK_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 0), /*!< Attach MAIN_CLK to CTIMER0. */ + + kPLL0_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 1), /*!< Attach PLL0 to CTIMER0. */ + + kFRO_HF_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 3), /*!< Attach FRO_HF to CTIMER0. */ + + kFRO1M_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 4), /*!< Attach FRO1M to CTIMER0. */ + + kMCLK_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 5), /*!< Attach MCLK to CTIMER0. */ + + kOSC32K_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 6), /*!< Attach OSC32K to CTIMER0. */ + + kNONE_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 7), /*!< Attach NONE to CTIMER0. */ + + kMAIN_CLK_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 0), /*!< Attach MAIN_CLK to CTIMER1. */ + + kPLL0_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 1), /*!< Attach PLL0 to CTIMER1. */ + + kFRO_HF_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 3), /*!< Attach FRO_HF to CTIMER1. */ + + kFRO1M_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 4), /*!< Attach FRO1M to CTIMER1. */ + + kMCLK_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 5), /*!< Attach MCLK to CTIMER1. */ + + kOSC32K_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 6), /*!< Attach OSC32K to CTIMER1. */ + + kNONE_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 7), /*!< Attach NONE to CTIMER1. */ + + kMAIN_CLK_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 0), /*!< Attach MAIN_CLK to CTIMER2. */ + + kPLL0_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 1), /*!< Attach PLL0 to CTIMER2. */ + + kFRO_HF_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 3), /*!< Attach FRO_HF to CTIMER2. */ + + kFRO1M_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 4), /*!< Attach FRO1M to CTIMER2. */ + + kMCLK_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 5), /*!< Attach MCLK to CTIMER2. */ + + kOSC32K_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 6), /*!< Attach OSC32K to CTIMER2. */ + + kNONE_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 7), /*!< Attach NONE to CTIMER2. */ + + kMAIN_CLK_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 0), /*!< Attach MAIN_CLK to CTIMER3. */ + + kPLL0_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 1), /*!< Attach PLL0 to CTIMER3. */ + + kFRO_HF_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 3), /*!< Attach FRO_HF to CTIMER3. */ + + kFRO1M_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 4), /*!< Attach FRO1M to CTIMER3. */ + + kMCLK_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 5), /*!< Attach MCLK to CTIMER3. */ + + kOSC32K_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 6), /*!< Attach OSC32K to CTIMER3. */ + + kNONE_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 7), /*!< Attach NONE to CTIMER3. */ + + kMAIN_CLK_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 0), /*!< Attach MAIN_CLK to CTIMER4. */ + + kPLL0_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 1), /*!< Attach PLL0 to CTIMER4. */ + + kFRO_HF_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 3), /*!< Attach FRO_HF to CTIMER4. */ + + kFRO1M_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 4), /*!< Attach FRO1M to CTIMER4. */ + + kMCLK_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 5), /*!< Attach MCLK to CTIMER4. */ + + kOSC32K_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 6), /*!< Attach OSC32K to CTIMER4. */ + + kNONE_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 7), /*!< Attach NONE to CTIMER4. */ + + kNONE_to_NONE = (int)0x80000000U, /*!< Attach NONE to NONE. */ + +} clock_attach_id_t; + +/*! @brief Clock dividers */ +typedef enum _clock_div_name +{ + kCLOCK_DivSystickClk0 = 0, /*!< Systick Clk0 Divider. */ + + kCLOCK_DivArmTrClkDiv = 2, /*!< Arm Tr Clk Div Divider. */ + + kCLOCK_DivCanClk = 3, /*!< Can Clock Divider. */ + + kCLOCK_DivFlexFrg0 = 8, /*!< Flex Frg0 Divider. */ + + kCLOCK_DivFlexFrg1 = 9, /*!< Flex Frg1 Divider. */ + + kCLOCK_DivFlexFrg2 = 10, /*!< Flex Frg2 Divider. */ + + kCLOCK_DivFlexFrg3 = 11, /*!< Flex Frg3 Divider. */ + + kCLOCK_DivFlexFrg4 = 12, /*!< Flex Frg4 Divider. */ + + kCLOCK_DivFlexFrg5 = 13, /*!< Flex Frg5 Divider. */ + + kCLOCK_DivFlexFrg6 = 14, /*!< Flex Frg6 Divider. */ + + kCLOCK_DivFlexFrg7 = 15, /*!< Flex Frg7 Divider. */ + + kCLOCK_DivAhbClk = 32, /*!< Ahb Clock Divider. */ + + kCLOCK_DivClkOut = 33, /*!< Clk Out Divider. */ + + kCLOCK_DivFrohfClk = 34, /*!< Frohf Clock Divider. */ + + kCLOCK_DivWdtClk = 35, /*!< Wdt Clock Divider. */ + + kCLOCK_DivAdcAsyncClk = 37, /*!< Adc Async Clock Divider. */ + + kCLOCK_DivUsb0Clk = 38, /*!< Usb0 Clock Divider. */ + + kCLOCK_DivFro1mClk = 40, /*!< Fro1m Clock Divider. */ + + kCLOCK_DivMClk = 43, /*!< I2S MCLK Clock Divider. */ + + kCLOCK_DivSctClk = 45, /*!< Sct Clock Divider. */ + + kCLOCK_DivPll0Clk = 49 /*!< PLL clock divider. */ +} clock_div_name_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/** + * @brief Enable the clock for specific IP. + * @param clk : Clock to be enabled. + * @return Nothing + */ +static inline void CLOCK_EnableClock(clock_ip_name_t clk) +{ + uint32_t index = CLK_GATE_ABSTRACT_REG_OFFSET(clk); + SYSCON->AHBCLKCTRLSET[index] = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); +} +/** + * @brief Disable the clock for specific IP. + * @param clk : Clock to be Disabled. + * @return Nothing + */ +static inline void CLOCK_DisableClock(clock_ip_name_t clk) +{ + uint32_t index = CLK_GATE_ABSTRACT_REG_OFFSET(clk); + SYSCON->AHBCLKCTRLCLR[index] = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); +} +/** + * @brief Initialize the Core clock to given frequency (12, 48 or 96 MHz). + * Turns on FRO and uses default CCO, if freq is 12000000, then high speed output is off, else high speed output is + * enabled. + * @param iFreq : Desired frequency (must be one of CLK_FRO_12MHZ or CLK_FRO_48MHZ or CLK_FRO_96MHZ) + * @return returns success or fail status. + */ +status_t CLOCK_SetupFROClocking(uint32_t iFreq); +/** + * @brief Set the flash wait states for the input freuqency. + * @param system_freq_hz : Input frequency + * @return Nothing + */ +void CLOCK_SetFLASHAccessCyclesForFreq(uint32_t system_freq_hz); +/** + * @brief Initialize the external osc clock to given frequency. + * @param iFreq : Desired frequency (must be equal to exact rate in Hz) + * @return returns success or fail status. + */ +status_t CLOCK_SetupExtClocking(uint32_t iFreq); +/** + * @brief Initialize the I2S MCLK clock to given frequency. + * @param iFreq : Desired frequency (must be equal to exact rate in Hz) + * @return returns success or fail status. + */ +status_t CLOCK_SetupI2SMClkClocking(uint32_t iFreq); +/** + * @brief Initialize the PLU CLKIN clock to given frequency. + * @param iFreq : Desired frequency (must be equal to exact rate in Hz) + * @return returns success or fail status. + */ +status_t CLOCK_SetupPLUClkInClocking(uint32_t iFreq); +/** + * @brief Configure the clock selection muxes. + * @param connection : Clock to be configured. + * @return Nothing + */ +void CLOCK_AttachClk(clock_attach_id_t connection); +/** + * @brief Get the actual clock attach id. + * This fuction uses the offset in input attach id, then it reads the actual source value in + * the register and combine the offset to obtain an actual attach id. + * @param attachId : Clock attach id to get. + * @return Clock source value. + */ +clock_attach_id_t CLOCK_GetClockAttachId(clock_attach_id_t attachId); +/** + * @brief Setup peripheral clock dividers. + * @param div_name : Clock divider name + * @param divided_by_value: Value to be divided + * @param reset : Whether to reset the divider counter. + * @return Nothing + */ +void CLOCK_SetClkDiv(clock_div_name_t div_name, uint32_t divided_by_value, bool reset); +/** + * @brief Setup rtc 1khz clock divider. + * @param divided_by_value: Value to be divided + * @return Nothing + */ +void CLOCK_SetRtc1khzClkDiv(uint32_t divided_by_value); +/** + * @brief Setup rtc 1hz clock divider. + * @param divided_by_value: Value to be divided + * @return Nothing + */ +void CLOCK_SetRtc1hzClkDiv(uint32_t divided_by_value); + +/** + * @brief Set the flexcomm output frequency. + * @param id : flexcomm instance id + * @param freq : output frequency + * @return 0 : the frequency range is out of range. + * 1 : switch successfully. + */ +uint32_t CLOCK_SetFlexCommClock(uint32_t id, uint32_t freq); + +/*! @brief Return Frequency of flexcomm input clock + * @param id : flexcomm instance id + * @return Frequency value + */ +uint32_t CLOCK_GetFlexCommInputClock(uint32_t id); + +/*! @brief Return Frequency of selected clock + * @return Frequency of selected clock + */ +uint32_t CLOCK_GetFreq(clock_name_t clockName); +/*! @brief Return Frequency of FRO 12MHz + * @return Frequency of FRO 12MHz + */ +uint32_t CLOCK_GetFro12MFreq(void); +/*! @brief Return Frequency of FRO 1MHz + * @return Frequency of FRO 1MHz + */ +uint32_t CLOCK_GetFro1MFreq(void); +/*! @brief Return Frequency of ClockOut + * @return Frequency of ClockOut + */ +uint32_t CLOCK_GetClockOutClkFreq(void); +/*! @brief Return Frequency of Can Clock + * @return Frequency of Can. + */ +uint32_t CLOCK_GetMCanClkFreq(void); +/*! @brief Return Frequency of Adc Clock + * @return Frequency of Adc. + */ +uint32_t CLOCK_GetAdcClkFreq(void); +/*! @brief Return Frequency of Usb0 Clock + * @return Frequency of Usb0 Clock. + */ +uint32_t CLOCK_GetUsb0ClkFreq(void); +/*! @brief Return Frequency of Usb1 Clock + * @return Frequency of Usb1 Clock. + */ +uint32_t CLOCK_GetUsb1ClkFreq(void); +/*! @brief Return Frequency of MClk Clock + * @return Frequency of MClk Clock. + */ +uint32_t CLOCK_GetMclkClkFreq(void); +/*! @brief Return Frequency of SCTimer Clock + * @return Frequency of SCTimer Clock. + */ +uint32_t CLOCK_GetSctClkFreq(void); +/*! @brief Return Frequency of External Clock + * @return Frequency of External Clock. If no external clock is used returns 0. + */ +uint32_t CLOCK_GetExtClkFreq(void); +/*! @brief Return Frequency of Watchdog + * @return Frequency of Watchdog + */ +uint32_t CLOCK_GetWdtClkFreq(void); +/*! @brief Return Frequency of High-Freq output of FRO + * @return Frequency of High-Freq output of FRO + */ +uint32_t CLOCK_GetFroHfFreq(void); +/*! @brief Return Frequency of PLL + * @return Frequency of PLL + */ +uint32_t CLOCK_GetPll0OutFreq(void); +/*! @brief Return Frequency of USB PLL + * @return Frequency of PLL + */ +uint32_t CLOCK_GetPll1OutFreq(void); +/*! @brief Return Frequency of 32kHz osc + * @return Frequency of 32kHz osc + */ +uint32_t CLOCK_GetOsc32KFreq(void); +/*! @brief Return Frequency of Core System + * @return Frequency of Core System + */ +uint32_t CLOCK_GetCoreSysClkFreq(void); +/*! @brief Return Frequency of I2S MCLK Clock + * @return Frequency of I2S MCLK Clock + */ +uint32_t CLOCK_GetI2SMClkFreq(void); +/*! @brief Return Frequency of PLU CLKIN Clock + * @return Frequency of PLU CLKIN Clock + */ +uint32_t CLOCK_GetPLUClkInFreq(void); +/*! @brief Return Frequency of FlexComm Clock + * @return Frequency of FlexComm Clock + */ +uint32_t CLOCK_GetFlexCommClkFreq(uint32_t id); +/*! @brief Return Frequency of High speed SPI Clock + * @return Frequency of High speed SPI Clock + */ +uint32_t CLOCK_GetHsLspiClkFreq(void); +/*! @brief Return Frequency of CTimer functional Clock + * @return Frequency of CTimer functional Clock + */ +uint32_t CLOCK_GetCTimerClkFreq(uint32_t id); +/*! @brief Return Frequency of SystickClock + * @return Frequency of Systick Clock + */ +uint32_t CLOCK_GetSystickClkFreq(uint32_t id); + +/*! @brief Return PLL0 input clock rate + * @return PLL0 input clock rate + */ +uint32_t CLOCK_GetPLL0InClockRate(void); + +/*! @brief Return PLL1 input clock rate + * @return PLL1 input clock rate + */ +uint32_t CLOCK_GetPLL1InClockRate(void); + +/*! @brief Return PLL0 output clock rate + * @param recompute : Forces a PLL rate recomputation if true + * @return PLL0 output clock rate + * @note The PLL rate is cached in the driver in a variable as + * the rate computation function can take some time to perform. It + * is recommended to use 'false' with the 'recompute' parameter. + */ +uint32_t CLOCK_GetPLL0OutClockRate(bool recompute); + +/*! @brief Return PLL1 output clock rate + * @param recompute : Forces a PLL rate recomputation if true + * @return PLL1 output clock rate + * @note The PLL rate is cached in the driver in a variable as + * the rate computation function can take some time to perform. It + * is recommended to use 'false' with the 'recompute' parameter. + */ +uint32_t CLOCK_GetPLL1OutClockRate(bool recompute); + +/*! @brief Enables and disables PLL0 bypass mode + * @brief bypass : true to bypass PLL0 (PLL0 output = PLL0 input, false to disable bypass + * @return PLL0 output clock rate + */ +__STATIC_INLINE void CLOCK_SetBypassPLL0(bool bypass) +{ + if (bypass) + { + SYSCON->PLL0CTRL |= (1UL << SYSCON_PLL0CTRL_BYPASSPLL_SHIFT); + } + else + { + SYSCON->PLL0CTRL &= ~(1UL << SYSCON_PLL0CTRL_BYPASSPLL_SHIFT); + } +} + +/*! @brief Enables and disables PLL1 bypass mode + * @brief bypass : true to bypass PLL1 (PLL1 output = PLL1 input, false to disable bypass + * @return PLL1 output clock rate + */ +__STATIC_INLINE void CLOCK_SetBypassPLL1(bool bypass) +{ + if (bypass) + { + SYSCON->PLL1CTRL |= (1UL << SYSCON_PLL1CTRL_BYPASSPLL_SHIFT); + } + else + { + SYSCON->PLL1CTRL &= ~(1UL << SYSCON_PLL1CTRL_BYPASSPLL_SHIFT); + } +} + +/*! @brief Check if PLL is locked or not + * @return true if the PLL is locked, false if not locked + */ +__STATIC_INLINE bool CLOCK_IsPLL0Locked(void) +{ + return (bool)((SYSCON->PLL0STAT & SYSCON_PLL0STAT_LOCK_MASK) != 0UL); +} + +/*! @brief Check if PLL1 is locked or not + * @return true if the PLL1 is locked, false if not locked + */ +__STATIC_INLINE bool CLOCK_IsPLL1Locked(void) +{ + return (bool)((SYSCON->PLL1STAT & SYSCON_PLL1STAT_LOCK_MASK) != 0UL); +} + +/*! @brief Store the current PLL0 rate + * @param rate: Current rate of the PLL0 + * @return Nothing + **/ +void CLOCK_SetStoredPLL0ClockRate(uint32_t rate); + +/*! @brief PLL configuration structure flags for 'flags' field + * These flags control how the PLL configuration function sets up the PLL setup structure.
+ * + * When the PLL_CONFIGFLAG_USEINRATE flag is selected, the 'InputRate' field in the + * configuration structure must be assigned with the expected PLL frequency. If the + * PLL_CONFIGFLAG_USEINRATE is not used, 'InputRate' is ignored in the configuration + * function and the driver will determine the PLL rate from the currently selected + * PLL source. This flag might be used to configure the PLL input clock more accurately + * when using the WDT oscillator or a more dyanmic CLKIN source.
+ * + * When the PLL_CONFIGFLAG_FORCENOFRACT flag is selected, the PLL hardware for the + * automatic bandwidth selection, Spread Spectrum (SS) support, and fractional M-divider + * are not used.
+ */ +#define PLL_CONFIGFLAG_USEINRATE (1U << 0U) /*!< Flag to use InputRate in PLL configuration structure for setup */ +#define PLL_CONFIGFLAG_FORCENOFRACT (1U << 2U) +/*!< Force non-fractional output mode, PLL output will not use the fractional, automatic bandwidth, or SS hardware */ + +/*! @brief PLL Spread Spectrum (SS) Programmable modulation frequency + * See (MF) field in the PLL0SSCG1 register in the UM. + */ +typedef enum _ss_progmodfm +{ + kSS_MF_512 = (0 << 20), /*!< Nss = 512 (fm ? 3.9 - 7.8 kHz) */ + kSS_MF_384 = (1 << 20), /*!< Nss ?= 384 (fm ? 5.2 - 10.4 kHz) */ + kSS_MF_256 = (2 << 20), /*!< Nss = 256 (fm ? 7.8 - 15.6 kHz) */ + kSS_MF_128 = (3 << 20), /*!< Nss = 128 (fm ? 15.6 - 31.3 kHz) */ + kSS_MF_64 = (4 << 20), /*!< Nss = 64 (fm ? 32.3 - 64.5 kHz) */ + kSS_MF_32 = (5 << 20), /*!< Nss = 32 (fm ? 62.5- 125 kHz) */ + kSS_MF_24 = (6 << 20), /*!< Nss ?= 24 (fm ? 83.3- 166.6 kHz) */ + kSS_MF_16 = (7 << 20) /*!< Nss = 16 (fm ? 125- 250 kHz) */ +} ss_progmodfm_t; + +/*! @brief PLL Spread Spectrum (SS) Programmable frequency modulation depth + * See (MR) field in the PLL0SSCG1 register in the UM. + */ +typedef enum _ss_progmoddp +{ + kSS_MR_K0 = (0 << 23), /*!< k = 0 (no spread spectrum) */ + kSS_MR_K1 = (1 << 23), /*!< k = 1 */ + kSS_MR_K1_5 = (2 << 23), /*!< k = 1.5 */ + kSS_MR_K2 = (3 << 23), /*!< k = 2 */ + kSS_MR_K3 = (4 << 23), /*!< k = 3 */ + kSS_MR_K4 = (5 << 23), /*!< k = 4 */ + kSS_MR_K6 = (6 << 23), /*!< k = 6 */ + kSS_MR_K8 = (7 << 23) /*!< k = 8 */ +} ss_progmoddp_t; + +/*! @brief PLL Spread Spectrum (SS) Modulation waveform control + * See (MC) field in the PLL0SSCG1 register in the UM.
+ * Compensation for low pass filtering of the PLL to get a triangular + * modulation at the output of the PLL, giving a flat frequency spectrum. + */ +typedef enum _ss_modwvctrl +{ + kSS_MC_NOC = (0 << 26), /*!< no compensation */ + kSS_MC_RECC = (2 << 26), /*!< recommended setting */ + kSS_MC_MAXC = (3 << 26), /*!< max. compensation */ +} ss_modwvctrl_t; + +/*! @brief PLL configuration structure + * + * This structure can be used to configure the settings for a PLL + * setup structure. Fill in the desired configuration for the PLL + * and call the PLL setup function to fill in a PLL setup structure. + */ +typedef struct _pll_config +{ + uint32_t desiredRate; /*!< Desired PLL rate in Hz */ + uint32_t inputRate; /*!< PLL input clock in Hz, only used if PLL_CONFIGFLAG_USEINRATE flag is set */ + uint32_t flags; /*!< PLL configuration flags, Or'ed value of PLL_CONFIGFLAG_* definitions */ + ss_progmodfm_t ss_mf; /*!< SS Programmable modulation frequency, only applicable when not using + PLL_CONFIGFLAG_FORCENOFRACT flag */ + ss_progmoddp_t ss_mr; /*!< SS Programmable frequency modulation depth, only applicable when not using + PLL_CONFIGFLAG_FORCENOFRACT flag */ + ss_modwvctrl_t + ss_mc; /*!< SS Modulation waveform control, only applicable when not using PLL_CONFIGFLAG_FORCENOFRACT flag */ + bool mfDither; /*!< false for fixed modulation frequency or true for dithering, only applicable when not using + PLL_CONFIGFLAG_FORCENOFRACT flag */ + +} pll_config_t; + +/*! @brief PLL setup structure flags for 'flags' field + * These flags control how the PLL setup function sets up the PLL + */ +#define PLL_SETUPFLAG_POWERUP (1U << 0U) /*!< Setup will power on the PLL after setup */ +#define PLL_SETUPFLAG_WAITLOCK (1U << 1U) /*!< Setup will wait for PLL lock, implies the PLL will be pwoered on */ +#define PLL_SETUPFLAG_ADGVOLT (1U << 2U) /*!< Optimize system voltage for the new PLL rate */ +#define PLL_SETUPFLAG_USEFEEDBACKDIV2 (1U << 3U) /*!< Use feedback divider by 2 in divider path */ + +/*! @brief PLL0 setup structure + * This structure can be used to pre-build a PLL setup configuration + * at run-time and quickly set the PLL to the configuration. It can be + * populated with the PLL setup function. If powering up or waiting + * for PLL lock, the PLL input clock source should be configured prior + * to PLL setup. + */ +typedef struct _pll_setup +{ + uint32_t pllctrl; /*!< PLL control register PLL0CTRL */ + uint32_t pllndec; /*!< PLL NDEC register PLL0NDEC */ + uint32_t pllpdec; /*!< PLL PDEC register PLL0PDEC */ + uint32_t pllmdec; /*!< PLL MDEC registers PLL0PDEC */ + uint32_t pllsscg[2]; /*!< PLL SSCTL registers PLL0SSCG*/ + uint32_t pllRate; /*!< Acutal PLL rate */ + uint32_t flags; /*!< PLL setup flags, Or'ed value of PLL_SETUPFLAG_* definitions */ +} pll_setup_t; + +/*! @brief PLL status definitions + */ +typedef enum _pll_error +{ + kStatus_PLL_Success = MAKE_STATUS(kStatusGroup_Generic, 0), /*!< PLL operation was successful */ + kStatus_PLL_OutputTooLow = MAKE_STATUS(kStatusGroup_Generic, 1), /*!< PLL output rate request was too low */ + kStatus_PLL_OutputTooHigh = MAKE_STATUS(kStatusGroup_Generic, 2), /*!< PLL output rate request was too high */ + kStatus_PLL_InputTooLow = MAKE_STATUS(kStatusGroup_Generic, 3), /*!< PLL input rate is too low */ + kStatus_PLL_InputTooHigh = MAKE_STATUS(kStatusGroup_Generic, 4), /*!< PLL input rate is too high */ + kStatus_PLL_OutsideIntLimit = MAKE_STATUS(kStatusGroup_Generic, 5), /*!< Requested output rate isn't possible */ + kStatus_PLL_CCOTooLow = MAKE_STATUS(kStatusGroup_Generic, 6), /*!< Requested CCO rate isn't possible */ + kStatus_PLL_CCOTooHigh = MAKE_STATUS(kStatusGroup_Generic, 7) /*!< Requested CCO rate isn't possible */ +} pll_error_t; + +/*! @brief USB FS clock source definition. */ +typedef enum _clock_usbfs_src +{ + kCLOCK_UsbfsSrcFro = (uint32_t)kCLOCK_FroHf, /*!< Use FRO 96 MHz. */ + kCLOCK_UsbfsSrcPll0 = (uint32_t)kCLOCK_Pll0Out, /*!< Use PLL0 output. */ + kCLOCK_UsbfsSrcMainClock = (uint32_t)kCLOCK_CoreSysClk, /*!< Use Main clock. */ + kCLOCK_UsbfsSrcPll1 = (uint32_t)kCLOCK_Pll1Out, /*!< Use PLL1 clock. */ + + kCLOCK_UsbfsSrcNone = + SYSCON_USB0CLKSEL_SEL(7) /*!COMP & ~(PMC_COMP_LOWPOWER_MASK | PMC_COMP_HYST_MASK | PMC_COMP_FILTERCGF_CLKDIV_MASK | + PMC_COMP_FILTERCGF_SAMPLEMODE_MASK)); + + if (true == config->enableLowPower) + { + tmpReg |= PMC_COMP_LOWPOWER_MASK; + } + else + { + tmpReg &= ~PMC_COMP_LOWPOWER_MASK; + } + + if (true == config->enableHysteresis) + { + tmpReg |= PMC_COMP_HYST_MASK; + } + else + { + tmpReg &= ~PMC_COMP_HYST_MASK; + } + + tmpReg |= (PMC_COMP_FILTERCGF_CLKDIV(config->filterClockDivider) | + PMC_COMP_FILTERCGF_SAMPLEMODE(config->filterSampleMode)); + + PMC->COMP = tmpReg; +} + +/*! + * @brief CMP deinitialization. + * + * This function gates the clock for CMP module. + */ +void CMP_Deinit(void) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Disable the clock. */ + CLOCK_DisableClock(kCLOCK_Comp); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/*! + * @brief Initializes the CMP user configuration structure. + * + * This function initializes the user configuration structure to these default values. + * @code + * config->enableHysteresis = true; + * config->enableLowPower = true; + * config->filterClockDivider = kCMP_FilterClockDivide1; + * config->filterSampleMode = kCMP_FilterSampleMode0; + * @endcode + * @param config Pointer to the configuration structure. + */ +void CMP_GetDefaultConfig(cmp_config_t *config) +{ + /* Initializes the configure structure to zero. */ + (void)memset(config, 0, sizeof(*config)); + + config->enableHysteresis = true; + config->enableLowPower = true; + config->filterClockDivider = kCMP_FilterClockDivide1; + config->filterSampleMode = kCMP_FilterSampleMode0; +} + +/*! + * @brief Configures the VREFINPUT. + * + * @param config Pointer to the configuration structure. + */ +void CMP_SetVREF(const cmp_vref_config_t *config) +{ + assert(NULL != config); + assert(config->vrefValue < 32U); + + uint32_t tmpReg = PMC->COMP & ~(PMC_COMP_VREF_MASK | PMC_COMP_VREFINPUT_MASK); + + tmpReg |= PMC_COMP_VREFINPUT(config->vrefSource) | PMC_COMP_VREF(config->vrefValue); + + PMC->COMP = tmpReg; +} diff --git a/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_cmp.h b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_cmp.h new file mode 100644 index 0000000000..1afdc97280 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_cmp.h @@ -0,0 +1,291 @@ +/* + * Copyright 2018-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __FSL_CMP_H_ +#define __FSL_CMP_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup cmp_1 + * @{ + */ + +/****************************************************************************** + * Definitions. + *****************************************************************************/ +/*! @name Driver version */ +/*@{*/ +/*! @brief Driver version 2.2.1. */ +#define FSL_CMP_DRIVER_VERSION (MAKE_VERSION(2U, 2U, 1U)) +/*@}*/ + +/*! @brief CMP input mux for positive and negative sides. */ +enum _cmp_input_mux +{ + kCMP_InputVREF = 0U, /*!< Cmp input from VREF. */ + kCMP_Input1 = 1U, /*!< Cmp input source 1. */ + kCMP_Input2 = 2U, /*!< Cmp input source 2. */ + kCMP_Input3 = 3U, /*!< Cmp input source 3. */ + kCMP_Input4 = 4U, /*!< Cmp input source 4. */ + kCMP_Input5 = 5U, /*!< Cmp input source 5. */ +}; + +/*! @brief CMP interrupt type. */ +enum _cmp_interrupt_type +{ + kCMP_EdgeDisable = 0U, /*!< Disable edge interupt. */ + kCMP_EdgeRising = 2U, /*!< Interrupt on falling edge. */ + kCMP_EdgeFalling = 4U, /*!< Interrupt on rising edge. */ + kCMP_EdgeRisingFalling = 6U, /*!< Interrupt on both rising and falling edges. */ + + kCMP_LevelDisable = 1U, /*!< Disable level interupt. */ + kCMP_LevelHigh = 3U, /*!< Interrupt on high level. */ + kCMP_LevelLow = 5U, /*!< Interrupt on low level. */ +}; + +/*! @brief CMP Voltage Reference source. */ +typedef enum _cmp_vref_source +{ + KCMP_VREFSourceVDDA = 1U, /*!< Select VDDA as VREF. */ + KCMP_VREFSourceInternalVREF = 0U, /*!< Select internal VREF as VREF. */ +} cmp_vref_source_t; + +typedef struct _cmp_vref_config +{ + cmp_vref_source_t vrefSource; /*!< Reference voltage source. */ + uint8_t vrefValue; /*!< Reference voltage step. Available range is 0-31. Per step equals to VREFINPUT/31. */ +} cmp_vref_config_t; + +/*! @brief CMP Filter sample mode. */ +typedef enum _cmp_filtercgf_samplemode +{ + kCMP_FilterSampleMode0 = 0U, /*!< Bypass mode. Filtering is disabled. */ + kCMP_FilterSampleMode1 = 1U, /*!< Filter 1 clock period. */ + kCMP_FilterSampleMode2 = 2U, /*!< Filter 2 clock period. */ + kCMP_FilterSampleMode3 = 3U /*!< Filter 3 clock period. */ +} cmp_filtercgf_samplemode_t; + +/*! @brief CMP Filter clock divider. */ +typedef enum _cmp_filtercgf_clkdiv +{ + kCMP_FilterClockDivide1 = 0U, /*!< Filter clock period duration equals 1 analog comparator clock period. */ + kCMP_FilterClockDivide2 = 1U, /*!< Filter clock period duration equals 2 analog comparator clock period. */ + kCMP_FilterClockDivide4 = 2U, /*!< Filter clock period duration equals 4 analog comparator clock period. */ + kCMP_FilterClockDivide8 = 3U, /*!< Filter clock period duration equals 8 analog comparator clock period. */ + kCMP_FilterClockDivide16 = 4U, /*!< Filter clock period duration equals 16 analog comparator clock period. */ + kCMP_FilterClockDivide32 = 5U, /*!< Filter clock period duration equals 32 analog comparator clock period. */ + kCMP_FilterClockDivide64 = 6U /*!< Filter clock period duration equals 64 analog comparator clock period. */ +} cmp_filtercgf_clkdiv_t; + +/*! @brief CMP configuration structure. */ +typedef struct _cmp_config +{ + bool enableHysteresis; /*!< Enable hysteresis. */ + bool enableLowPower; /*!< Enable low power mode. */ + cmp_filtercgf_clkdiv_t filterClockDivider; /* Filter clock divider. Filter clock equals the Analog Comparator clock + divided by 2^FILTERCGF_CLKDIV. */ + cmp_filtercgf_samplemode_t + filterSampleMode; /* Filter sample mode. Control the filtering of the Analog Comparator output. */ +} cmp_config_t; + +/************************************************************************************************* + * API + ************************************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief CMP initialization. + * + * This function enables the CMP module and do necessary settings. + * + * @param config Pointer to the configuration structure. + */ +void CMP_Init(const cmp_config_t *config); + +/*! + * @brief CMP deinitialization. + * + * This function gates the clock for CMP module. + */ +void CMP_Deinit(void); + +/*! + * @brief Initializes the CMP user configuration structure. + * + * This function initializes the user configuration structure to these default values. + * @code + * config->enableHysteresis = true; + * config->enableLowPower = true; + * config->filterClockDivider = kCMP_FilterClockDivide1; + * config->filterSampleMode = kCMP_FilterSampleMode0; + * @endcode + * @param config Pointer to the configuration structure. + */ +void CMP_GetDefaultConfig(cmp_config_t *config); + +/* @} */ + +/*! + * @name Compare Interface + * @{ + */ + +/* + * @brief Set the input channels for the comparator. + * + * @param positiveChannel Positive side input channel number. See "_cmp_input_mux". + * @param negativeChannel Negative side input channel number. See "_cmp_input_mux". + */ +static inline void CMP_SetInputChannels(uint8_t positiveChannel, uint8_t negativeChannel) +{ + PMC->COMP &= ~(PMC_COMP_PMUX_MASK | PMC_COMP_NMUX_MASK); + PMC->COMP |= (PMC_COMP_PMUX(positiveChannel) | PMC_COMP_NMUX(negativeChannel)); +} + +/*! + * @brief Configures the VREFINPUT. + * + * @param config Pointer to the configuration structure. + */ +void CMP_SetVREF(const cmp_vref_config_t *config); + +/*! + * @brief Get CMP compare output. + * + * @return The output result. true: voltage on positive side is greater than negative side. + * false: voltage on positive side is lower than negative side. + */ +static inline bool CMP_GetOutput(void) +{ + return SYSCON_COMP_INT_STATUS_VAL_MASK == (SYSCON->COMP_INT_STATUS & SYSCON_COMP_INT_STATUS_VAL_MASK); +} + +/* @} */ + +/*! + * @name Interrupt Interface + * @{ + */ + +/*! + * @brief CMP enable interrupt. + * + * @param type CMP interrupt type. See "_cmp_interrupt_type". + */ +static inline void CMP_EnableInterrupt(uint32_t type) +{ + SYSCON->COMP_INT_CTRL |= (SYSCON_COMP_INT_CTRL_INT_CTRL(type) | SYSCON_COMP_INT_CTRL_INT_ENABLE_MASK); +} + +/*! + * @brief CMP disable interrupt. + * + */ +static inline void CMP_DisableInterrupt(void) +{ + SYSCON->COMP_INT_CTRL &= ~SYSCON_COMP_INT_CTRL_INT_ENABLE_MASK; +} + +/*! + * @brief CMP clear interrupt. + * + */ +static inline void CMP_ClearInterrupt(void) +{ + SYSCON->COMP_INT_CTRL |= SYSCON_COMP_INT_CTRL_INT_CLEAR_MASK; +} + +/*! + * @brief Select which Analog comparator output (filtered or un-filtered) is used for interrupt detection. + * + * @param enable false: Select Analog Comparator raw output (unfiltered) as input for interrupt detection. + * true: Select Analog Comparator filtered output as input for interrupt detection. + * + * @note: When CMP is configured as the wakeup source in power down mode, this function must use the raw output as the + * interupt source, that is, call this function and set parameter enable to false. + */ +static inline void CMP_EnableFilteredInterruptSource(bool enable) +{ + if (enable) + { + SYSCON->COMP_INT_CTRL &= ~SYSCON_COMP_INT_CTRL_INT_SOURCE_MASK; + } + else + { + SYSCON->COMP_INT_CTRL |= SYSCON_COMP_INT_CTRL_INT_SOURCE_MASK; + } +} +/* @} */ + +/*! + * @name Status Interface + * @{ + */ + +/*! + * @brief Get CMP interrupt status before interupt enable. + * + * @return Interrupt status. true: interrupt pending, + * false: no interrupt pending. + */ +static inline bool CMP_GetPreviousInterruptStatus(void) +{ + return SYSCON_COMP_INT_STATUS_STATUS_MASK == (SYSCON->COMP_INT_STATUS & SYSCON_COMP_INT_STATUS_STATUS_MASK); +} + +/*! + * @brief Get CMP interrupt status after interupt enable. + * + * @return Interrupt status. true: interrupt pending, + * false: no interrupt pending. + */ +static inline bool CMP_GetInterruptStatus(void) +{ + return SYSCON_COMP_INT_STATUS_INT_STATUS_MASK == (SYSCON->COMP_INT_STATUS & SYSCON_COMP_INT_STATUS_INT_STATUS_MASK); +} +/* @} */ + +/*! + * @name Filter Interface + * @{ + */ + +/*! + * @brief CMP Filter Sample Config. + * + * This function allows the users to configure the sampling mode and clock divider of the CMP Filter. + * + * @param filterSampleMode CMP Select filter sample mode + * @param filterClockDivider CMP Set fileter clock divider + */ +static inline void CMP_FilterSampleConfig(cmp_filtercgf_samplemode_t filterSampleMode, + cmp_filtercgf_clkdiv_t filterClockDivider) +{ + uint32_t comp = PMC->COMP; + + comp &= ~(PMC_COMP_FILTERCGF_CLKDIV_MASK | PMC_COMP_FILTERCGF_SAMPLEMODE_MASK); + comp |= (((uint32_t)filterClockDivider << PMC_COMP_FILTERCGF_CLKDIV_SHIFT) | + ((uint32_t)filterSampleMode << PMC_COMP_FILTERCGF_SAMPLEMODE_SHIFT)); + + PMC->COMP = comp; +} +/* @} */ + +#if defined(__cplusplus) +} +#endif + +/*! @} */ +#endif /* __FSL_CMP_H_ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_common.c b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_common.c new file mode 100644 index 0000000000..d3af9fdfc6 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_common.c @@ -0,0 +1,85 @@ +/* + * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_common.h" + +#define SDK_MEM_MAGIC_NUMBER 12345U + +typedef struct _mem_align_control_block +{ + uint16_t identifier; /*!< Identifier for the memory control block. */ + uint16_t offset; /*!< offset from aligned address to real address */ +} mem_align_cb_t; + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.common" +#endif + +#if !((defined(__DSC__) && defined(__CW__))) +void *SDK_Malloc(size_t size, size_t alignbytes) +{ + mem_align_cb_t *p_cb = NULL; + uint32_t alignedsize; + + /* Check overflow. */ + alignedsize = (uint32_t)(unsigned int)SDK_SIZEALIGN(size, alignbytes); + if (alignedsize < size) + { + return NULL; + } + + if (alignedsize > SIZE_MAX - alignbytes - sizeof(mem_align_cb_t)) + { + return NULL; + } + + alignedsize += alignbytes + (uint32_t)sizeof(mem_align_cb_t); + + union + { + void *pointer_value; + uintptr_t unsigned_value; + } p_align_addr, p_addr; + + p_addr.pointer_value = malloc((size_t)alignedsize); + + if (p_addr.pointer_value == NULL) + { + return NULL; + } + + p_align_addr.unsigned_value = SDK_SIZEALIGN(p_addr.unsigned_value + sizeof(mem_align_cb_t), alignbytes); + + p_cb = (mem_align_cb_t *)(p_align_addr.unsigned_value - 4U); + p_cb->identifier = SDK_MEM_MAGIC_NUMBER; + p_cb->offset = (uint16_t)(p_align_addr.unsigned_value - p_addr.unsigned_value); + + return p_align_addr.pointer_value; +} + +void SDK_Free(void *ptr) +{ + union + { + void *pointer_value; + uintptr_t unsigned_value; + } p_free; + p_free.pointer_value = ptr; + mem_align_cb_t *p_cb = (mem_align_cb_t *)(p_free.unsigned_value - 4U); + + if (p_cb->identifier != SDK_MEM_MAGIC_NUMBER) + { + return; + } + + p_free.unsigned_value = p_free.unsigned_value - p_cb->offset; + + free(p_free.pointer_value); +} +#endif diff --git a/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_common.h b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_common.h new file mode 100644 index 0000000000..d9cb304f2f --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_common.h @@ -0,0 +1,316 @@ +/* + * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_COMMON_H_ +#define _FSL_COMMON_H_ + +#include +#include +#include +#include +#include + +#if defined(__ICCARM__) || (defined(__CC_ARM) || defined(__ARMCC_VERSION)) || defined(__GNUC__) +#include +#endif + +#include "fsl_device_registers.h" + +/*! + * @addtogroup ksdk_common + * @{ + */ + +/******************************************************************************* + * Configurations + ******************************************************************************/ + +/*! @brief Macro to use the default weak IRQ handler in drivers. */ +#ifndef FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ +#define FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ 1 +#endif + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief Construct a status code value from a group and code number. */ +#define MAKE_STATUS(group, code) ((((group)*100L) + (code))) + +/*! @brief Construct the version number for drivers. + * + * The driver version is a 32-bit number, for both 32-bit platforms(such as Cortex M) + * and 16-bit platforms(such as DSC). + * + * @verbatim + + | Unused || Major Version || Minor Version || Bug Fix | + 31 25 24 17 16 9 8 0 + + @endverbatim + */ +#define MAKE_VERSION(major, minor, bugfix) (((major) * 65536L) + ((minor) * 256L) + (bugfix)) + +/*! @name Driver version */ +/*@{*/ +/*! @brief common driver version. */ +#define FSL_COMMON_DRIVER_VERSION (MAKE_VERSION(2, 3, 2)) +/*@}*/ + +/* Debug console type definition. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_NONE 0U /*!< No debug console. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_UART 1U /*!< Debug console based on UART. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_LPUART 2U /*!< Debug console based on LPUART. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_LPSCI 3U /*!< Debug console based on LPSCI. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_USBCDC 4U /*!< Debug console based on USBCDC. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM 5U /*!< Debug console based on FLEXCOMM. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_IUART 6U /*!< Debug console based on i.MX UART. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_VUSART 7U /*!< Debug console based on LPC_VUSART. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_MINI_USART 8U /*!< Debug console based on LPC_USART. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_SWO 9U /*!< Debug console based on SWO. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_QSCI 10U /*!< Debug console based on QSCI. */ + +/*! @brief Status group numbers. */ +enum _status_groups +{ + kStatusGroup_Generic = 0, /*!< Group number for generic status codes. */ + kStatusGroup_FLASH = 1, /*!< Group number for FLASH status codes. */ + kStatusGroup_LPSPI = 4, /*!< Group number for LPSPI status codes. */ + kStatusGroup_FLEXIO_SPI = 5, /*!< Group number for FLEXIO SPI status codes. */ + kStatusGroup_DSPI = 6, /*!< Group number for DSPI status codes. */ + kStatusGroup_FLEXIO_UART = 7, /*!< Group number for FLEXIO UART status codes. */ + kStatusGroup_FLEXIO_I2C = 8, /*!< Group number for FLEXIO I2C status codes. */ + kStatusGroup_LPI2C = 9, /*!< Group number for LPI2C status codes. */ + kStatusGroup_UART = 10, /*!< Group number for UART status codes. */ + kStatusGroup_I2C = 11, /*!< Group number for UART status codes. */ + kStatusGroup_LPSCI = 12, /*!< Group number for LPSCI status codes. */ + kStatusGroup_LPUART = 13, /*!< Group number for LPUART status codes. */ + kStatusGroup_SPI = 14, /*!< Group number for SPI status code.*/ + kStatusGroup_XRDC = 15, /*!< Group number for XRDC status code.*/ + kStatusGroup_SEMA42 = 16, /*!< Group number for SEMA42 status code.*/ + kStatusGroup_SDHC = 17, /*!< Group number for SDHC status code */ + kStatusGroup_SDMMC = 18, /*!< Group number for SDMMC status code */ + kStatusGroup_SAI = 19, /*!< Group number for SAI status code */ + kStatusGroup_MCG = 20, /*!< Group number for MCG status codes. */ + kStatusGroup_SCG = 21, /*!< Group number for SCG status codes. */ + kStatusGroup_SDSPI = 22, /*!< Group number for SDSPI status codes. */ + kStatusGroup_FLEXIO_I2S = 23, /*!< Group number for FLEXIO I2S status codes */ + kStatusGroup_FLEXIO_MCULCD = 24, /*!< Group number for FLEXIO LCD status codes */ + kStatusGroup_FLASHIAP = 25, /*!< Group number for FLASHIAP status codes */ + kStatusGroup_FLEXCOMM_I2C = 26, /*!< Group number for FLEXCOMM I2C status codes */ + kStatusGroup_I2S = 27, /*!< Group number for I2S status codes */ + kStatusGroup_IUART = 28, /*!< Group number for IUART status codes */ + kStatusGroup_CSI = 29, /*!< Group number for CSI status codes */ + kStatusGroup_MIPI_DSI = 30, /*!< Group number for MIPI DSI status codes */ + kStatusGroup_SDRAMC = 35, /*!< Group number for SDRAMC status codes. */ + kStatusGroup_POWER = 39, /*!< Group number for POWER status codes. */ + kStatusGroup_ENET = 40, /*!< Group number for ENET status codes. */ + kStatusGroup_PHY = 41, /*!< Group number for PHY status codes. */ + kStatusGroup_TRGMUX = 42, /*!< Group number for TRGMUX status codes. */ + kStatusGroup_SMARTCARD = 43, /*!< Group number for SMARTCARD status codes. */ + kStatusGroup_LMEM = 44, /*!< Group number for LMEM status codes. */ + kStatusGroup_QSPI = 45, /*!< Group number for QSPI status codes. */ + kStatusGroup_DMA = 50, /*!< Group number for DMA status codes. */ + kStatusGroup_EDMA = 51, /*!< Group number for EDMA status codes. */ + kStatusGroup_DMAMGR = 52, /*!< Group number for DMAMGR status codes. */ + kStatusGroup_FLEXCAN = 53, /*!< Group number for FlexCAN status codes. */ + kStatusGroup_LTC = 54, /*!< Group number for LTC status codes. */ + kStatusGroup_FLEXIO_CAMERA = 55, /*!< Group number for FLEXIO CAMERA status codes. */ + kStatusGroup_LPC_SPI = 56, /*!< Group number for LPC_SPI status codes. */ + kStatusGroup_LPC_USART = 57, /*!< Group number for LPC_USART status codes. */ + kStatusGroup_DMIC = 58, /*!< Group number for DMIC status codes. */ + kStatusGroup_SDIF = 59, /*!< Group number for SDIF status codes.*/ + kStatusGroup_SPIFI = 60, /*!< Group number for SPIFI status codes. */ + kStatusGroup_OTP = 61, /*!< Group number for OTP status codes. */ + kStatusGroup_MCAN = 62, /*!< Group number for MCAN status codes. */ + kStatusGroup_CAAM = 63, /*!< Group number for CAAM status codes. */ + kStatusGroup_ECSPI = 64, /*!< Group number for ECSPI status codes. */ + kStatusGroup_USDHC = 65, /*!< Group number for USDHC status codes.*/ + kStatusGroup_LPC_I2C = 66, /*!< Group number for LPC_I2C status codes.*/ + kStatusGroup_DCP = 67, /*!< Group number for DCP status codes.*/ + kStatusGroup_MSCAN = 68, /*!< Group number for MSCAN status codes.*/ + kStatusGroup_ESAI = 69, /*!< Group number for ESAI status codes. */ + kStatusGroup_FLEXSPI = 70, /*!< Group number for FLEXSPI status codes. */ + kStatusGroup_MMDC = 71, /*!< Group number for MMDC status codes. */ + kStatusGroup_PDM = 72, /*!< Group number for MIC status codes. */ + kStatusGroup_SDMA = 73, /*!< Group number for SDMA status codes. */ + kStatusGroup_ICS = 74, /*!< Group number for ICS status codes. */ + kStatusGroup_SPDIF = 75, /*!< Group number for SPDIF status codes. */ + kStatusGroup_LPC_MINISPI = 76, /*!< Group number for LPC_MINISPI status codes. */ + kStatusGroup_HASHCRYPT = 77, /*!< Group number for Hashcrypt status codes */ + kStatusGroup_LPC_SPI_SSP = 78, /*!< Group number for LPC_SPI_SSP status codes. */ + kStatusGroup_I3C = 79, /*!< Group number for I3C status codes */ + kStatusGroup_LPC_I2C_1 = 97, /*!< Group number for LPC_I2C_1 status codes. */ + kStatusGroup_NOTIFIER = 98, /*!< Group number for NOTIFIER status codes. */ + kStatusGroup_DebugConsole = 99, /*!< Group number for debug console status codes. */ + kStatusGroup_SEMC = 100, /*!< Group number for SEMC status codes. */ + kStatusGroup_ApplicationRangeStart = 101, /*!< Starting number for application groups. */ + kStatusGroup_IAP = 102, /*!< Group number for IAP status codes */ + kStatusGroup_SFA = 103, /*!< Group number for SFA status codes*/ + kStatusGroup_SPC = 104, /*!< Group number for SPC status codes. */ + kStatusGroup_PUF = 105, /*!< Group number for PUF status codes. */ + kStatusGroup_TOUCH_PANEL = 106, /*!< Group number for touch panel status codes */ + + kStatusGroup_HAL_GPIO = 121, /*!< Group number for HAL GPIO status codes. */ + kStatusGroup_HAL_UART = 122, /*!< Group number for HAL UART status codes. */ + kStatusGroup_HAL_TIMER = 123, /*!< Group number for HAL TIMER status codes. */ + kStatusGroup_HAL_SPI = 124, /*!< Group number for HAL SPI status codes. */ + kStatusGroup_HAL_I2C = 125, /*!< Group number for HAL I2C status codes. */ + kStatusGroup_HAL_FLASH = 126, /*!< Group number for HAL FLASH status codes. */ + kStatusGroup_HAL_PWM = 127, /*!< Group number for HAL PWM status codes. */ + kStatusGroup_HAL_RNG = 128, /*!< Group number for HAL RNG status codes. */ + kStatusGroup_HAL_I2S = 129, /*!< Group number for HAL I2S status codes. */ + kStatusGroup_TIMERMANAGER = 135, /*!< Group number for TiMER MANAGER status codes. */ + kStatusGroup_SERIALMANAGER = 136, /*!< Group number for SERIAL MANAGER status codes. */ + kStatusGroup_LED = 137, /*!< Group number for LED status codes. */ + kStatusGroup_BUTTON = 138, /*!< Group number for BUTTON status codes. */ + kStatusGroup_EXTERN_EEPROM = 139, /*!< Group number for EXTERN EEPROM status codes. */ + kStatusGroup_SHELL = 140, /*!< Group number for SHELL status codes. */ + kStatusGroup_MEM_MANAGER = 141, /*!< Group number for MEM MANAGER status codes. */ + kStatusGroup_LIST = 142, /*!< Group number for List status codes. */ + kStatusGroup_OSA = 143, /*!< Group number for OSA status codes. */ + kStatusGroup_COMMON_TASK = 144, /*!< Group number for Common task status codes. */ + kStatusGroup_MSG = 145, /*!< Group number for messaging status codes. */ + kStatusGroup_SDK_OCOTP = 146, /*!< Group number for OCOTP status codes. */ + kStatusGroup_SDK_FLEXSPINOR = 147, /*!< Group number for FLEXSPINOR status codes.*/ + kStatusGroup_CODEC = 148, /*!< Group number for codec status codes. */ + kStatusGroup_ASRC = 149, /*!< Group number for codec status ASRC. */ + kStatusGroup_OTFAD = 150, /*!< Group number for codec status codes. */ + kStatusGroup_SDIOSLV = 151, /*!< Group number for SDIOSLV status codes. */ + kStatusGroup_MECC = 152, /*!< Group number for MECC status codes. */ + kStatusGroup_ENET_QOS = 153, /*!< Group number for ENET_QOS status codes. */ + kStatusGroup_LOG = 154, /*!< Group number for LOG status codes. */ + kStatusGroup_I3CBUS = 155, /*!< Group number for I3CBUS status codes. */ + kStatusGroup_QSCI = 156, /*!< Group number for QSCI status codes. */ + kStatusGroup_SNT = 157, /*!< Group number for SNT status codes. */ + kStatusGroup_QUEUEDSPI = 158, /*!< Group number for QSPI status codes. */ + kStatusGroup_POWER_MANAGER = 159, /*!< Group number for POWER_MANAGER status codes. */ + kStatusGroup_IPED = 160, /*!< Group number for IPED status codes. */ + kStatusGroup_CSS_PKC = 161, /*!< Group number for CSS PKC status codes. */ + kStatusGroup_HOSTIF = 162, /*!< Group number for HOSTIF status codes. */ + kStatusGroup_CLIF = 163, /*!< Group number for CLIF status codes. */ + kStatusGroup_BMA = 164, /*!< Group number for BMA status codes. */ +}; + +/*! \public + * @brief Generic status return codes. + */ +enum +{ + kStatus_Success = MAKE_STATUS(kStatusGroup_Generic, 0), /*!< Generic status for Success. */ + kStatus_Fail = MAKE_STATUS(kStatusGroup_Generic, 1), /*!< Generic status for Fail. */ + kStatus_ReadOnly = MAKE_STATUS(kStatusGroup_Generic, 2), /*!< Generic status for read only failure. */ + kStatus_OutOfRange = MAKE_STATUS(kStatusGroup_Generic, 3), /*!< Generic status for out of range access. */ + kStatus_InvalidArgument = MAKE_STATUS(kStatusGroup_Generic, 4), /*!< Generic status for invalid argument check. */ + kStatus_Timeout = MAKE_STATUS(kStatusGroup_Generic, 5), /*!< Generic status for timeout. */ + kStatus_NoTransferInProgress = + MAKE_STATUS(kStatusGroup_Generic, 6), /*!< Generic status for no transfer in progress. */ + kStatus_Busy = MAKE_STATUS(kStatusGroup_Generic, 7), /*!< Generic status for module is busy. */ + kStatus_NoData = + MAKE_STATUS(kStatusGroup_Generic, 8), /*!< Generic status for no data is found for the operation. */ +}; + +/*! @brief Type used for all status and error return values. */ +typedef int32_t status_t; + +/*! + * @name Min/max macros + * @{ + */ +#if !defined(MIN) +#define MIN(a, b) (((a) < (b)) ? (a) : (b)) +#endif + +#if !defined(MAX) +#define MAX(a, b) (((a) > (b)) ? (a) : (b)) +#endif +/* @} */ + +/*! @brief Computes the number of elements in an array. */ +#if !defined(ARRAY_SIZE) +#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) +#endif + +/*! @name UINT16_MAX/UINT32_MAX value */ +/* @{ */ +#if !defined(UINT16_MAX) +#define UINT16_MAX ((uint16_t)-1) +#endif + +#if !defined(UINT32_MAX) +#define UINT32_MAX ((uint32_t)-1) +#endif +/* @} */ + +/*! @name Suppress fallthrough warning macro */ +/* For switch case code block, if case section ends without "break;" statement, there wil be + fallthrough warning with compiler flag -Wextra or -Wimplicit-fallthrough=n when using armgcc. + To suppress this warning, "SUPPRESS_FALL_THROUGH_WARNING();" need to be added at the end of each + case section which misses "break;"statement. + */ +/* @{ */ +#if defined(__GNUC__) && !defined(__ARMCC_VERSION) +#define SUPPRESS_FALL_THROUGH_WARNING() __attribute__((fallthrough)) +#else +#define SUPPRESS_FALL_THROUGH_WARNING() +#endif +/* @} */ + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +#if !((defined(__DSC__) && defined(__CW__))) +/*! + * @brief Allocate memory with given alignment and aligned size. + * + * This is provided to support the dynamically allocated memory + * used in cache-able region. + * @param size The length required to malloc. + * @param alignbytes The alignment size. + * @retval The allocated memory. + */ +void *SDK_Malloc(size_t size, size_t alignbytes); + +/*! + * @brief Free memory. + * + * @param ptr The memory to be release. + */ +void SDK_Free(void *ptr); +#endif + +/*! + * @brief Delay at least for some time. + * Please note that, this API uses while loop for delay, different run-time environments make the time not precise, + * if precise delay count was needed, please implement a new delay function with hardware timer. + * + * @param delayTime_us Delay time in unit of microsecond. + * @param coreClock_Hz Core clock frequency with Hz. + */ +void SDK_DelayAtLeastUs(uint32_t delayTime_us, uint32_t coreClock_Hz); + +#if defined(__cplusplus) +} +#endif + +/*! @} */ + +#if (defined(__DSC__) && defined(__CW__)) +#include "fsl_common_dsc.h" +#elif defined(__XCC__) +#include "fsl_common_dsp.h" +#else +#include "fsl_common_arm.h" +#endif + +#endif /* _FSL_COMMON_H_ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_common_arm.c b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_common_arm.c new file mode 100644 index 0000000000..e77a265ce4 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_common_arm.c @@ -0,0 +1,233 @@ +/* + * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_common.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.common_arm" +#endif + +#ifndef __GIC_PRIO_BITS +#if defined(ENABLE_RAM_VECTOR_TABLE) +uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler) +{ +#ifdef __VECTOR_TABLE +#undef __VECTOR_TABLE +#endif + +/* Addresses for VECTOR_TABLE and VECTOR_RAM come from the linker file */ +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) + extern uint32_t Image$$VECTOR_ROM$$Base[]; + extern uint32_t Image$$VECTOR_RAM$$Base[]; + extern uint32_t Image$$RW_m_data$$Base[]; + +#define __VECTOR_TABLE Image$$VECTOR_ROM$$Base +#define __VECTOR_RAM Image$$VECTOR_RAM$$Base +#define __RAM_VECTOR_TABLE_SIZE (((uint32_t)Image$$RW_m_data$$Base - (uint32_t)Image$$VECTOR_RAM$$Base)) +#elif defined(__ICCARM__) + extern uint32_t __RAM_VECTOR_TABLE_SIZE[]; + extern uint32_t __VECTOR_TABLE[]; + extern uint32_t __VECTOR_RAM[]; +#elif defined(__GNUC__) + extern uint32_t __VECTOR_TABLE[]; + extern uint32_t __VECTOR_RAM[]; + extern uint32_t __RAM_VECTOR_TABLE_SIZE_BYTES[]; + uint32_t __RAM_VECTOR_TABLE_SIZE = (uint32_t)(__RAM_VECTOR_TABLE_SIZE_BYTES); +#endif /* defined(__CC_ARM) || defined(__ARMCC_VERSION) */ + uint32_t n; + uint32_t ret; + uint32_t irqMaskValue; + + irqMaskValue = DisableGlobalIRQ(); + if (SCB->VTOR != (uint32_t)__VECTOR_RAM) + { + /* Copy the vector table from ROM to RAM */ + for (n = 0; n < ((uint32_t)__RAM_VECTOR_TABLE_SIZE) / sizeof(uint32_t); n++) + { + __VECTOR_RAM[n] = __VECTOR_TABLE[n]; + } + /* Point the VTOR to the position of vector table */ + SCB->VTOR = (uint32_t)__VECTOR_RAM; + } + + ret = __VECTOR_RAM[(int32_t)irq + 16]; + /* make sure the __VECTOR_RAM is noncachable */ + __VECTOR_RAM[(int32_t)irq + 16] = irqHandler; + + EnableGlobalIRQ(irqMaskValue); + + return ret; +} +#endif /* ENABLE_RAM_VECTOR_TABLE. */ +#endif /* __GIC_PRIO_BITS. */ + +#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) + +/* + * When FSL_FEATURE_POWERLIB_EXTEND is defined to non-zero value, + * powerlib should be used instead of these functions. + */ +#if !(defined(FSL_FEATURE_POWERLIB_EXTEND) && (FSL_FEATURE_POWERLIB_EXTEND != 0)) + +/* + * When the SYSCON STARTER registers are discontinuous, these functions are + * implemented in fsl_power.c. + */ +#if !(defined(FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS) && FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS) + +void EnableDeepSleepIRQ(IRQn_Type interrupt) +{ + uint32_t intNumber = (uint32_t)interrupt; + + uint32_t index = 0; + + while (intNumber >= 32u) + { + index++; + intNumber -= 32u; + } + + SYSCON->STARTERSET[index] = 1UL << intNumber; + (void)EnableIRQ(interrupt); /* also enable interrupt at NVIC */ +} + +void DisableDeepSleepIRQ(IRQn_Type interrupt) +{ + uint32_t intNumber = (uint32_t)interrupt; + + (void)DisableIRQ(interrupt); /* also disable interrupt at NVIC */ + uint32_t index = 0; + + while (intNumber >= 32u) + { + index++; + intNumber -= 32u; + } + + SYSCON->STARTERCLR[index] = 1UL << intNumber; +} +#endif /* FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS */ +#endif /* FSL_FEATURE_POWERLIB_EXTEND */ +#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */ + +#if defined(SDK_DELAY_USE_DWT) && defined(DWT) +/* Use WDT. */ +static void enableCpuCycleCounter(void) +{ + /* Make sure the DWT trace fucntion is enabled. */ + if (CoreDebug_DEMCR_TRCENA_Msk != (CoreDebug_DEMCR_TRCENA_Msk & CoreDebug->DEMCR)) + { + CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk; + } + + /* CYCCNT not supported on this device. */ + assert(DWT_CTRL_NOCYCCNT_Msk != (DWT->CTRL & DWT_CTRL_NOCYCCNT_Msk)); + + /* Read CYCCNT directly if CYCCENT has already been enabled, otherwise enable CYCCENT first. */ + if (DWT_CTRL_CYCCNTENA_Msk != (DWT_CTRL_CYCCNTENA_Msk & DWT->CTRL)) + { + DWT->CTRL |= DWT_CTRL_CYCCNTENA_Msk; + } +} + +static uint32_t getCpuCycleCount(void) +{ + return DWT->CYCCNT; +} +#else /* defined(SDK_DELAY_USE_DWT) && defined(DWT) */ +/* Use software loop. */ +#if defined(__CC_ARM) /* This macro is arm v5 specific */ +/* clang-format off */ +__ASM static void DelayLoop(uint32_t count) +{ +loop + SUBS R0, R0, #1 + CMP R0, #0 + BNE loop + BX LR +} +/* clang-format on */ +#elif defined(__ARMCC_VERSION) || defined(__ICCARM__) || defined(__GNUC__) +/* Cortex-M0 has a smaller instruction set, SUBS isn't supported in thumb-16 mode reported from __GNUC__ compiler, + * use SUB and CMP here for compatibility */ +static void DelayLoop(uint32_t count) +{ + __ASM volatile(" MOV R0, %0" : : "r"(count)); + __ASM volatile( + "loop: \n" +#if defined(__GNUC__) && !defined(__ARMCC_VERSION) + " SUB R0, R0, #1 \n" +#else + " SUBS R0, R0, #1 \n" +#endif + " CMP R0, #0 \n" + + " BNE loop \n" + : + : + : "r0"); +} +#endif /* defined(__CC_ARM) */ +#endif /* defined(SDK_DELAY_USE_DWT) && defined(DWT) */ + +/*! + * @brief Delay at least for some time. + * Please note that, if not uses DWT, this API will use while loop for delay, different run-time environments have + * effect on the delay time. If precise delay is needed, please enable DWT delay. The two parmeters delayTime_us and + * coreClock_Hz have limitation. For example, in the platform with 1GHz coreClock_Hz, the delayTime_us only supports + * up to 4294967 in current code. If long time delay is needed, please implement a new delay function. + * + * @param delayTime_us Delay time in unit of microsecond. + * @param coreClock_Hz Core clock frequency with Hz. + */ +void SDK_DelayAtLeastUs(uint32_t delayTime_us, uint32_t coreClock_Hz) +{ + uint64_t count; + + if (delayTime_us > 0U) + { + count = USEC_TO_COUNT(delayTime_us, coreClock_Hz); + + assert(count <= UINT32_MAX); + +#if defined(SDK_DELAY_USE_DWT) && defined(DWT) /* Use DWT for better accuracy */ + + enableCpuCycleCounter(); + /* Calculate the count ticks. */ + count += getCpuCycleCount(); + + if (count > UINT32_MAX) + { + count -= UINT32_MAX; + /* Wait for cyccnt overflow. */ + while (count < getCpuCycleCount()) + { + } + } + + /* Wait for cyccnt reach count value. */ + while (count > getCpuCycleCount()) + { + } +#else + /* Divide value may be different in various environment to ensure delay is precise. + * Every loop count includes three instructions, due to Cortex-M7 sometimes executes + * two instructions in one period, through test here set divide 1.5. Other M cores use + * divide 4. By the way, divide 1.5 or 4 could let the count lose precision, but it does + * not matter because other instructions outside while loop is enough to fill the time. + */ +#if (__CORTEX_M == 7) + count = count / 3U * 2U; +#else + count = count / 4U; +#endif + DelayLoop((uint32_t)count); +#endif /* defined(SDK_DELAY_USE_DWT) && defined(DWT) */ + } +} diff --git a/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_common_arm.h b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_common_arm.h new file mode 100644 index 0000000000..2678ff625c --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_common_arm.h @@ -0,0 +1,671 @@ +/* + * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_COMMON_ARM_H_ +#define _FSL_COMMON_ARM_H_ + +/* + * For CMSIS pack RTE. + * CMSIS pack RTE generates "RTC_Components.h" which contains the statements + * of the related element for all selected software components. + */ +#ifdef _RTE_ +#include "RTE_Components.h" +#endif + +/*! + * @addtogroup ksdk_common + * @{ + */ + +/*! @name Atomic modification + * + * These macros are used for atomic access, such as read-modify-write + * to the peripheral registers. + * + * - SDK_ATOMIC_LOCAL_ADD + * - SDK_ATOMIC_LOCAL_SET + * - SDK_ATOMIC_LOCAL_CLEAR + * - SDK_ATOMIC_LOCAL_TOGGLE + * - SDK_ATOMIC_LOCAL_CLEAR_AND_SET + * + * Take SDK_ATOMIC_LOCAL_CLEAR_AND_SET as an example: the parameter @c addr + * means the address of the peripheral register or variable you want to modify + * atomically, the parameter @c clearBits is the bits to clear, the parameter + * @c setBits it the bits to set. + * For example, to set a 32-bit register bit1:bit0 to 0b10, use like this: + * + * @code + volatile uint32_t * reg = (volatile uint32_t *)REG_ADDR; + + SDK_ATOMIC_LOCAL_CLEAR_AND_SET(reg, 0x03, 0x02); + @endcode + * + * In this example, the register bit1:bit0 are cleared and bit1 is set, as a result, + * register bit1:bit0 = 0b10. + * + * @note For the platforms don't support exclusive load and store, these macros + * disable the global interrupt to pretect the modification. + * + * @note These macros only guarantee the local processor atomic operations. For + * the multi-processor devices, use hardware semaphore such as SEMA42 to + * guarantee exclusive access if necessary. + * + * @{ + */ + +/* clang-format off */ +#if ((defined(__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined(__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined(__ARM_ARCH_8M_BASE__) && (__ARM_ARCH_8M_BASE__ == 1))) +/* clang-format on */ + +/* If the LDREX and STREX are supported, use them. */ +#define _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, val, ops) \ + do \ + { \ + (val) = __LDREXB(addr); \ + (ops); \ + } while (0UL != __STREXB((val), (addr))) + +#define _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, val, ops) \ + do \ + { \ + (val) = __LDREXH(addr); \ + (ops); \ + } while (0UL != __STREXH((val), (addr))) + +#define _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, val, ops) \ + do \ + { \ + (val) = __LDREXW(addr); \ + (ops); \ + } while (0UL != __STREXW((val), (addr))) + +static inline void _SDK_AtomicLocalAdd1Byte(volatile uint8_t *addr, uint8_t val) +{ + uint8_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, s_val, s_val += val); +} + +static inline void _SDK_AtomicLocalAdd2Byte(volatile uint16_t *addr, uint16_t val) +{ + uint16_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, s_val, s_val += val); +} + +static inline void _SDK_AtomicLocalAdd4Byte(volatile uint32_t *addr, uint32_t val) +{ + uint32_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, s_val, s_val += val); +} + +static inline void _SDK_AtomicLocalSub1Byte(volatile uint8_t *addr, uint8_t val) +{ + uint8_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, s_val, s_val -= val); +} + +static inline void _SDK_AtomicLocalSub2Byte(volatile uint16_t *addr, uint16_t val) +{ + uint16_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, s_val, s_val -= val); +} + +static inline void _SDK_AtomicLocalSub4Byte(volatile uint32_t *addr, uint32_t val) +{ + uint32_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, s_val, s_val -= val); +} + +static inline void _SDK_AtomicLocalSet1Byte(volatile uint8_t *addr, uint8_t bits) +{ + uint8_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, s_val, s_val |= bits); +} + +static inline void _SDK_AtomicLocalSet2Byte(volatile uint16_t *addr, uint16_t bits) +{ + uint16_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, s_val, s_val |= bits); +} + +static inline void _SDK_AtomicLocalSet4Byte(volatile uint32_t *addr, uint32_t bits) +{ + uint32_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, s_val, s_val |= bits); +} + +static inline void _SDK_AtomicLocalClear1Byte(volatile uint8_t *addr, uint8_t bits) +{ + uint8_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, s_val, s_val &= ~bits); +} + +static inline void _SDK_AtomicLocalClear2Byte(volatile uint16_t *addr, uint16_t bits) +{ + uint16_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, s_val, s_val &= ~bits); +} + +static inline void _SDK_AtomicLocalClear4Byte(volatile uint32_t *addr, uint32_t bits) +{ + uint32_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, s_val, s_val &= ~bits); +} + +static inline void _SDK_AtomicLocalToggle1Byte(volatile uint8_t *addr, uint8_t bits) +{ + uint8_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, s_val, s_val ^= bits); +} + +static inline void _SDK_AtomicLocalToggle2Byte(volatile uint16_t *addr, uint16_t bits) +{ + uint16_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, s_val, s_val ^= bits); +} + +static inline void _SDK_AtomicLocalToggle4Byte(volatile uint32_t *addr, uint32_t bits) +{ + uint32_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, s_val, s_val ^= bits); +} + +static inline void _SDK_AtomicLocalClearAndSet1Byte(volatile uint8_t *addr, uint8_t clearBits, uint8_t setBits) +{ + uint8_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, s_val, s_val = (s_val & ~clearBits) | setBits); +} + +static inline void _SDK_AtomicLocalClearAndSet2Byte(volatile uint16_t *addr, uint16_t clearBits, uint16_t setBits) +{ + uint16_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, s_val, s_val = (s_val & ~clearBits) | setBits); +} + +static inline void _SDK_AtomicLocalClearAndSet4Byte(volatile uint32_t *addr, uint32_t clearBits, uint32_t setBits) +{ + uint32_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, s_val, s_val = (s_val & ~clearBits) | setBits); +} + +#define SDK_ATOMIC_LOCAL_ADD(addr, val) \ + ((1UL == sizeof(*(addr))) ? \ + _SDK_AtomicLocalAdd1Byte((volatile uint8_t *)(volatile void *)(addr), (uint8_t)(val)) : \ + ((2UL == sizeof(*(addr))) ? _SDK_AtomicLocalAdd2Byte((volatile uint16_t *)(volatile void *)(addr), (uint16_t)(val)) : \ + _SDK_AtomicLocalAdd4Byte((volatile uint32_t *)(volatile void *)(addr), (uint32_t)(val)))) + +#define SDK_ATOMIC_LOCAL_SET(addr, bits) \ + ((1UL == sizeof(*(addr))) ? \ + _SDK_AtomicLocalSet1Byte((volatile uint8_t *)(volatile void *)(addr), (uint8_t)(bits)) : \ + ((2UL == sizeof(*(addr))) ? _SDK_AtomicLocalSet2Byte((volatile uint16_t *)(volatile void *)(addr), (uint16_t)(bits)) : \ + _SDK_AtomicLocalSet4Byte((volatile uint32_t *)(volatile void *)(addr), (uint32_t)(bits)))) + +#define SDK_ATOMIC_LOCAL_CLEAR(addr, bits) \ + ((1UL == sizeof(*(addr))) ? \ + _SDK_AtomicLocalClear1Byte((volatile uint8_t *)(volatile void *)(addr), (uint8_t)(bits)) : \ + ((2UL == sizeof(*(addr))) ? \ + _SDK_AtomicLocalClear2Byte((volatile uint16_t *)(volatile void *)(addr), (uint16_t)(bits)) : \ + _SDK_AtomicLocalClear4Byte((volatile uint32_t *)(volatile void *)(addr), (uint32_t)(bits)))) + +#define SDK_ATOMIC_LOCAL_TOGGLE(addr, bits) \ + ((1UL == sizeof(*(addr))) ? \ + _SDK_AtomicLocalToggle1Byte((volatile uint8_t *)(volatile void *)(addr), (uint8_t)(bits)) : \ + ((2UL == sizeof(*(addr))) ? \ + _SDK_AtomicLocalToggle2Byte((volatile uint16_t *)(volatile void *)(addr), (uint16_t)(bits)) : \ + _SDK_AtomicLocalToggle4Byte((volatile uint32_t *)(volatile void *)(addr), (uint32_t)(bits)))) + +#define SDK_ATOMIC_LOCAL_CLEAR_AND_SET(addr, clearBits, setBits) \ + ((1UL == sizeof(*(addr))) ? \ + _SDK_AtomicLocalClearAndSet1Byte((volatile uint8_t *)(volatile void *)(addr), (uint8_t)(clearBits), (uint8_t)(setBits)) : \ + ((2UL == sizeof(*(addr))) ? \ + _SDK_AtomicLocalClearAndSet2Byte((volatile uint16_t *)(volatile void *)(addr), (uint16_t)(clearBits), (uint16_t)(setBits)) : \ + _SDK_AtomicLocalClearAndSet4Byte((volatile uint32_t *)(volatile void *)(addr), (uint32_t)(clearBits), (uint32_t)(setBits)))) +#else + +#define SDK_ATOMIC_LOCAL_ADD(addr, val) \ + do \ + { \ + uint32_t s_atomicOldInt; \ + s_atomicOldInt = DisableGlobalIRQ(); \ + *(addr) += (val); \ + EnableGlobalIRQ(s_atomicOldInt); \ + } while (0) + +#define SDK_ATOMIC_LOCAL_SET(addr, bits) \ + do \ + { \ + uint32_t s_atomicOldInt; \ + s_atomicOldInt = DisableGlobalIRQ(); \ + *(addr) |= (bits); \ + EnableGlobalIRQ(s_atomicOldInt); \ + } while (0) + +#define SDK_ATOMIC_LOCAL_CLEAR(addr, bits) \ + do \ + { \ + uint32_t s_atomicOldInt; \ + s_atomicOldInt = DisableGlobalIRQ(); \ + *(addr) &= ~(bits); \ + EnableGlobalIRQ(s_atomicOldInt); \ + } while (0) + +#define SDK_ATOMIC_LOCAL_TOGGLE(addr, bits) \ + do \ + { \ + uint32_t s_atomicOldInt; \ + s_atomicOldInt = DisableGlobalIRQ(); \ + *(addr) ^= (bits); \ + EnableGlobalIRQ(s_atomicOldInt); \ + } while (0) + +#define SDK_ATOMIC_LOCAL_CLEAR_AND_SET(addr, clearBits, setBits) \ + do \ + { \ + uint32_t s_atomicOldInt; \ + s_atomicOldInt = DisableGlobalIRQ(); \ + *(addr) = (*(addr) & ~(clearBits)) | (setBits); \ + EnableGlobalIRQ(s_atomicOldInt); \ + } while (0) + +#endif +/* @} */ + +/*! @name Timer utilities */ +/* @{ */ +/*! Macro to convert a microsecond period to raw count value */ +#define USEC_TO_COUNT(us, clockFreqInHz) (uint64_t)(((uint64_t)(us) * (clockFreqInHz)) / 1000000U) +/*! Macro to convert a raw count value to microsecond */ +#define COUNT_TO_USEC(count, clockFreqInHz) (uint64_t)((uint64_t)(count)*1000000U / (clockFreqInHz)) + +/*! Macro to convert a millisecond period to raw count value */ +#define MSEC_TO_COUNT(ms, clockFreqInHz) (uint64_t)((uint64_t)(ms) * (clockFreqInHz) / 1000U) +/*! Macro to convert a raw count value to millisecond */ +#define COUNT_TO_MSEC(count, clockFreqInHz) (uint64_t)((uint64_t)(count)*1000U / (clockFreqInHz)) +/* @} */ + +/*! @name ISR exit barrier + * @{ + * + * ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + * exception return operation might vector to incorrect interrupt. + * For Cortex-M7, if core speed much faster than peripheral register write speed, + * the peripheral interrupt flags may be still set after exiting ISR, this results to + * the same error similar with errata 83869. + */ +#if (defined __CORTEX_M) && ((__CORTEX_M == 4U) || (__CORTEX_M == 7U)) +#define SDK_ISR_EXIT_BARRIER __DSB() +#else +#define SDK_ISR_EXIT_BARRIER +#endif + +/* @} */ + +/*! @name Alignment variable definition macros */ +/* @{ */ +#if (defined(__ICCARM__)) +/* + * Workaround to disable MISRA C message suppress warnings for IAR compiler. + * http:/ /supp.iar.com/Support/?note=24725 + */ +_Pragma("diag_suppress=Pm120") +#define SDK_PRAGMA(x) _Pragma(#x) + _Pragma("diag_error=Pm120") +/*! Macro to define a variable with alignbytes alignment */ +#define SDK_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var +#elif defined(__CC_ARM) || defined(__ARMCC_VERSION) +/*! Macro to define a variable with alignbytes alignment */ +#define SDK_ALIGN(var, alignbytes) __attribute__((aligned(alignbytes))) var +#elif defined(__GNUC__) +/*! Macro to define a variable with alignbytes alignment */ +#define SDK_ALIGN(var, alignbytes) var __attribute__((aligned(alignbytes))) +#else +#error Toolchain not supported +#endif + +/*! Macro to define a variable with L1 d-cache line size alignment */ +#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) +#define SDK_L1DCACHE_ALIGN(var) SDK_ALIGN(var, FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) +#endif +/*! Macro to define a variable with L2 cache line size alignment */ +#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) +#define SDK_L2CACHE_ALIGN(var) SDK_ALIGN(var, FSL_FEATURE_L2CACHE_LINESIZE_BYTE) +#endif + +/*! Macro to change a value to a given size aligned value */ +#define SDK_SIZEALIGN(var, alignbytes) \ + ((unsigned int)((var) + ((alignbytes)-1U)) & (unsigned int)(~(unsigned int)((alignbytes)-1U))) +/* @} */ + +/*! @name Non-cacheable region definition macros */ +/* For initialized non-zero non-cacheable variables, please using "AT_NONCACHEABLE_SECTION_INIT(var) ={xx};" or + * "AT_NONCACHEABLE_SECTION_ALIGN_INIT(var) ={xx};" in your projects to define them, for zero-inited non-cacheable + * variables, please using "AT_NONCACHEABLE_SECTION(var);" or "AT_NONCACHEABLE_SECTION_ALIGN(var);" to define them, + * these zero-inited variables will be initialized to zero in system startup. + */ +/* @{ */ + +#if ((!(defined(FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION) && FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION)) && \ + defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE)) + +#if (defined(__ICCARM__)) +#define AT_NONCACHEABLE_SECTION(var) var @"NonCacheable" +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var @"NonCacheable" +#define AT_NONCACHEABLE_SECTION_INIT(var) var @"NonCacheable.init" +#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \ + SDK_PRAGMA(data_alignment = alignbytes) var @"NonCacheable.init" + +#elif (defined(__CC_ARM) || defined(__ARMCC_VERSION)) +#define AT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) var +#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \ + __attribute__((section("NonCacheable.init"))) __attribute__((aligned(alignbytes))) var +#if (defined(__CC_ARM)) +#define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable"), zero_init)) var +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \ + __attribute__((section("NonCacheable"), zero_init)) __attribute__((aligned(alignbytes))) var +#else +#define AT_NONCACHEABLE_SECTION(var) __attribute__((section(".bss.NonCacheable"))) var +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \ + __attribute__((section(".bss.NonCacheable"))) __attribute__((aligned(alignbytes))) var +#endif + +#elif (defined(__GNUC__)) +/* For GCC, when the non-cacheable section is required, please define "__STARTUP_INITIALIZE_NONCACHEDATA" + * in your projects to make sure the non-cacheable section variables will be initialized in system startup. + */ +#define AT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) var +#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \ + __attribute__((section("NonCacheable.init"))) var __attribute__((aligned(alignbytes))) +#define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable,\"aw\",%nobits @"))) var +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \ + __attribute__((section("NonCacheable,\"aw\",%nobits @"))) var __attribute__((aligned(alignbytes))) +#else +#error Toolchain not supported. +#endif + +#else + +#define AT_NONCACHEABLE_SECTION(var) var +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) SDK_ALIGN(var, alignbytes) +#define AT_NONCACHEABLE_SECTION_INIT(var) var +#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) SDK_ALIGN(var, alignbytes) + +#endif + +/* @} */ + +/*! + * @name Time sensitive region + * @{ + */ +#if (defined(__ICCARM__)) +#define AT_QUICKACCESS_SECTION_CODE(func) func @"CodeQuickAccess" +#define AT_QUICKACCESS_SECTION_DATA(var) var @"DataQuickAccess" +#define AT_QUICKACCESS_SECTION_DATA_ALIGN(var, alignbytes) \ + SDK_PRAGMA(data_alignment = alignbytes) var @"DataQuickAccess" +#elif (defined(__CC_ARM) || defined(__ARMCC_VERSION)) +#define AT_QUICKACCESS_SECTION_CODE(func) __attribute__((section("CodeQuickAccess"), __noinline__)) func +#define AT_QUICKACCESS_SECTION_DATA(var) __attribute__((section("DataQuickAccess"))) var +#define AT_QUICKACCESS_SECTION_DATA_ALIGN(var, alignbytes) \ + __attribute__((section("DataQuickAccess"))) __attribute__((aligned(alignbytes))) var +#elif (defined(__GNUC__)) +#define AT_QUICKACCESS_SECTION_CODE(func) __attribute__((section("CodeQuickAccess"), __noinline__)) func +#define AT_QUICKACCESS_SECTION_DATA(var) __attribute__((section("DataQuickAccess"))) var +#define AT_QUICKACCESS_SECTION_DATA_ALIGN(var, alignbytes) \ + __attribute__((section("DataQuickAccess"))) var __attribute__((aligned(alignbytes))) +#else +#error Toolchain not supported. +#endif /* defined(__ICCARM__) */ + +/*! @name Ram Function */ +#if (defined(__ICCARM__)) +#define RAMFUNCTION_SECTION_CODE(func) func @"RamFunction" +#elif (defined(__CC_ARM) || defined(__ARMCC_VERSION)) +#define RAMFUNCTION_SECTION_CODE(func) __attribute__((section("RamFunction"))) func +#elif (defined(__GNUC__)) +#define RAMFUNCTION_SECTION_CODE(func) __attribute__((section("RamFunction"))) func +#else +#error Toolchain not supported. +#endif /* defined(__ICCARM__) */ +/* @} */ + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + void DefaultISR(void); +#endif + +/* + * The fsl_clock.h is included here because it needs MAKE_VERSION/MAKE_STATUS/status_t + * defined in previous of this file. + */ +#include "fsl_clock.h" + +/* + * Chip level peripheral reset API, for MCUs that implement peripheral reset control external to a peripheral + */ +#if ((defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) || \ + (defined(FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT) && (FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT > 0))) +#include "fsl_reset.h" +#endif + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief Enable specific interrupt. + * + * Enable LEVEL1 interrupt. For some devices, there might be multiple interrupt + * levels. For example, there are NVIC and intmux. Here the interrupts connected + * to NVIC are the LEVEL1 interrupts, because they are routed to the core directly. + * The interrupts connected to intmux are the LEVEL2 interrupts, they are routed + * to NVIC first then routed to core. + * + * This function only enables the LEVEL1 interrupts. The number of LEVEL1 interrupts + * is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS. + * + * @param interrupt The IRQ number. + * @retval kStatus_Success Interrupt enabled successfully + * @retval kStatus_Fail Failed to enable the interrupt + */ +static inline status_t EnableIRQ(IRQn_Type interrupt) +{ + status_t status = kStatus_Success; + + if (NotAvail_IRQn == interrupt) + { + status = kStatus_Fail; + } + +#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0) + else if ((int32_t)interrupt >= (int32_t)FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) + { + status = kStatus_Fail; + } +#endif + + else + { +#if defined(__GIC_PRIO_BITS) + GIC_EnableIRQ(interrupt); +#else + NVIC_EnableIRQ(interrupt); +#endif + } + + return status; +} + +/*! + * @brief Disable specific interrupt. + * + * Disable LEVEL1 interrupt. For some devices, there might be multiple interrupt + * levels. For example, there are NVIC and intmux. Here the interrupts connected + * to NVIC are the LEVEL1 interrupts, because they are routed to the core directly. + * The interrupts connected to intmux are the LEVEL2 interrupts, they are routed + * to NVIC first then routed to core. + * + * This function only disables the LEVEL1 interrupts. The number of LEVEL1 interrupts + * is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS. + * + * @param interrupt The IRQ number. + * @retval kStatus_Success Interrupt disabled successfully + * @retval kStatus_Fail Failed to disable the interrupt + */ +static inline status_t DisableIRQ(IRQn_Type interrupt) +{ + status_t status = kStatus_Success; + + if (NotAvail_IRQn == interrupt) + { + status = kStatus_Fail; + } + +#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0) + else if ((int32_t)interrupt >= (int32_t)FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) + { + status = kStatus_Fail; + } +#endif + + else + { +#if defined(__GIC_PRIO_BITS) + GIC_DisableIRQ(interrupt); +#else + NVIC_DisableIRQ(interrupt); +#endif + } + + return status; +} + +/*! + * @brief Disable the global IRQ + * + * Disable the global interrupt and return the current primask register. User is required to provided the primask + * register for the EnableGlobalIRQ(). + * + * @return Current primask value. + */ +static inline uint32_t DisableGlobalIRQ(void) +{ +#if defined(CPSR_I_Msk) + uint32_t cpsr = __get_CPSR() & CPSR_I_Msk; + + __disable_irq(); + + return cpsr; +#else + uint32_t regPrimask = __get_PRIMASK(); + + __disable_irq(); + + return regPrimask; +#endif +} + +/*! + * @brief Enable the global IRQ + * + * Set the primask register with the provided primask value but not just enable the primask. The idea is for the + * convenience of integration of RTOS. some RTOS get its own management mechanism of primask. User is required to + * use the EnableGlobalIRQ() and DisableGlobalIRQ() in pair. + * + * @param primask value of primask register to be restored. The primask value is supposed to be provided by the + * DisableGlobalIRQ(). + */ +static inline void EnableGlobalIRQ(uint32_t primask) +{ +#if defined(CPSR_I_Msk) + __set_CPSR((__get_CPSR() & ~CPSR_I_Msk) | primask); +#else + __set_PRIMASK(primask); +#endif +} + +#if defined(ENABLE_RAM_VECTOR_TABLE) +/*! + * @brief install IRQ handler + * + * @param irq IRQ number + * @param irqHandler IRQ handler address + * @return The old IRQ handler address + */ +uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler); +#endif /* ENABLE_RAM_VECTOR_TABLE. */ + +#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) + +/* + * When FSL_FEATURE_POWERLIB_EXTEND is defined to non-zero value, + * powerlib should be used instead of these functions. + */ +#if !(defined(FSL_FEATURE_POWERLIB_EXTEND) && (FSL_FEATURE_POWERLIB_EXTEND != 0)) +/*! + * @brief Enable specific interrupt for wake-up from deep-sleep mode. + * + * Enable the interrupt for wake-up from deep sleep mode. + * Some interrupts are typically used in sleep mode only and will not occur during + * deep-sleep mode because relevant clocks are stopped. However, it is possible to enable + * those clocks (significantly increasing power consumption in the reduced power mode), + * making these wake-ups possible. + * + * @note This function also enables the interrupt in the NVIC (EnableIRQ() is called internaly). + * + * @param interrupt The IRQ number. + */ +void EnableDeepSleepIRQ(IRQn_Type interrupt); + +/*! + * @brief Disable specific interrupt for wake-up from deep-sleep mode. + * + * Disable the interrupt for wake-up from deep sleep mode. + * Some interrupts are typically used in sleep mode only and will not occur during + * deep-sleep mode because relevant clocks are stopped. However, it is possible to enable + * those clocks (significantly increasing power consumption in the reduced power mode), + * making these wake-ups possible. + * + * @note This function also disables the interrupt in the NVIC (DisableIRQ() is called internaly). + * + * @param interrupt The IRQ number. + */ +void DisableDeepSleepIRQ(IRQn_Type interrupt); +#endif /* FSL_FEATURE_POWERLIB_EXTEND */ +#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */ + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/*! @} */ + +#endif /* _FSL_COMMON_ARM_H_ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_crc.c b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_crc.c new file mode 100644 index 0000000000..c73f84997a --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_crc.c @@ -0,0 +1,185 @@ +/* + * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017, 2019-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#include "fsl_crc.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.lpc_crc" +#endif + +#if defined(CRC_DRIVER_USE_CRC16_CCITT_FALSE_AS_DEFAULT) && CRC_DRIVER_USE_CRC16_CCITT_FALSE_AS_DEFAULT +/* @brief Default user configuration structure for CRC-CCITT */ +#define CRC_DRIVER_DEFAULT_POLYNOMIAL kCRC_Polynomial_CRC_CCITT +/*< CRC-CCIT polynomial x^16 + x^12 + x^5 + x^0 */ +#define CRC_DRIVER_DEFAULT_REVERSE_IN false +/*< Default is no bit reverse */ +#define CRC_DRIVER_DEFAULT_COMPLEMENT_IN false +/*< Default is without complement of written data */ +#define CRC_DRIVER_DEFAULT_REVERSE_OUT false +/*< Default is no bit reverse */ +#define CRC_DRIVER_DEFAULT_COMPLEMENT_OUT false +/*< Default is without complement of CRC data register read data */ +#define CRC_DRIVER_DEFAULT_SEED 0xFFFFU +/*< Default initial checksum */ +#endif /* CRC_DRIVER_USE_CRC16_CCITT_FALSE_AS_DEFAULT */ + +/******************************************************************************* + * Code + ******************************************************************************/ + +/*! + * brief Enables and configures the CRC peripheral module. + * + * This functions enables the CRC peripheral clock in the LPC SYSCON block. + * It also configures the CRC engine and starts checksum computation by writing the seed. + * + * param base CRC peripheral address. + * param config CRC module configuration structure. + */ +void CRC_Init(CRC_Type *base, const crc_config_t *config) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* enable clock to CRC */ + CLOCK_EnableClock(kCLOCK_Crc); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if !(defined(FSL_FEATURE_CRC_HAS_NO_RESET) && FSL_FEATURE_CRC_HAS_NO_RESET) + RESET_PeripheralReset(kCRC_RST_SHIFT_RSTn); +#endif + + /* configure CRC module and write the seed */ + base->MODE = CRC_MODE_CRC_POLY(config->polynomial) | CRC_MODE_BIT_RVS_WR(config->reverseIn) | + CRC_MODE_CMPL_WR(config->complementIn) | CRC_MODE_BIT_RVS_SUM(config->reverseOut) | + CRC_MODE_CMPL_SUM(config->complementOut); + base->SEED = config->seed; +} + +/*! + * brief Loads default values to CRC protocol configuration structure. + * + * Loads default values to CRC protocol configuration structure. The default values are: + * code + * config->polynomial = kCRC_Polynomial_CRC_CCITT; + * config->reverseIn = false; + * config->complementIn = false; + * config->reverseOut = false; + * config->complementOut = false; + * config->seed = 0xFFFFU; + * endcode + * + * param config CRC protocol configuration structure + */ +void CRC_GetDefaultConfig(crc_config_t *config) +{ + /* Initializes the configure structure to zero. */ + (void)memset(config, 0, sizeof(*config)); + + static const crc_config_t default_config = {CRC_DRIVER_DEFAULT_POLYNOMIAL, CRC_DRIVER_DEFAULT_REVERSE_IN, + CRC_DRIVER_DEFAULT_COMPLEMENT_IN, CRC_DRIVER_DEFAULT_REVERSE_OUT, + CRC_DRIVER_DEFAULT_COMPLEMENT_OUT, CRC_DRIVER_DEFAULT_SEED}; + + *config = default_config; +} + +/*! + * brief resets CRC peripheral module. + * + * param base CRC peripheral address. + */ +void CRC_Reset(CRC_Type *base) +{ + crc_config_t config; + CRC_GetDefaultConfig(&config); + CRC_Init(base, &config); +} + +/*! + * brief Write seed (initial checksum) to CRC peripheral module. + * + * param base CRC peripheral address. + * param seed CRC Seed value. + */ +void CRC_WriteSeed(CRC_Type *base, uint32_t seed) +{ + /* write the seed (initial checksum) */ + base->SEED = seed; +} + +/*! + * brief Loads actual values configured in CRC peripheral to CRC protocol configuration structure. + * + * The values, including seed, can be used to resume CRC calculation later. + + * param base CRC peripheral address. + * param config CRC protocol configuration structure + */ +void CRC_GetConfig(CRC_Type *base, crc_config_t *config) +{ + /* extract CRC mode settings */ + uint32_t mode = base->MODE; + config->polynomial = + (crc_polynomial_t)(uint32_t)(((uint32_t)(mode & CRC_MODE_CRC_POLY_MASK)) >> CRC_MODE_CRC_POLY_SHIFT); + config->reverseIn = (bool)(mode & CRC_MODE_BIT_RVS_WR_MASK); + config->complementIn = (bool)(mode & CRC_MODE_CMPL_WR_MASK); + config->reverseOut = (bool)(mode & CRC_MODE_BIT_RVS_SUM_MASK); + config->complementOut = (bool)(mode & CRC_MODE_CMPL_SUM_MASK); + + /* reset CRC sum bit reverse and 1's complement setting, so its value can be used as a seed */ + base->MODE = mode & ~((1U << CRC_MODE_BIT_RVS_SUM_SHIFT) | (1U << CRC_MODE_CMPL_SUM_SHIFT)); + + /* now we can obtain intermediate raw CRC sum value */ + config->seed = base->SUM; + + /* restore original CRC sum bit reverse and 1's complement setting */ + base->MODE = mode; +} + +/*! + * brief Writes data to the CRC module. + * + * Writes input data buffer bytes to CRC data register. + * + * param base CRC peripheral address. + * param data Input data stream, MSByte in data[0]. + * param dataSize Size of the input data buffer in bytes. + */ +void CRC_WriteData(CRC_Type *base, const uint8_t *data, size_t dataSize) +{ + const uint32_t *data32; + + /* 8-bit reads and writes till source address is aligned 4 bytes */ + while ((0U != dataSize) && (0U != ((uint32_t)data & 3U))) + { + *((__O uint8_t *)&(base->WR_DATA)) = *data; + data++; + dataSize--; + } + + /* use 32-bit reads and writes as long as possible */ + data32 = (const uint32_t *)(uint32_t)data; + while (dataSize >= sizeof(uint32_t)) + { + *((__O uint32_t *)&(base->WR_DATA)) = *data32; + data32++; + dataSize -= sizeof(uint32_t); + } + + data = (const uint8_t *)data32; + + /* 8-bit reads and writes till end of data buffer */ + while (0U != dataSize) + { + *((__O uint8_t *)&(base->WR_DATA)) = *data; + data++; + dataSize--; + } +} diff --git a/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_crc.h b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_crc.h new file mode 100644 index 0000000000..08e08bd57d --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_crc.h @@ -0,0 +1,195 @@ +/* + * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017, 2019-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_CRC_H_ +#define _FSL_CRC_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup crc + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief CRC driver version. Version 2.1.1. + * + * Current version: 2.1.1 + * + * Change log: + * - Version 2.0.0 + * - initial version + * - Version 2.0.1 + * - add explicit type cast when writing to WR_DATA + * - Version 2.0.2 + * - Fix MISRA issue + * - Version 2.1.0 + * - Add CRC_WriteSeed function + * - Version 2.1.1 + * - Fix MISRA issue + */ +#define FSL_CRC_DRIVER_VERSION (MAKE_VERSION(2, 1, 1)) +/*@}*/ + +#ifndef CRC_DRIVER_CUSTOM_DEFAULTS +/*! @brief Default configuration structure filled by CRC_GetDefaultConfig(). Uses CRC-16/CCITT-FALSE as default. */ +#define CRC_DRIVER_USE_CRC16_CCITT_FALSE_AS_DEFAULT 1 +#endif + +/*! @brief CRC polynomials to use. */ +typedef enum _crc_polynomial +{ + kCRC_Polynomial_CRC_CCITT = 0U, /*!< x^16+x^12+x^5+1 */ + kCRC_Polynomial_CRC_16 = 1U, /*!< x^16+x^15+x^2+1 */ + kCRC_Polynomial_CRC_32 = 2U /*!< x^32+x^26+x^23+x^22+x^16+x^12+x^11+x^10+x^8+x^7+x^5+x^4+x^2+x+1 */ +} crc_polynomial_t; + +/*! + * @brief CRC protocol configuration. + * + * This structure holds the configuration for the CRC protocol. + * + */ +typedef struct _crc_config +{ + crc_polynomial_t polynomial; /*!< CRC polynomial. */ + bool reverseIn; /*!< Reverse bits on input. */ + bool complementIn; /*!< Perform 1's complement on input. */ + bool reverseOut; /*!< Reverse bits on output. */ + bool complementOut; /*!< Perform 1's complement on output. */ + uint32_t seed; /*!< Starting checksum value. */ +} crc_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Enables and configures the CRC peripheral module. + * + * This functions enables the CRC peripheral clock in the LPC SYSCON block. + * It also configures the CRC engine and starts checksum computation by writing the seed. + * + * @param base CRC peripheral address. + * @param config CRC module configuration structure. + */ +void CRC_Init(CRC_Type *base, const crc_config_t *config); + +/*! + * @brief Disables the CRC peripheral module. + * + * This functions disables the CRC peripheral clock in the LPC SYSCON block. + * + * @param base CRC peripheral address. + */ +static inline void CRC_Deinit(CRC_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* disable clock to CRC */ + CLOCK_DisableClock(kCLOCK_Crc); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/*! + * @brief resets CRC peripheral module. + * + * @param base CRC peripheral address. + */ +void CRC_Reset(CRC_Type *base); + +/*! + * @brief Write seed to CRC peripheral module. + * + * @param base CRC peripheral address. + * @param seed CRC Seed value. + */ +void CRC_WriteSeed(CRC_Type *base, uint32_t seed); + +/*! + * @brief Loads default values to CRC protocol configuration structure. + * + * Loads default values to CRC protocol configuration structure. The default values are: + * @code + * config->polynomial = kCRC_Polynomial_CRC_CCITT; + * config->reverseIn = false; + * config->complementIn = false; + * config->reverseOut = false; + * config->complementOut = false; + * config->seed = 0xFFFFU; + * @endcode + * + * @param config CRC protocol configuration structure + */ +void CRC_GetDefaultConfig(crc_config_t *config); + +/*! + * @brief Loads actual values configured in CRC peripheral to CRC protocol configuration structure. + * + * The values, including seed, can be used to resume CRC calculation later. + + * @param base CRC peripheral address. + * @param config CRC protocol configuration structure + */ +void CRC_GetConfig(CRC_Type *base, crc_config_t *config); + +/*! + * @brief Writes data to the CRC module. + * + * Writes input data buffer bytes to CRC data register. + * + * @param base CRC peripheral address. + * @param data Input data stream, MSByte in data[0]. + * @param dataSize Size of the input data buffer in bytes. + */ +void CRC_WriteData(CRC_Type *base, const uint8_t *data, size_t dataSize); + +/*! + * @brief Reads 32-bit checksum from the CRC module. + * + * Reads CRC data register. + * + * @param base CRC peripheral address. + * @return final 32-bit checksum, after configured bit reverse and complement operations. + */ +static inline uint32_t CRC_Get32bitResult(CRC_Type *base) +{ + return base->SUM; +} + +/*! + * @brief Reads 16-bit checksum from the CRC module. + * + * Reads CRC data register. + * + * @param base CRC peripheral address. + * @return final 16-bit checksum, after configured bit reverse and complement operations. + */ +static inline uint16_t CRC_Get16bitResult(CRC_Type *base) +{ + return (uint16_t)base->SUM; +} + +#if defined(__cplusplus) +} +#endif + +/*! + *@} + */ + +#endif /* _FSL_CRC_H_ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_ctimer.c b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_ctimer.c new file mode 100644 index 0000000000..e53bebdd01 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_ctimer.c @@ -0,0 +1,577 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_ctimer.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.ctimer" +#endif + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Gets the instance from the base address + * + * @param base Ctimer peripheral base address + * + * @return The Timer instance + */ +static uint32_t CTIMER_GetInstance(CTIMER_Type *base); + +/*! + * @brief CTIMER generic IRQ handle function. + * + * @param index FlexCAN peripheral instance index. + */ +static void CTIMER_GenericIRQHandler(uint32_t index); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Pointers to Timer bases for each instance. */ +static CTIMER_Type *const s_ctimerBases[] = CTIMER_BASE_PTRS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Pointers to Timer clocks for each instance. */ +static const clock_ip_name_t s_ctimerClocks[] = CTIMER_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_RESET) && (FSL_FEATURE_CTIMER_HAS_NO_RESET)) +#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) +#if defined(FSL_FEATURE_CTIMER_WRITE_ZERO_ASSERT_RESET) && FSL_FEATURE_CTIMER_WRITE_ZERO_ASSERT_RESET +/*! @brief Pointers to Timer resets for each instance, writing a zero asserts the reset */ +static const reset_ip_name_t s_ctimerResets[] = CTIMER_RSTS_N; +#else +/*! @brief Pointers to Timer resets for each instance, writing a one asserts the reset */ +static const reset_ip_name_t s_ctimerResets[] = CTIMER_RSTS; +#endif +#endif +#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ + +/*! @brief Pointers real ISRs installed by drivers for each instance. */ +static ctimer_callback_t *s_ctimerCallback[sizeof(s_ctimerBases) / sizeof(s_ctimerBases[0])] = {0}; + +/*! @brief Callback type installed by drivers for each instance. */ +static ctimer_callback_type_t ctimerCallbackType[sizeof(s_ctimerBases) / sizeof(s_ctimerBases[0])] = { + kCTIMER_SingleCallback}; + +/*! @brief Array to map timer instance to IRQ number. */ +static const IRQn_Type s_ctimerIRQ[] = CTIMER_IRQS; + +/******************************************************************************* + * Code + ******************************************************************************/ +static uint32_t CTIMER_GetInstance(CTIMER_Type *base) +{ + uint32_t instance; + uint32_t ctimerArrayCount = (sizeof(s_ctimerBases) / sizeof(s_ctimerBases[0])); + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ctimerArrayCount; instance++) + { + if (s_ctimerBases[instance] == base) + { + break; + } + } + + assert(instance < ctimerArrayCount); + + return instance; +} + +/*! + * brief Ungates the clock and configures the peripheral for basic operation. + * + * note This API should be called at the beginning of the application before using the driver. + * + * param base Ctimer peripheral base address + * param config Pointer to the user configuration structure. + */ +void CTIMER_Init(CTIMER_Type *base, const ctimer_config_t *config) +{ + assert(config != NULL); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable the timer clock*/ + CLOCK_EnableClock(s_ctimerClocks[CTIMER_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) +/* Reset the module. */ +#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_RESET) && (FSL_FEATURE_CTIMER_HAS_NO_RESET)) + RESET_PeripheralReset(s_ctimerResets[CTIMER_GetInstance(base)]); +#endif +#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ + +/* Setup the cimer mode and count select */ +#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && (FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE)) + base->CTCR = CTIMER_CTCR_CTMODE(config->mode) | CTIMER_CTCR_CINSEL(config->input); +#endif + /* Setup the timer prescale value */ + base->PR = CTIMER_PR_PRVAL(config->prescale); +} + +/*! + * brief Gates the timer clock. + * + * param base Ctimer peripheral base address + */ +void CTIMER_Deinit(CTIMER_Type *base) +{ + uint32_t index = CTIMER_GetInstance(base); + /* Stop the timer */ + base->TCR &= ~CTIMER_TCR_CEN_MASK; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Disable the timer clock*/ + CLOCK_DisableClock(s_ctimerClocks[index]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + /* Disable IRQ at NVIC Level */ + (void)DisableIRQ(s_ctimerIRQ[index]); +} + +/*! + * brief Fills in the timers configuration structure with the default settings. + * + * The default values are: + * code + * config->mode = kCTIMER_TimerMode; + * config->input = kCTIMER_Capture_0; + * config->prescale = 0; + * endcode + * param config Pointer to the user configuration structure. + */ +void CTIMER_GetDefaultConfig(ctimer_config_t *config) +{ + assert(config != NULL); + + /* Initializes the configure structure to zero. */ + (void)memset(config, 0, sizeof(*config)); + + /* Run as a timer */ + config->mode = kCTIMER_TimerMode; + /* This field is ignored when mode is timer */ + config->input = kCTIMER_Capture_0; + /* Timer counter is incremented on every APB bus clock */ + config->prescale = 0; +} + +/*! + * brief Configures the PWM signal parameters. + * + * Enables PWM mode on the match channel passed in and will then setup the match value + * and other match parameters to generate a PWM signal. + * This function can manually assign the specified channel to set the PWM cycle. + * + * note When setting PWM output from multiple output pins, all should use the same PWM + * frequency. Please use CTIMER_SetupPwmPeriod to set up the PWM with high resolution. + * + * param base Ctimer peripheral base address + * param pwmPeriodChannel Specify the channel to control the PWM period + * param matchChannel Match pin to be used to output the PWM signal + * param dutyCyclePercent PWM pulse width; the value should be between 0 to 100 + * param pwmFreq_Hz PWM signal frequency in Hz + * param srcClock_Hz Timer counter clock in Hz + * param enableInt Enable interrupt when the timer value reaches the match value of the PWM pulse, + * if it is 0 then no interrupt will be generated. + * + * return kStatus_Success on success + * kStatus_Fail If matchChannel is equal to pwmPeriodChannel; this channel is reserved to set the PWM cycle + */ +status_t CTIMER_SetupPwm(CTIMER_Type *base, + const ctimer_match_t pwmPeriodChannel, + ctimer_match_t matchChannel, + uint8_t dutyCyclePercent, + uint32_t pwmFreq_Hz, + uint32_t srcClock_Hz, + bool enableInt) +{ + assert(pwmFreq_Hz > 0U); + + uint32_t reg; + uint32_t period, pulsePeriod = 0; + uint32_t timerClock = srcClock_Hz / (base->PR + 1U); + uint32_t index = CTIMER_GetInstance(base); + + if (matchChannel == pwmPeriodChannel) + { + return kStatus_Fail; + } + + /* Enable PWM mode on the match channel */ + base->PWMC |= (1UL << (uint32_t)matchChannel); + + /* Clear the stop, reset and interrupt bits for this channel */ + reg = base->MCR; + reg &= + ~(((uint32_t)((uint32_t)CTIMER_MCR_MR0R_MASK | (uint32_t)CTIMER_MCR_MR0S_MASK | (uint32_t)CTIMER_MCR_MR0I_MASK)) + << ((uint32_t)matchChannel * 3U)); + + /* If call back function is valid then enable match interrupt for the channel */ + if (enableInt) + { + reg |= (((uint32_t)CTIMER_MCR_MR0I_MASK) << (CTIMER_MCR_MR0I_SHIFT + ((uint32_t)matchChannel * 3U))); + } + + /* Reset the counter when match on PWM period channel (pwmPeriodChannel) */ + reg |= ((uint32_t)((uint32_t)CTIMER_MCR_MR0R_MASK) << ((uint32_t)pwmPeriodChannel * 3U)); + + base->MCR = reg; + + /* Calculate PWM period match value */ + period = (timerClock / pwmFreq_Hz) - 1U; + + /* Calculate pulse width match value */ + if (dutyCyclePercent == 0U) + { + pulsePeriod = period + 1U; + } + else + { + pulsePeriod = (period * (100U - (uint32_t)dutyCyclePercent)) / 100U; + } + + /* Specified channel pwmPeriodChannel will define the PWM period */ + base->MR[pwmPeriodChannel] = period; + + /* This will define the PWM pulse period */ + base->MR[matchChannel] = pulsePeriod; + /* Clear status flags */ + CTIMER_ClearStatusFlags(base, ((uint32_t)CTIMER_IR_MR0INT_MASK) << (uint32_t)matchChannel); + /* If call back function is valid then enable interrupt and update the call back function */ + if (enableInt) + { + (void)EnableIRQ(s_ctimerIRQ[index]); + } + + return kStatus_Success; +} + +/*! + * brief Configures the PWM signal parameters. + * + * Enables PWM mode on the match channel passed in and will then setup the match value + * and other match parameters to generate a PWM signal. + * This function can manually assign the specified channel to set the PWM cycle. + * + * note When setting PWM output from multiple output pins, all should use the same PWM + * period + * + * param base Ctimer peripheral base address + * param pwmPeriodChannel Specify the channel to control the PWM period + * param matchChannel Match pin to be used to output the PWM signal + * param pwmPeriod PWM period match value + * param pulsePeriod Pulse width match value + * param enableInt Enable interrupt when the timer value reaches the match value of the PWM pulse, + * if it is 0 then no interrupt will be generated. + * + * return kStatus_Success on success + * kStatus_Fail If matchChannel is equal to pwmPeriodChannel; this channel is reserved to set the PWM period + */ +status_t CTIMER_SetupPwmPeriod(CTIMER_Type *base, + const ctimer_match_t pwmPeriodChannel, + ctimer_match_t matchChannel, + uint32_t pwmPeriod, + uint32_t pulsePeriod, + bool enableInt) +{ +/* Some CTimers only have 16bits , so the value is limited*/ +#if defined(FSL_FEATURE_SOC_CTIMER16B) && FSL_FEATURE_SOC_CTIMER16B + assert(!((FSL_FEATURE_CTIMER_BIT_SIZEn(base) < 32) && (pulsePeriod > 0xFFFFU))); +#endif + + uint32_t reg; + uint32_t index = CTIMER_GetInstance(base); + + if (matchChannel == pwmPeriodChannel) + { + return kStatus_Fail; + } + + /* Enable PWM mode on PWM pulse channel */ + base->PWMC |= (1UL << (uint32_t)matchChannel); + + /* Clear the stop, reset and interrupt bits for PWM pulse channel */ + reg = base->MCR; + reg &= + ~((uint32_t)((uint32_t)CTIMER_MCR_MR0R_MASK | (uint32_t)CTIMER_MCR_MR0S_MASK | (uint32_t)CTIMER_MCR_MR0I_MASK) + << ((uint32_t)matchChannel * 3U)); + + /* If call back function is valid then enable match interrupt for PWM pulse channel */ + if (enableInt) + { + reg |= (((uint32_t)CTIMER_MCR_MR0I_MASK) << (CTIMER_MCR_MR0I_SHIFT + ((uint32_t)matchChannel * 3U))); + } + + /* Reset the counter when match on PWM period channel (pwmPeriodChannel) */ + reg |= ((uint32_t)((uint32_t)CTIMER_MCR_MR0R_MASK) << ((uint32_t)pwmPeriodChannel * 3U)); + + base->MCR = reg; + + /* Specified channel pwmPeriodChannel will define the PWM period */ + base->MR[pwmPeriodChannel] = pwmPeriod; + + /* This will define the PWM pulse period */ + base->MR[matchChannel] = pulsePeriod; + /* Clear status flags */ + CTIMER_ClearStatusFlags(base, ((uint32_t)CTIMER_IR_MR0INT_MASK) << (uint32_t)matchChannel); + /* If call back function is valid then enable interrupt and update the call back function */ + if (enableInt) + { + (void)EnableIRQ(s_ctimerIRQ[index]); + } + + return kStatus_Success; +} + +/*! + * brief Updates the duty cycle of an active PWM signal. + * + * note Please use CTIMER_SetupPwmPeriod to update the PWM with high resolution. + * This function can manually assign the specified channel to set the PWM cycle. + * + * param base Ctimer peripheral base address + * param pwmPeriodChannel Specify the channel to control the PWM period + * param matchChannel Match pin to be used to output the PWM signal + * param dutyCyclePercent New PWM pulse width; the value should be between 0 to 100 + */ +void CTIMER_UpdatePwmDutycycle(CTIMER_Type *base, + const ctimer_match_t pwmPeriodChannel, + ctimer_match_t matchChannel, + uint8_t dutyCyclePercent) +{ + uint32_t pulsePeriod = 0, period; + + /* Specified channel pwmPeriodChannel defines the PWM period */ + period = base->MR[pwmPeriodChannel]; + + /* For 0% dutycyle, make pulse period greater than period so the event will never occur */ + if (dutyCyclePercent == 0U) + { + pulsePeriod = period + 1U; + } + else + { + pulsePeriod = (period * (100U - (uint32_t)dutyCyclePercent)) / 100U; + } + + /* Update dutycycle */ + base->MR[matchChannel] = pulsePeriod; +} + +/*! + * brief Setup the match register. + * + * User configuration is used to setup the match value and action to be taken when a match occurs. + * + * param base Ctimer peripheral base address + * param matchChannel Match register to configure + * param config Pointer to the match configuration structure + */ +void CTIMER_SetupMatch(CTIMER_Type *base, ctimer_match_t matchChannel, const ctimer_match_config_t *config) +{ +/* Some CTimers only have 16bits , so the value is limited*/ +#if defined(FSL_FEATURE_SOC_CTIMER16B) && FSL_FEATURE_SOC_CTIMER16B + assert(!(FSL_FEATURE_CTIMER_BIT_SIZEn(base) < 32 && config->matchValue > 0xFFFFU)); +#endif + uint32_t reg; + uint32_t index = CTIMER_GetInstance(base); + + /* Set the counter operation when a match on this channel occurs */ + reg = base->MCR; + reg &= + ~((uint32_t)((uint32_t)CTIMER_MCR_MR0R_MASK | (uint32_t)CTIMER_MCR_MR0S_MASK | (uint32_t)CTIMER_MCR_MR0I_MASK) + << ((uint32_t)matchChannel * 3U)); + reg |= ((uint32_t)(config->enableCounterReset) << (CTIMER_MCR_MR0R_SHIFT + ((uint32_t)matchChannel * 3U))); + reg |= ((uint32_t)(config->enableCounterStop) << (CTIMER_MCR_MR0S_SHIFT + ((uint32_t)matchChannel * 3U))); + reg |= ((uint32_t)(config->enableInterrupt) << (CTIMER_MCR_MR0I_SHIFT + ((uint32_t)matchChannel * 3U))); + base->MCR = reg; + + reg = base->EMR; + /* Set the match output operation when a match on this channel occurs */ + reg &= ~(((uint32_t)CTIMER_EMR_EMC0_MASK) << ((uint32_t)matchChannel * 2U)); + reg |= ((uint32_t)config->outControl) << (CTIMER_EMR_EMC0_SHIFT + ((uint32_t)matchChannel * 2U)); + + /* Set the initial state of the EM bit/output */ + reg &= ~(((uint32_t)CTIMER_EMR_EM0_MASK) << (uint32_t)matchChannel); + reg |= ((uint32_t)config->outPinInitState) << (uint32_t)matchChannel; + base->EMR = reg; + + /* Set the match value */ + base->MR[matchChannel] = config->matchValue; + /* Clear status flags */ + CTIMER_ClearStatusFlags(base, ((uint32_t)CTIMER_IR_MR0INT_MASK) << (uint32_t)matchChannel); + /* If interrupt is enabled then enable interrupt and update the call back function */ + if (config->enableInterrupt) + { + (void)EnableIRQ(s_ctimerIRQ[index]); + } +} + +/*! + * brief Get the status of output match. + * + * This function gets the status of output MAT, whether or not this output is connected to a pin. + * This status is driven to the MAT pins if the match function is selected via IOCON. 0 = LOW. 1 = HIGH. + * + * param base Ctimer peripheral base address + * param matchChannel External match channel, user can obtain the status of multiple match channels + * at the same time by using the logic of "|" + * enumeration ::ctimer_external_match_t + * return The mask of external match channel status flags. Users need to use the + * _ctimer_external_match type to decode the return variables. + */ +uint32_t CTIMER_GetOutputMatchStatus(CTIMER_Type *base, uint32_t matchChannel) +{ + return (base->EMR & matchChannel); +} + +#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && (FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE)) +/*! + * brief Setup the capture. + * + * param base Ctimer peripheral base address + * param capture Capture channel to configure + * param edge Edge on the channel that will trigger a capture + * param enableInt Flag to enable channel interrupts, if enabled then the registered call back + * is called upon capture + */ +void CTIMER_SetupCapture(CTIMER_Type *base, + ctimer_capture_channel_t capture, + ctimer_capture_edge_t edge, + bool enableInt) +{ + uint32_t reg = base->CCR; + uint32_t index = CTIMER_GetInstance(base); + + /* Set the capture edge */ + reg &= ~((uint32_t)((uint32_t)CTIMER_CCR_CAP0RE_MASK | (uint32_t)CTIMER_CCR_CAP0FE_MASK | + (uint32_t)CTIMER_CCR_CAP0I_MASK) + << ((uint32_t)capture * 3U)); + reg |= ((uint32_t)edge) << (CTIMER_CCR_CAP0RE_SHIFT + ((uint32_t)capture * 3U)); + /* Clear status flags */ + CTIMER_ClearStatusFlags(base, (((uint32_t)kCTIMER_Capture0Flag) << (uint32_t)capture)); + /* If call back function is valid then enable capture interrupt for the channel and update the call back function */ + if (enableInt) + { + reg |= ((uint32_t)CTIMER_CCR_CAP0I_MASK) << ((uint32_t)capture * 3U); + (void)EnableIRQ(s_ctimerIRQ[index]); + } + base->CCR = reg; +} +#endif + +/*! + * brief Register callback. + * + * param base Ctimer peripheral base address + * param cb_func callback function + * param cb_type callback function type, singular or multiple + */ +void CTIMER_RegisterCallBack(CTIMER_Type *base, ctimer_callback_t *cb_func, ctimer_callback_type_t cb_type) +{ + uint32_t index = CTIMER_GetInstance(base); + s_ctimerCallback[index] = cb_func; + ctimerCallbackType[index] = cb_type; +} + +/*! + * brief CTIMER generic IRQ handle function. + * + * param index FlexCAN peripheral instance index. + */ +static void CTIMER_GenericIRQHandler(uint32_t index) +{ + uint32_t int_stat, i, mask; + /* Get Interrupt status flags */ + int_stat = CTIMER_GetStatusFlags(s_ctimerBases[index]); + /* Clear the status flags that were set */ + CTIMER_ClearStatusFlags(s_ctimerBases[index], int_stat); + if (ctimerCallbackType[index] == kCTIMER_SingleCallback) + { + if (s_ctimerCallback[index][0] != NULL) + { + s_ctimerCallback[index][0](int_stat); + } + } + else + { +#if defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE + for (i = 0; i <= CTIMER_IR_MR3INT_SHIFT; i++) +#else +#if defined(FSL_FEATURE_CTIMER_HAS_IR_CR3INT) && FSL_FEATURE_CTIMER_HAS_IR_CR3INT + for (i = 0; i <= CTIMER_IR_CR3INT_SHIFT; i++) +#else +#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT) && FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT) + for (i = 0; i <= CTIMER_IR_CR2INT_SHIFT; i++) +#else + for (i = 0; i <= CTIMER_IR_CR1INT_SHIFT; i++) +#endif /* FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT */ +#endif /* FSL_FEATURE_CTIMER_HAS_IR_CR3INT */ +#endif + { + mask = 0x01UL << i; + /* For each status flag bit that was set call the callback function if it is valid */ + if (((int_stat & mask) != 0U) && (s_ctimerCallback[index][i] != NULL)) + { + s_ctimerCallback[index][i](int_stat); + } + } + } + SDK_ISR_EXIT_BARRIER; +} + +/* IRQ handler functions overloading weak symbols in the startup */ +#if defined(CTIMER0) +void CTIMER0_DriverIRQHandler(void); +void CTIMER0_DriverIRQHandler(void) +{ + CTIMER_GenericIRQHandler(0); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(CTIMER1) +void CTIMER1_DriverIRQHandler(void); +void CTIMER1_DriverIRQHandler(void) +{ + CTIMER_GenericIRQHandler(1); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(CTIMER2) +void CTIMER2_DriverIRQHandler(void); +void CTIMER2_DriverIRQHandler(void) +{ + CTIMER_GenericIRQHandler(2); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(CTIMER3) +void CTIMER3_DriverIRQHandler(void); +void CTIMER3_DriverIRQHandler(void) +{ + CTIMER_GenericIRQHandler(3); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(CTIMER4) +void CTIMER4_DriverIRQHandler(void); +void CTIMER4_DriverIRQHandler(void) +{ + CTIMER_GenericIRQHandler(4); + SDK_ISR_EXIT_BARRIER; +} +#endif diff --git a/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_ctimer.h b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_ctimer.h new file mode 100644 index 0000000000..ca39c95d30 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_ctimer.h @@ -0,0 +1,533 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_CTIMER_H_ +#define _FSL_CTIMER_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup ctimer + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +#define FSL_CTIMER_DRIVER_VERSION (MAKE_VERSION(2, 2, 2)) /*!< Version 2.2.2 */ +/*@}*/ + +/*! @brief List of Timer capture channels */ +typedef enum _ctimer_capture_channel +{ + kCTIMER_Capture_0 = 0U, /*!< Timer capture channel 0 */ + kCTIMER_Capture_1, /*!< Timer capture channel 1 */ +#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2) && FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2) + kCTIMER_Capture_2, /*!< Timer capture channel 2 */ +#endif /* FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2 */ +#if defined(FSL_FEATURE_CTIMER_HAS_CCR_CAP3) && FSL_FEATURE_CTIMER_HAS_CCR_CAP3 + kCTIMER_Capture_3 /*!< Timer capture channel 3 */ +#endif /* FSL_FEATURE_CTIMER_HAS_CCR_CAP3 */ +} ctimer_capture_channel_t; + +/*! @brief List of capture edge options */ +typedef enum _ctimer_capture_edge +{ + kCTIMER_Capture_RiseEdge = 1U, /*!< Capture on rising edge */ + kCTIMER_Capture_FallEdge = 2U, /*!< Capture on falling edge */ + kCTIMER_Capture_BothEdge = 3U, /*!< Capture on rising and falling edge */ +} ctimer_capture_edge_t; + +/*! @brief List of Timer match registers */ +typedef enum _ctimer_match +{ + kCTIMER_Match_0 = 0U, /*!< Timer match register 0 */ + kCTIMER_Match_1, /*!< Timer match register 1 */ + kCTIMER_Match_2, /*!< Timer match register 2 */ + kCTIMER_Match_3 /*!< Timer match register 3 */ +} ctimer_match_t; + +/*! @brief List of external match */ +typedef enum _ctimer_external_match +{ + kCTIMER_External_Match_0 = (1U << 0), /*!< External match 0 */ + kCTIMER_External_Match_1 = (1U << 1), /*!< External match 1 */ + kCTIMER_External_Match_2 = (1U << 2), /*!< External match 2 */ + kCTIMER_External_Match_3 = (1U << 3) /*!< External match 3 */ +} ctimer_external_match_t; + +/*! @brief List of output control options */ +typedef enum _ctimer_match_output_control +{ + kCTIMER_Output_NoAction = 0U, /*!< No action is taken */ + kCTIMER_Output_Clear, /*!< Clear the EM bit/output to 0 */ + kCTIMER_Output_Set, /*!< Set the EM bit/output to 1 */ + kCTIMER_Output_Toggle /*!< Toggle the EM bit/output */ +} ctimer_match_output_control_t; + +/*! @brief List of Timer modes */ +typedef enum _ctimer_timer_mode +{ + kCTIMER_TimerMode = 0U, /* TC is incremented every rising APB bus clock edge */ + kCTIMER_IncreaseOnRiseEdge, /* TC is incremented on rising edge of input signal */ + kCTIMER_IncreaseOnFallEdge, /* TC is incremented on falling edge of input signal */ + kCTIMER_IncreaseOnBothEdge /* TC is incremented on both edges of input signal */ +} ctimer_timer_mode_t; + +/*! @brief List of Timer interrupts */ +typedef enum _ctimer_interrupt_enable +{ + kCTIMER_Match0InterruptEnable = CTIMER_MCR_MR0I_MASK, /*!< Match 0 interrupt */ + kCTIMER_Match1InterruptEnable = CTIMER_MCR_MR1I_MASK, /*!< Match 1 interrupt */ + kCTIMER_Match2InterruptEnable = CTIMER_MCR_MR2I_MASK, /*!< Match 2 interrupt */ + kCTIMER_Match3InterruptEnable = CTIMER_MCR_MR3I_MASK, /*!< Match 3 interrupt */ +#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && (FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE)) + kCTIMER_Capture0InterruptEnable = CTIMER_CCR_CAP0I_MASK, /*!< Capture 0 interrupt */ + kCTIMER_Capture1InterruptEnable = CTIMER_CCR_CAP1I_MASK, /*!< Capture 1 interrupt */ +#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2) && FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2) + kCTIMER_Capture2InterruptEnable = CTIMER_CCR_CAP2I_MASK, /*!< Capture 2 interrupt */ +#endif /* FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2 */ +#if defined(FSL_FEATURE_CTIMER_HAS_CCR_CAP3) && FSL_FEATURE_CTIMER_HAS_CCR_CAP3 + kCTIMER_Capture3InterruptEnable = CTIMER_CCR_CAP3I_MASK, /*!< Capture 3 interrupt */ +#endif /* FSL_FEATURE_CTIMER_HAS_CCR_CAP3 */ +#endif +} ctimer_interrupt_enable_t; + +/*! @brief List of Timer flags */ +typedef enum _ctimer_status_flags +{ + kCTIMER_Match0Flag = CTIMER_IR_MR0INT_MASK, /*!< Match 0 interrupt flag */ + kCTIMER_Match1Flag = CTIMER_IR_MR1INT_MASK, /*!< Match 1 interrupt flag */ + kCTIMER_Match2Flag = CTIMER_IR_MR2INT_MASK, /*!< Match 2 interrupt flag */ + kCTIMER_Match3Flag = CTIMER_IR_MR3INT_MASK, /*!< Match 3 interrupt flag */ +#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && (FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE)) + kCTIMER_Capture0Flag = CTIMER_IR_CR0INT_MASK, /*!< Capture 0 interrupt flag */ + kCTIMER_Capture1Flag = CTIMER_IR_CR1INT_MASK, /*!< Capture 1 interrupt flag */ +#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT) && FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT) + kCTIMER_Capture2Flag = CTIMER_IR_CR2INT_MASK, /*!< Capture 2 interrupt flag */ +#endif /* FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT */ +#if defined(FSL_FEATURE_CTIMER_HAS_IR_CR3INT) && FSL_FEATURE_CTIMER_HAS_IR_CR3INT + kCTIMER_Capture3Flag = CTIMER_IR_CR3INT_MASK, /*!< Capture 3 interrupt flag */ +#endif /* FSL_FEATURE_CTIMER_HAS_IR_CR3INT */ +#endif +} ctimer_status_flags_t; + +typedef void (*ctimer_callback_t)(uint32_t flags); + +/*! @brief Callback type when registering for a callback. When registering a callback + * an array of function pointers is passed the size could be 1 or 8, the callback + * type will tell that. + */ +typedef enum +{ + kCTIMER_SingleCallback, /*!< Single Callback type where there is only one callback for the timer. + based on the status flags different channels needs to be handled differently */ + kCTIMER_MultipleCallback /*!< Multiple Callback type where there can be 8 valid callbacks, one per channel. + for both match/capture */ +} ctimer_callback_type_t; + +/*! + * @brief Match configuration + * + * This structure holds the configuration settings for each match register. + */ +typedef struct _ctimer_match_config +{ + uint32_t matchValue; /*!< This is stored in the match register */ + bool enableCounterReset; /*!< true: Match will reset the counter + false: Match will not reser the counter */ + bool enableCounterStop; /*!< true: Match will stop the counter + false: Match will not stop the counter */ + ctimer_match_output_control_t outControl; /*!< Action to be taken on a match on the EM bit/output */ + bool outPinInitState; /*!< Initial value of the EM bit/output */ + bool enableInterrupt; /*!< true: Generate interrupt upon match + false: Do not generate interrupt on match */ + +} ctimer_match_config_t; + +/*! + * @brief Timer configuration structure + * + * This structure holds the configuration settings for the Timer peripheral. To initialize this + * structure to reasonable defaults, call the CTIMER_GetDefaultConfig() function and pass a + * pointer to the configuration structure instance. + * + * The configuration structure can be made constant so as to reside in flash. + */ +typedef struct _ctimer_config +{ + ctimer_timer_mode_t mode; /*!< Timer mode */ + ctimer_capture_channel_t input; /*!< Input channel to increment the timer, used only in timer + modes that rely on this input signal to increment TC */ + uint32_t prescale; /*!< Prescale value */ +} ctimer_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Ungates the clock and configures the peripheral for basic operation. + * + * @note This API should be called at the beginning of the application before using the driver. + * + * @param base Ctimer peripheral base address + * @param config Pointer to the user configuration structure. + */ +void CTIMER_Init(CTIMER_Type *base, const ctimer_config_t *config); + +/*! + * @brief Gates the timer clock. + * + * @param base Ctimer peripheral base address + */ +void CTIMER_Deinit(CTIMER_Type *base); + +/*! + * @brief Fills in the timers configuration structure with the default settings. + * + * The default values are: + * @code + * config->mode = kCTIMER_TimerMode; + * config->input = kCTIMER_Capture_0; + * config->prescale = 0; + * @endcode + * @param config Pointer to the user configuration structure. + */ +void CTIMER_GetDefaultConfig(ctimer_config_t *config); + +/*! @}*/ + +/*! + * @name PWM setup operations + * @{ + */ + +/*! + * @brief Configures the PWM signal parameters. + * + * Enables PWM mode on the match channel passed in and will then setup the match value + * and other match parameters to generate a PWM signal. + * This function can manually assign the specified channel to set the PWM cycle. + * + * @note When setting PWM output from multiple output pins, all should use the same PWM + * period + * + * @param base Ctimer peripheral base address + * @param pwmPeriodChannel Specify the channel to control the PWM period + * @param matchChannel Match pin to be used to output the PWM signal + * @param pwmPeriod PWM period match value + * @param pulsePeriod Pulse width match value + * @param enableInt Enable interrupt when the timer value reaches the match value of the PWM pulse, + * if it is 0 then no interrupt will be generated. + */ +status_t CTIMER_SetupPwmPeriod(CTIMER_Type *base, + const ctimer_match_t pwmPeriodChannel, + ctimer_match_t matchChannel, + uint32_t pwmPeriod, + uint32_t pulsePeriod, + bool enableInt); + +/*! + * @brief Configures the PWM signal parameters. + * + * Enables PWM mode on the match channel passed in and will then setup the match value + * and other match parameters to generate a PWM signal. + * This function can manually assign the specified channel to set the PWM cycle. + * + * @note When setting PWM output from multiple output pins, all should use the same PWM + * frequency. Please use CTIMER_SetupPwmPeriod to set up the PWM with high resolution. + * + * @param base Ctimer peripheral base address + * @param pwmPeriodChannel Specify the channel to control the PWM period + * @param matchChannel Match pin to be used to output the PWM signal + * @param dutyCyclePercent PWM pulse width; the value should be between 0 to 100 + * @param pwmFreq_Hz PWM signal frequency in Hz + * @param srcClock_Hz Timer counter clock in Hz + * @param enableInt Enable interrupt when the timer value reaches the match value of the PWM pulse, + * if it is 0 then no interrupt will be generated. + */ +status_t CTIMER_SetupPwm(CTIMER_Type *base, + const ctimer_match_t pwmPeriodChannel, + ctimer_match_t matchChannel, + uint8_t dutyCyclePercent, + uint32_t pwmFreq_Hz, + uint32_t srcClock_Hz, + bool enableInt); + +/*! + * @brief Updates the pulse period of an active PWM signal. + * + * @param base Ctimer peripheral base address + * @param matchChannel Match pin to be used to output the PWM signal + * @param pulsePeriod New PWM pulse width match value + */ +static inline void CTIMER_UpdatePwmPulsePeriod(CTIMER_Type *base, ctimer_match_t matchChannel, uint32_t pulsePeriod) +{ + /* Update PWM pulse period match value */ + base->MR[matchChannel] = pulsePeriod; +} + +/*! + * @brief Updates the duty cycle of an active PWM signal. + * + * @note Please use CTIMER_SetupPwmPeriod to update the PWM with high resolution. + * This function can manually assign the specified channel to set the PWM cycle. + * + * @param base Ctimer peripheral base address + * @param pwmPeriodChannel Specify the channel to control the PWM period + * @param matchChannel Match pin to be used to output the PWM signal + * @param dutyCyclePercent New PWM pulse width; the value should be between 0 to 100 + */ +void CTIMER_UpdatePwmDutycycle(CTIMER_Type *base, + const ctimer_match_t pwmPeriodChannel, + ctimer_match_t matchChannel, + uint8_t dutyCyclePercent); + +/*! @}*/ + +/*! + * @brief Setup the match register. + * + * User configuration is used to setup the match value and action to be taken when a match occurs. + * + * @param base Ctimer peripheral base address + * @param matchChannel Match register to configure + * @param config Pointer to the match configuration structure + */ +void CTIMER_SetupMatch(CTIMER_Type *base, ctimer_match_t matchChannel, const ctimer_match_config_t *config); + +/*! + * @brief Get the status of output match. + * + * This function gets the status of output MAT, whether or not this output is connected to a pin. + * This status is driven to the MAT pins if the match function is selected via IOCON. 0 = LOW. 1 = HIGH. + * + * @param base Ctimer peripheral base address + * @param matchChannel External match channel, user can obtain the status of multiple match channels + * at the same time by using the logic of "|" + * enumeration ::ctimer_external_match_t + * @return The mask of external match channel status flags. Users need to use the + * _ctimer_external_match type to decode the return variables. + */ +uint32_t CTIMER_GetOutputMatchStatus(CTIMER_Type *base, uint32_t matchChannel); + +/*! + * @brief Setup the capture. + * + * @param base Ctimer peripheral base address + * @param capture Capture channel to configure + * @param edge Edge on the channel that will trigger a capture + * @param enableInt Flag to enable channel interrupts, if enabled then the registered call back + * is called upon capture + */ +void CTIMER_SetupCapture(CTIMER_Type *base, + ctimer_capture_channel_t capture, + ctimer_capture_edge_t edge, + bool enableInt); + +/*! + * @brief Get the timer count value from TC register. + * + * @param base Ctimer peripheral base address. + * @return return the timer count value. + */ +static inline uint32_t CTIMER_GetTimerCountValue(CTIMER_Type *base) +{ + return (base->TC); +} + +/*! + * @brief Register callback. + * + * @param base Ctimer peripheral base address + * @param cb_func callback function + * @param cb_type callback function type, singular or multiple + */ +void CTIMER_RegisterCallBack(CTIMER_Type *base, ctimer_callback_t *cb_func, ctimer_callback_type_t cb_type); + +/*! + * @name Interrupt Interface + * @{ + */ + +/*! + * @brief Enables the selected Timer interrupts. + * + * @param base Ctimer peripheral base address + * @param mask The interrupts to enable. This is a logical OR of members of the + * enumeration ::ctimer_interrupt_enable_t + */ +static inline void CTIMER_EnableInterrupts(CTIMER_Type *base, uint32_t mask) +{ + /* Enable match interrupts */ + base->MCR |= mask & (CTIMER_MCR_MR0I_MASK | CTIMER_MCR_MR1I_MASK | CTIMER_MCR_MR2I_MASK | CTIMER_MCR_MR3I_MASK); + +/* Enable capture interrupts */ +#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && (FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE)) + base->CCR |= mask & (CTIMER_CCR_CAP0I_MASK | CTIMER_CCR_CAP1I_MASK +#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2) && FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2) + | CTIMER_CCR_CAP2I_MASK +#endif /* FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2 */ +#if defined(FSL_FEATURE_CTIMER_HAS_CCR_CAP3) && FSL_FEATURE_CTIMER_HAS_CCR_CAP3 + | CTIMER_CCR_CAP3I_MASK +#endif /* FSL_FEATURE_CTIMER_HAS_CCR_CAP3 */ + ); +#endif +} + +/*! + * @brief Disables the selected Timer interrupts. + * + * @param base Ctimer peripheral base address + * @param mask The interrupts to enable. This is a logical OR of members of the + * enumeration ::ctimer_interrupt_enable_t + */ +static inline void CTIMER_DisableInterrupts(CTIMER_Type *base, uint32_t mask) +{ + /* Disable match interrupts */ + base->MCR &= ~(mask & (CTIMER_MCR_MR0I_MASK | CTIMER_MCR_MR1I_MASK | CTIMER_MCR_MR2I_MASK | CTIMER_MCR_MR3I_MASK)); + +/* Disable capture interrupts */ +#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && (FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE)) + base->CCR &= ~(mask & (CTIMER_CCR_CAP0I_MASK | CTIMER_CCR_CAP1I_MASK +#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2) && FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2) + | CTIMER_CCR_CAP2I_MASK +#endif /* FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2 */ +#if defined(FSL_FEATURE_CTIMER_HAS_CCR_CAP3) && FSL_FEATURE_CTIMER_HAS_CCR_CAP3 + | CTIMER_CCR_CAP3I_MASK +#endif /* FSL_FEATURE_CTIMER_HAS_CCR_CAP3 */ + )); +#endif +} + +/*! + * @brief Gets the enabled Timer interrupts. + * + * @param base Ctimer peripheral base address + * + * @return The enabled interrupts. This is the logical OR of members of the + * enumeration ::ctimer_interrupt_enable_t + */ +static inline uint32_t CTIMER_GetEnabledInterrupts(CTIMER_Type *base) +{ + uint32_t enabledIntrs = 0; + + /* Get all the match interrupts enabled */ + enabledIntrs = + base->MCR & (CTIMER_MCR_MR0I_MASK | CTIMER_MCR_MR1I_MASK | CTIMER_MCR_MR2I_MASK | CTIMER_MCR_MR3I_MASK); + +/* Get all the capture interrupts enabled */ +#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && (FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE)) + enabledIntrs |= base->CCR & (CTIMER_CCR_CAP0I_MASK | CTIMER_CCR_CAP1I_MASK +#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2) && FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2) + | CTIMER_CCR_CAP2I_MASK +#endif /* FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2 */ +#if defined(FSL_FEATURE_CTIMER_HAS_CCR_CAP3) && FSL_FEATURE_CTIMER_HAS_CCR_CAP3 + | CTIMER_CCR_CAP3I_MASK +#endif /* FSL_FEATURE_CTIMER_HAS_CCR_CAP3 */ + ); +#endif + + return enabledIntrs; +} + +/*! @}*/ + +/*! + * @name Status Interface + * @{ + */ + +/*! + * @brief Gets the Timer status flags. + * + * @param base Ctimer peripheral base address + * + * @return The status flags. This is the logical OR of members of the + * enumeration ::ctimer_status_flags_t + */ +static inline uint32_t CTIMER_GetStatusFlags(CTIMER_Type *base) +{ + return base->IR; +} + +/*! + * @brief Clears the Timer status flags. + * + * @param base Ctimer peripheral base address + * @param mask The status flags to clear. This is a logical OR of members of the + * enumeration ::ctimer_status_flags_t + */ +static inline void CTIMER_ClearStatusFlags(CTIMER_Type *base, uint32_t mask) +{ + base->IR = mask; +} + +/*! @}*/ + +/*! + * @name Counter Start and Stop + * @{ + */ + +/*! + * @brief Starts the Timer counter. + * + * @param base Ctimer peripheral base address + */ +static inline void CTIMER_StartTimer(CTIMER_Type *base) +{ + base->TCR |= CTIMER_TCR_CEN_MASK; +} + +/*! + * @brief Stops the Timer counter. + * + * @param base Ctimer peripheral base address + */ +static inline void CTIMER_StopTimer(CTIMER_Type *base) +{ + base->TCR &= ~CTIMER_TCR_CEN_MASK; +} + +/*! @}*/ + +/*! + * @brief Reset the counter. + * + * The timer counter and prescale counter are reset on the next positive edge of the APB clock. + * + * @param base Ctimer peripheral base address + */ +static inline void CTIMER_Reset(CTIMER_Type *base) +{ + base->TCR |= CTIMER_TCR_CRST_MASK; + base->TCR &= ~CTIMER_TCR_CRST_MASK; +} + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_CTIMER_H_ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_dma.c b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_dma.c new file mode 100644 index 0000000000..6b7bc594ad --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_dma.c @@ -0,0 +1,1079 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_dma.h" +#if (defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) +#include "fsl_memory.h" +#endif + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.lpc_dma" +#endif + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/*! + * @brief Get instance number for DMA. + * + * @param base DMA peripheral base address. + */ +static uint32_t DMA_GetInstance(DMA_Type *base); + +/*! + * @brief Get virtual channel number. + * + * @param base DMA peripheral base address. + */ +static uint32_t DMA_GetVirtualStartChannel(DMA_Type *base); + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/*! @brief Array to map DMA instance number to base pointer. */ +static DMA_Type *const s_dmaBases[] = DMA_BASE_PTRS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Array to map DMA instance number to clock name. */ +static const clock_ip_name_t s_dmaClockName[] = DMA_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if !(defined(FSL_FEATURE_DMA_HAS_NO_RESET) && FSL_FEATURE_DMA_HAS_NO_RESET) +/*! @brief Pointers to DMA resets for each instance. */ +static const reset_ip_name_t s_dmaResets[] = DMA_RSTS_N; +#endif /*! @brief Array to map DMA instance number to IRQ number. */ +static const IRQn_Type s_dmaIRQNumber[] = DMA_IRQS; + +/*! @brief Pointers to transfer handle for each DMA channel. */ +static dma_handle_t *s_DMAHandle[FSL_FEATURE_DMA_ALL_CHANNELS]; + +/*! @brief DMA driver internal descriptor table */ +#ifdef FSL_FEATURE_DMA0_DESCRIPTOR_ALIGN_SIZE +SDK_ALIGN(static dma_descriptor_t s_dma_descriptor_table0[FSL_FEATURE_DMA_MAX_CHANNELS], + FSL_FEATURE_DMA0_DESCRIPTOR_ALIGN_SIZE); +#else +#if (defined(CPU_MIMXRT685SEVKA_dsp) || defined(CPU_MIMXRT685SFVKB_dsp)) +AT_NONCACHEABLE_SECTION_ALIGN(static dma_descriptor_t s_dma_descriptor_table0[FSL_FEATURE_DMA_MAX_CHANNELS], + FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE); +#else +SDK_ALIGN(static dma_descriptor_t s_dma_descriptor_table0[FSL_FEATURE_DMA_MAX_CHANNELS], + FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE); +#endif /* (defined(CPU_MIMXRT685SEVKA_dsp) || defined(CPU_MIMXRT685SFVKB_dsp)) */ +#endif /* FSL_FEATURE_DMA0_DESCRIPTOR_ALIGN_SIZE */ + +#if defined(DMA1) +#ifdef FSL_FEATURE_DMA1_DESCRIPTOR_ALIGN_SIZE +SDK_ALIGN(static dma_descriptor_t s_dma_descriptor_table1[FSL_FEATURE_DMA_MAX_CHANNELS], + FSL_FEATURE_DMA1_DESCRIPTOR_ALIGN_SIZE); +#else +#if (defined(CPU_MIMXRT685SEVKA_dsp) || defined(CPU_MIMXRT685SFVKB_dsp)) +AT_NONCACHEABLE_SECTION_ALIGN(static dma_descriptor_t s_dma_descriptor_table1[FSL_FEATURE_DMA_MAX_CHANNELS], + FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE); +#else +SDK_ALIGN(static dma_descriptor_t s_dma_descriptor_table1[FSL_FEATURE_DMA_MAX_CHANNELS], + FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE); +#endif /* (defined(CPU_MIMXRT685SEVKA_dsp) || defined(CPU_MIMXRT685SFVKB_dsp)) */ +#endif /* FSL_FEATURE_DMA1_DESCRIPTOR_ALIGN_SIZE */ +static dma_descriptor_t *s_dma_descriptor_table[] = {s_dma_descriptor_table0, s_dma_descriptor_table1}; +#else +static dma_descriptor_t *s_dma_descriptor_table[] = {s_dma_descriptor_table0}; +#endif + +/******************************************************************************* + * Code + ******************************************************************************/ + +static uint32_t DMA_GetInstance(DMA_Type *base) +{ + uint32_t instance; + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_dmaBases); instance++) + { + if (s_dmaBases[instance] == base) + { + break; + } + } + assert(instance < ARRAY_SIZE(s_dmaBases)); + + return instance; +} + +static uint32_t DMA_GetVirtualStartChannel(DMA_Type *base) +{ + uint32_t startChannel = 0, instance = 0; + uint32_t i = 0; + + instance = DMA_GetInstance(base); + + /* Compute start channel */ + for (i = 0; i < instance; i++) + { + startChannel += (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(s_dmaBases[i]); + } + + return startChannel; +} + +/*! + * brief Initializes DMA peripheral. + * + * This function enable the DMA clock, set descriptor table and + * enable DMA peripheral. + * + * param base DMA peripheral base address. + */ +void DMA_Init(DMA_Type *base) +{ + uint32_t instance = DMA_GetInstance(base); +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* enable dma clock gate */ + CLOCK_EnableClock(s_dmaClockName[DMA_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if !(defined(FSL_FEATURE_DMA_HAS_NO_RESET) && FSL_FEATURE_DMA_HAS_NO_RESET) + /* Reset the DMA module */ + RESET_PeripheralReset(s_dmaResets[DMA_GetInstance(base)]); +#endif + /* set descriptor table */ +#if (defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) + base->SRAMBASE = MEMORY_ConvertMemoryMapAddress((uint32_t)s_dma_descriptor_table[instance], kMEMORY_Local2DMA); +#else + base->SRAMBASE = (uint32_t)s_dma_descriptor_table[instance]; +#endif + /* enable dma peripheral */ + base->CTRL |= DMA_CTRL_ENABLE_MASK; +} + +/*! + * brief Deinitializes DMA peripheral. + * + * This function gates the DMA clock. + * + * param base DMA peripheral base address. + */ +void DMA_Deinit(DMA_Type *base) +{ + /* Disable DMA peripheral */ + base->CTRL &= ~(DMA_CTRL_ENABLE_MASK); +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + CLOCK_DisableClock(s_dmaClockName[DMA_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/*! + * brief Set trigger settings of DMA channel. + * deprecated Do not use this function. It has been superceded by @ref DMA_SetChannelConfig. + * + * param base DMA peripheral base address. + * param channel DMA channel number. + * param trigger trigger configuration. + */ +void DMA_ConfigureChannelTrigger(DMA_Type *base, uint32_t channel, dma_channel_trigger_t *trigger) +{ + assert(FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base) != -1); + assert((channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base)) && (NULL != trigger)); + + uint32_t tmpReg = (DMA_CHANNEL_CFG_HWTRIGEN_MASK | DMA_CHANNEL_CFG_TRIGPOL_MASK | DMA_CHANNEL_CFG_TRIGTYPE_MASK | + DMA_CHANNEL_CFG_TRIGBURST_MASK | DMA_CHANNEL_CFG_BURSTPOWER_MASK | + DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK | DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK); + tmpReg = base->CHANNEL[channel].CFG & (~tmpReg); + tmpReg |= (uint32_t)(trigger->type) | (uint32_t)(trigger->burst) | (uint32_t)(trigger->wrap); + base->CHANNEL[channel].CFG = tmpReg; +} + +/*! + * brief Gets the remaining bytes of the current DMA descriptor transfer. + * + * param base DMA peripheral base address. + * param channel DMA channel number. + * return The number of bytes which have not been transferred yet. + */ +uint32_t DMA_GetRemainingBytes(DMA_Type *base, uint32_t channel) +{ + assert(FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base) != -1); + assert(channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base)); + + /* NOTE: when descriptors are chained, ACTIVE bit is set for whole chain. It makes + * impossible to distinguish between: + * - transfer finishes (represented by value '0x3FF') + * - and remaining 1024 bytes to transfer (value 0x3FF) + * for all descriptor in chain, except the last one. + * If you decide to use this function, please use 1023 transfers as maximal value */ + + /* Channel not active (transfer finished) and value is 0x3FF - nothing to transfer */ + if ((!DMA_ChannelIsActive(base, channel)) && + (0x3FFUL == ((base->CHANNEL[channel].XFERCFG & DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK) >> + DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT))) + { + return 0UL; + } + + return ((base->CHANNEL[channel].XFERCFG & DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK) >> + DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT) + + 1UL; +} + +/* Verify and convert dma_xfercfg_t to XFERCFG register */ +static void DMA_SetupXferCFG(dma_xfercfg_t *xfercfg, uint32_t *xfercfg_addr) +{ + assert(xfercfg != NULL); + /* check source increment */ + assert((xfercfg->srcInc <= (uint8_t)kDMA_AddressInterleave4xWidth) && + (xfercfg->dstInc <= (uint8_t)kDMA_AddressInterleave4xWidth)); + /* check data width */ + assert(xfercfg->byteWidth <= (uint8_t)kDMA_Transfer32BitWidth); + /* check transfer count */ + assert(xfercfg->transferCount <= DMA_MAX_TRANSFER_COUNT); + + uint32_t xfer = 0; + + /* set valid flag - descriptor is ready now */ + xfer |= DMA_CHANNEL_XFERCFG_CFGVALID(xfercfg->valid); + /* set reload - allow link to next descriptor */ + xfer |= DMA_CHANNEL_XFERCFG_RELOAD(xfercfg->reload); + /* set swtrig flag - start transfer */ + xfer |= DMA_CHANNEL_XFERCFG_SWTRIG(xfercfg->swtrig); + /* set transfer count */ + xfer |= DMA_CHANNEL_XFERCFG_CLRTRIG(xfercfg->clrtrig); + /* set INTA */ + xfer |= DMA_CHANNEL_XFERCFG_SETINTA(xfercfg->intA); + /* set INTB */ + xfer |= DMA_CHANNEL_XFERCFG_SETINTB(xfercfg->intB); + /* set data width */ + xfer |= DMA_CHANNEL_XFERCFG_WIDTH(xfercfg->byteWidth == 4U ? 2U : xfercfg->byteWidth - 1UL); + /* set source increment value */ + xfer |= DMA_CHANNEL_XFERCFG_SRCINC( + (xfercfg->srcInc == (uint8_t)kDMA_AddressInterleave4xWidth) ? (xfercfg->srcInc - 1UL) : xfercfg->srcInc); + /* set destination increment value */ + xfer |= DMA_CHANNEL_XFERCFG_DSTINC( + (xfercfg->dstInc == (uint8_t)kDMA_AddressInterleave4xWidth) ? (xfercfg->dstInc - 1UL) : xfercfg->dstInc); + /* set transfer count */ + xfer |= DMA_CHANNEL_XFERCFG_XFERCOUNT(xfercfg->transferCount - 1UL); + + /* store xferCFG */ + *xfercfg_addr = xfer; +} + +/*! + * brief setup dma descriptor + * Note: This function do not support configure wrap descriptor. + * param desc DMA descriptor address. + * param xfercfg Transfer configuration for DMA descriptor. + * param srcStartAddr Start address of source address. + * param dstStartAddr Start address of destination address. + * param nextDesc Address of next descriptor in chain. + */ +void DMA_SetupDescriptor( + dma_descriptor_t *desc, uint32_t xfercfg, void *srcStartAddr, void *dstStartAddr, void *nextDesc) +{ + assert((((uint32_t)(uint32_t *)nextDesc) & ((uint32_t)FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE - 1UL)) == 0UL); + +#if (defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) + srcStartAddr = (void *)MEMORY_ConvertMemoryMapAddress((uint32_t)(uint32_t *)srcStartAddr, kMEMORY_Local2DMA); + dstStartAddr = (void *)MEMORY_ConvertMemoryMapAddress((uint32_t)(uint32_t *)dstStartAddr, kMEMORY_Local2DMA); + nextDesc = (void *)MEMORY_ConvertMemoryMapAddress((uint32_t)(uint32_t *)nextDesc, kMEMORY_Local2DMA); +#endif + + uint32_t width = 0, srcInc = 0, dstInc = 0, transferCount = 0; + + width = (xfercfg & DMA_CHANNEL_XFERCFG_WIDTH_MASK) >> DMA_CHANNEL_XFERCFG_WIDTH_SHIFT; + srcInc = (xfercfg & DMA_CHANNEL_XFERCFG_SRCINC_MASK) >> DMA_CHANNEL_XFERCFG_SRCINC_SHIFT; + dstInc = (xfercfg & DMA_CHANNEL_XFERCFG_DSTINC_MASK) >> DMA_CHANNEL_XFERCFG_DSTINC_SHIFT; + transferCount = ((xfercfg & DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK) >> DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT) + 1U; + + /* covert register value to actual value */ + if (width == 2U) + { + width = kDMA_Transfer32BitWidth; + } + else + { + width += 1U; + } + + /* + * Transfers of 16 bit width require an address alignment to a multiple of 2 bytes. + * Transfers of 32 bit width require an address alignment to a multiple of 4 bytes. + * Transfers of 8 bit width can be at any address + */ + if (((NULL != srcStartAddr) && (0UL == ((uint32_t)(uint32_t *)srcStartAddr) % width)) && + ((NULL != dstStartAddr) && (0UL == ((uint32_t)(uint32_t *)dstStartAddr) % width))) + { + if (srcInc == 3U) + { + srcInc = kDMA_AddressInterleave4xWidth; + } + + if (dstInc == 3U) + { + dstInc = kDMA_AddressInterleave4xWidth; + } + + desc->xfercfg = xfercfg; + desc->srcEndAddr = DMA_DESCRIPTOR_END_ADDRESS((uint32_t *)srcStartAddr, srcInc, transferCount * width, width); + desc->dstEndAddr = DMA_DESCRIPTOR_END_ADDRESS((uint32_t *)dstStartAddr, dstInc, transferCount * width, width); + desc->linkToNextDesc = nextDesc; + } + else + { + /* if address alignment not satisfy the requirement, reset the descriptor to make sure DMA generate error */ + desc->xfercfg = 0U; + desc->srcEndAddr = NULL; + desc->dstEndAddr = NULL; + } +} + +/*! + * brief setup dma channel descriptor + * Note: This function support configure wrap descriptor. + * param desc DMA descriptor address. + * param xfercfg Transfer configuration for DMA descriptor. + * param srcStartAddr Start address of source address. + * param dstStartAddr Start address of destination address. + * param nextDesc Address of next descriptor in chain. + * param wrapType burst wrap type. + * param burstSize burst size, reference _dma_burst_size. + */ +void DMA_SetupChannelDescriptor(dma_descriptor_t *desc, + uint32_t xfercfg, + void *srcStartAddr, + void *dstStartAddr, + void *nextDesc, + dma_burst_wrap_t wrapType, + uint32_t burstSize) +{ + assert((((uint32_t)(uint32_t *)nextDesc) & ((uint32_t)FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE - 1UL)) == 0UL); + +#if (defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) + srcStartAddr = (void *)MEMORY_ConvertMemoryMapAddress((uint32_t)(uint32_t *)srcStartAddr, kMEMORY_Local2DMA); + dstStartAddr = (void *)MEMORY_ConvertMemoryMapAddress((uint32_t)(uint32_t *)dstStartAddr, kMEMORY_Local2DMA); + nextDesc = (void *)MEMORY_ConvertMemoryMapAddress((uint32_t)(uint32_t *)nextDesc, kMEMORY_Local2DMA); +#endif + + uint32_t width = 0, srcInc = 0, dstInc = 0, transferCount = 0; + + width = (xfercfg & DMA_CHANNEL_XFERCFG_WIDTH_MASK) >> DMA_CHANNEL_XFERCFG_WIDTH_SHIFT; + srcInc = (xfercfg & DMA_CHANNEL_XFERCFG_SRCINC_MASK) >> DMA_CHANNEL_XFERCFG_SRCINC_SHIFT; + dstInc = (xfercfg & DMA_CHANNEL_XFERCFG_DSTINC_MASK) >> DMA_CHANNEL_XFERCFG_DSTINC_SHIFT; + transferCount = ((xfercfg & DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK) >> DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT) + 1U; + + /* covert register value to actual value */ + if (width == 2U) + { + width = kDMA_Transfer32BitWidth; + } + else + { + width += 1U; + } + + /* + * Transfers of 16 bit width require an address alignment to a multiple of 2 bytes. + * Transfers of 32 bit width require an address alignment to a multiple of 4 bytes. + * Transfers of 8 bit width can be at any address + */ + if (((NULL != srcStartAddr) && (0UL == ((uint32_t)(uint32_t *)srcStartAddr) % width)) && + ((NULL != dstStartAddr) && (0UL == ((uint32_t)(uint32_t *)dstStartAddr) % width))) + { + if (srcInc == 3U) + { + srcInc = kDMA_AddressInterleave4xWidth; + } + + if (dstInc == 3U) + { + dstInc = kDMA_AddressInterleave4xWidth; + } + + desc->xfercfg = xfercfg; + + if (wrapType == kDMA_NoWrap) + { + desc->srcEndAddr = + DMA_DESCRIPTOR_END_ADDRESS((uint32_t *)srcStartAddr, srcInc, transferCount * width, width); + desc->dstEndAddr = + DMA_DESCRIPTOR_END_ADDRESS((uint32_t *)dstStartAddr, dstInc, transferCount * width, width); + } + /* for the wrap transfer, the destination address should be determined by the burstSize/width/interleave size */ + if (wrapType == kDMA_SrcWrap) + { + desc->srcEndAddr = + (uint32_t *)((uint32_t)(uint32_t *)srcStartAddr + ((1UL << burstSize) - 1UL) * width * srcInc); + desc->dstEndAddr = + DMA_DESCRIPTOR_END_ADDRESS((uint32_t *)dstStartAddr, dstInc, transferCount * width, width); + } + if (wrapType == kDMA_DstWrap) + { + desc->srcEndAddr = + DMA_DESCRIPTOR_END_ADDRESS((uint32_t *)srcStartAddr, srcInc, transferCount * width, width); + desc->dstEndAddr = + (uint32_t *)((uint32_t)(uint32_t *)dstStartAddr + ((1UL << burstSize) - 1UL) * width * dstInc); + } + if (wrapType == kDMA_SrcAndDstWrap) + { + desc->srcEndAddr = + (uint32_t *)(((uint32_t)(uint32_t *)srcStartAddr) + ((1UL << burstSize) - 1UL) * width * srcInc); + desc->dstEndAddr = + (uint32_t *)(((uint32_t)(uint32_t *)dstStartAddr) + ((1UL << burstSize) - 1UL) * width * dstInc); + } + + desc->linkToNextDesc = nextDesc; + } + else + { + /* if address alignment not satisfy the requirement, reset the descriptor to make sure DMA generate error */ + desc->xfercfg = 0U; + desc->srcEndAddr = NULL; + desc->dstEndAddr = NULL; + } +} + +/*! + * brief Create application specific DMA descriptor + * to be used in a chain in transfer + * deprecated Do not use this function. It has been superceded by @ref DMA_SetupDescriptor + * param desc DMA descriptor address. + * param xfercfg Transfer configuration for DMA descriptor. + * param srcAddr Address of last item to transmit + * param dstAddr Address of last item to receive. + * param nextDesc Address of next descriptor in chain. + */ +void DMA_CreateDescriptor(dma_descriptor_t *desc, dma_xfercfg_t *xfercfg, void *srcAddr, void *dstAddr, void *nextDesc) +{ + assert((((uint32_t)(uint32_t *)nextDesc) & ((uint32_t)FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE - 1UL)) == 0UL); + assert((NULL != srcAddr) && (0UL == ((uint32_t)(uint32_t *)srcAddr) % xfercfg->byteWidth)); + assert((NULL != dstAddr) && (0UL == ((uint32_t)(uint32_t *)dstAddr) % xfercfg->byteWidth)); + + uint32_t xfercfg_reg = 0; + + DMA_SetupXferCFG(xfercfg, &xfercfg_reg); + + /* Set descriptor structure */ + DMA_SetupDescriptor(desc, xfercfg_reg, srcAddr, dstAddr, nextDesc); +} + +/*! + * brief Abort running transfer by handle. + * + * This function aborts DMA transfer specified by handle. + * + * param handle DMA handle pointer. + */ +void DMA_AbortTransfer(dma_handle_t *handle) +{ + assert(NULL != handle); + + DMA_DisableChannel(handle->base, handle->channel); + while ((DMA_COMMON_CONST_REG_GET(handle->base, handle->channel, BUSY) & + (1UL << DMA_CHANNEL_INDEX(handle->base, handle->channel))) != 0UL) + { + } + DMA_COMMON_REG_GET(handle->base, handle->channel, ABORT) |= 1UL << DMA_CHANNEL_INDEX(handle->base, handle->channel); + DMA_EnableChannel(handle->base, handle->channel); +} + +/*! + * brief Creates the DMA handle. + * + * This function is called if using transaction API for DMA. This function + * initializes the internal state of DMA handle. + * + * param handle DMA handle pointer. The DMA handle stores callback function and + * parameters. + * param base DMA peripheral base address. + * param channel DMA channel number. + */ +void DMA_CreateHandle(dma_handle_t *handle, DMA_Type *base, uint32_t channel) +{ + assert(FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base) != -1); + assert((NULL != handle) && (channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base))); + + uint32_t dmaInstance; + uint32_t startChannel = 0; + /* base address is invalid DMA instance */ + dmaInstance = DMA_GetInstance(base); + startChannel = DMA_GetVirtualStartChannel(base); + + (void)memset(handle, 0, sizeof(*handle)); + handle->base = base; + handle->channel = (uint8_t)channel; + s_DMAHandle[startChannel + channel] = handle; + /* Enable NVIC interrupt */ + (void)EnableIRQ(s_dmaIRQNumber[dmaInstance]); + /* Enable channel interrupt */ + DMA_EnableChannelInterrupts(handle->base, channel); +} + +/*! + * brief Installs a callback function for the DMA transfer. + * + * This callback is called in DMA IRQ handler. Use the callback to do something after + * the current major loop transfer completes. + * + * param handle DMA handle pointer. + * param callback DMA callback function pointer. + * param userData Parameter for callback function. + */ +void DMA_SetCallback(dma_handle_t *handle, dma_callback callback, void *userData) +{ + assert(handle != NULL); + + handle->callback = callback; + handle->userData = userData; +} + +/*! + * brief Prepares the DMA transfer structure. + * deprecated Do not use this function. It has been superceded by @ref DMA_PrepareChannelTransfer and + * DMA_PrepareChannelXfer. + * This function prepares the transfer configuration structure according to the user input. + * + * param config The user configuration structure of type dma_transfer_t. + * param srcAddr DMA transfer source address. + * param dstAddr DMA transfer destination address. + * param byteWidth DMA transfer destination address width(bytes). + * param transferBytes DMA transfer bytes to be transferred. + * param type DMA transfer type. + * param nextDesc Chain custom descriptor to transfer. + * note The data address and the data width must be consistent. For example, if the SRC + * is 4 bytes, so the source address must be 4 bytes aligned, or it shall result in + * source address error(SAE). + */ +void DMA_PrepareTransfer(dma_transfer_config_t *config, + void *srcAddr, + void *dstAddr, + uint32_t byteWidth, + uint32_t transferBytes, + dma_transfer_type_t type, + void *nextDesc) +{ + uint32_t xfer_count; + assert((NULL != config) && (NULL != srcAddr) && (NULL != dstAddr)); + assert((byteWidth == 1UL) || (byteWidth == 2UL) || (byteWidth == 4UL)); + assert((((uint32_t)(uint32_t *)nextDesc) & ((uint32_t)FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE - 1UL)) == 0UL); + + /* check max */ + xfer_count = transferBytes / byteWidth; + assert((xfer_count <= DMA_MAX_TRANSFER_COUNT) && (0UL == transferBytes % byteWidth)); + + (void)memset(config, 0, sizeof(*config)); + + if (type == kDMA_MemoryToMemory) + { + config->xfercfg.srcInc = 1; + config->xfercfg.dstInc = 1; + config->isPeriph = false; + } + + else if (type == kDMA_PeripheralToMemory) + { + /* Peripheral register - source doesn't increment */ + config->xfercfg.srcInc = 0; + config->xfercfg.dstInc = 1; + config->isPeriph = true; + } + else if (type == kDMA_MemoryToPeripheral) + { + /* Peripheral register - destination doesn't increment */ + config->xfercfg.srcInc = 1; + config->xfercfg.dstInc = 0; + config->isPeriph = true; + } + /* kDMA_StaticToStatic */ + else + { + config->xfercfg.srcInc = 0; + config->xfercfg.dstInc = 0; + config->isPeriph = true; + } + + config->dstAddr = (uint8_t *)dstAddr; + config->srcAddr = (uint8_t *)srcAddr; + config->nextDesc = (uint8_t *)nextDesc; + config->xfercfg.transferCount = (uint16_t)xfer_count; + config->xfercfg.byteWidth = (uint8_t)byteWidth; + config->xfercfg.intA = true; + config->xfercfg.reload = nextDesc != NULL; + config->xfercfg.valid = true; +} + +/*! + * brief set channel config. + * + * This function provide a interface to configure channel configuration reisters. + * + * param base DMA base address. + * param channel DMA channel number. + * param config channel configurations structure. + */ +void DMA_SetChannelConfig(DMA_Type *base, uint32_t channel, dma_channel_trigger_t *trigger, bool isPeriph) +{ + assert(channel < (uint32_t)FSL_FEATURE_DMA_MAX_CHANNELS); + + uint32_t tmpReg = DMA_CHANNEL_CFG_PERIPHREQEN_MASK; + + if (trigger != NULL) + { + tmpReg |= DMA_CHANNEL_CFG_HWTRIGEN_MASK | DMA_CHANNEL_CFG_TRIGPOL_MASK | DMA_CHANNEL_CFG_TRIGTYPE_MASK | + DMA_CHANNEL_CFG_TRIGBURST_MASK | DMA_CHANNEL_CFG_BURSTPOWER_MASK | DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK | + DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK; + } + + tmpReg = base->CHANNEL[channel].CFG & (~tmpReg); + + if (trigger != NULL) + { + tmpReg |= (uint32_t)(trigger->type) | (uint32_t)(trigger->burst) | (uint32_t)(trigger->wrap); + } + + tmpReg |= DMA_CHANNEL_CFG_PERIPHREQEN(isPeriph); + + base->CHANNEL[channel].CFG = tmpReg; +} + +/*! + * brief Prepare channel transfer configurations. + * + * This function used to prepare channel transfer configurations. + * + * param config Pointer to DMA channel transfer configuration structure. + * param srcStartAddr source start address. + * param dstStartAddr destination start address. + * param xferCfg xfer configuration, user can reference DMA_CHANNEL_XFER about to how to get xferCfg value. + * param type transfer type. + * param trigger DMA channel trigger configurations. + * param nextDesc address of next descriptor. + */ +void DMA_PrepareChannelTransfer(dma_channel_config_t *config, + void *srcStartAddr, + void *dstStartAddr, + uint32_t xferCfg, + dma_transfer_type_t type, + dma_channel_trigger_t *trigger, + void *nextDesc) +{ + assert((NULL != config) && (NULL != srcStartAddr) && (NULL != dstStartAddr)); + assert((((uint32_t)(uint32_t *)nextDesc) & ((uint32_t)FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE - 1UL)) == 0UL); + + /* check max */ + (void)memset(config, 0, sizeof(*config)); + + if (type == kDMA_MemoryToMemory) + { + config->isPeriph = false; + } + else if (type == kDMA_PeripheralToMemory) + { + config->isPeriph = true; + } + else if (type == kDMA_MemoryToPeripheral) + { + config->isPeriph = true; + } + /* kDMA_StaticToStatic */ + else + { + config->isPeriph = true; + } + + config->dstStartAddr = (uint8_t *)dstStartAddr; + config->srcStartAddr = (uint8_t *)srcStartAddr; + config->nextDesc = (uint8_t *)nextDesc; + config->trigger = trigger; + config->xferCfg = xferCfg; +} + +/*! + * brief load channel transfer decriptor. + * + * This function can be used to load desscriptor to driver internal channel descriptor that is used to start DMA + * transfer, the head descriptor table is defined in DMA driver, it is useful for the case: + * 1. for the polling transfer, application can allocate a local descriptor memory table to prepare a descriptor firstly + * and then call this api to load the configured descriptor to driver descriptor table. code DMA_Init(DMA0); + * DMA_EnableChannel(DMA0, DEMO_DMA_CHANNEL); + * DMA_SetupDescriptor(desc, xferCfg, s_srcBuffer, &s_destBuffer[0], NULL); + * DMA_LoadChannelDescriptor(DMA0, DEMO_DMA_CHANNEL, (dma_descriptor_t *)desc); + * DMA_DoChannelSoftwareTrigger(DMA0, DEMO_DMA_CHANNEL); + * while(DMA_ChannelIsBusy(DMA0, DEMO_DMA_CHANNEL)) + * {} + * endcode + * + * param base DMA base address. + * param channel DMA channel. + * param descriptor configured DMA descriptor. + */ +void DMA_LoadChannelDescriptor(DMA_Type *base, uint32_t channel, dma_descriptor_t *descriptor) +{ + assert(NULL != descriptor); + assert(FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base) != -1); + assert(channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base)); + + uint32_t instance = DMA_GetInstance(base); + dma_descriptor_t *channelDescriptor = (dma_descriptor_t *)(&s_dma_descriptor_table[instance][channel]); + + channelDescriptor->xfercfg = descriptor->xfercfg; + channelDescriptor->srcEndAddr = descriptor->srcEndAddr; + channelDescriptor->dstEndAddr = descriptor->dstEndAddr; + channelDescriptor->linkToNextDesc = descriptor->linkToNextDesc; + + /* Set channel XFERCFG register according first channel descriptor. */ + base->CHANNEL[channel].XFERCFG = descriptor->xfercfg; +} + +/*! + * brief Install DMA descriptor memory. + * + * This function used to register DMA descriptor memory for linked transfer, a typical case is ping pong + * transfer which will request more than one DMA descriptor memory space, althrough current DMA driver has + * a default DMA descriptor buffer, but it support one DMA descriptor for one channel only. + * User should be take care about the address of DMA descriptor pool which required align with 512BYTE. + * + * param handle Pointer to DMA channel transfer handle. + * param addr DMA descriptor address + * param num DMA descriptor number. + */ +void DMA_InstallDescriptorMemory(DMA_Type *base, void *addr) +{ + assert(addr != NULL); + +#if defined FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZEn + assert((((uint32_t)(uint32_t *)addr) & ((uint32_t)FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZEn(base) - 1UL)) == 0U); +#else + assert((((uint32_t)(uint32_t *)addr) & ((uint32_t)FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE - 1UL)) == 0U); +#endif + /* reconfigure the DMA descriptor base address */ + base->SRAMBASE = (uint32_t)(uint32_t *)addr; +} + +/*! + * brief Submit channel transfer paramter directly. + * + * This function used to configue channel head descriptor that is used to start DMA transfer, the head descriptor table + * is defined in DMA driver, it is useful for the case: + * 1. for the single transfer, application doesn't need to allocate descriptor table, the head descriptor can be used + for it. + * code + DMA_SetChannelConfig(base, channel, trigger, isPeriph); + DMA_CreateHandle(handle, base, channel) + DMA_SubmitChannelTransferParameter(handle, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, + bytes), srcStartAddr, dstStartAddr, NULL); + DMA_StartTransfer(handle) + * endcode + * + * 2. for the linked transfer, application should responsible for link descriptor, for example, if 4 transfer is + required, then application should prepare + * three descriptor table with macro , the head descriptor in driver can be used for the first transfer descriptor. + * code + define link descriptor table in application with macro + DMA_ALLOCATE_LINK_DESCRIPTOR(nextDesc[3]); + + DMA_SetupDescriptor(nextDesc0, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), + srcStartAddr, dstStartAddr, nextDesc1); + DMA_SetupDescriptor(nextDesc1, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), + srcStartAddr, dstStartAddr, nextDesc2); + DMA_SetupDescriptor(nextDesc2, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), + srcStartAddr, dstStartAddr, NULL); + DMA_SetChannelConfig(base, channel, trigger, isPeriph); + DMA_CreateHandle(handle, base, channel) + DMA_SubmitChannelTransferParameter(handle, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, + bytes), srcStartAddr, dstStartAddr, nextDesc0); + DMA_StartTransfer(handle); + * endcode + * + * param handle Pointer to DMA handle. + * param xferCfg xfer configuration, user can reference DMA_CHANNEL_XFER about to how to get xferCfg value. + * param srcStartAddr source start address. + * param dstStartAddr destination start address. + * param nextDesc address of next descriptor. + */ +void DMA_SubmitChannelTransferParameter( + dma_handle_t *handle, uint32_t xferCfg, void *srcStartAddr, void *dstStartAddr, void *nextDesc) +{ + assert((NULL != srcStartAddr) && (NULL != dstStartAddr)); + assert(FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(handle->base) != -1); + assert(handle->channel < (uint8_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(handle->base)); + + uint32_t instance = DMA_GetInstance(handle->base); + dma_descriptor_t *descriptor = (dma_descriptor_t *)(&s_dma_descriptor_table[instance][handle->channel]); + + DMA_SetupDescriptor(descriptor, xferCfg, srcStartAddr, dstStartAddr, nextDesc); + + /* Set channel XFERCFG register according first channel descriptor. */ + handle->base->CHANNEL[handle->channel].XFERCFG = xferCfg; +} + +/*! + * brief Submit channel descriptor. + * + * This function used to configue channel head descriptor that is used to start DMA transfer, the head descriptor table + is defined in + * DMA driver, this functiono is typical for the ping pong case: + * + * 1. for the ping pong case, application should responsible for the descriptor, for example, application should + * prepare two descriptor table with macro. + * code + define link descriptor table in application with macro + DMA_ALLOCATE_LINK_DESCRIPTOR(nextDesc[2]); + + DMA_SetupDescriptor(nextDesc0, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), + srcStartAddr, dstStartAddr, nextDesc1); + DMA_SetupDescriptor(nextDesc1, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), + srcStartAddr, dstStartAddr, nextDesc0); + DMA_SetChannelConfig(base, channel, trigger, isPeriph); + DMA_CreateHandle(handle, base, channel) + DMA_SubmitChannelDescriptor(handle, nextDesc0); + DMA_StartTransfer(handle); + * endcode + * + * param handle Pointer to DMA handle. + * param descriptor descriptor to submit. + */ +void DMA_SubmitChannelDescriptor(dma_handle_t *handle, dma_descriptor_t *descriptor) +{ + assert((NULL != handle) && (NULL != descriptor)); + + DMA_LoadChannelDescriptor(handle->base, handle->channel, descriptor); +} + +/*! + * brief Submits the DMA channel transfer request. + * + * This function submits the DMA transfer request according to the transfer configuration structure. + * If the user submits the transfer request repeatedly, this function packs an unprocessed request as + * a TCD and enables scatter/gather feature to process it in the next time. + * It is used for the case: + * 1. for the single transfer, application doesn't need to allocate descriptor table, the head descriptor can be used + for it. + * code + DMA_CreateHandle(handle, base, channel) + DMA_PrepareChannelTransfer(config,srcStartAddr,dstStartAddr,xferCfg,type,trigger,NULL); + DMA_SubmitChannelTransfer(handle, config) + DMA_StartTransfer(handle) + * endcode + * + * 2. for the linked transfer, application should responsible for link descriptor, for example, if 4 transfer is + required, then application should prepare + * three descriptor table with macro , the head descriptor in driver can be used for the first transfer descriptor. + * code + define link descriptor table in application with macro + DMA_ALLOCATE_LINK_DESCRIPTOR(nextDesc); + + DMA_SetupDescriptor(nextDesc0, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), + srcStartAddr, dstStartAddr, nextDesc1); + DMA_SetupDescriptor(nextDesc1, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), + srcStartAddr, dstStartAddr, nextDesc2); + DMA_SetupDescriptor(nextDesc2, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), + srcStartAddr, dstStartAddr, NULL); + DMA_CreateHandle(handle, base, channel) + DMA_PrepareChannelTransfer(config,srcStartAddr,dstStartAddr,xferCfg,type,trigger,nextDesc0); + DMA_SubmitChannelTransfer(handle, config) + DMA_StartTransfer(handle) + * endcode + * + * 3. for the ping pong case, application should responsible for link descriptor, for example, application should + prepare + * two descriptor table with macro , the head descriptor in driver can be used for the first transfer descriptor. + * code + define link descriptor table in application with macro + DMA_ALLOCATE_LINK_DESCRIPTOR(nextDesc); + + DMA_SetupDescriptor(nextDesc0, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), + srcStartAddr, dstStartAddr, nextDesc1); + DMA_SetupDescriptor(nextDesc1, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), + srcStartAddr, dstStartAddr, nextDesc0); + DMA_CreateHandle(handle, base, channel) + DMA_PrepareChannelTransfer(config,srcStartAddr,dstStartAddr,xferCfg,type,trigger,nextDesc0); + DMA_SubmitChannelTransfer(handle, config) + DMA_StartTransfer(handle) + * endcode + * param handle DMA handle pointer. + * param config Pointer to DMA transfer configuration structure. + * retval kStatus_DMA_Success It means submit transfer request succeed. + * retval kStatus_DMA_QueueFull It means TCD queue is full. Submit transfer request is not allowed. + * retval kStatus_DMA_Busy It means the given channel is busy, need to submit request later. + */ +status_t DMA_SubmitChannelTransfer(dma_handle_t *handle, dma_channel_config_t *config) +{ + assert((NULL != handle) && (NULL != config)); + assert(FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(handle->base) != -1); + assert(handle->channel < (uint8_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(handle->base)); + uint32_t instance = DMA_GetInstance(handle->base); + dma_descriptor_t *descriptor = (dma_descriptor_t *)(&s_dma_descriptor_table[instance][handle->channel]); + + /* Previous transfer has not finished */ + if (DMA_ChannelIsActive(handle->base, handle->channel)) + { + return kStatus_DMA_Busy; + } + + /* setup channgel trigger configurations */ + DMA_SetChannelConfig(handle->base, handle->channel, config->trigger, config->isPeriph); + + DMA_SetupChannelDescriptor( + descriptor, config->xferCfg, config->srcStartAddr, config->dstStartAddr, config->nextDesc, + config->trigger == NULL ? kDMA_NoWrap : config->trigger->wrap, + (config->trigger == NULL ? (uint32_t)kDMA_BurstSize1 : + ((uint32_t)config->trigger->burst & (DMA_CHANNEL_CFG_BURSTPOWER_MASK)) >> + DMA_CHANNEL_CFG_BURSTPOWER_SHIFT)); + + /* Set channel XFERCFG register according first channel descriptor. */ + handle->base->CHANNEL[handle->channel].XFERCFG = config->xferCfg; + + return kStatus_Success; +} + +/*! + * brief Submits the DMA transfer request. + * deprecated Do not use this function. It has been superceded by @ref DMA_SubmitChannelTransfer. + * + * This function submits the DMA transfer request according to the transfer configuration structure. + * If the user submits the transfer request repeatedly, this function packs an unprocessed request as + * a TCD and enables scatter/gather feature to process it in the next time. + * + * param handle DMA handle pointer. + * param config Pointer to DMA transfer configuration structure. + * retval kStatus_DMA_Success It means submit transfer request succeed. + * retval kStatus_DMA_QueueFull It means TCD queue is full. Submit transfer request is not allowed. + * retval kStatus_DMA_Busy It means the given channel is busy, need to submit request later. + */ +status_t DMA_SubmitTransfer(dma_handle_t *handle, dma_transfer_config_t *config) +{ + assert((NULL != handle) && (NULL != config)); + assert(FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(handle->base) != -1); + assert(handle->channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(handle->base)); + + uint32_t instance = DMA_GetInstance(handle->base); + dma_descriptor_t *descriptor = (dma_descriptor_t *)(&s_dma_descriptor_table[instance][handle->channel]); + + /* Previous transfer has not finished */ + if (DMA_ChannelIsActive(handle->base, handle->channel)) + { + return kStatus_DMA_Busy; + } + + /* enable/disable peripheral request */ + if (config->isPeriph) + { + DMA_EnableChannelPeriphRq(handle->base, handle->channel); + } + else + { + DMA_DisableChannelPeriphRq(handle->base, handle->channel); + } + + DMA_CreateDescriptor(descriptor, &config->xfercfg, config->srcAddr, config->dstAddr, config->nextDesc); + /* Set channel XFERCFG register according first channel descriptor. */ + handle->base->CHANNEL[handle->channel].XFERCFG = descriptor->xfercfg; + + return kStatus_Success; +} + +/*! + * brief DMA start transfer. + * + * This function enables the channel request. User can call this function after submitting the transfer request + * It will trigger transfer start with software trigger only when hardware trigger is not used. + * + * param handle DMA handle pointer. + */ +void DMA_StartTransfer(dma_handle_t *handle) +{ + assert(NULL != handle); + assert(FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(handle->base) != -1); + + uint32_t channel = handle->channel; + assert(channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(handle->base)); + + /* enable channel */ + DMA_EnableChannel(handle->base, channel); + + /* Do software trigger only when HW trigger is not enabled. */ + if ((handle->base->CHANNEL[handle->channel].CFG & DMA_CHANNEL_CFG_HWTRIGEN_MASK) == 0U) + { + handle->base->CHANNEL[channel].XFERCFG |= DMA_CHANNEL_XFERCFG_SWTRIG_MASK; + } +} + +void DMA_IRQHandle(DMA_Type *base) +{ + dma_handle_t *handle; + uint8_t channel_index; + uint32_t startChannel = DMA_GetVirtualStartChannel(base); + uint32_t i = 0; + bool intEnabled = false, intA = false, intB = false; + + /* Find channels that have completed transfer */ + for (i = 0; i < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base); i++) + { + handle = s_DMAHandle[i + startChannel]; + /* Handle is not present */ + if (NULL == handle) + { + continue; + } + channel_index = DMA_CHANNEL_INDEX(base, handle->channel); + /* Channel uses INTA flag */ + intEnabled = ((DMA_COMMON_REG_GET(handle->base, handle->channel, INTENSET) & (1UL << channel_index)) != 0UL); + intA = ((DMA_COMMON_REG_GET(handle->base, handle->channel, INTA) & (1UL << channel_index)) != 0UL); + if (intEnabled && intA) + { + /* Clear INTA flag */ + DMA_COMMON_REG_SET(handle->base, handle->channel, INTA, (1UL << channel_index)); + if (handle->callback != NULL) + { + (handle->callback)(handle, handle->userData, true, kDMA_IntA); + } + } + + intB = ((DMA_COMMON_REG_GET(handle->base, handle->channel, INTB) & (1UL << channel_index)) != 0UL); + /* Channel uses INTB flag */ + if (intEnabled && intB) + { + /* Clear INTB flag */ + DMA_COMMON_REG_SET(handle->base, handle->channel, INTB, (1UL << channel_index)); + if (handle->callback != NULL) + { + (handle->callback)(handle, handle->userData, true, kDMA_IntB); + } + } + /* Error flag */ + if ((DMA_COMMON_REG_GET(handle->base, handle->channel, ERRINT) & (1UL << channel_index)) != 0UL) + { + /* Clear error flag */ + DMA_COMMON_REG_SET(handle->base, handle->channel, ERRINT, (1UL << channel_index)); + if (handle->callback != NULL) + { + (handle->callback)(handle, handle->userData, false, kDMA_IntError); + } + } + } +} + +void DMA0_DriverIRQHandler(void); +void DMA0_DriverIRQHandler(void) +{ + DMA_IRQHandle(DMA0); + SDK_ISR_EXIT_BARRIER; +} + +#if defined(DMA1) +void DMA1_DriverIRQHandler(void); +void DMA1_DriverIRQHandler(void) +{ + DMA_IRQHandle(DMA1); + SDK_ISR_EXIT_BARRIER; +} +#endif diff --git a/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_dma.h b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_dma.h new file mode 100644 index 0000000000..0e857752e5 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_dma.h @@ -0,0 +1,892 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_DMA_H_ +#define _FSL_DMA_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup dma + * @{ + */ + +/*! @file */ +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief DMA driver version */ +#define FSL_DMA_DRIVER_VERSION (MAKE_VERSION(2, 4, 4)) /*!< Version 2.4.4. */ +/*@}*/ + +/*! @brief DMA max transfer size */ +#define DMA_MAX_TRANSFER_COUNT 0x400U +/*! @brief DMA channel numbers */ +#if defined FSL_FEATURE_DMA_NUMBER_OF_CHANNELS +#define FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(x) FSL_FEATURE_DMA_NUMBER_OF_CHANNELS +#define FSL_FEATURE_DMA_MAX_CHANNELS FSL_FEATURE_DMA_NUMBER_OF_CHANNELS +#define FSL_FEATURE_DMA_ALL_CHANNELS (FSL_FEATURE_DMA_NUMBER_OF_CHANNELS * FSL_FEATURE_SOC_DMA_COUNT) +#endif +/*! @brief DMA head link descriptor table align size */ +#define FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE (16U) +/*! @brief DMA head descriptor table allocate macro + * To simplify user interface, this macro will help allocate descriptor memory, + * user just need to provide the name and the number for the allocate descriptor. + * + * @param name Allocate decriptor name. + * @param number Number of descriptor to be allocated. + */ +#define DMA_ALLOCATE_HEAD_DESCRIPTORS(name, number) \ + SDK_ALIGN(dma_descriptor_t name[number], FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE) +/*! @brief DMA head descriptor table allocate macro at noncacheable section + * To simplify user interface, this macro will help allocate descriptor memory at noncacheable section, + * user just need to provide the name and the number for the allocate descriptor. + * + * @param name Allocate decriptor name. + * @param number Number of descriptor to be allocated. + */ +#define DMA_ALLOCATE_HEAD_DESCRIPTORS_AT_NONCACHEABLE(name, number) \ + AT_NONCACHEABLE_SECTION_ALIGN(dma_descriptor_t name[number], FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE) +/*! @brief DMA link descriptor table allocate macro + * To simplify user interface, this macro will help allocate descriptor memory, + * user just need to provide the name and the number for the allocate descriptor. + * + * @param name Allocate decriptor name. + * @param number Number of descriptor to be allocated. + */ +#define DMA_ALLOCATE_LINK_DESCRIPTORS(name, number) \ + SDK_ALIGN(dma_descriptor_t name[number], FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE) +/*! @brief DMA link descriptor table allocate macro at noncacheable section + * To simplify user interface, this macro will help allocate descriptor memory at noncacheable section, + * user just need to provide the name and the number for the allocate descriptor. + * + * @param name Allocate decriptor name. + * @param number Number of descriptor to be allocated. + */ +#define DMA_ALLOCATE_LINK_DESCRIPTORS_AT_NONCACHEABLE(name, number) \ + AT_NONCACHEABLE_SECTION_ALIGN(dma_descriptor_t name[number], FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE) +/*! @brief DMA transfer buffer address need to align with the transfer width */ +#define DMA_ALLOCATE_DATA_TRANSFER_BUFFER(name, width) SDK_ALIGN(name, width) +/* Channel group consists of 32 channels. channel_group = 0 */ +#define DMA_CHANNEL_GROUP(channel) (((uint8_t)(channel)) >> 5U) +/* Channel index in channel group. channel_index = (channel % (channel number per instance)) */ +#define DMA_CHANNEL_INDEX(base, channel) (((uint8_t)(channel)) & 0x1FU) +/*! @brief DMA linked descriptor address algin size */ +#define DMA_COMMON_REG_GET(base, channel, reg) \ + (((volatile uint32_t *)(&((base)->COMMON[0].reg)))[DMA_CHANNEL_GROUP(channel)]) +#define DMA_COMMON_CONST_REG_GET(base, channel, reg) \ + (((volatile const uint32_t *)(&((base)->COMMON[0].reg)))[DMA_CHANNEL_GROUP(channel)]) +#define DMA_COMMON_REG_SET(base, channel, reg, value) \ + (((volatile uint32_t *)(&((base)->COMMON[0].reg)))[DMA_CHANNEL_GROUP(channel)] = (value)) + +/*! @brief DMA descriptor end address calculate + * @param start start address + * @param inc address interleave size + * @param bytes transfer bytes + * @param width transfer width + */ +#define DMA_DESCRIPTOR_END_ADDRESS(start, inc, bytes, width) \ + ((uint32_t *)((uint32_t)(start) + (inc) * (bytes) - (inc) * (width))) + +/*! @brief DMA channel transfer configurations macro + * @param reload true is reload link descriptor after current exhaust, false is not + * @param clrTrig true is clear trigger status, wait software trigger, false is not + * @param intA enable interruptA + * @param intB enable interruptB + * @param width transfer width + * @param srcInc source address interleave size + * @param dstInc destination address interleave size + * @param bytes transfer bytes + */ +#define DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes) \ + DMA_CHANNEL_XFERCFG_CFGVALID_MASK | DMA_CHANNEL_XFERCFG_RELOAD(reload) | DMA_CHANNEL_XFERCFG_CLRTRIG(clrTrig) | \ + DMA_CHANNEL_XFERCFG_SETINTA(intA) | DMA_CHANNEL_XFERCFG_SETINTB(intB) | \ + DMA_CHANNEL_XFERCFG_WIDTH(width == 4UL ? 2UL : (width - 1UL)) | \ + DMA_CHANNEL_XFERCFG_SRCINC(srcInc == (uint32_t)kDMA_AddressInterleave4xWidth ? (srcInc - 1UL) : srcInc) | \ + DMA_CHANNEL_XFERCFG_DSTINC(dstInc == (uint32_t)kDMA_AddressInterleave4xWidth ? (dstInc - 1UL) : dstInc) | \ + DMA_CHANNEL_XFERCFG_XFERCOUNT(bytes / width - 1UL) + +/*! @brief _dma_transfer_status DMA transfer status */ +enum +{ + kStatus_DMA_Busy = MAKE_STATUS(kStatusGroup_DMA, 0), /*!< Channel is busy and can't handle the + transfer request. */ +}; + +/*! @brief _dma_addr_interleave_size dma address interleave size */ +enum +{ + kDMA_AddressInterleave0xWidth = 0U, /*!< dma source/destination address no interleave */ + kDMA_AddressInterleave1xWidth = 1U, /*!< dma source/destination address interleave 1xwidth */ + kDMA_AddressInterleave2xWidth = 2U, /*!< dma source/destination address interleave 2xwidth */ + kDMA_AddressInterleave4xWidth = 4U, /*!< dma source/destination address interleave 3xwidth */ +}; + +/*! @brief _dma_transfer_width dma transfer width */ +enum +{ + kDMA_Transfer8BitWidth = 1U, /*!< dma channel transfer bit width is 8 bit */ + kDMA_Transfer16BitWidth = 2U, /*!< dma channel transfer bit width is 16 bit */ + kDMA_Transfer32BitWidth = 4U, /*!< dma channel transfer bit width is 32 bit */ +}; + +/*! @brief DMA descriptor structure */ +typedef struct _dma_descriptor +{ + volatile uint32_t xfercfg; /*!< Transfer configuration */ + void *srcEndAddr; /*!< Last source address of DMA transfer */ + void *dstEndAddr; /*!< Last destination address of DMA transfer */ + void *linkToNextDesc; /*!< Address of next DMA descriptor in chain */ +} dma_descriptor_t; + +/*! @brief DMA transfer configuration */ +typedef struct _dma_xfercfg +{ + bool valid; /*!< Descriptor is ready to transfer */ + bool reload; /*!< Reload channel configuration register after + current descriptor is exhausted */ + bool swtrig; /*!< Perform software trigger. Transfer if fired + when 'valid' is set */ + bool clrtrig; /*!< Clear trigger */ + bool intA; /*!< Raises IRQ when transfer is done and set IRQA status register flag */ + bool intB; /*!< Raises IRQ when transfer is done and set IRQB status register flag */ + uint8_t byteWidth; /*!< Byte width of data to transfer */ + uint8_t srcInc; /*!< Increment source address by 'srcInc' x 'byteWidth' */ + uint8_t dstInc; /*!< Increment destination address by 'dstInc' x 'byteWidth' */ + uint16_t transferCount; /*!< Number of transfers */ +} dma_xfercfg_t; + +/*! @brief DMA channel priority */ +typedef enum _dma_priority +{ + kDMA_ChannelPriority0 = 0, /*!< Highest channel priority - priority 0 */ + kDMA_ChannelPriority1, /*!< Channel priority 1 */ + kDMA_ChannelPriority2, /*!< Channel priority 2 */ + kDMA_ChannelPriority3, /*!< Channel priority 3 */ + kDMA_ChannelPriority4, /*!< Channel priority 4 */ + kDMA_ChannelPriority5, /*!< Channel priority 5 */ + kDMA_ChannelPriority6, /*!< Channel priority 6 */ + kDMA_ChannelPriority7, /*!< Lowest channel priority - priority 7 */ +} dma_priority_t; + +/*! @brief DMA interrupt flags */ +typedef enum _dma_int +{ + kDMA_IntA, /*!< DMA interrupt flag A */ + kDMA_IntB, /*!< DMA interrupt flag B */ + kDMA_IntError, /*!< DMA interrupt flag error */ +} dma_irq_t; + +/*! @brief DMA trigger type*/ +typedef enum _dma_trigger_type +{ + kDMA_NoTrigger = 0, /*!< Trigger is disabled */ + kDMA_LowLevelTrigger = DMA_CHANNEL_CFG_HWTRIGEN(1) | DMA_CHANNEL_CFG_TRIGTYPE(1), /*!< Low level active trigger */ + kDMA_HighLevelTrigger = DMA_CHANNEL_CFG_HWTRIGEN(1) | DMA_CHANNEL_CFG_TRIGTYPE(1) | + DMA_CHANNEL_CFG_TRIGPOL(1), /*!< High level active trigger */ + kDMA_FallingEdgeTrigger = DMA_CHANNEL_CFG_HWTRIGEN(1), /*!< Falling edge active trigger */ + kDMA_RisingEdgeTrigger = + DMA_CHANNEL_CFG_HWTRIGEN(1) | DMA_CHANNEL_CFG_TRIGPOL(1), /*!< Rising edge active trigger */ +} dma_trigger_type_t; + +/*! @brief _dma_burst_size DMA burst size*/ +enum +{ + kDMA_BurstSize1 = 0U, /*!< burst size 1 transfer */ + kDMA_BurstSize2 = 1U, /*!< burst size 2 transfer */ + kDMA_BurstSize4 = 2U, /*!< burst size 4 transfer */ + kDMA_BurstSize8 = 3U, /*!< burst size 8 transfer */ + kDMA_BurstSize16 = 4U, /*!< burst size 16 transfer */ + kDMA_BurstSize32 = 5U, /*!< burst size 32 transfer */ + kDMA_BurstSize64 = 6U, /*!< burst size 64 transfer */ + kDMA_BurstSize128 = 7U, /*!< burst size 128 transfer */ + kDMA_BurstSize256 = 8U, /*!< burst size 256 transfer */ + kDMA_BurstSize512 = 9U, /*!< burst size 512 transfer */ + kDMA_BurstSize1024 = 10U, /*!< burst size 1024 transfer */ +}; + +/*! @brief DMA trigger burst */ +typedef enum _dma_trigger_burst +{ + kDMA_SingleTransfer = 0, /*!< Single transfer */ + kDMA_LevelBurstTransfer = DMA_CHANNEL_CFG_TRIGBURST(1), /*!< Burst transfer driven by level trigger */ + kDMA_EdgeBurstTransfer1 = DMA_CHANNEL_CFG_TRIGBURST(1), /*!< Perform 1 transfer by edge trigger */ + kDMA_EdgeBurstTransfer2 = + DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(1), /*!< Perform 2 transfers by edge trigger */ + kDMA_EdgeBurstTransfer4 = + DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(2), /*!< Perform 4 transfers by edge trigger */ + kDMA_EdgeBurstTransfer8 = + DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(3), /*!< Perform 8 transfers by edge trigger */ + kDMA_EdgeBurstTransfer16 = + DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(4), /*!< Perform 16 transfers by edge trigger */ + kDMA_EdgeBurstTransfer32 = + DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(5), /*!< Perform 32 transfers by edge trigger */ + kDMA_EdgeBurstTransfer64 = + DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(6), /*!< Perform 64 transfers by edge trigger */ + kDMA_EdgeBurstTransfer128 = + DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(7), /*!< Perform 128 transfers by edge trigger */ + kDMA_EdgeBurstTransfer256 = + DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(8), /*!< Perform 256 transfers by edge trigger */ + kDMA_EdgeBurstTransfer512 = + DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(9), /*!< Perform 512 transfers by edge trigger */ + kDMA_EdgeBurstTransfer1024 = + DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(10), /*!< Perform 1024 transfers by edge trigger */ +} dma_trigger_burst_t; + +/*! @brief DMA burst wrapping */ +typedef enum _dma_burst_wrap +{ + kDMA_NoWrap = 0, /*!< Wrapping is disabled */ + kDMA_SrcWrap = DMA_CHANNEL_CFG_SRCBURSTWRAP(1), /*!< Wrapping is enabled for source */ + kDMA_DstWrap = DMA_CHANNEL_CFG_DSTBURSTWRAP(1), /*!< Wrapping is enabled for destination */ + kDMA_SrcAndDstWrap = DMA_CHANNEL_CFG_SRCBURSTWRAP(1) | + DMA_CHANNEL_CFG_DSTBURSTWRAP(1), /*!< Wrapping is enabled for source and destination */ +} dma_burst_wrap_t; + +/*! @brief DMA transfer type */ +typedef enum _dma_transfer_type +{ + kDMA_MemoryToMemory = 0x0U, /*!< Transfer from memory to memory (increment source and destination) */ + kDMA_PeripheralToMemory, /*!< Transfer from peripheral to memory (increment only destination) */ + kDMA_MemoryToPeripheral, /*!< Transfer from memory to peripheral (increment only source)*/ + kDMA_StaticToStatic, /*!< Peripheral to static memory (do not increment source or destination) */ +} dma_transfer_type_t; + +/*! @brief DMA channel trigger */ +typedef struct _dma_channel_trigger +{ + dma_trigger_type_t type; /*!< Select hardware trigger as edge triggered or level triggered. */ + dma_trigger_burst_t burst; /*!< Select whether hardware triggers cause a single or burst transfer. */ + dma_burst_wrap_t wrap; /*!< Select wrap type, source wrap or dest wrap, or both. */ +} dma_channel_trigger_t; + +/*! @brief DMA channel trigger */ +typedef struct _dma_channel_config +{ + void *srcStartAddr; /*!< Source data address */ + void *dstStartAddr; /*!< Destination data address */ + void *nextDesc; /*!< Chain custom descriptor */ + uint32_t xferCfg; /*!< channel transfer configurations */ + dma_channel_trigger_t *trigger; /*!< DMA trigger type */ + bool isPeriph; /*!< select the request type */ +} dma_channel_config_t; + +/*! @brief DMA transfer configuration */ +typedef struct _dma_transfer_config +{ + uint8_t *srcAddr; /*!< Source data address */ + uint8_t *dstAddr; /*!< Destination data address */ + uint8_t *nextDesc; /*!< Chain custom descriptor */ + dma_xfercfg_t xfercfg; /*!< Transfer options */ + bool isPeriph; /*!< DMA transfer is driven by peripheral */ +} dma_transfer_config_t; + +/*! @brief Callback for DMA */ +struct _dma_handle; + +/*! @brief Define Callback function for DMA. */ +typedef void (*dma_callback)(struct _dma_handle *handle, void *userData, bool transferDone, uint32_t intmode); + +/*! @brief DMA transfer handle structure */ +typedef struct _dma_handle +{ + dma_callback callback; /*!< Callback function. Invoked when transfer + of descriptor with interrupt flag finishes */ + void *userData; /*!< Callback function parameter */ + DMA_Type *base; /*!< DMA peripheral base address */ + uint8_t channel; /*!< DMA channel number */ +} dma_handle_t; + +/******************************************************************************* + * APIs + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/*! + * @name DMA initialization and De-initialization + * @{ + */ + +/*! + * @brief Initializes DMA peripheral. + * + * This function enable the DMA clock, set descriptor table and + * enable DMA peripheral. + * + * @param base DMA peripheral base address. + */ +void DMA_Init(DMA_Type *base); + +/*! + * @brief Deinitializes DMA peripheral. + * + * This function gates the DMA clock. + * + * @param base DMA peripheral base address. + */ +void DMA_Deinit(DMA_Type *base); + +/*! + * @brief Install DMA descriptor memory. + * + * This function used to register DMA descriptor memory for linked transfer, a typical case is ping pong + * transfer which will request more than one DMA descriptor memory space, althrough current DMA driver has + * a default DMA descriptor buffer, but it support one DMA descriptor for one channel only. + * + * @param base DMA base address. + * @param addr DMA descriptor address + */ +void DMA_InstallDescriptorMemory(DMA_Type *base, void *addr); + +/* @} */ + +/*! + * @name DMA Channel Operation + * @{ + */ + +/*! + * @brief Return whether DMA channel is processing transfer + * + * @param base DMA peripheral base address. + * @param channel DMA channel number. + * @return True for active state, false otherwise. + */ +static inline bool DMA_ChannelIsActive(DMA_Type *base, uint32_t channel) +{ + assert((FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base) != -1) && + (channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base))); + + return (DMA_COMMON_CONST_REG_GET(base, channel, ACTIVE) & (1UL << DMA_CHANNEL_INDEX(base, channel))) != 0UL; +} + +/*! + * @brief Return whether DMA channel is busy + * + * @param base DMA peripheral base address. + * @param channel DMA channel number. + * @return True for busy state, false otherwise. + */ +static inline bool DMA_ChannelIsBusy(DMA_Type *base, uint32_t channel) +{ + assert((FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base) != -1) && + (channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base))); + + return (DMA_COMMON_CONST_REG_GET(base, channel, BUSY) & (1UL << DMA_CHANNEL_INDEX(base, channel))) != 0UL; +} + +/*! + * @brief Enables the interrupt source for the DMA transfer. + * + * @param base DMA peripheral base address. + * @param channel DMA channel number. + */ +static inline void DMA_EnableChannelInterrupts(DMA_Type *base, uint32_t channel) +{ + assert((FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base) != -1) && + (channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base))); + DMA_COMMON_REG_GET(base, channel, INTENSET) |= 1UL << DMA_CHANNEL_INDEX(base, channel); +} + +/*! + * @brief Disables the interrupt source for the DMA transfer. + * + * @param base DMA peripheral base address. + * @param channel DMA channel number. + */ +static inline void DMA_DisableChannelInterrupts(DMA_Type *base, uint32_t channel) +{ + assert((FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base) != -1) && + (channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base))); + DMA_COMMON_REG_GET(base, channel, INTENCLR) |= 1UL << DMA_CHANNEL_INDEX(base, channel); +} + +/*! + * @brief Enable DMA channel. + * + * @param base DMA peripheral base address. + * @param channel DMA channel number. + */ +static inline void DMA_EnableChannel(DMA_Type *base, uint32_t channel) +{ + assert((FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base) != -1) && + (channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base))); + DMA_COMMON_REG_GET(base, channel, ENABLESET) |= 1UL << DMA_CHANNEL_INDEX(base, channel); +} + +/*! + * @brief Disable DMA channel. + * + * @param base DMA peripheral base address. + * @param channel DMA channel number. + */ +static inline void DMA_DisableChannel(DMA_Type *base, uint32_t channel) +{ + assert((FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base) != -1) && + (channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base))); + DMA_COMMON_REG_GET(base, channel, ENABLECLR) |= 1UL << DMA_CHANNEL_INDEX(base, channel); +} + +/*! + * @brief Set PERIPHREQEN of channel configuration register. + * + * @param base DMA peripheral base address. + * @param channel DMA channel number. + */ +static inline void DMA_EnableChannelPeriphRq(DMA_Type *base, uint32_t channel) +{ + assert((FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base) != -1) && + (channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base))); + base->CHANNEL[channel].CFG |= DMA_CHANNEL_CFG_PERIPHREQEN_MASK; +} + +/*! + * @brief Get PERIPHREQEN value of channel configuration register. + * + * @param base DMA peripheral base address. + * @param channel DMA channel number. + * @return True for enabled PeriphRq, false for disabled. + */ +static inline void DMA_DisableChannelPeriphRq(DMA_Type *base, uint32_t channel) +{ + assert((FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base) != -1) && + (channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base))); + base->CHANNEL[channel].CFG &= ~DMA_CHANNEL_CFG_PERIPHREQEN_MASK; +} + +/*! + * @brief Set trigger settings of DMA channel. + * @deprecated Do not use this function. It has been superceded by @ref DMA_SetChannelConfig. + * + * @param base DMA peripheral base address. + * @param channel DMA channel number. + * @param trigger trigger configuration. + */ +void DMA_ConfigureChannelTrigger(DMA_Type *base, uint32_t channel, dma_channel_trigger_t *trigger); + +/*! + * @brief set channel config. + * + * This function provide a interface to configure channel configuration reisters. + * + * @param base DMA base address. + * @param channel DMA channel number. + * @param trigger channel configurations structure. + * @param isPeriph true is periph request, false is not. + */ +void DMA_SetChannelConfig(DMA_Type *base, uint32_t channel, dma_channel_trigger_t *trigger, bool isPeriph); + +/*! + * @brief Gets the remaining bytes of the current DMA descriptor transfer. + * + * @param base DMA peripheral base address. + * @param channel DMA channel number. + * @return The number of bytes which have not been transferred yet. + */ +uint32_t DMA_GetRemainingBytes(DMA_Type *base, uint32_t channel); + +/*! + * @brief Set priority of channel configuration register. + * + * @param base DMA peripheral base address. + * @param channel DMA channel number. + * @param priority Channel priority value. + */ +static inline void DMA_SetChannelPriority(DMA_Type *base, uint32_t channel, dma_priority_t priority) +{ + assert((FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base) != -1) && + (channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base))); + base->CHANNEL[channel].CFG = + (base->CHANNEL[channel].CFG & (~(DMA_CHANNEL_CFG_CHPRIORITY_MASK))) | DMA_CHANNEL_CFG_CHPRIORITY(priority); +} + +/*! + * @brief Get priority of channel configuration register. + * + * @param base DMA peripheral base address. + * @param channel DMA channel number. + * @return Channel priority value. + */ +static inline dma_priority_t DMA_GetChannelPriority(DMA_Type *base, uint32_t channel) +{ + assert((FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base) != -1) && + (channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base))); + return (dma_priority_t)(uint8_t)((base->CHANNEL[channel].CFG & DMA_CHANNEL_CFG_CHPRIORITY_MASK) >> + DMA_CHANNEL_CFG_CHPRIORITY_SHIFT); +} + +/*! + * @brief Set channel configuration valid. + * + * @param base DMA peripheral base address. + * @param channel DMA channel number. + */ +static inline void DMA_SetChannelConfigValid(DMA_Type *base, uint32_t channel) +{ + base->CHANNEL[channel].XFERCFG |= DMA_CHANNEL_XFERCFG_CFGVALID_MASK; +} + +/*! + * @brief Do software trigger for the channel. + * + * @param base DMA peripheral base address. + * @param channel DMA channel number. + */ +static inline void DMA_DoChannelSoftwareTrigger(DMA_Type *base, uint32_t channel) +{ + base->CHANNEL[channel].XFERCFG |= DMA_CHANNEL_XFERCFG_SWTRIG_MASK; +} + +/*! + * @brief Load channel transfer configurations. + * + * @param base DMA peripheral base address. + * @param channel DMA channel number. + * @param xfer transfer configurations. + */ +static inline void DMA_LoadChannelTransferConfig(DMA_Type *base, uint32_t channel, uint32_t xfer) +{ + base->CHANNEL[channel].XFERCFG = xfer; +} + +/*! + * @brief Create application specific DMA descriptor + * to be used in a chain in transfer + * @deprecated Do not use this function. It has been superceded by @ref DMA_SetupDescriptor. + * @param desc DMA descriptor address. + * @param xfercfg Transfer configuration for DMA descriptor. + * @param srcAddr Address of last item to transmit + * @param dstAddr Address of last item to receive. + * @param nextDesc Address of next descriptor in chain. + */ +void DMA_CreateDescriptor(dma_descriptor_t *desc, dma_xfercfg_t *xfercfg, void *srcAddr, void *dstAddr, void *nextDesc); + +/*! + * @brief setup dma descriptor + * + * Note: This function do not support configure wrap descriptor. + * + * @param desc DMA descriptor address. + * @param xfercfg Transfer configuration for DMA descriptor. + * @param srcStartAddr Start address of source address. + * @param dstStartAddr Start address of destination address. + * @param nextDesc Address of next descriptor in chain. + */ +void DMA_SetupDescriptor( + dma_descriptor_t *desc, uint32_t xfercfg, void *srcStartAddr, void *dstStartAddr, void *nextDesc); + +/*! + * @brief setup dma channel descriptor + * + * Note: This function support configure wrap descriptor. + * + * @param desc DMA descriptor address. + * @param xfercfg Transfer configuration for DMA descriptor. + * @param srcStartAddr Start address of source address. + * @param dstStartAddr Start address of destination address. + * @param nextDesc Address of next descriptor in chain. + * @param wrapType burst wrap type. + * @param burstSize burst size, reference _dma_burst_size. + */ +void DMA_SetupChannelDescriptor(dma_descriptor_t *desc, + uint32_t xfercfg, + void *srcStartAddr, + void *dstStartAddr, + void *nextDesc, + dma_burst_wrap_t wrapType, + uint32_t burstSize); + +/*! + * @brief load channel transfer decriptor. + * + * This function can be used to load desscriptor to driver internal channel descriptor that is used to start DMA + * transfer, the head descriptor table is defined in DMA driver, it is useful for the case: + * 1. for the polling transfer, application can allocate a local descriptor memory table to prepare a descriptor firstly + * and then call this api to load the configured descriptor to driver descriptor table. + * @code + * DMA_Init(DMA0); + * DMA_EnableChannel(DMA0, DEMO_DMA_CHANNEL); + * DMA_SetupDescriptor(desc, xferCfg, s_srcBuffer, &s_destBuffer[0], NULL); + * DMA_LoadChannelDescriptor(DMA0, DEMO_DMA_CHANNEL, (dma_descriptor_t *)desc); + * DMA_DoChannelSoftwareTrigger(DMA0, DEMO_DMA_CHANNEL); + * while(DMA_ChannelIsBusy(DMA0, DEMO_DMA_CHANNEL)) + * {} + * @endcode + * + * @param base DMA base address. + * @param channel DMA channel. + * @param descriptor configured DMA descriptor. + */ +void DMA_LoadChannelDescriptor(DMA_Type *base, uint32_t channel, dma_descriptor_t *descriptor); + +/* @} */ + +/*! + * @name DMA Transactional Operation + * @{ + */ + +/*! + * @brief Abort running transfer by handle. + * + * This function aborts DMA transfer specified by handle. + * + * @param handle DMA handle pointer. + */ +void DMA_AbortTransfer(dma_handle_t *handle); + +/*! + * @brief Creates the DMA handle. + * + * This function is called if using transaction API for DMA. This function + * initializes the internal state of DMA handle. + * + * @param handle DMA handle pointer. The DMA handle stores callback function and + * parameters. + * @param base DMA peripheral base address. + * @param channel DMA channel number. + */ +void DMA_CreateHandle(dma_handle_t *handle, DMA_Type *base, uint32_t channel); + +/*! + * @brief Installs a callback function for the DMA transfer. + * + * This callback is called in DMA IRQ handler. Use the callback to do something after + * the current major loop transfer completes. + * + * @param handle DMA handle pointer. + * @param callback DMA callback function pointer. + * @param userData Parameter for callback function. + */ +void DMA_SetCallback(dma_handle_t *handle, dma_callback callback, void *userData); + +/*! + * @brief Prepares the DMA transfer structure. + * @deprecated Do not use this function. It has been superceded by @ref DMA_PrepareChannelTransfer. + * This function prepares the transfer configuration structure according to the user input. + * + * @param config The user configuration structure of type dma_transfer_t. + * @param srcAddr DMA transfer source address. + * @param dstAddr DMA transfer destination address. + * @param byteWidth DMA transfer destination address width(bytes). + * @param transferBytes DMA transfer bytes to be transferred. + * @param type DMA transfer type. + * @param nextDesc Chain custom descriptor to transfer. + * @note The data address and the data width must be consistent. For example, if the SRC + * is 4 bytes, so the source address must be 4 bytes aligned, or it shall result in + * source address error(SAE). + */ +void DMA_PrepareTransfer(dma_transfer_config_t *config, + void *srcAddr, + void *dstAddr, + uint32_t byteWidth, + uint32_t transferBytes, + dma_transfer_type_t type, + void *nextDesc); + +/*! + * @brief Prepare channel transfer configurations. + * + * This function used to prepare channel transfer configurations. + * + * @param config Pointer to DMA channel transfer configuration structure. + * @param srcStartAddr source start address. + * @param dstStartAddr destination start address. + * @param xferCfg xfer configuration, user can reference DMA_CHANNEL_XFER about to how to get xferCfg value. + * @param type transfer type. + * @param trigger DMA channel trigger configurations. + * @param nextDesc address of next descriptor. + */ +void DMA_PrepareChannelTransfer(dma_channel_config_t *config, + void *srcStartAddr, + void *dstStartAddr, + uint32_t xferCfg, + dma_transfer_type_t type, + dma_channel_trigger_t *trigger, + void *nextDesc); + +/*! + * @brief Submits the DMA transfer request. + * @deprecated Do not use this function. It has been superceded by @ref DMA_SubmitChannelTransfer. + * + * This function submits the DMA transfer request according to the transfer configuration structure. + * If the user submits the transfer request repeatedly, this function packs an unprocessed request as + * a TCD and enables scatter/gather feature to process it in the next time. + * + * @param handle DMA handle pointer. + * @param config Pointer to DMA transfer configuration structure. + * @retval kStatus_DMA_Success It means submit transfer request succeed. + * @retval kStatus_DMA_QueueFull It means TCD queue is full. Submit transfer request is not allowed. + * @retval kStatus_DMA_Busy It means the given channel is busy, need to submit request later. + */ +status_t DMA_SubmitTransfer(dma_handle_t *handle, dma_transfer_config_t *config); + +/*! + * @brief Submit channel transfer paramter directly. + * + * This function used to configue channel head descriptor that is used to start DMA transfer, the head descriptor table + * is defined in DMA driver, it is useful for the case: + * 1. for the single transfer, application doesn't need to allocate descriptor table, the head descriptor can be used + for it. + * @code + DMA_SetChannelConfig(base, channel, trigger, isPeriph); + DMA_CreateHandle(handle, base, channel) + DMA_SubmitChannelTransferParameter(handle, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, + bytes), srcStartAddr, dstStartAddr, NULL); + DMA_StartTransfer(handle) + * @endcode + * + * 2. for the linked transfer, application should responsible for link descriptor, for example, if 4 transfer is + required, then application should prepare + * three descriptor table with macro , the head descriptor in driver can be used for the first transfer descriptor. + * @code + define link descriptor table in application with macro + DMA_ALLOCATE_LINK_DESCRIPTOR(nextDesc[3]); + + DMA_SetupDescriptor(nextDesc0, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), + srcStartAddr, dstStartAddr, nextDesc1); + DMA_SetupDescriptor(nextDesc1, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), + srcStartAddr, dstStartAddr, nextDesc2); + DMA_SetupDescriptor(nextDesc2, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), + srcStartAddr, dstStartAddr, NULL); + DMA_SetChannelConfig(base, channel, trigger, isPeriph); + DMA_CreateHandle(handle, base, channel) + DMA_SubmitChannelTransferParameter(handle, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, + bytes), srcStartAddr, dstStartAddr, nextDesc0); + DMA_StartTransfer(handle); + * @endcode + * + * @param handle Pointer to DMA handle. + * @param xferCfg xfer configuration, user can reference DMA_CHANNEL_XFER about to how to get xferCfg value. + * @param srcStartAddr source start address. + * @param dstStartAddr destination start address. + * @param nextDesc address of next descriptor. + */ +void DMA_SubmitChannelTransferParameter( + dma_handle_t *handle, uint32_t xferCfg, void *srcStartAddr, void *dstStartAddr, void *nextDesc); + +/*! + * @brief Submit channel descriptor. + * + * This function used to configue channel head descriptor that is used to start DMA transfer, the head descriptor table + is defined in + * DMA driver, this functiono is typical for the ping pong case: + * + * 1. for the ping pong case, application should responsible for the descriptor, for example, application should + * prepare two descriptor table with macro. + * @code + define link descriptor table in application with macro + DMA_ALLOCATE_LINK_DESCRIPTOR(nextDesc[2]); + + DMA_SetupDescriptor(nextDesc0, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), + srcStartAddr, dstStartAddr, nextDesc1); + DMA_SetupDescriptor(nextDesc1, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), + srcStartAddr, dstStartAddr, nextDesc0); + DMA_SetChannelConfig(base, channel, trigger, isPeriph); + DMA_CreateHandle(handle, base, channel) + DMA_SubmitChannelDescriptor(handle, nextDesc0); + DMA_StartTransfer(handle); + * @endcode + * + * @param handle Pointer to DMA handle. + * @param descriptor descriptor to submit. + */ +void DMA_SubmitChannelDescriptor(dma_handle_t *handle, dma_descriptor_t *descriptor); + +/*! + * @brief Submits the DMA channel transfer request. + * + * This function submits the DMA transfer request according to the transfer configuration structure. + * If the user submits the transfer request repeatedly, this function packs an unprocessed request as + * a TCD and enables scatter/gather feature to process it in the next time. + * It is used for the case: + * 1. for the single transfer, application doesn't need to allocate descriptor table, the head descriptor can be used + for it. + * @code + DMA_CreateHandle(handle, base, channel) + DMA_PrepareChannelTransfer(config,srcStartAddr,dstStartAddr,xferCfg,type,trigger,NULL); + DMA_SubmitChannelTransfer(handle, config) + DMA_StartTransfer(handle) + * @endcode + * + * 2. for the linked transfer, application should responsible for link descriptor, for example, if 4 transfer is + required, then application should prepare + * three descriptor table with macro , the head descriptor in driver can be used for the first transfer descriptor. + * @code + define link descriptor table in application with macro + DMA_ALLOCATE_LINK_DESCRIPTOR(nextDesc); + DMA_SetupDescriptor(nextDesc0, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), + srcStartAddr, dstStartAddr, nextDesc1); + DMA_SetupDescriptor(nextDesc1, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), + srcStartAddr, dstStartAddr, nextDesc2); + DMA_SetupDescriptor(nextDesc2, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), + srcStartAddr, dstStartAddr, NULL); + DMA_CreateHandle(handle, base, channel) + DMA_PrepareChannelTransfer(config,srcStartAddr,dstStartAddr,xferCfg,type,trigger,nextDesc0); + DMA_SubmitChannelTransfer(handle, config) + DMA_StartTransfer(handle) + * @endcode + * + * 3. for the ping pong case, application should responsible for link descriptor, for example, application should + prepare + * two descriptor table with macro , the head descriptor in driver can be used for the first transfer descriptor. + * @code + define link descriptor table in application with macro + DMA_ALLOCATE_LINK_DESCRIPTOR(nextDesc); + + DMA_SetupDescriptor(nextDesc0, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), + srcStartAddr, dstStartAddr, nextDesc1); + DMA_SetupDescriptor(nextDesc1, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), + srcStartAddr, dstStartAddr, nextDesc0); + DMA_CreateHandle(handle, base, channel) + DMA_PrepareChannelTransfer(config,srcStartAddr,dstStartAddr,xferCfg,type,trigger,nextDesc0); + DMA_SubmitChannelTransfer(handle, config) + DMA_StartTransfer(handle) + * @endcode + * @param handle DMA handle pointer. + * @param config Pointer to DMA transfer configuration structure. + * @retval kStatus_DMA_Success It means submit transfer request succeed. + * @retval kStatus_DMA_QueueFull It means TCD queue is full. Submit transfer request is not allowed. + * @retval kStatus_DMA_Busy It means the given channel is busy, need to submit request later. + */ +status_t DMA_SubmitChannelTransfer(dma_handle_t *handle, dma_channel_config_t *config); + +/*! + * @brief DMA start transfer. + * + * This function enables the channel request. User can call this function after submitting the transfer request + * It will trigger transfer start with software trigger only when hardware trigger is not used. + * + * @param handle DMA handle pointer. + */ +void DMA_StartTransfer(dma_handle_t *handle); + +/*! + * @brief DMA IRQ handler for descriptor transfer complete. + * + * This function clears the channel major interrupt flag and call + * the callback function if it is not NULL. + * + * @param base DMA base address. + */ +void DMA_IRQHandle(DMA_Type *base); + +/* @} */ + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +/* @} */ + +#endif /*_FSL_DMA_H_*/ diff --git a/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_flexcomm.c b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_flexcomm.c new file mode 100644 index 0000000000..7a21a1ce0e --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_flexcomm.c @@ -0,0 +1,412 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2019 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_common.h" +#include "fsl_flexcomm.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.flexcomm" +#endif + +/*! + * @brief Used for conversion between `void*` and `uint32_t`. + */ +typedef union pvoid_to_u32 +{ + void *pvoid; + uint32_t u32; +} pvoid_to_u32_t; + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! @brief Set the FLEXCOMM mode . */ +static status_t FLEXCOMM_SetPeriph(FLEXCOMM_Type *base, FLEXCOMM_PERIPH_T periph, int lock); + +/*! @brief check whether flexcomm supports peripheral type */ +static bool FLEXCOMM_PeripheralIsPresent(FLEXCOMM_Type *base, FLEXCOMM_PERIPH_T periph); + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/*! @brief Array to map FLEXCOMM instance number to base address. */ +static const uint32_t s_flexcommBaseAddrs[] = FLEXCOMM_BASE_ADDRS; + +/*! @brief Pointers to real IRQ handlers installed by drivers for each instance. */ +static flexcomm_irq_handler_t s_flexcommIrqHandler[ARRAY_SIZE(s_flexcommBaseAddrs)]; + +/*! @brief Pointers to handles for each instance to provide context to interrupt routines */ +static void *s_flexcommHandle[ARRAY_SIZE(s_flexcommBaseAddrs)]; + +/*! @brief Array to map FLEXCOMM instance number to IRQ number. */ +IRQn_Type const kFlexcommIrqs[] = FLEXCOMM_IRQS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief IDs of clock for each FLEXCOMM module */ +static const clock_ip_name_t s_flexcommClocks[] = FLEXCOMM_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if !(defined(FSL_FEATURE_FLEXCOMM_HAS_NO_RESET) && FSL_FEATURE_FLEXCOMM_HAS_NO_RESET) +/*! @brief Pointers to FLEXCOMM resets for each instance. */ +static const reset_ip_name_t s_flexcommResets[] = FLEXCOMM_RSTS; +#endif + +/******************************************************************************* + * Code + ******************************************************************************/ + +/* check whether flexcomm supports peripheral type */ +static bool FLEXCOMM_PeripheralIsPresent(FLEXCOMM_Type *base, FLEXCOMM_PERIPH_T periph) +{ + if (periph == FLEXCOMM_PERIPH_NONE) + { + return true; + } + else if (periph <= FLEXCOMM_PERIPH_I2S_TX) + { + return (base->PSELID & (1UL << ((uint32_t)periph + 3U))) > 0UL ? true : false; + } + else if (periph == FLEXCOMM_PERIPH_I2S_RX) + { + return (base->PSELID & (1U << 7U)) > (uint32_t)0U ? true : false; + } + else + { + return false; + } +} + +/* Get the index corresponding to the FLEXCOMM */ +/*! brief Returns instance number for FLEXCOMM module with given base address. */ +uint32_t FLEXCOMM_GetInstance(void *base) +{ + uint32_t i; + pvoid_to_u32_t BaseAddr; + BaseAddr.pvoid = base; + + for (i = 0U; i < (uint32_t)FSL_FEATURE_SOC_FLEXCOMM_COUNT; i++) + { + if (BaseAddr.u32 == s_flexcommBaseAddrs[i]) + { + break; + } + } + + assert(i < (uint32_t)FSL_FEATURE_SOC_FLEXCOMM_COUNT); + return i; +} + +/* Changes FLEXCOMM mode */ +static status_t FLEXCOMM_SetPeriph(FLEXCOMM_Type *base, FLEXCOMM_PERIPH_T periph, int lock) +{ + /* Check whether peripheral type is present */ + if (!FLEXCOMM_PeripheralIsPresent(base, periph)) + { + return kStatus_OutOfRange; + } + + /* Flexcomm is locked to different peripheral type than expected */ + if (((base->PSELID & FLEXCOMM_PSELID_LOCK_MASK) != 0U) && + ((base->PSELID & FLEXCOMM_PSELID_PERSEL_MASK) != (uint32_t)periph)) + { + return kStatus_Fail; + } + + /* Check if we are asked to lock */ + if (lock != 0) + { + base->PSELID = (uint32_t)periph | FLEXCOMM_PSELID_LOCK_MASK; + } + else + { + base->PSELID = (uint32_t)periph; + } + + return kStatus_Success; +} + +/*! brief Initializes FLEXCOMM and selects peripheral mode according to the second parameter. */ +status_t FLEXCOMM_Init(void *base, FLEXCOMM_PERIPH_T periph) +{ + uint32_t idx = FLEXCOMM_GetInstance(base); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable the peripheral clock */ + CLOCK_EnableClock(s_flexcommClocks[idx]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if !(defined(FSL_FEATURE_FLEXCOMM_HAS_NO_RESET) && FSL_FEATURE_FLEXCOMM_HAS_NO_RESET) + /* Reset the FLEXCOMM module */ + RESET_PeripheralReset(s_flexcommResets[idx]); +#endif + + /* Set the FLEXCOMM to given peripheral */ + return FLEXCOMM_SetPeriph((FLEXCOMM_Type *)base, periph, 0); +} + +/*! brief Sets IRQ handler for given FLEXCOMM module. It is used by drivers register IRQ handler according to FLEXCOMM + * mode */ +void FLEXCOMM_SetIRQHandler(void *base, flexcomm_irq_handler_t handler, void *flexcommHandle) +{ + uint32_t instance; + + /* Look up instance number */ + instance = FLEXCOMM_GetInstance(base); + + /* Clear handler first to avoid execution of the handler with wrong handle */ + s_flexcommIrqHandler[instance] = NULL; + s_flexcommHandle[instance] = flexcommHandle; + s_flexcommIrqHandler[instance] = handler; + SDK_ISR_EXIT_BARRIER; +} + +/* IRQ handler functions overloading weak symbols in the startup */ +#if defined(FLEXCOMM0) +void FLEXCOMM0_DriverIRQHandler(void); +void FLEXCOMM0_DriverIRQHandler(void) +{ + uint32_t instance; + + /* Look up instance number */ + instance = FLEXCOMM_GetInstance(FLEXCOMM0); + assert(s_flexcommIrqHandler[instance] != NULL); + s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(FLEXCOMM1) +void FLEXCOMM1_DriverIRQHandler(void); +void FLEXCOMM1_DriverIRQHandler(void) +{ + uint32_t instance; + + /* Look up instance number */ + instance = FLEXCOMM_GetInstance(FLEXCOMM1); + assert(s_flexcommIrqHandler[instance] != NULL); + s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(FLEXCOMM2) +void FLEXCOMM2_DriverIRQHandler(void); +void FLEXCOMM2_DriverIRQHandler(void) +{ + uint32_t instance; + + /* Look up instance number */ + instance = FLEXCOMM_GetInstance(FLEXCOMM2); + assert(s_flexcommIrqHandler[instance] != NULL); + s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(FLEXCOMM3) +void FLEXCOMM3_DriverIRQHandler(void); +void FLEXCOMM3_DriverIRQHandler(void) +{ + uint32_t instance; + + /* Look up instance number */ + instance = FLEXCOMM_GetInstance(FLEXCOMM3); + assert(s_flexcommIrqHandler[instance] != NULL); + s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(FLEXCOMM4) +void FLEXCOMM4_DriverIRQHandler(void); +void FLEXCOMM4_DriverIRQHandler(void) +{ + uint32_t instance; + + /* Look up instance number */ + instance = FLEXCOMM_GetInstance(FLEXCOMM4); + assert(s_flexcommIrqHandler[instance] != NULL); + s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); + SDK_ISR_EXIT_BARRIER; +} + +#endif + +#if defined(FLEXCOMM5) +void FLEXCOMM5_DriverIRQHandler(void); +void FLEXCOMM5_DriverIRQHandler(void) +{ + uint32_t instance; + + /* Look up instance number */ + instance = FLEXCOMM_GetInstance(FLEXCOMM5); + assert(s_flexcommIrqHandler[instance] != NULL); + s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(FLEXCOMM6) +void FLEXCOMM6_DriverIRQHandler(void); +void FLEXCOMM6_DriverIRQHandler(void) +{ + uint32_t instance; + + /* Look up instance number */ + instance = FLEXCOMM_GetInstance(FLEXCOMM6); + assert(s_flexcommIrqHandler[instance] != NULL); + s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(FLEXCOMM7) +void FLEXCOMM7_DriverIRQHandler(void); +void FLEXCOMM7_DriverIRQHandler(void) +{ + uint32_t instance; + + /* Look up instance number */ + instance = FLEXCOMM_GetInstance(FLEXCOMM7); + assert(s_flexcommIrqHandler[instance] != NULL); + s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(FLEXCOMM8) +void FLEXCOMM8_DriverIRQHandler(void); +void FLEXCOMM8_DriverIRQHandler(void) +{ + uint32_t instance; + + /* Look up instance number */ + instance = FLEXCOMM_GetInstance(FLEXCOMM8); + assert(s_flexcommIrqHandler[instance] != NULL); + s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(FLEXCOMM9) +void FLEXCOMM9_DriverIRQHandler(void); +void FLEXCOMM9_DriverIRQHandler(void) +{ + uint32_t instance; + + /* Look up instance number */ + instance = FLEXCOMM_GetInstance(FLEXCOMM9); + assert(s_flexcommIrqHandler[instance] != NULL); + s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(FLEXCOMM10) +void FLEXCOMM10_DriverIRQHandler(void); +void FLEXCOMM10_DriverIRQHandler(void) +{ + uint32_t instance; + + /* Look up instance number */ + instance = FLEXCOMM_GetInstance(FLEXCOMM10); + assert(s_flexcommIrqHandler[instance] != NULL); + s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(FLEXCOMM11) +void FLEXCOMM11_DriverIRQHandler(void); +void FLEXCOMM11_DriverIRQHandler(void) +{ + uint32_t instance; + + /* Look up instance number */ + instance = FLEXCOMM_GetInstance(FLEXCOMM11); + assert(s_flexcommIrqHandler[instance] != NULL); + s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(FLEXCOMM12) +void FLEXCOMM12_DriverIRQHandler(void); +void FLEXCOMM12_DriverIRQHandler(void) +{ + uint32_t instance; + + /* Look up instance number */ + instance = FLEXCOMM_GetInstance(FLEXCOMM12); + assert(s_flexcommIrqHandler[instance] != NULL); + s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(FLEXCOMM13) +void FLEXCOMM13_DriverIRQHandler(void); +void FLEXCOMM13_DriverIRQHandler(void) +{ + uint32_t instance; + + /* Look up instance number */ + instance = FLEXCOMM_GetInstance(FLEXCOMM13); + assert(s_flexcommIrqHandler[instance] != NULL); + s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(FLEXCOMM14) +void FLEXCOMM14_DriverIRQHandler(void); +void FLEXCOMM14_DriverIRQHandler(void) +{ + uint32_t instance; + + /* Look up instance number */ + instance = FLEXCOMM_GetInstance(FLEXCOMM14); + assert(s_flexcommIrqHandler[instance] != NULL); + s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(FLEXCOMM15) +void FLEXCOMM15_DriverIRQHandler(void); +void FLEXCOMM15_DriverIRQHandler(void) +{ + uint32_t instance; + + /* Look up instance number */ + instance = FLEXCOMM_GetInstance(FLEXCOMM15); + assert(s_flexcommIrqHandler[instance] != NULL); + s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(FLEXCOMM16) +void FLEXCOMM16_DriverIRQHandler(void); +void FLEXCOMM16_DriverIRQHandler(void) +{ + uint32_t instance; + + /* Look up instance number */ + instance = FLEXCOMM_GetInstance(FLEXCOMM16); + assert(s_flexcommIrqHandler[instance] != NULL); + s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); + SDK_ISR_EXIT_BARRIER; +} +#endif diff --git a/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_flexcomm.h b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_flexcomm.h new file mode 100644 index 0000000000..f96086fdec --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_flexcomm.h @@ -0,0 +1,64 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2019 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_FLEXCOMM_H_ +#define _FSL_FLEXCOMM_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup flexcomm_driver + * @{ + */ + +/*! @name Driver version */ +/*@{*/ +/*! @brief FlexCOMM driver version 2.0.2. */ +#define FSL_FLEXCOMM_DRIVER_VERSION (MAKE_VERSION(2, 0, 2)) +/*@}*/ + +/*! @brief FLEXCOMM peripheral modes. */ +typedef enum +{ + FLEXCOMM_PERIPH_NONE, /*!< No peripheral */ + FLEXCOMM_PERIPH_USART, /*!< USART peripheral */ + FLEXCOMM_PERIPH_SPI, /*!< SPI Peripheral */ + FLEXCOMM_PERIPH_I2C, /*!< I2C Peripheral */ + FLEXCOMM_PERIPH_I2S_TX, /*!< I2S TX Peripheral */ + FLEXCOMM_PERIPH_I2S_RX, /*!< I2S RX Peripheral */ +} FLEXCOMM_PERIPH_T; + +/*! @brief Typedef for interrupt handler. */ +typedef void (*flexcomm_irq_handler_t)(void *base, void *handle); + +/*! @brief Array with IRQ number for each FLEXCOMM module. */ +extern IRQn_Type const kFlexcommIrqs[]; + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif + +/*! @brief Returns instance number for FLEXCOMM module with given base address. */ +uint32_t FLEXCOMM_GetInstance(void *base); + +/*! @brief Initializes FLEXCOMM and selects peripheral mode according to the second parameter. */ +status_t FLEXCOMM_Init(void *base, FLEXCOMM_PERIPH_T periph); + +/*! @brief Sets IRQ handler for given FLEXCOMM module. It is used by drivers register IRQ handler according to FLEXCOMM + * mode */ +void FLEXCOMM_SetIRQHandler(void *base, flexcomm_irq_handler_t handler, void *flexcommHandle); + +#if defined(__cplusplus) +} +#endif + +/*@}*/ + +#endif /* _FSL_FLEXCOMM_H_*/ diff --git a/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_fro_calib.h b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_fro_calib.h new file mode 100644 index 0000000000..9662444a52 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_fro_calib.h @@ -0,0 +1,61 @@ +/* + * Copyright (c) 2017, NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_FRO_CALIB_H_ +#define _FSL_FRO_CALIB_H_ + +#include "fsl_common.h" +#include "fsl_device_registers.h" +#include + +/*! + * @addtogroup power + * @{ + */ +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief FRO_CALIB driver version 1.0.0. */ +#define FSL_FRO_CALIB_DRIVER_VERSION (MAKE_VERSION(1, 0, 0)) +/*@}*/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.fro_calib" +#endif + +/******************************************************************************* + * API + ******************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Returns the version of the FRO Calibration library */ +unsigned int fro_calib_Get_Lib_Ver(void); + +/* ctimer instance */ +/* ctimer clock frquency in KHz */ +void Chip_TIMER_Instance_Freq(CTIMER_Type *base, unsigned int ctimerFreq); + +/* USB_SOF_Event */ +/* Application software should be written to make sure the USB_SOF_EVENT() is */ +/* being called with lower interrupt latency for calibration to work properly */ +void USB_SOF_Event(void); + +#ifdef __cplusplus +} +#endif + +/** + * @} + */ + +#endif /* _FSL_FRO_CALIB_H_ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_gint.c b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_gint.c new file mode 100644 index 0000000000..408844c3d1 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_gint.c @@ -0,0 +1,372 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017, 2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_gint.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.gint" +#endif + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Pointers to GINT bases for each instance. */ +static GINT_Type *const s_gintBases[FSL_FEATURE_SOC_GINT_COUNT] = GINT_BASE_PTRS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Clocks for each instance. */ +static const clock_ip_name_t s_gintClocks[FSL_FEATURE_SOC_GINT_COUNT] = GINT_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) +/*! @brief Resets for each instance. */ +static const reset_ip_name_t s_gintResets[FSL_FEATURE_SOC_GINT_COUNT] = GINT_RSTS; +#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ + +/* @brief Irq number for each instance */ +static const IRQn_Type s_gintIRQ[FSL_FEATURE_SOC_GINT_COUNT] = GINT_IRQS; + +/*! @brief Callback function array for GINT(s). */ +static gint_cb_t s_gintCallback[FSL_FEATURE_SOC_GINT_COUNT]; + +/******************************************************************************* + * Code + ******************************************************************************/ + +static uint32_t GINT_GetInstance(GINT_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_gintBases); instance++) + { + if (s_gintBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_gintBases)); + + return instance; +} + +/*! + * brief Initialize GINT peripheral. + + * This function initializes the GINT peripheral and enables the clock. + * + * param base Base address of the GINT peripheral. + * + * retval None. + */ +void GINT_Init(GINT_Type *base) +{ + uint32_t instance; + + instance = GINT_GetInstance(base); + + s_gintCallback[instance] = NULL; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable the peripheral clock */ + CLOCK_EnableClock(s_gintClocks[instance]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) + /* Reset the module. */ + RESET_PeripheralReset(s_gintResets[instance]); +#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ +} + +/*! + * brief Setup GINT peripheral control parameters. + + * This function sets the control parameters of GINT peripheral. + * + * param base Base address of the GINT peripheral. + * param comb Controls if the enabled inputs are logically ORed or ANDed for interrupt generation. + * param trig Controls if the enabled inputs are level or edge sensitive based on polarity. + * param callback This function is called when configured group interrupt is generated. + * + * retval None. + */ +void GINT_SetCtrl(GINT_Type *base, gint_comb_t comb, gint_trig_t trig, gint_cb_t callback) +{ + uint32_t instance; + + instance = GINT_GetInstance(base); + + base->CTRL = (GINT_CTRL_COMB(comb) | GINT_CTRL_TRIG(trig)); + + /* Save callback pointer */ + s_gintCallback[instance] = callback; +} + +/*! + * brief Get GINT peripheral control parameters. + + * This function returns the control parameters of GINT peripheral. + * + * param base Base address of the GINT peripheral. + * param comb Pointer to store combine input value. + * param trig Pointer to store trigger value. + * param callback Pointer to store callback function. + * + * retval None. + */ +void GINT_GetCtrl(GINT_Type *base, gint_comb_t *comb, gint_trig_t *trig, gint_cb_t *callback) +{ + uint32_t instance; + uint32_t combValue; + uint32_t trigValue; + + instance = GINT_GetInstance(base); + + combValue = (base->CTRL & GINT_CTRL_COMB_MASK) >> GINT_CTRL_COMB_SHIFT; + *comb = (gint_comb_t)combValue; + trigValue = (base->CTRL & GINT_CTRL_TRIG_MASK) >> GINT_CTRL_TRIG_SHIFT; + *trig = (gint_trig_t)trigValue; + *callback = s_gintCallback[instance]; +} + +/*! + * brief Configure GINT peripheral pins. + + * This function enables and controls the polarity of enabled pin(s) of a given port. + * + * param base Base address of the GINT peripheral. + * param port Port number. + * param polarityMask Each bit position selects the polarity of the corresponding enabled pin. + * 0 = The pin is active LOW. 1 = The pin is active HIGH. + * param enableMask Each bit position selects if the corresponding pin is enabled or not. + * 0 = The pin is disabled. 1 = The pin is enabled. + * + * retval None. + */ +void GINT_ConfigPins(GINT_Type *base, gint_port_t port, uint32_t polarityMask, uint32_t enableMask) +{ + base->PORT_POL[port] = polarityMask; + base->PORT_ENA[port] = enableMask; +} + +/*! + * brief Get GINT peripheral pin configuration. + + * This function returns the pin configuration of a given port. + * + * param base Base address of the GINT peripheral. + * param port Port number. + * param polarityMask Pointer to store the polarity mask Each bit position indicates the polarity of the corresponding + enabled pin. + * 0 = The pin is active LOW. 1 = The pin is active HIGH. + * param enableMask Pointer to store the enable mask. Each bit position indicates if the corresponding pin is enabled + or not. + * 0 = The pin is disabled. 1 = The pin is enabled. + * + * retval None. + */ +void GINT_GetConfigPins(GINT_Type *base, gint_port_t port, uint32_t *polarityMask, uint32_t *enableMask) +{ + *polarityMask = base->PORT_POL[port]; + *enableMask = base->PORT_ENA[port]; +} + +/*! + * brief Enable callback. + + * This function enables the interrupt for the selected GINT peripheral. Although the pin(s) are monitored + * as soon as they are enabled, the callback function is not enabled until this function is called. + * + * param base Base address of the GINT peripheral. + * + * retval None. + */ +void GINT_EnableCallback(GINT_Type *base) +{ + uint32_t instance; + + instance = GINT_GetInstance(base); + /* If GINT is configured in "AND" mode a spurious interrupt is generated. + Clear status and pending interrupt before enabling the irq in NVIC. */ + GINT_ClrStatus(base); + NVIC_ClearPendingIRQ(s_gintIRQ[instance]); + (void)EnableIRQ(s_gintIRQ[instance]); +} + +/*! + * brief Disable callback. + + * This function disables the interrupt for the selected GINT peripheral. Although the pins are still + * being monitored but the callback function is not called. + * + * param base Base address of the peripheral. + * + * retval None. + */ +void GINT_DisableCallback(GINT_Type *base) +{ + uint32_t instance; + + instance = GINT_GetInstance(base); + (void)DisableIRQ(s_gintIRQ[instance]); + GINT_ClrStatus(base); + NVIC_ClearPendingIRQ(s_gintIRQ[instance]); +} + +/*! + * brief Deinitialize GINT peripheral. + + * This function disables the GINT clock. + * + * param base Base address of the GINT peripheral. + * + * retval None. + */ +void GINT_Deinit(GINT_Type *base) +{ + uint32_t instance; + + instance = GINT_GetInstance(base); + + /* Cleanup */ + GINT_DisableCallback(base); + s_gintCallback[instance] = NULL; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) + /* Reset the module. */ + RESET_PeripheralReset(s_gintResets[instance]); +#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Disable the peripheral clock */ + CLOCK_DisableClock(s_gintClocks[instance]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/* IRQ handler functions overloading weak symbols in the startup */ +#if defined(GINT0) +void GINT0_DriverIRQHandler(void); +void GINT0_DriverIRQHandler(void) +{ + /* Clear interrupt before callback */ + s_gintBases[0]->CTRL |= GINT_CTRL_INT_MASK; + /* Call user function */ + if (s_gintCallback[0] != NULL) + { + s_gintCallback[0](); + } + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(GINT1) +void GINT1_DriverIRQHandler(void); +void GINT1_DriverIRQHandler(void) +{ + /* Clear interrupt before callback */ + s_gintBases[1]->CTRL |= GINT_CTRL_INT_MASK; + /* Call user function */ + if (s_gintCallback[1] != NULL) + { + s_gintCallback[1](); + } + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(GINT2) +void GINT2_DriverIRQHandler(void); +void GINT2_DriverIRQHandler(void) +{ + /* Clear interrupt before callback */ + s_gintBases[2]->CTRL |= GINT_CTRL_INT_MASK; + /* Call user function */ + if (s_gintCallback[2] != NULL) + { + s_gintCallback[2](); + } + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(GINT3) +void GINT3_DriverIRQHandler(void); +void GINT3_DriverIRQHandler(void) +{ + /* Clear interrupt before callback */ + s_gintBases[3]->CTRL |= GINT_CTRL_INT_MASK; + /* Call user function */ + if (s_gintCallback[3] != NULL) + { + s_gintCallback[3](); + } + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(GINT4) +void GINT4_DriverIRQHandler(void); +void GINT4_DriverIRQHandler(void) +{ + /* Clear interrupt before callback */ + s_gintBases[4]->CTRL |= GINT_CTRL_INT_MASK; + /* Call user function */ + if (s_gintCallback[4] != NULL) + { + s_gintCallback[4](); + } + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(GINT5) +void GINT5_DriverIRQHandler(void); +void GINT5_DriverIRQHandler(void) +{ + /* Clear interrupt before callback */ + s_gintBases[5]->CTRL |= GINT_CTRL_INT_MASK; + /* Call user function */ + if (s_gintCallback[5] != NULL) + { + s_gintCallback[5](); + } + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(GINT6) +void GINT6_DriverIRQHandler(void); +void GINT6_DriverIRQHandler(void) +{ + /* Clear interrupt before callback */ + s_gintBases[6]->CTRL |= GINT_CTRL_INT_MASK; + /* Call user function */ + if (s_gintCallback[6] != NULL) + { + s_gintCallback[6](); + } + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(GINT7) +void GINT7_DriverIRQHandler(void); +void GINT7_DriverIRQHandler(void) +{ + /* Clear interrupt before callback */ + s_gintBases[7]->CTRL |= GINT_CTRL_INT_MASK; + /* Call user function */ + if (s_gintCallback[7] != NULL) + { + s_gintCallback[7](); + } + SDK_ISR_EXIT_BARRIER; +} +#endif diff --git a/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_gint.h b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_gint.h new file mode 100644 index 0000000000..081be7a57c --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_gint.h @@ -0,0 +1,222 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017, 2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_GINT_H_ +#define _FSL_GINT_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup gint_driver + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +#define FSL_GINT_DRIVER_VERSION (MAKE_VERSION(2, 0, 3)) /*!< Version 2.0.3. */ +/*@}*/ + +/*! @brief GINT combine inputs type */ +typedef enum _gint_comb +{ + kGINT_CombineOr = 0U, /*!< A grouped interrupt is generated when any one of the enabled inputs is active */ + kGINT_CombineAnd = 1U /*!< A grouped interrupt is generated when all enabled inputs are active */ +} gint_comb_t; + +/*! @brief GINT trigger type */ +typedef enum _gint_trig +{ + kGINT_TrigEdge = 0U, /*!< Edge triggered based on polarity */ + kGINT_TrigLevel = 1U /*!< Level triggered based on polarity */ +} gint_trig_t; + +/* @brief GINT port type */ +typedef enum _gint_port +{ + kGINT_Port0 = 0U, + kGINT_Port1 = 1U, +#if defined(FSL_FEATURE_GINT_PORT_COUNT) && (FSL_FEATURE_GINT_PORT_COUNT > 2U) + kGINT_Port2 = 2U, +#endif +#if defined(FSL_FEATURE_GINT_PORT_COUNT) && (FSL_FEATURE_GINT_PORT_COUNT > 3U) + kGINT_Port3 = 3U, +#endif +#if defined(FSL_FEATURE_GINT_PORT_COUNT) && (FSL_FEATURE_GINT_PORT_COUNT > 4U) + kGINT_Port4 = 4U, +#endif +#if defined(FSL_FEATURE_GINT_PORT_COUNT) && (FSL_FEATURE_GINT_PORT_COUNT > 5U) + kGINT_Port5 = 5U, +#endif +#if defined(FSL_FEATURE_GINT_PORT_COUNT) && (FSL_FEATURE_GINT_PORT_COUNT > 6U) + kGINT_Port6 = 6U, +#endif +#if defined(FSL_FEATURE_GINT_PORT_COUNT) && (FSL_FEATURE_GINT_PORT_COUNT > 7U) + kGINT_Port7 = 7U, +#endif +} gint_port_t; + +/*! @brief GINT Callback function. */ +typedef void (*gint_cb_t)(void); + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Initialize GINT peripheral. + + * This function initializes the GINT peripheral and enables the clock. + * + * @param base Base address of the GINT peripheral. + * + * @retval None. + */ +void GINT_Init(GINT_Type *base); + +/*! + * @brief Setup GINT peripheral control parameters. + + * This function sets the control parameters of GINT peripheral. + * + * @param base Base address of the GINT peripheral. + * @param comb Controls if the enabled inputs are logically ORed or ANDed for interrupt generation. + * @param trig Controls if the enabled inputs are level or edge sensitive based on polarity. + * @param callback This function is called when configured group interrupt is generated. + * + * @retval None. + */ +void GINT_SetCtrl(GINT_Type *base, gint_comb_t comb, gint_trig_t trig, gint_cb_t callback); + +/*! + * @brief Get GINT peripheral control parameters. + + * This function returns the control parameters of GINT peripheral. + * + * @param base Base address of the GINT peripheral. + * @param comb Pointer to store combine input value. + * @param trig Pointer to store trigger value. + * @param callback Pointer to store callback function. + * + * @retval None. + */ +void GINT_GetCtrl(GINT_Type *base, gint_comb_t *comb, gint_trig_t *trig, gint_cb_t *callback); + +/*! + * @brief Configure GINT peripheral pins. + + * This function enables and controls the polarity of enabled pin(s) of a given port. + * + * @param base Base address of the GINT peripheral. + * @param port Port number. + * @param polarityMask Each bit position selects the polarity of the corresponding enabled pin. + * 0 = The pin is active LOW. 1 = The pin is active HIGH. + * @param enableMask Each bit position selects if the corresponding pin is enabled or not. + * 0 = The pin is disabled. 1 = The pin is enabled. + * + * @retval None. + */ +void GINT_ConfigPins(GINT_Type *base, gint_port_t port, uint32_t polarityMask, uint32_t enableMask); + +/*! + * @brief Get GINT peripheral pin configuration. + + * This function returns the pin configuration of a given port. + * + * @param base Base address of the GINT peripheral. + * @param port Port number. + * @param polarityMask Pointer to store the polarity mask Each bit position indicates the polarity of the corresponding + enabled pin. + * 0 = The pin is active LOW. 1 = The pin is active HIGH. + * @param enableMask Pointer to store the enable mask. Each bit position indicates if the corresponding pin is enabled + or not. + * 0 = The pin is disabled. 1 = The pin is enabled. + * + * @retval None. + */ +void GINT_GetConfigPins(GINT_Type *base, gint_port_t port, uint32_t *polarityMask, uint32_t *enableMask); + +/*! + * @brief Enable callback. + + * This function enables the interrupt for the selected GINT peripheral. Although the pin(s) are monitored + * as soon as they are enabled, the callback function is not enabled until this function is called. + * + * @param base Base address of the GINT peripheral. + * + * @retval None. + */ +void GINT_EnableCallback(GINT_Type *base); + +/*! + * @brief Disable callback. + + * This function disables the interrupt for the selected GINT peripheral. Although the pins are still + * being monitored but the callback function is not called. + * + * @param base Base address of the peripheral. + * + * @retval None. + */ +void GINT_DisableCallback(GINT_Type *base); + +/*! + * @brief Clear GINT status. + + * This function clears the GINT status bit. + * + * @param base Base address of the GINT peripheral. + * + * @retval None. + */ +static inline void GINT_ClrStatus(GINT_Type *base) +{ + base->CTRL |= GINT_CTRL_INT_MASK; +} + +/*! + * @brief Get GINT status. + + * This function returns the GINT status. + * + * @param base Base address of the GINT peripheral. + * + * @retval status = 0 No group interrupt request. = 1 Group interrupt request active. + */ +static inline uint32_t GINT_GetStatus(GINT_Type *base) +{ + return (base->CTRL & GINT_CTRL_INT_MASK); +} + +/*! + * @brief Deinitialize GINT peripheral. + + * This function disables the GINT clock. + * + * @param base Base address of the GINT peripheral. + * + * @retval None. + */ +void GINT_Deinit(GINT_Type *base); + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* _FSL_GINT_H_ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_gpio.c b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_gpio.c new file mode 100644 index 0000000000..be100d5e9e --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_gpio.c @@ -0,0 +1,317 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_gpio.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.lpc_gpio" +#endif + +/******************************************************************************* + * Variables + ******************************************************************************/ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Array to map FGPIO instance number to clock name. */ +static const clock_ip_name_t s_gpioClockName[] = GPIO_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if !(defined(FSL_FEATURE_GPIO_HAS_NO_RESET) && FSL_FEATURE_GPIO_HAS_NO_RESET) +/*! @brief Pointers to GPIO resets for each instance. */ +static const reset_ip_name_t s_gpioResets[] = GPIO_RSTS_N; +#endif +/******************************************************************************* + * Prototypes + ************ ******************************************************************/ +/*! + * @brief Enable GPIO port clock. + * + * @param base GPIO peripheral base pointer. + * @param port GPIO port number. + */ +static void GPIO_EnablePortClock(GPIO_Type *base, uint32_t port); + +/******************************************************************************* + * Code + ******************************************************************************/ +static void GPIO_EnablePortClock(GPIO_Type *base, uint32_t port) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + assert(port < ARRAY_SIZE(s_gpioClockName)); + + /* Upgate the GPIO clock */ + CLOCK_EnableClock(s_gpioClockName[port]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/*! + * brief Initializes the GPIO peripheral. + * + * This function ungates the GPIO clock. + * + * param base GPIO peripheral base pointer. + * param port GPIO port number. + */ +void GPIO_PortInit(GPIO_Type *base, uint32_t port) +{ + GPIO_EnablePortClock(base, port); + +#if !(defined(FSL_FEATURE_GPIO_HAS_NO_RESET) && FSL_FEATURE_GPIO_HAS_NO_RESET) + /* Reset the GPIO module */ + RESET_PeripheralReset(s_gpioResets[port]); +#endif +} + +/*! + * brief Initializes a GPIO pin used by the board. + * + * To initialize the GPIO, define a pin configuration, either input or output, in the user file. + * Then, call the GPIO_PinInit() function. + * + * This is an example to define an input pin or output pin configuration: + * code + * Define a digital input pin configuration, + * gpio_pin_config_t config = + * { + * kGPIO_DigitalInput, + * 0, + * } + * Define a digital output pin configuration, + * gpio_pin_config_t config = + * { + * kGPIO_DigitalOutput, + * 0, + * } + * endcode + * + * param base GPIO peripheral base pointer(Typically GPIO) + * param port GPIO port number + * param pin GPIO pin number + * param config GPIO pin configuration pointer + */ +void GPIO_PinInit(GPIO_Type *base, uint32_t port, uint32_t pin, const gpio_pin_config_t *config) +{ + GPIO_EnablePortClock(base, port); + + if (config->pinDirection == kGPIO_DigitalInput) + { +#if defined(FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR) && (FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR) + base->DIRCLR[port] = 1UL << pin; +#else + base->DIR[port] &= ~(1UL << pin); +#endif /*FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR*/ + } + else + { + /* Set default output value */ + if (config->outputLogic == 0U) + { + base->CLR[port] = (1UL << pin); + } + else + { + base->SET[port] = (1UL << pin); + } +/* Set pin direction */ +#if defined(FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR) && (FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR) + base->DIRSET[port] = 1UL << pin; +#else + base->DIR[port] |= 1UL << pin; +#endif /*FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR*/ + } +} + +#if defined(FSL_FEATURE_GPIO_HAS_INTERRUPT) && FSL_FEATURE_GPIO_HAS_INTERRUPT +/*! + * @brief Set the configuration of pin interrupt. + * + * @param base GPIO base pointer. + * @param port GPIO port number + * @param pin GPIO pin number. + * @param config GPIO pin interrupt configuration.. + */ +void GPIO_SetPinInterruptConfig(GPIO_Type *base, uint32_t port, uint32_t pin, gpio_interrupt_config_t *config) +{ + base->INTEDG[port] = (base->INTEDG[port] & ~(1UL << pin)) | ((uint32_t)config->mode << pin); + + base->INTPOL[port] = (base->INTPOL[port] & ~(1UL << pin)) | ((uint32_t)config->polarity << pin); +} + +/*! + * @brief Enables multiple pins interrupt. + * + * @param base GPIO base pointer. + * @param port GPIO port number. + * @param index GPIO interrupt number. + * @param mask GPIO pin number macro. + */ +void GPIO_PortEnableInterrupts(GPIO_Type *base, uint32_t port, uint32_t index, uint32_t mask) +{ + if ((uint32_t)kGPIO_InterruptA == index) + { + base->INTENA[port] = base->INTENA[port] | mask; + } + else if ((uint32_t)kGPIO_InterruptB == index) + { + base->INTENB[port] = base->INTENB[port] | mask; + } + else + { + /*Should not enter here*/ + } +} + +/*! + * @brief Disables multiple pins interrupt. + * + * @param base GPIO base pointer. + * @param port GPIO port number. + * @param index GPIO interrupt number. + * @param mask GPIO pin number macro. + */ +void GPIO_PortDisableInterrupts(GPIO_Type *base, uint32_t port, uint32_t index, uint32_t mask) +{ + if ((uint32_t)kGPIO_InterruptA == index) + { + base->INTENA[port] = base->INTENA[port] & ~mask; + } + else if ((uint32_t)kGPIO_InterruptB == index) + { + base->INTENB[port] = base->INTENB[port] & ~mask; + } + else + { + /*Should not enter here*/ + } +} + +/*! + * @brief Clears multiple pins interrupt flag. Status flags are cleared by + * writing a 1 to the corresponding bit position. + * + * @param base GPIO base pointer. + * @param port GPIO port number. + * @param index GPIO interrupt number. + * @param mask GPIO pin number macro. + */ +void GPIO_PortClearInterruptFlags(GPIO_Type *base, uint32_t port, uint32_t index, uint32_t mask) +{ + if ((uint32_t)kGPIO_InterruptA == index) + { + base->INTSTATA[port] = mask; + } + else if ((uint32_t)kGPIO_InterruptB == index) + { + base->INTSTATB[port] = mask; + } + else + { + /*Should not enter here*/ + } +} + +/*! + * @ Read port interrupt status. + * + * @param base GPIO base pointer. + * @param port GPIO port number + * @param index GPIO interrupt number. + * @retval masked GPIO status value + */ +uint32_t GPIO_PortGetInterruptStatus(GPIO_Type *base, uint32_t port, uint32_t index) +{ + uint32_t status = 0U; + + if ((uint32_t)kGPIO_InterruptA == index) + { + status = base->INTSTATA[port]; + } + else if ((uint32_t)kGPIO_InterruptB == index) + { + status = base->INTSTATB[port]; + } + else + { + /*Should not enter here*/ + } + return status; +} + +/*! + * @brief Enables the specific pin interrupt. + * + * @param base GPIO base pointer. + * @param port GPIO port number. + * @param pin GPIO pin number. + * @param index GPIO interrupt number. + */ +void GPIO_PinEnableInterrupt(GPIO_Type *base, uint32_t port, uint32_t pin, uint32_t index) +{ + if ((uint32_t)kGPIO_InterruptA == index) + { + base->INTENA[port] = base->INTENA[port] | (1UL << pin); + } + else if ((uint32_t)kGPIO_InterruptB == index) + { + base->INTENB[port] = base->INTENB[port] | (1UL << pin); + } + else + { + /*Should not enter here*/ + } +} + +/*! + * @brief Disables the specific pin interrupt. + * + * @param base GPIO base pointer. + * @param port GPIO port number. + * @param pin GPIO pin number. + * @param index GPIO interrupt number. + */ +void GPIO_PinDisableInterrupt(GPIO_Type *base, uint32_t port, uint32_t pin, uint32_t index) +{ + if ((uint32_t)kGPIO_InterruptA == index) + { + base->INTENA[port] = base->INTENA[port] & ~(1UL << pin); + } + else if ((uint32_t)kGPIO_InterruptB == index) + { + base->INTENB[port] = base->INTENB[port] & ~(1UL << pin); + } + else + { + /*Should not enter here*/ + } +} + +/*! + * @brief Clears the specific pin interrupt flag. Status flags are cleared by + * writing a 1 to the corresponding bit position. + * + * @param base GPIO base pointer. + * @param port GPIO port number. + * @param index GPIO interrupt number. + * @param mask GPIO pin number macro. + */ +void GPIO_PinClearInterruptFlag(GPIO_Type *base, uint32_t port, uint32_t pin, uint32_t index) +{ + if ((uint32_t)kGPIO_InterruptA == index) + { + base->INTSTATA[port] = 1UL << pin; + } + else if ((uint32_t)kGPIO_InterruptB == index) + { + base->INTSTATB[port] = 1UL << pin; + } + else + { + /*Should not enter here*/ + } +} +#endif /* FSL_FEATURE_GPIO_HAS_INTERRUPT */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_gpio.h b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_gpio.h new file mode 100644 index 0000000000..50a33f8920 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_gpio.h @@ -0,0 +1,364 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _LPC_GPIO_H_ +#define _LPC_GPIO_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup lpc_gpio + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief LPC GPIO driver version. */ +#define FSL_GPIO_DRIVER_VERSION (MAKE_VERSION(2, 1, 7)) +/*@}*/ + +/*! @brief LPC GPIO direction definition */ +typedef enum _gpio_pin_direction +{ + kGPIO_DigitalInput = 0U, /*!< Set current pin as digital input*/ + kGPIO_DigitalOutput = 1U, /*!< Set current pin as digital output*/ +} gpio_pin_direction_t; + +/*! + * @brief The GPIO pin configuration structure. + * + * Every pin can only be configured as either output pin or input pin at a time. + * If configured as a input pin, then leave the outputConfig unused. + */ +typedef struct _gpio_pin_config +{ + gpio_pin_direction_t pinDirection; /*!< GPIO direction, input or output */ + /* Output configurations, please ignore if configured as a input one */ + uint8_t outputLogic; /*!< Set default output logic, no use in input */ +} gpio_pin_config_t; + +#if (defined(FSL_FEATURE_GPIO_HAS_INTERRUPT) && FSL_FEATURE_GPIO_HAS_INTERRUPT) +#define GPIO_PIN_INT_LEVEL 0x00U +#define GPIO_PIN_INT_EDGE 0x01U + +#define PINT_PIN_INT_HIGH_OR_RISE_TRIGGER 0x00U +#define PINT_PIN_INT_LOW_OR_FALL_TRIGGER 0x01U + +/*! @brief GPIO Pin Interrupt enable mode */ +typedef enum _gpio_pin_enable_mode +{ + kGPIO_PinIntEnableLevel = GPIO_PIN_INT_LEVEL, /*!< Generate Pin Interrupt on level mode */ + kGPIO_PinIntEnableEdge = GPIO_PIN_INT_EDGE /*!< Generate Pin Interrupt on edge mode */ +} gpio_pin_enable_mode_t; + +/*! @brief GPIO Pin Interrupt enable polarity */ +typedef enum _gpio_pin_enable_polarity +{ + kGPIO_PinIntEnableHighOrRise = + PINT_PIN_INT_HIGH_OR_RISE_TRIGGER, /*!< Generate Pin Interrupt on high level or rising edge */ + kGPIO_PinIntEnableLowOrFall = + PINT_PIN_INT_LOW_OR_FALL_TRIGGER /*!< Generate Pin Interrupt on low level or falling edge */ +} gpio_pin_enable_polarity_t; + +/*! @brief LPC GPIO interrupt index definition */ +typedef enum _gpio_interrupt_index +{ + kGPIO_InterruptA = 0U, /*!< Set current pin as interrupt A*/ + kGPIO_InterruptB = 1U, /*!< Set current pin as interrupt B*/ +} gpio_interrupt_index_t; + +/*! @brief Configures the interrupt generation condition. */ +typedef struct _gpio_interrupt_config +{ + uint8_t mode; /* The trigger mode of GPIO interrupts */ + uint8_t polarity; /* The polarity of GPIO interrupts */ +} gpio_interrupt_config_t; +#endif + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif + +/*! @name GPIO Configuration */ +/*@{*/ + +/*! + * @brief Initializes the GPIO peripheral. + * + * This function ungates the GPIO clock. + * + * @param base GPIO peripheral base pointer. + * @param port GPIO port number. + */ +void GPIO_PortInit(GPIO_Type *base, uint32_t port); + +/*! + * @brief Initializes a GPIO pin used by the board. + * + * To initialize the GPIO, define a pin configuration, either input or output, in the user file. + * Then, call the GPIO_PinInit() function. + * + * This is an example to define an input pin or output pin configuration: + * @code + * Define a digital input pin configuration, + * gpio_pin_config_t config = + * { + * kGPIO_DigitalInput, + * 0, + * } + * Define a digital output pin configuration, + * gpio_pin_config_t config = + * { + * kGPIO_DigitalOutput, + * 0, + * } + * @endcode + * + * @param base GPIO peripheral base pointer(Typically GPIO) + * @param port GPIO port number + * @param pin GPIO pin number + * @param config GPIO pin configuration pointer + */ +void GPIO_PinInit(GPIO_Type *base, uint32_t port, uint32_t pin, const gpio_pin_config_t *config); + +/*@}*/ + +/*! @name GPIO Output Operations */ +/*@{*/ + +/*! + * @brief Sets the output level of the one GPIO pin to the logic 1 or 0. + * + * @param base GPIO peripheral base pointer(Typically GPIO) + * @param port GPIO port number + * @param pin GPIO pin number + * @param output GPIO pin output logic level. + * - 0: corresponding pin output low-logic level. + * - 1: corresponding pin output high-logic level. + */ +static inline void GPIO_PinWrite(GPIO_Type *base, uint32_t port, uint32_t pin, uint8_t output) +{ + base->B[port][pin] = output; +} + +/*@}*/ +/*! @name GPIO Input Operations */ +/*@{*/ + +/*! + * @brief Reads the current input value of the GPIO PIN. + * + * @param base GPIO peripheral base pointer(Typically GPIO) + * @param port GPIO port number + * @param pin GPIO pin number + * @retval GPIO port input value + * - 0: corresponding pin input low-logic level. + * - 1: corresponding pin input high-logic level. + */ +static inline uint32_t GPIO_PinRead(GPIO_Type *base, uint32_t port, uint32_t pin) +{ + return (uint32_t)base->B[port][pin]; +} + +/*@}*/ + +/*! + * @brief Sets the output level of the multiple GPIO pins to the logic 1. + * + * @param base GPIO peripheral base pointer(Typically GPIO) + * @param port GPIO port number + * @param mask GPIO pin number macro + */ +static inline void GPIO_PortSet(GPIO_Type *base, uint32_t port, uint32_t mask) +{ + base->SET[port] = mask; +} + +/*! + * @brief Sets the output level of the multiple GPIO pins to the logic 0. + * + * @param base GPIO peripheral base pointer(Typically GPIO) + * @param port GPIO port number + * @param mask GPIO pin number macro + */ +static inline void GPIO_PortClear(GPIO_Type *base, uint32_t port, uint32_t mask) +{ + base->CLR[port] = mask; +} + +/*! + * @brief Reverses current output logic of the multiple GPIO pins. + * + * @param base GPIO peripheral base pointer(Typically GPIO) + * @param port GPIO port number + * @param mask GPIO pin number macro + */ +static inline void GPIO_PortToggle(GPIO_Type *base, uint32_t port, uint32_t mask) +{ + base->NOT[port] = mask; +} + +/*@}*/ + +/*! + * @brief Reads the current input value of the whole GPIO port. + * + * @param base GPIO peripheral base pointer(Typically GPIO) + * @param port GPIO port number + */ +static inline uint32_t GPIO_PortRead(GPIO_Type *base, uint32_t port) +{ + return (uint32_t)base->PIN[port]; +} + +/*@}*/ +/*! @name GPIO Mask Operations */ +/*@{*/ + +/*! + * @brief Sets port mask, 0 - enable pin, 1 - disable pin. + * + * @param base GPIO peripheral base pointer(Typically GPIO) + * @param port GPIO port number + * @param mask GPIO pin number macro + */ +static inline void GPIO_PortMaskedSet(GPIO_Type *base, uint32_t port, uint32_t mask) +{ + base->MASK[port] = mask; +} + +/*! + * @brief Sets the output level of the masked GPIO port. Only pins enabled by GPIO_SetPortMask() will be affected. + * + * @param base GPIO peripheral base pointer(Typically GPIO) + * @param port GPIO port number + * @param output GPIO port output value. + */ +static inline void GPIO_PortMaskedWrite(GPIO_Type *base, uint32_t port, uint32_t output) +{ + base->MPIN[port] = output; +} + +/*! + * @brief Reads the current input value of the masked GPIO port. Only pins enabled by GPIO_SetPortMask() will be + * affected. + * + * @param base GPIO peripheral base pointer(Typically GPIO) + * @param port GPIO port number + * @retval masked GPIO port value + */ +static inline uint32_t GPIO_PortMaskedRead(GPIO_Type *base, uint32_t port) +{ + return (uint32_t)base->MPIN[port]; +} + +#if defined(FSL_FEATURE_GPIO_HAS_INTERRUPT) && FSL_FEATURE_GPIO_HAS_INTERRUPT +/*! + * @brief Set the configuration of pin interrupt. + * + * @param base GPIO base pointer. + * @param port GPIO port number + * @param pin GPIO pin number. + * @param config GPIO pin interrupt configuration.. + */ +void GPIO_SetPinInterruptConfig(GPIO_Type *base, uint32_t port, uint32_t pin, gpio_interrupt_config_t *config); + +/*! + * @brief Enables multiple pins interrupt. + * + * @param base GPIO base pointer. + * @param port GPIO port number. + * @param index GPIO interrupt number. + * @param mask GPIO pin number macro. + */ +void GPIO_PortEnableInterrupts(GPIO_Type *base, uint32_t port, uint32_t index, uint32_t mask); + +/*! + * @brief Disables multiple pins interrupt. + * + * @param base GPIO base pointer. + * @param port GPIO port number. + * @param index GPIO interrupt number. + * @param mask GPIO pin number macro. + */ +void GPIO_PortDisableInterrupts(GPIO_Type *base, uint32_t port, uint32_t index, uint32_t mask); + +/*! + * @brief Clears pin interrupt flag. Status flags are cleared by + * writing a 1 to the corresponding bit position. + * + * @param base GPIO base pointer. + * @param port GPIO port number. + * @param index GPIO interrupt number. + * @param mask GPIO pin number macro. + */ +void GPIO_PortClearInterruptFlags(GPIO_Type *base, uint32_t port, uint32_t index, uint32_t mask); + +/*! + * @ Read port interrupt status. + * + * @param base GPIO base pointer. + * @param port GPIO port number + * @param index GPIO interrupt number. + * @retval masked GPIO status value + */ +uint32_t GPIO_PortGetInterruptStatus(GPIO_Type *base, uint32_t port, uint32_t index); + +/*! + * @brief Enables the specific pin interrupt. + * + * @param base GPIO base pointer. + * @param port GPIO port number. + * @param pin GPIO pin number. + * @param index GPIO interrupt number. + */ +void GPIO_PinEnableInterrupt(GPIO_Type *base, uint32_t port, uint32_t pin, uint32_t index); + +/*! + * @brief Disables the specific pin interrupt. + * + * @param base GPIO base pointer. + * @param port GPIO port number. + * @param pin GPIO pin number. + * @param index GPIO interrupt number. + */ +void GPIO_PinDisableInterrupt(GPIO_Type *base, uint32_t port, uint32_t pin, uint32_t index); + +/*! + * @brief Clears the specific pin interrupt flag. Status flags are cleared by + * writing a 1 to the corresponding bit position. + * + * @param base GPIO base pointer. + * @param port GPIO port number. + * @param pin GPIO pin number. + * @param index GPIO interrupt number. + */ +void GPIO_PinClearInterruptFlag(GPIO_Type *base, uint32_t port, uint32_t pin, uint32_t index); + +#endif /* FSL_FEATURE_GPIO_HAS_INTERRUPT */ + +/*@}*/ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ + +#endif /* _LPC_GPIO_H_*/ diff --git a/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_hashcrypt.c b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_hashcrypt.c new file mode 100644 index 0000000000..85943dcfdd --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_hashcrypt.c @@ -0,0 +1,1726 @@ +/* + * Copyright 2017-2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_hashcrypt.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.hashcrypt" +#endif + +/******************************************************************************* + * Definitions + *******************************************************************************/ + +/*!< SHA-1 and SHA-256 block size */ +#define SHA_BLOCK_SIZE 64U +/*!< max number of blocks that can be proccessed in one run (master mode) */ +#define SHA_MASTER_MAX_BLOCKS 2048U + +/*!< Use standard C library memcpy */ +#define hashcrypt_memcpy memcpy + +/*! Internal states of the HASH creation process */ +typedef enum _hashcrypt_sha_algo_state +{ + kHASHCRYPT_HashInit = 1u, /*!< Init state, the NEW bit in SHA Control register has not been written yet. */ + kHASHCRYPT_HashUpdate, /*!< Update state, DIGEST registers contain running hash, NEW bit in SHA control register has + been written. */ +} hashcrypt_sha_algo_state_t; + +/*! 64-byte block represented as byte array of 16 32-bit words */ +typedef union _sha_hash_block +{ + uint32_t w[SHA_BLOCK_SIZE / 4]; /*!< array of 32-bit words */ + uint8_t b[SHA_BLOCK_SIZE]; /*!< byte array */ +} hashcrypt_sha_block_t; + +/*! internal sha context structure */ +typedef struct _hashcrypt_sha_ctx_internal +{ + hashcrypt_sha_block_t blk; /*!< memory buffer. only full 64-byte blocks are written to SHA during hash updates */ + size_t blksz; /*!< number of valid bytes in memory buffer */ + hashcrypt_algo_t algo; /*!< selected algorithm from the set of supported algorithms */ + hashcrypt_sha_algo_state_t state; /*!< finite machine state of the hash software process */ + size_t fullMessageSize; /*!< track message size during SHA_Update(). The value is used for padding. */ + uint32_t remainingBlcks; /*!< number of remaining blocks to process in AHB master mode */ + hashcrypt_callback_t hashCallback; /*!< pointer to HASH callback function */ + void + *userData; /*!< user data to be passed as an argument to callback function, once callback is invoked from isr */ +#if defined(FSL_FEATURE_HASHCRYPT_HAS_RELOAD_FEATURE) && (FSL_FEATURE_HASHCRYPT_HAS_RELOAD_FEATURE > 0) + uint32_t runningHash[8]; /*!< running hash. up to SHA-256, that is 32 bytes. */ +#endif +} hashcrypt_sha_ctx_internal_t; + +#if defined(FSL_FEATURE_HASHCRYPT_HAS_RELOAD_FEATURE) && (FSL_FEATURE_HASHCRYPT_HAS_RELOAD_FEATURE > 0) +#define SHA1_LEN 5u +#define SHA256_LEN 8u +#endif + +/*!< SHA-1 and SHA-256 digest length in bytes */ +enum _hashcrypt_sha_digest_len +{ + kHASHCRYPT_OutLenSha1 = 20u, + kHASHCRYPT_OutLenSha256 = 32u, +}; + +/*!< pointer to hash context structure used by isr */ +static hashcrypt_hash_ctx_t *s_ctx; + +/*!< macro for checking build time condition. It is used to assure the hashcrypt_sha_ctx_internal_t can fit into + * hashcrypt_hash_ctx_t */ +#define BUILD_ASSERT(condition, msg) extern int msg[1 - 2 * (!(condition))] __attribute__((unused)) + +/******************************************************************************* + * Code + ******************************************************************************/ + +/*! + * @brief Swap bytes withing 32-bit word. + * + * This function changes endianess of a 32-bit word. + * + * @param in 32-bit unsigned integer + * @return 32-bit unsigned integer with different endianess (big endian to little endian and vice versa). + */ + +#define swap_bytes(in) __REV(in) + +/*! + * @brief Increment a 16 byte integer. + * + * This function increments by one a 16 byte integer. + * + * @param input Pointer to a 16 byte integer to be incremented by one. + */ +static void ctrIncrement(uint8_t *input) +{ + int i = 15; + while (input[i] == (uint8_t)0xFFu) + { + input[i] = (uint8_t)0x00u; + i--; + if (i < 0) + { + return; + } + } + + if (i >= 0) + { + input[i] += (uint8_t)1u; + } +} + +/*! + * @brief Reads an unaligned word. + * + * This function creates a 32-bit word from an input array of four bytes. + * + * @param src Input array of four bytes. The array can start at any address in memory. + * @return 32-bit unsigned int created from the input byte array. + */ + +/* Force lower optimization for Keil, otherwise it replaces inline LDR with LDM */ +#if defined(__CC_ARM) +#pragma push +#pragma O0 +#endif + +static inline uint32_t hashcrypt_get_word_from_unaligned(const uint8_t *srcAddr) +{ +#if (!(defined(__CORTEX_M)) || (defined(__CORTEX_M) && (__CORTEX_M == 0))) + register const uint8_t *src = srcAddr; + /* Cortex M0 does not support misaligned loads */ + if (0U != ((uint32_t)src & 0x3u)) + { + union _align_bytes_t + { + uint32_t word; + uint8_t byte[sizeof(uint32_t)]; + } my_bytes; + + my_bytes.byte[0] = *src; + my_bytes.byte[1] = src[1]; + my_bytes.byte[2] = src[2]; + my_bytes.byte[3] = src[3]; + return my_bytes.word; + } + else + { + /* addr aligned to 0-modulo-4 so it is safe to type cast */ + return *((const uint32_t *)(uint32_t)src); + } +#elif defined(__CC_ARM) + /* -O3 optimization in Keil 5.15 and 5.16a uses LDM instruction here (LDM r4!, {r0}) + * which is wrong, because srcAddr might be unaligned. + * LDM on unaligned address causes hard-fault. in contrary, + * LDR supports unaligned address on Cortex M4 */ + + register uint32_t retVal; + __asm + { + LDR retVal, [srcAddr] + } + return retVal; +#else + return *((const uint32_t *)(uintptr_t)srcAddr); +#endif +} + +/* End lower optimization */ +#if defined(__CC_ARM) +#pragma pop +#endif + +static status_t hashcrypt_get_key_from_unaligned_src(uint8_t *dest, const uint8_t *src, size_t size) +{ + status_t retVal = kStatus_InvalidArgument; + uint32_t i; + + /* destination is SDK driver internal workspace and it must be aligned */ + assert(0x0u == ((uint32_t)dest & 0x1u)); + if (0U != ((uint32_t)dest & 0x1u)) + { + return retVal; + } + + for (i = 0; i < ((uint32_t)size / 4u); i++) + { + ((uint32_t *)(uintptr_t)dest)[i] = hashcrypt_get_word_from_unaligned(&src[i * sizeof(uint32_t)]); + } + + return kStatus_Success; +} + +/*! + * @brief LDM to SHA engine INDATA and ALIAS registers. + * + * This function writes 16 words starting from the src address (must be word aligned) + * to the dst address. Dst address does not increment (destination is peripheral module register INDATA). + * Src address increments to load 16 consecutive words. + * + * @param dst peripheral register address (word aligned) + * @param src address of the input 512-bit block (16 words) (word aligned) + * + */ +__STATIC_FORCEINLINE void hashcrypt_sha_ldm_stm_16_words(HASHCRYPT_Type *base, const uint32_t *src) +{ + /* Data Synchronization Barrier */ + __DSB(); + /* + typedef struct _one_block + { + uint32_t a[8]; + } one_block_t; + + volatile one_block_t *ldst = (void *)(uintptr_t)(&base->INDATA); + one_block_t *lsrc = (void *)(uintptr_t)src; + *ldst = lsrc[0]; + *ldst = lsrc[1]; + */ + + /* Data Synchronization Barrier prevent compiler from reordering memory write when -O2 or higher is used. */ + /* The address is passed to the crypto engine for hashing below, therefore out */ + /* of order memory write due to compiler optimization must be prevented. */ + __DSB(); + + base->MEMADDR = HASHCRYPT_MEMADDR_BASE(src); + base->MEMCTRL = HASHCRYPT_MEMCTRL_MASTER(1) | HASHCRYPT_MEMCTRL_COUNT(1); + + __DSB(); +} + +/*! + * @brief Loads data to Hashcrypt engine INDATA register. + * + * This function writes desired number of bytes starting from the src address + * to the dst address. Dst address does not increment (destination is peripheral module register INDATA). + * Src address increments to load consecutive words. + * + * @param src address of the input block + * @param size number of bytes to write + * + */ +__STATIC_INLINE void hashcrypt_load_data(HASHCRYPT_Type *base, uint32_t *src, size_t size) +{ + /* 16 bytes aligned input block */ + uint32_t __attribute__((aligned(4))) inAlign[HASHCRYPT_AES_BLOCK_SIZE / sizeof(uint32_t)]; + uint32_t *in; + uint8_t i; + + in = src; + /* Check if address of src data is aligned */ + if ((0U != ((uint32_t)in & 3U))) + { + for (i = 0; i < ((uint32_t)size / 4U); i++) + { + inAlign[i] = hashcrypt_get_word_from_unaligned((uint8_t *)&src[i]); + } + in = &inAlign[0]; + } + + if (size >= sizeof(uint32_t)) + { + base->INDATA = in[0]; + size -= sizeof(uint32_t); + } + + for (uint32_t j = 0; j < size / 4U; j++) + { + base->ALIAS[j] = in[j + 1U]; + } +} + +/*! + * @brief Checks availability of HW AES key. + * + * This function checks if the AES key is present at dedicated hardware bus + * and can be used at actual security level. + * + * @param base HASHCRYPT peripheral base address + * @param handle Handle used for this request. + * @return kStatus_Success if available, kStatus_Fail otherwise. + * + */ +static status_t hashcrypt_check_need_key(HASHCRYPT_Type *base, hashcrypt_handle_t *handle) +{ + if (handle->keyType == kHASHCRYPT_SecretKey) + { + volatile uint32_t wait = 50u; + /* wait until STATUS register is non-zero */ + while ((wait > 0U) && (base->STATUS == 0U)) + { + wait--; + } + /* if NEEDKEY bit is not set, HW key is available */ + if (0U == (base->STATUS & HASHCRYPT_STATUS_NEEDKEY_MASK)) + { + return kStatus_Success; + } + /* NEEDKEY is set, HW key is not available */ + return kStatus_Fail; + } + else + { + /* in case user key is used, return success */ + return kStatus_Success; + } +} + +/*! + * @brief Read OUTDATA registers. + * + * This function copies OUTDATA to output buffer. + * + * @param base Hachcrypt peripheral base address. + * @param[out] output Output buffer. + * @param Number of bytes to copy. + */ +static void hashcrypt_get_data(HASHCRYPT_Type *base, uint32_t *output, size_t outputSize) +{ + uint32_t digest[8]; + + while (0U == (base->STATUS & HASHCRYPT_STATUS_DIGEST_MASK)) + { + } + + /* Data Synchronization Barrier */ + __DSB(); + + for (int i = 0; i < 8; i++) + { + digest[i] = swap_bytes(base->DIGEST0[i]); + } + + if (outputSize > sizeof(digest)) + { + outputSize = sizeof(digest); + } + (void)hashcrypt_memcpy(output, digest, outputSize); +} + +/*! + * @brief Initialize the Hashcrypt engine for new operation. + * + * This function sets NEW and MODE fields in Hashcrypt Control register to start new operation. + * + * @param base Hashcrypt peripheral base address. + * @param hashcrypt_algo_t Internal context. + */ +static void hashcrypt_engine_init(HASHCRYPT_Type *base, hashcrypt_algo_t algo) +{ + /* NEW bit must be set before we switch from previous mode otherwise new mode will not work correctly */ + base->CTRL = HASHCRYPT_CTRL_NEW_HASH(1); + base->CTRL = HASHCRYPT_CTRL_MODE(algo) | HASHCRYPT_CTRL_NEW_HASH(1); +} + +/*! + * @brief Deinitialization of the Hashcrypt engine. + * + * This function sets MODE field in Hashcrypt Control register to zero - disabled. + * This reduces power consumption of HASHCRYPT. + * + * @param base Hashcrypt peripheral base address. + */ +static inline void hashcrypt_engine_deinit(HASHCRYPT_Type *base) +{ + base->CTRL &= ~(HASHCRYPT_CTRL_MODE_MASK); +} + +/*! + * @brief Loads user key to INDATA register. + * + * This function writes user key stored in handle into HashCrypt INDATA register. + * + * @param base Hashcrypt peripheral base address. + * @param handle Handle used for this request. + */ +static void hashcrypt_aes_load_userKey(HASHCRYPT_Type *base, hashcrypt_handle_t *handle) +{ + size_t keySize = 0; + + switch (handle->keySize) + { + case kHASHCRYPT_Aes128: + keySize = 16; + break; + case kHASHCRYPT_Aes192: + keySize = 24; + break; + case kHASHCRYPT_Aes256: + keySize = 32; + break; + default: + /* All the cases have been listed above, the default clause should not be reached. */ + break; + } + if (keySize == 0U) + { + return; + } + hashcrypt_load_data(base, &handle->keyWord[0], keySize); +} + +/*! + * @brief Performs AES encryption/decryption of one data block. + * + * This function encrypts/decrypts one block of data with specified size. + * + * @param base Hashcrypt peripheral base address. + * @param input input data + * @param output output data + * @param size size of data block to process in bytes (must be 16bytes multiple). + */ +static status_t hashcrypt_aes_one_block_aligned(HASHCRYPT_Type *base, + const uint8_t *input, + uint8_t *output, + size_t size) +{ + status_t status = kStatus_Fail; + uint32_t idx = 0; + + base->MEMADDR = HASHCRYPT_MEMADDR_BASE(input); + base->MEMCTRL = HASHCRYPT_MEMCTRL_MASTER(1) | HASHCRYPT_MEMCTRL_COUNT(size / 16U); + while (size >= HASHCRYPT_AES_BLOCK_SIZE) + { + /* Get result */ + while (0U == (base->STATUS & HASHCRYPT_STATUS_DIGEST_MASK)) + { + } + + for (int i = 0; i < 4; i++) + { + ((uint32_t *)(uintptr_t)output + idx)[i] = swap_bytes(base->DIGEST0[i]); + } + + idx += HASHCRYPT_AES_BLOCK_SIZE / 4U; + size -= HASHCRYPT_AES_BLOCK_SIZE; + } + + if (0U == (base->STATUS & HASHCRYPT_STATUS_ERROR_MASK)) + { + status = kStatus_Success; + } + + return status; +} + +/*! + * @brief Performs AES encryption/decryption of one data block. + * + * This function encrypts/decrypts one block of data with specified size. + * + * @param base Hashcrypt peripheral base address. + * @param input input data + * @param output output data + * @param size size of data block to process in bytes (must be 16bytes multiple). + */ +static status_t hashcrypt_aes_one_block_unaligned(HASHCRYPT_Type *base, + const uint8_t *input, + uint8_t *output, + size_t size) +{ + status_t status = kStatus_Fail; + + /* we use AHB master mode as much as possible */ + /* however, it can work only with aligned input data */ + /* so, if unaligned, we do memcpy to temp buffer on stack, which is aligned, and use AHB mode to read data in */ + /* then we read data back to it and do memcpy to the output buffer */ + uint32_t temp[256 / sizeof(uint32_t)]; + int cnt = 0; + while (size != 0U) + { + size_t actSz = size >= 256u ? 256u : size; + size_t actSzOrig = actSz; + (void)memcpy(temp, (const uint32_t *)(uintptr_t)(input + 256 * cnt), actSz); + size -= actSz; + base->MEMADDR = HASHCRYPT_MEMADDR_BASE(temp); + base->MEMCTRL = HASHCRYPT_MEMCTRL_MASTER(1) | HASHCRYPT_MEMCTRL_COUNT(actSz / 16U); + uint32_t outidx = 0; + while (actSz != 0U) + { + while (0U == (base->STATUS & HASHCRYPT_STATUS_DIGEST_MASK)) + { + } + for (int i = 0; i < 4; i++) + { + (temp + outidx)[i] = swap_bytes(base->DIGEST0[i]); + } + outidx += HASHCRYPT_AES_BLOCK_SIZE / 4U; + actSz -= HASHCRYPT_AES_BLOCK_SIZE; + } + (void)memcpy(output + 256 * cnt, (const uint8_t *)(uintptr_t)temp, actSzOrig); + cnt++; + } + + if (0U == (base->STATUS & HASHCRYPT_STATUS_ERROR_MASK)) + { + status = kStatus_Success; + } + + return status; +} + +/*! + * @brief Performs AES encryption/decryption of one data block. + * + * This function encrypts/decrypts one block of data with specified size. + * + * @param base Hashcrypt peripheral base address. + * @param input input data + * @param output output data + * @param size size of data block to process in bytes (must be 16bytes multiple). + */ +static status_t hashcrypt_aes_one_block(HASHCRYPT_Type *base, const uint8_t *input, uint8_t *output, size_t size) +{ + status_t status = kStatus_Fail; + + /*MEMCTRL bitfield for COUNT is 11 bits, and this limits the number of blocks to process in one Master run to 2047 + (2^11 -1) blocks . Each block is 16bytes long, so biggest data size which can we do in one Master run is (2047 + blocks *16 bytes) = 32752 So, when size is overflowing HASHCRYPT_MEMCTRL_COUNT field of MEMCTRL register, we split + our data into more smaller chunks */ + + if (size > 32752U) + + { + size_t numBlock = size / 32752U; /* number of blocks, each block is processed in one run*/ + size_t remainingSize = size - (numBlock * 32752U); /* size of last block */ + + if ((0U != ((uint32_t)input & 0x3u)) || (0U != ((uint32_t)output & 0x3u))) /* If data is unaligned*/ + { + for (uint32_t i = 0; i < numBlock; i++) + { + status = hashcrypt_aes_one_block_unaligned(base, input, output, 32752U); + input += 32752U; + output += 32752U; + } + status = hashcrypt_aes_one_block_unaligned(base, input, output, remainingSize); + } + else /* If data is aligned*/ + { + for (uint32_t i = 0; i < numBlock; i++) + { + status = hashcrypt_aes_one_block_aligned(base, input, output, 32752U); + input += 32752U; + output += 32752U; + } + status = hashcrypt_aes_one_block_aligned(base, input, output, remainingSize); + } + } + + else /* size is less than COUNT field of MEMCTRL register so we can process all data at once */ + { + /* we use AHB master mode as much as possible */ + /* however, it can work only with aligned input data */ + /* so, if unaligned, we do memcpy to temp buffer on stack, which is aligned, and use AHB mode to read data in */ + /* then we read data back to it and do memcpy to the output buffer */ + if ((0U != ((uint32_t)input & 0x3u)) || (0U != ((uint32_t)output & 0x3u))) + { + status = hashcrypt_aes_one_block_unaligned(base, input, output, size); + } + else + { + status = hashcrypt_aes_one_block_aligned(base, input, output, size); + } + } + return status; +} + +/*! + * @brief Check validity of algoritm. + * + * This function checks the validity of input argument. + * + * @param algo Tested algorithm value. + * @return kStatus_Success if valid, kStatus_InvalidArgument otherwise. + */ +static status_t hashcrypt_sha_check_input_alg(HASHCRYPT_Type *base, hashcrypt_algo_t algo) +{ + if ((algo == kHASHCRYPT_Sha1) || (algo == kHASHCRYPT_Sha256)) + { + return kStatus_Success; + } + + return kStatus_InvalidArgument; +} + +/*! + * @brief Check validity of input arguments. + * + * This function checks the validity of input arguments. + * + * @param base SHA peripheral base address. + * @param ctx Memory buffer given by user application where the SHA_Init/SHA_Update/SHA_Finish store context. + * @param algo Tested algorithm value. + * @return kStatus_Success if valid, kStatus_InvalidArgument otherwise. + */ +static status_t hashcrypt_sha_check_input_args(HASHCRYPT_Type *base, hashcrypt_hash_ctx_t *ctx, hashcrypt_algo_t algo) +{ + /* Check validity of input algorithm */ + if (kStatus_Success != hashcrypt_sha_check_input_alg(base, algo)) + { + return kStatus_InvalidArgument; + } + + if ((NULL == ctx) || (NULL == base)) + { + return kStatus_InvalidArgument; + } + + return kStatus_Success; +} + +/*! + * @brief Check validity of internal software context. + * + * This function checks if the internal context structure looks correct. + * + * @param ctxInternal Internal context. + * @return kStatus_Success if valid, kStatus_InvalidArgument otherwise. + */ +static status_t hashcrypt_sha_check_context(HASHCRYPT_Type *base, hashcrypt_sha_ctx_internal_t *ctxInternal) +{ + if ((NULL == ctxInternal) || (kStatus_Success != hashcrypt_sha_check_input_alg(base, ctxInternal->algo))) + { + return kStatus_InvalidArgument; + } + return kStatus_Success; +} + +/*! + * @brief Load 512-bit block (16 words) into SHA engine. + * + * This function aligns the input block and moves it into SHA engine INDATA. + * CPU polls the WAITING bit and then moves data by using LDM and STM instructions. + * + * @param base SHA peripheral base address. + * @param blk 512-bit block + */ +static void hashcrypt_sha_one_block(HASHCRYPT_Type *base, const uint8_t *blk) +{ + uint32_t temp[SHA_BLOCK_SIZE / sizeof(uint32_t)]; + const uint32_t *actBlk; + + /* make sure the 512-bit block is word aligned */ + if (0U != ((uintptr_t)blk & 0x3u)) + { + (void)hashcrypt_memcpy(temp, (const uint32_t *)(uintptr_t)blk, SHA_BLOCK_SIZE); + actBlk = (const uint32_t *)(uintptr_t)temp; + } + else + { + actBlk = (const uint32_t *)(uintptr_t)blk; + } + + /* poll waiting. */ + while (0U == (base->STATUS & HASHCRYPT_STATUS_WAITING_MASK)) + { + } + /* feed INDATA (and ALIASes). use STM instruction. */ + hashcrypt_sha_ldm_stm_16_words(base, actBlk); +} + +/*! + * @brief Adds message to current hash. + * + * This function merges the message to fill the internal buffer, empties the internal buffer if + * it becomes full, then process all remaining message data. + * + * + * @param base SHA peripheral base address. + * @param ctxInternal Internal context. + * @param message Input message. + * @param messageSize Size of input message in bytes. + * @return kStatus_Success. + */ +static status_t hashcrypt_sha_process_message_data(HASHCRYPT_Type *base, + hashcrypt_sha_ctx_internal_t *ctxInternal, + const uint8_t *message, + size_t messageSize) +{ + /* first fill the internal buffer to full block */ + if (ctxInternal->blksz != 0U) + { + size_t toCopy = SHA_BLOCK_SIZE - ctxInternal->blksz; + (void)hashcrypt_memcpy(&ctxInternal->blk.b[ctxInternal->blksz], message, toCopy); + message += toCopy; + messageSize -= toCopy; + + /* process full internal block */ + hashcrypt_sha_one_block(base, &ctxInternal->blk.b[0]); + } + + /* process all full blocks in message[] */ + if (messageSize >= SHA_BLOCK_SIZE) + { + if (0U != ((uintptr_t)message & 0x3u)) + { + while (messageSize >= SHA_BLOCK_SIZE) + { + hashcrypt_sha_one_block(base, message); + message += SHA_BLOCK_SIZE; + messageSize -= SHA_BLOCK_SIZE; + } + } + else + { + /* poll waiting. */ + while (0U == (base->STATUS & HASHCRYPT_STATUS_WAITING_MASK)) + { + } + uint32_t blkNum = (messageSize >> 6); /* div by 64 bytes */ + uint32_t blkBytes = blkNum * 64u; /* number of bytes in 64 bytes blocks */ + __DSB(); + __ISB(); + base->MEMADDR = HASHCRYPT_MEMADDR_BASE(message); + base->MEMCTRL = HASHCRYPT_MEMCTRL_MASTER(1) | HASHCRYPT_MEMCTRL_COUNT(blkNum); + message += blkBytes; + messageSize -= blkBytes; + while (0U == (base->STATUS & HASHCRYPT_STATUS_DIGEST_MASK)) + { + } + } + } + + /* copy last incomplete message bytes into internal block */ + (void)hashcrypt_memcpy(&ctxInternal->blk.b[0], message, messageSize); + ctxInternal->blksz = messageSize; + return kStatus_Success; +} + +/*! + * @brief Finalize the running hash to make digest. + * + * This function empties the internal buffer, adds padding bits, and generates final digest. + * + * @param base SHA peripheral base address. + * @param ctxInternal Internal context. + * @return kStatus_Success. + */ +static status_t hashcrypt_sha_finalize(HASHCRYPT_Type *base, hashcrypt_sha_ctx_internal_t *ctxInternal) +{ + hashcrypt_sha_block_t lastBlock; + + (void)memset(&lastBlock, 0, sizeof(hashcrypt_sha_block_t)); + + /* this is last call, so need to flush buffered message bytes along with padding */ + if (ctxInternal->blksz <= 55u) + { + /* last data is 440 bits or less. */ + (void)hashcrypt_memcpy(&lastBlock.b[0], &ctxInternal->blk.b[0], ctxInternal->blksz); + lastBlock.b[ctxInternal->blksz] = (uint8_t)0x80U; + lastBlock.w[SHA_BLOCK_SIZE / 4U - 1U] = swap_bytes(8u * ctxInternal->fullMessageSize); + hashcrypt_sha_one_block(base, &lastBlock.b[0]); + } + else + { + if (ctxInternal->blksz < SHA_BLOCK_SIZE) + { + ctxInternal->blk.b[ctxInternal->blksz] = (uint8_t)0x80U; + for (uint32_t i = ctxInternal->blksz + 1u; i < SHA_BLOCK_SIZE; i++) + { + ctxInternal->blk.b[i] = 0; + } + } + else + { + lastBlock.b[0] = (uint8_t)0x80U; + } + + hashcrypt_sha_one_block(base, &ctxInternal->blk.b[0]); + lastBlock.w[SHA_BLOCK_SIZE / 4U - 1U] = swap_bytes(8u * ctxInternal->fullMessageSize); + hashcrypt_sha_one_block(base, &lastBlock.b[0]); + } + /* poll wait for final digest */ + while (0U == (base->STATUS & HASHCRYPT_STATUS_DIGEST_MASK)) + { + } + return kStatus_Success; +} + +static void hashcrypt_save_running_hash(HASHCRYPT_Type *base, hashcrypt_sha_ctx_internal_t *ctxInternal) +{ +#if defined(FSL_FEATURE_HASHCRYPT_HAS_RELOAD_FEATURE) && (FSL_FEATURE_HASHCRYPT_HAS_RELOAD_FEATURE > 0) + size_t len = (ctxInternal->algo == kHASHCRYPT_Sha1) ? SHA1_LEN : SHA256_LEN; + + /* Wait until digest is ready */ + while (0U == (base->STATUS & HASHCRYPT_STATUS_DIGEST_MASK)) + { + } + + /* Store partial digest to context */ + for (uint32_t i = 0; i < len; i++) + { + ctxInternal->runningHash[i] = base->DIGEST0[i]; + } +#endif +} + +static void hashcrypt_restore_running_hash(HASHCRYPT_Type *base, hashcrypt_sha_ctx_internal_t *ctxInternal) +{ +#if defined(FSL_FEATURE_HASHCRYPT_HAS_RELOAD_FEATURE) && (FSL_FEATURE_HASHCRYPT_HAS_RELOAD_FEATURE > 0) + size_t len = (ctxInternal->algo == kHASHCRYPT_Sha1) ? SHA1_LEN : SHA256_LEN; + + /* When switching from different mode, need to set NEW bit to work properly */ + if ((base->CTRL & HASHCRYPT_CTRL_MODE_MASK) != HASHCRYPT_CTRL_MODE(ctxInternal->algo)) + { + base->CTRL = HASHCRYPT_CTRL_NEW_HASH(1); + base->CTRL = HASHCRYPT_CTRL_MODE(ctxInternal->algo) | HASHCRYPT_CTRL_NEW_HASH(1); + } + /* Set RELOAD bit to allow registers to be used */ + base->CTRL |= HASHCRYPT_CTRL_RELOAD_MASK; + + /* Reload partial hash digest */ + for (uint32_t i = 0; i < len; i++) + { + base->RELOAD[i] = ctxInternal->runningHash[i]; + } + /* Clear RELOAD register before continuing */ + base->CTRL &= ~HASHCRYPT_CTRL_RELOAD_MASK; +#endif +} + +status_t HASHCRYPT_SHA(HASHCRYPT_Type *base, + hashcrypt_algo_t algo, + const uint8_t *input, + size_t inputSize, + uint8_t *output, + size_t *outputSize) +{ + hashcrypt_hash_ctx_t hashCtx; + status_t status; + + status = HASHCRYPT_SHA_Init(base, &hashCtx, algo); + if (status != kStatus_Success) + { + return status; + } + + status = HASHCRYPT_SHA_Update(base, &hashCtx, input, inputSize); + if (status != kStatus_Success) + { + return status; + } + + status = HASHCRYPT_SHA_Finish(base, &hashCtx, output, outputSize); + + return status; +} + +status_t HASHCRYPT_SHA_Init(HASHCRYPT_Type *base, hashcrypt_hash_ctx_t *ctx, hashcrypt_algo_t algo) +{ + status_t status; + + hashcrypt_sha_ctx_internal_t *ctxInternal; + /* compile time check for the correct structure size */ + BUILD_ASSERT(sizeof(hashcrypt_hash_ctx_t) >= sizeof(hashcrypt_sha_ctx_internal_t), hashcrypt_hash_ctx_t_size); + + status = hashcrypt_sha_check_input_args(base, ctx, algo); + if (status != kStatus_Success) + { + return status; + } + + /* set algorithm in context struct for later use */ + ctxInternal = (hashcrypt_sha_ctx_internal_t *)(uint32_t)ctx; + ctxInternal->algo = algo; + ctxInternal->blksz = 0u; +#ifdef HASHCRYPT_SHA_DO_WIPE_CONTEXT + for (int i = 0; i < sizeof(ctxInternal->blk.w) / sizeof(ctxInternal->blk.w[0]); i++) + { + ctxInternal->blk.w[i] = 0u; + } +#endif /* HASHCRYPT_SHA_DO_WIPE_CONTEXT */ + ctxInternal->state = kHASHCRYPT_HashInit; + ctxInternal->fullMessageSize = 0; + return kStatus_Success; +} + +status_t HASHCRYPT_SHA_Update(HASHCRYPT_Type *base, hashcrypt_hash_ctx_t *ctx, const uint8_t *input, size_t inputSize) +{ + bool isUpdateState; + status_t status; + hashcrypt_sha_ctx_internal_t *ctxInternal; + size_t blockSize; + + if (inputSize == 0U) + { + return kStatus_Success; + } + + ctxInternal = (hashcrypt_sha_ctx_internal_t *)(uint32_t)ctx; +#ifdef HASHCRYPT_SHA_DO_CHECK_CONTEXT + status = hashcrypt_sha_check_context(base, ctxInternal); + if (kStatus_Success != status) + { + return status; + } +#endif /* HASHCRYPT_SHA_DO_CHECK_CONTEXT */ + + ctxInternal->fullMessageSize += inputSize; + blockSize = SHA_BLOCK_SIZE; + /* if we are still less than 64 bytes, keep only in context */ + if ((ctxInternal->blksz + inputSize) <= blockSize) + { + (void)hashcrypt_memcpy((&ctxInternal->blk.b[0]) + ctxInternal->blksz, input, inputSize); + ctxInternal->blksz += inputSize; + return kStatus_Success; + } + else + { + isUpdateState = ctxInternal->state == kHASHCRYPT_HashUpdate; + if (!isUpdateState) + { + /* start NEW hash */ + hashcrypt_engine_init(base, ctxInternal->algo); + ctxInternal->state = kHASHCRYPT_HashUpdate; + } + else + { + hashcrypt_restore_running_hash(base, ctxInternal); + } + } + + /* process message data */ + /* Data Synchronization Barrier */ + __DSB(); + status = hashcrypt_sha_process_message_data(base, ctxInternal, input, inputSize); + hashcrypt_save_running_hash(base, ctxInternal); + return status; +} + +status_t HASHCRYPT_SHA_Finish(HASHCRYPT_Type *base, hashcrypt_hash_ctx_t *ctx, uint8_t *output, size_t *outputSize) +{ + size_t algOutSize = 0; + status_t status; + hashcrypt_sha_ctx_internal_t *ctxInternal; +#ifdef HASHCRYPT_SHA_DO_CHECK_CONTEXT + uint32_t *ctxW; + uint32_t i; +#endif /* HASHCRYPT_SHA_DO_CHECK_CONTEXT */ + + if (output == NULL) + { + return kStatus_InvalidArgument; + } + + ctxInternal = (hashcrypt_sha_ctx_internal_t *)(uint32_t)ctx; +#ifdef HASHCRYPT_SHA_DO_CHECK_CONTEXT + status = hashcrypt_sha_check_context(base, ctxInternal); + if (kStatus_Success != status) + { + return status; + } +#endif /* HASHCRYPT_SHA_DO_CHECK_CONTEXT */ + + if (ctxInternal->state == kHASHCRYPT_HashInit) + { + hashcrypt_engine_init(base, ctxInternal->algo); + } + else + { + hashcrypt_restore_running_hash(base, ctxInternal); + } + + size_t outSize = 0u; + + /* compute algorithm output length */ + switch (ctxInternal->algo) + { + case kHASHCRYPT_Sha1: + outSize = (size_t)kHASHCRYPT_OutLenSha1; + break; + case kHASHCRYPT_Sha256: + outSize = (size_t)kHASHCRYPT_OutLenSha256; + break; + default: + /* All the cases have been listed above, the default clause should not be reached. */ + break; + } + algOutSize = outSize; + + /* flush message last incomplete block, if there is any, and add padding bits */ + status = hashcrypt_sha_finalize(base, ctxInternal); + + if (outputSize != NULL) + { + if (algOutSize < *outputSize) + { + *outputSize = algOutSize; + } + else + { + algOutSize = *outputSize; + } + } + + hashcrypt_get_data(base, (uint32_t *)(uintptr_t)output, algOutSize); + +#ifdef HASHCRYPT_SHA_DO_WIPE_CONTEXT + ctxW = (uint32_t *)ctx; + for (i = 0; i < HASHCRYPT_HASH_CTX_SIZE; i++) + { + ctxW[i] = 0u; + } +#endif /* HASHCRYPT_SHA_DO_WIPE_CONTEXT */ + return status; +} + +void HASHCRYPT_SHA_SetCallback(HASHCRYPT_Type *base, + hashcrypt_hash_ctx_t *ctx, + hashcrypt_callback_t callback, + void *userData) +{ + hashcrypt_sha_ctx_internal_t *ctxInternal; + + s_ctx = ctx; + ctxInternal = (hashcrypt_sha_ctx_internal_t *)(uint32_t)ctx; + ctxInternal->hashCallback = callback; + ctxInternal->userData = userData; + + (void)EnableIRQ(HASHCRYPT_IRQn); +} + +status_t HASHCRYPT_SHA_UpdateNonBlocking(HASHCRYPT_Type *base, + hashcrypt_hash_ctx_t *ctx, + const uint8_t *input, + size_t inputSize) +{ + hashcrypt_sha_ctx_internal_t *ctxInternal; + uint32_t numBlocks; + status_t status; + + if (inputSize == 0U) + { + return kStatus_Success; + } + + if (0U != ((uintptr_t)input & 0x3U)) + { + return kStatus_Fail; + } + + ctxInternal = (hashcrypt_sha_ctx_internal_t *)(uint32_t)ctx; + status = hashcrypt_sha_check_context(base, ctxInternal); + if (kStatus_Success != status) + { + return status; + } + + ctxInternal->fullMessageSize = inputSize; + ctxInternal->remainingBlcks = inputSize / SHA_BLOCK_SIZE; + ctxInternal->blksz = inputSize % SHA_BLOCK_SIZE; + + /* copy last incomplete block to context */ + if ((ctxInternal->blksz > 0U) && (ctxInternal->blksz <= SHA_BLOCK_SIZE)) + { + (void)hashcrypt_memcpy((&ctxInternal->blk.b[0]), input + SHA_BLOCK_SIZE * ctxInternal->remainingBlcks, + ctxInternal->blksz); + } + + if (ctxInternal->remainingBlcks >= SHA_MASTER_MAX_BLOCKS) + { + numBlocks = SHA_MASTER_MAX_BLOCKS - 1U; + } + else + { + numBlocks = ctxInternal->remainingBlcks; + } + /* update remainingBlks so that ISR can run another hash if necessary */ + ctxInternal->remainingBlcks -= numBlocks; + + /* compute hash using AHB Master mode for full blocks */ + if (numBlocks > 0U) + { + ctxInternal->state = kHASHCRYPT_HashUpdate; + hashcrypt_engine_init(base, ctxInternal->algo); + + /* Enable digest and error interrupts and start hash */ + base->INTENSET = HASHCRYPT_INTENCLR_DIGEST_MASK | HASHCRYPT_INTENCLR_ERROR_MASK; + base->MEMADDR = HASHCRYPT_MEMADDR_BASE(input); + base->MEMCTRL = HASHCRYPT_MEMCTRL_MASTER(1) | HASHCRYPT_MEMCTRL_COUNT(numBlocks); + } + /* no full blocks, invoke callback directly */ + else + { + ctxInternal->hashCallback(HASHCRYPT, ctx, status, ctxInternal->userData); + } + + return status; +} + +status_t HASHCRYPT_AES_SetKey(HASHCRYPT_Type *base, hashcrypt_handle_t *handle, const uint8_t *key, size_t keySize) +{ + status_t retVal = kStatus_InvalidArgument; + + switch (keySize) + { + case 16: + handle->keySize = kHASHCRYPT_Aes128; + break; + case 24: + handle->keySize = kHASHCRYPT_Aes192; + break; + case 32: + handle->keySize = kHASHCRYPT_Aes256; + break; + default: + handle->keySize = kHASHCRYPT_InvalidKey; + break; + } + + if (handle->keySize == kHASHCRYPT_InvalidKey) + { + return retVal; + } + + if (handle->keyType == kHASHCRYPT_SecretKey) + { + /* for kHASHCRYPT_SecretKey just return Success */ + retVal = kStatus_Success; + } + else if (handle->keyType == kHASHCRYPT_UserKey) + { + retVal = hashcrypt_get_key_from_unaligned_src((uint8_t *)&handle->keyWord[0], key, keySize); + } + else + { + retVal = kStatus_InvalidArgument; + } + + return retVal; +} + +status_t HASHCRYPT_AES_EncryptEcb( + HASHCRYPT_Type *base, hashcrypt_handle_t *handle, const uint8_t *plaintext, uint8_t *ciphertext, size_t size) +{ + status_t status = kStatus_Fail; + + if ((0U != (size % 16u)) || (handle->keySize == kHASHCRYPT_InvalidKey)) + { + return kStatus_InvalidArgument; + } + + uint32_t keyType = (handle->keyType == kHASHCRYPT_UserKey) ? 0U : 1u; + base->CRYPTCFG = HASHCRYPT_CRYPTCFG_AESMODE(kHASHCRYPT_AesEcb) | HASHCRYPT_CRYPTCFG_AESDECRYPT(AES_ENCRYPT) | + HASHCRYPT_CRYPTCFG_AESSECRET(keyType) | HASHCRYPT_CRYPTCFG_AESKEYSZ(handle->keySize) | + HASHCRYPT_CRYPTCFG_MSW1ST_OUT(1) | HASHCRYPT_CRYPTCFG_SWAPKEY(1) | HASHCRYPT_CRYPTCFG_SWAPDAT(1) | + HASHCRYPT_CRYPTCFG_MSW1ST(1); + + hashcrypt_engine_init(base, kHASHCRYPT_Aes); + + /* in case of HW AES key, check if it is available */ + if (hashcrypt_check_need_key(base, handle) != kStatus_Success) + { + hashcrypt_engine_deinit(base); + return kStatus_Fail; + } + + /* load key if kHASHCRYPT_UserKey is selected */ + if (handle->keyType == kHASHCRYPT_UserKey) + { + hashcrypt_aes_load_userKey(base, handle); + } + + /* load message and get result */ + status = hashcrypt_aes_one_block(base, plaintext, ciphertext, size); + /* After processing all data, hashcrypt engine is set to disabled to lower power consumption */ + hashcrypt_engine_deinit(base); + + return status; +} + +status_t HASHCRYPT_AES_DecryptEcb( + HASHCRYPT_Type *base, hashcrypt_handle_t *handle, const uint8_t *ciphertext, uint8_t *plaintext, size_t size) +{ + status_t status = kStatus_Fail; + + if ((0U != (size % 16u)) || (handle->keySize == kHASHCRYPT_InvalidKey)) + { + return kStatus_InvalidArgument; + } + + uint32_t keyType = (handle->keyType == kHASHCRYPT_UserKey) ? 0U : 1u; + base->CRYPTCFG = HASHCRYPT_CRYPTCFG_AESMODE(kHASHCRYPT_AesEcb) | HASHCRYPT_CRYPTCFG_AESDECRYPT(AES_DECRYPT) | + HASHCRYPT_CRYPTCFG_AESSECRET(keyType) | HASHCRYPT_CRYPTCFG_AESKEYSZ(handle->keySize) | + HASHCRYPT_CRYPTCFG_MSW1ST_OUT(1) | HASHCRYPT_CRYPTCFG_SWAPKEY(1) | HASHCRYPT_CRYPTCFG_SWAPDAT(1) | + HASHCRYPT_CRYPTCFG_MSW1ST(1); + + hashcrypt_engine_init(base, kHASHCRYPT_Aes); + + /* in case of HW AES key, check if it is available */ + if (hashcrypt_check_need_key(base, handle) != kStatus_Success) + { + hashcrypt_engine_deinit(base); + return kStatus_Fail; + } + + /* load key if kHASHCRYPT_UserKey is selected */ + if (handle->keyType == kHASHCRYPT_UserKey) + { + hashcrypt_aes_load_userKey(base, handle); + } + + /* load message and get result */ + status = hashcrypt_aes_one_block(base, ciphertext, plaintext, size); + + /* After processing all data, hashcrypt engine is set to disabled to lower power consumption */ + hashcrypt_engine_deinit(base); + return status; +} + +status_t HASHCRYPT_AES_EncryptCbc(HASHCRYPT_Type *base, + hashcrypt_handle_t *handle, + const uint8_t *plaintext, + uint8_t *ciphertext, + size_t size, + const uint8_t iv[16]) +{ + status_t status = kStatus_Fail; + + if (0U != ((size % 16u)) || (handle->keySize == kHASHCRYPT_InvalidKey)) + { + return kStatus_InvalidArgument; + } + + uint32_t keyType = (handle->keyType == kHASHCRYPT_UserKey) ? 0U : 1u; + base->CRYPTCFG = HASHCRYPT_CRYPTCFG_AESMODE(kHASHCRYPT_AesCbc) | HASHCRYPT_CRYPTCFG_AESDECRYPT(AES_ENCRYPT) | + HASHCRYPT_CRYPTCFG_AESSECRET(keyType) | HASHCRYPT_CRYPTCFG_AESKEYSZ(handle->keySize) | + HASHCRYPT_CRYPTCFG_MSW1ST_OUT(1) | HASHCRYPT_CRYPTCFG_SWAPKEY(1) | HASHCRYPT_CRYPTCFG_SWAPDAT(1) | + HASHCRYPT_CRYPTCFG_MSW1ST(1); + + hashcrypt_engine_init(base, kHASHCRYPT_Aes); + + /* in case of HW AES key, check if it is available */ + if (hashcrypt_check_need_key(base, handle) != kStatus_Success) + { + hashcrypt_engine_deinit(base); + return kStatus_Fail; + } + + /* load key if kHASHCRYPT_UserKey is selected */ + if (handle->keyType == kHASHCRYPT_UserKey) + { + hashcrypt_aes_load_userKey(base, handle); + } + + /* load 16b iv */ + hashcrypt_load_data(base, (uint32_t *)(uintptr_t)iv, 16); + + /* load message and get result */ + status = hashcrypt_aes_one_block(base, plaintext, ciphertext, size); + + /* After processing all data, hashcrypt engine is set to disabled to lower power consumption */ + hashcrypt_engine_deinit(base); + return status; +} + +status_t HASHCRYPT_AES_DecryptCbc(HASHCRYPT_Type *base, + hashcrypt_handle_t *handle, + const uint8_t *ciphertext, + uint8_t *plaintext, + size_t size, + const uint8_t iv[16]) +{ + status_t status = kStatus_Fail; + + if ((0U != (size % 16u)) || (handle->keySize == kHASHCRYPT_InvalidKey)) + { + return kStatus_InvalidArgument; + } + + uint32_t keyType = (handle->keyType == kHASHCRYPT_UserKey) ? 0U : 1u; + base->CRYPTCFG = HASHCRYPT_CRYPTCFG_AESMODE(kHASHCRYPT_AesCbc) | HASHCRYPT_CRYPTCFG_AESDECRYPT(AES_DECRYPT) | + HASHCRYPT_CRYPTCFG_AESSECRET(keyType) | HASHCRYPT_CRYPTCFG_AESKEYSZ(handle->keySize) | + HASHCRYPT_CRYPTCFG_MSW1ST_OUT(1) | HASHCRYPT_CRYPTCFG_SWAPKEY(1) | HASHCRYPT_CRYPTCFG_SWAPDAT(1) | + HASHCRYPT_CRYPTCFG_MSW1ST(1); + + hashcrypt_engine_init(base, kHASHCRYPT_Aes); + + /* in case of HW AES key, check if it is available */ + if (hashcrypt_check_need_key(base, handle) != kStatus_Success) + { + hashcrypt_engine_deinit(base); + return kStatus_Fail; + } + + /* load key if kHASHCRYPT_UserKey is selected */ + if (handle->keyType == kHASHCRYPT_UserKey) + { + hashcrypt_aes_load_userKey(base, handle); + } + + /* load iv */ + hashcrypt_load_data(base, (uint32_t *)(uintptr_t)iv, 16); + + /* load message and get result */ + status = hashcrypt_aes_one_block(base, ciphertext, plaintext, size); + + /* After processing all data, hashcrypt engine is set to disabled to lower power consumption */ + hashcrypt_engine_deinit(base); + return status; +} + +status_t HASHCRYPT_AES_CryptCtr(HASHCRYPT_Type *base, + hashcrypt_handle_t *handle, + const uint8_t *input, + uint8_t *output, + size_t size, + uint8_t counter[HASHCRYPT_AES_BLOCK_SIZE], + uint8_t counterlast[HASHCRYPT_AES_BLOCK_SIZE], + size_t *szLeft) +{ + uint32_t lastSize; + uint8_t lastBlock[HASHCRYPT_AES_BLOCK_SIZE] = {0}; + uint8_t *lastEncryptedCounter; + status_t status = kStatus_Fail; + + if (handle->keySize == kHASHCRYPT_InvalidKey) + { + return kStatus_InvalidArgument; + } + + uint32_t keyType = (handle->keyType == kHASHCRYPT_UserKey) ? 0U : 1u; + base->CRYPTCFG = HASHCRYPT_CRYPTCFG_AESMODE(kHASHCRYPT_AesCtr) | HASHCRYPT_CRYPTCFG_AESDECRYPT(AES_ENCRYPT) | + HASHCRYPT_CRYPTCFG_AESSECRET(keyType) | HASHCRYPT_CRYPTCFG_AESKEYSZ(handle->keySize) | + HASHCRYPT_CRYPTCFG_MSW1ST_OUT(1) | HASHCRYPT_CRYPTCFG_SWAPKEY(1) | HASHCRYPT_CRYPTCFG_SWAPDAT(1) | + HASHCRYPT_CRYPTCFG_MSW1ST(1); + + hashcrypt_engine_init(base, kHASHCRYPT_Aes); + + /* in case of HW AES key, check if it is available */ + if (hashcrypt_check_need_key(base, handle) != kStatus_Success) + { + hashcrypt_engine_deinit(base); + return kStatus_Fail; + } + + /* load key if kHASHCRYPT_UserKey is selected */ + if (handle->keyType == kHASHCRYPT_UserKey) + { + hashcrypt_aes_load_userKey(base, handle); + } + + /* load nonce */ + hashcrypt_load_data(base, (uint32_t *)(uintptr_t)counter, 16); + + lastSize = size % HASHCRYPT_AES_BLOCK_SIZE; + size -= lastSize; + + /* encrypt full 16byte blocks */ + status = hashcrypt_aes_one_block(base, input, output, size); + if (status != kStatus_Success) + { + hashcrypt_engine_deinit(base); + return status; + } + + while (size != 0U) + { + ctrIncrement(counter); + size -= 16u; + input += 16; + output += 16; + } + + if (lastSize != 0U) + { + if (counterlast != NULL) + { + lastEncryptedCounter = counterlast; + } + else + { + lastEncryptedCounter = lastBlock; + } + + /* Perform encryption with all zeros to get last counter. XOR with zeros doesn't change. */ + status = hashcrypt_aes_one_block(base, lastBlock, lastEncryptedCounter, HASHCRYPT_AES_BLOCK_SIZE); + if (status != kStatus_Success) + { + hashcrypt_engine_deinit(base); + return status; + } + /* remain output = input XOR counterlast */ + for (uint32_t i = 0; i < lastSize; i++) + { + output[i] = input[i] ^ lastEncryptedCounter[i]; + } + /* Increment counter parameter */ + ctrIncrement(counter); + } + else + { + lastSize = HASHCRYPT_AES_BLOCK_SIZE; + /* no remaining bytes in couterlast so clearing it */ + if (counterlast != NULL) + { + (void)memset(counterlast, 0, HASHCRYPT_AES_BLOCK_SIZE); + } + } + + if (szLeft != NULL) + { + *szLeft = HASHCRYPT_AES_BLOCK_SIZE - lastSize; + } + + /* After processing all data, hashcrypt engine is set to disabled to lower power consumption */ + hashcrypt_engine_deinit(base); + return kStatus_Success; +} + +status_t HASHCRYPT_AES_CryptOfb(HASHCRYPT_Type *base, + hashcrypt_handle_t *handle, + const uint8_t *input, + uint8_t *output, + size_t size, + const uint8_t iv[HASHCRYPT_AES_BLOCK_SIZE]) +{ + status_t status = kStatus_Fail; + uint8_t zeroes[HASHCRYPT_AES_BLOCK_SIZE] = {0}; + uint8_t blockOutput[HASHCRYPT_AES_BLOCK_SIZE] = {0}; + + if (handle->keySize == kHASHCRYPT_InvalidKey) + { + return kStatus_InvalidArgument; + } + + uint32_t keyType = (handle->keyType == kHASHCRYPT_UserKey) ? 0U : 1u; + + base->CRYPTCFG = HASHCRYPT_CRYPTCFG_AESMODE(kHASHCRYPT_AesCbc) | HASHCRYPT_CRYPTCFG_AESDECRYPT(AES_ENCRYPT) | + HASHCRYPT_CRYPTCFG_AESSECRET(keyType) | HASHCRYPT_CRYPTCFG_AESKEYSZ(handle->keySize) | + HASHCRYPT_CRYPTCFG_MSW1ST_OUT(1) | HASHCRYPT_CRYPTCFG_SWAPKEY(1) | HASHCRYPT_CRYPTCFG_SWAPDAT(1) | + HASHCRYPT_CRYPTCFG_MSW1ST(1); + + hashcrypt_engine_init(base, kHASHCRYPT_Aes); + + /* in case of HW AES key, check if it is available */ + if (hashcrypt_check_need_key(base, handle) != kStatus_Success) + { + hashcrypt_engine_deinit(base); + return kStatus_Fail; + } + + /* load key if kHASHCRYPT_UserKey is selected */ + if (handle->keyType == kHASHCRYPT_UserKey) + { + hashcrypt_aes_load_userKey(base, handle); + } + + /* load iv */ + hashcrypt_load_data(base, (uint32_t *)(uintptr_t)iv, HASHCRYPT_AES_BLOCK_SIZE); + + /*Use AES CBC mode and feed input with zeroes as input*/ + /*Output block is then XORed with input*/ + + while (size >= 16u) + { + status = hashcrypt_aes_one_block(base, zeroes, blockOutput, HASHCRYPT_AES_BLOCK_SIZE); + if (status != kStatus_Success) + { + hashcrypt_engine_deinit(base); + return status; + } + /* XOR input with output block to get output*/ + for (uint32_t i = 0; i < HASHCRYPT_AES_BLOCK_SIZE; i++) + { + output[i] = input[i] ^ blockOutput[i]; + } + size -= 16u; + output += 16; + input += 16; + } + + /* OFB can have non-block multiple size.*/ + if (size != 0U) + { + status = hashcrypt_aes_one_block(base, zeroes, blockOutput, HASHCRYPT_AES_BLOCK_SIZE); + if (status != kStatus_Success) + { + hashcrypt_engine_deinit(base); + return status; + } + + /* XOR input with output block to get output*/ + for (uint32_t i = 0; i < size; i++) + { + output[i] = input[i] ^ blockOutput[i]; + } + } + + /* After processing all data, hashcrypt engine is set to disabled to lower power consumption */ + hashcrypt_engine_deinit(base); + return status; +} + +status_t HASHCRYPT_AES_EncryptCfb(HASHCRYPT_Type *base, + hashcrypt_handle_t *handle, + const uint8_t *plaintext, + uint8_t *ciphertext, + size_t size, + const uint8_t iv[HASHCRYPT_AES_BLOCK_SIZE]) +{ + status_t status = kStatus_Fail; + uint8_t zeroes[HASHCRYPT_AES_BLOCK_SIZE] = {0}; + uint8_t blockOutput[HASHCRYPT_AES_BLOCK_SIZE] = {0}; + + /* For CFB mode size must be 16-byte multiple */ + if ((0U != (size % 16u)) || (handle->keySize == kHASHCRYPT_InvalidKey)) + { + return kStatus_InvalidArgument; + } + + uint32_t keyType = (handle->keyType == kHASHCRYPT_UserKey) ? 0U : 1u; + + base->CRYPTCFG = HASHCRYPT_CRYPTCFG_AESMODE(kHASHCRYPT_AesCbc) | HASHCRYPT_CRYPTCFG_AESDECRYPT(AES_ENCRYPT) | + HASHCRYPT_CRYPTCFG_AESSECRET(keyType) | HASHCRYPT_CRYPTCFG_AESKEYSZ(handle->keySize) | + HASHCRYPT_CRYPTCFG_MSW1ST_OUT(1) | HASHCRYPT_CRYPTCFG_SWAPKEY(1) | HASHCRYPT_CRYPTCFG_SWAPDAT(1) | + HASHCRYPT_CRYPTCFG_MSW1ST(1); + + hashcrypt_engine_init(base, kHASHCRYPT_Aes); + + /* in case of HW AES key, check if it is available */ + if (hashcrypt_check_need_key(base, handle) != kStatus_Success) + { + hashcrypt_engine_deinit(base); + return kStatus_Fail; + } + + /* load key if kHASHCRYPT_UserKey is selected */ + if (handle->keyType == kHASHCRYPT_UserKey) + { + hashcrypt_aes_load_userKey(base, handle); + } + + /* load iv */ + hashcrypt_load_data(base, (uint32_t *)(uintptr_t)iv, HASHCRYPT_AES_BLOCK_SIZE); + + /*Use AES CBC mode and feed input with zeroes for first block */ + /*Output block is then XORed with plaintext to get ciphertext*/ + + status = hashcrypt_aes_one_block(base, zeroes, blockOutput, HASHCRYPT_AES_BLOCK_SIZE); + if (status != kStatus_Success) + { + hashcrypt_engine_deinit(base); + return status; + } + /* XOR plaintext with output block to get ciphertext*/ + for (uint32_t i = 0; i < HASHCRYPT_AES_BLOCK_SIZE; i++) + { + ciphertext[i] = plaintext[i] ^ blockOutput[i]; + } + size -= 16u; + + /*Remaining blocks use previous plaintext as input for aes block function */ + while (size >= 16u) + { + status = hashcrypt_aes_one_block(base, plaintext, blockOutput, HASHCRYPT_AES_BLOCK_SIZE); + ciphertext += 16; + plaintext += 16; + + if (status != kStatus_Success) + { + hashcrypt_engine_deinit(base); + return status; + } + /* XOR plaintext with output block to get ciphertext*/ + for (uint32_t i = 0; i < HASHCRYPT_AES_BLOCK_SIZE; i++) + { + ciphertext[i] = plaintext[i] ^ blockOutput[i]; + } + size -= 16u; + } + + /* After processing all data, hashcrypt engine is set to disabled to lower power consumption */ + hashcrypt_engine_deinit(base); + return status; +} + +status_t HASHCRYPT_AES_DecryptCfb(HASHCRYPT_Type *base, + hashcrypt_handle_t *handle, + const uint8_t *ciphertext, + uint8_t *plaintext, + size_t size, + const uint8_t iv[HASHCRYPT_AES_BLOCK_SIZE]) +{ + status_t status = kStatus_Fail; + uint8_t zeroes[HASHCRYPT_AES_BLOCK_SIZE] = {0}; + uint8_t blockOutput[HASHCRYPT_AES_BLOCK_SIZE] = {0}; + + /* For CFB mode size must be 16-byte multiple */ + if ((0U != (size % 16u)) || (handle->keySize == kHASHCRYPT_InvalidKey)) + { + return kStatus_InvalidArgument; + } + + uint32_t keyType = (handle->keyType == kHASHCRYPT_UserKey) ? 0U : 1u; + + base->CRYPTCFG = HASHCRYPT_CRYPTCFG_AESMODE(kHASHCRYPT_AesCbc) | HASHCRYPT_CRYPTCFG_AESDECRYPT(AES_ENCRYPT) | + HASHCRYPT_CRYPTCFG_AESSECRET(keyType) | HASHCRYPT_CRYPTCFG_AESKEYSZ(handle->keySize) | + HASHCRYPT_CRYPTCFG_MSW1ST_OUT(1) | HASHCRYPT_CRYPTCFG_SWAPKEY(1) | HASHCRYPT_CRYPTCFG_SWAPDAT(1) | + HASHCRYPT_CRYPTCFG_MSW1ST(1); + + hashcrypt_engine_init(base, kHASHCRYPT_Aes); + + /* in case of HW AES key, check if it is available */ + if (hashcrypt_check_need_key(base, handle) != kStatus_Success) + { + hashcrypt_engine_deinit(base); + return kStatus_Fail; + } + + /* load key if kHASHCRYPT_UserKey is selected */ + if (handle->keyType == kHASHCRYPT_UserKey) + { + hashcrypt_aes_load_userKey(base, handle); + } + + /* load iv */ + hashcrypt_load_data(base, (uint32_t *)(uintptr_t)iv, HASHCRYPT_AES_BLOCK_SIZE); + + /*Use AES CBC mode and feed input with zeroes for first block */ + /*Output block is then XORed with ciphertext to get plaintext*/ + + status = hashcrypt_aes_one_block(base, zeroes, blockOutput, HASHCRYPT_AES_BLOCK_SIZE); + if (status != kStatus_Success) + { + hashcrypt_engine_deinit(base); + return status; + } + /* XOR ciphertext with output block to get plaintext*/ + for (uint32_t i = 0; i < HASHCRYPT_AES_BLOCK_SIZE; i++) + { + plaintext[i] = ciphertext[i] ^ blockOutput[i]; + } + size -= 16u; + + /*Remaining blocks use previous plaintext as input for aes block function */ + while (size >= 16u) + { + status = hashcrypt_aes_one_block(base, plaintext, blockOutput, HASHCRYPT_AES_BLOCK_SIZE); + ciphertext += 16; + plaintext += 16; + + if (status != kStatus_Success) + { + hashcrypt_engine_deinit(base); + return status; + } + /* XOR plaintext with ciphertext block to get plaintext*/ + for (uint32_t i = 0; i < HASHCRYPT_AES_BLOCK_SIZE; i++) + { + plaintext[i] = ciphertext[i] ^ blockOutput[i]; + } + size -= 16u; + } + + /* After processing all data, hashcrypt engine is set to disabled to lower power consumption */ + hashcrypt_engine_deinit(base); + return status; +} + +void HASHCRYPT_DriverIRQHandler(void); +void HASHCRYPT_DriverIRQHandler(void) +{ + hashcrypt_sha_ctx_internal_t *ctxInternal; + HASHCRYPT_Type *base = HASHCRYPT; + uint32_t numBlocks; + status_t status; + + ctxInternal = (hashcrypt_sha_ctx_internal_t *)(uint32_t)s_ctx; + + if (0U == (base->STATUS & HASHCRYPT_STATUS_ERROR_MASK)) + { + if (ctxInternal->remainingBlcks > 0U) + { + if (ctxInternal->remainingBlcks >= SHA_MASTER_MAX_BLOCKS) + { + numBlocks = SHA_MASTER_MAX_BLOCKS - 1U; + } + else + { + numBlocks = ctxInternal->remainingBlcks; + } + /* some blocks still remaining, update remainingBlcks for next ISR and start another hash */ + ctxInternal->remainingBlcks -= numBlocks; + base->MEMCTRL = HASHCRYPT_MEMCTRL_MASTER(1) | HASHCRYPT_MEMCTRL_COUNT(numBlocks); + return; + } + /* no full blocks left, disable interrupts and AHB master mode */ + base->INTENCLR = HASHCRYPT_INTENCLR_DIGEST_MASK | HASHCRYPT_INTENCLR_ERROR_MASK; + base->MEMCTRL = HASHCRYPT_MEMCTRL_MASTER(0); + hashcrypt_save_running_hash(base, ctxInternal); + status = kStatus_Success; + } + else + { + status = kStatus_Fail; + } + + /* Invoke callback if there is one */ + if (NULL != ctxInternal->hashCallback) + { + ctxInternal->hashCallback(HASHCRYPT, s_ctx, status, ctxInternal->userData); + } +} + +void HASHCRYPT_Init(HASHCRYPT_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + CLOCK_EnableClock(kCLOCK_HashCrypt); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + RESET_PeripheralReset(kHASHCRYPT_RST_SHIFT_RSTn); +} + +void HASHCRYPT_Deinit(HASHCRYPT_Type *base) +{ + RESET_SetPeripheralReset(kHASHCRYPT_RST_SHIFT_RSTn); +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + CLOCK_DisableClock(kCLOCK_HashCrypt); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} diff --git a/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_hashcrypt.h b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_hashcrypt.h new file mode 100644 index 0000000000..fa15b8cf71 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_hashcrypt.h @@ -0,0 +1,531 @@ +/* + * Copyright 2017-2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_HASHCRYPT_H_ +#define _FSL_HASHCRYPT_H_ + +#include "fsl_common.h" + +/*! @brief HASHCRYPT status return codes. */ +enum _hashcrypt_status +{ + kStatus_HASHCRYPT_Again = + MAKE_STATUS(kStatusGroup_HASHCRYPT, 0), /*!< Non-blocking function shall be called again. */ +}; + +/******************************************************************************* + * Definitions + *******************************************************************************/ + +/*! + * @addtogroup hashcrypt_driver + * @{ + */ +/*! @name Driver version */ +/*@{*/ +/*! @brief HASHCRYPT driver version. Version 2.2.6. + * + * Current version: 2.2.6 + * + * Change log: + * - Version 2.0.0 + * - Initial version + * - Version 2.0.1 + * - Support loading AES key from unaligned address + * - Version 2.0.2 + * - Support loading AES key from unaligned address for different compiler and core variants + * - Version 2.0.3 + * - Remove SHA512 and AES ICB algorithm definitions + * - Version 2.0.4 + * - Add SHA context switch support + * - Version 2.1.0 + * - Update the register name and macro to align with new header. + * - Version 2.1.1 + * - Fix MISRA C-2012. + * - Version 2.1.2 + * - Support loading AES input data from unaligned address. + * - Version 2.1.3 + * - Fix MISRA C-2012. + * - Version 2.1.4 + * - Fix context switch cannot work when switching from AES. + * - Version 2.1.5 + * - Add data synchronization barrier inside hashcrypt_sha_ldm_stm_16_words() + * to prevent possible optimization issue. + * - Version 2.2.0 + * - Add AES-OFB and AES-CFB mixed IP/SW modes. + * - Version 2.2.1 + * - Add data synchronization barrier inside hashcrypt_sha_ldm_stm_16_words() + * prevent compiler from reordering memory write when -O2 or higher is used. + * - Version 2.2.2 + * - Add data synchronization barrier inside hashcrypt_sha_ldm_stm_16_words() + * to fix optimization issue + * - Version 2.2.3 + * - Added check for size in hashcrypt_aes_one_block to prevent overflowing COUNT field in MEMCTRL register, if its + * bigger than COUNT field do a multiple runs. + * - Version 2.2.4 + * - In all HASHCRYPT_AES_xx functions have been added setting CTRL_MODE bitfield to 0 after processing data, which + * decreases power consumption. + * - Version 2.2.5 + * - Add data synchronization barrier and instruction synchronization barrier inside + * hashcrypt_sha_process_message_data() to fix optimization issue + * - Version 2.2.6 + * - Add data synchronization barrier inside HASHCRYPT_SHA_Update() and hashcrypt_get_data() function to fix + * optimization issue on MDK and ARMGCC release targets + */ +#define FSL_HASHCRYPT_DRIVER_VERSION (MAKE_VERSION(2, 2, 6)) +/*@}*/ + +/*! @brief Algorithm definitions correspond with the values for Mode field in Control register !*/ +#define HASHCRYPT_MODE_SHA1 0x1 +#define HASHCRYPT_MODE_SHA256 0x2 +#define HASHCRYPT_MODE_AES 0x4 + +/*! @brief Algorithm used for Hashcrypt operation */ +typedef enum _hashcrypt_algo_t +{ + kHASHCRYPT_Sha1 = HASHCRYPT_MODE_SHA1, /*!< SHA_1 */ + kHASHCRYPT_Sha256 = HASHCRYPT_MODE_SHA256, /*!< SHA_256 */ + kHASHCRYPT_Aes = HASHCRYPT_MODE_AES, /*!< AES */ +} hashcrypt_algo_t; + +/*! @} */ + +/******************************************************************************* + * AES Definitions + *******************************************************************************/ + +/*! + * @addtogroup hashcrypt_driver_aes + * @{ + */ + +/*! AES block size in bytes */ +#define HASHCRYPT_AES_BLOCK_SIZE 16U +#define AES_ENCRYPT 0 +#define AES_DECRYPT 1 + +/*! @brief AES mode */ +typedef enum _hashcrypt_aes_mode_t +{ + kHASHCRYPT_AesEcb = 0U, /*!< AES ECB mode */ + kHASHCRYPT_AesCbc = 1U, /*!< AES CBC mode */ + kHASHCRYPT_AesCtr = 2U, /*!< AES CTR mode */ +} hashcrypt_aes_mode_t; + +/*! @brief Size of AES key */ +typedef enum _hashcrypt_aes_keysize_t +{ + kHASHCRYPT_Aes128 = 0U, /*!< AES 128 bit key */ + kHASHCRYPT_Aes192 = 1U, /*!< AES 192 bit key */ + kHASHCRYPT_Aes256 = 2U, /*!< AES 256 bit key */ + kHASHCRYPT_InvalidKey = 3U, /*!< AES invalid key */ +} hashcrypt_aes_keysize_t; + +/*! @brief HASHCRYPT key source selection. + * + */ +typedef enum _hashcrypt_key +{ + kHASHCRYPT_UserKey = 0xc3c3U, /*!< HASHCRYPT user key */ + kHASHCRYPT_SecretKey = 0x3c3cU, /*!< HASHCRYPT secret key (dedicated hw bus from PUF) */ +} hashcrypt_key_t; + +/*! @brief Specify HASHCRYPT's key resource. */ +struct _hashcrypt_handle +{ + uint32_t keyWord[8]; /*!< Copy of user key (set by HASHCRYPT_AES_SetKey(). */ + hashcrypt_aes_keysize_t keySize; + hashcrypt_key_t keyType; /*!< For operations with key (such as AES encryption/decryption), specify key type. */ +} __attribute__((aligned)); + +typedef struct _hashcrypt_handle hashcrypt_handle_t; + +/*! + *@} + */ /* end of hashcrypt_driver_aes */ + +/******************************************************************************* + * HASH Definitions + ******************************************************************************/ +/*! + * @addtogroup hashcrypt_driver_hash + * @{ + */ + +/*! @brief HASHCRYPT HASH Context size. */ +#if defined(FSL_FEATURE_HASHCRYPT_HAS_RELOAD_FEATURE) && (FSL_FEATURE_HASHCRYPT_HAS_RELOAD_FEATURE > 0) +#define HASHCRYPT_HASH_CTX_SIZE 30 +#else +#define HASHCRYPT_HASH_CTX_SIZE 22 +#endif + +/*! @brief Storage type used to save hash context. */ +typedef struct _hashcrypt_hash_ctx_t +{ + uint32_t x[HASHCRYPT_HASH_CTX_SIZE]; /*!< storage */ +} hashcrypt_hash_ctx_t; + +/*! @brief HASHCRYPT background hash callback function. */ +typedef void (*hashcrypt_callback_t)(HASHCRYPT_Type *base, hashcrypt_hash_ctx_t *ctx, status_t status, void *userData); + +/*! + *@} + */ /* end of hashcrypt_driver_hash */ + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @addtogroup hashcrypt_driver + * @{ + */ + +/*! + * @brief Enables clock and disables reset for HASHCRYPT peripheral. + * + * Enable clock and disable reset for HASHCRYPT. + * + * @param base HASHCRYPT base address + */ +void HASHCRYPT_Init(HASHCRYPT_Type *base); + +/*! + * @brief Disables clock for HASHCRYPT peripheral. + * + * Disable clock and enable reset. + * + * @param base HASHCRYPT base address + */ +void HASHCRYPT_Deinit(HASHCRYPT_Type *base); + +/*! + *@} + */ /* end of hashcrypt_driver */ + +/******************************************************************************* + * AES API + ******************************************************************************/ + +/*! + * @addtogroup hashcrypt_driver_aes + * @{ + */ + +/*! + * @brief Set AES key to hashcrypt_handle_t struct and optionally to HASHCRYPT. + * + * Sets the AES key for encryption/decryption with the hashcrypt_handle_t structure. + * The hashcrypt_handle_t input argument specifies key source. + * + * @param base HASHCRYPT peripheral base address. + * @param handle Handle used for the request. + * @param key 0-mod-4 aligned pointer to AES key. + * @param keySize AES key size in bytes. Shall equal 16, 24 or 32. + * @return status from set key operation + */ +status_t HASHCRYPT_AES_SetKey(HASHCRYPT_Type *base, hashcrypt_handle_t *handle, const uint8_t *key, size_t keySize); + +/*! + * @brief Encrypts AES on one or multiple 128-bit block(s). + * + * Encrypts AES. + * The source plaintext and destination ciphertext can overlap in system memory. + * + * @param base HASHCRYPT peripheral base address + * @param handle Handle used for this request. + * @param plaintext Input plain text to encrypt + * @param[out] ciphertext Output cipher text + * @param size Size of input and output data in bytes. Must be multiple of 16 bytes. + * @return Status from encrypt operation + */ +status_t HASHCRYPT_AES_EncryptEcb( + HASHCRYPT_Type *base, hashcrypt_handle_t *handle, const uint8_t *plaintext, uint8_t *ciphertext, size_t size); + +/*! + * @brief Decrypts AES on one or multiple 128-bit block(s). + * + * Decrypts AES. + * The source ciphertext and destination plaintext can overlap in system memory. + * + * @param base HASHCRYPT peripheral base address + * @param handle Handle used for this request. + * @param ciphertext Input plain text to encrypt + * @param[out] plaintext Output cipher text + * @param size Size of input and output data in bytes. Must be multiple of 16 bytes. + * @return Status from decrypt operation + */ +status_t HASHCRYPT_AES_DecryptEcb( + HASHCRYPT_Type *base, hashcrypt_handle_t *handle, const uint8_t *ciphertext, uint8_t *plaintext, size_t size); + +/*! + * @brief Encrypts AES using CBC block mode. + * + * @param base HASHCRYPT peripheral base address + * @param handle Handle used for this request. + * @param plaintext Input plain text to encrypt + * @param[out] ciphertext Output cipher text + * @param size Size of input and output data in bytes. Must be multiple of 16 bytes. + * @param iv Input initial vector to combine with the first input block. + * @return Status from encrypt operation + */ +status_t HASHCRYPT_AES_EncryptCbc(HASHCRYPT_Type *base, + hashcrypt_handle_t *handle, + const uint8_t *plaintext, + uint8_t *ciphertext, + size_t size, + const uint8_t iv[16]); + +/*! + * @brief Decrypts AES using CBC block mode. + * + * @param base HASHCRYPT peripheral base address + * @param handle Handle used for this request. + * @param ciphertext Input cipher text to decrypt + * @param[out] plaintext Output plain text + * @param size Size of input and output data in bytes. Must be multiple of 16 bytes. + * @param iv Input initial vector to combine with the first input block. + * @return Status from decrypt operation + */ +status_t HASHCRYPT_AES_DecryptCbc(HASHCRYPT_Type *base, + hashcrypt_handle_t *handle, + const uint8_t *ciphertext, + uint8_t *plaintext, + size_t size, + const uint8_t iv[16]); + +/*! + * @brief Encrypts or decrypts AES using CTR block mode. + * + * Encrypts or decrypts AES using CTR block mode. + * AES CTR mode uses only forward AES cipher and same algorithm for encryption and decryption. + * The only difference between encryption and decryption is that, for encryption, the input argument + * is plain text and the output argument is cipher text. For decryption, the input argument is cipher text + * and the output argument is plain text. + * + * @param base HASHCRYPT peripheral base address + * @param handle Handle used for this request. + * @param input Input data for CTR block mode + * @param[out] output Output data for CTR block mode + * @param size Size of input and output data in bytes + * @param[in,out] counter Input counter (updates on return) + * @param[out] counterlast Output cipher of last counter, for chained CTR calls (statefull encryption). NULL can be + * passed if chained calls are + * not used. + * @param[out] szLeft Output number of bytes in left unused in counterlast block. NULL can be passed if chained calls + * are not used. + * @return Status from encrypt operation + */ +status_t HASHCRYPT_AES_CryptCtr(HASHCRYPT_Type *base, + hashcrypt_handle_t *handle, + const uint8_t *input, + uint8_t *output, + size_t size, + uint8_t counter[HASHCRYPT_AES_BLOCK_SIZE], + uint8_t counterlast[HASHCRYPT_AES_BLOCK_SIZE], + size_t *szLeft); + +/*! + * @brief Encrypts or decrypts AES using OFB block mode. + * + * Encrypts or decrypts AES using OFB block mode. + * AES OFB mode uses only forward AES cipher and same algorithm for encryption and decryption. + * The only difference between encryption and decryption is that, for encryption, the input argument + * is plain text and the output argument is cipher text. For decryption, the input argument is cipher text + * and the output argument is plain text. + * + * @param base HASHCRYPT peripheral base address + * @param handle Handle used for this request. + * @param input Input data for OFB block mode + * @param[out] output Output data for OFB block mode + * @param size Size of input and output data in bytes + * @param iv Input initial vector to combine with the first input block. + * @return Status from encrypt operation + */ + +status_t HASHCRYPT_AES_CryptOfb(HASHCRYPT_Type *base, + hashcrypt_handle_t *handle, + const uint8_t *input, + uint8_t *output, + size_t size, + const uint8_t iv[HASHCRYPT_AES_BLOCK_SIZE]); + +/*! + * @brief Encrypts AES using CFB block mode. + * + * @param base HASHCRYPT peripheral base address + * @param handle Handle used for this request. + * @param plaintext Input plain text to encrypt + * @param[out] ciphertext Output cipher text + * @param size Size of input and output data in bytes. Must be multiple of 16 bytes. + * @param iv Input initial vector to combine with the first input block. + * @return Status from encrypt operation + */ + +status_t HASHCRYPT_AES_EncryptCfb(HASHCRYPT_Type *base, + hashcrypt_handle_t *handle, + const uint8_t *plaintext, + uint8_t *ciphertext, + size_t size, + const uint8_t iv[16]); + +/*! + * @brief Decrypts AES using CFB block mode. + * + * @param base HASHCRYPT peripheral base address + * @param handle Handle used for this request. + * @param ciphertext Input cipher text to decrypt + * @param[out] plaintext Output plaintext text + * @param size Size of input and output data in bytes. Must be multiple of 16 bytes. + * @param iv Input initial vector to combine with the first input block. + * @return Status from encrypt operation + */ + +status_t HASHCRYPT_AES_DecryptCfb(HASHCRYPT_Type *base, + hashcrypt_handle_t *handle, + const uint8_t *ciphertext, + uint8_t *plaintext, + size_t size, + const uint8_t iv[16]); +/*! + *@} + */ /* end of hashcrypt_driver_aes */ + +/******************************************************************************* + * HASH API + ******************************************************************************/ + +/*! + * @addtogroup hashcrypt_driver_hash + * @{ + */ + +/*! + * @brief Create HASH on given data + * + * Perform the full SHA in one function call. The function is blocking. + * + * @param base HASHCRYPT peripheral base address + * @param algo Underlaying algorithm to use for hash computation. + * @param input Input data + * @param inputSize Size of input data in bytes + * @param[out] output Output hash data + * @param[out] outputSize Output parameter storing the size of the output hash in bytes + * @return Status of the one call hash operation. + */ +status_t HASHCRYPT_SHA(HASHCRYPT_Type *base, + hashcrypt_algo_t algo, + const uint8_t *input, + size_t inputSize, + uint8_t *output, + size_t *outputSize); + +/*! + * @brief Initialize HASH context + * + * This function initializes the HASH. + * + * @param base HASHCRYPT peripheral base address + * @param[out] ctx Output hash context + * @param algo Underlaying algorithm to use for hash computation. + * @return Status of initialization + */ +status_t HASHCRYPT_SHA_Init(HASHCRYPT_Type *base, hashcrypt_hash_ctx_t *ctx, hashcrypt_algo_t algo); + +/*! + * @brief Add data to current HASH + * + * Add data to current HASH. This can be called repeatedly with an arbitrary amount of data to be + * hashed. The functions blocks. If it returns kStatus_Success, the running hash + * has been updated (HASHCRYPT has processed the input data), so the memory at \p input pointer + * can be released back to system. The HASHCRYPT context buffer is updated with the running hash + * and with all necessary information to support possible context switch. + * + * @param base HASHCRYPT peripheral base address + * @param[in,out] ctx HASH context + * @param input Input data + * @param inputSize Size of input data in bytes + * @return Status of the hash update operation + */ +status_t HASHCRYPT_SHA_Update(HASHCRYPT_Type *base, hashcrypt_hash_ctx_t *ctx, const uint8_t *input, size_t inputSize); + +/*! + * @brief Finalize hashing + * + * Outputs the final hash (computed by HASHCRYPT_HASH_Update()) and erases the context. + * + * @param base HASHCRYPT peripheral base address + * @param[in,out] ctx Input hash context + * @param[out] output Output hash data + * @param[in,out] outputSize Optional parameter (can be passed as NULL). On function entry, it specifies the size of + * output[] buffer. On function return, it stores the number of updated output bytes. + * @return Status of the hash finish operation + */ +status_t HASHCRYPT_SHA_Finish(HASHCRYPT_Type *base, hashcrypt_hash_ctx_t *ctx, uint8_t *output, size_t *outputSize); + +/*! + *@} + */ /* end of hashcrypt_driver_hash */ + +/*! + * @addtogroup hashcrypt_background_driver_hash + * @{ + */ + +/*! + * @brief Initializes the HASHCRYPT handle for background hashing. + * + * This function initializes the hash context for background hashing + * (Non-blocking) APIs. This is less typical interface to hash function, but can be used + * for parallel processing, when main CPU has something else to do. + * Example is digital signature RSASSA-PKCS1-V1_5-VERIFY((n,e),M,S) algorithm, where + * background hashing of M can be started, then CPU can compute S^e mod n + * (in parallel with background hashing) and once the digest becomes available, + * CPU can proceed to comparison of EM with EM'. + * + * @param base HASHCRYPT peripheral base address. + * @param[out] ctx Hash context. + * @param callback Callback function. + * @param userData User data (to be passed as an argument to callback function, once callback is invoked from isr). + */ +void HASHCRYPT_SHA_SetCallback(HASHCRYPT_Type *base, + hashcrypt_hash_ctx_t *ctx, + hashcrypt_callback_t callback, + void *userData); + +/*! + * @brief Create running hash on given data. + * + * Configures the HASHCRYPT to compute new running hash as AHB master + * and returns immediately. HASHCRYPT AHB Master mode supports only aligned \p input + * address and can be called only once per continuous block of data. Every call to this function + * must be preceded with HASHCRYPT_SHA_Init() and finished with HASHCRYPT_SHA_Finish(). + * Once callback function is invoked by HASHCRYPT isr, it should set a flag + * for the main application to finalize the hashing (padding) and to read out the final digest + * by calling HASHCRYPT_SHA_Finish(). + * + * @param base HASHCRYPT peripheral base address + * @param ctx Specifies callback. Last incomplete 512-bit block of the input is copied into clear buffer for padding. + * @param input 32-bit word aligned pointer to Input data. + * @param inputSize Size of input data in bytes (must be word aligned) + * @return Status of the hash update operation. + */ +status_t HASHCRYPT_SHA_UpdateNonBlocking(HASHCRYPT_Type *base, + hashcrypt_hash_ctx_t *ctx, + const uint8_t *input, + size_t inputSize); +/*! + *@} + */ /* end of hashcrypt_background_driver_hash */ + +#if defined(__cplusplus) +} +#endif + +#endif /* _FSL_HASHCRYPT_H_ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_i2c.c b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_i2c.c new file mode 100644 index 0000000000..9ecde80c90 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_i2c.c @@ -0,0 +1,2085 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_i2c.h" +#include "fsl_flexcomm.h" +#include +#include + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.flexcomm_i2c" +#endif + +/*! @brief Common sets of flags used by the driver's transactional layer internally. */ +enum _i2c_flag_constants +{ + kI2C_MasterIrqFlags = I2C_INTSTAT_MSTPENDING_MASK | I2C_INTSTAT_MSTARBLOSS_MASK | I2C_INTSTAT_MSTSTSTPERR_MASK | + I2C_INTSTAT_EVENTTIMEOUT_MASK | I2C_INTSTAT_SCLTIMEOUT_MASK, + kI2C_SlaveIrqFlags = I2C_INTSTAT_SLVPENDING_MASK | I2C_INTSTAT_SLVDESEL_MASK, +}; + +/*! + * @brief Used for conversion from `flexcomm_irq_handler_t` to `flexcomm_i2c_master_irq_handler_t` and + * `flexcomm_i2c_slave_irq_handler_t`. + */ +typedef union i2c_to_flexcomm +{ + flexcomm_i2c_master_irq_handler_t i2c_master_handler; + flexcomm_i2c_slave_irq_handler_t i2c_slave_handler; + flexcomm_irq_handler_t flexcomm_handler; +} i2c_to_flexcomm_t; + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Waits for Master Pending status bit to set and check for bus error status. + * + * @param base The I2C peripheral base address. + * @return Bus status. + */ +static status_t I2C_PendingStatusWait(I2C_Type *base); + +/*! + * @brief Prepares the transfer state machine and fills in the command buffer. + * @param base The I2C peripheral base address. + * @param handle Master nonblocking driver handle. + * @param xfer The I2C transfer configuration structure. + */ +static status_t I2C_InitTransferStateMachine(I2C_Type *base, i2c_master_handle_t *handle, i2c_master_transfer_t *xfer); + +/*! + * @brief Resets the slave hardware state machine. + * According to documentation, after disabling slave to rest the slave hardware state machine, the register + * configuration remains unchanged. + * @param base The I2C peripheral base address. + */ +static void I2C_SlaveInternalStateMachineReset(I2C_Type *base); + +/*! + * @brief Compute CLKDIV + * + * This function computes CLKDIV value according to the given bus speed and Flexcomm source clock frequency. + * This setting is used by hardware during slave clock stretching. + * + * @param base The I2C peripheral base address. + * @return status of the operation + */ +static status_t I2C_SlaveDivVal(uint32_t srcClock_Hz, i2c_slave_bus_speed_t busSpeed, uint32_t *divVal); + +/*! + * @brief Poll wait for the SLVPENDING flag. + * + * Wait for the pending status to be set (SLVPENDING = 1) by polling the STAT register. + * + * @param base The I2C peripheral base address. + * @return status register at time the SLVPENDING bit is read as set + */ +static uint32_t I2C_SlavePollPending(I2C_Type *base); + +/*! + * @brief Invoke event from I2C_SlaveTransferHandleIRQ(). + * + * Sets the event type to transfer structure and invokes the event callback, if it has been + * enabled by eventMask. + * + * @param base The I2C peripheral base address. + * @param handle The I2C slave handle for non-blocking APIs. + * @param event The I2C slave event to invoke. + */ +static void I2C_SlaveInvokeEvent(I2C_Type *base, i2c_slave_handle_t *handle, i2c_slave_transfer_event_t event); + +/*! + * @brief Handle slave address match event. + * + * Called by Slave interrupt routine to ACK or NACK the matched address. + * It also determines master direction (read or write). + * + * @param base The I2C peripheral base address. + * @return true if the matched address is ACK'ed + * @return false if the matched address is NACK'ed + */ +static bool I2C_SlaveAddressIRQ(I2C_Type *base, i2c_slave_handle_t *handle); + +/*! + * @brief Starts accepting slave transfers. + * + * Call this API after calling I2C_SlaveInit() and I2C_SlaveTransferCreateHandle() to start processing + * transactions driven by an I2C master. The slave monitors the I2C bus and pass events to the + * callback that was passed into the call to I2C_SlaveTransferCreateHandle(). The callback is always invoked + * from the interrupt context. + * + * @param base The I2C peripheral base address. + * @param handle Pointer to #i2c_slave_handle_t structure which stores the transfer state. + * @param txData Data to be transmitted to master in response to master read from slave requests. NULL if slave RX only. + * @param txSize Size of txData buffer in bytes. + * @param rxData Data where received data from master will be stored in response to master write to slave requests. NULL + * if slave TX only. + * @param rxSize Size of rxData buffer in bytes. + * @retval #kStatus_Success Slave transfers were successfully started. + * @retval #kStatus_I2C_Busy Slave transfers have already been started on this handle. + */ +static status_t I2C_SlaveTransferNonBlockingInternal(I2C_Type *base, + i2c_slave_handle_t *handle, + const void *txData, + size_t txSize, + void *rxData, + size_t rxSize, + uint32_t eventMask); + +/*! + * @brief Execute master transfer software state machine until FIFOs are exhausted. + * + * For master transmit, the states would be kStartState->kTransmitSubaddrState->kTransmitDataState->kStopState + * For master receive, the states would be kStartState->kTransmitSubaddrState->kStartState->kReceiveDataState-> + * kWaitForCompletionState + * + * @param handle Master nonblocking driver handle. + * @param[out] isDone Set to true if the transfer has completed. + * @retval #kStatus_Success + * @retval #kStatus_I2C_ArbitrationLost + * @retval #kStatus_I2C_Nak + */ +static status_t I2C_RunTransferStateMachine(I2C_Type *base, i2c_master_handle_t *handle, bool *isDone); + +/*! + * @brief Checks the slave response to master's start signal. + * + * @param base I2C peripheral base address. + * @retval kStatus_Success Successfully complete the data transmission. + * @retval kStatus_I2C_Timeout Transfer error, wait signal timeout. + * @retval kStataus_I2C_Nak Transfer error, receive NAK during addressing. + */ +static status_t I2C_MasterCheckStartResponse(I2C_Type *base); +/******************************************************************************* + * Variables + ******************************************************************************/ + +/*! @brief Array to map i2c instance number to base address. */ +static const uint32_t s_i2cBaseAddrs[FSL_FEATURE_SOC_I2C_COUNT] = I2C_BASE_ADDRS; + +/*! @brief IRQ name array */ +static const IRQn_Type s_i2cIRQ[] = I2C_IRQS; + +/******************************************************************************* + * Code + ******************************************************************************/ + +/*! + * brief Returns an instance number given a base address. + * + * If an invalid base address is passed, debug builds will assert. Release builds will just return + * instance number 0. + * + * param base The I2C peripheral base address. + * return I2C instance number starting from 0. + */ +uint32_t I2C_GetInstance(I2C_Type *base) +{ + uint32_t i; + for (i = 0; i < (uint32_t)FSL_FEATURE_SOC_I2C_COUNT; i++) + { + if ((uint32_t)base == s_i2cBaseAddrs[i]) + { + break; + } + } + assert(i < (uint32_t)FSL_FEATURE_SOC_I2C_COUNT); + return i; +} + +/*! + * brief Provides a default configuration for the I2C master peripheral. + * + * This function provides the following default configuration for the I2C master peripheral: + * code + * masterConfig->enableMaster = true; + * masterConfig->baudRate_Bps = 100000U; + * masterConfig->enableTimeout = false; + * endcode + * + * After calling this function, you can override any settings in order to customize the configuration, + * prior to initializing the master driver with I2C_MasterInit(). + * + * param[out] masterConfig User provided configuration structure for default values. Refer to #i2c_master_config_t. + */ +void I2C_MasterGetDefaultConfig(i2c_master_config_t *masterConfig) +{ + /* Initializes the configure structure to zero. */ + (void)memset(masterConfig, 0, sizeof(*masterConfig)); + + masterConfig->enableMaster = true; + masterConfig->baudRate_Bps = 100000U; + masterConfig->enableTimeout = false; + masterConfig->timeout_Ms = 35; +} + +/*! + * brief Initializes the I2C master peripheral. + * + * This function enables the peripheral clock and initializes the I2C master peripheral as described by the user + * provided configuration. A software reset is performed prior to configuration. + * + * param base The I2C peripheral base address. + * param masterConfig User provided peripheral configuration. Use I2C_MasterGetDefaultConfig() to get a set of + * defaults + * that you can override. + * param srcClock_Hz Frequency in Hertz of the I2C functional clock. Used to calculate the baud rate divisors, + * filter widths, and timeout periods. + */ +void I2C_MasterInit(I2C_Type *base, const i2c_master_config_t *masterConfig, uint32_t srcClock_Hz) +{ + (void)FLEXCOMM_Init(base, FLEXCOMM_PERIPH_I2C); + I2C_MasterEnable(base, masterConfig->enableMaster); + I2C_MasterSetBaudRate(base, masterConfig->baudRate_Bps, srcClock_Hz); + I2C_MasterSetTimeoutValue(base, masterConfig->timeout_Ms, srcClock_Hz); +} + +/*! + * brief Deinitializes the I2C master peripheral. + * + * This function disables the I2C master peripheral and gates the clock. It also performs a software + * reset to restore the peripheral to reset conditions. + * + * param base The I2C peripheral base address. + */ +void I2C_MasterDeinit(I2C_Type *base) +{ + I2C_MasterEnable(base, false); +} + +/*! + * brief Gets the I2C status flags. + * + * A bit mask with the state of all I2C status flags is returned. For each flag, the corresponding bit + * in the return value is set if the flag is asserted. + * + * param base The I2C peripheral base address. + * return State of the status flags: + * - 1: related status flag is set. + * - 0: related status flag is not set. + * see ref _i2c_status_flags, ref _i2c_master_status_flags and ref _i2c_slave_status_flags. + */ +uint32_t I2C_GetStatusFlags(I2C_Type *base) +{ + uint32_t statusMask = base->STAT; + if ((statusMask & (uint32_t)I2C_STAT_MSTSTATE_MASK) == 0UL) + { + statusMask |= (uint32_t)kI2C_MasterIdleFlag; + } + if (((statusMask & (uint32_t)I2C_STAT_MSTSTATE_MASK) >> I2C_STAT_MSTSTATE_SHIFT) == 3UL) + { + statusMask = (statusMask & ~(uint32_t)I2C_STAT_MSTSTATE_MASK) | (uint32_t)kI2C_MasterAddrNackFlag; + } + if ((statusMask & (uint32_t)I2C_STAT_SLVSTATE_MASK) == 0UL) + { + statusMask |= (uint32_t)kI2C_SlaveAddressedFlag; + } + if ((statusMask & (uint32_t)I2C_STAT_SLVIDX_MASK) == 0UL) + { + statusMask |= (uint32_t)kI2C_SlaveAddress0MatchFlag; + } + if (((statusMask & (uint32_t)I2C_STAT_SLVIDX_MASK) >> I2C_STAT_SLVIDX_SHIFT) == 3UL) + { + statusMask = (statusMask & ~(uint32_t)I2C_STAT_SLVIDX_MASK) | (uint32_t)kI2C_SlaveAddress3MatchFlag; + } + return statusMask; +} + +/*! + * brief Sets the I2C bus frequency for master transactions. + * + * The I2C master is automatically disabled and re-enabled as necessary to configure the baud + * rate. Do not call this function during a transfer, or the transfer is aborted. + * + * param base The I2C peripheral base address. + * param srcClock_Hz I2C functional clock frequency in Hertz. + * param baudRate_Bps Requested bus frequency in bits per second. + */ +void I2C_MasterSetBaudRate(I2C_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz) +{ + uint32_t scl, divider; + uint32_t mindivider; + uint32_t err, best_err; + uint32_t best_scl = 0U; + uint32_t best_div = 0U; + +#if defined(FSL_FEATURE_I2C_PREPCLKFRG_8MHZ) && (FSL_FEATURE_I2C_PREPCLKFRG_8MHZ) + /* + * RFT1717/RFT1437: workaround for hardware bug when using DMA + * I2C peripheral clock frequency has to be fixed at 8MHz + * source clock is 32MHz or 48MHz so divider is a round integer value + */ + best_div = srcClock_Hz / 8000000U; + best_scl = 8000000U / baudRate_Bps; + + if ((8000000U / best_scl - baudRate_Bps) > (baudRate_Bps - (8000000U / (best_scl + 1U)))) + { + best_scl = best_scl + 1U; + } + + /* + * Fallback to usual baudrate computation method, when: + * 1.Master SCL frequency does not fit in workaround range, + * 2.User's setting of baudRate_Bps is 400kHz while the clock frequency after divval is larger than 2MHz + */ + if ((best_scl > 18U) || ((best_scl < 4U)) || ((baudRate_Bps == 400000U) && (srcClock_Hz / best_div > 2000000U))) + { +#endif /*FSL_FEATURE_I2C_PREPCLKFRG_8MHZ*/ + + /* Calculate the minimal divider value to make sure the clock frequency after divval is not larger than 2MHz */ + /* This is required in RM in order to generate 400kHz baudrate */ + mindivider = ((srcClock_Hz * 10U) / 2000000U + 5U) / 10U; + /* If the scl value with current mindivider is smaller than 4, which is the minimal value register can achieve, + update mindivider */ + if ((srcClock_Hz / mindivider / baudRate_Bps) < 4U) + { + mindivider = srcClock_Hz / 4U / baudRate_Bps; + } + /* Calculate the ideal div and scl value*/ + best_err = 0U; + for (divider = mindivider; divider <= 0x10000U; divider++) + { + /* Calculte ideal scl value, round up the value */ + scl = ((srcClock_Hz * 10U) / (divider * baudRate_Bps) + 5U) / 10U; + + /* adjust it if it is out of range */ + scl = (scl > 18U) ? 18U : scl; + + /* calculate error */ + err = srcClock_Hz - (baudRate_Bps * scl * divider); + if ((err < best_err) || (best_err == 0U)) + { + best_div = divider; + best_scl = scl; + best_err = err; + } + + if ((err == 0U) || (scl <= 4U)) + { + /* either exact value was found + or scl is at its min (it would be even smaller in the next iteration for sure) */ + break; + } + } +#if defined(FSL_FEATURE_I2C_PREPCLKFRG_8MHZ) && (FSL_FEATURE_I2C_PREPCLKFRG_8MHZ) + } +#endif /*FSL_FEATURE_I2C_PREPCLKFRG_8MHZ*/ + base->CLKDIV = I2C_CLKDIV_DIVVAL(best_div - 1U); + if (best_scl % 2U == 0U) + { + base->MSTTIME = I2C_MSTTIME_MSTSCLLOW(best_scl / 2U - 2U) | I2C_MSTTIME_MSTSCLHIGH(best_scl / 2U - 2U); + } + else + { + base->MSTTIME = I2C_MSTTIME_MSTSCLLOW(best_scl / 2U - 1U) | I2C_MSTTIME_MSTSCLHIGH(best_scl / 2U - 2U); + } +} + +/*! + * brief Sets the I2C bus timeout value. + * + * If the SCL signal remains low or bus does not have event longer than the timeout value, kI2C_SclTimeoutFlag or + * kI2C_EventTimeoutFlag is set. This can indicete the bus is held by slave or any fault occurs to the I2C module. + * + * param base The I2C peripheral base address. + * param timeout_Ms Timeout value in millisecond. + * param srcClock_Hz I2C functional clock frequency in Hertz. + */ +void I2C_MasterSetTimeoutValue(I2C_Type *base, uint8_t timeout_Ms, uint32_t srcClock_Hz) +{ + assert((timeout_Ms != 0U) && (srcClock_Hz != 0U)); + + /* The low 4 bits of the timout reister TIMEOUT is hard-wired to be 1, so the the time out value is always 16 times + the I2C functional clock, we only need to calculate the high bits. */ + uint32_t timeoutValue = ((uint32_t)timeout_Ms * srcClock_Hz / 16UL / 100UL + 5UL) / 10UL; + if (timeoutValue > 0x1000UL) + { + timeoutValue = 0x1000UL; + } + timeoutValue = ((timeoutValue - 1UL) << 4UL) | 0xFUL; + base->TIMEOUT = timeoutValue; +} + +static status_t I2C_PendingStatusWait(I2C_Type *base) +{ + status_t result = kStatus_Success; + uint32_t status; + +#if I2C_RETRY_TIMES != 0U + uint32_t waitTimes = I2C_RETRY_TIMES; +#endif + + do + { + status = I2C_GetStatusFlags(base); + if ((status & (uint32_t)kI2C_EventTimeoutFlag) != 0U) + { + result = kStatus_I2C_EventTimeout; + } + if ((status & (uint32_t)kI2C_SclTimeoutFlag) != 0U) + { + result = kStatus_I2C_SclLowTimeout; + } +#if defined(FSL_FEATURE_I2C_TIMEOUT_RECOVERY) && FSL_FEATURE_I2C_TIMEOUT_RECOVERY + if (result != kStatus_Success) + { + I2C_MasterEnable(base, false); + I2C_MasterEnable(base, true); + break; + } +#endif +#if I2C_RETRY_TIMES != 0U + waitTimes--; + } while (((status & (uint32_t)kI2C_MasterPendingFlag) == 0U) && (waitTimes != 0U)); + + if (waitTimes == 0U) + { +#if defined(FSL_FEATURE_I2C_TIMEOUT_RECOVERY) && FSL_FEATURE_I2C_TIMEOUT_RECOVERY + I2C_MasterEnable(base, false); + I2C_MasterEnable(base, true); +#endif + return kStatus_I2C_Timeout; + } +#else + } while ((status & (uint32_t)kI2C_MasterPendingFlag) == 0U); +#endif + + if ((status & (uint32_t)kI2C_MasterArbitrationLostFlag) != 0U) + { + result = kStatus_I2C_ArbitrationLost; + } + + if ((status & (uint32_t)kI2C_MasterStartStopErrorFlag) != 0U) + { + result = kStatus_I2C_StartStopError; + } + + /* Clear controller state. */ + I2C_ClearStatusFlags( + base, (uint32_t)kI2C_MasterAllClearFlags | (uint32_t)kI2C_EventTimeoutFlag | (uint32_t)kI2C_SclTimeoutFlag); + + return result; +} + +/*! + * brief Sends a START on the I2C bus. + * + * This function is used to initiate a new master mode transfer by sending the START signal. + * The slave address is sent following the I2C START signal. + * + * param base I2C peripheral base pointer + * param address 7-bit slave device address. + * param direction Master transfer directions(transmit/receive). + * retval kStatus_Success Successfully send the start signal. + * retval kStatus_I2C_Busy Current bus is busy. + */ +status_t I2C_MasterStart(I2C_Type *base, uint8_t address, i2c_direction_t direction) +{ + status_t result; + result = I2C_PendingStatusWait(base); + if (result != kStatus_Success) + { + return result; + } + + /* Write Address and RW bit to data register */ + base->MSTDAT = ((uint32_t)address << 1) | ((uint32_t)direction & 1U); + /* Start the transfer */ + base->MSTCTL = I2C_MSTCTL_MSTSTART_MASK; + + return kStatus_Success; +} + +/*! + * brief Sends a STOP signal on the I2C bus. + * + * retval kStatus_Success Successfully send the stop signal. + * retval kStatus_I2C_Timeout Send stop signal failed, timeout. + */ +status_t I2C_MasterStop(I2C_Type *base) +{ + status_t result = I2C_PendingStatusWait(base); + if (result != kStatus_Success) + { + return result; + } + + base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; + return kStatus_Success; +} + +/*! + * brief Performs a polling send transfer on the I2C bus. + * + * Sends up to a txSize number of bytes to the previously addressed slave device. The slave may + * reply with a NAK to any byte in order to terminate the transfer early. If this happens, this + * function returns #kStatus_I2C_Nak. + * + * param base The I2C peripheral base address. + * param txBuff The pointer to the data to be transferred. + * param txSize The length in bytes of the data to be transferred. + * param flags Transfer control flag to control special behavior like suppressing start or stop, for normal transfers + * use kI2C_TransferDefaultFlag + * retval kStatus_Success Data was sent successfully. + * retval #kStatus_I2C_Busy Another master is currently utilizing the bus. + * retval #kStatus_I2C_Nak The slave device sent a NAK in response to a byte. + * retval #kStatus_I2C_ArbitrationLost Arbitration lost error. + */ +status_t I2C_MasterWriteBlocking(I2C_Type *base, const void *txBuff, size_t txSize, uint32_t flags) +{ + uint32_t master_state; + status_t err; + + const uint8_t *buf = (const uint8_t *)txBuff; + + assert(txBuff != NULL); + + err = kStatus_Success; + while (txSize != 0U) + { + err = I2C_PendingStatusWait(base); + + if (err != kStatus_Success) + { + return err; + } + + master_state = (base->STAT & I2C_STAT_MSTSTATE_MASK) >> I2C_STAT_MSTSTATE_SHIFT; + switch (master_state) + { + case I2C_STAT_MSTCODE_TXREADY: + /* ready to send next byte */ + base->MSTDAT = *buf++; + txSize--; + base->MSTCTL = I2C_MSTCTL_MSTCONTINUE_MASK; + break; + + case I2C_STAT_MSTCODE_NACKADR: + case I2C_STAT_MSTCODE_NACKDAT: + err = kStatus_I2C_Nak; + /* Issue nack signal when nacked by slave. */ + (void)I2C_MasterStop(base); + break; + + default: + /* unexpected state */ + err = kStatus_I2C_UnexpectedState; + break; + } + + if (err != kStatus_Success) + { + return err; + } + } + + err = I2C_PendingStatusWait(base); + + if (err != kStatus_Success) + { + return err; + } + +#if !I2C_MASTER_TRANSMIT_IGNORE_LAST_NACK + /* Check nack signal. If master is nacked by slave of the last byte, return kStatus_I2C_Nak. */ + if (((base->STAT & I2C_STAT_MSTSTATE_MASK) >> I2C_STAT_MSTSTATE_SHIFT) == (uint32_t)I2C_STAT_MSTCODE_NACKDAT) + { + (void)I2C_MasterStop(base); + return kStatus_I2C_Nak; + } +#endif + + if (0U == (flags & (uint32_t)kI2C_TransferNoStopFlag)) + { + /* Initiate stop */ + base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; + err = I2C_PendingStatusWait(base); + if (err != kStatus_Success) + { + return err; + } + } + + return kStatus_Success; +} + +/*! + * brief Performs a polling receive transfer on the I2C bus. + * + * param base The I2C peripheral base address. + * param rxBuff The pointer to the data to be transferred. + * param rxSize The length in bytes of the data to be transferred. + * param flags Transfer control flag to control special behavior like suppressing start or stop, for normal transfers + * use kI2C_TransferDefaultFlag + * retval kStatus_Success Data was received successfully. + * retval #kStatus_I2C_Busy Another master is currently utilizing the bus. + * retval #kStatus_I2C_Nak The slave device sent a NAK in response to a byte. + * retval #kStatus_I2C_ArbitrationLost Arbitration lost error. + */ +status_t I2C_MasterReadBlocking(I2C_Type *base, void *rxBuff, size_t rxSize, uint32_t flags) +{ + uint32_t master_state; + status_t err; + + uint8_t *buf = (uint8_t *)(rxBuff); + + assert(rxBuff != NULL); + + err = kStatus_Success; + while (rxSize != 0U) + { + err = I2C_PendingStatusWait(base); + + if (err != kStatus_Success) + { + return err; + } + + master_state = (base->STAT & I2C_STAT_MSTSTATE_MASK) >> I2C_STAT_MSTSTATE_SHIFT; + switch (master_state) + { + case I2C_STAT_MSTCODE_RXREADY: + /* ready to send next byte */ + *(buf++) = (uint8_t)base->MSTDAT; + if (--rxSize != 0U) + { + base->MSTCTL = I2C_MSTCTL_MSTCONTINUE_MASK; + } + else + { + if ((flags & (uint32_t)kI2C_TransferNoStopFlag) == 0U) + { + /* initiate NAK and stop */ + base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; + err = I2C_PendingStatusWait(base); + } + } + break; + + case I2C_STAT_MSTCODE_NACKADR: + case I2C_STAT_MSTCODE_NACKDAT: + /* slave nacked the last byte */ + err = kStatus_I2C_Nak; + break; + + default: + /* unexpected state */ + err = kStatus_I2C_UnexpectedState; + break; + } + + if (err != kStatus_Success) + { + return err; + } + } + + return kStatus_Success; +} + +static status_t I2C_MasterCheckStartResponse(I2C_Type *base) +{ + /* Wait for start signal to be transmitted. */ + status_t result = I2C_PendingStatusWait(base); + + if (result != kStatus_Success) + { + return result; + } + + if (((base->STAT & I2C_STAT_MSTSTATE_MASK) >> I2C_STAT_MSTSTATE_SHIFT) == I2C_STAT_MSTCODE_NACKADR) + { + (void)I2C_MasterStop(base); + return kStatus_I2C_Addr_Nak; + } + return kStatus_Success; +} + +/*! + * brief Performs a master polling transfer on the I2C bus. + * + * note The API does not return until the transfer succeeds or fails due + * to arbitration lost or receiving a NAK. + * + * param base I2C peripheral base address. + * param xfer Pointer to the transfer structure. + * retval kStatus_Success Successfully complete the data transmission. + * retval kStatus_I2C_Busy Previous transmission still not finished. + * retval kStatus_I2C_Timeout Transfer error, wait signal timeout. + * retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost. + * retval kStataus_I2C_Nak Transfer error, receive NAK during transfer. + * retval kStataus_I2C_Addr_Nak Transfer error, receive NAK during addressing. + */ +status_t I2C_MasterTransferBlocking(I2C_Type *base, i2c_master_transfer_t *xfer) +{ + status_t result = kStatus_Success; + uint32_t subaddress; + uint8_t subaddrBuf[4]; + i2c_direction_t direction; + int i; + + assert(xfer != NULL); + + /* If start signal is requested, send start signal. */ + if (0U == (xfer->flags & (uint32_t)kI2C_TransferNoStartFlag)) + { + direction = (xfer->subaddressSize != 0U) ? kI2C_Write : xfer->direction; + result = I2C_MasterStart(base, xfer->slaveAddress, direction); + if (result == kStatus_Success) + { + result = I2C_MasterCheckStartResponse(base); + if (result != kStatus_Success) + { + return result; + } + if ((xfer->subaddressSize) != 0U) + { + /* Prepare subaddress transmit buffer, most significant byte is stored at the lowest address */ + subaddress = xfer->subaddress; + for (i = (int)xfer->subaddressSize - 1; i >= 0; i--) + { + subaddrBuf[i] = (uint8_t)subaddress & 0xffU; + subaddress >>= 8; + } + /* Send subaddress. */ + result = + I2C_MasterWriteBlocking(base, subaddrBuf, xfer->subaddressSize, (uint32_t)kI2C_TransferNoStopFlag); + if (result != kStatus_Success) + { + if (result == kStatus_I2C_Nak) + { + (void)I2C_MasterStop(base); + return kStatus_I2C_Addr_Nak; + } + } + else if (xfer->direction == kI2C_Read) + { + result = I2C_MasterRepeatedStart(base, xfer->slaveAddress, xfer->direction); + if (result == kStatus_Success) + { + result = I2C_MasterCheckStartResponse(base); + if (result != kStatus_Success) + { + return result; + } + } + } + else + { + /* Empty else block to avoid MISRA 14.1 violation. */ + } + } + } + } + + if (result == kStatus_Success) + { + if ((xfer->direction == kI2C_Write) && (xfer->dataSize > 0U)) + { + /* Transmit data. */ + result = I2C_MasterWriteBlocking(base, xfer->data, xfer->dataSize, xfer->flags); + } + else + { + if ((xfer->direction == kI2C_Read) && (xfer->dataSize > 0U)) + { + /* Receive Data. */ + result = I2C_MasterReadBlocking(base, xfer->data, xfer->dataSize, xfer->flags); + } + } + } + + if (result == kStatus_I2C_Nak) + { + (void)I2C_MasterStop(base); + } + + return result; +} + +/*! + * brief Creates a new handle for the I2C master non-blocking APIs. + * + * The creation of a handle is for use with the non-blocking APIs. Once a handle + * is created, there is not a corresponding destroy handle. If the user wants to + * terminate a transfer, the I2C_MasterTransferAbort() API shall be called. + * + * param base The I2C peripheral base address. + * param[out] handle Pointer to the I2C master driver handle. + * param callback User provided pointer to the asynchronous callback function. + * param userData User provided pointer to the application callback data. + */ +void I2C_MasterTransferCreateHandle(I2C_Type *base, + i2c_master_handle_t *handle, + i2c_master_transfer_callback_t callback, + void *userData) +{ + assert(handle != NULL); + + uint32_t instance; + i2c_to_flexcomm_t handler; + handler.i2c_master_handler = I2C_MasterTransferHandleIRQ; + + /* Clear out the handle. */ + (void)memset(handle, 0, sizeof(*handle)); + + /* Look up instance number */ + instance = I2C_GetInstance(base); + + /* Save base and instance. */ + handle->completionCallback = callback; + handle->userData = userData; + + FLEXCOMM_SetIRQHandler(base, handler.flexcomm_handler, handle); + + /* Clear internal IRQ enables and enable NVIC IRQ. */ + I2C_DisableInterrupts(base, (uint32_t)kI2C_MasterIrqFlags); + (void)EnableIRQ(s_i2cIRQ[instance]); +} + +/*! + * brief Performs a non-blocking transaction on the I2C bus. + * + * param base The I2C peripheral base address. + * param handle Pointer to the I2C master driver handle. + * param xfer The pointer to the transfer descriptor. + * retval kStatus_Success The transaction was started successfully. + * retval #kStatus_I2C_Busy Either another master is currently utilizing the bus, or a non-blocking + * transaction is already in progress. + */ +status_t I2C_MasterTransferNonBlocking(I2C_Type *base, i2c_master_handle_t *handle, i2c_master_transfer_t *xfer) +{ + status_t result; + + assert(handle != NULL); + assert(xfer != NULL); + assert(xfer->subaddressSize <= sizeof(xfer->subaddress)); + + /* Return busy if another transaction is in progress. */ + if (handle->state != (uint8_t)kIdleState) + { + return kStatus_I2C_Busy; + } + + /* Disable I2C IRQ sources while we configure stuff. */ + I2C_DisableInterrupts(base, (uint32_t)kI2C_MasterIrqFlags); + + /* Prepare transfer state machine. */ + result = I2C_InitTransferStateMachine(base, handle, xfer); + + /* Clear error flags. */ + I2C_ClearStatusFlags(base, I2C_STAT_MSTARBLOSS_MASK | I2C_STAT_MSTSTSTPERR_MASK); + + /* Enable I2C internal IRQ sources. */ + I2C_EnableInterrupts(base, (uint32_t)kI2C_MasterIrqFlags); + + return result; +} + +/*! + * brief Returns number of bytes transferred so far. + * param base The I2C peripheral base address. + * param handle Pointer to the I2C master driver handle. + * param[out] count Number of bytes transferred so far by the non-blocking transaction. + * retval kStatus_Success + * retval #kStatus_I2C_Busy + */ +status_t I2C_MasterTransferGetCount(I2C_Type *base, i2c_master_handle_t *handle, size_t *count) +{ + assert(handle != NULL); + + if (NULL == count) + { + return kStatus_InvalidArgument; + } + + /* Catch when there is not an active transfer. */ + if (handle->state == (uint8_t)kIdleState) + { + *count = 0; + return kStatus_NoTransferInProgress; + } + + /* There is no necessity to disable interrupts as we read a single integer value */ + *count = handle->transferCount; + return kStatus_Success; +} + +/*! + * brief Terminates a non-blocking I2C master transmission early. + * + * note It is not safe to call this function from an IRQ handler that has a higher priority than the + * I2C peripheral's IRQ priority. + * + * param base The I2C peripheral base address. + * param handle Pointer to the I2C master driver handle. + * retval kStatus_Success A transaction was successfully aborted. + * retval #kStatus_I2C_Timeout Timeout during polling for flags. + */ +status_t I2C_MasterTransferAbort(I2C_Type *base, i2c_master_handle_t *handle) +{ + status_t result = kStatus_Success; + uint32_t master_state; + + if (handle->state != (uint8_t)kIdleState) + { + /* Disable internal IRQ enables. */ + I2C_DisableInterrupts(base, (uint32_t)kI2C_MasterIrqFlags); + + /* Wait until module is ready */ + result = I2C_PendingStatusWait(base); + + if (result != kStatus_Success) + { + handle->state = (uint8_t)kIdleState; + return result; + } + + /* Get the state of the I2C module */ + master_state = (base->STAT & I2C_STAT_MSTSTATE_MASK) >> I2C_STAT_MSTSTATE_SHIFT; + + if (master_state != (uint32_t)I2C_STAT_MSTCODE_IDLE) + { + /* Send a stop command to finalize the transfer. */ + base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; + + /* Wait until the STOP is completed */ + result = I2C_PendingStatusWait(base); + + if (result != kStatus_Success) + { + handle->state = (uint8_t)kIdleState; + return result; + } + } + + /* Reset handle. */ + handle->state = (uint8_t)kIdleState; + handle->checkAddrNack = false; + } + return kStatus_Success; +} + +static status_t I2C_InitTransferStateMachine(I2C_Type *base, i2c_master_handle_t *handle, i2c_master_transfer_t *xfer) +{ + struct _i2c_master_transfer *transfer; + + handle->transfer = *xfer; + transfer = &(handle->transfer); + + handle->transferCount = 0; + handle->remainingBytes = transfer->dataSize; + handle->buf = (uint8_t *)transfer->data; + handle->remainingSubaddr = 0; + handle->checkAddrNack = false; + + if ((transfer->flags & (uint32_t)kI2C_TransferNoStartFlag) != 0U) + { + /* Start condition shall be ommited, switch directly to next phase */ + if (transfer->dataSize == 0U) + { + handle->state = (uint8_t)kStopState; + } + else if (handle->transfer.direction == kI2C_Write) + { + handle->state = (uint8_t)kTransmitDataState; + } + else if (handle->transfer.direction == kI2C_Read) + { + handle->state = (uint8_t)kReceiveDataBeginState; + } + else + { + return kStatus_I2C_InvalidParameter; + } + } + else + { + if (transfer->subaddressSize != 0U) + { + int i; + uint32_t subaddress; + + if (transfer->subaddressSize > sizeof(handle->subaddrBuf)) + { + return kStatus_I2C_InvalidParameter; + } + + /* Prepare subaddress transmit buffer, most significant byte is stored at the lowest address */ + subaddress = xfer->subaddress; + for (i = (int)xfer->subaddressSize - 1; i >= 0; i--) + { + handle->subaddrBuf[i] = (uint8_t)subaddress & 0xffU; + subaddress >>= 8; + } + handle->remainingSubaddr = transfer->subaddressSize; + } + handle->state = (uint8_t)kStartState; + handle->checkAddrNack = true; + } + + return kStatus_Success; +} + +static status_t I2C_RunTransferStateMachine(I2C_Type *base, i2c_master_handle_t *handle, bool *isDone) +{ + uint32_t status; + uint32_t master_state; + struct _i2c_master_transfer *transfer; + status_t err; + + transfer = &(handle->transfer); + bool ignoreNak = ((handle->state == (uint8_t)kWaitForCompletionState) && (handle->remainingBytes == 0U)) +#if I2C_MASTER_TRANSMIT_IGNORE_LAST_NACK + /* If master is nacked by slave after the last byte during transmit, ignore the nack. */ + || ((handle->state == (uint8_t)kStopState) && (handle->remainingBytes == 0U)) +#endif + ; + + *isDone = false; + + status = I2C_GetStatusFlags(base); + + if ((status & I2C_STAT_MSTARBLOSS_MASK) != 0U) + { + I2C_ClearStatusFlags(base, I2C_STAT_MSTARBLOSS_MASK); + return kStatus_I2C_ArbitrationLost; + } + + if ((status & I2C_STAT_MSTSTSTPERR_MASK) != 0U) + { + I2C_ClearStatusFlags(base, I2C_STAT_MSTSTSTPERR_MASK); + return kStatus_I2C_StartStopError; + } + + /* Event timeout happens when the time since last bus event has been longer than the time specified by TIMEOUT + register. eg: Start signal fails to generate, no error status is set and transfer hangs if glitch on bus happens + before, the timeout status can be used to avoid the transfer hangs indefinitely. */ + if ((status & (uint32_t)kI2C_EventTimeoutFlag) != 0U) + { + I2C_ClearStatusFlags(base, (uint32_t)kI2C_EventTimeoutFlag); + return kStatus_I2C_EventTimeout; + } + + /* SCL timeout happens when the slave is holding the SCL line low and the time has been longer than the time + specified by TIMEOUT register. */ + if ((status & (uint32_t)kI2C_SclTimeoutFlag) != 0U) + { + I2C_ClearStatusFlags(base, (uint32_t)kI2C_SclTimeoutFlag); + return kStatus_I2C_SclLowTimeout; + } + + if ((status & I2C_STAT_MSTPENDING_MASK) == 0U) + { + return kStatus_I2C_Busy; + } + + /* Get the hardware state of the I2C module */ + master_state = (base->STAT & I2C_STAT_MSTSTATE_MASK) >> I2C_STAT_MSTSTATE_SHIFT; + if (((master_state == (uint32_t)I2C_STAT_MSTCODE_NACKADR) || + (master_state == (uint32_t)I2C_STAT_MSTCODE_NACKDAT)) && + (ignoreNak != true)) + { + /* Slave NACKed last byte, issue stop and return error */ + base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; + handle->state = (uint8_t)kWaitForCompletionState; + /* If master is nacked during slave probe or during sending subaddress, return kStatus_I2C_ADDR_Nak. */ + if ((master_state == (uint32_t)I2C_STAT_MSTCODE_NACKADR) || (handle->checkAddrNack)) + { + return kStatus_I2C_Addr_Nak; + } + else /* Otherwise just return kStatus_I2C_Nak */ + { + return kStatus_I2C_Nak; + } + } + + err = kStatus_Success; + switch (handle->state) + { + case (uint8_t)kStartState: + if (handle->remainingSubaddr != 0U) + { + /* Subaddress takes precedence over the data transfer, direction is always "write" in this case */ + base->MSTDAT = (uint32_t)transfer->slaveAddress << 1U; + handle->state = (uint8_t)kTransmitSubaddrState; + } + else if (transfer->direction == kI2C_Write) + { + base->MSTDAT = (uint32_t)transfer->slaveAddress << 1; + handle->state = (handle->remainingBytes != 0U) ? (uint8_t)kTransmitDataState : (uint8_t)kStopState; + } + else + { + base->MSTDAT = ((uint32_t)transfer->slaveAddress << 1) | 1u; + handle->state = (handle->remainingBytes != 0U) ? (uint8_t)kReceiveDataState : (uint8_t)kStopState; + } + /* Send start condition */ + base->MSTCTL = I2C_MSTCTL_MSTSTART_MASK; + break; + + case (uint8_t)kTransmitSubaddrState: + if (master_state != (uint32_t)I2C_STAT_MSTCODE_TXREADY) + { + return kStatus_I2C_UnexpectedState; + } + /* Most significant subaddress byte comes first */ + base->MSTDAT = handle->subaddrBuf[handle->transfer.subaddressSize - handle->remainingSubaddr]; + base->MSTCTL = I2C_MSTCTL_MSTCONTINUE_MASK; + if (--(handle->remainingSubaddr) != 0U) + { + /* There are still subaddress bytes to be transmitted */ + break; + } + if (handle->remainingBytes != 0U) + { + /* There is data to be transferred, if there is write to read turnaround it is necessary to perform + * repeated start */ + handle->state = (transfer->direction == kI2C_Read) ? (uint8_t)kStartState : (uint8_t)kTransmitDataState; + } + else + { + /* No more data, schedule stop condition */ + handle->state = (uint8_t)kStopState; + } + break; + + case (uint8_t)kTransmitDataState: + handle->checkAddrNack = false; + if (master_state != (uint32_t)I2C_STAT_MSTCODE_TXREADY) + { + return kStatus_I2C_UnexpectedState; + } + base->MSTDAT = *(handle->buf)++; + base->MSTCTL = I2C_MSTCTL_MSTCONTINUE_MASK; + if (--handle->remainingBytes == 0U) + { + /* No more data, schedule stop condition */ + handle->state = (uint8_t)kStopState; + } + handle->transferCount++; + break; + + case (uint8_t)kReceiveDataBeginState: + handle->checkAddrNack = false; + if (master_state != (uint32_t)I2C_STAT_MSTCODE_RXREADY) + { + return kStatus_I2C_UnexpectedState; + } + (void)base->MSTDAT; + base->MSTCTL = I2C_MSTCTL_MSTCONTINUE_MASK; + handle->state = (uint8_t)kReceiveDataState; + break; + + case (uint8_t)kReceiveDataState: + handle->checkAddrNack = false; + if (master_state != (uint32_t)I2C_STAT_MSTCODE_RXREADY) + { + return kStatus_I2C_UnexpectedState; + } + *(handle->buf)++ = (uint8_t)base->MSTDAT; + if (--handle->remainingBytes != 0U) + { + base->MSTCTL = I2C_MSTCTL_MSTCONTINUE_MASK; + } + else + { + /* No more data expected, issue NACK and STOP right away */ + if (0U == (transfer->flags & (uint32_t)kI2C_TransferNoStopFlag)) + { + base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; + } + handle->state = (uint8_t)kWaitForCompletionState; + } + handle->transferCount++; + break; + + case (uint8_t)kStopState: + handle->checkAddrNack = false; + if ((transfer->flags & (uint32_t)kI2C_TransferNoStopFlag) != 0U) + { + /* Stop condition is omitted, we are done */ + *isDone = true; + handle->state = (uint8_t)kIdleState; + break; + } + /* Send stop condition */ + base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; + handle->state = (uint8_t)kWaitForCompletionState; + break; + + case (uint8_t)kWaitForCompletionState: + *isDone = true; + handle->state = (uint8_t)kIdleState; + break; + + case (uint8_t)kIdleState: + default: + /* State machine shall not be invoked again once it enters the idle state */ + err = kStatus_I2C_UnexpectedState; + break; + } + + return err; +} + +/*! + * brief Reusable routine to handle master interrupts. + * note This function does not need to be called unless you are reimplementing the + * nonblocking API's interrupt handler routines to add special functionality. + * param base The I2C peripheral base address. + * param handle Pointer to the I2C master driver handle. + */ +void I2C_MasterTransferHandleIRQ(I2C_Type *base, i2c_master_handle_t *handle) +{ + bool isDone; + status_t result; + + /* Don't do anything if we don't have a valid handle. */ + if (NULL == handle) + { + return; + } + + result = I2C_RunTransferStateMachine(base, handle, &isDone); + + if ((result != kStatus_Success) || isDone) + { + /* Restore handle to idle state. */ + handle->state = (uint8_t)kIdleState; + + /* Disable internal IRQ enables. */ + I2C_DisableInterrupts(base, (uint32_t)kI2C_MasterIrqFlags); + + /* Invoke callback. */ + if (handle->completionCallback != NULL) + { + handle->completionCallback(base, handle, result, handle->userData); + } + } +} + +static void I2C_SlaveInternalStateMachineReset(I2C_Type *base) +{ + I2C_SlaveEnable(base, false); /* clear SLVEN Slave enable bit */ +} + +static status_t I2C_SlaveDivVal(uint32_t srcClock_Hz, i2c_slave_bus_speed_t busSpeed, uint32_t *divVal) +{ + uint32_t dataSetupTime_ns; + + switch ((uint8_t)(busSpeed)) + { + case (uint8_t)kI2C_SlaveStandardMode: + dataSetupTime_ns = 250U; + break; + + case (uint8_t)kI2C_SlaveFastMode: + dataSetupTime_ns = 100U; + break; + + case (uint8_t)kI2C_SlaveFastModePlus: + dataSetupTime_ns = 50U; + break; + + case (uint8_t)kI2C_SlaveHsMode: + dataSetupTime_ns = 10U; + break; + + default: + dataSetupTime_ns = 0U; + break; + } + + if (0U == dataSetupTime_ns) + { + return kStatus_InvalidArgument; + } + + /* divVal = (sourceClock_Hz / 1000000) * (dataSetupTime_ns / 1000) */ + *divVal = srcClock_Hz / 1000U; + *divVal = (*divVal) * dataSetupTime_ns; + *divVal = (*divVal) / 1000000U; + + if ((*divVal) > I2C_CLKDIV_DIVVAL_MASK) + { + *divVal = I2C_CLKDIV_DIVVAL_MASK; + } + + return kStatus_Success; +} + +static uint32_t I2C_SlavePollPending(I2C_Type *base) +{ + uint32_t stat; + +#if I2C_RETRY_TIMES != 0U + uint32_t waitTimes = I2C_RETRY_TIMES; +#endif + do + { + stat = base->STAT; +#if I2C_RETRY_TIMES != 0U + waitTimes--; + } while ((0U == (stat & I2C_STAT_SLVPENDING_MASK)) && (waitTimes != 0U)); + + if (waitTimes == 0U) + { + return (uint32_t)kStatus_I2C_Timeout; + } +#else + } while (0U == (stat & I2C_STAT_SLVPENDING_MASK)); +#endif + + return stat; +} + +static void I2C_SlaveInvokeEvent(I2C_Type *base, i2c_slave_handle_t *handle, i2c_slave_transfer_event_t event) +{ + uint32_t eventMask = handle->transfer.eventMask; + handle->transfer.event = event; + if (((handle->callback) != NULL) && ((eventMask & (uint32_t)event) != 0U)) + { + handle->callback(base, &handle->transfer, handle->userData); + + size_t txSize = handle->transfer.txSize; + size_t rxSize = handle->transfer.rxSize; + /* if after event callback we have data buffer (callback func has added new data), keep transfer busy */ + if (false == handle->isBusy) + { + if (((handle->transfer.txData != NULL) && (txSize != 0U)) || + ((handle->transfer.rxData != NULL) && (rxSize != 0U))) + { + handle->isBusy = true; + } + } + + /* Clear the transferred count now that we have a new buffer. */ + if ((event == kI2C_SlaveReceiveEvent) || (event == kI2C_SlaveTransmitEvent)) + { + handle->transfer.transferredCount = 0; + } + } +} + +static bool I2C_SlaveAddressIRQ(I2C_Type *base, i2c_slave_handle_t *handle) +{ + uint8_t addressByte0; + size_t txSize; + size_t rxSize; + + addressByte0 = (uint8_t)base->SLVDAT; + + /* store the matched address */ + handle->transfer.receivedAddress = addressByte0; + + /* R/nW */ + if ((addressByte0 & 1U) != 0U) + { + txSize = handle->transfer.txSize; + /* if we have no data in this transfer, call callback to get new */ + if ((handle->transfer.txData == NULL) || (txSize == 0U)) + { + I2C_SlaveInvokeEvent(base, handle, kI2C_SlaveTransmitEvent); + } + + txSize = handle->transfer.txSize; + /* NACK if we have no data in this transfer. */ + if ((handle->transfer.txData == NULL) || (txSize == 0U)) + { + base->SLVCTL = I2C_SLVCTL_SLVNACK_MASK; + return false; + } + + /* master wants to read, so slave transmit is next state */ + handle->slaveFsm = kI2C_SlaveFsmTransmit; + } + else + { + rxSize = handle->transfer.rxSize; + /* if we have no receive buffer in this transfer, call callback to get new */ + if ((handle->transfer.rxData == NULL) || (rxSize == 0U)) + { + I2C_SlaveInvokeEvent(base, handle, kI2C_SlaveReceiveEvent); + } + + rxSize = handle->transfer.rxSize; + /* NACK if we have no data in this transfer */ + if ((handle->transfer.rxData == NULL) || (rxSize == 0U)) + { + base->SLVCTL = I2C_SLVCTL_SLVNACK_MASK; + return false; + } + + /* master wants write, so slave receive is next state */ + handle->slaveFsm = kI2C_SlaveFsmReceive; + } + + /* continue transaction */ + base->SLVCTL = I2C_SLVCTL_SLVCONTINUE_MASK; + + return true; +} + +static status_t I2C_SlaveTransferNonBlockingInternal(I2C_Type *base, + i2c_slave_handle_t *handle, + const void *txData, + size_t txSize, + void *rxData, + size_t rxSize, + uint32_t eventMask) +{ + assert(handle != NULL); + + status_t status; + status = kStatus_Success; + + /* Disable I2C IRQ sources while we configure stuff. */ + I2C_DisableInterrupts(base, (uint32_t)kI2C_SlaveIrqFlags); + + /* Return busy if another transaction is in progress. */ + if (handle->isBusy) + { + status = kStatus_I2C_Busy; + } + + /* Save transfer into handle. */ + handle->transfer.txData = (const uint8_t *)txData; + handle->transfer.txSize = txSize; + handle->transfer.rxData = (uint8_t *)rxData; + handle->transfer.rxSize = rxSize; + handle->transfer.transferredCount = 0; + handle->transfer.eventMask = eventMask | (uint32_t)kI2C_SlaveTransmitEvent | (uint32_t)kI2C_SlaveReceiveEvent; + handle->isBusy = true; + + /* Set the SLVEN bit to 1 in the CFG register. */ + I2C_SlaveEnable(base, true); + + /* Clear w1c flags. */ + base->STAT |= 0u; + + /* Enable I2C internal IRQ sources. */ + I2C_EnableInterrupts(base, (uint32_t)kI2C_SlaveIrqFlags); + + return status; +} + +/*! + * brief Starts accepting master read from slave requests. + * + * The function can be called in response to #kI2C_SlaveTransmitEvent callback to start a new slave Tx transfer + * from within the transfer callback. + * + * The set of events received by the callback is customizable. To do so, set the a eventMask parameter to + * the OR'd combination of #i2c_slave_transfer_event_t enumerators for the events you wish to receive. + * The #kI2C_SlaveTransmitEvent and #kI2C_SlaveReceiveEvent events are always enabled and do not need + * to be included in the mask. Alternatively, you can pass 0 to get a default set of only the transmit and + * receive events that are always enabled. In addition, the #kI2C_SlaveAllEvents constant is provided as + * a convenient way to enable all events. + * + * param base The I2C peripheral base address. + * param transfer Pointer to #i2c_slave_transfer_t structure. + * param txData Pointer to data to send to master. + * param txSize Size of txData in bytes. + * param eventMask Bit mask formed by OR'ing together #i2c_slave_transfer_event_t enumerators to specify + * which events to send to the callback. Other accepted values are 0 to get a default set of + * only the transmit and receive events, and #kI2C_SlaveAllEvents to enable all events. + * + * retval kStatus_Success Slave transfers were successfully started. + * retval #kStatus_I2C_Busy Slave transfers have already been started on this handle. + */ +status_t I2C_SlaveSetSendBuffer( + I2C_Type *base, volatile i2c_slave_transfer_t *transfer, const void *txData, size_t txSize, uint32_t eventMask) +{ + return I2C_SlaveTransferNonBlockingInternal(base, transfer->handle, txData, txSize, NULL, 0u, eventMask); +} + +/*! + * brief Starts accepting master write to slave requests. + * + * The function can be called in response to #kI2C_SlaveReceiveEvent callback to start a new slave Rx transfer + * from within the transfer callback. + * + * The set of events received by the callback is customizable. To do so, set the a eventMask parameter to + * the OR'd combination of #i2c_slave_transfer_event_t enumerators for the events you wish to receive. + * The #kI2C_SlaveTransmitEvent and #kI2C_SlaveReceiveEvent events are always enabled and do not need + * to be included in the mask. Alternatively, you can pass 0 to get a default set of only the transmit and + * receive events that are always enabled. In addition, the #kI2C_SlaveAllEvents constant is provided as + * a convenient way to enable all events. + * + * param base The I2C peripheral base address. + * param transfer Pointer to #i2c_slave_transfer_t structure. + * param rxData Pointer to data to store data from master. + * param rxSize Size of rxData in bytes. + * param eventMask Bit mask formed by OR'ing together #i2c_slave_transfer_event_t enumerators to specify + * which events to send to the callback. Other accepted values are 0 to get a default set of + * only the transmit and receive events, and #kI2C_SlaveAllEvents to enable all events. + * + * retval kStatus_Success Slave transfers were successfully started. + * retval #kStatus_I2C_Busy Slave transfers have already been started on this handle. + */ +status_t I2C_SlaveSetReceiveBuffer( + I2C_Type *base, volatile i2c_slave_transfer_t *transfer, void *rxData, size_t rxSize, uint32_t eventMask) +{ + return I2C_SlaveTransferNonBlockingInternal(base, transfer->handle, NULL, 0u, rxData, rxSize, eventMask); +} + +/*! + * brief Configures Slave Address n register. + * + * This function writes new value to Slave Address register. + * + * param base The I2C peripheral base address. + * param addressRegister The module supports multiple address registers. The parameter determines which one shall be + * changed. + * param address The slave address to be stored to the address register for matching. + * param addressDisable Disable matching of the specified address register. + */ +void I2C_SlaveSetAddress(I2C_Type *base, + i2c_slave_address_register_t addressRegister, + uint8_t address, + bool addressDisable) +{ + base->SLVADR[addressRegister] = I2C_SLVADR_SLVADR(address) | I2C_SLVADR_SADISABLE(addressDisable); +} + +/*! + * brief Provides a default configuration for the I2C slave peripheral. + * + * This function provides the following default configuration for the I2C slave peripheral: + * code + * slaveConfig->enableSlave = true; + * slaveConfig->address0.disable = false; + * slaveConfig->address0.address = 0u; + * slaveConfig->address1.disable = true; + * slaveConfig->address2.disable = true; + * slaveConfig->address3.disable = true; + * slaveConfig->busSpeed = kI2C_SlaveStandardMode; + * endcode + * + * After calling this function, override any settings to customize the configuration, + * prior to initializing the master driver with I2C_SlaveInit(). Be sure to override at least the a + * address0.address member of the configuration structure with the desired slave address. + * + * param[out] slaveConfig User provided configuration structure that is set to default values. Refer to + * #i2c_slave_config_t. + */ +void I2C_SlaveGetDefaultConfig(i2c_slave_config_t *slaveConfig) +{ + assert(slaveConfig != NULL); + + i2c_slave_config_t mySlaveConfig = {0}; + + /* default config enables slave address 0 match to general I2C call address zero */ + mySlaveConfig.enableSlave = true; + mySlaveConfig.address1.addressDisable = true; + mySlaveConfig.address2.addressDisable = true; + mySlaveConfig.address3.addressDisable = true; + + *slaveConfig = mySlaveConfig; +} + +/*! + * brief Initializes the I2C slave peripheral. + * + * This function enables the peripheral clock and initializes the I2C slave peripheral as described by the user + * provided configuration. + * + * param base The I2C peripheral base address. + * param slaveConfig User provided peripheral configuration. Use I2C_SlaveGetDefaultConfig() to get a set of defaults + * that you can override. + * param srcClock_Hz Frequency in Hertz of the I2C functional clock. Used to calculate CLKDIV value to provide + * enough + * data setup time for master when slave stretches the clock. + */ +status_t I2C_SlaveInit(I2C_Type *base, const i2c_slave_config_t *slaveConfig, uint32_t srcClock_Hz) +{ + status_t status; + uint32_t divVal = 0; + + /* configure data setup time used when slave stretches clock */ + status = I2C_SlaveDivVal(srcClock_Hz, slaveConfig->busSpeed, &divVal); + if (kStatus_Success != status) + { + return status; + } + + (void)FLEXCOMM_Init(base, FLEXCOMM_PERIPH_I2C); + + /* I2C Clock Divider register */ + base->CLKDIV = divVal; + + /* set Slave address */ + I2C_SlaveSetAddress(base, kI2C_SlaveAddressRegister0, slaveConfig->address0.address, + slaveConfig->address0.addressDisable); + I2C_SlaveSetAddress(base, kI2C_SlaveAddressRegister1, slaveConfig->address1.address, + slaveConfig->address1.addressDisable); + I2C_SlaveSetAddress(base, kI2C_SlaveAddressRegister2, slaveConfig->address2.address, + slaveConfig->address2.addressDisable); + I2C_SlaveSetAddress(base, kI2C_SlaveAddressRegister3, slaveConfig->address3.address, + slaveConfig->address3.addressDisable); + + /* set Slave address 0 qual */ + base->SLVQUAL0 = I2C_SLVQUAL0_QUALMODE0(slaveConfig->qualMode) | I2C_SLVQUAL0_SLVQUAL0(slaveConfig->qualAddress); + + /* set Slave enable */ + base->CFG = I2C_CFG_SLVEN(slaveConfig->enableSlave); + + return status; +} + +/*! + * brief Deinitializes the I2C slave peripheral. + * + * This function disables the I2C slave peripheral and gates the clock. It also performs a software + * reset to restore the peripheral to reset conditions. + * + * param base The I2C peripheral base address. + */ +void I2C_SlaveDeinit(I2C_Type *base) +{ + I2C_SlaveEnable(base, false); +} + +/*! + * brief Performs a polling send transfer on the I2C bus. + * + * The function executes blocking address phase and blocking data phase. + * + * param base The I2C peripheral base address. + * param txBuff The pointer to the data to be transferred. + * param txSize The length in bytes of the data to be transferred. + * return kStatus_Success Data has been sent. + * return kStatus_Fail Unexpected slave state (master data write while master read from slave is expected). + */ +status_t I2C_SlaveWriteBlocking(I2C_Type *base, const uint8_t *txBuff, size_t txSize) +{ + const uint8_t *buf = txBuff; + uint32_t stat; + bool slaveAddress; + bool slaveTransmit; + + /* Set the SLVEN bit to 1 in the CFG register. */ + I2C_SlaveEnable(base, true); + + /* wait for SLVPENDING */ + stat = I2C_SlavePollPending(base); + if (stat == (uint32_t)kStatus_I2C_Timeout) + { + return kStatus_I2C_Timeout; + } + + /* Get slave machine state */ + slaveAddress = (((stat & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == (uint32_t)I2C_STAT_SLVST_ADDR); + slaveTransmit = (((stat & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == (uint32_t)I2C_STAT_SLVST_TX); + + /* in I2C_SlaveSend() it shall be either slaveAddress or slaveTransmit */ + if (!(slaveAddress || slaveTransmit)) + { + I2C_SlaveInternalStateMachineReset(base); + return kStatus_Fail; + } + + if (slaveAddress) + { + /* Acknowledge (ack) the address by setting SLVCONTINUE = 1 in the slave control register */ + base->SLVCTL = I2C_SLVCTL_SLVCONTINUE_MASK; + + /* wait for SLVPENDING */ + stat = I2C_SlavePollPending(base); + if (stat == (uint32_t)kStatus_I2C_Timeout) + { + return kStatus_I2C_Timeout; + } + } + + /* send bytes up to txSize */ + while (txSize != 0U) + { + slaveTransmit = (((stat & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == (uint32_t)I2C_STAT_SLVST_TX); + + if (!slaveTransmit) + { + I2C_SlaveInternalStateMachineReset(base); + return kStatus_Fail; + } + + /* Write 8 bits of data to the SLVDAT register */ + base->SLVDAT = I2C_SLVDAT_DATA(*buf); + + /* continue transaction */ + base->SLVCTL = I2C_SLVCTL_SLVCONTINUE_MASK; + + /* advance counters and pointers for next data */ + buf++; + txSize--; + + if (txSize != 0U) + { + /* wait for SLVPENDING */ + stat = I2C_SlavePollPending(base); + if (stat == (uint32_t)kStatus_I2C_Timeout) + { + return kStatus_I2C_Timeout; + } + } + } + + return kStatus_Success; +} + +/*! + * brief Performs a polling receive transfer on the I2C bus. + * + * The function executes blocking address phase and blocking data phase. + * + * param base The I2C peripheral base address. + * param rxBuff The pointer to the data to be transferred. + * param rxSize The length in bytes of the data to be transferred. + * return kStatus_Success Data has been received. + * return kStatus_Fail Unexpected slave state (master data read while master write to slave is expected). + */ +status_t I2C_SlaveReadBlocking(I2C_Type *base, uint8_t *rxBuff, size_t rxSize) +{ + uint8_t *buf = rxBuff; + uint32_t stat; + bool slaveAddress; + bool slaveReceive; + + /* Set the SLVEN bit to 1 in the CFG register. */ + I2C_SlaveEnable(base, true); + + /* wait for SLVPENDING */ + stat = I2C_SlavePollPending(base); + if (stat == (uint32_t)kStatus_I2C_Timeout) + { + return kStatus_I2C_Timeout; + } + + /* Get slave machine state */ + slaveAddress = (((stat & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == (uint32_t)I2C_STAT_SLVST_ADDR); + slaveReceive = (((stat & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == (uint32_t)I2C_STAT_SLVST_RX); + + /* in I2C_SlaveReceive() it shall be either slaveAddress or slaveReceive */ + if (!(slaveAddress || slaveReceive)) + { + I2C_SlaveInternalStateMachineReset(base); + return kStatus_Fail; + } + + if (slaveAddress) + { + /* Acknowledge (ack) the address by setting SLVCONTINUE = 1 in the slave control register */ + base->SLVCTL = I2C_SLVCTL_SLVCONTINUE_MASK; + + /* wait for SLVPENDING */ + stat = I2C_SlavePollPending(base); + if (stat == (uint32_t)kStatus_I2C_Timeout) + { + return kStatus_I2C_Timeout; + } + } + + /* receive bytes up to rxSize */ + while (rxSize != 0U) + { + slaveReceive = (((stat & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == (uint32_t)I2C_STAT_SLVST_RX); + + if (!slaveReceive) + { + I2C_SlaveInternalStateMachineReset(base); + return kStatus_Fail; + } + + /* Read 8 bits of data from the SLVDAT register */ + *buf = (uint8_t)base->SLVDAT; + + /* continue transaction */ + base->SLVCTL = I2C_SLVCTL_SLVCONTINUE_MASK; + + /* advance counters and pointers for next data */ + buf++; + rxSize--; + + if (rxSize != 0U) + { + /* wait for SLVPENDING */ + stat = I2C_SlavePollPending(base); + if (stat == (uint32_t)kStatus_I2C_Timeout) + { + return kStatus_I2C_Timeout; + } + } + } + + return kStatus_Success; +} + +/*! + * brief Creates a new handle for the I2C slave non-blocking APIs. + * + * The creation of a handle is for use with the non-blocking APIs. Once a handle + * is created, there is not a corresponding destroy handle. If the user wants to + * terminate a transfer, the I2C_SlaveTransferAbort() API shall be called. + * + * param base The I2C peripheral base address. + * param[out] handle Pointer to the I2C slave driver handle. + * param callback User provided pointer to the asynchronous callback function. + * param userData User provided pointer to the application callback data. + */ +void I2C_SlaveTransferCreateHandle(I2C_Type *base, + i2c_slave_handle_t *handle, + i2c_slave_transfer_callback_t callback, + void *userData) +{ + assert(handle != NULL); + + uint32_t instance; + i2c_to_flexcomm_t handler; + handler.i2c_slave_handler = I2C_SlaveTransferHandleIRQ; + + /* Clear out the handle. */ + (void)memset(handle, 0, sizeof(*handle)); + + /* Look up instance number */ + instance = I2C_GetInstance(base); + + /* Save base and instance. */ + handle->callback = callback; + handle->userData = userData; + + /* initialize fsm */ + handle->slaveFsm = kI2C_SlaveFsmAddressMatch; + + /* store pointer to handle into transfer struct */ + handle->transfer.handle = handle; + + FLEXCOMM_SetIRQHandler(base, handler.flexcomm_handler, handle); + + /* Clear internal IRQ enables and enable NVIC IRQ. */ + I2C_DisableInterrupts(base, (uint32_t)kI2C_SlaveIrqFlags); + (void)EnableIRQ(s_i2cIRQ[instance]); +} + +/*! + * brief Starts accepting slave transfers. + * + * Call this API after calling I2C_SlaveInit() and I2C_SlaveTransferCreateHandle() to start processing + * transactions driven by an I2C master. The slave monitors the I2C bus and pass events to the + * callback that was passed into the call to I2C_SlaveTransferCreateHandle(). The callback is always invoked + * from the interrupt context. + * + * If no slave Tx transfer is busy, a master read from slave request invokes #kI2C_SlaveTransmitEvent callback. + * If no slave Rx transfer is busy, a master write to slave request invokes #kI2C_SlaveReceiveEvent callback. + * + * The set of events received by the callback is customizable. To do so, set the a eventMask parameter to + * the OR'd combination of #i2c_slave_transfer_event_t enumerators for the events you wish to receive. + * The #kI2C_SlaveTransmitEvent and #kI2C_SlaveReceiveEvent events are always enabled and do not need + * to be included in the mask. Alternatively, you can pass 0 to get a default set of only the transmit and + * receive events that are always enabled. In addition, the #kI2C_SlaveAllEvents constant is provided as + * a convenient way to enable all events. + * + * param base The I2C peripheral base address. + * param handle Pointer to i2c_slave_handle_t structure which stores the transfer state. + * param eventMask Bit mask formed by OR'ing together #i2c_slave_transfer_event_t enumerators to specify + * which events to send to the callback. Other accepted values are 0 to get a default set of + * only the transmit and receive events, and #kI2C_SlaveAllEvents to enable all events. + * + * retval kStatus_Success Slave transfers were successfully started. + * retval #kStatus_I2C_Busy Slave transfers have already been started on this handle. + */ +status_t I2C_SlaveTransferNonBlocking(I2C_Type *base, i2c_slave_handle_t *handle, uint32_t eventMask) +{ + return I2C_SlaveTransferNonBlockingInternal(base, handle, NULL, 0u, NULL, 0u, eventMask); +} + +/*! + * brief Gets the slave transfer remaining bytes during a interrupt non-blocking transfer. + * + * param base I2C base pointer. + * param handle pointer to i2c_slave_handle_t structure. + * param count Number of bytes transferred so far by the non-blocking transaction. + * retval kStatus_InvalidArgument count is Invalid. + * retval kStatus_Success Successfully return the count. + */ +status_t I2C_SlaveTransferGetCount(I2C_Type *base, i2c_slave_handle_t *handle, size_t *count) +{ + assert(handle != NULL); + + if (NULL == count) + { + return kStatus_InvalidArgument; + } + + /* Catch when there is not an active transfer. */ + if (!handle->isBusy) + { + *count = 0; + return kStatus_NoTransferInProgress; + } + + /* For an active transfer, just return the count from the handle. */ + *count = handle->transfer.transferredCount; + + return kStatus_Success; +} + +/*! + * brief Aborts the slave non-blocking transfers. + * note This API could be called at any time to stop slave for handling the bus events. + * param base The I2C peripheral base address. + * param handle Pointer to i2c_slave_handle_t structure which stores the transfer state. + * retval kStatus_Success + * retval #kStatus_I2C_Idle + */ +void I2C_SlaveTransferAbort(I2C_Type *base, i2c_slave_handle_t *handle) +{ + /* Disable I2C IRQ sources while we configure stuff. */ + I2C_DisableInterrupts(base, (uint32_t)kI2C_SlaveIrqFlags); + + /* Set the SLVEN bit to 0 in the CFG register. */ + I2C_SlaveEnable(base, false); + + handle->isBusy = false; + handle->transfer.txSize = 0U; + handle->transfer.rxSize = 0U; +} + +/*! + * brief Reusable routine to handle slave interrupts. + * note This function does not need to be called unless you are reimplementing the + * non blocking API's interrupt handler routines to add special functionality. + * param base The I2C peripheral base address. + * param handle Pointer to i2c_slave_handle_t structure which stores the transfer state. + */ +void I2C_SlaveTransferHandleIRQ(I2C_Type *base, i2c_slave_handle_t *handle) +{ + uint32_t i2cStatus = base->STAT; + uint8_t tmpdata; + size_t txSize; + size_t rxSize; + + if ((i2cStatus & I2C_STAT_SLVDESEL_MASK) != 0U) + { + I2C_SlaveInvokeEvent(base, handle, kI2C_SlaveDeselectedEvent); + I2C_SlaveClearStatusFlags(base, I2C_STAT_SLVDESEL_MASK); + } + + /* SLVPENDING flag is cleared by writing I2C_SLVCTL_SLVCONTINUE_MASK to SLVCTL register */ + if ((i2cStatus & I2C_STAT_SLVPENDING_MASK) != 0U) + { + bool slaveAddress = + (((i2cStatus & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == (uint32_t)I2C_STAT_SLVST_ADDR); + + if (slaveAddress) + { + I2C_SlaveInvokeEvent(base, handle, kI2C_SlaveAddressMatchEvent); + (void)I2C_SlaveAddressIRQ(base, handle); + } + else + { + switch (handle->slaveFsm) + { + case kI2C_SlaveFsmReceive: + { + bool slaveReceive = (((i2cStatus & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == + (uint32_t)I2C_STAT_SLVST_RX); + + if (slaveReceive) + { + rxSize = handle->transfer.rxSize; + /* if we have no receive buffer in this transfer, call callback to get new */ + if ((handle->transfer.rxData == NULL) || (rxSize == 0U)) + { + I2C_SlaveInvokeEvent(base, handle, kI2C_SlaveReceiveEvent); + } + + rxSize = handle->transfer.rxSize; + /* receive a byte */ + if ((handle->transfer.rxData != NULL) && (rxSize != 0U)) + { + /* continue transaction */ + base->SLVCTL = I2C_SLVCTL_SLVCONTINUE_MASK; + tmpdata = (uint8_t)base->SLVDAT; + *(handle->transfer.rxData) = tmpdata; + (handle->transfer.rxSize)--; + (handle->transfer.rxData)++; + (handle->transfer.transferredCount)++; + } + + rxSize = handle->transfer.rxSize; + txSize = handle->transfer.txSize; + /* is this last transaction for this transfer? allow next transaction */ + if ((0U == rxSize) && (0U == txSize)) + { + handle->isBusy = false; + I2C_SlaveInvokeEvent(base, handle, kI2C_SlaveCompletionEvent); + } + } + else + { + base->SLVCTL = I2C_SLVCTL_SLVNACK_MASK; + } + } + break; + + case kI2C_SlaveFsmTransmit: + { + bool slaveTransmit = (((i2cStatus & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == + (uint32_t)I2C_STAT_SLVST_TX); + + if (slaveTransmit) + { + txSize = handle->transfer.txSize; + /* if we have no data in this transfer, call callback to get new */ + if ((handle->transfer.txData == NULL) || (txSize == 0U)) + { + I2C_SlaveInvokeEvent(base, handle, kI2C_SlaveTransmitEvent); + } + + txSize = handle->transfer.txSize; + /* transmit a byte */ + if ((handle->transfer.txData != NULL) && (txSize != 0U)) + { + base->SLVDAT = *(handle->transfer.txData); + /* continue transaction */ + base->SLVCTL = I2C_SLVCTL_SLVCONTINUE_MASK; + (handle->transfer.txSize)--; + (handle->transfer.txData)++; + (handle->transfer.transferredCount)++; + } + + rxSize = handle->transfer.rxSize; + txSize = handle->transfer.txSize; + /* is this last transaction for this transfer? allow next transaction */ + if ((0U == rxSize) && (0U == txSize)) + { + handle->isBusy = false; + I2C_SlaveInvokeEvent(base, handle, kI2C_SlaveCompletionEvent); + } + } + else + { + base->SLVCTL = I2C_SLVCTL_SLVNACK_MASK; + } + } + break; + + default: + /* incorrect state, slv_abort()? */ + break; + } + } + } +} diff --git a/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_i2c.h b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_i2c.h new file mode 100644 index 0000000000..b521a1ad75 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_i2c.h @@ -0,0 +1,1148 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_I2C_H_ +#define _FSL_I2C_H_ + +#include +#include "fsl_device_registers.h" +#include "fsl_common.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +#define I2C_CFG_MASK 0x1f + +/*! + * @addtogroup i2c_driver + * @{ + */ + +/*! @file */ + +/*! @name Driver version */ +/*@{*/ +/*! @brief I2C driver version. */ +#define FSL_I2C_DRIVER_VERSION (MAKE_VERSION(2, 3, 0)) +/*@}*/ + +/*! @brief Retry times for waiting flag. */ +#ifndef I2C_RETRY_TIMES +#define I2C_RETRY_TIMES 0U /* Define to zero means keep waiting until the flag is assert/deassert. */ +#endif + +/*! @brief Whether to ignore the nack signal of the last byte during master transmit. */ +#ifndef I2C_MASTER_TRANSMIT_IGNORE_LAST_NACK +#define I2C_MASTER_TRANSMIT_IGNORE_LAST_NACK \ + 1U /* Define to one means master ignores the last byte's nack and considers the transfer successful. */ +#endif + +/* definitions for MSTCODE bits in I2C Status register STAT */ +#define I2C_STAT_MSTCODE_IDLE (0U) /*!< Master Idle State Code */ +#define I2C_STAT_MSTCODE_RXREADY (1U) /*!< Master Receive Ready State Code */ +#define I2C_STAT_MSTCODE_TXREADY (2U) /*!< Master Transmit Ready State Code */ +#define I2C_STAT_MSTCODE_NACKADR (3U) /*!< Master NACK by slave on address State Code */ +#define I2C_STAT_MSTCODE_NACKDAT (4U) /*!< Master NACK by slave on data State Code */ + +/* definitions for SLVSTATE bits in I2C Status register STAT */ +#define I2C_STAT_SLVST_ADDR (0) +#define I2C_STAT_SLVST_RX (1) +#define I2C_STAT_SLVST_TX (2) + +/*! @brief I2C status return codes. */ +enum +{ + kStatus_I2C_Busy = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 0), /*!< The master is already performing a transfer. */ + kStatus_I2C_Idle = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 1), /*!< The slave driver is idle. */ + kStatus_I2C_Nak = + MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 2), /*!< The slave device sent a NAK in response to a byte. */ + kStatus_I2C_InvalidParameter = + MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 3), /*!< Unable to proceed due to invalid parameter. */ + kStatus_I2C_BitError = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 4), /*!< Transferred bit was not seen on the bus. */ + kStatus_I2C_ArbitrationLost = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 5), /*!< Arbitration lost error. */ + kStatus_I2C_NoTransferInProgress = + MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 6), /*!< Attempt to abort a transfer when one is not in progress. */ + kStatus_I2C_DmaRequestFail = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 7), /*!< DMA request failed. */ + kStatus_I2C_StartStopError = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 8), /*!< Start and stop error. */ + kStatus_I2C_UnexpectedState = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 9), /*!< Unexpected state. */ + kStatus_I2C_Timeout = + MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, + 10), /*!< Timeout when waiting for I2C master/slave pending status to set to continue transfer. */ + kStatus_I2C_Addr_Nak = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 11), /*!< NAK received for Address */ + kStatus_I2C_EventTimeout = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 12), /*!< Timeout waiting for bus event. */ + kStatus_I2C_SclLowTimeout = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 13), /*!< Timeout SCL signal remains low. */ +}; + +/*! @} */ + +/*! + * @addtogroup i2c_driver + * @{ + */ + +/*! + * @brief I2C status flags. + * + * @note These enums are meant to be OR'd together to form a bit mask. + */ +enum _i2c_status_flags +{ + kI2C_MasterPendingFlag = I2C_STAT_MSTPENDING_MASK, /*!< The I2C module is waiting for software interaction. bit 0 */ + kI2C_MasterArbitrationLostFlag = + I2C_STAT_MSTARBLOSS_MASK, /*!< The arbitration of the bus was lost. There was collision on the bus. bit 4*/ + kI2C_MasterStartStopErrorFlag = + I2C_STAT_MSTSTSTPERR_MASK, /*!< There was an error during start or stop phase of the transaction. bit 6 */ + kI2C_MasterIdleFlag = 1UL << 5U, /*!< The I2C master idle status. bit 5 */ + kI2C_MasterRxReadyFlag = 1UL << I2C_STAT_MSTSTATE_SHIFT, /*!< The I2C master rx ready status. bit 1 */ + kI2C_MasterTxReadyFlag = 1UL << (I2C_STAT_MSTSTATE_SHIFT + 1U), /*!< The I2C master tx ready status. bit 2 */ + kI2C_MasterAddrNackFlag = 1UL << 7U, /*!< The I2C master address nack status. bit 7 */ + kI2C_MasterDataNackFlag = 1UL << (I2C_STAT_MSTSTATE_SHIFT + 2U), /*!< The I2C master data nack status. bit 3 */ + kI2C_SlavePendingFlag = I2C_STAT_SLVPENDING_MASK, /*!< The I2C module is waiting for software interaction. bit 8 */ + kI2C_SlaveNotStretching = I2C_STAT_SLVNOTSTR_MASK, /*!< Indicates whether the slave is currently stretching clock (0 + = yes, 1 = no). bit 11 */ + kI2C_SlaveSelected = + I2C_STAT_SLVSEL_MASK, /*!< Indicates whether the slave is selected by an address match. bit 14 */ + kI2C_SaveDeselected = I2C_STAT_SLVDESEL_MASK, /*!< Indicates that slave was previously deselected (deselect event + took place, w1c). bit 15 */ + kI2C_SlaveAddressedFlag = 1UL << 22U, /*!< One of the I2C slave's 4 addresses is matched. bit 22 */ + kI2C_SlaveReceiveFlag = 1UL << I2C_STAT_SLVSTATE_SHIFT, /*!< Slave receive data available. bit 9 */ + kI2C_SlaveTransmitFlag = 1UL << (I2C_STAT_SLVSTATE_SHIFT + 1U), /*!< Slave data can be transmitted. bit 10 */ + kI2C_SlaveAddress0MatchFlag = 1UL << 20U, /*!< Slave address0 match. bit 20 */ + kI2C_SlaveAddress1MatchFlag = 1UL << I2C_STAT_SLVIDX_SHIFT, /*!< Slave address1 match. bit 12 */ + kI2C_SlaveAddress2MatchFlag = 1UL << (I2C_STAT_SLVIDX_SHIFT + 1U), /*!< Slave address2 match. bit 13 */ + kI2C_SlaveAddress3MatchFlag = 1UL << 21U, /*!< Slave address3 match. bit 21 */ + kI2C_MonitorReadyFlag = I2C_STAT_MONRDY_MASK, /*!< The I2C monitor ready interrupt. bit 16 */ + kI2C_MonitorOverflowFlag = I2C_STAT_MONOV_MASK, /*!< The monitor data overrun interrupt. bit 17 */ + kI2C_MonitorActiveFlag = I2C_STAT_MONACTIVE_MASK, /*!< The monitor is active. bit 18 */ + kI2C_MonitorIdleFlag = I2C_STAT_MONIDLE_MASK, /*!< The monitor idle interrupt. bit 19 */ + kI2C_EventTimeoutFlag = I2C_STAT_EVENTTIMEOUT_MASK, /*!< The bus event timeout interrupt. bit 24 */ + kI2C_SclTimeoutFlag = I2C_STAT_SCLTIMEOUT_MASK, /*!< The SCL timeout interrupt. bit 25 */ + + /* All master flags that can be cleared by software */ + kI2C_MasterAllClearFlags = kI2C_MasterArbitrationLostFlag | kI2C_MasterStartStopErrorFlag, + /* All slave flags that can be cleared by software */ + kI2C_SlaveAllClearFlags = kI2C_SaveDeselected, + /* All common flags that can be cleared by software */ + kI2C_CommonAllClearFlags = + kI2C_MonitorOverflowFlag | kI2C_MonitorIdleFlag | kI2C_EventTimeoutFlag | kI2C_SclTimeoutFlag, +}; + +/*! + * @brief I2C interrupt enable. + * + * @note These enums are meant to be OR'd together to form a bit mask. + */ +enum _i2c_interrupt_enable +{ + kI2C_MasterPendingInterruptEnable = + I2C_STAT_MSTPENDING_MASK, /*!< The I2C master communication pending interrupt. */ + kI2C_MasterArbitrationLostInterruptEnable = + I2C_STAT_MSTARBLOSS_MASK, /*!< The I2C master arbitration lost interrupt. */ + kI2C_MasterStartStopErrorInterruptEnable = + I2C_STAT_MSTSTSTPERR_MASK, /*!< The I2C master start/stop timing error interrupt. */ + kI2C_SlavePendingInterruptEnable = I2C_STAT_SLVPENDING_MASK, /*!< The I2C slave communication pending interrupt. */ + kI2C_SlaveNotStretchingInterruptEnable = + I2C_STAT_SLVNOTSTR_MASK, /*!< The I2C slave not streching interrupt, deep-sleep mode can be entered only when + this interrupt occurs. */ + kI2C_SlaveDeselectedInterruptEnable = I2C_STAT_SLVDESEL_MASK, /*!< The I2C slave deselection interrupt. */ + kI2C_MonitorReadyInterruptEnable = I2C_STAT_MONRDY_MASK, /*!< The I2C monitor ready interrupt. */ + kI2C_MonitorOverflowInterruptEnable = I2C_STAT_MONOV_MASK, /*!< The monitor data overrun interrupt. */ + kI2C_MonitorIdleInterruptEnable = I2C_STAT_MONIDLE_MASK, /*!< The monitor idle interrupt. */ + kI2C_EventTimeoutInterruptEnable = I2C_STAT_EVENTTIMEOUT_MASK, /*!< The bus event timeout interrupt. */ + kI2C_SclTimeoutInterruptEnable = I2C_STAT_SCLTIMEOUT_MASK, /*!< The SCL timeout interrupt. */ + + /* All master interrupt sources */ + kI2C_MasterAllInterruptEnable = kI2C_MasterPendingInterruptEnable | kI2C_MasterArbitrationLostInterruptEnable | + kI2C_MasterStartStopErrorInterruptEnable, + /* All slave interrupt sources */ + kI2C_SlaveAllInterruptEnable = + kI2C_SlavePendingInterruptEnable | kI2C_SlaveNotStretchingInterruptEnable | kI2C_SlaveDeselectedInterruptEnable, + /* All common interrupt sources */ + kI2C_CommonAllInterruptEnable = kI2C_MonitorReadyInterruptEnable | kI2C_MonitorOverflowInterruptEnable | + kI2C_MonitorIdleInterruptEnable | kI2C_EventTimeoutInterruptEnable | + kI2C_SclTimeoutInterruptEnable, +}; +/*! @} */ + +/*! + * @addtogroup i2c_master_driver + * @{ + */ + +/*! @brief Direction of master and slave transfers. */ +typedef enum _i2c_direction +{ + kI2C_Write = 0U, /*!< Master transmit. */ + kI2C_Read = 1U /*!< Master receive. */ +} i2c_direction_t; + +/*! + * @brief Structure with settings to initialize the I2C master module. + * + * This structure holds configuration settings for the I2C peripheral. To initialize this + * structure to reasonable defaults, call the I2C_MasterGetDefaultConfig() function and + * pass a pointer to your configuration structure instance. + * + * The configuration structure can be made constant so it resides in flash. + */ +typedef struct _i2c_master_config +{ + bool enableMaster; /*!< Whether to enable master mode. */ + uint32_t baudRate_Bps; /*!< Desired baud rate in bits per second. */ + bool enableTimeout; /*!< Enable internal timeout function. */ + uint8_t timeout_Ms; /*!< Event timeout and SCL low timeout value. */ +} i2c_master_config_t; + +/* Forward declaration of the transfer descriptor and handle typedefs. */ +/*! @brief I2C master transfer typedef */ +typedef struct _i2c_master_transfer i2c_master_transfer_t; + +/*! @brief I2C master handle typedef */ +typedef struct _i2c_master_handle i2c_master_handle_t; + +/*! + * @brief Master completion callback function pointer type. + * + * This callback is used only for the non-blocking master transfer API. Specify the callback you wish to use + * in the call to I2C_MasterTransferCreateHandle(). + * + * @param base The I2C peripheral base address. + * @param completionStatus Either kStatus_Success or an error code describing how the transfer completed. + * @param userData Arbitrary pointer-sized value passed from the application. + */ +typedef void (*i2c_master_transfer_callback_t)(I2C_Type *base, + i2c_master_handle_t *handle, + status_t completionStatus, + void *userData); + +/*! + * @brief Transfer option flags. + * + * @note These enumerations are intended to be OR'd together to form a bit mask of options for + * the #_i2c_master_transfer::flags field. + */ +enum _i2c_master_transfer_flags +{ + kI2C_TransferDefaultFlag = 0x00U, /*!< Transfer starts with a start signal, stops with a stop signal. */ + kI2C_TransferNoStartFlag = 0x01U, /*!< Don't send a start condition, address, and sub address */ + kI2C_TransferRepeatedStartFlag = 0x02U, /*!< Send a repeated start condition */ + kI2C_TransferNoStopFlag = 0x04U, /*!< Don't send a stop condition. */ +}; + +/*! @brief States for the state machine used by transactional APIs. */ +enum _i2c_transfer_states +{ + kIdleState = 0, + kTransmitSubaddrState, + kTransmitDataState, + kReceiveDataBeginState, + kReceiveDataState, + kReceiveLastDataState, + kStartState, + kStopState, + kWaitForCompletionState +}; + +/*! + * @brief Non-blocking transfer descriptor structure. + * + * This structure is used to pass transaction parameters to the I2C_MasterTransferNonBlocking() API. + */ +struct _i2c_master_transfer +{ + uint32_t flags; /*!< Bit mask of options for the transfer. See enumeration #_i2c_master_transfer_flags for available + options. Set to 0 or #kI2C_TransferDefaultFlag for normal transfers. */ + uint8_t slaveAddress; /*!< The 7-bit slave address. */ + i2c_direction_t direction; /*!< Either #kI2C_Read or #kI2C_Write. */ + uint32_t subaddress; /*!< Sub address. Transferred MSB first. */ + size_t subaddressSize; /*!< Length of sub address to send in bytes. Maximum size is 4 bytes. */ + void *data; /*!< Pointer to data to transfer. */ + size_t dataSize; /*!< Number of bytes to transfer. */ +}; + +/*! + * @brief Driver handle for master non-blocking APIs. + * @note The contents of this structure are private and subject to change. + */ +struct _i2c_master_handle +{ + uint8_t state; /*!< Transfer state machine current state. */ + uint32_t transferCount; /*!< Indicates progress of the transfer */ + uint32_t remainingBytes; /*!< Remaining byte count in current state. */ + uint8_t *buf; /*!< Buffer pointer for current state. */ + uint32_t remainingSubaddr; + uint8_t subaddrBuf[4]; + bool checkAddrNack; /*!< Whether to check the nack signal is detected during addressing. */ + i2c_master_transfer_t transfer; /*!< Copy of the current transfer info. */ + i2c_master_transfer_callback_t completionCallback; /*!< Callback function pointer. */ + void *userData; /*!< Application data passed to callback. */ +}; + +/*! @} */ + +/*! + * @addtogroup i2c_slave_driver + * @{ + */ +/*! @brief I2C slave address register. */ +typedef enum _i2c_slave_address_register +{ + kI2C_SlaveAddressRegister0 = 0U, /*!< Slave Address 0 register. */ + kI2C_SlaveAddressRegister1 = 1U, /*!< Slave Address 1 register. */ + kI2C_SlaveAddressRegister2 = 2U, /*!< Slave Address 2 register. */ + kI2C_SlaveAddressRegister3 = 3U, /*!< Slave Address 3 register. */ +} i2c_slave_address_register_t; + +/*! @brief Data structure with 7-bit Slave address and Slave address disable. */ +typedef struct _i2c_slave_address +{ + uint8_t address; /*!< 7-bit Slave address SLVADR. */ + bool addressDisable; /*!< Slave address disable SADISABLE. */ +} i2c_slave_address_t; + +/*! @brief I2C slave address match options. */ +typedef enum _i2c_slave_address_qual_mode +{ + kI2C_QualModeMask = 0U, /*!< The SLVQUAL0 field (qualAddress) is used as a logical mask for matching address0. */ + kI2C_QualModeExtend = + 1U, /*!< The SLVQUAL0 (qualAddress) field is used to extend address 0 matching in a range of addresses. */ +} i2c_slave_address_qual_mode_t; + +/*! @brief I2C slave bus speed options. */ +typedef enum _i2c_slave_bus_speed +{ + kI2C_SlaveStandardMode = 0U, + kI2C_SlaveFastMode = 1U, + kI2C_SlaveFastModePlus = 2U, + kI2C_SlaveHsMode = 3U, +} i2c_slave_bus_speed_t; + +/*! + * @brief Structure with settings to initialize the I2C slave module. + * + * This structure holds configuration settings for the I2C slave peripheral. To initialize this + * structure to reasonable defaults, call the I2C_SlaveGetDefaultConfig() function and + * pass a pointer to your configuration structure instance. + * + * The configuration structure can be made constant so it resides in flash. + */ +typedef struct _i2c_slave_config +{ + i2c_slave_address_t address0; /*!< Slave's 7-bit address and disable. */ + i2c_slave_address_t address1; /*!< Alternate slave 7-bit address and disable. */ + i2c_slave_address_t address2; /*!< Alternate slave 7-bit address and disable. */ + i2c_slave_address_t address3; /*!< Alternate slave 7-bit address and disable. */ + i2c_slave_address_qual_mode_t qualMode; /*!< Qualify mode for slave address 0. */ + uint8_t qualAddress; /*!< Slave address qualifier for address 0. */ + i2c_slave_bus_speed_t + busSpeed; /*!< Slave bus speed mode. If the slave function stretches SCL to allow for software response, it must + provide sufficient data setup time to the master before releasing the stretched clock. + This is accomplished by inserting one clock time of CLKDIV at that point. + The #busSpeed value is used to configure CLKDIV + such that one clock time is greater than the tSU;DAT value noted + in the I2C bus specification for the I2C mode that is being used. + If the #busSpeed mode is unknown at compile time, use the longest data setup time + kI2C_SlaveStandardMode (250 ns) */ + bool enableSlave; /*!< Enable slave mode. */ +} i2c_slave_config_t; + +/*! + * @brief Set of events sent to the callback for non blocking slave transfers. + * + * These event enumerations are used for two related purposes. First, a bit mask created by OR'ing together + * events is passed to I2C_SlaveTransferNonBlocking() in order to specify which events to enable. + * Then, when the slave callback is invoked, it is passed the current event through its @a transfer + * parameter. + * + * @note These enumerations are meant to be OR'd together to form a bit mask of events. + */ +typedef enum _i2c_slave_transfer_event +{ + kI2C_SlaveAddressMatchEvent = 0x01U, /*!< Received the slave address after a start or repeated start. */ + kI2C_SlaveTransmitEvent = 0x02U, /*!< Callback is requested to provide data to transmit + (slave-transmitter role). */ + kI2C_SlaveReceiveEvent = 0x04U, /*!< Callback is requested to provide a buffer in which to place received + data (slave-receiver role). */ + kI2C_SlaveCompletionEvent = 0x20U, /*!< All data in the active transfer have been consumed. */ + kI2C_SlaveDeselectedEvent = + 0x40U, /*!< The slave function has become deselected (SLVSEL flag changing from 1 to 0. */ + + /*! Bit mask of all available events. */ + kI2C_SlaveAllEvents = kI2C_SlaveAddressMatchEvent | kI2C_SlaveTransmitEvent | kI2C_SlaveReceiveEvent | + kI2C_SlaveCompletionEvent | kI2C_SlaveDeselectedEvent, +} i2c_slave_transfer_event_t; + +/*! @brief I2C slave handle typedef. */ +typedef struct _i2c_slave_handle i2c_slave_handle_t; + +/*! @brief I2C slave transfer structure */ +typedef struct _i2c_slave_transfer +{ + i2c_slave_handle_t *handle; /*!< Pointer to handle that contains this transfer. */ + i2c_slave_transfer_event_t event; /*!< Reason the callback is being invoked. */ + uint8_t receivedAddress; /*!< Matching address send by master. 7-bits plus R/nW bit0 */ + uint32_t eventMask; /*!< Mask of enabled events. */ + uint8_t *rxData; /*!< Transfer buffer for receive data */ + const uint8_t *txData; /*!< Transfer buffer for transmit data */ + size_t txSize; /*!< Transfer size */ + size_t rxSize; /*!< Transfer size */ + size_t transferredCount; /*!< Number of bytes transferred during this transfer. */ + status_t completionStatus; /*!< Success or error code describing how the transfer completed. Only applies for + #kI2C_SlaveCompletionEvent. */ +} i2c_slave_transfer_t; + +/*! + * @brief Slave event callback function pointer type. + * + * This callback is used only for the slave non-blocking transfer API. To install a callback, + * use the I2C_SlaveSetCallback() function after you have created a handle. + * + * @param base Base address for the I2C instance on which the event occurred. + * @param transfer Pointer to transfer descriptor containing values passed to and/or from the callback. + * @param userData Arbitrary pointer-sized value passed from the application. + */ +typedef void (*i2c_slave_transfer_callback_t)(I2C_Type *base, volatile i2c_slave_transfer_t *transfer, void *userData); + +/*! + * @brief I2C slave software finite state machine states. + */ +typedef enum _i2c_slave_fsm +{ + kI2C_SlaveFsmAddressMatch = 0u, + kI2C_SlaveFsmReceive = 2u, + kI2C_SlaveFsmTransmit = 3u, +} i2c_slave_fsm_t; + +/*! + * @brief I2C slave handle structure. + * @note The contents of this structure are private and subject to change. + */ +struct _i2c_slave_handle +{ + volatile i2c_slave_transfer_t transfer; /*!< I2C slave transfer. */ + volatile bool isBusy; /*!< Whether transfer is busy. */ + volatile i2c_slave_fsm_t slaveFsm; /*!< slave transfer state machine. */ + i2c_slave_transfer_callback_t callback; /*!< Callback function called at transfer event. */ + void *userData; /*!< Callback parameter passed to callback. */ +}; + +/*! @brief Typedef for master interrupt handler. */ +typedef void (*flexcomm_i2c_master_irq_handler_t)(I2C_Type *base, i2c_master_handle_t *handle); + +/*! @brief Typedef for slave interrupt handler. */ +typedef void (*flexcomm_i2c_slave_irq_handler_t)(I2C_Type *base, i2c_slave_handle_t *handle); +/*! @} */ + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @addtogroup i2c_master_driver + * @{ + */ + +/*! @name Initialization and deinitialization */ +/*@{*/ + +/*! + * @brief Provides a default configuration for the I2C master peripheral. + * + * This function provides the following default configuration for the I2C master peripheral: + * @code + * masterConfig->enableMaster = true; + * masterConfig->baudRate_Bps = 100000U; + * masterConfig->enableTimeout = false; + * @endcode + * + * After calling this function, you can override any settings in order to customize the configuration, + * prior to initializing the master driver with I2C_MasterInit(). + * + * @param[out] masterConfig User provided configuration structure for default values. Refer to #i2c_master_config_t. + */ +void I2C_MasterGetDefaultConfig(i2c_master_config_t *masterConfig); + +/*! + * @brief Initializes the I2C master peripheral. + * + * This function enables the peripheral clock and initializes the I2C master peripheral as described by the user + * provided configuration. A software reset is performed prior to configuration. + * + * @param base The I2C peripheral base address. + * @param masterConfig User provided peripheral configuration. Use I2C_MasterGetDefaultConfig() to get a set of + * defaults + * that you can override. + * @param srcClock_Hz Frequency in Hertz of the I2C functional clock. Used to calculate the baud rate divisors, + * filter widths, and timeout periods. + */ +void I2C_MasterInit(I2C_Type *base, const i2c_master_config_t *masterConfig, uint32_t srcClock_Hz); + +/*! + * @brief Deinitializes the I2C master peripheral. + * + * This function disables the I2C master peripheral and gates the clock. It also performs a software + * reset to restore the peripheral to reset conditions. + * + * @param base The I2C peripheral base address. + */ +void I2C_MasterDeinit(I2C_Type *base); + +/*! + * @brief Returns an instance number given a base address. + * + * If an invalid base address is passed, debug builds will assert. Release builds will just return + * instance number 0. + * + * @param base The I2C peripheral base address. + * @return I2C instance number starting from 0. + */ +uint32_t I2C_GetInstance(I2C_Type *base); + +/*! + * @brief Performs a software reset. + * + * Restores the I2C master peripheral to reset conditions. + * + * @param base The I2C peripheral base address. + */ +static inline void I2C_MasterReset(I2C_Type *base) +{ +} + +/*! + * @brief Enables or disables the I2C module as master. + * + * @param base The I2C peripheral base address. + * @param enable Pass true to enable or false to disable the specified I2C as master. + */ +static inline void I2C_MasterEnable(I2C_Type *base, bool enable) +{ + if (enable) + { + base->CFG = (base->CFG & (uint32_t)I2C_CFG_MASK) | I2C_CFG_MSTEN_MASK; + } + else + { + base->CFG = (base->CFG & (uint32_t)I2C_CFG_MASK) & ~I2C_CFG_MSTEN_MASK; + } +} + +/*@}*/ + +/*! @name Status */ +/*@{*/ +/*! + * @brief Gets the I2C status flags. + * + * A bit mask with the state of all I2C status flags is returned. For each flag, the corresponding bit + * in the return value is set if the flag is asserted. + * + * @param base The I2C peripheral base address. + * @return State of the status flags: + * - 1: related status flag is set. + * - 0: related status flag is not set. + * @see @ref _i2c_status_flags. + */ +uint32_t I2C_GetStatusFlags(I2C_Type *base); + +/*! + * @brief Clears the I2C status flag state. + * + * Refer to kI2C_CommonAllClearStatusFlags, kI2C_MasterAllClearStatusFlags and kI2C_SlaveAllClearStatusFlags to see + * the clearable flags. Attempts to clear other flags has no effect. + * + * @param base The I2C peripheral base address. + * @param statusMask A bitmask of status flags that are to be cleared. The mask is composed of the members in + * kI2C_CommonAllClearStatusFlags, kI2C_MasterAllClearStatusFlags and kI2C_SlaveAllClearStatusFlags. You may pass + * the result of a previous call to I2C_GetStatusFlags(). + * @see #_i2c_status_flags, _i2c_master_status_flags and _i2c_slave_status_flags. + */ +static inline void I2C_ClearStatusFlags(I2C_Type *base, uint32_t statusMask) +{ + /* Only deal with the clearable flags */ + statusMask &= + ((uint32_t)kI2C_CommonAllClearFlags | (uint32_t)kI2C_MasterAllClearFlags | (uint32_t)kI2C_SlaveAllClearFlags); + base->STAT = statusMask; +} + +/*! + * @brief Clears the I2C master status flag state. + * @deprecated Do not use this function. It has been superceded by @ref I2C_ClearStatusFlags + * The following status register flags can be cleared: + * - #kI2C_MasterArbitrationLostFlag + * - #kI2C_MasterStartStopErrorFlag + * + * Attempts to clear other flags has no effect. + * + * @param base The I2C peripheral base address. + * @param statusMask A bitmask of status flags that are to be cleared. The mask is composed of + * #_i2c_status_flags enumerators OR'd together. You may pass the result of a previous call to + * I2C_GetStatusFlags(). + * @see _i2c_status_flags. + */ +static inline void I2C_MasterClearStatusFlags(I2C_Type *base, uint32_t statusMask) +{ + /* Allow clearing just master status flags */ + base->STAT = statusMask & (I2C_STAT_MSTARBLOSS_MASK | I2C_STAT_MSTSTSTPERR_MASK); +} + +/*@}*/ + +/*! @name Interrupts */ +/*@{*/ + +/*! + * @brief Enables the I2C interrupt requests. + * + * @param base The I2C peripheral base address. + * @param interruptMask Bit mask of interrupts to enable. See #_i2c_interrupt_enable for the set + * of constants that should be OR'd together to form the bit mask. + */ +static inline void I2C_EnableInterrupts(I2C_Type *base, uint32_t interruptMask) +{ + base->INTENSET = interruptMask; +} + +/*! + * @brief Disables the I2C interrupt requests. + * + * @param base The I2C peripheral base address. + * @param interruptMask Bit mask of interrupts to disable. See #_i2c_interrupt_enable for the set + * of constants that should be OR'd together to form the bit mask. + */ +static inline void I2C_DisableInterrupts(I2C_Type *base, uint32_t interruptMask) +{ + base->INTENCLR = interruptMask; +} + +/*! + * @brief Returns the set of currently enabled I2C interrupt requests. + * + * @param base The I2C peripheral base address. + * @return A bitmask composed of #_i2c_interrupt_enable enumerators OR'd together to indicate the + * set of enabled interrupts. + */ +static inline uint32_t I2C_GetEnabledInterrupts(I2C_Type *base) +{ + return base->INTSTAT; +} + +/*@}*/ + +/*! @name Bus operations */ +/*@{*/ + +/*! + * @brief Sets the I2C bus frequency for master transactions. + * + * The I2C master is automatically disabled and re-enabled as necessary to configure the baud + * rate. Do not call this function during a transfer, or the transfer is aborted. + * + * @param base The I2C peripheral base address. + * @param srcClock_Hz I2C functional clock frequency in Hertz. + * @param baudRate_Bps Requested bus frequency in bits per second. + */ +void I2C_MasterSetBaudRate(I2C_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz); + +/*! + * @brief Sets the I2C bus timeout value. + * + * If the SCL signal remains low or bus does not have event longer than the timeout value, kI2C_SclTimeoutFlag or + * kI2C_EventTimeoutFlag is set. This can indicete the bus is held by slave or any fault occurs to the I2C module. + * + * @param base The I2C peripheral base address. + * @param timeout_Ms Timeout value in millisecond. + * @param srcClock_Hz I2C functional clock frequency in Hertz. + */ +void I2C_MasterSetTimeoutValue(I2C_Type *base, uint8_t timeout_Ms, uint32_t srcClock_Hz); + +/*! + * @brief Returns whether the bus is idle. + * + * Requires the master mode to be enabled. + * + * @param base The I2C peripheral base address. + * @retval true Bus is busy. + * @retval false Bus is idle. + */ +static inline bool I2C_MasterGetBusIdleState(I2C_Type *base) +{ + /* True if MSTPENDING flag is set and MSTSTATE is zero == idle */ + return ((base->STAT & (I2C_STAT_MSTPENDING_MASK | I2C_STAT_MSTSTATE_MASK)) == I2C_STAT_MSTPENDING_MASK); +} + +/*! + * @brief Sends a START on the I2C bus. + * + * This function is used to initiate a new master mode transfer by sending the START signal. + * The slave address is sent following the I2C START signal. + * + * @param base I2C peripheral base pointer + * @param address 7-bit slave device address. + * @param direction Master transfer directions(transmit/receive). + * @retval kStatus_Success Successfully send the start signal. + * @retval kStatus_I2C_Busy Current bus is busy. + */ +status_t I2C_MasterStart(I2C_Type *base, uint8_t address, i2c_direction_t direction); + +/*! + * @brief Sends a STOP signal on the I2C bus. + * + * @retval kStatus_Success Successfully send the stop signal. + * @retval kStatus_I2C_Timeout Send stop signal failed, timeout. + */ +status_t I2C_MasterStop(I2C_Type *base); + +/*! + * @brief Sends a REPEATED START on the I2C bus. + * + * @param base I2C peripheral base pointer + * @param address 7-bit slave device address. + * @param direction Master transfer directions(transmit/receive). + * @retval kStatus_Success Successfully send the start signal. + * @retval kStatus_I2C_Busy Current bus is busy but not occupied by current I2C master. + */ +static inline status_t I2C_MasterRepeatedStart(I2C_Type *base, uint8_t address, i2c_direction_t direction) +{ + return I2C_MasterStart(base, address, direction); +} + +/*! + * @brief Performs a polling send transfer on the I2C bus. + * + * Sends up to @a txSize number of bytes to the previously addressed slave device. The slave may + * reply with a NAK to any byte in order to terminate the transfer early. If this happens, this + * function returns #kStatus_I2C_Nak. + * + * @param base The I2C peripheral base address. + * @param txBuff The pointer to the data to be transferred. + * @param txSize The length in bytes of the data to be transferred. + * @param flags Transfer control flag to control special behavior like suppressing start or stop, for normal transfers + * use kI2C_TransferDefaultFlag + * @retval kStatus_Success Data was sent successfully. + * @retval #kStatus_I2C_Busy Another master is currently utilizing the bus. + * @retval #kStatus_I2C_Nak The slave device sent a NAK in response to a byte. + * @retval #kStatus_I2C_ArbitrationLost Arbitration lost error. + */ +status_t I2C_MasterWriteBlocking(I2C_Type *base, const void *txBuff, size_t txSize, uint32_t flags); + +/*! + * @brief Performs a polling receive transfer on the I2C bus. + * + * @param base The I2C peripheral base address. + * @param rxBuff The pointer to the data to be transferred. + * @param rxSize The length in bytes of the data to be transferred. + * @param flags Transfer control flag to control special behavior like suppressing start or stop, for normal transfers + * use kI2C_TransferDefaultFlag + * @retval kStatus_Success Data was received successfully. + * @retval #kStatus_I2C_Busy Another master is currently utilizing the bus. + * @retval #kStatus_I2C_Nak The slave device sent a NAK in response to a byte. + * @retval #kStatus_I2C_ArbitrationLost Arbitration lost error. + */ +status_t I2C_MasterReadBlocking(I2C_Type *base, void *rxBuff, size_t rxSize, uint32_t flags); + +/*! + * @brief Performs a master polling transfer on the I2C bus. + * + * @note The API does not return until the transfer succeeds or fails due + * to arbitration lost or receiving a NAK. + * + * @param base I2C peripheral base address. + * @param xfer Pointer to the transfer structure. + * @retval kStatus_Success Successfully complete the data transmission. + * @retval kStatus_I2C_Busy Previous transmission still not finished. + * @retval kStatus_I2C_Timeout Transfer error, wait signal timeout. + * @retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost. + * @retval kStataus_I2C_Nak Transfer error, receive NAK during transfer. + * @retval kStataus_I2C_Addr_Nak Transfer error, receive NAK during addressing. + */ +status_t I2C_MasterTransferBlocking(I2C_Type *base, i2c_master_transfer_t *xfer); + +/*@}*/ + +/*! @name Non-blocking */ +/*@{*/ + +/*! + * @brief Creates a new handle for the I2C master non-blocking APIs. + * + * The creation of a handle is for use with the non-blocking APIs. Once a handle + * is created, there is not a corresponding destroy handle. If the user wants to + * terminate a transfer, the I2C_MasterTransferAbort() API shall be called. + * + * @param base The I2C peripheral base address. + * @param[out] handle Pointer to the I2C master driver handle. + * @param callback User provided pointer to the asynchronous callback function. + * @param userData User provided pointer to the application callback data. + */ +void I2C_MasterTransferCreateHandle(I2C_Type *base, + i2c_master_handle_t *handle, + i2c_master_transfer_callback_t callback, + void *userData); + +/*! + * @brief Performs a non-blocking transaction on the I2C bus. + * + * @param base The I2C peripheral base address. + * @param handle Pointer to the I2C master driver handle. + * @param xfer The pointer to the transfer descriptor. + * @retval kStatus_Success The transaction was started successfully. + * @retval #kStatus_I2C_Busy Either another master is currently utilizing the bus, or a non-blocking + * transaction is already in progress. + */ +status_t I2C_MasterTransferNonBlocking(I2C_Type *base, i2c_master_handle_t *handle, i2c_master_transfer_t *xfer); + +/*! + * @brief Returns number of bytes transferred so far. + * @param base The I2C peripheral base address. + * @param handle Pointer to the I2C master driver handle. + * @param[out] count Number of bytes transferred so far by the non-blocking transaction. + * @retval kStatus_Success + * @retval #kStatus_I2C_Busy + */ +status_t I2C_MasterTransferGetCount(I2C_Type *base, i2c_master_handle_t *handle, size_t *count); + +/*! + * @brief Terminates a non-blocking I2C master transmission early. + * + * @note It is not safe to call this function from an IRQ handler that has a higher priority than the + * I2C peripheral's IRQ priority. + * + * @param base The I2C peripheral base address. + * @param handle Pointer to the I2C master driver handle. + * @retval kStatus_Success A transaction was successfully aborted. + * @retval #kStatus_I2C_Timeout Timeout during polling for flags. + */ +status_t I2C_MasterTransferAbort(I2C_Type *base, i2c_master_handle_t *handle); + +/*@}*/ + +/*! @name IRQ handler */ +/*@{*/ + +/*! + * @brief Reusable routine to handle master interrupts. + * @note This function does not need to be called unless you are reimplementing the + * nonblocking API's interrupt handler routines to add special functionality. + * @param base The I2C peripheral base address. + * @param handle Pointer to the I2C master driver handle. + */ +void I2C_MasterTransferHandleIRQ(I2C_Type *base, i2c_master_handle_t *handle); + +/*@}*/ + +/*! @} */ /* end of i2c_master_driver */ + +/*! + * @addtogroup i2c_slave_driver + * @{ + */ + +/*! @name Slave initialization and deinitialization */ +/*@{*/ + +/*! + * @brief Provides a default configuration for the I2C slave peripheral. + * + * This function provides the following default configuration for the I2C slave peripheral: + * @code + * slaveConfig->enableSlave = true; + * slaveConfig->address0.disable = false; + * slaveConfig->address0.address = 0u; + * slaveConfig->address1.disable = true; + * slaveConfig->address2.disable = true; + * slaveConfig->address3.disable = true; + * slaveConfig->busSpeed = kI2C_SlaveStandardMode; + * @endcode + * + * After calling this function, override any settings to customize the configuration, + * prior to initializing the master driver with I2C_SlaveInit(). Be sure to override at least the @a + * address0.address member of the configuration structure with the desired slave address. + * + * @param[out] slaveConfig User provided configuration structure that is set to default values. Refer to + * #i2c_slave_config_t. + */ +void I2C_SlaveGetDefaultConfig(i2c_slave_config_t *slaveConfig); + +/*! + * @brief Initializes the I2C slave peripheral. + * + * This function enables the peripheral clock and initializes the I2C slave peripheral as described by the user + * provided configuration. + * + * @param base The I2C peripheral base address. + * @param slaveConfig User provided peripheral configuration. Use I2C_SlaveGetDefaultConfig() to get a set of defaults + * that you can override. + * @param srcClock_Hz Frequency in Hertz of the I2C functional clock. Used to calculate CLKDIV value to provide + * enough + * data setup time for master when slave stretches the clock. + */ +status_t I2C_SlaveInit(I2C_Type *base, const i2c_slave_config_t *slaveConfig, uint32_t srcClock_Hz); + +/*! + * @brief Configures Slave Address n register. + * + * This function writes new value to Slave Address register. + * + * @param base The I2C peripheral base address. + * @param addressRegister The module supports multiple address registers. The parameter determines which one shall be + * changed. + * @param address The slave address to be stored to the address register for matching. + * @param addressDisable Disable matching of the specified address register. + */ +void I2C_SlaveSetAddress(I2C_Type *base, + i2c_slave_address_register_t addressRegister, + uint8_t address, + bool addressDisable); + +/*! + * @brief Deinitializes the I2C slave peripheral. + * + * This function disables the I2C slave peripheral and gates the clock. It also performs a software + * reset to restore the peripheral to reset conditions. + * + * @param base The I2C peripheral base address. + */ +void I2C_SlaveDeinit(I2C_Type *base); + +/*! + * @brief Enables or disables the I2C module as slave. + * + * @param base The I2C peripheral base address. + * @param enable True to enable or flase to disable. + */ +static inline void I2C_SlaveEnable(I2C_Type *base, bool enable) +{ + /* Set or clear the SLVEN bit in the CFG register. */ + base->CFG = I2C_CFG_SLVEN(enable); +} + +/*@}*/ /* end of Slave initialization and deinitialization */ + +/*! @name Slave status */ +/*@{*/ + +/*! + * @brief Clears the I2C status flag state. + * + * The following status register flags can be cleared: + * - slave deselected flag + * + * Attempts to clear other flags has no effect. + * + * @param base The I2C peripheral base address. + * @param statusMask A bitmask of status flags that are to be cleared. The mask is composed of + * _i2c_slave_flags enumerators OR'd together. You may pass the result of a previous call to + * I2C_SlaveGetStatusFlags(). + * @see _i2c_slave_flags. + */ +static inline void I2C_SlaveClearStatusFlags(I2C_Type *base, uint32_t statusMask) +{ + /* Allow clearing just slave status flags */ + base->STAT = statusMask & I2C_STAT_SLVDESEL_MASK; +} + +/*@}*/ /* end of Slave status */ + +/*! @name Slave bus operations */ +/*@{*/ + +/*! + * @brief Performs a polling send transfer on the I2C bus. + * + * The function executes blocking address phase and blocking data phase. + * + * @param base The I2C peripheral base address. + * @param txBuff The pointer to the data to be transferred. + * @param txSize The length in bytes of the data to be transferred. + * @return kStatus_Success Data has been sent. + * @return kStatus_Fail Unexpected slave state (master data write while master read from slave is expected). + */ +status_t I2C_SlaveWriteBlocking(I2C_Type *base, const uint8_t *txBuff, size_t txSize); + +/*! + * @brief Performs a polling receive transfer on the I2C bus. + * + * The function executes blocking address phase and blocking data phase. + * + * @param base The I2C peripheral base address. + * @param rxBuff The pointer to the data to be transferred. + * @param rxSize The length in bytes of the data to be transferred. + * @return kStatus_Success Data has been received. + * @return kStatus_Fail Unexpected slave state (master data read while master write to slave is expected). + */ +status_t I2C_SlaveReadBlocking(I2C_Type *base, uint8_t *rxBuff, size_t rxSize); + +/*@}*/ /* end of Slave bus operations */ + +/*! @name Slave non-blocking */ +/*@{*/ + +/*! + * @brief Creates a new handle for the I2C slave non-blocking APIs. + * + * The creation of a handle is for use with the non-blocking APIs. Once a handle + * is created, there is not a corresponding destroy handle. If the user wants to + * terminate a transfer, the I2C_SlaveTransferAbort() API shall be called. + * + * @param base The I2C peripheral base address. + * @param[out] handle Pointer to the I2C slave driver handle. + * @param callback User provided pointer to the asynchronous callback function. + * @param userData User provided pointer to the application callback data. + */ +void I2C_SlaveTransferCreateHandle(I2C_Type *base, + i2c_slave_handle_t *handle, + i2c_slave_transfer_callback_t callback, + void *userData); + +/*! + * @brief Starts accepting slave transfers. + * + * Call this API after calling I2C_SlaveInit() and I2C_SlaveTransferCreateHandle() to start processing + * transactions driven by an I2C master. The slave monitors the I2C bus and pass events to the + * callback that was passed into the call to I2C_SlaveTransferCreateHandle(). The callback is always invoked + * from the interrupt context. + * + * If no slave Tx transfer is busy, a master read from slave request invokes #kI2C_SlaveTransmitEvent callback. + * If no slave Rx transfer is busy, a master write to slave request invokes #kI2C_SlaveReceiveEvent callback. + * + * The set of events received by the callback is customizable. To do so, set the @a eventMask parameter to + * the OR'd combination of #i2c_slave_transfer_event_t enumerators for the events you wish to receive. + * The #kI2C_SlaveTransmitEvent and #kI2C_SlaveReceiveEvent events are always enabled and do not need + * to be included in the mask. Alternatively, you can pass 0 to get a default set of only the transmit and + * receive events that are always enabled. In addition, the #kI2C_SlaveAllEvents constant is provided as + * a convenient way to enable all events. + * + * @param base The I2C peripheral base address. + * @param handle Pointer to i2c_slave_handle_t structure which stores the transfer state. + * @param eventMask Bit mask formed by OR'ing together #i2c_slave_transfer_event_t enumerators to specify + * which events to send to the callback. Other accepted values are 0 to get a default set of + * only the transmit and receive events, and #kI2C_SlaveAllEvents to enable all events. + * + * @retval kStatus_Success Slave transfers were successfully started. + * @retval #kStatus_I2C_Busy Slave transfers have already been started on this handle. + */ +status_t I2C_SlaveTransferNonBlocking(I2C_Type *base, i2c_slave_handle_t *handle, uint32_t eventMask); + +/*! + * @brief Starts accepting master read from slave requests. + * + * The function can be called in response to #kI2C_SlaveTransmitEvent callback to start a new slave Tx transfer + * from within the transfer callback. + * + * The set of events received by the callback is customizable. To do so, set the @a eventMask parameter to + * the OR'd combination of #i2c_slave_transfer_event_t enumerators for the events you wish to receive. + * The #kI2C_SlaveTransmitEvent and #kI2C_SlaveReceiveEvent events are always enabled and do not need + * to be included in the mask. Alternatively, you can pass 0 to get a default set of only the transmit and + * receive events that are always enabled. In addition, the #kI2C_SlaveAllEvents constant is provided as + * a convenient way to enable all events. + * + * @param base The I2C peripheral base address. + * @param transfer Pointer to #i2c_slave_transfer_t structure. + * @param txData Pointer to data to send to master. + * @param txSize Size of txData in bytes. + * @param eventMask Bit mask formed by OR'ing together #i2c_slave_transfer_event_t enumerators to specify + * which events to send to the callback. Other accepted values are 0 to get a default set of + * only the transmit and receive events, and #kI2C_SlaveAllEvents to enable all events. + * + * @retval kStatus_Success Slave transfers were successfully started. + * @retval #kStatus_I2C_Busy Slave transfers have already been started on this handle. + */ +status_t I2C_SlaveSetSendBuffer( + I2C_Type *base, volatile i2c_slave_transfer_t *transfer, const void *txData, size_t txSize, uint32_t eventMask); + +/*! + * @brief Starts accepting master write to slave requests. + * + * The function can be called in response to #kI2C_SlaveReceiveEvent callback to start a new slave Rx transfer + * from within the transfer callback. + * + * The set of events received by the callback is customizable. To do so, set the @a eventMask parameter to + * the OR'd combination of #i2c_slave_transfer_event_t enumerators for the events you wish to receive. + * The #kI2C_SlaveTransmitEvent and #kI2C_SlaveReceiveEvent events are always enabled and do not need + * to be included in the mask. Alternatively, you can pass 0 to get a default set of only the transmit and + * receive events that are always enabled. In addition, the #kI2C_SlaveAllEvents constant is provided as + * a convenient way to enable all events. + * + * @param base The I2C peripheral base address. + * @param transfer Pointer to #i2c_slave_transfer_t structure. + * @param rxData Pointer to data to store data from master. + * @param rxSize Size of rxData in bytes. + * @param eventMask Bit mask formed by OR'ing together #i2c_slave_transfer_event_t enumerators to specify + * which events to send to the callback. Other accepted values are 0 to get a default set of + * only the transmit and receive events, and #kI2C_SlaveAllEvents to enable all events. + * + * @retval kStatus_Success Slave transfers were successfully started. + * @retval #kStatus_I2C_Busy Slave transfers have already been started on this handle. + */ +status_t I2C_SlaveSetReceiveBuffer( + I2C_Type *base, volatile i2c_slave_transfer_t *transfer, void *rxData, size_t rxSize, uint32_t eventMask); + +/*! + * @brief Returns the slave address sent by the I2C master. + * + * This function should only be called from the address match event callback #kI2C_SlaveAddressMatchEvent. + * + * @param base The I2C peripheral base address. + * @param transfer The I2C slave transfer. + * @return The 8-bit address matched by the I2C slave. Bit 0 contains the R/w direction bit, and + * the 7-bit slave address is in the upper 7 bits. + */ +static inline uint32_t I2C_SlaveGetReceivedAddress(I2C_Type *base, volatile i2c_slave_transfer_t *transfer) +{ + return transfer->receivedAddress; +} + +/*! + * @brief Aborts the slave non-blocking transfers. + * @note This API could be called at any time to stop slave for handling the bus events. + * @param base The I2C peripheral base address. + * @param handle Pointer to i2c_slave_handle_t structure which stores the transfer state. + * @retval kStatus_Success + * @retval #kStatus_I2C_Idle + */ +void I2C_SlaveTransferAbort(I2C_Type *base, i2c_slave_handle_t *handle); + +/*! + * @brief Gets the slave transfer remaining bytes during a interrupt non-blocking transfer. + * + * @param base I2C base pointer. + * @param handle pointer to i2c_slave_handle_t structure. + * @param count Number of bytes transferred so far by the non-blocking transaction. + * @retval kStatus_InvalidArgument count is Invalid. + * @retval kStatus_Success Successfully return the count. + */ +status_t I2C_SlaveTransferGetCount(I2C_Type *base, i2c_slave_handle_t *handle, size_t *count); + +/*@}*/ /* end of Slave non-blocking */ + +/*! @name Slave IRQ handler */ +/*@{*/ + +/*! + * @brief Reusable routine to handle slave interrupts. + * @note This function does not need to be called unless you are reimplementing the + * non blocking API's interrupt handler routines to add special functionality. + * @param base The I2C peripheral base address. + * @param handle Pointer to i2c_slave_handle_t structure which stores the transfer state. + */ +void I2C_SlaveTransferHandleIRQ(I2C_Type *base, i2c_slave_handle_t *handle); + +/*@}*/ /* end of Slave IRQ handler */ + +/*! @} */ /* end of i2c_slave_driver */ + +#if defined(__cplusplus) +} +#endif + +#endif /* _FSL_I2C_H_ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_i2c_dma.c b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_i2c_dma.c new file mode 100644 index 0000000000..45d47e5907 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_i2c_dma.c @@ -0,0 +1,652 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_i2c_dma.h" +#include "fsl_flexcomm.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.flexcomm_i2c_dma" +#endif + +/*transfer = *xfer; + transfer = &(handle->transfer); + + handle->transferCount = 0U; + handle->remainingBytesDMA = 0U; + handle->buf = (uint8_t *)transfer->data; + handle->remainingSubaddr = 0U; + + if ((transfer->flags & (uint32_t)kI2C_TransferNoStartFlag) != 0U) + { + handle->checkAddrNack = false; + /* Start condition shall not be ommited, switch directly to next phase */ + if (transfer->dataSize == 0U) + { + handle->state = (uint8_t)kStopState; + } + else if (handle->transfer.direction == kI2C_Write) + { + handle->state = (uint8_t)kTransmitDataState; + } + else if (handle->transfer.direction == kI2C_Read) + { + handle->state = (xfer->dataSize == 1U) ? (uint8_t)kReceiveLastDataState : (uint8_t)kReceiveDataState; + } + else + { + return kStatus_I2C_InvalidParameter; + } + } + else + { + if (transfer->subaddressSize != 0U) + { + int i; + uint32_t subaddress; + + if (transfer->subaddressSize > sizeof(handle->subaddrBuf)) + { + return kStatus_I2C_InvalidParameter; + } + + /* Prepare subaddress transmit buffer, most significant byte is stored at the lowest address */ + subaddress = xfer->subaddress; + for (i = (int)xfer->subaddressSize - 1; i >= 0; i--) + { + handle->subaddrBuf[i] = (uint8_t)subaddress & 0xffU; + subaddress >>= 8; + } + handle->remainingSubaddr = transfer->subaddressSize; + } + + handle->state = (uint8_t)kStartState; + handle->checkAddrNack = true; + } + + return kStatus_Success; +} + +static void I2C_RunDMATransfer(I2C_Type *base, i2c_master_dma_handle_t *handle) +{ + uint32_t transfer_size; + dma_transfer_config_t xferConfig; + uint32_t address; + address = (uint32_t)&base->MSTDAT; + + /* Update transfer count */ + int32_t count = handle->buf - (uint8_t *)handle->transfer.data; + assert(count >= 0); + handle->transferCount = (uint32_t)count; + + /* Check if there is anything to be transferred at all */ + if (handle->remainingBytesDMA == 0U) + { + /* No data to be transferrred, disable DMA */ + base->MSTCTL = 0; + return; + } + + /* Calculate transfer size */ + transfer_size = handle->remainingBytesDMA; + if (transfer_size > (uint32_t)I2C_MAX_DMA_TRANSFER_COUNT) + { + transfer_size = (uint32_t)I2C_MAX_DMA_TRANSFER_COUNT; + } + + switch (handle->transfer.direction) + { + case kI2C_Write: + DMA_PrepareTransfer(&xferConfig, handle->buf, (uint32_t *)address, sizeof(uint8_t), transfer_size, + kDMA_MemoryToPeripheral, NULL); + break; + + case kI2C_Read: + DMA_PrepareTransfer(&xferConfig, (uint32_t *)address, handle->buf, sizeof(uint8_t), transfer_size, + kDMA_PeripheralToMemory, NULL); + break; + + default: + /* This should never happen */ + assert(0); + break; + } + + (void)DMA_SubmitTransfer(handle->dmaHandle, &xferConfig); + DMA_StartTransfer(handle->dmaHandle); + + handle->remainingBytesDMA -= transfer_size; + handle->buf += transfer_size; + handle->checkAddrNack = false; +} + +static status_t I2C_RunTransferStateMachineDMA(I2C_Type *base, i2c_master_dma_handle_t *handle, bool *isDone) +{ + uint32_t status; + uint32_t master_state; + struct _i2c_master_transfer *transfer; + dma_transfer_config_t xferConfig; + status_t err; + uint32_t start_flag = 0U; + uint32_t address; + address = (uint32_t)&base->MSTDAT; + + transfer = &(handle->transfer); + + *isDone = false; + + status = I2C_GetStatusFlags(base); + + if ((status & (uint32_t)I2C_STAT_MSTARBLOSS_MASK) != 0U) + { + I2C_MasterClearStatusFlags(base, I2C_STAT_MSTARBLOSS_MASK); + DMA_AbortTransfer(handle->dmaHandle); + base->MSTCTL = 0; + return kStatus_I2C_ArbitrationLost; + } + + if ((status & (uint32_t)I2C_STAT_MSTSTSTPERR_MASK) != 0U) + { + I2C_MasterClearStatusFlags(base, I2C_STAT_MSTSTSTPERR_MASK); + DMA_AbortTransfer(handle->dmaHandle); + base->MSTCTL = 0; + return kStatus_I2C_StartStopError; + } + + /* Event timeout happens when the time since last bus event has been longer than the time specified by TIMEOUT + register. eg: Start signal fails to generate, no error status is set and transfer hangs if glitch on bus happens + before, the timeout status can be used to avoid the transfer hangs indefinitely. */ + if ((status & (uint32_t)kI2C_EventTimeoutFlag) != 0U) + { + I2C_ClearStatusFlags(base, (uint32_t)kI2C_EventTimeoutFlag); + DMA_AbortTransfer(handle->dmaHandle); + base->MSTCTL = 0; + return kStatus_I2C_EventTimeout; + } + + /* SCL timeout happens when the slave is holding the SCL line low and the time has been longer than the time + specified by TIMEOUT register. */ + if ((status & (uint32_t)kI2C_SclTimeoutFlag) != 0U) + { + I2C_ClearStatusFlags(base, (uint32_t)kI2C_SclTimeoutFlag); + DMA_AbortTransfer(handle->dmaHandle); + base->MSTCTL = 0; + return kStatus_I2C_SclLowTimeout; + } + + if ((status & (uint32_t)I2C_STAT_MSTPENDING_MASK) == 0U) + { + return kStatus_I2C_Busy; + } + + /* Get the state of the I2C module */ + master_state = (base->STAT & (uint32_t)I2C_STAT_MSTSTATE_MASK) >> I2C_STAT_MSTSTATE_SHIFT; + + if ((master_state == (uint32_t)I2C_STAT_MSTCODE_NACKADR) || (master_state == (uint32_t)I2C_STAT_MSTCODE_NACKDAT)) + { + /* Slave NACKed last byte, issue stop and return error */ + DMA_AbortTransfer(handle->dmaHandle); + base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; + handle->state = (uint8_t)kWaitForCompletionState; + if ((master_state == (uint32_t)I2C_STAT_MSTCODE_NACKADR) || (handle->checkAddrNack == true)) + { + return kStatus_I2C_Addr_Nak; + } + else + { + return kStatus_I2C_Nak; + } + } + + err = kStatus_Success; + + if (handle->state == (uint8_t)kStartState) + { + /* set start flag for later use */ + start_flag = I2C_MSTCTL_MSTSTART_MASK; + + if (handle->remainingSubaddr != 0U) + { + base->MSTDAT = (uint32_t)transfer->slaveAddress << 1; + handle->state = (uint8_t)kTransmitSubaddrState; + } + else if (transfer->direction == kI2C_Write) + { + base->MSTDAT = (uint32_t)transfer->slaveAddress << 1; + if (transfer->dataSize == 0U) + { + /* No data to be transferred, initiate start and schedule stop */ + base->MSTCTL = I2C_MSTCTL_MSTSTART_MASK; + handle->state = (uint8_t)kStopState; + return err; + } + handle->state = (uint8_t)kTransmitDataState; + } + else if ((transfer->direction == kI2C_Read) && (transfer->dataSize > 0U)) + { + base->MSTDAT = ((uint32_t)transfer->slaveAddress << 1) | 1u; + if (transfer->dataSize == 1U) + { + /* The very last byte is always received by means of SW */ + base->MSTCTL = I2C_MSTCTL_MSTSTART_MASK; + handle->state = (uint8_t)kReceiveLastDataState; + return err; + } + handle->state = (uint8_t)kReceiveDataState; + } + else + { + handle->state = (uint8_t)kIdleState; + err = kStatus_I2C_UnexpectedState; + return err; + } + } + + switch (handle->state) + { + case (uint8_t)kTransmitSubaddrState: + if ((master_state != (uint32_t)I2C_STAT_MSTCODE_TXREADY) && (0U == start_flag)) + { + return kStatus_I2C_UnexpectedState; + } + + base->MSTCTL = start_flag | I2C_MSTCTL_MSTDMA_MASK; + + /* Prepare and submit DMA transfer. */ + DMA_PrepareTransfer(&xferConfig, handle->subaddrBuf, (uint32_t *)address, sizeof(uint8_t), + handle->remainingSubaddr, kDMA_MemoryToPeripheral, NULL); + (void)DMA_SubmitTransfer(handle->dmaHandle, &xferConfig); + DMA_StartTransfer(handle->dmaHandle); + handle->remainingSubaddr = 0; + if (transfer->dataSize != 0U) + { + /* There is data to be transferred, if there is write to read turnaround it is necessary to perform + * repeated start */ + handle->state = (transfer->direction == kI2C_Read) ? (uint8_t)kStartState : (uint8_t)kTransmitDataState; + } + else + { + /* No more data, schedule stop condition */ + handle->state = (uint8_t)kStopState; + } + break; + + case (uint8_t)kTransmitDataState: + if ((master_state != (uint32_t)I2C_STAT_MSTCODE_TXREADY) && (0U == start_flag)) + { + return kStatus_I2C_UnexpectedState; + } + + base->MSTCTL = start_flag | I2C_MSTCTL_MSTDMA_MASK; + handle->remainingBytesDMA = handle->transfer.dataSize; + + I2C_RunDMATransfer(base, handle); + + /* Schedule stop condition */ + handle->state = (uint8_t)kStopState; + handle->checkAddrNack = false; + break; + + case (uint8_t)kReceiveDataState: + if ((master_state != (uint32_t)I2C_STAT_MSTCODE_RXREADY) && (0U == start_flag)) + { + if (0U == (transfer->flags & (uint32_t)kI2C_TransferNoStartFlag)) + { + return kStatus_I2C_UnexpectedState; + } + } + + base->MSTCTL = start_flag | I2C_MSTCTL_MSTDMA_MASK; + handle->remainingBytesDMA = handle->transfer.dataSize - 1U; + + if ((transfer->flags & (uint32_t)kI2C_TransferNoStartFlag) != 0U) + { + /* Read the master data register to avoid the data be read again */ + (void)base->MSTDAT; + } + I2C_RunDMATransfer(base, handle); + + /* Schedule reception of last data byte */ + handle->state = (uint8_t)kReceiveLastDataState; + handle->checkAddrNack = false; + break; + + case (uint8_t)kReceiveLastDataState: + if (master_state != (uint32_t)I2C_STAT_MSTCODE_RXREADY) + { + return kStatus_I2C_UnexpectedState; + } + + ((uint8_t *)transfer->data)[transfer->dataSize - 1U] = (uint8_t)base->MSTDAT; + handle->transferCount++; + + /* No more data expected, issue NACK and STOP right away */ + if (0U == (transfer->flags & (uint32_t)kI2C_TransferNoStopFlag)) + { + base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; + } + handle->state = (uint8_t)kWaitForCompletionState; + break; + + case (uint8_t)kStopState: + if ((transfer->flags & (uint32_t)kI2C_TransferNoStopFlag) != 0U) + { + /* Stop condition is omitted, we are done */ + *isDone = true; + handle->state = (uint8_t)kIdleState; + break; + } + /* Send stop condition */ + base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; + handle->state = (uint8_t)kWaitForCompletionState; + break; + + case (uint8_t)kWaitForCompletionState: + *isDone = true; + handle->state = (uint8_t)kIdleState; + break; + + case (uint8_t)kStartState: + case (uint8_t)kIdleState: + default: + /* State machine shall not be invoked again once it enters the idle state */ + err = kStatus_I2C_UnexpectedState; + break; + } + + return err; +} + +static void I2C_MasterTransferDMAHandleIRQ(I2C_Type *base, i2c_master_dma_handle_t *handle) +{ + bool isDone; + status_t result; + + /* Don't do anything if we don't have a valid handle. */ + if (NULL == handle) + { + return; + } + + result = I2C_RunTransferStateMachineDMA(base, handle, &isDone); + + if ((result != kStatus_Success) || isDone) + { + /* Restore handle to idle state. */ + handle->state = (uint8_t)kIdleState; + + /* Disable internal IRQ enables. */ + I2C_DisableInterrupts(base, I2C_INTSTAT_MSTPENDING_MASK | I2C_INTSTAT_MSTARBLOSS_MASK | + I2C_INTSTAT_MSTSTSTPERR_MASK | I2C_INTSTAT_EVENTTIMEOUT_MASK); + + /* Invoke callback. */ + if (handle->completionCallback != NULL) + { + handle->completionCallback(base, handle, result, handle->userData); + } + } +} + +static void I2C_MasterTransferCallbackDMA(dma_handle_t *handle, void *userData, bool transferDone, uint32_t intmode) +{ + i2c_master_dma_private_handle_t *dmaPrivateHandle; + + /* Don't do anything if we don't have a valid handle. */ + if (NULL == handle) + { + return; + } + + dmaPrivateHandle = (i2c_master_dma_private_handle_t *)userData; + I2C_RunDMATransfer(dmaPrivateHandle->base, dmaPrivateHandle->handle); +} + +/*! + * brief Init the I2C handle which is used in transactional functions + * + * param base I2C peripheral base address + * param handle pointer to i2c_master_dma_handle_t structure + * param callback pointer to user callback function + * param userData user param passed to the callback function + * param dmaHandle DMA handle pointer + */ +void I2C_MasterTransferCreateHandleDMA(I2C_Type *base, + i2c_master_dma_handle_t *handle, + i2c_master_dma_transfer_callback_t callback, + void *userData, + dma_handle_t *dmaHandle) +{ + assert(handle != NULL); + assert(dmaHandle != NULL); + + uint32_t instance; + i2c_dma_to_flexcomm_t handler; + handler.i2c_dma_master_handler = I2C_MasterTransferDMAHandleIRQ; + + /* Zero handle. */ + (void)memset(handle, 0, sizeof(*handle)); + + /* Look up instance number */ + instance = I2C_GetInstance(base); + + /* Set the user callback and userData. */ + handle->completionCallback = callback; + handle->userData = userData; + + FLEXCOMM_SetIRQHandler(base, handler.flexcomm_handler, handle); + + /* Clear internal IRQ enables and enable NVIC IRQ. */ + I2C_DisableInterrupts(base, I2C_INTSTAT_MSTPENDING_MASK | I2C_INTSTAT_MSTARBLOSS_MASK | + I2C_INTSTAT_MSTSTSTPERR_MASK | I2C_INTSTAT_EVENTTIMEOUT_MASK); + (void)EnableIRQ(s_i2cIRQ[instance]); + + /* Set the handle for DMA. */ + handle->dmaHandle = dmaHandle; + + s_dmaPrivateHandle[instance].base = base; + s_dmaPrivateHandle[instance].handle = handle; + + DMA_SetCallback(dmaHandle, I2C_MasterTransferCallbackDMA, &s_dmaPrivateHandle[instance]); +} + +/*! + * brief Performs a master dma non-blocking transfer on the I2C bus + * + * param base I2C peripheral base address + * param handle pointer to i2c_master_dma_handle_t structure + * param xfer pointer to transfer structure of i2c_master_transfer_t + * retval kStatus_Success Sucessully complete the data transmission. + * retval kStatus_I2C_Busy Previous transmission still not finished. + * retval kStatus_I2C_Timeout Transfer error, wait signal timeout. + * retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost. + * retval kStataus_I2C_Nak Transfer error, receive Nak during transfer. + */ +status_t I2C_MasterTransferDMA(I2C_Type *base, i2c_master_dma_handle_t *handle, i2c_master_transfer_t *xfer) +{ + status_t result; + + assert(handle != NULL); + assert(xfer != NULL); + assert(xfer->subaddressSize <= sizeof(xfer->subaddress)); + + /* Return busy if another transaction is in progress. */ + if (handle->state != (uint8_t)kIdleState) + { + return kStatus_I2C_Busy; + } + + /* Prepare transfer state machine. */ + result = I2C_InitTransferStateMachineDMA(base, handle, xfer); + + /* Clear error flags. */ + I2C_MasterClearStatusFlags(base, I2C_STAT_MSTARBLOSS_MASK | I2C_STAT_MSTSTSTPERR_MASK); + + /* Enable I2C internal IRQ sources */ + /* Enable arbitration lost interrupt, start/stop error interrupt and master pending interrupt. + The master pending flag is not set during dma transfer. */ + I2C_EnableInterrupts(base, I2C_INTSTAT_MSTARBLOSS_MASK | I2C_INTSTAT_MSTSTSTPERR_MASK | + I2C_INTSTAT_MSTPENDING_MASK | I2C_INTSTAT_EVENTTIMEOUT_MASK); + + return result; +} + +/*! + * brief Get master transfer status during a dma non-blocking transfer + * + * param base I2C peripheral base address + * param handle pointer to i2c_master_dma_handle_t structure + * param count Number of bytes transferred so far by the non-blocking transaction. + */ +status_t I2C_MasterTransferGetCountDMA(I2C_Type *base, i2c_master_dma_handle_t *handle, size_t *count) +{ + assert(handle != NULL); + + if (NULL == count) + { + return kStatus_InvalidArgument; + } + + /* Catch when there is not an active transfer. */ + if (handle->state == (uint8_t)kIdleState) + { + *count = 0; + return kStatus_NoTransferInProgress; + } + + /* There is no necessity to disable interrupts as we read a single integer value */ + *count = handle->transferCount; + return kStatus_Success; +} + +/*! + * brief Abort a master dma non-blocking transfer in a early time + * + * param base I2C peripheral base address + * param handle pointer to i2c_master_dma_handle_t structure + */ +void I2C_MasterTransferAbortDMA(I2C_Type *base, i2c_master_dma_handle_t *handle) +{ + uint32_t status; + uint32_t master_state; + + if (handle->state != (uint8_t)kIdleState) + { + DMA_AbortTransfer(handle->dmaHandle); + + /* Disable DMA */ + base->MSTCTL = 0; + + /* Disable internal IRQ enables. */ + I2C_DisableInterrupts(base, I2C_INTSTAT_MSTPENDING_MASK | I2C_INTSTAT_MSTARBLOSS_MASK | + I2C_INTSTAT_MSTSTSTPERR_MASK | I2C_INTSTAT_EVENTTIMEOUT_MASK); + + /* Wait until module is ready */ + do + { + status = I2C_GetStatusFlags(base); + } while ((status & (uint8_t)I2C_STAT_MSTPENDING_MASK) == 0U); + + /* Clear controller state. */ + I2C_MasterClearStatusFlags(base, I2C_STAT_MSTARBLOSS_MASK | I2C_STAT_MSTSTSTPERR_MASK); + + /* Get the state of the I2C module */ + master_state = (base->STAT & I2C_STAT_MSTSTATE_MASK) >> I2C_STAT_MSTSTATE_SHIFT; + + if (master_state != (uint32_t)I2C_STAT_MSTCODE_IDLE) + { + /* Send a stop command to finalize the transfer. */ + base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; + + /* Wait until module is ready */ + do + { + status = I2C_GetStatusFlags(base); + } while ((status & (uint32_t)I2C_STAT_MSTPENDING_MASK) == 0U); + + /* Clear controller state. */ + I2C_MasterClearStatusFlags(base, I2C_STAT_MSTARBLOSS_MASK | I2C_STAT_MSTSTSTPERR_MASK); + } + + /* Reset the state to idle. */ + handle->state = (uint8_t)kIdleState; + } +} diff --git a/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_i2c_dma.h b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_i2c_dma.h new file mode 100644 index 0000000000..07899f9c7c --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_i2c_dma.h @@ -0,0 +1,124 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_I2C_DMA_H_ +#define _FSL_I2C_DMA_H_ + +#include "fsl_i2c.h" +#include "fsl_dma.h" + +/*! + * @addtogroup i2c_dma_driver + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief I2C DMA driver version. */ +#define FSL_I2C_DMA_DRIVER_VERSION (MAKE_VERSION(2, 3, 0)) +/*@}*/ + +/*! @brief Maximum lenght of single DMA transfer (determined by capability of the DMA engine) */ +#define I2C_MAX_DMA_TRANSFER_COUNT 1024 + +/*! @brief I2C master dma handle typedef. */ +typedef struct _i2c_master_dma_handle i2c_master_dma_handle_t; + +/*! @brief I2C master dma transfer callback typedef. */ +typedef void (*i2c_master_dma_transfer_callback_t)(I2C_Type *base, + i2c_master_dma_handle_t *handle, + status_t status, + void *userData); + +/*! @brief Typedef for master dma handler. */ +typedef void (*flexcomm_i2c_dma_master_irq_handler_t)(I2C_Type *base, i2c_master_dma_handle_t *handle); + +/*! @brief I2C master dma transfer structure. */ +struct _i2c_master_dma_handle +{ + uint8_t state; /*!< Transfer state machine current state. */ + uint32_t transferCount; /*!< Indicates progress of the transfer */ + uint32_t remainingBytesDMA; /*!< Remaining byte count to be transferred using DMA. */ + uint8_t *buf; /*!< Buffer pointer for current state. */ + uint32_t remainingSubaddr; + uint8_t subaddrBuf[4]; + bool checkAddrNack; /*!< Whether to check the nack signal is detected during addressing. */ + dma_handle_t *dmaHandle; /*!< The DMA handler used. */ + i2c_master_transfer_t transfer; /*!< Copy of the current transfer info. */ + i2c_master_dma_transfer_callback_t completionCallback; /*!< Callback function called after dma transfer finished. */ + void *userData; /*!< Callback parameter passed to callback function. */ +}; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /*_cplusplus. */ + +/*! + * @name I2C Block DMA Transfer Operation + * @{ + */ + +/*! + * @brief Init the I2C handle which is used in transactional functions + * + * @param base I2C peripheral base address + * @param handle pointer to i2c_master_dma_handle_t structure + * @param callback pointer to user callback function + * @param userData user param passed to the callback function + * @param dmaHandle DMA handle pointer + */ +void I2C_MasterTransferCreateHandleDMA(I2C_Type *base, + i2c_master_dma_handle_t *handle, + i2c_master_dma_transfer_callback_t callback, + void *userData, + dma_handle_t *dmaHandle); + +/*! + * @brief Performs a master dma non-blocking transfer on the I2C bus + * + * @param base I2C peripheral base address + * @param handle pointer to i2c_master_dma_handle_t structure + * @param xfer pointer to transfer structure of i2c_master_transfer_t + * @retval kStatus_Success Sucessully complete the data transmission. + * @retval kStatus_I2C_Busy Previous transmission still not finished. + * @retval kStatus_I2C_Timeout Transfer error, wait signal timeout. + * @retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost. + * @retval kStataus_I2C_Nak Transfer error, receive Nak during transfer. + */ +status_t I2C_MasterTransferDMA(I2C_Type *base, i2c_master_dma_handle_t *handle, i2c_master_transfer_t *xfer); + +/*! + * @brief Get master transfer status during a dma non-blocking transfer + * + * @param base I2C peripheral base address + * @param handle pointer to i2c_master_dma_handle_t structure + * @param count Number of bytes transferred so far by the non-blocking transaction. + */ +status_t I2C_MasterTransferGetCountDMA(I2C_Type *base, i2c_master_dma_handle_t *handle, size_t *count); + +/*! + * @brief Abort a master dma non-blocking transfer in a early time + * + * @param base I2C peripheral base address + * @param handle pointer to i2c_master_dma_handle_t structure + */ +void I2C_MasterTransferAbortDMA(I2C_Type *base, i2c_master_dma_handle_t *handle); + +/* @} */ +#if defined(__cplusplus) +} +#endif /*_cplusplus. */ +/*@}*/ +#endif /*_FSL_I2C_DMA_H_*/ diff --git a/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_i2s.c b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_i2s.c new file mode 100644 index 0000000000..c13f2f4bcd --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_i2s.c @@ -0,0 +1,1198 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_i2s.h" +#include "fsl_flexcomm.h" +#include + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.flexcomm_i2s" +#endif + +/* TODO - absent in device header files, should be there */ +#define I2S_FIFOCFG_TXI2SE0_MASK (0x4U) +#define I2S_FIFOCFG_TXI2SE0_SHIFT (2U) +#define I2S_FIFOCFG_TXI2SE0(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_TXI2SE0_SHIFT)) & I2S_FIFOCFG_TXI2SE0_MASK) +#define I2S_FIFOCFG_PACK48_MASK (0x8U) +#define I2S_FIFOCFG_PACK48_SHIFT (3U) +#define I2S_FIFOCFG_PACK48(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_PACK48_SHIFT)) & I2S_FIFOCFG_PACK48_MASK) +/*! @brief i2s empty tx fifo timeout value */ +#define I2S_FIFO_DEPTH (8U) +#define I2S_TX_ONE_SAMPLE_MAX_TIMEOUT (125U) /* 8K/8bit one sample need 125us*/ +#define I2S_TX_FIFO_EMPTY_TIMEOUT(count) (count) * I2S_TX_ONE_SAMPLE_MAX_TIMEOUT +/*! @brief _i2s_state I2S states. */ +enum +{ + kI2S_StateIdle = 0x0, /*!< Not performing transfer */ + kI2S_StateTx, /*!< Performing transmit */ + kI2S_StateTxWaitToWriteDummyData, /*!< Wait on FIFO in order to write final dummy data there */ + kI2S_StateTxWaitForEmptyFifo, /*!< Wait for FIFO to be flushed */ + kI2S_StateRx, /*!< Performing receive */ +}; + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +static void I2S_Config(I2S_Type *base, const i2s_config_t *config); +static void I2S_TxEnable(I2S_Type *base, bool enable); +static void I2S_RxEnable(I2S_Type *base, bool enable); +static status_t I2S_ValidateBuffer(i2s_handle_t *handle, i2s_transfer_t *transfer); + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/*! @brief Array to map i2c instance number to base address. */ +static const uint32_t s_i2sBaseAddrs[] = I2S_BASE_ADDRS; + +/*! @brief IRQ name array */ +static const IRQn_Type s_i2sIRQ[] = I2S_IRQS; + +/******************************************************************************* + * Code + ******************************************************************************/ +/*! + * @brief Returns an instance number given a base address. + * + * If an invalid base address is passed, debug builds will assert. Release builds will just return + * instance number 0. + * + * @param base The I2S peripheral base address. + * @return I2S instance number starting from 0. + */ +static uint32_t I2S_GetInstance(I2S_Type *base) +{ + uint32_t i; + for (i = 0; i < (uint32_t)ARRAY_SIZE(s_i2sBaseAddrs); i++) + { + if ((uint32_t)base == s_i2sBaseAddrs[i]) + { + return i; + } + } + assert(false); + return 0; +} + +/*! + * brief Transmitter bit clock rate configurations. + * + * param base SAI base pointer. + * param sourceClockHz, bit clock source frequency. + * param sampleRate audio data sample rate. + * param bitWidth, audio data bitWidth. + * param channelNumbers, audio channel numbers. + */ +void I2S_SetBitClockRate( + I2S_Type *base, uint32_t sourceClockHz, uint32_t sampleRate, uint32_t bitWidth, uint32_t channelNumbers) +{ + uint32_t bitClockDivider = sourceClockHz / sampleRate / bitWidth / channelNumbers; + + assert(bitClockDivider >= 1U); + base->DIV = I2S_DIV_DIV(bitClockDivider - 1U); +} + +/*! + * brief Initializes the FLEXCOMM peripheral for I2S transmit functionality. + * + * Ungates the FLEXCOMM clock and configures the module + * for I2S transmission using a configuration structure. + * The configuration structure can be custom filled or set with default values by + * I2S_TxGetDefaultConfig(). + * + * note This API should be called at the beginning of the application to use + * the I2S driver. + * + * param base I2S base pointer. + * param config pointer to I2S configuration structure. + */ +void I2S_TxInit(I2S_Type *base, const i2s_config_t *config) +{ + uint32_t cfg = 0U; + uint32_t trig = 0U; + + (void)FLEXCOMM_Init(base, FLEXCOMM_PERIPH_I2S_TX); + I2S_Config(base, config); + + /* Configure FIFO */ + + cfg |= I2S_FIFOCFG_ENABLETX(1U); /* enable TX FIFO */ + cfg |= I2S_FIFOCFG_EMPTYTX(1U); /* empty TX FIFO */ + cfg |= I2S_FIFOCFG_TXI2SE0(config->txEmptyZero); /* transmit zero when buffer becomes empty or last item */ + cfg |= I2S_FIFOCFG_PACK48(config->pack48); /* set pack 48-bit format or not */ + trig |= I2S_FIFOTRIG_TXLVLENA(1U); /* enable TX FIFO trigger */ + trig |= I2S_FIFOTRIG_TXLVL(config->watermark); /* set TX FIFO trigger level */ + + base->FIFOCFG = cfg; + base->FIFOTRIG = trig; +} + +/*! + * brief Initializes the FLEXCOMM peripheral for I2S receive functionality. + * + * Ungates the FLEXCOMM clock and configures the module + * for I2S receive using a configuration structure. + * The configuration structure can be custom filled or set with default values by + * I2S_RxGetDefaultConfig(). + * + * note This API should be called at the beginning of the application to use + * the I2S driver. + * + * param base I2S base pointer. + * param config pointer to I2S configuration structure. + */ +void I2S_RxInit(I2S_Type *base, const i2s_config_t *config) +{ + uint32_t cfg = 0U; + uint32_t trig = 0U; + + (void)FLEXCOMM_Init(base, FLEXCOMM_PERIPH_I2S_RX); + I2S_Config(base, config); + + /* Configure FIFO */ + + cfg |= I2S_FIFOCFG_ENABLERX(1U); /* enable RX FIFO */ + cfg |= I2S_FIFOCFG_EMPTYRX(1U); /* empty RX FIFO */ + cfg |= I2S_FIFOCFG_PACK48(config->pack48); /* set pack 48-bit format or not */ + trig |= I2S_FIFOTRIG_RXLVLENA(1U); /* enable RX FIFO trigger */ + trig |= I2S_FIFOTRIG_RXLVL(config->watermark); /* set RX FIFO trigger level */ + + base->FIFOCFG = cfg; + base->FIFOTRIG = trig; +} + +/*! + * brief Flush the valid data in TX fifo. + * + * param base I2S base pointer. + * return kStatus_Fail empty TX fifo failed, kStatus_Success empty tx fifo success. + */ +status_t I2S_EmptyTxFifo(I2S_Type *base) +{ + uint32_t timeout = I2S_TX_FIFO_EMPTY_TIMEOUT(I2S_FIFO_DEPTH); + + while (((base->FIFOSTAT & I2S_FIFOSTAT_TXEMPTY_MASK) == 0U) && (timeout != 0U)) + { + timeout -= I2S_TX_ONE_SAMPLE_MAX_TIMEOUT; + SDK_DelayAtLeastUs(I2S_TX_ONE_SAMPLE_MAX_TIMEOUT, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); + } + + /* The last piece of valid data can be still being transmitted from I2S at this moment */ + timeout = I2S_TX_ONE_SAMPLE_MAX_TIMEOUT; + /* Write additional data to FIFO */ + base->FIFOWR = 0U; + while (((base->FIFOSTAT & I2S_FIFOSTAT_TXEMPTY_MASK) == 0U) && (timeout != 0U)) + { + timeout -= I2S_TX_ONE_SAMPLE_MAX_TIMEOUT; + SDK_DelayAtLeastUs(I2S_TX_ONE_SAMPLE_MAX_TIMEOUT, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); + } + + return ((base->FIFOSTAT & I2S_FIFOSTAT_TXEMPTY_MASK) == 0U) ? kStatus_Fail : kStatus_Success; +} + +/*! + * brief Sets the I2S Tx configuration structure to default values. + * + * This API initializes the configuration structure for use in I2S_TxInit(). + * The initialized structure can remain unchanged in I2S_TxInit(), or it can be modified + * before calling I2S_TxInit(). + * Example: + code + i2s_config_t config; + I2S_TxGetDefaultConfig(&config); + endcode + * + * Default values: + * code + * config->masterSlave = kI2S_MasterSlaveNormalMaster; + * config->mode = kI2S_ModeI2sClassic; + * config->rightLow = false; + * config->leftJust = false; + * config->pdmData = false; + * config->sckPol = false; + * config->wsPol = false; + * config->divider = 1; + * config->oneChannel = false; + * config->dataLength = 16; + * config->frameLength = 32; + * config->position = 0; + * config->watermark = 4; + * config->txEmptyZero = true; + * config->pack48 = false; + * endcode + * + * param config pointer to I2S configuration structure. + */ +void I2S_TxGetDefaultConfig(i2s_config_t *config) +{ + config->masterSlave = kI2S_MasterSlaveNormalMaster; + config->mode = kI2S_ModeI2sClassic; + config->rightLow = false; + config->leftJust = false; +#if (defined(FSL_FEATURE_FLEXCOMM_I2S_HAS_DMIC_INTERCONNECTION) && FSL_FEATURE_FLEXCOMM_I2S_HAS_DMIC_INTERCONNECTION) + config->pdmData = false; +#endif + config->sckPol = false; + config->wsPol = false; + config->divider = 1U; + config->oneChannel = false; + config->dataLength = 16U; + config->frameLength = 32U; + config->position = 0U; + config->watermark = 4U; + config->txEmptyZero = true; + config->pack48 = false; +} + +/*! + * brief Sets the I2S Rx configuration structure to default values. + * + * This API initializes the configuration structure for use in I2S_RxInit(). + * The initialized structure can remain unchanged in I2S_RxInit(), or it can be modified + * before calling I2S_RxInit(). + * Example: + code + i2s_config_t config; + I2S_RxGetDefaultConfig(&config); + endcode + * + * Default values: + * code + * config->masterSlave = kI2S_MasterSlaveNormalSlave; + * config->mode = kI2S_ModeI2sClassic; + * config->rightLow = false; + * config->leftJust = false; + * config->pdmData = false; + * config->sckPol = false; + * config->wsPol = false; + * config->divider = 1; + * config->oneChannel = false; + * config->dataLength = 16; + * config->frameLength = 32; + * config->position = 0; + * config->watermark = 4; + * config->txEmptyZero = false; + * config->pack48 = false; + * endcode + * + * param config pointer to I2S configuration structure. + */ +void I2S_RxGetDefaultConfig(i2s_config_t *config) +{ + config->masterSlave = kI2S_MasterSlaveNormalSlave; + config->mode = kI2S_ModeI2sClassic; + config->rightLow = false; + config->leftJust = false; +#if (defined(FSL_FEATURE_FLEXCOMM_I2S_HAS_DMIC_INTERCONNECTION) && FSL_FEATURE_FLEXCOMM_I2S_HAS_DMIC_INTERCONNECTION) + config->pdmData = false; +#endif + config->sckPol = false; + config->wsPol = false; + config->divider = 1U; + config->oneChannel = false; + config->dataLength = 16U; + config->frameLength = 32U; + config->position = 0U; + config->watermark = 4U; + config->txEmptyZero = false; + config->pack48 = false; +} + +static void I2S_Config(I2S_Type *base, const i2s_config_t *config) +{ + assert(config != NULL); + + uint32_t cfg1 = 0U; + uint32_t cfg2 = 0U; + + /* set master/slave configuration */ + cfg1 |= I2S_CFG1_MSTSLVCFG(config->masterSlave); + + /* set I2S mode */ + cfg1 |= I2S_CFG1_MODE(config->mode); + + /* set right low (channel swap) */ + cfg1 |= I2S_CFG1_RIGHTLOW(config->rightLow); + + /* set data justification */ + cfg1 |= I2S_CFG1_LEFTJUST(config->leftJust); + +#if (defined(FSL_FEATURE_FLEXCOMM_I2S_HAS_DMIC_INTERCONNECTION) && FSL_FEATURE_FLEXCOMM_I2S_HAS_DMIC_INTERCONNECTION) + if (FSL_FEATURE_FLEXCOMM_INSTANCE_I2S_HAS_DMIC_INTERCONNECTIONn((FLEXCOMM_Type *)(uint32_t)base) > 0) + { + /* set source to PDM dmic */ + cfg1 |= I2S_CFG1_PDMDATA(config->pdmData); + } +#endif + + /* set SCLK polarity */ + cfg1 |= I2S_CFG1_SCK_POL(config->sckPol); + + /* set WS polarity */ + cfg1 |= I2S_CFG1_WS_POL(config->wsPol); + + /* set mono mode */ + cfg1 |= I2S_CFG1_ONECHANNEL(config->oneChannel); + + /* set data length */ + cfg1 |= I2S_CFG1_DATALEN(config->dataLength - 1UL); + + /* set frame length */ + cfg2 |= I2S_CFG2_FRAMELEN(config->frameLength - 1UL); + + /* set data position of this channel pair within the frame */ + cfg2 |= I2S_CFG2_POSITION(config->position); + + /* write to registers */ + base->CFG1 = cfg1; + base->CFG2 = cfg2; + + /* set the clock divider */ + base->DIV = I2S_DIV_DIV(config->divider - 1UL); +} + +/*! + * brief De-initializes the I2S peripheral. + * + * This API gates the FLEXCOMM clock. The I2S module can't operate unless I2S_TxInit + * or I2S_RxInit is called to enable the clock. + * + * param base I2S base pointer. + */ +void I2S_Deinit(I2S_Type *base) +{ + /* TODO gate FLEXCOMM clock via FLEXCOMM driver */ +} + +static void I2S_TxEnable(I2S_Type *base, bool enable) +{ + if (enable) + { + I2S_Enable(base); + I2S_EnableInterrupts(base, (uint32_t)kI2S_TxErrorFlag | (uint32_t)kI2S_TxLevelFlag); + } + else + { + I2S_DisableInterrupts(base, (uint32_t)kI2S_TxErrorFlag | (uint32_t)kI2S_TxLevelFlag); + I2S_Disable(base); + base->FIFOCFG |= I2S_FIFOCFG_EMPTYTX_MASK; + } +} + +static void I2S_RxEnable(I2S_Type *base, bool enable) +{ + if (enable) + { + I2S_Enable(base); + I2S_EnableInterrupts(base, (uint32_t)kI2S_RxErrorFlag | (uint32_t)kI2S_RxLevelFlag); + } + else + { + I2S_DisableInterrupts(base, (uint32_t)kI2S_RxErrorFlag | (uint32_t)kI2S_RxLevelFlag); + I2S_Disable(base); + base->FIFOCFG |= I2S_FIFOCFG_EMPTYRX_MASK; + } +} + +static status_t I2S_ValidateBuffer(i2s_handle_t *handle, i2s_transfer_t *transfer) +{ + assert(transfer->data != NULL); + + if (transfer->data == NULL) + { + return kStatus_InvalidArgument; + } + + assert(transfer->dataSize > 0U); + if (transfer->dataSize <= 0U) + { + return kStatus_InvalidArgument; + } + + if (handle->dataLength == 4U) + { + /* No alignment and data length requirements */ + } + else if ((handle->dataLength >= 5U) && (handle->dataLength <= 8U)) + { + assert((((uint32_t)transfer->data) % 2U) == 0U); + if ((((uint32_t)transfer->data) % 2U) != 0U) + { + /* Data not 2-bytes aligned */ + return kStatus_InvalidArgument; + } + + assert((transfer->dataSize % 2U) == 0U); + if ((transfer->dataSize % 2U) != 0U) + { + /* Data not in pairs of left/right channel bytes */ + return kStatus_InvalidArgument; + } + } + else if ((handle->dataLength >= 9U) && (handle->dataLength <= 16U)) + { + assert((((uint32_t)transfer->data) % 4U) == 0U); + if ((((uint32_t)transfer->data) % 4U) != 0U) + { + /* Data not 4-bytes aligned */ + return kStatus_InvalidArgument; + } + + assert((transfer->dataSize % 4U) == 0U); + if ((transfer->dataSize % 4U) != 0U) + { + /* Data lenght not multiply of 4 */ + return kStatus_InvalidArgument; + } + } + else if ((handle->dataLength >= 17U) && (handle->dataLength <= 24U)) + { + assert((transfer->dataSize % 6U) == 0U); + if ((transfer->dataSize % 6U) != 0U) + { + /* Data lenght not multiply of 6 */ + return kStatus_InvalidArgument; + } + + assert(!((handle->pack48) && ((((uint32_t)transfer->data) % 4U) != 0U))); + if ((handle->pack48) && ((((uint32_t)transfer->data) % 4U) != 0U)) + { + /* Data not 4-bytes aligned */ + return kStatus_InvalidArgument; + } + } + else /* if (handle->dataLength >= 25U) */ + { + assert((((uint32_t)transfer->data) % 4U) == 0U); + if ((((uint32_t)transfer->data) % 4U) != 0U) + { + /* Data not 4-bytes aligned */ + return kStatus_InvalidArgument; + } + + if (handle->oneChannel) + { + assert((transfer->dataSize % 4U) == 0U); + if ((transfer->dataSize % 4U) != 0U) + { + /* Data lenght not multiply of 4 */ + return kStatus_InvalidArgument; + } + } + else + { + assert((transfer->dataSize % 8U) == 0U); + if ((transfer->dataSize % 8U) != 0U) + { + /* Data lenght not multiply of 8 */ + return kStatus_InvalidArgument; + } + } + } + + return kStatus_Success; +} + +#if (defined(FSL_FEATURE_I2S_SUPPORT_SECONDARY_CHANNEL) && FSL_FEATURE_I2S_SUPPORT_SECONDARY_CHANNEL) +/*! + * brief Enables I2S secondary channel. + * + * param base I2S base pointer. + * param channel seondary channel channel number, reference _i2s_secondary_channel. + * param oneChannel true is treated as single channel, functionality left channel for this pair. + * param position define the location within the frame of the data, should not bigger than 0x1FFU. + */ +void I2S_EnableSecondaryChannel(I2S_Type *base, uint32_t channel, bool oneChannel, uint32_t position) +{ + assert(channel <= (uint32_t)kI2S_SecondaryChannel3); +#if defined FSL_FEATURE_FLEXCOMM_INSTANCE_I2S_SUPPORT_SECONDARY_CHANNELn + assert(FSL_FEATURE_FLEXCOMM_INSTANCE_I2S_SUPPORT_SECONDARY_CHANNELn((FLEXCOMM_Type *)(uint32_t)base) == 1); +#endif + + uint32_t pcfg1 = base->SECCHANNEL[channel].PCFG1; + uint32_t pcfg2 = base->SECCHANNEL[channel].PCFG2; + + pcfg1 &= ~I2S_CFG1_ONECHANNEL_MASK; + pcfg1 |= I2S_CFG1_MAINENABLE_MASK | I2S_CFG1_ONECHANNEL(oneChannel); + + pcfg2 &= ~I2S_CFG2_POSITION_MASK; + pcfg2 |= I2S_CFG2_POSITION(position); + + base->SECCHANNEL[channel].PCFG1 = pcfg1; + base->SECCHANNEL[channel].PCFG2 = pcfg2; +} +#endif + +/*! + * brief Initializes handle for transfer of audio data. + * + * param base I2S base pointer. + * param handle pointer to handle structure. + * param callback function to be called back when transfer is done or fails. + * param userData pointer to data passed to callback. + */ +void I2S_TxTransferCreateHandle(I2S_Type *base, i2s_handle_t *handle, i2s_transfer_callback_t callback, void *userData) +{ + assert(handle != NULL); + + uint32_t instance; + + /* Clear out the handle */ + (void)memset(handle, 0, sizeof(*handle)); + + /* Look up instance number */ + instance = I2S_GetInstance(base); + + /* Save callback and user data */ + handle->completionCallback = callback; + handle->userData = userData; + + /* Remember some items set previously by configuration */ + handle->watermark = (uint8_t)((base->FIFOTRIG & I2S_FIFOTRIG_TXLVL_MASK) >> I2S_FIFOTRIG_TXLVL_SHIFT); + handle->oneChannel = ((base->CFG1 & I2S_CFG1_ONECHANNEL_MASK) >> I2S_CFG1_ONECHANNEL_SHIFT) != 0U ? true : false; + handle->dataLength = (uint8_t)((base->CFG1 & I2S_CFG1_DATALEN_MASK) >> I2S_CFG1_DATALEN_SHIFT) + 1U; + handle->pack48 = ((base->FIFOCFG & I2S_FIFOCFG_PACK48_MASK) >> I2S_FIFOCFG_PACK48_SHIFT) != 0u ? true : false; + + handle->useFifo48H = false; + + /* Register IRQ handling */ + FLEXCOMM_SetIRQHandler(base, (flexcomm_irq_handler_t)I2S_TxHandleIRQ, handle); + /* Clear internal IRQ enables and enable NVIC IRQ. */ + I2S_DisableInterrupts(base, (uint32_t)kI2S_TxErrorFlag | (uint32_t)kI2S_TxLevelFlag); + (void)EnableIRQ(s_i2sIRQ[instance]); +} + +/*! + * brief Begins or queue sending of the given data. + * + * param base I2S base pointer. + * param handle pointer to handle structure. + * param transfer data buffer. + * + * retval kStatus_Success + * retval kStatus_I2S_Busy if all queue slots are occupied with unsent buffers. + */ +status_t I2S_TxTransferNonBlocking(I2S_Type *base, i2s_handle_t *handle, i2s_transfer_t transfer) +{ + assert(handle != NULL); + + status_t result; + + if (handle == NULL) + { + return kStatus_InvalidArgument; + } + + result = I2S_ValidateBuffer(handle, &transfer); + if (result != kStatus_Success) + { + return result; + } + + if (handle->i2sQueue[handle->queueUser].dataSize != 0UL) + { + /* Previously prepared buffers not processed yet */ + return kStatus_I2S_Busy; + } + + handle->i2sQueue[handle->queueUser].data = transfer.data; + handle->i2sQueue[handle->queueUser].dataSize = transfer.dataSize; + handle->queueUser = (handle->queueUser + 1U) % I2S_NUM_BUFFERS; + + base->FIFOTRIG = (base->FIFOTRIG & (~I2S_FIFOTRIG_TXLVL_MASK)) | I2S_FIFOTRIG_TXLVL(handle->watermark); + I2S_TxEnable(base, true); + + return kStatus_Success; +} + +/*! + * brief Aborts sending of data. + * + * param base I2S base pointer. + * param handle pointer to handle structure. + */ +void I2S_TxTransferAbort(I2S_Type *base, i2s_handle_t *handle) +{ + assert(handle != NULL); + + /* Disable I2S operation and interrupts */ + I2S_TxEnable(base, false); + + /* Reset state */ + handle->state = (uint32_t)kI2S_StateIdle; + + /* Clear transfer queue */ + (void)memset((void *)&handle->i2sQueue, 0, sizeof(i2s_transfer_t) * I2S_NUM_BUFFERS); + handle->queueDriver = 0U; + handle->queueUser = 0U; +} + +/*! + * brief Initializes handle for reception of audio data. + * + * param base I2S base pointer. + * param handle pointer to handle structure. + * param callback function to be called back when transfer is done or fails. + * param userData pointer to data passed to callback. + */ +void I2S_RxTransferCreateHandle(I2S_Type *base, i2s_handle_t *handle, i2s_transfer_callback_t callback, void *userData) +{ + assert(handle != NULL); + + uint32_t instance; + + /* Clear out the handle */ + (void)memset(handle, 0, sizeof(*handle)); + + /* Look up instance number */ + instance = I2S_GetInstance(base); + + /* Save callback and user data */ + handle->completionCallback = callback; + handle->userData = userData; + + /* Remember some items set previously by configuration */ + handle->watermark = (uint8_t)((base->FIFOTRIG & I2S_FIFOTRIG_RXLVL_MASK) >> I2S_FIFOTRIG_RXLVL_SHIFT); + handle->oneChannel = ((base->CFG1 & I2S_CFG1_ONECHANNEL_MASK) >> I2S_CFG1_ONECHANNEL_SHIFT) != 0UL ? true : false; + handle->dataLength = (uint8_t)((base->CFG1 & I2S_CFG1_DATALEN_MASK) >> I2S_CFG1_DATALEN_SHIFT) + 1U; + handle->pack48 = ((base->FIFOCFG & I2S_FIFOCFG_PACK48_MASK) >> I2S_FIFOCFG_PACK48_SHIFT) != 0UL ? true : false; + + handle->useFifo48H = false; + + /* Register IRQ handling */ + FLEXCOMM_SetIRQHandler(base, (flexcomm_irq_handler_t)I2S_RxHandleIRQ, handle); + /* Clear internal IRQ enables and enable NVIC IRQ. */ + I2S_DisableInterrupts(base, (uint32_t)kI2S_RxErrorFlag | (uint32_t)kI2S_RxLevelFlag); + + (void)EnableIRQ(s_i2sIRQ[instance]); +} + +/*! + * brief Begins or queue reception of data into given buffer. + * + * param base I2S base pointer. + * param handle pointer to handle structure. + * param transfer data buffer. + * + * retval kStatus_Success + * retval kStatus_I2S_Busy if all queue slots are occupied with buffers which are not full. + */ +status_t I2S_RxTransferNonBlocking(I2S_Type *base, i2s_handle_t *handle, i2s_transfer_t transfer) +{ + assert(handle != NULL); + + status_t result; + + if (NULL == handle) + { + return kStatus_InvalidArgument; + } + + result = I2S_ValidateBuffer(handle, &transfer); + if (result != kStatus_Success) + { + return result; + } + + if (handle->i2sQueue[handle->queueUser].dataSize != 0UL) + { + /* Previously prepared buffers not processed yet */ + return kStatus_I2S_Busy; + } + + handle->i2sQueue[handle->queueUser].data = transfer.data; + handle->i2sQueue[handle->queueUser].dataSize = transfer.dataSize; + handle->queueUser = (handle->queueUser + 1U) % I2S_NUM_BUFFERS; + + base->FIFOTRIG = (base->FIFOTRIG & (~I2S_FIFOTRIG_RXLVL_MASK)) | I2S_FIFOTRIG_RXLVL(handle->watermark); + I2S_RxEnable(base, true); + + return kStatus_Success; +} + +/*! + * brief Aborts receiving of data. + * + * param base I2S base pointer. + * param handle pointer to handle structure. + */ +void I2S_RxTransferAbort(I2S_Type *base, i2s_handle_t *handle) +{ + assert(handle != NULL); + + /* Disable I2S operation and interrupts */ + I2S_RxEnable(base, false); + + /* Reset state */ + handle->state = (uint32_t)kI2S_StateIdle; + + /* Clear transfer queue */ + (void)memset((void *)&handle->i2sQueue, 0, sizeof(i2s_transfer_t) * I2S_NUM_BUFFERS); + handle->queueDriver = 0U; + handle->queueUser = 0U; +} + +/*! + * brief Returns number of bytes transferred so far. + * + * param base I2S base pointer. + * param handle pointer to handle structure. + * param[out] count number of bytes transferred so far by the non-blocking transaction. + * + * retval kStatus_Success + * retval kStatus_NoTransferInProgress there is no non-blocking transaction currently in progress. + */ +status_t I2S_TransferGetCount(I2S_Type *base, i2s_handle_t *handle, size_t *count) +{ + assert(handle != NULL); + assert(count != NULL); + + if (NULL == handle) + { + return kStatus_InvalidArgument; + } + + if (NULL == count) + { + return kStatus_InvalidArgument; + } + + if (handle->state == (uint32_t)kI2S_StateIdle) + { + return kStatus_NoTransferInProgress; + } + + *count = handle->transferCount; + + return kStatus_Success; +} + +/*! + * brief Returns number of buffer underruns or overruns. + * + * param base I2S base pointer. + * param handle pointer to handle structure. + * param[out] count number of transmit errors encountered so far by the non-blocking transaction. + * + * retval kStatus_Success + * retval kStatus_NoTransferInProgress there is no non-blocking transaction currently in progress. + */ +status_t I2S_TransferGetErrorCount(I2S_Type *base, i2s_handle_t *handle, size_t *count) +{ + assert(handle != NULL); + assert(count != NULL); + + if (NULL == handle) + { + return kStatus_InvalidArgument; + } + + if (NULL == count) + { + return kStatus_InvalidArgument; + } + + if (handle->state == (uint32_t)kI2S_StateIdle) + { + return kStatus_NoTransferInProgress; + } + + *count = handle->errorCount; + + return kStatus_Success; +} + +/*! + * brief Invoked from interrupt handler when transmit FIFO level decreases. + * + * param base I2S base pointer. + * param handle pointer to handle structure. + */ +void I2S_TxHandleIRQ(I2S_Type *base, i2s_handle_t *handle) +{ + uint32_t intstat = base->FIFOINTSTAT; + uint32_t data; + uint8_t queueDriverIndex = handle->queueDriver; + uint32_t dataAddr = (uint32_t)handle->i2sQueue[queueDriverIndex].data; + uint32_t dataSize = handle->i2sQueue[queueDriverIndex].dataSize; + + if ((intstat & I2S_FIFOINTSTAT_TXERR_MASK) != 0UL) + { + handle->errorCount++; + + /* Clear TX error interrupt flag */ + base->FIFOSTAT = I2S_FIFOSTAT_TXERR(1U); + } + + if ((intstat & I2S_FIFOINTSTAT_TXLVL_MASK) != 0UL) + { + if ((handle->state != (uint32_t)kI2S_StateTx) && (dataSize != 0U) && (dataAddr != 0U)) + { + handle->state = (uint32_t)kI2S_StateTx; + } + + if (handle->state == (uint32_t)kI2S_StateTx) + { + /* Send data */ + + while (((base->FIFOSTAT & I2S_FIFOSTAT_TXNOTFULL_MASK) != 0UL) && (dataSize > 0U)) + { + /* Write output data */ + if (handle->dataLength == 4U) + { + data = *((uint8_t *)dataAddr); + base->FIFOWR = ((data & 0xF0U) << 12U) | (data & 0xFU); + dataAddr++; + handle->transferCount++; + dataSize--; + } + else if (handle->dataLength <= 8U) + { + data = *((volatile uint16_t *)dataAddr); + if (handle->oneChannel) + { + base->FIFOWR = (data & 0xFFU); + dataAddr += sizeof(uint8_t); + handle->transferCount += sizeof(uint8_t); + dataSize -= sizeof(uint8_t); + } + else + { + base->FIFOWR = ((data & 0xFF00U) << 8U) | (data & 0xFFU); + dataAddr += sizeof(uint16_t); + handle->transferCount += sizeof(uint16_t); + dataSize -= sizeof(uint16_t); + } + } + else if (handle->dataLength <= 16U) + { + data = *((volatile uint32_t *)(dataAddr)); + if (handle->oneChannel) + { + base->FIFOWR = data & 0xFFFFU; + dataAddr += sizeof(uint16_t); + handle->transferCount += sizeof(uint16_t); + dataSize -= sizeof(uint16_t); + } + else + { + base->FIFOWR = data; + dataAddr += sizeof(uint32_t); + handle->transferCount += sizeof(uint32_t); + dataSize -= sizeof(uint32_t); + } + } + else if (handle->dataLength <= 24U) + { + if (handle->pack48) + { + if (handle->useFifo48H) + { + base->FIFOWR48H = *((volatile uint16_t *)(dataAddr)); + dataAddr += sizeof(uint16_t); + handle->transferCount += sizeof(uint16_t); + dataSize -= sizeof(uint16_t); + handle->useFifo48H = false; + } + else + { + base->FIFOWR = *((volatile uint32_t *)(dataAddr)); + dataAddr += sizeof(uint32_t); + handle->transferCount += sizeof(uint32_t); + dataSize -= sizeof(uint32_t); + handle->useFifo48H = true; + } + } + else + { + data = (uint32_t)(*(uint8_t *)(dataAddr++)); + data |= ((uint32_t)(*(uint8_t *)(dataAddr++))) << 8U; + data |= ((uint32_t)(*(uint8_t *)(dataAddr++))) << 16U; + if ((handle->useFifo48H) && (handle->oneChannel == false)) + { + base->FIFOWR48H = data; + handle->useFifo48H = false; + } + else + { + base->FIFOWR = data; + handle->useFifo48H = true; + } + handle->transferCount += 3U; + dataSize -= 3U; + } + } + else /* if (handle->dataLength <= 32U) */ + { + base->FIFOWR = *((volatile uint32_t *)(dataAddr)); + dataAddr += sizeof(uint32_t); + handle->transferCount += sizeof(uint32_t); + dataSize -= sizeof(uint32_t); + } + + if (dataSize == 0U) + { + handle->i2sQueue[queueDriverIndex].dataSize = 0U; + /* Actual data buffer sent out, switch to a next one */ + handle->queueDriver = (queueDriverIndex + 1U) % I2S_NUM_BUFFERS; + + /* Notify user */ + if (handle->completionCallback != NULL) + { + handle->completionCallback(base, handle, kStatus_I2S_BufferComplete, handle->userData); + } + + /* Check if the next buffer contains anything to send */ + if (handle->i2sQueue[handle->queueDriver].dataSize == 0U) + { + /* Everything has been written to FIFO */ + handle->state = kI2S_StateTxWaitToWriteDummyData; + break; + } + } + else + { + handle->i2sQueue[queueDriverIndex].dataSize = dataSize; + handle->i2sQueue[queueDriverIndex].data = (uint8_t *)dataAddr; + } + } + } + else if (handle->state == (uint32_t)kI2S_StateTxWaitToWriteDummyData) + { + /* Write dummy data */ + if ((handle->dataLength > 16U) && (handle->dataLength < 25U)) + { + if (handle->useFifo48H) + { + base->FIFOWR48H = 0U; + handle->useFifo48H = false; + } + else + { + base->FIFOWR = 0U; + base->FIFOWR48H = 0U; + } + } + else + { + base->FIFOWR = 0U; + } + + /* Next time invoke this handler when FIFO becomes empty (TX level 0) */ + base->FIFOTRIG &= ~I2S_FIFOTRIG_TXLVL_MASK; + handle->state = (uint32_t)kI2S_StateTxWaitForEmptyFifo; + } + else if (handle->state == (uint32_t)kI2S_StateTxWaitForEmptyFifo) + { + /* FIFO, including additional dummy data, has been emptied now, + * all relevant data should have been output from peripheral */ + + /* Stop transfer */ + I2S_Disable(base); + I2S_DisableInterrupts(base, (uint32_t)kI2S_TxErrorFlag | (uint32_t)kI2S_TxLevelFlag); + base->FIFOCFG |= I2S_FIFOCFG_EMPTYTX_MASK; + + /* Reset state */ + handle->state = (uint32_t)kI2S_StateIdle; + + /* Notify user */ + if (handle->completionCallback != NULL) + { + handle->completionCallback(base, handle, kStatus_I2S_Done, handle->userData); + } + } + else + { + /* Do nothing */ + } + + /* Clear TX level interrupt flag */ + base->FIFOSTAT = I2S_FIFOSTAT_TXLVL(1U); + } +} + +/*! + * brief Invoked from interrupt handler when receive FIFO level decreases. + * + * param base I2S base pointer. + * param handle pointer to handle structure. + */ +void I2S_RxHandleIRQ(I2S_Type *base, i2s_handle_t *handle) +{ + uint32_t intstat = base->FIFOINTSTAT; + uint32_t data; + uint8_t queueDriverIndex = handle->queueDriver; + uint32_t dataAddr = (uint32_t)handle->i2sQueue[queueDriverIndex].data; + uint32_t dataSize = handle->i2sQueue[queueDriverIndex].dataSize; + + if ((intstat & I2S_FIFOINTSTAT_RXERR_MASK) != 0UL) + { + handle->errorCount++; + + /* Clear RX error interrupt flag */ + base->FIFOSTAT = I2S_FIFOSTAT_RXERR(1U); + } + + if ((intstat & I2S_FIFOINTSTAT_RXLVL_MASK) != 0UL) + { + while (((base->FIFOSTAT & I2S_FIFOSTAT_RXNOTEMPTY_MASK) != 0UL) && (dataSize > 0U)) + { + /* Read input data */ + if (handle->dataLength == 4U) + { + data = base->FIFORD; + *((uint8_t *)dataAddr) = (uint8_t)(((data & 0x000F0000U) >> 12U) | (data & 0x0000000FU)); + dataAddr++; + handle->transferCount++; + dataSize--; + } + else if (handle->dataLength <= 8U) + { + data = base->FIFORD; + + if (handle->oneChannel) + { + *((volatile uint8_t *)dataAddr) = (uint8_t)(data & 0xFFU); + dataAddr += sizeof(uint8_t); + handle->transferCount += sizeof(uint8_t); + dataSize -= sizeof(uint8_t); + } + else + { + *((volatile uint16_t *)dataAddr) = (uint16_t)(((data >> 8U) & 0xFF00U) | (data & 0xFFU)); + dataAddr += sizeof(uint16_t); + handle->transferCount += sizeof(uint16_t); + dataSize -= sizeof(uint16_t); + } + } + else if (handle->dataLength <= 16U) + { + data = base->FIFORD; + + if (handle->oneChannel) + { + *((volatile uint16_t *)dataAddr) = (uint16_t)(data & 0xFFFFU); + dataAddr += sizeof(uint16_t); + handle->transferCount += sizeof(uint16_t); + dataSize -= sizeof(uint16_t); + } + else + { + *((volatile uint32_t *)dataAddr) = data; + dataAddr += sizeof(uint32_t); + handle->transferCount += sizeof(uint32_t); + dataSize -= sizeof(uint32_t); + } + } + else if (handle->dataLength <= 24U) + { + if (handle->pack48) + { + if (handle->useFifo48H) + { + data = base->FIFORD48H; + handle->useFifo48H = false; + + *((volatile uint16_t *)dataAddr) = (uint16_t)data; + dataAddr += sizeof(uint16_t); + handle->transferCount += sizeof(uint16_t); + dataSize -= sizeof(uint16_t); + } + else + { + data = base->FIFORD; + handle->useFifo48H = true; + + *((volatile uint32_t *)dataAddr) = data; + dataAddr += sizeof(uint32_t); + handle->transferCount += sizeof(uint32_t); + dataSize -= sizeof(uint32_t); + } + } + else + { + if (handle->useFifo48H) + { + data = base->FIFORD48H; + handle->useFifo48H = false; + } + else + { + data = base->FIFORD; + handle->useFifo48H = true; + } + + *(uint8_t *)(dataAddr++) = (uint8_t)(data & 0xFFU); + *(uint8_t *)(dataAddr++) = (uint8_t)((data >> 8U) & 0xFFU); + *(uint8_t *)(dataAddr++) = (uint8_t)((data >> 16U) & 0xFFU); + handle->transferCount += 3U; + dataSize -= 3U; + } + } + else /* if (handle->dataLength <= 32U) */ + { + data = base->FIFORD; + *((volatile uint32_t *)dataAddr) = data; + dataAddr += sizeof(uint32_t); + handle->transferCount += sizeof(uint32_t); + dataSize -= sizeof(uint32_t); + } + + if (dataSize == 0U) + { + handle->i2sQueue[queueDriverIndex].dataSize = 0U; + /* Actual data buffer filled with input data, switch to a next one */ + handle->queueDriver = (queueDriverIndex + 1U) % I2S_NUM_BUFFERS; + + /* Notify user */ + if (handle->completionCallback != NULL) + { + handle->completionCallback(base, handle, kStatus_I2S_BufferComplete, handle->userData); + } + + if (handle->i2sQueue[handle->queueDriver].dataSize == 0U) + { + /* No other buffer prepared to receive data into */ + + /* Disable I2S operation and interrupts */ + I2S_Disable(base); + I2S_DisableInterrupts(base, (uint32_t)kI2S_RxErrorFlag | (uint32_t)kI2S_RxLevelFlag); + base->FIFOCFG |= I2S_FIFOCFG_EMPTYRX_MASK; + + /* Reset state */ + handle->state = (uint32_t)kI2S_StateIdle; + + /* Notify user */ + if (handle->completionCallback != NULL) + { + handle->completionCallback(base, handle, kStatus_I2S_Done, handle->userData); + } + + /* Clear RX level interrupt flag */ + base->FIFOSTAT = I2S_FIFOSTAT_RXLVL(1U); + + return; + } + } + else + { + handle->i2sQueue[queueDriverIndex].dataSize = dataSize; + handle->i2sQueue[queueDriverIndex].data = (uint8_t *)dataAddr; + } + } + + /* Clear RX level interrupt flag */ + base->FIFOSTAT = I2S_FIFOSTAT_RXLVL(1U); + } +} diff --git a/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_i2s.h b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_i2s.h new file mode 100644 index 0000000000..e0787d6b14 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_i2s.h @@ -0,0 +1,513 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_I2S_H_ +#define _FSL_I2S_H_ + +#include "fsl_device_registers.h" +#include "fsl_common.h" +#include "fsl_flexcomm.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! + * @addtogroup i2s_driver + * @{ + */ + +/*! @file */ + +/*! @name Driver version */ +/*@{*/ + +/*! @brief I2S driver version 2.3.1. */ +#define FSL_I2S_DRIVER_VERSION (MAKE_VERSION(2, 3, 1)) +/*@}*/ + +#ifndef I2S_NUM_BUFFERS + +/*! @brief Number of buffers . */ +#define I2S_NUM_BUFFERS (4U) + +#endif + +/*! @brief _i2s_status I2S status codes. */ +enum +{ + kStatus_I2S_BufferComplete = + MAKE_STATUS(kStatusGroup_I2S, 0), /*!< Transfer from/into a single buffer has completed */ + kStatus_I2S_Done = MAKE_STATUS(kStatusGroup_I2S, 1), /*!< All buffers transfers have completed */ + kStatus_I2S_Busy = + MAKE_STATUS(kStatusGroup_I2S, 2), /*!< Already performing a transfer and cannot queue another buffer */ +}; + +/*! + * @brief I2S flags. + * + * @note These enums are meant to be OR'd together to form a bit mask. + */ +typedef enum _i2s_flags +{ + kI2S_TxErrorFlag = I2S_FIFOINTENSET_TXERR_MASK, /*!< TX error interrupt */ + kI2S_TxLevelFlag = I2S_FIFOINTENSET_TXLVL_MASK, /*!< TX level interrupt */ + kI2S_RxErrorFlag = I2S_FIFOINTENSET_RXERR_MASK, /*!< RX error interrupt */ + kI2S_RxLevelFlag = I2S_FIFOINTENSET_RXLVL_MASK /*!< RX level interrupt */ +} i2s_flags_t; + +/*! @brief Master / slave mode. */ +typedef enum _i2s_master_slave +{ + kI2S_MasterSlaveNormalSlave = 0x0, /*!< Normal slave */ + kI2S_MasterSlaveWsSyncMaster = 0x1, /*!< WS synchronized master */ + kI2S_MasterSlaveExtSckMaster = 0x2, /*!< Master using existing SCK */ + kI2S_MasterSlaveNormalMaster = 0x3 /*!< Normal master */ +} i2s_master_slave_t; + +/*! @brief I2S mode. */ +typedef enum _i2s_mode +{ + kI2S_ModeI2sClassic = 0x0, /*!< I2S classic mode */ + kI2S_ModeDspWs50 = 0x1, /*!< DSP mode, WS having 50% duty cycle */ + kI2S_ModeDspWsShort = 0x2, /*!< DSP mode, WS having one clock long pulse */ + kI2S_ModeDspWsLong = 0x3 /*!< DSP mode, WS having one data slot long pulse */ +} i2s_mode_t; + +/*! @brief _i2s_secondary_channel I2S secondary channel. */ +enum +{ + kI2S_SecondaryChannel1 = 0U, /*!< secondary channel 1 */ + kI2S_SecondaryChannel2 = 1U, /*!< secondary channel 2 */ + kI2S_SecondaryChannel3 = 2U, /*!< secondary channel 3 */ +}; + +/*! @brief I2S configuration structure. */ +typedef struct _i2s_config +{ + i2s_master_slave_t masterSlave; /*!< Master / slave configuration */ + i2s_mode_t mode; /*!< I2S mode */ + bool rightLow; /*!< Right channel data in low portion of FIFO */ + bool leftJust; /*!< Left justify data in FIFO */ +#if (defined(FSL_FEATURE_FLEXCOMM_I2S_HAS_DMIC_INTERCONNECTION) && FSL_FEATURE_FLEXCOMM_I2S_HAS_DMIC_INTERCONNECTION) + bool pdmData; /*!< Data source is the D-Mic subsystem */ +#endif + bool sckPol; /*!< SCK polarity */ + bool wsPol; /*!< WS polarity */ + uint16_t divider; /*!< Flexcomm function clock divider (1 - 4096) */ + bool oneChannel; /*!< true mono, false stereo */ + uint8_t dataLength; /*!< Data length (4 - 32) */ + uint16_t frameLength; /*!< Frame width (4 - 512) */ + uint16_t position; /*!< Data position in the frame */ + uint8_t watermark; /*!< FIFO trigger level */ + bool txEmptyZero; /*!< Transmit zero when buffer becomes empty or last item */ + bool pack48; /*!< Packing format for 48-bit data (false - 24 bit values, true - alternating 32-bit and 16-bit + values) */ +} i2s_config_t; + +/*! @brief Buffer to transfer from or receive audio data into. */ +typedef struct _i2s_transfer +{ + uint8_t *data; /*!< Pointer to data buffer. */ + size_t dataSize; /*!< Buffer size in bytes. */ +} i2s_transfer_t; + +/*! @brief Transactional state of the intialized transfer or receive I2S operation. */ +typedef struct _i2s_handle i2s_handle_t; + +/*! + * @brief Callback function invoked from transactional API + * on completion of a single buffer transfer. + * + * @param base I2S base pointer. + * @param handle pointer to I2S transaction. + * @param completionStatus status of the transaction. + * @param userData optional pointer to user arguments data. + */ +typedef void (*i2s_transfer_callback_t)(I2S_Type *base, + i2s_handle_t *handle, + status_t completionStatus, + void *userData); + +/*! @brief Members not to be accessed / modified outside of the driver. */ +struct _i2s_handle +{ + volatile uint32_t state; /*!< State of transfer */ + i2s_transfer_callback_t completionCallback; /*!< Callback function pointer */ + void *userData; /*!< Application data passed to callback */ + bool oneChannel; /*!< true mono, false stereo */ + uint8_t dataLength; /*!< Data length (4 - 32) */ + bool pack48; /*!< Packing format for 48-bit data (false - 24 bit values, true - alternating 32-bit and 16-bit + values) */ + uint8_t watermark; /*!< FIFO trigger level */ + bool useFifo48H; /*!< When dataLength 17-24: true use FIFOWR48H, false use FIFOWR */ + + volatile i2s_transfer_t i2sQueue[I2S_NUM_BUFFERS]; /*!< Transfer queue storing transfer buffers */ + volatile uint8_t queueUser; /*!< Queue index where user's next transfer will be stored */ + volatile uint8_t queueDriver; /*!< Queue index of buffer actually used by the driver */ + volatile uint32_t errorCount; /*!< Number of buffer underruns/overruns */ + volatile uint32_t transferCount; /*!< Number of bytes transferred */ +}; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Initializes the FLEXCOMM peripheral for I2S transmit functionality. + * + * Ungates the FLEXCOMM clock and configures the module + * for I2S transmission using a configuration structure. + * The configuration structure can be custom filled or set with default values by + * I2S_TxGetDefaultConfig(). + * + * @note This API should be called at the beginning of the application to use + * the I2S driver. + * + * @param base I2S base pointer. + * @param config pointer to I2S configuration structure. + */ +void I2S_TxInit(I2S_Type *base, const i2s_config_t *config); + +/*! + * @brief Initializes the FLEXCOMM peripheral for I2S receive functionality. + * + * Ungates the FLEXCOMM clock and configures the module + * for I2S receive using a configuration structure. + * The configuration structure can be custom filled or set with default values by + * I2S_RxGetDefaultConfig(). + * + * @note This API should be called at the beginning of the application to use + * the I2S driver. + * + * @param base I2S base pointer. + * @param config pointer to I2S configuration structure. + */ +void I2S_RxInit(I2S_Type *base, const i2s_config_t *config); + +/*! + * @brief Sets the I2S Tx configuration structure to default values. + * + * This API initializes the configuration structure for use in I2S_TxInit(). + * The initialized structure can remain unchanged in I2S_TxInit(), or it can be modified + * before calling I2S_TxInit(). + * Example: + @code + i2s_config_t config; + I2S_TxGetDefaultConfig(&config); + @endcode + * + * Default values: + * @code + * config->masterSlave = kI2S_MasterSlaveNormalMaster; + * config->mode = kI2S_ModeI2sClassic; + * config->rightLow = false; + * config->leftJust = false; + * config->pdmData = false; + * config->sckPol = false; + * config->wsPol = false; + * config->divider = 1; + * config->oneChannel = false; + * config->dataLength = 16; + * config->frameLength = 32; + * config->position = 0; + * config->watermark = 4; + * config->txEmptyZero = true; + * config->pack48 = false; + * @endcode + * + * @param config pointer to I2S configuration structure. + */ +void I2S_TxGetDefaultConfig(i2s_config_t *config); + +/*! + * @brief Sets the I2S Rx configuration structure to default values. + * + * This API initializes the configuration structure for use in I2S_RxInit(). + * The initialized structure can remain unchanged in I2S_RxInit(), or it can be modified + * before calling I2S_RxInit(). + * Example: + @code + i2s_config_t config; + I2S_RxGetDefaultConfig(&config); + @endcode + * + * Default values: + * @code + * config->masterSlave = kI2S_MasterSlaveNormalSlave; + * config->mode = kI2S_ModeI2sClassic; + * config->rightLow = false; + * config->leftJust = false; + * config->pdmData = false; + * config->sckPol = false; + * config->wsPol = false; + * config->divider = 1; + * config->oneChannel = false; + * config->dataLength = 16; + * config->frameLength = 32; + * config->position = 0; + * config->watermark = 4; + * config->txEmptyZero = false; + * config->pack48 = false; + * @endcode + * + * @param config pointer to I2S configuration structure. + */ +void I2S_RxGetDefaultConfig(i2s_config_t *config); + +/*! + * @brief De-initializes the I2S peripheral. + * + * This API gates the FLEXCOMM clock. The I2S module can't operate unless I2S_TxInit + * or I2S_RxInit is called to enable the clock. + * + * @param base I2S base pointer. + */ +void I2S_Deinit(I2S_Type *base); + +/*! + * @brief Transmitter/Receiver bit clock rate configurations. + * + * @param base SAI base pointer. + * @param sourceClockHz bit clock source frequency. + * @param sampleRate audio data sample rate. + * @param bitWidth audio data bitWidth. + * @param channelNumbers audio channel numbers. + */ +void I2S_SetBitClockRate( + I2S_Type *base, uint32_t sourceClockHz, uint32_t sampleRate, uint32_t bitWidth, uint32_t channelNumbers); + +/*! @} */ + +/*! + * @name Non-blocking API + * @{ + */ + +/*! + * @brief Initializes handle for transfer of audio data. + * + * @param base I2S base pointer. + * @param handle pointer to handle structure. + * @param callback function to be called back when transfer is done or fails. + * @param userData pointer to data passed to callback. + */ +void I2S_TxTransferCreateHandle(I2S_Type *base, i2s_handle_t *handle, i2s_transfer_callback_t callback, void *userData); + +/*! + * @brief Begins or queue sending of the given data. + * + * @param base I2S base pointer. + * @param handle pointer to handle structure. + * @param transfer data buffer. + * + * @retval kStatus_Success + * @retval kStatus_I2S_Busy if all queue slots are occupied with unsent buffers. + */ +status_t I2S_TxTransferNonBlocking(I2S_Type *base, i2s_handle_t *handle, i2s_transfer_t transfer); + +/*! + * @brief Aborts sending of data. + * + * @param base I2S base pointer. + * @param handle pointer to handle structure. + */ +void I2S_TxTransferAbort(I2S_Type *base, i2s_handle_t *handle); + +/*! + * @brief Initializes handle for reception of audio data. + * + * @param base I2S base pointer. + * @param handle pointer to handle structure. + * @param callback function to be called back when transfer is done or fails. + * @param userData pointer to data passed to callback. + */ +void I2S_RxTransferCreateHandle(I2S_Type *base, i2s_handle_t *handle, i2s_transfer_callback_t callback, void *userData); + +/*! + * @brief Begins or queue reception of data into given buffer. + * + * @param base I2S base pointer. + * @param handle pointer to handle structure. + * @param transfer data buffer. + * + * @retval kStatus_Success + * @retval kStatus_I2S_Busy if all queue slots are occupied with buffers which are not full. + */ +status_t I2S_RxTransferNonBlocking(I2S_Type *base, i2s_handle_t *handle, i2s_transfer_t transfer); + +/*! + * @brief Aborts receiving of data. + * + * @param base I2S base pointer. + * @param handle pointer to handle structure. + */ +void I2S_RxTransferAbort(I2S_Type *base, i2s_handle_t *handle); + +/*! + * @brief Returns number of bytes transferred so far. + * + * @param base I2S base pointer. + * @param handle pointer to handle structure. + * @param[out] count number of bytes transferred so far by the non-blocking transaction. + * + * @retval kStatus_Success + * @retval kStatus_NoTransferInProgress there is no non-blocking transaction currently in progress. + */ +status_t I2S_TransferGetCount(I2S_Type *base, i2s_handle_t *handle, size_t *count); + +/*! + * @brief Returns number of buffer underruns or overruns. + * + * @param base I2S base pointer. + * @param handle pointer to handle structure. + * @param[out] count number of transmit errors encountered so far by the non-blocking transaction. + * + * @retval kStatus_Success + * @retval kStatus_NoTransferInProgress there is no non-blocking transaction currently in progress. + */ +status_t I2S_TransferGetErrorCount(I2S_Type *base, i2s_handle_t *handle, size_t *count); + +/*! @} */ + +/*! + * @name Enable / disable + * @{ + */ + +/*! + * @brief Enables I2S operation. + * + * @param base I2S base pointer. + */ +static inline void I2S_Enable(I2S_Type *base) +{ + base->CFG1 |= I2S_CFG1_MAINENABLE(1U); +} + +#if (defined(FSL_FEATURE_I2S_SUPPORT_SECONDARY_CHANNEL) && FSL_FEATURE_I2S_SUPPORT_SECONDARY_CHANNEL) +/*! + * @brief Enables I2S secondary channel. + * + * @param base I2S base pointer. + * @param channel seondary channel channel number, reference _i2s_secondary_channel. + * @param oneChannel true is treated as single channel, functionality left channel for this pair. + * @param position define the location within the frame of the data, should not bigger than 0x1FFU. + */ +void I2S_EnableSecondaryChannel(I2S_Type *base, uint32_t channel, bool oneChannel, uint32_t position); + +/*! + * @brief Disables I2S secondary channel. + * + * @param base I2S base pointer. + * @param channel seondary channel channel number, reference _i2s_secondary_channel. + */ +static inline void I2S_DisableSecondaryChannel(I2S_Type *base, uint32_t channel) +{ +#if defined FSL_FEATURE_FLEXCOMM_INSTANCE_I2S_SUPPORT_SECONDARY_CHANNELn + assert(FSL_FEATURE_FLEXCOMM_INSTANCE_I2S_SUPPORT_SECONDARY_CHANNELn((FLEXCOMM_Type *)(uint32_t)base) == 1); +#endif + + base->SECCHANNEL[channel].PCFG1 &= ~I2S_CFG1_MAINENABLE_MASK; +} +#endif +/*! + * @brief Disables I2S operation. + * + * @param base I2S base pointer. + */ +static inline void I2S_Disable(I2S_Type *base) +{ + base->CFG1 &= (~I2S_CFG1_MAINENABLE(1U)); +} + +/*! @} */ + +/*! + * @name Interrupts + * @{ + */ + +/*! + * @brief Enables I2S FIFO interrupts. + * + * @param base I2S base pointer. + * @param interruptMask bit mask of interrupts to enable. See #i2s_flags_t for the set + * of constants that should be OR'd together to form the bit mask. + */ +static inline void I2S_EnableInterrupts(I2S_Type *base, uint32_t interruptMask) +{ + base->FIFOINTENSET = interruptMask; +} + +/*! + * @brief Disables I2S FIFO interrupts. + * + * @param base I2S base pointer. + * @param interruptMask bit mask of interrupts to enable. See #i2s_flags_t for the set + * of constants that should be OR'd together to form the bit mask. + */ +static inline void I2S_DisableInterrupts(I2S_Type *base, uint32_t interruptMask) +{ + base->FIFOINTENCLR = interruptMask; +} + +/*! + * @brief Returns the set of currently enabled I2S FIFO interrupts. + * + * @param base I2S base pointer. + * + * @return A bitmask composed of #i2s_flags_t enumerators OR'd together + * to indicate the set of enabled interrupts. + */ +static inline uint32_t I2S_GetEnabledInterrupts(I2S_Type *base) +{ + return base->FIFOINTENSET; +} + +/*! + * @brief Flush the valid data in TX fifo. + * + * @param base I2S base pointer. + * @return kStatus_Fail empty TX fifo failed, kStatus_Success empty tx fifo success. + */ +status_t I2S_EmptyTxFifo(I2S_Type *base); + +/*! + * @brief Invoked from interrupt handler when transmit FIFO level decreases. + * + * @param base I2S base pointer. + * @param handle pointer to handle structure. + */ +void I2S_TxHandleIRQ(I2S_Type *base, i2s_handle_t *handle); + +/*! + * @brief Invoked from interrupt handler when receive FIFO level decreases. + * + * @param base I2S base pointer. + * @param handle pointer to handle structure. + */ +void I2S_RxHandleIRQ(I2S_Type *base, i2s_handle_t *handle); + +/*! @} */ + +/*! @} */ + +#if defined(__cplusplus) +} +#endif + +#endif /* _FSL_I2S_H_ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_i2s_dma.c b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_i2s_dma.c new file mode 100644 index 0000000000..84f25b30e9 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_i2s_dma.c @@ -0,0 +1,848 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_dma.h" +#include "fsl_i2s_dma.h" +#include "fsl_flexcomm.h" +#include + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.flexcomm_i2s_dma" +#endif + +#define DMA_MAX_TRANSFER_BYTES (DMA_MAX_TRANSFER_COUNT * sizeof(uint32_t)) +#define DMA_DESCRIPTORS (2U) + +/*i2sQueue[handle->queueUser].dataSize != 0UL) + { + /* Previously prepared buffers not processed yet, reject request */ + return kStatus_I2S_Busy; + } + + /* Enqueue data */ + privateHandle->descriptorQueue[handle->queueUser].data = transfer.data; + privateHandle->descriptorQueue[handle->queueUser].dataSize = transfer.dataSize; + handle->i2sQueue[handle->queueUser].data = transfer.data; + handle->i2sQueue[handle->queueUser].dataSize = transfer.dataSize; + handle->queueUser = (handle->queueUser + 1U) % I2S_NUM_BUFFERS; + + return kStatus_Success; +} + +static uint32_t I2S_GetInstance(I2S_Type *base) +{ + uint32_t i; + + for (i = 0U; i < ARRAY_SIZE(s_I2sBaseAddrs); i++) + { + if ((uint32_t)base == s_I2sBaseAddrs[i]) + { + return i; + } + } + + assert(false); + return 0U; +} + +static inline void I2S_DisableDMAInterrupts(i2s_dma_handle_t *handle) +{ + DMA_DisableChannelInterrupts(handle->dmaHandle->base, handle->dmaHandle->channel); +} + +static inline void I2S_EnableDMAInterrupts(i2s_dma_handle_t *handle) +{ + if (handle->state != (uint32_t)kI2S_DmaStateIdle) + { + DMA_EnableChannelInterrupts(handle->dmaHandle->base, handle->dmaHandle->channel); + } +} + +/*! + * brief Initializes handle for transfer of audio data. + * + * param base I2S base pointer. + * param handle pointer to handle structure. + * param dmaHandle pointer to dma handle structure. + * param callback function to be called back when transfer is done or fails. + * param userData pointer to data passed to callback. + */ +void I2S_TxTransferCreateHandleDMA(I2S_Type *base, + i2s_dma_handle_t *handle, + dma_handle_t *dmaHandle, + i2s_dma_transfer_callback_t callback, + void *userData) +{ + assert(handle != NULL); + assert(dmaHandle != NULL); + + uint32_t instance = I2S_GetInstance(base); + i2s_dma_private_handle_t *privateHandle = &(s_DmaPrivateHandle[instance]); + + (void)memset(handle, 0, sizeof(*handle)); + handle->state = (uint32_t)kI2S_DmaStateIdle; + handle->dmaHandle = dmaHandle; + handle->completionCallback = callback; + handle->userData = userData; + + handle->bytesPerFrame = (uint8_t)((((base->CFG1 & I2S_CFG1_DATALEN_MASK) >> I2S_CFG1_DATALEN_SHIFT) + 1U) / 8U); + /* if one channel is disabled, bytesPerFrame should be 4U, user should pay attention that when data length is + * shorter than 16, the data format: left data put in 0-15 bit and right data should put in 16-31 + */ + if (((base->CFG1 & I2S_CFG1_ONECHANNEL_MASK) == 0U)) + { + handle->bytesPerFrame = 4U; + } + /* since DMA do not support 24bit transfer width, use 32bit instead */ + if (handle->bytesPerFrame == 3U) + { + handle->bytesPerFrame = 4U; + } + + (void)memset(privateHandle, 0, sizeof(*privateHandle)); + privateHandle->base = base; + privateHandle->handle = handle; + + DMA_SetCallback(dmaHandle, I2S_DMACallback, privateHandle); +} + +/*! + * brief Begins or queue sending of the given data. + * + * param base I2S base pointer. + * param handle pointer to handle structure. + * param transfer data buffer. + * + * retval kStatus_Success + * retval kStatus_I2S_Busy if all queue slots are occupied with unsent buffers. + */ +status_t I2S_TxTransferSendDMA(I2S_Type *base, i2s_dma_handle_t *handle, i2s_transfer_t transfer) +{ + status_t status; + + I2S_DisableDMAInterrupts(handle); + + /* Enqueue transfer buffer */ + status = I2S_EnqueueUserBuffer(base, handle, transfer); + if (status != kStatus_Success) + { + I2S_EnableDMAInterrupts(handle); + return status; + } + + /* Initialize DMA transfer */ + if (handle->state == (uint32_t)kI2S_DmaStateIdle) + { + handle->state = (uint32_t)kI2S_DmaStateTx; + status = I2S_StartTransferDMA(base, handle); + if (status != kStatus_Success) + { + I2S_EnableDMAInterrupts(handle); + return status; + } + } + + I2S_AddTransferDMA(base, handle); + I2S_EnableDMAInterrupts(handle); + + return kStatus_Success; +} + +/*! + * brief Aborts transfer of data. + * + * param base I2S base pointer. + * param handle pointer to handle structure. + */ +void I2S_TransferAbortDMA(I2S_Type *base, i2s_dma_handle_t *handle) +{ + assert(handle != NULL); + assert(handle->dmaHandle != NULL); + + uint32_t instance = I2S_GetInstance(base); + i2s_dma_private_handle_t *privateHandle = &(s_DmaPrivateHandle[instance]); + + I2S_DisableDMAInterrupts(handle); + + /* Abort operation */ + DMA_AbortTransfer(handle->dmaHandle); + + if (handle->state == (uint32_t)kI2S_DmaStateTx) + { + /* Disable TX */ + I2S_TxEnableDMA(base, false); + } + else + { + /* Disable RX */ + I2S_RxEnableDMA(base, false); + } + + I2S_Disable(base); + + /* Reset state */ + handle->state = (uint32_t)kI2S_DmaStateIdle; + + /* Clear transfer queue */ + (void)memset((void *)&(handle->i2sQueue), 0, sizeof(handle->i2sQueue)); + handle->queueDriver = 0U; + handle->queueUser = 0U; + + /* Clear internal state */ + (void)memset((void *)&(privateHandle->descriptorQueue), 0, sizeof(privateHandle->descriptorQueue)); + (void)memset((void *)&(privateHandle->enqueuedBytes), 0, sizeof(privateHandle->enqueuedBytes)); + privateHandle->enqueuedBytesStart = 0U; + privateHandle->enqueuedBytesEnd = 0U; + privateHandle->dmaDescriptorsUsed = 0U; + privateHandle->descriptor = 0U; + privateHandle->queueDescriptor = 0U; + privateHandle->intA = false; +} + +/*! + * brief Initializes handle for reception of audio data. + * + * param base I2S base pointer. + * param handle pointer to handle structure. + * param dmaHandle pointer to dma handle structure. + * param callback function to be called back when transfer is done or fails. + * param userData pointer to data passed to callback. + */ +void I2S_RxTransferCreateHandleDMA(I2S_Type *base, + i2s_dma_handle_t *handle, + dma_handle_t *dmaHandle, + i2s_dma_transfer_callback_t callback, + void *userData) +{ + I2S_TxTransferCreateHandleDMA(base, handle, dmaHandle, callback, userData); +} + +/*! + * brief Begins or queue reception of data into given buffer. + * + * param base I2S base pointer. + * param handle pointer to handle structure. + * param transfer data buffer. + * + * retval kStatus_Success + * retval kStatus_I2S_Busy if all queue slots are occupied with buffers + * which are not full. + */ +status_t I2S_RxTransferReceiveDMA(I2S_Type *base, i2s_dma_handle_t *handle, i2s_transfer_t transfer) +{ + status_t status; + + I2S_DisableDMAInterrupts(handle); + + /* Enqueue transfer buffer */ + status = I2S_EnqueueUserBuffer(base, handle, transfer); + if (status != kStatus_Success) + { + I2S_EnableDMAInterrupts(handle); + return status; + } + + /* Initialize DMA transfer */ + if (handle->state == (uint32_t)kI2S_DmaStateIdle) + { + handle->state = (uint32_t)kI2S_DmaStateRx; + status = I2S_StartTransferDMA(base, handle); + if (status != kStatus_Success) + { + I2S_EnableDMAInterrupts(handle); + return status; + } + } + + I2S_AddTransferDMA(base, handle); + I2S_EnableDMAInterrupts(handle); + + return kStatus_Success; +} + +static void I2S_TxEnableDMA(I2S_Type *base, bool enable) +{ + if (enable) + { + base->FIFOCFG |= I2S_FIFOCFG_DMATX_MASK; + } + else + { + base->FIFOCFG &= (~I2S_FIFOCFG_DMATX_MASK); + base->FIFOCFG |= I2S_FIFOCFG_EMPTYTX_MASK; + } +} + +static void I2S_RxEnableDMA(I2S_Type *base, bool enable) +{ + if (enable) + { + base->FIFOCFG |= I2S_FIFOCFG_DMARX_MASK; + } + else + { + base->FIFOCFG &= (~I2S_FIFOCFG_DMARX_MASK); + base->FIFOCFG |= I2S_FIFOCFG_EMPTYRX_MASK; + } +} + +static uint16_t I2S_GetTransferBytes(volatile i2s_transfer_t *transfer) +{ + assert(transfer != NULL); + + uint16_t transferBytes; + + if (transfer->dataSize >= (2UL * DMA_MAX_TRANSFER_BYTES)) + { + transferBytes = DMA_MAX_TRANSFER_BYTES; + } + else if (transfer->dataSize > DMA_MAX_TRANSFER_BYTES) + { + transferBytes = (uint16_t)(transfer->dataSize / 2U); + if ((transferBytes % 4U) != 0U) + { + transferBytes -= (transferBytes % 4U); + } + } + else + { + transferBytes = (uint16_t)transfer->dataSize; + } + + return transferBytes; +} + +/*! + * brief Install DMA descriptor memory for loop transfer only. + * + * This function used to register DMA descriptor memory for the i2s loop dma transfer. + * + * It must be callbed before I2S_TransferSendLoopDMA/I2S_TransferReceiveLoopDMA and after + * I2S_RxTransferCreateHandleDMA/I2S_TxTransferCreateHandleDMA. + * + * User should be take care about the address of DMA descriptor pool which required align with 16BYTE at least. + * + * param handle Pointer to i2s DMA transfer handle. + * param dmaDescriptorAddr DMA descriptor start address. + * param dmaDescriptorNum DMA descriptor number. + */ +void I2S_TransferInstallLoopDMADescriptorMemory(i2s_dma_handle_t *handle, + void *dmaDescriptorAddr, + size_t dmaDescriptorNum) +{ + assert(handle != NULL); + assert((((uint32_t)(uint32_t *)dmaDescriptorAddr) & ((uint32_t)FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE - 1UL)) == + 0UL); + + handle->i2sLoopDMADescriptor = (dma_descriptor_t *)dmaDescriptorAddr; + handle->i2sLoopDMADescriptorNum = dmaDescriptorNum; +} + +static status_t I2S_TransferLoopDMA(I2S_Type *base, + i2s_dma_handle_t *handle, + i2s_transfer_t *xfer, + uint32_t loopTransferCount) +{ + assert(handle != NULL); + assert(handle->dmaHandle != NULL); + assert(xfer != NULL); + + uint32_t *srcAddr = NULL, *destAddr = NULL, srcInc = 4UL, destInc = 4UL; + i2s_transfer_t *currentTransfer = xfer; + bool intA = true; + + if (handle->i2sLoopDMADescriptor == NULL) + { + return kStatus_InvalidArgument; + } + + if (handle->state == (uint32_t)kI2S_DmaStateBusyLoopTransfer) + { + return kStatus_I2S_Busy; + } + + for (uint32_t i = 0U; i < loopTransferCount; i++) + { + currentTransfer = &xfer[i]; + + if ((currentTransfer->data == NULL) || (currentTransfer->dataSize == 0U) || + (i >= handle->i2sLoopDMADescriptorNum) || + (currentTransfer->dataSize / handle->bytesPerFrame > DMA_MAX_TRANSFER_COUNT)) + { + return kStatus_InvalidArgument; + } + + if (handle->state == (uint32_t)kI2S_DmaStateTx) + { + srcAddr = (uint32_t *)(uint32_t)currentTransfer->data; + destAddr = (uint32_t *)(uint32_t)(&(base->FIFOWR)); + srcInc = 1U; + destInc = 0UL; + } + else + { + srcAddr = (uint32_t *)(uint32_t)(&(base->FIFORD)); + destAddr = (uint32_t *)(uint32_t)currentTransfer->data; + srcInc = 0U; + destInc = 1UL; + } + + intA = intA == true ? false : true; + + if (i == (loopTransferCount - 1U)) + { + /* set up linked descriptor */ + DMA_SetupDescriptor(&handle->i2sLoopDMADescriptor[i], + DMA_CHANNEL_XFER(1UL, 0UL, intA, !intA, handle->bytesPerFrame, srcInc, destInc, + currentTransfer->dataSize), + srcAddr, destAddr, &handle->i2sLoopDMADescriptor[0U]); + } + else + { + /* set up linked descriptor */ + DMA_SetupDescriptor(&handle->i2sLoopDMADescriptor[i], + DMA_CHANNEL_XFER(1UL, 0UL, intA, !intA, handle->bytesPerFrame, srcInc, destInc, + currentTransfer->dataSize), + srcAddr, destAddr, &handle->i2sLoopDMADescriptor[i + 1U]); + } + } + + /* transferSize make sense to non link transfer only */ + if (handle->state == (uint32_t)kI2S_DmaStateTx) + { + srcAddr = (uint32_t *)(uint32_t)xfer->data; + destAddr = (uint32_t *)(uint32_t)(&(base->FIFOWR)); + srcInc = 1U; + destInc = 0UL; + } + else + { + srcAddr = (uint32_t *)(uint32_t)(&(base->FIFORD)); + destAddr = (uint32_t *)(uint32_t)xfer->data; + srcInc = 0U; + destInc = 1UL; + } + + DMA_SubmitChannelTransferParameter( + handle->dmaHandle, + DMA_CHANNEL_XFER(1UL, 0UL, 0UL, 1UL, handle->bytesPerFrame, srcInc, destInc, (uint32_t)xfer->dataSize), srcAddr, + destAddr, (void *)&handle->i2sLoopDMADescriptor[1U]); + + /* Submit and start initial DMA transfer */ + if (handle->state == (uint32_t)kI2S_DmaStateTx) + { + I2S_TxEnableDMA(base, true); + } + else + { + I2S_RxEnableDMA(base, true); + } + DMA_EnableChannelPeriphRq(handle->dmaHandle->base, handle->dmaHandle->channel); + /* start transfer */ + DMA_StartTransfer(handle->dmaHandle); + I2S_Enable(base); + + handle->state = (uint32_t)kI2S_DmaStateBusyLoopTransfer; + + return kStatus_Success; +} + +/*! + * brief Send loop transfer data using DMA. + * + * This function receives data using DMA. This is a non-blocking function, which returns + * right away. When all data is received, the receive callback function is called. + * + * This function support loop transfer, such as A->B->...->A, the loop transfer chain + * will be converted into a chain of descriptor and submit to dma. + * Application must be aware of that the more counts of the loop transfer, then more DMA descriptor memory required, + * user can use function I2S_InstallDMADescriptorMemory to register the dma descriptor memory. + * + * As the DMA support maximum 1024 transfer count, so application must be aware of that this transfer function support + * maximum 1024 samples in each transfer, otherwise assert error or error status will be returned. Once the loop + * transfer start, application can use function I2S_TransferAbortDMA to stop the loop transfer. + * + * param base I2S peripheral base address. + * param handle Pointer to usart_dma_handle_t structure. + * param xfer I2S DMA transfer structure. See #i2s_transfer_t. + * param i2s_channel I2S start channel number + * retval kStatus_Success + */ +status_t I2S_TransferSendLoopDMA(I2S_Type *base, + i2s_dma_handle_t *handle, + i2s_transfer_t *xfer, + uint32_t loopTransferCount) +{ + assert(handle != NULL); + assert(handle->i2sLoopDMADescriptor != NULL); + + handle->state = (uint32_t)kI2S_DmaStateTx; + + return I2S_TransferLoopDMA(base, handle, xfer, loopTransferCount); +} + +/*! + * brief Receive loop transfer data using DMA. + * + * This function receives data using DMA. This is a non-blocking function, which returns + * right away. When all data is received, the receive callback function is called. + * + * This function support loop transfer, such as A->B->...->A, the loop transfer chain + * will be converted into a chain of descriptor and submit to dma. + * Application must be aware of that the more counts of the loop transfer, then more DMA descriptor memory required, + * user can use function I2S_InstallDMADescriptorMemory to register the dma descriptor memory. + * + * As the DMA support maximum 1024 transfer count, so application must be aware of that this transfer function support + * maximum 1024 samples in each transfer, otherwise assert error or error status will be returned. Once the loop + * transfer start, application can use function I2S_TransferAbortDMA to stop the loop transfer. + * + * param base I2S peripheral base address. + * param handle Pointer to usart_dma_handle_t structure. + * param xfer I2S DMA transfer structure. See #i2s_transfer_t. + * param i2s_channel I2S start channel number + * retval kStatus_Success + */ +status_t I2S_TransferReceiveLoopDMA(I2S_Type *base, + i2s_dma_handle_t *handle, + i2s_transfer_t *xfer, + uint32_t loopTransferCount) +{ + assert(handle != NULL); + assert(handle->i2sLoopDMADescriptor != NULL); + + handle->state = (uint32_t)kI2S_DmaStateRx; + + return I2S_TransferLoopDMA(base, handle, xfer, loopTransferCount); +} + +static status_t I2S_StartTransferDMA(I2S_Type *base, i2s_dma_handle_t *handle) +{ + uint32_t instance = I2S_GetInstance(base); + i2s_dma_private_handle_t *privateHandle = &(s_DmaPrivateHandle[instance]); + volatile i2s_transfer_t *transfer = &(privateHandle->descriptorQueue[privateHandle->queueDescriptor]); + uint16_t transferBytes = I2S_GetTransferBytes(transfer); + uint32_t i = 0U; + uint32_t xferConfig = 0U; + uint32_t *srcAddr = NULL, *destAddr = NULL, srcInc = 4UL, destInc = 4UL; + + if (handle->state == (uint32_t)kI2S_DmaStateTx) + { + srcAddr = (uint32_t *)(uint32_t)transfer->data; + destAddr = (uint32_t *)(uint32_t)(&(base->FIFOWR)); + srcInc = 1U; + destInc = 0UL; + } + else + { + srcAddr = (uint32_t *)(uint32_t)(&(base->FIFORD)); + destAddr = (uint32_t *)(uint32_t)transfer->data; + srcInc = 0U; + destInc = 1UL; + } + /* Initial descriptor is stored in another place in memory, but treat it as another descriptor for simplicity */ + privateHandle->dmaDescriptorsUsed = 1U; + privateHandle->intA = false; + + /* submit transfer parameter directly */ + xferConfig = DMA_CHANNEL_XFER(1UL, 0UL, 0UL, 1UL, handle->bytesPerFrame, srcInc, destInc, (uint32_t)transferBytes); + + DMA_SubmitChannelTransferParameter(handle->dmaHandle, xferConfig, srcAddr, destAddr, + (void *)&(s_DmaDescriptors[(instance * DMA_DESCRIPTORS) + 0U])); + + privateHandle->enqueuedBytes[privateHandle->enqueuedBytesEnd] = transferBytes; + privateHandle->enqueuedBytesEnd = (privateHandle->enqueuedBytesEnd + 1U) % DMA_DESCRIPTORS; + + transfer->dataSize -= transferBytes; + transfer->data = (uint8_t *)((uint32_t)transfer->data + transferBytes); + + if (transfer->dataSize == 0U) + { + transfer->data = NULL; + privateHandle->queueDescriptor = (privateHandle->queueDescriptor + 1U) % I2S_NUM_BUFFERS; + } + + /* Link the DMA descriptors for the case when no additional transfer is queued before the initial one finishes + * The configuration for the DMA dummy descriptor make no sense to tx or rx transfer, since it will be overwritten + * when another transfer request comes before the previous finished. + * To make sure the audio data transfer continuously, application must request another transfer by call + * I2S_RxTransferReceiveDMA or I2S_TxTransferSendDMA before previous transfer finished. + */ + for (i = 0; i < DMA_DESCRIPTORS; i++) + { + /* DMA_CHANNEL_XFER(1UL, 0UL, 0UL, 0UL, sizeof(uint32_t), 0U, 0U, 8U) = 0x10203UL */ + DMA_SetupDescriptor( + &(s_DmaDescriptors[(instance * DMA_DESCRIPTORS) + i]), 0x10203UL, + ((handle->state == (uint32_t)kI2S_DmaStateTx) ? &s_DummyBufferTx : (uint32_t *)(uint32_t)(&(base->FIFORD))), + ((handle->state == (uint32_t)kI2S_DmaStateTx) ? (uint32_t *)(uint32_t)(&(base->FIFOWR)) : &s_DummyBufferRx), + &(s_DmaDescriptors[(instance * DMA_DESCRIPTORS) + ((i + 1U) % DMA_DESCRIPTORS)])); + } + + /* Submit and start initial DMA transfer */ + if (handle->state == (uint32_t)kI2S_DmaStateTx) + { + I2S_TxEnableDMA(base, true); + } + else + { + I2S_RxEnableDMA(base, true); + } + /* enable I2S peripheral request and put the channel into triggered status */ + DMA_EnableChannelPeriphRq(handle->dmaHandle->base, handle->dmaHandle->channel); + DMA_StartTransfer(handle->dmaHandle); + + I2S_Enable(base); + + return kStatus_Success; +} + +static void I2S_AddTransferDMA(I2S_Type *base, i2s_dma_handle_t *handle) +{ + volatile i2s_transfer_t *transfer; + uint16_t transferBytes; + uint32_t instance; + i2s_dma_private_handle_t *privateHandle; + dma_descriptor_t *descriptor; + dma_descriptor_t *nextDescriptor; + uint32_t xferConfig = 0U; + bool intA = false; + uint32_t *srcAddr = NULL, *destAddr = NULL, srcInc = 4UL, destInc = 4UL; + + instance = I2S_GetInstance(base); + privateHandle = &(s_DmaPrivateHandle[instance]); + + while (privateHandle->dmaDescriptorsUsed < DMA_DESCRIPTORS) + { + transfer = &(privateHandle->descriptorQueue[privateHandle->queueDescriptor]); + intA = privateHandle->intA; + if (transfer->dataSize == 0U) + { + /* Nothing to be added */ + return; + } + + if (handle->state == (uint32_t)kI2S_DmaStateTx) + { + srcAddr = (uint32_t *)(uint32_t)transfer->data; + destAddr = (uint32_t *)(uint32_t)(&(base->FIFOWR)); + srcInc = 1U; + destInc = 0UL; + } + else + { + srcAddr = (uint32_t *)(uint32_t)(&(base->FIFORD)); + destAddr = (uint32_t *)(uint32_t)transfer->data; + srcInc = 0U; + destInc = 1UL; + } + + /* Determine currently configured descriptor and the other which it will link to */ + descriptor = &(s_DmaDescriptors[(instance * DMA_DESCRIPTORS) + privateHandle->descriptor]); + privateHandle->descriptor = (privateHandle->descriptor + 1U) % DMA_DESCRIPTORS; + nextDescriptor = &(s_DmaDescriptors[(instance * DMA_DESCRIPTORS) + privateHandle->descriptor]); + + transferBytes = I2S_GetTransferBytes(transfer); + privateHandle->enqueuedBytes[privateHandle->enqueuedBytesEnd] = transferBytes; + privateHandle->enqueuedBytesEnd = (privateHandle->enqueuedBytesEnd + 1U) % DMA_DESCRIPTORS; + + xferConfig = + DMA_CHANNEL_XFER(1UL, 0UL, !intA, intA, handle->bytesPerFrame, srcInc, destInc, (uint32_t)transferBytes); + + DMA_SetupDescriptor(descriptor, xferConfig, srcAddr, destAddr, nextDescriptor); + + /* Advance internal state */ + privateHandle->dmaDescriptorsUsed++; + privateHandle->intA = !privateHandle->intA; + + transfer->dataSize -= transferBytes; + transfer->data += transferBytes; + if (transfer->dataSize == 0U) + { + transfer->data = NULL; + privateHandle->queueDescriptor = (privateHandle->queueDescriptor + 1U) % I2S_NUM_BUFFERS; + } + } +} + +/*! + * brief Invoked from DMA interrupt handler. + * + * param handle pointer to DMA handle structure. + * param userData argument for user callback. + * param transferDone if transfer was done. + * param tcds + */ +void I2S_DMACallback(dma_handle_t *handle, void *userData, bool transferDone, uint32_t tcds) +{ + i2s_dma_private_handle_t *privateHandle = (i2s_dma_private_handle_t *)userData; + i2s_dma_handle_t *i2sHandle = privateHandle->handle; + I2S_Type *base = privateHandle->base; + uint8_t queueDriverIndex = i2sHandle->queueDriver; + uint32_t enqueueBytes = privateHandle->enqueuedBytes[privateHandle->enqueuedBytesStart]; + uint32_t queueDataAddr = (uint32_t)i2sHandle->i2sQueue[queueDriverIndex].data; + + if ((!transferDone) || (i2sHandle->state == (uint32_t)kI2S_DmaStateIdle)) + { + return; + } + + if (privateHandle->dmaDescriptorsUsed > 0U) + { + /* Finished descriptor, decrease amount of data to be processed */ + + i2sHandle->i2sQueue[queueDriverIndex].dataSize -= enqueueBytes; + i2sHandle->i2sQueue[queueDriverIndex].data = (uint8_t *)(queueDataAddr + enqueueBytes); + privateHandle->enqueuedBytes[privateHandle->enqueuedBytesStart] = 0U; + privateHandle->enqueuedBytesStart = (privateHandle->enqueuedBytesStart + 1U) % DMA_DESCRIPTORS; + privateHandle->dmaDescriptorsUsed--; + } + + if (i2sHandle->i2sQueue[queueDriverIndex].dataSize == 0U) + { + /* Entire user buffer sent or received - advance to next one */ + i2sHandle->i2sQueue[queueDriverIndex].data = NULL; + i2sHandle->queueDriver = (queueDriverIndex + 1U) % I2S_NUM_BUFFERS; + /* Notify user about buffer completion */ + if (i2sHandle->completionCallback != NULL) + { + (i2sHandle->completionCallback)(base, i2sHandle, kStatus_I2S_BufferComplete, i2sHandle->userData); + } + } + + if (i2sHandle->state != (uint32_t)kI2S_DmaStateBusyLoopTransfer) + { + /* check next buffer queue is avaliable or not */ + if (i2sHandle->i2sQueue[i2sHandle->queueDriver].dataSize == 0U) + { + if (i2sHandle->state == (uint32_t)kI2S_DmaStateTx) + { + (void)I2S_EmptyTxFifo(base); + } + /* All user buffers processed */ + I2S_TransferAbortDMA(base, i2sHandle); + } + else + { + /* Enqueue another user buffer to DMA if it could not be done when in I2S_Rx/TxTransferSendDMA */ + I2S_AddTransferDMA(base, i2sHandle); + } + } +} diff --git a/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_i2s_dma.h b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_i2s_dma.h new file mode 100644 index 0000000000..ec63472653 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_i2s_dma.h @@ -0,0 +1,235 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_I2S_DMA_H_ +#define _FSL_I2S_DMA_H_ + +#include "fsl_device_registers.h" +#include "fsl_common.h" +#include "fsl_flexcomm.h" + +#include "fsl_dma.h" +#include "fsl_i2s.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! + * @addtogroup i2s_dma_driver + * @{ + */ + +/*! @name Driver version */ +/*@{*/ +/*! @brief I2S DMA driver version 2.3.1. */ +#define FSL_I2S_DMA_DRIVER_VERSION (MAKE_VERSION(2, 3, 1)) +/*@}*/ + +/*! @brief Members not to be accessed / modified outside of the driver. */ +typedef struct _i2s_dma_handle i2s_dma_handle_t; + +/*! + * @brief Callback function invoked from DMA API on completion. + * + * @param base I2S base pointer. + * @param handle pointer to I2S transaction. + * @param completionStatus status of the transaction. + * @param userData optional pointer to user arguments data. + */ +typedef void (*i2s_dma_transfer_callback_t)(I2S_Type *base, + i2s_dma_handle_t *handle, + status_t completionStatus, + void *userData); +/*! @brief i2s dma handle */ +struct _i2s_dma_handle +{ + uint32_t state; /*!< Internal state of I2S DMA transfer */ + uint8_t bytesPerFrame; /*!< bytes per frame */ + i2s_dma_transfer_callback_t completionCallback; /*!< Callback function pointer */ + void *userData; /*!< Application data passed to callback */ + dma_handle_t *dmaHandle; /*!< DMA handle */ + volatile i2s_transfer_t i2sQueue[I2S_NUM_BUFFERS]; /*!< Transfer queue storing transfer buffers */ + volatile uint8_t queueUser; /*!< Queue index where user's next transfer will be stored */ + volatile uint8_t queueDriver; /*!< Queue index of buffer actually used by the driver */ + + dma_descriptor_t *i2sLoopDMADescriptor; /*!< descriptor pool pointer */ + size_t i2sLoopDMADescriptorNum; /*!< number of descriptor in descriptors pool */ +}; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! @} */ + +/*! + * @name DMA API + * @{ + */ + +/*! + * @brief Initializes handle for transfer of audio data. + * + * @param base I2S base pointer. + * @param handle pointer to handle structure. + * @param dmaHandle pointer to dma handle structure. + * @param callback function to be called back when transfer is done or fails. + * @param userData pointer to data passed to callback. + */ +void I2S_TxTransferCreateHandleDMA(I2S_Type *base, + i2s_dma_handle_t *handle, + dma_handle_t *dmaHandle, + i2s_dma_transfer_callback_t callback, + void *userData); + +/*! + * @brief Begins or queue sending of the given data. + * + * @param base I2S base pointer. + * @param handle pointer to handle structure. + * @param transfer data buffer. + * + * @retval kStatus_Success + * @retval kStatus_I2S_Busy if all queue slots are occupied with unsent buffers. + */ +status_t I2S_TxTransferSendDMA(I2S_Type *base, i2s_dma_handle_t *handle, i2s_transfer_t transfer); + +/*! + * @brief Aborts transfer of data. + * + * @param base I2S base pointer. + * @param handle pointer to handle structure. + */ +void I2S_TransferAbortDMA(I2S_Type *base, i2s_dma_handle_t *handle); + +/*! + * @brief Initializes handle for reception of audio data. + * + * @param base I2S base pointer. + * @param handle pointer to handle structure. + * @param dmaHandle pointer to dma handle structure. + * @param callback function to be called back when transfer is done or fails. + * @param userData pointer to data passed to callback. + */ +void I2S_RxTransferCreateHandleDMA(I2S_Type *base, + i2s_dma_handle_t *handle, + dma_handle_t *dmaHandle, + i2s_dma_transfer_callback_t callback, + void *userData); + +/*! + * @brief Begins or queue reception of data into given buffer. + * + * @param base I2S base pointer. + * @param handle pointer to handle structure. + * @param transfer data buffer. + * + * @retval kStatus_Success + * @retval kStatus_I2S_Busy if all queue slots are occupied with buffers + * which are not full. + */ +status_t I2S_RxTransferReceiveDMA(I2S_Type *base, i2s_dma_handle_t *handle, i2s_transfer_t transfer); + +/*! + * @brief Invoked from DMA interrupt handler. + * + * @param handle pointer to DMA handle structure. + * @param userData argument for user callback. + * @param transferDone if transfer was done. + * @param tcds + */ +void I2S_DMACallback(dma_handle_t *handle, void *userData, bool transferDone, uint32_t tcds); + +/*! + * @brief Install DMA descriptor memory for loop transfer only. + * + * This function used to register DMA descriptor memory for the i2s loop dma transfer. + * + * It must be callbed before I2S_TransferSendLoopDMA/I2S_TransferReceiveLoopDMA and after + * I2S_RxTransferCreateHandleDMA/I2S_TxTransferCreateHandleDMA. + * + * User should be take care about the address of DMA descriptor pool which required align with 16BYTE at least. + * + * @param handle Pointer to i2s DMA transfer handle. + * @param dmaDescriptorAddr DMA descriptor start address. + * @param dmaDescriptorNum DMA descriptor number. + */ +void I2S_TransferInstallLoopDMADescriptorMemory(i2s_dma_handle_t *handle, + void *dmaDescriptorAddr, + size_t dmaDescriptorNum); + +/*! + * @brief Send link transfer data using DMA. + * + * This function receives data using DMA. This is a non-blocking function, which returns + * right away. When all data is received, the receive callback function is called. + * + * This function support loop transfer, such as A->B->...->A, the loop transfer chain + * will be converted into a chain of descriptor and submit to dma. + * Application must be aware of that the more counts of the loop transfer, then more DMA descriptor memory required, + * user can use function I2S_InstallDMADescriptorMemory to register the dma descriptor memory. + * + * As the DMA support maximum 1024 transfer count, so application must be aware of that this transfer function support + * maximum 1024 samples in each transfer, otherwise assert error or error status will be returned. Once the loop + * transfer start, application can use function I2S_TransferAbortDMA to stop the loop transfer. + * + * @param base I2S peripheral base address. + * @param handle Pointer to usart_dma_handle_t structure. + * @param xfer I2S DMA transfer structure. See #i2s_transfer_t. + * @param loopTransferCount loop count + * @retval kStatus_Success + */ +status_t I2S_TransferSendLoopDMA(I2S_Type *base, + i2s_dma_handle_t *handle, + i2s_transfer_t *xfer, + uint32_t loopTransferCount); + +/*! + * @brief Receive link transfer data using DMA. + * + * This function receives data using DMA. This is a non-blocking function, which returns + * right away. When all data is received, the receive callback function is called. + * + * This function support loop transfer, such as A->B->...->A, the loop transfer chain + * will be converted into a chain of descriptor and submit to dma. + * Application must be aware of that the more counts of the loop transfer, then more DMA descriptor memory required, + * user can use function I2S_InstallDMADescriptorMemory to register the dma descriptor memory. + * + * As the DMA support maximum 1024 transfer count, so application must be aware of that this transfer function support + * maximum 1024 samples in each transfer, otherwise assert error or error status will be returned. Once the loop + * transfer start, application can use function I2S_TransferAbortDMA to stop the loop transfer. + * + * @param base I2S peripheral base address. + * @param handle Pointer to usart_dma_handle_t structure. + * @param xfer I2S DMA transfer structure. See #i2s_transfer_t. + * @param loopTransferCount loop count + * @retval kStatus_Success + */ +status_t I2S_TransferReceiveLoopDMA(I2S_Type *base, + i2s_dma_handle_t *handle, + i2s_transfer_t *xfer, + uint32_t loopTransferCount); + +/*! @} */ + +/*! @} */ + +#if defined(__cplusplus) +} +#endif + +#endif /* _FSL_I2S_DMA_H_ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_iap.c b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_iap.c new file mode 100644 index 0000000000..712b0faef7 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_iap.c @@ -0,0 +1,666 @@ +/* + * Copyright 2018-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "fsl_iap.h" +#include "fsl_iap_ffr.h" +#include "fsl_iap_kbp.h" +#include "fsl_iap_skboot_authenticate.h" +#include "fsl_device_registers.h" +/******************************************************************************* + * Definitions + ******************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.iap1" +#endif + +#if (defined(LPC5512_SERIES) || defined(LPC5514_SERIES) || defined(LPC55S14_SERIES) || defined(LPC5516_SERIES) || \ + defined(LPC55S16_SERIES) || defined(LPC5524_SERIES) || defined(LPC5502_SERIES) || defined(LPC5504_SERIES) || \ + defined(LPC5506_SERIES) || defined(LPC55S04_SERIES) || defined(LPC55S06_SERIES)) + +#define BOOTLOADER_API_TREE_POINTER ((bootloader_tree_t *)0x1301fe00U) + +#elif (defined(LPC55S69_cm33_core0_SERIES) || defined(LPC55S69_cm33_core1_SERIES) || defined(LPC5526_SERIES) || \ + defined(LPC55S26_SERIES) || defined(LPC5528_SERIES) || defined(LPC55S28_SERIES) || \ + defined(LPC55S66_cm33_core0_SERIES) || defined(LPC55S66_cm33_core1_SERIES)) + +#define BOOTLOADER_API_TREE_POINTER ((bootloader_tree_t *)0x130010f0U) + +#else +#error "No valid CPU defined!" + +#endif + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +static status_t get_cfpa_higher_version(flash_config_t *config); + +/*! + * @name flash and ffr Structure + * @{ + */ + +typedef union functionCommandOption +{ + uint32_t commandAddr; + status_t (*eraseCommand)(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, uint32_t key); + status_t (*programCommand)(flash_config_t *config, uint32_t start, uint8_t *src, uint32_t lengthInBytes); + status_t (*verifyProgramCommand)(flash_config_t *config, + uint32_t start, + uint32_t lengthInBytes, + const uint8_t *expectedData, + uint32_t *failedAddress, + uint32_t *failedData); + status_t (*flashReadCommand)(flash_config_t *config, uint32_t start, uint8_t *dest, uint32_t lengthInBytes); +} function_command_option_t; + +/* + *!@brief Structure of version property. + * + *!@ingroup bl_core + */ +typedef union StandardVersion +{ + struct + { + uint32_t bugfix : 8; /*!< bugfix version [7:0] */ + uint32_t minor : 8; /*!< minor version [15:8] */ + uint32_t major : 8; /*!< major version [23:16] */ + uint32_t name : 8; /*!< name [31:24] */ + }; + uint32_t version; /*!< combined version numbers. */ +#if defined(__cplusplus) + StandardVersion() : version(0) + { + } + StandardVersion(uint32_t version) : version(version) + { + } +#endif +} standard_version_t; + +/*! @brief Interface for the flash driver.*/ +typedef struct version1FlashDriverInterface +{ + standard_version_t version; /*!< flash driver API version number.*/ + + /*!< Flash driver.*/ + status_t (*flash_init)(flash_config_t *config); + status_t (*flash_erase)(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, uint32_t key); + status_t (*flash_program)(flash_config_t *config, uint32_t start, uint8_t *src, uint32_t lengthInBytes); + status_t (*flash_verify_erase)(flash_config_t *config, uint32_t start, uint32_t lengthInBytes); + status_t (*flash_verify_program)(flash_config_t *config, + uint32_t start, + uint32_t lengthInBytes, + const uint8_t *expectedData, + uint32_t *failedAddress, + uint32_t *failedData); + status_t (*flash_get_property)(flash_config_t *config, flash_property_tag_t whichProperty, uint32_t *value); + uint32_t reserved[3]; /*! Reserved for future use */ + /*!< Flash FFR driver*/ + status_t (*ffr_init)(flash_config_t *config); + status_t (*ffr_lock_all)(flash_config_t *config); + status_t (*ffr_cust_factory_page_write)(flash_config_t *config, uint8_t *page_data, bool seal_part); + status_t (*ffr_get_uuid)(flash_config_t *config, uint8_t *uuid); + status_t (*ffr_get_customer_data)(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len); + status_t (*ffr_keystore_write)(flash_config_t *config, ffr_key_store_t *pKeyStore); + status_t (*ffr_keystore_get_ac)(flash_config_t *config, uint8_t *pActivationCode); + status_t (*ffr_keystore_get_kc)(flash_config_t *config, uint8_t *pKeyCode, ffr_key_type_t keyIndex); + status_t (*ffr_infield_page_write)(flash_config_t *config, uint8_t *page_data, uint32_t valid_len); + status_t (*ffr_get_customer_infield_data)(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len); +} version1_flash_driver_interface_t; + +/*! @brief Interface for the flash driver.*/ +typedef struct version0FlashDriverInterface +{ + standard_version_t version; /*!< flash driver API version number.*/ + + /*!< Flash driver.*/ + status_t (*flash_init)(flash_config_t *config); + status_t (*flash_erase)(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, uint32_t key); + status_t (*flash_program)(flash_config_t *config, uint32_t start, uint8_t *src, uint32_t lengthInBytes); + status_t (*flash_verify_erase)(flash_config_t *config, uint32_t start, uint32_t lengthInBytes); + status_t (*flash_verify_program)(flash_config_t *config, + uint32_t start, + uint32_t lengthInBytes, + const uint8_t *expectedData, + uint32_t *failedAddress, + uint32_t *failedData); + status_t (*flash_get_property)(flash_config_t *config, flash_property_tag_t whichProperty, uint32_t *value); + + /*!< Flash FFR driver*/ + status_t (*ffr_init)(flash_config_t *config); + status_t (*ffr_lock_all)(flash_config_t *config); + status_t (*ffr_cust_factory_page_write)(flash_config_t *config, uint8_t *page_data, bool seal_part); + status_t (*ffr_get_uuid)(flash_config_t *config, uint8_t *uuid); + status_t (*ffr_get_customer_data)(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len); + status_t (*ffr_keystore_write)(flash_config_t *config, ffr_key_store_t *pKeyStore); + status_t (*ffr_keystore_get_ac)(flash_config_t *config, uint8_t *pActivationCode); + status_t (*ffr_keystore_get_kc)(flash_config_t *config, uint8_t *pKeyCode, ffr_key_type_t keyIndex); + status_t (*ffr_infield_page_write)(flash_config_t *config, uint8_t *page_data, uint32_t valid_len); + status_t (*ffr_get_customer_infield_data)(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len); +} version0_flash_driver_interface_t; + +typedef union flashDriverInterface +{ + const version1_flash_driver_interface_t *version1FlashDriver; + const version0_flash_driver_interface_t *version0FlashDriver; +} flash_driver_interface_t; + +/*! @}*/ + +/*! + * @name Bootloader API and image authentication Structure + * @{ + */ + +/*! @brief Interface for Bootloader API functions. */ +typedef struct _kb_interface +{ + /*!< Initialize the API. */ + status_t (*kb_init_function)(kb_session_ref_t **session, const kb_options_t *options); + status_t (*kb_deinit_function)(kb_session_ref_t *session); + status_t (*kb_execute_function)(kb_session_ref_t *session, const uint8_t *data, uint32_t dataLength); +} kb_interface_t; + +//! @brief Interface for image authentication API +typedef struct _skboot_authenticate_interface +{ + skboot_status_t (*skboot_authenticate_function)(const uint8_t *imageStartAddr, secure_bool_t *isSignVerified); + void (*skboot_hashcrypt_irq_handler)(void); +} skboot_authenticate_interface_t; +/*! @}*/ + +/*! + * @brief Root of the bootloader API tree. + * + * An instance of this struct resides in read-only memory in the bootloader. It + * provides a user application access to APIs exported by the bootloader. + * + * @note The order of existing fields must not be changed. + */ +typedef struct BootloaderTree +{ + void (*runBootloader)(void *arg); /*!< Function to start the bootloader executing. */ + standard_version_t bootloader_version; /*!< Bootloader version number. */ + const char *copyright; /*!< Copyright string. */ + const uint32_t reserved0; /*!< Do NOT use. */ + flash_driver_interface_t flashDriver; + const kb_interface_t *kbApi; /*!< Bootloader API. */ + const uint32_t reserved1[4]; /*!< Do NOT use. */ + const skboot_authenticate_interface_t *skbootAuthenticate; /*!< Image authentication API. */ +} bootloader_tree_t; + +/******************************************************************************* + * Prototype + ******************************************************************************/ +static uint32_t get_rom_api_version(void); + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/*! Get pointer to flash driver API table in ROM. */ +#define VERSION1_FLASH_API_TREE BOOTLOADER_API_TREE_POINTER->flashDriver.version1FlashDriver +#define VERSION0_FLASH_API_TREE BOOTLOADER_API_TREE_POINTER->flashDriver.version0FlashDriver +#define LPC55S69_REV0_FLASH_READ_ADDR (0x130043a3U) +#define LPC55S69_REV1_FLASH_READ_ADDR (0x13007539U) +#define LPC55S16_REV0_FLASH_READ_ADDR (0x1300ade5U) + +/******************************************************************************* + * Code + ******************************************************************************/ + +static uint32_t get_rom_api_version(void) +{ + if (BOOTLOADER_API_TREE_POINTER->bootloader_version.major == 3u) + { + return 1u; + } + else + { + return 0u; + } +} + +/*! + * @brief Initializes the global flash properties structure members. + * + * This function checks and initializes the Flash module for the other Flash APIs. + */ +status_t FLASH_Init(flash_config_t *config) +{ + status_t status; + /* Initialize the clock to 96MHz */ + config->modeConfig.sysFreqInMHz = (uint32_t)kSysToFlashFreq_defaultInMHz; + if (get_rom_api_version() == 1u) + { + status = VERSION1_FLASH_API_TREE->flash_init(config); + } + else + { + status = VERSION0_FLASH_API_TREE->flash_init(config); + } + + if (config->PFlashTotalSize == 0xA0000U) + { + config->PFlashTotalSize -= 17U * config->PFlashPageSize; + } + + return status; +} + +/*! + * @brief Erases the flash sectors encompassed by parameters passed into function. + * + * This function erases the appropriate number of flash sectors based on the + * desired start address and length. + */ +status_t FLASH_Erase(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, uint32_t key) +{ + if (get_rom_api_version() == 0u) + { + function_command_option_t runCmdFuncOption; + runCmdFuncOption.commandAddr = 0x1300413bU; /*!< get the flash erase api location adress in rom */ + return runCmdFuncOption.eraseCommand(config, start, lengthInBytes, key); + } + else + { + return VERSION1_FLASH_API_TREE->flash_erase(config, start, lengthInBytes, key); + } +} + +/*! See fsl_iap.h for documentation of this function. */ +status_t FLASH_Program(flash_config_t *config, uint32_t start, uint8_t *src, uint32_t lengthInBytes) +{ + if (get_rom_api_version() == 0u) + { + function_command_option_t runCmdFuncOption; + runCmdFuncOption.commandAddr = 0x1300419dU; /*!< get the flash program api location adress in rom*/ + return runCmdFuncOption.programCommand(config, start, src, lengthInBytes); + } + else + { + assert(VERSION1_FLASH_API_TREE); + return VERSION1_FLASH_API_TREE->flash_program(config, start, src, lengthInBytes); + } +} + +/*! See fsl_iap.h for documentation of this function. */ +status_t FLASH_Read(flash_config_t *config, uint32_t start, uint8_t *dest, uint32_t lengthInBytes) +{ + if (get_rom_api_version() == 0u) + { + /*!< get the flash read api location adress in rom*/ + function_command_option_t runCmdFuncOption; + runCmdFuncOption.commandAddr = LPC55S69_REV0_FLASH_READ_ADDR; + return runCmdFuncOption.flashReadCommand(config, start, dest, lengthInBytes); + } + else + { + /*!< get the flash read api location adress in rom*/ + function_command_option_t runCmdFuncOption; + if ((SYSCON->DIEID & SYSCON_DIEID_REV_ID_MASK) != 0u) + { + runCmdFuncOption.commandAddr = LPC55S69_REV1_FLASH_READ_ADDR; + } + else + { + runCmdFuncOption.commandAddr = LPC55S16_REV0_FLASH_READ_ADDR; + } + return runCmdFuncOption.flashReadCommand(config, start, dest, lengthInBytes); + } +} + +/*! See fsl_iap.h for documentation of this function. */ +status_t FLASH_VerifyErase(flash_config_t *config, uint32_t start, uint32_t lengthInBytes) +{ + assert(VERSION1_FLASH_API_TREE); + return VERSION1_FLASH_API_TREE->flash_verify_erase(config, start, lengthInBytes); +} + +/*! + * @brief Verifies programming of the desired flash area at a specified margin level. + * + * This function verifies the data programed in the flash memory using the + * Flash Program Check Command and compares it to the expected data for a given + * flash area as determined by the start address and length. + */ +status_t FLASH_VerifyProgram(flash_config_t *config, + uint32_t start, + uint32_t lengthInBytes, + const uint8_t *expectedData, + uint32_t *failedAddress, + uint32_t *failedData) +{ + if (get_rom_api_version() == 0u) + { + function_command_option_t runCmdFuncOption; + runCmdFuncOption.commandAddr = 0x1300427dU; /*!< get the flash verify program api location adress in rom*/ + return runCmdFuncOption.verifyProgramCommand(config, start, lengthInBytes, expectedData, failedAddress, + failedData); + } + else + { + assert(VERSION1_FLASH_API_TREE); + return VERSION1_FLASH_API_TREE->flash_verify_program(config, start, lengthInBytes, expectedData, failedAddress, + failedData); + } +} + +/*! + * @brief Returns the desired flash property. + */ +status_t FLASH_GetProperty(flash_config_t *config, flash_property_tag_t whichProperty, uint32_t *value) +{ + assert(VERSION1_FLASH_API_TREE); + return VERSION1_FLASH_API_TREE->flash_get_property(config, whichProperty, value); +} +/******************************************************************************** + * fsl iap ffr CODE + *******************************************************************************/ + +static status_t get_cfpa_higher_version(flash_config_t *config) +{ + uint32_t pageData[FLASH_FFR_MAX_PAGE_SIZE / sizeof(uint32_t)]; + uint32_t versionPing = 0U; + uint32_t versionPong = 0U; + + /* Get the CFPA ping page data and the corresponding version */ + config->ffrConfig.cfpaPageOffset = 1U; + status_t status = FFR_GetCustomerInfieldData(config, (uint8_t *)pageData, 0U, FLASH_FFR_MAX_PAGE_SIZE); + if (status != (int32_t)kStatus_FLASH_Success) + { + return status; + } + versionPing = pageData[1]; + + /* Get the CFPA pong page data and the corresponding version */ + config->ffrConfig.cfpaPageOffset = 2U; + status = FFR_GetCustomerInfieldData(config, (uint8_t *)pageData, 0U, FLASH_FFR_MAX_PAGE_SIZE); + if (status != (int32_t)kStatus_FLASH_Success) + { + return status; + } + versionPong = pageData[1]; + + /* Compare the CFPA ping version and pong version and set it correctly in flash_config structure */ + if (versionPing > versionPong) + { + config->ffrConfig.cfpaPageVersion = versionPing; + config->ffrConfig.cfpaPageOffset = 1U; + } + else + { + config->ffrConfig.cfpaPageVersion = versionPong; + config->ffrConfig.cfpaPageOffset = 2U; + } + return (int32_t)kStatus_FLASH_Success; +} + +/*! + * Initializes the global FFR properties structure members. + */ +status_t FFR_Init(flash_config_t *config) +{ + status_t status; + if (get_rom_api_version() == 0u) + { + assert(VERSION0_FLASH_API_TREE); + status = VERSION0_FLASH_API_TREE->ffr_init(config); + if (status != (status_t)kStatus_FLASH_Success) + { + return status; + } + return get_cfpa_higher_version(config); + } + else + { + assert(VERSION1_FLASH_API_TREE); + status = VERSION1_FLASH_API_TREE->ffr_init(config); + if (status != (status_t)kStatus_FLASH_Success) + { + return status; + } + return get_cfpa_higher_version(config); + } +} + +/*! + * Enable firewall for all flash banks. + */ +status_t FFR_Lock_All(flash_config_t *config) +{ + if (get_rom_api_version() == 0u) + { + assert(VERSION0_FLASH_API_TREE); + return VERSION0_FLASH_API_TREE->ffr_lock_all(config); + } + else + { + assert(VERSION1_FLASH_API_TREE); + return VERSION1_FLASH_API_TREE->ffr_lock_all(config); + } +} + +/*! + * APIs to access CMPA pages; + * This routine will erase "customer factory page" and program the page with passed data. + */ +status_t FFR_CustFactoryPageWrite(flash_config_t *config, uint8_t *page_data, bool seal_part) +{ + if (get_rom_api_version() == 0u) + { + assert(VERSION0_FLASH_API_TREE); + return VERSION0_FLASH_API_TREE->ffr_cust_factory_page_write(config, page_data, seal_part); + } + else + { + assert(VERSION1_FLASH_API_TREE); + return VERSION1_FLASH_API_TREE->ffr_cust_factory_page_write(config, page_data, seal_part); + } +} + +/*! + * See fsl_iap_ffr.h for documentation of this function. + */ +status_t FFR_GetUUID(flash_config_t *config, uint8_t *uuid) +{ + if (get_rom_api_version() == 0u) + { + assert(VERSION0_FLASH_API_TREE); + return VERSION0_FLASH_API_TREE->ffr_get_uuid(config, uuid); + } + else + { + assert(VERSION1_FLASH_API_TREE); + return VERSION1_FLASH_API_TREE->ffr_get_uuid(config, uuid); + } +} + +/*! + * APIs to access CMPA pages + * Read data stored in 'Customer Factory CFG Page'. + */ +status_t FFR_GetCustomerData(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len) +{ + if (get_rom_api_version() == 0u) + { + assert(VERSION0_FLASH_API_TREE); + return VERSION0_FLASH_API_TREE->ffr_get_customer_data(config, pData, offset, len); + } + else + { + assert(VERSION1_FLASH_API_TREE); + return VERSION1_FLASH_API_TREE->ffr_get_customer_data(config, pData, offset, len); + } +} + +/*! + * This routine writes the 3 pages allocated for Key store data, + * Used during manufacturing. Should write pages when 'customer factory page' is not in sealed state. + */ +status_t FFR_KeystoreWrite(flash_config_t *config, ffr_key_store_t *pKeyStore) +{ + if (get_rom_api_version() == 0u) + { + assert(VERSION0_FLASH_API_TREE); + return VERSION0_FLASH_API_TREE->ffr_keystore_write(config, pKeyStore); + } + else + { + assert(VERSION1_FLASH_API_TREE); + return VERSION1_FLASH_API_TREE->ffr_keystore_write(config, pKeyStore); + } +} + +/*! See fsl_iap_ffr.h for documentation of this function. */ +status_t FFR_KeystoreGetAC(flash_config_t *config, uint8_t *pActivationCode) +{ + if (get_rom_api_version() == 0u) + { + assert(VERSION0_FLASH_API_TREE); + return VERSION0_FLASH_API_TREE->ffr_keystore_get_ac(config, pActivationCode); + } + else + { + assert(VERSION1_FLASH_API_TREE); + return VERSION1_FLASH_API_TREE->ffr_keystore_get_ac(config, pActivationCode); + } +} + +/*! See fsl_iap_ffr.h for documentation of this function. */ +status_t FFR_KeystoreGetKC(flash_config_t *config, uint8_t *pKeyCode, ffr_key_type_t keyIndex) +{ + if (get_rom_api_version() == 0u) + { + assert(VERSION0_FLASH_API_TREE); + return VERSION0_FLASH_API_TREE->ffr_keystore_get_kc(config, pKeyCode, keyIndex); + } + else + { + assert(VERSION1_FLASH_API_TREE); + return VERSION1_FLASH_API_TREE->ffr_keystore_get_kc(config, pKeyCode, keyIndex); + } +} + +/*! + * APIs to access CFPA pages + * This routine will erase CFPA and program the CFPA page with passed data. + */ +status_t FFR_InfieldPageWrite(flash_config_t *config, uint8_t *page_data, uint32_t valid_len) +{ + if (get_rom_api_version() == 0u) + { + assert(VERSION0_FLASH_API_TREE); + return VERSION0_FLASH_API_TREE->ffr_infield_page_write(config, page_data, valid_len); + } + else + { + assert(VERSION1_FLASH_API_TREE); + return VERSION1_FLASH_API_TREE->ffr_infield_page_write(config, page_data, valid_len); + } +} + +/*! + * APIs to access CFPA pages + * Generic read function, used by customer to read data stored in 'Customer In-field Page'. + */ +status_t FFR_GetCustomerInfieldData(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len) +{ + if (get_rom_api_version() == 0u) + { + assert(VERSION0_FLASH_API_TREE); + return VERSION0_FLASH_API_TREE->ffr_get_customer_infield_data(config, pData, offset, len); + } + else + { + assert(VERSION1_FLASH_API_TREE); + return VERSION1_FLASH_API_TREE->ffr_get_customer_infield_data(config, pData, offset, len); + } +} + +/******************************************************************************** + * Bootloader API + *******************************************************************************/ +/*! + * @brief Initialize ROM API for a given operation. + * + * Inits the ROM API based on the options provided by the application in the second + * argument. Every call to rom_init() should be paired with a call to rom_deinit(). + */ +status_t kb_init(kb_session_ref_t **session, const kb_options_t *options) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->kbApi->kb_init_function(session, options); +} + +/*! + * @brief Cleans up the ROM API context. + * + * After this call, the @a context parameter can be reused for another operation + * by calling rom_init() again. + */ +status_t kb_deinit(kb_session_ref_t *session) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->kbApi->kb_deinit_function(session); +} + +/*! + * Perform the operation configured during init. + * + * This application must call this API repeatedly, passing in sequential chunks of + * data from the boot image (SB file) that is to be processed. The ROM will perform + * the selected operation on this data and return. The application may call this + * function with as much or as little data as it wishes, which can be used to select + * the granularity of time given to the application in between executing the operation. + * + * @param context Current ROM context pointer. + * @param data Buffer of boot image data provided to the ROM by the application. + * @param dataLength Length in bytes of the data in the buffer provided to the ROM. + * + * @retval #kStatus_Success The operation has completed successfully. + * @retval #kStatus_Fail An error occurred while executing the operation. + * @retval #kStatus_RomApiNeedMoreData No error occurred, but the ROM needs more data to + * continue processing the boot image. + */ +status_t kb_execute(kb_session_ref_t *session, const uint8_t *data, uint32_t dataLength) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->kbApi->kb_execute_function(session, data, dataLength); +} + +/******************************************************************************** + * Image authentication API + *******************************************************************************/ + +/*! + * @brief Authenticate entry function with ARENA allocator init + * + * This is called by ROM boot or by ROM API g_skbootAuthenticateInterface + */ +skboot_status_t skboot_authenticate(const uint8_t *imageStartAddr, secure_bool_t *isSignVerified) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->skbootAuthenticate->skboot_authenticate_function(imageStartAddr, + isSignVerified); +} + +/*! + * @brief Interface for image authentication API + */ +void HASH_IRQHandler(void) +{ + assert(BOOTLOADER_API_TREE_POINTER); + BOOTLOADER_API_TREE_POINTER->skbootAuthenticate->skboot_hashcrypt_irq_handler(); +} +/******************************************************************************** + * EOF + *******************************************************************************/ diff --git a/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_iap.h b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_iap.h new file mode 100644 index 0000000000..f7b318b66b --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_iap.h @@ -0,0 +1,528 @@ +/* + * Copyright 2018-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef __FSL_IAP_H_ +#define __FSL_IAP_H_ + +#include "fsl_common.h" +/*! + * @addtogroup flash_driver + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! + * @name Flash version + * @{ + */ +/*! @brief Constructs the version number for drivers. */ +#if !defined(MAKE_VERSION) +#define MAKE_VERSION(major, minor, bugfix) (((major) << 16) | ((minor) << 8) | (bugfix)) +#endif + +/*! @brief Flash driver version for SDK*/ +#define FSL_FLASH_DRIVER_VERSION (MAKE_VERSION(2, 1, 4)) /*!< Version 2.1.4. */ + +/*! @brief Flash driver version for ROM*/ +enum _flash_driver_version_constants +{ + kFLASH_DriverVersionName = 'F', /*!< Flash driver version name.*/ + kFLASH_DriverVersionMajor = 2, /*!< Major flash driver version.*/ + kFLASH_DriverVersionMinor = 1, /*!< Minor flash driver version.*/ + kFLASH_DriverVersionBugfix = 3 /*!< Bugfix for flash driver version.*/ +}; + +/*@}*/ + +/*! + * @name Flash configuration + * @{ + */ +/*! @brief Flash IP Type. */ +#if !defined(FSL_FEATURE_FLASH_IP_IS_C040HD_ATFC) +#define FSL_FEATURE_FLASH_IP_IS_C040HD_ATFC (1) +#endif +#if !defined(FSL_FEATURE_FLASH_IP_IS_C040HD_FC) +#define FSL_FEATURE_FLASH_IP_IS_C040HD_FC (0) +#endif + +/*! + * @name Flash status + * @{ + */ +/*! @brief Flash driver status group. */ +#if defined(kStatusGroup_FlashDriver) +#define kStatusGroupGeneric kStatusGroup_Generic +#define kStatusGroupFlashDriver kStatusGroup_FlashDriver +#elif defined(kStatusGroup_FLASHIAP) +#define kStatusGroupGeneric kStatusGroup_Generic +#define kStatusGroupFlashDriver kStatusGroup_FLASH +#else +#define kStatusGroupGeneric 0 +#define kStatusGroupFlashDriver 1 +#endif + +/*! @brief Constructs a status code value from a group and a code number. */ +#if !defined(MAKE_STATUS) +#define MAKE_STATUS(group, code) ((((group)*100) + (code))) +#endif + +/*! + * @brief Flash driver status codes. + */ +enum _flash_status +{ + kStatus_FLASH_Success = MAKE_STATUS(kStatusGroupGeneric, 0), /*!< API is executed successfully*/ + kStatus_FLASH_InvalidArgument = MAKE_STATUS(kStatusGroupGeneric, 4), /*!< Invalid argument*/ + kStatus_FLASH_SizeError = MAKE_STATUS(kStatusGroupFlashDriver, 0), /*!< Error size*/ + kStatus_FLASH_AlignmentError = + MAKE_STATUS(kStatusGroupFlashDriver, 1), /*!< Parameter is not aligned with the specified baseline*/ + kStatus_FLASH_AddressError = MAKE_STATUS(kStatusGroupFlashDriver, 2), /*!< Address is out of range */ + kStatus_FLASH_AccessError = + MAKE_STATUS(kStatusGroupFlashDriver, 3), /*!< Invalid instruction codes and out-of bound addresses */ + kStatus_FLASH_ProtectionViolation = MAKE_STATUS( + kStatusGroupFlashDriver, 4), /*!< The program/erase operation is requested to execute on protected areas */ + kStatus_FLASH_CommandFailure = + MAKE_STATUS(kStatusGroupFlashDriver, 5), /*!< Run-time error during command execution. */ + kStatus_FLASH_UnknownProperty = MAKE_STATUS(kStatusGroupFlashDriver, 6), /*!< Unknown property.*/ + kStatus_FLASH_EraseKeyError = MAKE_STATUS(kStatusGroupFlashDriver, 7), /*!< API erase key is invalid.*/ + kStatus_FLASH_RegionExecuteOnly = + MAKE_STATUS(kStatusGroupFlashDriver, 8), /*!< The current region is execute-only.*/ + kStatus_FLASH_ExecuteInRamFunctionNotReady = + MAKE_STATUS(kStatusGroupFlashDriver, 9), /*!< Execute-in-RAM function is not available.*/ + + kStatus_FLASH_CommandNotSupported = MAKE_STATUS(kStatusGroupFlashDriver, 11), /*!< Flash API is not supported.*/ + kStatus_FLASH_ReadOnlyProperty = MAKE_STATUS(kStatusGroupFlashDriver, 12), /*!< The flash property is read-only.*/ + kStatus_FLASH_InvalidPropertyValue = + MAKE_STATUS(kStatusGroupFlashDriver, 13), /*!< The flash property value is out of range.*/ + kStatus_FLASH_InvalidSpeculationOption = + MAKE_STATUS(kStatusGroupFlashDriver, 14), /*!< The option of flash prefetch speculation is invalid.*/ + kStatus_FLASH_EccError = MAKE_STATUS(kStatusGroupFlashDriver, + 0x10), /*!< A correctable or uncorrectable error during command execution. */ + kStatus_FLASH_CompareError = + MAKE_STATUS(kStatusGroupFlashDriver, 0x11), /*!< Destination and source memory contents do not match. */ + kStatus_FLASH_RegulationLoss = MAKE_STATUS(kStatusGroupFlashDriver, 0x12), /*!< A loss of regulation during read. */ + kStatus_FLASH_InvalidWaitStateCycles = + MAKE_STATUS(kStatusGroupFlashDriver, 0x13), /*!< The wait state cycle set to r/w mode is invalid. */ + + kStatus_FLASH_OutOfDateCfpaPage = + MAKE_STATUS(kStatusGroupFlashDriver, 0x20), /*!< CFPA page version is out of date. */ + kStatus_FLASH_BlankIfrPageData = MAKE_STATUS(kStatusGroupFlashDriver, 0x21), /*!< Blank page cannnot be read. */ + kStatus_FLASH_EncryptedRegionsEraseNotDoneAtOnce = + MAKE_STATUS(kStatusGroupFlashDriver, 0x22), /*!< Encrypted flash subregions are not erased at once. */ + kStatus_FLASH_ProgramVerificationNotAllowed = MAKE_STATUS( + kStatusGroupFlashDriver, 0x23), /*!< Program verification is not allowed when the encryption is enabled. */ + kStatus_FLASH_HashCheckError = + MAKE_STATUS(kStatusGroupFlashDriver, 0x24), /*!< Hash check of page data is failed. */ + kStatus_FLASH_SealedFfrRegion = MAKE_STATUS(kStatusGroupFlashDriver, 0x25), /*!< The FFR region is sealed. */ + kStatus_FLASH_FfrRegionWriteBroken = MAKE_STATUS( + kStatusGroupFlashDriver, 0x26), /*!< The FFR Spec region is not allowed to be written discontinuously. */ + kStatus_FLASH_NmpaAccessNotAllowed = + MAKE_STATUS(kStatusGroupFlashDriver, 0x27), /*!< The NMPA region is not allowed to be read/written/erased. */ + kStatus_FLASH_CmpaCfgDirectEraseNotAllowed = + MAKE_STATUS(kStatusGroupFlashDriver, 0x28), /*!< The CMPA Cfg region is not allowed to be erased directly. */ + kStatus_FLASH_FfrBankIsLocked = MAKE_STATUS(kStatusGroupFlashDriver, 0x29), /*!< The FFR bank region is locked. */ +}; +/*@}*/ + +/*! + * @name Flash API key + * @{ + */ +/*! @brief Constructs the four character code for the Flash driver API key. */ +#if !defined(FOUR_CHAR_CODE) +#define FOUR_CHAR_CODE(a, b, c, d) (((d) << 24) | ((c) << 16) | ((b) << 8) | ((a))) +#endif + +/*! + * @brief Enumeration for Flash driver API keys. + * + * @note The resulting value is built with a byte order such that the string + * being readable in expected order when viewed in a hex editor, if the value + * is treated as a 32-bit little endian value. + */ +enum _flash_driver_api_keys +{ + kFLASH_ApiEraseKey = FOUR_CHAR_CODE('l', 'f', 'e', 'k') /*!< Key value used to validate all flash erase APIs.*/ +}; +/*@}*/ + +/*! + * @brief Enumeration for various flash properties. + */ +typedef enum _flash_property_tag +{ + kFLASH_PropertyPflashSectorSize = 0x00U, /*!< Pflash sector size property.*/ + kFLASH_PropertyPflashTotalSize = 0x01U, /*!< Pflash total size property.*/ + kFLASH_PropertyPflashBlockSize = 0x02U, /*!< Pflash block size property.*/ + kFLASH_PropertyPflashBlockCount = 0x03U, /*!< Pflash block count property.*/ + kFLASH_PropertyPflashBlockBaseAddr = 0x04U, /*!< Pflash block base address property.*/ + + kFLASH_PropertyPflashPageSize = 0x30U, /*!< Pflash page size property.*/ + kFLASH_PropertyPflashSystemFreq = 0x31U, /*!< System Frequency System Frequency.*/ + + kFLASH_PropertyFfrSectorSize = 0x40U, /*!< FFR sector size property.*/ + kFLASH_PropertyFfrTotalSize = 0x41U, /*!< FFR total size property.*/ + kFLASH_PropertyFfrBlockBaseAddr = 0x42U, /*!< FFR block base address property.*/ + kFLASH_PropertyFfrPageSize = 0x43U, /*!< FFR page size property.*/ +} flash_property_tag_t; + +/*! + * @brief Enumeration for flash max pages to erase. + */ +enum _flash_max_erase_page_value +{ + kFLASH_MaxPagesToErase = 100U /*!< The max value in pages to erase. */ +}; + +/*! + * @brief Enumeration for flash alignment property. + */ +enum _flash_alignment_property +{ + kFLASH_AlignementUnitVerifyErase = 4, /*!< The alignment unit in bytes used for verify erase operation.*/ + kFLASH_AlignementUnitProgram = 512, /*!< The alignment unit in bytes used for program operation.*/ + /*kFLASH_AlignementUnitVerifyProgram = 4,*/ /*!< The alignment unit in bytes used for verify program operation.*/ + kFLASH_AlignementUnitSingleWordRead = 16 /*!< The alignment unit in bytes used for SingleWordRead command.*/ +}; + +/*! + * @brief Enumeration for flash read ecc option + */ +enum _flash_read_ecc_option +{ + kFLASH_ReadWithEccOn = 0, /*! ECC is on */ + kFLASH_ReadWithEccOff = 1, /*! ECC is off */ +}; + +/* set flash Controller timing before flash init */ +enum _flash_freq_tag +{ + kSysToFlashFreq_lowInMHz = 12u, + kSysToFlashFreq_defaultInMHz = 96u, +}; + +/*! + * @brief Enumeration for flash read margin option + */ +enum _flash_read_margin_option +{ + kFLASH_ReadMarginNormal = 0, /*!< Normal read */ + kFLASH_ReadMarginVsProgram = 1, /*!< Margin vs. program */ + kFLASH_ReadMarginVsErase = 2, /*!< Margin vs. erase */ + kFLASH_ReadMarginIllegalBitCombination = 3 /*!< Illegal bit combination */ +}; + +/*! + * @brief Enumeration for flash read dmacc option + */ +enum _flash_read_dmacc_option +{ + kFLASH_ReadDmaccDisabled = 0, /*!< Memory word */ + kFLASH_ReadDmaccEnabled = 1, /*!< DMACC word */ +}; + +/*! + * @brief Enumeration for flash ramp control option + */ +enum _flash_ramp_control_option +{ + kFLASH_RampControlDivisionFactorReserved = 0, /*!< Reserved */ + kFLASH_RampControlDivisionFactor256 = 1, /*!< clk48mhz / 256 = 187.5KHz */ + kFLASH_RampControlDivisionFactor128 = 2, /*!< clk48mhz / 128 = 375KHz */ + kFLASH_RampControlDivisionFactor64 = 3 /*!< clk48mhz / 64 = 750KHz */ +}; + +/*! @brief Flash ECC log info. */ +typedef struct _flash_ecc_log +{ + uint32_t firstEccEventAddress; + uint32_t eccErrorCount; + uint32_t eccCorrectionCount; + uint32_t reserved; +} flash_ecc_log_t; + +/*! @brief Flash controller paramter config. */ +typedef struct _flash_mode_config +{ + uint32_t sysFreqInMHz; + /* ReadSingleWord parameter. */ + struct + { + uint8_t readWithEccOff : 1; + uint8_t readMarginLevel : 2; + uint8_t readDmaccWord : 1; + uint8_t reserved0 : 4; + uint8_t reserved1[3]; + } readSingleWord; + /* SetWriteMode parameter. */ + struct + { + uint8_t programRampControl; + uint8_t eraseRampControl; + uint8_t reserved[2]; + } setWriteMode; + /* SetReadMode parameter. */ + struct + { + uint16_t readInterfaceTimingTrim; + uint16_t readControllerTimingTrim; + uint8_t readWaitStates; + uint8_t reserved[3]; + } setReadMode; +} flash_mode_config_t; + +/*! @brief Flash controller paramter config. */ +typedef struct _flash_ffr_config +{ + uint32_t ffrBlockBase; + uint32_t ffrTotalSize; + uint32_t ffrPageSize; + uint32_t cfpaPageVersion; + uint32_t cfpaPageOffset; +} flash_ffr_config_t; + +/*! @brief Flash driver state information. + * + * An instance of this structure is allocated by the user of the flash driver and + * passed into each of the driver APIs. + */ +typedef struct _flash_config +{ + uint32_t PFlashBlockBase; /*!< A base address of the first PFlash block */ + uint32_t PFlashTotalSize; /*!< The size of the combined PFlash block. */ + uint32_t PFlashBlockCount; /*!< A number of PFlash blocks. */ + uint32_t PFlashPageSize; /*!< The size in bytes of a page of PFlash. */ + uint32_t PFlashSectorSize; /*!< The size in bytes of a sector of PFlash. */ + flash_ffr_config_t ffrConfig; + flash_mode_config_t modeConfig; +} flash_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Initialization + * @{ + */ + +/*! + * @brief Initializes the global flash properties structure members. + * + * This function checks and initializes the Flash module for the other Flash APIs. + * + * @param config Pointer to the storage for the driver runtime state. + * + * @retval #kStatus_FLASH_Success API was executed successfully. + * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. + * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution. + * @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported. + * @retval #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution. + */ +status_t FLASH_Init(flash_config_t *config); + +/*@}*/ + +/*! + * @name Erasing + * @{ + */ + +/*! + * @brief Erases the flash sectors encompassed by parameters passed into function. + * + * This function erases the appropriate number of flash sectors based on the + * desired start address and length. + * + * @param config The pointer to the storage for the driver runtime state. + * @param start The start address of the desired flash memory to be erased. + * The start address need to be 512bytes-aligned. + * @param lengthInBytes The length, given in bytes (not words or long-words) + * to be erased. Must be 512bytes-aligned. + * @param key The value used to validate all flash erase APIs. + * + * @retval #kStatus_FLASH_Success API was executed successfully; + * the appropriate number of flash sectors based on the desired + * start address and length were erased successfully. + * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. + * @retval #kStatus_FLASH_AlignmentError The parameter is not aligned with the specified baseline. + * @retval #kStatus_FLASH_AddressError The address is out of range. + * @retval #kStatus_FLASH_EraseKeyError The API erase key is invalid. + * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution. + * @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported. + * @retval #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution. + */ +status_t FLASH_Erase(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, uint32_t key); + +/*@}*/ + +/*! + * @name Programming + * @{ + */ + +/*! + * @brief Programs flash with data at locations passed in through parameters. + * + * This function programs the flash memory with the desired data for a given + * flash area as determined by the start address and the length. + * + * @param config A pointer to the storage for the driver runtime state. + * @param start The start address of the desired flash memory to be programmed. Must be + * 512bytes-aligned. + * @param src A pointer to the source buffer of data that is to be programmed + * into the flash. + * @param lengthInBytes The length, given in bytes (not words or long-words), + * to be programmed. Must be 512bytes-aligned. + * + * @retval #kStatus_FLASH_Success API was executed successfully; the desired data were programed successfully + * into flash based on desired start address and length. + * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. + * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with the specified baseline. + * @retval #kStatus_FLASH_AddressError Address is out of range. + * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses. + * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution. + * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution. + * @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported. + * @retval #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution. + */ +status_t FLASH_Program(flash_config_t *config, uint32_t start, uint8_t *src, uint32_t lengthInBytes); + +/*@}*/ + +/*! + * @brief Reads flash at locations passed in through parameters. + * + * This function read the flash memory from a given flash area as determined + * by the start address and the length. + * + * @param config A pointer to the storage for the driver runtime state. + * @param start The start address of the desired flash memory to be read. + * @param dest A pointer to the dest buffer of data that is to be read + * from the flash. + * @param lengthInBytes The length, given in bytes (not words or long-words), + * to be read. + * + * @retval #kStatus_FLASH_Success API was executed successfully. + * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. + * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with the specified baseline. + * @retval #kStatus_FLASH_AddressError Address is out of range. + * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses. + * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution. + * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution. + * @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported. + * @retval #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution. + */ +status_t FLASH_Read(flash_config_t *config, uint32_t start, uint8_t *dest, uint32_t lengthInBytes); + +/*! + * @name Verification + * @{ + */ + +/*! + * @brief Verifies an erasure of the desired flash area at a specified margin level. + * + * This function checks the appropriate number of flash sectors based on + * the desired start address and length to check whether the flash is erased + * to the specified read margin level. + * + * @param config A pointer to the storage for the driver runtime state. + * @param start The start address of the desired flash memory to be verified. + * The start address need to be 512bytes-aligned. + * @param lengthInBytes The length, given in bytes (not words or long-words), + * to be verified. Must be 512bytes-aligned. + * + * @retval #kStatus_FLASH_Success API was executed successfully; the specified FLASH region has been erased. + * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. + * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with specified baseline. + * @retval #kStatus_FLASH_AddressError Address is out of range. + * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses. + * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution. + * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution. + * @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported. + * @retval #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution. + */ +status_t FLASH_VerifyErase(flash_config_t *config, uint32_t start, uint32_t lengthInBytes); + +/*! + * @brief Verifies programming of the desired flash area at a specified margin level. + * + * This function verifies the data programed in the flash memory using the + * Flash Program Check Command and compares it to the expected data for a given + * flash area as determined by the start address and length. + * + * @param config A pointer to the storage for the driver runtime state. + * @param start The start address of the desired flash memory to be verified. need be 512bytes-aligned. + * @param lengthInBytes The length, given in bytes (not words or long-words), + * to be verified. need be 512bytes-aligned. + * @param expectedData A pointer to the expected data that is to be + * verified against. + * @param failedAddress A pointer to the returned failing address. + * @param failedData A pointer to the returned failing data. Some derivatives do + * not include failed data as part of the FCCOBx registers. In this + * case, zeros are returned upon failure. + * + * @retval #kStatus_FLASH_Success API was executed successfully; + * the desired data have been successfully programed into specified FLASH region. + * + * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. + * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with specified baseline. + * @retval #kStatus_FLASH_AddressError Address is out of range. + * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses. + * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution. + * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution. + * @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported. + * @retval #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution. + */ +status_t FLASH_VerifyProgram(flash_config_t *config, + uint32_t start, + uint32_t lengthInBytes, + const uint8_t *expectedData, + uint32_t *failedAddress, + uint32_t *failedData); + +/*@}*/ + +/*! + * @name Properties + * @{ + */ + +/*! + * @brief Returns the desired flash property. + * + * @param config A pointer to the storage for the driver runtime state. + * @param whichProperty The desired property from the list of properties in + * enum flash_property_tag_t + * @param value A pointer to the value returned for the desired flash property. + * + * @retval #kStatus_FLASH_Success API was executed successfully; the flash property was stored to value. + * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. + * @retval #kStatus_FLASH_UnknownProperty An unknown property tag. + */ +status_t FLASH_GetProperty(flash_config_t *config, flash_property_tag_t whichProperty, uint32_t *value); + +/*@}*/ + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* __FLASH_FLASH_H_ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_iap_ffr.h b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_iap_ffr.h new file mode 100644 index 0000000000..9481e07af1 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_iap_ffr.h @@ -0,0 +1,388 @@ +/* + * Copyright 2018-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef __FSL_IAP_FFR_H_ +#define __FSL_IAP_FFR_H_ + +#include "fsl_iap.h" + +/*! + * @addtogroup flash_ifr_driver + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! + * @name Flash IFR version + * @{ + */ +/*! @brief Flash IFR driver version for SDK*/ +#define FSL_FLASH_IFR_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) /*!< Version 2.1.0. */ +/*@}*/ + +/*! @brief Alignment(down) utility. */ +#if !defined(ALIGN_DOWN) +#define ALIGN_DOWN(x, a) ((x) & (uint32_t)(-((int32_t)(a)))) +#endif + +/*! @brief Alignment(up) utility. */ +#if !defined(ALIGN_UP) +#define ALIGN_UP(x, a) (-((int32_t)((uint32_t)(-((int32_t)(x))) & (uint32_t)(-((int32_t)(a)))))) +#endif + +#define FLASH_FFR_MAX_PAGE_SIZE (512u) +#define FLASH_FFR_HASH_DIGEST_SIZE (32u) +#define FLASH_FFR_IV_CODE_SIZE (52u) + +/*! @brief flash ffr page offset. */ +enum _flash_ffr_page_offset +{ + kFfrPageOffset_CFPA = 0, /*!< Customer In-Field programmed area*/ + kFfrPageOffset_CFPA_Scratch = 0, /*!< CFPA Scratch page */ + kFfrPageOffset_CFPA_Cfg = 1, /*!< CFPA Configuration area (Ping page)*/ + kFfrPageOffset_CFPA_CfgPong = 2, /*!< Same as CFPA page (Pong page)*/ + + kFfrPageOffset_CMPA = 3, /*!< Customer Manufacturing programmed area*/ + kFfrPageOffset_CMPA_Cfg = 3, /*!< CMPA Configuration area (Part of CMPA)*/ + kFfrPageOffset_CMPA_Key = 4, /*!< Key Store area (Part of CMPA)*/ + + kFfrPageOffset_NMPA = 7, /*!< NXP Manufacturing programmed area*/ + kFfrPageOffset_NMPA_Romcp = 7, /*!< ROM patch area (Part of NMPA)*/ + kFfrPageOffset_NMPA_Repair = 9, /*!< Repair area (Part of NMPA)*/ + kFfrPageOffset_NMPA_Cfg = 15, /*!< NMPA configuration area (Part of NMPA)*/ + kFfrPageOffset_NMPA_End = 16, /*!< Reserved (Part of NMPA)*/ +}; + +/*! @brief flash ffr page number. */ +enum _flash_ffr_page_num +{ + kFfrPageNum_CFPA = 3, /*!< Customer In-Field programmed area*/ + kFfrPageNum_CMPA = 4, /*!< Customer Manufacturing programmed area*/ + kFfrPageNum_NMPA = 10, /*!< NXP Manufacturing programmed area*/ + + kFfrPageNum_CMPA_Cfg = 1, + kFfrPageNum_CMPA_Key = 3, + kFfrPageNum_NMPA_Romcp = 2, + + kFfrPageNum_SpecArea = kFfrPageNum_CFPA + kFfrPageNum_CMPA, + kFfrPageNum_Total = (kFfrPageNum_CFPA + kFfrPageNum_CMPA + kFfrPageNum_NMPA), +}; + +enum _flash_ffr_block_size +{ + kFfrBlockSize_Key = 52u, + kFfrBlockSize_ActivationCode = 1192u, +}; + +typedef enum _cfpa_cfg_cmpa_prog_process +{ + kFfrCmpaProgProcess_Pre = 0x0u, + kFfrCmpaProgProcess_Post = 0xFFFFFFFFu, +} cmpa_prog_process_t; + +typedef struct _cfpa_cfg_iv_code +{ + uint32_t keycodeHeader; + uint8_t reserved[FLASH_FFR_IV_CODE_SIZE]; +} cfpa_cfg_iv_code_t; + +typedef struct _cfpa_cfg_info +{ + uint32_t header; /*!< [0x000-0x003] */ + uint32_t version; /*!< [0x004-0x007 */ + uint32_t secureFwVersion; /*!< [0x008-0x00b */ + uint32_t nsFwVersion; /*!< [0x00c-0x00f] */ + uint32_t imageKeyRevoke; /*!< [0x010-0x013] */ + uint8_t reserved0[4]; /*!< [0x014-0x017] */ + uint32_t rotkhRevoke; /*!< [0x018-0x01b] */ + uint32_t vendorUsage; /*!< [0x01c-0x01f] */ + uint32_t dcfgNsPin; /*!< [0x020-0x013] */ + uint32_t dcfgNsDflt; /*!< [0x024-0x017] */ + uint32_t enableFaMode; /*!< [0x028-0x02b] */ + uint8_t reserved1[4]; /*!< [0x02c-0x02f] */ + cfpa_cfg_iv_code_t ivCodePrinceRegion[3]; /*!< [0x030-0x0d7] */ + uint8_t reserved2[264]; /*!< [0x0d8-0x1df] */ + uint8_t sha256[32]; /*!< [0x1e0-0x1ff] */ +} cfpa_cfg_info_t; + +#define FFR_BOOTCFG_BOOTSPEED_MASK (0x18U) +#define FFR_BOOTCFG_BOOTSPEED_SHIFT (7U) +#define FFR_BOOTCFG_BOOTSPEED_48MHZ (0x0U) +#define FFR_BOOTCFG_BOOTSPEED_96MHZ (0x1U) + +#define FFR_USBID_VENDORID_MASK (0xFFFFU) +#define FFR_USBID_VENDORID_SHIFT (0U) +#define FFR_USBID_PRODUCTID_MASK (0xFFFF0000U) +#define FFR_USBID_PRODUCTID_SHIFT (16U) + +typedef struct _cmpa_cfg_info +{ + uint32_t bootCfg; /*!< [0x000-0x003] */ + uint32_t spiFlashCfg; /*!< [0x004-0x007] */ + struct + { + uint16_t vid; + uint16_t pid; + } usbId; /*!< [0x008-0x00b] */ + uint32_t sdioCfg; /*!< [0x00c-0x00f] */ + uint32_t dcfgPin; /*!< [0x010-0x013] */ + uint32_t dcfgDflt; /*!< [0x014-0x017] */ + uint32_t dapVendorUsage; /*!< [0x018-0x01b] */ + uint32_t secureBootCfg; /*!< [0x01c-0x01f] */ + uint32_t princeBaseAddr; /*!< [0x020-0x023] */ + uint32_t princeSr[3]; /*!< [0x024-0x02f] */ + uint8_t reserved0[32]; /*!< [0x030-0x04f] */ + uint32_t rotkh[8]; /*!< [0x050-0x06f] */ + uint8_t reserved1[368]; /*!< [0x070-0x1df] */ + uint8_t sha256[32]; /*!< [0x1e0-0x1ff] */ +} cmpa_cfg_info_t; + +typedef struct _cmpa_key_store_header +{ + uint32_t header; + uint8_t reserved[4]; +} cmpa_key_store_header_t; + +#define FFR_SYSTEM_SPEED_CODE_MASK (0x3U) +#define FFR_SYSTEM_SPEED_CODE_SHIFT (0U) +#define FFR_SYSTEM_SPEED_CODE_FRO12MHZ_12MHZ (0x0U) +#define FFR_SYSTEM_SPEED_CODE_FROHF96MHZ_24MHZ (0x1U) +#define FFR_SYSTEM_SPEED_CODE_FROHF96MHZ_48MHZ (0x2U) +#define FFR_SYSTEM_SPEED_CODE_FROHF96MHZ_96MHZ (0x3U) + +#define FFR_PERIPHERALCFG_PERI_MASK (0x7FFFFFFFU) +#define FFR_PERIPHERALCFG_PERI_SHIFT (0U) +#define FFR_PERIPHERALCFG_COREEN_MASK (0x10000000U) +#define FFR_PERIPHERALCFG_COREEN_SHIFT (31U) + +typedef struct _nmpa_cfg_info +{ + uint16_t fro32kCfg; /*!< [0x000-0x001] */ + uint8_t reserved0[6]; /*!< [0x002-0x007] */ + uint8_t sysCfg; /*!< [0x008-0x008] */ + uint8_t reserved1[7]; /*!< [0x009-0x00f] */ + struct + { + uint32_t data; + uint32_t reserved[3]; + } GpoInitData[3]; /*!< [0x010-0x03f] */ + uint32_t GpoDataChecksum[4]; /*!< [0x040-0x04f] */ + uint32_t finalTestBatchId[4]; /*!< [0x050-0x05f] */ + uint32_t deviceType; /*!< [0x060-0x063] */ + uint32_t finalTestProgVersion; /*!< [0x064-0x067] */ + uint32_t finalTestDate; /*!< [0x068-0x06b] */ + uint32_t finalTestTime; /*!< [0x06c-0x06f] */ + uint32_t uuid[4]; /*!< [0x070-0x07f] */ + uint8_t reserved2[32]; /*!< [0x080-0x09f] */ + uint32_t peripheralCfg; /*!< [0x0a0-0x0a3] */ + uint32_t ramSizeCfg; /*!< [0x0a4-0x0a7] */ + uint32_t flashSizeCfg; /*!< [0x0a8-0x0ab] */ + uint8_t reserved3[36]; /*!< [0x0ac-0x0cf] */ + uint8_t fro1mCfg; /*!< [0x0d0-0x0d0] */ + uint8_t reserved4[15]; /*!< [0x0d1-0x0df] */ + uint32_t dcdc[4]; /*!< [0x0e0-0x0ef] */ + uint32_t bod; /*!< [0x0f0-0x0f3] */ + uint8_t reserved5[12]; /*!< [0x0f4-0x0ff] */ + uint8_t calcHashReserved[192]; /*!< [0x100-0x1bf] */ + uint8_t sha256[32]; /*!< [0x1c0-0x1df] */ + uint32_t ecidBackup[4]; /*!< [0x1e0-0x1ef] */ + uint32_t pageChecksum[4]; /*!< [0x1f0-0x1ff] */ +} nmpa_cfg_info_t; + +typedef struct _ffr_key_store +{ + uint8_t reserved[3][FLASH_FFR_MAX_PAGE_SIZE]; +} ffr_key_store_t; + +typedef enum _ffr_key_type +{ + kFFR_KeyTypeSbkek = 0x00U, + kFFR_KeyTypeUser = 0x01U, + kFFR_KeyTypeUds = 0x02U, + kFFR_KeyTypePrinceRegion0 = 0x03U, + kFFR_KeyTypePrinceRegion1 = 0x04U, + kFFR_KeyTypePrinceRegion2 = 0x05U, +} ffr_key_type_t; + +typedef enum _ffr_bank_type +{ + kFFR_BankTypeBank0_NMPA = 0x00U, + kFFR_BankTypeBank1_CMPA = 0x01U, + kFFR_BankTypeBank2_CFPA = 0x02U +} ffr_bank_type_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name FFR APIs + * @{ + */ + +/*! + * @brief Initializes the global FFR properties structure members. + * + * @param config A pointer to the storage for the driver runtime state. + * + * @retval #kStatus_FLASH_Success API was executed successfully. + * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. + */ +status_t FFR_Init(flash_config_t *config); + +/*! + * @brief Enable firewall for all flash banks. + * + * CFPA, CMPA, and NMPA flash areas region will be locked, After this function executed; + * Unless the board is reset again. + * + * @param config A pointer to the storage for the driver runtime state. + * + * @retval #kStatus_FLASH_Success An invalid argument is provided. + * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. + */ +status_t FFR_Lock_All(flash_config_t *config); + +/*! + * @brief APIs to access CFPA pages + * + * This routine will erase CFPA and program the CFPA page with passed data. + * + * @param config A pointer to the storage for the driver runtime state. + * @param page_data A pointer to the source buffer of data that is to be programmed + * into the CFPA. + * @param valid_len The length, given in bytes, to be programmed. + * + * @retval #kStatus_FLASH_Success The desire page-data were programed successfully into CFPA. + * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. + * @retval kStatus_FTFx_AddressError Address is out of range. + * @retval #kStatus_FLASH_FfrBankIsLocked The CFPA was locked. + * @retval #kStatus_FLASH_OutOfDateCfpaPage It is not newest CFPA page. + */ +status_t FFR_InfieldPageWrite(flash_config_t *config, uint8_t *page_data, uint32_t valid_len); + +/*! + * @brief APIs to access CFPA pages + * + * Generic read function, used by customer to read data stored in 'Customer In-field Page'. + * + * @param config A pointer to the storage for the driver runtime state. + * @param pData A pointer to the dest buffer of data that is to be read from 'Customer In-field Page'. + * @param offset An offset from the 'Customer In-field Page' start address. + * @param len The length, given in bytes, to be read. + * + * @retval #kStatus_FLASH_Success Get data from 'Customer In-field Page'. + * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. + * @retval kStatus_FTFx_AddressError Address is out of range. + * @retval #kStatus_FLASH_CommandFailure access error. + */ +status_t FFR_GetCustomerInfieldData(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len); + +/*! + * @brief APIs to access CMPA pages + * + * This routine will erase "customer factory page" and program the page with passed data. + * If 'seal_part' parameter is TRUE then the routine will compute SHA256 hash of + * the page contents and then programs the pages. + * 1.During development customer code uses this API with 'seal_part' set to FALSE. + * 2.During manufacturing this parameter should be set to TRUE to seal the part + * from further modifications + * 3.This routine checks if the page is sealed or not. A page is said to be sealed if + * the SHA256 value in the page has non-zero value. On boot ROM locks the firewall for + * the region if hash is programmed anyways. So, write/erase commands will fail eventually. + * + * @param config A pointer to the storage for the driver runtime state. + * @param page_data A pointer to the source buffer of data that is to be programmed + * into the "customer factory page". + * @param seal_part Set fasle for During development customer code. + * + * @retval #kStatus_FLASH_Success The desire page-data were programed successfully into CMPA. + * @retval #kStatus_FLASH_InvalidArgument Parameter is not aligned with the specified baseline. + * @retval kStatus_FTFx_AddressError Address is out of range. + * @retval #kStatus_FLASH_CommandFailure access error. + */ +status_t FFR_CustFactoryPageWrite(flash_config_t *config, uint8_t *page_data, bool seal_part); + +/*! + * @brief APIs to access CMPA page + * + * Read data stored in 'Customer Factory CFG Page'. + * + * @param config A pointer to the storage for the driver runtime state. + * @param pData A pointer to the dest buffer of data that is to be read + * from the Customer Factory CFG Page. + * @param offset Address offset relative to the CMPA area. + * @param len The length, given in bytes to be read. + * + * @retval #kStatus_FLASH_Success Get data from 'Customer Factory CFG Page'. + * @retval #kStatus_FLASH_InvalidArgument Parameter is not aligned with the specified baseline. + * @retval kStatus_FTFx_AddressError Address is out of range. + * @retval #kStatus_FLASH_CommandFailure access error. + */ +status_t FFR_GetCustomerData(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len); + +/*! + * @brief APIs to access CMPA page + * + * 1.SW should use this API routine to get the UUID of the chip. + * 2.Calling routine should pass a pointer to buffer which can hold 128-bit value. + */ +status_t FFR_GetUUID(flash_config_t *config, uint8_t *uuid); + +/*! + * @brief This routine writes the 3 pages allocated for Key store data, + * + * 1.Used during manufacturing. Should write pages when 'customer factory page' is not in sealed state. + * 2.Optional routines to set individual data members (activation code, key codes etc) to construct + * the key store structure in RAM before committing it to IFR/FFR. + * + * @param config A pointer to the storage for the driver runtime state. + * @param pKeyStore A Pointer to the 3 pages allocated for Key store data. + * that will be written to 'customer factory page'. + * + * @retval #kStatus_FLASH_Success The key were programed successfully into FFR. + * @retval #kStatus_FLASH_InvalidArgument Parameter is not aligned with the specified baseline. + * @retval kStatus_FTFx_AddressError Address is out of range. + * @retval #kStatus_FLASH_CommandFailure access error. + */ +status_t FFR_KeystoreWrite(flash_config_t *config, ffr_key_store_t *pKeyStore); + +/*! + * @brief Get/Read Key store code routines + * + * 1. Calling code should pass buffer pointer which can hold activation code 1192 bytes. + * 2. Check if flash aperture is small or regular and read the data appropriately. + */ +status_t FFR_KeystoreGetAC(flash_config_t *config, uint8_t *pActivationCode); + +/*! + * @brief Get/Read Key store code routines + * + * 1. Calling code should pass buffer pointer which can hold key code 52 bytes. + * 2. Check if flash aperture is small or regular and read the data appropriately. + * 3. keyIndex specifies which key code is read. + */ +status_t FFR_KeystoreGetKC(flash_config_t *config, uint8_t *pKeyCode, ffr_key_type_t keyIndex); + +/*@}*/ + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /*! __FSL_FLASH_FFR_H_ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_iap_kbp.h b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_iap_kbp.h new file mode 100644 index 0000000000..453a89a8fd --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_iap_kbp.h @@ -0,0 +1,245 @@ +/* + * Copyright (c) 2020-2021, Freescale Semiconductor, Inc. + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_IAP_KBP_H_ +#define _FSL_IAP_KBP_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup kb_driver + * @{ + */ +/******************************************************************************* + * Definitions + *******************************************************************************/ + +/*! @brief ROM API status group number */ +#define kStatusGroup_RomApi (108U) + +/*! @brief ROM API status codes. */ +enum +{ + kStatus_RomApiExecuteCompleted = kStatus_Success, /*!< ROM successfully process the whole sb file/boot image.*/ + kStatus_RomApiNeedMoreData = + MAKE_STATUS(kStatusGroup_RomApi, 1), /*!< ROM needs more data to continue processing the boot image.*/ + kStatus_RomApiBufferSizeNotEnough = + MAKE_STATUS(kStatusGroup_RomApi, + 2), /*!< The user buffer is not enough for use by Kboot during execution of the operation.*/ + kStatus_RomApiInvalidBuffer = + MAKE_STATUS(kStatusGroup_RomApi, 3), /*!< The user buffer is not ok for sbloader or authentication.*/ +}; + +/*! + * @brief Details of the operation to be performed by the ROM. + * + * The #kRomAuthenticateImage operation requires the entire signed image to be + * available to the application. + */ +typedef enum _kb_operation +{ + kRomAuthenticateImage = 1, /*!< Authenticate a signed image.*/ + kRomLoadImage = 2, /*!< Load SB file.*/ + kRomOperationCount = 3, +} kb_operation_t; + +/*! + * @brief Security constraint flags, Security profile flags. + */ +enum _kb_security_profile +{ + kKbootMinRSA4096 = (1 << 16), +}; + +/*! + * @brief Memory region definition. + */ +typedef struct _kb_region +{ + uint32_t address; + uint32_t length; +} kb_region_t; + +/*! + * @brief User-provided options passed into kb_init(). + * + * The buffer field is a pointer to memory provided by the caller for use by + * Kboot during execution of the operation. Minimum size is the size of each + * certificate in the chain plus 432 bytes additional per certificate. + * + * The profile field is a mask that specifies which features are required in + * the SB file or image being processed. This includes the minimum AES and RSA + * key sizes. See the _kb_security_profile enum for profile mask constants. + * The image being loaded or authenticated must match the profile or an error will + * be returned. + * + * minBuildNumber is an optional field that can be used to prevent version + * rollback. The API will check the build number of the image, and if it is less + * than minBuildNumber will fail with an error. + * + * maxImageLength is used to verify the offsetToCertificateBlockHeaderInBytes + * value at the beginning of a signed image. It should be set to the length of + * the SB file. If verifying an image in flash, it can be set to the internal + * flash size or a large number like 0x10000000. + * + * userRHK can optionally be used by the user to override the RHK in IFR. If + * userRHK is not NULL, it points to a 32-byte array containing the SHA-256 of + * the root certificate's RSA public key. + * + * The regions field points to an array of memory regions that the SB file being + * loaded is allowed to access. If regions is NULL, then all memory is + * accessible by the SB file. This feature is required to prevent a malicious + * image from erasing good code or RAM contents while it is being loaded, only + * for us to find that the image is inauthentic when we hit the end of the + * section. + * + * overrideSBBootSectionID lets the caller override the default section of the + * SB file that is processed during a kKbootLoadSB operation. By default, + * the section specified in the firstBootableSectionID field of the SB header + * is loaded. If overrideSBBootSectionID is non-zero, then the section with + * the given ID will be loaded instead. + * + * The userSBKEK field lets a user provide their own AES-256 key for unwrapping + * keys in an SB file during the kKbootLoadSB operation. userSBKEK should point + * to a 32-byte AES-256 key. If userSBKEK is NULL then the IFR SBKEK will be used. + * After kb_init() returns, the caller should zero out the data pointed to by + * userSBKEK, as the API will have installed the key in the CAU3. + */ + +typedef struct _kb_load_sb +{ + uint32_t profile; + uint32_t minBuildNumber; + uint32_t overrideSBBootSectionID; + uint32_t *userSBKEK; + uint32_t regionCount; + const kb_region_t *regions; +} kb_load_sb_t; + +typedef struct _kb_authenticate +{ + uint32_t profile; + uint32_t minBuildNumber; + uint32_t maxImageLength; + uint32_t *userRHK; +} kb_authenticate_t; + +typedef struct _kb_options +{ + uint32_t version; /*!< Should be set to kKbootApiVersion.*/ + uint8_t *buffer; /*!< Caller-provided buffer used by Kboot.*/ + uint32_t bufferLength; + kb_operation_t op; + union + { + kb_authenticate_t authenticate; /*! Settings for kKbootAuthenticate operation.*/ + kb_load_sb_t loadSB; /*! Settings for kKbootLoadSB operation.*/ + }; +} kb_options_t; + +/*! + * @brief Interface to memory operations for one region of memory. + */ +typedef struct _memory_region_interface +{ + status_t (*init)(void); + status_t (*read)(uint32_t address, uint32_t length, uint8_t *buffer); + status_t (*write)(uint32_t address, uint32_t length, const uint8_t *buffer); + status_t (*fill)(uint32_t address, uint32_t length, uint32_t pattern); + status_t (*flush)(void); + status_t (*erase)(uint32_t address, uint32_t length); + status_t (*config)(uint32_t *buffer); + status_t (*erase_all)(void); +} memory_region_interface_t; + +/*! + * @brief Structure of a memory map entry. + */ +typedef struct _memory_map_entry +{ + uint32_t startAddress; + uint32_t endAddress; + uint32_t memoryProperty; + uint32_t memoryId; + const memory_region_interface_t *memoryInterface; +} memory_map_entry_t; + +typedef struct _kb_opaque_session_ref +{ + kb_options_t context; + bool cau3Initialized; + memory_map_entry_t *memoryMap; +} kb_session_ref_t; + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Initialize ROM API for a given operation. + * + * Inits the ROM API based on the options provided by the application in the second + * argument. Every call to rom_init() should be paired with a call to rom_deinit(). + * + * @retval #kStatus_Success API was executed successfully. + * @retval #kStatus_InvalidArgument An invalid argument is provided. + * @retval #kStatus_RomApiBufferSizeNotEnough The user buffer is not enough for use by Kboot during execution of the + * operation. + * @retval #kStatus_RomApiInvalidBuffer The user buffer is not ok for sbloader or authentication. + * @retval #kStatus_SKBOOT_Fail Return the failed status of secure boot. + * @retval #kStatus_SKBOOT_KeyStoreMarkerInvalid The key code for the particular PRINCE region is not present in the + * keystore + * @retval #kStatus_SKBOOT_Success Return the successful status of secure boot. + */ +status_t kb_init(kb_session_ref_t **session, const kb_options_t *options); + +/*! + * @brief Cleans up the ROM API context. + * + * After this call, the context parameter can be reused for another operation + * by calling rom_init() again. + * + * @retval #kStatus_Success API was executed successfully + */ +status_t kb_deinit(kb_session_ref_t *session); + +/*! + * Perform the operation configured during init. + * + * This application must call this API repeatedly, passing in sequential chunks of + * data from the boot image (SB file) that is to be processed. The ROM will perform + * the selected operation on this data and return. The application may call this + * function with as much or as little data as it wishes, which can be used to select + * the granularity of time given to the application in between executing the operation. + * + * @param session Current ROM context pointer. + * @param data Buffer of boot image data provided to the ROM by the application. + * @param dataLength Length in bytes of the data in the buffer provided to the ROM. + * + * @retval #kStatus_Success ROM successfully process the part of sb file/boot image. + * @retval #kStatus_RomApiExecuteCompleted ROM successfully process the whole sb file/boot image. + * @retval #kStatus_Fail An error occurred while executing the operation. + * @retval #kStatus_RomApiNeedMoreData No error occurred, but the ROM needs more data to + * continue processing the boot image. + * @retval #kStatus_RomApiBufferSizeNotEnough user buffer is not enough for + * use by Kboot during execution of the operation. + */ +status_t kb_execute(kb_session_ref_t *session, const uint8_t *data, uint32_t dataLength); + +#if defined(__cplusplus) +} +#endif + +/*! + *@} + */ + +#endif /* _FSL_IAP_KBP_H_ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_iap_skboot_authenticate.h b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_iap_skboot_authenticate.h new file mode 100644 index 0000000000..67a513bc3c --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_iap_skboot_authenticate.h @@ -0,0 +1,77 @@ +/* + * Copyright 2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef _FSL_IAP_SKBOOT_AUTHENTICATE_H_ +#define _FSL_IAP_SKBOOT_AUTHENTICATE_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup skboot_authenticate + * @{ + */ + +/******************************************************************************* + * Definitions + *******************************************************************************/ + +/*! @brief SKBOOT return status*/ +typedef enum _skboot_status +{ + kStatus_SKBOOT_Success = 0x5ac3c35au, /*!< SKBOOT return success status.*/ + kStatus_SKBOOT_Fail = 0xc35ac35au, /*!< SKBOOT return fail status.*/ + kStatus_SKBOOT_InvalidArgument = 0xc35a5ac3u, /*!< SKBOOT return invalid argument status.*/ + kStatus_SKBOOT_KeyStoreMarkerInvalid = 0xc3c35a5au, /*!< SKBOOT return Keystore invalid Marker status.*/ + kStatus_SKBOOT_HashcryptFinishedWithStatusSuccess = + 0xc15a5ac3, /*!< SKBOOT return Hashcrypt finished with the success status.*/ + kStatus_SKBOOT_HashcryptFinishedWithStatusFail = + 0xc15a5acb, /*!< SKBOOT return Hashcrypt finished with the fail status.*/ +} skboot_status_t; + +/*! @brief Secure bool flag*/ +typedef enum _secure_bool +{ + kSECURE_TRUE = 0xc33cc33cU, /*!< Secure true flag.*/ + kSECURE_FALSE = 0x5aa55aa5U, /*!< Secure false flag.*/ + kSECURE_CALLPROTECT_SECURITY_FLAGS = 0xc33c5aa5U, /*!< Secure call protect the security flag.*/ + kSECURE_CALLPROTECT_IS_APP_READY = 0x5aa5c33cU, /*!< Secure call protect the app is ready flag.*/ + kSECURE_TRACKER_VERIFIED = 0x55aacc33U, /*!< Secure tracker verified flag.*/ +} secure_bool_t; + +/******************************************************************************* + * Externs + ******************************************************************************/ + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Authenticate entry function with ARENA allocator init + * + * This is called by ROM boot or by ROM API g_skbootAuthenticateInterface + */ +skboot_status_t skboot_authenticate(const uint8_t *imageStartAddr, secure_bool_t *isSignVerified); + +/*! + * @brief Interface for image authentication API + */ +void HASH_IRQHandler(void); + +#if defined(__cplusplus) +} +#endif + +/*! + *@} + */ + +#endif /* _FSL_IAP_SKBOOT_AUTHENTICATE_H_ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_inputmux.c b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_inputmux.c new file mode 100644 index 0000000000..ab208b78a4 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_inputmux.c @@ -0,0 +1,135 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_inputmux.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.inputmux" +#endif + +/******************************************************************************* + * Code + ******************************************************************************/ + +/*! + * brief Initialize INPUTMUX peripheral. + + * This function enables the INPUTMUX clock. + * + * param base Base address of the INPUTMUX peripheral. + * + * retval None. + */ +void INPUTMUX_Init(INPUTMUX_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +#if defined(FSL_FEATURE_INPUTMUX_HAS_NO_INPUTMUX_CLOCK_SOURCE) && FSL_FEATURE_INPUTMUX_HAS_NO_INPUTMUX_CLOCK_SOURCE + CLOCK_EnableClock(kCLOCK_Sct); + CLOCK_EnableClock(kCLOCK_Dma); +#else + CLOCK_EnableClock(kCLOCK_InputMux); +#endif /* FSL_FEATURE_INPUTMUX_HAS_NO_INPUTMUX_CLOCK_SOURCE */ +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/*! + * brief Attaches a signal + * + * This function gates the INPUTPMUX clock. + * + * param base Base address of the INPUTMUX peripheral. + * param index Destination peripheral to attach the signal to. + * param connection Selects connection. + * + * retval None. + */ +void INPUTMUX_AttachSignal(INPUTMUX_Type *base, uint32_t index, inputmux_connection_t connection) +{ + uint32_t pmux_id; + uint32_t output_id; + + /* extract pmux to be used */ + pmux_id = ((uint32_t)(connection)) >> PMUX_SHIFT; + /* extract function number */ + output_id = ((uint32_t)(connection)) & ((1UL << PMUX_SHIFT) - 1U); + /* programm signal */ + *(volatile uint32_t *)(((uint32_t)base) + pmux_id + (index * 4U)) = output_id; +} + +#if defined(FSL_FEATURE_INPUTMUX_HAS_SIGNAL_ENA) +/*! + * brief Enable/disable a signal + * + * This function gates the INPUTPMUX clock. + * + * param base Base address of the INPUTMUX peripheral. + * param signal Enable signal register id and bit offset. + * param enable Selects enable or disable. + * + * retval None. + */ +void INPUTMUX_EnableSignal(INPUTMUX_Type *base, inputmux_signal_t signal, bool enable) +{ + uint32_t ena_id; + uint32_t ena_id_mask = (1UL << (32U - ENA_SHIFT)) - 1U; + uint32_t bit_offset; + +#if defined(FSL_FEATURE_INPUTMUX_HAS_CHANNEL_MUX) && FSL_FEATURE_INPUTMUX_HAS_CHANNEL_MUX + uint32_t chmux_offset; + uint32_t chmux_value; + + /* Only enable need to update channel mux */ + if (enable && ((((uint32_t)signal) & (1UL << CHMUX_AVL_SHIFT)) != 0U)) + { + chmux_offset = (((uint32_t)signal) >> CHMUX_OFF_SHIFT) & ((1UL << (CHMUX_AVL_SHIFT - CHMUX_OFF_SHIFT)) - 1UL); + chmux_value = (((uint32_t)signal) >> CHMUX_VAL_SHIFT) & ((1UL << (CHMUX_OFF_SHIFT - CHMUX_VAL_SHIFT)) - 1UL); + *(volatile uint32_t *)(((uint32_t)base) + chmux_offset) = chmux_value; + } + ena_id_mask = (1UL << (CHMUX_VAL_SHIFT - ENA_SHIFT)) - 1U; +#endif + /* extract enable register to be used */ + ena_id = (((uint32_t)signal) >> ENA_SHIFT) & ena_id_mask; + /* extract enable bit offset */ + bit_offset = ((uint32_t)signal) & ((1UL << ENA_SHIFT) - 1U); + /* set signal */ + if (enable) + { + *(volatile uint32_t *)(((uint32_t)base) + ena_id) |= (1UL << bit_offset); + } + else + { + *(volatile uint32_t *)(((uint32_t)base) + ena_id) &= ~(1UL << bit_offset); + } +} +#endif + +/*! + * brief Deinitialize INPUTMUX peripheral. + + * This function disables the INPUTMUX clock. + * + * param base Base address of the INPUTMUX peripheral. + * + * retval None. + */ +void INPUTMUX_Deinit(INPUTMUX_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +#if defined(FSL_FEATURE_INPUTMUX_HAS_NO_INPUTMUX_CLOCK_SOURCE) && FSL_FEATURE_INPUTMUX_HAS_NO_INPUTMUX_CLOCK_SOURCE + CLOCK_DisableClock(kCLOCK_Sct); + CLOCK_DisableClock(kCLOCK_Dma); +#else + CLOCK_DisableClock(kCLOCK_InputMux); +#endif /* FSL_FEATURE_INPUTMUX_HAS_NO_INPUTMUX_CLOCK_SOURCE */ +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} diff --git a/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_inputmux.h b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_inputmux.h new file mode 100644 index 0000000000..90dd905fcf --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_inputmux.h @@ -0,0 +1,97 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_INPUTMUX_H_ +#define _FSL_INPUTMUX_H_ + +#include "fsl_inputmux_connections.h" +#include "fsl_common.h" + +/*! + * @addtogroup inputmux_driver + * @{ + */ + +/*! @file */ +/*! @file fsl_inputmux_connections.h */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief Group interrupt driver version for SDK */ +#define FSL_INPUTMUX_DRIVER_VERSION (MAKE_VERSION(2, 0, 4)) +/*@}*/ + +/******************************************************************************* + * API + ******************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + +/*! + * @brief Initialize INPUTMUX peripheral. + + * This function enables the INPUTMUX clock. + * + * @param base Base address of the INPUTMUX peripheral. + * + * @retval None. + */ +void INPUTMUX_Init(INPUTMUX_Type *base); + +/*! + * @brief Attaches a signal + * + * This function gates the INPUTPMUX clock. + * + * @param base Base address of the INPUTMUX peripheral. + * @param index Destination peripheral to attach the signal to. + * @param connection Selects connection. + * + * @retval None. + */ +void INPUTMUX_AttachSignal(INPUTMUX_Type *base, uint32_t index, inputmux_connection_t connection); + +#if defined(FSL_FEATURE_INPUTMUX_HAS_SIGNAL_ENA) +/*! + * @brief Enable/disable a signal + * + * This function gates the INPUTPMUX clock. + * + * @param base Base address of the INPUTMUX peripheral. + * @param signal Enable signal register id and bit offset. + * @param enable Selects enable or disable. + * + * @retval None. + */ +void INPUTMUX_EnableSignal(INPUTMUX_Type *base, inputmux_signal_t signal, bool enable); +#endif + +/*! + * @brief Deinitialize INPUTMUX peripheral. + + * This function disables the INPUTMUX clock. + * + * @param base Base address of the INPUTMUX peripheral. + * + * @retval None. + */ +void INPUTMUX_Deinit(INPUTMUX_Type *base); + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* _FSL_INPUTMUX_H_ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_inputmux_connections.h b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_inputmux_connections.h new file mode 100644 index 0000000000..3c142c7eba --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_inputmux_connections.h @@ -0,0 +1,481 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016, NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_INPUTMUX_CONNECTIONS_ +#define _FSL_INPUTMUX_CONNECTIONS_ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.inputmux_connections" +#endif + +/*! + * @addtogroup inputmux_driver + * @{ + */ + +/*! + * @name Input multiplexing connections + * @{ + */ + +/*! @brief Periphinmux IDs */ +#define SCT0_INMUX0 0x00U +#define TIMER0CAPTSEL0 0x20U +#define TIMER1CAPTSEL0 0x40U +#define TIMER2CAPTSEL0 0x60U +#define PINTSEL_PMUX_ID 0xC0U +#define PINTSEL0 0xC0U +#define DMA0_ITRIG_INMUX0 0xE0U +#define DMA0_OTRIG_INMUX0 0x160U +#define FREQMEAS_REF_REG 0x180U +#define FREQMEAS_TARGET_REG 0x184U +#define TIMER3CAPTSEL0 0x1A0U +#define TIMER4CAPTSEL0 0x1C0U +#define PINTSECSEL0 0x1E0U +#define DMA1_ITRIG_INMUX0 0x200U +#define DMA1_OTRIG_INMUX0 0x240U +#define DMA0_REQ_ENA_ID 0x740U +#define DMA1_REQ_ENA_ID 0x760U +#define DMA0_ITRIG_ENA_ID 0x780U +#define DMA1_ITRIG_ENA_ID 0x7A0U +#define ENA_SHIFT 8U +#define PMUX_SHIFT 20U + +/*! @brief INPUTMUX connections type */ +typedef enum _inputmux_connection_t +{ + /*!< SCT0 INMUX. */ + kINPUTMUX_SctGpi0ToSct0 = 0U + (SCT0_INMUX0 << PMUX_SHIFT), + kINPUTMUX_SctGpi1ToSct0 = 1U + (SCT0_INMUX0 << PMUX_SHIFT), + kINPUTMUX_SctGpi2ToSct0 = 2U + (SCT0_INMUX0 << PMUX_SHIFT), + kINPUTMUX_SctGpi3ToSct0 = 3U + (SCT0_INMUX0 << PMUX_SHIFT), + kINPUTMUX_SctGpi4ToSct0 = 4U + (SCT0_INMUX0 << PMUX_SHIFT), + kINPUTMUX_SctGpi5ToSct0 = 5U + (SCT0_INMUX0 << PMUX_SHIFT), + kINPUTMUX_SctGpi6ToSct0 = 6U + (SCT0_INMUX0 << PMUX_SHIFT), + kINPUTMUX_SctGpi7ToSct0 = 7U + (SCT0_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Ctimer0M0ToSct0 = 8U + (SCT0_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Ctimer1M0ToSct0 = 9U + (SCT0_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Ctimer2M0ToSct0 = 10U + (SCT0_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Ctimer3M0ToSct0 = 11U + (SCT0_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Ctimer4M0ToSct0 = 12U + (SCT0_INMUX0 << PMUX_SHIFT), + kINPUTMUX_AdcIrqToSct0 = 13U + (SCT0_INMUX0 << PMUX_SHIFT), + kINPUTMUX_GpiointBmatchToSct0 = 14U + (SCT0_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Usb0FrameToggleToSct0 = 15U + (SCT0_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Usb1FrameToggleToSct0 = 16U + (SCT0_INMUX0 << PMUX_SHIFT), + kINPUTMUX_CompOutToSct0 = 17U + (SCT0_INMUX0 << PMUX_SHIFT), + kINPUTMUX_I2sSharedSck0ToSct0 = 18U + (SCT0_INMUX0 << PMUX_SHIFT), + kINPUTMUX_I2sSharedSck1ToSct0 = 19U + (SCT0_INMUX0 << PMUX_SHIFT), + kINPUTMUX_I2sSharedWs0ToSct0 = 20U + (SCT0_INMUX0 << PMUX_SHIFT), + kINPUTMUX_I2sSharedWs1ToSct0 = 21U + (SCT0_INMUX0 << PMUX_SHIFT), + kINPUTMUX_ArmTxevToSct0 = 22U + (SCT0_INMUX0 << PMUX_SHIFT), + kINPUTMUX_DebugHaltedToSct0 = 23U + (SCT0_INMUX0 << PMUX_SHIFT), + + /*!< TIMER0 CAPTSEL. */ + kINPUTMUX_CtimerInp0ToTimer0Captsel = 0U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp1ToTimer0Captsel = 1U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp2ToTimer0Captsel = 2U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp3ToTimer0Captsel = 3U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp4ToTimer0Captsel = 4U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp5ToTimer0Captsel = 5U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp6ToTimer0Captsel = 6U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp7ToTimer0Captsel = 7U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp8ToTimer0Captsel = 8U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp9ToTimer0Captsel = 9U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp10ToTimer0Captsel = 10U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp11ToTimer0Captsel = 11U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp12ToTimer0Captsel = 12U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp13ToTimer0Captsel = 13U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp14ToTimer0Captsel = 14U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp15ToTimer0Captsel = 15U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp16ToTimer0Captsel = 16U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Usb0FrameToggleToTimer0Captsel = 20U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Usb1FrameToggleToTimer0Captsel = 21U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CompOutToTimer0Captsel = 22U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_I2sSharedWs0ToTimer0Captsel = 23U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_I2sSharedWs1ToTimer0Captsel = 24U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + + /*!< TIMER1 CAPTSEL. */ + kINPUTMUX_CtimerInp0ToTimer1Captsel = 0U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp1ToTimer1Captsel = 1U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp2ToTimer1Captsel = 2U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp3ToTimer1Captsel = 3U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp4ToTimer1Captsel = 4U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp5ToTimer1Captsel = 5U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp6ToTimer1Captsel = 6U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp7ToTimer1Captsel = 7U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp8ToTimer1Captsel = 8U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp9ToTimer1Captsel = 9U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp10ToTimer1Captsel = 10U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp11ToTimer1Captsel = 11U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp12ToTimer1Captsel = 12U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp13ToTimer1Captsel = 13U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp14ToTimer1Captsel = 14U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp15ToTimer1Captsel = 15U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp16ToTimer1Captsel = 16U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Usb0FrameToggleToTimer1Captsel = 20U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Usb1FrameToggleToTimer1Captsel = 21U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CompOutToTimer1Captsel = 22U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_I2sSharedWs0ToTimer1Captsel = 23U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_I2sSharedWs1ToTimer1Captsel = 24U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + + /*!< TIMER2 CAPTSEL. */ + kINPUTMUX_CtimerInp0ToTimer2Captsel = 0U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp1ToTimer2Captsel = 1U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp2ToTimer2Captsel = 2U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp3ToTimer2Captsel = 3U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp4ToTimer2Captsel = 4U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp5ToTimer2Captsel = 5U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp6ToTimer2Captsel = 6U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp7ToTimer2Captsel = 7U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp8ToTimer2Captsel = 8U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp9ToTimer2Captsel = 9U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp10ToTimer2Captsel = 10U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp11ToTimer2Captsel = 11U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp12ToTimer2Captsel = 12U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp13ToTimer2Captsel = 13U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp14ToTimer2Captsel = 14U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp15ToTimer2Captsel = 15U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp16ToTimer2Captsel = 16U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Usb0FrameToggleToTimer2Captsel = 20U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Usb1FrameToggleToTimer2Captsel = 21U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CompOutToTimer2Captsel = 22U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_I2sSharedWs0ToTimer2Captsel = 23U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_I2sSharedWs1ToTimer2Captsel = 24U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + + /*!< Pin interrupt select. */ + kINPUTMUX_GpioPort0Pin0ToPintsel = 0U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin1ToPintsel = 1U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin2ToPintsel = 2U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin3ToPintsel = 3U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin4ToPintsel = 4U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin5ToPintsel = 5U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin6ToPintsel = 6U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin7ToPintsel = 7U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin8ToPintsel = 8U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin9ToPintsel = 9U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin10ToPintsel = 10U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin11ToPintsel = 11U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin12ToPintsel = 12U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin13ToPintsel = 13U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin14ToPintsel = 14U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin15ToPintsel = 15U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin16ToPintsel = 16U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin17ToPintsel = 17U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin18ToPintsel = 18U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin19ToPintsel = 19U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin20ToPintsel = 20U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin21ToPintsel = 21U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin22ToPintsel = 22U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin23ToPintsel = 23U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin24ToPintsel = 24U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin25ToPintsel = 25U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin26ToPintsel = 26U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin27ToPintsel = 27U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin28ToPintsel = 28U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin29ToPintsel = 29U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin30ToPintsel = 30U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin31ToPintsel = 31U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin0ToPintsel = 32U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin1ToPintsel = 33U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin2ToPintsel = 34U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin3ToPintsel = 35U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin4ToPintsel = 36U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin5ToPintsel = 37U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin6ToPintsel = 38U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin7ToPintsel = 39U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin8ToPintsel = 40U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin9ToPintsel = 41U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin10ToPintsel = 42U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin11ToPintsel = 43U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin12ToPintsel = 44U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin13ToPintsel = 45U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin14ToPintsel = 46U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin15ToPintsel = 47U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin16ToPintsel = 48U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin17ToPintsel = 49U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin18ToPintsel = 50U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin19ToPintsel = 51U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin20ToPintsel = 52U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin21ToPintsel = 53U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin22ToPintsel = 54U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin23ToPintsel = 55U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin24ToPintsel = 56U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin25ToPintsel = 57U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin26ToPintsel = 58U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin27ToPintsel = 59U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin28ToPintsel = 60U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin29ToPintsel = 61U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin30ToPintsel = 62U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin31ToPintsel = 63U + (PINTSEL0 << PMUX_SHIFT), + + /*!< DMA0 Input trigger. */ + kINPUTMUX_PinInt0ToDma0 = 0U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_PinInt1ToDma0 = 1U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_PinInt2ToDma0 = 2U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_PinInt3ToDma0 = 3U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Ctimer0M0ToDma0 = 4U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Ctimer0M1ToDma0 = 5U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Ctimer1M0ToDma0 = 6U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Ctimer1M1ToDma0 = 7U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Ctimer2M0ToDma0 = 8U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Ctimer2M1ToDma0 = 9U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Ctimer3M0ToDma0 = 10U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Ctimer3M1ToDma0 = 11U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Ctimer4M0ToDma0 = 12U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Ctimer4M1ToDma0 = 13U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_CompOutToDma0 = 14U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Otrig0ToDma0 = 15U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Otrig1ToDma0 = 16U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Otrig2ToDma0 = 17U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Otrig3ToDma0 = 18U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Sct0DmaReq0ToDma0 = 19U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Sct0DmaReq1ToDma0 = 20U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_HashDmaRxToDma0 = 21U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), + + /*!< DMA0 output trigger. */ + kINPUTMUX_Dma0Hash0TxTrigoutToTriginChannels = 0U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma0HsLspiRxTrigoutToTriginChannels = 2U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma0HsLspiTxTrigoutToTriginChannels = 3U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma0Flexcomm0RxTrigoutToTriginChannels = 4U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma0Flexcomm0TxTrigoutToTriginChannels = 5U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma0Flexcomm1RxTrigoutToTriginChannels = 6U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma0Flexcomm1TxTrigoutToTriginChannels = 7U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma0Flexcomm3RxTrigoutToTriginChannels = 8U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma0Flexcomm3TxTrigoutToTriginChannels = 9U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma0Flexcomm2RxTrigoutToTriginChannels = 10U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma0Flexcomm2TxTrigoutToTriginChannels = 11U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma0Flexcomm4RxTrigoutToTriginChannels = 12U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma0Flexcomm4TxTrigoutToTriginChannels = 13U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma0Flexcomm5RxTrigoutToTriginChannels = 14U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma0Flexcomm5TxTrigoutToTriginChannels = 15U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma0Flexcomm6RxTrigoutToTriginChannels = 16U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma0Flexcomm6TxTrigoutToTriginChannels = 17U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma0Flexcomm7RxTrigoutToTriginChannels = 18U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma0Flexcomm7TxTrigoutToTriginChannels = 19U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma0Adc0Ch0TrigoutToTriginChannels = 21U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma0Adc0Ch1TrigoutToTriginChannels = 22U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), + + /*!< Selection for frequency measurement reference clock. */ + kINPUTMUX_ExternOscToFreqmeasRef = 0U + (FREQMEAS_REF_REG << PMUX_SHIFT), + kINPUTMUX_Fro12MhzToFreqmeasRef = 1u + (FREQMEAS_REF_REG << PMUX_SHIFT), + kINPUTMUX_Fro96MhzToFreqmeasRef = 2u + (FREQMEAS_REF_REG << PMUX_SHIFT), + kINPUTMUX_WdtOscToFreqmeasRef = 3u + (FREQMEAS_REF_REG << PMUX_SHIFT), + kINPUTMUX_32KhzOscToFreqmeasRef = 4u + (FREQMEAS_REF_REG << PMUX_SHIFT), + kINPUTMUX_MainClkToFreqmeasRef = 5u + (FREQMEAS_REF_REG << PMUX_SHIFT), + kINPUTMUX_FreqmeGpioClk_aRef = 6u + (FREQMEAS_REF_REG << PMUX_SHIFT), + kINPUTMUX_FreqmeGpioClk_bRef = 7u + (FREQMEAS_REF_REG << PMUX_SHIFT), + + /*!< Selection for frequency measurement target clock. */ + kINPUTMUX_ExternOscToFreqmeasTarget = 0U + (FREQMEAS_TARGET_REG << PMUX_SHIFT), + kINPUTMUX_Fro12MhzToFreqmeasTarget = 1u + (FREQMEAS_TARGET_REG << PMUX_SHIFT), + kINPUTMUX_Fro96MhzToFreqmeasTarget = 2u + (FREQMEAS_TARGET_REG << PMUX_SHIFT), + kINPUTMUX_WdtOscToFreqmeasTarget = 3u + (FREQMEAS_TARGET_REG << PMUX_SHIFT), + kINPUTMUX_32KhzOscToFreqmeasTarget = 4u + (FREQMEAS_TARGET_REG << PMUX_SHIFT), + kINPUTMUX_MainClkToFreqmeasTarget = 5u + (FREQMEAS_TARGET_REG << PMUX_SHIFT), + kINPUTMUX_FreqmeGpioClk_aTarget = 6u + (FREQMEAS_TARGET_REG << PMUX_SHIFT), + kINPUTMUX_FreqmeGpioClk_bTarget = 7u + (FREQMEAS_TARGET_REG << PMUX_SHIFT), + + /*!< TIMER3 CAPTSEL. */ + kINPUTMUX_CtimerInp0ToTimer3Captsel = 0U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp1ToTimer3Captsel = 1U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp2ToTimer3Captsel = 2U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp3ToTimer3Captsel = 3U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp4ToTimer3Captsel = 4U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp5ToTimer3Captsel = 5U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp6ToTimer3Captsel = 6U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp7ToTimer3Captsel = 7U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp8ToTimer3Captsel = 8U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp9ToTimer3Captsel = 9U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp10ToTimer3Captsel = 10U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp11ToTimer3Captsel = 11U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp12ToTimer3Captsel = 12U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp13ToTimer3Captsel = 13U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp14ToTimer3Captsel = 14U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp15ToTimer3Captsel = 15U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp16ToTimer3Captsel = 16U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Usb0FrameToggleToTimer3Captsel = 20U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Usb1FrameToggleToTimer3Captsel = 21U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CompOutToTimer3Captsel = 22U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_I2sSharedWs0ToTimer3Captsel = 23U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_I2sSharedWs1ToTimer3Captsel = 24U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + + /*!< Timer4 CAPTSEL. */ + kINPUTMUX_CtimerInp0ToTimer4Captsel = 0U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp1ToTimer4Captsel = 1U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp2ToTimer4Captsel = 2U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp3ToTimer4Captsel = 3U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp4ToTimer4Captsel = 4U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp5ToTimer4Captsel = 5U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp6ToTimer4Captsel = 6U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp7ToTimer4Captsel = 7U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp8ToTimer4Captsel = 8U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp9ToTimer4Captsel = 9U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp10ToTimer4Captsel = 10U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp11ToTimer4Captsel = 11U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp12ToTimer4Captsel = 12U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp13ToTimer4Captsel = 13U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp14ToTimer4Captsel = 14U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp15ToTimer4Captsel = 15U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp16ToTimer4Captsel = 16U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Usb0FrameToggleToTimer4Captsel = 20U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Usb1FrameToggleToTimer4Captsel = 21U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CompOutToTimer4Captsel = 22U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_I2sSharedWs0ToTimer4Captsel = 23U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_I2sSharedWs1ToTimer4Captsel = 24U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + + /*Pin interrupt secure select */ + kINPUTMUX_GpioPort0Pin0ToPintSecsel = 0U + (PINTSECSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin1ToPintSecsel = 1U + (PINTSECSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin2ToPintSecsel = 2U + (PINTSECSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin3ToPintSecsel = 3U + (PINTSECSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin4ToPintSecsel = 4U + (PINTSECSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin5ToPintSecsel = 5U + (PINTSECSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin6ToPintSecsel = 6U + (PINTSECSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin7ToPintSecsel = 7U + (PINTSECSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin8ToPintSecsel = 8U + (PINTSECSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin9ToPintSecsel = 9U + (PINTSECSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin10ToPintSecsel = 10U + (PINTSECSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin11ToPintSecsel = 11U + (PINTSECSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin12ToPintSecsel = 12U + (PINTSECSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin13ToPintSecsel = 13U + (PINTSECSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin14ToPintSecsel = 14U + (PINTSECSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin15ToPintSecsel = 15U + (PINTSECSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin16ToPintSecsel = 16U + (PINTSECSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin17ToPintSecsel = 17U + (PINTSECSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin18ToPintSecsel = 18U + (PINTSECSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin19ToPintSecsel = 19U + (PINTSECSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin20ToPintSecsel = 20U + (PINTSECSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin21ToPintSecsel = 21U + (PINTSECSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin22ToPintSecsel = 22U + (PINTSECSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin23ToPintSecsel = 23U + (PINTSECSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin24ToPintSecsel = 24U + (PINTSECSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin25ToPintSecsel = 25U + (PINTSECSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin26ToPintSecsel = 26U + (PINTSECSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin27ToPintSecsel = 27U + (PINTSECSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin28ToPintSecsel = 28U + (PINTSECSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin29ToPintSecsel = 29U + (PINTSECSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin30ToPintSecsel = 30U + (PINTSECSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin31ToPintSecsel = 31U + (PINTSECSEL0 << PMUX_SHIFT), + + /*!< DMA1 Input trigger. */ + kINPUTMUX_PinInt0ToDma1 = 0U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_PinInt1ToDma1 = 1U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_PinInt2ToDma1 = 2U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_PinInt3ToDma1 = 3U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Ctimer0M0ToDma1 = 4U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Ctimer0M1ToDma1 = 5U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Ctimer2M0ToDma1 = 6U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Ctimer4M0ToDma1 = 7U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Otrig0ToDma1 = 8U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Otrig1ToDma1 = 9U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Otrig2ToDma1 = 10U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Otrig3ToDma1 = 11U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Sct0DmaReq0ToDma1 = 12U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Sct0DmaReq1ToDma1 = 13U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_HashDmaRxToDma1 = 14U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), + + /*!< DMA1 output trigger. */ + kINPUTMUX_Dma1Hash0TxTrigoutToTriginChannels = 0U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma1HsLspiRxTrigoutToTriginChannels = 2U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma1HsLspiTxTrigoutToTriginChannels = 3U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma1Flexcomm0RxTrigoutToTriginChannels = 4U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma1Flexcomm0TxTrigoutToTriginChannels = 5U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma1Flexcomm1RxTrigoutToTriginChannels = 6U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma1Flexcomm1TxTrigoutToTriginChannels = 7U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma1Flexcomm3RxTrigoutToTriginChannels = 8U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma1Flexcomm3TxTrigoutToTriginChannels = 9U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT), +} inputmux_connection_t; + +/*! @brief INPUTMUX signal enable/disable type */ +typedef enum _inputmux_signal_t +{ + /*!< DMA0 REQ signal. */ + kINPUTMUX_HashCryptToDmac0Ch0RequestEna = 0U + (DMA0_REQ_ENA_ID << ENA_SHIFT), + kINPUTMUX_Flexcomm8RxToDmac0Ch2RequestEna = 2U + (DMA0_REQ_ENA_ID << ENA_SHIFT), + kINPUTMUX_Flexcomm8TxToDmac0Ch3RequestEna = 3U + (DMA0_REQ_ENA_ID << ENA_SHIFT), + kINPUTMUX_Flexcomm0RxToDmac0Ch4RequestEna = 4U + (DMA0_REQ_ENA_ID << ENA_SHIFT), + kINPUTMUX_Flexcomm0TxToDmac0Ch5RequestEna = 5U + (DMA0_REQ_ENA_ID << ENA_SHIFT), + kINPUTMUX_Flexcomm1RxToDmac0Ch6RequestEna = 6U + (DMA0_REQ_ENA_ID << ENA_SHIFT), + kINPUTMUX_Flexcomm1TxToDmac0Ch7RequestEna = 7U + (DMA0_REQ_ENA_ID << ENA_SHIFT), + kINPUTMUX_Flexcomm3RxToDmac0Ch8RequestEna = 8U + (DMA0_REQ_ENA_ID << ENA_SHIFT), + kINPUTMUX_Flexcomm3TxToDmac0Ch9RequestEna = 9U + (DMA0_REQ_ENA_ID << ENA_SHIFT), + kINPUTMUX_Flexcomm2RxToDmac0Ch10RequestEna = 10U + (DMA0_REQ_ENA_ID << ENA_SHIFT), + kINPUTMUX_Flexcomm2TxToDmac0Ch11RequestEna = 11U + (DMA0_REQ_ENA_ID << ENA_SHIFT), + kINPUTMUX_Flexcomm4RxToDmac0Ch12RequestEna = 12U + (DMA0_REQ_ENA_ID << ENA_SHIFT), + kINPUTMUX_Flexcomm4TxToDmac0Ch13RequestEna = 13U + (DMA0_REQ_ENA_ID << ENA_SHIFT), + kINPUTMUX_Flexcomm5RxToDmac0Ch14RequestEna = 14U + (DMA0_REQ_ENA_ID << ENA_SHIFT), + kINPUTMUX_Flexcomm5TxToDmac0Ch15RequestEna = 15U + (DMA0_REQ_ENA_ID << ENA_SHIFT), + kINPUTMUX_Flexcomm6RxToDmac0Ch16RequestEna = 16U + (DMA0_REQ_ENA_ID << ENA_SHIFT), + kINPUTMUX_Flexcomm6TxToDmac0Ch17RequestEna = 17U + (DMA0_REQ_ENA_ID << ENA_SHIFT), + kINPUTMUX_Flexcomm7RxToDmac0Ch18RequestEna = 18U + (DMA0_REQ_ENA_ID << ENA_SHIFT), + kINPUTMUX_Flexcomm7TxToDmac0Ch19RequestEna = 19U + (DMA0_REQ_ENA_ID << ENA_SHIFT), + kINPUTMUX_Adc0FIFO0ToDmac0Ch21RequestEna = 21U + (DMA0_REQ_ENA_ID << ENA_SHIFT), + kINPUTMUX_Adc0FIFO1ToDmac0Ch22RequestEna = 22U + (DMA0_REQ_ENA_ID << ENA_SHIFT), + + /*!< DMA1 REQ signal. */ + kINPUTMUX_HashCryptToDmac1Ch0RequestEna = 0U + (DMA1_REQ_ENA_ID << ENA_SHIFT), + kINPUTMUX_Flexcomm8RxToDmac1Ch2RequestEna = 2U + (DMA1_REQ_ENA_ID << ENA_SHIFT), + kINPUTMUX_Flexcomm8TxToDmac1Ch3RequestEna = 3U + (DMA1_REQ_ENA_ID << ENA_SHIFT), + kINPUTMUX_Flexcomm0RxToDmac1Ch4RequestEna = 4U + (DMA1_REQ_ENA_ID << ENA_SHIFT), + kINPUTMUX_Flexcomm0TxToDmac1Ch5RequestEna = 5U + (DMA1_REQ_ENA_ID << ENA_SHIFT), + kINPUTMUX_Flexcomm1RxToDmac1Ch6RequestEna = 6U + (DMA1_REQ_ENA_ID << ENA_SHIFT), + kINPUTMUX_Flexcomm1TxToDmac1Ch7RequestEna = 7U + (DMA1_REQ_ENA_ID << ENA_SHIFT), + kINPUTMUX_Flexcomm3RxToDmac1Ch8RequestEna = 8U + (DMA1_REQ_ENA_ID << ENA_SHIFT), + kINPUTMUX_Flexcomm3TxToDmac1Ch9RequestEna = 9U + (DMA1_REQ_ENA_ID << ENA_SHIFT), + + /*!< DMA0 input trigger source enable. */ + kINPUTMUX_Dmac0InputTriggerPint0Ena = 0U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT), + kINPUTMUX_Dmac0InputTriggerPint1Ena = 1U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT), + kINPUTMUX_Dmac0InputTriggerPint2Ena = 2U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT), + kINPUTMUX_Dmac0InputTriggerPint3Ena = 3U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT), + kINPUTMUX_Dmac0InputTriggerCtimer0M0Ena = 4U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT), + kINPUTMUX_Dmac0InputTriggerCtimer0M1Ena = 5U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT), + kINPUTMUX_Dmac0InputTriggerCtimer1M0Ena = 6U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT), + kINPUTMUX_Dmac0InputTriggerCtimer1M1Ena = 7U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT), + kINPUTMUX_Dmac0InputTriggerCtimer2M0Ena = 8U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT), + kINPUTMUX_Dmac0InputTriggerCtimer2M1Ena = 9U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT), + kINPUTMUX_Dmac0InputTriggerCtimer3M0Ena = 10U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT), + kINPUTMUX_Dmac0InputTriggerCtimer3M1Ena = 11U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT), + kINPUTMUX_Dmac0InputTriggerCtimer4M0Ena = 12U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT), + kINPUTMUX_Dmac0InputTriggerCtimer4M1Ena = 13U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT), + kINPUTMUX_Dmac0InputTriggerCompOutEna = 14U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT), + kINPUTMUX_Dmac0InputTriggerDma0Out0Ena = 15U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT), + kINPUTMUX_Dmac0InputTriggerDma0Out1Ena = 16U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT), + kINPUTMUX_Dmac0InputTriggerDma0Out2Ena = 17U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT), + kINPUTMUX_Dmac0InputTriggerDma0Out3Ena = 18U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT), + kINPUTMUX_Dmac0InputTriggerSctDmac0Ena = 19U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT), + kINPUTMUX_Dmac0InputTriggerSctDmac1Ena = 20U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT), + kINPUTMUX_Dmac0InputTriggerHashOutEna = 21U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT), + + /*!< DMA1 input trigger source enable. */ + kINPUTMUX_Dmac1InputTriggerPint0Ena = 0U + (DMA1_ITRIG_ENA_ID << ENA_SHIFT), + kINPUTMUX_Dmac1InputTriggerPint1Ena = 1U + (DMA1_ITRIG_ENA_ID << ENA_SHIFT), + kINPUTMUX_Dmac1InputTriggerPint2Ena = 2U + (DMA1_ITRIG_ENA_ID << ENA_SHIFT), + kINPUTMUX_Dmac1InputTriggerPint3Ena = 3U + (DMA1_ITRIG_ENA_ID << ENA_SHIFT), + kINPUTMUX_Dmac1InputTriggerCtimer0M0Ena = 4U + (DMA1_ITRIG_ENA_ID << ENA_SHIFT), + kINPUTMUX_Dmac1InputTriggerCtimer0M1Ena = 5U + (DMA1_ITRIG_ENA_ID << ENA_SHIFT), + kINPUTMUX_Dmac1InputTriggerCtimer2M0Ena = 6U + (DMA1_ITRIG_ENA_ID << ENA_SHIFT), + kINPUTMUX_Dmac1InputTriggerCtimer4M0Ena = 7U + (DMA1_ITRIG_ENA_ID << ENA_SHIFT), + kINPUTMUX_Dmac1InputTriggerDma1Out0Ena = 8U + (DMA1_ITRIG_ENA_ID << ENA_SHIFT), + kINPUTMUX_Dmac1InputTriggerDma1Out1Ena = 9U + (DMA1_ITRIG_ENA_ID << ENA_SHIFT), + kINPUTMUX_Dmac1InputTriggerDma1Out2Ena = 10U + (DMA1_ITRIG_ENA_ID << ENA_SHIFT), + kINPUTMUX_Dmac1InputTriggerDma1Out3Ena = 11U + (DMA1_ITRIG_ENA_ID << ENA_SHIFT), + kINPUTMUX_Dmac1InputTriggerSctDmac0Ena = 12U + (DMA1_ITRIG_ENA_ID << ENA_SHIFT), + kINPUTMUX_Dmac1InputTriggerSctDmac1Ena = 13U + (DMA1_ITRIG_ENA_ID << ENA_SHIFT), + kINPUTMUX_Dmac1InputTriggerHashOutEna = 14U + (DMA1_ITRIG_ENA_ID << ENA_SHIFT), +} inputmux_signal_t; + +/*@}*/ + +/*@}*/ + +#endif /* _FSL_INPUTMUX_CONNECTIONS_ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_iocon.h b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_iocon.h new file mode 100644 index 0000000000..e705e91f66 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_iocon.h @@ -0,0 +1,215 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_IOCON_H_ +#define _FSL_IOCON_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup lpc_iocon + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.lpc_iocon" +#endif + +/*! @name Driver version */ +/*@{*/ +/*! @brief IOCON driver version. */ +#define FSL_IOCON_DRIVER_VERSION (MAKE_VERSION(2, 2, 0)) +/*@}*/ + +/** + * @brief Array of IOCON pin definitions passed to IOCON_SetPinMuxing() must be in this format + */ +typedef struct _iocon_group +{ + uint8_t port; /* Pin port */ + uint8_t pin; /* Pin number */ + uint8_t ionumber; /* IO number */ + uint16_t modefunc; /* Function and mode */ +} iocon_group_t; + +/** + * @brief IOCON function and mode selection definitions + * @note See the User Manual for specific modes and functions supported by the various pins. + */ +#define IOCON_FUNC0 0x0 /*!< Selects pin function 0 */ +#define IOCON_FUNC1 0x1 /*!< Selects pin function 1 */ +#define IOCON_FUNC2 0x2 /*!< Selects pin function 2 */ +#define IOCON_FUNC3 0x3 /*!< Selects pin function 3 */ +#define IOCON_FUNC4 0x4 /*!< Selects pin function 4 */ +#define IOCON_FUNC5 0x5 /*!< Selects pin function 5 */ +#define IOCON_FUNC6 0x6 /*!< Selects pin function 6 */ +#define IOCON_FUNC7 0x7 /*!< Selects pin function 7 */ +#if defined(FSL_FEATURE_IOCON_FUNC_FIELD_WIDTH) && (FSL_FEATURE_IOCON_FUNC_FIELD_WIDTH == 4) +#define IOCON_FUNC8 0x8 /*!< Selects pin function 8 */ +#define IOCON_FUNC9 0x9 /*!< Selects pin function 9 */ +#define IOCON_FUNC10 0xA /*!< Selects pin function 10 */ +#define IOCON_FUNC11 0xB /*!< Selects pin function 11 */ +#define IOCON_FUNC12 0xC /*!< Selects pin function 12 */ +#define IOCON_FUNC13 0xD /*!< Selects pin function 13 */ +#define IOCON_FUNC14 0xE /*!< Selects pin function 14 */ +#define IOCON_FUNC15 0xF /*!< Selects pin function 15 */ +#endif /* FSL_FEATURE_IOCON_FUNC_FIELD_WIDTH */ + +#if defined(IOCON_PIO_MODE_SHIFT) +#define IOCON_MODE_INACT (0x0 << IOCON_PIO_MODE_SHIFT) /*!< No addition pin function */ +#define IOCON_MODE_PULLDOWN (0x1 << IOCON_PIO_MODE_SHIFT) /*!< Selects pull-down function */ +#define IOCON_MODE_PULLUP (0x2 << IOCON_PIO_MODE_SHIFT) /*!< Selects pull-up function */ +#define IOCON_MODE_REPEATER (0x3 << IOCON_PIO_MODE_SHIFT) /*!< Selects pin repeater function */ +#endif + +#if defined(IOCON_PIO_I2CSLEW_SHIFT) +#define IOCON_GPIO_MODE (0x1 << IOCON_PIO_I2CSLEW_SHIFT) /*!< GPIO Mode */ +#define IOCON_I2C_MODE (0x0 << IOCON_PIO_I2CSLEW_SHIFT) /*!< I2C Slew Rate Control */ +#define IOCON_I2C_SLEW IOCON_I2C_MODE /*!< Deprecated name for #IOCON_I2C_MODE */ +#endif + +#if defined(IOCON_PIO_EGP_SHIFT) +#define IOCON_GPIO_MODE (0x1 << IOCON_PIO_EGP_SHIFT) /*!< GPIO Mode */ +#define IOCON_I2C_MODE (0x0 << IOCON_PIO_EGP_SHIFT) /*!< I2C Slew Rate Control */ +#define IOCON_I2C_SLEW IOCON_I2C_MODE /*!< Deprecated name for #IOCON_I2C_MODE */ +#endif + +#if defined(IOCON_PIO_SLEW_SHIFT) +#define IOCON_SLEW_STANDARD (0x0 << IOCON_PIO_SLEW_SHIFT) /*!< Driver Slew Rate Control */ +#define IOCON_SLEW_FAST (0x1 << IOCON_PIO_SLEW_SHIFT) /*!< Driver Slew Rate Control */ +#endif + +#if defined(IOCON_PIO_INVERT_SHIFT) +#define IOCON_INV_EN (0x1 << IOCON_PIO_INVERT_SHIFT) /*!< Enables invert function on input */ +#endif + +#if defined(IOCON_PIO_DIGIMODE_SHIFT) +#define IOCON_ANALOG_EN (0x0 << IOCON_PIO_DIGIMODE_SHIFT) /*!< Enables analog function by setting 0 to bit 7 */ +#define IOCON_DIGITAL_EN \ + (0x1 << IOCON_PIO_DIGIMODE_SHIFT) /*!< Enables digital function by setting 1 to bit 7(default) */ +#endif + +#if defined(IOCON_PIO_FILTEROFF_SHIFT) +#define IOCON_INPFILT_OFF (0x1 << IOCON_PIO_FILTEROFF_SHIFT) /*!< Input filter Off for GPIO pins */ +#define IOCON_INPFILT_ON (0x0 << IOCON_PIO_FILTEROFF_SHIFT) /*!< Input filter On for GPIO pins */ +#endif + +#if defined(IOCON_PIO_I2CDRIVE_SHIFT) +#define IOCON_I2C_LOWDRIVER (0x0 << IOCON_PIO_I2CDRIVE_SHIFT) /*!< Low drive, Output drive sink is 4 mA */ +#define IOCON_I2C_HIGHDRIVER (0x1 << IOCON_PIO_I2CDRIVE_SHIFT) /*!< High drive, Output drive sink is 20 mA */ +#endif + +#if defined(IOCON_PIO_OD_SHIFT) +#define IOCON_OPENDRAIN_EN (0x1 << IOCON_PIO_OD_SHIFT) /*!< Enables open-drain function */ +#endif + +#if defined(IOCON_PIO_I2CFILTER_SHIFT) +#define IOCON_I2CFILTER_OFF (0x1 << IOCON_PIO_I2CFILTER_SHIFT) /*!< I2C 50 ns glitch filter enabled */ +#define IOCON_I2CFILTER_ON (0x0 << IOCON_PIO_I2CFILTER_SHIFT) /*!< I2C 50 ns glitch filter not enabled, */ +#endif + +#if defined(IOCON_PIO_ASW_SHIFT) +#define IOCON_AWS_EN (0x1 << IOCON_PIO_ASW_SHIFT) /*!< Enables analog switch function */ +#endif + +#if defined(IOCON_PIO_SSEL_SHIFT) +#define IOCON_SSEL_3V3 (0x0 << IOCON_PIO_SSEL_SHIFT) /*!< 3V3 signaling in I2C mode */ +#define IOCON_SSEL_1V8 (0x1 << IOCON_PIO_SSEL_SHIFT) /*!< 1V8 signaling in I2C mode */ +#endif + +#if defined(IOCON_PIO_ECS_SHIFT) +#define IOCON_ECS_OFF (0x0 << IOCON_PIO_ECS_SHIFT) /*!< IO is an open drain cell */ +#define IOCON_ECS_ON (0x1 << IOCON_PIO_ECS_SHIFT) /*!< Pull-up resistor is connected */ +#endif + +#if defined(IOCON_PIO_S_MODE_SHIFT) +#define IOCON_S_MODE_0CLK (0x0 << IOCON_PIO_S_MODE_SHIFT) /*!< Bypass input filter */ +#define IOCON_S_MODE_1CLK \ + (0x1 << IOCON_PIO_S_MODE_SHIFT) /*!< Input pulses shorter than 1 filter clock are rejected \ \ \ \ \ + */ +#define IOCON_S_MODE_2CLK \ + (0x2 << IOCON_PIO_S_MODE_SHIFT) /*!< Input pulses shorter than 2 filter clock2 are rejected \ \ \ \ \ + */ +#define IOCON_S_MODE_3CLK \ + (0x3 << IOCON_PIO_S_MODE_SHIFT) /*!< Input pulses shorter than 3 filter clock2 are rejected \ \ \ \ \ + */ +#define IOCON_S_MODE(clks) ((clks) << IOCON_PIO_S_MODE_SHIFT) /*!< Select clocks for digital input filter mode */ +#endif + +#if defined(IOCON_PIO_CLK_DIV_SHIFT) +#define IOCON_CLKDIV(div) \ + ((div) \ + << IOCON_PIO_CLK_DIV_SHIFT) /*!< Select peripheral clock divider for input filter sampling clock, 2^n, n=0-6 */ +#endif + +#if defined(__cplusplus) +extern "C" { +#endif + +#if (defined(FSL_FEATURE_IOCON_ONE_DIMENSION) && (FSL_FEATURE_IOCON_ONE_DIMENSION == 1)) +/** + * @brief Sets I/O Control pin mux + * @param base : The base of IOCON peripheral on the chip + * @param ionumber : GPIO number to mux + * @param modefunc : OR'ed values of type IOCON_* + * @return Nothing + */ +__STATIC_INLINE void IOCON_PinMuxSet(IOCON_Type *base, uint8_t ionumber, uint32_t modefunc) +{ + base->PIO[ionumber] = modefunc; +} +#else +/** + * @brief Sets I/O Control pin mux + * @param base : The base of IOCON peripheral on the chip + * @param port : GPIO port to mux + * @param pin : GPIO pin to mux + * @param modefunc : OR'ed values of type IOCON_* + * @return Nothing + */ +__STATIC_INLINE void IOCON_PinMuxSet(IOCON_Type *base, uint8_t port, uint8_t pin, uint32_t modefunc) +{ + base->PIO[port][pin] = modefunc; +} +#endif + +/** + * @brief Set all I/O Control pin muxing + * @param base : The base of IOCON peripheral on the chip + * @param pinArray : Pointer to array of pin mux selections + * @param arrayLength : Number of entries in pinArray + * @return Nothing + */ +__STATIC_INLINE void IOCON_SetPinMuxing(IOCON_Type *base, const iocon_group_t *pinArray, uint32_t arrayLength) +{ + uint32_t i; + + for (i = 0; i < arrayLength; i++) + { +#if (defined(FSL_FEATURE_IOCON_ONE_DIMENSION) && (FSL_FEATURE_IOCON_ONE_DIMENSION == 1)) + IOCON_PinMuxSet(base, pinArray[i].ionumber, pinArray[i].modefunc); +#else + IOCON_PinMuxSet(base, pinArray[i].port, pinArray[i].pin, pinArray[i].modefunc); +#endif /* FSL_FEATURE_IOCON_ONE_DIMENSION */ + } +} + +/* @} */ + +#if defined(__cplusplus) +} +#endif + +#endif /* _FSL_IOCON_H_ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_lpadc.c b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_lpadc.c new file mode 100644 index 0000000000..7835e6fc45 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_lpadc.c @@ -0,0 +1,612 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_lpadc.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.lpadc" +#endif + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Get instance number for LPADC module. + * + * @param base LPADC peripheral base address + */ +static uint32_t LPADC_GetInstance(ADC_Type *base); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Pointers to LPADC bases for each instance. */ +static ADC_Type *const s_lpadcBases[] = ADC_BASE_PTRS; +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Pointers to LPADC clocks for each instance. */ +static const clock_ip_name_t s_lpadcClocks[] = LPADC_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/******************************************************************************* + * Code + ******************************************************************************/ +static uint32_t LPADC_GetInstance(ADC_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_lpadcBases); instance++) + { + if (s_lpadcBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_lpadcBases)); + + return instance; +} + +/*! + * brief Initializes the LPADC module. + * + * param base LPADC peripheral base address. + * param config Pointer to configuration structure. See "lpadc_config_t". + */ +void LPADC_Init(ADC_Type *base, const lpadc_config_t *config) +{ + /* Check if the pointer is available. */ + assert(config != NULL); + + uint32_t tmp32 = 0U; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable the clock for LPADC instance. */ + (void)CLOCK_EnableClock(s_lpadcClocks[LPADC_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + /* Reset the module. */ + LPADC_DoResetConfig(base); +#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) + LPADC_DoResetFIFO0(base); + LPADC_DoResetFIFO1(base); +#else + LPADC_DoResetFIFO(base); +#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ + + /* Disable the module before setting configuration. */ + LPADC_Enable(base, false); + + /* Configure the module generally. */ + if (config->enableInDozeMode) + { + base->CTRL &= ~ADC_CTRL_DOZEN_MASK; + } + else + { + base->CTRL |= ADC_CTRL_DOZEN_MASK; + } + +#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS) && FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS + /* Set calibration average mode. */ + base->CTRL |= ADC_CTRL_CAL_AVGS(config->conversionAverageMode); +#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS */ + +/* ADCx_CFG. */ +#if defined(FSL_FEATURE_LPADC_HAS_CFG_ADCKEN) && FSL_FEATURE_LPADC_HAS_CFG_ADCKEN + if (config->enableInternalClock) + { + tmp32 |= ADC_CFG_ADCKEN_MASK; + } +#endif /* FSL_FEATURE_LPADC_HAS_CFG_ADCKEN */ +#if defined(FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG) && FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG + if (config->enableVref1LowVoltage) + { + tmp32 |= ADC_CFG_VREF1RNG_MASK; + } +#endif /* FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG */ + if (config->enableAnalogPreliminary) + { + tmp32 |= ADC_CFG_PWREN_MASK; + } + tmp32 |= ADC_CFG_PUDLY(config->powerUpDelay) /* Power up delay. */ + | ADC_CFG_REFSEL(config->referenceVoltageSource) /* Reference voltage. */ + | ADC_CFG_PWRSEL(config->powerLevelMode) /* Power configuration. */ + | ADC_CFG_TPRICTRL(config->triggerPriorityPolicy); /* Trigger priority policy. */ + base->CFG = tmp32; + + /* ADCx_PAUSE. */ + if (config->enableConvPause) + { + base->PAUSE = ADC_PAUSE_PAUSEEN_MASK | ADC_PAUSE_PAUSEDLY(config->convPauseDelay); + } + else + { + base->PAUSE = 0U; + } + +#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) + /* ADCx_FCTRL0. */ + base->FCTRL[0] = ADC_FCTRL_FWMARK(config->FIFO0Watermark); + /* ADCx_FCTRL1. */ + base->FCTRL[1] = ADC_FCTRL_FWMARK(config->FIFO1Watermark); +#else + /* ADCx_FCTRL. */ + base->FCTRL = ADC_FCTRL_FWMARK(config->FIFOWatermark); +#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ + + /* Enable the module after setting configuration. */ + LPADC_Enable(base, true); +} + +/*! + * brief Gets an available pre-defined settings for initial configuration. + * + * This function initializes the converter configuration structure with an available settings. The default values are: + * code + * config->enableInDozeMode = true; + * config->conversionAverageMode = kLPADC_ConversionAverage1; + * config->enableAnalogPreliminary = false; + * config->powerUpDelay = 0x80; + * config->referenceVoltageSource = kLPADC_ReferenceVoltageAlt1; + * config->powerLevelMode = kLPADC_PowerLevelAlt1; + * config->triggerPriorityPolicy = kLPADC_TriggerPriorityPreemptImmediately; + * config->enableConvPause = false; + * config->convPauseDelay = 0U; + * config->FIFO0Watermark = 0U; + * config->FIFO1Watermark = 0U; + * config->FIFOWatermark = 0U; + * endcode + * param config Pointer to configuration structure. + */ +void LPADC_GetDefaultConfig(lpadc_config_t *config) +{ + /* Initializes the configure structure to zero. */ + (void)memset(config, 0, sizeof(*config)); + +#if defined(FSL_FEATURE_LPADC_HAS_CFG_ADCKEN) && FSL_FEATURE_LPADC_HAS_CFG_ADCKEN + config->enableInternalClock = false; +#endif /* FSL_FEATURE_LPADC_HAS_CFG_ADCKEN */ +#if defined(FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG) && FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG + config->enableVref1LowVoltage = false; +#endif /* FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG */ + config->enableInDozeMode = true; +#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS) && FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS + /* Set calibration average mode. */ + config->conversionAverageMode = kLPADC_ConversionAverage1; +#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS */ + config->enableAnalogPreliminary = false; + config->powerUpDelay = 0x80; + config->referenceVoltageSource = kLPADC_ReferenceVoltageAlt1; + config->powerLevelMode = kLPADC_PowerLevelAlt1; + config->triggerPriorityPolicy = kLPADC_TriggerPriorityPreemptImmediately; + config->enableConvPause = false; + config->convPauseDelay = 0U; +#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) + config->FIFO0Watermark = 0U; + config->FIFO1Watermark = 0U; +#else + config->FIFOWatermark = 0U; +#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ +} + +/*! + * brief De-initializes the LPADC module. + * + * param base LPADC peripheral base address. + */ +void LPADC_Deinit(ADC_Type *base) +{ + /* Disable the module. */ + LPADC_Enable(base, false); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Gate the clock. */ + (void)CLOCK_DisableClock(s_lpadcClocks[LPADC_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) +/*! + * brief Get the result in conversion FIFOn. + * + * param base LPADC peripheral base address. + * param result Pointer to structure variable that keeps the conversion result in conversion FIFOn. + * param index Result FIFO index. + * + * return Status whether FIFOn entry is valid. + */ +bool LPADC_GetConvResult(ADC_Type *base, lpadc_conv_result_t *result, uint8_t index) +{ + assert(result != NULL); /* Check if the input pointer is available. */ + + uint32_t tmp32; + + tmp32 = base->RESFIFO[index]; + + if (0U == (ADC_RESFIFO_VALID_MASK & tmp32)) + { + return false; /* FIFO is empty. Discard any read from RESFIFO. */ + } + + result->commandIdSource = (tmp32 & ADC_RESFIFO_CMDSRC_MASK) >> ADC_RESFIFO_CMDSRC_SHIFT; + result->loopCountIndex = (tmp32 & ADC_RESFIFO_LOOPCNT_MASK) >> ADC_RESFIFO_LOOPCNT_SHIFT; + result->triggerIdSource = (tmp32 & ADC_RESFIFO_TSRC_MASK) >> ADC_RESFIFO_TSRC_SHIFT; + result->convValue = (uint16_t)(tmp32 & ADC_RESFIFO_D_MASK); + + return true; +} +#else +/*! + * brief Get the result in conversion FIFO. + * + * param base LPADC peripheral base address. + * param result Pointer to structure variable that keeps the conversion result in conversion FIFO. + * + * return Status whether FIFO entry is valid. + */ +bool LPADC_GetConvResult(ADC_Type *base, lpadc_conv_result_t *result) +{ + assert(result != NULL); /* Check if the input pointer is available. */ + + uint32_t tmp32; + + tmp32 = base->RESFIFO; + + if (0U == (ADC_RESFIFO_VALID_MASK & tmp32)) + { + return false; /* FIFO is empty. Discard any read from RESFIFO. */ + } + + result->commandIdSource = (tmp32 & ADC_RESFIFO_CMDSRC_MASK) >> ADC_RESFIFO_CMDSRC_SHIFT; + result->loopCountIndex = (tmp32 & ADC_RESFIFO_LOOPCNT_MASK) >> ADC_RESFIFO_LOOPCNT_SHIFT; + result->triggerIdSource = (tmp32 & ADC_RESFIFO_TSRC_MASK) >> ADC_RESFIFO_TSRC_SHIFT; + result->convValue = (uint16_t)(tmp32 & ADC_RESFIFO_D_MASK); + + return true; +} +#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ + +/*! + * brief Configure the conversion trigger source. + * + * Each programmable trigger can launch the conversion command in command buffer. + * + * param base LPADC peripheral base address. + * param triggerId ID for each trigger. Typically, the available value range is from 0. + * param config Pointer to configuration structure. See to #lpadc_conv_trigger_config_t. + */ +void LPADC_SetConvTriggerConfig(ADC_Type *base, uint32_t triggerId, const lpadc_conv_trigger_config_t *config) +{ + assert(triggerId < ADC_TCTRL_COUNT); /* Check if the triggerId is available in this device. */ + assert(config != NULL); /* Check if the input pointer is available. */ + + uint32_t tmp32; + + tmp32 = ADC_TCTRL_TCMD(config->targetCommandId) /* Trigger command select. */ + | ADC_TCTRL_TDLY(config->delayPower) /* Trigger delay select. */ + | ADC_TCTRL_TPRI(config->priority) /* Trigger priority setting. */ +#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) + | ADC_TCTRL_FIFO_SEL_A(config->channelAFIFOSelect) +#if !(defined(FSL_FEATURE_LPADC_HAS_NO_TCTRL_FIFO_SEL_B) && FSL_FEATURE_LPADC_HAS_NO_TCTRL_FIFO_SEL_B) + | ADC_TCTRL_FIFO_SEL_B(config->channelBFIFOSelect) +#endif /* FSL_FEATURE_LPADC_HAS_NO_TCTRL_FIFO_SEL_B */ +#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ + ; + if (config->enableHardwareTrigger) + { + tmp32 |= ADC_TCTRL_HTEN_MASK; + } + + base->TCTRL[triggerId] = tmp32; +} + +/*! + * brief Gets an available pre-defined settings for trigger's configuration. + * + * This function initializes the trigger's configuration structure with an available settings. The default values are: + * code + * config->commandIdSource = 0U; + * config->loopCountIndex = 0U; + * config->triggerIdSource = 0U; + * config->enableHardwareTrigger = false; + * config->channelAFIFOSelect = 0U; + * config->channelBFIFOSelect = 0U; + * endcode + * param config Pointer to configuration structure. + */ +void LPADC_GetDefaultConvTriggerConfig(lpadc_conv_trigger_config_t *config) +{ + assert(config != NULL); /* Check if the input pointer is available. */ + + /* Initializes the configure structure to zero. */ + (void)memset(config, 0, sizeof(*config)); + + config->targetCommandId = 0U; + config->delayPower = 0U; + config->priority = 0U; +#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) + config->channelAFIFOSelect = 0U; + config->channelBFIFOSelect = 0U; +#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ + config->enableHardwareTrigger = false; +} + +/*! + * brief Configure conversion command. + * + * param base LPADC peripheral base address. + * param commandId ID for command in command buffer. Typically, the available value range is 1 - 15. + * param config Pointer to configuration structure. See to #lpadc_conv_command_config_t. + */ +void LPADC_SetConvCommandConfig(ADC_Type *base, uint32_t commandId, const lpadc_conv_command_config_t *config) +{ + assert(commandId < (ADC_CMDL_COUNT + 1U)); /* Check if the commandId is available on this device. */ + assert(config != NULL); /* Check if the input pointer is available. */ + + uint32_t tmp32 = 0; + + commandId--; /* The available command number are 1-15, while the index of register group are 0-14. */ + + /* ADCx_CMDL. */ + tmp32 = ADC_CMDL_ADCH(config->channelNumber); /* Channel number. */ +#if defined(FSL_FEATURE_LPADC_HAS_CMDL_CSCALE) && FSL_FEATURE_LPADC_HAS_CMDL_CSCALE + tmp32 |= ADC_CMDL_CSCALE(config->sampleScaleMode); /* Full/Part scale input voltage. */ +#endif /* FSL_FEATURE_LPADC_HAS_CMDL_CSCALE */ +#if defined(FSL_FEATURE_LPADC_HAS_CMDL_CTYPE) && FSL_FEATURE_LPADC_HAS_CMDL_CTYPE + tmp32 |= ADC_CMDL_CTYPE(config->sampleChannelMode); +#else + switch (config->sampleChannelMode) /* Sample input. */ + { + case kLPADC_SampleChannelSingleEndSideB: + tmp32 |= ADC_CMDL_ABSEL_MASK; + break; +#if defined(FSL_FEATURE_LPADC_HAS_CMDL_DIFF) && FSL_FEATURE_LPADC_HAS_CMDL_DIFF + case kLPADC_SampleChannelDiffBothSideAB: + tmp32 |= ADC_CMDL_DIFF_MASK; + break; + case kLPADC_SampleChannelDiffBothSideBA: + tmp32 |= ADC_CMDL_ABSEL_MASK | ADC_CMDL_DIFF_MASK; + break; +#endif /* FSL_FEATURE_LPADC_HAS_CMDL_DIFF */ + default: /* kLPADC_SampleChannelSingleEndSideA. */ + break; + } +#endif /* FSL_FEATURE_LPADC_HAS_CMDL_CTYPE */ +#if defined(FSL_FEATURE_LPADC_HAS_CMDL_MODE) && FSL_FEATURE_LPADC_HAS_CMDL_MODE + tmp32 |= ADC_CMDL_MODE(config->conversionResolutionMode); +#endif /* FSL_FEATURE_LPADC_HAS_CMDL_MODE */ + base->CMD[commandId].CMDL = tmp32; + + /* ADCx_CMDH. */ + tmp32 = ADC_CMDH_NEXT(config->chainedNextCommandNumber) /* Next Command Select. */ + | ADC_CMDH_LOOP(config->loopCount) /* Loop Count Select. */ + | ADC_CMDH_AVGS(config->hardwareAverageMode) /* Hardware Average Select. */ + | ADC_CMDH_STS(config->sampleTimeMode) /* Sample Time Select. */ + | ADC_CMDH_CMPEN(config->hardwareCompareMode); /* Hardware compare enable. */ +#if (defined(FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG) && FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG) + if (config->enableWaitTrigger) + { + tmp32 |= ADC_CMDH_WAIT_TRIG_MASK; /* Wait trigger enable. */ + } +#endif /* FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG */ + + if (config->enableAutoChannelIncrement) + { + tmp32 |= ADC_CMDH_LWI_MASK; + } + base->CMD[commandId].CMDH = tmp32; + + /* Hardware compare settings. + * Not all Command Buffers have an associated Compare Value register. The compare function is only available on + * Command Buffers that have a corresponding Compare Value register. + */ + if (kLPADC_HardwareCompareDisabled != config->hardwareCompareMode) + { + /* Check if the hardware compare feature is available for indicated command buffer. */ + assert(commandId < ADC_CV_COUNT); + + /* Set CV register. */ + base->CV[commandId] = ADC_CV_CVH(config->hardwareCompareValueHigh) /* Compare value high. */ + | ADC_CV_CVL(config->hardwareCompareValueLow); /* Compare value low. */ + } +} + +/*! + * brief Gets an available pre-defined settings for conversion command's configuration. + * + * This function initializes the conversion command's configuration structure with an available settings. The default + * values are: + * code + * config->sampleScaleMode = kLPADC_SampleFullScale; + * config->channelSampleMode = kLPADC_SampleChannelSingleEndSideA; + * config->channelNumber = 0U; + * config->chainedNextCmdNumber = 0U; + * config->enableAutoChannelIncrement = false; + * config->loopCount = 0U; + * config->hardwareAverageMode = kLPADC_HardwareAverageCount1; + * config->sampleTimeMode = kLPADC_SampleTimeADCK3; + * config->hardwareCompareMode = kLPADC_HardwareCompareDisabled; + * config->hardwareCompareValueHigh = 0U; + * config->hardwareCompareValueLow = 0U; + * config->conversionResolutionMode = kLPADC_ConversionResolutionStandard; + * config->enableWaitTrigger = false; + * endcode + * param config Pointer to configuration structure. + */ +void LPADC_GetDefaultConvCommandConfig(lpadc_conv_command_config_t *config) +{ + assert(config != NULL); /* Check if the input pointer is available. */ + + /* Initializes the configure structure to zero. */ + (void)memset(config, 0, sizeof(*config)); + +#if defined(FSL_FEATURE_LPADC_HAS_CMDL_CSCALE) && FSL_FEATURE_LPADC_HAS_CMDL_CSCALE + config->sampleScaleMode = kLPADC_SampleFullScale; +#endif /* FSL_FEATURE_LPADC_HAS_CMDL_CSCALE */ + config->sampleChannelMode = kLPADC_SampleChannelSingleEndSideA; + config->channelNumber = 0U; + config->chainedNextCommandNumber = 0U; /* No next command defined. */ + config->enableAutoChannelIncrement = false; + config->loopCount = 0U; + config->hardwareAverageMode = kLPADC_HardwareAverageCount1; + config->sampleTimeMode = kLPADC_SampleTimeADCK3; + config->hardwareCompareMode = kLPADC_HardwareCompareDisabled; + config->hardwareCompareValueHigh = 0U; /* No used. */ + config->hardwareCompareValueLow = 0U; /* No used. */ +#if defined(FSL_FEATURE_LPADC_HAS_CMDL_MODE) && FSL_FEATURE_LPADC_HAS_CMDL_MODE + config->conversionResolutionMode = kLPADC_ConversionResolutionStandard; +#endif /* FSL_FEATURE_LPADC_HAS_CMDL_MODE */ +#if defined(FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG) && FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG + config->enableWaitTrigger = false; +#endif /* FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG */ +} + +#if defined(FSL_FEATURE_LPADC_HAS_CFG_CALOFS) && FSL_FEATURE_LPADC_HAS_CFG_CALOFS +/*! + * brief Enable the calibration function. + * + * When CALOFS is set, the ADC is configured to perform a calibration function anytime the ADC executes + * a conversion. Any channel selected is ignored and the value returned in the RESFIFO is a signed value + * between -31 and 31. -32 is not a valid and is never a returned value. Software should copy the lower 6- + * bits of the conversion result stored in the RESFIFO after a completed calibration conversion to the + * OFSTRIM field. The OFSTRIM field is used in normal operation for offset correction. + * + * param base LPADC peripheral base address. + * param enable switcher to the calibration function. + */ +void LPADC_EnableCalibration(ADC_Type *base, bool enable) +{ + LPADC_Enable(base, false); + if (enable) + { + base->CFG |= ADC_CFG_CALOFS_MASK; + } + else + { + base->CFG &= ~ADC_CFG_CALOFS_MASK; + } + LPADC_Enable(base, true); +} + +#if defined(FSL_FEATURE_LPADC_HAS_OFSTRIM) && FSL_FEATURE_LPADC_HAS_OFSTRIM +/*! + * brief Do auto calibration. + * + * Calibration function should be executed before using converter in application. It used the software trigger and a + * dummy conversion, get the offset and write them into the OFSTRIM register. It called some of functional API + * including: -LPADC_EnableCalibration(...) -LPADC_LPADC_SetOffsetValue(...) -LPADC_SetConvCommandConfig(...) + * -LPADC_SetConvTriggerConfig(...) + * + * param base LPADC peripheral base address. + */ +void LPADC_DoAutoCalibration(ADC_Type *base) +{ + assert(0u == LPADC_GetConvResultCount(base)); + + uint32_t mLpadcCMDL; + uint32_t mLpadcCMDH; + uint32_t mLpadcTrigger; + lpadc_conv_trigger_config_t mLpadcTriggerConfigStruct; + lpadc_conv_command_config_t mLpadcCommandConfigStruct; + lpadc_conv_result_t mLpadcResultConfigStruct; + + /* Enable the calibration function. */ + LPADC_EnableCalibration(base, true); + + /* Keep the CMD and TRG state here and restore it later if the calibration completes.*/ + mLpadcCMDL = base->CMD[0].CMDL; /* CMD1L. */ + mLpadcCMDH = base->CMD[0].CMDH; /* CMD1H. */ + mLpadcTrigger = base->TCTRL[0]; /* Trigger0. */ + + /* Set trigger0 configuration - for software trigger. */ + LPADC_GetDefaultConvTriggerConfig(&mLpadcTriggerConfigStruct); + mLpadcTriggerConfigStruct.targetCommandId = 1U; /* CMD1 is executed. */ + LPADC_SetConvTriggerConfig(base, 0U, &mLpadcTriggerConfigStruct); /* Configurate the trigger0. */ + + /* Set conversion CMD configuration. */ + LPADC_GetDefaultConvCommandConfig(&mLpadcCommandConfigStruct); + mLpadcCommandConfigStruct.hardwareAverageMode = kLPADC_HardwareAverageCount128; + LPADC_SetConvCommandConfig(base, 1U, &mLpadcCommandConfigStruct); /* Set CMD1 configuration. */ + + /* Do calibration. */ + LPADC_DoSoftwareTrigger(base, 1U); /* 1U is trigger0 mask. */ + while (!LPADC_GetConvResult(base, &mLpadcResultConfigStruct)) + { + } + /* The valid bits of data are bits 14:3 in the RESFIFO register. */ + LPADC_SetOffsetValue(base, (uint32_t)(mLpadcResultConfigStruct.convValue) >> 3UL); + /* Disable the calibration function. */ + LPADC_EnableCalibration(base, false); + + /* restore CMD and TRG registers. */ + base->CMD[0].CMDL = mLpadcCMDL; /* CMD1L. */ + base->CMD[0].CMDH = mLpadcCMDH; /* CMD1H. */ + base->TCTRL[0] = mLpadcTrigger; /* Trigger0. */ +} +#endif /* FSL_FEATURE_LPADC_HAS_OFSTRIM */ +#endif /* FSL_FEATURE_LPADC_HAS_CFG_CALOFS */ + +#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CALOFS) && FSL_FEATURE_LPADC_HAS_CTRL_CALOFS +/*! + * brief Do offset calibration. + * + * param base LPADC peripheral base address. + */ +void LPADC_DoOffsetCalibration(ADC_Type *base) +{ + LPADC_EnableOffsetCalibration(base, true); + while (ADC_STAT_CAL_RDY_MASK != (base->STAT & ADC_STAT_CAL_RDY_MASK)) + { + } +} + +#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ) && FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ +/*! + * brief Do auto calibration. + * + * param base LPADC peripheral base address. + */ +void LPADC_DoAutoCalibration(ADC_Type *base) +{ + assert((0u == LPADC_GetConvResultCount(base, 0)) && (0u == LPADC_GetConvResultCount(base, 1))); + + uint32_t GCCa; + uint32_t GCCb; + uint32_t GCRa; + uint32_t GCRb; + + /* Request gain calibration. */ + base->CTRL |= ADC_CTRL_CAL_REQ_MASK; + while ((ADC_GCC_RDY_MASK != (base->GCC[0] & ADC_GCC_RDY_MASK)) || + (ADC_GCC_RDY_MASK != (base->GCC[1] & ADC_GCC_RDY_MASK))) + { + } + + /* Calculate gain offset. */ + GCCa = (base->GCC[0] & ADC_GCC_GAIN_CAL_MASK); + GCCb = (base->GCC[1] & ADC_GCC_GAIN_CAL_MASK); + GCRa = (uint16_t)((GCCa << 16U) / + (0x1FFFFU - GCCa)); /* Gain_CalA = (131072 / (131072-(ADC_GCC_GAIN_CAL(ADC0->GCC[0])) - 1. */ + GCRb = (uint16_t)((GCCb << 16U) / + (0x1FFFFU - GCCb)); /* Gain_CalB = (131072 / (131072-(ADC_GCC_GAIN_CAL(ADC0->GCC[1])) - 1. */ + base->GCR[0] = ADC_GCR_GCALR(GCRa); + base->GCR[1] = ADC_GCR_GCALR(GCRb); + + /* Indicate the values are valid. */ + base->GCR[0] |= ADC_GCR_RDY_MASK; + base->GCR[1] |= ADC_GCR_RDY_MASK; + + while (ADC_STAT_CAL_RDY_MASK != (base->STAT & ADC_STAT_CAL_RDY_MASK)) + { + } +} +#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ */ +#endif /* FSL_FEATURE_LPADC_HAS_CFG_CALOFS */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_lpadc.h b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_lpadc.h new file mode 100644 index 0000000000..d3e5a9ec30 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_lpadc.h @@ -0,0 +1,964 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_LPADC_H_ +#define _FSL_LPADC_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup lpadc + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief LPADC driver version 2.5.1. */ +#define FSL_LPADC_DRIVER_VERSION (MAKE_VERSION(2, 5, 1)) +/*@}*/ + +/*! + * @brief Define the MACRO function to get command status from status value. + * + * The statusVal is the return value from LPADC_GetStatusFlags(). + */ +#define LPADC_GET_ACTIVE_COMMAND_STATUS(statusVal) ((statusVal & ADC_STAT_CMDACT_MASK) >> ADC_STAT_CMDACT_SHIFT) + +/*! + * @brief Define the MACRO function to get trigger status from status value. + * + * The statusVal is the return value from LPADC_GetStatusFlags(). + */ +#define LPADC_GET_ACTIVE_TRIGGER_STATUE(statusVal) ((statusVal & ADC_STAT_TRGACT_MASK) >> ADC_STAT_TRGACT_SHIFT) + +#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) +/*! + * @brief Define hardware flags of the module. + */ +enum _lpadc_status_flags +{ + kLPADC_ResultFIFO0OverflowFlag = ADC_STAT_FOF0_MASK, /*!< Indicates that more data has been written to the Result + FIFO 0 than it can hold. */ + kLPADC_ResultFIFO0ReadyFlag = ADC_STAT_RDY0_MASK, /*!< Indicates when the number of valid datawords in the result + FIFO 0 is greater than the setting watermark level. */ + kLPADC_ResultFIFO1OverflowFlag = ADC_STAT_FOF1_MASK, /*!< Indicates that more data has been written to the Result + FIFO 1 than it can hold. */ + kLPADC_ResultFIFO1ReadyFlag = ADC_STAT_RDY1_MASK, /*!< Indicates when the number of valid datawords in the result + FIFO 1 is greater than the setting watermark level. */ +}; + +/*! + * @brief Define interrupt switchers of the module. + */ +enum _lpadc_interrupt_enable +{ + kLPADC_ResultFIFO0OverflowInterruptEnable = ADC_IE_FOFIE0_MASK, /*!< Configures ADC to generate overflow interrupt + requests when FOF0 flag is asserted. */ + kLPADC_FIFO0WatermarkInterruptEnable = ADC_IE_FWMIE0_MASK, /*!< Configures ADC to generate watermark interrupt + requests when RDY0 flag is asserted. */ + kLPADC_ResultFIFO1OverflowInterruptEnable = ADC_IE_FOFIE1_MASK, /*!< Configures ADC to generate overflow interrupt + requests when FOF1 flag is asserted. */ + kLPADC_FIFO1WatermarkInterruptEnable = ADC_IE_FWMIE1_MASK, /*!< Configures ADC to generate watermark interrupt + requests when RDY1 flag is asserted. */ +#if (defined(FSL_FEATURE_LPADC_HAS_TSTAT) && FSL_FEATURE_LPADC_HAS_TSTAT) + kLPADC_TriggerExceptionInterruptEnable = ADC_IE_TEXC_IE_MASK, /*!< Configures ADC to generate trigger exception + interrupt. */ + kLPADC_Trigger0CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 0UL), /*!< Configures ADC to generate interrupt + when trigger 0 completion. */ + kLPADC_Trigger1CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 1UL), /*!< Configures ADC to generate interrupt + when trigger 1 completion. */ + kLPADC_Trigger2CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 2UL), /*!< Configures ADC to generate interrupt + when trigger 2 completion. */ + kLPADC_Trigger3CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 3UL), /*!< Configures ADC to generate interrupt + when trigger 3 completion. */ + kLPADC_Trigger4CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 4UL), /*!< Configures ADC to generate interrupt + when trigger 4 completion. */ + kLPADC_Trigger5CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 5UL), /*!< Configures ADC to generate interrupt + when trigger 5 completion. */ + kLPADC_Trigger6CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 6UL), /*!< Configures ADC to generate interrupt + when trigger 6 completion. */ + kLPADC_Trigger7CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 7UL), /*!< Configures ADC to generate interrupt + when trigger 7 completion. */ + kLPADC_Trigger8CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 8UL), /*!< Configures ADC to generate interrupt + when trigger 8 completion. */ + kLPADC_Trigger9CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 9UL), /*!< Configures ADC to generate interrupt + when trigger 9 completion. */ + kLPADC_Trigger10CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 10UL), /*!< Configures ADC to generate interrupt + when trigger 10 completion. */ + kLPADC_Trigger11CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 11UL), /*!< Configures ADC to generate interrupt + when trigger 11 completion. */ + kLPADC_Trigger12CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 12UL), /*!< Configures ADC to generate interrupt + when trigger 12 completion. */ + kLPADC_Trigger13CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 13UL), /*!< Configures ADC to generate interrupt + when trigger 13 completion. */ + kLPADC_Trigger14CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 14UL), /*!< Configures ADC to generate interrupt + when trigger 14 completion. */ + kLPADC_Trigger15CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 15UL), /*!< Configures ADC to generate interrupt + when trigger 15 completion. */ +#endif /* FSL_FEATURE_LPADC_HAS_TSTAT */ +}; +#else +/*! + * @brief Define hardware flags of the module. + */ +enum _lpadc_status_flags +{ + kLPADC_ResultFIFOOverflowFlag = ADC_STAT_FOF_MASK, /*!< Indicates that more data has been written to the Result FIFO + than it can hold. */ + kLPADC_ResultFIFOReadyFlag = ADC_STAT_RDY_MASK, /*!< Indicates when the number of valid datawords in the result FIFO + is greater than the setting watermark level. */ +}; + +/*! + * @brief Define interrupt switchers of the module. + */ +enum _lpadc_interrupt_enable +{ + kLPADC_ResultFIFOOverflowInterruptEnable = ADC_IE_FOFIE_MASK, /*!< Configures ADC to generate overflow interrupt + requests when FOF flag is asserted. */ + kLPADC_FIFOWatermarkInterruptEnable = ADC_IE_FWMIE_MASK, /*!< Configures ADC to generate watermark interrupt + requests when RDY flag is asserted. */ +}; +#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ + +#if (defined(FSL_FEATURE_LPADC_HAS_TSTAT) && FSL_FEATURE_LPADC_HAS_TSTAT) +/*! + * @brief The enumerator of lpadc trigger status flags, including interrupted flags and completed flags. + */ +enum _lpadc_trigger_status_flags +{ + kLPADC_Trigger0InterruptedFlag = 1UL << 0UL, /*!< Trigger 0 is interrupted by a high priority exception. */ + kLPADC_Trigger1InterruptedFlag = 1UL << 1UL, /*!< Trigger 1 is interrupted by a high priority exception. */ + kLPADC_Trigger2InterruptedFlag = 1UL << 2UL, /*!< Trigger 2 is interrupted by a high priority exception. */ + kLPADC_Trigger3InterruptedFlag = 1UL << 3UL, /*!< Trigger 3 is interrupted by a high priority exception. */ + kLPADC_Trigger4InterruptedFlag = 1UL << 4UL, /*!< Trigger 4 is interrupted by a high priority exception. */ + kLPADC_Trigger5InterruptedFlag = 1UL << 5UL, /*!< Trigger 5 is interrupted by a high priority exception. */ + kLPADC_Trigger6InterruptedFlag = 1UL << 6UL, /*!< Trigger 6 is interrupted by a high priority exception. */ + kLPADC_Trigger7InterruptedFlag = 1UL << 7UL, /*!< Trigger 7 is interrupted by a high priority exception. */ + kLPADC_Trigger8InterruptedFlag = 1UL << 8UL, /*!< Trigger 8 is interrupted by a high priority exception. */ + kLPADC_Trigger9InterruptedFlag = 1UL << 9UL, /*!< Trigger 9 is interrupted by a high priority exception. */ + kLPADC_Trigger10InterruptedFlag = 1UL << 10UL, /*!< Trigger 10 is interrupted by a high priority exception. */ + kLPADC_Trigger11InterruptedFlag = 1UL << 11UL, /*!< Trigger 11 is interrupted by a high priority exception. */ + kLPADC_Trigger12InterruptedFlag = 1UL << 12UL, /*!< Trigger 12 is interrupted by a high priority exception. */ + kLPADC_Trigger13InterruptedFlag = 1UL << 13UL, /*!< Trigger 13 is interrupted by a high priority exception. */ + kLPADC_Trigger14InterruptedFlag = 1UL << 14UL, /*!< Trigger 14 is interrupted by a high priority exception. */ + kLPADC_Trigger15InterruptedFlag = 1UL << 15UL, /*!< Trigger 15 is interrupted by a high priority exception. */ + + kLPADC_Trigger0CompletedFlag = 1UL << 16UL, /*!< Trigger 0 is completed and + trigger 0 has enabled completion interrupts. */ + kLPADC_Trigger1CompletedFlag = 1UL << 17UL, /*!< Trigger 1 is completed and + trigger 1 has enabled completion interrupts. */ + kLPADC_Trigger2CompletedFlag = 1UL << 18UL, /*!< Trigger 2 is completed and + trigger 2 has enabled completion interrupts. */ + kLPADC_Trigger3CompletedFlag = 1UL << 19UL, /*!< Trigger 3 is completed and + trigger 3 has enabled completion interrupts. */ + kLPADC_Trigger4CompletedFlag = 1UL << 20UL, /*!< Trigger 4 is completed and + trigger 4 has enabled completion interrupts. */ + kLPADC_Trigger5CompletedFlag = 1UL << 21UL, /*!< Trigger 5 is completed and + trigger 5 has enabled completion interrupts. */ + kLPADC_Trigger6CompletedFlag = 1UL << 22UL, /*!< Trigger 6 is completed and + trigger 6 has enabled completion interrupts. */ + kLPADC_Trigger7CompletedFlag = 1UL << 23UL, /*!< Trigger 7 is completed and + trigger 7 has enabled completion interrupts. */ + kLPADC_Trigger8CompletedFlag = 1UL << 24UL, /*!< Trigger 8 is completed and + trigger 8 has enabled completion interrupts. */ + kLPADC_Trigger9CompletedFlag = 1UL << 25UL, /*!< Trigger 9 is completed and + trigger 9 has enabled completion interrupts. */ + kLPADC_Trigger10CompletedFlag = 1UL << 26UL, /*!< Trigger 10 is completed and + trigger 10 has enabled completion interrupts. */ + kLPADC_Trigger11CompletedFlag = 1UL << 27UL, /*!< Trigger 11 is completed and + trigger 11 has enabled completion interrupts. */ + kLPADC_Trigger12CompletedFlag = 1UL << 28UL, /*!< Trigger 12 is completed and + trigger 12 has enabled completion interrupts. */ + kLPADC_Trigger13CompletedFlag = 1UL << 29UL, /*!< Trigger 13 is completed and + trigger 13 has enabled completion interrupts. */ + kLPADC_Trigger14CompletedFlag = 1UL << 30UL, /*!< Trigger 14 is completed and + trigger 14 has enabled completion interrupts. */ + kLPADC_Trigger15CompletedFlag = 1UL << 31UL, /*!< Trigger 15 is completed and + trigger 15 has enabled completion interrupts. */ +}; +#endif /* FSL_FEATURE_LPADC_HAS_TSTAT */ + +/*! + * @brief Define enumeration of sample scale mode. + * + * The sample scale mode is used to reduce the selected ADC analog channel input voltage level by a factor. The maximum + * possible voltage on the ADC channel input should be considered when selecting a scale mode to ensure that the + * reducing factor always results voltage level at or below the VREFH reference. This reducing capability allows + * conversion of analog inputs higher than VREFH. A-side and B-side channel inputs are both scaled using the scale mode. + */ +typedef enum _lpadc_sample_scale_mode +{ + kLPADC_SamplePartScale = 0U, /*!< Use divided input voltage signal. (Factor of 30/64). */ + kLPADC_SampleFullScale = 1U, /*!< Full scale (Factor of 1). */ +} lpadc_sample_scale_mode_t; + +/*! + * @brief Define enumeration of channel sample mode. + * + * The channel sample mode configures the channel with single-end/differential/dual-single-end, side A/B. + */ +typedef enum _lpadc_sample_channel_mode +{ + kLPADC_SampleChannelSingleEndSideA = 0U, /*!< Single end mode, using side A. */ + kLPADC_SampleChannelSingleEndSideB = 1U, /*!< Single end mode, using side B. */ +#if defined(FSL_FEATURE_LPADC_HAS_CMDL_DIFF) && FSL_FEATURE_LPADC_HAS_CMDL_DIFF + kLPADC_SampleChannelDiffBothSideAB = 2U, /*!< Differential mode, using A as plus side and B as minus side. */ + kLPADC_SampleChannelDiffBothSideBA = 3U, /*!< Differential mode, using B as plus side and A as minus side. */ +#elif defined(FSL_FEATURE_LPADC_HAS_CMDL_CTYPE) && FSL_FEATURE_LPADC_HAS_CMDL_CTYPE + kLPADC_SampleChannelDiffBothSide = 2U, /*!< Differential mode, using A and B. */ + kLPADC_SampleChannelDualSingleEndBothSide = + 3U, /*!< Dual-Single-Ended Mode. Both A side and B side channels are converted independently. */ +#endif +} lpadc_sample_channel_mode_t; + +/*! + * @brief Define enumeration of hardware average selection. + * + * It Selects how many ADC conversions are averaged to create the ADC result. An internal storage buffer is used to + * capture temporary results while the averaging iterations are executed. + */ +typedef enum _lpadc_hardware_average_mode +{ + kLPADC_HardwareAverageCount1 = 0U, /*!< Single conversion. */ + kLPADC_HardwareAverageCount2 = 1U, /*!< 2 conversions averaged. */ + kLPADC_HardwareAverageCount4 = 2U, /*!< 4 conversions averaged. */ + kLPADC_HardwareAverageCount8 = 3U, /*!< 8 conversions averaged. */ + kLPADC_HardwareAverageCount16 = 4U, /*!< 16 conversions averaged. */ + kLPADC_HardwareAverageCount32 = 5U, /*!< 32 conversions averaged. */ + kLPADC_HardwareAverageCount64 = 6U, /*!< 64 conversions averaged. */ + kLPADC_HardwareAverageCount128 = 7U, /*!< 128 conversions averaged. */ +} lpadc_hardware_average_mode_t; + +/*! + * @brief Define enumeration of sample time selection. + * + * The shortest sample time maximizes conversion speed for lower impedance inputs. Extending sample time allows higher + * impedance inputs to be accurately sampled. Longer sample times can also be used to lower overall power consumption + * when command looping and sequencing is configured and high conversion rates are not required. + */ +typedef enum _lpadc_sample_time_mode +{ + kLPADC_SampleTimeADCK3 = 0U, /*!< 3 ADCK cycles total sample time. */ + kLPADC_SampleTimeADCK5 = 1U, /*!< 5 ADCK cycles total sample time. */ + kLPADC_SampleTimeADCK7 = 2U, /*!< 7 ADCK cycles total sample time. */ + kLPADC_SampleTimeADCK11 = 3U, /*!< 11 ADCK cycles total sample time. */ + kLPADC_SampleTimeADCK19 = 4U, /*!< 19 ADCK cycles total sample time. */ + kLPADC_SampleTimeADCK35 = 5U, /*!< 35 ADCK cycles total sample time. */ + kLPADC_SampleTimeADCK67 = 6U, /*!< 69 ADCK cycles total sample time. */ + kLPADC_SampleTimeADCK131 = 7U, /*!< 131 ADCK cycles total sample time. */ +} lpadc_sample_time_mode_t; + +/*! + * @brief Define enumeration of hardware compare mode. + * + * After an ADC channel input is sampled and converted and any averaging iterations are performed, this mode setting + * guides operation of the automatic compare function to optionally only store when the compare operation is true. + * When compare is enabled, the conversion result is compared to the compare values. + */ +typedef enum _lpadc_hardware_compare_mode +{ + kLPADC_HardwareCompareDisabled = 0U, /*!< Compare disabled. */ + kLPADC_HardwareCompareStoreOnTrue = 2U, /*!< Compare enabled. Store on true. */ + kLPADC_HardwareCompareRepeatUntilTrue = 3U, /*!< Compare enabled. Repeat channel acquisition until true. */ +} lpadc_hardware_compare_mode_t; + +#if defined(FSL_FEATURE_LPADC_HAS_CMDL_MODE) && FSL_FEATURE_LPADC_HAS_CMDL_MODE +/*! + * @brief Define enumeration of conversion resolution mode. + * + * Configure the resolution bit in specific conversion type. For detailed resolution accuracy, see to + * #lpadc_sample_channel_mode_t + */ +typedef enum _lpadc_conversion_resolution_mode +{ + kLPADC_ConversionResolutionStandard = 0U, /*!< Standard resolution. Single-ended 12-bit conversion, Differential + 13-bit conversion with 2’s complement output. */ + kLPADC_ConversionResolutionHigh = 1U, /*!< High resolution. Single-ended 16-bit conversion; Differential 16-bit + conversion with 2’s complement output. */ +} lpadc_conversion_resolution_mode_t; +#endif /* FSL_FEATURE_LPADC_HAS_CMDL_MODE */ + +#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS) && FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS +/*! + * @brief Define enumeration of conversion averages mode. + * + * Configure the converion average number for auto-calibration. + */ +typedef enum _lpadc_conversion_average_mode +{ + kLPADC_ConversionAverage1 = 0U, /*!< Single conversion. */ + kLPADC_ConversionAverage2 = 1U, /*!< 2 conversions averaged. */ + kLPADC_ConversionAverage4 = 2U, /*!< 4 conversions averaged. */ + kLPADC_ConversionAverage8 = 3U, /*!< 8 conversions averaged. */ + kLPADC_ConversionAverage16 = 4U, /*!< 16 conversions averaged. */ + kLPADC_ConversionAverage32 = 5U, /*!< 32 conversions averaged. */ + kLPADC_ConversionAverage64 = 6U, /*!< 64 conversions averaged. */ + kLPADC_ConversionAverage128 = 7U, /*!< 128 conversions averaged. */ +} lpadc_conversion_average_mode_t; +#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS */ + +/*! + * @brief Define enumeration of reference voltage source. + * + * For detail information, need to check the SoC's specification. + */ +typedef enum _lpadc_reference_voltage_mode +{ + kLPADC_ReferenceVoltageAlt1 = 0U, /*!< Option 1 setting. */ + kLPADC_ReferenceVoltageAlt2 = 1U, /*!< Option 2 setting. */ + kLPADC_ReferenceVoltageAlt3 = 2U, /*!< Option 3 setting. */ +} lpadc_reference_voltage_source_t; + +/*! + * @brief Define enumeration of power configuration. + * + * Configures the ADC for power and performance. In the highest power setting the highest conversion rates will be + * possible. Refer to the device data sheet for power and performance capabilities for each setting. + */ +typedef enum _lpadc_power_level_mode +{ + kLPADC_PowerLevelAlt1 = 0U, /*!< Lowest power setting. */ + kLPADC_PowerLevelAlt2 = 1U, /*!< Next lowest power setting. */ + kLPADC_PowerLevelAlt3 = 2U, /*!< ... */ + kLPADC_PowerLevelAlt4 = 3U, /*!< Highest power setting. */ +} lpadc_power_level_mode_t; + +/*! + * @brief Define enumeration of trigger priority policy. + * + * This selection controls how higher priority triggers are handled. + */ +typedef enum _lpadc_trigger_priority_policy +{ + kLPADC_TriggerPriorityPreemptImmediately = 0U, /*!< If a higher priority trigger is detected during command + processing, the current conversion is aborted and the new + command specified by the trigger is started. */ + kLPADC_TriggerPriorityPreemptSoftly = 1U, /*!< If a higher priority trigger is received during command processing, + the current conversion is completed (including averaging iterations + and compare function if enabled) and stored to the result FIFO + before the higher priority trigger/command is initiated. */ +#if defined(FSL_FEATURE_LPADC_HAS_CFG_SUBSEQUENT_PRIORITY) && FSL_FEATURE_LPADC_HAS_CFG_SUBSEQUENT_PRIORITY + kLPADC_TriggerPriorityPreemptSubsequently = 2U, /*!< If a higher priority trigger is received during command + processing, the current command will be completed (averaging, + looping, compare) before servicing the higher priority trigger. */ +#endif /* FSL_FEATURE_LPADC_HAS_CFG_SUBSEQUENT_PRIORITY */ +} lpadc_trigger_priority_policy_t; + +/*! + * @brief LPADC global configuration. + * + * This structure would used to keep the settings for initialization. + */ +typedef struct +{ +#if defined(FSL_FEATURE_LPADC_HAS_CFG_ADCKEN) && FSL_FEATURE_LPADC_HAS_CFG_ADCKEN + bool enableInternalClock; /*!< Enables the internally generated clock source. The clock source is used in clock + selection logic at the chip level and is optionally used for the ADC clock source. */ +#endif /* FSL_FEATURE_LPADC_HAS_CFG_ADCKEN */ +#if defined(FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG) && FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG + bool enableVref1LowVoltage; /*!< If voltage reference option1 input is below 1.8V, it should be "true". + If voltage reference option1 input is above 1.8V, it should be "false". */ +#endif /* FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG */ + bool enableInDozeMode; /*!< Control system transition to Stop and Wait power modes while ADC is converting. When + enabled in Doze mode, immediate entries to Wait or Stop are allowed. When disabled, the + ADC will wait for the current averaging iteration/FIFO storage to complete before + acknowledging stop or wait mode entry. */ +#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS) && FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS + lpadc_conversion_average_mode_t conversionAverageMode; /*!< Auto-Calibration Averages. */ +#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS */ + bool enableAnalogPreliminary; /*!< ADC analog circuits are pre-enabled and ready to execute conversions without + startup delays(at the cost of higher DC current consumption). */ + uint32_t powerUpDelay; /*!< When the analog circuits are not pre-enabled, the ADC analog circuits are only powered + while the ADC is active and there is a counted delay defined by this field after an + initial trigger transitions the ADC from its Idle state to allow time for the analog + circuits to stabilize. The startup delay count of (powerUpDelay * 4) ADCK cycles must + result in a longer delay than the analog startup time. */ + lpadc_reference_voltage_source_t referenceVoltageSource; /*!< Selects the voltage reference high used for + conversions.*/ + lpadc_power_level_mode_t powerLevelMode; /*!< Power Configuration Selection. */ + lpadc_trigger_priority_policy_t triggerPriorityPolicy; /*!< Control how higher priority triggers are handled, see to + lpadc_trigger_priority_policy_t. */ + bool enableConvPause; /*!< Enables the ADC pausing function. When enabled, a programmable delay is inserted during + command execution sequencing between LOOP iterations, between commands in a sequence, and + between conversions when command is executing in "Compare Until True" configuration. */ + uint32_t convPauseDelay; /*!< Controls the duration of pausing during command execution sequencing. The pause delay + is a count of (convPauseDelay*4) ADCK cycles. Only available when ADC pausing + function is enabled. The available value range is in 9-bit. */ +#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) + /* for FIFO0. */ + uint32_t FIFO0Watermark; /*!< FIFO0Watermark is a programmable threshold setting. When the number of datawords + stored in the ADC Result FIFO0 is greater than the value in this field, the ready flag + would be asserted to indicate stored data has reached the programmable threshold. */ + /* for FIFO1. */ + uint32_t FIFO1Watermark; /*!< FIFO1Watermark is a programmable threshold setting. When the number of datawords + stored in the ADC Result FIFO1 is greater than the value in this field, the ready flag + would be asserted to indicate stored data has reached the programmable threshold. */ +#else + /* for FIFO. */ + uint32_t FIFOWatermark; /*!< FIFOWatermark is a programmable threshold setting. When the number of datawords stored + in the ADC Result FIFO is greater than the value in this field, the ready flag would be + asserted to indicate stored data has reached the programmable threshold. */ +#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ +} lpadc_config_t; + +/*! + * @brief Define structure to keep the configuration for conversion command. + */ +typedef struct +{ +#if defined(FSL_FEATURE_LPADC_HAS_CMDL_CSCALE) && FSL_FEATURE_LPADC_HAS_CMDL_CSCALE + lpadc_sample_scale_mode_t sampleScaleMode; /*!< Sample scale mode. */ +#endif /* FSL_FEATURE_LPADC_HAS_CMDL_CSCALE */ + lpadc_sample_channel_mode_t sampleChannelMode; /*!< Channel sample mode. */ + uint32_t channelNumber; /*!< Channel number, select the channel or channel pair. */ + uint32_t chainedNextCommandNumber; /*!< Selects the next command to be executed after this command completes. + 1-15 is available, 0 is to terminate the chain after this command. */ + bool enableAutoChannelIncrement; /*!< Loop with increment: when disabled, the "loopCount" field selects the number + of times the selected channel is converted consecutively; when enabled, the + "loopCount" field defines how many consecutive channels are converted as part + of the command execution. */ + uint32_t loopCount; /*!< Selects how many times this command executes before finish and transition to the next + command or Idle state. Command executes LOOP+1 times. 0-15 is available. */ + lpadc_hardware_average_mode_t hardwareAverageMode; /*!< Hardware average selection. */ + lpadc_sample_time_mode_t sampleTimeMode; /*!< Sample time selection. */ + + lpadc_hardware_compare_mode_t hardwareCompareMode; /*!< Hardware compare selection. */ + uint32_t hardwareCompareValueHigh; /*!< Compare Value High. The available value range is in 16-bit. */ + uint32_t hardwareCompareValueLow; /*!< Compare Value Low. The available value range is in 16-bit. */ +#if defined(FSL_FEATURE_LPADC_HAS_CMDL_MODE) && FSL_FEATURE_LPADC_HAS_CMDL_MODE + lpadc_conversion_resolution_mode_t conversionResolutionMode; /*!< Conversion resolution mode. */ +#endif /* FSL_FEATURE_LPADC_HAS_CMDL_MODE */ +#if defined(FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG) && FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG + bool enableWaitTrigger; /*!< Wait for trigger assertion before execution: when disabled, this command will be + automatically executed; when enabled, the active trigger must be asserted again before + executing this command. */ +#endif /* FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG */ +} lpadc_conv_command_config_t; + +/*! + * @brief Define structure to keep the configuration for conversion trigger. + */ +typedef struct +{ + uint32_t targetCommandId; /*!< Select the command from command buffer to execute upon detect of the associated + trigger event. */ + uint32_t delayPower; /*!< Select the trigger delay duration to wait at the start of servicing a trigger event. + When this field is clear, then no delay is incurred. When this field is set to a non-zero + value, the duration for the delay is 2^delayPower ADCK cycles. The available value range + is 4-bit. */ + uint32_t priority; /*!< Sets the priority of the associated trigger source. If two or more triggers have the same + priority level setting, the lower order trigger event has the higher priority. The lower + value for this field is for the higher priority, the available value range is 1-bit. */ +#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) + uint8_t channelAFIFOSelect; /* SAR Result Destination For Channel A. */ + uint8_t channelBFIFOSelect; /* SAR Result Destination For Channel B. */ +#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ + bool enableHardwareTrigger; /*!< Enable hardware trigger source to initiate conversion on the rising edge of the + input trigger source or not. THe software trigger is always available. */ +} lpadc_conv_trigger_config_t; + +/*! + * @brief Define the structure to keep the conversion result. + */ +typedef struct +{ + uint32_t commandIdSource; /*!< Indicate the command buffer being executed that generated this result. */ + uint32_t loopCountIndex; /*!< Indicate the loop count value during command execution that generated this result. */ + uint32_t triggerIdSource; /*!< Indicate the trigger source that initiated a conversion and generated this result. */ + uint16_t convValue; /*!< Data result. */ +} lpadc_conv_result_t; + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* + * API + ******************************************************************************/ +/*! + * @name Initialization & de-initialization. + * @{ + */ + +/*! + * @brief Initializes the LPADC module. + * + * @param base LPADC peripheral base address. + * @param config Pointer to configuration structure. See "lpadc_config_t". + */ +void LPADC_Init(ADC_Type *base, const lpadc_config_t *config); + +/*! + * @brief Gets an available pre-defined settings for initial configuration. + * + * This function initializes the converter configuration structure with an available settings. The default values are: + * @code + * config->enableInDozeMode = true; + * config->enableAnalogPreliminary = false; + * config->powerUpDelay = 0x80; + * config->referenceVoltageSource = kLPADC_ReferenceVoltageAlt1; + * config->powerLevelMode = kLPADC_PowerLevelAlt1; + * config->triggerPriorityPolicy = kLPADC_TriggerPriorityPreemptImmediately; + * config->enableConvPause = false; + * config->convPauseDelay = 0U; + * config->FIFOWatermark = 0U; + * @endcode + * @param config Pointer to configuration structure. + */ +void LPADC_GetDefaultConfig(lpadc_config_t *config); + +/*! + * @brief De-initializes the LPADC module. + * + * @param base LPADC peripheral base address. + */ +void LPADC_Deinit(ADC_Type *base); + +/*! + * @brief Switch on/off the LPADC module. + * + * @param base LPADC peripheral base address. + * @param enable switcher to the module. + */ +static inline void LPADC_Enable(ADC_Type *base, bool enable) +{ + if (enable) + { + base->CTRL |= ADC_CTRL_ADCEN_MASK; + } + else + { + base->CTRL &= ~ADC_CTRL_ADCEN_MASK; + } +} + +#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) +/*! + * @brief Do reset the conversion FIFO0. + * + * @param base LPADC peripheral base address. + */ +static inline void LPADC_DoResetFIFO0(ADC_Type *base) +{ + base->CTRL |= ADC_CTRL_RSTFIFO0_MASK; +} + +/*! + * @brief Do reset the conversion FIFO1. + * + * @param base LPADC peripheral base address. + */ +static inline void LPADC_DoResetFIFO1(ADC_Type *base) +{ + base->CTRL |= ADC_CTRL_RSTFIFO1_MASK; +} +#else +/*! + * @brief Do reset the conversion FIFO. + * + * @param base LPADC peripheral base address. + */ +static inline void LPADC_DoResetFIFO(ADC_Type *base) +{ + base->CTRL |= ADC_CTRL_RSTFIFO_MASK; +} +#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ + +/*! + * @brief Do reset the module's configuration. + * + * Reset all ADC internal logic and registers, except the Control Register (ADCx_CTRL). + * + * @param base LPADC peripheral base address. + */ +static inline void LPADC_DoResetConfig(ADC_Type *base) +{ + base->CTRL |= ADC_CTRL_RST_MASK; + base->CTRL &= ~ADC_CTRL_RST_MASK; +} + +/* @} */ + +/*! + * @name Status + * @{ + */ + +/*! + * @brief Get status flags. + * + * @param base LPADC peripheral base address. + * @return status flags' mask. See to #_lpadc_status_flags. + */ +static inline uint32_t LPADC_GetStatusFlags(ADC_Type *base) +{ + return base->STAT; +} + +/*! + * @brief Clear status flags. + * + * Only the flags can be cleared by writing ADCx_STATUS register would be cleared by this API. + * + * @param base LPADC peripheral base address. + * @param mask Mask value for flags to be cleared. See to #_lpadc_status_flags. + */ +static inline void LPADC_ClearStatusFlags(ADC_Type *base, uint32_t mask) +{ + base->STAT = mask; +} + +#if (defined(FSL_FEATURE_LPADC_HAS_TSTAT) && FSL_FEATURE_LPADC_HAS_TSTAT) +/*! + * @brief Get trigger status flags to indicate which trigger sequences have been completed or interrupted by a high + * priority trigger exception. + * + * @param base LPADC peripheral base address. + * @return The OR'ed value of @ref _lpadc_trigger_status_flags. + */ +static inline uint32_t LPADC_GetTriggerStatusFlags(ADC_Type *base) +{ + return base->TSTAT; +} + +/*! + * @brief Clear trigger status flags. + * + * @param base LPADC peripheral base address. + * @param mask The mask of trigger status flags to be cleared, should be the + * OR'ed value of @ref _lpadc_trigger_status_flags. + */ +static inline void LPADC_ClearTriggerStatusFlags(ADC_Type *base, uint32_t mask) +{ + base->TSTAT = mask; +} +#endif /* FSL_FEATURE_LPADC_HAS_TSTAT */ + +/* @} */ + +/*! + * @name Interrupts + * @{ + */ + +/*! + * @brief Enable interrupts. + * + * @param base LPADC peripheral base address. + * @param mask Mask value for interrupt events. See to #_lpadc_interrupt_enable. + */ +static inline void LPADC_EnableInterrupts(ADC_Type *base, uint32_t mask) +{ + base->IE |= mask; +} + +/*! + * @brief Disable interrupts. + * + * @param base LPADC peripheral base address. + * @param mask Mask value for interrupt events. See to #_lpadc_interrupt_enable. + */ +static inline void LPADC_DisableInterrupts(ADC_Type *base, uint32_t mask) +{ + base->IE &= ~mask; +} + +/*! + * @name DMA Control + * @{ + */ + +#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) +/*! + * @brief Switch on/off the DMA trigger for FIFO0 watermark event. + * + * @param base LPADC peripheral base address. + * @param enable Switcher to the event. + */ +static inline void LPADC_EnableFIFO0WatermarkDMA(ADC_Type *base, bool enable) +{ + if (enable) + { + base->DE |= ADC_DE_FWMDE0_MASK; + } + else + { + base->DE &= ~ADC_DE_FWMDE0_MASK; + } +} + +/*! + * @brief Switch on/off the DMA trigger for FIFO1 watermark event. + * + * @param base LPADC peripheral base address. + * @param enable Switcher to the event. + */ +static inline void LPADC_EnableFIFO1WatermarkDMA(ADC_Type *base, bool enable) +{ + if (enable) + { + base->DE |= ADC_DE_FWMDE1_MASK; + } + else + { + base->DE &= ~ADC_DE_FWMDE1_MASK; + } +} +#else +/*! + * @brief Switch on/off the DMA trigger for FIFO watermark event. + * + * @param base LPADC peripheral base address. + * @param enable Switcher to the event. + */ +static inline void LPADC_EnableFIFOWatermarkDMA(ADC_Type *base, bool enable) +{ + if (enable) + { + base->DE |= ADC_DE_FWMDE_MASK; + } + else + { + base->DE &= ~ADC_DE_FWMDE_MASK; + } +} +#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ + /* @} */ + +/*! + * @name Trigger and conversion with FIFO. + * @{ + */ + +#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) +/*! + * @brief Get the count of result kept in conversion FIFOn. + * + * @param base LPADC peripheral base address. + * @param index Result FIFO index. + * @return The count of result kept in conversion FIFOn. + */ +static inline uint32_t LPADC_GetConvResultCount(ADC_Type *base, uint8_t index) +{ + return (ADC_FCTRL_FCOUNT_MASK & base->FCTRL[index]) >> ADC_FCTRL_FCOUNT_SHIFT; +} + +/*! + * brief Get the result in conversion FIFOn. + * + * param base LPADC peripheral base address. + * param result Pointer to structure variable that keeps the conversion result in conversion FIFOn. + * param index Result FIFO index. + * + * return Status whether FIFOn entry is valid. + */ +bool LPADC_GetConvResult(ADC_Type *base, lpadc_conv_result_t *result, uint8_t index); +#else +/*! + * @brief Get the count of result kept in conversion FIFO. + * + * @param base LPADC peripheral base address. + * @return The count of result kept in conversion FIFO. + */ +static inline uint32_t LPADC_GetConvResultCount(ADC_Type *base) +{ + return (ADC_FCTRL_FCOUNT_MASK & base->FCTRL) >> ADC_FCTRL_FCOUNT_SHIFT; +} + +/*! + * @brief Get the result in conversion FIFO. + * + * @param base LPADC peripheral base address. + * @param result Pointer to structure variable that keeps the conversion result in conversion FIFO. + * + * @return Status whether FIFO entry is valid. + */ +bool LPADC_GetConvResult(ADC_Type *base, lpadc_conv_result_t *result); +#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ + +/*! + * @brief Configure the conversion trigger source. + * + * Each programmable trigger can launch the conversion command in command buffer. + * + * @param base LPADC peripheral base address. + * @param triggerId ID for each trigger. Typically, the available value range is from 0. + * @param config Pointer to configuration structure. See to #lpadc_conv_trigger_config_t. + */ +void LPADC_SetConvTriggerConfig(ADC_Type *base, uint32_t triggerId, const lpadc_conv_trigger_config_t *config); + +/*! + * @brief Gets an available pre-defined settings for trigger's configuration. + * + * This function initializes the trigger's configuration structure with an available settings. The default values are: + * @code + * config->commandIdSource = 0U; + * config->loopCountIndex = 0U; + * config->triggerIdSource = 0U; + * config->enableHardwareTrigger = false; + * @endcode + * @param config Pointer to configuration structure. + */ +void LPADC_GetDefaultConvTriggerConfig(lpadc_conv_trigger_config_t *config); + +/*! + * @brief Do software trigger to conversion command. + * + * @param base LPADC peripheral base address. + * @param triggerIdMask Mask value for software trigger indexes, which count from zero. + */ +static inline void LPADC_DoSoftwareTrigger(ADC_Type *base, uint32_t triggerIdMask) +{ + /* Writes to ADCx_SWTRIG register are ignored while ADCx_CTRL[ADCEN] is clear. */ + base->SWTRIG = triggerIdMask; +} + +/*! + * @brief Configure conversion command. + * + * @param base LPADC peripheral base address. + * @param commandId ID for command in command buffer. Typically, the available value range is 1 - 15. + * @param config Pointer to configuration structure. See to #lpadc_conv_command_config_t. + */ +void LPADC_SetConvCommandConfig(ADC_Type *base, uint32_t commandId, const lpadc_conv_command_config_t *config); + +/*! + * @brief Gets an available pre-defined settings for conversion command's configuration. + * + * This function initializes the conversion command's configuration structure with an available settings. The default + * values are: + * @code + * config->sampleScaleMode = kLPADC_SampleFullScale; + * config->channelSampleMode = kLPADC_SampleChannelSingleEndSideA; + * config->channelNumber = 0U; + * config->chainedNextCmdNumber = 0U; + * config->enableAutoChannelIncrement = false; + * config->loopCount = 0U; + * config->hardwareAverageMode = kLPADC_HardwareAverageCount1; + * config->sampleTimeMode = kLPADC_SampleTimeADCK3; + * config->hardwareCompareMode = kLPADC_HardwareCompareDisabled; + * config->hardwareCompareValueHigh = 0U; + * config->hardwareCompareValueLow = 0U; + * config->conversionResolutionMode = kLPADC_ConversionResolutionStandard; + * config->enableWaitTrigger = false; + * @endcode + * @param config Pointer to configuration structure. + */ +void LPADC_GetDefaultConvCommandConfig(lpadc_conv_command_config_t *config); + +#if defined(FSL_FEATURE_LPADC_HAS_CFG_CALOFS) && FSL_FEATURE_LPADC_HAS_CFG_CALOFS +/*! + * @brief Enable the calibration function. + * + * When CALOFS is set, the ADC is configured to perform a calibration function anytime the ADC executes + * a conversion. Any channel selected is ignored and the value returned in the RESFIFO is a signed value + * between -31 and 31. -32 is not a valid and is never a returned value. Software should copy the lower 6- + * bits of the conversion result stored in the RESFIFO after a completed calibration conversion to the + * OFSTRIM field. The OFSTRIM field is used in normal operation for offset correction. + * + * @param base LPADC peripheral base address. + * @param enable switcher to the calibration function. + */ +void LPADC_EnableCalibration(ADC_Type *base, bool enable); +#if defined(FSL_FEATURE_LPADC_HAS_OFSTRIM) && FSL_FEATURE_LPADC_HAS_OFSTRIM +/*! + * @brief Set proper offset value to trim ADC. + * + * To minimize the offset during normal operation, software should read the conversion result from + * the RESFIFO calibration operation and write the lower 6 bits to the OFSTRIM register. + * + * @param base LPADC peripheral base address. + * @param value Setting offset value. + */ +static inline void LPADC_SetOffsetValue(ADC_Type *base, uint32_t value) +{ + base->OFSTRIM = (value & ADC_OFSTRIM_OFSTRIM_MASK) >> ADC_OFSTRIM_OFSTRIM_SHIFT; +} + +/*! + * @brief Do auto calibration. + * + * Calibration function should be executed before using converter in application. It used the software trigger and a + * dummy conversion, get the offset and write them into the OFSTRIM register. It called some of functional API + * including: -LPADC_EnableCalibration(...) -LPADC_LPADC_SetOffsetValue(...) -LPADC_SetConvCommandConfig(...) + * -LPADC_SetConvTriggerConfig(...) + * + * @param base LPADC peripheral base address. + */ +void LPADC_DoAutoCalibration(ADC_Type *base); +#endif /* FSL_FEATURE_LPADC_HAS_OFSTRIM */ +#endif /* FSL_FEATURE_LPADC_HAS_CFG_CALOFS */ + +#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CALOFS) && FSL_FEATURE_LPADC_HAS_CTRL_CALOFS +#if defined(FSL_FEATURE_LPADC_HAS_OFSTRIM) && FSL_FEATURE_LPADC_HAS_OFSTRIM +/*! + * @brief Set proper offset value to trim ADC. + * + * Set the offset trim value for offset calibration manually. + * + * @param base LPADC peripheral base address. + * @param valueA Setting offset value A. + * @param valueB Setting offset value B. + * @note In normal adc sequence, the values are automatically calculated by LPADC_EnableOffsetCalibration. + */ +static inline void LPADC_SetOffsetValue(ADC_Type *base, uint32_t valueA, uint32_t valueB) +{ + base->OFSTRIM = ADC_OFSTRIM_OFSTRIM_A(valueA) | ADC_OFSTRIM_OFSTRIM_B(valueB); +} +#endif /* FSL_FEATURE_LPADC_HAS_OFSTRIM */ + +/*! + * @brief Enable the offset calibration function. + * + * @param base LPADC peripheral base address. + * @param enable switcher to the calibration function. + */ +static inline void LPADC_EnableOffsetCalibration(ADC_Type *base, bool enable) +{ + if (enable) + { + base->CTRL |= ADC_CTRL_CALOFS_MASK; + } + else + { + base->CTRL &= ~ADC_CTRL_CALOFS_MASK; + } +} + +/*! + * @brief Do offset calibration. + * + * @param base LPADC peripheral base address. + */ +void LPADC_DoOffsetCalibration(ADC_Type *base); + +#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ) && FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ +/*! + * brief Do auto calibration. + * + * param base LPADC peripheral base address. + */ +void LPADC_DoAutoCalibration(ADC_Type *base); +#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ */ +#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CALOFS */ + +/* @} */ + +#if defined(__cplusplus) +} +#endif +/*! + * @} + */ +#endif /* _FSL_LPADC_H_ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_mcan.c b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_mcan.c new file mode 100644 index 0000000000..9de9217473 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_mcan.c @@ -0,0 +1,1744 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_mcan.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.mcan" +#endif + +/* According to CiA doc 1301 v1.0.0, specified data/nominal phase sample point postion for CAN FD at 80 MHz. */ +#define IDEAL_DATA_SP_1 (800U) +#define IDEAL_DATA_SP_2 (750U) +#define IDEAL_DATA_SP_3 (700U) +#define IDEAL_DATA_SP_4 (625U) +#define IDEAL_NOMINAL_SP (800U) + +/* According to CiA doc 301 v4.2.0 and previous version, specified sample point postion for classic CAN. */ +#define IDEAL_SP_LOW (750U) +#define IDEAL_SP_MID (800U) +#define IDEAL_SP_HIGH (875U) +#define IDEAL_SP_FACTOR (1000U) + +#define MAX_DSJW (CAN_DBTP_DSJW_MASK >> CAN_DBTP_DSJW_SHIFT) +#define MAX_DTSEG2 (CAN_DBTP_DTSEG2_MASK >> CAN_DBTP_DTSEG2_SHIFT) +#define MAX_DTSEG1 (CAN_DBTP_DTSEG1_MASK >> CAN_DBTP_DTSEG1_SHIFT) +#define MAX_DBRP (CAN_DBTP_DBRP_MASK >> CAN_DBTP_DBRP_SHIFT) + +#define MAX_NSJW (CAN_NBTP_NSJW_MASK >> CAN_NBTP_NSJW_SHIFT) +#define MAX_NTSEG2 (CAN_NBTP_NTSEG2_MASK >> CAN_NBTP_NTSEG2_SHIFT) +#define MAX_NTSEG1 (CAN_NBTP_NTSEG1_MASK >> CAN_NBTP_NTSEG1_SHIFT) +#define MAX_NBRP (CAN_NBTP_NBRP_MASK >> CAN_NBTP_NBRP_SHIFT) + +#define DBTP_MAX_TIME_QUANTA (1U + MAX_DTSEG2 + 1U + MAX_DTSEG1 + 1U) +#define DBTP_MIN_TIME_QUANTA (3U) +#define NBTP_MAX_TIME_QUANTA (1U + MAX_NTSEG2 + 1U + MAX_NTSEG1 + 1U) +#define NBTP_MIN_TIME_QUANTA (3U) + +#define MAX_TDCOFF ((uint32_t)CAN_TDCR_TDCO_MASK >> CAN_TDCR_TDCO_SHIFT) + +#define MAX_CANFD_BAUDRATE (8000000U) +#define MAX_CAN_BAUDRATE (1000000U) + +/*! @brief MCAN Internal State. */ +enum _mcan_state +{ + kMCAN_StateIdle = 0x0, /*!< MB/RxFIFO idle.*/ + kMCAN_StateRxData = 0x1, /*!< MB receiving.*/ + kMCAN_StateRxRemote = 0x2, /*!< MB receiving remote reply.*/ + kMCAN_StateTxData = 0x3, /*!< MB transmitting.*/ + kMCAN_StateTxRemote = 0x4, /*!< MB transmitting remote request.*/ + kMCAN_StateRxFifo = 0x5, /*!< RxFIFO receiving.*/ +}; + +/* Typedef for interrupt handler. */ +typedef void (*mcan_isr_t)(CAN_Type *base, mcan_handle_t *handle); + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/*! + * @brief Get the MCAN instance from peripheral base address. + * + * @param base MCAN peripheral base address. + * @return MCAN instance. + */ +static uint32_t MCAN_GetInstance(CAN_Type *base); + +/*! + * @brief Reset the MCAN instance. + * + * @param base MCAN peripheral base address. + */ +static void MCAN_Reset(CAN_Type *base); + +/*! + * @brief Calculates the segment values for a single bit time for classical CAN + * + * @param baudRate The data speed in bps + * @param tqNum Number of time quantas per bit, range in 4~385 + * @param pconfig Pointer to the MCAN timing configuration structure. + */ +static void MCAN_GetSegments(uint32_t baudRate, uint32_t tqNum, mcan_timing_config_t *pconfig); + +#if (defined(FSL_FEATURE_CAN_SUPPORT_CANFD) && FSL_FEATURE_CAN_SUPPORT_CANFD) +/*! + * @brief Calculates the segment values for a single bit time for CANFD bus data baud Rate + * + * @param baudRate The canfd bus data speed in bps + * @param tqNum Number of time quanta per bit, range in 3 ~ 33 + * @param pconfig Pointer to the MCAN timing configuration structure. + */ +static void MCAN_FDGetSegments(uint32_t baudRateFD, uint32_t tqNum, mcan_timing_config_t *pconfig); + +#endif /* FSL_FEATURE_CAN_SUPPORT_CANFD */ + +/*! + * @brief Get the element's address when read receive fifo 0. + * + * @param base MCAN peripheral base address. + * @return Address of the element in receive fifo 0. + */ +static uint32_t MCAN_GetRxFifo0ElementAddress(CAN_Type *base); + +/*! + * @brief Get the element's address when read receive fifo 1. + * + * @param base MCAN peripheral base address. + * @return Address of the element in receive fifo 1. + */ +static uint32_t MCAN_GetRxFifo1ElementAddress(CAN_Type *base); + +/*! + * @brief Get the element's address when read receive buffer. + * + * @param base MCAN peripheral base address. + * @param idx Number of the erceive buffer element. + * @return Address of the element in receive buffer. + */ +static uint32_t MCAN_GetRxBufferElementAddress(CAN_Type *base, uint8_t idx); + +/*! + * @brief Get the element's address when read transmit buffer. + * + * @param base MCAN peripheral base address. + * @param idx Number of the transmit buffer element. + * @return Address of the element in transmit buffer. + */ +static uint32_t MCAN_GetTxBufferElementAddress(CAN_Type *base, uint8_t idx); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/* Array of MCAN handle. */ +static mcan_handle_t *s_mcanHandle[FSL_FEATURE_SOC_LPC_CAN_COUNT]; + +/* Array of MCAN peripheral base address. */ +static CAN_Type *const s_mcanBases[] = CAN_BASE_PTRS; + +/* Array of MCAN IRQ number. */ +static const IRQn_Type s_mcanIRQ[][2] = CAN_IRQS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/* Array of MCAN clock name. */ +static const clock_ip_name_t s_mcanClock[] = MCAN_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if !(defined(FSL_FEATURE_MCAN_HAS_NO_RESET) && FSL_FEATURE_MCAN_HAS_NO_RESET) +/*! @brief Pointers to MCAN resets for each instance. */ +static const reset_ip_name_t s_mcanResets[] = MCAN_RSTS; +#endif + +/* MCAN ISR for transactional APIs. */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +static mcan_isr_t s_mcanIsr = (mcan_isr_t)DefaultISR; +#else +static mcan_isr_t s_mcanIsr; +#endif + +/******************************************************************************* + * Code + ******************************************************************************/ + +static uint32_t MCAN_GetInstance(CAN_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_mcanBases); instance++) + { + if (s_mcanBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_mcanBases)); + + return instance; +} + +static void MCAN_Reset(CAN_Type *base) +{ + /* Set INIT bit. */ + base->CCCR |= CAN_CCCR_INIT_MASK; + /* Confirm the value has been accepted. */ + while (0U == (base->CCCR & CAN_CCCR_INIT_MASK)) + { + } + + /* Set CCE bit to have access to the protected configuration registers, + and clear some status registers. */ + base->CCCR |= CAN_CCCR_CCE_MASK; +} + +/*! + * brief Initializes an MCAN instance. + * + * This function initializes the MCAN module with user-defined settings. + * This example shows how to set up the mcan_config_t parameters and how + * to call the MCAN_Init function by passing in these parameters. + * code + * mcan_config_t config; + * config->baudRateA = 500000U; + * config->baudRateD = 1000000U; + * config->enableCanfdNormal = false; + * config->enableCanfdSwitch = false; + * config->enableLoopBackInt = false; + * config->enableLoopBackExt = false; + * config->enableBusMon = false; + * MCAN_Init(CANFD0, &config, 8000000UL); + * endcode + * + * param base MCAN peripheral base address. + * param config Pointer to the user-defined configuration structure. + * param sourceClock_Hz MCAN Protocol Engine clock source frequency in Hz. + */ +void MCAN_Init(CAN_Type *base, const mcan_config_t *config, uint32_t sourceClock_Hz) +{ + mcan_timing_config_t timingCfg = config->timingConfig; + uint32_t quantum = 0U; + uint32_t tqFre = 0U; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable MCAN clock. */ + CLOCK_EnableClock(s_mcanClock[MCAN_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if !(defined(FSL_FEATURE_MCAN_HAS_NO_RESET) && FSL_FEATURE_MCAN_HAS_NO_RESET) + /* Reset the MCAN module */ + RESET_PeripheralReset(s_mcanResets[MCAN_GetInstance(base)]); +#endif + + MCAN_Reset(base); + + if (config->enableLoopBackInt) + { + base->CCCR |= CAN_CCCR_TEST_MASK | CAN_CCCR_MON_MASK; + base->TEST |= CAN_TEST_LBCK_MASK; + } + if (config->enableLoopBackExt) + { + base->CCCR |= CAN_CCCR_TEST_MASK; + base->TEST |= CAN_TEST_LBCK_MASK; + } + if (config->enableBusMon) + { + base->CCCR |= CAN_CCCR_MON_MASK; + } + + /* Nominal quantum = 1 + (NTSEG1 + 1) + (NTSEG2 + 1) */ + quantum = (1U + ((uint32_t)timingCfg.seg1 + 1U) + ((uint32_t)timingCfg.seg2 + 1U)); + tqFre = config->baudRateA * quantum; + + /* Assertion: Source clock should greater than baud rate * quantum. */ + assert((tqFre != 0U) && (tqFre <= sourceClock_Hz)); + + /* Check whether Nominal Bit Rate Prescaler is overflow. */ + if ((sourceClock_Hz / tqFre - 1U) > 0x1FFU) + { + timingCfg.preDivider = 0x1FFU; + } + else + { + timingCfg.preDivider = (uint16_t)(sourceClock_Hz / tqFre) - 1U; + } + /* Update actual timing characteristic to set baud rate of arbitration phase. */ + MCAN_SetArbitrationTimingConfig(base, &timingCfg); + +#if (defined(FSL_FEATURE_CAN_SUPPORT_CANFD) && FSL_FEATURE_CAN_SUPPORT_CANFD) + if (config->enableCanfdNormal) + { + base->CCCR |= CAN_CCCR_FDOE_MASK; + } + if (config->enableCanfdSwitch) + { + /* Enable the CAN FD mode and Bit Rate Switch feature. */ + base->CCCR |= CAN_CCCR_FDOE_MASK | CAN_CCCR_BRSE_MASK; + + /* Data quantum = 1 + (NTSEG1 + 1) + (NTSEG2 + 1) */ + quantum = (1U + ((uint32_t)timingCfg.dataseg1 + 1U) + ((uint32_t)timingCfg.dataseg2 + 1U)); + tqFre = config->baudRateD * quantum; + assert((tqFre != 0U) && (tqFre <= sourceClock_Hz)); + + /* Check whether Data Bit Rate Prescaler is overflow. */ + if ((sourceClock_Hz / tqFre - 1U) > 0x1FU) + { + timingCfg.datapreDivider = 0x1FU; + } + else + { + timingCfg.datapreDivider = (uint16_t)(sourceClock_Hz / tqFre) - 1U; + } + + /* Update actual timing characteristic to set baud rate of data phase. */ + MCAN_SetDataTimingConfig(base, &timingCfg); + if (!config->enableLoopBackInt && !config->enableLoopBackExt) + { + /* Enable the Transceiver Delay Compensation. */ + base->DBTP |= CAN_DBTP_TDC_MASK; + /* Cleaning previous TDCO Setting. */ + base->TDCR &= ~CAN_TDCR_TDCO_MASK; + /* The TDC offset should be configured as shown in this equation : offset = (DTSEG1 + 2) * (DBRP + 1) */ + if (((uint32_t)timingCfg.dataseg1 + 2U) * (timingCfg.datapreDivider + 1U) < MAX_TDCOFF) + { + base->TDCR |= CAN_TDCR_TDCO(((uint32_t)timingCfg.dataseg1 + 2U) * (timingCfg.datapreDivider + 1U)); + } + else + { + /* Set the Transceiver Delay Compensation offset to max value. */ + base->TDCR |= CAN_TDCR_TDCO(MAX_TDCOFF); + } + } + } +#endif +} + +/*! + * brief Deinitializes an MCAN instance. + * + * This function deinitializes the MCAN module. + * + * param base MCAN peripheral base address. + */ +void MCAN_Deinit(CAN_Type *base) +{ + /* Reset all Register Contents. */ + MCAN_Reset(base); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Disable MCAN clock. */ + CLOCK_DisableClock(s_mcanClock[MCAN_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/*! + * brief MCAN enters normal mode. + * + * After initialization, INIT bit in CCCR register must be cleared to enter + * normal mode thus synchronizes to the CAN bus and ready for communication. + * + * param base MCAN peripheral base address. + */ +void MCAN_EnterNormalMode(CAN_Type *base) +{ + /* Reset INIT bit to enter normal mode. */ + base->CCCR &= ~CAN_CCCR_INIT_MASK; + while (0U != (base->CCCR & CAN_CCCR_INIT_MASK)) + { + } +} + +/*! + * brief Gets the default configuration structure. + * + * This function initializes the MCAN configuration structure to default values. The default + * values are as follows. + * config->baudRateA = 500000U; + * config->baudRateD = 1000000U; + * config->enableCanfdNormal = false; + * config->enableCanfdSwitch = false; + * config->enableLoopBackInt = false; + * config->enableLoopBackExt = false; + * config->enableBusMon = false; + * + * param config Pointer to the MCAN configuration structure. + */ +void MCAN_GetDefaultConfig(mcan_config_t *config) +{ + /* Assertion. */ + assert(NULL != config); + + /* Initializes the configure structure to zero. */ + (void)memset(config, 0, sizeof(*config)); + + /* Initialize MCAN Module config struct with default value. */ + config->baudRateA = 500000U; + config->baudRateD = 2000000U; + config->enableCanfdNormal = false; + config->enableCanfdSwitch = false; + config->enableLoopBackInt = false; + config->enableLoopBackExt = false; + config->enableBusMon = false; + /* Default protocol timing configuration, time quantum is 16. */ + config->timingConfig.seg1 = 0xAU; + config->timingConfig.seg2 = 0x3U; + config->timingConfig.rJumpwidth = 0x3U; +#if (defined(FSL_FEATURE_CAN_SUPPORT_CANFD) && FSL_FEATURE_CAN_SUPPORT_CANFD) + config->timingConfig.dataseg1 = 0xAU; + config->timingConfig.dataseg2 = 0x3U; + config->timingConfig.datarJumpwidth = 0x3U; +#endif +} + +#if (defined(FSL_FEATURE_CAN_SUPPORT_CANFD) && FSL_FEATURE_CAN_SUPPORT_CANFD) +/*! + * @brief Calculates the segment values for a single bit time for CANFD bus data baud Rate + * + * @param baudRate The canfd bus data speed in bps + * @param tqNum Number of time quanta per bit, range in 3 ~ 33 + * @param pconfig Pointer to the MCAN timing configuration structure. + */ +static void MCAN_FDGetSegments(uint32_t baudRateFD, uint32_t tqNum, mcan_timing_config_t *pconfig) +{ + uint32_t ideal_sp, seg1Temp; + + /* get ideal sample point. */ + if (baudRateFD <= 1000000U) + { + ideal_sp = IDEAL_DATA_SP_1; + } + else if (baudRateFD <= 2000000U) + { + ideal_sp = IDEAL_DATA_SP_2; + } + else if (baudRateFD <= 4000000U) + { + ideal_sp = IDEAL_DATA_SP_3; + } + else + { + ideal_sp = IDEAL_DATA_SP_4; + } + /* distribute time quanta. */ + pconfig->dataseg2 = (uint8_t)(tqNum - (tqNum * ideal_sp) / (uint32_t)IDEAL_SP_FACTOR - 1U); + + if (pconfig->dataseg2 > MAX_DTSEG2) + { + pconfig->dataseg2 = MAX_DTSEG2; + } + + seg1Temp = tqNum - pconfig->dataseg2 - 3U; + + if (seg1Temp > MAX_DTSEG1) + { + pconfig->dataseg2 = (uint8_t)(tqNum - MAX_DTSEG1 - 3U); + pconfig->dataseg1 = MAX_DTSEG1; + } + else + { + pconfig->dataseg1 = (uint8_t)seg1Temp; + } + + /* sjw is the minimum value of phaseSeg1 and phaseSeg2. */ + pconfig->datarJumpwidth = (pconfig->dataseg1 > pconfig->dataseg2) ? pconfig->dataseg2 : pconfig->dataseg1; + if (pconfig->datarJumpwidth > (uint8_t)MAX_DSJW) + { + pconfig->datarJumpwidth = (uint8_t)MAX_DSJW; + } +} + +/*! + * brief Calculates the improved timing values by specific bit rate for CAN FD nominal phase. + * + * This function use to calculates the CAN FD nominal phase timing values according to the given nominal phase bit rate. + * The calculation is based on the recommendation of the CiA 1301 v1.0.0 document. + * + * param baudRate The CAN FD nominal phase speed in bps defined by user, should be less than or equal to 1Mbps. + * param sourceClock_Hz The Source clock frequency in Hz. + * param pconfig Pointer to the MCAN timing configuration structure. + * + * return TRUE if timing configuration found, FALSE if failed to find configuration. + */ +static bool MCAN_CalculateImprovedNominalTimingValues(uint32_t baudRate, + uint32_t sourceClock_Hz, + mcan_timing_config_t *pconfig) +{ + uint32_t clk; /* the clock is tqNumb x baudRate. */ + uint32_t tqNum; /* Numbers of TQ. */ + uint32_t seg1Temp; + bool fgRet = false; + uint32_t spTemp = 1000U; + mcan_timing_config_t configTemp; + + /* Auto Improved Protocal timing for NBTP. */ + for (tqNum = NBTP_MAX_TIME_QUANTA; tqNum >= NBTP_MIN_TIME_QUANTA; tqNum--) + { + clk = baudRate * tqNum; + if (clk > sourceClock_Hz) + { + continue; /* tqNum too large, clk has been exceed sourceClock_Hz. */ + } + + if ((sourceClock_Hz / clk * clk) != sourceClock_Hz) + { + continue; /* Non-supporting: the frequency of clock source is not divisible by target baud rate, the user + should change a divisible baud rate. */ + } + + configTemp.preDivider = (uint16_t)(sourceClock_Hz / clk - 1U); + if (configTemp.preDivider > MAX_NBRP) + { + break; /* The frequency of source clock is too large or the baud rate is too small, the pre-divider could + not handle it. */ + } + /* Calculates the best timing configuration under current tqNum. */ + configTemp.seg2 = (uint8_t)(tqNum - (tqNum * IDEAL_NOMINAL_SP) / (uint32_t)IDEAL_SP_FACTOR - 1U); + + if (configTemp.seg2 > MAX_NTSEG2) + { + configTemp.seg2 = MAX_NTSEG2; + } + + seg1Temp = tqNum - configTemp.seg2 - 3U; + + if (seg1Temp > MAX_NTSEG1) + { + configTemp.seg2 = (uint8_t)(tqNum - MAX_NTSEG1 - 3U); + configTemp.seg1 = MAX_NTSEG1; + } + else + { + configTemp.seg1 = (uint8_t)seg1Temp; + } + + /* sjw is the minimum value of phaseSeg1 and phaseSeg2. */ + configTemp.rJumpwidth = (configTemp.seg1 > configTemp.seg2) ? configTemp.seg2 : configTemp.seg1; + if (configTemp.rJumpwidth > (uint8_t)MAX_NSJW) + { + configTemp.rJumpwidth = (uint8_t)MAX_NSJW; + } + /* Determine whether the calculated timing configuration can get the optimal sampling point. */ + if (((((uint32_t)configTemp.seg2 + 1U) * 1000U) / tqNum) < spTemp) + { + spTemp = (((uint32_t)configTemp.seg2 + 1U) * 1000U) / tqNum; + pconfig->preDivider = configTemp.preDivider; + pconfig->rJumpwidth = configTemp.rJumpwidth; + pconfig->seg1 = configTemp.seg1; + pconfig->seg2 = configTemp.seg2; + } + fgRet = true; + } + return fgRet; +} +/*! + * brief Calculates the improved timing values by specific baudrates for CANFD + * + * param baudRate The CANFD bus control speed in bps defined by user + * param baudRateFD The CANFD bus data speed in bps defined by user + * param sourceClock_Hz The Source clock data speed in bps. + * param pconfig Pointer to the MCAN timing configuration structure. + * + * return TRUE if timing configuration found, FALSE if failed to find configuration + */ +bool MCAN_FDCalculateImprovedTimingValues(uint32_t baudRate, + uint32_t baudRateFD, + uint32_t sourceClock_Hz, + mcan_timing_config_t *pconfig) +{ + uint32_t clk; + uint32_t tqNum; /* Numbers of TQ. */ + bool fgRet = false; + uint16_t preDividerTemp = 1U; + /* observe baud rate maximums */ + assert(baudRate <= MAX_CAN_BAUDRATE); + assert(baudRateFD <= MAX_CANFD_BAUDRATE); + /* Data phase bit rate need greater or equal to nominal phase bit rate. */ + assert(baudRate <= baudRateFD); + + if (baudRate < baudRateFD) + { + /* To minimize errors when processing FD frames, try to get the same bit rate prescaler value for nominal phase + and data phase. */ + while (MCAN_CalculateImprovedNominalTimingValues(baudRate, sourceClock_Hz / preDividerTemp, pconfig)) + { + pconfig->datapreDivider = 0U; + for (tqNum = DBTP_MAX_TIME_QUANTA; tqNum >= DBTP_MIN_TIME_QUANTA; tqNum--) + { + clk = baudRateFD * tqNum; + if (clk > sourceClock_Hz) + { + continue; /* tqNumbrs too large, clk x tqNumbrs has been exceed sourceClock_Hz. */ + } + + if ((sourceClock_Hz / clk * clk) != sourceClock_Hz) + { + continue; /* Non-supporting: the frequency of clock source is not divisible by target bit rate. */ + } + + pconfig->datapreDivider = (uint16_t)(sourceClock_Hz / clk - 1U); + + if (pconfig->datapreDivider > MAX_DBRP) + { + break; /* The frequency of source clock is too large or the bit rate is too small, the pre-divider + could not handle it. */ + } + + if (pconfig->datapreDivider < ((pconfig->preDivider + 1U) * preDividerTemp - 1U)) + { + continue; /* try to get the same bit rate prescaler value for nominal phase and data phase. */ + } + else if (pconfig->datapreDivider == ((pconfig->preDivider + 1U) * preDividerTemp - 1U)) + { + /* Calculates the best data phase timing configuration under current tqNum. */ + MCAN_FDGetSegments(baudRateFD, tqNum, pconfig); + fgRet = true; + break; + } + else + { + break; + } + } + + if (fgRet) + { + /* Find same bit rate prescaler (BRP) configuration in both nominal and data bit timing configurations. + */ + pconfig->preDivider = (pconfig->preDivider + 1U) * preDividerTemp - 1U; + break; + } + else + { + if ((pconfig->datapreDivider <= MAX_DBRP) && (pconfig->datapreDivider != 0U)) + { + /* Can't find same data bit rate prescaler (BRP) configuration under current nominal phase bit rate + prescaler, double the nominal phase bit rate prescaler and recalculate. */ + preDividerTemp++; + } + else + { + break; + } + } + } + } + else + { + if (MCAN_CalculateImprovedTimingValues(baudRate, sourceClock_Hz, pconfig)) + { + /* No need data phase timing configuration, data phase rate equal to nominal phase rate, user don't use Brs + feature. */ + pconfig->datapreDivider = 0U; + pconfig->datarJumpwidth = 0U; + pconfig->dataseg1 = 0U; + pconfig->dataseg2 = 0U; + fgRet = true; + } + } + + return fgRet; +} + +/*! + * brief Sets the MCAN protocol data phase timing characteristic. + * + * This function gives user settings to CAN bus timing characteristic. + * The function is for an experienced user. For less experienced users, call + * the MCAN_Init() and fill the baud rate field with a desired value. + * This provides the default data phase timing characteristics. + * + * Note that calling MCAN_SetArbitrationTimingConfig() overrides the baud rate + * set in MCAN_Init(). + * + * param base MCAN peripheral base address. + * param config Pointer to the timing configuration structure. + */ +void MCAN_SetDataTimingConfig(CAN_Type *base, const mcan_timing_config_t *config) +{ + /* Assertion. */ + assert(NULL != config); + + /* Cleaning previous Timing Setting. */ + base->DBTP &= ~(CAN_DBTP_DSJW_MASK | CAN_DBTP_DTSEG2_MASK | CAN_DBTP_DTSEG1_MASK | CAN_DBTP_DBRP_MASK); + + /* Updating Timing Setting according to configuration structure. */ + base->DBTP |= (CAN_DBTP_DBRP(config->datapreDivider) | CAN_DBTP_DSJW(config->datarJumpwidth) | + CAN_DBTP_DTSEG1(config->dataseg1) | CAN_DBTP_DTSEG2(config->dataseg2)); +} + +/*! + * brief Set Baud Rate of MCAN FD mode. + * + * This function set the baud rate of MCAN FD base on MCAN_FDCalculateImprovedTimingValues API calculated timing values. + * + * param base MCAN peripheral base address. + * param sourceClock_Hz Source Clock in Hz. + * param baudRateN_Bps Nominal Baud Rate in Bps. + * param baudRateD_Bps Data Baud Rate in Bps. + * return kStatus_Success - Set CAN FD baud rate (include Nominal and Data phase) successfully. + */ +status_t MCAN_SetBaudRateFD(CAN_Type *base, uint32_t sourceClock_Hz, uint32_t baudRateN_Bps, uint32_t baudRateD_Bps) +{ + mcan_timing_config_t timingCfg; + + if (MCAN_FDCalculateImprovedTimingValues(baudRateN_Bps, baudRateD_Bps, sourceClock_Hz, &timingCfg)) + { + /* Enable write access to the protected configuration registers */ + base->CCCR |= CAN_CCCR_INIT_MASK; + while (0U == (base->CCCR & CAN_CCCR_INIT_MASK)) + { + } + base->CCCR |= CAN_CCCR_CCE_MASK; + /* Update actual timing characteristic. */ + MCAN_SetArbitrationTimingConfig(base, &timingCfg); + MCAN_SetDataTimingConfig(base, &timingCfg); + /* Update TDCO value when not enable loopback mode */ + if (0U == (base->TEST & CAN_TEST_LBCK_MASK)) + { + /* Cleaning previous TDCO Setting. */ + base->TDCR &= ~CAN_TDCR_TDCO_MASK; + /* The TDC offset should be configured as shown in this equation : offset = (DTSEG1 + 2) * (DBRP + 1) */ + if (((uint32_t)timingCfg.dataseg1 + 2U) * (timingCfg.datapreDivider + 1U) < MAX_TDCOFF) + { + base->TDCR |= CAN_TDCR_TDCO(((uint32_t)timingCfg.dataseg1 + 2U) * (timingCfg.datapreDivider + 1U)); + } + else + { + /* Set the Transceiver Delay Compensation offset to max value. */ + base->TDCR |= CAN_TDCR_TDCO(MAX_TDCOFF); + } + } + MCAN_EnterNormalMode(base); + return kStatus_Success; + } + else + { + return kStatus_Fail; + } +} +#endif /* FSL_FEATURE_CAN_SUPPORT_CANFD */ + +/*! + * @brief Calculates the segment values for a single bit time for classical CAN + * + * @param baudRate The data speed in bps + * @param tqNum Number of time quantas per bit, range in 4~385 + * @param pconfig Pointer to the MCAN timing configuration structure. + */ +static void MCAN_GetSegments(uint32_t baudRate, uint32_t tqNum, mcan_timing_config_t *pconfig) +{ + uint32_t ideal_sp, seg1Temp; + + /* get ideal sample point. */ + if (baudRate >= 1000000U) + { + ideal_sp = IDEAL_SP_LOW; + } + else if (baudRate >= 800000U) + { + ideal_sp = IDEAL_SP_MID; + } + else + { + ideal_sp = IDEAL_SP_HIGH; + } + + /* distribute time quanta. */ + pconfig->seg2 = (uint8_t)(tqNum - (tqNum * ideal_sp) / (uint32_t)IDEAL_SP_FACTOR - 1U); + + if (pconfig->seg2 > MAX_NTSEG2) + { + pconfig->seg2 = MAX_NTSEG2; + } + + seg1Temp = tqNum - pconfig->seg2 - 3U; + + if (seg1Temp > MAX_NTSEG1) + { + pconfig->seg2 = (uint8_t)(tqNum - MAX_NTSEG1 - 3U); + pconfig->seg1 = MAX_NTSEG1; + } + else + { + pconfig->seg1 = (uint8_t)seg1Temp; + } + + /* sjw is the minimum value of phaseSeg1 and phaseSeg2. */ + pconfig->rJumpwidth = (pconfig->seg1 > pconfig->seg2) ? pconfig->seg2 : pconfig->seg1; + if (pconfig->rJumpwidth > (uint8_t)MAX_NSJW) + { + pconfig->rJumpwidth = (uint8_t)MAX_NSJW; + } +} + +/*! + * brief Calculates the improved timing values by specific baudrates for classical CAN + * + * param baudRate The classical CAN speed in bps defined by user + * param sourceClock_Hz The Source clock data speed in bps. Zero to disable baudrate switching + * param pconfig Pointer to the MCAN timing configuration structure. + * + * return TRUE if timing configuration found, FALSE if failed to find configuration + */ +bool MCAN_CalculateImprovedTimingValues(uint32_t baudRate, uint32_t sourceClock_Hz, mcan_timing_config_t *pconfig) +{ + uint32_t clk; /* the clock is tqNumb x baudRate. */ + uint32_t tqNum; /* Numbers of TQ. */ + bool fgRet = false; + uint32_t spTemp = 1000U; + mcan_timing_config_t configTemp = {0}; + /* observe baud rate maximums. */ + assert(baudRate <= MAX_CAN_BAUDRATE); + + /* Auto Improved Protocal timing for NBTP. */ + for (tqNum = NBTP_MAX_TIME_QUANTA; tqNum >= NBTP_MIN_TIME_QUANTA; tqNum--) + { + clk = baudRate * tqNum; + if (clk > sourceClock_Hz) + { + continue; /* tqNum too large, clk has been exceed sourceClock_Hz. */ + } + + if ((sourceClock_Hz / clk * clk) != sourceClock_Hz) + { + continue; /* Non-supporting: the frequency of clock source is not divisible by target baud rate, the user + should change a divisible baud rate. */ + } + + configTemp.preDivider = (uint16_t)(sourceClock_Hz / clk - 1U); + if (configTemp.preDivider > MAX_NBRP) + { + break; /* The frequency of source clock is too large or the baud rate is too small, the pre-divider could + not handle it. */ + } + /* Calculates the best timing configuration under current tqNum. */ + MCAN_GetSegments(baudRate, tqNum, &configTemp); + /* Determine whether the calculated timing configuration can get the optimal sampling point. */ + if (((((uint32_t)configTemp.seg2 + 1U) * 1000U) / tqNum) < spTemp) + { + spTemp = (((uint32_t)configTemp.seg2 + 1U) * 1000U) / tqNum; + pconfig->preDivider = configTemp.preDivider; + pconfig->rJumpwidth = configTemp.rJumpwidth; + pconfig->seg1 = configTemp.seg1; + pconfig->seg2 = configTemp.seg2; + } + fgRet = true; + } + return fgRet; +} +/*! + * brief Set Baud Rate of MCAN classic mode. + * + * This function set the baud rate of MCAN base on MCAN_CalculateImprovedTimingValues() API calculated timing values. + * + * param base MCAN peripheral base address. + * param sourceClock_Hz Source Clock in Hz. + * param baudRate_Bps Baud Rate in Bps. + * return kStatus_Success - Set CAN baud rate (only has Nominal phase) successfully. + */ +status_t MCAN_SetBaudRate(CAN_Type *base, uint32_t sourceClock_Hz, uint32_t baudRate_Bps) +{ + mcan_timing_config_t timingCfg; + + if (MCAN_CalculateImprovedTimingValues(baudRate_Bps, sourceClock_Hz, &timingCfg)) + { + /* Enable write access to the protected configuration registers */ + base->CCCR |= CAN_CCCR_INIT_MASK; + while (0U == (base->CCCR & CAN_CCCR_INIT_MASK)) + { + } + base->CCCR |= CAN_CCCR_CCE_MASK; + /* Update actual timing characteristic. */ + MCAN_SetArbitrationTimingConfig(base, &timingCfg); + MCAN_EnterNormalMode(base); + return kStatus_Success; + } + else + { + return kStatus_Fail; + } +} + +/*! + * brief Sets the MCAN protocol arbitration phase timing characteristic. + * + * This function gives user settings to CAN bus timing characteristic. + * The function is for an experienced user. For less experienced users, call + * the MCAN_Init() and fill the baud rate field with a desired value. + * This provides the default arbitration phase timing characteristics. + * + * Note that calling MCAN_SetArbitrationTimingConfig() overrides the baud rate + * set in MCAN_Init(). + * + * param base MCAN peripheral base address. + * param config Pointer to the timing configuration structure. + */ +void MCAN_SetArbitrationTimingConfig(CAN_Type *base, const mcan_timing_config_t *config) +{ + /* Assertion. */ + assert(NULL != config); + + /* Cleaning previous Timing Setting. */ + base->NBTP &= ~(CAN_NBTP_NSJW_MASK | CAN_NBTP_NTSEG2_MASK | CAN_NBTP_NTSEG1_MASK | CAN_NBTP_NBRP_MASK); + + /* Updating Timing Setting according to configuration structure. */ + base->NBTP |= (CAN_NBTP_NBRP(config->preDivider) | CAN_NBTP_NSJW(config->rJumpwidth) | + CAN_NBTP_NTSEG1(config->seg1) | CAN_NBTP_NTSEG2(config->seg2)); +} + +/*! + * brief Set filter configuration. + * + * This function sets remote and non masking frames in global filter configuration, + * also the start address, list size in standard/extended ID filter configuration. + * + * param base MCAN peripheral base address. + * param config The MCAN filter configuration. + */ +void MCAN_SetFilterConfig(CAN_Type *base, const mcan_frame_filter_config_t *config) +{ + /* Set global configuration of remote/nonmasking frames, set filter address and list size. */ + if (config->idFormat == kMCAN_FrameIDStandard) + { + base->GFC |= CAN_GFC_RRFS(config->remFrame) | CAN_GFC_ANFS(config->nmFrame); + base->SIDFC |= CAN_SIDFC_FLSSA(config->address >> CAN_SIDFC_FLSSA_SHIFT) | CAN_SIDFC_LSS(config->listSize); + } + else + { + base->GFC |= CAN_GFC_RRFE(config->remFrame) | CAN_GFC_ANFE(config->nmFrame); + base->XIDFC |= CAN_XIDFC_FLESA(config->address >> CAN_XIDFC_FLESA_SHIFT) | CAN_XIDFC_LSE(config->listSize); + } +} + +/*! + * brief Configures an MCAN receive fifo 0 buffer. + * + * This function sets start address, element size, watermark, operation mode + * and datafield size of the recieve fifo 0. + * + * param base MCAN peripheral base address. + * param config The receive fifo 0 configuration structure. + */ +void MCAN_SetRxFifo0Config(CAN_Type *base, const mcan_rx_fifo_config_t *config) +{ + /* Set Rx FIFO 0 start address, element size, watermark, operation mode. */ + base->RXF0C |= CAN_RXF0C_F0SA(config->address >> CAN_RXF0C_F0SA_SHIFT) | CAN_RXF0C_F0S(config->elementSize) | + CAN_RXF0C_F0WM(config->watermark) | CAN_RXF0C_F0OM(config->opmode); + /* Set Rx FIFO 0 data field size */ + base->RXESC |= CAN_RXESC_F0DS(config->datafieldSize); +} + +/*! + * brief Configures an MCAN receive fifo 1 buffer. + * + * This function sets start address, element size, watermark, operation mode + * and datafield size of the recieve fifo 1. + * + * param base MCAN peripheral base address. + * param config The receive fifo 1 configuration structure. + */ +void MCAN_SetRxFifo1Config(CAN_Type *base, const mcan_rx_fifo_config_t *config) +{ + /* Set Rx FIFO 1 start address, element size, watermark, operation mode. */ + base->RXF1C |= CAN_RXF1C_F1SA(config->address >> CAN_RXF1C_F1SA_SHIFT) | CAN_RXF1C_F1S(config->elementSize) | + CAN_RXF1C_F1WM(config->watermark) | CAN_RXF1C_F1OM(config->opmode); + /* Set Rx FIFO 1 data field size */ + base->RXESC |= CAN_RXESC_F1DS(config->datafieldSize); +} + +/*! + * brief Configures an MCAN receive buffer. + * + * This function sets start address and datafield size of the recieve buffer. + * + * param base MCAN peripheral base address. + * param config The receive buffer configuration structure. + */ +void MCAN_SetRxBufferConfig(CAN_Type *base, const mcan_rx_buffer_config_t *config) +{ + /* Set Rx Buffer start address. */ + base->RXBC |= CAN_RXBC_RBSA(config->address >> CAN_RXBC_RBSA_SHIFT); + /* Set Rx Buffer data field size */ + base->RXESC |= CAN_RXESC_RBDS(config->datafieldSize); +} + +/*! + * brief Configures an MCAN transmit event fifo. + * + * This function sets start address, element size, watermark of the transmit event fifo. + * + * param base MCAN peripheral base address. + * param config The transmit event fifo configuration structure. + */ +void MCAN_SetTxEventFifoConfig(CAN_Type *base, const mcan_tx_fifo_config_t *config) +{ + /* Set TX Event FIFO start address, element size, watermark. */ + base->TXEFC |= CAN_TXEFC_EFSA(config->address >> CAN_TXEFC_EFSA_SHIFT) | CAN_TXEFC_EFS(config->elementSize) | + CAN_TXEFC_EFWM(config->watermark); +} + +/*! + * brief Configures an MCAN transmit buffer. + * + * This function sets start address, element size, fifo/queue mode and datafield + * size of the transmit buffer. + * + * param base MCAN peripheral base address. + * param config The transmit buffer configuration structure. + */ +void MCAN_SetTxBufferConfig(CAN_Type *base, const mcan_tx_buffer_config_t *config) +{ + assert((config->dedicatedSize + config->fqSize) <= 32U); + + /* Set Tx Buffer start address, size, fifo/queue mode. */ + base->TXBC |= CAN_TXBC_TBSA(config->address >> CAN_TXBC_TBSA_SHIFT) | CAN_TXBC_NDTB(config->dedicatedSize) | + CAN_TXBC_TFQS(config->fqSize) | CAN_TXBC_TFQM(config->mode); + /* Set Tx Buffer data field size */ + base->TXESC |= CAN_TXESC_TBDS(config->datafieldSize); +} + +/*! + * brief Set standard message ID filter element configuration. + * + * param base MCAN peripheral base address. + * param config The MCAN filter configuration. + * param filter The MCAN standard message ID filter element configuration. + * param idx The standard message ID filter element index. + */ +void MCAN_SetSTDFilterElement(CAN_Type *base, + const mcan_frame_filter_config_t *config, + const mcan_std_filter_element_config_t *filter, + uint8_t idx) +{ + uint32_t *elementAddress = NULL; + elementAddress = (uint32_t *)(MCAN_GetMsgRAMBase(base) + config->address + idx * 4U); + (void)memcpy((void *)elementAddress, (const void *)filter, sizeof(mcan_std_filter_element_config_t)); +} + +/*! + * brief Set extended message ID filter element configuration. + * + * param base MCAN peripheral base address. + * param config The MCAN filter configuration. + * param filter The MCAN extended message ID filter element configuration. + * param idx The extended message ID filter element index. + */ +void MCAN_SetEXTFilterElement(CAN_Type *base, + const mcan_frame_filter_config_t *config, + const mcan_ext_filter_element_config_t *filter, + uint8_t idx) +{ + uint32_t *elementAddress = NULL; + elementAddress = (uint32_t *)(MCAN_GetMsgRAMBase(base) + config->address + idx * 8U); + (void)memcpy((void *)elementAddress, (const void *)filter, sizeof(mcan_ext_filter_element_config_t)); +} + +static uint32_t MCAN_GetRxFifo0ElementAddress(CAN_Type *base) +{ + uint32_t eSize; + uint32_t eAddress; + eSize = (base->RXESC & CAN_RXESC_F0DS_MASK) >> CAN_RXESC_F0DS_SHIFT; + if (eSize < 5U) + { + eSize += 4U; + } + else + { + eSize = eSize * 4U - 10U; + } + eAddress = base->RXF0C & CAN_RXF0C_F0SA_MASK; + eAddress += ((base->RXF0S & CAN_RXF0S_F0GI_MASK) >> CAN_RXF0S_F0GI_SHIFT) * eSize * 4U; + return eAddress; +} + +static uint32_t MCAN_GetRxFifo1ElementAddress(CAN_Type *base) +{ + uint32_t eSize; + uint32_t eAddress; + eSize = (base->RXESC & CAN_RXESC_F1DS_MASK) >> CAN_RXESC_F1DS_SHIFT; + if (eSize < 5U) + { + eSize += 4U; + } + else + { + eSize = eSize * 4U - 10U; + } + eAddress = base->RXF1C & CAN_RXF1C_F1SA_MASK; + eAddress += ((base->RXF1S & CAN_RXF1S_F1GI_MASK) >> CAN_RXF1S_F1GI_SHIFT) * eSize * 4U; + return eAddress; +} + +static uint32_t MCAN_GetRxBufferElementAddress(CAN_Type *base, uint8_t idx) +{ + assert(idx <= 63U); + uint32_t eSize; + eSize = (base->RXESC & CAN_RXESC_RBDS_MASK) >> CAN_RXESC_RBDS_SHIFT; + if (eSize < 5U) + { + eSize += 4U; + } + else + { + eSize = eSize * 4U - 10U; + } + return (base->RXBC & CAN_RXBC_RBSA_MASK) + idx * eSize * 4U; +} + +static uint32_t MCAN_GetTxBufferElementAddress(CAN_Type *base, uint8_t idx) +{ + assert(idx <= 31U); + uint32_t eSize; + eSize = (base->TXESC & CAN_TXESC_TBDS_MASK) >> CAN_TXESC_TBDS_SHIFT; + if (eSize < 5U) + { + eSize += 4U; + } + else + { + eSize = eSize * 4U - 10U; + } + return (base->TXBC & CAN_TXBC_TBSA_MASK) + idx * eSize * 4U; +} + +/*! + * brief Gets the Tx buffer request pending status. + * + * This function returns Tx Message Buffer transmission request pending status. + * + * param base MCAN peripheral base address. + * param idx The MCAN Tx Buffer index. + */ +uint32_t MCAN_IsTransmitRequestPending(CAN_Type *base, uint8_t idx) +{ + return (base->TXBRP & ((uint32_t)1U << idx)) >> (uint32_t)idx; +} + +/*! + * brief Gets the Tx buffer transmission occurred status. + * + * This function returns Tx Message Buffer transmission occurred status. + * + * param base MCAN peripheral base address. + * param idx The MCAN Tx Buffer index. + */ +uint32_t MCAN_IsTransmitOccurred(CAN_Type *base, uint8_t idx) +{ + return (base->TXBTO & ((uint32_t)1U << idx)) >> (uint32_t)idx; +} + +/*! + * brief Writes an MCAN Message to the Transmit Buffer. + * + * This function writes a CAN Message to the specified Transmit Message Buffer + * and changes the Message Buffer state to start CAN Message transmit. After + * that the function returns immediately. + * + * param base MCAN peripheral base address. + * param idx The MCAN Tx Buffer index. + * param pTxFrame Pointer to CAN message frame to be sent. + */ +status_t MCAN_WriteTxBuffer(CAN_Type *base, uint8_t idx, const mcan_tx_buffer_frame_t *pTxFrame) +{ + /* Assertion. */ + assert(NULL != pTxFrame); + + status_t status; + uint8_t *elementAddress = NULL; + uint8_t *elementPayloadAddress = NULL; + + if (0U == MCAN_IsTransmitRequestPending(base, idx)) + { + elementAddress = (uint8_t *)(MCAN_GetMsgRAMBase(base) + MCAN_GetTxBufferElementAddress(base, idx)); + elementPayloadAddress = (uint8_t *)((uint32_t)elementAddress + 8U); + + /* Write 2 words configuration field. */ + (void)memcpy(elementAddress, (const uint8_t *)pTxFrame, 8U); + /* Write data field. */ + (void)memcpy(elementPayloadAddress, pTxFrame->data, pTxFrame->size); + status = kStatus_Success; + } + else + { + status = kStatus_Fail; + } + + return status; +} + +/*! + * brief Reads an MCAN Message from Rx Buffer. + * + * This function reads a CAN message from the Rx Buffer in the Message RAM. + * + * param base MCAN peripheral base address. + * param idx The MCAN Rx Buffer index. + * param pRxFrame Pointer to CAN message frame structure for reception. + * retval kStatus_Success - Read Message from Rx Buffer successfully. + */ +status_t MCAN_ReadRxBuffer(CAN_Type *base, uint8_t idx, mcan_rx_buffer_frame_t *pRxFrame) +{ + /* Assertion. */ + assert(NULL != pRxFrame); + + mcan_rx_buffer_frame_t *elementAddress = NULL; + uint32_t u4PayloadLength = (uint32_t)(pRxFrame->size) + 8U; + + elementAddress = (mcan_rx_buffer_frame_t *)(MCAN_GetMsgRAMBase(base) + MCAN_GetRxBufferElementAddress(base, idx)); + (void)memcpy((void *)pRxFrame, (void *)elementAddress, u4PayloadLength); + + return kStatus_Success; +} + +/*! + * brief Reads an MCAN Message from Rx FIFO. + * + * This function reads a CAN message from the Rx FIFO in the Message RAM. + * + * param base MCAN peripheral base address. + * param fifoBlock Rx FIFO block 0 or 1. + * param pRxFrame Pointer to CAN message frame structure for reception. + * retval kStatus_Success - Read Message from Rx FIFO successfully. + */ +status_t MCAN_ReadRxFifo(CAN_Type *base, uint8_t fifoBlock, mcan_rx_buffer_frame_t *pRxFrame) +{ + /* Assertion. */ + assert((0U == fifoBlock) || (1U == fifoBlock)); + assert(NULL != pRxFrame); + + mcan_rx_buffer_frame_t *elementAddress = NULL; + + if (0U == fifoBlock) + { + if ((base->RXF0S & CAN_RXF0S_F0FL_MASK) != 0U) + { + elementAddress = (mcan_rx_buffer_frame_t *)(MCAN_GetMsgRAMBase(base) + MCAN_GetRxFifo0ElementAddress(base)); + } + else + { + return kStatus_Fail; + } + } + else + { + if ((base->RXF1S & CAN_RXF1S_F1FL_MASK) != 0U) + { + elementAddress = (mcan_rx_buffer_frame_t *)(MCAN_GetMsgRAMBase(base) + MCAN_GetRxFifo1ElementAddress(base)); + } + else + { + return kStatus_Fail; + } + } + (void)memcpy(pRxFrame, elementAddress, 8U); + pRxFrame->data = (uint8_t *)((uint32_t)elementAddress + 8U); + /* Acknowledge the read. */ + if (0U == fifoBlock) + { + base->RXF0A = (base->RXF0S & CAN_RXF0S_F0GI_MASK) >> CAN_RXF0S_F0GI_SHIFT; + } + else + { + base->RXF1A = (base->RXF1S & CAN_RXF1S_F1GI_MASK) >> CAN_RXF1S_F1GI_SHIFT; + } + return kStatus_Success; +} + +/*! + * brief Performs a polling send transaction on the CAN bus. + * + * Note that a transfer handle does not need to be created before calling this API. + * + * param base MCAN peripheral base pointer. + * param idx The MCAN buffer index. + * param pTxFrame Pointer to CAN message frame to be sent. + * retval kStatus_Success - Write Tx Message Buffer Successfully. + * retval kStatus_Fail - Tx Message Buffer is currently in use. + */ +status_t MCAN_TransferSendBlocking(CAN_Type *base, uint8_t idx, mcan_tx_buffer_frame_t *pTxFrame) +{ + status_t status; + + if (kStatus_Success == MCAN_WriteTxBuffer(base, idx, pTxFrame)) + { + MCAN_TransmitAddRequest(base, idx); + + /* Wait until message sent out. */ + while (0U == MCAN_IsTransmitOccurred(base, idx)) + { + } + status = kStatus_Success; + } + else + { + status = kStatus_Fail; + } + + return status; +} + +/*! + * brief Performs a polling receive transaction on the CAN bus. + * + * Note that a transfer handle does not need to be created before calling this API. + * + * param base MCAN peripheral base pointer. + * param idx The MCAN buffer index. + * param pRxFrame Pointer to CAN message frame structure for reception. + * retval kStatus_Success - Read Rx Message Buffer Successfully. + * retval kStatus_Fail - No new message. + */ +status_t MCAN_TransferReceiveBlocking(CAN_Type *base, uint8_t idx, mcan_rx_buffer_frame_t *pRxFrame) +{ + assert(idx <= 63U); + + status_t status = kStatus_Success; + +#if (defined(MCAN_RETRY_TIMES) && MCAN_RETRY_TIMES) + uint32_t u4Retry = MCAN_RETRY_TIMES; +#endif + + while (!MCAN_GetRxBufferStatusFlag(base, idx)) + { +#if (defined(MCAN_RETRY_TIMES) && MCAN_RETRY_TIMES) + if (0U == u4Retry--) + { + status = kStatus_Fail; + } +#endif + } +#if (defined(MCAN_RETRY_TIMES) && MCAN_RETRY_TIMES) + if (kStatus_Success == status) +#endif + { + MCAN_ClearRxBufferStatusFlag(base, idx); + status = MCAN_ReadRxBuffer(base, idx, pRxFrame); + } + + return status; +} + +/*! + * brief Performs a polling receive transaction from Rx FIFO on the CAN bus. + * + * Note that a transfer handle does not need to be created before calling this API. + * + * param base MCAN peripheral base pointer. + * param fifoBlock Rx FIFO block, 0 or 1. + * param pRxFrame Pointer to CAN message frame structure for reception. + * retval kStatus_Success - Read Message from Rx FIFO successfully. + * retval kStatus_Fail - No new message in Rx FIFO. + */ +status_t MCAN_TransferReceiveFifoBlocking(CAN_Type *base, uint8_t fifoBlock, mcan_rx_buffer_frame_t *pRxFrame) +{ + assert((0U == fifoBlock) || (1U == fifoBlock)); + + status_t status = kStatus_Success; + uint32_t maskCanIR; +#if (defined(MCAN_RETRY_TIMES) && MCAN_RETRY_TIMES) + uint32_t u4Retry = MCAN_RETRY_TIMES; +#endif + + maskCanIR = (0U == fifoBlock) ? CAN_IR_RF0N_MASK : CAN_IR_RF1N_MASK; + + while (0U == MCAN_GetStatusFlag(base, maskCanIR)) + { +#if (defined(MCAN_RETRY_TIMES) && MCAN_RETRY_TIMES) + if (0U == u4Retry--) + { + status = kStatus_Fail; + } +#endif + } + +#if (defined(MCAN_RETRY_TIMES) && MCAN_RETRY_TIMES) + if (kStatus_Success == status) +#endif + { + MCAN_ClearStatusFlag(base, maskCanIR); + status = MCAN_ReadRxFifo(base, fifoBlock, pRxFrame); + } + + return status; +} + +/*! + * brief Initializes the MCAN handle. + * + * This function initializes the MCAN handle, which can be used for other MCAN + * transactional APIs. Usually, for a specified MCAN instance, + * call this API once to get the initialized handle. + * + * param base MCAN peripheral base address. + * param handle MCAN handle pointer. + * param callback The callback function. + * param userData The parameter of the callback function. + */ +void MCAN_TransferCreateHandle(CAN_Type *base, mcan_handle_t *handle, mcan_transfer_callback_t callback, void *userData) +{ + assert(NULL != handle); + + uint8_t instance; + + /* Clean MCAN transfer handle. */ + (void)memset(handle, 0, sizeof(*handle)); + + /* Get instance from peripheral base address. */ + instance = (uint8_t)MCAN_GetInstance(base); + + /* Save the context in global variables to support the double weak mechanism. */ + s_mcanHandle[instance] = handle; + + /* Register Callback function. */ + handle->callback = callback; + handle->userData = userData; + + s_mcanIsr = MCAN_TransferHandleIRQ; + + /* We Enable Error & Status interrupt here, because this interrupt just + * report current status of MCAN module through Callback function. + * It is insignificance without a available callback function. + */ + if (handle->callback != NULL) + { + MCAN_EnableInterrupts(base, 0U, + (uint32_t)kMCAN_BusOffInterruptEnable | (uint32_t)kMCAN_ErrorInterruptEnable | + (uint32_t)kMCAN_WarningInterruptEnable); + } + else + { + MCAN_DisableInterrupts(base, (uint32_t)kMCAN_BusOffInterruptEnable | (uint32_t)kMCAN_ErrorInterruptEnable | + (uint32_t)kMCAN_WarningInterruptEnable); + } + + /* Enable interrupts in NVIC. */ + (void)EnableIRQ((IRQn_Type)(s_mcanIRQ[instance][0])); + (void)EnableIRQ((IRQn_Type)(s_mcanIRQ[instance][1])); +} + +/*! + * brief Sends a message using IRQ. + * + * This function sends a message using IRQ. This is a non-blocking function, which returns + * right away. When messages have been sent out, the send callback function is called. + * + * param base MCAN peripheral base address. + * param handle MCAN handle pointer. + * param xfer MCAN Buffer transfer structure. See the #mcan_buffer_transfer_t. + * retval kStatus_Success Start Tx Buffer sending process successfully. + * retval kStatus_Fail Write Tx Buffer failed. + * retval kStatus_MCAN_TxBusy Tx Buffer is in use. + */ +status_t MCAN_TransferSendNonBlocking(CAN_Type *base, mcan_handle_t *handle, mcan_buffer_transfer_t *xfer) +{ + /* Assertion. */ + assert(NULL != handle); + assert(NULL != xfer); + assert(xfer->bufferIdx <= 63U); + + status_t status; + + /* Check if Tx Buffer is idle. */ + if ((uint8_t)kMCAN_StateIdle == handle->bufferState[xfer->bufferIdx]) + { + /* Distinguish transmit type. */ + if ((uint8_t)kMCAN_FrameTypeRemote == xfer->frame->xtd) + { + handle->bufferState[xfer->bufferIdx] = (uint8_t)kMCAN_StateTxRemote; + + /* Register user Frame buffer to receive remote Frame. */ + handle->bufferFrameBuf[xfer->bufferIdx] = xfer->frame; + } + else + { + handle->bufferState[xfer->bufferIdx] = (uint8_t)kMCAN_StateTxData; + } + + if (kStatus_Success == MCAN_WriteTxBuffer(base, xfer->bufferIdx, xfer->frame)) + { + /* Enable Buffer Interrupt. */ + MCAN_EnableTransmitBufferInterrupts(base, xfer->bufferIdx); + MCAN_EnableInterrupts(base, 0U, CAN_IE_TCE_MASK); + + MCAN_TransmitAddRequest(base, xfer->bufferIdx); + + status = kStatus_Success; + } + else + { + handle->bufferState[xfer->bufferIdx] = (uint8_t)kMCAN_StateIdle; + status = kStatus_Fail; + } + } + else + { + status = kStatus_MCAN_TxBusy; + } + + return status; +} + +/*! + * brief Receives a message from Rx FIFO using IRQ. + * + * This function receives a message using IRQ. This is a non-blocking function, which returns + * right away. When all messages have been received, the receive callback function is called. + * + * param base MCAN peripheral base address. + * param handle MCAN handle pointer. + * param fifoBlock Rx FIFO block, 0 or 1. + * param xfer MCAN Rx FIFO transfer structure. See the ref mcan_fifo_transfer_t. + * retval kStatus_Success - Start Rx FIFO receiving process successfully. + * retval kStatus_MCAN_RxFifo0Busy - Rx FIFO 0 is currently in use. + * retval kStatus_MCAN_RxFifo1Busy - Rx FIFO 1 is currently in use. + */ +status_t MCAN_TransferReceiveFifoNonBlocking(CAN_Type *base, + uint8_t fifoBlock, + mcan_handle_t *handle, + mcan_fifo_transfer_t *xfer) +{ + /* Assertion. */ + assert((0U == fifoBlock) || (1U == fifoBlock)); + assert(NULL != handle); + assert(NULL != xfer); + + status_t status; + + /* Check if Message Buffer is idle. */ + if ((uint8_t)kMCAN_StateIdle == handle->rxFifoState) + { + handle->rxFifoState = (uint8_t)kMCAN_StateRxFifo; + + /* Register Message Buffer. */ + handle->rxFifoFrameBuf = xfer->frame; + + /* Enable FIFO Interrupt. */ + if (1U == fifoBlock) + { + MCAN_EnableInterrupts(base, 0U, CAN_IE_RF1NE_MASK); + } + else + { + MCAN_EnableInterrupts(base, 0U, CAN_IE_RF0NE_MASK); + } + status = kStatus_Success; + } + else + { + status = (1U == fifoBlock) ? kStatus_MCAN_RxFifo1Busy : kStatus_MCAN_RxFifo0Busy; + } + + return status; +} + +/*! + * brief Aborts the interrupt driven message send process. + * + * This function aborts the interrupt driven message send process. + * + * param base MCAN peripheral base address. + * param handle MCAN handle pointer. + * param bufferIdx The MCAN Buffer index. + */ +void MCAN_TransferAbortSend(CAN_Type *base, mcan_handle_t *handle, uint8_t bufferIdx) +{ + /* Assertion. */ + assert(NULL != handle); + assert(bufferIdx <= 63U); + + /* Disable Message Buffer Interrupt. */ + MCAN_DisableTransmitBufferInterrupts(base, bufferIdx); + + /* Cancel send request. */ + MCAN_TransmitCancelRequest(base, bufferIdx); + + /* Un-register handle. */ + handle->bufferFrameBuf[bufferIdx] = NULL; + + handle->bufferState[bufferIdx] = (uint8_t)kMCAN_StateIdle; +} + +/*! + * brief Aborts the interrupt driven message receive from Rx FIFO process. + * + * This function aborts the interrupt driven message receive from Rx FIFO process. + * + * param base MCAN peripheral base address. + * param fifoBlock MCAN Fifo block, 0 or 1. + * param handle MCAN handle pointer. + */ +void MCAN_TransferAbortReceiveFifo(CAN_Type *base, uint8_t fifoBlock, mcan_handle_t *handle) +{ + /* Assertion. */ + assert(NULL != handle); + assert((0U == fifoBlock) || (1U == fifoBlock)); + + /* Check if Rx FIFO is enabled. */ + if (1U == fifoBlock) + { + /* Disable Rx Message FIFO Interrupts. */ + MCAN_DisableInterrupts(base, CAN_IE_RF1NE_MASK); + } + else + { + MCAN_DisableInterrupts(base, CAN_IE_RF0NE_MASK); + } + /* Un-register handle. */ + handle->rxFifoFrameBuf = NULL; + + handle->rxFifoState = (uint8_t)kMCAN_StateIdle; +} + +/*! + * brief MCAN IRQ handle function. + * + * This function handles the MCAN Error, the Buffer, and the Rx FIFO IRQ request. + * + * param base MCAN peripheral base address. + * param handle MCAN handle pointer. + */ +void MCAN_TransferHandleIRQ(CAN_Type *base, mcan_handle_t *handle) +{ + /* Assertion. */ + assert(NULL != handle); + + status_t status = kStatus_MCAN_UnHandled; + uint32_t valueIR; + uint32_t result; + + /* Store Current MCAN Module Error and Status. */ + valueIR = base->IR; + + do + { + if (0U != (valueIR & ((uint32_t)kMCAN_ErrorWarningIntFlag | (uint32_t)kMCAN_ErrorPassiveIntFlag | + (uint32_t)kMCAN_BusOffIntFlag))) + { + /* Solve error. */ + result = (valueIR & ((uint32_t)kMCAN_ErrorWarningIntFlag | (uint32_t)kMCAN_ErrorPassiveIntFlag | + (uint32_t)kMCAN_BusOffIntFlag)); + status = kStatus_MCAN_ErrorStatus; + } + else if (0U != (valueIR & (uint32_t)kMCAN_TxTransmitCompleteFlag)) + { + /* Solve Tx interrupt. */ + uint8_t idx = 0U; + for (; idx < (uint8_t)((base->TXBC & CAN_TXBC_NDTB_MASK) >> CAN_TXBC_NDTB_SHIFT); idx++) + { + /* Get the lowest unhandled Tx Message Buffer */ + if (0U != MCAN_IsTransmitOccurred(base, idx)) + { + if ((base->TXBTIE & ((uint32_t)1U << idx)) != 0U) + { + MCAN_TransferAbortSend(base, handle, idx); + } + } + } + result = (uint32_t)kMCAN_TxTransmitCompleteFlag; + status = kStatus_MCAN_TxIdle; + } + else if (0U != (valueIR & (uint32_t)kMCAN_RxFifo0NewFlag)) + { + (void)MCAN_ReadRxFifo(base, 0U, handle->rxFifoFrameBuf); + result = (uint32_t)kMCAN_RxFifo0NewFlag; + status = kStatus_MCAN_RxFifo0Idle; + MCAN_TransferAbortReceiveFifo(base, 0U, handle); + } + else if (0U != (valueIR & (uint32_t)kMCAN_RxFifo0LostFlag)) + { + result = (uint32_t)kMCAN_RxFifo0LostFlag; + status = kStatus_MCAN_RxFifo0Lost; + } + else if (0U != (valueIR & (uint32_t)kMCAN_RxFifo1NewFlag)) + { + (void)MCAN_ReadRxFifo(base, 1U, handle->rxFifoFrameBuf); + result = (uint32_t)kMCAN_RxFifo1NewFlag; + status = kStatus_MCAN_RxFifo1Idle; + MCAN_TransferAbortReceiveFifo(base, 1U, handle); + } + else if (0U != (valueIR & (uint32_t)kMCAN_RxFifo1LostFlag)) + { + result = (uint32_t)kMCAN_RxFifo1LostFlag; + status = kStatus_MCAN_RxFifo0Lost; + } + else + { + /* Handle the interrupt flag unsupported in current version of MCAN driver. + * User can get these unsupported interrupt flags by callback function, + * we can clear directly in the handler to prevent endless loop. + */ + result = valueIR; + result &= ~((uint32_t)kMCAN_ErrorWarningIntFlag | (uint32_t)kMCAN_ErrorPassiveIntFlag | + (uint32_t)kMCAN_BusOffIntFlag | (uint32_t)kMCAN_TxTransmitCompleteFlag | + (uint32_t)kMCAN_RxFifo0NewFlag | (uint32_t)kMCAN_RxFifo0LostFlag | + (uint32_t)kMCAN_RxFifo1NewFlag | (uint32_t)kMCAN_RxFifo1LostFlag); + } + + /* Clear Error interrupt, resolved Rx FIFO, Tx Buffer IRQ and other unsupported interrupt flags. */ + MCAN_ClearStatusFlag(base, result); + + /* Calling Callback Function if has one. */ + if (handle->callback != NULL) + { + handle->callback(base, handle, status, result, handle->userData); + } + + /* Reset return status */ + status = kStatus_MCAN_UnHandled; + + /* Store Current MCAN Module Error and Status. */ + valueIR = base->IR; + } while (0U != valueIR); +} + +#if defined(CAN0) +void CAN0_IRQ0_DriverIRQHandler(void); +void CAN0_IRQ0_DriverIRQHandler(void) +{ + assert(NULL != s_mcanHandle[0]); + + s_mcanIsr(CAN0, s_mcanHandle[0]); + SDK_ISR_EXIT_BARRIER; +} + +void CAN0_IRQ1_DriverIRQHandler(void); +void CAN0_IRQ1_DriverIRQHandler(void) +{ + assert(NULL != s_mcanHandle[0]); + + s_mcanIsr(CAN0, s_mcanHandle[0]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(CAN1) +void CAN1_IRQ0_DriverIRQHandler(void); +void CAN1_IRQ0_DriverIRQHandler(void) +{ + assert(NULL != s_mcanHandle[1]); + + s_mcanIsr(CAN1, s_mcanHandle[1]); + SDK_ISR_EXIT_BARRIER; +} + +void CAN1_IRQ1_DriverIRQHandler(void); +void CAN1_IRQ1_DriverIRQHandler(void) +{ + assert(NULL != s_mcanHandle[1]); + + s_mcanIsr(CAN1, s_mcanHandle[1]); + SDK_ISR_EXIT_BARRIER; +} +#endif diff --git a/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_mcan.h b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_mcan.h new file mode 100644 index 0000000000..7b0ee3e1c3 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_mcan.h @@ -0,0 +1,1056 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_MCAN_H_ +#define _FSL_MCAN_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup mcan + * @{ + */ + +/****************************************************************************** + * Definitions + *****************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief MCAN driver version. */ +#define FSL_MCAN_DRIVER_VERSION (MAKE_VERSION(2, 2, 0)) +/*@}*/ + +#ifndef MCAN_RETRY_TIMES +/* Define to 0 by default means to retry infinitely until the flag is assert/de-assert. + * User can change the macro with their requirement by defined the MACRO. + */ +#define MCAN_RETRY_TIMES (0U) +#endif + +/*! @brief MCAN transfer status. */ +enum +{ + kStatus_MCAN_TxBusy = MAKE_STATUS(kStatusGroup_MCAN, 0), /*!< Tx Buffer is Busy. */ + kStatus_MCAN_TxIdle = MAKE_STATUS(kStatusGroup_MCAN, 1), /*!< Tx Buffer is Idle. */ + kStatus_MCAN_RxBusy = MAKE_STATUS(kStatusGroup_MCAN, 2), /*!< Rx Buffer is Busy. */ + kStatus_MCAN_RxIdle = MAKE_STATUS(kStatusGroup_MCAN, 3), /*!< Rx Buffer is Idle. */ + kStatus_MCAN_RxFifo0New = MAKE_STATUS(kStatusGroup_MCAN, 4), /*!< New message written to Rx FIFO 0. */ + kStatus_MCAN_RxFifo0Idle = MAKE_STATUS(kStatusGroup_MCAN, 5), /*!< Rx FIFO 0 is Idle. */ + kStatus_MCAN_RxFifo0Watermark = MAKE_STATUS(kStatusGroup_MCAN, 6), /*!< Rx FIFO 0 fill level reached watermark. */ + kStatus_MCAN_RxFifo0Full = MAKE_STATUS(kStatusGroup_MCAN, 7), /*!< Rx FIFO 0 full. */ + kStatus_MCAN_RxFifo0Lost = MAKE_STATUS(kStatusGroup_MCAN, 8), /*!< Rx FIFO 0 message lost. */ + kStatus_MCAN_RxFifo1New = MAKE_STATUS(kStatusGroup_MCAN, 9), /*!< New message written to Rx FIFO 1. */ + kStatus_MCAN_RxFifo1Idle = MAKE_STATUS(kStatusGroup_MCAN, 10), /*!< Rx FIFO 1 is Idle. */ + kStatus_MCAN_RxFifo1Watermark = MAKE_STATUS(kStatusGroup_MCAN, 11), /*!< Rx FIFO 1 fill level reached watermark. */ + kStatus_MCAN_RxFifo1Full = MAKE_STATUS(kStatusGroup_MCAN, 12), /*!< Rx FIFO 1 full. */ + kStatus_MCAN_RxFifo1Lost = MAKE_STATUS(kStatusGroup_MCAN, 13), /*!< Rx FIFO 1 message lost. */ + kStatus_MCAN_RxFifo0Busy = MAKE_STATUS(kStatusGroup_MCAN, 14), /*!< Rx FIFO 0 is busy. */ + kStatus_MCAN_RxFifo1Busy = MAKE_STATUS(kStatusGroup_MCAN, 15), /*!< Rx FIFO 1 is busy. */ + kStatus_MCAN_ErrorStatus = MAKE_STATUS(kStatusGroup_MCAN, 16), /*!< MCAN Module Error and Status. */ + kStatus_MCAN_UnHandled = MAKE_STATUS(kStatusGroup_MCAN, 17), /*!< UnHadled Interrupt asserted. */ +}; + +/*! + * @brief MCAN status flags. + * + * This provides constants for the MCAN status flags for use in the MCAN functions. + * Note: The CPU read action clears MCAN_ErrorFlag, therefore user need to + * read MCAN_ErrorFlag and distinguish which error is occur using + * _mcan_error_flags enumerations. + */ +enum _mcan_flags +{ + kMCAN_AccesstoRsvdFlag = CAN_IR_ARA_MASK, /*!< CAN Synchronization Status. */ + kMCAN_ProtocolErrDIntFlag = CAN_IR_PED_MASK, /*!< Tx Warning Interrupt Flag. */ + kMCAN_ProtocolErrAIntFlag = CAN_IR_PEA_MASK, /*!< Rx Warning Interrupt Flag. */ + kMCAN_BusOffIntFlag = CAN_IR_BO_MASK, /*!< Tx Error Warning Status. */ + kMCAN_ErrorWarningIntFlag = CAN_IR_EW_MASK, /*!< Rx Error Warning Status. */ + kMCAN_ErrorPassiveIntFlag = CAN_IR_EP_MASK, /*!< Rx Error Warning Status. */ +}; + +/*! + * @brief MCAN Rx FIFO status flags. + * + * The MCAN Rx FIFO Status enumerations are used to determine the status of the + * Rx FIFO. + */ +enum _mcan_rx_fifo_flags +{ + kMCAN_RxFifo0NewFlag = CAN_IR_RF0N_MASK, /*!< Rx FIFO 0 new message flag. */ + kMCAN_RxFifo0WatermarkFlag = CAN_IR_RF0W_MASK, /*!< Rx FIFO 0 watermark reached flag. */ + kMCAN_RxFifo0FullFlag = CAN_IR_RF0F_MASK, /*!< Rx FIFO 0 full flag. */ + kMCAN_RxFifo0LostFlag = CAN_IR_RF0L_MASK, /*!< Rx FIFO 0 message lost flag. */ + kMCAN_RxFifo1NewFlag = CAN_IR_RF1N_MASK, /*!< Rx FIFO 0 new message flag. */ + kMCAN_RxFifo1WatermarkFlag = CAN_IR_RF1W_MASK, /*!< Rx FIFO 0 watermark reached flag. */ + kMCAN_RxFifo1FullFlag = CAN_IR_RF1F_MASK, /*!< Rx FIFO 0 full flag. */ + kMCAN_RxFifo1LostFlag = CAN_IR_RF1L_MASK, /*!< Rx FIFO 0 message lost flag. */ +}; + +/*! + * @brief MCAN Tx status flags. + * + * The MCAN Tx Status enumerations are used to determine the status of the + * Tx Buffer/Event FIFO. + */ +enum _mcan_tx_flags +{ + kMCAN_TxTransmitCompleteFlag = CAN_IR_TC_MASK, /*!< Transmission completed flag. */ + kMCAN_TxTransmitCancelFinishFlag = CAN_IR_TCF_MASK, /*!< Transmission cancellation finished flag. */ + kMCAN_TxEventFifoLostFlag = CAN_IR_TEFL_MASK, /*!< Tx Event FIFO element lost. */ + kMCAN_TxEventFifoFullFlag = CAN_IR_TEFF_MASK, /*!< Tx Event FIFO full. */ + kMCAN_TxEventFifoWatermarkFlag = CAN_IR_TEFW_MASK, /*!< Tx Event FIFO fill level reached watermark. */ + kMCAN_TxEventFifoNewFlag = CAN_IR_TEFN_MASK, /*!< Tx Handler wrote Tx Event FIFO element flag. */ + kMCAN_TxEventFifoEmptyFlag = CAN_IR_TFE_MASK, /*!< Tx FIFO empty flag. */ +}; + +/*! + * @brief MCAN interrupt configuration structure, default settings all disabled. + * + * This structure contains the settings for all of the MCAN Module interrupt configurations. + */ +enum _mcan_interrupt_enable +{ + kMCAN_BusOffInterruptEnable = CAN_IE_BOE_MASK, /*!< Bus Off interrupt. */ + kMCAN_ErrorInterruptEnable = CAN_IE_EPE_MASK, /*!< Error interrupt. */ + kMCAN_WarningInterruptEnable = CAN_IE_EWE_MASK, /*!< Rx Warning interrupt. */ +}; + +/*! @brief MCAN frame format. */ +typedef enum _mcan_frame_idformat +{ + kMCAN_FrameIDStandard = 0x0U, /*!< Standard frame format attribute. */ + kMCAN_FrameIDExtend = 0x1U, /*!< Extend frame format attribute. */ +} mcan_frame_idformat_t; + +/*! @brief MCAN frame type. */ +typedef enum _mcan_frame_type +{ + kMCAN_FrameTypeData = 0x0U, /*!< Data frame type attribute. */ + kMCAN_FrameTypeRemote = 0x1U, /*!< Remote frame type attribute. */ +} mcan_frame_type_t; + +/*! @brief MCAN frame datafield size. */ +typedef enum _mcan_bytes_in_datafield +{ + kMCAN_8ByteDatafield = 0x0U, /*!< 8 byte data field. */ + kMCAN_12ByteDatafield = 0x1U, /*!< 12 byte data field. */ + kMCAN_16ByteDatafield = 0x2U, /*!< 16 byte data field. */ + kMCAN_20ByteDatafield = 0x3U, /*!< 20 byte data field. */ + kMCAN_24ByteDatafield = 0x4U, /*!< 24 byte data field. */ + kMCAN_32ByteDatafield = 0x5U, /*!< 32 byte data field. */ + kMCAN_48ByteDatafield = 0x6U, /*!< 48 byte data field. */ + kMCAN_64ByteDatafield = 0x7U, /*!< 64 byte data field. */ +} mcan_bytes_in_datafield_t; + +#if defined(__CC_ARM) +#pragma anon_unions +#endif +/*! @brief MCAN Tx Buffer structure. */ +typedef struct _mcan_tx_buffer_frame +{ + struct + { + uint32_t id : 29; /*!< CAN Frame Identifier. */ + uint32_t rtr : 1; /*!< CAN Frame Type(DATA or REMOTE). */ + uint32_t xtd : 1; /*!< CAN Frame Type(STD or EXT). */ + uint32_t esi : 1; /*!< CAN Frame Error State Indicator. */ + }; + struct + { + uint32_t : 16; + uint32_t dlc : 4; /*!< Data Length Code 9 10 11 12 13 14 15 + Number of data bytes 12 16 20 24 32 48 64 */ + uint32_t brs : 1; /*!< Bit Rate Switch. */ + uint32_t fdf : 1; /*!< CAN FD format. */ + uint32_t : 1; /*!< Reserved. */ + uint32_t efc : 1; /*!< Event FIFO control. */ + uint32_t mm : 8; /*!< Message Marker. */ + }; + uint8_t *data; + uint8_t size; /*!< classical CAN is 8(bytes), FD is 12/64 such. */ +} mcan_tx_buffer_frame_t; + +/*! @brief MCAN Rx FIFO/Buffer structure. */ +typedef struct _mcan_rx_buffer_frame +{ + struct + { + uint32_t id : 29; /*!< CAN Frame Identifier. */ + uint32_t rtr : 1; /*!< CAN Frame Type(DATA or REMOTE). */ + uint32_t xtd : 1; /*!< CAN Frame Type(STD or EXT). */ + uint32_t esi : 1; /*!< CAN Frame Error State Indicator. */ + }; + struct + { + uint32_t rxts : 16; /*!< Rx Timestamp. */ + uint32_t dlc : 4; /*!< Data Length Code 9 10 11 12 13 14 15 + Number of data bytes 12 16 20 24 32 48 64 */ + uint32_t brs : 1; /*!< Bit Rate Switch. */ + uint32_t fdf : 1; /*!< CAN FD format. */ + uint32_t : 2; /*!< Reserved. */ + uint32_t fidx : 7; /*!< Filter Index. */ + uint32_t anmf : 1; /*!< Accepted Non-matching Frame. */ + }; + uint8_t *data; + uint8_t size; /*!< classical CAN is 8(bytes), FD is 12/64 such. */ +} mcan_rx_buffer_frame_t; + +/*! @brief MCAN Rx FIFO block number. */ +typedef enum _mcan_fifo_type +{ + kMCAN_Fifo0 = 0x0U, /*!< CAN Rx FIFO 0. */ + kMCAN_Fifo1 = 0x1U, /*!< CAN Rx FIFO 1. */ +} mcan_fifo_type_t; + +/*! @brief MCAN FIFO Operation Mode. */ +typedef enum _mcan_fifo_opmode_config +{ + kMCAN_FifoBlocking = 0x0U, /*!< FIFO blocking mode. */ + kMCAN_FifoOverwrite = 0x1U, /*!< FIFO overwrite mode. */ +} mcan_fifo_opmode_config_t; + +/*! @brief MCAN Tx FIFO/Queue Mode. */ +typedef enum _mcan_txmode_config +{ + kMCAN_txFifo = 0x0U, /*!< Tx FIFO operation. */ + kMCAN_txQueue = 0x1U, /*!< Tx Queue operation. */ +} mcan_txmode_config_t; + +/*! @brief MCAN remote frames treatment. */ +typedef enum _mcan_remote_frame_config +{ + kMCAN_filterFrame = 0x0U, /*!< Filter remote frames. */ + kMCAN_rejectFrame = 0x1U, /*!< Reject all remote frames. */ +} mcan_remote_frame_config_t; + +/*! @brief MCAN non-masking frames treatment. */ +typedef enum _mcan_nonmasking_frame_config +{ + kMCAN_acceptinFifo0 = 0x0U, /*!< Accept non-masking frames in Rx FIFO 0. */ + kMCAN_acceptinFifo1 = 0x1U, /*!< Accept non-masking frames in Rx FIFO 1. */ + kMCAN_reject0 = 0x2U, /*!< Reject non-masking frames. */ + kMCAN_reject1 = 0x3U, /*!< Reject non-masking frames. */ +} mcan_nonmasking_frame_config_t; + +/*! @brief MCAN Filter Element Configuration. */ +typedef enum _mcan_fec_config +{ + kMCAN_disable = 0x0U, /*!< Disable filter element. */ + kMCAN_storeinFifo0 = 0x1U, /*!< Store in Rx FIFO 0 if filter matches. */ + kMCAN_storeinFifo1 = 0x2U, /*!< Store in Rx FIFO 1 if filter matches. */ + kMCAN_reject = 0x3U, /*!< Reject ID if filter matches. */ + kMCAN_setprio = 0x4U, /*!< Set priority if filter matches. */ + kMCAN_setpriofifo0 = 0x5U, /*!< Set priority and store in FIFO 0 if filter matches. */ + kMCAN_setpriofifo1 = 0x6U, /*!< Set priority and store in FIFO 1 if filter matches. */ + kMCAN_storeinbuffer = 0x7U, /*!< Store into Rx Buffer or as debug message. */ +} mcan_fec_config_t; + +/*! @brief MCAN Rx FIFO configuration. */ +typedef struct _mcan_rx_fifo_config +{ + uint32_t address; /*!< FIFOn start address. */ + uint32_t elementSize; /*!< FIFOn element number. */ + uint32_t watermark; /*!< FIFOn watermark level. */ + mcan_fifo_opmode_config_t opmode; /*!< FIFOn blocking/overwrite mode. */ + mcan_bytes_in_datafield_t datafieldSize; /*!< Data field size per frame, size>8 is for CANFD. */ +} mcan_rx_fifo_config_t; + +/*! @brief MCAN Rx Buffer configuration. */ +typedef struct _mcan_rx_buffer_config +{ + uint32_t address; /*!< Rx Buffer start address. */ + mcan_bytes_in_datafield_t datafieldSize; /*!< Data field size per frame, size>8 is for CANFD. */ +} mcan_rx_buffer_config_t; + +/*! @brief MCAN Tx Event FIFO configuration. */ +typedef struct _mcan_tx_fifo_config +{ + uint32_t address; /*!< Event fifo start address. */ + uint32_t elementSize; /*!< FIFOn element number. */ + uint32_t watermark; /*!< FIFOn watermark level. */ +} mcan_tx_fifo_config_t; + +/*! @brief MCAN Tx Buffer configuration. */ +typedef struct _mcan_tx_buffer_config +{ + uint32_t address; /*!< Tx Buffers Start Address. */ + uint32_t dedicatedSize; /*!< Number of Dedicated Transmit Buffers. */ + uint32_t fqSize; /*!< Transmit FIFO/Queue Size. */ + mcan_txmode_config_t mode; /*!< Tx FIFO/Queue Mode.*/ + mcan_bytes_in_datafield_t datafieldSize; /*!< Data field size per frame, size>8 is for CANFD. */ +} mcan_tx_buffer_config_t; + +/*! @brief MCAN Filter Type. */ +typedef enum _mcan_std_filter_type +{ + kMCAN_range = 0x0U, /*!< Range filter from SFID1 to SFID2. */ + kMCAN_dual = 0x1U, /*!< Dual ID filter for SFID1 or SFID2. */ + kMCAN_classic = 0x2U, /*!< Classic filter: SFID1 = filter, SFID2 = mask. */ + kMCAN_disableORrange2 = 0x3U, /*!< Filter element disabled for standard filter + or Range filter, XIDAM mask not applied for extended filter. */ +} mcan_filter_type_t; + +/*! @brief MCAN Standard Message ID Filter Element. */ +typedef struct _mcan_std_filter_element_config +{ + uint32_t sfid2 : 11; /*!< Standard Filter ID 2. */ + uint32_t : 5; /*!< Reserved. */ + uint32_t sfid1 : 11; /*!< Standard Filter ID 1. */ + uint32_t sfec : 3; /*!< Standard Filter Element Configuration. */ + uint32_t sft : 2; /*!< Standard Filter Type. */ +} mcan_std_filter_element_config_t; + +/*! @brief MCAN Extended Message ID Filter Element. */ +typedef struct _mcan_ext_filter_element_config +{ + uint32_t efid1 : 29; /*!< Extended Filter ID 1. */ + uint32_t efec : 3; /*!< Extended Filter Element Configuration. */ + uint32_t efid2 : 29; /*!< Extended Filter ID 2. */ + uint32_t : 1; /*!< Reserved. */ + uint32_t eft : 2; /*!< Extended Filter Type. */ +} mcan_ext_filter_element_config_t; + +/*! @brief MCAN Rx filter configuration. */ +typedef struct _mcan_frame_filter_config +{ + uint32_t address; /*!< Filter start address. */ + uint32_t listSize; /*!< Filter list size. */ + mcan_frame_idformat_t idFormat; /*!< Frame format. */ + mcan_remote_frame_config_t remFrame; /*!< Remote frame treatment. */ + mcan_nonmasking_frame_config_t nmFrame; /*!< Non-masking frame treatment. */ +} mcan_frame_filter_config_t; + +/*! @brief MCAN protocol timing characteristic configuration structure. */ +typedef struct _mcan_timing_config +{ + uint16_t preDivider; /*!< Nominal Clock Pre-scaler Division Factor. */ + uint8_t rJumpwidth; /*!< Nominal Re-sync Jump Width. */ + uint8_t seg1; /*!< Nominal Time Segment 1. */ + uint8_t seg2; /*!< Nominal Time Segment 2. */ +#if (defined(FSL_FEATURE_CAN_SUPPORT_CANFD) && FSL_FEATURE_CAN_SUPPORT_CANFD) + uint16_t datapreDivider; /*!< Data Clock Pre-scaler Division Factor. */ + uint8_t datarJumpwidth; /*!< Data Re-sync Jump Width. */ + uint8_t dataseg1; /*!< Data Time Segment 1. */ + uint8_t dataseg2; /*!< Data Time Segment 2. */ +#endif +} mcan_timing_config_t; + +/*! @brief MCAN module configuration structure. */ +typedef struct _mcan_config +{ + uint32_t baudRateA; /*!< Baud rate of Arbitration phase in bps. */ + uint32_t baudRateD; /*!< Baud rate of Data phase in bps. */ + bool enableCanfdNormal; /*!< Enable or Disable CANFD normal. */ + bool enableCanfdSwitch; /*!< Enable or Disable CANFD with baudrate switch. */ + bool enableLoopBackInt; /*!< Enable or Disable Internal Back. */ + bool enableLoopBackExt; /*!< Enable or Disable External Loop Back. */ + bool enableBusMon; /*!< Enable or Disable Bus Monitoring Mode. */ + mcan_timing_config_t timingConfig; /*!< Protocol timing . */ +} mcan_config_t; + +/*! @brief MCAN Buffer transfer. */ +typedef struct _mcan_buffer_transfer +{ + mcan_tx_buffer_frame_t *frame; /*!< The buffer of CAN Message to be transfer. */ + uint8_t bufferIdx; /*!< The index of Message buffer used to transfer Message. */ +} mcan_buffer_transfer_t; + +/*! @brief MCAN Rx FIFO transfer. */ +typedef struct _mcan_fifo_transfer +{ + mcan_rx_buffer_frame_t *frame; /*!< The buffer of CAN Message to be received from Rx FIFO. */ +} mcan_fifo_transfer_t; + +/*! @brief MCAN handle structure definition. */ +typedef struct _mcan_handle mcan_handle_t; + +/*! @brief MCAN transfer callback function. + * + * The MCAN transfer callback returns a value from the underlying layer. + * If the status equals to kStatus_MCAN_ErrorStatus, the result parameter is the Content of + * MCAN status register which can be used to get the working status(or error status) of MCAN module. + * If the status equals to other MCAN Message Buffer transfer status, the result is the index of + * Message Buffer that generate transfer event. + * If the status equals to other MCAN Message Buffer transfer status, the result is meaningless and should be + * Ignored. + */ +typedef void (*mcan_transfer_callback_t)( + CAN_Type *base, mcan_handle_t *handle, status_t status, uint32_t result, void *userData); + +/*! @brief MCAN handle structure. */ +struct _mcan_handle +{ + mcan_transfer_callback_t callback; /*!< Callback function. */ + void *userData; /*!< MCAN callback function parameter.*/ + mcan_tx_buffer_frame_t *volatile bufferFrameBuf[64]; /*!< The buffer for received data from Buffers. */ + mcan_rx_buffer_frame_t *volatile rxFifoFrameBuf; /*!< The buffer for received data from Rx FIFO. */ + volatile uint8_t bufferState[64]; /*!< Message Buffer transfer state. */ + volatile uint8_t rxFifoState; /*!< Rx FIFO transfer state. */ +}; + +/****************************************************************************** + * API + *****************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Initializes an MCAN instance. + * + * This function initializes the MCAN module with user-defined settings. + * This example shows how to set up the mcan_config_t parameters and how + * to call the MCAN_Init function by passing in these parameters. + * @code + * mcan_config_t config; + * config->baudRateA = 500000U; + * config->baudRateD = 1000000U; + * config->enableCanfdNormal = false; + * config->enableCanfdSwitch = false; + * config->enableLoopBackInt = false; + * config->enableLoopBackExt = false; + * config->enableBusMon = false; + * MCAN_Init(CANFD0, &config, 8000000UL); + * @endcode + * + * @param base MCAN peripheral base address. + * @param config Pointer to the user-defined configuration structure. + * @param sourceClock_Hz MCAN Protocol Engine clock source frequency in Hz. + */ +void MCAN_Init(CAN_Type *base, const mcan_config_t *config, uint32_t sourceClock_Hz); + +/*! + * @brief Deinitializes an MCAN instance. + * + * This function deinitializes the MCAN module. + * + * @param base MCAN peripheral base address. + */ +void MCAN_Deinit(CAN_Type *base); + +/*! + * @brief Gets the default configuration structure. + * + * This function initializes the MCAN configuration structure to default values. The default + * values are as follows. + * config->baudRateA = 500000U; + * config->baudRateD = 1000000U; + * config->enableCanfdNormal = false; + * config->enableCanfdSwitch = false; + * config->enableLoopBackInt = false; + * config->enableLoopBackExt = false; + * config->enableBusMon = false; + * + * @param config Pointer to the MCAN configuration structure. + */ +void MCAN_GetDefaultConfig(mcan_config_t *config); + +/*! + * @brief MCAN enters normal mode. + * + * After initialization, INIT bit in CCCR register must be cleared to enter + * normal mode thus synchronizes to the CAN bus and ready for communication. + * + * @param base MCAN peripheral base address. + */ +void MCAN_EnterNormalMode(CAN_Type *base); + +/*! + * @name Configuration. + * @{ + */ + +/*! + * @brief Sets the MCAN Message RAM base address. + * + * This function sets the Message RAM base address. + * + * @param base MCAN peripheral base address. + * @param value Desired Message RAM base. + */ +static inline void MCAN_SetMsgRAMBase(CAN_Type *base, uint32_t value) +{ + assert(((value >= 0x20000000U) && (value <= 0x20027FFFU)) || ((value >= 0x04000000U) && (value <= 0x04007FFFU))); + + base->MRBA = CAN_MRBA_BA(value >> 16U); +} + +/*! + * @brief Gets the MCAN Message RAM base address. + * + * This function gets the Message RAM base address. + * + * @param base MCAN peripheral base address. + * @return Message RAM base address. + */ +static inline uint32_t MCAN_GetMsgRAMBase(CAN_Type *base) +{ + return base->MRBA; +} + +/*! + * @brief Calculates the improved timing values by specific baudrates for classical CAN + * + * @param baudRate The classical CAN speed in bps defined by user + * @param sourceClock_Hz The Source clock data speed in bps. Zero to disable baudrate switching + * @param pconfig Pointer to the MCAN timing configuration structure. + * + * @return TRUE if timing configuration found, FALSE if failed to find configuration + */ +bool MCAN_CalculateImprovedTimingValues(uint32_t baudRate, uint32_t sourceClock_Hz, mcan_timing_config_t *pconfig); + +/*! + * @brief Sets the MCAN protocol arbitration phase timing characteristic. + * + * This function gives user settings to CAN bus timing characteristic. + * The function is for an experienced user. For less experienced users, call + * the MCAN_Init() and fill the baud rate field with a desired value. + * This provides the default arbitration phase timing characteristics. + * + * Note that calling MCAN_SetArbitrationTimingConfig() overrides the baud rate + * set in MCAN_Init(). + * + * @param base MCAN peripheral base address. + * @param config Pointer to the timing configuration structure. + */ +void MCAN_SetArbitrationTimingConfig(CAN_Type *base, const mcan_timing_config_t *config); + +/*! + * @brief Set Baud Rate of MCAN classic mode. + * + * This function set the baud rate of MCAN base on MCAN_CalculateImprovedTimingValues() API calculated timing values. + * + * @param base MCAN peripheral base address. + * @param sourceClock_Hz Source Clock in Hz. + * @param baudRate_Bps Baud Rate in Bps. + * @return kStatus_Success - Set CAN baud rate (only has Nominal phase) successfully. + */ +status_t MCAN_SetBaudRate(CAN_Type *base, uint32_t sourceClock_Hz, uint32_t baudRate_Bps); + +#if (defined(FSL_FEATURE_CAN_SUPPORT_CANFD) && FSL_FEATURE_CAN_SUPPORT_CANFD) +/*! + * @brief Calculates the improved timing values by specific baudrates for CANFD + * + * @param baudRate The CANFD bus control speed in bps defined by user + * @param baudRateFD The CANFD bus data speed in bps defined by user + * @param sourceClock_Hz The Source clock data speed in bps. + * @param pconfig Pointer to the MCAN timing configuration structure. + * + * @return TRUE if timing configuration found, FALSE if failed to find configuration + */ +bool MCAN_FDCalculateImprovedTimingValues(uint32_t baudRate, + uint32_t baudRateFD, + uint32_t sourceClock_Hz, + mcan_timing_config_t *pconfig); + +/*! + * @brief Set Baud Rate of MCAN FD mode. + * + * This function set the baud rate of MCAN FD base on MCAN_FDCalculateImprovedTimingValues API calculated timing values. + * + * @param base MCAN peripheral base address. + * @param sourceClock_Hz Source Clock in Hz. + * @param baudRateN_Bps Nominal Baud Rate in Bps. + * @param baudRateD_Bps Data Baud Rate in Bps. + * @return kStatus_Success - Set CAN FD baud rate (include Nominal and Data phase) successfully. + */ +status_t MCAN_SetBaudRateFD(CAN_Type *base, uint32_t sourceClock_Hz, uint32_t baudRateN_Bps, uint32_t baudRateD_Bps); +/*! + * @brief Sets the MCAN protocol data phase timing characteristic. + * + * This function gives user settings to CAN bus timing characteristic. + * The function is for an experienced user. For less experienced users, call + * the MCAN_Init() and fill the baud rate field with a desired value. + * This provides the default data phase timing characteristics. + * + * Note that calling MCAN_SetArbitrationTimingConfig() overrides the baud rate + * set in MCAN_Init(). + * + * @param base MCAN peripheral base address. + * @param config Pointer to the timing configuration structure. + */ +void MCAN_SetDataTimingConfig(CAN_Type *base, const mcan_timing_config_t *config); +#endif /* FSL_FEATURE_CAN_SUPPORT_CANFD */ + +/*! + * @brief Configures an MCAN receive fifo 0 buffer. + * + * This function sets start address, element size, watermark, operation mode + * and datafield size of the recieve fifo 0. + * + * @param base MCAN peripheral base address. + * @param config The receive fifo 0 configuration structure. + */ +void MCAN_SetRxFifo0Config(CAN_Type *base, const mcan_rx_fifo_config_t *config); + +/*! + * @brief Configures an MCAN receive fifo 1 buffer. + * + * This function sets start address, element size, watermark, operation mode + * and datafield size of the recieve fifo 1. + * + * @param base MCAN peripheral base address. + * @param config The receive fifo 1 configuration structure. + */ +void MCAN_SetRxFifo1Config(CAN_Type *base, const mcan_rx_fifo_config_t *config); + +/*! + * @brief Configures an MCAN receive buffer. + * + * This function sets start address and datafield size of the recieve buffer. + * + * @param base MCAN peripheral base address. + * @param config The receive buffer configuration structure. + */ +void MCAN_SetRxBufferConfig(CAN_Type *base, const mcan_rx_buffer_config_t *config); + +/*! + * @brief Configures an MCAN transmit event fifo. + * + * This function sets start address, element size, watermark of the transmit event fifo. + * + * @param base MCAN peripheral base address. + * @param config The transmit event fifo configuration structure. + */ +void MCAN_SetTxEventFifoConfig(CAN_Type *base, const mcan_tx_fifo_config_t *config); + +/*! + * @brief Configures an MCAN transmit buffer. + * + * This function sets start address, element size, fifo/queue mode and datafield + * size of the transmit buffer. + * + * @param base MCAN peripheral base address. + * @param config The transmit buffer configuration structure. + */ +void MCAN_SetTxBufferConfig(CAN_Type *base, const mcan_tx_buffer_config_t *config); + +/*! + * @brief Set filter configuration. + * + * This function sets remote and non masking frames in global filter configuration, + * also the start address, list size in standard/extended ID filter configuration. + * + * @param base MCAN peripheral base address. + * @param config The MCAN filter configuration. + */ +void MCAN_SetFilterConfig(CAN_Type *base, const mcan_frame_filter_config_t *config); + +/*! + * @brief Set standard message ID filter element configuration. + * + * @param base MCAN peripheral base address. + * @param config The MCAN filter configuration. + * @param filter The MCAN standard message ID filter element configuration. + * @param idx The standard message ID filter element index. + */ +void MCAN_SetSTDFilterElement(CAN_Type *base, + const mcan_frame_filter_config_t *config, + const mcan_std_filter_element_config_t *filter, + uint8_t idx); + +/*! + * @brief Set extended message ID filter element configuration. + * + * @param base MCAN peripheral base address. + * @param config The MCAN filter configuration. + * @param filter The MCAN extended message ID filter element configuration. + * @param idx The extended message ID filter element index. + */ +void MCAN_SetEXTFilterElement(CAN_Type *base, + const mcan_frame_filter_config_t *config, + const mcan_ext_filter_element_config_t *filter, + uint8_t idx); + +/*! + * @name Status + * @{ + */ + +/*! + * @brief Gets the MCAN module interrupt flags. + * + * This function gets all MCAN interrupt status flags. + * + * @param base MCAN peripheral base address. + * @param mask The ORed MCAN interrupt mask. + * @return MCAN status flags which are ORed. + */ +static inline uint32_t MCAN_GetStatusFlag(CAN_Type *base, uint32_t mask) +{ + return (base->IR & mask); +} + +/*! + * @brief Clears the MCAN module interrupt flags. + * + * This function clears MCAN interrupt status flags. + * + * @param base MCAN peripheral base address. + * @param mask The ORed MCAN interrupt mask. + */ +static inline void MCAN_ClearStatusFlag(CAN_Type *base, uint32_t mask) +{ + /* Write 1 to clear status flag, write 0 has no effect. */ + base->IR = mask; +} + +/*! + * @brief Gets the new data flag of specific Rx Buffer. + * + * This function gets new data flag of specific Rx Buffer. + * + * @param base MCAN peripheral base address. + * @param idx Rx Buffer index. + * @return Rx Buffer new data status flag. + */ +static inline bool MCAN_GetRxBufferStatusFlag(CAN_Type *base, uint8_t idx) +{ + assert(idx <= 63U); + + bool fgRet; + + if (idx <= 31U) + { + fgRet = (0U != (base->NDAT1 & ((uint32_t)1U << idx))); + } + else + { + fgRet = (0U != (base->NDAT2 & ((uint32_t)1U << (idx - 32U)))); + } + + return fgRet; +} + +/*! + * @brief Clears the new data flag of specific Rx Buffer. + * + * This function clears new data flag of specific Rx Buffer. + * + * @param base MCAN peripheral base address. + * @param idx Rx Buffer index. + */ +static inline void MCAN_ClearRxBufferStatusFlag(CAN_Type *base, uint8_t idx) +{ + assert(idx <= 63U); + + if (idx <= 31U) + { + base->NDAT1 = ((uint32_t)1U << idx); + } + else + { + base->NDAT2 = ((uint32_t)1U << (idx - 32U)); + } +} + +/* @} */ + +/*! + * @name Interrupts + * @{ + */ + +/*! + * @brief Enables MCAN interrupts according to the provided interrupt line and mask. + * + * This function enables the MCAN interrupts according to the provided interrupt line and mask. + * The mask is a logical OR of enumeration members. + * + * @param base MCAN peripheral base address. + * @param line Interrupt line number, 0 or 1. + * @param mask The interrupts to enable. + */ +static inline void MCAN_EnableInterrupts(CAN_Type *base, uint32_t line, uint32_t mask) +{ + base->ILE |= ((uint32_t)1U << line); + if (0U == line) + { + base->ILS &= ~mask; + } + else + { + base->ILS |= mask; + } + base->IE |= mask; +} + +/*! + * @brief Enables MCAN Tx Buffer interrupts according to the provided index. + * + * This function enables the MCAN Tx Buffer interrupts. + * + * @param base MCAN peripheral base address. + * @param idx Tx Buffer index. + */ +static inline void MCAN_EnableTransmitBufferInterrupts(CAN_Type *base, uint8_t idx) +{ + base->TXBTIE |= ((uint32_t)1U << idx); +} + +/*! + * @brief Disables MCAN Tx Buffer interrupts according to the provided index. + * + * This function disables the MCAN Tx Buffer interrupts. + * + * @param base MCAN peripheral base address. + * @param idx Tx Buffer index. + */ +static inline void MCAN_DisableTransmitBufferInterrupts(CAN_Type *base, uint8_t idx) +{ + base->TXBTIE &= (~((uint32_t)1U << idx)); +} + +/*! + * @brief Disables MCAN interrupts according to the provided mask. + * + * This function disables the MCAN interrupts according to the provided mask. + * The mask is a logical OR of enumeration members. + * + * @param base MCAN peripheral base address. + * @param mask The interrupts to disable. + */ +static inline void MCAN_DisableInterrupts(CAN_Type *base, uint32_t mask) +{ + base->IE &= ~mask; +} + +/* @} */ + +/*! + * @name Bus Operations + * @{ + */ + +/*! + * @brief Gets the Tx buffer request pending status. + * + * This function returns Tx Message Buffer transmission request pending status. + * + * @param base MCAN peripheral base address. + * @param idx The MCAN Tx Buffer index. + */ +uint32_t MCAN_IsTransmitRequestPending(CAN_Type *base, uint8_t idx); + +/*! + * @brief Gets the Tx buffer transmission occurred status. + * + * This function returns Tx Message Buffer transmission occurred status. + * + * @param base MCAN peripheral base address. + * @param idx The MCAN Tx Buffer index. + */ +uint32_t MCAN_IsTransmitOccurred(CAN_Type *base, uint8_t idx); + +/*! + * @brief Writes an MCAN Message to the Transmit Buffer. + * + * This function writes a CAN Message to the specified Transmit Message Buffer + * and changes the Message Buffer state to start CAN Message transmit. After + * that the function returns immediately. + * + * @param base MCAN peripheral base address. + * @param idx The MCAN Tx Buffer index. + * @param pTxFrame Pointer to CAN message frame to be sent. + */ +status_t MCAN_WriteTxBuffer(CAN_Type *base, uint8_t idx, const mcan_tx_buffer_frame_t *pTxFrame); + +/*! + * @brief Reads an MCAN Message from Rx Buffer. + * + * This function reads a CAN message from the Rx Buffer in the Message RAM. + * + * @param base MCAN peripheral base address. + * @param idx The MCAN Rx Buffer index. + * @param pRxFrame Pointer to CAN message frame structure for reception. + * @retval kStatus_Success - Read Message from Rx Buffer successfully. + */ +status_t MCAN_ReadRxBuffer(CAN_Type *base, uint8_t idx, mcan_rx_buffer_frame_t *pRxFrame); + +/*! + * @brief Reads an MCAN Message from Rx FIFO. + * + * This function reads a CAN message from the Rx FIFO in the Message RAM. + * + * @param base MCAN peripheral base address. + * @param fifoBlock Rx FIFO block 0 or 1. + * @param pRxFrame Pointer to CAN message frame structure for reception. + * @retval kStatus_Success - Read Message from Rx FIFO successfully. + */ +status_t MCAN_ReadRxFifo(CAN_Type *base, uint8_t fifoBlock, mcan_rx_buffer_frame_t *pRxFrame); + +/* @} */ + +/*! + * @name Transactional + * @{ + */ + +/*! + * @brief Tx Buffer add request to send message out. + * + * This function add sending request to corresponding Tx Buffer. + * + * @param base MCAN peripheral base address. + * @param idx Tx Buffer index. + */ +static inline void MCAN_TransmitAddRequest(CAN_Type *base, uint8_t idx) +{ + base->TXBAR = ((uint32_t)1U << idx); +} + +/*! + * @brief Tx Buffer cancel sending request. + * + * This function clears Tx buffer request pending bit. + * + * @param base MCAN peripheral base address. + * @param idx Tx Buffer index. + */ +static inline void MCAN_TransmitCancelRequest(CAN_Type *base, uint8_t idx) +{ + base->TXBCR = ((uint32_t)1U << idx); +} + +/*! + * @brief Performs a polling send transaction on the CAN bus. + * + * Note that a transfer handle does not need to be created before calling this API. + * + * @param base MCAN peripheral base pointer. + * @param idx The MCAN buffer index. + * @param pTxFrame Pointer to CAN message frame to be sent. + * @retval kStatus_Success - Write Tx Message Buffer Successfully. + * @retval kStatus_Fail - Tx Message Buffer is currently in use. + */ +status_t MCAN_TransferSendBlocking(CAN_Type *base, uint8_t idx, mcan_tx_buffer_frame_t *pTxFrame); + +/*! + * @brief Performs a polling receive transaction on the CAN bus. + * + * Note that a transfer handle does not need to be created before calling this API. + * + * @param base MCAN peripheral base pointer. + * @param idx The MCAN buffer index. + * @param pRxFrame Pointer to CAN message frame structure for reception. + * @retval kStatus_Success - Read Rx Message Buffer Successfully. + * @retval kStatus_Fail - No new message. + */ +status_t MCAN_TransferReceiveBlocking(CAN_Type *base, uint8_t idx, mcan_rx_buffer_frame_t *pRxFrame); + +/*! + * @brief Performs a polling receive transaction from Rx FIFO on the CAN bus. + * + * Note that a transfer handle does not need to be created before calling this API. + * + * @param base MCAN peripheral base pointer. + * @param fifoBlock Rx FIFO block, 0 or 1. + * @param pRxFrame Pointer to CAN message frame structure for reception. + * @retval kStatus_Success - Read Message from Rx FIFO successfully. + * @retval kStatus_Fail - No new message in Rx FIFO. + */ +status_t MCAN_TransferReceiveFifoBlocking(CAN_Type *base, uint8_t fifoBlock, mcan_rx_buffer_frame_t *pRxFrame); + +/*! + * @brief Initializes the MCAN handle. + * + * This function initializes the MCAN handle, which can be used for other MCAN + * transactional APIs. Usually, for a specified MCAN instance, + * call this API once to get the initialized handle. + * + * @param base MCAN peripheral base address. + * @param handle MCAN handle pointer. + * @param callback The callback function. + * @param userData The parameter of the callback function. + */ +void MCAN_TransferCreateHandle(CAN_Type *base, + mcan_handle_t *handle, + mcan_transfer_callback_t callback, + void *userData); + +/*! + * @brief Sends a message using IRQ. + * + * This function sends a message using IRQ. This is a non-blocking function, which returns + * right away. When messages have been sent out, the send callback function is called. + * + * @param base MCAN peripheral base address. + * @param handle MCAN handle pointer. + * @param xfer MCAN Buffer transfer structure. See the #mcan_buffer_transfer_t. + * @retval kStatus_Success Start Tx Buffer sending process successfully. + * @retval kStatus_Fail Write Tx Buffer failed. + * @retval kStatus_MCAN_TxBusy Tx Buffer is in use. + */ +status_t MCAN_TransferSendNonBlocking(CAN_Type *base, mcan_handle_t *handle, mcan_buffer_transfer_t *xfer); + +/*! + * @brief Receives a message from Rx FIFO using IRQ. + * + * This function receives a message using IRQ. This is a non-blocking function, which returns + * right away. When all messages have been received, the receive callback function is called. + * + * @param base MCAN peripheral base address. + * @param handle MCAN handle pointer. + * @param fifoBlock Rx FIFO block, 0 or 1. + * @param xfer MCAN Rx FIFO transfer structure. See the @ref mcan_fifo_transfer_t. + * @retval kStatus_Success - Start Rx FIFO receiving process successfully. + * @retval kStatus_MCAN_RxFifo0Busy - Rx FIFO 0 is currently in use. + * @retval kStatus_MCAN_RxFifo1Busy - Rx FIFO 1 is currently in use. + */ +status_t MCAN_TransferReceiveFifoNonBlocking(CAN_Type *base, + uint8_t fifoBlock, + mcan_handle_t *handle, + mcan_fifo_transfer_t *xfer); + +/*! + * @brief Aborts the interrupt driven message send process. + * + * This function aborts the interrupt driven message send process. + * + * @param base MCAN peripheral base address. + * @param handle MCAN handle pointer. + * @param bufferIdx The MCAN Buffer index. + */ +void MCAN_TransferAbortSend(CAN_Type *base, mcan_handle_t *handle, uint8_t bufferIdx); + +/*! + * @brief Aborts the interrupt driven message receive from Rx FIFO process. + * + * This function aborts the interrupt driven message receive from Rx FIFO process. + * + * @param base MCAN peripheral base address. + * @param fifoBlock MCAN Fifo block, 0 or 1. + * @param handle MCAN handle pointer. + */ +void MCAN_TransferAbortReceiveFifo(CAN_Type *base, uint8_t fifoBlock, mcan_handle_t *handle); + +/*! + * @brief MCAN IRQ handle function. + * + * This function handles the MCAN Error, the Buffer, and the Rx FIFO IRQ request. + * + * @param base MCAN peripheral base address. + * @param handle MCAN handle pointer. + */ +void MCAN_TransferHandleIRQ(CAN_Type *base, mcan_handle_t *handle); + +/* @} */ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_MCAN_H_ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_mrt.c b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_mrt.c new file mode 100644 index 0000000000..69697a21b5 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_mrt.c @@ -0,0 +1,152 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017, 2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_mrt.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.mrt" +#endif + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Gets the instance from the base address + * + * @param base Multi-Rate timer peripheral base address + * + * @return The MRT instance + */ +static uint32_t MRT_GetInstance(MRT_Type *base); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Pointers to MRT bases for each instance. */ +static MRT_Type *const s_mrtBases[] = MRT_BASE_PTRS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Pointers to MRT clocks for each instance. */ +static const clock_ip_name_t s_mrtClocks[] = MRT_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) +#if defined(MRT_RSTS_N) +/*! @brief Pointers to MRT resets for each instance, writing a zero asserts the reset */ +static const reset_ip_name_t s_mrtResets[] = MRT_RSTS_N; +#elif defined(MRT_RSTS) +/*! @brief Pointers to MRT resets for each instance, writing a one asserts the reset */ +static const reset_ip_name_t s_mrtResets[] = MRT_RSTS; +#endif +#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ + +/******************************************************************************* + * Code + ******************************************************************************/ +static uint32_t MRT_GetInstance(MRT_Type *base) +{ + uint32_t instance; + uint32_t mrtArrayCount = (sizeof(s_mrtBases) / sizeof(s_mrtBases[0])); + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < mrtArrayCount; instance++) + { + if (s_mrtBases[instance] == base) + { + break; + } + } + + assert(instance < mrtArrayCount); + + return instance; +} + +/*! + * brief Ungates the MRT clock and configures the peripheral for basic operation. + * + * note This API should be called at the beginning of the application using the MRT driver. + * + * param base Multi-Rate timer peripheral base address + * param config Pointer to user's MRT config structure. If MRT has MULTITASK bit field in + * MODCFG reigster, param config is useless. + */ +void MRT_Init(MRT_Type *base, const mrt_config_t *config) +{ + assert(config != NULL); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Ungate the MRT clock */ + CLOCK_EnableClock(s_mrtClocks[MRT_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) +#if defined(MRT_RSTS_N) || defined(MRT_RSTS) + /* Reset the module. */ + RESET_PeripheralReset(s_mrtResets[MRT_GetInstance(base)]); +#endif +#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ + +#if !(defined(FSL_FEATURE_MRT_HAS_NO_MODCFG_MULTITASK) && FSL_FEATURE_MRT_HAS_NO_MODCFG_MULTITASK) + /* Set timer operating mode */ + base->MODCFG = MRT_MODCFG_MULTITASK(config->enableMultiTask); +#endif +} + +/*! + * brief Gate the MRT clock + * + * param base Multi-Rate timer peripheral base address + */ +void MRT_Deinit(MRT_Type *base) +{ + /* Stop all the timers */ + MRT_StopTimer(base, kMRT_Channel_0); + MRT_StopTimer(base, kMRT_Channel_1); +#if (FSL_FEATURE_MRT_NUMBER_OF_CHANNELS > 2U) + MRT_StopTimer(base, kMRT_Channel_2); +#endif +#if (FSL_FEATURE_MRT_NUMBER_OF_CHANNELS > 3U) + MRT_StopTimer(base, kMRT_Channel_3); +#endif + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Gate the MRT clock*/ + CLOCK_DisableClock(s_mrtClocks[MRT_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/*! + * brief Used to update the timer period in units of count. + * + * The new value will be immediately loaded or will be loaded at the end of the current time + * interval. For one-shot interrupt mode the new value will be immediately loaded. + * + * note User can call the utility macros provided in fsl_common.h to convert to ticks + * + * param base Multi-Rate timer peripheral base address + * param channel Timer channel number + * param count Timer period in units of ticks + * param immediateLoad true: Load the new value immediately into the TIMER register; + * false: Load the new value at the end of current timer interval + */ +void MRT_UpdateTimerPeriod(MRT_Type *base, mrt_chnl_t channel, uint32_t count, bool immediateLoad) +{ + assert((uint8_t)channel < (uint8_t)FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); + + uint32_t newValue = count; + if (((base->CHANNEL[channel].CTRL & MRT_CHANNEL_CTRL_MODE_MASK) == (uint8_t)kMRT_OneShotMode) || (immediateLoad)) + { + /* For one-shot interrupt mode, load the new value immediately even if user forgot to enable */ + newValue |= MRT_CHANNEL_INTVAL_LOAD_MASK; + } + + /* Update the timer interval value */ + base->CHANNEL[channel].INTVAL = newValue; +} diff --git a/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_mrt.h b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_mrt.h new file mode 100644 index 0000000000..7829d984e2 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_mrt.h @@ -0,0 +1,366 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017, 2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_MRT_H_ +#define _FSL_MRT_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup mrt + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +#define FSL_MRT_DRIVER_VERSION (MAKE_VERSION(2, 0, 3)) /*!< Version 2.0.3 */ +/*@}*/ + +/*! @brief List of MRT channels */ +typedef enum _mrt_chnl +{ + kMRT_Channel_0 = 0U, /*!< MRT channel number 0*/ + kMRT_Channel_1, /*!< MRT channel number 1 */ + kMRT_Channel_2, /*!< MRT channel number 2 */ + kMRT_Channel_3 /*!< MRT channel number 3 */ +} mrt_chnl_t; + +/*! @brief List of MRT timer modes */ +typedef enum _mrt_timer_mode +{ + kMRT_RepeatMode = (0 << MRT_CHANNEL_CTRL_MODE_SHIFT), /*!< Repeat Interrupt mode */ + kMRT_OneShotMode = (1 << MRT_CHANNEL_CTRL_MODE_SHIFT), /*!< One-shot Interrupt mode */ + kMRT_OneShotStallMode = (2 << MRT_CHANNEL_CTRL_MODE_SHIFT) /*!< One-shot stall mode */ +} mrt_timer_mode_t; + +/*! @brief List of MRT interrupts */ +typedef enum _mrt_interrupt_enable +{ + kMRT_TimerInterruptEnable = MRT_CHANNEL_CTRL_INTEN_MASK /*!< Timer interrupt enable*/ +} mrt_interrupt_enable_t; + +/*! @brief List of MRT status flags */ +typedef enum _mrt_status_flags +{ + kMRT_TimerInterruptFlag = MRT_CHANNEL_STAT_INTFLAG_MASK, /*!< Timer interrupt flag */ + kMRT_TimerRunFlag = MRT_CHANNEL_STAT_RUN_MASK, /*!< Indicates state of the timer */ +} mrt_status_flags_t; + +/*! + * @brief MRT configuration structure + * + * This structure holds the configuration settings for the MRT peripheral. To initialize this + * structure to reasonable defaults, call the MRT_GetDefaultConfig() function and pass a + * pointer to your config structure instance. + * + * The config struct can be made const so it resides in flash + */ +typedef struct _mrt_config +{ + bool enableMultiTask; /*!< true: Timers run in multi-task mode; false: Timers run in hardware status mode */ +} mrt_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Ungates the MRT clock and configures the peripheral for basic operation. + * + * @note This API should be called at the beginning of the application using the MRT driver. + * + * @param base Multi-Rate timer peripheral base address + * @param config Pointer to user's MRT config structure. If MRT has MULTITASK bit field in + * MODCFG reigster, param config is useless. + */ +void MRT_Init(MRT_Type *base, const mrt_config_t *config); + +/*! + * @brief Gate the MRT clock + * + * @param base Multi-Rate timer peripheral base address + */ +void MRT_Deinit(MRT_Type *base); + +/*! + * @brief Fill in the MRT config struct with the default settings + * + * The default values are: + * @code + * config->enableMultiTask = false; + * @endcode + * @param config Pointer to user's MRT config structure. + */ +static inline void MRT_GetDefaultConfig(mrt_config_t *config) +{ + assert(config != NULL); +#if !(defined(FSL_FEATURE_MRT_HAS_NO_MODCFG_MULTITASK) && FSL_FEATURE_MRT_HAS_NO_MODCFG_MULTITASK) + /* Use hardware status operating mode */ + config->enableMultiTask = false; +#endif +} + +/*! + * @brief Sets up an MRT channel mode. + * + * @param base Multi-Rate timer peripheral base address + * @param channel Channel that is being configured. + * @param mode Timer mode to use for the channel. + */ +static inline void MRT_SetupChannelMode(MRT_Type *base, mrt_chnl_t channel, const mrt_timer_mode_t mode) +{ + assert((uint8_t)channel < (uint8_t)FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); + + uint32_t reg = base->CHANNEL[channel].CTRL; + + /* Clear old value */ + reg &= ~MRT_CHANNEL_CTRL_MODE_MASK; + /* Add the new mode */ + reg |= (uint32_t)mode; + + base->CHANNEL[channel].CTRL = reg; +} + +/*! @}*/ + +/*! + * @name Interrupt Interface + * @{ + */ + +/*! + * @brief Enables the MRT interrupt. + * + * @param base Multi-Rate timer peripheral base address + * @param channel Timer channel number + * @param mask The interrupts to enable. This is a logical OR of members of the + * enumeration ::mrt_interrupt_enable_t + */ +static inline void MRT_EnableInterrupts(MRT_Type *base, mrt_chnl_t channel, uint32_t mask) +{ + assert((uint8_t)channel < (uint8_t)FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); + base->CHANNEL[channel].CTRL |= mask; +} + +/*! + * @brief Disables the selected MRT interrupt. + * + * @param base Multi-Rate timer peripheral base address + * @param channel Timer channel number + * @param mask The interrupts to disable. This is a logical OR of members of the + * enumeration ::mrt_interrupt_enable_t + */ +static inline void MRT_DisableInterrupts(MRT_Type *base, mrt_chnl_t channel, uint32_t mask) +{ + assert((uint8_t)channel < (uint8_t)FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); + base->CHANNEL[channel].CTRL &= ~mask; +} + +/*! + * @brief Gets the enabled MRT interrupts. + * + * @param base Multi-Rate timer peripheral base address + * @param channel Timer channel number + * + * @return The enabled interrupts. This is the logical OR of members of the + * enumeration ::mrt_interrupt_enable_t + */ +static inline uint32_t MRT_GetEnabledInterrupts(MRT_Type *base, mrt_chnl_t channel) +{ + assert((uint8_t)channel < (uint8_t)FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); + return (base->CHANNEL[channel].CTRL & MRT_CHANNEL_CTRL_INTEN_MASK); +} + +/*! @}*/ + +/*! + * @name Status Interface + * @{ + */ + +/*! + * @brief Gets the MRT status flags + * + * @param base Multi-Rate timer peripheral base address + * @param channel Timer channel number + * + * @return The status flags. This is the logical OR of members of the + * enumeration ::mrt_status_flags_t + */ +static inline uint32_t MRT_GetStatusFlags(MRT_Type *base, mrt_chnl_t channel) +{ + assert((uint8_t)channel < (uint8_t)FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); + return (base->CHANNEL[channel].STAT & (MRT_CHANNEL_STAT_INTFLAG_MASK | MRT_CHANNEL_STAT_RUN_MASK)); +} + +/*! + * @brief Clears the MRT status flags. + * + * @param base Multi-Rate timer peripheral base address + * @param channel Timer channel number + * @param mask The status flags to clear. This is a logical OR of members of the + * enumeration ::mrt_status_flags_t + */ +static inline void MRT_ClearStatusFlags(MRT_Type *base, mrt_chnl_t channel, uint32_t mask) +{ + assert((uint8_t)channel < (uint8_t)FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); + base->CHANNEL[channel].STAT = (mask & MRT_CHANNEL_STAT_INTFLAG_MASK); +} + +/*! @}*/ + +/*! + * @name Read and Write the timer period + * @{ + */ + +/*! + * @brief Used to update the timer period in units of count. + * + * The new value will be immediately loaded or will be loaded at the end of the current time + * interval. For one-shot interrupt mode the new value will be immediately loaded. + * + * @note User can call the utility macros provided in fsl_common.h to convert to ticks + * + * @param base Multi-Rate timer peripheral base address + * @param channel Timer channel number + * @param count Timer period in units of ticks + * @param immediateLoad true: Load the new value immediately into the TIMER register; + * false: Load the new value at the end of current timer interval + */ +void MRT_UpdateTimerPeriod(MRT_Type *base, mrt_chnl_t channel, uint32_t count, bool immediateLoad); + +/*! + * @brief Reads the current timer counting value. + * + * This function returns the real-time timer counting value, in a range from 0 to a + * timer period. + * + * @note User can call the utility macros provided in fsl_common.h to convert ticks to usec or msec + * + * @param base Multi-Rate timer peripheral base address + * @param channel Timer channel number + * + * @return Current timer counting value in ticks + */ +static inline uint32_t MRT_GetCurrentTimerCount(MRT_Type *base, mrt_chnl_t channel) +{ + assert((uint8_t)channel < (uint8_t)FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); + return base->CHANNEL[channel].TIMER; +} + +/*! @}*/ + +/*! + * @name Timer Start and Stop + * @{ + */ + +/*! + * @brief Starts the timer counting. + * + * After calling this function, timers load period value, counts down to 0 and + * depending on the timer mode it will either load the respective start value again or stop. + * + * @note User can call the utility macros provided in fsl_common.h to convert to ticks + * + * @param base Multi-Rate timer peripheral base address + * @param channel Timer channel number. + * @param count Timer period in units of ticks. Count can contain the LOAD bit, which control the force load feature. + */ +static inline void MRT_StartTimer(MRT_Type *base, mrt_chnl_t channel, uint32_t count) +{ + assert((uint8_t)channel < (uint8_t)FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); + assert((uint32_t)(count & ~MRT_CHANNEL_INTVAL_LOAD_MASK) <= (uint32_t)MRT_CHANNEL_INTVAL_IVALUE_MASK); + /* Write the timer interval value */ + base->CHANNEL[channel].INTVAL = count; +} + +/*! + * @brief Stops the timer counting. + * + * This function stops the timer from counting. + * + * @param base Multi-Rate timer peripheral base address + * @param channel Timer channel number. + */ +static inline void MRT_StopTimer(MRT_Type *base, mrt_chnl_t channel) +{ + assert((uint8_t)channel < (uint8_t)FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); + /* Stop the timer immediately */ + base->CHANNEL[channel].INTVAL = MRT_CHANNEL_INTVAL_LOAD_MASK; +} + +/*! @}*/ + +/*! + * @name Get & release channel + * @{ + */ + +/*! + * @brief Find the available channel. + * + * This function returns the lowest available channel number. + * + * @param base Multi-Rate timer peripheral base address + */ +static inline uint32_t MRT_GetIdleChannel(MRT_Type *base) +{ + return base->IDLE_CH; +} + +#if !(defined(FSL_FEATURE_MRT_HAS_NO_CHANNEL_STAT_INUSE) && FSL_FEATURE_MRT_HAS_NO_CHANNEL_STAT_INUSE) +/*! + * @brief Release the channel when the timer is using the multi-task mode. + * + * In multi-task mode, the INUSE flags allow more control over when MRT channels are released for + * further use. The user can hold on to a channel acquired by calling MRT_GetIdleChannel() for as + * long as it is needed and release it by calling this function. This removes the need to ask for + * an available channel for every use. + * + * @param base Multi-Rate timer peripheral base address + * @param channel Timer channel number. + */ +static inline void MRT_ReleaseChannel(MRT_Type *base, mrt_chnl_t channel) +{ + assert((uint8_t)channel < (uint8_t)FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); + + uint32_t reg = base->CHANNEL[channel].STAT; + + /* Clear flag bits to prevent accidentally clearing anything when writing back */ + reg = ~MRT_CHANNEL_STAT_INTFLAG_MASK; + reg |= MRT_CHANNEL_STAT_INUSE_MASK; + + base->CHANNEL[channel].STAT = reg; +} +#endif + +/*! @}*/ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_MRT_H_ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_ostimer.c b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_ostimer.c new file mode 100644 index 0000000000..c3acfb0e48 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_ostimer.c @@ -0,0 +1,381 @@ +/* + * Copyright 2018-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_ostimer.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.ostimer" +#endif + +/* Typedef for interrupt handler. */ +typedef void (*ostimer_isr_t)(OSTIMER_Type *base, ostimer_callback_t cb); + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Gets the instance from the base address + * + * @param base OSTIMER peripheral base address + * + * @return The OSTIMER instance + */ +static uint32_t OSTIMER_GetInstance(OSTIMER_Type *base); + +#if (defined(FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY) && FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY) +/* @brief Translate the value from gray-code to decimal by the Code Gray in SYSCTL. + * + * @param gray The gray value input. + * + * @return the decimal value. + */ +static uint64_t OSTIMER_GrayToDecimalbyCodeGray(uint64_t gray); +#endif /* FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY. */ + +/******************************************************************************* + * Variables + ******************************************************************************/ +/* Array of OSTIMER handle. */ +static ostimer_callback_t s_ostimerHandle[FSL_FEATURE_SOC_OSTIMER_COUNT]; +/* Array of OSTIMER peripheral base address. */ +static OSTIMER_Type *const s_ostimerBases[] = OSTIMER_BASE_PTRS; +/* Array of OSTIMER IRQ number. */ +static const IRQn_Type s_ostimerIRQ[] = OSTIMER_IRQS; +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/* Array of OSTIMER clock name. */ +static const clock_ip_name_t s_ostimerClock[] = OSTIMER_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/* OSTIMER ISR for transactional APIs. */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +static ostimer_isr_t s_ostimerIsr = (ostimer_isr_t)DefaultISR; +#else +static ostimer_isr_t s_ostimerIsr; +#endif + +/******************************************************************************* + * Code + ******************************************************************************/ + +/* @brief Function for getting the instance number of OS timer. */ +static uint32_t OSTIMER_GetInstance(OSTIMER_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_ostimerBases); instance++) + { + if (s_ostimerBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_ostimerBases)); + + return instance; +} + +#if (defined(FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY) && FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY) +/* @brief Translate the value from gray-code to decimal by the Code Gray in SYSCTL. + * + * @param gray The gray value input. + * + * @return the decimal value. + */ +static uint64_t OSTIMER_GrayToDecimalbyCodeGray(uint64_t gray) +{ + uint64_t decOut; + + SYSCTL->CODE_GRAY_LSB = (uint32_t)(gray & 0xFFFFFFFFU); + SYSCTL->CODE_GRAY_MSB = (uint32_t)((gray >> 32U) & 0x3FFU); // limit to 42bits as OSevent timer + __NOP(); + decOut = ((uint64_t)(SYSCTL->CODE_BIN_MSB) & 0x3FFU) << 32U; + decOut |= (uint64_t)(SYSCTL->CODE_BIN_LSB); + + return decOut; +} +#endif /* FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY. */ + +/* @brief Translate the value from gray-code to decimal. */ +/* + * @param gray The gray value input. + * + * @return the decimal value. + */ +uint64_t OSTIMER_GrayToDecimal(uint64_t gray) +{ +#if (defined(FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY) && FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY) + return OSTIMER_GrayToDecimalbyCodeGray(gray); +#else + uint64_t temp = gray; + while (temp != 0U) + { + temp >>= 1U; + gray ^= temp; + } + + return gray; +#endif /* FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY. */ +} + +/* @brief Enable the OSTIMER interrupt. + * + * After calling this function, the OSTIMER driver will enable/disable the IRQ and module interrupt enablement. + * + * @param base OSTIMER peripheral base address. + * @param enable enable/disable the IRQ and module interrupt enablement. + * - true: Disable the IRQ and module interrupt enablement. + * - false: Disable the IRQ and module interrupt enablement. + * @return none + */ +static void OSTIMER_EnableInterrupt(OSTIMER_Type *base, bool enable) +{ + assert(NULL != base); + + if (enable) + { + /* Enable the IRQ and module interrupt enablement. */ + (void)EnableIRQ(s_ostimerIRQ[OSTIMER_GetInstance(base)]); + base->OSEVENT_CTRL |= OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_MASK; + } + else + { + /* Clear interrupt flag, disable the IRQ and module interrupt enablement. */ + (void)DisableIRQ(s_ostimerIRQ[OSTIMER_GetInstance(base)]); + base->OSEVENT_CTRL &= ~OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_MASK; /* Clear interrupt flag by writing 1. */ + } +} + +/*! + * @brief Initializes an OSTIMER by turning it's clock on. + * + */ +void OSTIMER_Init(OSTIMER_Type *base) +{ + assert(NULL != base); + + uint32_t instance = OSTIMER_GetInstance(base); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +#if !(defined(FSL_FEATURE_PMC_HAS_NO_OSTIMER_REG) && FSL_FEATURE_PMC_HAS_NO_OSTIMER_REG) + /* Enable the OSTIMER 32k clock in PMC module. */ + CLOCK_EnableOstimer32kClock(); +#endif + /* Enable clock for OSTIMER. */ + CLOCK_EnableClock(s_ostimerClock[instance]); +#if (defined(FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY) && FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY) + CLOCK_EnableClock(kCLOCK_Sysctl); +#endif /* FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY. */ +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/*! + * @brief Deinitializes a OSTIMER instance. + * + * This function shuts down OSTIMER clock + * + * @param base OSTIMER peripheral base address. + */ +void OSTIMER_Deinit(OSTIMER_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable clock for OSTIMER. */ + CLOCK_DisableClock(s_ostimerClock[OSTIMER_GetInstance(base)]); +#if (defined(FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY) && FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY) + CLOCK_DisableClock(kCLOCK_Sysctl); +#endif /* FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY. */ +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/*! + * @brief Get OSTIMER status Flags. + * + * This returns the status flag. + * Currently, only match interrupt flag can be got. + * + * @param base OSTIMER peripheral base address. + * @return status register value + */ +uint32_t OSTIMER_GetStatusFlags(OSTIMER_Type *base) +{ + return base->OSEVENT_CTRL & OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_MASK; +} + +/*! + * @brief Clear Status Interrupt Flags. + * + * This clears intr status flag. + * Currently, only match interrupt flag can be cleared. + * + * @param base OSTIMER peripheral base address. + * @param mask Clear bit mask. + * @return none + */ +void OSTIMER_ClearStatusFlags(OSTIMER_Type *base, uint32_t mask) +{ + base->OSEVENT_CTRL |= mask; +} + +/*! + * @brief Set the match raw value for OSTIMER. + * + * This function will set a match value for OSTIMER with an optional callback. And this callback + * will be called while the data in dedicated pair match register is equals to the value of central EVTIMER. + * Please note that, the data format is gray-code, if decimal data was desired, please using OSTIMER_SetMatchValue(). + * + * @param base OSTIMER peripheral base address. + * @param count OSTIMER timer match value.(Value is gray-code format) + * + * @param cb OSTIMER callback (can be left as NULL if none, otherwise should be a void func(void)). + * @retval kStatus_Success - Set match raw value and enable interrupt Successfully. + * @retval kStatus_Fail - Set match raw value fail. + */ +status_t OSTIMER_SetMatchRawValue(OSTIMER_Type *base, uint64_t count, ostimer_callback_t cb) +{ +#ifdef OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_MASK + uint64_t decValueTimer; +#endif + status_t status; + uint64_t tmp = count; + uint32_t instance = OSTIMER_GetInstance(base); + + /* Clear interrupt flag, disable the IRQ and module interrupt enablement. */ + OSTIMER_EnableInterrupt(base, false); + + s_ostimerIsr = OSTIMER_HandleIRQ; + s_ostimerHandle[instance] = cb; + + /* Set the match value. */ + base->MATCH_L = (uint32_t)tmp; + base->MATCH_H = (uint32_t)(tmp >> 32U); + +#ifdef OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_MASK + /* Workaround-2019-12-30: + * Since OSTimer's counter register is Gray-encoded, it would cost more time to write register. When EVTimer Match + * Write Ready bit is low, which means the previous match value has been updated successfully by that time, it is + * safe to reload (write) the Match Registers. Even if there is the RM comment that "In typical applications, it + * should not be necessary to test this bit", but we found the interruption would not be reported when the delta + * timer user added is smaller(IE: RT595 11us in 1MHz typical application) in release version." To prevent such + * issue from happening, we'd better wait for the match value to update successfully before enabling IRQ. + */ + while (0U != (base->OSEVENT_CTRL & OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_MASK)) + { + } + + /* After the WR_RDY bit became low, we need to check whether current time goes ahead of the match value we set. + * (1) If current timer value has gone ahead of the match value, the interrupt will not be reported before 64-bit + * timer value over flow. We need to check whether the interrupt flag has been set or not: if yes, we will enable + * interrupt and return success; if not, we will return fail directly. + * (2) If current timer value has not gone ahead of match value, we will enable interrupt and return success. + */ + decValueTimer = OSTIMER_GetCurrentTimerValue(base); + if ((decValueTimer >= OSTIMER_GrayToDecimal(tmp)) && + (0U == (base->OSEVENT_CTRL & (uint32_t)kOSTIMER_MatchInterruptFlag))) + { + status = kStatus_Fail; + } + else +#endif /* #ifdef OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_MASK */ + { + /* Enable the module interrupt enablement. */ + OSTIMER_EnableInterrupt(base, true); + status = kStatus_Success; + } + + return status; +} + +/*! + * @brief Set the match value for OSTIMER. + * + * This function will set a match value for OSTIMER with an optional callback. And this callback + * will be called while the data in dedicated pair match register is equals to the value of central EVTIMER. + * + * @param base OSTIMER peripheral base address. + * @param count OSTIMER timer match value.(Value is decimal format, and this value will be translate to Gray code in + * API. ) + * @param cb OSTIMER callback (can be left as NULL if none, otherwise should be a void func(void)). + * @retval kStatus_Success - Set match value and enable interrupt Successfully. + * @retval kStatus_Fail - Set match value fail. + */ +status_t OSTIMER_SetMatchValue(OSTIMER_Type *base, uint64_t count, ostimer_callback_t cb) +{ + uint64_t tmp = OSTIMER_DecimalToGray(count); + + return OSTIMER_SetMatchRawValue(base, tmp, cb); +} + +/*! + * @brief Get current timer count value from OSTIMER. + * + * This function will get a decimal timer count value. + * The RAW value of timer count is gray code format, will be translated to decimal data internally. + * + * @param base OSTIMER peripheral base address. + * @return Value of OSTIMER which will formated to decimal value. + */ +uint64_t OSTIMER_GetCurrentTimerValue(OSTIMER_Type *base) +{ + uint64_t tmp = 0U; + + tmp = OSTIMER_GetCurrentTimerRawValue(base); + + return OSTIMER_GrayToDecimal(tmp); +} + +/*! + * @brief Get the capture value from OSTIMER. + * + * This function will get a capture decimal-value from OSTIMER. + * The RAW value of timer capture is gray code format, will be translated to decimal data internally. + * + * @param base OSTIMER peripheral base address. + * @return Value of capture register, data format is decimal. + */ +uint64_t OSTIMER_GetCaptureValue(OSTIMER_Type *base) +{ + uint64_t tmp = 0U; + + tmp = OSTIMER_GetCaptureRawValue(base); + + return OSTIMER_GrayToDecimal(tmp); +} + +void OSTIMER_HandleIRQ(OSTIMER_Type *base, ostimer_callback_t cb) +{ + /* Clear interrupt flag, disable the IRQ and module interrupt enablement. */ + OSTIMER_EnableInterrupt(base, false); + + if (cb != NULL) + { + cb(); + } +} + +#if defined(OSTIMER0) +void OS_EVENT_DriverIRQHandler(void); +void OS_EVENT_DriverIRQHandler(void) +{ + s_ostimerIsr(OSTIMER0, s_ostimerHandle[0]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(OSTIMER) +void OS_EVENT_DriverIRQHandler(void); +void OS_EVENT_DriverIRQHandler(void) +{ + s_ostimerIsr(OSTIMER, s_ostimerHandle[0]); + SDK_ISR_EXIT_BARRIER; +} +#endif diff --git a/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_ostimer.h b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_ostimer.h new file mode 100644 index 0000000000..c74a793136 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_ostimer.h @@ -0,0 +1,273 @@ +/* + * Copyright 2018-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_OSTIMER_H_ +#define _FSL_OSTIMER_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup ostimer + * @{ + */ + +/*! @file*/ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief OSTIMER driver version. */ +#define FSL_OSTIMER_DRIVER_VERSION (MAKE_VERSION(2, 2, 0)) +/*@}*/ + +/*! + * @brief OSTIMER status flags. + */ +enum _ostimer_flags +{ + kOSTIMER_MatchInterruptFlag = (OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_MASK), /*!< Match interrupt flag bit, sets if + the match value was reached. */ +}; + +/*! @brief ostimer callback function. */ +typedef void (*ostimer_callback_t)(void); + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* _cplusplus */ + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Initializes an OSTIMER by turning its bus clock on + * + */ +void OSTIMER_Init(OSTIMER_Type *base); + +/*! + * @brief Deinitializes a OSTIMER instance. + * + * This function shuts down OSTIMER bus clock + * + * @param base OSTIMER peripheral base address. + */ +void OSTIMER_Deinit(OSTIMER_Type *base); + +/*! + * @brief Translate the value from gray-code to decimal. + * + * @param gray The gray value input. + * @return The decimal value. + */ +uint64_t OSTIMER_GrayToDecimal(uint64_t gray); + +/*! + * @brief Translate the value from decimal to gray-code. + * + * @param dec The decimal value. + * @return The gray code of the input value. + */ +static inline uint64_t OSTIMER_DecimalToGray(uint64_t dec) +{ + return (dec ^ (dec >> 1U)); +} + +/*! + * @brief Get OSTIMER status Flags. + * + * This returns the status flag. + * Currently, only match interrupt flag can be got. + * + * @param base OSTIMER peripheral base address. + * @return status register value + */ +uint32_t OSTIMER_GetStatusFlags(OSTIMER_Type *base); + +/*! + * @brief Clear Status Interrupt Flags. + * + * This clears intrrupt status flag. + * Currently, only match interrupt flag can be cleared. + * + * @param base OSTIMER peripheral base address. + * @param mask Clear bit mask. + * @return none + */ +void OSTIMER_ClearStatusFlags(OSTIMER_Type *base, uint32_t mask); + +/*! + * @brief Set the match raw value for OSTIMER. + * + * This function will set a match value for OSTIMER with an optional callback. And this callback + * will be called while the data in dedicated pair match register is equals to the value of central EVTIMER. + * Please note that, the data format is gray-code, if decimal data was desired, please using OSTIMER_SetMatchValue(). + * + * @param base OSTIMER peripheral base address. + * @param count OSTIMER timer match value.(Value is gray-code format) + * + * @param cb OSTIMER callback (can be left as NULL if none, otherwise should be a void func(void)). + * @retval kStatus_Success - Set match raw value and enable interrupt Successfully. + * @retval kStatus_Fail - Set match raw value fail. + */ +status_t OSTIMER_SetMatchRawValue(OSTIMER_Type *base, uint64_t count, ostimer_callback_t cb); + +/*! + * @brief Set the match value for OSTIMER. + * + * This function will set a match value for OSTIMER with an optional callback. And this callback + * will be called while the data in dedicated pair match register is equals to the value of central OS TIMER. + * + * @param base OSTIMER peripheral base address. + * @param count OSTIMER timer match value.(Value is decimal format, and this value will be translate to Gray code + * internally.) + * + * @param cb OSTIMER callback (can be left as NULL if none, otherwise should be a void func(void)). + * @retval kStatus_Success - Set match value and enable interrupt Successfully. + * @retval kStatus_Fail - Set match value fail. + */ +status_t OSTIMER_SetMatchValue(OSTIMER_Type *base, uint64_t count, ostimer_callback_t cb); + +/*! + * @brief Set value to OSTIMER MATCH register directly. + * + * This function writes the input value to OSTIMER MATCH register directly, + * it does not touch any other registers. Note that, the data format is + * gray-code. The function @ref OSTIMER_DecimalToGray could convert decimal + * value to gray code. + * + * @param base OSTIMER peripheral base address. + * @param count OSTIMER timer match value (Value is gray-code format). + */ +static inline void OSTIMER_SetMatchRegister(OSTIMER_Type *base, uint64_t value) +{ +#ifdef OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_MASK + /* Wait for MATCH register ready for write. */ + while (0U != (base->OSEVENT_CTRL & OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_MASK)) + { + } +#endif + + base->MATCH_L = (uint32_t)value; + base->MATCH_H = (uint32_t)(value >> 32U); +} + +/*! + * @brief Enable the OSTIMER counter match interrupt. + * + * Enable the timer counter match interrupt. The interrupt happens when OSTIMER + * counter matches the value in MATCH registers. + * + * @param base OSTIMER peripheral base address. + */ +static inline void OSTIMER_EnableMatchInterrupt(OSTIMER_Type *base) +{ + base->OSEVENT_CTRL |= OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_MASK; +} + +/*! + * @brief Disable the OSTIMER counter match interrupt. + * + * Disable the timer counter match interrupt. The interrupt happens when OSTIMER + * counter matches the value in MATCH registers. + * + * @param base OSTIMER peripheral base address. + */ +static inline void OSTIMER_DisableMatchInterrupt(OSTIMER_Type *base) +{ + base->OSEVENT_CTRL &= ~OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_MASK; +} + +/*! + * @brief Get current timer raw count value from OSTIMER. + * + * This function will get a gray code type timer count value from OS timer register. + * The raw value of timer count is gray code format. + * + * @param base OSTIMER peripheral base address. + * @return Raw value of OSTIMER, gray code format. + */ +static inline uint64_t OSTIMER_GetCurrentTimerRawValue(OSTIMER_Type *base) +{ + uint64_t tmp = 0U; + + tmp = base->EVTIMERL; + tmp |= (uint64_t)(base->EVTIMERH) << 32U; + + return tmp; +} + +/*! + * @brief Get current timer count value from OSTIMER. + * + * This function will get a decimal timer count value. + * The RAW value of timer count is gray code format, will be translated to decimal data internally. + * + * @param base OSTIMER peripheral base address. + * @return Value of OSTIMER which will be formated to decimal value. + */ +uint64_t OSTIMER_GetCurrentTimerValue(OSTIMER_Type *base); + +/*! + * @brief Get the capture value from OSTIMER. + * + * This function will get a captured gray-code value from OSTIMER. + * The Raw value of timer capture is gray code format. + * + * @param base OSTIMER peripheral base address. + * @return Raw value of capture register, data format is gray code. + */ +static inline uint64_t OSTIMER_GetCaptureRawValue(OSTIMER_Type *base) +{ + uint64_t tmp = 0U; + + tmp = base->CAPTURE_L; + tmp |= (uint64_t)(base->CAPTURE_H) << 32U; + + return tmp; +} + +/*! + * @brief Get the capture value from OSTIMER. + * + * This function will get a capture decimal-value from OSTIMER. + * The RAW value of timer capture is gray code format, will be translated to decimal data internally. + * + * @param base OSTIMER peripheral base address. + * @return Value of capture register, data format is decimal. + */ +uint64_t OSTIMER_GetCaptureValue(OSTIMER_Type *base); + +/*! + * @brief OS timer interrupt Service Handler. + * + * This function handles the interrupt and refers to the callback array in the driver to callback user (as per request + * in OSTIMER_SetMatchValue()). + * if no user callback is scheduled, the interrupt will simply be cleared. + * + * @param base OS timer peripheral base address. + * @param cb callback scheduled for this instance of OS timer + * @return none + */ +void OSTIMER_HandleIRQ(OSTIMER_Type *base, ostimer_callback_t cb); +/* @} */ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_OSTIMER_H_ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_pint.c b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_pint.c new file mode 100644 index 0000000000..74b44ea7ad --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_pint.c @@ -0,0 +1,971 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_pint.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.pint" +#endif + +/******************************************************************************* + * Variables + ******************************************************************************/ + +#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) +/*! @brief Irq number array */ +static const IRQn_Type s_pintIRQ[FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS + + FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS] = PINT_IRQS; + +/*! @brief Callback function array for SECPINT(s). */ +static pint_cb_t s_secpintCallback[FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS]; +#else +/*! @brief Irq number array */ +static const IRQn_Type s_pintIRQ[FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS] = PINT_IRQS; +#endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */ + +/*! @brief Callback function array for PINT(s). */ +static pint_cb_t s_pintCallback[FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS]; + +/******************************************************************************* + * Code + ******************************************************************************/ + +/*! + * brief Initialize PINT peripheral. + + * This function initializes the PINT peripheral and enables the clock. + * + * param base Base address of the PINT peripheral. + * + * retval None. + */ +void PINT_Init(PINT_Type *base) +{ + uint32_t i; + uint32_t pmcfg = 0; + uint8_t pintcount = 0; + assert(base != NULL); + + if (base == PINT) + { + pintcount = FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; + /* clear PINT callback array*/ + for (i = 0; i < (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; i++) + { + s_pintCallback[i] = NULL; + } + } + else + { +#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) + pintcount = FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS; + /* clear SECPINT callback array*/ + for (i = 0; i < (uint32_t)FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS; i++) + { + s_secpintCallback[i] = NULL; + } +#endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */ + } + + /* Disable all bit slices for pint*/ + for (i = 0; i < pintcount; i++) + { + pmcfg = pmcfg | ((uint32_t)kPINT_PatternMatchNever << (PININT_BITSLICE_CFG_START + (i * 3U))); + } + +#if defined(FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE) && (FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE == 1) + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable the clock. */ + CLOCK_EnableClock(kCLOCK_GpioInt); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) + /* Reset the module. */ + RESET_PeripheralReset(kGPIOINT_RST_N_SHIFT_RSTn); +#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ + +#elif defined(FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE) && (FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE == 0) + + if (base == PINT) + { +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable the clock. */ + CLOCK_EnableClock(kCLOCK_Gpio0); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) + /* Reset the module. */ + RESET_PeripheralReset(kGPIO0_RST_N_SHIFT_RSTn); +#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ + } + else + { +#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable the clock. */ + CLOCK_EnableClock(kCLOCK_Gpio_Sec); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) + /* Reset the module. */ + RESET_PeripheralReset(kGPIOSEC_RST_SHIFT_RSTn); +#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ +#endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */ + } + +#else + + if (base == PINT) + { +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable the clock. */ + CLOCK_EnableClock(kCLOCK_Pint); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) + /* Reset the module. */ + RESET_PeripheralReset(kPINT_RST_SHIFT_RSTn); +#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ + } + else + { + /* if need config SECURE PINT device,then enable secure pint interrupt clock */ +#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable the clock. */ + CLOCK_EnableClock(kCLOCK_Gpio_Sec_Int); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) + /* Reset the module. */ + RESET_PeripheralReset(kGPIOSECINT_RST_SHIFT_RSTn); +#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ +#endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */ + } +#endif /* FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE */ + + /* Disable all pattern match bit slices */ + base->PMCFG = pmcfg; +} + +/*! + * brief Configure PINT peripheral pin interrupt. + + * This function configures a given pin interrupt. + * + * param base Base address of the PINT peripheral. + * param intr Pin interrupt. + * param enable Selects detection logic. + * param callback Callback. + * + * retval None. + */ +void PINT_PinInterruptConfig(PINT_Type *base, pint_pin_int_t intr, pint_pin_enable_t enable, pint_cb_t callback) +{ + assert(base != NULL); + + /* Clear Rise and Fall flags first */ + PINT_PinInterruptClrRiseFlag(base, intr); + PINT_PinInterruptClrFallFlag(base, intr); + + /* Security PINT uses additional callback array */ + if (base == PINT) + { + s_pintCallback[intr] = callback; + } + else + { +#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) + s_secpintCallback[intr] = callback; +#endif + } + + /* select level or edge sensitive */ + base->ISEL = (base->ISEL & ~(1UL << (uint32_t)intr)) | + ((((uint32_t)enable & PINT_PIN_INT_LEVEL) != 0U) ? (1UL << (uint32_t)intr) : 0U); + + /* enable rising or level interrupt */ + if (((unsigned)enable & (PINT_PIN_INT_LEVEL | PINT_PIN_INT_RISE)) != 0U) + { + base->SIENR = 1UL << (uint32_t)intr; + } + else + { + base->CIENR = 1UL << (uint32_t)intr; + } + + /* Enable falling or select high level */ + if (((unsigned)enable & PINT_PIN_INT_FALL_OR_HIGH_LEVEL) != 0U) + { + base->SIENF = 1UL << (uint32_t)intr; + } + else + { + base->CIENF = 1UL << (uint32_t)intr; + } +} + +/*! + * brief Get PINT peripheral pin interrupt configuration. + + * This function returns the configuration of a given pin interrupt. + * + * param base Base address of the PINT peripheral. + * param pintr Pin interrupt. + * param enable Pointer to store the detection logic. + * param callback Callback. + * + * retval None. + */ +void PINT_PinInterruptGetConfig(PINT_Type *base, pint_pin_int_t pintr, pint_pin_enable_t *enable, pint_cb_t *callback) +{ + uint32_t mask; + bool level; + + assert(base != NULL); + + *enable = kPINT_PinIntEnableNone; + level = false; + + mask = 1UL << (uint32_t)pintr; + if ((base->ISEL & mask) != 0U) + { + /* Pin interrupt is level sensitive */ + level = true; + } + + if ((base->IENR & mask) != 0U) + { + if (level) + { + /* Level interrupt is enabled */ + *enable = kPINT_PinIntEnableLowLevel; + } + else + { + /* Rising edge interrupt */ + *enable = kPINT_PinIntEnableRiseEdge; + } + } + + if ((base->IENF & mask) != 0U) + { + if (level) + { + /* Level interrupt is active high */ + *enable = kPINT_PinIntEnableHighLevel; + } + else + { + /* Either falling or both edge */ + if (*enable == kPINT_PinIntEnableRiseEdge) + { + /* Rising and faling edge */ + *enable = kPINT_PinIntEnableBothEdges; + } + else + { + /* Falling edge */ + *enable = kPINT_PinIntEnableFallEdge; + } + } + } + + /* Security PINT uses additional callback array */ + if (base == PINT) + { + *callback = s_pintCallback[pintr]; + } + else + { +#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) + *callback = s_secpintCallback[pintr]; +#endif + } +} + +/*! + * brief Configure PINT pattern match. + + * This function configures a given pattern match bit slice. + * + * param base Base address of the PINT peripheral. + * param bslice Pattern match bit slice number. + * param cfg Pointer to bit slice configuration. + * + * retval None. + */ +void PINT_PatternMatchConfig(PINT_Type *base, pint_pmatch_bslice_t bslice, pint_pmatch_cfg_t *cfg) +{ + uint32_t src_shift; + uint32_t cfg_shift; + uint32_t pmcfg; + uint32_t tmp_src_shift = PININT_BITSLICE_SRC_MASK; + uint32_t tmp_cfg_shift = PININT_BITSLICE_CFG_MASK; + + assert(base != NULL); + + src_shift = PININT_BITSLICE_SRC_START + ((uint32_t)bslice * 3UL); + cfg_shift = PININT_BITSLICE_CFG_START + ((uint32_t)bslice * 3UL); + + /* Input source selection for selected bit slice */ + base->PMSRC = (base->PMSRC & ~(tmp_src_shift << src_shift)) | ((uint32_t)(cfg->bs_src) << src_shift); + + /* Bit slice configuration */ + pmcfg = base->PMCFG; + pmcfg = (pmcfg & ~(tmp_cfg_shift << cfg_shift)) | ((uint32_t)(cfg->bs_cfg) << cfg_shift); + + /* If end point is true, enable the bits */ + if ((uint32_t)bslice != 7UL) + { + if (cfg->end_point) + { + pmcfg |= (1UL << (uint32_t)bslice); + } + else + { + pmcfg &= ~(1UL << (uint32_t)bslice); + } + } + + base->PMCFG = pmcfg; + + /* Save callback pointer */ + if (base == PINT) + { + if ((uint32_t)bslice < (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS) + { + s_pintCallback[bslice] = cfg->callback; + } + } + else + { +#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) + if ((uint32_t)bslice < (uint32_t)FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) + { + s_secpintCallback[bslice] = cfg->callback; + } +#endif + } +} + +/*! + * brief Get PINT pattern match configuration. + + * This function returns the configuration of a given pattern match bit slice. + * + * param base Base address of the PINT peripheral. + * param bslice Pattern match bit slice number. + * param cfg Pointer to bit slice configuration. + * + * retval None. + */ +void PINT_PatternMatchGetConfig(PINT_Type *base, pint_pmatch_bslice_t bslice, pint_pmatch_cfg_t *cfg) +{ + uint32_t src_shift; + uint32_t cfg_shift; + uint32_t tmp_src_shift = PININT_BITSLICE_SRC_MASK; + uint32_t tmp_cfg_shift = PININT_BITSLICE_CFG_MASK; + + assert(base != NULL); + + src_shift = PININT_BITSLICE_SRC_START + ((uint32_t)bslice * 3UL); + cfg_shift = PININT_BITSLICE_CFG_START + ((uint32_t)bslice * 3UL); + + cfg->bs_src = (pint_pmatch_input_src_t)(uint32_t)((base->PMSRC & (tmp_src_shift << src_shift)) >> src_shift); + cfg->bs_cfg = (pint_pmatch_bslice_cfg_t)(uint32_t)((base->PMCFG & (tmp_cfg_shift << cfg_shift)) >> cfg_shift); + + if ((uint32_t)bslice == 7U) + { + cfg->end_point = true; + } + else + { + cfg->end_point = (((base->PMCFG & (1UL << (uint32_t)bslice)) >> (uint32_t)bslice) != 0U) ? true : false; + } + + if (base == PINT) + { + if ((uint32_t)bslice < (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS) + { + cfg->callback = s_pintCallback[bslice]; + } + } + else + { +#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) + if ((uint32_t)bslice < (uint32_t)FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) + { + cfg->callback = s_secpintCallback[bslice]; + } +#endif + } +} + +/*! + * brief Reset pattern match detection logic. + + * This function resets the pattern match detection logic if any of the product term is matching. + * + * param base Base address of the PINT peripheral. + * + * retval pmstatus Each bit position indicates the match status of corresponding bit slice. + * = 0 Match was detected. = 1 Match was not detected. + */ +uint32_t PINT_PatternMatchResetDetectLogic(PINT_Type *base) +{ + uint32_t pmctrl; + uint32_t pmstatus; + uint32_t pmsrc; + + pmctrl = base->PMCTRL; + pmstatus = pmctrl >> PINT_PMCTRL_PMAT_SHIFT; + if (pmstatus != 0UL) + { + /* Reset Pattern match engine detection logic */ + pmsrc = base->PMSRC; + base->PMSRC = pmsrc; + } + return (pmstatus); +} + +/*! + * @brief Clear Selected pin interrupt status only when the pin was triggered by edge-sensitive. + + * This function clears the selected pin interrupt status. + * + * @param base Base address of the PINT peripheral. + * @param pintr Pin interrupt. + * + * @retval None. + */ +void PINT_PinInterruptClrStatus(PINT_Type *base, pint_pin_int_t pintr) +{ + uint32_t pinIntMode = base->ISEL & (1UL << (uint32_t)pintr); + uint32_t pinIntStatus = base->IST & (1UL << (uint32_t)pintr); + + /* Edge sensitive and pin interrupt that is currently requesting an interrupt. */ + if ((pinIntMode == 0x0UL) && (pinIntStatus != 0x0UL)) + { + base->IST = (1UL << (uint32_t)pintr); + } +} + +/*! + * @brief Clear all pin interrupts status only when pins were triggered by edge-sensitive. + + * This function clears the status of all pin interrupts. + * + * @param base Base address of the PINT peripheral. + * + * @retval None. + */ +void PINT_PinInterruptClrStatusAll(PINT_Type *base) +{ + uint32_t pinIntMode = 0; + uint32_t pinIntStatus = 0; + uint32_t pinIntCount = 0; + uint32_t mask = 0; + uint32_t i; + + if (base == PINT) + { + pinIntCount = (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; + } + else + { +#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) + pinIntCount = (uint32_t)FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS; +#endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */ + } + + for (i = 0; i < pinIntCount; i++) + { + pinIntMode = base->ISEL & (1UL << i); + pinIntStatus = base->IST & (1UL << i); + + /* Edge sensitive and pin interrupt that is currently requesting an interrupt. */ + if ((pinIntMode == 0x0UL) && (pinIntStatus != 0x0UL)) + { + mask |= 1UL << i; + } + } + + base->IST = mask; +} + +/*! + * brief Enable callback. + + * This function enables the interrupt for the selected PINT peripheral. Although the pin(s) are monitored + * as soon as they are enabled, the callback function is not enabled until this function is called. + * + * param base Base address of the PINT peripheral. + * + * retval None. + */ +void PINT_EnableCallback(PINT_Type *base) +{ + uint32_t i; + + assert(base != NULL); + + if (base == PINT) + { + for (i = 0; i < (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; i++) + { + PINT_PinInterruptClrStatus(base, (pint_pin_int_t)i); + NVIC_ClearPendingIRQ(s_pintIRQ[i]); + (void)EnableIRQ(s_pintIRQ[i]); + } + } + else + { +#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) + for (i = 0; i < (uint32_t)FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS; i++) + { + PINT_PinInterruptClrStatus(base, (pint_pin_int_t)i); + NVIC_ClearPendingIRQ(s_pintIRQ[i + (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS]); + (void)EnableIRQ(s_pintIRQ[i + (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS]); + } +#endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */ + } +} + +/*! + * brief enable callback by pin index. + + * This function enables callback by pin index instead of enabling all pins. + * + * param base Base address of the peripheral. + * param pinIdx pin index. + * + * retval None. + */ +void PINT_EnableCallbackByIndex(PINT_Type *base, pint_pin_int_t pintIdx) +{ + assert(base != NULL); + + PINT_PinInterruptClrStatus(base, (pint_pin_int_t)pintIdx); + +#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) + /* Get the right security pint irq index in array */ + if (base == SECPINT) + { + pintIdx = + (pint_pin_int_t)(uint32_t)((uint32_t)pintIdx + (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS); + } +#endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */ + + NVIC_ClearPendingIRQ(s_pintIRQ[pintIdx]); + (void)EnableIRQ(s_pintIRQ[pintIdx]); +} + +/*! + * brief Disable callback. + + * This function disables the interrupt for the selected PINT peripheral. Although the pins are still + * being monitored but the callback function is not called. + * + * param base Base address of the peripheral. + * + * retval None. + */ +void PINT_DisableCallback(PINT_Type *base) +{ + uint32_t i; + + assert(base != NULL); + + if (base == PINT) + { + for (i = 0; i < (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; i++) + { + (void)DisableIRQ(s_pintIRQ[i]); + PINT_PinInterruptClrStatus(base, (pint_pin_int_t)i); + NVIC_ClearPendingIRQ(s_pintIRQ[i]); + } + } + else + { +#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) + for (i = 0; i < (uint32_t)FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS; i++) + { + (void)DisableIRQ(s_pintIRQ[i + (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS]); + PINT_PinInterruptClrStatus(base, (pint_pin_int_t)i); + NVIC_ClearPendingIRQ(s_pintIRQ[i + (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS]); + } +#endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */ + } +} + +/*! + * brief disable callback by pin index. + + * This function disables callback by pin index instead of disabling all pins. + * + * param base Base address of the peripheral. + * param pinIdx pin index. + * + * retval None. + */ +void PINT_DisableCallbackByIndex(PINT_Type *base, pint_pin_int_t pintIdx) +{ + assert(base != NULL); + + if (base == PINT) + { + (void)DisableIRQ(s_pintIRQ[pintIdx]); + PINT_PinInterruptClrStatus(base, (pint_pin_int_t)pintIdx); + NVIC_ClearPendingIRQ(s_pintIRQ[pintIdx]); + } + else + { +#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) + (void)DisableIRQ(s_pintIRQ[(uint32_t)pintIdx + (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS]); + PINT_PinInterruptClrStatus(base, (pint_pin_int_t)pintIdx); + NVIC_ClearPendingIRQ(s_pintIRQ[(uint32_t)pintIdx + (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS]); +#endif + } +} + +/*! + * brief Deinitialize PINT peripheral. + + * This function disables the PINT clock. + * + * param base Base address of the PINT peripheral. + * + * retval None. + */ +void PINT_Deinit(PINT_Type *base) +{ + uint32_t i; + + assert(base != NULL); + + /* Cleanup */ + PINT_DisableCallback(base); + if (base == PINT) + { + /* clear PINT callback array*/ + for (i = 0; i < (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; i++) + { + s_pintCallback[i] = NULL; + } + } + else + { +#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) + /* clear SECPINT callback array */ + for (i = 0; i < (uint32_t)FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS; i++) + { + s_secpintCallback[i] = NULL; + } +#endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */ + } + +#if defined(FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE) && (FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE == 1) + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable the clock. */ + CLOCK_DisableClock(kCLOCK_GpioInt); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) + /* Reset the module. */ + RESET_PeripheralReset(kGPIOINT_RST_N_SHIFT_RSTn); +#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ + +#elif defined(FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE) && (FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE == 0) + + if (base == PINT) + { +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable the clock. */ + CLOCK_DisableClock(kCLOCK_Gpio0); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) + /* Reset the module. */ + RESET_PeripheralReset(kGPIO0_RST_N_SHIFT_RSTn); +#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ + } + else + { +#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable the clock. */ + CLOCK_DisableClock(kCLOCK_Gpio_Sec); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) + /* Reset the module. */ + RESET_PeripheralReset(kGPIOSEC_RST_SHIFT_RSTn); +#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ +#endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */ + } + +#else + + if (base == PINT) + { +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable the clock. */ + CLOCK_DisableClock(kCLOCK_Pint); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) + /* Reset the module. */ + RESET_PeripheralReset(kPINT_RST_SHIFT_RSTn); +#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ + } + else + { + /* if need config SECURE PINT device,then enable secure pint interrupt clock */ +#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable the clock. */ + CLOCK_DisableClock(kCLOCK_Gpio_Sec_Int); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) + /* Reset the module. */ + RESET_PeripheralReset(kGPIOSECINT_RST_SHIFT_RSTn); +#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ +#endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */ + } +#endif /* FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE */ +} +#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) +/* IRQ handler functions overloading weak symbols in the startup */ +void SEC_GPIO_INT0_IRQ0_DriverIRQHandler(void); +void SEC_GPIO_INT0_IRQ0_DriverIRQHandler(void) +{ + uint32_t pmstatus = 0; + + /* Reset pattern match detection */ + pmstatus = PINT_PatternMatchResetDetectLogic(SECPINT); + /* Call user function */ + if (s_secpintCallback[kPINT_SecPinInt0] != NULL) + { + s_secpintCallback[kPINT_SecPinInt0](kPINT_SecPinInt0, pmstatus); + } + if ((SECPINT->ISEL & 0x1U) == 0x0U) + { + /* Edge sensitive: clear Pin interrupt after callback */ + PINT_PinInterruptClrStatus(SECPINT, kPINT_PinInt0); + } + SDK_ISR_EXIT_BARRIER; +} + +#if (FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS > 1U) +/* IRQ handler functions overloading weak symbols in the startup */ +void SEC_GPIO_INT0_IRQ1_DriverIRQHandler(void); +void SEC_GPIO_INT0_IRQ1_DriverIRQHandler(void) +{ + uint32_t pmstatus; + + /* Reset pattern match detection */ + pmstatus = PINT_PatternMatchResetDetectLogic(SECPINT); + /* Call user function */ + if (s_secpintCallback[kPINT_SecPinInt1] != NULL) + { + s_secpintCallback[kPINT_SecPinInt1](kPINT_SecPinInt1, pmstatus); + } + if ((SECPINT->ISEL & 0x1U) == 0x0U) + { + /* Edge sensitive: clear Pin interrupt after callback */ + PINT_PinInterruptClrStatus(SECPINT, kPINT_PinInt1); + } + SDK_ISR_EXIT_BARRIER; +} +#endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */ +#endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */ + +/* IRQ handler functions overloading weak symbols in the startup */ +void PIN_INT0_DriverIRQHandler(void); +void PIN_INT0_DriverIRQHandler(void) +{ + uint32_t pmstatus; + + /* Reset pattern match detection */ + pmstatus = PINT_PatternMatchResetDetectLogic(PINT); + /* Call user function */ + if (s_pintCallback[kPINT_PinInt0] != NULL) + { + s_pintCallback[kPINT_PinInt0](kPINT_PinInt0, pmstatus); + } + if ((PINT->ISEL & 0x1U) == 0x0U) + { + /* Edge sensitive: clear Pin interrupt after callback */ + PINT_PinInterruptClrStatus(PINT, kPINT_PinInt0); + } + SDK_ISR_EXIT_BARRIER; +} + +#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 1U) +void PIN_INT1_DriverIRQHandler(void); +void PIN_INT1_DriverIRQHandler(void) +{ + uint32_t pmstatus; + + /* Reset pattern match detection */ + pmstatus = PINT_PatternMatchResetDetectLogic(PINT); + /* Call user function */ + if (s_pintCallback[kPINT_PinInt1] != NULL) + { + s_pintCallback[kPINT_PinInt1](kPINT_PinInt1, pmstatus); + } + if ((PINT->ISEL & 0x2U) == 0x0U) + { + /* Edge sensitive: clear Pin interrupt after callback */ + PINT_PinInterruptClrStatus(PINT, kPINT_PinInt1); + } + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 2U) +void PIN_INT2_DriverIRQHandler(void); +void PIN_INT2_DriverIRQHandler(void) +{ + uint32_t pmstatus; + + /* Reset pattern match detection */ + pmstatus = PINT_PatternMatchResetDetectLogic(PINT); + /* Call user function */ + if (s_pintCallback[kPINT_PinInt2] != NULL) + { + s_pintCallback[kPINT_PinInt2](kPINT_PinInt2, pmstatus); + } + if ((PINT->ISEL & 0x4U) == 0x0U) + { + /* Edge sensitive: clear Pin interrupt after callback */ + PINT_PinInterruptClrStatus(PINT, kPINT_PinInt2); + } + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 3U) +void PIN_INT3_DriverIRQHandler(void); +void PIN_INT3_DriverIRQHandler(void) +{ + uint32_t pmstatus; + + /* Reset pattern match detection */ + pmstatus = PINT_PatternMatchResetDetectLogic(PINT); + /* Call user function */ + if (s_pintCallback[kPINT_PinInt3] != NULL) + { + s_pintCallback[kPINT_PinInt3](kPINT_PinInt3, pmstatus); + } + if ((PINT->ISEL & 0x8U) == 0x0U) + { + /* Edge sensitive: clear Pin interrupt after callback */ + PINT_PinInterruptClrStatus(PINT, kPINT_PinInt3); + } + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 4U) +void PIN_INT4_DriverIRQHandler(void); +void PIN_INT4_DriverIRQHandler(void) +{ + uint32_t pmstatus; + + /* Reset pattern match detection */ + pmstatus = PINT_PatternMatchResetDetectLogic(PINT); + /* Call user function */ + if (s_pintCallback[kPINT_PinInt4] != NULL) + { + s_pintCallback[kPINT_PinInt4](kPINT_PinInt4, pmstatus); + } + if ((PINT->ISEL & 0x10U) == 0x0U) + { + /* Edge sensitive: clear Pin interrupt after callback */ + PINT_PinInterruptClrStatus(PINT, kPINT_PinInt4); + } + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 5U) +#if defined(FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER) && FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER +void PIN_INT5_DAC1_IRQHandler(void); +void PIN_INT5_DAC1_IRQHandler(void) +#else +void PIN_INT5_DriverIRQHandler(void); +void PIN_INT5_DriverIRQHandler(void) +#endif /* FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER */ +{ + uint32_t pmstatus; + + /* Reset pattern match detection */ + pmstatus = PINT_PatternMatchResetDetectLogic(PINT); + /* Call user function */ + if (s_pintCallback[kPINT_PinInt5] != NULL) + { + s_pintCallback[kPINT_PinInt5](kPINT_PinInt5, pmstatus); + } + if ((PINT->ISEL & 0x20U) == 0x0U) + { + /* Edge sensitive: clear Pin interrupt after callback */ + PINT_PinInterruptClrStatus(PINT, kPINT_PinInt5); + } + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 6U) +#if defined(FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER) && FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER +void PIN_INT6_USART3_IRQHandler(void); +void PIN_INT6_USART3_IRQHandler(void) +#else +void PIN_INT6_DriverIRQHandler(void); +void PIN_INT6_DriverIRQHandler(void) +#endif /* FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER */ +{ + uint32_t pmstatus; + + /* Reset pattern match detection */ + pmstatus = PINT_PatternMatchResetDetectLogic(PINT); + /* Call user function */ + if (s_pintCallback[kPINT_PinInt6] != NULL) + { + s_pintCallback[kPINT_PinInt6](kPINT_PinInt6, pmstatus); + } + if ((PINT->ISEL & 0x40U) == 0x0U) + { + /* Edge sensitive: clear Pin interrupt after callback */ + PINT_PinInterruptClrStatus(PINT, kPINT_PinInt6); + } + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 7U) +#if defined(FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER) && FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER +void PIN_INT7_USART4_IRQHandler(void); +void PIN_INT7_USART4_IRQHandler(void) +#else +void PIN_INT7_DriverIRQHandler(void); +void PIN_INT7_DriverIRQHandler(void) +#endif /* FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER */ +{ + uint32_t pmstatus; + + /* Reset pattern match detection */ + pmstatus = PINT_PatternMatchResetDetectLogic(PINT); + /* Call user function */ + if (s_pintCallback[kPINT_PinInt7] != NULL) + { + s_pintCallback[kPINT_PinInt7](kPINT_PinInt7, pmstatus); + } + if ((PINT->ISEL & 0x80U) == 0x0U) + { + /* Edge sensitive: clear Pin interrupt after callback */ + PINT_PinInterruptClrStatus(PINT, kPINT_PinInt7); + } + SDK_ISR_EXIT_BARRIER; +} +#endif diff --git a/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_pint.h b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_pint.h new file mode 100644 index 0000000000..85be865571 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_pint.h @@ -0,0 +1,581 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_PINT_H_ +#define _FSL_PINT_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup pint_driver + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +#define FSL_PINT_DRIVER_VERSION (MAKE_VERSION(2, 1, 9)) /*!< Version 2.1.9 */ +/*@}*/ + +/* Number of interrupt line supported by PINT */ +#define PINT_PIN_INT_COUNT 8U + +/* Number of interrupt line supported by SECURE PINT */ +#define SEC_PINT_PIN_INT_COUNT 2U + +/* Number of input sources supported by PINT */ +#define PINT_INPUT_COUNT 8U + +/* PININT Bit slice source register bits */ +#define PININT_BITSLICE_SRC_START 8U +#define PININT_BITSLICE_SRC_MASK 7U + +/* PININT Bit slice configuration register bits */ +#define PININT_BITSLICE_CFG_START 8U +#define PININT_BITSLICE_CFG_MASK 7U +#define PININT_BITSLICE_ENDP_MASK 7U + +#define PINT_PIN_INT_LEVEL 0x10U +#define PINT_PIN_INT_EDGE 0x00U +#define PINT_PIN_INT_FALL_OR_HIGH_LEVEL 0x02U +#define PINT_PIN_INT_RISE 0x01U +#define PINT_PIN_RISE_EDGE (PINT_PIN_INT_EDGE | PINT_PIN_INT_RISE) +#define PINT_PIN_FALL_EDGE (PINT_PIN_INT_EDGE | PINT_PIN_INT_FALL_OR_HIGH_LEVEL) +#define PINT_PIN_BOTH_EDGE (PINT_PIN_INT_EDGE | PINT_PIN_INT_RISE | PINT_PIN_INT_FALL_OR_HIGH_LEVEL) +#define PINT_PIN_LOW_LEVEL (PINT_PIN_INT_LEVEL) +#define PINT_PIN_HIGH_LEVEL (PINT_PIN_INT_LEVEL | PINT_PIN_INT_FALL_OR_HIGH_LEVEL) + +/*! @brief PINT Pin Interrupt enable type */ +typedef enum _pint_pin_enable +{ + kPINT_PinIntEnableNone = 0U, /*!< Do not generate Pin Interrupt */ + kPINT_PinIntEnableRiseEdge = PINT_PIN_RISE_EDGE, /*!< Generate Pin Interrupt on rising edge */ + kPINT_PinIntEnableFallEdge = PINT_PIN_FALL_EDGE, /*!< Generate Pin Interrupt on falling edge */ + kPINT_PinIntEnableBothEdges = PINT_PIN_BOTH_EDGE, /*!< Generate Pin Interrupt on both edges */ + kPINT_PinIntEnableLowLevel = PINT_PIN_LOW_LEVEL, /*!< Generate Pin Interrupt on low level */ + kPINT_PinIntEnableHighLevel = PINT_PIN_HIGH_LEVEL /*!< Generate Pin Interrupt on high level */ +} pint_pin_enable_t; + +/*! @brief PINT Pin Interrupt type */ +typedef enum _pint_int +{ + kPINT_PinInt0 = 0U, /*!< Pin Interrupt 0 */ +#if defined(FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 1U) + kPINT_PinInt1 = 1U, /*!< Pin Interrupt 1 */ +#endif +#if defined(FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 2U) + kPINT_PinInt2 = 2U, /*!< Pin Interrupt 2 */ +#endif +#if defined(FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 3U) + kPINT_PinInt3 = 3U, /*!< Pin Interrupt 3 */ +#endif +#if defined(FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 4U) + kPINT_PinInt4 = 4U, /*!< Pin Interrupt 4 */ +#endif +#if defined(FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 5U) + kPINT_PinInt5 = 5U, /*!< Pin Interrupt 5 */ +#endif +#if defined(FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 6U) + kPINT_PinInt6 = 6U, /*!< Pin Interrupt 6 */ +#endif +#if defined(FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 7U) + kPINT_PinInt7 = 7U, /*!< Pin Interrupt 7 */ +#endif +#if defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS > 0U) + kPINT_SecPinInt0 = 0U, /*!< Secure Pin Interrupt 0 */ +#endif +#if defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS > 1U) + kPINT_SecPinInt1 = 1U, /*!< Secure Pin Interrupt 1 */ +#endif +} pint_pin_int_t; + +/*! @brief PINT Pattern Match bit slice input source type */ +typedef enum _pint_pmatch_input_src +{ + kPINT_PatternMatchInp0Src = 0U, /*!< Input source 0 */ + kPINT_PatternMatchInp1Src = 1U, /*!< Input source 1 */ + kPINT_PatternMatchInp2Src = 2U, /*!< Input source 2 */ + kPINT_PatternMatchInp3Src = 3U, /*!< Input source 3 */ + kPINT_PatternMatchInp4Src = 4U, /*!< Input source 4 */ + kPINT_PatternMatchInp5Src = 5U, /*!< Input source 5 */ + kPINT_PatternMatchInp6Src = 6U, /*!< Input source 6 */ + kPINT_PatternMatchInp7Src = 7U, /*!< Input source 7 */ + kPINT_SecPatternMatchInp0Src = 0U, /*!< Input source 0 */ + kPINT_SecPatternMatchInp1Src = 1U, /*!< Input source 1 */ +} pint_pmatch_input_src_t; + +/*! @brief PINT Pattern Match bit slice type */ +typedef enum _pint_pmatch_bslice +{ + kPINT_PatternMatchBSlice0 = 0U, /*!< Bit slice 0 */ +#if defined(FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 1U) + kPINT_PatternMatchBSlice1 = 1U, /*!< Bit slice 1 */ +#endif +#if defined(FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 2U) + kPINT_PatternMatchBSlice2 = 2U, /*!< Bit slice 2 */ +#endif +#if defined(FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 3U) + kPINT_PatternMatchBSlice3 = 3U, /*!< Bit slice 3 */ +#endif +#if defined(FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 4U) + kPINT_PatternMatchBSlice4 = 4U, /*!< Bit slice 4 */ +#endif +#if defined(FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 5U) + kPINT_PatternMatchBSlice5 = 5U, /*!< Bit slice 5 */ +#endif +#if defined(FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 6U) + kPINT_PatternMatchBSlice6 = 6U, /*!< Bit slice 6 */ +#endif +#if defined(FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 7U) + kPINT_PatternMatchBSlice7 = 7U, /*!< Bit slice 7 */ +#endif +#if defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS > 0U) + kPINT_SecPatternMatchBSlice0 = 0U, /*!< Bit slice 0 */ +#endif +#if defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS > 1U) + kPINT_SecPatternMatchBSlice1 = 1U, /*!< Bit slice 1 */ +#endif +} pint_pmatch_bslice_t; + +/*! @brief PINT Pattern Match configuration type */ +typedef enum _pint_pmatch_bslice_cfg +{ + kPINT_PatternMatchAlways = 0U, /*!< Always Contributes to product term match */ + kPINT_PatternMatchStickyRise = 1U, /*!< Sticky Rising edge */ + kPINT_PatternMatchStickyFall = 2U, /*!< Sticky Falling edge */ + kPINT_PatternMatchStickyBothEdges = 3U, /*!< Sticky Rising or Falling edge */ + kPINT_PatternMatchHigh = 4U, /*!< High level */ + kPINT_PatternMatchLow = 5U, /*!< Low level */ + kPINT_PatternMatchNever = 6U, /*!< Never contributes to product term match */ + kPINT_PatternMatchBothEdges = 7U, /*!< Either rising or falling edge */ +} pint_pmatch_bslice_cfg_t; + +/*! @brief PINT Callback function. */ +typedef void (*pint_cb_t)(pint_pin_int_t pintr, uint32_t pmatch_status); + +typedef struct _pint_pmatch_cfg +{ + pint_pmatch_input_src_t bs_src; + pint_pmatch_bslice_cfg_t bs_cfg; + bool end_point; + pint_cb_t callback; +} pint_pmatch_cfg_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Initialize PINT peripheral. + + * This function initializes the PINT peripheral and enables the clock. + * + * @param base Base address of the PINT peripheral. + * + * @retval None. + */ +void PINT_Init(PINT_Type *base); + +/*! + * @brief Configure PINT peripheral pin interrupt. + + * This function configures a given pin interrupt. + * + * @param base Base address of the PINT peripheral. + * @param intr Pin interrupt. + * @param enable Selects detection logic. + * @param callback Callback. + * + * @retval None. + */ +void PINT_PinInterruptConfig(PINT_Type *base, pint_pin_int_t intr, pint_pin_enable_t enable, pint_cb_t callback); + +/*! + * @brief Get PINT peripheral pin interrupt configuration. + + * This function returns the configuration of a given pin interrupt. + * + * @param base Base address of the PINT peripheral. + * @param pintr Pin interrupt. + * @param enable Pointer to store the detection logic. + * @param callback Callback. + * + * @retval None. + */ +void PINT_PinInterruptGetConfig(PINT_Type *base, pint_pin_int_t pintr, pint_pin_enable_t *enable, pint_cb_t *callback); + +/*! + * @brief Clear Selected pin interrupt status only when the pin was triggered by edge-sensitive. + + * This function clears the selected pin interrupt status. + * + * @param base Base address of the PINT peripheral. + * @param pintr Pin interrupt. + * + * @retval None. + */ +void PINT_PinInterruptClrStatus(PINT_Type *base, pint_pin_int_t pintr); + +/*! + * @brief Get Selected pin interrupt status. + + * This function returns the selected pin interrupt status. + * + * @param base Base address of the PINT peripheral. + * @param pintr Pin interrupt. + * + * @retval status = 0 No pin interrupt request. = 1 Selected Pin interrupt request active. + */ +static inline uint32_t PINT_PinInterruptGetStatus(PINT_Type *base, pint_pin_int_t pintr) +{ + return ((base->IST & (1UL << (uint32_t)pintr)) != 0U ? 1U : 0U); +} + +/*! + * @brief Clear all pin interrupts status only when pins were triggered by edge-sensitive. + + * This function clears the status of all pin interrupts. + * + * @param base Base address of the PINT peripheral. + * + * @retval None. + */ +void PINT_PinInterruptClrStatusAll(PINT_Type *base); + +/*! + * @brief Get all pin interrupts status. + + * This function returns the status of all pin interrupts. + * + * @param base Base address of the PINT peripheral. + * + * @retval status Each bit position indicates the status of corresponding pin interrupt. + * = 0 No pin interrupt request. = 1 Pin interrupt request active. + */ +static inline uint32_t PINT_PinInterruptGetStatusAll(PINT_Type *base) +{ + return (base->IST); +} + +/*! + * @brief Clear Selected pin interrupt fall flag. + + * This function clears the selected pin interrupt fall flag. + * + * @param base Base address of the PINT peripheral. + * @param pintr Pin interrupt. + * + * @retval None. + */ +static inline void PINT_PinInterruptClrFallFlag(PINT_Type *base, pint_pin_int_t pintr) +{ + base->FALL = (1UL << (uint32_t)pintr); +} + +/*! + * @brief Get selected pin interrupt fall flag. + + * This function returns the selected pin interrupt fall flag. + * + * @param base Base address of the PINT peripheral. + * @param pintr Pin interrupt. + * + * @retval flag = 0 Falling edge has not been detected. = 1 Falling edge has been detected. + */ +static inline uint32_t PINT_PinInterruptGetFallFlag(PINT_Type *base, pint_pin_int_t pintr) +{ + return ((base->FALL & (1UL << (uint32_t)pintr)) != 0U ? 1U : 0U); +} + +/*! + * @brief Clear all pin interrupt fall flags. + + * This function clears the fall flag for all pin interrupts. + * + * @param base Base address of the PINT peripheral. + * + * @retval None. + */ +static inline void PINT_PinInterruptClrFallFlagAll(PINT_Type *base) +{ + base->FALL = PINT_FALL_FDET_MASK; +} + +/*! + * @brief Get all pin interrupt fall flags. + + * This function returns the fall flag of all pin interrupts. + * + * @param base Base address of the PINT peripheral. + * + * @retval flags Each bit position indicates the falling edge detection of the corresponding pin interrupt. + * 0 Falling edge has not been detected. = 1 Falling edge has been detected. + */ +static inline uint32_t PINT_PinInterruptGetFallFlagAll(PINT_Type *base) +{ + return (base->FALL); +} + +/*! + * @brief Clear Selected pin interrupt rise flag. + + * This function clears the selected pin interrupt rise flag. + * + * @param base Base address of the PINT peripheral. + * @param pintr Pin interrupt. + * + * @retval None. + */ +static inline void PINT_PinInterruptClrRiseFlag(PINT_Type *base, pint_pin_int_t pintr) +{ + base->RISE = (1UL << (uint32_t)pintr); +} + +/*! + * @brief Get selected pin interrupt rise flag. + + * This function returns the selected pin interrupt rise flag. + * + * @param base Base address of the PINT peripheral. + * @param pintr Pin interrupt. + * + * @retval flag = 0 Rising edge has not been detected. = 1 Rising edge has been detected. + */ +static inline uint32_t PINT_PinInterruptGetRiseFlag(PINT_Type *base, pint_pin_int_t pintr) +{ + return ((base->RISE & (1UL << (uint32_t)pintr)) != 0U ? 1U : 0U); +} + +/*! + * @brief Clear all pin interrupt rise flags. + + * This function clears the rise flag for all pin interrupts. + * + * @param base Base address of the PINT peripheral. + * + * @retval None. + */ +static inline void PINT_PinInterruptClrRiseFlagAll(PINT_Type *base) +{ + base->RISE = PINT_RISE_RDET_MASK; +} + +/*! + * @brief Get all pin interrupt rise flags. + + * This function returns the rise flag of all pin interrupts. + * + * @param base Base address of the PINT peripheral. + * + * @retval flags Each bit position indicates the rising edge detection of the corresponding pin interrupt. + * 0 Rising edge has not been detected. = 1 Rising edge has been detected. + */ +static inline uint32_t PINT_PinInterruptGetRiseFlagAll(PINT_Type *base) +{ + return (base->RISE); +} + +/*! + * @brief Configure PINT pattern match. + + * This function configures a given pattern match bit slice. + * + * @param base Base address of the PINT peripheral. + * @param bslice Pattern match bit slice number. + * @param cfg Pointer to bit slice configuration. + * + * @retval None. + */ +void PINT_PatternMatchConfig(PINT_Type *base, pint_pmatch_bslice_t bslice, pint_pmatch_cfg_t *cfg); + +/*! + * @brief Get PINT pattern match configuration. + + * This function returns the configuration of a given pattern match bit slice. + * + * @param base Base address of the PINT peripheral. + * @param bslice Pattern match bit slice number. + * @param cfg Pointer to bit slice configuration. + * + * @retval None. + */ +void PINT_PatternMatchGetConfig(PINT_Type *base, pint_pmatch_bslice_t bslice, pint_pmatch_cfg_t *cfg); + +/*! + * @brief Get pattern match bit slice status. + + * This function returns the status of selected bit slice. + * + * @param base Base address of the PINT peripheral. + * @param bslice Pattern match bit slice number. + * + * @retval status = 0 Match has not been detected. = 1 Match has been detected. + */ +static inline uint32_t PINT_PatternMatchGetStatus(PINT_Type *base, pint_pmatch_bslice_t bslice) +{ + return ((base->PMCTRL >> PINT_PMCTRL_PMAT_SHIFT) & (1UL << (uint32_t)bslice)) >> (uint32_t)bslice; +} + +/*! + * @brief Get status of all pattern match bit slices. + + * This function returns the status of all bit slices. + * + * @param base Base address of the PINT peripheral. + * + * @retval status Each bit position indicates the match status of corresponding bit slice. + * = 0 Match has not been detected. = 1 Match has been detected. + */ +static inline uint32_t PINT_PatternMatchGetStatusAll(PINT_Type *base) +{ + return base->PMCTRL >> PINT_PMCTRL_PMAT_SHIFT; +} + +/*! + * @brief Reset pattern match detection logic. + + * This function resets the pattern match detection logic if any of the product term is matching. + * + * @param base Base address of the PINT peripheral. + * + * @retval pmstatus Each bit position indicates the match status of corresponding bit slice. + * = 0 Match was detected. = 1 Match was not detected. + */ +uint32_t PINT_PatternMatchResetDetectLogic(PINT_Type *base); + +/*! + * @brief Enable pattern match function. + + * This function enables the pattern match function. + * + * @param base Base address of the PINT peripheral. + * + * @retval None. + */ +static inline void PINT_PatternMatchEnable(PINT_Type *base) +{ + base->PMCTRL = (base->PMCTRL & PINT_PMCTRL_ENA_RXEV_MASK) | PINT_PMCTRL_SEL_PMATCH_MASK; +} + +/*! + * @brief Disable pattern match function. + + * This function disables the pattern match function. + * + * @param base Base address of the PINT peripheral. + * + * @retval None. + */ +static inline void PINT_PatternMatchDisable(PINT_Type *base) +{ + base->PMCTRL = (base->PMCTRL & PINT_PMCTRL_ENA_RXEV_MASK) & ~PINT_PMCTRL_SEL_PMATCH_MASK; +} + +/*! + * @brief Enable RXEV output. + + * This function enables the pattern match RXEV output. + * + * @param base Base address of the PINT peripheral. + * + * @retval None. + */ +static inline void PINT_PatternMatchEnableRXEV(PINT_Type *base) +{ + base->PMCTRL = (base->PMCTRL & PINT_PMCTRL_SEL_PMATCH_MASK) | PINT_PMCTRL_ENA_RXEV_MASK; +} + +/*! + * @brief Disable RXEV output. + + * This function disables the pattern match RXEV output. + * + * @param base Base address of the PINT peripheral. + * + * @retval None. + */ +static inline void PINT_PatternMatchDisableRXEV(PINT_Type *base) +{ + base->PMCTRL = (base->PMCTRL & PINT_PMCTRL_SEL_PMATCH_MASK) & ~PINT_PMCTRL_ENA_RXEV_MASK; +} + +/*! + * @brief Enable callback. + + * This function enables the interrupt for the selected PINT peripheral. Although the pin(s) are monitored + * as soon as they are enabled, the callback function is not enabled until this function is called. + * + * @param base Base address of the PINT peripheral. + * + * @retval None. + */ +void PINT_EnableCallback(PINT_Type *base); + +/*! + * @brief Disable callback. + + * This function disables the interrupt for the selected PINT peripheral. Although the pins are still + * being monitored but the callback function is not called. + * + * @param base Base address of the peripheral. + * + * @retval None. + */ +void PINT_DisableCallback(PINT_Type *base); + +/*! + * @brief Deinitialize PINT peripheral. + + * This function disables the PINT clock. + * + * @param base Base address of the PINT peripheral. + * + * @retval None. + */ +void PINT_Deinit(PINT_Type *base); + +/*! + * @brief enable callback by pin index. + + * This function enables callback by pin index instead of enabling all pins. + * + * @param base Base address of the peripheral. + * @param pintIdx pin index. + * + * @retval None. + */ +void PINT_EnableCallbackByIndex(PINT_Type *base, pint_pin_int_t pintIdx); + +/*! + * @brief disable callback by pin index. + + * This function disables callback by pin index instead of disabling all pins. + * + * @param base Base address of the peripheral. + * @param pintIdx pin index. + * + * @retval None. + */ +void PINT_DisableCallbackByIndex(PINT_Type *base, pint_pin_int_t pintIdx); + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* _FSL_PINT_H_ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_plu.c b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_plu.c new file mode 100644 index 0000000000..b50f472675 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_plu.c @@ -0,0 +1,163 @@ +/* + * Copyright 2018-2019 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_plu.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.plu" +#endif + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/*! + * @brief Gets the instance from the base address + * + * @param base PLU peripheral base address + * + * @return The PLU instance + */ +static uint32_t PLU_GetInstance(PLU_Type *base); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Pointers to PLU bases for each instance. */ +static PLU_Type *const s_pluBases[] = PLU_BASE_PTRS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Pointers to PLU clocks for each instance. */ +static const clock_ip_name_t s_pluClocks[] = PLU_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) +/*! @brief Pointers to PLU resets for each instance. */ +static const reset_ip_name_t s_lpuResets[] = PLU_RSTS_N; +#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ + +/******************************************************************************* + * Code + ******************************************************************************/ +static uint32_t PLU_GetInstance(PLU_Type *base) +{ + uint32_t instance; + uint32_t pluArrayCount = (sizeof(s_pluBases) / sizeof(s_pluBases[0])); + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < pluArrayCount; instance++) + { + if (s_pluBases[instance] == base) + { + break; + } + } + + assert(instance < pluArrayCount); + + return instance; +} + +/*! + * brief Ungates the PLU clock and reset the module. + * + * note This API should be called at the beginning of the application using the PLU driver. + * + * param base PLU peripheral base address + */ +void PLU_Init(PLU_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable the PLU peripheral clock */ + CLOCK_EnableClock(s_pluClocks[PLU_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) + /* Reset the module. */ + RESET_PeripheralReset(s_lpuResets[PLU_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ +} + +/*! + * brief Gate the PLU clock + * + * param base PLU peripheral base address + */ +void PLU_Deinit(PLU_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Gate the module clock */ + CLOCK_DisableClock((s_pluClocks[PLU_GetInstance(base)])); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +#if defined(FSL_FEATURE_PLU_HAS_WAKEINT_CTRL_REG) && FSL_FEATURE_PLU_HAS_WAKEINT_CTRL_REG +/*! + * @brief Gets an available pre-defined settings for wakeup/interrupt control. + * + * This function initializes the initial configuration structure with an available settings. The default values are: + * @code + * config->filterMode = kPLU_WAKEINT_FILTER_MODE_BYPASS; + * config->clockSource = kPLU_WAKEINT_FILTER_CLK_SRC_1MHZ_LPOSC; + * @endcode + * @param config Pointer to configuration structure. + */ +void PLU_GetDefaultWakeIntConfig(plu_wakeint_config_t *config) +{ + /* Initializes the configure structure to zero. */ + (void)memset(config, 0, sizeof(*config)); + + config->filterMode = kPLU_WAKEINT_FILTER_MODE_BYPASS; + config->clockSource = kPLU_WAKEINT_FILTER_CLK_SRC_1MHZ_LPOSC; +} + +/*! + * @brief Enable PLU outputs wakeup/interrupt request. + * + * This function enables Any of the eight selected PLU outputs to contribute to an asynchronous wake-up or an interrupt + * request. + * + * Note: If a PLU_CLKIN is provided, the raw wake-up/interrupt request will be set on the rising-edge of the PLU_CLKIN + * whenever the raw request signal is high. This registered signal will be glitch-free and just use the default wakeint + * config by PLU_GetDefaultWakeIntConfig(). If not, have to specify the filter mode and clock source to eliminate the + * glitches caused by long and widely disparate delays through the network of LUTs making up the PLU. This way may + * increase power consumption in low-power operating modes and inject delay before the wake-up/interrupt request is + * generated. + * + * @param base PLU peripheral base address. + * @param interruptMask PLU interrupt mask (see @ref _plu_interrupt_mask enumeration). + * @param config Pointer to configuration structure (see @ref plu_wakeint_config_t typedef enumeration) + */ +void PLU_EnableWakeIntRequest(PLU_Type *base, uint32_t interruptMask, const plu_wakeint_config_t *config) +{ + uint32_t tmp32 = 0U; + + tmp32 = PLU_WAKEINT_CTRL_FILTER_MODE(config->filterMode) | PLU_WAKEINT_CTRL_FILTER_CLKSEL(config->clockSource) | + PLU_WAKEINT_CTRL_MASK(interruptMask); + + base->WAKEINT_CTRL = tmp32; +} + +/*! + * @brief Clear the latched interrupt + * + * This function clears the wake-up/interrupt request flag latched by PLU_LatchInterrupt() + * + * Note: It is not necessary for the PLU bus clock to be enabled in order to write-to or read-back this bit. + * + * @param base PLU peripheral base address. + */ +void PLU_ClearLatchedInterrupt(PLU_Type *base) +{ + base->WAKEINT_CTRL |= PLU_WAKEINT_CTRL_INTR_CLEAR_MASK; + /* It will take a delay of up to 1.5 PLU_CLKIN clock cycles before this write-to-clear takes effect. */ + while (PLU_WAKEINT_CTRL_INTR_CLEAR_MASK == (base->WAKEINT_CTRL & PLU_WAKEINT_CTRL_INTR_CLEAR_MASK)) + { + } +} +#endif /* FSL_FEATURE_PLU_HAS_WAKEINT_CTRL_REG */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_plu.h b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_plu.h new file mode 100644 index 0000000000..0c94d49091 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_plu.h @@ -0,0 +1,374 @@ +/* + * Copyright 2018-2019 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_PLU_H_ +#define _FSL_PLU_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup plu + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +#define FSL_PLU_DRIVER_VERSION (MAKE_VERSION(2, 2, 1)) /*!< Version 2.2.1 */ + /*@}*/ + +/*! @brief Index of LUT */ +typedef enum _plu_lut_index +{ + kPLU_LUT_0 = 0U, /*!< 5-input Look-up Table 0 */ + kPLU_LUT_1 = 1U, /*!< 5-input Look-up Table 1 */ + kPLU_LUT_2 = 2U, /*!< 5-input Look-up Table 2 */ + kPLU_LUT_3 = 3U, /*!< 5-input Look-up Table 3 */ + kPLU_LUT_4 = 4U, /*!< 5-input Look-up Table 4 */ + kPLU_LUT_5 = 5U, /*!< 5-input Look-up Table 5 */ + kPLU_LUT_6 = 6U, /*!< 5-input Look-up Table 6 */ + kPLU_LUT_7 = 7U, /*!< 5-input Look-up Table 7 */ + kPLU_LUT_8 = 8U, /*!< 5-input Look-up Table 8 */ + kPLU_LUT_9 = 9U, /*!< 5-input Look-up Table 9 */ + kPLU_LUT_10 = 10U, /*!< 5-input Look-up Table 10 */ + kPLU_LUT_11 = 11U, /*!< 5-input Look-up Table 11 */ + kPLU_LUT_12 = 12U, /*!< 5-input Look-up Table 12 */ + kPLU_LUT_13 = 13U, /*!< 5-input Look-up Table 13 */ + kPLU_LUT_14 = 14U, /*!< 5-input Look-up Table 14 */ + kPLU_LUT_15 = 15U, /*!< 5-input Look-up Table 15 */ + kPLU_LUT_16 = 16U, /*!< 5-input Look-up Table 16 */ + kPLU_LUT_17 = 17U, /*!< 5-input Look-up Table 17 */ + kPLU_LUT_18 = 18U, /*!< 5-input Look-up Table 18 */ + kPLU_LUT_19 = 19U, /*!< 5-input Look-up Table 19 */ + kPLU_LUT_20 = 20U, /*!< 5-input Look-up Table 20 */ + kPLU_LUT_21 = 21U, /*!< 5-input Look-up Table 21 */ + kPLU_LUT_22 = 22U, /*!< 5-input Look-up Table 22 */ + kPLU_LUT_23 = 23U, /*!< 5-input Look-up Table 23 */ + kPLU_LUT_24 = 24U, /*!< 5-input Look-up Table 24 */ + kPLU_LUT_25 = 25U /*!< 5-input Look-up Table 25 */ +} plu_lut_index_t; + +/*! @brief Inputs of LUT. 5 input present for each LUT. */ +typedef enum _plu_lut_in_index +{ + kPLU_LUT_IN_0 = 0U, /*!< LUT input 0 */ + kPLU_LUT_IN_1 = 1U, /*!< LUT input 1 */ + kPLU_LUT_IN_2 = 2U, /*!< LUT input 2 */ + kPLU_LUT_IN_3 = 3U, /*!< LUT input 3 */ + kPLU_LUT_IN_4 = 4U /*!< LUT input 4 */ +} plu_lut_in_index_t; + +/*! @brief Available sources of LUT input */ +typedef enum _plu_lut_input_source +{ + kPLU_LUT_IN_SRC_PLU_IN_0 = 0U, /*!< Select PLU input 0 to be connected to LUTn Input x */ + kPLU_LUT_IN_SRC_PLU_IN_1 = 1U, /*!< Select PLU input 1 to be connected to LUTn Input x */ + kPLU_LUT_IN_SRC_PLU_IN_2 = 2U, /*!< Select PLU input 2 to be connected to LUTn Input x */ + kPLU_LUT_IN_SRC_PLU_IN_3 = 3U, /*!< Select PLU input 3 to be connected to LUTn Input x */ + kPLU_LUT_IN_SRC_PLU_IN_4 = 4U, /*!< Select PLU input 4 to be connected to LUTn Input x */ + kPLU_LUT_IN_SRC_PLU_IN_5 = 5U, /*!< Select PLU input 5 to be connected to LUTn Input x */ + kPLU_LUT_IN_SRC_LUT_OUT_0 = 6U, /*!< Select LUT output 0 to be connected to LUTn Input x */ + kPLU_LUT_IN_SRC_LUT_OUT_1 = 7U, /*!< Select LUT output 1 to be connected to LUTn Input x */ + kPLU_LUT_IN_SRC_LUT_OUT_2 = 8U, /*!< Select LUT output 2 to be connected to LUTn Input x */ + kPLU_LUT_IN_SRC_LUT_OUT_3 = 9U, /*!< Select LUT output 3 to be connected to LUTn Input x */ + kPLU_LUT_IN_SRC_LUT_OUT_4 = 10U, /*!< Select LUT output 4 to be connected to LUTn Input x */ + kPLU_LUT_IN_SRC_LUT_OUT_5 = 11U, /*!< Select LUT output 5 to be connected to LUTn Input x */ + kPLU_LUT_IN_SRC_LUT_OUT_6 = 12U, /*!< Select LUT output 6 to be connected to LUTn Input x */ + kPLU_LUT_IN_SRC_LUT_OUT_7 = 13U, /*!< Select LUT output 7 to be connected to LUTn Input x */ + kPLU_LUT_IN_SRC_LUT_OUT_8 = 14U, /*!< Select LUT output 8 to be connected to LUTn Input x */ + kPLU_LUT_IN_SRC_LUT_OUT_9 = 15U, /*!< Select LUT output 9 to be connected to LUTn Input x */ + kPLU_LUT_IN_SRC_LUT_OUT_10 = 16U, /*!< Select LUT output 10 to be connected to LUTn Input x */ + kPLU_LUT_IN_SRC_LUT_OUT_11 = 17U, /*!< Select LUT output 11 to be connected to LUTn Input x */ + kPLU_LUT_IN_SRC_LUT_OUT_12 = 18U, /*!< Select LUT output 12 to be connected to LUTn Input x */ + kPLU_LUT_IN_SRC_LUT_OUT_13 = 19U, /*!< Select LUT output 13 to be connected to LUTn Input x */ + kPLU_LUT_IN_SRC_LUT_OUT_14 = 20U, /*!< Select LUT output 14 to be connected to LUTn Input x */ + kPLU_LUT_IN_SRC_LUT_OUT_15 = 21U, /*!< Select LUT output 15 to be connected to LUTn Input x */ + kPLU_LUT_IN_SRC_LUT_OUT_16 = 22U, /*!< Select LUT output 16 to be connected to LUTn Input x */ + kPLU_LUT_IN_SRC_LUT_OUT_17 = 23U, /*!< Select LUT output 17 to be connected to LUTn Input x */ + kPLU_LUT_IN_SRC_LUT_OUT_18 = 24U, /*!< Select LUT output 18 to be connected to LUTn Input x */ + kPLU_LUT_IN_SRC_LUT_OUT_19 = 25U, /*!< Select LUT output 19 to be connected to LUTn Input x */ + kPLU_LUT_IN_SRC_LUT_OUT_20 = 26U, /*!< Select LUT output 20 to be connected to LUTn Input x */ + kPLU_LUT_IN_SRC_LUT_OUT_21 = 27U, /*!< Select LUT output 21 to be connected to LUTn Input x */ + kPLU_LUT_IN_SRC_LUT_OUT_22 = 28U, /*!< Select LUT output 22 to be connected to LUTn Input x */ + kPLU_LUT_IN_SRC_LUT_OUT_23 = 29U, /*!< Select LUT output 23 to be connected to LUTn Input x */ + kPLU_LUT_IN_SRC_LUT_OUT_24 = 30U, /*!< Select LUT output 24 to be connected to LUTn Input x */ + kPLU_LUT_IN_SRC_LUT_OUT_25 = 31U, /*!< Select LUT output 25 to be connected to LUTn Input x */ + kPLU_LUT_IN_SRC_FLIPFLOP_0 = 32U, /*!< Select Flip-Flops state 0 to be connected to LUTn Input x */ + kPLU_LUT_IN_SRC_FLIPFLOP_1 = 33U, /*!< Select Flip-Flops state 1 to be connected to LUTn Input x */ + kPLU_LUT_IN_SRC_FLIPFLOP_2 = 34U, /*!< Select Flip-Flops state 2 to be connected to LUTn Input x */ + kPLU_LUT_IN_SRC_FLIPFLOP_3 = 35U /*!< Select Flip-Flops state 3 to be connected to LUTn Input x */ +} plu_lut_input_source_t; + +/*! @brief PLU output multiplexer registers */ +typedef enum _plu_output_index +{ + kPLU_OUTPUT_0 = 0U, /*!< PLU OUTPUT 0 */ + kPLU_OUTPUT_1 = 1U, /*!< PLU OUTPUT 1 */ + kPLU_OUTPUT_2 = 2U, /*!< PLU OUTPUT 2 */ + kPLU_OUTPUT_3 = 3U, /*!< PLU OUTPUT 3 */ + kPLU_OUTPUT_4 = 4U, /*!< PLU OUTPUT 4 */ + kPLU_OUTPUT_5 = 5U, /*!< PLU OUTPUT 5 */ + kPLU_OUTPUT_6 = 6U, /*!< PLU OUTPUT 6 */ + kPLU_OUTPUT_7 = 7U /*!< PLU OUTPUT 7 */ +} plu_output_index_t; + +/*! @brief Available sources of PLU output */ +typedef enum _plu_output_source +{ + kPLU_OUT_SRC_LUT_0 = 0U, /*!< Select LUT0 output to be connected to PLU output */ + kPLU_OUT_SRC_LUT_1 = 1U, /*!< Select LUT1 output to be connected to PLU output */ + kPLU_OUT_SRC_LUT_2 = 2U, /*!< Select LUT2 output to be connected to PLU output */ + kPLU_OUT_SRC_LUT_3 = 3U, /*!< Select LUT3 output to be connected to PLU output */ + kPLU_OUT_SRC_LUT_4 = 4U, /*!< Select LUT4 output to be connected to PLU output */ + kPLU_OUT_SRC_LUT_5 = 5U, /*!< Select LUT5 output to be connected to PLU output */ + kPLU_OUT_SRC_LUT_6 = 6U, /*!< Select LUT6 output to be connected to PLU output */ + kPLU_OUT_SRC_LUT_7 = 7U, /*!< Select LUT7 output to be connected to PLU output */ + kPLU_OUT_SRC_LUT_8 = 8U, /*!< Select LUT8 output to be connected to PLU output */ + kPLU_OUT_SRC_LUT_9 = 9U, /*!< Select LUT9 output to be connected to PLU output */ + kPLU_OUT_SRC_LUT_10 = 10U, /*!< Select LUT10 output to be connected to PLU output */ + kPLU_OUT_SRC_LUT_11 = 11U, /*!< Select LUT11 output to be connected to PLU output */ + kPLU_OUT_SRC_LUT_12 = 12U, /*!< Select LUT12 output to be connected to PLU output */ + kPLU_OUT_SRC_LUT_13 = 13U, /*!< Select LUT13 output to be connected to PLU output */ + kPLU_OUT_SRC_LUT_14 = 14U, /*!< Select LUT14 output to be connected to PLU output */ + kPLU_OUT_SRC_LUT_15 = 15U, /*!< Select LUT15 output to be connected to PLU output */ + kPLU_OUT_SRC_LUT_16 = 16U, /*!< Select LUT16 output to be connected to PLU output */ + kPLU_OUT_SRC_LUT_17 = 17U, /*!< Select LUT17 output to be connected to PLU output */ + kPLU_OUT_SRC_LUT_18 = 18U, /*!< Select LUT18 output to be connected to PLU output */ + kPLU_OUT_SRC_LUT_19 = 19U, /*!< Select LUT19 output to be connected to PLU output */ + kPLU_OUT_SRC_LUT_20 = 20U, /*!< Select LUT20 output to be connected to PLU output */ + kPLU_OUT_SRC_LUT_21 = 21U, /*!< Select LUT21 output to be connected to PLU output */ + kPLU_OUT_SRC_LUT_22 = 22U, /*!< Select LUT22 output to be connected to PLU output */ + kPLU_OUT_SRC_LUT_23 = 23U, /*!< Select LUT23 output to be connected to PLU output */ + kPLU_OUT_SRC_LUT_24 = 24U, /*!< Select LUT24 output to be connected to PLU output */ + kPLU_OUT_SRC_LUT_25 = 25U, /*!< Select LUT25 output to be connected to PLU output */ + kPLU_OUT_SRC_FLIPFLOP_0 = 26U, /*!< Select Flip-Flops state(0) to be connected to PLU output */ + kPLU_OUT_SRC_FLIPFLOP_1 = 27U, /*!< Select Flip-Flops state(1) to be connected to PLU output */ + kPLU_OUT_SRC_FLIPFLOP_2 = 28U, /*!< Select Flip-Flops state(2) to be connected to PLU output */ + kPLU_OUT_SRC_FLIPFLOP_3 = 29U /*!< Select Flip-Flops state(3) to be connected to PLU output */ +} plu_output_source_t; + +#if defined(FSL_FEATURE_PLU_HAS_WAKEINT_CTRL_REG) && FSL_FEATURE_PLU_HAS_WAKEINT_CTRL_REG + +/*! @brief The enumerator of PLU Interrupt. */ +enum _plu_interrupt_mask +{ + kPLU_OUTPUT_0_INTERRUPT_MASK = 1 << 0, /*!< Select PLU output 0 contribute to interrupt/wake-up generation */ + kPLU_OUTPUT_1_INTERRUPT_MASK = 1 << 1, /*!< Select PLU output 1 contribute to interrupt/wake-up generation */ + kPLU_OUTPUT_2_INTERRUPT_MASK = 1 << 2, /*!< Select PLU output 2 contribute to interrupt/wake-up generation */ + kPLU_OUTPUT_3_INTERRUPT_MASK = 1 << 3, /*!< Select PLU output 3 contribute to interrupt/wake-up generation */ + kPLU_OUTPUT_4_INTERRUPT_MASK = 1 << 4, /*!< Select PLU output 4 contribute to interrupt/wake-up generation */ + kPLU_OUTPUT_5_INTERRUPT_MASK = 1 << 5, /*!< Select PLU output 5 contribute to interrupt/wake-up generation */ + kPLU_OUTPUT_6_INTERRUPT_MASK = 1 << 6, /*!< Select PLU output 6 contribute to interrupt/wake-up generation */ + kPLU_OUTPUT_7_INTERRUPT_MASK = 1 << 7 /*!< Select PLU output 7 contribute to interrupt/wake-up generation */ +}; + +/*! @brief Control input of the PLU, add filtering for glitch. */ +typedef enum _plu_wakeint_filter_mode +{ + kPLU_WAKEINT_FILTER_MODE_BYPASS = 0U, /*!< Select Bypass mode */ + kPLU_WAKEINT_FILTER_MODE_1_CLK_PERIOD = 1U, /*!< Filter 1 clock period */ + kPLU_WAKEINT_FILTER_MODE_2_CLK_PERIOD = 2U, /*!< Filter 2 clock period */ + kPLU_WAKEINT_FILTER_MODE_3_CLK_PERIOD = 3U /*!< Filter 3 clock period */ +} plu_wakeint_filter_mode_t; + +/*! @brief Clock source for filter mode. */ +typedef enum _plu_wakeint_filter_clock_source +{ + kPLU_WAKEINT_FILTER_CLK_SRC_1MHZ_LPOSC = 0U, /*!< Select the 1MHz low-power oscillator as the filter clock */ + kPLU_WAKEINT_FILTER_CLK_SRC_12MHZ_FRO = 1U, /*!< Select the 12MHz FRO as the filer clock */ + kPLU_WAKEINT_FILTER_CLK_SRC_ALT = 2U /*!< Select a third clock source */ +} plu_wakeint_filter_clock_source_t; + +/*! @brief Wake configuration. */ +typedef struct _plu_wakeint_config +{ + plu_wakeint_filter_mode_t filterMode; /*!< Filter Mode. */ + plu_wakeint_filter_clock_source_t clockSource; /*!< The clock source for filter mode. */ +} plu_wakeint_config_t; +#endif /* FSL_FEATURE_PLU_HAS_WAKEINT_CTRL_REG */ + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Enable the PLU clock and reset the module. + * + * @note This API should be called at the beginning of the application using the PLU driver. + * + * @param base PLU peripheral base address + */ +void PLU_Init(PLU_Type *base); + +/*! + * @brief Gate the PLU clock + * + * @param base PLU peripheral base address + */ +void PLU_Deinit(PLU_Type *base); + +/*! @}*/ + +/*! + * @name Set input/output source and Truth Table + * @{ + */ + +/*! + * @brief Set Input source of LUT. + * + * Note: An external clock must be applied to the PLU_CLKIN input when using FFs. + * For each LUT, the slot associated with the output from LUTn itself is tied low. + * + * @param base PLU peripheral base address. + * @param lutIndex LUT index (see @ref plu_lut_index_t typedef enumeration). + * @param lutInIndex LUT input index (see @ref plu_lut_in_index_t typedef enumeration). + * @param inputSrc LUT input source (see @ref plu_lut_input_source_t typedef enumeration). + */ +static inline void PLU_SetLutInputSource(PLU_Type *base, + plu_lut_index_t lutIndex, + plu_lut_in_index_t lutInIndex, + plu_lut_input_source_t inputSrc) +{ + PLU->LUT[lutIndex].INP_MUX[lutInIndex] = (uint32_t)inputSrc; +} + +/*! + * @brief Set Output source of PLU. + * + * Note: An external clock must be applied to the PLU_CLKIN input when using FFs. + * + * @param base PLU peripheral base address. + * @param outputIndex PLU output index (see @ref plu_output_index_t typedef enumeration). + * @param outputSrc PLU output source (see @ref plu_output_source_t typedef enumeration). + */ +static inline void PLU_SetOutputSource(PLU_Type *base, plu_output_index_t outputIndex, plu_output_source_t outputSrc) +{ + base->OUTPUT_MUX[outputIndex] = (uint32_t)outputSrc; +} + +/*! + * @brief Set Truth Table of LUT. + * + * @param base PLU peripheral base address. + * @param lutIndex LUT index (see @ref plu_lut_index_t typedef enumeration). + * @param truthTable Truth Table value. + */ +static inline void PLU_SetLutTruthTable(PLU_Type *base, plu_lut_index_t lutIndex, uint32_t truthTable) +{ + base->LUT_TRUTH[lutIndex] = truthTable; +} + +/*! @}*/ + +/*! + * @name Read current Output State + * @{ + */ + +/*! + * @brief Read the current state of the 8 designated PLU Outputs. + * + * Note: The PLU bus clock must be re-enabled prior to reading the Outpus Register if PLU bus clock is + * shut-off. + * + * @param base PLU peripheral base address. + * @return Current PLU output state value. + */ +static inline uint32_t PLU_ReadOutputState(PLU_Type *base) +{ + return (base->OUTPUTS & PLU_OUTPUTS_OUTPUT_STATE_MASK); +} + +/*! @}*/ + +#if defined(FSL_FEATURE_PLU_HAS_WAKEINT_CTRL_REG) && FSL_FEATURE_PLU_HAS_WAKEINT_CTRL_REG +/*! + * @name Wake-up/Interrupt Control + * @{ + */ + +/*! + * @brief Gets an available pre-defined settings for wakeup/interrupt control. + * + * This function initializes the initial configuration structure with an available settings. The default values are: + * @code + * config->filterMode = kPLU_WAKEINT_FILTER_MODE_BYPASS; + * config->clockSource = kPLU_WAKEINT_FILTER_CLK_SRC_1MHZ_LPOSC; + * @endcode + * @param config Pointer to configuration structure. + */ +void PLU_GetDefaultWakeIntConfig(plu_wakeint_config_t *config); + +/*! + * @brief Enable PLU outputs wakeup/interrupt request. + * + * This function enables Any of the eight selected PLU outputs to contribute to an asynchronous wake-up or an interrupt + * request. + * + * Note: If a PLU_CLKIN is provided, the raw wake-up/interrupt request will be set on the rising-edge of the PLU_CLKIN + * whenever the raw request signal is high. This registered signal will be glitch-free and just use the default wakeint + * config by PLU_GetDefaultWakeIntConfig(). If not, have to specify the filter mode and clock source to eliminate the + * glitches caused by long and widely disparate delays through the network of LUTs making up the PLU. This way may + * increase power consumption in low-power operating modes and inject delay before the wake-up/interrupt request is + * generated. + * + * @param base PLU peripheral base address. + * @param interruptMask PLU interrupt mask (see @ref _plu_interrupt_mask enumeration). + * @param config Pointer to configuration structure (see @ref plu_wakeint_config_t typedef enumeration) + */ +void PLU_EnableWakeIntRequest(PLU_Type *base, uint32_t interruptMask, const plu_wakeint_config_t *config); + +/*! + * @brief Latch an interrupt + * + * This function latches the interrupt and then it can be cleared with PLU_ClearLatchedInterrupt(). + * + * Note: This mode is not compatible with use of the glitch filter. If this bit is set, the FILTER MODE should be set + * to kPLU_WAKEINT_FILTER_MODE_BYPASS (Bypass Mode) and PLU_CLKIN should be provided. If this bit is set, the + * wake-up/interrupt request will be set on the rising-edge of PLU_CLKIN whenever the raw wake-up/interrupt signal is + * high. The request must be cleared by software. + * + * @param base PLU peripheral base address. + */ +static inline void PLU_LatchInterrupt(PLU_Type *base) +{ + base->WAKEINT_CTRL |= PLU_WAKEINT_CTRL_LATCH_ENABLE_MASK; +} + +/*! + * @brief Clear the latched interrupt + * + * This function clears the wake-up/interrupt request flag latched by PLU_LatchInterrupt() + * + * Note: It is not necessary for the PLU bus clock to be enabled in order to write-to or read-back this bit. + * + * @param base PLU peripheral base address. + */ +void PLU_ClearLatchedInterrupt(PLU_Type *base); + +/*! @}*/ +#endif /* FSL_FEATURE_PLU_HAS_WAKEINT_CTRL_REG */ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_PLU_H_ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_power.c b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_power.c new file mode 100644 index 0000000000..b4c0279437 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_power.c @@ -0,0 +1,1985 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016, NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#include "fsl_common.h" +#include "fsl_power.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.power" +#endif + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/** @brief Low Power main structure */ +typedef enum +{ + VD_AON = 0x0, /*!< Digital Always On power domain */ + VD_MEM = 0x1, /*!< Memories (SRAM) power domain */ + VD_DCDC = 0x2, /*!< Core logic power domain */ + VD_DEEPSLEEP = 0x3 /*!< Core logic power domain */ +} LPC_POWER_DOMAIN_T; + +/** + * @brief LDO_FLASH_NV & LDO_USB voltage settings + */ +typedef enum _v_flashnv +{ + V_LDOFLASHNV_1P650 = 0, /*!< 0.95 V */ + V_LDOFLASHNV_1P700 = 1, /*!< 0.975 V */ + V_LDOFLASHNV_1P750 = 2, /*!< 1 V */ + V_LDOFLASHNV_0P800 = 3, /*!< 1.025 V */ + V_LDOFLASHNV_1P850 = 4, /*!< 1.050 V */ + V_LDOFLASHNV_1P900 = 5, /*!< 1.075 V */ + V_LDOFLASHNV_1P950 = 6, /*!< 1.1 V */ + V_LDOFLASHNV_2P000 = 7 /*!< 1.125 V */ +} v_flashnv_t; + +/** @brief Low Power main structure */ +typedef struct +{ /* */ + __IO uint32_t CFG; /*!< Low Power Mode Configuration, and miscallenous options */ + __IO uint32_t PDCTRL0; /*!< Power Down control : controls power of various modules + in the different Low power modes, including ROM */ + __IO uint32_t SRAMRETCTRL; /*!< Power Down control : controls power SRAM instances + in the different Low power modes */ + __IO uint32_t CPURETCTRL; /*!< CPU0 retention control : controls CPU retention parameters in POWER DOWN modes */ + __IO uint64_t VOLTAGE; /*!< Voltage control in Low Power Modes */ + __IO uint64_t WAKEUPSRC; /*!< Wake up sources control for sleepcon */ + __IO uint64_t WAKEUPINT; /*!< Wake up sources control for ARM */ + __IO uint32_t HWWAKE; /*!< Interrupt that can postpone power down modes + in case an interrupt is pending when the processor request deepsleep */ + __IO uint32_t WAKEUPIOSRC; /*!< Wake up I/O sources in DEEP POWER DOWN mode */ + __IO uint32_t TIMERCFG; /*!< Wake up timers configuration */ + __IO uint32_t TIMERCOUNT; /*!< Wake up Timer count*/ + __IO uint32_t POWERCYCLE; /*!< Cancels entry in Low Power mode if set with 0xDEADABBA (might be used by some + interrupt handlers)*/ +} LPC_LOWPOWER_T; + +/* */ +#define LOWPOWER_POWERCYCLE_CANCELLED 0xDEADABBAUL /*!< */ + +/** + * @brief SRAM Low Power Modes + */ +#define LOWPOWER_SRAM_LPMODE_MASK (0xFUL) +#define LOWPOWER_SRAM_LPMODE_ACTIVE (0x6UL) /*!< SRAM functional mode */ +#define LOWPOWER_SRAM_LPMODE_SLEEP (0xFUL) /*!< SRAM Sleep mode (Data retention, fast wake up) */ +#define LOWPOWER_SRAM_LPMODE_DEEPSLEEP (0x8UL) /*!< SRAM Deep Sleep mode (Data retention, slow wake up) */ +#define LOWPOWER_SRAM_LPMODE_SHUTDOWN (0x9UL) /*!< SRAM Shut Down mode (no data retention) */ +#define LOWPOWER_SRAM_LPMODE_POWERUP (0xAUL) /*!< SRAM is powering up */ + +/** + * @brief Wake up timers configuration in Low Power Modes + */ +#define LOWPOWER_TIMERCFG_CTRL_INDEX 0 +#define LOWPOWER_TIMERCFG_CTRL_MASK (0x1UL << LOWPOWER_TIMERCFG_CTRL_INDEX) +#define LOWPOWER_TIMERCFG_TIMER_INDEX 1 +#define LOWPOWER_TIMERCFG_TIMER_MASK (0x7UL << LOWPOWER_TIMERCFG_TIMER_INDEX) +#define LOWPOWER_TIMERCFG_OSC32K_INDEX 4 +#define LOWPOWER_TIMERCFG_OSC32K_MASK (0x1UL << LOWPOWER_TIMERCFG_OSC32K_INDEX) + +#define LOWPOWER_TIMERCFG_CTRL_DISABLE 0 /*!< Wake Timer Disable */ +#define LOWPOWER_TIMERCFG_CTRL_ENABLE 1 /*!< Wake Timer Enable */ + +/** + * @brief Primary Wake up timers configuration in Low Power Modes + */ +#define LOWPOWER_TIMERCFG_TIMER_RTC1KHZ 0 /*!< 1 KHz Real Time Counter (RTC) used as wake up source */ +#define LOWPOWER_TIMERCFG_TIMER_RTC1HZ 1 /*!< 1 Hz Real Time Counter (RTC) used as wake up source */ +#define LOWPOWER_TIMERCFG_TIMER_OSTIMER 2 /*!< OS Event Timer used as wake up source */ + +#define LOWPOWER_TIMERCFG_OSC32K_FRO32KHZ 0 /*!< Wake up Timers uses FRO 32 KHz as clock source */ +#define LOWPOWER_TIMERCFG_OSC32K_XTAL32KHZ 1 /*!< Wake up Timers uses Chrystal 32 KHz as clock source */ + +//! @brief Interface for lowpower functions +typedef struct LowpowerDriverInterface +{ + void (*power_cycle_cpu_and_flash)(void); + void (*set_lowpower_mode)(LPC_LOWPOWER_T *p_lowpower_cfg); +} lowpower_driver_interface_t; + +/**< DCDC Power Profiles */ +typedef enum +{ + DCDC_POWER_PROFILE_LOW, /**< LOW (for CPU frequencies below DCDC_POWER_PROFILE_LOW_MAX_FREQ_HZ) */ + DCDC_POWER_PROFILE_MEDIUM, /**< MEDIUM (for CPU frequencies between DCDC_POWER_PROFILE_LOW_MAX_FREQ_HZ and + DCDC_POWER_PROFILE_MEDIUM_MAX_FREQ_HZ) */ + DCDC_POWER_PROFILE_HIGH, /**< HIGH (for CPU frequencies between DCDC_POWER_PROFILE_MEDIUM_MAX_FREQ_HZ and + DCDC_POWER_PROFILE_HIGH_MAX_FREQ_HZ) */ +} lowpower_dcdc_power_profile_enum; + +/**< Manufacturing Process Corners */ +typedef enum +{ + PROCESS_CORNER_SSS, /**< Slow Corner Process */ + PROCESS_CORNER_NNN, /**< Nominal Corner Process */ + PROCESS_CORNER_FFF, /**< Fast Corner Process */ + PROCESS_CORNER_OTHERS, /**< SFN, SNF, NFS, Poly Res ... Corner Process */ +} lowpower_process_corner_enum; + +/** + * @brief DCDC voltage settings + */ +typedef enum _v_dcdc +{ + V_DCDC_0P950 = 0, /*!< 0.95 V */ + V_DCDC_0P975 = 1, /*!< 0.975 V */ + V_DCDC_1P000 = 2, /*!< 1 V */ + V_DCDC_1P025 = 3, /*!< 1.025 V */ + V_DCDC_1P050 = 4, /*!< 1.050 V */ + V_DCDC_1P075 = 5, /*!< 1.075 V */ + V_DCDC_1P100 = 6, /*!< 1.1 V */ + V_DCDC_1P125 = 7, /*!< 1.125 V */ + V_DCDC_1P150 = 8, /*!< 1.150 V */ + V_DCDC_1P175 = 9, /*!< 1.175 V */ + V_DCDC_1P200 = 10 /*!< 1.2 V */ +} v_dcdc_t; + +/** + * @brief Deep Sleep LDO voltage settings + */ +typedef enum _v_deepsleep +{ + V_DEEPSLEEP_0P900 = 0, /*!< 0.9 V */ + V_DEEPSLEEP_0P925 = 1, /*!< 0.925 V */ + V_DEEPSLEEP_0P950 = 2, /*!< 0.95 V */ + V_DEEPSLEEP_0P975 = 3, /*!< 0.975 V */ + V_DEEPSLEEP_1P000 = 4, /*!< 1.000 V */ + V_DEEPSLEEP_1P025 = 5, /*!< 1.025 V */ + V_DEEPSLEEP_1P050 = 6, /*!< 1.050 V */ + V_DEEPSLEEP_1P075 = 7 /*!< 1.075 V */ +} v_deepsleep_t; + +/** + * @brief Always On and Memories LDO voltage settings + */ +typedef enum _v_ao +{ + V_AO_0P700 = 1, /*!< 0.7 V */ + V_AO_0P725 = 2, /*!< 0.725 V */ + V_AO_0P750 = 3, /*!< 0.75 V */ + V_AO_0P775 = 4, /*!< 0.775 V */ + V_AO_0P800 = 5, /*!< 0.8 V */ + V_AO_0P825 = 6, /*!< 0.825 V */ + V_AO_0P850 = 7, /*!< 0.85 V */ + V_AO_0P875 = 8, /*!< 0.875 V */ + V_AO_0P900 = 9, /*!< 0.9 V */ + V_AO_0P960 = 10, /*!< 0.96 V */ + V_AO_0P970 = 11, /*!< 0.97 V */ + V_AO_0P980 = 12, /*!< 0.98 V */ + V_AO_0P990 = 13, /*!< 0.99 V */ + V_AO_1P000 = 14, /*!< 1 V */ + V_AO_1P010 = 15, /*!< 1.01 V */ + V_AO_1P020 = 16, /*!< 1.02 V */ + V_AO_1P030 = 17, /*!< 1.03 V */ + V_AO_1P040 = 18, /*!< 1.04 V */ + V_AO_1P050 = 19, /*!< 1.05 V */ + V_AO_1P060 = 20, /*!< 1.06 V */ + V_AO_1P070 = 21, /*!< 1.07 V */ + V_AO_1P080 = 22, /*!< 1.08 V */ + V_AO_1P090 = 23, /*!< 1.09 V */ + V_AO_1P100 = 24, /*!< 1.1 V */ + V_AO_1P110 = 25, /*!< 1.11 V */ + V_AO_1P120 = 26, /*!< 1.12 V */ + V_AO_1P130 = 27, /*!< 1.13 V */ + V_AO_1P140 = 28, /*!< 1.14 V */ + V_AO_1P150 = 29, /*!< 1.15 V */ + V_AO_1P160 = 30, /*!< 1.16 V */ + V_AO_1P220 = 31 /*!< 1.22 V */ +} v_ao_t; + +/* Low Power modes */ +#define LOWPOWER_CFG_LPMODE_INDEX 0 +#define LOWPOWER_CFG_LPMODE_MASK (0x3UL << LOWPOWER_CFG_LPMODE_INDEX) +#define LOWPOWER_CFG_SELCLOCK_INDEX 2 +#define LOWPOWER_CFG_SELCLOCK_MASK (0x1UL << LOWPOWER_CFG_SELCLOCK_INDEX) +#define LOWPOWER_CFG_SELMEMSUPPLY_INDEX 3 +#define LOWPOWER_CFG_SELMEMSUPPLY_MASK (0x1UL << LOWPOWER_CFG_SELMEMSUPPLY_INDEX) +#define LOWPOWER_CFG_MEMLOWPOWERMODE_INDEX 4 +#define LOWPOWER_CFG_MEMLOWPOWERMODE_MASK (0x1UL << LOWPOWER_CFG_MEMLOWPOWERMODE_INDEX) +#define LOWPOWER_CFG_LDODEEPSLEEPREF_INDEX 5 +#define LOWPOWER_CFG_LDODEEPSLEEPREF_MASK (0x1UL << LOWPOWER_CFG_LDODEEPSLEEPREF_INDEX) + +#define LOWPOWER_CFG_LPMODE_ACTIVE 0 /*!< ACTIVE mode */ +#define LOWPOWER_CFG_LPMODE_DEEPSLEEP 1 /*!< DEEP SLEEP mode */ +#define LOWPOWER_CFG_LPMODE_POWERDOWN 2 /*!< POWER DOWN mode */ +#define LOWPOWER_CFG_LPMODE_DEEPPOWERDOWN 3 /*!< DEEP POWER DOWN mode */ +#define LOWPOWER_CFG_LPMODE_SLEEP 4 /*!< SLEEP mode */ + +#define LOWPOWER_CFG_SELCLOCK_1MHZ 0 /*!< The 1 MHz clock is used during the configuration of the PMC */ +#define LOWPOWER_CFG_SELCLOCK_12MHZ \ + 1 /*!< The 12 MHz clock is used during the configuration of the PMC (to speed up PMC configuration process)*/ + +#define LOWPOWER_CFG_SELMEMSUPPLY_LDOMEM 0 /*!< In DEEP SLEEP power mode, the Memories are supplied by the LDO_MEM */ +#define LOWPOWER_CFG_SELMEMSUPPLY_LDODEEPSLEEP \ + 1 /*!< In DEEP SLEEP power mode, the Memories are supplied by the LDO_DEEP_SLEEP (or DCDC) */ + +#define LOWPOWER_CFG_MEMLOWPOWERMODE_SOURCEBIASING \ + 0 /*!< All SRAM instances use "Source Biasing" as low power mode technic (it is recommended to set LDO_MEM as high \ + as possible -- 1.1V typical -- during low power mode) */ +#define LOWPOWER_CFG_MEMLOWPOWERMODE_VOLTAGESCALING \ + 1 /*!< All SRAM instances use "Voltage Scaling" as low power mode technic (it is recommended to set LDO_MEM as low \ + as possible -- down to 0.7V -- during low power mode) */ + +/* CPU Retention Control*/ +#define LOWPOWER_CPURETCTRL_ENA_INDEX 0 +#define LOWPOWER_CPURETCTRL_ENA_MASK (0x1UL << LOWPOWER_CPURETCTRL_ENA_INDEX) +#define LOWPOWER_CPURETCTRL_MEMBASE_INDEX 1 +#define LOWPOWER_CPURETCTRL_MEMBASE_MASK (0x1FFFUL << LOWPOWER_CPURETCTRL_MEMBASE_INDEX) +#define LOWPOWER_CPURETCTRL_RETDATALENGTH_INDEX 14 +#define LOWPOWER_CPURETCTRL_RETDATALENGTH_MASK (0x3FFUL << LOWPOWER_CPURETCTRL_RETDATALENGTH_INDEX) + +/* Voltgae setting*/ +#define DCDC_POWER_PROFILE_LOW_MAX_FREQ_HZ \ + (72000000U) /* Maximum System Frequency allowed with DCDC Power Profile LOW */ +#define DCDC_POWER_PROFILE_MEDIUM_MAX_FREQ_HZ \ + (100000000U) /* Maximum System Frequency allowed with DCDC Power Profile MEDIUM */ +#define DCDC_POWER_PROFILE_HIGH_MAX_FREQ_HZ \ + (150000000U) /* Maximum System Frequency allowed with DCDC Power Profile HIGH */ +#define PROCESS_NNN_AVG_HZ (19300000U) /* Average Ring OScillator value for Nominal (NNN) Manufacturing Process */ +#define PROCESS_NNN_STD_HZ \ + (400000U) /* Standard Deviation Ring OScillator value for Nominal (NNN) Manufacturing Process */ +#define PROCESS_NNN_LIMITS \ + (6U) /* Nominal (NNN) Manufacturing Process Ring Oscillator values limit (with respect to the Average value) */ +#define PROCESS_NNN_MIN_HZ \ + (PROCESS_NNN_AVG_HZ - \ + (PROCESS_NNN_LIMITS * \ + PROCESS_NNN_STD_HZ)) /* Minimum Ring OScillator value for Nominal (NNN) Manufacturing Process */ +#define PROCESS_NNN_MAX_HZ \ + (PROCESS_NNN_AVG_HZ + \ + (PROCESS_NNN_LIMITS * \ + PROCESS_NNN_STD_HZ)) /* Maximum Ring OScillator value for Nominal (NNN) Manufacturing Process */ +#define VOLTAGE_SSS_LOW_MV (1100U) /* Voltage Settings for : Process=SSS, DCDC Power Profile=LOW */ +#define VOLTAGE_SSS_MED_MV (1150U) /* Voltage Settings for : Process=SSS, DCDC Power Profile=MEDIUM */ +#define VOLTAGE_SSS_HIG_MV (1200U) /* Voltage Settings for : Process=SSS, DCDC Power Profile=HIGH */ +#define VOLTAGE_NNN_LOW_MV (1050U) /* Voltage Settings for : Process=NNN, DCDC Power Profile=LOW */ +#define VOLTAGE_NNN_MED_MV (1075U) /* Voltage Settings for : Process=NNN, DCDC Power Profile=MEDIUM */ +#define VOLTAGE_NNN_HIG_MV (1150U) /* Voltage Settings for : Process=NNN, DCDC Power Profile=HIGH */ +#define VOLTAGE_FFF_LOW_MV (1000U) /* Voltage Settings for : Process=FFF, DCDC Power Profile=LOW */ +#define VOLTAGE_FFF_MED_MV (1025U) /* Voltage Settings for : Process=FFF, DCDC Power Profile=MEDIUM */ +#define VOLTAGE_FFF_HIG_MV (1050U) /* Voltage Settings for : Process=FFF, DCDC Power Profile=HIGH */ + +/** + * @brief LDO Voltage control in Low Power Modes + */ +#define LOWPOWER_VOLTAGE_LDO_PMU_INDEX 0 +#define LOWPOWER_VOLTAGE_LDO_PMU_MASK (0x1FULL << LOWPOWER_VOLTAGE_LDO_PMU_INDEX) +#define LOWPOWER_VOLTAGE_LDO_MEM_INDEX 5 +#define LOWPOWER_VOLTAGE_LDO_MEM_MASK (0x1FULL << LOWPOWER_VOLTAGE_LDO_MEM_INDEX) +#define LOWPOWER_VOLTAGE_LDO_DEEP_SLEEP_INDEX 10 +#define LOWPOWER_VOLTAGE_LDO_DEEP_SLEEP_MASK (0x7ULL << LOWPOWER_VOLTAGE_LDO_DEEP_SLEEP_INDEX) +#define LOWPOWER_VOLTAGE_LDO_PMU_BOOST_INDEX 19 +#define LOWPOWER_VOLTAGE_LDO_PMU_BOOST_MASK (0x1FULL << LOWPOWER_VOLTAGE_LDO_PMU_BOOST_INDEX) +#define LOWPOWER_VOLTAGE_LDO_MEM_BOOST_INDEX 24 +#define LOWPOWER_VOLTAGE_LDO_MEM_BOOST_MASK (0x1FULL << LOWPOWER_VOLTAGE_LDO_MEM_BOOST_INDEX) +#define LOWPOWER_VOLTAGE_DCDC_INDEX 29 +#define LOWPOWER_VOLTAGE_DCDC_MASK (0xFULL << LOWPOWER_VOLTAGE_DCDC_INDEX) + +/*! @brief set and clear bit MACRO's. */ +#define U32_SET_BITS(P, B) ((*(uint32_t *)P) |= (B)) +#define U32_CLR_BITS(P, B) ((*(uint32_t *)P) &= ~(B)) +/* Return values from Config (N-2) page of flash */ +#define GET_16MXO_TRIM() (*(uint32_t *)(FLASH_NMPA_BASE + 0xC8U)) // (0x3FCC8) +#define GET_32KXO_TRIM() (*(uint32_t *)(FLASH_NMPA_BASE + 0xCCU)) // (0x3FCCC) + +#define CPU_RETENTION_RAMX_STORAGE_START_ADDR (0x04002000) + +#define XO_SLAVE_EN (1) +/******************************************************************************* + * Codes + ******************************************************************************/ + +/******************************************************************************* + * LOCAL FUNCTIONS PROTOTYPES + ******************************************************************************/ +static void lf_get_deepsleep_core_supply_cfg(uint32_t exclude_from_pd, uint32_t *dcdc_voltage); +static uint32_t lf_set_ldo_ao_ldo_mem_voltage(uint32_t p_lp_mode, uint32_t p_dcdc_voltage); +static uint32_t lf_wakeup_io_ctrl(uint32_t p_wakeup_io_ctrl); +static uint8_t CLOCK_u8OscCapConvert(uint8_t u8OscCap, uint8_t u8CapBankDiscontinuity); + +static void lowpower_set_dcdc_power_profile(lowpower_dcdc_power_profile_enum dcdc_power_profile); +static lowpower_process_corner_enum lowpower_get_part_process_corner(void); +static void lowpower_set_voltage_for_process(lowpower_dcdc_power_profile_enum dcdc_power_profile); +static lowpower_driver_interface_t *s_lowpowerDriver = (lowpower_driver_interface_t *)(0x130050e4); + +/** + * @brief Configures and enters in low power mode + * @param p_lowpower_cfg: pointer to a structure that contains all low power mode parameters + * @return Nothing + * + * !!! IMPORTANT NOTES : + * 1 - CPU Interrupt Enable registers are updated with p_lowpower_cfg->WAKEUPINT. They are NOT restored by the + * API. + * 2 - The Non Maskable Interrupt (NMI) should be disable before calling this API (otherwise, there is a risk + * of Dead Lock). + * 3 - The HARD FAULT handler should execute from SRAM. (The Hard fault handler should initiate a full chip + * reset) + */ +static void POWER_EnterLowPower(LPC_LOWPOWER_T *p_lowpower_cfg); + +/** + * @brief + * @param + * @return + */ +static void lf_set_dcdc_power_profile_low(void) +{ +#define DCDC_POWER_PROFILE_LOW_0_ADDRS (FLASH_NMPA_BASE + 0xE0U) // N4M (0x3FCE0U) / N4S (0x9FCE0U) +#define DCDC_POWER_PROFILE_LOW_1_ADDRS (FLASH_NMPA_BASE + 0xE4U) // N4M (0x3FCE4U) / N4S (0x9FCE4U) + + uint32_t dcdcTrimValue0 = (*((volatile unsigned int *)(DCDC_POWER_PROFILE_LOW_0_ADDRS))); + uint32_t dcdcTrimValue1 = (*((volatile unsigned int *)(DCDC_POWER_PROFILE_LOW_1_ADDRS))); + + if (0UL != (dcdcTrimValue0 & 0x1UL)) + { + PMC->DCDC0 = dcdcTrimValue0 >> 1; + PMC->DCDC1 = dcdcTrimValue1; + } +} + +/** + * @brief Configures and enters in low power mode + * @param : p_lowpower_cfg + * @return Nothing + */ +static void POWER_EnterLowPower(LPC_LOWPOWER_T *p_lowpower_cfg) +{ + /* PMC clk set to 12 MHZ */ + p_lowpower_cfg->CFG |= (uint32_t)LOWPOWER_CFG_SELCLOCK_12MHZ << LOWPOWER_CFG_SELCLOCK_INDEX; + + /* Enable Analog References fast wake-up in case of wake-up from a low power mode (DEEP SLEEP, POWER DOWN and DEEP + * POWER DOWN) and Hardware Pin reset */ + PMC->REFFASTWKUP = (PMC->REFFASTWKUP & (~PMC_REFFASTWKUP_LPWKUP_MASK) & (~PMC_REFFASTWKUP_HWWKUP_MASK)) | + PMC_REFFASTWKUP_LPWKUP(1) | PMC_REFFASTWKUP_HWWKUP(1); + + /* SRAM uses Voltage Scaling in all Low Power modes */ + PMC->SRAMCTRL = (PMC->SRAMCTRL & (~PMC_SRAMCTRL_SMB_MASK)) | PMC_SRAMCTRL_SMB(3); + + /* CPU Retention configuration : preserve the value of FUNCRETENTIONCTRL.RET_LENTH which is a Hardware defined + * parameter. */ + p_lowpower_cfg->CPURETCTRL = (SYSCON->FUNCRETENTIONCTRL & SYSCON_FUNCRETENTIONCTRL_RET_LENTH_MASK) | + (p_lowpower_cfg->CPURETCTRL & (~SYSCON_FUNCRETENTIONCTRL_RET_LENTH_MASK)); + + /* Switch System Clock to FRO12Mhz (the configuration before calling this function will not be restored back) */ + CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /* Switch main clock to FRO12MHz */ + CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /* Main clock divided by 1 */ + SYSCON->FMCCR = (SYSCON->FMCCR & 0xFFFF0000UL) | 0x201AUL; /* Adjust FMC waiting time cycles */ + lf_set_dcdc_power_profile_low(); /* Align DCDC Power profile with the 12 MHz clock (DCDC Power Profile LOW) */ + + (*(s_lowpowerDriver->set_lowpower_mode))(p_lowpower_cfg); + + /* Restore the configuration of the MISCCTRL Register : LOWPWR_FLASH_BUF = 0, LDOMEMBLEEDDSLP = 0, LDOMEMHIGHZMODE = + * 0 */ + PMC->MISCCTRL &= (~PMC_MISCCTRL_LOWPWR_FLASH_BUF_MASK) & (~PMC_MISCCTRL_DISABLE_BLEED_MASK) & + (~PMC_MISCCTRL_LDOMEMHIGHZMODE_MASK); +} + +/** + * @brief Shut off the Flash and execute the _WFI(), then power up the Flash after wake-up event + * @param None + * @return Nothing + */ +void POWER_CycleCpuAndFlash(void) +{ + (*(s_lowpowerDriver->power_cycle_cpu_and_flash))(); +}; + +/** + * brief PMC Deep Sleep function call + * return nothing + */ +void POWER_EnterDeepSleep(uint32_t exclude_from_pd, + uint32_t sram_retention_ctrl, + uint64_t wakeup_interrupts, + uint32_t hardware_wake_ctrl) +{ + LPC_LOWPOWER_T lv_low_power_mode_cfg; /* Low Power Mode configuration structure */ + uint32_t cpu0_nmi_enable; + uint32_t cpu0_int_enable_0; + uint32_t cpu0_int_enable_1; + uint32_t dcdc_voltage; + uint32_t pmc_reset_ctrl; + /* Clear Low Power Mode configuration variable */ + (void)memset(&lv_low_power_mode_cfg, 0x0, sizeof(LPC_LOWPOWER_T)); + + /* Configure Low Power Mode configuration variable */ + lv_low_power_mode_cfg.CFG |= (uint32_t)LOWPOWER_CFG_LPMODE_DEEPSLEEP + << LOWPOWER_CFG_LPMODE_INDEX; /* DEEPSLEEP mode */ + + lf_get_deepsleep_core_supply_cfg(exclude_from_pd, &dcdc_voltage); + + if (((exclude_from_pd & (uint32_t)kPDRUNCFG_PD_USB1_PHY) != 0UL) && + ((exclude_from_pd & (uint32_t)kPDRUNCFG_PD_LDOUSBHS) != 0UL)) + { + /* USB High Speed is required as wake-up source in Deep Sleep mode: make sure LDO FLASH NV stays powered during + * deep-sleep */ + exclude_from_pd = exclude_from_pd | (uint32_t)kPDRUNCFG_PD_LDOFLASHNV; + } + + /* DCDC will be always used during Deep Sleep (instead of LDO Deep Sleep); Make sure LDO MEM & Analog references + * will stay powered, Shut down ROM */ + lv_low_power_mode_cfg.PDCTRL0 = (~exclude_from_pd & ~(uint32_t)kPDRUNCFG_PD_DCDC & ~(uint32_t)kPDRUNCFG_PD_LDOMEM & + ~(uint32_t)kPDRUNCFG_PD_BIAS) | + (uint32_t)kPDRUNCFG_PD_LDODEEPSLEEP | (uint32_t)kPDRUNCFG_PD_ROM; + + /* Voltage control in DeepSleep Low Power Modes */ + /* The Memories Voltage settings below are for voltage scaling */ + lv_low_power_mode_cfg.VOLTAGE = lf_set_ldo_ao_ldo_mem_voltage(LOWPOWER_CFG_LPMODE_POWERDOWN, dcdc_voltage); + + /* SRAM retention control during POWERDOWN */ + lv_low_power_mode_cfg.SRAMRETCTRL = sram_retention_ctrl; + + /* CPU Wake up & Interrupt sources control */ + lv_low_power_mode_cfg.WAKEUPINT = wakeup_interrupts; + lv_low_power_mode_cfg.WAKEUPSRC = wakeup_interrupts; + + /* Interrupts that allow DMA transfers with Flexcomm without waking up the Processor */ + if (0UL != (hardware_wake_ctrl & (LOWPOWER_HWWAKE_PERIPHERALS | LOWPOWER_HWWAKE_SDMA0 | LOWPOWER_HWWAKE_SDMA1))) + { + lv_low_power_mode_cfg.HWWAKE = (hardware_wake_ctrl & ~LOWPOWER_HWWAKE_FORCED) | LOWPOWER_HWWAKE_ENABLE_FRO192M; + } + + cpu0_nmi_enable = SYSCON->NMISRC & SYSCON_NMISRC_NMIENCPU0_MASK; /* Save the configuration of the NMI Register */ + SYSCON->NMISRC &= ~SYSCON_NMISRC_NMIENCPU0_MASK; /* Disable NMI of CPU0 */ + + /* Save the configuration of the CPU interrupt enable Registers (because they are overwritten inside the low power + * API */ + cpu0_int_enable_0 = NVIC->ISER[0]; + cpu0_int_enable_1 = NVIC->ISER[1]; + + pmc_reset_ctrl = PMC->RESETCTRL; + + if ((pmc_reset_ctrl & (PMC_RESETCTRL_BODCORERESETENA_SECURE_MASK | PMC_RESETCTRL_BODCORERESETENA_SECURE_DP_MASK)) == + ((0x1UL << PMC_RESETCTRL_BODCORERESETENA_SECURE_SHIFT) | + (0x1UL << PMC_RESETCTRL_BODCORERESETENA_SECURE_DP_SHIFT))) + { + /* BoD CORE reset is activated, so make sure BoD Core and Biasing won't be shutdown */ + lv_low_power_mode_cfg.PDCTRL0 &= ~(uint32_t)kPDRUNCFG_PD_BODCORE & ~(uint32_t)kPDRUNCFG_PD_BIAS; + } + if ((pmc_reset_ctrl & (PMC_RESETCTRL_BODVBATRESETENA_SECURE_MASK | PMC_RESETCTRL_BODVBATRESETENA_SECURE_DP_MASK)) == + ((0x1UL << PMC_RESETCTRL_BODVBATRESETENA_SECURE_SHIFT) | + (0x1UL << PMC_RESETCTRL_BODVBATRESETENA_SECURE_DP_SHIFT))) + { + /* BoD VBAT reset is activated, so make sure BoD VBAT and Biasing won't be shutdown */ + lv_low_power_mode_cfg.PDCTRL0 &= ~(uint32_t)kPDRUNCFG_PD_BODVBAT & ~(uint32_t)kPDRUNCFG_PD_BIAS; + } + + /* Enter low power mode */ + POWER_EnterLowPower(&lv_low_power_mode_cfg); + + /* Restore the configuration of the NMI Register */ + SYSCON->NMISRC |= cpu0_nmi_enable; + + /* Restore the configuration of the CPU interrupt enable Registers (because they have been overwritten inside the + * low power API */ + NVIC->ISER[0] = cpu0_int_enable_0; + NVIC->ISER[1] = cpu0_int_enable_1; +} + +/** + * brief PMC power Down function call + * return nothing + */ +void POWER_EnterPowerDown(uint32_t exclude_from_pd, + uint32_t sram_retention_ctrl, + uint64_t wakeup_interrupts, + uint32_t cpu_retention_ctrl) +{ + LPC_LOWPOWER_T lv_low_power_mode_cfg; /* Low Power Mode configuration structure */ + uint32_t cpu0_nmi_enable; + uint32_t cpu0_int_enable_0; + uint32_t cpu0_int_enable_1; + uint64_t wakeup_src_int; + uint32_t pmc_reset_ctrl; + uint32_t rng_entropy_save[6]; + + uint32_t analog_ctrl_regs[12]; /* To store Analog Controller Regristers */ + + /* Clear Low Power Mode configuration variable */ + (void)memset(&lv_low_power_mode_cfg, 0x0, sizeof(LPC_LOWPOWER_T)); + + /* Configure Low Power Mode configuration variable */ + lv_low_power_mode_cfg.CFG |= (uint32_t)LOWPOWER_CFG_LPMODE_POWERDOWN + << LOWPOWER_CFG_LPMODE_INDEX; /* POWER DOWN mode */ + + /* Only FRO32K, XTAL32K, COMP, BIAS and LDO_MEM can be stay powered during POWERDOWN (valid from application point + * of view; Hardware allows BODVBAT, LDODEEPSLEEP and FRO1M to stay powered, that's why they are excluded below) */ + lv_low_power_mode_cfg.PDCTRL0 = (~exclude_from_pd) | (uint32_t)kPDRUNCFG_PD_BODVBAT | (uint32_t)kPDRUNCFG_PD_FRO1M | + (uint32_t)kPDRUNCFG_PD_LDODEEPSLEEP; + + /* @TODO Guillaume: add save/restore entropy during PowerDown */ + /* Entropy for RNG need to saved */ + if ((exclude_from_pd & (uint32_t)kPDRUNCFG_PD_RNG) != 0UL) + { + CLOCK_EnableClock(kCLOCK_Rng); + RESET_ClearPeripheralReset(kRNG_RST_SHIFT_RSTn); + for (int i = 0; i < 6; i++) + { + rng_entropy_save[i] = RNG->RANDOM_NUMBER; + } + } + + /* CPU0 retention Ctrl. + * For the time being, we do not allow customer to relocate the CPU retention area in SRAMX, meaning that the + * retention area range is [0x0400_6000 - 0x0400_6600] (beginning of RAMX2 for N4S) If required by customer, + * retention area range is [0x0400_2000 - 0x0400_2600] (beginning of RAMX2 for N4M) If required by customer, + * cpu_retention_ctrl[13:1] will be used for that to modify the default retention area + */ + lv_low_power_mode_cfg.CPURETCTRL = + (cpu_retention_ctrl & LOWPOWER_CPURETCTRL_ENA_MASK) | + ((((uint32_t)CPU_RETENTION_RAMX_STORAGE_START_ADDR >> 2UL) << LOWPOWER_CPURETCTRL_MEMBASE_INDEX) & + LOWPOWER_CPURETCTRL_MEMBASE_MASK); + if (0UL != (cpu_retention_ctrl & 0x1UL)) + { + /* Add RAMX2 for retention */ + sram_retention_ctrl |= LOWPOWER_SRAMRETCTRL_RETEN_RAMX2; + /* CPU retention is required: store Analog Controller Registers */ + analog_ctrl_regs[0] = ANACTRL->FRO192M_CTRL; + analog_ctrl_regs[1] = ANACTRL->ANALOG_CTRL_CFG; + analog_ctrl_regs[2] = ANACTRL->ADC_CTRL; + analog_ctrl_regs[3] = ANACTRL->XO32M_CTRL; + analog_ctrl_regs[4] = ANACTRL->BOD_DCDC_INT_CTRL; + analog_ctrl_regs[5] = ANACTRL->RINGO0_CTRL; + analog_ctrl_regs[6] = ANACTRL->RINGO1_CTRL; + analog_ctrl_regs[7] = ANACTRL->RINGO2_CTRL; + analog_ctrl_regs[8] = ANACTRL->LDO_XO32M; + analog_ctrl_regs[9] = ANACTRL->AUX_BIAS; + analog_ctrl_regs[10] = ANACTRL->USBHS_PHY_CTRL; + analog_ctrl_regs[11] = ANACTRL->USBHS_PHY_TRIM; + } + + /* SRAM retention control during POWERDOWN */ + lv_low_power_mode_cfg.SRAMRETCTRL = sram_retention_ctrl; + + /* Sanity check: If retention is required for any of SRAM instances, make sure LDO MEM will stay powered */ + if ((sram_retention_ctrl & 0x7FFFUL) != 0UL) + { + lv_low_power_mode_cfg.PDCTRL0 &= ~(uint32_t)kPDRUNCFG_PD_LDOMEM; + } + + /* Voltage control in Low Power Modes */ + /* The Memories Voltage settings below are for voltage scaling */ + lv_low_power_mode_cfg.VOLTAGE = lf_set_ldo_ao_ldo_mem_voltage(LOWPOWER_CFG_LPMODE_POWERDOWN, 0); + + /* CPU Wake up & Interrupt sources control : only WAKEUP_GPIO_GLOBALINT0, WAKEUP_GPIO_GLOBALINT1, WAKEUP_FLEXCOMM3, + * WAKEUP_ACMP_CAPT, WAKEUP_RTC_LITE_ALARM_WAKEUP, WAKEUP_OS_EVENT_TIMER, WAKEUP_ALLWAKEUPIOS */ + wakeup_src_int = (uint64_t)(WAKEUP_GPIO_GLOBALINT0 | WAKEUP_GPIO_GLOBALINT1 | WAKEUP_FLEXCOMM3 | WAKEUP_ACMP | + WAKEUP_RTC_LITE_ALARM_WAKEUP | WAKEUP_OS_EVENT_TIMER | WAKEUP_ALLWAKEUPIOS); + lv_low_power_mode_cfg.WAKEUPINT = wakeup_interrupts & wakeup_src_int; + lv_low_power_mode_cfg.WAKEUPSRC = wakeup_interrupts & wakeup_src_int; + + cpu0_nmi_enable = SYSCON->NMISRC & SYSCON_NMISRC_NMIENCPU0_MASK; /* Save the configuration of the NMI Register */ + SYSCON->NMISRC &= ~SYSCON_NMISRC_NMIENCPU0_MASK; /* Disable NMI of CPU0 */ + + /* Save the configuration of the CPU interrupt enable Registers (because they are overwritten inside the low power + * API */ + cpu0_int_enable_0 = NVIC->ISER[0]; + cpu0_int_enable_1 = NVIC->ISER[1]; + + /* Disable BoD VBAT and BoD Core resets */ + /* BOD VBAT disable reset */ + pmc_reset_ctrl = + PMC->RESETCTRL & (~(PMC_RESETCTRL_BODVBATRESETENA_SECURE_MASK | PMC_RESETCTRL_BODVBATRESETENA_SECURE_DP_MASK)); + pmc_reset_ctrl |= (0x2UL << PMC_RESETCTRL_BODVBATRESETENA_SECURE_SHIFT) | + (0x2UL << PMC_RESETCTRL_BODVBATRESETENA_SECURE_DP_SHIFT); + + /* BOD CORE disable reset */ + pmc_reset_ctrl &= (~(PMC_RESETCTRL_BODCORERESETENA_SECURE_MASK | PMC_RESETCTRL_BODCORERESETENA_SECURE_DP_MASK)); + pmc_reset_ctrl |= (0x2UL << PMC_RESETCTRL_BODCORERESETENA_SECURE_SHIFT) | + (0x2UL << PMC_RESETCTRL_BODCORERESETENA_SECURE_DP_SHIFT); + + PMC->RESETCTRL = pmc_reset_ctrl; + + /* Enter low power mode */ + POWER_EnterLowPower(&lv_low_power_mode_cfg); + + /*** We'll reach this point in case of POWERDOWN with CPU retention or if the POWERDOWN has not been taken (for + instance because an interrupt is pending). In case of CPU retention, assumption is that the SRAM containing the + stack used to call this function shall be preserved during low power ***/ + +#if defined(PUF_SRAM_CTRL_CFG_ENABLE_MASK) + /* Following code is to reset PUF to remove over consumption */ + /* Enable PUF register clock to access register */ + SYSCON->AHBCLKCTRLSET[2] = SYSCON_AHBCLKCTRL2_PUF_MASK; + /* Release PUF reset */ + SYSCON->PRESETCTRLCLR[2] = SYSCON_PRESETCTRL2_PUF_RST_MASK; + /* Enable PUF SRAM */ + PUF_SRAM_CTRL->CFG |= PUF_SRAM_CTRL_CFG_ENABLE_MASK | PUF_SRAM_CTRL_CFG_CKGATING_MASK; + + /* Disable PUF register clock. */ + // Delaying the line of code below until the PUF State Machine execution is completed: + // Shuting down the clock to early will prevent the state machine from reaching the end. + // => Wait for status bit in PUF Controller Registers before stop PUF clock. + while (0UL == (PUF_SRAM_CTRL->INT_STATUS & PUF_SRAM_CTRL_INT_STATUS_READY_MASK)) + { + } + + SYSCON->AHBCLKCTRLCLR[2] = SYSCON_AHBCLKCTRL2_PUF_MASK; +#endif + /* Restore the configuration of the NMI Register */ + SYSCON->NMISRC |= cpu0_nmi_enable; + + /* Restore PMC RESETCTRL register */ + PMC->RESETCTRL = pmc_reset_ctrl; + + /* Restore the configuration of the CPU interrupt enable Registers (because they have been overwritten inside the + * low power API */ + NVIC->ISER[0] = cpu0_int_enable_0; + NVIC->ISER[1] = cpu0_int_enable_1; + + if ((cpu_retention_ctrl & 0x1UL) != 0UL) + { + /* Restore Analog Controller Registers */ + ANACTRL->FRO192M_CTRL = analog_ctrl_regs[0] | ANACTRL_FRO192M_CTRL_WRTRIM_MASK; + ANACTRL->ANALOG_CTRL_CFG = analog_ctrl_regs[1]; + ANACTRL->ADC_CTRL = analog_ctrl_regs[2]; + ANACTRL->XO32M_CTRL = analog_ctrl_regs[3]; + ANACTRL->BOD_DCDC_INT_CTRL = analog_ctrl_regs[4]; + ANACTRL->RINGO0_CTRL = analog_ctrl_regs[5]; + ANACTRL->RINGO1_CTRL = analog_ctrl_regs[6]; + ANACTRL->RINGO2_CTRL = analog_ctrl_regs[7]; + ANACTRL->LDO_XO32M = analog_ctrl_regs[8]; + ANACTRL->AUX_BIAS = analog_ctrl_regs[9]; + ANACTRL->USBHS_PHY_CTRL = analog_ctrl_regs[10]; + ANACTRL->USBHS_PHY_TRIM = analog_ctrl_regs[11]; + } + + /* @TODO Guillaume: add save/restore entropy during PowerDown */ + /* Restore Entropy for RNG */ + if ((exclude_from_pd & (uint32_t)kPDRUNCFG_PD_RNG) != 0UL) + { + RNG->POWERDOWN &= ~RNG_POWERDOWN_POWERDOWN_MASK; + for (int i = 0; i < 6; i++) + { + RNG->ENTROPY_INJECT = rng_entropy_save[i]; + } + } +} + +/** + * brief PMC Deep Sleep Power Down function call + * return nothing + */ +void POWER_EnterDeepPowerDown(uint32_t exclude_from_pd, + uint32_t sram_retention_ctrl, + uint64_t wakeup_interrupts, + uint32_t wakeup_io_ctrl) +{ + LPC_LOWPOWER_T lv_low_power_mode_cfg; /* Low Power Mode configuration structure */ + uint32_t cpu0_nmi_enable; + uint32_t cpu0_int_enable_0; + uint32_t cpu0_int_enable_1; + uint32_t pmc_reset_ctrl; + + /* Clear Low Power Mode configuration variable */ + (void)memset(&lv_low_power_mode_cfg, 0x0, sizeof(LPC_LOWPOWER_T)); + + /* Configure Low Power Mode configuration variable */ + lv_low_power_mode_cfg.CFG |= (uint32_t)LOWPOWER_CFG_LPMODE_DEEPPOWERDOWN + << LOWPOWER_CFG_LPMODE_INDEX; /* DEEP POWER DOWN mode */ + + /* Only FRO32K, XTAL32K and LDO_MEM can be stay powered during DEEPPOWERDOWN (valid from application point of view; + * Hardware allows BODVBAT, BIAS FRO1M and COMP to stay powered, that's why they are excluded below) */ + lv_low_power_mode_cfg.PDCTRL0 = (~exclude_from_pd) | (uint32_t)kPDRUNCFG_PD_BIAS | (uint32_t)kPDRUNCFG_PD_BODVBAT | + (uint32_t)kPDRUNCFG_PD_FRO1M | (uint32_t)kPDRUNCFG_PD_COMP; + + /* SRAM retention control during DEEPPOWERDOWN */ + /* RAM00 used by ROM code to restart. */ + sram_retention_ctrl = sram_retention_ctrl & (~(LOWPOWER_SRAMRETCTRL_RETEN_RAM00)); + + /* SRAM retention control during DEEPPOWERDOWN */ + lv_low_power_mode_cfg.SRAMRETCTRL = sram_retention_ctrl; + + /* Sanity check: If retention is required for any of SRAM instances, make sure LDO MEM will stay powered */ + if ((sram_retention_ctrl & 0x7FFFUL) != 0UL) + { + lv_low_power_mode_cfg.PDCTRL0 &= ~(uint32_t)kPDRUNCFG_PD_LDOMEM; + } + + /* Voltage control in Low Power Modes */ + /* The Memories Voltage settings below are for voltage scaling */ + lv_low_power_mode_cfg.VOLTAGE = lf_set_ldo_ao_ldo_mem_voltage(LOWPOWER_CFG_LPMODE_DEEPPOWERDOWN, 0); + + lv_low_power_mode_cfg.WAKEUPINT = + wakeup_interrupts & (WAKEUP_RTC_LITE_ALARM_WAKEUP | + WAKEUP_OS_EVENT_TIMER); /* CPU Wake up sources control : only WAKEUP_RTC_LITE_ALARM_WAKEUP, + WAKEUP_OS_EVENT_TIMER */ + lv_low_power_mode_cfg.WAKEUPSRC = + wakeup_interrupts & + (WAKEUP_RTC_LITE_ALARM_WAKEUP | WAKEUP_OS_EVENT_TIMER | + WAKEUP_ALLWAKEUPIOS); /*!< Hardware Wake up sources control: : only WAKEUP_RTC_LITE_ALARM_WAKEUP, + WAKEUP_OS_EVENT_TIMER and WAKEUP_ALLWAKEUPIOS */ + + /* Wake up I/O sources */ + lv_low_power_mode_cfg.WAKEUPIOSRC = lf_wakeup_io_ctrl(wakeup_io_ctrl); + + cpu0_nmi_enable = SYSCON->NMISRC & SYSCON_NMISRC_NMIENCPU0_MASK; /* Save the configuration of the NMI Register */ + SYSCON->NMISRC &= ~SYSCON_NMISRC_NMIENCPU0_MASK; /* Disable NMI of CPU0 */ + + /* Save the configuration of the CPU interrupt enable Registers (because they are overwritten inside the low power + * API */ + cpu0_int_enable_0 = NVIC->ISER[0]; + cpu0_int_enable_1 = NVIC->ISER[1]; + + /* Save the configuration of the PMC RESETCTRL register */ + /* BOD VBAT disable reset */ + pmc_reset_ctrl = + PMC->RESETCTRL & (~(PMC_RESETCTRL_BODVBATRESETENA_SECURE_MASK | PMC_RESETCTRL_BODVBATRESETENA_SECURE_DP_MASK)); + pmc_reset_ctrl |= (0x2UL << PMC_RESETCTRL_BODVBATRESETENA_SECURE_SHIFT) | + (0x2UL << PMC_RESETCTRL_BODVBATRESETENA_SECURE_DP_SHIFT); + + /* BOD CORE disable reset */ + pmc_reset_ctrl &= (~(PMC_RESETCTRL_BODCORERESETENA_SECURE_MASK | PMC_RESETCTRL_BODCORERESETENA_SECURE_DP_MASK)); + pmc_reset_ctrl |= (0x2UL << PMC_RESETCTRL_BODCORERESETENA_SECURE_SHIFT) | + (0x2UL << PMC_RESETCTRL_BODCORERESETENA_SECURE_DP_SHIFT); + + PMC->RESETCTRL = pmc_reset_ctrl; + + /* Enter low power mode */ + POWER_EnterLowPower(&lv_low_power_mode_cfg); + + /*** We'll reach this point ONLY and ONLY if the DEEPPOWERDOWN has not been taken (for instance because an RTC or + * OSTIMER interrupt is pending) ***/ + + /* Restore the configuration of the NMI Register */ + SYSCON->NMISRC |= cpu0_nmi_enable; + + /* Restore PMC RESETCTRL register */ + PMC->RESETCTRL = pmc_reset_ctrl; + + /* Restore the configuration of the CPU interrupt enable Registers (because they have been overwritten inside the + * low power API */ + NVIC->ISER[0] = cpu0_int_enable_0; + NVIC->ISER[1] = cpu0_int_enable_1; +} + +/** + * brief PMC Sleep function call + * return nothing + */ +void POWER_EnterSleep(void) +{ + uint32_t pmsk; + pmsk = __get_PRIMASK(); + __disable_irq(); + SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; + __WFI(); + __set_PRIMASK(pmsk); +} + +/** + * @brief Get Digital Core logic supply source to be used during Deep Sleep. + * @param [in] exclude_from_pd: COmpoenents NOT to be powered down during Deep Sleep + * @param [out] core_supply: 0 = LDO DEEPSLEEP will be used / 1 = DCDC will be used + * @param [out] dcdc_voltage: as defined by V_DCDC_* in fsl_power.h + + * @return Nothing + */ +static void lf_get_deepsleep_core_supply_cfg(uint32_t exclude_from_pd, uint32_t *dcdc_voltage) +{ + *dcdc_voltage = V_DCDC_0P950; /* Default value */ + + if (((exclude_from_pd & (uint32_t)kPDRUNCFG_PD_USB1_PHY) != 0) && + ((exclude_from_pd & (uint32_t)kPDRUNCFG_PD_LDOUSBHS) != 0)) + { + /* USB High Speed is required as wake-up source in Deep Sleep mode */ + PMC->MISCCTRL |= PMC_MISCCTRL_LOWPWR_FLASH_BUF_MASK; /* Force flash buffer in low power mode */ + *dcdc_voltage = V_DCDC_1P000; /* Set DCDC voltage to be 1.000 V (USB HS IP cannot work below 0.990 V) */ + } +} + +/** + * @brief + * @param + * @return + */ +static uint32_t lf_set_ldo_ao_ldo_mem_voltage(uint32_t p_lp_mode, uint32_t p_dcdc_voltage) +{ +#define FLASH_NMPA_LDO_AO_ADDRS (FLASH_NMPA_BASE + 0x0F4U) // N4M (0x3FCF4U) / N4S (0x9FCF4U) +#define FLASH_NMPA_LDO_AO_DSLP_TRIM_VALID_MASK (0x100U) +#define FLASH_NMPA_LDO_AO_DSLP_TRIM_MASK (0x3E00U) +#define FLASH_NMPA_LDO_AO_DSLP_TRIM_SHIFT (9U) +#define FLASH_NMPA_LDO_AO_PDWN_TRIM_VALID_MASK (0x10000U) +#define FLASH_NMPA_LDO_AO_PDWN_TRIM_MASK (0x3E0000U) +#define FLASH_NMPA_LDO_AO_PDWN_TRIM_SHIFT (17U) +#define FLASH_NMPA_LDO_AO_DPDW_TRIM_VALID_MASK (0x1000000U) +#define FLASH_NMPA_LDO_AO_DPDW_TRIM_MASK (0x3E000000U) +#define FLASH_NMPA_LDO_AO_DPDW_TRIM_SHIFT (25U) + + uint32_t ldo_ao_trim, voltage; + uint32_t lv_v_ldo_pmu, lv_v_ldo_pmu_boost; + + ldo_ao_trim = (*((volatile unsigned int *)(FLASH_NMPA_LDO_AO_ADDRS))); + + switch (p_lp_mode) + { + case LOWPOWER_CFG_LPMODE_DEEPSLEEP: + { + if ((ldo_ao_trim & FLASH_NMPA_LDO_AO_DSLP_TRIM_VALID_MASK) != 0UL) + { + /* Apply settings coming from Flash */ + lv_v_ldo_pmu = (ldo_ao_trim & FLASH_NMPA_LDO_AO_DSLP_TRIM_MASK) >> FLASH_NMPA_LDO_AO_DSLP_TRIM_SHIFT; + lv_v_ldo_pmu_boost = lv_v_ldo_pmu - 2UL; /* - 50 mV */ + } + else + { + /* Apply default settings */ + lv_v_ldo_pmu = (uint32_t)V_AO_0P900; + lv_v_ldo_pmu_boost = (uint32_t)V_AO_0P850; + } + } + break; + + case LOWPOWER_CFG_LPMODE_POWERDOWN: + { + if ((ldo_ao_trim & FLASH_NMPA_LDO_AO_PDWN_TRIM_VALID_MASK) != 0UL) + { + /* Apply settings coming from Flash */ + lv_v_ldo_pmu = (ldo_ao_trim & FLASH_NMPA_LDO_AO_PDWN_TRIM_MASK) >> FLASH_NMPA_LDO_AO_PDWN_TRIM_SHIFT; + lv_v_ldo_pmu_boost = lv_v_ldo_pmu - 2UL; /* - 50 mV */ + } + else + { + /* Apply default settings */ + lv_v_ldo_pmu = (uint32_t)V_AO_0P800; + lv_v_ldo_pmu_boost = (uint32_t)V_AO_0P750; + } + } + break; + + case LOWPOWER_CFG_LPMODE_DEEPPOWERDOWN: + { + if ((ldo_ao_trim & FLASH_NMPA_LDO_AO_DPDW_TRIM_VALID_MASK) != 0UL) + { + /* Apply settings coming from Flash */ + lv_v_ldo_pmu = (ldo_ao_trim & FLASH_NMPA_LDO_AO_DPDW_TRIM_MASK) >> FLASH_NMPA_LDO_AO_DPDW_TRIM_SHIFT; + lv_v_ldo_pmu_boost = lv_v_ldo_pmu - 2UL; /* - 50 mV */ + } + else + { + /* Apply default settings */ + lv_v_ldo_pmu = (uint32_t)V_AO_0P800; + lv_v_ldo_pmu_boost = (uint32_t)V_AO_0P750; + } + } + break; + + default: + /* Should never reach this point */ + lv_v_ldo_pmu = (uint32_t)V_AO_1P100; + lv_v_ldo_pmu_boost = (uint32_t)V_AO_1P050; + break; + } + + /* The Memories Voltage settings below are for voltage scaling */ + voltage = + (lv_v_ldo_pmu << LOWPOWER_VOLTAGE_LDO_PMU_INDEX) | /* */ + (lv_v_ldo_pmu_boost << LOWPOWER_VOLTAGE_LDO_PMU_BOOST_INDEX) | /* */ + ((uint32_t)V_AO_0P750 << LOWPOWER_VOLTAGE_LDO_MEM_INDEX) | /* Set to 0.75V (voltage Scaling) */ + ((uint32_t)V_AO_0P700 << LOWPOWER_VOLTAGE_LDO_MEM_BOOST_INDEX) | /* Set to 0.7V (voltage Scaling) */ + ((uint32_t)V_DEEPSLEEP_0P900 + << LOWPOWER_VOLTAGE_LDO_DEEP_SLEEP_INDEX) | /* Set to 0.90 V (Not used because LDO_DEEP_SLEEP is disabled)*/ + (p_dcdc_voltage << LOWPOWER_VOLTAGE_DCDC_INDEX) /* */ + ; + + return (voltage); +} + +/** + * @brief + * @param + * @return + */ +static uint32_t lf_wakeup_io_ctrl(uint32_t p_wakeup_io_ctrl) +{ + uint32_t wake_up_type; + uint32_t wakeup_io_ctrl_reg; + uint8_t use_external_pullupdown = 0; + + /* Configure Pull up & Pull down based on the required wake-up edge */ + CLOCK_EnableClock(kCLOCK_Iocon); + + wakeup_io_ctrl_reg = 0UL; + + /* Wake-up I/O 0 */ + wake_up_type = (p_wakeup_io_ctrl & 0x3UL) >> LOWPOWER_WAKEUPIOSRC_PIO0_INDEX; + wakeup_io_ctrl_reg |= (wake_up_type << LOWPOWER_WAKEUPIOSRC_PIO0_INDEX); + use_external_pullupdown = (uint8_t)((p_wakeup_io_ctrl & LOWPOWER_WAKEUPIO_PIO0_USEEXTERNALPULLUPDOWN_MASK) >> + LOWPOWER_WAKEUPIO_PIO0_USEEXTERNALPULLUPDOWN_INDEX); + + if (use_external_pullupdown == 0UL) + { + if ((wake_up_type == 1UL) || (wake_up_type == 3UL)) + { + /* Rising edge and both rising and falling edges */ + IOCON->PIO[1][1] = IOCON_PIO_DIGIMODE(1) | IOCON_PIO_MODE(1); /* Pull down */ + wakeup_io_ctrl_reg |= + ((uint32_t)LOWPOWER_WAKEUPIOSRC_IO_MODE_PULLDOWN << LOWPOWER_WAKEUPIOSRC_PIO0MODE_INDEX); + } + else + { + if (wake_up_type == 2UL) + { + /* Falling edge only */ + IOCON->PIO[1][1] = IOCON_PIO_DIGIMODE(1) | IOCON_PIO_MODE(2); /* Pull up */ + wakeup_io_ctrl_reg |= + ((uint32_t)LOWPOWER_WAKEUPIOSRC_IO_MODE_PULLUP << LOWPOWER_WAKEUPIOSRC_PIO0MODE_INDEX); + } + else + { + /* Wake-up I/O is disabled : set it as required by the user */ + if ((p_wakeup_io_ctrl & LOWPOWER_WAKEUPIO_PIO0_DISABLEPULLUPDOWN_MASK) != 0UL) + { + /* Wake-up I/O is configured as Plain Input */ + // @TODO not used p_wakeup_io_ctrl &= ~LOWPOWER_WAKEUPIO_PIO0_PULLUPDOWN_MASK; + wakeup_io_ctrl_reg |= + ((uint32_t)LOWPOWER_WAKEUPIOSRC_IO_MODE_PLAIN << LOWPOWER_WAKEUPIOSRC_PIO0MODE_INDEX); + } + else + { + /* Wake-up I/O is configured as pull-up or pull-down */ + // @TODO update for mask name + if ((p_wakeup_io_ctrl & LOWPOWER_WAKEUPIO_PIO0_PULLUPDOWN_MASK) != 0UL) + { + /* Wake-up I/O is configured as pull-up */ + wakeup_io_ctrl_reg |= + ((uint32_t)LOWPOWER_WAKEUPIOSRC_IO_MODE_PULLUP << LOWPOWER_WAKEUPIOSRC_PIO0MODE_INDEX); + } + else + { + /* Wake-up I/O is configured as pull-down */ + wakeup_io_ctrl_reg |= + ((uint32_t)LOWPOWER_WAKEUPIOSRC_IO_MODE_PULLDOWN << LOWPOWER_WAKEUPIOSRC_PIO0MODE_INDEX); + } + } + } + } + } + else + { + wakeup_io_ctrl_reg |= ((uint32_t)LOWPOWER_WAKEUPIOSRC_IO_MODE_PLAIN << LOWPOWER_WAKEUPIOSRC_PIO0MODE_INDEX); + } + + /* Wake-up I/O 1 */ + wake_up_type = (p_wakeup_io_ctrl & 0xCUL) >> LOWPOWER_WAKEUPIOSRC_PIO1_INDEX; + wakeup_io_ctrl_reg |= (wake_up_type << LOWPOWER_WAKEUPIOSRC_PIO1_INDEX); + use_external_pullupdown = (uint8_t)((p_wakeup_io_ctrl & LOWPOWER_WAKEUPIO_PIO1_USEEXTERNALPULLUPDOWN_MASK) >> + LOWPOWER_WAKEUPIO_PIO1_USEEXTERNALPULLUPDOWN_INDEX); + + if (use_external_pullupdown == 0UL) + { + if ((wake_up_type == 1UL) || (wake_up_type == 3UL)) + { + /* Rising edge and both rising and falling edges */ + IOCON->PIO[0][28] = IOCON_PIO_DIGIMODE(1) | IOCON_PIO_MODE(1); /* Pull down */ + wakeup_io_ctrl_reg |= + ((uint32_t)LOWPOWER_WAKEUPIOSRC_IO_MODE_PULLDOWN << LOWPOWER_WAKEUPIOSRC_PIO1MODE_INDEX); + } + else + { + if (wake_up_type == 2UL) + { + /* Falling edge only */ + IOCON->PIO[0][28] = IOCON_PIO_DIGIMODE(1) | IOCON_PIO_MODE(2); /* Pull up */ + wakeup_io_ctrl_reg |= + ((uint32_t)LOWPOWER_WAKEUPIOSRC_IO_MODE_PULLUP << LOWPOWER_WAKEUPIOSRC_PIO1MODE_INDEX); + } + else + { + /* Wake-up I/O is disabled : set it as required by the user */ + if ((p_wakeup_io_ctrl & LOWPOWER_WAKEUPIO_PIO1_DISABLEPULLUPDOWN_MASK) != 0UL) + { + /* Wake-up I/O is configured as Plain Input */ + // @TODO not used p_wakeup_io_ctrl &= ~LOWPOWER_WAKEUPIO_PIO1_PULLUPDOWN_MASK; + wakeup_io_ctrl_reg |= + ((uint32_t)LOWPOWER_WAKEUPIOSRC_IO_MODE_PLAIN << LOWPOWER_WAKEUPIOSRC_PIO1MODE_INDEX); + } + else + { + /* Wake-up I/O is configured as pull-up or pull-down */ + // @TODO update for mask name + if ((p_wakeup_io_ctrl & LOWPOWER_WAKEUPIO_PIO1_PULLUPDOWN_MASK) != 0UL) + { + /* Wake-up I/O is configured as pull-up */ + wakeup_io_ctrl_reg |= + ((uint32_t)LOWPOWER_WAKEUPIOSRC_IO_MODE_PULLUP << LOWPOWER_WAKEUPIOSRC_PIO1MODE_INDEX); + } + else + { + /* Wake-up I/O is configured as pull-down */ + wakeup_io_ctrl_reg |= + ((uint32_t)LOWPOWER_WAKEUPIOSRC_IO_MODE_PULLDOWN << LOWPOWER_WAKEUPIOSRC_PIO1MODE_INDEX); + } + } + } + } + } + else + { + wakeup_io_ctrl_reg |= ((uint32_t)LOWPOWER_WAKEUPIOSRC_IO_MODE_PLAIN << LOWPOWER_WAKEUPIOSRC_PIO1MODE_INDEX); + } + + /* Wake-up I/O 2 */ + wake_up_type = (p_wakeup_io_ctrl & 0x30UL) >> LOWPOWER_WAKEUPIOSRC_PIO2_INDEX; + wakeup_io_ctrl_reg |= (wake_up_type << LOWPOWER_WAKEUPIOSRC_PIO2_INDEX); + use_external_pullupdown = (uint8_t)((p_wakeup_io_ctrl & LOWPOWER_WAKEUPIO_PIO2_USEEXTERNALPULLUPDOWN_MASK) >> + LOWPOWER_WAKEUPIO_PIO2_USEEXTERNALPULLUPDOWN_INDEX); + + if (use_external_pullupdown == 0UL) + { + if ((wake_up_type == 1UL) || (wake_up_type == 3UL)) + { + /* Rising edge and both rising and falling edges */ + IOCON->PIO[1][18] = IOCON_PIO_DIGIMODE(1) | IOCON_PIO_MODE(1); /* Pull down */ + wakeup_io_ctrl_reg |= + ((uint32_t)LOWPOWER_WAKEUPIOSRC_IO_MODE_PULLDOWN << LOWPOWER_WAKEUPIOSRC_PIO2MODE_INDEX); + } + else + { + if (wake_up_type == 2UL) + { + /* Falling edge only */ + IOCON->PIO[1][18] = IOCON_PIO_DIGIMODE(1) | IOCON_PIO_MODE(2); /* Pull up */ + wakeup_io_ctrl_reg |= + ((uint32_t)LOWPOWER_WAKEUPIOSRC_IO_MODE_PULLUP << LOWPOWER_WAKEUPIOSRC_PIO2MODE_INDEX); + } + else + { + /* Wake-up I/O is disabled : set it as required by the user */ + if ((p_wakeup_io_ctrl & LOWPOWER_WAKEUPIO_PIO2_DISABLEPULLUPDOWN_MASK) != 0UL) + { + /* Wake-up I/O is configured as Plain Input */ + // @TODO not used p_wakeup_io_ctrl &= ~LOWPOWER_WAKEUPIO_PIO2_PULLUPDOWN_MASK; + wakeup_io_ctrl_reg |= + ((uint32_t)LOWPOWER_WAKEUPIOSRC_IO_MODE_PLAIN << LOWPOWER_WAKEUPIOSRC_PIO2MODE_INDEX); + } + else + { + /* Wake-up I/O is configured as pull-up or pull-down */ + // @TODO update for mask name + if ((p_wakeup_io_ctrl & LOWPOWER_WAKEUPIO_PIO2_PULLUPDOWN_MASK) != 0UL) + { + /* Wake-up I/O is configured as pull-up */ + wakeup_io_ctrl_reg |= + ((uint32_t)LOWPOWER_WAKEUPIOSRC_IO_MODE_PULLUP << LOWPOWER_WAKEUPIOSRC_PIO2MODE_INDEX); + } + else + { + /* Wake-up I/O is configured as pull-down */ + wakeup_io_ctrl_reg |= + ((uint32_t)LOWPOWER_WAKEUPIOSRC_IO_MODE_PULLDOWN << LOWPOWER_WAKEUPIOSRC_PIO2MODE_INDEX); + } + } + } + } + } + else + { + wakeup_io_ctrl_reg |= ((uint32_t)LOWPOWER_WAKEUPIOSRC_IO_MODE_PLAIN << LOWPOWER_WAKEUPIOSRC_PIO2MODE_INDEX); + } + + /* Wake-up I/O 3 */ + wake_up_type = (p_wakeup_io_ctrl & 0xC0UL) >> LOWPOWER_WAKEUPIOSRC_PIO3_INDEX; + wakeup_io_ctrl_reg |= (wake_up_type << LOWPOWER_WAKEUPIOSRC_PIO3_INDEX); + use_external_pullupdown = (uint8_t)((p_wakeup_io_ctrl & LOWPOWER_WAKEUPIO_PIO3_USEEXTERNALPULLUPDOWN_MASK) >> + LOWPOWER_WAKEUPIO_PIO3_USEEXTERNALPULLUPDOWN_INDEX); + + if (use_external_pullupdown == 0UL) + { + if ((wake_up_type == 1UL) || (wake_up_type == 3UL)) + { + /* Rising edge and both rising and falling edges */ + IOCON->PIO[1][30] = IOCON_PIO_DIGIMODE(1) | IOCON_PIO_MODE(1); /* Pull down */ + wakeup_io_ctrl_reg |= + ((uint32_t)LOWPOWER_WAKEUPIOSRC_IO_MODE_PULLDOWN << LOWPOWER_WAKEUPIOSRC_PIO3MODE_INDEX); + } + else + { + if (wake_up_type == 2UL) + { + /* Falling edge only */ + IOCON->PIO[1][30] = IOCON_PIO_DIGIMODE(1) | IOCON_PIO_MODE(2); /* Pull up */ + wakeup_io_ctrl_reg |= + ((uint32_t)LOWPOWER_WAKEUPIOSRC_IO_MODE_PULLUP << LOWPOWER_WAKEUPIOSRC_PIO3MODE_INDEX); + } + else + { + /* Wake-up I/O is disabled : set it as required by the user */ + if ((p_wakeup_io_ctrl & LOWPOWER_WAKEUPIO_PIO3_DISABLEPULLUPDOWN_MASK) != 0UL) + { + /* Wake-up I/O is configured as Plain Input */ + // @TODO not used p_wakeup_io_ctrl &= ~LOWPOWER_WAKEUPIO_PIO3_PULLUPDOWN_MASK; + wakeup_io_ctrl_reg |= + ((uint32_t)LOWPOWER_WAKEUPIOSRC_IO_MODE_PLAIN << LOWPOWER_WAKEUPIOSRC_PIO3MODE_INDEX); + } + else + { + /* Wake-up I/O is configured as pull-up or pull-down */ + // @TODO update for mask name + if ((p_wakeup_io_ctrl & LOWPOWER_WAKEUPIO_PIO3_PULLUPDOWN_MASK) != 0UL) + { + /* Wake-up I/O is configured as pull-up */ + wakeup_io_ctrl_reg |= + ((uint32_t)LOWPOWER_WAKEUPIOSRC_IO_MODE_PULLUP << LOWPOWER_WAKEUPIOSRC_PIO3MODE_INDEX); + } + else + { + /* Wake-up I/O is configured as pull-down */ + wakeup_io_ctrl_reg |= + ((uint32_t)LOWPOWER_WAKEUPIOSRC_IO_MODE_PULLDOWN << LOWPOWER_WAKEUPIOSRC_PIO3MODE_INDEX); + } + } + } + } + } + else + { + wakeup_io_ctrl_reg |= ((uint32_t)LOWPOWER_WAKEUPIOSRC_IO_MODE_PLAIN << LOWPOWER_WAKEUPIOSRC_PIO3MODE_INDEX); + } + + return (wakeup_io_ctrl_reg); +} + +/** + * @brief + * @param + * @return + */ +static uint8_t CLOCK_u8OscCapConvert(uint8_t u8OscCap, uint8_t u8CapBankDiscontinuity) +{ + /* Compensate for discontinuity in the capacitor banks */ + if (u8OscCap < 64U) + { + if (u8OscCap >= u8CapBankDiscontinuity) + { + u8OscCap -= u8CapBankDiscontinuity; + } + else + { + u8OscCap = 0U; + } + } + else + { + if (u8OscCap <= (127U - u8CapBankDiscontinuity)) + { + u8OscCap += u8CapBankDiscontinuity; + } + else + { + u8OscCap = 127U; + } + } + return u8OscCap; +} + +/** + * @brief Described in fsl_common.h + * @param + * @return + */ +static void lowpower_set_system_voltage(uint32_t system_voltage_mv) +{ + /* + * Set system voltage + */ + uint32_t lv_ldo_ao = (uint32_t)V_AO_1P100; /* */ + uint32_t lv_ldo_ao_boost = (uint32_t)V_AO_1P150; /* */ + uint32_t lv_dcdc = (uint32_t)V_DCDC_1P100; /* */ + + if (system_voltage_mv <= 950UL) + { + lv_dcdc = (uint32_t)V_DCDC_0P950; + lv_ldo_ao = (uint32_t)V_AO_0P960; + lv_ldo_ao_boost = (uint32_t)V_AO_1P010; + } + else if (system_voltage_mv <= 975UL) + { + lv_dcdc = (uint32_t)V_DCDC_0P975; + lv_ldo_ao = (uint32_t)V_AO_0P980; + lv_ldo_ao_boost = (uint32_t)V_AO_1P030; + } + else if (system_voltage_mv <= 1000UL) + { + lv_dcdc = (uint32_t)V_DCDC_1P000; + lv_ldo_ao = (uint32_t)V_AO_1P000; + lv_ldo_ao_boost = (uint32_t)V_AO_1P050; + } + else if (system_voltage_mv <= 1025UL) + { + lv_dcdc = (uint32_t)V_DCDC_1P025; + lv_ldo_ao = (uint32_t)V_AO_1P030; + lv_ldo_ao_boost = (uint32_t)V_AO_1P080; + } + else if (system_voltage_mv <= 1050UL) + { + lv_dcdc = (uint32_t)V_DCDC_1P050; + lv_ldo_ao = (uint32_t)V_AO_1P060; + lv_ldo_ao_boost = (uint32_t)V_AO_1P110; + } + else if (system_voltage_mv <= 1075UL) + { + lv_dcdc = (uint32_t)V_DCDC_1P075; + lv_ldo_ao = (uint32_t)V_AO_1P080; + lv_ldo_ao_boost = (uint32_t)V_AO_1P130; + } + else if (system_voltage_mv <= 1100UL) + { + lv_dcdc = (uint32_t)V_DCDC_1P100; + lv_ldo_ao = (uint32_t)V_AO_1P100; + lv_ldo_ao_boost = (uint32_t)V_AO_1P150; + } + else if (system_voltage_mv <= 1125UL) + { + lv_dcdc = (uint32_t)V_DCDC_1P125; + lv_ldo_ao = (uint32_t)V_AO_1P130; + lv_ldo_ao_boost = (uint32_t)V_AO_1P160; + } + else if (system_voltage_mv <= 1150UL) + { + lv_dcdc = (uint32_t)V_DCDC_1P150; + lv_ldo_ao = (uint32_t)V_AO_1P160; + lv_ldo_ao_boost = (uint32_t)V_AO_1P220; + } + else if (system_voltage_mv <= 1175UL) + { + lv_dcdc = (uint32_t)V_DCDC_1P175; + lv_ldo_ao = (uint32_t)V_AO_1P160; + lv_ldo_ao_boost = (uint32_t)V_AO_1P220; + } + else + { + lv_dcdc = (uint32_t)V_DCDC_1P200; + lv_ldo_ao = (uint32_t)V_AO_1P160; + lv_ldo_ao_boost = (uint32_t)V_AO_1P220; + } + + /* Set up LDO Always-On voltages */ + PMC->LDOPMU = (PMC->LDOPMU & (~PMC_LDOPMU_VADJ_MASK) & (~PMC_LDOPMU_VADJ_BOOST_MASK)) | PMC_LDOPMU_VADJ(lv_ldo_ao) | + PMC_LDOPMU_VADJ_BOOST(lv_ldo_ao_boost); + + /* Set up DCDC voltage */ + PMC->DCDC0 = (PMC->DCDC0 & (~PMC_DCDC0_VOUT_MASK)) | PMC_DCDC0_VOUT(lv_dcdc); +} + +/** + * @brief Described in fsl_common.h + * @param + * @return + */ +static void lowpower_set_dcdc_power_profile(lowpower_dcdc_power_profile_enum dcdc_power_profile) +{ +#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_ADDRS (FLASH_NMPA_BASE + 0xE0U) +#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_ADDRS (FLASH_NMPA_BASE + 0xE4U) +#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_ADDRS (FLASH_NMPA_BASE + 0xE8U) +#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_ADDRS (FLASH_NMPA_BASE + 0xECU) +#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_ADDRS (FLASH_NMPA_BASE + 0xD8U) +#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_ADDRS (FLASH_NMPA_BASE + 0xDCU) + + const uint32_t PMC_DCDC0_DEFAULT = 0x010C4E68; + const uint32_t PMC_DCDC1_DEFAULT = 0x01803A98; + + uint32_t dcdcTrimValue0; + uint32_t dcdcTrimValue1; + + switch (dcdc_power_profile) + { + case DCDC_POWER_PROFILE_LOW: + /* Low */ + dcdcTrimValue0 = (*((volatile unsigned int *)(FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_ADDRS))); + dcdcTrimValue1 = (*((volatile unsigned int *)(FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_ADDRS))); + + if (0UL != (dcdcTrimValue0 & 0x1UL)) + { + dcdcTrimValue0 = dcdcTrimValue0 >> 1; + + PMC->DCDC0 = dcdcTrimValue0; + PMC->DCDC1 = dcdcTrimValue1; +#if (defined(NIOBE_DEBUG_LEVEL) && (NIOBE_DEBUG_LEVEL >= 1)) + PRINTF( + "\nINFO : DCDC Power Profile set to " + "LOW" + "\n"); +#endif + } + break; + + case DCDC_POWER_PROFILE_MEDIUM: + /* Medium */ + dcdcTrimValue0 = (*((volatile unsigned int *)(FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_ADDRS))); + dcdcTrimValue1 = (*((volatile unsigned int *)(FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_ADDRS))); + + if (0UL != (dcdcTrimValue0 & 0x1UL)) + { + dcdcTrimValue0 = dcdcTrimValue0 >> 1; + + PMC->DCDC0 = dcdcTrimValue0; + PMC->DCDC1 = dcdcTrimValue1; +#if (defined(NIOBE_DEBUG_LEVEL) && (NIOBE_DEBUG_LEVEL >= 1)) + PRINTF( + "\nINFO : DCDC Power Profile set to " + "MEDIUM" + "\n"); +#endif + } + break; + + case DCDC_POWER_PROFILE_HIGH: + /* High */ + dcdcTrimValue0 = (*((volatile unsigned int *)(FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_ADDRS))); + dcdcTrimValue1 = (*((volatile unsigned int *)(FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_ADDRS))); + + if (0UL != (dcdcTrimValue0 & 0x1UL)) + { + dcdcTrimValue0 = dcdcTrimValue0 >> 1; + + PMC->DCDC0 = dcdcTrimValue0; + PMC->DCDC1 = dcdcTrimValue1; +#if (defined(NIOBE_DEBUG_LEVEL) && (NIOBE_DEBUG_LEVEL >= 1)) + PRINTF( + "\nINFO : DCDC Power Profile set to " + "HIGH" + "\n"); +#endif + } + break; + + default: + /* Low */ + PMC->DCDC0 = PMC_DCDC0_DEFAULT; + PMC->DCDC1 = PMC_DCDC1_DEFAULT; +#if (defined(NIOBE_DEBUG_LEVEL) && (NIOBE_DEBUG_LEVEL >= 1)) + PRINTF( + "\nINFO : DCDC Power Profile set to " + "LOW" + "\n"); +#endif + break; + } +} + +/** + * @brief + * @param + * @return + */ +static lowpower_process_corner_enum lowpower_get_part_process_corner(void) +{ +#define FLASH_NMPA_PVT_MONITOR_0_RINGO_ADDRS (FLASH_NMPA_BASE + 0x130U) +#define FLASH_NMPA_PVT_MONITOR_1_RINGO_ADDRS (FLASH_NMPA_BASE + 0x140U) + + lowpower_process_corner_enum part_process_corner; + uint32_t pvt_ringo_hz; + uint32_t pvt_ringo_0 = (*((volatile unsigned int *)(FLASH_NMPA_PVT_MONITOR_0_RINGO_ADDRS))); + uint32_t pvt_ringo_1 = (*((volatile unsigned int *)(FLASH_NMPA_PVT_MONITOR_1_RINGO_ADDRS))); + + /* + * Check that the PVT Monitors Trimmings in flash are valid. + */ + if (0UL != (pvt_ringo_0 & 0x1UL)) + { + /* PVT Trimmings in Flash are valid */ + pvt_ringo_0 = pvt_ringo_0 >> 1; + } + else + { + /* PVT Trimmings in Flash are NOT valid (average value assumed) */ + pvt_ringo_0 = PROCESS_NNN_AVG_HZ; + } + + if (0UL != (pvt_ringo_1 & 0x1UL)) + { + /* PVT Trimmings in Flash are valid */ + pvt_ringo_1 = pvt_ringo_1 >> 1; + } + else + { + /* PVT Trimmings in Flash are NOT valid (average value assumed) */ + pvt_ringo_1 = PROCESS_NNN_AVG_HZ; + } + + if (pvt_ringo_1 <= pvt_ringo_0) + { + pvt_ringo_hz = pvt_ringo_1; + } + else + { + pvt_ringo_hz = pvt_ringo_0; + } + + /* + * Determine the process corner based on the value of the Ring Oscillator frequency + */ + if (pvt_ringo_hz <= PROCESS_NNN_MIN_HZ) + { + /* SSS Process Corner */ + part_process_corner = PROCESS_CORNER_SSS; +#if (defined(NIOBE_DEBUG_LEVEL) && (NIOBE_DEBUG_LEVEL >= 1)) + PRINTF( + "\nINFO : Process Corner : " + "SSS" + "\n"); +#endif + } + else + { + if (pvt_ringo_hz <= PROCESS_NNN_MAX_HZ) + { + /* NNN Process Corner */ + part_process_corner = PROCESS_CORNER_NNN; +#if (defined(NIOBE_DEBUG_LEVEL) && (NIOBE_DEBUG_LEVEL >= 1)) + PRINTF( + "\nINFO : Process Corner : " + "NNN" + "\n"); +#endif + } + else + { + /* FFF Process Corner */ + part_process_corner = PROCESS_CORNER_FFF; +#if (defined(NIOBE_DEBUG_LEVEL) && (NIOBE_DEBUG_LEVEL >= 1)) + PRINTF( + "\nINFO : Process Corner : " + "FFF" + "\n"); +#endif + } + } + + return (part_process_corner); +} + +/** + * @brief Described in fsl_common.h + * @param + * @return + */ +static void lowpower_set_voltage_for_process(lowpower_dcdc_power_profile_enum dcdc_power_profile) +{ + /* Get Sample Process Corner */ + lowpower_process_corner_enum part_process_corner = lowpower_get_part_process_corner(); + + switch (part_process_corner) + { + case PROCESS_CORNER_SSS: + /* Slow Corner */ + { + switch (dcdc_power_profile) + { + case DCDC_POWER_PROFILE_MEDIUM: + /* Medium */ + lowpower_set_system_voltage(VOLTAGE_SSS_MED_MV); + break; + + case DCDC_POWER_PROFILE_HIGH: + /* High */ + lowpower_set_system_voltage(VOLTAGE_SSS_HIG_MV); + break; + + default: + /* DCDC_POWER_PROFILE_LOW */ + lowpower_set_system_voltage(VOLTAGE_SSS_LOW_MV); + break; + } // switch(dcdc_power_profile) + } + break; + + case PROCESS_CORNER_FFF: + /* Fast Corner */ + { + switch (dcdc_power_profile) + { + case DCDC_POWER_PROFILE_MEDIUM: + /* Medium */ + lowpower_set_system_voltage(VOLTAGE_FFF_MED_MV); + break; + + case DCDC_POWER_PROFILE_HIGH: + /* High */ + lowpower_set_system_voltage(VOLTAGE_FFF_HIG_MV); + break; + + default: + /* DCDC_POWER_PROFILE_LOW */ + lowpower_set_system_voltage(VOLTAGE_FFF_LOW_MV); + break; + } // switch(dcdc_power_profile) + } + break; + + default: + /* Nominal (NNN) and all others Process Corners : assume Nominal Corner */ + { + switch (dcdc_power_profile) + { + case DCDC_POWER_PROFILE_MEDIUM: + /* Medium */ + lowpower_set_system_voltage(VOLTAGE_NNN_MED_MV); + break; + + case DCDC_POWER_PROFILE_HIGH: + /* High */ + lowpower_set_system_voltage(VOLTAGE_NNN_HIG_MV); + break; + + default: + /* DCDC_POWER_PROFILE_LOW */ + lowpower_set_system_voltage(VOLTAGE_NNN_LOW_MV); + break; + } // switch(dcdc_power_profile) + break; + } + } // switch(part_process_corner) +} + +/** + * @brief Described in fsl_common.h + * @param + * @return + */ +void POWER_SetVoltageForFreq(uint32_t system_freq_hz) +{ + if (system_freq_hz <= DCDC_POWER_PROFILE_LOW_MAX_FREQ_HZ) + { + /* [0 Hz - DCDC_POWER_PROFILE_LOW_MAX_FREQ_HZ Hz] */ + lowpower_set_dcdc_power_profile(DCDC_POWER_PROFILE_LOW); /* DCDC VOUT = 1.05 V by default */ + lowpower_set_voltage_for_process(DCDC_POWER_PROFILE_LOW); + } + else + { + if (system_freq_hz <= DCDC_POWER_PROFILE_MEDIUM_MAX_FREQ_HZ) + { + /* ]DCDC_POWER_PROFILE_LOW_MAX_FREQ_HZ Hz - DCDC_POWER_PROFILE_MEDIUM_MAX_FREQ_HZ Hz] */ + lowpower_set_dcdc_power_profile(DCDC_POWER_PROFILE_MEDIUM); /* DCDC VOUT = 1.15 V by default */ + lowpower_set_voltage_for_process(DCDC_POWER_PROFILE_MEDIUM); + } + else + { + /* > DCDC_POWER_PROFILE_MEDIUM_MAX_FREQ_HZ Hz */ + lowpower_set_dcdc_power_profile(DCDC_POWER_PROFILE_HIGH); /* DCDC VOUT = 1.2 V by default */ + lowpower_set_voltage_for_process(DCDC_POWER_PROFILE_HIGH); + } + } +} + +void POWER_Xtal16mhzCapabankTrim(int32_t pi32_16MfXtalIecLoadpF_x100, + int32_t pi32_16MfXtalPPcbParCappF_x100, + int32_t pi32_16MfXtalNPcbParCappF_x100) +{ + uint32_t u32XOTrimValue; + uint8_t u8IECXinCapCal6pF, u8IECXinCapCal8pF, u8IECXoutCapCal6pF, u8IECXoutCapCal8pF, u8XOSlave; + int32_t iaXin_x4, ibXin, iaXout_x4, ibXout; + int32_t iXOCapInpF_x100, iXOCapOutpF_x100; + uint8_t u8XOCapInCtrl, u8XOCapOutCtrl; + uint32_t u32RegVal; + int32_t i32Tmp; + + /* Enable and set LDO, if not already done */ + POWER_SetXtal16mhzLdo(); + /* Get Cal values from Flash */ + u32XOTrimValue = GET_16MXO_TRIM(); + /* Check validity and apply */ + if ((0UL != (u32XOTrimValue & 1UL)) && (0UL != ((u32XOTrimValue >> 15UL) & 1UL))) + { + /* These fields are 7 bits, unsigned */ + u8IECXinCapCal6pF = (uint8_t)((u32XOTrimValue >> 1UL) & 0x7fUL); + u8IECXinCapCal8pF = (uint8_t)((u32XOTrimValue >> 8UL) & 0x7fUL); + u8IECXoutCapCal6pF = (uint8_t)((u32XOTrimValue >> 16UL) & 0x7fUL); + u8IECXoutCapCal8pF = (uint8_t)((u32XOTrimValue >> 23UL) & 0x7fUL); + /* This field is 1 bit */ + u8XOSlave = (uint8_t)((u32XOTrimValue >> 30UL) & 0x1UL); + /* Linear fit coefficients calculation */ + iaXin_x4 = (int)u8IECXinCapCal8pF - (int)u8IECXinCapCal6pF; + ibXin = (int)u8IECXinCapCal6pF - iaXin_x4 * 3; + iaXout_x4 = (int)u8IECXoutCapCal8pF - (int)u8IECXoutCapCal6pF; + ibXout = (int)u8IECXoutCapCal6pF - iaXout_x4 * 3; + } + else + { + iaXin_x4 = 20; // gain in LSB/pF + ibXin = -9; // offset in LSB + iaXout_x4 = 20; // gain in LSB/pF + ibXout = -13; // offset in LSB + u8XOSlave = 0; + } + /* In & out load cap calculation with derating */ + iXOCapInpF_x100 = 2 * pi32_16MfXtalIecLoadpF_x100 - pi32_16MfXtalNPcbParCappF_x100 + + 39 * ((int32_t)XO_SLAVE_EN - (int32_t)u8XOSlave) - 15; + iXOCapOutpF_x100 = 2 * pi32_16MfXtalIecLoadpF_x100 - pi32_16MfXtalPPcbParCappF_x100 - 21; + /* In & out XO_OSC_CAP_Code_CTRL calculation, with rounding */ + i32Tmp = ((iXOCapInpF_x100 * iaXin_x4 + ibXin * 400) + 200) / 400; + u8XOCapInCtrl = (uint8_t)i32Tmp; + i32Tmp = ((iXOCapOutpF_x100 * iaXout_x4 + ibXout * 400) + 200) / 400; + u8XOCapOutCtrl = (uint8_t)i32Tmp; + /* Read register and clear fields to be written */ + u32RegVal = ANACTRL->XO32M_CTRL; + u32RegVal &= ~(ANACTRL_XO32M_CTRL_OSC_CAP_IN_MASK | ANACTRL_XO32M_CTRL_OSC_CAP_OUT_MASK); + /* Configuration of 32 MHz XO output buffers */ +#if (XO_SLAVE_EN == 0) + u32RegVal &= ~(ANACTRL_XO32M_CTRL_SLAVE_MASK | ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_MASK); +#else + u32RegVal |= ANACTRL_XO32M_CTRL_SLAVE_MASK | ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_MASK; +#endif + /* XO_OSC_CAP_Code_CTRL to XO_OSC_CAP_Code conversion */ + u32RegVal |= (uint32_t)CLOCK_u8OscCapConvert(u8XOCapInCtrl, 13) << ANACTRL_XO32M_CTRL_OSC_CAP_IN_SHIFT; + u32RegVal |= (uint32_t)CLOCK_u8OscCapConvert(u8XOCapOutCtrl, 13) << ANACTRL_XO32M_CTRL_OSC_CAP_OUT_SHIFT; + /* Write back to register */ + ANACTRL->XO32M_CTRL = u32RegVal; +} + +void POWER_Xtal32khzCapabankTrim(int32_t pi32_32kfXtalIecLoadpF_x100, + int32_t pi32_32kfXtalPPcbParCappF_x100, + int32_t pi32_32kfXtalNPcbParCappF_x100) +{ + uint32_t u32XOTrimValue; + uint8_t u8IECXinCapCal6pF, u8IECXinCapCal8pF, u8IECXoutCapCal6pF, u8IECXoutCapCal8pF; + int32_t iaXin_x4, ibXin, iaXout_x4, ibXout; + int32_t iXOCapInpF_x100, iXOCapOutpF_x100; + uint8_t u8XOCapInCtrl, u8XOCapOutCtrl; + uint32_t u32RegVal; + int32_t i32Tmp; + /* Get Cal values from Flash */ + u32XOTrimValue = GET_32KXO_TRIM(); + /* check validity and apply */ + if ((0UL != (u32XOTrimValue & 1UL)) && (0UL != ((u32XOTrimValue >> 15UL) & 1UL))) + { + /* These fields are 7 bits, unsigned */ + u8IECXinCapCal6pF = (uint8_t)((u32XOTrimValue >> 1UL) & 0x7fUL); + u8IECXinCapCal8pF = (uint8_t)((u32XOTrimValue >> 8UL) & 0x7fUL); + u8IECXoutCapCal6pF = (uint8_t)((u32XOTrimValue >> 16UL) & 0x7fUL); + u8IECXoutCapCal8pF = (uint8_t)((u32XOTrimValue >> 23UL) & 0x7fUL); + /* Linear fit coefficients calculation */ + iaXin_x4 = (int)u8IECXinCapCal8pF - (int)u8IECXinCapCal6pF; + ibXin = (int)u8IECXinCapCal6pF - iaXin_x4 * 3; + iaXout_x4 = (int)u8IECXoutCapCal8pF - (int)u8IECXoutCapCal6pF; + ibXout = (int)u8IECXoutCapCal6pF - iaXout_x4 * 3; + } + else + { + iaXin_x4 = 16; // gain in LSB/pF + ibXin = 12; // offset in LSB + iaXout_x4 = 16; // gain in LSB/pF + ibXout = 11; // offset in LSB + } + + /* In & out load cap calculation with derating */ + iXOCapInpF_x100 = 2 * pi32_32kfXtalIecLoadpF_x100 - pi32_32kfXtalNPcbParCappF_x100 - 130; + iXOCapOutpF_x100 = 2 * pi32_32kfXtalIecLoadpF_x100 - pi32_32kfXtalPPcbParCappF_x100 - 41; + + /* In & out XO_OSC_CAP_Code_CTRL calculation, with rounding */ + i32Tmp = ((iXOCapInpF_x100 * iaXin_x4 + ibXin * 400) + 200) / 400; + u8XOCapInCtrl = (uint8_t)i32Tmp; + i32Tmp = ((iXOCapOutpF_x100 * iaXout_x4 + ibXout * 400) + 200) / 400; + u8XOCapOutCtrl = (uint8_t)i32Tmp; + + /* Read register and clear fields to be written */ + u32RegVal = PMC->XTAL32K; + u32RegVal &= ~(PMC_XTAL32K_CAPBANKIN_MASK | PMC_XTAL32K_CAPBANKOUT_MASK); + + /* XO_OSC_CAP_Code_CTRL to XO_OSC_CAP_Code conversion */ + u32RegVal |= (uint32_t)CLOCK_u8OscCapConvert(u8XOCapInCtrl, 23) << PMC_XTAL32K_CAPBANKIN_SHIFT; + u32RegVal |= (uint32_t)CLOCK_u8OscCapConvert(u8XOCapOutCtrl, 23) << PMC_XTAL32K_CAPBANKOUT_SHIFT; + + /* Write back to register */ + PMC->XTAL32K = u32RegVal; +} + +void POWER_SetXtal16mhzLdo(void) +{ + uint32_t temp; + const uint32_t u32Mask = + (ANACTRL_LDO_XO32M_VOUT_MASK | ANACTRL_LDO_XO32M_IBIAS_MASK | ANACTRL_LDO_XO32M_STABMODE_MASK); + + const uint32_t u32Value = + (ANACTRL_LDO_XO32M_VOUT(0x5) | ANACTRL_LDO_XO32M_IBIAS(0x2) | ANACTRL_LDO_XO32M_STABMODE(0x1)); + + /* Enable & set-up XTAL 32 MHz clock LDO */ + temp = ANACTRL->LDO_XO32M; + + if ((temp & u32Mask) != u32Value) + { + temp &= ~u32Mask; + + /* + * Enable the XTAL32M LDO + * Adjust the output voltage level, 0x5 for 1.1V + * Adjust the biasing current, 0x2 value + * Stability configuration, 0x1 default mode + */ + temp |= u32Value; + + ANACTRL->LDO_XO32M = temp; + + /* Delay for LDO to be up */ + // CLOCK_uDelay(20); + } + + /* Enable LDO XO32M */ + PMC->PDRUNCFGCLR0 = PMC_PDRUNCFG0_PDEN_LDOXO32M_MASK; +} + +/*! + * @brief set BOD VBAT level. + * + * @param level BOD detect level + * @param hyst BoD Hysteresis control + * @param enBodVbatReset VBAT brown out detect reset + */ +void POWER_SetBodVbatLevel(power_bod_vbat_level_t level, power_bod_hyst_t hyst, bool enBodVbatReset) +{ + uint32_t pmc_reset_ctrl; + /* BOD VBAT disable reset */ + pmc_reset_ctrl = + PMC->RESETCTRL & (~(PMC_RESETCTRL_BODVBATRESETENA_SECURE_MASK | PMC_RESETCTRL_BODVBATRESETENA_SECURE_DP_MASK)); + pmc_reset_ctrl |= (0x2UL << PMC_RESETCTRL_BODVBATRESETENA_SECURE_SHIFT) | + (0x2UL << PMC_RESETCTRL_BODVBATRESETENA_SECURE_DP_SHIFT); + + PMC->RESETCTRL = pmc_reset_ctrl; + + PMC->BODVBAT = (PMC->BODVBAT & (~(PMC_BODVBAT_TRIGLVL_MASK | PMC_BODVBAT_HYST_MASK))) | PMC_BODVBAT_TRIGLVL(level) | + PMC_BODVBAT_HYST(hyst); + + /* BOD VBAT enable reset */ + if ((uint32_t)enBodVbatReset == 1UL) + { + pmc_reset_ctrl &= (~(PMC_RESETCTRL_BODVBATRESETENA_SECURE_MASK | PMC_RESETCTRL_BODVBATRESETENA_SECURE_DP_MASK)); + pmc_reset_ctrl |= (0x1UL << PMC_RESETCTRL_BODVBATRESETENA_SECURE_SHIFT) | + (0x1UL << PMC_RESETCTRL_BODVBATRESETENA_SECURE_DP_SHIFT); + PMC->RESETCTRL = pmc_reset_ctrl; + } +} + +#if defined(PMC_BODCORE_TRIGLVL_MASK) +/*! + * @brief set BOD core level. + * + * @param level BOD detect level + * @param hyst BoD Hysteresis control + * @param enBodCoreReset core brown out detect reset + */ +void POWER_SetBodCoreLevel(power_bod_core_level_t level, power_bod_hyst_t hyst, bool enBodCoreReset) +{ + uint32_t pmc_reset_ctrl; + /* BOD CORE disable reset */ + pmc_reset_ctrl = + PMC->RESETCTRL & (~(PMC_RESETCTRL_BODCORERESETENA_SECURE_MASK | PMC_RESETCTRL_BODCORERESETENA_SECURE_DP_MASK)); + pmc_reset_ctrl |= + (0x2 << PMC_RESETCTRL_BODCORERESETENA_SECURE_SHIFT) | (0x2 << PMC_RESETCTRL_BODCORERESETENA_SECURE_DP_SHIFT); + + PMC->RESETCTRL = pmc_reset_ctrl; + + PMC->BODCORE = (PMC->BODCORE & (~(PMC_BODCORE_TRIGLVL_MASK | PMC_BODCORE_HYST_MASK))) | PMC_BODCORE_TRIGLVL(level) | + PMC_BODCORE_HYST(hyst); + + /* BOD CORE enable reset */ + if (enBodCoreReset == 1) + { + pmc_reset_ctrl &= (~(PMC_RESETCTRL_BODCORERESETENA_SECURE_MASK | PMC_RESETCTRL_BODCORERESETENA_SECURE_DP_MASK)); + pmc_reset_ctrl |= (0x1 << PMC_RESETCTRL_BODCORERESETENA_SECURE_SHIFT) | + (0x1 << PMC_RESETCTRL_BODCORERESETENA_SECURE_DP_SHIFT); + PMC->RESETCTRL = pmc_reset_ctrl; + } +} +#endif + +/** + * @brief Return some key information related to the device reset causes / wake-up sources, for all power modes. + * @param p_reset_cause : the device reset cause, according to the definition of power_device_reset_cause_t type. + * @param p_boot_mode : the device boot mode, according to the definition of power_device_boot_mode_t type. + * @param p_wakeupio_cause: the wake-up pin sources, according to the definition of register PMC->WAKEIOCAUSE[3:0]. + + * @return Nothing + * + * !!! IMPORTANT ERRATA - IMPORTANT ERRATA - IMPORTANT ERRATA !!! + * !!! valid ONLY for LPC55S69 (not for LPC55S16 and LPC55S06) !!! + * !!! when FALLING EDGE DETECTION is enabled on wake-up pins: !!! + * - 1. p_wakeupio_cause is NOT ACCURATE + * - 2. Spurious kRESET_CAUSE_DPDRESET_WAKEUPIO* event is reported when + * several wake-up sources are enabled during DEEP-POWER-DOWN + * (like enabling wake-up on RTC and Falling edge wake-up pins) + * + */ +void POWER_GetWakeUpCause(power_device_reset_cause_t *p_reset_cause, + power_device_boot_mode_t *p_boot_mode, + uint32_t *p_wakeupio_cause) +{ + uint32_t reset_cause_reg; + uint32_t boot_mode_reg; + +#if (defined(LPC55S06_SERIES) || defined(LPC55S04_SERIES) || defined(LPC5506_SERIES) || defined(LPC5504_SERIES) || \ + defined(LPC5502_SERIES) || defined(LPC55S16_SERIES) || defined(LPC55S14_SERIES) || defined(LPC5516_SERIES) || \ + defined(LPC5514_SERIES) || defined(LPC5512_SERIES)) + reset_cause_reg = (PMC->AOREG1) & 0x3FF0UL; +#else /* LPC55S69/28 */ + reset_cause_reg = (PMC->AOREG1) & 0x1FF0UL; +#endif + + /* + * Prioritize interrupts source with respect to their critical level + */ +#if (defined(LPC55S06_SERIES) || defined(LPC55S04_SERIES) || defined(LPC5506_SERIES) || defined(LPC5504_SERIES) || \ + defined(LPC5502_SERIES) || defined(LPC55S16_SERIES) || defined(LPC55S14_SERIES) || defined(LPC5516_SERIES) || \ + defined(LPC5514_SERIES) || defined(LPC5512_SERIES)) + if (0UL != (reset_cause_reg & PMC_AOREG1_CDOGRESET_MASK)) + { /* Code Watchdog Reset */ + *p_reset_cause = kRESET_CAUSE_CDOGRESET; + *p_boot_mode = kBOOT_MODE_POWER_UP; + *p_wakeupio_cause = 0; /* Device has not been waked-up by any wake-up pins */ + } + else +#endif + { + if (0UL != (reset_cause_reg & PMC_AOREG1_WDTRESET_MASK)) + { /* Watchdog Timer Reset */ + *p_reset_cause = kRESET_CAUSE_WDTRESET; + *p_boot_mode = kBOOT_MODE_POWER_UP; + *p_wakeupio_cause = 0; /* Device has not been waked-up by any wake-up pins */ + } + else + { + if (0UL != (reset_cause_reg & PMC_AOREG1_SYSTEMRESET_MASK)) + { /* ARM System Reset */ + *p_reset_cause = kRESET_CAUSE_ARMSYSTEMRESET; + *p_boot_mode = kBOOT_MODE_POWER_UP; + *p_wakeupio_cause = 0; /* Device has not been waked-up by any wake-up pins */ + } + else + { + boot_mode_reg = (PMC->STATUS & PMC_STATUS_BOOTMODE_MASK) >> PMC_STATUS_BOOTMODE_SHIFT; + + if (boot_mode_reg == 0UL) /* POWER-UP: Power On Reset, Pin reset, Brown Out Detectors, Software Reset */ + { + *p_boot_mode = kBOOT_MODE_POWER_UP; /* All non wake-up from a Low Power mode */ + *p_wakeupio_cause = 0; /* Device has not been waked-up by any wake-up pins */ + + /* + * Prioritise Reset causes, starting from the strongest (Power On Reset) + */ + if (0UL != (reset_cause_reg & PMC_AOREG1_POR_MASK)) + { /* Power On Reset */ + *p_reset_cause = kRESET_CAUSE_POR; + } + else + { + if (0UL != (reset_cause_reg & PMC_AOREG1_BODRESET_MASK)) + { /* Brown-out Detector reset (either BODVBAT or BODCORE) */ + *p_reset_cause = kRESET_CAUSE_BODRESET; + } + else + { + if (0UL != (reset_cause_reg & PMC_AOREG1_PADRESET_MASK)) + { /* Hardware Pin Reset */ + *p_reset_cause = kRESET_CAUSE_PADRESET; + } + else + { + if (0UL != (reset_cause_reg & PMC_AOREG1_SWRRESET_MASK)) + { /* Software triggered Reset */ + *p_reset_cause = kRESET_CAUSE_SWRRESET; + } + else + { /* Unknown Reset Cause */ + *p_reset_cause = kRESET_CAUSE_NOT_DETERMINISTIC; + } + } + } + } + +#if (defined(LPC55S06_SERIES) || defined(LPC55S04_SERIES) || defined(LPC5506_SERIES) || defined(LPC5504_SERIES) || \ + defined(LPC5502_SERIES) || defined(LPC55S16_SERIES) || defined(LPC55S14_SERIES) || defined(LPC5516_SERIES) || \ + defined(LPC5514_SERIES) || defined(LPC5512_SERIES)) + /* Transfer the control of the 4 wake-up pins to IOCON (instead of the Power Management Controller + */ + PMC->WAKEUPIOCTRL = PMC->WAKEUPIOCTRL & (~PMC_WAKEUPIOCTRL_WAKEUPIO_ENABLE_CTRL_MASK); +#endif + } + else /* DEEP-SLEEP, POWER-DOWN and DEEP-POWER-DOWN */ + { + /* + * 1- First, save wakeup_io_cause register ... + */ + *p_wakeupio_cause = PMC->WAKEIOCAUSE; + + if (boot_mode_reg == 3UL) /* DEEP-POWER-DOWN */ + { + *p_boot_mode = kBOOT_MODE_LP_DEEP_POWER_DOWN; + + switch (((reset_cause_reg >> PMC_AOREG1_DPDRESET_WAKEUPIO_SHIFT) & 0x7UL)) + { + case 1: + *p_reset_cause = kRESET_CAUSE_DPDRESET_WAKEUPIO; + break; + case 2: + *p_reset_cause = kRESET_CAUSE_DPDRESET_RTC; + break; + case 3: + *p_reset_cause = kRESET_CAUSE_DPDRESET_WAKEUPIO_RTC; + break; + case 4: + *p_reset_cause = kRESET_CAUSE_DPDRESET_OSTIMER; + break; + case 5: + *p_reset_cause = kRESET_CAUSE_DPDRESET_WAKEUPIO_OSTIMER; + break; + case 6: + *p_reset_cause = kRESET_CAUSE_DPDRESET_RTC_OSTIMER; + break; + case 7: + *p_reset_cause = kRESET_CAUSE_DPDRESET_WAKEUPIO_RTC_OSTIMER; + break; + default: + /* Unknown Reset Cause */ + *p_reset_cause = kRESET_CAUSE_NOT_DETERMINISTIC; + break; + } + +#if (defined(LPC55S06_SERIES) || defined(LPC55S04_SERIES) || defined(LPC5506_SERIES) || defined(LPC5504_SERIES) || \ + defined(LPC5502_SERIES) || defined(LPC55S16_SERIES) || defined(LPC55S14_SERIES) || defined(LPC5516_SERIES) || \ + defined(LPC5514_SERIES) || defined(LPC5512_SERIES)) + /* + * 2- Next, transfer the control of the 4 wake-up pins + * to IOCON (instead of the Power Management Controller) + */ + PMC->WAKEUPIOCTRL = PMC->WAKEUPIOCTRL & (~PMC_WAKEUPIOCTRL_WAKEUPIO_ENABLE_CTRL_MASK); +#endif + } + else /* DEEP-SLEEP and POWER-DOWN */ + { + *p_reset_cause = kRESET_CAUSE_NOT_RELEVANT; + + /* + * The control of the 4 wake-up pins is already in IOCON, + * so there is nothing special to do. + */ + + if (boot_mode_reg == 1UL) /* DEEP-SLEEP */ + { + *p_boot_mode = kBOOT_MODE_LP_DEEP_SLEEP; + } + else /* POWER-DOWN */ + { + *p_boot_mode = kBOOT_MODE_LP_POWER_DOWN; + + } /* if ( boot_mode_reg == 1 ) DEEP-SLEEP */ + + } /* if ( boot_mode == 3 ) DEEP-POWER-DOWN */ + + } /* if ( boot_mode == 0 ) POWER-UP */ + + } /* if ( reset_cause_reg & PMC_AOREG1_CDOGRESET_MASK ) */ + + } /* if ( reset_cause_reg & PMC_AOREG1_WDTRESET_MASK ) */ + + } /* if ( reset_cause_reg & PMC_AOREG1_SYSTEMRESET_MASK ) */ +} diff --git a/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_power.h b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_power.h new file mode 100644 index 0000000000..6b1c0f1fb4 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_power.h @@ -0,0 +1,598 @@ +/* + * Copyright 2017, NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_POWER_H_ +#define _FSL_POWER_H_ + +#include "fsl_common.h" +#include "fsl_device_registers.h" +#include + +/*! + * @addtogroup power + * @{ + */ +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief power driver version 1.0.0. */ +#define FSL_POWER_DRIVER_VERSION (MAKE_VERSION(1, 0, 0)) +/*@}*/ + +/* Power mode configuration API parameter */ +typedef enum _power_mode_config +{ + kPmu_Sleep = 0U, + kPmu_Deep_Sleep = 1U, + kPmu_PowerDown = 2U, + kPmu_Deep_PowerDown = 3U, +} power_mode_cfg_t; + +/** + * @brief Analog components power modes control during low power modes + */ +typedef enum pd_bits +{ + kPDRUNCFG_PD_DCDC = (1UL << 0), + kPDRUNCFG_PD_BIAS = (1UL << 1), + kPDRUNCFG_PD_BODCORE = (1UL << 2), + kPDRUNCFG_PD_BODVBAT = (1UL << 3), + kPDRUNCFG_PD_FRO1M = (1UL << 4), + kPDRUNCFG_PD_FRO192M = (1UL << 5), + kPDRUNCFG_PD_FRO32K = (1UL << 6), + kPDRUNCFG_PD_XTAL32K = (1UL << 7), + kPDRUNCFG_PD_XTAL32M = (1UL << 8), + kPDRUNCFG_PD_PLL0 = (1UL << 9), + kPDRUNCFG_PD_PLL1 = (1UL << 10), + kPDRUNCFG_PD_USB0_PHY = (1UL << 11), + kPDRUNCFG_PD_USB1_PHY = (1UL << 12), + kPDRUNCFG_PD_COMP = (1UL << 13), + kPDRUNCFG_PD_TEMPSENS = (1UL << 14), + kPDRUNCFG_PD_GPADC = (1UL << 15), + kPDRUNCFG_PD_LDOMEM = (1UL << 16), + kPDRUNCFG_PD_LDODEEPSLEEP = (1UL << 17), + kPDRUNCFG_PD_LDOUSBHS = (1UL << 18), + kPDRUNCFG_PD_LDOGPADC = (1UL << 19), + kPDRUNCFG_PD_LDOXO32M = (1UL << 20), + kPDRUNCFG_PD_LDOFLASHNV = (1UL << 21), + kPDRUNCFG_PD_RNG = (1UL << 22), + kPDRUNCFG_PD_PLL0_SSCG = (1UL << 23), + kPDRUNCFG_PD_ROM = (1UL << 24), + /* + This enum member has no practical meaning,it is used to avoid MISRA issue, + user should not trying to use it. + */ + kPDRUNCFG_ForceUnsigned = 0x80000000U, +} pd_bit_t; + +/** + * @brief BOD VBAT level + */ +typedef enum _power_bod_vbat_level +{ + kPOWER_BodVbatLevel1000mv = 0, /*!< Brown out detector VBAT level 1V */ + kPOWER_BodVbatLevel1100mv = 1, /*!< Brown out detector VBAT level 1.1V */ + kPOWER_BodVbatLevel1200mv = 2, /*!< Brown out detector VBAT level 1.2V */ + kPOWER_BodVbatLevel1300mv = 3, /*!< Brown out detector VBAT level 1.3V */ + kPOWER_BodVbatLevel1400mv = 4, /*!< Brown out detector VBAT level 1.4V */ + kPOWER_BodVbatLevel1500mv = 5, /*!< Brown out detector VBAT level 1.5V */ + kPOWER_BodVbatLevel1600mv = 6, /*!< Brown out detector VBAT level 1.6V */ + kPOWER_BodVbatLevel1650mv = 7, /*!< Brown out detector VBAT level 1.65V */ + kPOWER_BodVbatLevel1700mv = 8, /*!< Brown out detector VBAT level 1.7V */ + kPOWER_BodVbatLevel1750mv = 9, /*!< Brown out detector VBAT level 1.75V */ + kPOWER_BodVbatLevel1800mv = 10, /*!< Brown out detector VBAT level 1.8V */ + kPOWER_BodVbatLevel1900mv = 11, /*!< Brown out detector VBAT level 1.9V */ + kPOWER_BodVbatLevel2000mv = 12, /*!< Brown out detector VBAT level 2V */ + kPOWER_BodVbatLevel2100mv = 13, /*!< Brown out detector VBAT level 2.1V */ + kPOWER_BodVbatLevel2200mv = 14, /*!< Brown out detector VBAT level 2.2V */ + kPOWER_BodVbatLevel2300mv = 15, /*!< Brown out detector VBAT level 2.3V */ + kPOWER_BodVbatLevel2400mv = 16, /*!< Brown out detector VBAT level 2.4V */ + kPOWER_BodVbatLevel2500mv = 17, /*!< Brown out detector VBAT level 2.5V */ + kPOWER_BodVbatLevel2600mv = 18, /*!< Brown out detector VBAT level 2.6V */ + kPOWER_BodVbatLevel2700mv = 19, /*!< Brown out detector VBAT level 2.7V */ + kPOWER_BodVbatLevel2806mv = 20, /*!< Brown out detector VBAT level 2.806V */ + kPOWER_BodVbatLevel2900mv = 21, /*!< Brown out detector VBAT level 2.9V */ + kPOWER_BodVbatLevel3000mv = 22, /*!< Brown out detector VBAT level 3.0V */ + kPOWER_BodVbatLevel3100mv = 23, /*!< Brown out detector VBAT level 3.1V */ + kPOWER_BodVbatLevel3200mv = 24, /*!< Brown out detector VBAT level 3.2V */ + kPOWER_BodVbatLevel3300mv = 25, /*!< Brown out detector VBAT level 3.3V */ +} power_bod_vbat_level_t; + +/** + * @brief BOD Hysteresis control + */ +typedef enum _power_bod_hyst +{ + kPOWER_BodHystLevel25mv = 0U, /*!< BOD Hysteresis control level 25mv */ + kPOWER_BodHystLevel50mv = 1U, /*!< BOD Hysteresis control level 50mv */ + kPOWER_BodHystLevel75mv = 2U, /*!< BOD Hysteresis control level 75mv */ + kPOWER_BodHystLevel100mv = 3U, /*!< BOD Hysteresis control level 100mv */ +} power_bod_hyst_t; +/** + * @brief BOD core level + */ +typedef enum _power_bod_core_level +{ + kPOWER_BodCoreLevel600mv = 0, /*!< Brown out detector core level 600mV */ + kPOWER_BodCoreLevel650mv = 1, /*!< Brown out detector core level 650mV */ + kPOWER_BodCoreLevel700mv = 2, /*!< Brown out detector core level 700mV */ + kPOWER_BodCoreLevel750mv = 3, /*!< Brown out detector core level 750mV */ + kPOWER_BodCoreLevel800mv = 4, /*!< Brown out detector core level 800mV */ + kPOWER_BodCoreLevel850mv = 5, /*!< Brown out detector core level 850mV */ + kPOWER_BodCoreLevel900mv = 6, /*!< Brown out detector core level 900mV */ + kPOWER_BodCoreLevel950mv = 7, /*!< Brown out detector core level 950mV */ +} power_bod_core_level_t; + +/** + * @brief Device Reset Causes + */ +typedef enum _power_device_reset_cause +{ + kRESET_CAUSE_POR = 0UL, /*!< Power On Reset */ + kRESET_CAUSE_PADRESET = 1UL, /*!< Hardware Pin Reset */ + kRESET_CAUSE_BODRESET = 2UL, /*!< Brown-out Detector reset (either BODVBAT or BODCORE) */ + kRESET_CAUSE_ARMSYSTEMRESET = 3UL, /*!< ARM System Reset */ + kRESET_CAUSE_WDTRESET = 4UL, /*!< Watchdog Timer Reset */ + kRESET_CAUSE_SWRRESET = 5UL, /*!< Software Reset */ + kRESET_CAUSE_CDOGRESET = 6UL, /*!< Code Watchdog Reset */ + /* Reset causes in DEEP-POWER-DOWN low power mode */ + kRESET_CAUSE_DPDRESET_WAKEUPIO = 7UL, /*!< Any of the 4 wake-up pins */ + kRESET_CAUSE_DPDRESET_RTC = 8UL, /*!< Real Time Counter (RTC) */ + kRESET_CAUSE_DPDRESET_OSTIMER = 9UL, /*!< OS Event Timer (OSTIMER) */ + kRESET_CAUSE_DPDRESET_WAKEUPIO_RTC = 10UL, /*!< Any of the 4 wake-up pins and RTC (it is not possible to distinguish + which of these 2 events occured first) */ + kRESET_CAUSE_DPDRESET_WAKEUPIO_OSTIMER = 11UL, /*!< Any of the 4 wake-up pins and OSTIMER (it is not possible to + distinguish which of these 2 events occured first) */ + kRESET_CAUSE_DPDRESET_RTC_OSTIMER = 12UL, /*!< Real Time Counter or OS Event Timer (it is not possible to + distinguish which of these 2 events occured first) */ + kRESET_CAUSE_DPDRESET_WAKEUPIO_RTC_OSTIMER = 13UL, /*!< Any of the 4 wake-up pins (it is not possible to distinguish + which of these 3 events occured first) */ + /* Miscallenous */ + kRESET_CAUSE_NOT_RELEVANT = + 14UL, /*!< No reset cause (for example, this code is used when waking up from DEEP-SLEEP low power mode) */ + kRESET_CAUSE_NOT_DETERMINISTIC = 15UL, /*!< Unknown Reset Cause. Should be treated like "Hardware Pin Reset" from an + application point of view. */ +} power_device_reset_cause_t; + +/** + * @brief Device Boot Modes + */ +typedef enum _power_device_boot_mode +{ + kBOOT_MODE_POWER_UP = + 0UL, /*!< All non Low Power Mode wake up (Power On Reset, Pin Reset, BoD Reset, ARM System Reset ... ) */ + kBOOT_MODE_LP_DEEP_SLEEP = 1UL, /*!< Wake up from DEEP-SLEEP Low Power mode */ + kBOOT_MODE_LP_POWER_DOWN = 2UL, /*!< Wake up from POWER-DOWN Low Power mode */ + kBOOT_MODE_LP_DEEP_POWER_DOWN = 4UL, /*!< Wake up from DEEP-POWER-DOWN Low Power mode */ +} power_device_boot_mode_t; + +/** + * @brief SRAM instances retention control during low power modes + */ +#define LOWPOWER_SRAMRETCTRL_RETEN_RAMX0 \ + (1UL << 0) /*!< Enable SRAMX_0 retention when entering in Low power modes */ +#define LOWPOWER_SRAMRETCTRL_RETEN_RAMX1 \ + (1UL << 1) /*!< Enable SRAMX_1 retention when entering in Low power modes */ +#define LOWPOWER_SRAMRETCTRL_RETEN_RAMX2 \ + (1UL << 2) /*!< Enable SRAMX_2 retention when entering in Low power modes */ +#define LOWPOWER_SRAMRETCTRL_RETEN_RAMX3 \ + (1UL << 3) /*!< Enable SRAMX_3 retention when entering in Low power modes */ +#define LOWPOWER_SRAMRETCTRL_RETEN_RAM00 \ + (1UL << 4) /*!< Enable SRAM0_0 retention when entering in Low power modes */ +#define LOWPOWER_SRAMRETCTRL_RETEN_RAM10 \ + (1UL << 6) /*!< Enable SRAM1_0 retention when entering in Low power modes */ +#define LOWPOWER_SRAMRETCTRL_RETEN_RAM20 \ + (1UL << 7) /*!< Enable SRAM2_0 retention when entering in Low power modes */ +#define LOWPOWER_SRAMRETCTRL_RETEN_RAM_USB_HS \ + (1UL << 14) /*!< Enable SRAM USB HS retention when entering in Low power modes */ + +/** + * @brief Low Power Modes Wake up sources + */ +#define WAKEUP_SYS (1ULL << 0) /*!< [SLEEP, DEEP SLEEP ] */ /* WWDT0_IRQ and BOD_IRQ*/ +#define WAKEUP_SDMA0 (1ULL << 1) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_GPIO_GLOBALINT0 (1ULL << 2) /*!< [SLEEP, DEEP SLEEP, POWER DOWN ] */ +#define WAKEUP_GPIO_GLOBALINT1 (1ULL << 3) /*!< [SLEEP, DEEP SLEEP, POWER DOWN ] */ +#define WAKEUP_GPIO_INT0_0 (1ULL << 4) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_GPIO_INT0_1 (1ULL << 5) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_GPIO_INT0_2 (1ULL << 6) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_GPIO_INT0_3 (1ULL << 7) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_UTICK (1ULL << 8) /*!< [SLEEP, ] */ +#define WAKEUP_MRT (1ULL << 9) /*!< [SLEEP, ] */ +#define WAKEUP_CTIMER0 (1ULL << 10) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_CTIMER1 (1ULL << 11) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_SCT (1ULL << 12) /*!< [SLEEP, ] */ +#define WAKEUP_CTIMER3 (1ULL << 13) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_FLEXCOMM0 (1ULL << 14) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_FLEXCOMM1 (1ULL << 15) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_FLEXCOMM2 (1ULL << 16) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_FLEXCOMM3 (1ULL << 17) /*!< [SLEEP, DEEP SLEEP, POWER DOWN ] */ +#define WAKEUP_FLEXCOMM4 (1ULL << 18) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_FLEXCOMM5 (1ULL << 19) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_FLEXCOMM6 (1ULL << 20) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_FLEXCOMM7 (1ULL << 21) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_ADC (1ULL << 22) /*!< [SLEEP, ] */ +// reserved (1ULL << 23) +#define WAKEUP_ACMP (1ULL << 24) /*!< [SLEEP, DEEP SLEEP, POWER DOWN ] */ +// reserved (1ULL << 25) +// reserved (1ULL << 26) +#define WAKEUP_USB0_NEEDCLK (1ULL << 27) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_USB0 (1ULL << 28) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_RTC_LITE_ALARM_WAKEUP (1ULL << 29) /*!< [SLEEP, DEEP SLEEP, POWER DOWN, DEEP POWER DOWN] */ +// reserved (1ULL << 30) +// reserved (1ULL << 31) +#define WAKEUP_GPIO_INT0_4 (1ULL << 32) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_GPIO_INT0_5 (1ULL << 33) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_GPIO_INT0_6 (1ULL << 34) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_GPIO_INT0_7 (1ULL << 35) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_CTIMER2 (1ULL << 36) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_CTIMER4 (1ULL << 37) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_OS_EVENT_TIMER (1ULL << 38) /*!< [SLEEP, DEEP SLEEP, POWER DOWN, DEEP POWER DOWN] */ +// reserved (1ULL << 39) +// reserved (1ULL << 40) +// reserved (1ULL << 41) +// reserved (1ULL << 42) +#define CAN0_INT0 (1ULL << 43) /*!< [SLEEP, ] */ +#define CAN1_INT0 (1ULL << 44) /*!< [SLEEP, ] */ +// reserved (1ULL << 45) +// reserved (1ULL << 46) +#define WAKEUP_USB1 (1ULL << 47) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_USB1_NEEDCLK (1ULL << 48) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_SEC_HYPERVISOR_CALL (1ULL << 49) /*!< [SLEEP, ] */ +#define WAKEUP_SEC_GPIO_INT0_0 (1ULL << 50) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_SEC_GPIO_INT0_1 (1ULL << 51) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_PLU (1ULL << 52) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_SEC_VIO (1ULL << 53) +#define WAKEUP_SHA (1ULL << 54) /*!< [SLEEP, ] */ +#define WAKEUP_CASPER (1ULL << 55) /*!< [SLEEP, ] */ +#define WAKEUP_PUF (1ULL << 56) /*!< [SLEEP, ] */ +// reserved (1ULL << 57) +#define WAKEUP_SDMA1 (1ULL << 58) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_LSPI_HS (1ULL << 59) /*!< [SLEEP, DEEP SLEEP ] */ +//#define CDOG (1ULL << 60) !< [SLEEP, ] +// reserved (1ULL << 61) +// reserved (1ULL << 62) +#define WAKEUP_ALLWAKEUPIOS (1ULL << 63) /*!< [ , DEEP POWER DOWN] */ + +/** + * @brief Sleep Postpone + */ +#define LOWPOWER_HWWAKE_FORCED (1UL << 0) /*!< Force peripheral clocking to stay on during deep-sleep mode. */ +#define LOWPOWER_HWWAKE_PERIPHERALS \ + (1UL << 1) /*!< Wake for Flexcomms. Any Flexcomm FIFO reaching the level specified by its own TXLVL will cause \ + peripheral clocking to wake up temporarily while the related status is asserted */ +#define LOWPOWER_HWWAKE_SDMA0 \ + (1UL << 3) /*!< Wake for DMA0. DMA0 being busy will cause peripheral clocking to remain running until DMA \ + completes. Used in conjonction with LOWPOWER_HWWAKE_PERIPHERALS */ +#define LOWPOWER_HWWAKE_SDMA1 \ + (1UL << 5) /*!< Wake for DMA1. DMA0 being busy will cause peripheral clocking to remain running until DMA \ + completes. Used in conjonction with LOWPOWER_HWWAKE_PERIPHERALS */ +#define LOWPOWER_HWWAKE_ENABLE_FRO192M \ + (1UL << 31) /*!< Need to be set if FRO192M is disable - via PDCTRL0 - in Deep Sleep mode and any of \ + LOWPOWER_HWWAKE_PERIPHERALS, LOWPOWER_HWWAKE_SDMA0 or LOWPOWER_HWWAKE_SDMA1 is set */ + +#define LOWPOWER_CPURETCTRL_ENA_DISABLE 0 /*!< In POWER DOWN mode, CPU Retention is disabled */ +#define LOWPOWER_CPURETCTRL_ENA_ENABLE 1 /*!< In POWER DOWN mode, CPU Retention is enabled */ +/** + * @brief Wake up I/O sources + */ +#define LOWPOWER_WAKEUPIOSRC_PIO0_INDEX 0 /*!< Pin P1( 1) */ +#define LOWPOWER_WAKEUPIOSRC_PIO1_INDEX 2 /*!< Pin P0(28) */ +#define LOWPOWER_WAKEUPIOSRC_PIO2_INDEX 4 /*!< Pin P1(18) */ +#define LOWPOWER_WAKEUPIOSRC_PIO3_INDEX 6 /*!< Pin P1(30) */ + +#define LOWPOWER_WAKEUPIOSRC_DISABLE 0 /*!< Wake up is disable */ +#define LOWPOWER_WAKEUPIOSRC_RISING 1 /*!< Wake up on rising edge */ +#define LOWPOWER_WAKEUPIOSRC_FALLING 2 /*!< Wake up on falling edge */ +#define LOWPOWER_WAKEUPIOSRC_RISING_FALLING 3 /*!< Wake up on both rising or falling edges */ + +#define LOWPOWER_WAKEUPIOSRC_PIO0MODE_INDEX 12 /*!< Pin P1( 1) */ +#define LOWPOWER_WAKEUPIOSRC_PIO1MODE_INDEX 14 /*!< Pin P0(28) */ +#define LOWPOWER_WAKEUPIOSRC_PIO2MODE_INDEX 16 /*!< Pin P1(18) */ +#define LOWPOWER_WAKEUPIOSRC_PIO3MODE_INDEX 18 /*!< Pin P1(30) */ + +#define LOWPOWER_WAKEUPIOSRC_IO_MODE_PLAIN 0 /*!< Wake up Pad is plain input */ +#define LOWPOWER_WAKEUPIOSRC_IO_MODE_PULLDOWN 1 /*!< Wake up Pad is pull-down */ +#define LOWPOWER_WAKEUPIOSRC_IO_MODE_PULLUP 2 /*!< Wake up Pad is pull-up */ +#define LOWPOWER_WAKEUPIOSRC_IO_MODE_REPEATER 3 /*!< Wake up Pad is in repeater */ + +#define LOWPOWER_WAKEUPIO_PIO0_PULLUPDOWN_INDEX 8 /*!< Wake-up I/O 0 pull-up/down configuration index */ +#define LOWPOWER_WAKEUPIO_PIO1_PULLUPDOWN_INDEX 9 /*!< Wake-up I/O 1 pull-up/down configuration index */ +#define LOWPOWER_WAKEUPIO_PIO2_PULLUPDOWN_INDEX 10 /*!< Wake-up I/O 2 pull-up/down configuration index */ +#define LOWPOWER_WAKEUPIO_PIO3_PULLUPDOWN_INDEX 11 /*!< Wake-up I/O 3 pull-up/down configuration index */ + +#define LOWPOWER_WAKEUPIO_PIO0_PULLUPDOWN_MASK \ + (1UL << LOWPOWER_WAKEUPIO_PIO0_PULLUPDOWN_INDEX) /*!< Wake-up I/O 0 pull-up/down mask */ +#define LOWPOWER_WAKEUPIO_PIO1_PULLUPDOWN_MASK \ + (1UL << LOWPOWER_WAKEUPIO_PIO1_PULLUPDOWN_INDEX) /*!< Wake-up I/O 1 pull-up/down mask */ +#define LOWPOWER_WAKEUPIO_PIO2_PULLUPDOWN_MASK \ + (1UL << LOWPOWER_WAKEUPIO_PIO2_PULLUPDOWN_INDEX) /*!< Wake-up I/O 2 pull-up/down mask */ +#define LOWPOWER_WAKEUPIO_PIO3_PULLUPDOWN_MASK \ + (1UL << LOWPOWER_WAKEUPIO_PIO3_PULLUPDOWN_INDEX) /*!< Wake-up I/O 3 pull-up/down mask */ + +#define LOWPOWER_WAKEUPIO_PULLDOWN 0 /*!< Select pull-down */ +#define LOWPOWER_WAKEUPIO_PULLUP 1 /*!< Select pull-up */ + +#define LOWPOWER_WAKEUPIO_PIO0_DISABLEPULLUPDOWN_INDEX \ + 12 /*!< Wake-up I/O 0 pull-up/down disable/enable control index */ +#define LOWPOWER_WAKEUPIO_PIO1_DISABLEPULLUPDOWN_INDEX \ + 13 /*!< Wake-up I/O 1 pull-up/down disable/enable control index */ +#define LOWPOWER_WAKEUPIO_PIO2_DISABLEPULLUPDOWN_INDEX \ + 14 /*!< Wake-up I/O 2 pull-up/down disable/enable control index */ +#define LOWPOWER_WAKEUPIO_PIO3_DISABLEPULLUPDOWN_INDEX \ + 15 /*!< Wake-up I/O 3 pull-up/down disable/enable control index */ +#define LOWPOWER_WAKEUPIO_PIO0_DISABLEPULLUPDOWN_MASK \ + (1UL << LOWPOWER_WAKEUPIO_PIO0_DISABLEPULLUPDOWN_INDEX) /*!< Wake-up I/O 0 pull-up/down disable/enable mask */ +#define LOWPOWER_WAKEUPIO_PIO1_DISABLEPULLUPDOWN_MASK \ + (1UL << LOWPOWER_WAKEUPIO_PIO1_DISABLEPULLUPDOWN_INDEX) /*!< Wake-up I/O 1 pull-up/down disable/enable mask */ +#define LOWPOWER_WAKEUPIO_PIO2_DISABLEPULLUPDOWN_MASK \ + (1UL << LOWPOWER_WAKEUPIO_PIO2_DISABLEPULLUPDOWN_INDEX) /*!< Wake-up I/O 2 pull-up/down disable/enable mask */ +#define LOWPOWER_WAKEUPIO_PIO3_DISABLEPULLUPDOWN_MASK \ + (1UL << LOWPOWER_WAKEUPIO_PIO3_DISABLEPULLUPDOWN_INDEX) /*!< Wake-up I/O 3 pull-up/down disable/enable mask */ + +#define LOWPOWER_WAKEUPIO_PIO0_USEEXTERNALPULLUPDOWN_INDEX \ + (16) /*!< Wake-up I/O 0 use external pull-up/down disable/enable control index*/ +#define LOWPOWER_WAKEUPIO_PIO1_USEEXTERNALPULLUPDOWN_INDEX \ + (17) /*!< Wake-up I/O 1 use external pull-up/down disable/enable control index */ +#define LOWPOWER_WAKEUPIO_PIO2_USEEXTERNALPULLUPDOWN_INDEX \ + (18) /*!< Wake-up I/O 2 use external pull-up/down disable/enable control index */ +#define LOWPOWER_WAKEUPIO_PIO3_USEEXTERNALPULLUPDOWN_INDEX \ + (19) /*!< Wake-up I/O 3 use external pull-up/down disable/enable control index */ +#define LOWPOWER_WAKEUPIO_PIO0_USEEXTERNALPULLUPDOWN_MASK \ + (1UL << LOWPOWER_WAKEUPIO_PIO0_USEEXTERNALPULLUPDOWN_INDEX) /*!< Wake-up I/O 0 use external pull-up/down \ + disable/enable mask, 0: disable, 1: enable */ +#define LOWPOWER_WAKEUPIO_PIO1_USEEXTERNALPULLUPDOWN_MASK \ + (1UL << LOWPOWER_WAKEUPIO_PIO1_USEEXTERNALPULLUPDOWN_INDEX) /*!< Wake-up I/O 1 use external pull-up/down \ + disable/enable mask, 0: disable, 1: enable */ +#define LOWPOWER_WAKEUPIO_PIO2_USEEXTERNALPULLUPDOWN_MASK \ + (1UL << LOWPOWER_WAKEUPIO_PIO2_USEEXTERNALPULLUPDOWN_INDEX) /*!< Wake-up I/O 2 use external pull-up/down \ + disable/enable mask, 0: disable, 1: enable */ +#define LOWPOWER_WAKEUPIO_PIO3_USEEXTERNALPULLUPDOWN_MASK \ + (1UL << LOWPOWER_WAKEUPIO_PIO3_USEEXTERNALPULLUPDOWN_INDEX) /*!< Wake-up I/O 3 use external pull-up/down \ + disable/enable mask, 0: disable, 1: enable */ + +#ifdef __cplusplus +extern "C" { +#endif +/******************************************************************************* + * API + ******************************************************************************/ + +/*! + * @brief API to enable PDRUNCFG bit in the Syscon. Note that enabling the bit powers down the peripheral + * + * @param en peripheral for which to enable the PDRUNCFG bit + * @return none + */ +static inline void POWER_EnablePD(pd_bit_t en) +{ + /* PDRUNCFGSET */ + PMC->PDRUNCFGSET0 = (uint32_t)en; +} + +/*! + * @brief API to disable PDRUNCFG bit in the Syscon. Note that disabling the bit powers up the peripheral + * + * @param en peripheral for which to disable the PDRUNCFG bit + * @return none + */ +static inline void POWER_DisablePD(pd_bit_t en) +{ + /* PDRUNCFGCLR */ + PMC->PDRUNCFGCLR0 = (uint32_t)en; +} + +/*! + * @brief set BOD VBAT level. + * + * @param level BOD detect level + * @param hyst BoD Hysteresis control + * @param enBodVbatReset VBAT brown out detect reset + */ +void POWER_SetBodVbatLevel(power_bod_vbat_level_t level, power_bod_hyst_t hyst, bool enBodVbatReset); + +#if defined(PMC_BODCORE_TRIGLVL_MASK) +/*! + * @brief set BOD core level. + * + * @param level BOD detect level + * @param hyst BoD Hysteresis control + * @param enBodCoreReset core brown out detect reset + */ +void POWER_SetBodCoreLevel(power_bod_core_level_t level, power_bod_hyst_t hyst, bool enBodCoreReset); +#endif + +/*! + * @brief API to enable deep sleep bit in the ARM Core. + * + * @return none + */ +static inline void POWER_EnableDeepSleep(void) +{ + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; +} + +/*! + * @brief API to disable deep sleep bit in the ARM Core. + * + * @return none + */ +static inline void POWER_DisableDeepSleep(void) +{ + SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; +} + +/** + * @brief Shut off the Flash and execute the _WFI(), then power up the Flash after wake-up event + * This MUST BE EXECUTED outside the Flash: + * either from ROM or from SRAM. The rest could stay in Flash. But, for consistency, it is + * preferable to have all functions defined in this file implemented in ROM. + * + * @return Nothing + */ +void POWER_CycleCpuAndFlash(void); + +/** + * @brief Configures and enters in DEEP-SLEEP low power mode + * @param exclude_from_pd: + * @param sram_retention_ctrl: + * @param wakeup_interrupts: + * @param hardware_wake_ctrl: + + * @return Nothing + * + * !!! IMPORTANT NOTES : + 0 - CPU0 & System CLock frequency is switched to FRO12MHz and is NOT restored back by the API. + * 1 - CPU0 Interrupt Enable registers (NVIC->ISER) are modified by this function. They are restored back in + case of CPU retention or if POWERDOWN is not taken (for instance because an interrupt is pending). + * 2 - The Non Maskable Interrupt (NMI) is disabled and its configuration before calling this function will be + restored back if POWERDOWN is not taken (for instance because an RTC or OSTIMER interrupt is pending). + * 3 - The HARD FAULT handler should execute from SRAM. (The Hard fault handler should initiate a full chip + reset) reset) + */ +void POWER_EnterDeepSleep(uint32_t exclude_from_pd, + uint32_t sram_retention_ctrl, + uint64_t wakeup_interrupts, + uint32_t hardware_wake_ctrl); + +/** + * @brief Configures and enters in POWERDOWN low power mode + * @param exclude_from_pd: + * @param sram_retention_ctrl: + * @param wakeup_interrupts: + * @param cpu_retention_ctrl: 0 = CPU retention is disable / 1 = CPU retention is enabled, all other values are + RESERVED. + + * @return Nothing + * + * !!! IMPORTANT NOTES : + 0 - CPU0 & System CLock frequency is switched to FRO12MHz and is NOT restored back by the API. + * 1 - CPU0 Interrupt Enable registers (NVIC->ISER) are modified by this function. They are restored back in + case of CPU retention or if POWERDOWN is not taken (for instance because an interrupt is pending). + * 2 - The Non Maskable Interrupt (NMI) is disabled and its configuration before calling this function will be + restored back if POWERDOWN is not taken (for instance because an RTC or OSTIMER interrupt is pending). + * 3 - In case of CPU retention, it is the responsability of the user to make sure that SRAM instance + containing the stack used to call this function WILL BE preserved during low power (via parameter + "sram_retention_ctrl") + * 4 - The HARD FAULT handler should execute from SRAM. (The Hard fault handler should initiate a full chip + reset) reset) + */ + +void POWER_EnterPowerDown(uint32_t exclude_from_pd, + uint32_t sram_retention_ctrl, + uint64_t wakeup_interrupts, + uint32_t cpu_retention_ctrl); + +/** + * @brief Configures and enters in DEEPPOWERDOWN low power mode + * @param exclude_from_pd: + * @param sram_retention_ctrl: + * @param wakeup_interrupts: + * @param wakeup_io_ctrl: + + * @return Nothing + * + * !!! IMPORTANT NOTES : + 0 - CPU0 & System CLock frequency is switched to FRO12MHz and is NOT restored back by the API. + * 1 - CPU0 Interrupt Enable registers (NVIC->ISER) are modified by this function. They are restored back if + DEEPPOWERDOWN is not taken (for instance because an RTC or OSTIMER interrupt is pending). + * 2 - The Non Maskable Interrupt (NMI) is disabled and its configuration before calling this function will be + restored back if DEEPPOWERDOWN is not taken (for instance because an RTC or OSTIMER interrupt is pending). + * 3 - The HARD FAULT handler should execute from SRAM. (The Hard fault handler should initiate a full chip + reset) + */ +void POWER_EnterDeepPowerDown(uint32_t exclude_from_pd, + uint32_t sram_retention_ctrl, + uint64_t wakeup_interrupts, + uint32_t wakeup_io_ctrl); + +/** + * @brief Configures and enters in SLEEP low power mode + * + * @return Nothing + */ +void POWER_EnterSleep(void); + +/*! + * @brief Power Library API to choose normal regulation and set the voltage for the desired operating frequency. + * + * @param system_freq_hz - The desired frequency (in Hertz) at which the part would like to operate, + * note that the voltage and flash wait states should be set before changing frequency + * @return none + */ +void POWER_SetVoltageForFreq(uint32_t system_freq_hz); + +/** + * @brief Sets board-specific trim values for 16MHz XTAL + * @param pi32_16MfXtalIecLoadpF_x100 Load capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF becomes 120 + * @param pi32_16MfXtalPPcbParCappF_x100 PCB +ve parasitic capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF + * becomes 120 + * @param pi32_16MfXtalNPcbParCappF_x100 PCB -ve parasitic capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF + * becomes 120 + * @return none + * @note Following default Values can be used: + * pi32_32MfXtalIecLoadpF_x100 Load capacitance, pF x 100 : 600 + * pi32_32MfXtalPPcbParCappF_x100 PCB +ve parasitic capacitance, pF x 100 : 20 + * pi32_32MfXtalNPcbParCappF_x100 PCB -ve parasitic capacitance, pF x 100 : 40 + */ +extern void POWER_Xtal16mhzCapabankTrim(int32_t pi32_16MfXtalIecLoadpF_x100, + int32_t pi32_16MfXtalPPcbParCappF_x100, + int32_t pi32_16MfXtalNPcbParCappF_x100); +/** + * @brief Sets board-specific trim values for 32kHz XTAL + * @param pi32_32kfXtalIecLoadpF_x100 Load capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF becomes 120 + * @param pi32_32kfXtalPPcbParCappF_x100 PCB +ve parasitic capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF + becomes 120 + * @param pi32_32kfXtalNPcbParCappF_x100 PCB -ve parasitic capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF + becomes 120 + + * @return none + * @note Following default Values can be used: + * pi32_32kfXtalIecLoadpF_x100 Load capacitance, pF x 100 : 600 + * pi32_32kfXtalPPcbParCappF_x100 PCB +ve parasitic capacitance, pF x 100 : 40 + * pi32_32kfXtalNPcbParCappF_x100 PCB -ve parasitic capacitance, pF x 100 : 40 + */ +extern void POWER_Xtal32khzCapabankTrim(int32_t pi32_32kfXtalIecLoadpF_x100, + int32_t pi32_32kfXtalPPcbParCappF_x100, + int32_t pi32_32kfXtalNPcbParCappF_x100); +/** + * @brief Enables and sets LDO for 16MHz XTAL + * @return none + */ +extern void POWER_SetXtal16mhzLdo(void); + +/** + * @brief Return some key information related to the device reset causes / wake-up sources, for all power modes. + * @param p_reset_cause : the device reset cause, according to the definition of power_device_reset_cause_t type. + * @param p_boot_mode : the device boot mode, according to the definition of power_device_boot_mode_t type. + * @param p_wakeupio_cause: the wake-up pin sources, according to the definition of register PMC->WAKEIOCAUSE[3:0]. + + * @return Nothing + * + * !!! IMPORTANT ERRATA - IMPORTANT ERRATA - IMPORTANT ERRATA !!! + * !!! valid ONLY for LPC55S69 (not for LPC55S16 and LPC55S06) !!! + * !!! when FALLING EDGE DETECTION is enabled on wake-up pins: !!! + * - 1. p_wakeupio_cause is NOT ACCURATE + * - 2. Spurious kRESET_CAUSE_DPDRESET_WAKEUPIO* event is reported when + * several wake-up sources are enabled during DEEP-POWER-DOWN + * (like enabling wake-up on RTC and Falling edge wake-up pins) + * + */ +void POWER_GetWakeUpCause(power_device_reset_cause_t *p_reset_cause, + power_device_boot_mode_t *p_boot_mode, + uint32_t *p_wakeupio_cause); +#ifdef __cplusplus +} +#endif + +/** + * @} + */ + +#endif /* _FSL_POWER_H_ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_prince.c b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_prince.c new file mode 100644 index 0000000000..63e4c27852 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_prince.c @@ -0,0 +1,1096 @@ +/* + * Copyright 2018 - 2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_prince.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/* Component ID definition, used by tools. */ + +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.prince" +#endif + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +#if !defined(FSL_PRINCE_DRIVER_LPC55S3x) +static secure_bool_t PRINCE_CheckerAlgorithm(uint32_t address, + uint32_t length, + prince_flags_t flag, + flash_config_t *flash_context) +{ + uint32_t temp_base = 0, temp_sr = 0, region_index = 0, contiguous_start_index = 0, contiguous_end_index = 32; + secure_bool_t is_prince_region_contiguous = kSECURE_TRUE; + uint8_t prince_iv_code[FLASH_FFR_IV_CODE_SIZE] = {0}; + + if (address >= flash_context->ffrConfig.ffrBlockBase) + { + /* If it is not in flash region, return true to allow erase/write operation. */ + return kSECURE_TRUE; + } + + /* Iterate for all PRINCE regions */ + for (region_index = (uint32_t)kPRINCE_Region0; region_index <= (uint32_t)kPRINCE_Region2; region_index++) + { + contiguous_start_index = 0; + contiguous_end_index = 32; + switch (region_index) + { + case (uint32_t)kPRINCE_Region0: + temp_base = PRINCE->BASE_ADDR0; + temp_sr = PRINCE->SR_ENABLE0; + break; + + case (uint32_t)kPRINCE_Region1: + temp_base = PRINCE->BASE_ADDR1; + temp_sr = PRINCE->SR_ENABLE1; + break; + + case (uint32_t)kPRINCE_Region2: + temp_base = PRINCE->BASE_ADDR2; + temp_sr = PRINCE->SR_ENABLE2; + break; + + default: + /* All the cases have been listed above, the default clause should not be reached. */ + break; + } + + if (((address >= temp_base) && + ((address + length) < (temp_base + (FSL_PRINCE_DRIVER_SUBREGION_SIZE_IN_KB * 32U * 1024U)))) && + (temp_sr != 0U)) + { + /* Check if the mask is contiguous */ + secure_bool_t first_set_bit_found = kSECURE_FALSE; + secure_bool_t contiguous_end_found = kSECURE_FALSE; + for (uint32_t i = 0; i < 32U; i++) + { + if (0U != (temp_sr & (1UL << i))) + { + if (kSECURE_FALSE == first_set_bit_found) + { + first_set_bit_found = kSECURE_TRUE; + contiguous_start_index = i; + } + if (kSECURE_TRUE == contiguous_end_found) + { + is_prince_region_contiguous = kSECURE_FALSE; + break; + } + } + else + { + if ((kSECURE_TRUE == first_set_bit_found) && (kSECURE_FALSE == contiguous_end_found)) + { + contiguous_end_found = kSECURE_TRUE; + contiguous_end_index = i; + } + } + } + } + else + { + continue; /* No encryption enabled, continue with the next region checking. */ + } + + /* Check if the provided memory range covers all addresses defined in the SR mask */ + if ((kSECURE_TRUE == is_prince_region_contiguous) && + ((address <= (temp_base + (contiguous_start_index * FSL_PRINCE_DRIVER_SUBREGION_SIZE_IN_KB * 1024U)))) && + (((address + length) >= + (temp_base + (contiguous_end_index * FSL_PRINCE_DRIVER_SUBREGION_SIZE_IN_KB * 1024U))))) + { + /* In case of erase operation, invalidate the old PRINCE IV by regenerating the new one */ + if (kPRINCE_Flag_EraseCheck == flag) + { + /* Re-generate the PRINCE IV in case of erase operation */ + + /* Generate new IV code for the PRINCE region and store the new IV into the respective FFRs */ + if (kStatus_Success == + PRINCE_GenNewIV((prince_region_t)region_index, &prince_iv_code[0], true, flash_context)) + { + /* Store the new IV for the PRINCE region into PRINCE registers. */ + if (kStatus_Success == PRINCE_LoadIV((prince_region_t)region_index, &prince_iv_code[0])) + { + /* Encryption is enabled, all subregions are to be erased/written at once, IV successfully + * regenerated, return true to allow erase operation. */ + return kSECURE_TRUE; + } + } + /* Encryption is enabled, all subregions are to be erased/written at once but IV has not been correctly + * regenerated, return false to disable erase operation. */ + return kSECURE_FALSE; + } + + /* Encryption is enabled and all subregions are to be erased/written at once, return true to allow + * erase/write operation. */ + return kSECURE_TRUE; + } + /* The provided memory range does not cover all addresses defined in the SR mask. */ + else + { + /* Is the provided memory range outside the addresses defined by the SR mask? */ + if ((kSECURE_TRUE == is_prince_region_contiguous) && + ((((address + length) <= + (temp_base + (contiguous_start_index * FSL_PRINCE_DRIVER_SUBREGION_SIZE_IN_KB * 1024U)))) || + ((address >= (temp_base + (contiguous_end_index * FSL_PRINCE_DRIVER_SUBREGION_SIZE_IN_KB * 1024U)))))) + { + /* No encryption enabled for the provided memory range, true could be returned to allow erase/write + operation, but due to the same base address for all three prince regions on Niobe4Mini we should + continue with other regions (SR mask) checking. */ + continue; + } + else + { + /* Encryption is enabled but not all subregions are to be erased/written at once, return false to + * disable erase/write operation. */ + return kSECURE_FALSE; + } + } + } + return kSECURE_TRUE; +} +#endif /* !defined(FSL_PRINCE_DRIVER_LPC55S3x) */ + +#if !defined(FSL_PRINCE_DRIVER_LPC55S3x) +/*! + * @brief Generate new IV code. + * + * This function generates new IV code and stores it into the persistent memory. + * Ensure about 800 bytes free space on the stack when calling this routine with the store parameter set to true! + * + * @param region PRINCE region index. + * @param iv_code IV code pointer used for storing the newly generated 52 bytes long IV code. + * @param store flag to allow storing the newly generated IV code into the persistent memory (FFR). + * @param flash_context pointer to the flash driver context structure. + * + * @return kStatus_Success upon success + * @return kStatus_Fail otherwise, kStatus_Fail is also returned if the key code for the particular + * PRINCE region is not present in the keystore (though new IV code has been provided) + */ +status_t PRINCE_GenNewIV(prince_region_t region, uint8_t *iv_code, bool store, flash_config_t *flash_context) +{ + status_t status = kStatus_Fail; + uint8_t prince_iv_code[FLASH_FFR_IV_CODE_SIZE] = {0}; + uint8_t tempBuffer[FLASH_FFR_MAX_PAGE_SIZE] = {0}; + + /* Make sure PUF is started to allow key and IV code decryption and generation */ + if (true != PUF_IsGetKeyAllowed(PUF)) + { + return status; + } + + /* Generate new IV code for the PRINCE region */ + status = + PUF_SetIntrinsicKey(PUF, (puf_key_index_register_t)(uint32_t)((uint32_t)kPUF_KeyIndex_02 + (uint32_t)region), 8, + &prince_iv_code[0], FLASH_FFR_IV_CODE_SIZE); + if ((kStatus_Success == status) && (true == store)) + { + /* Store the new IV code for the PRINCE region into the respective FFRs. */ + /* Create a new version of "Customer Field Programmable" (CFP) page. */ + if ((int32_t)kStatus_FLASH_Success == + FFR_GetCustomerInfieldData(flash_context, (uint8_t *)tempBuffer, 0, FLASH_FFR_MAX_PAGE_SIZE)) + { + /* Set the IV code in the page */ + (void)memcpy(&tempBuffer[offsetof(cfpa_cfg_info_t, ivCodePrinceRegion) + + (((uint32_t)region * sizeof(cfpa_cfg_iv_code_t))) + 4U], + &prince_iv_code[0], FLASH_FFR_IV_CODE_SIZE); + + uint32_t *p32 = (uint32_t *)(uint32_t)tempBuffer; + uint32_t version = p32[1]; + if (version == 0xFFFFFFFFu) + { + return kStatus_Fail; + } + version++; + p32[1] = version; + + /* Program the page and enable firewall for "Customer field area" */ + if ((int32_t)kStatus_FLASH_Success == + FFR_InfieldPageWrite(flash_context, (uint8_t *)tempBuffer, FLASH_FFR_MAX_PAGE_SIZE)) + { + status = kStatus_Success; + } + else + { + status = kStatus_Fail; + } + } + } + if (status == kStatus_Success) + { + /* Pass the new IV code */ + (void)memcpy(iv_code, &prince_iv_code[0], FLASH_FFR_IV_CODE_SIZE); + } + + return status; +} +#endif /* !defined(FSL_PRINCE_DRIVER_LPC55S3x) */ + +#if !defined(FSL_PRINCE_DRIVER_LPC55S3x) +/*! + * @brief Load IV code. + * + * This function enables IV code loading into the PRINCE bus encryption engine. + * + * @param region PRINCE region index. + * @param iv_code IV code pointer used for passing the IV code. + * + * @return kStatus_Success upon success + * @return kStatus_Fail otherwise + */ +status_t PRINCE_LoadIV(prince_region_t region, uint8_t *iv_code) +{ + status_t status = kStatus_Fail; + uint32_t keyIndex = (0x0Fu & (uint32_t)iv_code[1]); + uint8_t prince_iv[8] = {0}; + + /* Make sure PUF is started to allow key and IV code decryption and generation */ + if (true != PUF_IsGetKeyAllowed(PUF)) + { + return kStatus_Fail; + } + + /* Check if region number matches the PUF index value */ + if (((uint32_t)kPUF_KeyIndex_02 + (uint32_t)region) == (uint32_t)keyIndex) + { + /* Decrypt the IV */ + if (kStatus_Success == PUF_GetKey(PUF, iv_code, FLASH_FFR_IV_CODE_SIZE, &prince_iv[0], 8)) + { + /* Store the new IV for the PRINCE region into PRINCE registers. */ + (void)PRINCE_SetRegionIV(PRINCE, (prince_region_t)region, prince_iv); + status = kStatus_Success; + } + } + + return status; +} +#endif /* !defined(FSL_PRINCE_DRIVER_LPC55S3x) */ + +#if !defined(FSL_PRINCE_DRIVER_LPC55S3x) +/*! + * @brief Allow encryption/decryption for specified address range. + * + * This function sets the encryption/decryption for specified address range. + * The SR mask value for the selected Prince region is calculated from provided + * start_address and length parameters. This calculated value is OR'ed with the + * actual SR mask value and stored into the PRINCE SR_ENABLE register and also + * into the persistent memory (FFR) to be used after the device reset. It is + * possible to define several nonadjacent encrypted areas within one Prince + * region when calling this function repeatedly. If the length parameter is set + * to 0, the SR mask value is set to 0 and thus the encryption/decryption for + * the whole selected Prince region is disabled. + * Ensure about 800 bytes free space on the stack when calling this routine! + * + * @param region PRINCE region index. + * @param start_address start address of the area to be encrypted/decrypted. + * @param length length of the area to be encrypted/decrypted. + * @param flash_context pointer to the flash driver context structure. + * @param regenerate_iv flag to allow IV code regenerating, storing into + * the persistent memory (FFR) and loading into the PRINCE engine + * + * @return kStatus_Success upon success + * @return kStatus_Fail otherwise + */ +status_t PRINCE_SetEncryptForAddressRange( + prince_region_t region, uint32_t start_address, uint32_t length, flash_config_t *flash_context, bool regenerate_iv) +{ + status_t status = kStatus_Fail; + uint32_t srEnableRegister = 0; + uint32_t alignedStartAddress; + uint32_t prince_base_addr_ffr_word = 0; + uint32_t end_address = start_address + length; + uint32_t prince_region_base_address = 0; + uint8_t tempBuffer[FLASH_FFR_MAX_PAGE_SIZE] = {0}; + + /* Check input parameters. */ + if (NULL == flash_context) + { + return kStatus_Fail; + } + + /* Check the address range, region borders crossing. */ +#if (defined(FSL_PRINCE_DRIVER_LPC55S0x)) || (defined(FSL_PRINCE_DRIVER_LPC55S1x)) || \ + (defined(FSL_PRINCE_DRIVER_LPC55S2x)) || (defined(FSL_PRINCE_DRIVER_LPC55S3x)) + if ((start_address > FSL_PRINCE_DRIVER_MAX_FLASH_ADDR) || + ((start_address < FSL_PRINCE_DRIVER_MAX_FLASH_ADDR) && (end_address > FSL_PRINCE_DRIVER_MAX_FLASH_ADDR))) + { + return kStatus_Fail; + } +#endif +#if (defined(FSL_PRINCE_DRIVER_LPC55S6x)) + if ((start_address > FSL_PRINCE_DRIVER_MAX_FLASH_ADDR) || + ((start_address < 0x40000U) && (end_address > 0x40000U)) || + ((start_address < 0x80000U) && (end_address > 0x80000U)) || + ((start_address < FSL_PRINCE_DRIVER_MAX_FLASH_ADDR) && (end_address > FSL_PRINCE_DRIVER_MAX_FLASH_ADDR))) + { + return kStatus_Fail; + } +#endif + + if (true == regenerate_iv) + { + uint8_t prince_iv_code[FLASH_FFR_IV_CODE_SIZE] = {0}; + + /* Generate new IV code for the PRINCE region and store the new IV into the respective FFRs */ + status = PRINCE_GenNewIV((prince_region_t)region, &prince_iv_code[0], true, flash_context); + if (kStatus_Success != status) + { + return kStatus_Fail; + } + + /* Store the new IV for the PRINCE region into PRINCE registers. */ + status = PRINCE_LoadIV((prince_region_t)region, &prince_iv_code[0]); + if (kStatus_Success != status) + { + return kStatus_Fail; + } + } + + alignedStartAddress = ALIGN_DOWN(start_address, (int32_t)FSL_PRINCE_DRIVER_SUBREGION_SIZE_IN_KB * 1024); + + uint32_t subregion = alignedStartAddress / (FSL_PRINCE_DRIVER_SUBREGION_SIZE_IN_KB * 1024U); + if (subregion < (32U)) + { + /* PRINCE_Region0 */ + prince_region_base_address = 0; + } + else if (subregion < (64U)) + { + /* PRINCE_Region1 */ + subregion = subregion - 32U; + prince_region_base_address = 0x40000; + } + else + { + /* PRINCE_Region2 */ + subregion = subregion - 64U; + prince_region_base_address = 0x80000; + } + + /* If length > 0 then srEnableRegister mask is set based on the alignedStartAddress and the length. + If the length is 0, srEnableRegister should be kept 0 (no subregion enabled). */ + if (length != 0U) + { + srEnableRegister = (1UL << subregion); + alignedStartAddress += (FSL_PRINCE_DRIVER_SUBREGION_SIZE_IN_KB * 1024U); + + while (alignedStartAddress < (start_address + length)) + { + subregion++; + srEnableRegister |= (1UL << subregion); + alignedStartAddress += (FSL_PRINCE_DRIVER_SUBREGION_SIZE_IN_KB * 1024U); + } + + uint32_t srEnableRegisterActual = 0; + (void)PRINCE_GetRegionSREnable(PRINCE, (prince_region_t)region, &srEnableRegisterActual); + srEnableRegister |= srEnableRegisterActual; + } + + /* Store BASE_ADDR into PRINCE register before storing the SR to avoid en/decryption triggering + from addresses being defined by current BASE_ADDR register content (could be 0 and the decryption + of actually executed code can be started causing the hardfault then). */ + status = PRINCE_SetRegionBaseAddress(PRINCE, (prince_region_t)region, prince_region_base_address); + if (kStatus_Success != status) + { + return status; + } + + /* Store SR into PRINCE register */ + status = PRINCE_SetRegionSREnable(PRINCE, (prince_region_t)region, srEnableRegister); + if (kStatus_Success != status) + { + return status; + } + + /* Store SR and BASE_ADDR into CMPA FFR */ + if (kStatus_Success == FFR_GetCustomerData(flash_context, (uint8_t *)&tempBuffer, 0, FLASH_FFR_MAX_PAGE_SIZE)) + { + /* Set the PRINCE_SR_X in the page */ + (void)memcpy((uint32_t *)(uintptr_t)&tempBuffer[offsetof(cmpa_cfg_info_t, princeSr) + + ((uint32_t)region * sizeof(uint32_t))], + &srEnableRegister, sizeof(uint32_t)); + /* Set the ADDRX_PRG in the page */ + (void)memcpy(&prince_base_addr_ffr_word, + (const uint32_t *)(uintptr_t)&tempBuffer[offsetof(cmpa_cfg_info_t, princeBaseAddr)], + sizeof(uint32_t)); + prince_base_addr_ffr_word &= + ~(((uint32_t)FLASH_CMPA_PRINCE_BASE_ADDR_ADDR0_PRG_MASK) << ((uint32_t)region * 4U)); + prince_base_addr_ffr_word |= (((prince_region_base_address >> PRINCE_BASE_ADDR0_ADDR_PRG_SHIFT) & + FLASH_CMPA_PRINCE_BASE_ADDR_ADDR0_PRG_MASK) + << ((uint32_t)region * 4U)); + (void)memcpy((uint32_t *)(uintptr_t)&tempBuffer[offsetof(cmpa_cfg_info_t, princeBaseAddr)], + &prince_base_addr_ffr_word, sizeof(uint32_t)); + + /* Program the CMPA page, set seal_part parameter to false (used during development to avoid sealing the + * part) + */ + status = FFR_CustFactoryPageWrite(flash_context, (uint8_t *)tempBuffer, false); + } + + return status; +} +#endif /* !defined(FSL_PRINCE_DRIVER_LPC55S3x) */ + +/*! + * @brief Gets the PRINCE Sub-Region Enable register. + * + * This function gets PRINCE SR_ENABLE register. + * + * @param base PRINCE peripheral address. + * @param region PRINCE region index. + * @param sr_enable Sub-Region Enable register pointer. + * + * @return kStatus_Success upon success + * @return kStatus_InvalidArgument + */ +status_t PRINCE_GetRegionSREnable(PRINCE_Type *base, prince_region_t region, uint32_t *sr_enable) +{ + status_t status = kStatus_Success; + + switch (region) + { + case kPRINCE_Region0: + *sr_enable = base->SR_ENABLE0; + break; + + case kPRINCE_Region1: + *sr_enable = base->SR_ENABLE1; + break; + + case kPRINCE_Region2: + *sr_enable = base->SR_ENABLE2; + break; + + default: + status = kStatus_InvalidArgument; + break; + } + + return status; +} + +/*! + * @brief Gets the PRINCE region base address register. + * + * This function gets PRINCE BASE_ADDR register. + * + * @param base PRINCE peripheral address. + * @param region PRINCE region index. + * @param region_base_addr Region base address pointer. + * + * @return kStatus_Success upon success + * @return kStatus_InvalidArgument + */ +status_t PRINCE_GetRegionBaseAddress(PRINCE_Type *base, prince_region_t region, uint32_t *region_base_addr) +{ + status_t status = kStatus_Success; + + switch (region) + { + case kPRINCE_Region0: + *region_base_addr = base->BASE_ADDR0; + break; + + case kPRINCE_Region1: + *region_base_addr = base->BASE_ADDR1; + break; + + case kPRINCE_Region2: + *region_base_addr = base->BASE_ADDR2; + break; + + default: + status = kStatus_InvalidArgument; + break; + } + + return status; +} + +/*! + * @brief Sets the PRINCE region IV. + * + * This function sets specified AES IV for the given region. + * + * @param base PRINCE peripheral address. + * @param region Selection of the PRINCE region to be configured. + * @param iv 64-bit AES IV in little-endian byte order. + * + * @return kStatus_Success upon success + * @return kStatus_InvalidArgument + */ +status_t PRINCE_SetRegionIV(PRINCE_Type *base, prince_region_t region, const uint8_t iv[8]) +{ + status_t status = kStatus_Fail; + volatile uint32_t *IVMsb_reg = NULL; + volatile uint32_t *IVLsb_reg = NULL; + + switch (region) + { + case kPRINCE_Region0: + IVLsb_reg = &base->IV_LSB0; + IVMsb_reg = &base->IV_MSB0; + break; + + case kPRINCE_Region1: + IVLsb_reg = &base->IV_LSB1; + IVMsb_reg = &base->IV_MSB1; + break; + + case kPRINCE_Region2: + IVLsb_reg = &base->IV_LSB2; + IVMsb_reg = &base->IV_MSB2; + break; + + default: + status = kStatus_InvalidArgument; + break; + } + + if (status != kStatus_InvalidArgument) + { + *IVLsb_reg = ((uint32_t *)(uintptr_t)iv)[0]; + *IVMsb_reg = ((uint32_t *)(uintptr_t)iv)[1]; + status = kStatus_Success; + } + + return status; +} + +/*! + * @brief Sets the PRINCE region base address. + * + * This function configures PRINCE region base address. + * + * @param base PRINCE peripheral address. + * @param region Selection of the PRINCE region to be configured. + * @param region_base_addr Base Address for region. + * + * @return kStatus_Success upon success + * @return kStatus_InvalidArgument + */ +status_t PRINCE_SetRegionBaseAddress(PRINCE_Type *base, prince_region_t region, uint32_t region_base_addr) +{ + status_t status = kStatus_Success; + + /* Check input parameters. */ +#if (defined(FSL_PRINCE_DRIVER_LPC55S0x)) || (defined(FSL_PRINCE_DRIVER_LPC55S1x)) || \ + (defined(FSL_PRINCE_DRIVER_LPC55S2x)) || (defined(FSL_PRINCE_DRIVER_LPC55S3x)) + if (region_base_addr > 0U) + { + return kStatus_InvalidArgument; + } +#endif +#if (defined(FSL_PRINCE_DRIVER_LPC55S6x)) + if (region_base_addr > 0x80000U) + { + return kStatus_InvalidArgument; + } +#endif + + switch (region) + { + case kPRINCE_Region0: + base->BASE_ADDR0 = region_base_addr; + break; + + case kPRINCE_Region1: + base->BASE_ADDR1 = region_base_addr; + break; + + case kPRINCE_Region2: + base->BASE_ADDR2 = region_base_addr; + break; + + default: + status = kStatus_InvalidArgument; + break; + } + + return status; +} + +/*! + * @brief Sets the PRINCE Sub-Region Enable register. + * + * This function configures PRINCE SR_ENABLE register. + * + * @param base PRINCE peripheral address. + * @param region Selection of the PRINCE region to be configured. + * @param sr_enable Sub-Region Enable register value. + * + * @return kStatus_Success upon success + * @return kStatus_InvalidArgument + */ +status_t PRINCE_SetRegionSREnable(PRINCE_Type *base, prince_region_t region, uint32_t sr_enable) +{ + status_t status = kStatus_Success; + + switch (region) + { + case kPRINCE_Region0: + base->SR_ENABLE0 = sr_enable; + break; + + case kPRINCE_Region1: + base->SR_ENABLE1 = sr_enable; + break; + + case kPRINCE_Region2: + base->SR_ENABLE2 = sr_enable; + break; + + default: + status = kStatus_InvalidArgument; + break; + } + + return status; +} + +#if !defined(FSL_PRINCE_DRIVER_LPC55S3x) +/*! + * @brief Erases the flash sectors encompassed by parameters passed into function. + * + * This function erases the appropriate number of flash sectors based on the + * desired start address and length. It deals with the flash erase function + * complenentary to the standard erase API of the IAP1 driver. This implementation + * additionally checks if the whole encrypted PRINCE subregions are erased at once + * to avoid secrets revealing. The checker implementation is limited to one contiguous + * PRINCE-controlled memory area. + * + * @param config The pointer to the flash driver context structure. + * @param start The start address of the desired flash memory to be erased. + * The start address needs to be prince-sburegion-aligned. + * @param lengthInBytes The length, given in bytes (not words or long-words) + * to be erased. Must be prince-sburegion-size-aligned. + * @param key The value used to validate all flash erase APIs. + * + * @return #kStatus_FLASH_Success API was executed successfully. + * @return #kStatus_FLASH_InvalidArgument An invalid argument is provided. + * @return #kStatus_FLASH_AlignmentError The parameter is not aligned with the specified baseline. + * @return #kStatus_FLASH_AddressError The address is out of range. + * @return #kStatus_FLASH_EraseKeyError The API erase key is invalid. + * @return #kStatus_FLASH_CommandFailure Run-time error during the command execution. + * @return #kStatus_FLASH_CommandNotSupported Flash API is not supported. + * @return #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution. + * @return #kStatus_FLASH_EncryptedRegionsEraseNotDoneAtOnce Encrypted flash subregions are not erased at once. + */ +status_t PRINCE_FlashEraseWithChecker(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, uint32_t key) +{ + /* Check input parameters. */ + if (NULL == config) + { + return kStatus_Fail; + } + /* Check that the whole encrypted region is erased at once. */ + if (kSECURE_TRUE != PRINCE_CheckerAlgorithm(start, lengthInBytes, kPRINCE_Flag_EraseCheck, config)) + { + return (int32_t)kStatus_FLASH_EncryptedRegionsEraseNotDoneAtOnce; + } + return FLASH_Erase(config, start, lengthInBytes, key); +} + +/*! + * @brief Programs flash with data at locations passed in through parameters. + * + * This function programs the flash memory with the desired data for a given + * flash area as determined by the start address and the length. It deals with the + * flash program function complenentary to the standard program API of the IAP1 driver. + * This implementation additionally checks if the whole PRINCE subregions are + * programmed at once to avoid secrets revealing. The checker implementation is limited + * to one contiguous PRINCE-controlled memory area. + * + * @param config The pointer to the flash driver context structure. + * @param start The start address of the desired flash memory to be programmed. Must be + * prince-sburegion-aligned. + * @param src A pointer to the source buffer of data that is to be programmed + * into the flash. + * @param lengthInBytes The length, given in bytes (not words or long-words), + * to be programmed. Must be prince-sburegion-size-aligned. + * + * @return #kStatus_FLASH_Success API was executed successfully. + * @return #kStatus_FLASH_InvalidArgument An invalid argument is provided. + * @return #kStatus_FLASH_AlignmentError Parameter is not aligned with the specified baseline. + * @return #kStatus_FLASH_AddressError Address is out of range. + * @return #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses. + * @return #kStatus_FLASH_CommandFailure Run-time error during the command execution. + * @return #kStatus_FLASH_CommandFailure Run-time error during the command execution. + * @return #kStatus_FLASH_CommandNotSupported Flash API is not supported. + * @return #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution. + * @return #kStatus_FLASH_SizeError Encrypted flash subregions are not programmed at once. + */ +status_t PRINCE_FlashProgramWithChecker(flash_config_t *config, uint32_t start, uint8_t *src, uint32_t lengthInBytes) +{ + /* Check input parameters. */ + if (NULL == config) + { + return kStatus_Fail; + } + /* Check that the whole encrypted subregions will be writen at once. */ + if (kSECURE_TRUE != PRINCE_CheckerAlgorithm(start, lengthInBytes, kPRINCE_Flag_WriteCheck, config)) + { + return (int32_t)kStatus_FLASH_SizeError; + } + return FLASH_Program(config, start, src, lengthInBytes); +} +#endif /* !defined(FSL_PRINCE_DRIVER_LPC55S3x) */ + +#if defined(FSL_PRINCE_DRIVER_LPC55S3x) +static status_t PRINCE_CSS_generate_random(uint8_t *output, size_t outputByteLen); +static status_t PRINCE_CSS_check_key(uint8_t keyIdx, mcuxClCss_KeyProp_t *pKeyProp); +static status_t PRINCE_CSS_gen_iv_key(void); +static status_t PRINCE_CSS_enable(void); +static status_t PRINCE_CSS_calculate_iv(uint32_t *IvReg); + +/*! + * @brief Configures PRINCE setting. + * + * This function does the initial PRINCE configuration via ROM IAP API call. + * PRINCE_SR_x configuration for each region configuration is stored into FFR (CMPA). + * PRINCE IV erase counters (MCTR_INT_IV_CTRx) in CFPA are updated accordingly. + * + * Note: This function is expected to be called once in the device lifetime, + * typically during the initial device provisioning, since it is programming the CMPA pages in PFR flash. + * + * @param coreCtx The pointer to the ROM API driver context structure. + * @param config The pointer to the PRINCE driver configuration structure. + * + * @retval #kStatus_Success + * @retval #kStatus_CommandUnsupported + * @retval #kStatus_InvalidArgument + * @retval #kStatus_FLASH_ModifyProtectedAreaDisallowed + * @retval #kStatusMemoryRangeInvalid + * @retval #kStatus_Fail + * @retval #kStatus_OutOfRange + * @retval #kStatus_SPI_BaudrateNotSupport + */ +status_t PRINCE_Configure(api_core_context_t *coreCtx, prince_prot_region_arg_t *config) +{ + /* Enable CSS and check keys */ + if (kStatus_Success != PRINCE_CSS_enable()) + { + return kStatus_Fail; + } + + return MEM_Config(coreCtx, (uint32_t *)config, kMemoryInternal); +} + +/*! + * @brief Configures PRINCE setting. + * + * This function is used to re-configure PRINCE IP based on configuration stored in FFR. + * This function also needs to be called after wake up from power-down mode to regenerate IV + * encryption key in CSS key store whose presence is necessary for correct PRINCE operation + * during erase and write operations to encrypted regions of internal flash memory + * (dependency for correct operation of MEM_Erase() and MEM_Write() after wake up from power-down mode). + * + * @param coreCtx The pointer to the ROM API driver context structure. + * + * @retval #kStatus_Success + * @retval #kStatus_Fail + */ +status_t PRINCE_Reconfigure(api_core_context_t *coreCtx) +{ + status_t status = kStatus_Fail; + uint64_t princeMask; + uint32_t IvReg[4] = {0}; + uint32_t ivEraseCounter[3]; + uint32_t srEnable[3]; + uint32_t uuid[4]; + flash_config_t flash_config; + uint32_t lockWord; + uint8_t lock[3]; + + /* Enable CSS and check keys */ + status = PRINCE_CSS_enable(); + if (kStatus_Success != status) + { + return kStatus_Fail; + } + + /* Set PRINCE mask value. */ + status = PRINCE_CSS_generate_random((uint8_t *)&princeMask, sizeof(princeMask)); + if (kStatus_Success != status) + { + return kStatus_Fail; + } + PRINCE_SetMask(PRINCE, princeMask); + + /* Clean up Flash driver structure and Init*/ + memset(&flash_config, 0, sizeof(flash_config_t)); + if (FLASH_Init(&flash_config) != kStatus_Success) + { + return kStatus_Fail; + } + + /* FFR Init */ + if (FFR_Init(&flash_config) != kStatus_Success) + { + return kStatus_Fail; + } + + /* Get UUID from FFR */ + status = FFR_GetUUID(&flash_config, (uint8_t *)uuid); + if (kStatus_Success != status) + { + return kStatus_Fail; + } + + /* Check version of CFPA scratch first */ + uint32_t cfpaScratchVer = 0u; + memcpy(&cfpaScratchVer, (void *)(CFPA_SCRATCH_VER), sizeof(uint32_t)); + + /* Get CFPA version using FFR ROM API */ + uint32_t cfpaVer = 0u; + if (kStatus_Success != + FFR_GetCustomerInfieldData(&flash_config, (uint8_t *)&cfpaVer, CFPA_VER_OFFSET, sizeof(uint32_t))) + { + status = kStatus_Fail; + return status; + } + + /* Compare the version of CFPA scratch and version of CFPA returned by ROM API */ + if (cfpaScratchVer > cfpaVer) + { + /* Get PRINCE_IV_CTRs from CFPA scratch */ + memcpy(&ivEraseCounter, (void *)CFPA_SCRATCH_IV, sizeof(uint32_t) * PRINCE_REGION_COUNT); + } + else + { + /* Get PRINCE_IV_CTRs IVs from CFPA ping/pong page */ + status = FFR_GetCustomerInfieldData(&flash_config, (uint8_t *)ivEraseCounter, CFPA_PRINCE_IV_OFFSET, + sizeof(uint32_t) * PRINCE_REGION_COUNT); + if (kStatus_Success != status) + { + return kStatus_Fail; + } + } + + /* Get PRINCE sub-region enable word from FFR */ + status = FFR_GetCustomerData(&flash_config, (uint8_t *)srEnable, CMPA_PRINCE_SR_OFFSET, + sizeof(uint32_t) * PRINCE_REGION_COUNT); + if (kStatus_Success != status) + { + return kStatus_Fail; + } + + /* Get PRINCE lock setting from FFR */ + status = FFR_GetCustomerData(&flash_config, (uint8_t *)&lockWord, CMPA_PRINCE_LOCK_OFFSET, sizeof(uint32_t)); + if (kStatus_Success != status) + { + return kStatus_Fail; + } + + lock[0] = (lockWord & PRINCE_BASE_ADDR_LOCK_REG0_MASK) >> PRINCE_BASE_ADDR_LOCK_REG0_SHIFT; + lock[1] = (lockWord & PRINCE_BASE_ADDR_LOCK_REG1_MASK) >> PRINCE_BASE_ADDR_LOCK_REG1_SHIFT; + lock[2] = (lockWord & PRINCE_BASE_ADDR_LOCK_REG2_MASK) >> PRINCE_BASE_ADDR_LOCK_REG2_SHIFT; + + /* Iterate for all internal PRINCE regions */ + for (prince_region_t region = kPRINCE_Region0; region <= kPRINCE_Region2; region++) + { + /* Set region base address. Should be always 0x0 on LPC55S36 */ + status = PRINCE_SetRegionBaseAddress(PRINCE, (prince_region_t)region, 0x0u); + if (kStatus_Success != status) + { + return kStatus_Fail; + } + + status = PRINCE_SetRegionSREnable(PRINCE, region, srEnable[region]); + if (kStatus_Success != status) + { + return kStatus_Fail; + } + + /* Prepare ivSeed for current region */ + IvReg[0] = uuid[0]; + IvReg[1] = uuid[1]; + IvReg[2] = uuid[2] ^ region; + IvReg[3] = ivEraseCounter[region]; + + /* Calculate IV as IvReg = AES_ECB_ENC(DUK_derived_key, {ctx_erase_counter, ctx_id}) */ + status = PRINCE_CSS_calculate_iv(IvReg); + if (status != kStatus_Success) + { + return kStatus_Fail; + } + + /* Load IV into PRINCE registers */ + status = PRINCE_SetRegionIV(PRINCE, (prince_region_t)region, (uint8_t *)IvReg); + if (status != kStatus_Success) + { + return kStatus_Fail; + } + + /* Lock region if required */ + if ((lock[region] == 0x1u) || (lock[region] == 0x2u) || (lock[region] == 0x3u)) + { + PRINCE_SetLock(PRINCE, (kPRINCE_Region0Lock << region)); + } + } + + /* Break the main loop in case that error occured during PRINCE configuration */ + if (status != kStatus_Success) + { + return kStatus_Fail; + } + + /* When ENC_ENABLE is set, reading from PRINCE-encrypted regions is disabled. */ + /* For LPC55S36, the ENC_ENABLE is self-cleared after programming memory. */ + PRINCE_EncryptDisable(PRINCE); + return status; +} + +static status_t PRINCE_CSS_generate_random(uint8_t *output, size_t outputByteLen) +{ + status_t status = kStatus_Fail; + + // PRNG needs to be initialized; this can be done by calling mcuxClCss_KeyDelete_Async + // (delete any key slot, can be empty) + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClCss_KeyDelete_Async(18)); + // mcuxClCss_KeyDelete_Async is a flow-protected function: Check the protection token and the return value + if ((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClCss_KeyDelete_Async) != token) || (MCUXCLCSS_STATUS_OK_WAIT != result)) + return kStatus_Fail; // Expect that no error occurred, meaning that the mcuxClCss_KeyDelete_Async operation was + // started. + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + // Wait for operation to finish + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClCss_WaitForOperation(MCUXCLCSS_ERROR_FLAGS_CLEAR)); + // mcuxClCss_WaitForOperation is a flow-protected function: Check the protection token and the return value + if ((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClCss_WaitForOperation) != token) || (MCUXCLCSS_STATUS_OK != result)) + return kStatus_Fail; // Expect that no error occurred, meaning that the mcuxClCss_WaitForOperation operation was + // started. + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClCss_Prng_GetRandom(output, outputByteLen)); + if ((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClCss_Prng_GetRandom) != token) || (MCUXCLCSS_STATUS_OK != result)) + return kStatus_Fail; + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + status = kStatus_Success; + return status; +} + +static status_t PRINCE_CSS_check_key(uint8_t keyIdx, mcuxClCss_KeyProp_t *pKeyProp) +{ + /* Check if CSS required keys are available in CSS keystore */ + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, + mcuxClCss_GetKeyProperties(keyIdx, pKeyProp)); // Get key propertis from the CSS. + // mcuxClCss_GetKeyProperties is a flow-protected function: Check the protection token and the return value + if ((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClCss_GetKeyProperties) != token) || (MCUXCLCSS_STATUS_OK != result)) + return kStatus_Fail; + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + return kStatus_Success; +} + +static status_t PRINCE_CSS_gen_iv_key(void) +{ + /* The NXP_DIE_MEM_IV_ENC_SK is not loaded and needs to be regenerated (power-down wakeup) */ + /* Set KDF mask and key properties for NXP_DIE_MEM_IV_ENC_SK */ + SYSCON->CSS_KDF_MASK = SYSCON_CSS_KDF_MASK; + static const uint32_t ddata2[3] = {0x62032504, 0x72f04280, 0x87a2bbae}; + mcuxClCss_KeyProp_t keyProp; + /* Set key properties in structure */ + keyProp.word.value = CSS_CSS_KS2_ks2_uaes_MASK | CSS_CSS_KS2_ks2_fgp_MASK | CSS_CSS_KS2_ks2_kact_MASK; + status_t status = kStatus_Fail; + + /* Generate the key using CKDF */ + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN( + result, token, + mcuxClCss_Ckdf_Sp800108_Async((mcuxClCss_KeyIndex_t)0, (mcuxClCss_KeyIndex_t)NXP_DIE_MEM_IV_ENC_SK, keyProp, + (uint8_t const *)ddata2)); + if ((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClCss_Ckdf_Sp800108_Async) != token) && (MCUXCLCSS_STATUS_OK != result)) + { + return kStatus_Fail; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + /* Wait for CKDF to finish */ + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClCss_WaitForOperation(MCUXCLCSS_ERROR_FLAGS_CLEAR)); + if ((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClCss_WaitForOperation) == token) && (MCUXCLCSS_STATUS_OK == result)) + { + status = kStatus_Success; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + return status; +} + +static status_t PRINCE_CSS_enable(void) +{ + mcuxClCss_KeyProp_t key_properties; + status_t status = kStatus_Fail; + + /* Enable CSS and related clocks */ + status = CSS_PowerDownWakeupInit(CSS); + if (status != kStatus_Success) + { + return kStatus_Fail; + } + + /* Check if MEM_ENC_SK key is available in CSS keystore */ + status = PRINCE_CSS_check_key(NXP_DIE_MEM_ENC_SK, &key_properties); + if (status != kStatus_Success || key_properties.bits.kactv != 1u) + { + return kStatus_Fail; + } + + /* Check if MEM_IV_ENC_SK key is available in CSS keystore */ + status = PRINCE_CSS_check_key(NXP_DIE_MEM_IV_ENC_SK, &key_properties); + if (status != kStatus_Success || key_properties.bits.kactv != 1u) + { + return PRINCE_CSS_gen_iv_key(); + } + + return kStatus_Success; +} + +static status_t PRINCE_CSS_calculate_iv(uint32_t *IvReg) +{ + mcuxClCss_CipherOption_t cipherOptions = {0}; + status_t status = kStatus_Fail; + + /* Configure CSS for AES ECB-128, using NXP_DIE_MEM_IV_ENC_SK key */ + cipherOptions.bits.cphmde = MCUXCLCSS_CIPHERPARAM_ALGORITHM_AES_ECB; + cipherOptions.bits.dcrpt = MCUXCLCSS_CIPHER_ENCRYPT; + cipherOptions.bits.extkey = MCUXCLCSS_CIPHER_INTERNAL_KEY; + + do + { + /* Calculate IV as IvReg = AES_ECB_ENC(NXP_DIE_MEM_IV_ENC_SK, ivSeed[127:0]) */ + /* ivSeed[127:0] = {UUID[96:0] ^ regionNumber[1:0], ivEraseCounter[31:0]} */ + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN( + result, token, + mcuxClCss_Cipher_Async(cipherOptions, (mcuxClCss_KeyIndex_t)NXP_DIE_MEM_IV_ENC_SK, NULL, + MCUXCLCSS_CIPHER_KEY_SIZE_AES_128, (uint8_t *)IvReg, MCUXCLCSS_CIPHER_BLOCK_SIZE_AES, + NULL, (uint8_t *)IvReg)); + if ((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClCss_Cipher_Async) != token) || (MCUXCLCSS_STATUS_OK_WAIT != result)) + break; + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN( + result, token, + mcuxClCss_WaitForOperation( + MCUXCLCSS_ERROR_FLAGS_CLEAR)); // Wait for the mcuxClCss_Enable_Async operation to complete. + // mcuxClCss_WaitForOperation is a flow-protected function: Check the protection token and the return value + if ((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClCss_WaitForOperation) == token) && (MCUXCLCSS_STATUS_OK == result)) + { + status = kStatus_Success; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + } while (0); + + return status; +} +#endif /* defined(FSL_PRINCE_DRIVER_LPC55S3x) */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_prince.h b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_prince.h new file mode 100644 index 0000000000..1d702ae499 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_prince.h @@ -0,0 +1,522 @@ +/* + * Copyright 2018 - 2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_PRINCE_H_ +#define _FSL_PRINCE_H_ + +#include "fsl_common.h" + +#include FFR_INCLUDE + +/*! + * @addtogroup prince + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief PRINCE driver version 2.5.0. + * + * Current version: 2.5.0 + * + * Change log: + * - Version 2.0.0 + * - Initial version. + * - Version 2.1.0 + * - Update for the A1 rev. of LPC55Sxx serie. + * - Version 2.2.0 + * - Add runtime checking of the A0 and A1 rev. of LPC55Sxx serie to support + * both silicone revisions. + * - Version 2.3.0 + * - Add support for LPC55S1x and LPC55S2x series + * - Version 2.3.0 + * - Fix MISRA-2012 issues. + * - Version 2.3.1 + * - Add support for LPC55S0x series + * - Version 2.3.2 + * - Fix documentation of enumeration. Extend PRINCE example. + * - Version 2.4.0 + * - Add support for LPC55S3x series + * - Version 2.5.0 + * - Add PRINCE_Config() and PRINCE_Reconfig() features. + */ +#define FSL_PRINCE_DRIVER_VERSION (MAKE_VERSION(2, 5, 0)) +/*@}*/ + +#if (defined(LPC55S04_SERIES) || defined(LPC55S06_SERIES)) +/* LPC55S0x series*/ +#define FSL_PRINCE_DRIVER_LPC55S0x +#include "fsl_puf.h" + +#elif (defined(LPC55S14_SERIES) || defined(LPC55S16_SERIES)) +/* LPC55S1x series*/ +#define FSL_PRINCE_DRIVER_LPC55S1x +#include "fsl_puf.h" + +#elif (defined(LPC55S26_SERIES) || defined(LPC55S28_SERIES)) +/* LPC55S2x series*/ +#define FSL_PRINCE_DRIVER_LPC55S2x +#include "fsl_puf.h" + +#elif (defined(LPC55S69_cm33_core0_SERIES) || defined(LPC55S69_cm33_core1_SERIES) || \ + defined(LPC55S66_cm33_core0_SERIES) || defined(LPC55S66_cm33_core1_SERIES)) +/* LPC55S6x series*/ +#define FSL_PRINCE_DRIVER_LPC55S6x +#include "fsl_puf.h" + +#elif (defined(LPC55S36_SERIES)) +/* LPC55S3x series*/ +#define FSL_PRINCE_DRIVER_LPC55S3x +#define PRINCE PRINCE0 +#include "fsl_mem_interface.h" +#include "fsl_css.h" // Power Down Wake-up Init +#include // Interface to the entire nxpClCss component +#include // Code flow protection +#else +#error "No valid CPU defined!" +#endif + +#define FSL_PRINCE_DRIVER_SUBREGION_SIZE_IN_KB (8U) +#define FSL_PRINCE_DRIVER_MAX_FLASH_ADDR \ + ((uint32_t)FSL_FEATURE_SYSCON_FLASH_SIZE_BYTES - (FSL_PRINCE_DRIVER_SUBREGION_SIZE_IN_KB * 2U * 1024U)) + +#if !defined(ALIGN_DOWN) +#define ALIGN_DOWN(x, a) ((x) & (uint32_t)(-((int32_t)(a)))) +#endif + +/*! @brief Secure status enumeration. */ +typedef enum _skboot_status +{ + kStatus_SKBOOT_Success = 0x5ac3c35au, /*!< PRINCE Success */ + kStatus_SKBOOT_Fail = 0xc35ac35au, /*!< PRINCE Fail */ + kStatus_SKBOOT_InvalidArgument = 0xc35a5ac3u, /*!< PRINCE Invalid argument */ + kStatus_SKBOOT_KeyStoreMarkerInvalid = 0xc3c35a5au, /*!< PRINCE Invalid marker */ +} skboot_status_t; + +/*! @brief Secure boolean enumeration. */ +typedef enum _secure_bool +{ + kSECURE_TRUE = 0xc33cc33cU, /*!< PRINCE true */ + kSECURE_FALSE = 0x5aa55aa5U, /*!< PRINCE false */ +} secure_bool_t; + +/*! @brief Prince region. */ +typedef enum _prince_region +{ + kPRINCE_Region0 = 0U, /*!< PRINCE region 0 */ + kPRINCE_Region1 = 1U, /*!< PRINCE region 1 */ + kPRINCE_Region2 = 2U, /*!< PRINCE region 2 */ +} prince_region_t; + +/*! @brief Prince lock. */ +typedef enum _prince_lock +{ + kPRINCE_Region0Lock = 1U, /*!< PRINCE region 0 lock */ + kPRINCE_Region1Lock = 2U, /*!< PRINCE region 1 lock */ + kPRINCE_Region2Lock = 4U, /*!< PRINCE region 2 lock */ + kPRINCE_MaskLock = 256U, /*!< PRINCE mask register lock */ +} prince_lock_t; + +/*! @brief Prince flag. */ +typedef enum _prince_flags +{ + kPRINCE_Flag_None = 0U, /*!< PRINCE Flag None */ + kPRINCE_Flag_EraseCheck = 1U, /*!< PRINCE Flag Erase check */ + kPRINCE_Flag_WriteCheck = 2U, /*!< PRINCE Flag Write check */ +} prince_flags_t; + +#if defined(FSL_PRINCE_DRIVER_LPC55S3x) +typedef struct +{ + uint32_t target_prince_region : 2; // 0/1/2 + uint32_t reserved : 22; + uint32_t tag : 8; // Fixed to 0x50 ('P') +} prince_prot_region_option_t; +typedef struct +{ + prince_prot_region_option_t option; + uint32_t start; + uint32_t length; +} prince_prot_region_arg_t; + +/*! @brief Prince fixed tag in prince_prot_region_option_t structure */ +#define PRINCE_TAG 0x50u +#define PRINCE_TAG_SHIFT 24u +/*! @brief Prince region count */ +#define PRINCE_REGION_COUNT 3u +/*! @brief Define for CSS key store indexes */ +#define NXP_DIE_MEM_ENC_SK 2u +#define NXP_DIE_MEM_IV_ENC_SK 4u +/*! @brief KDF mask and key properties for NXP_DIE_MEM_IV_ENC_SK (see SYSCON documentation)*/ +#define SYSCON_CSS_KDF_MASK 0x07000FCF +/*! @brief CFPA version and IV indexes (see Protected Flash Region table) */ +#define CFPA_VER_OFFSET 0x04 +#define CFPA_PRINCE_IV_OFFSET 0x14u +/*! @brief CMPA SR and lock indexes (see Protected Flash Region table) */ +#define CMPA_PRINCE_SR_OFFSET 0x24u +#define CMPA_PRINCE_LOCK_OFFSET 0x20u +/*! @brief CFPA scrach version and IV addresses (see Protected Flash Region table) */ +#define CFPA_SCRATCH_VER 0x3dc04 +#define CFPA_SCRATCH_IV 0x3dc14 +/*! @brief CMPA lock bit-field defines (see Protected Flash Region table) */ +#define PRINCE_BASE_ADDR_LOCK_REG0_SHIFT (16u) +#define PRINCE_BASE_ADDR_LOCK_REG0_MASK (0x3u << PRINCE_BASE_ADDR_LOCK_REG0_SHIFT) +#define PRINCE_BASE_ADDR_LOCK_REG1_SHIFT (18u) +#define PRINCE_BASE_ADDR_LOCK_REG1_MASK (0x3u << PRINCE_BASE_ADDR_LOCK_REG1_SHIFT) +#define PRINCE_BASE_ADDR_LOCK_REG2_SHIFT (20u) +#define PRINCE_BASE_ADDR_LOCK_REG2_MASK (0x3u << PRINCE_BASE_ADDR_LOCK_REG2_SHIFT) + +#endif /* defined(FSL_PRINCE_DRIVER_LPC55S3x) */ + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Enable data encryption. + * + * This function enables PRINCE on-the-fly data encryption. + * + * @param base PRINCE peripheral address. + */ +static inline void PRINCE_EncryptEnable(PRINCE_Type *base) +{ + base->ENC_ENABLE = 1u; +} + +/*! + * @brief Disable data encryption. + * + * This function disables PRINCE on-the-fly data encryption. + * + * @param base PRINCE peripheral address. + */ +static inline void PRINCE_EncryptDisable(PRINCE_Type *base) +{ + base->ENC_ENABLE = 0u; +} + +/*! + * @brief Is Enable data encryption. + * + * This function test if PRINCE on-the-fly data encryption is enabled. + * + * @param base PRINCE peripheral address. + * @return true if enabled, false if not + */ +static inline bool PRINCE_IsEncryptEnable(PRINCE_Type *base) +{ + return (base->ENC_ENABLE == 1u) ? true : false; +} + +/*! + * @brief Sets PRINCE data mask. + * + * This function sets the PRINCE mask that is used to mask decrypted data. + * + * @param base PRINCE peripheral address. + * @param mask 64-bit data mask value. + */ +static inline void PRINCE_SetMask(PRINCE_Type *base, uint64_t mask) +{ + base->MASK_LSB = (uint32_t)(mask & 0xffffffffu); + base->MASK_MSB = (uint32_t)(mask >> 32u); +} + +/*! + * @brief Locks access for specified region registers or data mask register. + * + * This function sets lock on specified region registers or mask register. + * + * @param base PRINCE peripheral address. + * @param lock registers to lock. This is a logical OR of members of the + * enumeration ::prince_lock_t + */ +static inline void PRINCE_SetLock(PRINCE_Type *base, uint32_t lock) +{ + base->LOCK = lock & 0x1ffu; +} + +#if !defined(FSL_PRINCE_DRIVER_LPC55S3x) +/*! + * @brief Generate new IV code. + * + * This function generates new IV code and stores it into the persistent memory. + * Ensure about 800 bytes free space on the stack when calling this routine with the store parameter set to true! + * + * @param region PRINCE region index. + * @param iv_code IV code pointer used for storing the newly generated 52 bytes long IV code. + * @param store flag to allow storing the newly generated IV code into the persistent memory (FFR). + * @param flash_context pointer to the flash driver context structure. + * + * @return kStatus_Success upon success + * @return kStatus_Fail otherwise, kStatus_Fail is also returned if the key code for the particular + * PRINCE region is not present in the keystore (though new IV code has been provided) + */ +status_t PRINCE_GenNewIV(prince_region_t region, uint8_t *iv_code, bool store, flash_config_t *flash_context); +#endif /* !defined(FSL_PRINCE_DRIVER_LPC55S3x) */ + +#if !defined(FSL_PRINCE_DRIVER_LPC55S3x) +/*! + * @brief Load IV code. + * + * This function enables IV code loading into the PRINCE bus encryption engine. + * + * @param region PRINCE region index. + * @param iv_code IV code pointer used for passing the IV code. + * + * @return kStatus_Success upon success + * @return kStatus_Fail otherwise + */ +status_t PRINCE_LoadIV(prince_region_t region, uint8_t *iv_code); +#endif /* !defined(FSL_PRINCE_DRIVER_LPC55S3x) */ + +#if !defined(FSL_PRINCE_DRIVER_LPC55S3x) +/*! + * @brief Allow encryption/decryption for specified address range. + * + * This function sets the encryption/decryption for specified address range. + * The SR mask value for the selected Prince region is calculated from provided + * start_address and length parameters. This calculated value is OR'ed with the + * actual SR mask value and stored into the PRINCE SR_ENABLE register and also + * into the persistent memory (FFR) to be used after the device reset. It is + * possible to define several nonadjacent encrypted areas within one Prince + * region when calling this function repeatedly. If the length parameter is set + * to 0, the SR mask value is set to 0 and thus the encryption/decryption for + * the whole selected Prince region is disabled. + * Ensure about 800 bytes free space on the stack when calling this routine! + * + * @param region PRINCE region index. + * @param start_address start address of the area to be encrypted/decrypted. + * @param length length of the area to be encrypted/decrypted. + * @param flash_context pointer to the flash driver context structure. + * @param regenerate_iv flag to allow IV code regenerating, storing into + * the persistent memory (FFR) and loading into the PRINCE engine + * + * @return kStatus_Success upon success + * @return kStatus_Fail otherwise + */ +status_t PRINCE_SetEncryptForAddressRange( + prince_region_t region, uint32_t start_address, uint32_t length, flash_config_t *flash_context, bool regenerate_iv); +#endif /* !defined(FSL_PRINCE_DRIVER_LPC55S3x) */ + +/*! + * @brief Gets the PRINCE Sub-Region Enable register. + * + * This function gets PRINCE SR_ENABLE register. + * + * @param base PRINCE peripheral address. + * @param region PRINCE region index. + * @param sr_enable Sub-Region Enable register pointer. + * + * @return kStatus_Success upon success + * @return kStatus_InvalidArgument + */ +status_t PRINCE_GetRegionSREnable(PRINCE_Type *base, prince_region_t region, uint32_t *sr_enable); + +/*! + * @brief Gets the PRINCE region base address register. + * + * This function gets PRINCE BASE_ADDR register. + * + * @param base PRINCE peripheral address. + * @param region PRINCE region index. + * @param region_base_addr Region base address pointer. + * + * @return kStatus_Success upon success + * @return kStatus_InvalidArgument + */ +status_t PRINCE_GetRegionBaseAddress(PRINCE_Type *base, prince_region_t region, uint32_t *region_base_addr); + +/*! + * @brief Sets the PRINCE region IV. + * + * This function sets specified AES IV for the given region. + * + * @param base PRINCE peripheral address. + * @param region Selection of the PRINCE region to be configured. + * @param iv 64-bit AES IV in little-endian byte order. + */ +status_t PRINCE_SetRegionIV(PRINCE_Type *base, prince_region_t region, const uint8_t iv[8]); + +/*! + * @brief Sets the PRINCE region base address. + * + * This function configures PRINCE region base address. + * + * @param base PRINCE peripheral address. + * @param region Selection of the PRINCE region to be configured. + * @param region_base_addr Base Address for region. + */ +status_t PRINCE_SetRegionBaseAddress(PRINCE_Type *base, prince_region_t region, uint32_t region_base_addr); + +/*! + * @brief Sets the PRINCE Sub-Region Enable register. + * + * This function configures PRINCE SR_ENABLE register. + * + * @param base PRINCE peripheral address. + * @param region Selection of the PRINCE region to be configured. + * @param sr_enable Sub-Region Enable register value. + */ +status_t PRINCE_SetRegionSREnable(PRINCE_Type *base, prince_region_t region, uint32_t sr_enable); + +#if !defined(FSL_PRINCE_DRIVER_LPC55S3x) +/*! + * @brief Erases the flash sectors encompassed by parameters passed into function. + * + * This function erases the appropriate number of flash sectors based on the + * desired start address and length. It deals with the flash erase function + * complenentary to the standard erase API of the IAP1 driver. This implementation + * additionally checks if the whole encrypted PRINCE subregions are erased at once + * to avoid secrets revealing. The checker implementation is limited to one contiguous + * PRINCE-controlled memory area. + * + * @param config The pointer to the flash driver context structure. + * @param start The start address of the desired flash memory to be erased. + * The start address needs to be prince-sburegion-aligned. + * @param lengthInBytes The length, given in bytes (not words or long-words) + * to be erased. Must be prince-sburegion-size-aligned. + * @param key The value used to validate all flash erase APIs. + * + * @return #kStatus_FLASH_Success API was executed successfully. + * @return #kStatus_FLASH_InvalidArgument An invalid argument is provided. + * @return #kStatus_FLASH_AlignmentError The parameter is not aligned with the specified baseline. + * @return #kStatus_FLASH_AddressError The address is out of range. + * @return #kStatus_FLASH_EraseKeyError The API erase key is invalid. + * @return #kStatus_FLASH_CommandFailure Run-time error during the command execution. + * @return #kStatus_FLASH_CommandNotSupported Flash API is not supported. + * @return #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution. + * @return #kStatus_FLASH_EncryptedRegionsEraseNotDoneAtOnce Encrypted flash subregions are not erased at once. + */ +status_t PRINCE_FlashEraseWithChecker(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, uint32_t key); +#endif /* !defined(FSL_PRINCE_DRIVER_LPC55S3x) */ + +#if !defined(FSL_PRINCE_DRIVER_LPC55S3x) +/*! + * @brief Programs flash with data at locations passed in through parameters. + * + * This function programs the flash memory with the desired data for a given + * flash area as determined by the start address and the length. It deals with the + * flash program function complenentary to the standard program API of the IAP1 driver. + * This implementation additionally checks if the whole PRINCE subregions are + * programmed at once to avoid secrets revealing. The checker implementation is limited + * to one contiguous PRINCE-controlled memory area. + * + * @param config The pointer to the flash driver context structure. + * @param start The start address of the desired flash memory to be programmed. Must be + * prince-sburegion-aligned. + * @param src A pointer to the source buffer of data that is to be programmed + * into the flash. + * @param lengthInBytes The length, given in bytes (not words or long-words), + * to be programmed. Must be prince-sburegion-size-aligned. + * + * @return #kStatus_FLASH_Success API was executed successfully. + * @return #kStatus_FLASH_InvalidArgument An invalid argument is provided. + * @return #kStatus_FLASH_AlignmentError Parameter is not aligned with the specified baseline. + * @return #kStatus_FLASH_AddressError Address is out of range. + * @return #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses. + * @return #kStatus_FLASH_CommandFailure Run-time error during the command execution. + * @return #kStatus_FLASH_CommandFailure Run-time error during the command execution. + * @return #kStatus_FLASH_CommandNotSupported Flash API is not supported. + * @return #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution. + * @return #kStatus_FLASH_SizeError Encrypted flash subregions are not programmed at once. + */ +status_t PRINCE_FlashProgramWithChecker(flash_config_t *config, uint32_t start, uint8_t *src, uint32_t lengthInBytes); +#endif /* !defined(FSL_PRINCE_DRIVER_LPC55S3x) */ + +#if defined(FSL_PRINCE_DRIVER_LPC55S3x) +/*! + * @brief Configures PRINCE setting. + * + * This function does the initial PRINCE configuration via ROM IAP API call. + * PRINCE_SR_x configuration for each region configuration is stored into FFR (CMPA). + * PRINCE IV erase counters (MCTR_INT_IV_CTRx) in CFPA are updated accordingly. + * + * Note: This function is expected to be called once in the device lifetime, + * typically during the initial device provisioning, since it is programming the CMPA pages in PFR flash. + * + * @param coreCtx The pointer to the ROM API driver context structure. + * @param config The pointer to the PRINCE driver configuration structure. + * + * @retval #kStatus_Success + * @retval #kStatus_CommandUnsupported + * @retval #kStatus_InvalidArgument + * @retval #kStatus_FLASH_ModifyProtectedAreaDisallowed + * @retval #kStatusMemoryRangeInvalid + * @retval #kStatus_Fail + * @retval #kStatus_OutOfRange + * @retval #kStatus_SPI_BaudrateNotSupport + */ +status_t PRINCE_Configure(api_core_context_t *coreCtx, prince_prot_region_arg_t *config); +#endif /* defined(FSL_PRINCE_DRIVER_LPC55S3x) */ + +#if defined(FSL_PRINCE_DRIVER_LPC55S3x) +/*! + * @brief Reconfigures PRINCE setting. + * + * This function is used to re-configure PRINCE IP based on configuration stored in FFR. + * This function also needs to be called after wake up from power-down mode to regenerate IV + * encryption key in CSS key store whose presence is necessary for correct PRINCE operation + * during erase and write operations to encrypted regions of internal flash memory + * (dependency for correct operation of MEM_Erase() and MEM_Write() after wake up from power-down mode). + * + * @param coreCtx The pointer to the ROM API driver context structure. + * + * @retval #kStatus_Success + * @retval #kStatus_CommandUnsupported + * @retval #kStatus_InvalidArgument + * @retval #kStatus_FLASH_ModifyProtectedAreaDisallowed + * @retval #kStatusMemoryRangeInvalid + * @retval #kStatus_Fail + * @retval #kStatus_OutOfRange + * @retval #kStatus_SPI_BaudrateNotSupport + */ +status_t PRINCE_Reconfigure(api_core_context_t *coreCtx); +#endif /* defined(FSL_PRINCE_DRIVER_LPC55S3x) */ + +#if (defined(FSL_PRINCE_DRIVER_LPC55S0x)) || defined(FSL_PRINCE_DRIVER_LPC55S1x) || defined(FSL_PRINCE_DRIVER_LPC55S3x) +/*! + * @brief Gets the PRINCE Error status register. + * + * @param base PRINCE peripheral address. + * + * @return PRINCE Error status register + */ +static inline uint32_t PRINCE_GetErrorStatus(PRINCE_Type *base) +{ + return base->ERR; +} + +/*! + * @brief Clears the PRINCE Error status register. + * + * @param base PRINCE peripheral address. + */ +static inline void PRINCE_ClearErrorStatus(PRINCE_Type *base) +{ + base->ERR = 0U; +} +#endif /* defined(FSL_PRINCE_DRIVER_LPC55S0x) || defined(FSL_PRINCE_DRIVER_LPC55S1x) || \ + defined(FSL_PRINCE_DRIVER_LPC55S3x) */ + +#if defined(__cplusplus) +} +#endif + +/*! + *@} + */ + +#endif /* _FSL_PRINCE_H_ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_puf.c b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_puf.c new file mode 100644 index 0000000000..d82299ed24 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_puf.c @@ -0,0 +1,949 @@ +/* + * Copyright 2018-2021 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_puf.h" +#include "fsl_clock.h" +#include "fsl_common.h" + +#if !(defined(FSL_FEATURE_PUF_HAS_NO_RESET) && (FSL_FEATURE_PUF_HAS_NO_RESET > 0)) +#include "fsl_reset.h" +#endif /* FSL_FEATURE_PUF_HAS_NO_RESET */ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.puf" +#endif + +/* RT6xx POWER CONTROL bit masks */ +#if defined(FSL_FEATURE_PUF_PWR_HAS_MANUAL_SLEEP_CONTROL) && (FSL_FEATURE_PUF_PWR_HAS_MANUAL_SLEEP_CONTROL > 0) +#define PUF_PWRCTRL_CKDIS_MASK (0x4U) +#define PUF_PWRCTRL_RAMINIT_MASK (0x8U) +#define PUF_PWRCTRL_RAMPSWLARGEMA_MASK (0x10U) +#define PUF_PWRCTRL_RAMPSWLARGEMP_MASK (0x20U) +#define PUF_PWRCTRL_RAMPSWSMALLMA_MASK (0x40U) +#define PUF_PWRCTRL_RAMPSWSMALLMP_MASK (0x80U) +#endif + +#if defined(FSL_FEATURE_PUF_HAS_SRAM_CTRL) && (FSL_FEATURE_PUF_HAS_SRAM_CTRL > 0) +#define DEFAULT_CKGATING 0x0u +#define PUF_ENABLE_MASK 0xFFFFFFFEu +#define PUF_ENABLE_CTRL 0x1u + +#else +static void puf_wait_usec(volatile uint32_t usec, uint32_t coreClockFrequencyMHz) +{ + SDK_DelayAtLeastUs(usec, coreClockFrequencyMHz * 1000000U); + + /* Instead of calling SDK_DelayAtLeastUs() implement delay loop here */ + // while (usec > 0U) + // { + // usec--; + + // number of MHz is directly number of core clocks to wait 1 usec. + // the while loop below is actually 4 clocks so divide by 4 for ~1 usec + // volatile uint32_t ticksCount = coreClockFrequencyMHz / 4u + 1u; + // while (0U != ticksCount--) + // { + // } + // } +} +#endif /* defined(FSL_FEATURE_PUF_HAS_SRAM_CTRL) && (FSL_FEATURE_PUF_HAS_SRAM_CTRL > 0) */ + +static status_t puf_waitForInit(PUF_Type *base) +{ + status_t status = kStatus_Fail; + + /* wait until status register reads non-zero. All zero is not valid. It should be BUSY or OK or ERROR */ + while (0U == base->STAT) + { + } + + /* wait if busy */ + while ((base->STAT & PUF_STAT_BUSY_MASK) != 0U) + { + } + + /* return status */ + if (0U != (base->STAT & (PUF_STAT_SUCCESS_MASK | PUF_STAT_ERROR_MASK))) + { + status = kStatus_Success; + } + + return status; +} + +static void puf_powerOn(PUF_Type *base, puf_config_t *conf) +{ +#if defined(FSL_FEATURE_PUF_PWR_HAS_MANUAL_SLEEP_CONTROL) && (FSL_FEATURE_PUF_PWR_HAS_MANUAL_SLEEP_CONTROL > 0) + /* RT6xxs */ + base->PWRCTRL = (PUF_PWRCTRL_RAM_ON_MASK | PUF_PWRCTRL_CK_DIS_MASK); + base->PWRCTRL = (PUF_PWRCTRL_RAM_ON_MASK | PUF_PWRCTRL_CK_DIS_MASK | PUF_PWRCTRL_RAMINIT_MASK); + base->PWRCTRL = (PUF_PWRCTRL_RAM_ON_MASK | PUF_PWRCTRL_RAMINIT_MASK); +#elif defined(FSL_FEATURE_PUF_HAS_SRAM_CTRL) && (FSL_FEATURE_PUF_HAS_SRAM_CTRL > 0) + /* LPCXpresso55s16 */ + conf->puf_sram_base->CFG |= PUF_ENABLE_CTRL; + while (0U == (PUF_SRAM_CTRL_STATUS_READY_MASK & conf->puf_sram_base->STATUS)) + { + } +#else /* !FSL_FEATURE_PUF_PWR_HAS_MANUAL_SLEEP_CONTROL */ + /* LPCXpresso55s69 & LPCXpresso54S018 */ + base->PWRCTRL = PUF_PWRCTRL_RAMON_MASK; + while (0U == (PUF_PWRCTRL_RAMSTAT_MASK & base->PWRCTRL)) + { + } +#endif /* FSL_FEATURE_PUF_PWR_HAS_MANUAL_SLEEP_CONTROL */ +} +/*! + * brief Powercycle PUF + * + * This function make powercycle of PUF. + * + * param base PUF peripheral base address + * param conf PUF configuration structure + * return Status of the powercycle operation. + */ +status_t PUF_PowerCycle(PUF_Type *base, puf_config_t *conf) +{ +#if defined(FSL_FEATURE_PUF_PWR_HAS_MANUAL_SLEEP_CONTROL) && (FSL_FEATURE_PUF_PWR_HAS_MANUAL_SLEEP_CONTROL > 0) + /* RT6xxs */ + uint32_t coreClockFrequencyMHz = conf->coreClockFrequencyHz / 1000000u; + + base->PWRCTRL = (PUF_PWRCTRL_RAM_ON_MASK | PUF_PWRCTRL_CK_DIS_MASK | PUF_PWRCTRL_RAMINIT_MASK); /* disable RAM CK */ + + /* enter ASPS mode */ + base->PWRCTRL = (PUF_PWRCTRL_CK_DIS_MASK | PUF_PWRCTRL_RAMINIT_MASK); /* SLEEP = 1 */ + base->PWRCTRL = (PUF_PWRCTRL_RAMINIT_MASK); /* enable RAM CK */ + base->PWRCTRL = (PUF_PWRCTRL_RAMINIT_MASK | PUF_PWRCTRL_RAMPSWLARGEMA_MASK | PUF_PWRCTRL_RAMPSWLARGEMP_MASK | + PUF_PWRCTRL_RAMPSWSMALLMA_MASK | PUF_PWRCTRL_RAMPSWSMALLMP_MASK); /* SLEEP=1, PSW*=1 */ + + /* Wait enough time to discharge fully */ + puf_wait_usec(conf->dischargeTimeMsec * 1000u, conf->coreClockFrequencyHz / 1000000u); + + /* write PWRCTRL=0x38. wait time > 1 us */ + base->PWRCTRL = (PUF_PWRCTRL_RAMINIT_MASK | PUF_PWRCTRL_RAMPSWLARGEMA_MASK | + PUF_PWRCTRL_RAMPSWLARGEMP_MASK); /* SLEEP=1. PSWSMALL*=0. PSWLARGE*=1. */ + puf_wait_usec(1, coreClockFrequencyMHz); + + /* write PWRCTRL=0x8. wait time > 1 us */ + base->PWRCTRL = PUF_PWRCTRL_RAMINIT_MASK; /* SLEEP=1. PSWSMALL*=0. PSWLARGE*=0 */ + puf_wait_usec(1, coreClockFrequencyMHz); + + base->PWRCTRL = (PUF_PWRCTRL_CK_DIS_MASK | PUF_PWRCTRL_RAMINIT_MASK); + base->PWRCTRL = (PUF_PWRCTRL_RAM_ON_MASK | PUF_PWRCTRL_CK_DIS_MASK | PUF_PWRCTRL_RAMINIT_MASK); + base->PWRCTRL = (PUF_PWRCTRL_RAM_ON_MASK | PUF_PWRCTRL_RAMINIT_MASK); + + /* Generate INITN low pulse */ + base->PWRCTRL = (PUF_PWRCTRL_RAM_ON_MASK | PUF_PWRCTRL_CK_DIS_MASK | PUF_PWRCTRL_RAMINIT_MASK); + base->PWRCTRL = (PUF_PWRCTRL_RAM_ON_MASK | PUF_PWRCTRL_CK_DIS_MASK); + base->PWRCTRL = PUF_PWRCTRL_RAM_ON_MASK; +#elif defined(FSL_FEATURE_PUF_HAS_SRAM_CTRL) && (FSL_FEATURE_PUF_HAS_SRAM_CTRL > 0) + /* LPCXpresso55s16 */ + conf->puf_sram_base->CFG &= PUF_ENABLE_MASK; +#else + /* LPCXpresso55s69 & LPCXpresso54S018 */ + base->PWRCTRL = 0x0u; + while (0U != (PUF_PWRCTRL_RAMSTAT_MASK & base->PWRCTRL)) + { + } + + /* Wait enough time to discharge fully */ + puf_wait_usec(conf->dischargeTimeMsec * 1000u, conf->coreClockFrequencyHz / 1000000u); +#endif + +#if !(defined(FSL_FEATURE_PUF_HAS_NO_RESET) && (FSL_FEATURE_PUF_HAS_NO_RESET > 0)) + /* Reset PUF and reenable power to PUF SRAM */ + RESET_PeripheralReset(kPUF_RST_SHIFT_RSTn); +#endif /* FSL_TEATURE_PUF_HAS_NO_RESET */ + puf_powerOn(base, conf); + + return kStatus_Success; +} + +/*! + * brief Sets the default configuration of PUF + * + * This function initialize PUF config structure to default values. + * + * param conf PUF configuration structure + */ +void PUF_GetDefaultConfig(puf_config_t *conf) +{ +#if defined(FSL_FEATURE_PUF_HAS_SRAM_CTRL) && (FSL_FEATURE_PUF_HAS_SRAM_CTRL > 0) + /* LPCXpresso55s16 */ + conf->puf_sram_base = PUF_SRAM_CTRL; + + /* Default configuration after reset */ + conf->CKGATING = DEFAULT_CKGATING; /* PUF SRAM Clock Gating */ +#endif /* FSL_FEATURE_PUF_HAS_SRAM_CTRL */ + + conf->dischargeTimeMsec = KEYSTORE_PUF_DISCHARGE_TIME_FIRST_TRY_MS; + conf->coreClockFrequencyHz = CLOCK_GetFreq(kCLOCK_CoreSysClk); + + return; +} + +/*! + * brief Initialize PUF + * + * This function enables power to PUF block and waits until the block initializes. + * + * param base PUF peripheral base address + * param conf PUF configuration structure + * return Status of the init operation + */ +status_t PUF_Init(PUF_Type *base, puf_config_t *conf) +{ + status_t status = kStatus_Fail; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + CLOCK_EnableClock(kCLOCK_Puf); +#endif +#if !(defined(FSL_FEATURE_PUF_HAS_NO_RESET) && (FSL_FEATURE_PUF_HAS_NO_RESET > 0)) + /* Reset PUF */ + RESET_PeripheralReset(kPUF_RST_SHIFT_RSTn); +#endif /* FSL_FEATURE_PUF_HAS_NO_RESET */ + +#if defined(FSL_FEATURE_PUF_HAS_SRAM_CTRL) && (FSL_FEATURE_PUF_HAS_SRAM_CTRL > 0) + /* Set configuration for SRAM */ + conf->puf_sram_base->CFG |= PUF_SRAM_CTRL_CFG_CKGATING(conf->CKGATING); + +#endif /* FSL_FEATURE_PUF_HAS_SRAM_CTRL */ + + /* Enable power to PUF SRAM */ + puf_powerOn(base, conf); + + /* Wait for peripheral to become ready */ + status = puf_waitForInit(base); + + /* In case of error or enroll or start not allowed, do power-cycle */ + /* First try with shorter discharge time, if then it also fails try with longer time */ + /* conf->dischargeTimeMsec = KEYSTORE_PUF_DISCHARGE_TIME_FIRST_TRY_MS; */ + if ((status != kStatus_Success) || (0U == (base->ALLOW & (PUF_ALLOW_ALLOWENROLL_MASK | PUF_ALLOW_ALLOWSTART_MASK)))) + { + (void)PUF_PowerCycle(base, conf); + status = puf_waitForInit(base); + } + + /* In case of error or enroll or start not allowed, do power-cycle with worst discharge timing */ + if ((status != kStatus_Success) || (0U == (base->ALLOW & (PUF_ALLOW_ALLOWENROLL_MASK | PUF_ALLOW_ALLOWSTART_MASK)))) + { + conf->dischargeTimeMsec = KEYSTORE_PUF_DISCHARGE_TIME_MAX_MS; + (void)PUF_PowerCycle(base, conf); + status = puf_waitForInit(base); + } + + return status; +} + +/*! + * brief Denitialize PUF + * + * This function disables power to PUF SRAM and peripheral clock. + * + * param base PUF peripheral base address + * param conf PUF configuration structure + */ +void PUF_Deinit(PUF_Type *base, puf_config_t *conf) +{ +#if defined(FSL_FEATURE_PUF_PWR_HAS_MANUAL_SLEEP_CONTROL) && (FSL_FEATURE_PUF_PWR_HAS_MANUAL_SLEEP_CONTROL > 0) + /* RT6xxs */ + base->PWRCTRL = (PUF_PWRCTRL_RAM_ON_MASK | PUF_PWRCTRL_CK_DIS_MASK | PUF_PWRCTRL_RAMINIT_MASK); /* disable RAM CK */ + + /* enter ASPS mode */ + base->PWRCTRL = (PUF_PWRCTRL_CK_DIS_MASK | PUF_PWRCTRL_RAMINIT_MASK); /* SLEEP = 1 */ + base->PWRCTRL = PUF_PWRCTRL_RAMINIT_MASK; /* enable RAM CK */ + base->PWRCTRL = (PUF_PWRCTRL_RAMINIT_MASK | PUF_PWRCTRL_RAMPSWLARGEMA_MASK | PUF_PWRCTRL_RAMPSWLARGEMP_MASK | + PUF_PWRCTRL_RAMPSWSMALLMA_MASK | PUF_PWRCTRL_RAMPSWSMALLMP_MASK); /* SLEEP=1, PSW*=1 */ + puf_wait_usec(conf->dischargeTimeMsec * 1000u, conf->coreClockFrequencyHz / 1000000u); +#elif defined(FSL_FEATURE_PUF_HAS_SRAM_CTRL) && (FSL_FEATURE_PUF_HAS_SRAM_CTRL > 0) + /* LPCXpresso55s16 */ + conf->puf_sram_base = PUF_SRAM_CTRL; + conf->puf_sram_base->CFG &= PUF_ENABLE_MASK; +#else /* !FSL_FEATURE_PUF_PWR_HAS_MANUAL_SLEEP_CONTROL */ + /* LPCXpresso55s69 & LPCXpresso54S018 */ + base->PWRCTRL = 0x00u; + puf_wait_usec(conf->dischargeTimeMsec * 1000u, conf->coreClockFrequencyHz / 1000000u); +#endif + +#if !(defined(FSL_FEATURE_PUF_HAS_NO_RESET) && (FSL_FEATURE_PUF_HAS_NO_RESET > 0)) + RESET_SetPeripheralReset(kPUF_RST_SHIFT_RSTn); +#endif /* FSL_FEATURE_PUF_HAS_NO_RESET */ + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + CLOCK_DisableClock(kCLOCK_Puf); +#endif +} + +/*! + * brief Enroll PUF + * + * This function derives a digital fingerprint, generates the corresponding Activation Code (AC) + * and returns it to be stored in an NVM or a file. This step needs to be + * performed only once for each device. This function may be permanently disallowed by a fuse. + * + * param base PUF peripheral base address + * param[out] activationCode Word aligned address of the resulting activation code. + * param activationCodeSize Size of the activationCode buffer in bytes. Shall be 1192 bytes. + * return Status of enroll operation. + */ +status_t PUF_Enroll(PUF_Type *base, uint8_t *activationCode, size_t activationCodeSize) +{ + status_t status = kStatus_Fail; + uint32_t *activationCodeAligned = NULL; + register uint32_t temp32 = 0; + + /* check that activation code buffer size is at least 1192 bytes */ + if (activationCodeSize < PUF_ACTIVATION_CODE_SIZE) + { + return kStatus_InvalidArgument; + } + + /* only work with aligned activationCode */ + if (0U != (0x3u & (uintptr_t)activationCode)) + { + return kStatus_InvalidArgument; + } + + activationCodeAligned = (uint32_t *)(uintptr_t)activationCode; + + /* check if ENROLL is allowed */ + if (0x0u == (base->ALLOW & PUF_ALLOW_ALLOWENROLL_MASK)) + { + return kStatus_EnrollNotAllowed; + } + + /* begin */ + base->CTRL = PUF_CTRL_ENROLL_MASK; + + /* check status */ + while (0U == (base->STAT & (PUF_STAT_BUSY_MASK | PUF_STAT_ERROR_MASK))) + { + } + + /* read out AC */ + while (0U != (base->STAT & PUF_STAT_BUSY_MASK)) + { + if (0U != (PUF_STAT_CODEOUTAVAIL_MASK & base->STAT)) + { + temp32 = base->CODEOUTPUT; + if (activationCodeSize >= sizeof(uint32_t)) + { + *activationCodeAligned = temp32; + activationCodeAligned++; + activationCodeSize -= sizeof(uint32_t); + } + } + } + + if (((base->STAT & PUF_STAT_SUCCESS_MASK) != 0U) && (activationCodeSize == 0U)) + { + status = kStatus_Success; + } + + return status; +} + +/*! + * brief Start PUF + * + * The Activation Code generated during the Enroll operation is used to + * reconstruct the digital fingerprint. This needs to be done after every power-up + * and reset. + * + * param base PUF peripheral base address + * param activationCode Word aligned address of the input activation code. + * param activationCodeSize Size of the activationCode buffer in bytes. Shall be 1192 bytes. + * return Status of start operation. + */ +status_t PUF_Start(PUF_Type *base, const uint8_t *activationCode, size_t activationCodeSize) +{ + status_t status = kStatus_Fail; + const uint32_t *activationCodeAligned = NULL; + register uint32_t temp32 = 0; + + /* check that activation code size is at least 1192 bytes */ + if (activationCodeSize < 1192U) + { + return kStatus_InvalidArgument; + } + + /* only work with aligned activationCode */ + if (0U != (0x3u & (uintptr_t)activationCode)) + { + return kStatus_InvalidArgument; + } + + activationCodeAligned = (const uint32_t *)(uintptr_t)activationCode; + + /* check if START is allowed */ + if (0x0u == (base->ALLOW & PUF_ALLOW_ALLOWSTART_MASK)) + { + return kStatus_StartNotAllowed; + } + + /* begin */ + base->CTRL = PUF_CTRL_START_MASK; + + /* check status */ + while (0U == (base->STAT & (PUF_STAT_BUSY_MASK | PUF_STAT_ERROR_MASK))) + { + } + + /* while busy send AC */ + while (0U != (base->STAT & PUF_STAT_BUSY_MASK)) + { + if (0U != (PUF_STAT_CODEINREQ_MASK & base->STAT)) + { + if (activationCodeSize >= sizeof(uint32_t)) + { + temp32 = *activationCodeAligned; + activationCodeAligned++; + activationCodeSize -= sizeof(uint32_t); + } + base->CODEINPUT = temp32; + } + } + + /* get status */ + if (0U != (base->STAT & PUF_STAT_SUCCESS_MASK)) + { + status = kStatus_Success; + } + + return status; +} + +/*! + * brief Set intrinsic key + * + * The digital fingerprint generated during the Enroll/Start + * operations is used to generate a Key Code (KC) that defines a unique intrinsic + * key. This KC is returned to be stored in an NVM or a file. This operation + * needs to be done only once for each intrinsic key. + * Each time a Set Intrinsic Key operation is executed a new unique key is + * generated. + * + * param base PUF peripheral base address + * param keyIndex PUF key index register + * param keySize Size of the intrinsic key to generate in bytes. + * param[out] keyCode Word aligned address of the resulting key code. + * param keyCodeSize Size of the keyCode buffer in bytes. Shall be PUF_GET_KEY_CODE_SIZE_FOR_KEY_SIZE(keySize). + * return Status of set intrinsic key operation. + */ +status_t PUF_SetIntrinsicKey( + PUF_Type *base, puf_key_index_register_t keyIndex, size_t keySize, uint8_t *keyCode, size_t keyCodeSize) +{ + status_t status = kStatus_Fail; + uint32_t *keyCodeAligned = NULL; + register uint32_t temp32 = 0; + + /* check if SET KEY is allowed */ + if (0x0u == (base->ALLOW & PUF_ALLOW_ALLOWSETKEY_MASK)) + { + return kStatus_Fail; + } + + /* only work with aligned keyCode */ + if (0U != (0x3u & (uintptr_t)keyCode)) + { + return kStatus_InvalidArgument; + } + + /* Check that keySize is in the correct range and that it is multiple of 8 */ + if ((keySize < (uint32_t)kPUF_KeySizeMin) || (keySize > (uint32_t)kPUF_KeySizeMax) || (0U != (keySize & 0x7U))) + { + return kStatus_InvalidArgument; + } + + /* check that keyCodeSize is correct for given keySize */ + if (keyCodeSize < PUF_GET_KEY_CODE_SIZE_FOR_KEY_SIZE(keySize)) + { + return kStatus_InvalidArgument; + } + + if ((uint32_t)keyIndex > (uint32_t)kPUF_KeyIndexMax) + { + return kStatus_InvalidArgument; + } + + keyCodeAligned = (uint32_t *)(uintptr_t)keyCode; + + /* program the key size and index */ + base->KEYSIZE = keySize >> 3; + base->KEYINDEX = (uint32_t)keyIndex; + + /* begin */ + base->CTRL = PUF_CTRL_GENERATEKEY_MASK; + + /* wait till command is accepted */ + while (0U == (base->STAT & (PUF_STAT_BUSY_MASK | PUF_STAT_ERROR_MASK))) + { + } + + /* while busy read KC */ + while (0U != (base->STAT & PUF_STAT_BUSY_MASK)) + { + if (0U != (PUF_STAT_CODEOUTAVAIL_MASK & base->STAT)) + { + temp32 = base->CODEOUTPUT; + if (keyCodeSize >= sizeof(uint32_t)) + { + *keyCodeAligned = temp32; + keyCodeAligned++; + keyCodeSize -= sizeof(uint32_t); + } + } + } + + /* get status */ + if (0U != (base->STAT & PUF_STAT_SUCCESS_MASK)) + { + status = kStatus_Success; + } + + return status; +} + +/*! + * brief Set user key + * + * The digital fingerprint generated during the Enroll/Start + * operations and a user key (UK) provided as input are used to + * generate a Key Code (KC). This KC is sent returned to be stored + * in an NVM or a file. This operation needs to be done only once for each user key. + * + * param base PUF peripheral base address + * param keyIndex PUF key index register + * param userKey Word aligned address of input user key. + * param userKeySize Size of the input user key in bytes. + * param[out] keyCode Word aligned address of the resulting key code. + * param keyCodeSize Size of the keyCode buffer in bytes. Shall be PUF_GET_KEY_CODE_SIZE_FOR_KEY_SIZE(userKeySize). + * return Status of set user key operation. + */ +status_t PUF_SetUserKey(PUF_Type *base, + puf_key_index_register_t keyIndex, + const uint8_t *userKey, + size_t userKeySize, + uint8_t *keyCode, + size_t keyCodeSize) +{ + status_t status = kStatus_Fail; + uint32_t *keyCodeAligned = NULL; + const uint32_t *userKeyAligned = NULL; + register uint32_t temp32 = 0; + + /* check if SET KEY is allowed */ + if (0x0u == (base->ALLOW & PUF_ALLOW_ALLOWSETKEY_MASK)) + { + return kStatus_Fail; + } + + /* only work with aligned keyCode */ + if (0U != (0x3u & (uintptr_t)keyCode)) + { + return kStatus_InvalidArgument; + } + + /* Check that userKeySize is in the correct range and that it is multiple of 8 */ + if ((userKeySize < (uint32_t)kPUF_KeySizeMin) || (userKeySize > (uint32_t)kPUF_KeySizeMax) || + (0U != (userKeySize & 0x7U))) + { + return kStatus_InvalidArgument; + } + + /* check that keyCodeSize is correct for given userKeySize */ + if (keyCodeSize < PUF_GET_KEY_CODE_SIZE_FOR_KEY_SIZE(userKeySize)) + { + return kStatus_InvalidArgument; + } + + if ((uint32_t)keyIndex > (uint32_t)kPUF_KeyIndexMax) + { + return kStatus_InvalidArgument; + } + + keyCodeAligned = (uint32_t *)(uintptr_t)keyCode; + userKeyAligned = (const uint32_t *)(uintptr_t)userKey; + + /* program the key size and index */ + base->KEYSIZE = userKeySize >> 3; /* convert to 64-bit blocks */ + base->KEYINDEX = (uint32_t)keyIndex; + + /* We have to store the user key on index 0 swaped for HW bus */ + if (keyIndex == kPUF_KeyIndex_00) + { + userKeyAligned = userKeyAligned + (userKeySize / sizeof(uint32_t)); + } + + /* begin */ + base->CTRL = PUF_CTRL_SETKEY_MASK; + + /* wait till command is accepted */ + while (0U == (base->STAT & (PUF_STAT_BUSY_MASK | PUF_STAT_ERROR_MASK))) + { + } + + /* while busy write UK and read KC */ + while (0U != (base->STAT & PUF_STAT_BUSY_MASK)) + { + if (0U != (PUF_STAT_KEYINREQ_MASK & base->STAT)) + { + if (userKeySize >= sizeof(uint32_t)) + { +#if defined(LPC54S018_SERIES) + if (keyIndex == kPUF_KeyIndex_00) + { + userKeyAligned--; + temp32 = *userKeyAligned; + userKeySize -= sizeof(uint32_t); + } +#else + if (keyIndex == kPUF_KeyIndex_00) + { + userKeyAligned--; + temp32 = __REV(*userKeyAligned); + userKeySize--; + } +#endif /* defined(LPC54S018_SERIES) */ + else if (keyIndex != kPUF_KeyIndex_00) + { + temp32 = *userKeyAligned; + userKeyAligned++; + userKeySize -= sizeof(uint32_t); + } + else + { + /* Intentional empty */ + } + } + base->KEYINPUT = temp32; + } + + if (0U != (PUF_STAT_CODEOUTAVAIL_MASK & base->STAT)) + { + temp32 = base->CODEOUTPUT; + if (keyCodeSize >= sizeof(uint32_t)) + { + *keyCodeAligned = temp32; + keyCodeAligned++; + keyCodeSize -= sizeof(uint32_t); + } + } + } + + /* get status */ + if (0U != (base->STAT & PUF_STAT_SUCCESS_MASK)) + { + status = kStatus_Success; + } + + return status; +} + +static status_t puf_getHwKey(PUF_Type *base, const uint8_t *keyCode, size_t keyCodeSize) +{ + status_t status = kStatus_Fail; + uint32_t *keyCodeAligned = NULL; + register uint32_t temp32 = 0; + + keyCodeAligned = (uint32_t *)(uintptr_t)keyCode; + + /* begin */ + base->CTRL = PUF_CTRL_GETKEY_MASK; + + /* wait till command is accepted */ + while (0U == (base->STAT & (PUF_STAT_BUSY_MASK | PUF_STAT_ERROR_MASK))) + { + } + + /* while busy send KC, key is reconstructed to HW bus */ + while (0U != (base->STAT & PUF_STAT_BUSY_MASK)) + { + if (0U != (PUF_STAT_CODEINREQ_MASK & base->STAT)) + { + if (keyCodeSize >= sizeof(uint32_t)) + { + temp32 = *keyCodeAligned; + keyCodeAligned++; + keyCodeSize -= sizeof(uint32_t); + } + base->CODEINPUT = temp32; + } + } + + /* get status */ + if (0U != (base->STAT & PUF_STAT_SUCCESS_MASK)) + { + status = kStatus_Success; + } + + return status; +} + +/*! + * brief Reconstruct hw bus key from a key code + * + * The digital fingerprint generated during the Start operation and the KC + * generated during a Set Key operation (Set intrinsic key or Set user key) are used to retrieve a stored key. This + * operation needs to be done every time a key is needed. + * This function accepts only Key Codes created for PUF index register kPUF_KeyIndex_00. + * Such a key is output directly to a dedicated hardware bus. The reconstructed key is not exposed to system memory. + * + * param base PUF peripheral base address + * param keyCode Word aligned address of the input key code. + * param keyCodeSize Size of the keyCode buffer in bytes. Shall be PUF_GET_KEY_CODE_SIZE_FOR_KEY_SIZE(keySize). + * param keySlot key slot to output on hw bus. Parameter is ignored on devices with less than two key slots. + * param keyMask key masking value. Shall be random for each POR/reset. Value does not have to be cryptographicaly + * secure. + * return Status of get key operation. + */ +status_t PUF_GetHwKey( + PUF_Type *base, const uint8_t *keyCode, size_t keyCodeSize, puf_key_slot_t keySlot, uint32_t keyMask) +{ + status_t status = kStatus_Fail; + uint32_t keyIndex; + + /* check if GET KEY is allowed */ + if (0x0u == (base->ALLOW & PUF_ALLOW_ALLOWGETKEY_MASK)) + { + return kStatus_Fail; + } + + /* only work with aligned keyCode */ + if (0U != (0x3u & (uintptr_t)keyCode)) + { + return kStatus_Fail; + } + + /* check that keyCodeSize is at least PUF_MIN_KEY_CODE_SIZE */ + if (keyCodeSize < PUF_MIN_KEY_CODE_SIZE) + { + return kStatus_InvalidArgument; + } + + keyIndex = (uint32_t)(0x0Fu & (uint32_t)keyCode[1]); + + /* check the Key Code header byte 1. index must be zero for the hw key. */ + if (kPUF_KeyIndex_00 != (puf_key_index_register_t)keyIndex) + { + return kStatus_Fail; + } + +#if defined(PUF_KEYMASK_COUNT) && (PUF_KEYMASK_COUNT > 0) + volatile uint32_t *keyMask_reg = NULL; + uint32_t regVal = ((uint32_t)2U << ((uint32_t)2U * (uint32_t)keySlot)); + + switch (keySlot) + { + case kPUF_KeySlot0: + keyMask_reg = &base->KEYMASK[0]; + break; + + case kPUF_KeySlot1: + keyMask_reg = &base->KEYMASK[1]; + break; +#if (PUF_KEYMASK_COUNT > 2) + case kPUF_KeySlot2: + keyMask_reg = &base->KEYMASK[2]; + break; + + case kPUF_KeySlot3: + keyMask_reg = &base->KEYMASK[3]; + break; +#endif /* PUF_KEYMASK_COUNT > 2 */ + default: + status = kStatus_InvalidArgument; + break; + } +#endif /* PUF_KEYMASK_COUNT */ + + if (status != kStatus_InvalidArgument) + { +#if defined(PUF_KEYMASK_COUNT) && (PUF_KEYMASK_COUNT > 0) + base->KEYRESET = regVal; + base->KEYENABLE = regVal; + *keyMask_reg = keyMask; +#endif /* FSL_FEATURE_PUF_HAS_KEYSLOTS */ + + status = puf_getHwKey(base, keyCode, keyCodeSize); + +#if defined(FSL_FEATURE_PUF_HAS_SHIFT_STATUS) && (FSL_FEATURE_PUF_HAS_SHIFT_STATUS > 0) + size_t keyWords = 0; + + if (status == kStatus_Success) + { + /* if the corresponding shift count does not match, return fail anyway */ + keyWords = ((((size_t)keyCode[3]) * 2U) - 1u) << ((size_t)keySlot << 2U); + if (keyWords != ((0x0FUL << ((uint32_t)keySlot << 2U)) & base->SHIFT_STATUS)) + { + status = kStatus_Fail; + } + } +#elif defined(PUF_IDXBLK_SHIFT_IND_KEY0_MASK) && PUF_IDXBLK_SHIFT_IND_KEY0_MASK + size_t keyWords = 0; + + if (status == kStatus_Success) + { + /* if the corresponding shift count does not match, return fail anyway */ + keyWords = ((((size_t)keyCode[3]) * 2U) - 1u) << ((size_t)keySlot << 2U); + if (keyWords != ((0x0FUL << ((uint32_t)keySlot << 2U)) & base->IDXBLK_SHIFT)) + { + status = kStatus_Fail; + } + } +#endif /* FSL_FEATURE_PUF_HAS_SHIFT_STATUS || PUF_IDXBLK_SHIFT_IND_KEY0_MASK */ + } + + return status; +} + +/*! + * brief Checks if Get Key operation is allowed. + * + * This function returns true if get key operation is allowed. + * + * param base PUF peripheral base address + * return true if get key operation is allowed + */ +bool PUF_IsGetKeyAllowed(PUF_Type *base) +{ + /* check if GET KEY is allowed */ + if (0x0u == (base->ALLOW & PUF_ALLOW_ALLOWGETKEY_MASK)) + { + return false; + } + + return true; +} + +/*! + * brief Reconstruct key from a key code + * + * The digital fingerprint generated during the Start operation and the KC + * generated during a Set Key operation (Set intrinsic key or Set user key) are used to retrieve a stored key. This + * operation needs to be done every time a key is needed. + * This function accepts only Key Codes created for PUF index registers kPUF_KeyIndex_01 to kPUF_KeyIndex_15. + * + * param base PUF peripheral base address + * param keyCode Word aligned address of the input key code. + * param keyCodeSize Size of the keyCode buffer in bytes. Shall be PUF_GET_KEY_CODE_SIZE_FOR_KEY_SIZE(keySize). + * param[out] key Word aligned address of output key. + * param keySize Size of the output key in bytes. + * return Status of get key operation. + */ +status_t PUF_GetKey(PUF_Type *base, const uint8_t *keyCode, size_t keyCodeSize, uint8_t *key, size_t keySize) +{ + status_t status = kStatus_Fail; + uint32_t *keyCodeAligned = NULL; + uint32_t *keyAligned = NULL; + uint32_t keyIndex; + register uint32_t temp32 = 0; + + /* check if GET KEY is allowed */ + if (0x0u == (base->ALLOW & PUF_ALLOW_ALLOWGETKEY_MASK)) + { + return kStatus_Fail; + } + + /* only work with aligned keyCode */ + if (0U != (0x3u & (uintptr_t)keyCode)) + { + return kStatus_Fail; + } + + /* only work with aligned key */ + if (0U != (0x3u & (uintptr_t)key)) + { + return kStatus_Fail; + } + + /* check that keyCodeSize is correct for given keySize */ + if (keyCodeSize < PUF_GET_KEY_CODE_SIZE_FOR_KEY_SIZE(keySize)) + { + return kStatus_InvalidArgument; + } + + keyIndex = (0x0Fu & (uint32_t)keyCode[1]); + + /* check the Key Code header byte 1. index must be non-zero for the register key. */ + if (kPUF_KeyIndex_00 == (puf_key_index_register_t)keyIndex) + { + return kStatus_Fail; + } + + keyCodeAligned = (uint32_t *)(uintptr_t)keyCode; + keyAligned = (uint32_t *)(uintptr_t)key; + + /* begin */ + base->CTRL = PUF_CTRL_GETKEY_MASK; + + /* wait till command is accepted */ + while (0U == (base->STAT & (PUF_STAT_BUSY_MASK | PUF_STAT_ERROR_MASK))) + { + } + + /* while busy send KC, read key */ + while (0U != (base->STAT & PUF_STAT_BUSY_MASK)) + { + if (0U != (PUF_STAT_CODEINREQ_MASK & base->STAT)) + { + temp32 = 0; + if (keyCodeSize >= sizeof(uint32_t)) + { + temp32 = *keyCodeAligned; + keyCodeAligned++; + keyCodeSize -= sizeof(uint32_t); + } + base->CODEINPUT = temp32; + } + + if (0U != (PUF_STAT_KEYOUTAVAIL_MASK & base->STAT)) + { + keyIndex = base->KEYOUTINDEX; + temp32 = base->KEYOUTPUT; + if (keySize >= sizeof(uint32_t)) + { + *keyAligned = temp32; + keyAligned++; + keySize -= sizeof(uint32_t); + } + } + } + + /* get status */ + if ((keyIndex != 0U) && (0U != (base->STAT & PUF_STAT_SUCCESS_MASK))) + { + status = kStatus_Success; + } + + return status; +} + +/*! + * brief Zeroize PUF + * + * This function clears all PUF internal logic and puts the PUF to error state. + * + * param base PUF peripheral base address + * return Status of the zeroize operation. + */ +status_t PUF_Zeroize(PUF_Type *base) +{ + status_t status = kStatus_Fail; + + /* zeroize command is always allowed */ + base->CTRL = PUF_CTRL_ZEROIZE_MASK; + + /* check that command is accepted */ + if ((0U != (base->STAT & PUF_STAT_ERROR_MASK)) && (0U == base->ALLOW)) + { + status = kStatus_Success; + } + + return status; +} diff --git a/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_puf.h b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_puf.h new file mode 100644 index 0000000000..b8a5c51c85 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_puf.h @@ -0,0 +1,335 @@ +/* + * Copyright 2018-2021 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _PUF_H_ +#define _PUF_H_ + +#include +#include + +#include "fsl_common.h" + +/******************************************************************************* + * Definitions + *******************************************************************************/ + +/*! + * @addtogroup puf_driver + * @{ + */ +/*! @name Driver version */ +/*@{*/ +/*! @brief PUF driver version. Version 2.1.6. + * + * Current version: 2.1.6 + * + * Change log: + * - 2.0.0 + * - Initial version. + * - 2.0.1 + * - Fixed puf_wait_usec function optimization issue. + * - 2.0.2 + * - Add PUF configuration structure and support for PUF SRAM controller. + * Remove magic constants. + * - 2.0.3 + * - Fix MISRA C-2012 issue. + * - 2.1.0 + * - Align driver with PUF SRAM controller registers on LPCXpresso55s16. + * - Update initizalition logic . + * - 2.1.1 + * - Fix ARMGCC build warning . + * - 2.1.2 + * - Update: Add automatic big to little endian swap for user + * (pre-shared) keys destinated to secret hardware bus (PUF key index 0). + * - 2.1.3 + * - Fix MISRA C-2012 issue. + * - 2.1.4 + * - Replace register uint32_t ticksCount with volatile uint32_t ticksCount in puf_wait_usec() to prevent optimization + * out delay loop. + * - 2.1.5 + * - Use common SDK delay in puf_wait_usec() + * - 2.1.6 + * - Changed wait time in PUF_Init(), when initialization fails it will try PUF_Powercycle() with shorter time. If + * this shorter time will also fail, initialization will be tried with worst case time as before. + */ +#define FSL_PUF_DRIVER_VERSION (MAKE_VERSION(2, 1, 6)) +/*@}*/ + +typedef enum _puf_key_index_register +{ + kPUF_KeyIndex_00 = 0x00U, + kPUF_KeyIndex_01 = 0x01U, + kPUF_KeyIndex_02 = 0x02U, + kPUF_KeyIndex_03 = 0x03U, + kPUF_KeyIndex_04 = 0x04U, + kPUF_KeyIndex_05 = 0x05U, + kPUF_KeyIndex_06 = 0x06U, + kPUF_KeyIndex_07 = 0x07U, + kPUF_KeyIndex_08 = 0x08U, + kPUF_KeyIndex_09 = 0x09U, + kPUF_KeyIndex_10 = 0x0AU, + kPUF_KeyIndex_11 = 0x0BU, + kPUF_KeyIndex_12 = 0x0CU, + kPUF_KeyIndex_13 = 0x0DU, + kPUF_KeyIndex_14 = 0x0EU, + kPUF_KeyIndex_15 = 0x0FU, +} puf_key_index_register_t; + +typedef enum _puf_min_max +{ + kPUF_KeySizeMin = 8u, + kPUF_KeySizeMax = 512u, + kPUF_KeyIndexMax = kPUF_KeyIndex_15, +} puf_min_max_t; + +/*! @brief PUF key slot. */ +typedef enum _puf_key_slot +{ + kPUF_KeySlot0 = 0U, /*!< PUF key slot 0 */ + kPUF_KeySlot1 = 1U, /*!< PUF key slot 1 */ +#if defined(PUF_KEYMASK_COUNT) && (PUF_KEYMASK_COUNT > 2) + kPUF_KeySlot2 = 2U, /*!< PUF key slot 2 */ + kPUF_KeySlot3 = 3U, /*!< PUF key slot 3 */ +#endif +} puf_key_slot_t; + +typedef struct +{ + uint32_t dischargeTimeMsec; + uint32_t coreClockFrequencyHz; +#if defined(FSL_FEATURE_PUF_HAS_SRAM_CTRL) && (FSL_FEATURE_PUF_HAS_SRAM_CTRL > 0) + /* LPCXpresso55s16 */ + PUF_SRAM_CTRL_Type *puf_sram_base; + uint8_t CKGATING; +#endif /* FSL_FEATURE_PUF_HAS_SRAM_CTRL */ +} puf_config_t; +/*! @brief Get Key Code size in bytes from key size in bytes at compile time. */ +#define PUF_GET_KEY_CODE_SIZE_FOR_KEY_SIZE(x) ((160u + (((((x) << 3) + 255u) >> 8) << 8)) >> 3) +#define PUF_MIN_KEY_CODE_SIZE PUF_GET_KEY_CODE_SIZE_FOR_KEY_SIZE(8UL) +#define PUF_ACTIVATION_CODE_SIZE 1192U +#define KEYSTORE_PUF_DISCHARGE_TIME_FIRST_TRY_MS 50 +#define KEYSTORE_PUF_DISCHARGE_TIME_MAX_MS 400 + +/*! PUF status return codes. */ +enum +{ + kStatus_EnrollNotAllowed = MAKE_STATUS(kStatusGroup_PUF, 1), + kStatus_StartNotAllowed = MAKE_STATUS(kStatusGroup_PUF, 2) +}; + +/*! @} */ +/******************************************************************************* + * API + *******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/*! + * @brief Sets the default configuration of PUF + * + * This function initialize PUF config structure to default values. + * + * @param conf PUF configuration structure + */ +void PUF_GetDefaultConfig(puf_config_t *conf); + +/*! + * @brief Initialize PUF + * + * This function enables power to PUF block and waits until the block initializes. + * + * @param base PUF peripheral base address + * @param conf PUF configuration structure + * @return Status of the init operation + */ +status_t PUF_Init(PUF_Type *base, puf_config_t *conf); + +/*! + * @brief Denitialize PUF + * + * This function disables power to PUF SRAM and peripheral clock. + * + * @param base PUF peripheral base address + * @param conf PUF configuration structure + */ +void PUF_Deinit(PUF_Type *base, puf_config_t *conf); + +/*! + * @brief Enroll PUF + * + * This function derives a digital fingerprint, generates the corresponding Activation Code (AC) + * and returns it to be stored in an NVM or a file. This step needs to be + * performed only once for each device. This function may be permanently disallowed by a fuse. + * + * @param base PUF peripheral base address + * @param[out] activationCode Word aligned address of the resulting activation code. + * @param activationCodeSize Size of the activationCode buffer in bytes. Shall be 1192 bytes. + * @return Status of enroll operation. + */ +status_t PUF_Enroll(PUF_Type *base, uint8_t *activationCode, size_t activationCodeSize); + +/*! + * @brief Start PUF + * + * The Activation Code generated during the Enroll operation is used to + * reconstruct the digital fingerprint. This needs to be done after every power-up + * and reset. + * + * @param base PUF peripheral base address + * @param activationCode Word aligned address of the input activation code. + * @param activationCodeSize Size of the activationCode buffer in bytes. Shall be 1192 bytes. + * @return Status of start operation. + */ +status_t PUF_Start(PUF_Type *base, const uint8_t *activationCode, size_t activationCodeSize); + +/*! + * @brief Set intrinsic key + * + * The digital fingerprint generated during the Enroll/Start + * operations is used to generate a Key Code (KC) that defines a unique intrinsic + * key. This KC is returned to be stored in an NVM or a file. This operation + * needs to be done only once for each intrinsic key. + * Each time a Set Intrinsic Key operation is executed a new unique key is + * generated. + * + * @param base PUF peripheral base address + * @param keyIndex PUF key index register + * @param keySize Size of the intrinsic key to generate in bytes. + * @param[out] keyCode Word aligned address of the resulting key code. + * @param keyCodeSize Size of the keyCode buffer in bytes. Shall be PUF_GET_KEY_CODE_SIZE_FOR_KEY_SIZE(keySize). + * @return Status of set intrinsic key operation. + */ +status_t PUF_SetIntrinsicKey( + PUF_Type *base, puf_key_index_register_t keyIndex, size_t keySize, uint8_t *keyCode, size_t keyCodeSize); + +/*! + * @brief Set user key + * + * The digital fingerprint generated during the Enroll/Start + * operations and a user key (UK) provided as input are used to + * generate a Key Code (KC). This KC is sent returned to be stored + * in an NVM or a file. This operation needs to be done only once for each user key. + * + * @param base PUF peripheral base address + * @param keyIndex PUF key index register + * @param userKey Word aligned address of input user key. + * @param userKeySize Size of the input user key in bytes. + * @param[out] keyCode Word aligned address of the resulting key code. + * @param keyCodeSize Size of the keyCode buffer in bytes. Shall be PUF_GET_KEY_CODE_SIZE_FOR_KEY_SIZE(userKeySize). + * @return Status of set user key operation. + */ +status_t PUF_SetUserKey(PUF_Type *base, + puf_key_index_register_t keyIndex, + const uint8_t *userKey, + size_t userKeySize, + uint8_t *keyCode, + size_t keyCodeSize); + +/*! + * @brief Reconstruct key from a key code + * + * The digital fingerprint generated during the Start operation and the KC + * generated during a Set Key operation (Set intrinsic key or Set user key) are used to retrieve a stored key. This + * operation needs to be done every time a key is needed. + * This function accepts only Key Codes created for PUF index registers kPUF_KeyIndex_01 to kPUF_KeyIndex_15. + * + * @param base PUF peripheral base address + * @param keyCode Word aligned address of the input key code. + * @param keyCodeSize Size of the keyCode buffer in bytes. Shall be PUF_GET_KEY_CODE_SIZE_FOR_KEY_SIZE(keySize). + * @param[out] key Word aligned address of output key. + * @param keySize Size of the output key in bytes. + * @return Status of get key operation. + */ +status_t PUF_GetKey(PUF_Type *base, const uint8_t *keyCode, size_t keyCodeSize, uint8_t *key, size_t keySize); + +/*! + * @brief Reconstruct hw bus key from a key code + * + * The digital fingerprint generated during the Start operation and the KC + * generated during a Set Key operation (Set intrinsic key or Set user key) are used to retrieve a stored key. This + * operation needs to be done every time a key is needed. + * This function accepts only Key Codes created for PUF index register kPUF_KeyIndex_00. + * Such a key is output directly to a dedicated hardware bus. The reconstructed key is not exposed to system memory. + * + * @param base PUF peripheral base address + * @param keyCode Word aligned address of the input key code. + * @param keyCodeSize Size of the keyCode buffer in bytes. Shall be PUF_GET_KEY_CODE_SIZE_FOR_KEY_SIZE(keySize). + * @param keySlot key slot to output on hw bus. Parameter is ignored on devices with less than two key slots. + * @param keyMask key masking value. Shall be random for each POR/reset. Value does not have to be cryptographicaly + * secure. + * @return Status of get key operation. + */ +status_t PUF_GetHwKey( + PUF_Type *base, const uint8_t *keyCode, size_t keyCodeSize, puf_key_slot_t keySlot, uint32_t keyMask); + +/*! + * @brief Zeroize PUF + * + * This function clears all PUF internal logic and puts the PUF to error state. + * + * @param base PUF peripheral base address + * @return Status of the zeroize operation. + */ +status_t PUF_Zeroize(PUF_Type *base); + +/*! + * @brief Checks if Get Key operation is allowed. + * + * This function returns true if get key operation is allowed. + * + * @param base PUF peripheral base address + * @return true if get key operation is allowed + */ +bool PUF_IsGetKeyAllowed(PUF_Type *base); + +#if defined(PUF_CFG_BLOCKKEYOUTPUT_MASK) && PUF_CFG_BLOCKKEYOUTPUT_MASK +static inline void PUF_BlockSetKey(PUF_Type *base) +{ + base->CFG |= PUF_CFG_BLOCKKEYOUTPUT_MASK; /* block set key */ +} +#endif /* PUF_CFG_BLOCKKEYOUTPUT_MASK */ + +#if defined(PUF_CFG_PUF_BLOCK_SET_KEY_MASK) && PUF_CFG_PUF_BLOCK_SET_KEY_MASK +static inline void PUF_BlockSetKey(PUF_Type *base) +{ + base->CFG |= PUF_CFG_PUF_BLOCK_SET_KEY_MASK; /* block set key */ +} +#endif /* PUF_CFG_PUF_BLOCK_SET_KEY_MASK */ + +#if defined(PUF_CFG_BLOCKENROLL_SETKEY_MASK) && PUF_CFG_BLOCKENROLL_SETKEY_MASK +static inline void PUF_BlockEnroll(PUF_Type *base) +{ + base->CFG |= PUF_CFG_BLOCKENROLL_SETKEY_MASK; /* block enroll */ +} +#endif /* PUF_CFG_BLOCKENROLL_SETKEY_MASK */ + +#if defined(PUF_CFG_PUF_BLOCK_ENROLL_MASK) && PUF_CFG_PUF_BLOCK_ENROLL_MASK +static inline void PUF_BlockEnroll(PUF_Type *base) +{ + base->CFG |= PUF_CFG_PUF_BLOCK_ENROLL_MASK; /* block enroll */ +} +#endif /* PUF_CFG_PUF_BLOCK_ENROLL_MASK */ + +/*! + * @brief Powercycle PUF + * + * This function make powercycle. + * + * @param base PUF peripheral base address + * @param conf PUF configuration structure + * @return Status of the powercycle operation. + */ +status_t PUF_PowerCycle(PUF_Type *base, puf_config_t *conf); + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +#endif /* _PUF_H_ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_reset.c b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_reset.c new file mode 100644 index 0000000000..4326e0dae2 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_reset.c @@ -0,0 +1,99 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016, NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_common.h" +#include "fsl_reset.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.reset" +#endif + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ + +#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) + +/*! + * brief Assert reset to peripheral. + * + * Asserts reset signal to specified peripheral module. + * + * param peripheral Assert reset to this peripheral. The enum argument contains encoding of reset register + * and reset bit position in the reset register. + */ +void RESET_SetPeripheralReset(reset_ip_name_t peripheral) +{ + const uint32_t regIndex = ((uint32_t)peripheral & 0xFFFF0000u) >> 16; + const uint32_t bitPos = ((uint32_t)peripheral & 0x0000FFFFu); + const uint32_t bitMask = 1UL << bitPos; + + assert(bitPos < 32u); + + /* reset register is in SYSCON */ + /* set bit */ + SYSCON->PRESETCTRLSET[regIndex] = bitMask; + /* wait until it reads 0b1 */ + while (0u == (SYSCON->PRESETCTRLX[regIndex] & bitMask)) + { + } +} + +/*! + * brief Clear reset to peripheral. + * + * Clears reset signal to specified peripheral module, allows it to operate. + * + * param peripheral Clear reset to this peripheral. The enum argument contains encoding of reset register + * and reset bit position in the reset register. + */ +void RESET_ClearPeripheralReset(reset_ip_name_t peripheral) +{ + const uint32_t regIndex = ((uint32_t)peripheral & 0xFFFF0000u) >> 16; + const uint32_t bitPos = ((uint32_t)peripheral & 0x0000FFFFu); + const uint32_t bitMask = 1UL << bitPos; + + assert(bitPos < 32u); + + /* reset register is in SYSCON */ + + /* clear bit */ + SYSCON->PRESETCTRLCLR[regIndex] = bitMask; + /* wait until it reads 0b0 */ + while (bitMask == (SYSCON->PRESETCTRLX[regIndex] & bitMask)) + { + } +} + +/*! + * brief Reset peripheral module. + * + * Reset peripheral module. + * + * param peripheral Peripheral to reset. The enum argument contains encoding of reset register + * and reset bit position in the reset register. + */ +void RESET_PeripheralReset(reset_ip_name_t peripheral) +{ + RESET_SetPeripheralReset(peripheral); + RESET_ClearPeripheralReset(peripheral); +} + +#endif /* FSL_FEATURE_SOC_SYSCON_COUNT || FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_reset.h b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_reset.h new file mode 100644 index 0000000000..3766c890cd --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_reset.h @@ -0,0 +1,267 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016, NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_RESET_H_ +#define _FSL_RESET_H_ + +#include +#include +#include +#include +#include "fsl_device_registers.h" + +/*! + * @addtogroup reset + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief reset driver version 2.0.2. */ +#define FSL_RESET_DRIVER_VERSION (MAKE_VERSION(2, 0, 2)) +/*@}*/ + +/*! + * @brief Enumeration for peripheral reset control bits + * + * Defines the enumeration for peripheral reset control bits in PRESETCTRL/ASYNCPRESETCTRL registers + */ +typedef enum _SYSCON_RSTn +{ + kROM_RST_SHIFT_RSTn = 0 | 1U, /**< ROM reset control */ + kSRAM1_RST_SHIFT_RSTn = 0 | 3U, /**< SRAM1 reset control */ + kSRAM2_RST_SHIFT_RSTn = 0 | 4U, /**< SRAM2 reset control */ + kFLASH_RST_SHIFT_RSTn = 0 | 7U, /**< Flash controller reset control */ + kFMC_RST_SHIFT_RSTn = 0 | 8U, /**< Flash accelerator reset control */ + kMUX0_RST_SHIFT_RSTn = 0 | 11U, /**< Input mux0 reset control */ + kIOCON_RST_SHIFT_RSTn = 0 | 13U, /**< IOCON reset control */ + kGPIO0_RST_SHIFT_RSTn = 0 | 14U, /**< GPIO0 reset control */ + kGPIO1_RST_SHIFT_RSTn = 0 | 15U, /**< GPIO1 reset control */ + kPINT_RST_SHIFT_RSTn = 0 | 18U, /**< Pin interrupt (PINT) reset control */ + kGINT_RST_SHIFT_RSTn = 0 | 19U, /**< Grouped interrupt (PINT) reset control. */ + kDMA0_RST_SHIFT_RSTn = 0 | 20U, /**< DMA reset control */ + kCRC_RST_SHIFT_RSTn = 0 | 21U, /**< CRC reset control */ + kWWDT_RST_SHIFT_RSTn = 0 | 22U, /**< Watchdog timer reset control */ + kRTC_RST_SHIFT_RSTn = 0 | 23U, /**< RTC reset control */ + kMAILBOX_RST_SHIFT_RSTn = 0 | 26U, /**< Mailbox reset control */ + kADC0_RST_SHIFT_RSTn = 0 | 27U, /**< ADC0 reset control */ + + kMRT_RST_SHIFT_RSTn = 65536 | 0U, /**< Multi-rate timer (MRT) reset control */ + kOSTIMER0_RST_SHIFT_RSTn = 65536 | 1U, /**< OSTimer0 reset control */ + kSCT0_RST_SHIFT_RSTn = 65536 | 2U, /**< SCTimer/PWM 0 (SCT0) reset control */ + kMCAN_RST_SHIFT_RSTn = 65536 | 7U, /**< MCAN reset control */ + kUTICK_RST_SHIFT_RSTn = 65536 | 10U, /**< Micro-tick timer reset control */ + kFC0_RST_SHIFT_RSTn = 65536 | 11U, /**< Flexcomm Interface 0 reset control */ + kFC1_RST_SHIFT_RSTn = 65536 | 12U, /**< Flexcomm Interface 1 reset control */ + kFC2_RST_SHIFT_RSTn = 65536 | 13U, /**< Flexcomm Interface 2 reset control */ + kFC3_RST_SHIFT_RSTn = 65536 | 14U, /**< Flexcomm Interface 3 reset control */ + kFC4_RST_SHIFT_RSTn = 65536 | 15U, /**< Flexcomm Interface 4 reset control */ + kFC5_RST_SHIFT_RSTn = 65536 | 16U, /**< Flexcomm Interface 5 reset control */ + kFC6_RST_SHIFT_RSTn = 65536 | 17U, /**< Flexcomm Interface 6 reset control */ + kFC7_RST_SHIFT_RSTn = 65536 | 18U, /**< Flexcomm Interface 7 reset control */ + kCTIMER2_RST_SHIFT_RSTn = 65536 | 22U, /**< CTimer 2 reset control */ + kUSB0D_RST_SHIFT_RSTn = 65536 | 25U, /**< USB0 Device reset control */ + kCTIMER0_RST_SHIFT_RSTn = 65536 | 26U, /**< CTimer 0 reset control */ + kCTIMER1_RST_SHIFT_RSTn = 65536 | 27U, /**< CTimer 1 reset control */ + kEZHA_RST_SHIFT_RSTn = 65536 | 30U, /**< EZHA reset control */ + kEZHB_RST_SHIFT_RSTn = 65536 | 31U, /**< EZHB reset control */ + + kDMA1_RST_SHIFT_RSTn = 131072 | 1U, /**< DMA1 reset control */ + kCMP_RST_SHIFT_RSTn = 131072 | 2U, /**< CMP reset control */ + kUSB1H_RST_SHIFT_RSTn = 131072 | 4U, /**< USBHS Host reset control */ + kUSB1D_RST_SHIFT_RSTn = 131072 | 5U, /**< USBHS Device reset control */ + kUSB1RAM_RST_SHIFT_RSTn = 131072 | 6U, /**< USB RAM reset control */ + kUSB1_RST_SHIFT_RSTn = 131072 | 7U, /**< USBHS reset control */ + kFREQME_RST_SHIFT_RSTn = 131072 | 8U, /**< FREQME reset control */ + kCDOG_RST_SHIFT_RSTn = 131072 | 11U, /**< Code Watchdog reset control */ + kRNG_RST_SHIFT_RSTn = 131072 | 13U, /**< RNG reset control */ + kSYSCTL_RST_SHIFT_RSTn = 131072 | 15U, /**< SYSCTL reset control */ + kUSB0HMR_RST_SHIFT_RSTn = 131072 | 16U, /**< USB0HMR reset control */ + kUSB0HSL_RST_SHIFT_RSTn = 131072 | 17U, /**< USB0HSL reset control */ + kHASHCRYPT_RST_SHIFT_RSTn = 131072 | 18U, /**< HASHCRYPT reset control */ + kPLULUT_RST_SHIFT_RSTn = 131072 | 20U, /**< PLU LUT reset control */ + kCTIMER3_RST_SHIFT_RSTn = 131072 | 21U, /**< CTimer 3 reset control */ + kCTIMER4_RST_SHIFT_RSTn = 131072 | 22U, /**< CTimer 4 reset control */ + kPUF_RST_SHIFT_RSTn = 131072 | 23U, /**< PUF reset control */ + kCASPER_RST_SHIFT_RSTn = 131072 | 24U, /**< CASPER reset control */ + kANALOGCTL_RST_SHIFT_RSTn = 131072 | 27U, /**< ANALOG_CTL reset control */ + kHSLSPI_RST_SHIFT_RSTn = 131072 | 28U, /**< HS LSPI reset control */ + kGPIOSEC_RST_SHIFT_RSTn = 131072 | 29U, /**< GPIO Secure reset control */ + kGPIOSECINT_RST_SHIFT_RSTn = 131072 | 30U, /**< GPIO Secure int reset control */ +} SYSCON_RSTn_t; + +/** Array initializers with peripheral reset bits **/ +#define ADC_RSTS \ + { \ + kADC0_RST_SHIFT_RSTn \ + } /* Reset bits for ADC peripheral */ +#define MCAN_RSTS \ + { \ + kMCAN_RST_SHIFT_RSTn \ + } /* Reset bits for CAN peripheral */ +#define CRC_RSTS \ + { \ + kCRC_RST_SHIFT_RSTn \ + } /* Reset bits for CRC peripheral */ +#define CTIMER_RSTS \ + { \ + kCTIMER0_RST_SHIFT_RSTn, kCTIMER1_RST_SHIFT_RSTn, kCTIMER2_RST_SHIFT_RSTn, kCTIMER3_RST_SHIFT_RSTn, \ + kCTIMER4_RST_SHIFT_RSTn \ + } /* Reset bits for CTIMER peripheral */ +#define DMA_RSTS_N \ + { \ + kDMA0_RST_SHIFT_RSTn, kDMA1_RST_SHIFT_RSTn \ + } /* Reset bits for DMA peripheral */ + +#define FLEXCOMM_RSTS \ + { \ + kFC0_RST_SHIFT_RSTn, kFC1_RST_SHIFT_RSTn, kFC2_RST_SHIFT_RSTn, kFC3_RST_SHIFT_RSTn, kFC4_RST_SHIFT_RSTn, \ + kFC5_RST_SHIFT_RSTn, kFC6_RST_SHIFT_RSTn, kFC7_RST_SHIFT_RSTn, kHSLSPI_RST_SHIFT_RSTn \ + } /* Reset bits for FLEXCOMM peripheral */ +#define GINT_RSTS \ + { \ + kGINT_RST_SHIFT_RSTn, kGINT_RST_SHIFT_RSTn \ + } /* Reset bits for GINT peripheral. GINT0 & GINT1 share same slot */ +#define GPIO_RSTS_N \ + { \ + kGPIO0_RST_SHIFT_RSTn, kGPIO1_RST_SHIFT_RSTn \ + } /* Reset bits for GPIO peripheral */ +#define INPUTMUX_RSTS \ + { \ + kMUX0_RST_SHIFT_RSTn \ + } /* Reset bits for INPUTMUX peripheral */ +#define IOCON_RSTS \ + { \ + kIOCON_RST_SHIFT_RSTn \ + } /* Reset bits for IOCON peripheral */ +#define FLASH_RSTS \ + { \ + kFLASH_RST_SHIFT_RSTn, kFMC_RST_SHIFT_RSTn \ + } /* Reset bits for Flash peripheral */ +#define MRT_RSTS \ + { \ + kMRT_RST_SHIFT_RSTn \ + } /* Reset bits for MRT peripheral */ +#define PINT_RSTS \ + { \ + kPINT_RST_SHIFT_RSTn \ + } /* Reset bits for PINT peripheral */ +#define CDOG_RSTS \ + { \ + kCDOG_RST_SHIFT_RSTn \ + } /* Reset bits for CDOG peripheral */ +#define RNG_RSTS \ + { \ + kRNG_RST_SHIFT_RSTn \ + } /* Reset bits for RNG peripheral */ +#define SCT_RSTS \ + { \ + kSCT0_RST_SHIFT_RSTn \ + } /* Reset bits for SCT peripheral */ +#define USB0D_RST \ + { \ + kUSB0D_RST_SHIFT_RSTn \ + } /* Reset bits for USB0D peripheral */ +#define USB0HMR_RST \ + { \ + kUSB0HMR_RST_SHIFT_RSTn \ + } /* Reset bits for USB0HMR peripheral */ +#define USB0HSL_RST \ + { \ + kUSB0HSL_RST_SHIFT_RSTn \ + } /* Reset bits for USB0HSL peripheral */ +#define USB1H_RST \ + { \ + kUSB1H_RST_SHIFT_RSTn \ + } /* Reset bits for USB1H peripheral */ +#define USB1D_RST \ + { \ + kUSB1D_RST_SHIFT_RSTn \ + } /* Reset bits for USB1D peripheral */ +#define USB1RAM_RST \ + { \ + kUSB1RAM_RST_SHIFT_RSTn \ + } /* Reset bits for USB1RAM peripheral */ +#define UTICK_RSTS \ + { \ + kUTICK_RST_SHIFT_RSTn \ + } /* Reset bits for UTICK peripheral */ +#define WWDT_RSTS \ + { \ + kWWDT_RST_SHIFT_RSTn \ + } /* Reset bits for WWDT peripheral */ +#define PLU_RSTS_N \ + { \ + kPLULUT_RST_SHIFT_RSTn \ + } /* Reset bits for PLU peripheral */ +#define OSTIMER_RSTS \ + { \ + kOSTIMER0_RST_SHIFT_RSTn \ + } /* Reset bits for OSTIMER peripheral */ +#define CASPER_RSTS \ + { \ + kCASPER_RST_SHIFT_RSTn \ + } /* Reset bits for Casper peripheral */ +#define HASHCRYPT_RSTS \ + { \ + kHASHCRYPT_RST_SHIFT_RSTn \ + } /* Reset bits for Hashcrypt peripheral */ +#define PUF_RSTS \ + { \ + kPUF_RST_SHIFT_RSTn \ + } /* Reset bits for PUF peripheral */ +typedef SYSCON_RSTn_t reset_ip_name_t; + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Assert reset to peripheral. + * + * Asserts reset signal to specified peripheral module. + * + * @param peripheral Assert reset to this peripheral. The enum argument contains encoding of reset register + * and reset bit position in the reset register. + */ +void RESET_SetPeripheralReset(reset_ip_name_t peripheral); + +/*! + * @brief Clear reset to peripheral. + * + * Clears reset signal to specified peripheral module, allows it to operate. + * + * @param peripheral Clear reset to this peripheral. The enum argument contains encoding of reset register + * and reset bit position in the reset register. + */ +void RESET_ClearPeripheralReset(reset_ip_name_t peripheral); + +/*! + * @brief Reset peripheral module. + * + * Reset peripheral module. + * + * @param peripheral Peripheral to reset. The enum argument contains encoding of reset register + * and reset bit position in the reset register. + */ +void RESET_PeripheralReset(reset_ip_name_t peripheral); + +#if defined(__cplusplus) +} +#endif + +/*! @} */ + +#endif /* _FSL_RESET_H_ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_rng.c b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_rng.c new file mode 100644 index 0000000000..1b2e9d4d61 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_rng.c @@ -0,0 +1,212 @@ +/* + * Copyright 2017, 2019, 2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_rng.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.rng_1" +#endif + +/******************************************************************************* + * Definitions + *******************************************************************************/ + +/******************************************************************************* + * Prototypes + *******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +static void rng_accumulateEntropy(RNG_Type *base) +{ + uint32_t minChiSq; + uint32_t maxChiSq; + + /* Steps to accumulate entropy, more info can be found in LPC55SXX UM*/ + + /* Select fourth clock on which to compute CHI SQUARE statistics*/ + base->COUNTER_CFG = (base->COUNTER_CFG & ~RNG_COUNTER_CFG_CLOCK_SEL_MASK) | RNG_COUNTER_CFG_CLOCK_SEL(4U); + + /* Activate CHI computing */ + base->ONLINE_TEST_CFG = RNG_ONLINE_TEST_CFG_ACTIVATE(1U); + + /* Read min chi squared value, on power on should be higher than max chi squared value */ + minChiSq = ((base->ONLINE_TEST_VAL & RNG_ONLINE_TEST_VAL_MIN_CHI_SQUARED_MASK) >> + RNG_ONLINE_TEST_VAL_MIN_CHI_SQUARED_SHIFT); + + /* Read max chi squared value */ + maxChiSq = ((base->ONLINE_TEST_VAL & RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED_MASK) >> + RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED_SHIFT); + + /* Wait until minChiSq decreases and become smaller than maxChiSq*/ + while (minChiSq > (maxChiSq - 1U)) + { + maxChiSq = ((base->ONLINE_TEST_VAL & RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED_MASK) >> + RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED_SHIFT); + minChiSq = ((base->ONLINE_TEST_VAL & RNG_ONLINE_TEST_VAL_MIN_CHI_SQUARED_MASK) >> + RNG_ONLINE_TEST_VAL_MIN_CHI_SQUARED_SHIFT); + } +} + +/*! + * @brief Gets a entry data from the RNG. + * + * This function gets an entropy data from RNG. + */ +static uint32_t rng_readEntropy(RNG_Type *base) +{ + uint32_t data; + uint32_t refreshCnt, maxChiSq, tmpShift4x; + + /* Activate CHI computing */ + base->ONLINE_TEST_CFG = RNG_ONLINE_TEST_CFG_ACTIVATE(1); + + /* Wait for refresh count become 31 to refill fresh entropy since last read of random number*/ + do + { + refreshCnt = ((base->COUNTER_VAL & RNG_COUNTER_VAL_REFRESH_CNT_MASK) >> RNG_COUNTER_VAL_REFRESH_CNT_SHIFT); + } while (refreshCnt < 31U); + + /* reading RANDOM_NUMBER register will reset refCnt to 0 */ + data = base->RANDOM_NUMBER; + + /* Perform CHI computing by checking max chi squared value */ + /* Wait until maxChiSq become smaller or equal than 4, then next random number can be read*/ + maxChiSq = ((base->ONLINE_TEST_VAL & RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED_MASK) >> + RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED_SHIFT); + + while (maxChiSq > 4U) + { + /* Deactivate CHI computing to reset*/ + base->ONLINE_TEST_CFG = RNG_ONLINE_TEST_CFG_ACTIVATE(0); + + /* read Shift4x register, if is less than 7 increment it and then start accumulating entropy again */ + tmpShift4x = ((base->COUNTER_CFG & RNG_COUNTER_CFG_SHIFT4X_MASK) >> RNG_COUNTER_CFG_SHIFT4X_SHIFT); + if (tmpShift4x < 7U) + { + tmpShift4x++; + base->COUNTER_CFG = + (base->COUNTER_CFG & ~RNG_COUNTER_CFG_SHIFT4X_MASK) | RNG_COUNTER_CFG_SHIFT4X(tmpShift4x); + } + rng_accumulateEntropy(base); + + maxChiSq = ((base->ONLINE_TEST_VAL & RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED_MASK) >> + RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED_SHIFT); + } + + return data; +} + +void RNG_Init(RNG_Type *base) +{ + uint32_t maxChiSq, tmpShift4x; + + /* Clear ring oscilator disable bit*/ + PMC->PDRUNCFGCLR0 = PMC_PDRUNCFG0_PDEN_RNG_MASK; +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + CLOCK_EnableClock(kCLOCK_Rng); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) + /* Reset the module. */ + RESET_PeripheralReset(kRNG_RST_SHIFT_RSTn); +#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ + + /* Turn on CHI Squared test */ + /* Activate CHI computing and wait until min chi squared become smaller than max chi squared */ + rng_accumulateEntropy(base); + + maxChiSq = ((base->ONLINE_TEST_VAL & RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED_MASK) >> + RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED_SHIFT); + + /* When maxChiSq is bigger than 4 its assumed there is not enough entropy and previous steps are repeated */ + /* When maxChiSq is 4 or less initialization is complete and random number can be read*/ + while (maxChiSq > 4U) + { + /* Deactivate CHI coputing to reset*/ + base->ONLINE_TEST_CFG = RNG_ONLINE_TEST_CFG_ACTIVATE(0); + + /* read Shift4x register, if is less than 7 increment it and then start accumulating entropy again */ + tmpShift4x = ((base->COUNTER_CFG & RNG_COUNTER_CFG_SHIFT4X_MASK) >> RNG_COUNTER_CFG_SHIFT4X_SHIFT); + if (tmpShift4x < 7U) + { + tmpShift4x++; + base->COUNTER_CFG = + (base->COUNTER_CFG & ~RNG_COUNTER_CFG_SHIFT4X_MASK) | RNG_COUNTER_CFG_SHIFT4X(tmpShift4x); + } + rng_accumulateEntropy(base); + + maxChiSq = ((base->ONLINE_TEST_VAL & RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED_MASK) >> + RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED_SHIFT); + } +} + +void RNG_Deinit(RNG_Type *base) +{ + /* Set ring oscilator disable bit*/ + PMC->PDRUNCFGSET0 = PMC_PDRUNCFG0_PDEN_RNG_MASK; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) + /* Reset the module. */ + RESET_PeripheralReset(kRNG_RST_SHIFT_RSTn); +#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + CLOCK_DisableClock(kCLOCK_Rng); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +status_t RNG_GetRandomData(RNG_Type *base, void *data, size_t dataSize) +{ + status_t result = kStatus_Fail; + uint32_t random32; + uint32_t randomSize; + uint8_t *pRandom; + uint8_t *pData = (uint8_t *)data; + uint32_t i; + + /* Check input parameters.*/ + if (!((base != NULL) && (data != NULL) && (dataSize != 0U))) + { + result = kStatus_InvalidArgument; + } + else + { + /* Check that ring oscilator is enabled */ + if (0U == (PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_RNG_MASK)) + { + do + { + /* Read Entropy.*/ + random32 = rng_readEntropy(base); + pRandom = (uint8_t *)&random32; + + if (dataSize < sizeof(random32)) + { + randomSize = dataSize; + } + else + { + randomSize = sizeof(random32); + } + + for (i = 0; i < randomSize; i++) + { + *pData++ = *pRandom++; + } + + dataSize -= randomSize; + } while (dataSize > 0U); + + result = kStatus_Success; + } + } + + return result; +} diff --git a/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_rng.h b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_rng.h new file mode 100644 index 0000000000..38279cad7f --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_rng.h @@ -0,0 +1,104 @@ +/* + * Copyright 2017, 2019, 2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_RNG_DRIVER_H_ +#define _FSL_RNG_DRIVER_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup rng + * @{ + */ + +/******************************************************************************* + * Definitions + *******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief RNG driver version. Version 2.0.3. + * + * Current version: 2.0.3 + * + * Change log: + * - Version 2.0.0 + * - Initial version + * + * - Version 2.0.1 + * - Fix MISRA C-2012 issue. + * + * - Version 2.0.2 + * - Add RESET_PeripheralReset function inside RNG_Init and RNG_Deinit functions. + * + * - Version 2.0.3 + * - Modified RNG_Init and RNG_GetRandomData functions, added rng_accumulateEntropy and rng_readEntropy functions. + * - These changes are reflecting recommended usage of RNG according to device UM. + */ +#define FSL_RNG_DRIVER_VERSION (MAKE_VERSION(2, 0, 3)) +/*@}*/ + +/******************************************************************************* + * API + *******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Initializes the RNG. + * + * This function initializes the RNG. + * When called, the RNG module and ring oscillator is enabled. + * + * @param base RNG base address + * @return If successful, returns the kStatus_RNG_Success. Otherwise, it returns an error. + */ +void RNG_Init(RNG_Type *base); + +/*! + * @brief Shuts down the RNG. + * + * This function shuts down the RNG. + * + * @param base RNG base address. + */ +void RNG_Deinit(RNG_Type *base); + +/*! + * @brief Gets random data. + * + * This function gets random data from the RNG. + * + * @param base RNG base address. + * @param data Pointer address used to store random data. + * @param dataSize Size of the buffer pointed by the data parameter. + * @return random data + */ +status_t RNG_GetRandomData(RNG_Type *base, void *data, size_t dataSize); + +/*! + * @brief Returns random 32-bit number. + * + * This function gets random number from the RNG. + * + * @param base RNG base address. + * @return random number + */ +static inline uint32_t RNG_GetRandomWord(RNG_Type *base) +{ + return base->RANDOM_NUMBER; +} + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /*_FSL_RNG_H_*/ diff --git a/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_rtc.c b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_rtc.c new file mode 100644 index 0000000000..b39370b683 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_rtc.c @@ -0,0 +1,322 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_rtc.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.lpc_rtc" +#endif + +#define SECONDS_IN_A_DAY (86400U) +#define SECONDS_IN_A_HOUR (3600U) +#define SECONDS_IN_A_MINUTE (60U) +#define DAYS_IN_A_YEAR (365U) +#define YEAR_RANGE_START (1970U) +#define YEAR_RANGE_END (2099U) + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Check whether the date and time passed in is valid + * + * @param datetime Pointer to structure where the date and time details are stored + * + * @return Returns false if the date & time details are out of range; true if in range + */ +static bool RTC_CheckDatetimeFormat(const rtc_datetime_t *datetime); + +/*! + * @brief Convert time data from datetime to seconds + * + * @param datetime Pointer to datetime structure where the date and time details are stored + * + * @return The result of the conversion in seconds + */ +static uint32_t RTC_ConvertDatetimeToSeconds(const rtc_datetime_t *datetime); + +/*! + * @brief Convert time data from seconds to a datetime structure + * + * @param seconds Seconds value that needs to be converted to datetime format + * @param datetime Pointer to the datetime structure where the result of the conversion is stored + */ +static void RTC_ConvertSecondsToDatetime(uint32_t seconds, rtc_datetime_t *datetime); + +/******************************************************************************* + * Code + ******************************************************************************/ +static bool RTC_CheckDatetimeFormat(const rtc_datetime_t *datetime) +{ + assert(datetime); + + /* Table of days in a month for a non leap year. First entry in the table is not used, + * valid months start from 1 + */ + uint8_t daysPerMonth[] = {0U, 31U, 28U, 31U, 30U, 31U, 30U, 31U, 31U, 30U, 31U, 30U, 31U}; + + /* Check year, month, hour, minute, seconds */ + if ((datetime->year < YEAR_RANGE_START) || (datetime->year > YEAR_RANGE_END) || (datetime->month > 12U) || + (datetime->month < 1U) || (datetime->hour >= 24U) || (datetime->minute >= 60U) || (datetime->second >= 60U)) + { + /* If not correct then error*/ + return false; + } + + /* Adjust the days in February for a leap year */ + if ((((datetime->year & 3U) == 0U) && (datetime->year % 100U != 0U)) || (datetime->year % 400U == 0U)) + { + daysPerMonth[2] = 29U; + } + + /* Check the validity of the day */ + if ((datetime->day > daysPerMonth[datetime->month]) || (datetime->day < 1U)) + { + return false; + } + + return true; +} + +static uint32_t RTC_ConvertDatetimeToSeconds(const rtc_datetime_t *datetime) +{ + assert(datetime); + + /* Number of days from begin of the non Leap-year*/ + /* Number of days from begin of the non Leap-year*/ + uint16_t monthDays[] = {0U, 0U, 31U, 59U, 90U, 120U, 151U, 181U, 212U, 243U, 273U, 304U, 334U}; + uint32_t seconds; + + /* Compute number of days from 1970 till given year*/ + seconds = ((uint32_t)datetime->year - 1970U) * DAYS_IN_A_YEAR; + /* Add leap year days */ + seconds += (((uint32_t)datetime->year / 4U) - (1970U / 4U)); + /* Add number of days till given month*/ + seconds += monthDays[datetime->month]; + /* Add days in given month. We subtract the current day as it is + * represented in the hours, minutes and seconds field*/ + seconds += ((uint32_t)datetime->day - 1U); + /* For leap year if month less than or equal to Febraury, decrement day counter*/ + if (((datetime->year & 3U) == 0x00U) && (datetime->month <= 2U)) + { + seconds--; + } + + seconds = (seconds * SECONDS_IN_A_DAY) + (datetime->hour * SECONDS_IN_A_HOUR) + + (datetime->minute * SECONDS_IN_A_MINUTE) + datetime->second; + + return seconds; +} + +static void RTC_ConvertSecondsToDatetime(uint32_t seconds, rtc_datetime_t *datetime) +{ + assert(datetime); + + uint8_t i; + uint16_t daysInYear; + uint32_t secondsRemaining; + uint32_t days; + /* Table of days in a month for a non leap year. First entry in the table is not used, + * valid months start from 1 + */ + uint8_t daysPerMonth[] = {0U, 31U, 28U, 31U, 30U, 31U, 30U, 31U, 31U, 30U, 31U, 30U, 31U}; + + /* Start with the seconds value that is passed in to be converted to date time format */ + secondsRemaining = seconds; + + /* Calcuate the number of days, we add 1 for the current day which is represented in the + * hours and seconds field + */ + days = secondsRemaining / SECONDS_IN_A_DAY + 1U; + + /* Update seconds left*/ + secondsRemaining = secondsRemaining % SECONDS_IN_A_DAY; + + /* Calculate the datetime hour, minute and second fields */ + datetime->hour = (uint8_t)(secondsRemaining / SECONDS_IN_A_HOUR); + secondsRemaining = secondsRemaining % SECONDS_IN_A_HOUR; + datetime->minute = (uint8_t)(secondsRemaining / 60U); + datetime->second = (uint8_t)(secondsRemaining % SECONDS_IN_A_MINUTE); + + /* Calculate year */ + daysInYear = DAYS_IN_A_YEAR; + datetime->year = YEAR_RANGE_START; + while (days > daysInYear) + { + /* Decrease day count by a year and increment year by 1 */ + days -= daysInYear; + datetime->year++; + + /* Adjust the number of days for a leap year */ + if ((datetime->year & 3U) != 0x00U) + { + daysInYear = DAYS_IN_A_YEAR; + } + else + { + daysInYear = DAYS_IN_A_YEAR + 1U; + } + } + + /* Adjust the days in February for a leap year */ + if ((datetime->year & 3U) == 0x00U) + { + daysPerMonth[2] = 29U; + } + + for (i = 1U; i <= 12U; i++) + { + if (days <= daysPerMonth[i]) + { + datetime->month = i; + break; + } + else + { + days -= daysPerMonth[i]; + } + } + + datetime->day = (uint8_t)days; +} + +/*! + * brief Ungate the RTC clock and enables the RTC oscillator. + * + * note This API should be called at the beginning of the application using the RTC driver. + * + * param base RTC peripheral base address + */ +void RTC_Init(RTC_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable the RTC peripheral clock */ + CLOCK_EnableClock(kCLOCK_Rtc); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if !(defined(FSL_FEATURE_RTC_HAS_NO_RESET) && FSL_FEATURE_RTC_HAS_NO_RESET) + RESET_PeripheralReset(kRTC_RST_SHIFT_RSTn); +#endif + /* Make sure the reset bit is cleared */ + base->CTRL &= ~RTC_CTRL_SWRESET_MASK; + +#if !(defined(FSL_FEATURE_RTC_HAS_NO_OSC_PD) && FSL_FEATURE_RTC_HAS_NO_OSC_PD) + /* Make sure the RTC OSC is powered up */ + base->CTRL &= ~RTC_CTRL_RTC_OSC_PD_MASK; +#endif +} + +/*! + * brief Set the RTC date and time according to the given time structure. + * + * The RTC counter must be stopped prior to calling this function as writes to the RTC + * seconds register will fail if the RTC counter is running. + * + * param base RTC peripheral base address + * param datetime Pointer to structure where the date and time details to set are stored + * + * return kStatus_Success: Success in setting the time and starting the RTC + * kStatus_InvalidArgument: Error because the datetime format is incorrect + */ +status_t RTC_SetDatetime(RTC_Type *base, const rtc_datetime_t *datetime) +{ + assert(datetime); + + /* Return error if the time provided is not valid */ + if (!(RTC_CheckDatetimeFormat(datetime))) + { + return kStatus_InvalidArgument; + } + + /* Set time in seconds */ + base->COUNT = RTC_ConvertDatetimeToSeconds(datetime); + + return kStatus_Success; +} + +/*! + * brief Gets the RTC time and stores it in the given time structure. + * + * param base RTC peripheral base address + * param datetime Pointer to structure where the date and time details are stored. + */ +void RTC_GetDatetime(RTC_Type *base, rtc_datetime_t *datetime) +{ + assert(datetime); + + uint32_t seconds = 0; + + seconds = RTC_GetSecondsTimerCount(base); + RTC_ConvertSecondsToDatetime(seconds, datetime); +} + +/*! + * brief Set the RTC alarm time + * + * The function checks whether the specified alarm time is greater than the present + * time. If not, the function does not set the alarm and returns an error. + * + * param base RTC peripheral base address + * param alarmTime Pointer to structure where the alarm time is stored. + * + * return kStatus_Success: success in setting the RTC alarm + * kStatus_InvalidArgument: Error because the alarm datetime format is incorrect + * kStatus_Fail: Error because the alarm time has already passed + */ +status_t RTC_SetAlarm(RTC_Type *base, const rtc_datetime_t *alarmTime) +{ + assert(alarmTime != NULL); + + uint32_t alarmSeconds = 0; + uint32_t currSeconds = 0; + + /* Return error if the alarm time provided is not valid */ + if (!(RTC_CheckDatetimeFormat(alarmTime))) + { + return kStatus_InvalidArgument; + } + + alarmSeconds = RTC_ConvertDatetimeToSeconds(alarmTime); + + /* Get the current time */ + currSeconds = RTC_GetSecondsTimerCount(base); + + /* Return error if the alarm time has passed */ + if (alarmSeconds < currSeconds) + { + return kStatus_Fail; + } + + /* Set alarm in seconds*/ + base->MATCH = alarmSeconds; + + return kStatus_Success; +} + +/*! + * brief Return the RTC alarm time. + * + * param base RTC peripheral base address + * param datetime Pointer to structure where the alarm date and time details are stored. + */ +void RTC_GetAlarm(RTC_Type *base, rtc_datetime_t *datetime) +{ + assert(datetime); + + uint32_t alarmSeconds = 0; + + /* Get alarm in seconds */ + alarmSeconds = base->MATCH; + + RTC_ConvertSecondsToDatetime(alarmSeconds, datetime); +} diff --git a/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_rtc.h b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_rtc.h new file mode 100644 index 0000000000..a960d8baf7 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_rtc.h @@ -0,0 +1,493 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_RTC_H_ +#define _FSL_RTC_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup rtc + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +#define FSL_RTC_DRIVER_VERSION (MAKE_VERSION(2, 1, 2)) /*!< Version 2.1.2 */ +/*@}*/ + +/*! @brief List of RTC interrupts */ +typedef enum _rtc_interrupt_enable +{ + kRTC_AlarmInterruptEnable = RTC_CTRL_ALARMDPD_EN_MASK, /*!< Alarm interrupt.*/ + kRTC_WakeupInterruptEnable = RTC_CTRL_WAKEDPD_EN_MASK /*!< Wake-up interrupt.*/ +} rtc_interrupt_enable_t; + +/*! @brief List of RTC flags */ +typedef enum _rtc_status_flags +{ + kRTC_AlarmFlag = RTC_CTRL_ALARM1HZ_MASK, /*!< Alarm flag*/ + kRTC_WakeupFlag = RTC_CTRL_WAKE1KHZ_MASK /*!< 1kHz wake-up timer flag*/ +} rtc_status_flags_t; + +/*! @brief Structure is used to hold the date and time */ +typedef struct _rtc_datetime +{ + uint16_t year; /*!< Range from 1970 to 2099.*/ + uint8_t month; /*!< Range from 1 to 12.*/ + uint8_t day; /*!< Range from 1 to 31 (depending on month).*/ + uint8_t hour; /*!< Range from 0 to 23.*/ + uint8_t minute; /*!< Range from 0 to 59.*/ + uint8_t second; /*!< Range from 0 to 59.*/ +} rtc_datetime_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Un-gate the RTC clock and enable the RTC oscillator. + * + * @note This API should be called at the beginning of the application using the RTC driver. + * + * @param base RTC peripheral base address + */ +void RTC_Init(RTC_Type *base); + +/*! + * @brief Stop the timer and gate the RTC clock + * + * @param base RTC peripheral base address + */ +static inline void RTC_Deinit(RTC_Type *base) +{ + /* Stop the RTC timer */ + base->CTRL &= ~RTC_CTRL_RTC_EN_MASK; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Gate the module clock */ + CLOCK_DisableClock(kCLOCK_Rtc); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/*! @}*/ + +/*! + * @name Current Time & Alarm + * @{ + */ + +/*! + * @brief Set the RTC date and time according to the given time structure. + * + * The RTC counter must be stopped prior to calling this function as writes to the RTC + * seconds register will fail if the RTC counter is running. + * + * @param base RTC peripheral base address + * @param datetime Pointer to structure where the date and time details to set are stored + * + * @return kStatus_Success: Success in setting the time and starting the RTC + * kStatus_InvalidArgument: Error because the datetime format is incorrect + */ +status_t RTC_SetDatetime(RTC_Type *base, const rtc_datetime_t *datetime); + +/*! + * @brief Get the RTC time and stores it in the given time structure. + * + * @param base RTC peripheral base address + * @param datetime Pointer to structure where the date and time details are stored. + */ +void RTC_GetDatetime(RTC_Type *base, rtc_datetime_t *datetime); + +/*! + * @brief Set the RTC alarm time + * + * The function checks whether the specified alarm time is greater than the present + * time. If not, the function does not set the alarm and returns an error. + * + * @param base RTC peripheral base address + * @param alarmTime Pointer to structure where the alarm time is stored. + * + * @return kStatus_Success: success in setting the RTC alarm + * kStatus_InvalidArgument: Error because the alarm datetime format is incorrect + * kStatus_Fail: Error because the alarm time has already passed + */ +status_t RTC_SetAlarm(RTC_Type *base, const rtc_datetime_t *alarmTime); + +/*! + * @brief Return the RTC alarm time. + * + * @param base RTC peripheral base address + * @param datetime Pointer to structure where the alarm date and time details are stored. + */ +void RTC_GetAlarm(RTC_Type *base, rtc_datetime_t *datetime); + +/*! @}*/ + +/*! + * @name RTC wake-up timer (1KHZ) Enable + * @{ + */ + +/*! + * @brief Enable the RTC wake-up timer (1KHZ). + * + * After calling this function, the RTC driver will use/un-use the RTC wake-up (1KHZ) at the same time. + * + * @param base RTC peripheral base address + * @param enable Use/Un-use the RTC wake-up timer. + * - true: Use RTC wake-up timer at the same time. + * - false: Un-use RTC wake-up timer, RTC only use the normal seconds timer by default. + */ +static inline void RTC_EnableWakeupTimer(RTC_Type *base, bool enable) +{ + if (enable) + { + base->CTRL |= RTC_CTRL_RTC1KHZ_EN_MASK; + } + else + { + base->CTRL &= ~RTC_CTRL_RTC1KHZ_EN_MASK; + } +} + +/*! + * @brief Get the enabled status of the RTC wake-up timer (1KHZ). + * + + * @param base RTC peripheral base address + * + * @return The enabled status of RTC wake-up timer (1KHZ). + */ +static inline uint32_t RTC_GetEnabledWakeupTimer(RTC_Type *base) +{ + return (base->CTRL & RTC_CTRL_RTC1KHZ_EN_MASK); +} + +/*! @}*/ + +/*! + * @brief Set the RTC seconds timer (1HZ) MATCH value. + * + * @param base RTC peripheral base address + * @param matchValue The value to be set into the RTC MATCH register + */ +static inline void RTC_SetSecondsTimerMatch(RTC_Type *base, uint32_t matchValue) +{ + /* Set the start match value into the default RTC seconds timer (1HZ). */ + base->MATCH = matchValue; +} + +/*! + * @brief Read actual RTC seconds timer (1HZ) MATCH value. + * + * @param base RTC peripheral base address + * + * @return The actual RTC seconds timer (1HZ) MATCH value. + */ +static inline uint32_t RTC_GetSecondsTimerMatch(RTC_Type *base) +{ + /* Read the RTC default seconds timer (1HZ) MATCH value. */ + return base->MATCH; +} + +/*! + * @brief Set the RTC seconds timer (1HZ) COUNT value. + * + * @param base RTC peripheral base address + * @param countValue The value to be loaded into the RTC COUNT register + */ +static inline void RTC_SetSecondsTimerCount(RTC_Type *base, uint32_t countValue) +{ + /* Set the start count value into the default RTC seconds timer (1HZ). */ + base->COUNT = countValue; +} + +/*! + * @brief Read the actual RTC seconds timer (1HZ) COUNT value. + * + * @param base RTC peripheral base address + * + * @return The actual RTC seconds timer (1HZ) COUNT value. + */ +static inline uint32_t RTC_GetSecondsTimerCount(RTC_Type *base) +{ + uint32_t a, b; + + /* Follow the RF document to read the RTC default seconds timer (1HZ) counter value. */ + do + { + a = base->COUNT; + b = base->COUNT; + } while (a != b); + + return b; +} + +/*! + * @brief Enable the RTC wake-up timer (1KHZ) and set countdown value to the RTC WAKE register. + * + * @param base RTC peripheral base address + * @param wakeupValue The value to be loaded into the WAKE register in RTC wake-up timer (1KHZ). + */ +static inline void RTC_SetWakeupCount(RTC_Type *base, uint16_t wakeupValue) +{ + /* Use the RTC wake-up timer (1KHZ) */ + base->CTRL |= RTC_CTRL_RTC1KHZ_EN_MASK; + + /* Set the start countdown value into the RTC WAKE register */ + base->WAKE = RTC_WAKE_VAL((uint32_t)wakeupValue); +} + +/*! + * @brief Read the actual value from the WAKE register value in RTC wake-up timer (1KHZ). + * + * @param base RTC peripheral base address + * + * @return The actual value of the WAKE register value in RTC wake-up timer (1HZ). + */ +static inline uint16_t RTC_GetWakeupCount(RTC_Type *base) +{ + /* Read current wake-up countdown value */ + return (uint16_t)((base->WAKE & RTC_WAKE_VAL_MASK) >> RTC_WAKE_VAL_SHIFT); +} + +/*! + * @name Interrupt Interface + * @{ + */ + +/*! + * @brief Enable the wake-up timer interrupt from deep power down mode. + * + * @param base RTC peripheral base address + * @param enable Enable/Disable wake-up timer interrupt from deep power down mode. + * - true: Enable wake-up timer interrupt from deep power down mode. + * - false: Disable wake-up timer interrupt from deep power down mode. + */ +static inline void RTC_EnableWakeUpTimerInterruptFromDPD(RTC_Type *base, bool enable) +{ + if (enable) + { + base->CTRL |= RTC_CTRL_WAKEDPD_EN_MASK; + } + else + { + base->CTRL &= ~RTC_CTRL_WAKEDPD_EN_MASK; + } +} + +/*! + * @brief Enable the alarm timer interrupt from deep power down mode. + * + * @param base RTC peripheral base address + * @param enable Enable/Disable alarm timer interrupt from deep power down mode. + * - true: Enable alarm timer interrupt from deep power down mode. + * - false: Disable alarm timer interrupt from deep power down mode. + */ +static inline void RTC_EnableAlarmTimerInterruptFromDPD(RTC_Type *base, bool enable) +{ + if (enable) + { + base->CTRL |= RTC_CTRL_ALARMDPD_EN_MASK; + } + else + { + base->CTRL &= ~RTC_CTRL_ALARMDPD_EN_MASK; + } +} + +/*! + * @brief Enables the selected RTC interrupts. + * @deprecated Do not use this function. It has been superceded by @ref RTC_EnableAlarmTimerInterruptFromDPD + * and RTC_EnableWakeUpTimerInterruptFromDPD + * + * @param base RTC peripheral base address + * @param mask The interrupts to enable. This is a logical OR of members of the + * enumeration ::rtc_interrupt_enable_t + */ +static inline void RTC_EnableInterrupts(RTC_Type *base, uint32_t mask) +{ + uint32_t reg = base->CTRL; + + /* Clear flag bits to prevent accidentally clearing anything when writing back */ + reg &= ~(RTC_CTRL_ALARM1HZ_MASK | RTC_CTRL_WAKE1KHZ_MASK); + reg |= mask; + + base->CTRL = reg; +} + +/*! + * @brief Disables the selected RTC interrupts. + * @deprecated Do not use this function. It has been superceded by @ref RTC_EnableAlarmTimerInterruptFromDPD + * and RTC_EnableWakeUpTimerInterruptFromDPD + * + * @param base RTC peripheral base address + * @param mask The interrupts to enable. This is a logical OR of members of the + * enumeration ::rtc_interrupt_enable_t + */ +static inline void RTC_DisableInterrupts(RTC_Type *base, uint32_t mask) +{ + uint32_t reg = base->CTRL; + + /* Clear flag bits to prevent accidentally clearing anything when writing back */ + reg &= ~(RTC_CTRL_ALARM1HZ_MASK | RTC_CTRL_WAKE1KHZ_MASK | mask); + + base->CTRL = reg; +} + +/*! + * @brief Get the enabled RTC interrupts. + * @deprecated Do not use this function. It will be deleted in next release version. + * + * @param base RTC peripheral base address + * + * @return The enabled interrupts. This is the logical OR of members of the + * enumeration ::rtc_interrupt_enable_t + */ +static inline uint32_t RTC_GetEnabledInterrupts(RTC_Type *base) +{ + return (base->CTRL & (RTC_CTRL_ALARMDPD_EN_MASK | RTC_CTRL_WAKEDPD_EN_MASK)); +} + +/*! @}*/ + +/*! + * @name Status Interface + * @{ + */ + +/*! + * @brief Get the RTC status flags + * + * @param base RTC peripheral base address + * + * @return The status flags. This is the logical OR of members of the + * enumeration ::rtc_status_flags_t + */ +static inline uint32_t RTC_GetStatusFlags(RTC_Type *base) +{ + return (base->CTRL & (RTC_CTRL_ALARM1HZ_MASK | RTC_CTRL_WAKE1KHZ_MASK)); +} + +/*! + * @brief Clear the RTC status flags. + * + * @param base RTC peripheral base address + * @param mask The status flags to clear. This is a logical OR of members of the + * enumeration ::rtc_status_flags_t + */ +static inline void RTC_ClearStatusFlags(RTC_Type *base, uint32_t mask) +{ + uint32_t reg = base->CTRL; + + /* Clear flag bits to prevent accidentally clearing anything when writing back */ + reg &= ~(RTC_CTRL_ALARM1HZ_MASK | RTC_CTRL_WAKE1KHZ_MASK); + + /* Write 1 to the flags we wish to clear */ + reg |= mask; + + base->CTRL = reg; +} + +/*! @}*/ + +/*! + * @name Timer Enable + * @{ + */ + +/*! + * @brief Enable the RTC timer counter. + * + * After calling this function, the RTC inner counter increments once a second when only using the RTC seconds timer + * (1hz), while the RTC inner wake-up timer countdown once a millisecond when using RTC wake-up timer (1KHZ) at the + * same time. RTC timer contain two timers, one is the RTC normal seconds timer, the other one is the RTC wake-up timer, + * the RTC enable bit is the master switch for the whole RTC timer, so user can use the RTC seconds (1HZ) timer + * independly, but they can't use the RTC wake-up timer (1KHZ) independently. + * + * @param base RTC peripheral base address + * @param enable Enable/Disable RTC Timer counter. + * - true: Enable RTC Timer counter. + * - false: Disable RTC Timer counter. + */ +static inline void RTC_EnableTimer(RTC_Type *base, bool enable) +{ + if (enable) + { + base->CTRL |= RTC_CTRL_RTC_EN_MASK; + } + else + { + base->CTRL &= ~RTC_CTRL_RTC_EN_MASK; + } +} + +/*! + * @brief Starts the RTC time counter. + * @deprecated Do not use this function. It has been superceded by @ref RTC_EnableTimer + * + * After calling this function, the timer counter increments once a second provided SR[TOF] or + * SR[TIF] are not set. + * + * @param base RTC peripheral base address + */ +static inline void RTC_StartTimer(RTC_Type *base) +{ + base->CTRL |= RTC_CTRL_RTC_EN_MASK; +} + +/*! + * @brief Stops the RTC time counter. + * @deprecated Do not use this function. It has been superceded by @ref RTC_EnableTimer + * + * RTC's seconds register can be written to only when the timer is stopped. + * + * @param base RTC peripheral base address + */ +static inline void RTC_StopTimer(RTC_Type *base) +{ + base->CTRL &= ~RTC_CTRL_RTC_EN_MASK; +} + +/*! @}*/ + +/*! + * @brief Perform a software reset on the RTC module. + * + * This resets all RTC registers to their reset value. The bit is cleared by software explicitly clearing it. + * + * @param base RTC peripheral base address + */ +static inline void RTC_Reset(RTC_Type *base) +{ + base->CTRL |= RTC_CTRL_SWRESET_MASK; + base->CTRL &= ~RTC_CTRL_SWRESET_MASK; +} + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_RTC_H_ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_sctimer.c b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_sctimer.c new file mode 100644 index 0000000000..4208097a8b --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_sctimer.c @@ -0,0 +1,791 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_sctimer.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.sctimer" +#endif + +/*! @brief Typedef for interrupt handler. */ +typedef void (*sctimer_isr_t)(SCT_Type *base); + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Gets the instance from the base address + * + * @param base SCTimer peripheral base address + * + * @return The SCTimer instance + */ +static uint32_t SCTIMER_GetInstance(SCT_Type *base); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Pointers to SCT bases for each instance. */ +static SCT_Type *const s_sctBases[] = SCT_BASE_PTRS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Pointers to SCT clocks for each instance. */ +static const clock_ip_name_t s_sctClocks[] = SCT_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) +#if defined(FSL_FEATURE_SCT_WRITE_ZERO_ASSERT_RESET) && FSL_FEATURE_SCT_WRITE_ZERO_ASSERT_RESET +/*! @brief Pointers to SCT resets for each instance, writing a zero asserts the reset */ +static const reset_ip_name_t s_sctResets[] = SCT_RSTS_N; +#else +/*! @brief Pointers to SCT resets for each instance, writing a one asserts the reset */ +static const reset_ip_name_t s_sctResets[] = SCT_RSTS; +#endif +#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ + +/*!< @brief SCTimer event Callback function. */ +static sctimer_event_callback_t s_eventCallback[FSL_FEATURE_SCT_NUMBER_OF_EVENTS]; + +/*!< @brief Keep track of SCTimer event number */ +static uint32_t s_currentEvent; + +/*!< @brief Keep track of SCTimer state number */ +static uint32_t s_currentState; + +/*!< @brief Keep track of SCTimer unify 32-bit or low 16-bit match/capture register number. */ +static uint32_t s_currentMatch; +/*!< @brief Keep track of SCTimer high 16-bit match/capture register number. */ +static uint32_t s_currentMatchhigh; + +/*! @brief Pointer to SCTimer IRQ handler */ +static sctimer_isr_t s_sctimerIsr; + +/******************************************************************************* + * Code + ******************************************************************************/ +static uint32_t SCTIMER_GetInstance(SCT_Type *base) +{ + uint32_t instance; + uint32_t sctArrayCount = (sizeof(s_sctBases) / sizeof(s_sctBases[0])); + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < sctArrayCount; instance++) + { + if (s_sctBases[instance] == base) + { + break; + } + } + + assert(instance < sctArrayCount); + + return instance; +} + +/*! + * brief Ungates the SCTimer clock and configures the peripheral for basic operation. + * + * note This API should be called at the beginning of the application using the SCTimer driver. + * + * param base SCTimer peripheral base address + * param config Pointer to the user configuration structure. + * + * return kStatus_Success indicates success; Else indicates failure. + */ +status_t SCTIMER_Init(SCT_Type *base, const sctimer_config_t *config) +{ + assert(NULL != config); + + uint32_t i; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable the SCTimer clock*/ + CLOCK_EnableClock(s_sctClocks[SCTIMER_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) + /* Reset the module. */ + RESET_PeripheralReset(s_sctResets[SCTIMER_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ + + /* Setup the counter operation. For Current Driver interface SCTIMER_Init don't know detail + * frequency of input clock, but User know it. So the INSYNC have to set by user level. */ + base->CONFIG = SCT_CONFIG_CKSEL(config->clockSelect) | SCT_CONFIG_CLKMODE(config->clockMode) | + SCT_CONFIG_UNIFY(config->enableCounterUnify) | SCT_CONFIG_INSYNC(config->inputsync); + + /* Write to the control register, keep the counters halted. */ + base->CTRL = + SCT_CTRL_BIDIR_L(config->enableBidirection_l) | SCT_CTRL_PRE_L(config->prescale_l) | SCT_CTRL_HALT_L_MASK; + /* Clear the counter after changing the PRE value. */ + base->CTRL |= SCT_CTRL_CLRCTR_L_MASK; + + if (!(config->enableCounterUnify)) + { + base->CTRL |= + SCT_CTRL_BIDIR_H(config->enableBidirection_h) | SCT_CTRL_PRE_H(config->prescale_h) | SCT_CTRL_HALT_H_MASK; + base->CTRL |= SCT_CTRL_CLRCTR_H_MASK; + } + + /* Initial state of channel output */ + base->OUTPUT = config->outInitState; + + /* Clear the global variables */ + s_currentEvent = 0U; + s_currentState = 0U; + s_currentMatch = 0U; + s_currentMatchhigh = 0U; + + /* Clear the callback array */ + for (i = 0; i < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_EVENTS; i++) + { + s_eventCallback[i] = NULL; + } + + /* Save interrupt handler */ + s_sctimerIsr = SCTIMER_EventHandleIRQ; + + return kStatus_Success; +} + +/*! + * brief Gates the SCTimer clock. + * + * param base SCTimer peripheral base address + */ +void SCTIMER_Deinit(SCT_Type *base) +{ + /* Halt the counters */ + base->CTRL |= (SCT_CTRL_HALT_L_MASK | SCT_CTRL_HALT_H_MASK); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Disable the SCTimer clock*/ + CLOCK_DisableClock(s_sctClocks[SCTIMER_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/*! + * brief Fills in the SCTimer configuration structure with the default settings. + * + * The default values are: + * code + * config->enableCounterUnify = true; + * config->clockMode = kSCTIMER_System_ClockMode; + * config->clockSelect = kSCTIMER_Clock_On_Rise_Input_0; + * config->enableBidirection_l = false; + * config->enableBidirection_h = false; + * config->prescale_l = 0U; + * config->prescale_h = 0U; + * config->outInitState = 0U; + * config->inputsync = 0xFU; + * endcode + * param config Pointer to the user configuration structure. + */ +void SCTIMER_GetDefaultConfig(sctimer_config_t *config) +{ + assert(NULL != config); + + /* Initializes the configure structure to zero. */ + (void)memset(config, 0, sizeof(*config)); + + /* SCT operates as a unified 32-bit counter */ + config->enableCounterUnify = true; + /* System clock clocks the entire SCT module */ + config->clockMode = kSCTIMER_System_ClockMode; + /* This is used only by certain clock modes */ + config->clockSelect = kSCTIMER_Clock_On_Rise_Input_0; + /* Up count mode only for the unified counter */ + config->enableBidirection_l = false; + /* Up count mode only for Counte_H */ + config->enableBidirection_h = false; + /* Prescale factor of 1 */ + config->prescale_l = 0U; + /* Prescale factor of 1 for Counter_H*/ + config->prescale_h = 0U; + /* Clear outputs */ + config->outInitState = 0U; + /* Default value is 0xFU, it can be clear as 0 when speical conditions met. + * Condition can be clear as 0: (for all Clock Modes): + * (1) The corresponding input is already synchronous to the SCTimer/PWM clock. + * (2) The SCTimer/PWM clock frequency does not exceed 100 MHz. + * Note: The SCTimer/PWM clock is the bus/system clock for CKMODE 0-2 or asynchronous input + * clock for CKMODE3. + * Another condition can be clear as 0: (for CKMODE2 only) + * (1) The corresponding input is synchronous to the designated CKMODE2 input clock. + * (2) The CKMODE2 input clock frequency is less than one-third the frequency of the bus/system clock. + * Default value set as 0U, input0~input3 are set as bypasses. */ + config->inputsync = 0xFU; +} + +/*! + * brief Configures the PWM signal parameters. + * + * Call this function to configure the PWM signal period, mode, duty cycle, and edge. This + * function will create 2 events; one of the events will trigger on match with the pulse value + * and the other will trigger when the counter matches the PWM period. The PWM period event is + * also used as a limit event to reset the counter or change direction. Both events are enabled + * for the same state. The state number can be retrieved by calling the function + * SCTIMER_GetCurrentStateNumber(). + * The counter is set to operate as one 32-bit counter (unify bit is set to 1). + * The counter operates in bi-directional mode when generating a center-aligned PWM. + * + * note When setting PWM output from multiple output pins, they all should use the same PWM mode + * i.e all PWM's should be either edge-aligned or center-aligned. + * When using this API, the PWM signal frequency of all the initialized channels must be the same. + * Otherwise all the initialized channels' PWM signal frequency is equal to the last call to the + * API's pwmFreq_Hz. + * + * param base SCTimer peripheral base address + * param pwmParams PWM parameters to configure the output + * param mode PWM operation mode, options available in enumeration ::sctimer_pwm_mode_t + * param pwmFreq_Hz PWM signal frequency in Hz + * param srcClock_Hz SCTimer counter clock in Hz + * param event Pointer to a variable where the PWM period event number is stored + * + * return kStatus_Success on success + * kStatus_Fail If we have hit the limit in terms of number of events created or if + * an incorrect PWM dutycylce is passed in. + */ +status_t SCTIMER_SetupPwm(SCT_Type *base, + const sctimer_pwm_signal_param_t *pwmParams, + sctimer_pwm_mode_t mode, + uint32_t pwmFreq_Hz, + uint32_t srcClock_Hz, + uint32_t *event) +{ + assert(NULL != pwmParams); + assert(0U != srcClock_Hz); + assert(0U != pwmFreq_Hz); + assert((uint32_t)pwmParams->output < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS); + assert(1U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); + + /* If we do not have enough events available (this function will create two events), + * the function will return fail. + */ + status_t status = kStatus_Fail; + status_t status2; + uint32_t period, pulsePeriod = 0; + uint32_t sctClock = srcClock_Hz / (((base->CTRL & SCT_CTRL_PRE_L_MASK) >> SCT_CTRL_PRE_L_SHIFT) + 1U); + uint32_t periodEvent = 0, pulseEvent = 0; + uint32_t reg; + + if ((s_currentEvent + 2U) <= (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_EVENTS) + { + /* Use bi-directional mode for center-aligned PWM */ + if (mode == kSCTIMER_CenterAlignedPwm) + { + base->CTRL |= SCT_CTRL_BIDIR_L_MASK; + } + + /* Calculate PWM period match value */ + if (mode == kSCTIMER_EdgeAlignedPwm) + { + period = (sctClock / pwmFreq_Hz) - 1U; + } + else + { + period = sctClock / (pwmFreq_Hz * 2U); + } + + /* For 100% dutycyle, make pulse period greater than period so the event will never occur */ + if (pwmParams->dutyCyclePercent >= 100U) + { + pulsePeriod = period + 2U; + } + else + { + pulsePeriod = (uint32_t)(((uint64_t)period * pwmParams->dutyCyclePercent) / 100U); + } + + /* Schedule an event when we reach the PWM period */ + status = + SCTIMER_CreateAndScheduleEvent(base, kSCTIMER_MatchEventOnly, period, 0, kSCTIMER_Counter_U, &periodEvent); + + /* Schedule an event when we reach the pulse width */ + status2 = SCTIMER_CreateAndScheduleEvent(base, kSCTIMER_MatchEventOnly, pulsePeriod, 0, kSCTIMER_Counter_U, + &pulseEvent); + + if ((kStatus_Success == status) && (kStatus_Success == status2)) + { + /* Reset the counter when we reach the PWM period */ + SCTIMER_SetupCounterLimitAction(base, kSCTIMER_Counter_U, periodEvent); + + /* Return the period event to the user */ + *event = periodEvent; + + /* For high-true level */ + if ((uint32_t)pwmParams->level == (uint32_t)kSCTIMER_HighTrue) + { + if (mode == kSCTIMER_EdgeAlignedPwm) + { + /* Set the initial output level to low which is the inactive state */ + base->OUTPUT &= ~(1UL << (uint32_t)pwmParams->output); + /* Set the output when we reach the PWM period */ + SCTIMER_SetupOutputSetAction(base, (uint32_t)pwmParams->output, periodEvent); + /* Clear the output when we reach the PWM pulse value */ + SCTIMER_SetupOutputClearAction(base, (uint32_t)pwmParams->output, pulseEvent); + } + else + { + /* Set the initial output level to high which is the inactive state */ + base->OUTPUT |= (1UL << (uint32_t)pwmParams->output); + /* Clear the output when we reach the PWM pulse event */ + SCTIMER_SetupOutputClearAction(base, (uint32_t)pwmParams->output, pulseEvent); + /* Reverse output when down counting */ + reg = base->OUTPUTDIRCTRL; + reg &= ~((uint32_t)SCT_OUTPUTDIRCTRL_SETCLR0_MASK << (2U * (uint32_t)pwmParams->output)); + reg |= (1UL << (2U * (uint32_t)pwmParams->output)); + base->OUTPUTDIRCTRL = reg; + } + } + /* For low-true level */ + else + { + if (mode == kSCTIMER_EdgeAlignedPwm) + { + /* Set the initial output level to high which is the inactive state */ + base->OUTPUT |= (1UL << (uint32_t)pwmParams->output); + /* Clear the output when we reach the PWM period */ + SCTIMER_SetupOutputClearAction(base, (uint32_t)pwmParams->output, periodEvent); + /* Set the output when we reach the PWM pulse value */ + SCTIMER_SetupOutputSetAction(base, (uint32_t)pwmParams->output, pulseEvent); + } + else + { + /* Set the initial output level to low which is the inactive state */ + base->OUTPUT &= ~(1UL << (uint32_t)pwmParams->output); + /* Set the output when we reach the PWM pulse event */ + SCTIMER_SetupOutputSetAction(base, (uint32_t)pwmParams->output, pulseEvent); + /* Reverse output when down counting */ + reg = base->OUTPUTDIRCTRL; + reg &= ~((uint32_t)SCT_OUTPUTDIRCTRL_SETCLR0_MASK << (2U * (uint32_t)pwmParams->output)); + reg |= (1UL << (2U * (uint32_t)pwmParams->output)); + base->OUTPUTDIRCTRL = reg; + } + } + } + else + { + status = kStatus_Fail; + } + } + + return status; +} + +/*! + * brief Updates the duty cycle of an active PWM signal. + * + * Before calling this function, the counter is set to operate as one 32-bit counter (unify bit is set to 1). + * + * param base SCTimer peripheral base address + * param output The output to configure + * param dutyCyclePercent New PWM pulse width; the value should be between 0 to 100 + * param event Event number associated with this PWM signal. This was returned to the user by the + * function SCTIMER_SetupPwm(). + */ +void SCTIMER_UpdatePwmDutycycle(SCT_Type *base, sctimer_out_t output, uint8_t dutyCyclePercent, uint32_t event) + +{ + assert(dutyCyclePercent <= 100U); + assert((uint32_t)output < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS); + assert(1U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); + + uint32_t periodMatchReg, pulseMatchReg; + uint32_t pulsePeriod = 0, period; + + /* Retrieve the match register number for the PWM period */ + periodMatchReg = base->EV[event].CTRL & SCT_EV_CTRL_MATCHSEL_MASK; + + /* Retrieve the match register number for the PWM pulse period */ + pulseMatchReg = base->EV[event + 1U].CTRL & SCT_EV_CTRL_MATCHSEL_MASK; + + period = base->MATCH[periodMatchReg]; + + /* For 100% dutycyle, make pulse period greater than period so the event will never occur */ + if (dutyCyclePercent >= 100U) + { + pulsePeriod = period + 2U; + } + else + { + pulsePeriod = (uint32_t)(((uint64_t)period * dutyCyclePercent) / 100U); + } + + /* Stop the counter before updating match register */ + SCTIMER_StopTimer(base, (uint32_t)kSCTIMER_Counter_U); + + /* Update dutycycle */ + base->MATCH[pulseMatchReg] = SCT_MATCH_MATCHn_L(pulsePeriod); + base->MATCHREL[pulseMatchReg] = SCT_MATCHREL_RELOADn_L(pulsePeriod); + + /* Restart the counter */ + SCTIMER_StartTimer(base, (uint32_t)kSCTIMER_Counter_U); +} + +/*! + * brief Create an event that is triggered on a match or IO and schedule in current state. + * + * This function will configure an event using the options provided by the user. If the event type uses + * the counter match, then the function will set the user provided match value into a match register + * and put this match register number into the event control register. + * The event is enabled for the current state and the event number is increased by one at the end. + * The function returns the event number; this event number can be used to configure actions to be + * done when this event is triggered. + * + * param base SCTimer peripheral base address + * param howToMonitor Event type; options are available in the enumeration ::sctimer_interrupt_enable_t + * param matchValue The match value that will be programmed to a match register + * param whichIO The input or output that will be involved in event triggering. This field + * is ignored if the event type is "match only" + * param whichCounter SCTimer counter to use. In 16-bit mode, we can select Counter_L and Counter_H, + * In 32-bit mode, we can select Counter_U. + * param event Pointer to a variable where the new event number is stored + * + * return kStatus_Success on success + * kStatus_Error if we have hit the limit in terms of number of events created or + if we have reached the limit in terms of number of match registers + */ +status_t SCTIMER_CreateAndScheduleEvent(SCT_Type *base, + sctimer_event_t howToMonitor, + uint32_t matchValue, + uint32_t whichIO, + sctimer_counter_t whichCounter, + uint32_t *event) +{ + uint32_t combMode = (((uint32_t)howToMonitor & SCT_EV_CTRL_COMBMODE_MASK) >> SCT_EV_CTRL_COMBMODE_SHIFT); + uint32_t currentCtrlVal = (uint32_t)howToMonitor; + status_t status = kStatus_Success; + uint32_t temp = 0; + + if (s_currentEvent < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_EVENTS) + { + if (2U == combMode) + { + base->EV[s_currentEvent].CTRL = currentCtrlVal | SCT_EV_CTRL_IOSEL(whichIO); + } + else + { + if ((0U == combMode) || (3U == combMode)) + { + currentCtrlVal |= SCT_EV_CTRL_IOSEL(whichIO); + } + + if ((kSCTIMER_Counter_L == whichCounter) && (0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK))) + { + if (s_currentMatch < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE) + { + currentCtrlVal |= SCT_EV_CTRL_MATCHSEL(s_currentMatch); + + /* Use Counter_L bits if user wants to setup the Low counter */ + base->MATCH_ACCESS16BIT[s_currentMatch].MATCHL = (uint16_t)matchValue; + base->MATCHREL_ACCESS16BIT[s_currentMatch].MATCHRELL = (uint16_t)matchValue; + base->EV[s_currentEvent].CTRL = currentCtrlVal; + + /* Increment the match register number */ + s_currentMatch++; + } + else + { + /* An error would occur if we have hit the limit in terms of number of match registers */ + status = kStatus_Fail; + } + } + else if ((kSCTIMER_Counter_H == whichCounter) && (0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK))) + { + if (s_currentMatchhigh < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE) + { + currentCtrlVal |= SCT_EV_CTRL_MATCHSEL(s_currentMatchhigh); + + /* Use Counter_H bits if user wants to setup the High counter */ + currentCtrlVal |= SCT_EV_CTRL_HEVENT(1U); + temp = base->MATCH_ACCESS16BIT[s_currentMatchhigh].MATCHL; + base->MATCH[s_currentMatchhigh] = temp | (matchValue << 16U); + temp = base->MATCHREL_ACCESS16BIT[s_currentMatchhigh].MATCHRELL; + base->MATCHREL[s_currentMatchhigh] = temp | (matchValue << 16U); + + base->EV[s_currentEvent].CTRL = currentCtrlVal; + /* Increment the match register number */ + s_currentMatchhigh++; + } + else + { + /* An error would occur if we have hit the limit in terms of number of match registers */ + status = kStatus_Fail; + } + } + else if ((kSCTIMER_Counter_U == whichCounter) && (0U != (base->CONFIG & SCT_CONFIG_UNIFY_MASK))) + { + if (s_currentMatch < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE) + { + /* Use Counter_L bits if counter is operating in 32-bit mode */ + currentCtrlVal |= SCT_EV_CTRL_MATCHSEL(s_currentMatch); + + base->MATCH[s_currentMatch] = matchValue; + base->MATCHREL[s_currentMatch] = matchValue; + base->EV[s_currentEvent].CTRL = currentCtrlVal; + + /* Increment the match register number */ + s_currentMatch++; + } + else + { + /* An error would occur if we have hit the limit in terms of number of match registers */ + status = kStatus_Fail; + } + } + else + { + /* The used counter must match the CONFIG[UNIFY] bit selection */ + status = kStatus_Fail; + } + } + + if (kStatus_Success == status) + { + /* Enable the event in the current state */ + base->EV[s_currentEvent].STATE = (1UL << s_currentState); + + /* Return the event number */ + *event = s_currentEvent; + + /* Increment the event number */ + s_currentEvent++; + } + } + else + { + /* An error would occur if we have hit the limit in terms of number of events created */ + status = kStatus_Fail; + } + + return status; +} + +/*! + * brief Enable an event in the current state. + * + * This function will allow the event passed in to trigger in the current state. The event must + * be created earlier by either calling the function SCTIMER_SetupPwm() or function + * SCTIMER_CreateAndScheduleEvent() . + * + * param base SCTimer peripheral base address + * param event Event number to enable in the current state + * + */ +void SCTIMER_ScheduleEvent(SCT_Type *base, uint32_t event) +{ + /* Enable event in the current state */ + base->EV[event].STATE |= (1UL << s_currentState); +} + +/*! + * brief Increase the state by 1 + * + * All future events created by calling the function SCTIMER_ScheduleEvent() will be enabled in this new + * state. + * + * param base SCTimer peripheral base address + * + * return kStatus_Success on success + * kStatus_Error if we have hit the limit in terms of states used + + */ +status_t SCTIMER_IncreaseState(SCT_Type *base) +{ + status_t status = kStatus_Success; + + /* Return an error if we have hit the limit in terms of states used */ + if (s_currentState >= (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_STATES) + { + status = kStatus_Fail; + } + else + { + s_currentState++; + } + + return status; +} + +/*! + * brief Provides the current state + * + * User can use this to set the next state by calling the function SCTIMER_SetupNextStateAction(). + * + * param base SCTimer peripheral base address + * + * return The current state + */ +uint32_t SCTIMER_GetCurrentState(SCT_Type *base) +{ + return s_currentState; +} + +/*! + * brief Toggle the output level. + * + * This change in the output level is triggered by the event number that is passed in by the user. + * + * param base SCTimer peripheral base address + * param whichIO The output to toggle + * param event Event number that will trigger the output change + */ +void SCTIMER_SetupOutputToggleAction(SCT_Type *base, uint32_t whichIO, uint32_t event) +{ + assert(whichIO < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS); + + uint32_t reg; + + /* Set the same event to set and clear the output */ + base->OUT[whichIO].CLR |= (1UL << event); + base->OUT[whichIO].SET |= (1UL << event); + + /* Set the conflict resolution to toggle output */ + reg = base->RES; + reg &= ~(((uint32_t)SCT_RES_O0RES_MASK) << (2U * whichIO)); + reg |= ((uint32_t)(kSCTIMER_ResolveToggle)) << (2U * whichIO); + base->RES = reg; +} + +/*! + * brief Setup capture of the counter value on trigger of a selected event + * + * param base SCTimer peripheral base address + * param whichCounter SCTimer counter to use. In 16-bit mode, we can select Counter_L and Counter_H, + * In 32-bit mode, we can select Counter_U. + * param captureRegister Pointer to a variable where the capture register number will be returned. User + * can read the captured value from this register when the specified event is triggered. + * param event Event number that will trigger the capture + * + * return kStatus_Success on success + * kStatus_Error if we have hit the limit in terms of number of match/capture registers available + */ +status_t SCTIMER_SetupCaptureAction(SCT_Type *base, + sctimer_counter_t whichCounter, + uint32_t *captureRegister, + uint32_t event) +{ + status_t status; + uint32_t temp = 0; + + if ((kSCTIMER_Counter_L == whichCounter) || (kSCTIMER_Counter_U == whichCounter)) + { + if (s_currentMatch < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE) + { + /* Set the bit to enable event */ + base->CAPCTRL_ACCESS16BIT[s_currentMatch].CAPCTRLL |= SCT_CAPCTRLL_CAPCTRLL(1UL << event); + + /* Set this resource to be a capture rather than match */ + base->REGMODE_ACCESS16BIT.REGMODEL |= SCT_REGMODEL_REGMODEL(1UL << s_currentMatch); + + /* Return the match register number */ + *captureRegister = s_currentMatch; + + /* Increase the match register number */ + s_currentMatch++; + + status = kStatus_Success; + } + else + { + /* Return an error if we have hit the limit in terms of number of capture/match registers used */ + status = kStatus_Fail; + } + } + else + { + if (s_currentMatchhigh < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE) + { + /* Set bit to enable event */ + temp = base->CAPCTRL_ACCESS16BIT[s_currentMatchhigh].CAPCTRLL; + base->CAPCTRL[s_currentMatchhigh] = temp | ((uint32_t)((uint32_t)(1UL << event) << 16U) & 0xFFFF000U); + /* Set this resource to be a capture rather than match */ + temp = base->REGMODE_ACCESS16BIT.REGMODEL; + base->REGMODE = temp | ((uint32_t)((uint32_t)(1UL << s_currentMatchhigh) << 16U) & 0xFFFF000U); + + /* Return the match register number */ + *captureRegister = s_currentMatchhigh; + + /* Increase the match register number */ + s_currentMatchhigh++; + + status = kStatus_Success; + } + else + { + /* Return an error if we have hit the limit in terms of number of capture/match registers used */ + status = kStatus_Fail; + } + } + + return status; +} + +/*! + * brief Receive noticification when the event trigger an interrupt. + * + * If the interrupt for the event is enabled by the user, then a callback can be registered + * which will be invoked when the event is triggered + * + * param base SCTimer peripheral base address + * param event Event number that will trigger the interrupt + * param callback Function to invoke when the event is triggered + */ + +void SCTIMER_SetCallback(SCT_Type *base, sctimer_event_callback_t callback, uint32_t event) +{ + s_eventCallback[event] = callback; +} + +/*! + * brief SCTimer interrupt handler. + * + * param base SCTimer peripheral base address. + */ +void SCTIMER_EventHandleIRQ(SCT_Type *base) +{ + uint32_t eventFlag = SCT0->EVFLAG; + /* Only clear the flags whose interrupt field is enabled */ + uint32_t clearFlag = (eventFlag & SCT0->EVEN); + uint32_t mask = eventFlag; + uint32_t i; + + /* Invoke the callback for certain events */ + for (i = 0; i < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_EVENTS; i++) + { + if ((mask & 0x1U) != 0U) + { + if (s_eventCallback[i] != NULL) + { + s_eventCallback[i](); + } + } + mask >>= 1UL; + + if (0U == mask) + { + /* All events have been handled. */ + break; + } + } + + /* Clear event interrupt flag */ + SCT0->EVFLAG = clearFlag; +} + +void SCT0_DriverIRQHandler(void); +void SCT0_DriverIRQHandler(void) +{ + s_sctimerIsr(SCT0); + SDK_ISR_EXIT_BARRIER; +} diff --git a/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_sctimer.h b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_sctimer.h new file mode 100644 index 0000000000..283a5b7019 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_sctimer.h @@ -0,0 +1,1258 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_SCTIMER_H_ +#define _FSL_SCTIMER_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup sctimer + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +#define FSL_SCTIMER_DRIVER_VERSION (MAKE_VERSION(2, 4, 4)) /*!< Version */ +/*@}*/ + +#ifndef SCT_EV_STATE_STATEMSKn +#define SCT_EV_STATE_STATEMSKn(x) (((uint32_t)(x) & (1UL << FSL_FEATURE_SCT_NUMBER_OF_STATES) - 1UL)) +#endif + +/*! @brief SCTimer PWM operation modes */ +typedef enum _sctimer_pwm_mode +{ + kSCTIMER_EdgeAlignedPwm = 0U, /*!< Edge-aligned PWM */ + kSCTIMER_CenterAlignedPwm /*!< Center-aligned PWM */ +} sctimer_pwm_mode_t; + +/*! @brief SCTimer counters type. */ +typedef enum _sctimer_counter +{ + kSCTIMER_Counter_L = (1U << 0), /*!< 16-bit Low counter. */ + kSCTIMER_Counter_H = (1U << 1), /*!< 16-bit High counter. */ + kSCTIMER_Counter_U = (1U << 2), /*!< 32-bit Unified counter. */ +} sctimer_counter_t; + +/*! @brief List of SCTimer input pins */ +typedef enum _sctimer_input +{ + kSCTIMER_Input_0 = 0U, /*!< SCTIMER input 0 */ + kSCTIMER_Input_1, /*!< SCTIMER input 1 */ + kSCTIMER_Input_2, /*!< SCTIMER input 2 */ + kSCTIMER_Input_3, /*!< SCTIMER input 3 */ + kSCTIMER_Input_4, /*!< SCTIMER input 4 */ + kSCTIMER_Input_5, /*!< SCTIMER input 5 */ + kSCTIMER_Input_6, /*!< SCTIMER input 6 */ + kSCTIMER_Input_7 /*!< SCTIMER input 7 */ +} sctimer_input_t; + +/*! @brief List of SCTimer output pins */ +typedef enum _sctimer_out +{ + kSCTIMER_Out_0 = 0U, /*!< SCTIMER output 0*/ + kSCTIMER_Out_1, /*!< SCTIMER output 1 */ + kSCTIMER_Out_2, /*!< SCTIMER output 2 */ + kSCTIMER_Out_3, /*!< SCTIMER output 3 */ + kSCTIMER_Out_4, /*!< SCTIMER output 4 */ + kSCTIMER_Out_5, /*!< SCTIMER output 5 */ + kSCTIMER_Out_6, /*!< SCTIMER output 6 */ + kSCTIMER_Out_7, /*!< SCTIMER output 7 */ + kSCTIMER_Out_8, /*!< SCTIMER output 8 */ + kSCTIMER_Out_9 /*!< SCTIMER output 9 */ +} sctimer_out_t; + +/*! @brief SCTimer PWM output pulse mode: high-true, low-true or no output */ +typedef enum _sctimer_pwm_level_select +{ + kSCTIMER_LowTrue = 0U, /*!< Low true pulses */ + kSCTIMER_HighTrue /*!< High true pulses */ +} sctimer_pwm_level_select_t; + +/*! @brief Options to configure a SCTimer PWM signal */ +typedef struct _sctimer_pwm_signal_param +{ + sctimer_out_t output; /*!< The output pin to use to generate the PWM signal */ + sctimer_pwm_level_select_t level; /*!< PWM output active level select. */ + uint8_t dutyCyclePercent; /*!< PWM pulse width, value should be between 0 to 100 + 0 = always inactive signal (0% duty cycle) + 100 = always active signal (100% duty cycle).*/ +} sctimer_pwm_signal_param_t; + +/*! @brief SCTimer clock mode options */ +typedef enum _sctimer_clock_mode +{ + kSCTIMER_System_ClockMode = 0U, /*!< System Clock Mode */ + kSCTIMER_Sampled_ClockMode, /*!< Sampled System Clock Mode */ + kSCTIMER_Input_ClockMode, /*!< SCT Input Clock Mode */ + kSCTIMER_Asynchronous_ClockMode /*!< Asynchronous Mode */ +} sctimer_clock_mode_t; + +/*! @brief SCTimer clock select options */ +typedef enum _sctimer_clock_select +{ + kSCTIMER_Clock_On_Rise_Input_0 = 0U, /*!< Rising edges on input 0 */ + kSCTIMER_Clock_On_Fall_Input_0, /*!< Falling edges on input 0 */ + kSCTIMER_Clock_On_Rise_Input_1, /*!< Rising edges on input 1 */ + kSCTIMER_Clock_On_Fall_Input_1, /*!< Falling edges on input 1 */ + kSCTIMER_Clock_On_Rise_Input_2, /*!< Rising edges on input 2 */ + kSCTIMER_Clock_On_Fall_Input_2, /*!< Falling edges on input 2 */ + kSCTIMER_Clock_On_Rise_Input_3, /*!< Rising edges on input 3 */ + kSCTIMER_Clock_On_Fall_Input_3, /*!< Falling edges on input 3 */ + kSCTIMER_Clock_On_Rise_Input_4, /*!< Rising edges on input 4 */ + kSCTIMER_Clock_On_Fall_Input_4, /*!< Falling edges on input 4 */ + kSCTIMER_Clock_On_Rise_Input_5, /*!< Rising edges on input 5 */ + kSCTIMER_Clock_On_Fall_Input_5, /*!< Falling edges on input 5 */ + kSCTIMER_Clock_On_Rise_Input_6, /*!< Rising edges on input 6 */ + kSCTIMER_Clock_On_Fall_Input_6, /*!< Falling edges on input 6 */ + kSCTIMER_Clock_On_Rise_Input_7, /*!< Rising edges on input 7 */ + kSCTIMER_Clock_On_Fall_Input_7 /*!< Falling edges on input 7 */ +} sctimer_clock_select_t; + +/*! + * @brief SCTimer output conflict resolution options. + * + * Specifies what action should be taken if multiple events dictate that a given output should be + * both set and cleared at the same time + */ +typedef enum _sctimer_conflict_resolution +{ + kSCTIMER_ResolveNone = 0U, /*!< No change */ + kSCTIMER_ResolveSet, /*!< Set output */ + kSCTIMER_ResolveClear, /*!< Clear output */ + kSCTIMER_ResolveToggle /*!< Toggle output */ +} sctimer_conflict_resolution_t; + +/*! @brief List of SCTimer event generation active direction when the counters are operating in BIDIR mode. */ +typedef enum _sctimer_event_active_direction +{ + kSCTIMER_ActiveIndependent = 0U, /*!< This event is triggered regardless of the count direction. */ + kSCTIMER_ActiveInCountUp, /*!< This event is triggered only during up-counting when BIDIR = 1. */ + kSCTIMER_ActiveInCountDown /*!< This event is triggered only during down-counting when BIDIR = 1. */ +} sctimer_event_active_direction_t; + +/*! @brief List of SCTimer event types */ +typedef enum _sctimer_event +{ + kSCTIMER_InputLowOrMatchEvent = + (0 << SCT_EV_CTRL_COMBMODE_SHIFT) + (0 << SCT_EV_CTRL_IOCOND_SHIFT) + (0 << SCT_EV_CTRL_OUTSEL_SHIFT), + kSCTIMER_InputRiseOrMatchEvent = + (0 << SCT_EV_CTRL_COMBMODE_SHIFT) + (1 << SCT_EV_CTRL_IOCOND_SHIFT) + (0 << SCT_EV_CTRL_OUTSEL_SHIFT), + kSCTIMER_InputFallOrMatchEvent = + (0 << SCT_EV_CTRL_COMBMODE_SHIFT) + (2 << SCT_EV_CTRL_IOCOND_SHIFT) + (0 << SCT_EV_CTRL_OUTSEL_SHIFT), + kSCTIMER_InputHighOrMatchEvent = + (0 << SCT_EV_CTRL_COMBMODE_SHIFT) + (3 << SCT_EV_CTRL_IOCOND_SHIFT) + (0 << SCT_EV_CTRL_OUTSEL_SHIFT), + + kSCTIMER_MatchEventOnly = + (1 << SCT_EV_CTRL_COMBMODE_SHIFT) + (0 << SCT_EV_CTRL_IOCOND_SHIFT) + (0 << SCT_EV_CTRL_OUTSEL_SHIFT), + + kSCTIMER_InputLowEvent = + (2 << SCT_EV_CTRL_COMBMODE_SHIFT) + (0 << SCT_EV_CTRL_IOCOND_SHIFT) + (0 << SCT_EV_CTRL_OUTSEL_SHIFT), + kSCTIMER_InputRiseEvent = + (2 << SCT_EV_CTRL_COMBMODE_SHIFT) + (1 << SCT_EV_CTRL_IOCOND_SHIFT) + (0 << SCT_EV_CTRL_OUTSEL_SHIFT), + kSCTIMER_InputFallEvent = + (2 << SCT_EV_CTRL_COMBMODE_SHIFT) + (2 << SCT_EV_CTRL_IOCOND_SHIFT) + (0 << SCT_EV_CTRL_OUTSEL_SHIFT), + kSCTIMER_InputHighEvent = + (2 << SCT_EV_CTRL_COMBMODE_SHIFT) + (3 << SCT_EV_CTRL_IOCOND_SHIFT) + (0 << SCT_EV_CTRL_OUTSEL_SHIFT), + + kSCTIMER_InputLowAndMatchEvent = + (3 << SCT_EV_CTRL_COMBMODE_SHIFT) + (0 << SCT_EV_CTRL_IOCOND_SHIFT) + (0 << SCT_EV_CTRL_OUTSEL_SHIFT), + kSCTIMER_InputRiseAndMatchEvent = + (3 << SCT_EV_CTRL_COMBMODE_SHIFT) + (1 << SCT_EV_CTRL_IOCOND_SHIFT) + (0 << SCT_EV_CTRL_OUTSEL_SHIFT), + kSCTIMER_InputFallAndMatchEvent = + (3 << SCT_EV_CTRL_COMBMODE_SHIFT) + (2 << SCT_EV_CTRL_IOCOND_SHIFT) + (0 << SCT_EV_CTRL_OUTSEL_SHIFT), + kSCTIMER_InputHighAndMatchEvent = + (3 << SCT_EV_CTRL_COMBMODE_SHIFT) + (3 << SCT_EV_CTRL_IOCOND_SHIFT) + (0 << SCT_EV_CTRL_OUTSEL_SHIFT), + + kSCTIMER_OutputLowOrMatchEvent = + (0 << SCT_EV_CTRL_COMBMODE_SHIFT) + (0 << SCT_EV_CTRL_IOCOND_SHIFT) + (1 << SCT_EV_CTRL_OUTSEL_SHIFT), + kSCTIMER_OutputRiseOrMatchEvent = + (0 << SCT_EV_CTRL_COMBMODE_SHIFT) + (1 << SCT_EV_CTRL_IOCOND_SHIFT) + (1 << SCT_EV_CTRL_OUTSEL_SHIFT), + kSCTIMER_OutputFallOrMatchEvent = + (0 << SCT_EV_CTRL_COMBMODE_SHIFT) + (2 << SCT_EV_CTRL_IOCOND_SHIFT) + (1 << SCT_EV_CTRL_OUTSEL_SHIFT), + kSCTIMER_OutputHighOrMatchEvent = + (0 << SCT_EV_CTRL_COMBMODE_SHIFT) + (3 << SCT_EV_CTRL_IOCOND_SHIFT) + (1 << SCT_EV_CTRL_OUTSEL_SHIFT), + + kSCTIMER_OutputLowEvent = + (2 << SCT_EV_CTRL_COMBMODE_SHIFT) + (0 << SCT_EV_CTRL_IOCOND_SHIFT) + (1 << SCT_EV_CTRL_OUTSEL_SHIFT), + kSCTIMER_OutputRiseEvent = + (2 << SCT_EV_CTRL_COMBMODE_SHIFT) + (1 << SCT_EV_CTRL_IOCOND_SHIFT) + (1 << SCT_EV_CTRL_OUTSEL_SHIFT), + kSCTIMER_OutputFallEvent = + (2 << SCT_EV_CTRL_COMBMODE_SHIFT) + (2 << SCT_EV_CTRL_IOCOND_SHIFT) + (1 << SCT_EV_CTRL_OUTSEL_SHIFT), + kSCTIMER_OutputHighEvent = + (2 << SCT_EV_CTRL_COMBMODE_SHIFT) + (3 << SCT_EV_CTRL_IOCOND_SHIFT) + (1 << SCT_EV_CTRL_OUTSEL_SHIFT), + + kSCTIMER_OutputLowAndMatchEvent = + (3 << SCT_EV_CTRL_COMBMODE_SHIFT) + (0 << SCT_EV_CTRL_IOCOND_SHIFT) + (1 << SCT_EV_CTRL_OUTSEL_SHIFT), + kSCTIMER_OutputRiseAndMatchEvent = + (3 << SCT_EV_CTRL_COMBMODE_SHIFT) + (1 << SCT_EV_CTRL_IOCOND_SHIFT) + (1 << SCT_EV_CTRL_OUTSEL_SHIFT), + kSCTIMER_OutputFallAndMatchEvent = + (3 << SCT_EV_CTRL_COMBMODE_SHIFT) + (2 << SCT_EV_CTRL_IOCOND_SHIFT) + (1 << SCT_EV_CTRL_OUTSEL_SHIFT), + kSCTIMER_OutputHighAndMatchEvent = + (3 << SCT_EV_CTRL_COMBMODE_SHIFT) + (3 << SCT_EV_CTRL_IOCOND_SHIFT) + (1 << SCT_EV_CTRL_OUTSEL_SHIFT) +} sctimer_event_t; + +/*! @brief SCTimer callback typedef. */ +typedef void (*sctimer_event_callback_t)(void); + +/*! @brief List of SCTimer interrupts */ +typedef enum _sctimer_interrupt_enable +{ + kSCTIMER_Event0InterruptEnable = (1U << 0), /*!< Event 0 interrupt */ + kSCTIMER_Event1InterruptEnable = (1U << 1), /*!< Event 1 interrupt */ + kSCTIMER_Event2InterruptEnable = (1U << 2), /*!< Event 2 interrupt */ + kSCTIMER_Event3InterruptEnable = (1U << 3), /*!< Event 3 interrupt */ + kSCTIMER_Event4InterruptEnable = (1U << 4), /*!< Event 4 interrupt */ + kSCTIMER_Event5InterruptEnable = (1U << 5), /*!< Event 5 interrupt */ + kSCTIMER_Event6InterruptEnable = (1U << 6), /*!< Event 6 interrupt */ + kSCTIMER_Event7InterruptEnable = (1U << 7), /*!< Event 7 interrupt */ + kSCTIMER_Event8InterruptEnable = (1U << 8), /*!< Event 8 interrupt */ + kSCTIMER_Event9InterruptEnable = (1U << 9), /*!< Event 9 interrupt */ + kSCTIMER_Event10InterruptEnable = (1U << 10), /*!< Event 10 interrupt */ + kSCTIMER_Event11InterruptEnable = (1U << 11), /*!< Event 11 interrupt */ + kSCTIMER_Event12InterruptEnable = (1U << 12), /*!< Event 12 interrupt */ +} sctimer_interrupt_enable_t; + +/*! @brief List of SCTimer flags */ +typedef enum _sctimer_status_flags +{ + kSCTIMER_Event0Flag = (1U << 0), /*!< Event 0 Flag */ + kSCTIMER_Event1Flag = (1U << 1), /*!< Event 1 Flag */ + kSCTIMER_Event2Flag = (1U << 2), /*!< Event 2 Flag */ + kSCTIMER_Event3Flag = (1U << 3), /*!< Event 3 Flag */ + kSCTIMER_Event4Flag = (1U << 4), /*!< Event 4 Flag */ + kSCTIMER_Event5Flag = (1U << 5), /*!< Event 5 Flag */ + kSCTIMER_Event6Flag = (1U << 6), /*!< Event 6 Flag */ + kSCTIMER_Event7Flag = (1U << 7), /*!< Event 7 Flag */ + kSCTIMER_Event8Flag = (1U << 8), /*!< Event 8 Flag */ + kSCTIMER_Event9Flag = (1U << 9), /*!< Event 9 Flag */ + kSCTIMER_Event10Flag = (1U << 10), /*!< Event 10 Flag */ + kSCTIMER_Event11Flag = (1U << 11), /*!< Event 11 Flag */ + kSCTIMER_Event12Flag = (1U << 12), /*!< Event 12 Flag */ + kSCTIMER_BusErrorLFlag = + (1U << SCT_CONFLAG_BUSERRL_SHIFT), /*!< Bus error due to write when L counter was not halted */ + kSCTIMER_BusErrorHFlag = + (int)(1U << SCT_CONFLAG_BUSERRH_SHIFT) /*!< Bus error due to write when H counter was not halted */ +} sctimer_status_flags_t; + +/*! + * @brief SCTimer configuration structure + * + * This structure holds the configuration settings for the SCTimer peripheral. To initialize this + * structure to reasonable defaults, call the SCTMR_GetDefaultConfig() function and pass a + * pointer to the configuration structure instance. + * + * The configuration structure can be made constant so as to reside in flash. + */ +typedef struct _sctimer_config +{ + bool enableCounterUnify; /*!< true: SCT operates as a unified 32-bit counter; + false: SCT operates as two 16-bit counters. + User can use the 16-bit low counter and the 16-bit high counters at the + same time; for Hardware limit, user can not use unified 32-bit counter + and any 16-bit low/high counter at the same time. */ + sctimer_clock_mode_t clockMode; /*!< SCT clock mode value */ + sctimer_clock_select_t clockSelect; /*!< SCT clock select value */ + bool enableBidirection_l; /*!< true: Up-down count mode for the L or unified counter + false: Up count mode only for the L or unified counter */ + bool enableBidirection_h; /*!< true: Up-down count mode for the H or unified counter + false: Up count mode only for the H or unified counter. + This field is used only if the enableCounterUnify is set + to false */ + uint8_t prescale_l; /*!< Prescale value to produce the L or unified counter clock */ + uint8_t prescale_h; /*!< Prescale value to produce the H counter clock. + This field is used only if the enableCounterUnify is set + to false */ + uint8_t outInitState; /*!< Defines the initial output value */ + uint8_t inputsync; /*!< SCT INSYNC value, INSYNC field in the CONFIG register, from bit9 to bit 16. + it is used to define synchronization for input N: + bit 9 = input 0 + bit 10 = input 1 + bit 11 = input 2 + bit 12 = input 3 + All other bits are reserved (bit13 ~bit 16). + How User to set the the value for the member inputsync. + IE: delay for input0, and input 1, bypasses for input 2 and input 3 + MACRO definition in user level. + \#define INPUTSYNC0 (0U) + \#define INPUTSYNC1 (1U) + \#define INPUTSYNC2 (2U) + \#define INPUTSYNC3 (3U) + User Code. + sctimerInfo.inputsync = (1 << INPUTSYNC2) | (1 << INPUTSYNC3); */ +} sctimer_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Ungates the SCTimer clock and configures the peripheral for basic operation. + * + * @note This API should be called at the beginning of the application using the SCTimer driver. + * + * @param base SCTimer peripheral base address + * @param config Pointer to the user configuration structure. + * + * @return kStatus_Success indicates success; Else indicates failure. + */ +status_t SCTIMER_Init(SCT_Type *base, const sctimer_config_t *config); + +/*! + * @brief Gates the SCTimer clock. + * + * @param base SCTimer peripheral base address + */ +void SCTIMER_Deinit(SCT_Type *base); + +/*! + * @brief Fills in the SCTimer configuration structure with the default settings. + * + * The default values are: + * @code + * config->enableCounterUnify = true; + * config->clockMode = kSCTIMER_System_ClockMode; + * config->clockSelect = kSCTIMER_Clock_On_Rise_Input_0; + * config->enableBidirection_l = false; + * config->enableBidirection_h = false; + * config->prescale_l = 0U; + * config->prescale_h = 0U; + * config->outInitState = 0U; + * config->inputsync = 0xFU; + * @endcode + * @param config Pointer to the user configuration structure. + */ +void SCTIMER_GetDefaultConfig(sctimer_config_t *config); + +/*! @}*/ + +/*! + * @name PWM setup operations + * @{ + */ + +/*! + * @brief Configures the PWM signal parameters. + * + * Call this function to configure the PWM signal period, mode, duty cycle, and edge. This + * function will create 2 events; one of the events will trigger on match with the pulse value + * and the other will trigger when the counter matches the PWM period. The PWM period event is + * also used as a limit event to reset the counter or change direction. Both events are enabled + * for the same state. The state number can be retrieved by calling the function + * SCTIMER_GetCurrentStateNumber(). + * The counter is set to operate as one 32-bit counter (unify bit is set to 1). + * The counter operates in bi-directional mode when generating a center-aligned PWM. + * + * @note When setting PWM output from multiple output pins, they all should use the same PWM mode + * i.e all PWM's should be either edge-aligned or center-aligned. + * When using this API, the PWM signal frequency of all the initialized channels must be the same. + * Otherwise all the initialized channels' PWM signal frequency is equal to the last call to the + * API's pwmFreq_Hz. + * + * @param base SCTimer peripheral base address + * @param pwmParams PWM parameters to configure the output + * @param mode PWM operation mode, options available in enumeration ::sctimer_pwm_mode_t + * @param pwmFreq_Hz PWM signal frequency in Hz + * @param srcClock_Hz SCTimer counter clock in Hz + * @param event Pointer to a variable where the PWM period event number is stored + * + * @return kStatus_Success on success + * kStatus_Fail If we have hit the limit in terms of number of events created or if + * an incorrect PWM dutycylce is passed in. + */ +status_t SCTIMER_SetupPwm(SCT_Type *base, + const sctimer_pwm_signal_param_t *pwmParams, + sctimer_pwm_mode_t mode, + uint32_t pwmFreq_Hz, + uint32_t srcClock_Hz, + uint32_t *event); + +/*! + * @brief Updates the duty cycle of an active PWM signal. + * + * Before calling this function, the counter is set to operate as one 32-bit counter (unify bit is set to 1). + * + * @param base SCTimer peripheral base address + * @param output The output to configure + * @param dutyCyclePercent New PWM pulse width; the value should be between 1 to 100 + * @param event Event number associated with this PWM signal. This was returned to the user by the + * function SCTIMER_SetupPwm(). + */ +void SCTIMER_UpdatePwmDutycycle(SCT_Type *base, sctimer_out_t output, uint8_t dutyCyclePercent, uint32_t event); + +/*! + * @name Interrupt Interface + * @{ + */ + +/*! + * @brief Enables the selected SCTimer interrupts. + * + * @param base SCTimer peripheral base address + * @param mask The interrupts to enable. This is a logical OR of members of the + * enumeration ::sctimer_interrupt_enable_t + */ +static inline void SCTIMER_EnableInterrupts(SCT_Type *base, uint32_t mask) +{ + base->EVEN |= mask; +} + +/*! + * @brief Disables the selected SCTimer interrupts. + * + * @param base SCTimer peripheral base address + * @param mask The interrupts to enable. This is a logical OR of members of the + * enumeration ::sctimer_interrupt_enable_t + */ +static inline void SCTIMER_DisableInterrupts(SCT_Type *base, uint32_t mask) +{ + base->EVEN &= ~mask; +} + +/*! + * @brief Gets the enabled SCTimer interrupts. + * + * @param base SCTimer peripheral base address + * + * @return The enabled interrupts. This is the logical OR of members of the + * enumeration ::sctimer_interrupt_enable_t + */ +static inline uint32_t SCTIMER_GetEnabledInterrupts(SCT_Type *base) +{ + return (base->EVEN & 0xFFFFU); +} + +/*! @}*/ + +/*! + * @name Status Interface + * @{ + */ + +/*! + * @brief Gets the SCTimer status flags. + * + * @param base SCTimer peripheral base address + * + * @return The status flags. This is the logical OR of members of the + * enumeration ::sctimer_status_flags_t + */ +static inline uint32_t SCTIMER_GetStatusFlags(SCT_Type *base) +{ + uint32_t statusFlags = 0; + + /* Add the recorded events */ + statusFlags = (base->EVFLAG & 0xFFFFU); + + /* Add bus error flags */ + statusFlags |= (base->CONFLAG & (SCT_CONFLAG_BUSERRL_MASK | SCT_CONFLAG_BUSERRH_MASK)); + + return statusFlags; +} + +/*! + * @brief Clears the SCTimer status flags. + * + * @param base SCTimer peripheral base address + * @param mask The status flags to clear. This is a logical OR of members of the + * enumeration ::sctimer_status_flags_t + */ +static inline void SCTIMER_ClearStatusFlags(SCT_Type *base, uint32_t mask) +{ + /* Write to the flag registers */ + base->EVFLAG = (mask & 0xFFFFU); + base->CONFLAG = (mask & (SCT_CONFLAG_BUSERRL_MASK | SCT_CONFLAG_BUSERRH_MASK)); +} + +/*! @}*/ + +/*! + * @name Counter Start and Stop + * @{ + */ + +/*! + * @brief Starts the SCTimer counter. + * + * @note In 16-bit mode, we can enable both Counter_L and Counter_H, In 32-bit mode, we only can select Counter_U. + * + * @param base SCTimer peripheral base address + * @param countertoStart The SCTimer counters to enable. This is a logical OR of members of the + * enumeration ::sctimer_counter_t. + */ +static inline void SCTIMER_StartTimer(SCT_Type *base, uint32_t countertoStart) +{ + switch (countertoStart) + { + case (uint32_t)kSCTIMER_Counter_L: + assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); + /* Clear HALT_L bit when user wants to start the Low counter */ + base->CTRL_ACCESS16BIT.CTRLL &= ~((uint16_t)SCT_CTRLL_HALT_L_MASK); + break; + + case (uint32_t)kSCTIMER_Counter_H: + assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); + /* Clear HALT_H bit when user wants to start the High counter */ + base->CTRL_ACCESS16BIT.CTRLH &= ~((uint16_t)SCT_CTRLH_HALT_H_MASK); + break; + + case (uint32_t)kSCTIMER_Counter_L | (uint32_t)kSCTIMER_Counter_H: + assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); + /* Clear HALT_L/HALT_H bit when user wants to H counter and L counter at same time */ + base->CTRL &= ~(SCT_CTRL_HALT_L_MASK | SCT_CTRL_HALT_H_MASK); + break; + + case (uint32_t)kSCTIMER_Counter_U: + assert(1U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); + /* Clear HALT_L bit when the counter is operating in 32-bit mode (unify counter). */ + base->CTRL &= ~(SCT_CTRL_HALT_L_MASK); + break; + + default: + /* Counter_L/Counter_H can't work together with Counter_U. */ + assert(false); + break; + } +} + +/*! + * @brief Halts the SCTimer counter. + * + * @param base SCTimer peripheral base address + * @param countertoStop The SCTimer counters to stop. This is a logical OR of members of the + * enumeration ::sctimer_counter_t. + */ +static inline void SCTIMER_StopTimer(SCT_Type *base, uint32_t countertoStop) +{ + switch (countertoStop) + { + case (uint32_t)kSCTIMER_Counter_L: + assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); + /* Set HALT_L bit when user wants to start the Low counter */ + base->CTRL_ACCESS16BIT.CTRLL |= (SCT_CTRLL_HALT_L_MASK); + break; + + case (uint32_t)kSCTIMER_Counter_H: + assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); + /* Set HALT_H bit when user wants to start the High counter */ + base->CTRL_ACCESS16BIT.CTRLH |= (SCT_CTRLH_HALT_H_MASK); + break; + + case (uint32_t)kSCTIMER_Counter_L | (uint32_t)kSCTIMER_Counter_H: + assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); + /* Clear HALT_L/HALT_H bit when user wants to H counter and L counter at same time */ + base->CTRL |= (SCT_CTRL_HALT_L_MASK | SCT_CTRL_HALT_H_MASK); + break; + + case (uint32_t)kSCTIMER_Counter_U: + assert(1U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); + /* Set HALT_L bit when the counter is operating in 32-bit mode (unify counter). */ + base->CTRL |= (SCT_CTRL_HALT_L_MASK); + break; + + default: + /* Counter_L/Counter_H can't work together with Counter_U. */ + assert(false); + break; + } +} + +/*! @}*/ + +/*! + * @name Functions to create a new event and manage the state logic + * @{ + */ + +/*! + * @brief Create an event that is triggered on a match or IO and schedule in current state. + * + * This function will configure an event using the options provided by the user. If the event type uses + * the counter match, then the function will set the user provided match value into a match register + * and put this match register number into the event control register. + * The event is enabled for the current state and the event number is increased by one at the end. + * The function returns the event number; this event number can be used to configure actions to be + * done when this event is triggered. + * + * @param base SCTimer peripheral base address + * @param howToMonitor Event type; options are available in the enumeration ::sctimer_interrupt_enable_t + * @param matchValue The match value that will be programmed to a match register + * @param whichIO The input or output that will be involved in event triggering. This field + * is ignored if the event type is "match only" + * @param whichCounter SCTimer counter to use. In 16-bit mode, we can select Counter_L and Counter_H, + * In 32-bit mode, we can select Counter_U. + * @param event Pointer to a variable where the new event number is stored + * + * @return kStatus_Success on success + * kStatus_Error if we have hit the limit in terms of number of events created or + if we have reached the limit in terms of number of match registers + */ +status_t SCTIMER_CreateAndScheduleEvent(SCT_Type *base, + sctimer_event_t howToMonitor, + uint32_t matchValue, + uint32_t whichIO, + sctimer_counter_t whichCounter, + uint32_t *event); + +/*! + * @brief Enable an event in the current state. + * + * This function will allow the event passed in to trigger in the current state. The event must + * be created earlier by either calling the function SCTIMER_SetupPwm() or function + * SCTIMER_CreateAndScheduleEvent() . + * + * @param base SCTimer peripheral base address + * @param event Event number to enable in the current state + * + */ +void SCTIMER_ScheduleEvent(SCT_Type *base, uint32_t event); + +/*! + * @brief Increase the state by 1 + * + * All future events created by calling the function SCTIMER_ScheduleEvent() will be enabled in this new + * state. + * + * @param base SCTimer peripheral base address + * + * @return kStatus_Success on success + * kStatus_Error if we have hit the limit in terms of states used + + */ +status_t SCTIMER_IncreaseState(SCT_Type *base); + +/*! + * @brief Provides the current state + * + * User can use this to set the next state by calling the function SCTIMER_SetupNextStateAction(). + * + * @param base SCTimer peripheral base address + * + * @return The current state + */ +uint32_t SCTIMER_GetCurrentState(SCT_Type *base); + +/*! + * @brief Set the counter current state. + * + * The function is to set the state variable bit field of STATE register. Writing to the STATE_L, STATE_H, or unified + * register is only allowed when the corresponding counter is halted (HALT bits are set to 1 in the CTRL register). + * + * @param base SCTimer peripheral base address + * @param whichCounter SCTimer counter to use. In 16-bit mode, we can select Counter_L and Counter_H, + * In 32-bit mode, we can select Counter_U. + * @param state The counter current state number (only support range from 0~31). + */ +static inline void SCTIMER_SetCounterState(SCT_Type *base, sctimer_counter_t whichCounter, uint32_t state) +{ + /* SCT only support 0 ~ FSL_FEATURE_SCT_NUMBER_OF_STATES state value. */ + assert(state < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_STATES); + + SCTIMER_StopTimer(base, (uint32_t)whichCounter); + + switch (whichCounter) + { + case kSCTIMER_Counter_L: + assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); + /* Use STATE_L bits when user wants to setup the Low counter */ + base->STATE_ACCESS16BIT.STATEL = SCT_STATEL_STATEL(state); + break; + + case kSCTIMER_Counter_H: + assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); + /* Use STATE_H bits when user wants to start the High counter */ + base->STATE_ACCESS16BIT.STATEH = SCT_STATEH_STATEH(state); + break; + + case kSCTIMER_Counter_U: + assert(1U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); + /* Use STATE_L bits when counter is operating in 32-bit mode (unify counter). */ + base->STATE = SCT_STATE_STATE_L(state); + break; + + default: + /* Fix the MISRA C-2012 issue rule 16.4. */ + break; + } + + SCTIMER_StartTimer(base, (uint32_t)whichCounter); +} + +/*! + * @brief Get the counter current state value. + * + * The function is to get the state variable bit field of STATE register. + * + * @param base SCTimer peripheral base address + * @param whichCounter SCTimer counter to use. In 16-bit mode, we can select Counter_L and Counter_H, + * In 32-bit mode, we can select Counter_U. + * @return The the counter current state value. + */ +static inline uint16_t SCTIMER_GetCounterState(SCT_Type *base, sctimer_counter_t whichCounter) +{ + uint16_t regs; + + switch (whichCounter) + { + case kSCTIMER_Counter_L: + assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); + /* Use STATE_L bits when user wants to setup the Low counter */ + regs = base->STATE_ACCESS16BIT.STATEL & SCT_STATEL_STATEL_MASK; + break; + + case kSCTIMER_Counter_H: + assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); + /* Use STATE_H bits when user wants to start the High counter */ + regs = base->STATE_ACCESS16BIT.STATEH & SCT_STATEH_STATEH_MASK; + break; + + case kSCTIMER_Counter_U: + assert(1U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); + /* Use STATE_L bits when counter is operating in 32-bit mode (unify counter). */ + regs = (uint16_t)(base->STATE & SCT_STATE_STATE_L_MASK); + break; + + default: + /* Fix the MISRA C-2012 issue rule 16.4. */ + break; + } + + return regs; +} + +/*! @}*/ + +/*! + * @name Actions to take in response to an event + * @{ + */ + +/*! + * @brief Setup capture of the counter value on trigger of a selected event + * + * @param base SCTimer peripheral base address + * @param whichCounter SCTimer counter to use. In 16-bit mode, we can select Counter_L and Counter_H, + * In 32-bit mode, we can select Counter_U. + * @param captureRegister Pointer to a variable where the capture register number will be returned. User + * can read the captured value from this register when the specified event is triggered. + * @param event Event number that will trigger the capture + * + * @return kStatus_Success on success + * kStatus_Error if we have hit the limit in terms of number of match/capture registers available + */ +status_t SCTIMER_SetupCaptureAction(SCT_Type *base, + sctimer_counter_t whichCounter, + uint32_t *captureRegister, + uint32_t event); + +/*! + * @brief Receive noticification when the event trigger an interrupt. + * + * If the interrupt for the event is enabled by the user, then a callback can be registered + * which will be invoked when the event is triggered + * + * @param base SCTimer peripheral base address + * @param event Event number that will trigger the interrupt + * @param callback Function to invoke when the event is triggered + */ + +void SCTIMER_SetCallback(SCT_Type *base, sctimer_event_callback_t callback, uint32_t event); + +/*! + * @brief Change the load method of transition to the specified state. + * + * Change the load method of transition, it will be triggered by the event number that is passed in by the user. + * + * @param base SCTimer peripheral base address + * @param event Event number that will change the method to trigger the state transition + * @param fgLoad The method to load highest-numbered event occurring for that state to the STATE register. + * - true: Load the STATEV value to STATE when the event occurs to be the next state. + * - false: Add the STATEV value to STATE when the event occurs to be the next state. + */ +static inline void SCTIMER_SetupStateLdMethodAction(SCT_Type *base, uint32_t event, bool fgLoad) +{ + uint32_t reg = base->EV[event].CTRL; + + if (fgLoad) + { + /* Load the STATEV value to STATE when the event occurs to be the next state */ + reg |= SCT_EV_CTRL_STATELD_MASK; + } + else + { + /* Add the STATEV value to STATE when the event occurs to be the next state */ + reg &= ~SCT_EV_CTRL_STATELD_MASK; + } + + base->EV[event].CTRL = reg; +} + +/*! + * @brief Transition to the specified state with Load method. + * + * This transition will be triggered by the event number that is passed in by the user, the method decide how to load + * the highest-numbered event occurring for that state to the STATE register. + * + * @param base SCTimer peripheral base address + * @param nextState The next state SCTimer will transition to + * @param event Event number that will trigger the state transition + * @param fgLoad The method to load the highest-numbered event occurring for that state to the STATE register. + * - true: Load the STATEV value to STATE when the event occurs to be the next state. + * - false: Add the STATEV value to STATE when the event occurs to be the next state. + */ +static inline void SCTIMER_SetupNextStateActionwithLdMethod(SCT_Type *base, + uint32_t nextState, + uint32_t event, + bool fgLoad) +{ + uint32_t reg = base->EV[event].CTRL; + + reg &= ~(SCT_EV_CTRL_STATEV_MASK | SCT_EV_CTRL_STATELD_MASK); + + reg |= SCT_EV_CTRL_STATEV(nextState); + + if (fgLoad) + { + /* Load the STATEV value when the event occurs to be the next state */ + reg |= SCT_EV_CTRL_STATELD_MASK; + } + + base->EV[event].CTRL = reg; +} + +/*! + * @brief Transition to the specified state. + * @deprecated Do not use this function. It has been superceded by @ref SCTIMER_SetupNextStateActionwithLdMethod + * + * This transition will be triggered by the event number that is passed in by the user. + * + * @param base SCTimer peripheral base address + * @param nextState The next state SCTimer will transition to + * @param event Event number that will trigger the state transition + */ +static inline void SCTIMER_SetupNextStateAction(SCT_Type *base, uint32_t nextState, uint32_t event) +{ + uint32_t reg = base->EV[event].CTRL; + + reg &= ~(SCT_EV_CTRL_STATEV_MASK); + /* Load the STATEV value when the event occurs to be the next state */ + reg |= SCT_EV_CTRL_STATEV(nextState) | SCT_EV_CTRL_STATELD_MASK; + + base->EV[event].CTRL = reg; +} + +/*! + * @brief Setup event active direction when the counters are operating in BIDIR mode. + * + * @param base SCTimer peripheral base address + * @param activeDirection Event generation active direction, see @ref sctimer_event_active_direction_t. + * @param event Event number that need setup the active direction. + */ +static inline void SCTIMER_SetupEventActiveDirection(SCT_Type *base, + sctimer_event_active_direction_t activeDirection, + uint32_t event) +{ + uint32_t reg = base->EV[event].CTRL; + + reg &= ~(SCT_EV_CTRL_DIRECTION_MASK); + + reg |= SCT_EV_CTRL_DIRECTION(activeDirection); + + base->EV[event].CTRL = reg; +} + +/*! + * @brief Set the Output. + * + * This output will be set when the event number that is passed in by the user is triggered. + * + * @param base SCTimer peripheral base address + * @param whichIO The output to set + * @param event Event number that will trigger the output change + */ +static inline void SCTIMER_SetupOutputSetAction(SCT_Type *base, uint32_t whichIO, uint32_t event) +{ + assert(whichIO < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS); + + base->OUT[whichIO].SET |= (1UL << event); +} + +/*! + * @brief Clear the Output. + * + * This output will be cleared when the event number that is passed in by the user is triggered. + * + * @param base SCTimer peripheral base address + * @param whichIO The output to clear + * @param event Event number that will trigger the output change + */ +static inline void SCTIMER_SetupOutputClearAction(SCT_Type *base, uint32_t whichIO, uint32_t event) +{ + assert(whichIO < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS); + + base->OUT[whichIO].CLR |= (1UL << event); +} + +/*! + * @brief Toggle the output level. + * + * This change in the output level is triggered by the event number that is passed in by the user. + * + * @param base SCTimer peripheral base address + * @param whichIO The output to toggle + * @param event Event number that will trigger the output change + */ +void SCTIMER_SetupOutputToggleAction(SCT_Type *base, uint32_t whichIO, uint32_t event); + +/*! + * @brief Limit the running counter. + * + * The counter is limited when the event number that is passed in by the user is triggered. + * + * @param base SCTimer peripheral base address + * @param whichCounter SCTimer counter to use. In 16-bit mode, we can select Counter_L and Counter_H, + * In 32-bit mode, we can select Counter_U. + * @param event Event number that will trigger the counter to be limited + */ +static inline void SCTIMER_SetupCounterLimitAction(SCT_Type *base, sctimer_counter_t whichCounter, uint32_t event) +{ + switch (whichCounter) + { + case kSCTIMER_Counter_L: + assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); + /* Use Counter_L bits when user wants to setup the Low counter */ + base->LIMIT_ACCESS16BIT.LIMITL |= SCT_LIMITL_LIMITL(1UL << event); + break; + + case kSCTIMER_Counter_H: + assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); + /* Use Counter_H bits when user wants to start the High counter */ + base->LIMIT_ACCESS16BIT.LIMITH |= SCT_LIMITH_LIMITH(1UL << event); + break; + + case kSCTIMER_Counter_U: + assert(1U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); + /* Use Counter_L bits when counter is operating in 32-bit mode (unify counter). */ + base->LIMIT |= SCT_LIMIT_LIMMSK_L(1UL << event); + break; + + default: + /* Fix the MISRA C-2012 issue rule 16.4. */ + break; + } +} + +/*! + * @brief Stop the running counter. + * + * The counter is stopped when the event number that is passed in by the user is triggered. + * + * @param base SCTimer peripheral base address + * @param whichCounter SCTimer counter to use. In 16-bit mode, we can select Counter_L and Counter_H, + * In 32-bit mode, we can select Counter_U. + * @param event Event number that will trigger the counter to be stopped + */ +static inline void SCTIMER_SetupCounterStopAction(SCT_Type *base, sctimer_counter_t whichCounter, uint32_t event) +{ + switch (whichCounter) + { + case kSCTIMER_Counter_L: + assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); + /* Use Counter_L bits when user wants to setup the Low counter */ + base->STOP_ACCESS16BIT.STOPL |= SCT_STOPL_STOPL(1UL << event); + break; + + case kSCTIMER_Counter_H: + assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); + /* Use Counter_H bits when user wants to start the High counter */ + base->STOP_ACCESS16BIT.STOPH |= SCT_STOPH_STOPH(1UL << event); + break; + + case kSCTIMER_Counter_U: + assert(1U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); + /* Use Counter_L bits when counter is operating in 32-bit mode (unify counter). */ + base->STOP |= SCT_STOP_STOPMSK_L(1UL << event); + break; + + default: + /* Fix the MISRA C-2012 issue rule 16.4. */ + break; + } +} + +/*! + * @brief Re-start the stopped counter. + * + * The counter will re-start when the event number that is passed in by the user is triggered. + * + * @param base SCTimer peripheral base address + * @param whichCounter SCTimer counter to use. In 16-bit mode, we can select Counter_L and Counter_H, + * In 32-bit mode, we can select Counter_U. + * @param event Event number that will trigger the counter to re-start + */ +static inline void SCTIMER_SetupCounterStartAction(SCT_Type *base, sctimer_counter_t whichCounter, uint32_t event) +{ + switch (whichCounter) + { + case kSCTIMER_Counter_L: + assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); + /* Use Counter_L bits when user wants to setup the Low counter */ + base->START_ACCESS16BIT.STARTL |= SCT_STARTL_STARTL(1UL << event); + break; + + case kSCTIMER_Counter_H: + assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); + /* Use Counter_H bits when user wants to start the High counter */ + base->START_ACCESS16BIT.STARTH |= SCT_STARTH_STARTH(1UL << event); + break; + + case kSCTIMER_Counter_U: + assert(1U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); + /* Use Counter_L bits when counter is operating in 32-bit mode (unify counter). */ + base->START |= SCT_START_STARTMSK_L(1UL << event); + break; + + default: + /* Fix the MISRA C-2012 issue rule 16.4. */ + break; + } +} + +/*! + * @brief Halt the running counter. + * + * The counter is disabled (halted) when the event number that is passed in by the user is + * triggered. When the counter is halted, all further events are disabled. The HALT condition + * can only be removed by calling the SCTIMER_StartTimer() function. + * + * @param base SCTimer peripheral base address + * @param whichCounter SCTimer counter to use. In 16-bit mode, we can select Counter_L and Counter_H, + * In 32-bit mode, we can select Counter_U. + * @param event Event number that will trigger the counter to be halted + */ +static inline void SCTIMER_SetupCounterHaltAction(SCT_Type *base, sctimer_counter_t whichCounter, uint32_t event) +{ + switch (whichCounter) + { + case kSCTIMER_Counter_L: + assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); + /* Use Counter_L bits when user wants to setup the Low counter */ + base->HALT_ACCESS16BIT.HALTL |= SCT_HALTL_HALTL(1UL << event); + break; + + case kSCTIMER_Counter_H: + assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); + /* Use Counter_H bits when user wants to start the High counter */ + base->HALT_ACCESS16BIT.HALTH |= SCT_HALTH_HALTH(1UL << event); + break; + + case kSCTIMER_Counter_U: + assert(1U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); + /* Use Counter_L bits when counter is operating in 32-bit mode (unify counter). */ + base->HALT |= SCT_HALT_HALTMSK_L(1UL << event); + break; + + default: + /* Fix the MISRA C-2012 issue rule 16.4. */ + break; + } +} + +#if !(defined(FSL_FEATURE_SCT_HAS_NO_DMA_REQUEST) && FSL_FEATURE_SCT_HAS_NO_DMA_REQUEST) +/*! + * @brief Generate a DMA request. + * + * DMA request will be triggered by the event number that is passed in by the user. + * + * @param base SCTimer peripheral base address + * @param dmaNumber The DMA request to generate + * @param event Event number that will trigger the DMA request + */ +static inline void SCTIMER_SetupDmaTriggerAction(SCT_Type *base, uint32_t dmaNumber, uint32_t event) +{ + if (dmaNumber == 0U) + { + base->DMAREQ0 |= (1UL << event); + } + else + { + base->DMAREQ1 |= (1UL << event); + } +} +#endif /* FSL_FEATURE_SCT_HAS_NO_DMA_REQUEST */ + +/*! + * @brief Set the value of counter. + * + * The function is to set the value of Count register, Writing to the COUNT_L, COUNT_H, or unified register + * is only allowed when the corresponding counter is halted (HALT bits are set to 1 in the CTRL register). + * + * @param base SCTimer peripheral base address + * @param whichCounter SCTimer counter to use. In 16-bit mode, we can select Counter_L and Counter_H, + * In 32-bit mode, we can select Counter_U. + * @param value the counter value update to the COUNT register. + */ +static inline void SCTIMER_SetCOUNTValue(SCT_Type *base, sctimer_counter_t whichCounter, uint32_t value) +{ + SCTIMER_StopTimer(base, (uint32_t)whichCounter); + + switch (whichCounter) + { + case kSCTIMER_Counter_L: + assert(value <= 0xFFFFU); + assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); + /* Use Counter_L bits when user wants to setup the Low counter */ + base->COUNT_ACCESS16BIT.COUNTL = (uint16_t)value; + break; + + case kSCTIMER_Counter_H: + assert(value <= 0xFFFFU); + assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); + /* Use Counter_H bits when user wants to start the High counter */ + base->COUNT_ACCESS16BIT.COUNTH = (uint16_t)value; + break; + + case kSCTIMER_Counter_U: + assert(1U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); + /* Use Counter_L bits when counter is operating in 32-bit mode (unify counter). */ + base->COUNT &= ~SCT_COUNT_CTR_L_MASK; + base->COUNT |= SCT_COUNT_CTR_L(value); + break; + + default: + /* Fix the MISRA C-2012 issue rule 16.4. */ + break; + } + + SCTIMER_StartTimer(base, (uint32_t)whichCounter); +} + +/*! + * @brief Get the value of counter. + * + * The function is to read the value of Count register, software can read the counter registers at any time.. + * + * @param base SCTimer peripheral base address + * @param whichCounter SCTimer counter to use. In 16-bit mode, we can select Counter_L and Counter_H, + * In 32-bit mode, we can select Counter_U. + * @return The value of counter selected. + */ +static inline uint32_t SCTIMER_GetCOUNTValue(SCT_Type *base, sctimer_counter_t whichCounter) +{ + uint32_t value; + + switch (whichCounter) + { + case kSCTIMER_Counter_L: + assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); + /* Use Counter_L bits when user wants to setup the Low counter */ + value = base->COUNT_ACCESS16BIT.COUNTL; + break; + + case kSCTIMER_Counter_H: + assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); + /* Use Counter_H bits when user wants to start the High counter */ + value = base->COUNT_ACCESS16BIT.COUNTH; + break; + + case kSCTIMER_Counter_U: + assert(1U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); + /* Use Counter_L bits when counter is operating in 32-bit mode (unify counter). */ + value = base->COUNT; + break; + + default: + /* Fix the MISRA C-2012 issue rule 16.4. */ + break; + } + + return value; +} + +/*! + * @brief Set the state mask bit field of EV_STATE register. + * + * @param base SCTimer peripheral base address + * @param event The EV_STATE register be set. + * @param state The state value in which the event is enabled to occur. + */ +static inline void SCTIMER_SetEventInState(SCT_Type *base, uint32_t event, uint32_t state) +{ + assert(state < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_STATES); + assert(event < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_EVENTS); + + base->EV[event].STATE |= SCT_EV_STATE_STATEMSKn((uint32_t)1U << state); +} + +/*! + * @brief Clear the state mask bit field of EV_STATE register. + * + * @param base SCTimer peripheral base address + * @param event The EV_STATE register be clear. + * @param state The state value in which the event is disabled to occur. + */ +static inline void SCTIMER_ClearEventInState(SCT_Type *base, uint32_t event, uint32_t state) +{ + assert(state < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_STATES); + assert(event < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_EVENTS); + + base->EV[event].STATE &= ~SCT_EV_STATE_STATEMSKn((uint32_t)1U << state); +} + +/*! + * @brief Get the state mask bit field of EV_STATE register. + * + * @note This function is to check whether the event is enabled in a specific state. + * + * @param base SCTimer peripheral base address + * @param event The EV_STATE register be read. + * @param state The state value. + * + * @return The the state mask bit field of EV_STATE register. + * - true: The event is enable in state. + * - false: The event is disable in state. + */ +static inline bool SCTIMER_GetEventInState(SCT_Type *base, uint32_t event, uint32_t state) +{ + assert(state < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_STATES); + assert(event < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_EVENTS); + + return (0U != (base->EV[event].STATE & SCT_EV_STATE_STATEMSKn((uint32_t)1U << state))); +} + +/*! + * @brief SCTimer interrupt handler. + * + * @param base SCTimer peripheral base address. + */ +void SCTIMER_EventHandleIRQ(SCT_Type *base); + +/*! @}*/ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_SCTIMER_H_ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_spi.c b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_spi.c new file mode 100644 index 0000000000..456361e620 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_spi.c @@ -0,0 +1,1072 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_spi.h" +#include "fsl_flexcomm.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.flexcomm_spi" +#endif + +/* Note: FIFOCFG[SIZE] has always value 1 = 8 items depth */ + +#if defined(FSL_FEATURE_SPI_FIFOSIZE_CFG) && (FSL_FEATURE_SPI_FIFOSIZE_CFG) +#define SPI_FIFO_DEPTH(base) 4 +#else +#define SPI_FIFO_DEPTH(base) ((((base)->FIFOCFG & SPI_FIFOCFG_SIZE_MASK) >> SPI_FIFOCFG_SIZE_SHIFT) << 3) +#endif /*FSL_FEATURE_SPI_FIFOSIZE_CFG*/ + +/* Convert transfer count to transfer bytes. dataWidth is a + * range <0,15>. Range <8,15> represents 2B transfer */ +#define SPI_COUNT_TO_BYTES(dataWidth, count) ((count) << ((dataWidth) >> 3U)) +#define SPI_BYTES_TO_COUNT(dataWidth, bytes) ((bytes) >> ((dataWidth) >> 3U)) +#if defined(FSL_FEATURE_SPI_IS_SSEL_PIN_COUNT_EQUAL_TO_THREE) && (FSL_FEATURE_SPI_IS_SSEL_PIN_COUNT_EQUAL_TO_THREE) +#define SPI_SSELPOL_MASK ((SPI_CFG_SPOL0_MASK) | (SPI_CFG_SPOL1_MASK) | (SPI_CFG_SPOL2_MASK)) +#else +#define SPI_SSELPOL_MASK ((SPI_CFG_SPOL0_MASK) | (SPI_CFG_SPOL1_MASK) | (SPI_CFG_SPOL2_MASK) | (SPI_CFG_SPOL3_MASK)) +#endif /*FSL_FEATURE_SPI_IS_SSEL_PIN_COUNT_EQUAL_TO_THREE*/ + +/*! + * @brief Used for conversion from `flexcomm_irq_handler_t` to `flexcomm_spi_master_irq_handler_t` and + * `flexcomm_spi_slave_irq_handler_t`. + */ +typedef union spi_to_flexcomm +{ + flexcomm_spi_master_irq_handler_t spi_master_handler; + flexcomm_spi_slave_irq_handler_t spi_slave_handler; + flexcomm_irq_handler_t flexcomm_handler; +} spi_to_flexcomm_t; + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief internal SPI config array */ +static spi_config_t g_configs[FSL_FEATURE_SOC_SPI_COUNT] = {(spi_data_width_t)0}; + +/*! @brief Array to map SPI instance number to base address. */ +static const uint32_t s_spiBaseAddrs[FSL_FEATURE_SOC_SPI_COUNT] = SPI_BASE_ADDRS; + +/*! @brief IRQ name array */ +static const IRQn_Type s_spiIRQ[] = SPI_IRQS; + +/* @brief Dummy data for each instance. This data is used when user's tx buffer is NULL*/ +volatile uint8_t s_dummyData[FSL_FEATURE_SOC_SPI_COUNT] = {0}; +/******************************************************************************* + * Code + ******************************************************************************/ + +/* Get the index corresponding to the FLEXCOMM */ +/*! brief Returns instance number for SPI peripheral base address. */ +uint32_t SPI_GetInstance(SPI_Type *base) +{ + uint32_t i; + + for (i = 0U; i < (uint32_t)FSL_FEATURE_SOC_SPI_COUNT; i++) + { + if ((uint32_t)base == s_spiBaseAddrs[i]) + { + break; + } + } + + assert(i < (uint32_t)FSL_FEATURE_SOC_SPI_COUNT); + return i; +} + +/*! + * brief Set up the dummy data. + * + * param base SPI peripheral address. + * param dummyData Data to be transferred when tx buffer is NULL. + */ +void SPI_SetDummyData(SPI_Type *base, uint8_t dummyData) +{ + uint32_t instance = SPI_GetInstance(base); + s_dummyData[instance] = dummyData; +} + +/*! + * brief Returns the configurations. + * + * param base SPI peripheral address. + * return return configurations which contain datawidth and SSEL numbers. + * return data type is a pointer of spi_config_t. + */ +void *SPI_GetConfig(SPI_Type *base) +{ + uint32_t instance; + instance = SPI_GetInstance(base); + return &g_configs[instance]; +} + +/*! + * brief Sets the SPI master configuration structure to default values. + * + * The purpose of this API is to get the configuration structure initialized for use in SPI_MasterInit(). + * User may use the initialized structure unchanged in SPI_MasterInit(), or modify + * some fields of the structure before calling SPI_MasterInit(). After calling this API, + * the master is ready to transfer. + * Example: + code + spi_master_config_t config; + SPI_MasterGetDefaultConfig(&config); + endcode + * + * param config pointer to master config structure + */ +void SPI_MasterGetDefaultConfig(spi_master_config_t *config) +{ + assert(NULL != config); + + /* Initializes the configure structure to zero. */ + (void)memset(config, 0, sizeof(*config)); + + config->enableLoopback = false; + config->enableMaster = true; + config->polarity = kSPI_ClockPolarityActiveHigh; + config->phase = kSPI_ClockPhaseFirstEdge; + config->direction = kSPI_MsbFirst; + config->baudRate_Bps = 500000U; + config->dataWidth = kSPI_Data8Bits; + config->sselNum = kSPI_Ssel0; + config->txWatermark = (uint8_t)kSPI_TxFifo0; + config->rxWatermark = (uint8_t)kSPI_RxFifo1; + config->sselPol = kSPI_SpolActiveAllLow; + config->delayConfig.preDelay = 0U; + config->delayConfig.postDelay = 0U; + config->delayConfig.frameDelay = 0U; + config->delayConfig.transferDelay = 0U; +} + +/*! + * brief Initializes the SPI with master configuration. + * + * The configuration structure can be filled by user from scratch, or be set with default + * values by SPI_MasterGetDefaultConfig(). After calling this API, the slave is ready to transfer. + * Example + code + spi_master_config_t config = { + .baudRate_Bps = 400000, + ... + }; + SPI_MasterInit(SPI0, &config); + endcode + * + * param base SPI base pointer + * param config pointer to master configuration structure + * param srcClock_Hz Source clock frequency. + */ +status_t SPI_MasterInit(SPI_Type *base, const spi_master_config_t *config, uint32_t srcClock_Hz) +{ + status_t result = kStatus_Success; + uint32_t instance; + uint32_t tmpConfig; + + /* assert params */ + assert(!((NULL == base) || (NULL == config) || (0U == srcClock_Hz))); + if ((NULL == base) || (NULL == config) || (0U == srcClock_Hz)) + { + return kStatus_InvalidArgument; + } + + /* initialize flexcomm to SPI mode */ + result = FLEXCOMM_Init(base, FLEXCOMM_PERIPH_SPI); + if (kStatus_Success != result) + { + return result; + } + + /* set divider */ + result = SPI_MasterSetBaud(base, config->baudRate_Bps, srcClock_Hz); + if (kStatus_Success != result) + { + return result; + } + + /* get instance number */ + instance = SPI_GetInstance(base); + + /* configure SPI mode */ + tmpConfig = base->CFG; + tmpConfig &= ~(SPI_CFG_MASTER_MASK | SPI_CFG_LSBF_MASK | SPI_CFG_CPHA_MASK | SPI_CFG_CPOL_MASK | SPI_CFG_LOOP_MASK | + SPI_CFG_ENABLE_MASK | SPI_SSELPOL_MASK); + /* phase */ + tmpConfig |= SPI_CFG_CPHA(config->phase); + /* polarity */ + tmpConfig |= SPI_CFG_CPOL(config->polarity); + /* direction */ + tmpConfig |= SPI_CFG_LSBF(config->direction); + /* master mode */ + tmpConfig |= SPI_CFG_MASTER(1); + /* loopback */ + tmpConfig |= SPI_CFG_LOOP(config->enableLoopback); + /* configure active level for all CS */ + tmpConfig |= ((uint32_t)config->sselPol & (SPI_SSELPOL_MASK)); + base->CFG = tmpConfig; + + /* store configuration */ + g_configs[instance].dataWidth = config->dataWidth; + g_configs[instance].sselNum = config->sselNum; + /* enable FIFOs */ + base->FIFOCFG |= SPI_FIFOCFG_EMPTYTX_MASK | SPI_FIFOCFG_EMPTYRX_MASK; + base->FIFOCFG |= SPI_FIFOCFG_ENABLETX_MASK | SPI_FIFOCFG_ENABLERX_MASK; + /* trigger level - empty txFIFO, one item in rxFIFO */ + tmpConfig = base->FIFOTRIG & (~(SPI_FIFOTRIG_RXLVL_MASK | SPI_FIFOTRIG_TXLVL_MASK)); + tmpConfig |= SPI_FIFOTRIG_TXLVL(config->txWatermark) | SPI_FIFOTRIG_RXLVL(config->rxWatermark); + /* enable generating interrupts for FIFOTRIG levels */ + tmpConfig |= SPI_FIFOTRIG_TXLVLENA_MASK | SPI_FIFOTRIG_RXLVLENA_MASK; + /* set FIFOTRIG */ + base->FIFOTRIG = tmpConfig; + + /* Set the delay configuration. */ + SPI_SetTransferDelay(base, &config->delayConfig); + /* Set the dummy data. */ + SPI_SetDummyData(base, (uint8_t)SPI_DUMMYDATA); + + SPI_Enable(base, config->enableMaster); + return kStatus_Success; +} + +/*! + * brief Sets the SPI slave configuration structure to default values. + * + * The purpose of this API is to get the configuration structure initialized for use in SPI_SlaveInit(). + * Modify some fields of the structure before calling SPI_SlaveInit(). + * Example: + code + spi_slave_config_t config; + SPI_SlaveGetDefaultConfig(&config); + endcode + * + * param config pointer to slave configuration structure + */ +void SPI_SlaveGetDefaultConfig(spi_slave_config_t *config) +{ + assert(NULL != config); + + /* Initializes the configure structure to zero. */ + (void)memset(config, 0, sizeof(*config)); + + config->enableSlave = true; + config->polarity = kSPI_ClockPolarityActiveHigh; + config->phase = kSPI_ClockPhaseFirstEdge; + config->direction = kSPI_MsbFirst; + config->dataWidth = kSPI_Data8Bits; + config->txWatermark = (uint8_t)kSPI_TxFifo0; + config->rxWatermark = (uint8_t)kSPI_RxFifo1; + config->sselPol = kSPI_SpolActiveAllLow; +} + +/*! + * brief Initializes the SPI with slave configuration. + * + * The configuration structure can be filled by user from scratch or be set with + * default values by SPI_SlaveGetDefaultConfig(). + * After calling this API, the slave is ready to transfer. + * Example + code + spi_slave_config_t config = { + .polarity = flexSPIClockPolarity_ActiveHigh; + .phase = flexSPIClockPhase_FirstEdge; + .direction = flexSPIMsbFirst; + ... + }; + SPI_SlaveInit(SPI0, &config); + endcode + * + * param base SPI base pointer + * param config pointer to slave configuration structure + */ +status_t SPI_SlaveInit(SPI_Type *base, const spi_slave_config_t *config) +{ + status_t result = kStatus_Success; + uint32_t instance; + uint32_t tmpConfig; + + /* assert params */ + assert(!((NULL == base) || (NULL == config))); + if ((NULL == base) || (NULL == config)) + { + return kStatus_InvalidArgument; + } + /* configure flexcomm to SPI, enable clock gate */ + result = FLEXCOMM_Init(base, FLEXCOMM_PERIPH_SPI); + if (kStatus_Success != result) + { + return result; + } + + instance = SPI_GetInstance(base); + + /* configure SPI mode */ + tmpConfig = base->CFG; + tmpConfig &= ~(SPI_CFG_MASTER_MASK | SPI_CFG_LSBF_MASK | SPI_CFG_CPHA_MASK | SPI_CFG_CPOL_MASK | + SPI_CFG_ENABLE_MASK | SPI_SSELPOL_MASK); + /* phase */ + tmpConfig |= SPI_CFG_CPHA(config->phase); + /* polarity */ + tmpConfig |= SPI_CFG_CPOL(config->polarity); + /* direction */ + tmpConfig |= SPI_CFG_LSBF(config->direction); + /* configure active level for all CS */ + tmpConfig |= ((uint32_t)config->sselPol & (SPI_SSELPOL_MASK)); + base->CFG = tmpConfig; + + /* store configuration */ + g_configs[instance].dataWidth = config->dataWidth; + /* empty and enable FIFOs */ + base->FIFOCFG |= SPI_FIFOCFG_EMPTYTX_MASK | SPI_FIFOCFG_EMPTYRX_MASK; + base->FIFOCFG |= SPI_FIFOCFG_ENABLETX_MASK | SPI_FIFOCFG_ENABLERX_MASK; + /* trigger level - empty txFIFO, one item in rxFIFO */ + tmpConfig = base->FIFOTRIG & (~(SPI_FIFOTRIG_RXLVL_MASK | SPI_FIFOTRIG_TXLVL_MASK)); + tmpConfig |= SPI_FIFOTRIG_TXLVL(config->txWatermark) | SPI_FIFOTRIG_RXLVL(config->rxWatermark); + /* enable generating interrupts for FIFOTRIG levels */ + tmpConfig |= SPI_FIFOTRIG_TXLVLENA_MASK | SPI_FIFOTRIG_RXLVLENA_MASK; + /* set FIFOTRIG */ + base->FIFOTRIG = tmpConfig; + + SPI_SetDummyData(base, (uint8_t)SPI_DUMMYDATA); + + SPI_Enable(base, config->enableSlave); + return kStatus_Success; +} + +/*! + * brief De-initializes the SPI. + * + * Calling this API resets the SPI module, gates the SPI clock. + * The SPI module can't work unless calling the SPI_MasterInit/SPI_SlaveInit to initialize module. + * + * param base SPI base pointer + */ +void SPI_Deinit(SPI_Type *base) +{ + /* Assert arguments */ + assert(NULL != base); + /* Disable interrupts, disable dma requests, disable peripheral */ + base->FIFOINTENCLR = SPI_FIFOINTENCLR_TXERR_MASK | SPI_FIFOINTENCLR_RXERR_MASK | SPI_FIFOINTENCLR_TXLVL_MASK | + SPI_FIFOINTENCLR_RXLVL_MASK; + base->FIFOCFG &= ~(SPI_FIFOCFG_DMATX_MASK | SPI_FIFOCFG_DMARX_MASK); + base->CFG &= ~(SPI_CFG_ENABLE_MASK); +} + +/*! + * brief Enables the DMA request from SPI txFIFO. + * + * param base SPI base pointer + * param enable True means enable DMA, false means disable DMA + */ +void SPI_EnableTxDMA(SPI_Type *base, bool enable) +{ + if (enable) + { + base->FIFOCFG |= SPI_FIFOCFG_DMATX_MASK; + } + else + { + base->FIFOCFG &= ~SPI_FIFOCFG_DMATX_MASK; + } +} + +/*! + * brief Enables the DMA request from SPI rxFIFO. + * + * param base SPI base pointer + * param enable True means enable DMA, false means disable DMA + */ +void SPI_EnableRxDMA(SPI_Type *base, bool enable) +{ + if (enable) + { + base->FIFOCFG |= SPI_FIFOCFG_DMARX_MASK; + } + else + { + base->FIFOCFG &= ~SPI_FIFOCFG_DMARX_MASK; + } +} + +/*! + * brief Sets the baud rate for SPI transfer. This is only used in master. + * + * param base SPI base pointer + * param baudrate_Bps baud rate needed in Hz. + * param srcClock_Hz SPI source clock frequency in Hz. + */ +status_t SPI_MasterSetBaud(SPI_Type *base, uint32_t baudrate_Bps, uint32_t srcClock_Hz) +{ + uint32_t tmpDiv; + + /* assert params */ + assert(!((NULL == base) || (0U == baudrate_Bps) || (0U == srcClock_Hz))); + if ((NULL == base) || (0U == baudrate_Bps) || (0U == srcClock_Hz)) + { + return kStatus_InvalidArgument; + } + + /* calculate baudrate, round up the result */ + tmpDiv = ((srcClock_Hz * 10U) / baudrate_Bps + 5U) / 10U - 1U; + if (tmpDiv > 0xFFFFU) + { + return kStatus_SPI_BaudrateNotSupport; + } + base->DIV &= ~SPI_DIV_DIVVAL_MASK; + base->DIV |= SPI_DIV_DIVVAL(tmpDiv); + return kStatus_Success; +} + +/*! + * brief Writes a data into the SPI data register. + * + * param base SPI base pointer + * param data needs to be write. + * param configFlags transfer configuration options ref spi_xfer_option_t + */ +void SPI_WriteData(SPI_Type *base, uint16_t data, uint32_t configFlags) +{ + uint32_t control = 0U; + uint32_t instance; + + /* check params */ + assert(NULL != base); + /* get and check instance */ + instance = SPI_GetInstance(base); + + /* set data width */ + control |= (uint32_t)SPI_FIFOWR_LEN((g_configs[instance].dataWidth)); + /* set sssel */ + control |= (SPI_DEASSERT_ALL & (~SPI_DEASSERTNUM_SSEL((uint32_t)(g_configs[instance].sselNum)))); + /* mask configFlags */ + control |= (configFlags & (uint32_t)SPI_FIFOWR_FLAGS_MASK); + /* control should not affect lower 16 bits */ + assert(0U == (control & 0xFFFFU)); + base->FIFOWR = data | control; +} + +/*! + * brief Initializes the SPI master handle. + * + * This function initializes the SPI master handle which can be used for other SPI master transactional APIs. Usually, + * for a specified SPI instance, call this API once to get the initialized handle. + * + * param base SPI peripheral base address. + * param handle SPI handle pointer. + * param callback Callback function. + * param userData User data. + */ +status_t SPI_MasterTransferCreateHandle(SPI_Type *base, + spi_master_handle_t *handle, + spi_master_callback_t callback, + void *userData) +{ + /* check 'base' */ + assert(NULL != base); + /* check 'handle' */ + assert(NULL != handle); + + uint32_t instance; + spi_to_flexcomm_t handler; + + /* get flexcomm instance by 'base' param */ + instance = SPI_GetInstance(base); + + (void)memset(handle, 0, sizeof(*handle)); + /* Initialize the handle */ + if ((base->CFG & SPI_CFG_MASTER_MASK) != 0U) + { + handler.spi_master_handler = SPI_MasterTransferHandleIRQ; + FLEXCOMM_SetIRQHandler(base, handler.flexcomm_handler, handle); + } + else + { + handler.spi_slave_handler = SPI_SlaveTransferHandleIRQ; + FLEXCOMM_SetIRQHandler(base, handler.flexcomm_handler, handle); + } + + handle->dataWidth = (uint8_t)(g_configs[instance].dataWidth); + /* in slave mode, the sselNum is not important */ + handle->sselNum = (uint8_t)(g_configs[instance].sselNum); + handle->txWatermark = (uint8_t)SPI_FIFOTRIG_TXLVL_GET(base); + handle->rxWatermark = (uint8_t)SPI_FIFOTRIG_RXLVL_GET(base); + handle->callback = callback; + handle->userData = userData; + + /* Enable SPI NVIC */ + (void)EnableIRQ(s_spiIRQ[instance]); + + return kStatus_Success; +} + +/*! + * brief Transfers a block of data using a polling method. + * + * param base SPI base pointer + * param xfer pointer to spi_xfer_config_t structure + * retval kStatus_Success Successfully start a transfer. + * retval kStatus_InvalidArgument Input argument is invalid. + * retval kStatus_SPI_Timeout The transfer timed out and was aborted. + */ +status_t SPI_MasterTransferBlocking(SPI_Type *base, spi_transfer_t *xfer) +{ + uint32_t instance; + uint32_t tx_ctrl = 0U, last_ctrl = 0U; + uint32_t tmp32, rxRemainingBytes, txRemainingBytes, dataWidth; + uint32_t toReceiveCount = 0; + uint8_t *txData, *rxData; + uint32_t fifoDepth; +#if SPI_RETRY_TIMES + uint32_t waitTimes = SPI_RETRY_TIMES; +#endif + + /* check params */ + assert(!((NULL == base) || (NULL == xfer) || ((NULL == xfer->txData) && (NULL == xfer->rxData)))); + if ((NULL == base) || (NULL == xfer) || ((NULL == xfer->txData) && (NULL == xfer->rxData))) + { + return kStatus_InvalidArgument; + } + + fifoDepth = SPI_FIFO_DEPTH(base); + txData = xfer->txData; + rxData = xfer->rxData; + txRemainingBytes = (txData != NULL) ? xfer->dataSize : 0U; + rxRemainingBytes = (rxData != NULL) ? xfer->dataSize : 0U; + + instance = SPI_GetInstance(base); + dataWidth = (uint32_t)(g_configs[instance].dataWidth); + + /* dataSize (in bytes) is not aligned to 16bit (2B) transfer */ + if ((dataWidth > (uint32_t)kSPI_Data8Bits) && ((xfer->dataSize & 0x1U) != 0U)) + { + return kStatus_InvalidArgument; + } + + /* clear tx/rx errors and empty FIFOs */ + base->FIFOCFG |= SPI_FIFOCFG_EMPTYTX_MASK | SPI_FIFOCFG_EMPTYRX_MASK; + base->FIFOSTAT |= SPI_FIFOSTAT_TXERR_MASK | SPI_FIFOSTAT_RXERR_MASK; + /* select slave to talk with */ + tx_ctrl |= (SPI_DEASSERT_ALL & (~SPI_DEASSERTNUM_SSEL((uint32_t)(g_configs[instance].sselNum)))); + /* set width of data - range asserted at entry */ + tx_ctrl |= SPI_FIFOWR_LEN(dataWidth); + /* delay for frames */ + tx_ctrl |= ((xfer->configFlags & (uint32_t)kSPI_FrameDelay) != 0U) ? (uint32_t)kSPI_FrameDelay : 0U; + /* end of transfer */ + last_ctrl |= ((xfer->configFlags & (uint32_t)kSPI_FrameAssert) != 0U) ? (uint32_t)kSPI_FrameAssert : 0U; + /* last index of loop */ + while ((txRemainingBytes != 0U) || (rxRemainingBytes != 0U) || (toReceiveCount != 0U)) + { +#if SPI_RETRY_TIMES + if (--waitTimes == 0U) + { + return kStatus_SPI_Timeout; + } +#endif + /* if rxFIFO is not empty */ + if ((base->FIFOSTAT & SPI_FIFOSTAT_RXNOTEMPTY_MASK) != 0U) + { + tmp32 = base->FIFORD; + /* rxBuffer is not empty */ + if (rxRemainingBytes != 0U) + { + *(rxData++) = (uint8_t)tmp32; + rxRemainingBytes--; + /* read 16 bits at once */ + if (dataWidth > 8U) + { + *(rxData++) = (uint8_t)(tmp32 >> 8); + rxRemainingBytes--; + } + } + /* decrease number of data expected to receive */ + toReceiveCount -= 1U; + } + /* transmit if txFIFO is not full and data to receive does not exceed FIFO depth */ + if (((base->FIFOSTAT & SPI_FIFOSTAT_TXNOTFULL_MASK) != 0U) && (toReceiveCount < fifoDepth) && + ((txRemainingBytes != 0U) || (rxRemainingBytes >= SPI_COUNT_TO_BYTES(dataWidth, toReceiveCount + 1U)))) + { + /* txBuffer is not empty */ + if (txRemainingBytes != 0U) + { + tmp32 = *(txData++); + txRemainingBytes--; + /* write 16 bit at once */ + if (dataWidth > 8U) + { + tmp32 |= ((uint32_t)(*(txData++))) << 8U; + txRemainingBytes--; + } + if (txRemainingBytes == 0U) + { + tx_ctrl |= last_ctrl; + } + } + else + { + tmp32 = (uint32_t)s_dummyData[instance]; + tmp32 |= (uint32_t)s_dummyData[instance] << 8U; + /* last transfer */ + if (rxRemainingBytes == SPI_COUNT_TO_BYTES(dataWidth, toReceiveCount + 1U)) + { + tx_ctrl |= last_ctrl; + } + } + /* send data */ + tmp32 = tx_ctrl | tmp32; + base->FIFOWR = tmp32; + toReceiveCount += 1U; + } + } + /* wait if TX FIFO of previous transfer is not empty */ +#if SPI_RETRY_TIMES + waitTimes = SPI_RETRY_TIMES; + while ((0U == (base->FIFOSTAT & SPI_FIFOSTAT_TXEMPTY_MASK)) && (0U != --waitTimes)) +#else + while (0U == (base->FIFOSTAT & SPI_FIFOSTAT_TXEMPTY_MASK)) +#endif + { + } +#if SPI_RETRY_TIMES + if (waitTimes == 0U) + { + return kStatus_SPI_Timeout; + } +#endif + return kStatus_Success; +} + +/*! + * brief Performs a non-blocking SPI interrupt transfer. + * + * param base SPI peripheral base address. + * param handle pointer to spi_master_handle_t structure which stores the transfer state + * param xfer pointer to spi_xfer_config_t structure + * retval kStatus_Success Successfully start a transfer. + * retval kStatus_InvalidArgument Input argument is invalid. + * retval kStatus_SPI_Busy SPI is not idle, is running another transfer. + */ +status_t SPI_MasterTransferNonBlocking(SPI_Type *base, spi_master_handle_t *handle, spi_transfer_t *xfer) +{ + /* check params */ + assert( + !((NULL == base) || (NULL == handle) || (NULL == xfer) || ((NULL == xfer->txData) && (NULL == xfer->rxData)))); + if ((NULL == base) || (NULL == handle) || (NULL == xfer) || ((NULL == xfer->txData) && (NULL == xfer->rxData))) + { + return kStatus_InvalidArgument; + } + + /* dataSize (in bytes) is not aligned to 16bit (2B) transfer */ + assert(!((handle->dataWidth > (uint8_t)kSPI_Data8Bits) && ((xfer->dataSize & 0x1U) != 0U))); + if ((handle->dataWidth > (uint8_t)kSPI_Data8Bits) && ((xfer->dataSize & 0x1U) != 0U)) + { + return kStatus_InvalidArgument; + } + + /* Check if SPI is busy */ + if (handle->state == (uint32_t)kStatus_SPI_Busy) + { + return kStatus_SPI_Busy; + } + + /* Set the handle information */ + handle->txData = xfer->txData; + handle->rxData = xfer->rxData; + /* set count */ + handle->txRemainingBytes = (xfer->txData != NULL) ? xfer->dataSize : 0U; + handle->rxRemainingBytes = (xfer->rxData != NULL) ? xfer->dataSize : 0U; + handle->totalByteCount = xfer->dataSize; + /* other options */ + handle->toReceiveCount = 0; + handle->configFlags = xfer->configFlags; + /* Set the SPI state to busy */ + handle->state = (uint32_t)kStatus_SPI_Busy; + /* clear FIFOs when transfer starts */ + base->FIFOCFG |= SPI_FIFOCFG_EMPTYTX_MASK | SPI_FIFOCFG_EMPTYRX_MASK; + base->FIFOSTAT |= SPI_FIFOSTAT_TXERR_MASK | SPI_FIFOSTAT_RXERR_MASK; + /* enable generating txIRQ and rxIRQ, first transfer is fired by empty txFIFO */ + base->FIFOINTENSET |= SPI_FIFOINTENSET_TXLVL_MASK | SPI_FIFOINTENSET_RXLVL_MASK; + return kStatus_Success; +} + +/*! + * brief Transfers a block of data using a polling method. + * + * This function will do a half-duplex transfer for SPI master, This is a blocking function, + * which does not retuen until all transfer have been completed. And data transfer mechanism is half-duplex, + * users can set transmit first or receive first. + * + * param base SPI base pointer + * param xfer pointer to spi_half_duplex_transfer_t structure + * return status of status_t. + */ +status_t SPI_MasterHalfDuplexTransferBlocking(SPI_Type *base, spi_half_duplex_transfer_t *xfer) +{ + assert(xfer != NULL); + + spi_transfer_t tempXfer = {0}; + status_t status; + + if (xfer->isTransmitFirst) + { + tempXfer.txData = xfer->txData; + tempXfer.rxData = NULL; + tempXfer.dataSize = xfer->txDataSize; + } + else + { + tempXfer.txData = NULL; + tempXfer.rxData = xfer->rxData; + tempXfer.dataSize = xfer->rxDataSize; + } + /* If the pcs pin keep assert between transmit and receive. */ + if (xfer->isPcsAssertInTransfer) + { + tempXfer.configFlags = (xfer->configFlags) & (~(uint32_t)kSPI_FrameAssert); + } + else + { + tempXfer.configFlags = (xfer->configFlags) | (uint32_t)kSPI_FrameAssert; + } + + status = SPI_MasterTransferBlocking(base, &tempXfer); + + if (status != kStatus_Success) + { + return status; + } + + if (xfer->isTransmitFirst) + { + tempXfer.txData = NULL; + tempXfer.rxData = xfer->rxData; + tempXfer.dataSize = xfer->rxDataSize; + } + else + { + tempXfer.txData = xfer->txData; + tempXfer.rxData = NULL; + tempXfer.dataSize = xfer->txDataSize; + } + tempXfer.configFlags = xfer->configFlags; + + /* SPI transfer blocking. */ + status = SPI_MasterTransferBlocking(base, &tempXfer); + + return status; +} + +/*! + * brief Performs a non-blocking SPI interrupt transfer. + * + * This function using polling way to do the first half transimission and using interrupts to + * do the second half transimission, the transfer mechanism is half-duplex. + * When do the second half transimission, code will return right away. When all data is transferred, + * the callback function is called. + * + * param base SPI peripheral base address. + * param handle pointer to spi_master_handle_t structure which stores the transfer state + * param xfer pointer to spi_half_duplex_transfer_t structure + * return status of status_t. + */ +status_t SPI_MasterHalfDuplexTransferNonBlocking(SPI_Type *base, + spi_master_handle_t *handle, + spi_half_duplex_transfer_t *xfer) +{ + assert(xfer != NULL); + assert(handle != NULL); + spi_transfer_t tempXfer = {0}; + status_t status; + + if (xfer->isTransmitFirst) + { + tempXfer.txData = xfer->txData; + tempXfer.rxData = NULL; + tempXfer.dataSize = xfer->txDataSize; + } + else + { + tempXfer.txData = NULL; + tempXfer.rxData = xfer->rxData; + tempXfer.dataSize = xfer->rxDataSize; + } + /* If the PCS pin keep assert between transmit and receive. */ + if (xfer->isPcsAssertInTransfer) + { + tempXfer.configFlags = (xfer->configFlags) & (~(uint32_t)kSPI_FrameAssert); + } + else + { + tempXfer.configFlags = (xfer->configFlags) | (uint32_t)kSPI_FrameAssert; + } + + status = SPI_MasterTransferBlocking(base, &tempXfer); + if (status != kStatus_Success) + { + return status; + } + + if (xfer->isTransmitFirst) + { + tempXfer.txData = NULL; + tempXfer.rxData = xfer->rxData; + tempXfer.dataSize = xfer->rxDataSize; + } + else + { + tempXfer.txData = xfer->txData; + tempXfer.rxData = NULL; + tempXfer.dataSize = xfer->txDataSize; + } + tempXfer.configFlags = xfer->configFlags; + + status = SPI_MasterTransferNonBlocking(base, handle, &tempXfer); + + return status; +} + +/*! + * brief Gets the master transfer count. + * + * This function gets the master transfer count. + * + * param base SPI peripheral base address. + * param handle Pointer to the spi_master_handle_t structure which stores the transfer state. + * param count The number of bytes transferred by using the non-blocking transaction. + * return status of status_t. + */ +status_t SPI_MasterTransferGetCount(SPI_Type *base, spi_master_handle_t *handle, size_t *count) +{ + assert(NULL != handle); + + if (NULL == count) + { + return kStatus_InvalidArgument; + } + + /* Catch when there is not an active transfer. */ + if (handle->state != (uint32_t)kStatus_SPI_Busy) + { + *count = 0; + return kStatus_NoTransferInProgress; + } + + *count = handle->totalByteCount - handle->rxRemainingBytes; + return kStatus_Success; +} + +/*! + * brief SPI master aborts a transfer using an interrupt. + * + * This function aborts a transfer using an interrupt. + * + * param base SPI peripheral base address. + * param handle Pointer to the spi_master_handle_t structure which stores the transfer state. + */ +void SPI_MasterTransferAbort(SPI_Type *base, spi_master_handle_t *handle) +{ + assert(NULL != handle); + + /* Disable interrupt requests*/ + base->FIFOINTENSET &= ~(SPI_FIFOINTENSET_TXLVL_MASK | SPI_FIFOINTENSET_RXLVL_MASK); + /* Empty FIFOs */ + base->FIFOCFG |= SPI_FIFOCFG_EMPTYTX_MASK | SPI_FIFOCFG_EMPTYRX_MASK; + + handle->state = (uint32_t)kStatus_SPI_Idle; + handle->txRemainingBytes = 0U; + handle->rxRemainingBytes = 0U; +} + +static void SPI_TransferHandleIRQInternal(SPI_Type *base, spi_master_handle_t *handle) +{ + uint32_t tx_ctrl = 0U, last_ctrl = 0U, tmp32; + bool loopContinue; + uint32_t fifoDepth; + /* Get flexcomm instance by 'base' param */ + uint32_t instance = SPI_GetInstance(base); + size_t txRemainingBytes; + size_t rxRemainingBytes; + uint8_t toReceiveCount; + + /* check params */ + assert((NULL != base) && (NULL != handle) && ((NULL != handle->txData) || (NULL != handle->rxData))); + + fifoDepth = SPI_FIFO_DEPTH(base); + /* select slave to talk with */ + tx_ctrl |= ((uint32_t)SPI_DEASSERT_ALL & (uint32_t)SPI_ASSERTNUM_SSEL(handle->sselNum)); + /* set width of data */ + tx_ctrl |= SPI_FIFOWR_LEN(handle->dataWidth); + /* delay for frames */ + tx_ctrl |= ((handle->configFlags & (uint32_t)kSPI_FrameDelay) != 0U) ? (uint32_t)kSPI_FrameDelay : 0U; + /* end of transfer */ + last_ctrl |= ((handle->configFlags & (uint32_t)kSPI_FrameAssert) != 0U) ? (uint32_t)kSPI_FrameAssert : 0U; + do + { + loopContinue = false; + + /* rxFIFO is not empty */ + if ((base->FIFOSTAT & SPI_FIFOSTAT_RXNOTEMPTY_MASK) != 0U) + { + tmp32 = base->FIFORD; + /* rxBuffer is not empty */ + if (handle->rxRemainingBytes != 0U) + { + /* low byte must go first */ + *(handle->rxData++) = (uint8_t)tmp32; + handle->rxRemainingBytes--; + /* read 16 bits at once */ + if (handle->dataWidth > (uint8_t)kSPI_Data8Bits) + { + *(handle->rxData++) = (uint8_t)(tmp32 >> 8); + handle->rxRemainingBytes--; + } + } + + /* decrease number of data expected to receive */ + handle->toReceiveCount -= 1; + loopContinue = true; + } + + /* - txFIFO is not full + * - we cannot cause rxFIFO overflow by sending more data than is the depth of FIFO + * - txBuffer is not empty or the next 'toReceiveCount' data can fit into rxBuffer + */ + txRemainingBytes = handle->txRemainingBytes; + rxRemainingBytes = handle->rxRemainingBytes; + toReceiveCount = (handle->toReceiveCount > 0) ? (uint8_t)handle->toReceiveCount : 0U; + if (((base->FIFOSTAT & SPI_FIFOSTAT_TXNOTFULL_MASK) != 0U) && ((uint32_t)toReceiveCount < fifoDepth) && + ((txRemainingBytes != 0U) || + (rxRemainingBytes >= SPI_COUNT_TO_BYTES(handle->dataWidth, (uint32_t)toReceiveCount + 1U)))) + { + /* txBuffer is not empty */ + if ((txRemainingBytes != 0U) && (handle->txData != NULL)) + { + /* low byte must go first */ + tmp32 = *(handle->txData++); + handle->txRemainingBytes--; + txRemainingBytes = handle->txRemainingBytes; + /* write 16 bit at once */ + if (handle->dataWidth > (uint8_t)kSPI_Data8Bits) + { + tmp32 |= ((uint32_t)(*(handle->txData++))) << 8U; + handle->txRemainingBytes--; + txRemainingBytes = handle->txRemainingBytes; + } + /* last transfer */ + if (handle->txRemainingBytes == 0U) + { + tx_ctrl |= last_ctrl; + } + } + else + { + tmp32 = (uint32_t)s_dummyData[instance]; + tmp32 |= (uint32_t)s_dummyData[instance] << 8U; + /* last transfer */ + if (rxRemainingBytes == SPI_COUNT_TO_BYTES(handle->dataWidth, (uint32_t)toReceiveCount + 1U)) + { + tx_ctrl |= last_ctrl; + } + } + /* send data */ + tmp32 = tx_ctrl | tmp32; + base->FIFOWR = tmp32; + /* increase number of expected data to receive */ + handle->toReceiveCount += 1; + toReceiveCount = (handle->toReceiveCount > 0) ? (uint8_t)handle->toReceiveCount : 0U; + loopContinue = true; + } + } while (loopContinue); +} + +/*! + * brief Interrupts the handler for the SPI. + * + * param base SPI peripheral base address. + * param handle pointer to spi_master_handle_t structure which stores the transfer state. + */ +void SPI_MasterTransferHandleIRQ(SPI_Type *base, spi_master_handle_t *handle) +{ + assert((NULL != base) && (NULL != handle)); + size_t txRemainingBytes; + uint8_t toReceiveCount; + + /* IRQ behaviour: + * - first interrupt is triggered by empty txFIFO. The transfer function + * then tries empty rxFIFO and fill txFIFO interleaved that results to + * strategy to process as many items as possible. + * - the next IRQs can be: + * rxIRQ from nonempty rxFIFO which requires to empty rxFIFO. + * txIRQ from empty txFIFO which requires to refill txFIFO. + * - last interrupt is triggered by empty txFIFO. The last state is + * known by empty rxBuffer and txBuffer. If there is nothing to receive + * or send - both operations have been finished and interrupts can be + * disabled. + */ + + /* Data to send or read or expected to receive */ + if ((handle->txRemainingBytes != 0U) || (handle->rxRemainingBytes != 0U) || (handle->toReceiveCount != 0)) + { + /* Transmit or receive data */ + SPI_TransferHandleIRQInternal(base, handle); + /* No data to send or read or receive. Transfer ends. Set txTrigger to 0 level and + * enable txIRQ to confirm when txFIFO becomes empty */ + if ((0U == handle->txRemainingBytes) && (0U == handle->rxRemainingBytes) && (0 == handle->toReceiveCount)) + { + base->FIFOTRIG = base->FIFOTRIG & (~SPI_FIFOTRIG_TXLVL_MASK); + base->FIFOINTENSET |= SPI_FIFOINTENSET_TXLVL_MASK; + } + else + { + uint32_t rxRemainingCount = SPI_BYTES_TO_COUNT(handle->dataWidth, handle->rxRemainingBytes); + /* If, there are no data to send or rxFIFO is already filled with necessary number of dummy data, + * disable txIRQ. From this point only rxIRQ is used to receive data without any transmission */ + toReceiveCount = (handle->toReceiveCount > 0) ? (uint8_t)handle->toReceiveCount : 0U; + if ((0U == handle->txRemainingBytes) && (rxRemainingCount <= toReceiveCount)) + { + base->FIFOINTENCLR = SPI_FIFOINTENCLR_TXLVL_MASK; + } + /* Nothing to receive or transmit, but we still have pending data which are bellow rxLevel. + * Cannot clear rxFIFO, txFIFO might be still active */ + if (rxRemainingCount == 0U) + { + txRemainingBytes = handle->txRemainingBytes; + if ((txRemainingBytes == 0U) && (toReceiveCount != 0U) && + (toReceiveCount < SPI_FIFOTRIG_RXLVL_GET(base) + 1U)) + { + base->FIFOTRIG = (base->FIFOTRIG & (~SPI_FIFOTRIG_RXLVL_MASK)) | + SPI_FIFOTRIG_RXLVL((uint32_t)toReceiveCount - 1U); + } + } + else + { + /* Expected to receive less data than rxLevel value, we have to update rxLevel */ + if (rxRemainingCount < (SPI_FIFOTRIG_RXLVL_GET(base) + 1U)) + { + base->FIFOTRIG = + (base->FIFOTRIG & (~SPI_FIFOTRIG_RXLVL_MASK)) | SPI_FIFOTRIG_RXLVL(rxRemainingCount - 1U); + } + } + } + } + else + { + /* Empty txFIFO is confirmed. Disable IRQs and restore triggers values */ + base->FIFOINTENCLR = SPI_FIFOINTENCLR_RXLVL_MASK | SPI_FIFOINTENCLR_TXLVL_MASK; + base->FIFOTRIG = (base->FIFOTRIG & (~(SPI_FIFOTRIG_RXLVL_MASK | SPI_FIFOTRIG_RXLVL_MASK))) | + SPI_FIFOTRIG_RXLVL(handle->rxWatermark) | SPI_FIFOTRIG_TXLVL(handle->txWatermark); + /* set idle state and call user callback */ + handle->state = (uint32_t)kStatus_SPI_Idle; + if (handle->callback != NULL) + { + (handle->callback)(base, handle, handle->state, handle->userData); + } + } +} diff --git a/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_spi.h b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_spi.h new file mode 100644 index 0000000000..2320e574cc --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_spi.h @@ -0,0 +1,746 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_SPI_H_ +#define _FSL_SPI_H_ + +#include "fsl_common.h" +#include "fsl_flexcomm.h" + +/*! + * @addtogroup spi_driver + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief SPI driver version. */ +#define FSL_SPI_DRIVER_VERSION (MAKE_VERSION(2, 2, 1)) +/*@}*/ + +/*! @brief Global variable for dummy data value setting. */ +extern volatile uint8_t s_dummyData[]; + +#ifndef SPI_DUMMYDATA +/*! @brief SPI dummy transfer data, the data is sent while txBuff is NULL. */ +#define SPI_DUMMYDATA (0xFFU) +#endif + +/*! @brief Retry times for waiting flag. */ +#ifndef SPI_RETRY_TIMES +#define SPI_RETRY_TIMES 0U /* Define to zero means keep waiting until the flag is assert/deassert. */ +#endif + +#define SPI_DATA(n) (((uint32_t)(n)) & 0xFFFFUL) +#define SPI_CTRLMASK (0xFFFF0000U) + +#define SPI_ASSERTNUM_SSEL(n) ((~(1UL << ((n) + 16UL))) & 0xF0000UL) +#define SPI_DEASSERTNUM_SSEL(n) (1UL << ((n) + 16UL)) +#define SPI_DEASSERT_ALL (0xF0000UL) + +#define SPI_FIFOWR_FLAGS_MASK (~(SPI_DEASSERT_ALL | SPI_FIFOWR_TXDATA_MASK | SPI_FIFOWR_LEN_MASK)) + +#define SPI_FIFOTRIG_TXLVL_GET(base) (((base)->FIFOTRIG & SPI_FIFOTRIG_TXLVL_MASK) >> SPI_FIFOTRIG_TXLVL_SHIFT) +#define SPI_FIFOTRIG_RXLVL_GET(base) (((base)->FIFOTRIG & SPI_FIFOTRIG_RXLVL_MASK) >> SPI_FIFOTRIG_RXLVL_SHIFT) + +/*! @brief SPI transfer option.*/ +typedef enum _spi_xfer_option +{ + kSPI_FrameDelay = (SPI_FIFOWR_EOF_MASK), /*!< A delay may be inserted, defined in the DLY register.*/ + kSPI_FrameAssert = (SPI_FIFOWR_EOT_MASK), /*!< SSEL will be deasserted at the end of a transfer */ +} spi_xfer_option_t; + +/*! @brief SPI data shifter direction options.*/ +typedef enum _spi_shift_direction +{ + kSPI_MsbFirst = 0U, /*!< Data transfers start with most significant bit. */ + kSPI_LsbFirst = 1U /*!< Data transfers start with least significant bit. */ +} spi_shift_direction_t; + +/*! @brief SPI clock polarity configuration.*/ +typedef enum _spi_clock_polarity +{ + kSPI_ClockPolarityActiveHigh = 0x0U, /*!< Active-high SPI clock (idles low). */ + kSPI_ClockPolarityActiveLow /*!< Active-low SPI clock (idles high). */ +} spi_clock_polarity_t; + +/*! @brief SPI clock phase configuration.*/ +typedef enum _spi_clock_phase +{ + kSPI_ClockPhaseFirstEdge = 0x0U, /*!< First edge on SCK occurs at the middle of the first + * cycle of a data transfer. */ + kSPI_ClockPhaseSecondEdge /*!< First edge on SCK occurs at the start of the + * first cycle of a data transfer. */ +} spi_clock_phase_t; + +/*! @brief txFIFO watermark values */ +typedef enum _spi_txfifo_watermark +{ + kSPI_TxFifo0 = 0, /*!< SPI tx watermark is empty */ + kSPI_TxFifo1 = 1, /*!< SPI tx watermark at 1 item */ + kSPI_TxFifo2 = 2, /*!< SPI tx watermark at 2 items */ + kSPI_TxFifo3 = 3, /*!< SPI tx watermark at 3 items */ + kSPI_TxFifo4 = 4, /*!< SPI tx watermark at 4 items */ + kSPI_TxFifo5 = 5, /*!< SPI tx watermark at 5 items */ + kSPI_TxFifo6 = 6, /*!< SPI tx watermark at 6 items */ + kSPI_TxFifo7 = 7, /*!< SPI tx watermark at 7 items */ +} spi_txfifo_watermark_t; + +/*! @brief rxFIFO watermark values */ +typedef enum _spi_rxfifo_watermark +{ + kSPI_RxFifo1 = 0, /*!< SPI rx watermark at 1 item */ + kSPI_RxFifo2 = 1, /*!< SPI rx watermark at 2 items */ + kSPI_RxFifo3 = 2, /*!< SPI rx watermark at 3 items */ + kSPI_RxFifo4 = 3, /*!< SPI rx watermark at 4 items */ + kSPI_RxFifo5 = 4, /*!< SPI rx watermark at 5 items */ + kSPI_RxFifo6 = 5, /*!< SPI rx watermark at 6 items */ + kSPI_RxFifo7 = 6, /*!< SPI rx watermark at 7 items */ + kSPI_RxFifo8 = 7, /*!< SPI rx watermark at 8 items */ +} spi_rxfifo_watermark_t; + +/*! @brief Transfer data width */ +typedef enum _spi_data_width +{ + kSPI_Data4Bits = 3, /*!< 4 bits data width */ + kSPI_Data5Bits = 4, /*!< 5 bits data width */ + kSPI_Data6Bits = 5, /*!< 6 bits data width */ + kSPI_Data7Bits = 6, /*!< 7 bits data width */ + kSPI_Data8Bits = 7, /*!< 8 bits data width */ + kSPI_Data9Bits = 8, /*!< 9 bits data width */ + kSPI_Data10Bits = 9, /*!< 10 bits data width */ + kSPI_Data11Bits = 10, /*!< 11 bits data width */ + kSPI_Data12Bits = 11, /*!< 12 bits data width */ + kSPI_Data13Bits = 12, /*!< 13 bits data width */ + kSPI_Data14Bits = 13, /*!< 14 bits data width */ + kSPI_Data15Bits = 14, /*!< 15 bits data width */ + kSPI_Data16Bits = 15, /*!< 16 bits data width */ +} spi_data_width_t; + +/*! @brief Slave select */ +typedef enum _spi_ssel +{ + kSPI_Ssel0 = 0, /*!< Slave select 0 */ + kSPI_Ssel1 = 1, /*!< Slave select 1 */ + kSPI_Ssel2 = 2, /*!< Slave select 2 */ + kSPI_Ssel3 = 3, /*!< Slave select 3 */ +} spi_ssel_t; + +/*! @brief ssel polarity */ +typedef enum _spi_spol +{ + kSPI_Spol0ActiveHigh = SPI_CFG_SPOL0(1), + kSPI_Spol1ActiveHigh = SPI_CFG_SPOL1(1), + kSPI_Spol2ActiveHigh = SPI_CFG_SPOL2(1), +#if defined(FSL_FEATURE_SPI_IS_SSEL_PIN_COUNT_EQUAL_TO_THREE) && (FSL_FEATURE_SPI_IS_SSEL_PIN_COUNT_EQUAL_TO_THREE) + kSPI_SpolActiveAllHigh = (kSPI_Spol0ActiveHigh | kSPI_Spol1ActiveHigh | kSPI_Spol2ActiveHigh), +#else + kSPI_Spol3ActiveHigh = SPI_CFG_SPOL3(1), + kSPI_SpolActiveAllHigh = + (kSPI_Spol0ActiveHigh | kSPI_Spol1ActiveHigh | kSPI_Spol2ActiveHigh | kSPI_Spol3ActiveHigh), +#endif + kSPI_SpolActiveAllLow = 0, +} spi_spol_t; + +/*! + * @brief SPI delay time configure structure. + * Note: + * The DLY register controls several programmable delays related to SPI signalling, + * it stands for how many SPI clock time will be inserted. + * The maxinun value of these delay time is 15. + */ +typedef struct _spi_delay_config +{ + uint8_t preDelay; /*!< Delay between SSEL assertion and the beginning of transfer. */ + uint8_t postDelay; /*!< Delay between the end of transfer and SSEL deassertion. */ + uint8_t frameDelay; /*!< Delay between frame to frame. */ + uint8_t transferDelay; /*!< Delay between transfer to transfer. */ +} spi_delay_config_t; + +/*! @brief SPI master user configure structure.*/ +typedef struct _spi_master_config +{ + bool enableLoopback; /*!< Enable loopback for test purpose */ + bool enableMaster; /*!< Enable SPI at initialization time */ + spi_clock_polarity_t polarity; /*!< Clock polarity */ + spi_clock_phase_t phase; /*!< Clock phase */ + spi_shift_direction_t direction; /*!< MSB or LSB */ + uint32_t baudRate_Bps; /*!< Baud Rate for SPI in Hz */ + spi_data_width_t dataWidth; /*!< Width of the data */ + spi_ssel_t sselNum; /*!< Slave select number */ + spi_spol_t sselPol; /*!< Configure active CS polarity */ + uint8_t txWatermark; /*!< txFIFO watermark */ + uint8_t rxWatermark; /*!< rxFIFO watermark */ + spi_delay_config_t delayConfig; /*!< Delay configuration. */ +} spi_master_config_t; + +/*! @brief SPI slave user configure structure.*/ +typedef struct _spi_slave_config +{ + bool enableSlave; /*!< Enable SPI at initialization time */ + spi_clock_polarity_t polarity; /*!< Clock polarity */ + spi_clock_phase_t phase; /*!< Clock phase */ + spi_shift_direction_t direction; /*!< MSB or LSB */ + spi_data_width_t dataWidth; /*!< Width of the data */ + spi_spol_t sselPol; /*!< Configure active CS polarity */ + uint8_t txWatermark; /*!< txFIFO watermark */ + uint8_t rxWatermark; /*!< rxFIFO watermark */ +} spi_slave_config_t; + +/*! @brief SPI transfer status.*/ +enum +{ + kStatus_SPI_Busy = MAKE_STATUS(kStatusGroup_LPC_SPI, 0), /*!< SPI bus is busy */ + kStatus_SPI_Idle = MAKE_STATUS(kStatusGroup_LPC_SPI, 1), /*!< SPI is idle */ + kStatus_SPI_Error = MAKE_STATUS(kStatusGroup_LPC_SPI, 2), /*!< SPI error */ + kStatus_SPI_BaudrateNotSupport = + MAKE_STATUS(kStatusGroup_LPC_SPI, 3), /*!< Baudrate is not support in current clock source */ + kStatus_SPI_Timeout = MAKE_STATUS(kStatusGroup_LPC_SPI, 4) /*!< SPI timeout polling status flags. */ +}; + +/*! @brief SPI interrupt sources.*/ +enum _spi_interrupt_enable +{ + kSPI_RxLvlIrq = SPI_FIFOINTENSET_RXLVL_MASK, /*!< Rx level interrupt */ + kSPI_TxLvlIrq = SPI_FIFOINTENSET_TXLVL_MASK, /*!< Tx level interrupt */ +}; + +/*! @brief SPI status flags.*/ +enum _spi_statusflags +{ + kSPI_TxEmptyFlag = SPI_FIFOSTAT_TXEMPTY_MASK, /*!< txFifo is empty */ + kSPI_TxNotFullFlag = SPI_FIFOSTAT_TXNOTFULL_MASK, /*!< txFifo is not full */ + kSPI_RxNotEmptyFlag = SPI_FIFOSTAT_RXNOTEMPTY_MASK, /*!< rxFIFO is not empty */ + kSPI_RxFullFlag = SPI_FIFOSTAT_RXFULL_MASK, /*!< rxFIFO is full */ +}; + +/*! @brief SPI transfer structure */ +typedef struct _spi_transfer +{ + uint8_t *txData; /*!< Send buffer */ + uint8_t *rxData; /*!< Receive buffer */ + uint32_t configFlags; /*!< Additional option to control transfer, @ref spi_xfer_option_t. */ + size_t dataSize; /*!< Transfer bytes */ +} spi_transfer_t; + +/*! @brief SPI half-duplex(master only) transfer structure */ +typedef struct _spi_half_duplex_transfer +{ + uint8_t *txData; /*!< Send buffer */ + uint8_t *rxData; /*!< Receive buffer */ + size_t txDataSize; /*!< Transfer bytes for transmit */ + size_t rxDataSize; /*!< Transfer bytes */ + uint32_t configFlags; /*!< Transfer configuration flags, @ref spi_xfer_option_t. */ + bool isPcsAssertInTransfer; /*!< If PCS pin keep assert between transmit and receive. true for assert and false for + deassert. */ + bool isTransmitFirst; /*!< True for transmit first and false for receive first. */ +} spi_half_duplex_transfer_t; + +/*! @brief Internal configuration structure used in 'spi' and 'spi_dma' driver */ +typedef struct _spi_config +{ + spi_data_width_t dataWidth; + spi_ssel_t sselNum; +} spi_config_t; + +/*! @brief Master handle type */ +typedef struct _spi_master_handle spi_master_handle_t; + +/*! @brief Slave handle type */ +typedef spi_master_handle_t spi_slave_handle_t; + +/*! @brief SPI master callback for finished transmit */ +typedef void (*spi_master_callback_t)(SPI_Type *base, spi_master_handle_t *handle, status_t status, void *userData); + +/*! @brief SPI slave callback for finished transmit */ +typedef void (*spi_slave_callback_t)(SPI_Type *base, spi_slave_handle_t *handle, status_t status, void *userData); + +/*! @brief SPI transfer handle structure */ +struct _spi_master_handle +{ + uint8_t *volatile txData; /*!< Transfer buffer */ + uint8_t *volatile rxData; /*!< Receive buffer */ + volatile size_t txRemainingBytes; /*!< Number of data to be transmitted [in bytes] */ + volatile size_t rxRemainingBytes; /*!< Number of data to be received [in bytes] */ + volatile int8_t toReceiveCount; /*!< The number of data expected to receive in data width. Since the received count + and sent count should be the same to complete the transfer, if the sent count is + x and the received count is y, toReceiveCount is x-y. */ + size_t totalByteCount; /*!< A number of transfer bytes */ + volatile uint32_t state; /*!< SPI internal state */ + spi_master_callback_t callback; /*!< SPI callback */ + void *userData; /*!< Callback parameter */ + uint8_t dataWidth; /*!< Width of the data [Valid values: 1 to 16] */ + uint8_t sselNum; /*!< Slave select number to be asserted when transferring data [Valid values: 0 to 3] */ + uint32_t configFlags; /*!< Additional option to control transfer */ + uint8_t txWatermark; /*!< txFIFO watermark */ + uint8_t rxWatermark; /*!< rxFIFO watermark */ +}; + +/*! @brief Typedef for master interrupt handler. */ +typedef void (*flexcomm_spi_master_irq_handler_t)(SPI_Type *base, spi_master_handle_t *handle); + +/*! @brief Typedef for slave interrupt handler. */ +typedef void (*flexcomm_spi_slave_irq_handler_t)(SPI_Type *base, spi_slave_handle_t *handle); +/*! @} */ + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! @brief Returns instance number for SPI peripheral base address. */ +uint32_t SPI_GetInstance(SPI_Type *base); + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Sets the SPI master configuration structure to default values. + * + * The purpose of this API is to get the configuration structure initialized for use in SPI_MasterInit(). + * User may use the initialized structure unchanged in SPI_MasterInit(), or modify + * some fields of the structure before calling SPI_MasterInit(). After calling this API, + * the master is ready to transfer. + * Example: + @code + spi_master_config_t config; + SPI_MasterGetDefaultConfig(&config); + @endcode + * + * @param config pointer to master config structure + */ +void SPI_MasterGetDefaultConfig(spi_master_config_t *config); + +/*! + * @brief Initializes the SPI with master configuration. + * + * The configuration structure can be filled by user from scratch, or be set with default + * values by SPI_MasterGetDefaultConfig(). After calling this API, the slave is ready to transfer. + * Example + @code + spi_master_config_t config = { + .baudRate_Bps = 400000, + ... + }; + SPI_MasterInit(SPI0, &config); + @endcode + * + * @param base SPI base pointer + * @param config pointer to master configuration structure + * @param srcClock_Hz Source clock frequency. + */ +status_t SPI_MasterInit(SPI_Type *base, const spi_master_config_t *config, uint32_t srcClock_Hz); + +/*! + * @brief Sets the SPI slave configuration structure to default values. + * + * The purpose of this API is to get the configuration structure initialized for use in SPI_SlaveInit(). + * Modify some fields of the structure before calling SPI_SlaveInit(). + * Example: + @code + spi_slave_config_t config; + SPI_SlaveGetDefaultConfig(&config); + @endcode + * + * @param config pointer to slave configuration structure + */ +void SPI_SlaveGetDefaultConfig(spi_slave_config_t *config); + +/*! + * @brief Initializes the SPI with slave configuration. + * + * The configuration structure can be filled by user from scratch or be set with + * default values by SPI_SlaveGetDefaultConfig(). + * After calling this API, the slave is ready to transfer. + * Example + @code + spi_slave_config_t config = { + .polarity = flexSPIClockPolarity_ActiveHigh; + .phase = flexSPIClockPhase_FirstEdge; + .direction = flexSPIMsbFirst; + ... + }; + SPI_SlaveInit(SPI0, &config); + @endcode + * + * @param base SPI base pointer + * @param config pointer to slave configuration structure + */ +status_t SPI_SlaveInit(SPI_Type *base, const spi_slave_config_t *config); + +/*! + * @brief De-initializes the SPI. + * + * Calling this API resets the SPI module, gates the SPI clock. + * The SPI module can't work unless calling the SPI_MasterInit/SPI_SlaveInit to initialize module. + * + * @param base SPI base pointer + */ +void SPI_Deinit(SPI_Type *base); + +/*! + * @brief Enable or disable the SPI Master or Slave + * @param base SPI base pointer + * @param enable or disable ( true = enable, false = disable) + */ +static inline void SPI_Enable(SPI_Type *base, bool enable) +{ + if (enable) + { + base->CFG |= SPI_CFG_ENABLE_MASK; + } + else + { + base->CFG &= ~SPI_CFG_ENABLE_MASK; + } +} + +/*! @} */ + +/*! + * @name Status + * @{ + */ + +/*! + * @brief Gets the status flag. + * + * @param base SPI base pointer + * @return SPI Status, use status flag to AND @ref _spi_statusflags could get the related status. + */ +static inline uint32_t SPI_GetStatusFlags(SPI_Type *base) +{ + assert(NULL != base); + return base->FIFOSTAT; +} + +/*! @} */ + +/*! + * @name Interrupts + * @{ + */ + +/*! + * @brief Enables the interrupt for the SPI. + * + * @param base SPI base pointer + * @param irqs SPI interrupt source. The parameter can be any combination of the following values: + * @arg kSPI_RxLvlIrq + * @arg kSPI_TxLvlIrq + */ +static inline void SPI_EnableInterrupts(SPI_Type *base, uint32_t irqs) +{ + assert(NULL != base); + base->FIFOINTENSET = irqs; +} + +/*! + * @brief Disables the interrupt for the SPI. + * + * @param base SPI base pointer + * @param irqs SPI interrupt source. The parameter can be any combination of the following values: + * @arg kSPI_RxLvlIrq + * @arg kSPI_TxLvlIrq + */ +static inline void SPI_DisableInterrupts(SPI_Type *base, uint32_t irqs) +{ + assert(NULL != base); + base->FIFOINTENCLR = irqs; +} + +/*! @} */ + +/*! + * @name DMA Control + * @{ + */ + +/*! + * @brief Enables the DMA request from SPI txFIFO. + * + * @param base SPI base pointer + * @param enable True means enable DMA, false means disable DMA + */ +void SPI_EnableTxDMA(SPI_Type *base, bool enable); + +/*! + * @brief Enables the DMA request from SPI rxFIFO. + * + * @param base SPI base pointer + * @param enable True means enable DMA, false means disable DMA + */ +void SPI_EnableRxDMA(SPI_Type *base, bool enable); + +/*! @} */ + +/*! + * @name Bus Operations + * @{ + */ +/*! + * @brief Returns the configurations. + * + * @param base SPI peripheral address. + * @return return configurations which contain datawidth and SSEL numbers. + * return data type is a pointer of spi_config_t. + */ +void *SPI_GetConfig(SPI_Type *base); + +/*! + * @brief Sets the baud rate for SPI transfer. This is only used in master. + * + * @param base SPI base pointer + * @param baudrate_Bps baud rate needed in Hz. + * @param srcClock_Hz SPI source clock frequency in Hz. + */ +status_t SPI_MasterSetBaud(SPI_Type *base, uint32_t baudrate_Bps, uint32_t srcClock_Hz); + +/*! + * @brief Writes a data into the SPI data register. + * + * @param base SPI base pointer + * @param data needs to be write. + * @param configFlags transfer configuration options @ref spi_xfer_option_t + */ +void SPI_WriteData(SPI_Type *base, uint16_t data, uint32_t configFlags); + +/*! + * @brief Gets a data from the SPI data register. + * + * @param base SPI base pointer + * @return Data in the register. + */ +static inline uint32_t SPI_ReadData(SPI_Type *base) +{ + assert(NULL != base); + return base->FIFORD; +} + +/*! + * @brief Set delay time for transfer. + * the delay uint is SPI clock time, maximum value is 0xF. + * @param base SPI base pointer + * @param config configuration for delay option @ref spi_delay_config_t. + */ +static inline void SPI_SetTransferDelay(SPI_Type *base, const spi_delay_config_t *config) +{ + assert(NULL != base); + assert(NULL != config); + base->DLY = (SPI_DLY_PRE_DELAY(config->preDelay) | SPI_DLY_POST_DELAY(config->postDelay) | + SPI_DLY_FRAME_DELAY(config->frameDelay) | SPI_DLY_TRANSFER_DELAY(config->transferDelay)); +} + +/*! + * @brief Set up the dummy data. + * + * @param base SPI peripheral address. + * @param dummyData Data to be transferred when tx buffer is NULL. + */ +void SPI_SetDummyData(SPI_Type *base, uint8_t dummyData); + +/*! @} */ + +/*! + * @name Transactional + * @{ + */ + +/*! + * @brief Initializes the SPI master handle. + * + * This function initializes the SPI master handle which can be used for other SPI master transactional APIs. Usually, + * for a specified SPI instance, call this API once to get the initialized handle. + * + * @param base SPI peripheral base address. + * @param handle SPI handle pointer. + * @param callback Callback function. + * @param userData User data. + */ +status_t SPI_MasterTransferCreateHandle(SPI_Type *base, + spi_master_handle_t *handle, + spi_master_callback_t callback, + void *userData); + +/*! + * @brief Transfers a block of data using a polling method. + * + * @param base SPI base pointer + * @param xfer pointer to spi_xfer_config_t structure + * @retval kStatus_Success Successfully start a transfer. + * @retval kStatus_InvalidArgument Input argument is invalid. + * @retval kStatus_SPI_Timeout The transfer timed out and was aborted. + */ +status_t SPI_MasterTransferBlocking(SPI_Type *base, spi_transfer_t *xfer); + +/*! + * @brief Performs a non-blocking SPI interrupt transfer. + * + * @param base SPI peripheral base address. + * @param handle pointer to spi_master_handle_t structure which stores the transfer state + * @param xfer pointer to spi_xfer_config_t structure + * @retval kStatus_Success Successfully start a transfer. + * @retval kStatus_InvalidArgument Input argument is invalid. + * @retval kStatus_SPI_Busy SPI is not idle, is running another transfer. + */ +status_t SPI_MasterTransferNonBlocking(SPI_Type *base, spi_master_handle_t *handle, spi_transfer_t *xfer); + +/*! + * @brief Transfers a block of data using a polling method. + * + * This function will do a half-duplex transfer for SPI master, This is a blocking function, + * which does not retuen until all transfer have been completed. And data transfer mechanism is half-duplex, + * users can set transmit first or receive first. + * + * @param base SPI base pointer + * @param xfer pointer to spi_half_duplex_transfer_t structure + * @return status of status_t. + */ +status_t SPI_MasterHalfDuplexTransferBlocking(SPI_Type *base, spi_half_duplex_transfer_t *xfer); + +/*! + * @brief Performs a non-blocking SPI interrupt transfer. + * + * This function using polling way to do the first half transimission and using interrupts to + * do the second half transimission, the transfer mechanism is half-duplex. + * When do the second half transimission, code will return right away. When all data is transferred, + * the callback function is called. + * + * @param base SPI peripheral base address. + * @param handle pointer to spi_master_handle_t structure which stores the transfer state + * @param xfer pointer to spi_half_duplex_transfer_t structure + * @return status of status_t. + */ +status_t SPI_MasterHalfDuplexTransferNonBlocking(SPI_Type *base, + spi_master_handle_t *handle, + spi_half_duplex_transfer_t *xfer); + +/*! + * @brief Gets the master transfer count. + * + * This function gets the master transfer count. + * + * @param base SPI peripheral base address. + * @param handle Pointer to the spi_master_handle_t structure which stores the transfer state. + * @param count The number of bytes transferred by using the non-blocking transaction. + * @return status of status_t. + */ +status_t SPI_MasterTransferGetCount(SPI_Type *base, spi_master_handle_t *handle, size_t *count); + +/*! + * @brief SPI master aborts a transfer using an interrupt. + * + * This function aborts a transfer using an interrupt. + * + * @param base SPI peripheral base address. + * @param handle Pointer to the spi_master_handle_t structure which stores the transfer state. + */ +void SPI_MasterTransferAbort(SPI_Type *base, spi_master_handle_t *handle); + +/*! + * @brief Interrupts the handler for the SPI. + * + * @param base SPI peripheral base address. + * @param handle pointer to spi_master_handle_t structure which stores the transfer state. + */ +void SPI_MasterTransferHandleIRQ(SPI_Type *base, spi_master_handle_t *handle); + +/*! + * @brief Initializes the SPI slave handle. + * + * This function initializes the SPI slave handle which can be used for other SPI slave transactional APIs. Usually, + * for a specified SPI instance, call this API once to get the initialized handle. + * + * @param base SPI peripheral base address. + * @param handle SPI handle pointer. + * @param callback Callback function. + * @param userData User data. + */ +static inline status_t SPI_SlaveTransferCreateHandle(SPI_Type *base, + spi_slave_handle_t *handle, + spi_slave_callback_t callback, + void *userData) +{ + return SPI_MasterTransferCreateHandle(base, handle, callback, userData); +} + +/*! + * @brief Performs a non-blocking SPI slave interrupt transfer. + * + * @note The API returns immediately after the transfer initialization is finished. + * + * @param base SPI peripheral base address. + * @param handle pointer to spi_master_handle_t structure which stores the transfer state + * @param xfer pointer to spi_xfer_config_t structure + * @retval kStatus_Success Successfully start a transfer. + * @retval kStatus_InvalidArgument Input argument is invalid. + * @retval kStatus_SPI_Busy SPI is not idle, is running another transfer. + */ +static inline status_t SPI_SlaveTransferNonBlocking(SPI_Type *base, spi_slave_handle_t *handle, spi_transfer_t *xfer) +{ + return SPI_MasterTransferNonBlocking(base, handle, xfer); +} + +/*! + * @brief Gets the slave transfer count. + * + * This function gets the slave transfer count. + * + * @param base SPI peripheral base address. + * @param handle Pointer to the spi_master_handle_t structure which stores the transfer state. + * @param count The number of bytes transferred by using the non-blocking transaction. + * @return status of status_t. + */ +static inline status_t SPI_SlaveTransferGetCount(SPI_Type *base, spi_slave_handle_t *handle, size_t *count) +{ + return SPI_MasterTransferGetCount(base, (spi_master_handle_t *)handle, count); +} + +/*! + * @brief SPI slave aborts a transfer using an interrupt. + * + * This function aborts a transfer using an interrupt. + * + * @param base SPI peripheral base address. + * @param handle Pointer to the spi_slave_handle_t structure which stores the transfer state. + */ +static inline void SPI_SlaveTransferAbort(SPI_Type *base, spi_slave_handle_t *handle) +{ + SPI_MasterTransferAbort(base, (spi_master_handle_t *)handle); +} + +/*! + * @brief Interrupts a handler for the SPI slave. + * + * @param base SPI peripheral base address. + * @param handle pointer to spi_slave_handle_t structure which stores the transfer state + */ +static inline void SPI_SlaveTransferHandleIRQ(SPI_Type *base, spi_slave_handle_t *handle) +{ + SPI_MasterTransferHandleIRQ(base, handle); +} + +/*! @} */ + +#if defined(__cplusplus) +} +#endif + +/*! @} */ + +#endif /* _FSL_SPI_H_*/ diff --git a/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_spi_dma.c b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_spi_dma.c new file mode 100644 index 0000000000..ed0aaa6a9f --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_spi_dma.c @@ -0,0 +1,568 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_spi_dma.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.flexcomm_spi_dma" +#endif + +/*configFlags & (uint32_t)kSPI_FrameDelay) != 0U) ? (uint32_t)kSPI_FrameDelay : 0U; + *fifowr |= ((xfer->configFlags & (uint32_t)kSPI_FrameAssert) != 0U) ? (uint32_t)kSPI_FrameAssert : 0U; +} + +static void SpiConfigToFifoWR(spi_config_t *config, uint32_t *fifowr) +{ + *fifowr |= ((uint32_t)SPI_DEASSERT_ALL & (~(uint32_t)SPI_DEASSERTNUM_SSEL((uint32_t)config->sselNum))); + /* set width of data - range asserted at entry */ + *fifowr |= SPI_FIFOWR_LEN(config->dataWidth); +} + +static void PrepareTxLastWord(spi_transfer_t *xfer, uint32_t *txLastWord, spi_config_t *config) +{ + if (config->dataWidth > kSPI_Data8Bits) + { + *txLastWord = (((uint32_t)xfer->txData[xfer->dataSize - 1U] << 8U) | (xfer->txData[xfer->dataSize - 2U])); + } + else + { + *txLastWord = xfer->txData[xfer->dataSize - 1U]; + } + XferToFifoWR(xfer, txLastWord); + SpiConfigToFifoWR(config, txLastWord); +} + +static void SPI_SetupDummy(SPI_Type *base, spi_dma_txdummy_t *dummy, spi_transfer_t *xfer, spi_config_t *spi_config_p) +{ + uint32_t instance = SPI_GetInstance(base); + uint32_t dummydata = (uint32_t)s_dummyData[instance]; + dummydata |= (uint32_t)s_dummyData[instance] << 8U; + + dummy->word = dummydata; + dummy->lastWord = dummydata; + + XferToFifoWR(xfer, &dummy->word); + XferToFifoWR(xfer, &dummy->lastWord); + SpiConfigToFifoWR(spi_config_p, &dummy->word); + SpiConfigToFifoWR(spi_config_p, &dummy->lastWord); + /* Clear the end of transfer bit for continue word transfer. */ + dummy->word &= (~(uint32_t)kSPI_FrameAssert); +} + +/*! + * brief Initialize the SPI master DMA handle. + * + * This function initializes the SPI master DMA handle which can be used for other SPI master transactional APIs. + * Usually, for a specified SPI instance, user need only call this API once to get the initialized handle. + * + * param base SPI peripheral base address. + * param handle SPI handle pointer. + * param callback User callback function called at the end of a transfer. + * param userData User data for callback. + * param txHandle DMA handle pointer for SPI Tx, the handle shall be static allocated by users. + * param rxHandle DMA handle pointer for SPI Rx, the handle shall be static allocated by users. + */ +status_t SPI_MasterTransferCreateHandleDMA(SPI_Type *base, + spi_dma_handle_t *handle, + spi_dma_callback_t callback, + void *userData, + dma_handle_t *txHandle, + dma_handle_t *rxHandle) +{ + uint32_t instance; + + /* check 'base' */ + assert(!(NULL == base)); + if (NULL == base) + { + return kStatus_InvalidArgument; + } + /* check 'handle' */ + assert(!(NULL == handle)); + if (NULL == handle) + { + return kStatus_InvalidArgument; + } + + instance = SPI_GetInstance(base); + + (void)memset(handle, 0, sizeof(*handle)); + /* Set spi base to handle */ + handle->txHandle = txHandle; + handle->rxHandle = rxHandle; + handle->callback = callback; + handle->userData = userData; + + /* Set SPI state to idle */ + handle->state = (uint8_t)kSPI_Idle; + + /* Set handle to global state */ + s_dmaPrivateHandle[instance].base = base; + s_dmaPrivateHandle[instance].handle = handle; + + /* Install callback for Tx dma channel */ + DMA_SetCallback(handle->txHandle, SPI_TxDMACallback, &s_dmaPrivateHandle[instance]); + DMA_SetCallback(handle->rxHandle, SPI_RxDMACallback, &s_dmaPrivateHandle[instance]); + + return kStatus_Success; +} + +/*! + * brief Perform a non-blocking SPI transfer using DMA. + * + * note This interface returned immediately after transfer initiates, users should call + * SPI_GetTransferStatus to poll the transfer status to check whether SPI transfer finished. + * + * param base SPI peripheral base address. + * param handle SPI DMA handle pointer. + * param xfer Pointer to dma transfer structure. + * retval kStatus_Success Successfully start a transfer. + * retval kStatus_InvalidArgument Input argument is invalid. + * retval kStatus_SPI_Busy SPI is not idle, is running another transfer. + */ +status_t SPI_MasterTransferDMA(SPI_Type *base, spi_dma_handle_t *handle, spi_transfer_t *xfer) +{ + assert(!((NULL == handle) || (NULL == xfer))); + + uint32_t instance; + status_t result = kStatus_Success; + spi_config_t *spi_config_p; + uint32_t address; + + if ((NULL == handle) || (NULL == xfer)) + { + return kStatus_InvalidArgument; + } + + /* Byte size is zero. */ + if (xfer->dataSize == 0U) + { + return kStatus_InvalidArgument; + } + /* cannot get instance from base address */ + instance = SPI_GetInstance(base); + + /* Check if the device is busy */ + if (handle->state == (uint8_t)kSPI_Busy) + { + return kStatus_SPI_Busy; + } + else + { + /* Clear FIFOs before transfer. */ + base->FIFOCFG |= SPI_FIFOCFG_EMPTYTX_MASK | SPI_FIFOCFG_EMPTYRX_MASK; + base->FIFOSTAT |= SPI_FIFOSTAT_TXERR_MASK | SPI_FIFOSTAT_RXERR_MASK; + + dma_transfer_config_t xferConfig = {0}; + spi_config_p = (spi_config_t *)SPI_GetConfig(base); + + handle->state = (uint8_t)kSPI_Busy; + handle->transferSize = xfer->dataSize; + + /* receive */ + SPI_EnableRxDMA(base, true); + address = (uint32_t)&base->FIFORD; + if (xfer->rxData != NULL) + { + DMA_PrepareTransfer(&xferConfig, (uint32_t *)address, xfer->rxData, + ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (sizeof(uint16_t)) : (sizeof(uint8_t))), + xfer->dataSize, kDMA_PeripheralToMemory, NULL); + } + else + { + DMA_PrepareTransfer(&xferConfig, (uint32_t *)address, &s_rxDummy, + ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (sizeof(uint16_t)) : (sizeof(uint8_t))), + xfer->dataSize, kDMA_StaticToStatic, NULL); + } + (void)DMA_SubmitTransfer(handle->rxHandle, &xferConfig); + handle->rxInProgress = true; + DMA_StartTransfer(handle->rxHandle); + + /* transmit */ + SPI_EnableTxDMA(base, true); + address = (uint32_t)&base->FIFOWR; + if (xfer->txData != NULL) + { + if ((xfer->configFlags & (uint32_t)kSPI_FrameAssert) != 0U) + { + PrepareTxLastWord(xfer, &s_txLastWord[instance], spi_config_p); + } + /* If end of tranfer function is enabled and data transfer frame is bigger then 1, use dma + * descriptor to send the last data. + */ + if (((xfer->configFlags & (uint32_t)kSPI_FrameAssert) != 0U) && + ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (xfer->dataSize > 2U) : (xfer->dataSize > 1U))) + { + dma_xfercfg_t tmp_xfercfg; + tmp_xfercfg.valid = true; + tmp_xfercfg.swtrig = true; + tmp_xfercfg.intA = true; + tmp_xfercfg.byteWidth = 4U; + tmp_xfercfg.srcInc = 0; + tmp_xfercfg.dstInc = 0; + tmp_xfercfg.transferCount = 1; + tmp_xfercfg.reload = false; + tmp_xfercfg.clrtrig = false; + tmp_xfercfg.intB = false; + /* Create chained descriptor to transmit last word */ + DMA_CreateDescriptor(&s_spi_descriptor_table[instance], &tmp_xfercfg, &s_txLastWord[instance], + (uint32_t *)address, NULL); + + DMA_PrepareTransfer( + &xferConfig, xfer->txData, (uint32_t *)address, + ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (sizeof(uint16_t)) : (sizeof(uint8_t))), + ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (xfer->dataSize - 2U) : (xfer->dataSize - 1U)), + kDMA_MemoryToPeripheral, &s_spi_descriptor_table[instance]); + /* Disable interrupts for first descriptor to avoid calling callback twice. */ + xferConfig.xfercfg.intA = false; + xferConfig.xfercfg.intB = false; + result = DMA_SubmitTransfer(handle->txHandle, &xferConfig); + if (result != kStatus_Success) + { + return result; + } + } + else + { + DMA_PrepareTransfer( + &xferConfig, xfer->txData, (uint32_t *)address, + ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (sizeof(uint16_t)) : (sizeof(uint8_t))), + xfer->dataSize, kDMA_MemoryToPeripheral, NULL); + (void)DMA_SubmitTransfer(handle->txHandle, &xferConfig); + } + } + else + { + /* Setup tx dummy data. */ + SPI_SetupDummy(base, &s_txDummy[instance], xfer, spi_config_p); + if (((xfer->configFlags & (uint32_t)kSPI_FrameAssert) != 0U) && + ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (xfer->dataSize > 2U) : (xfer->dataSize > 1U))) + { + dma_xfercfg_t tmp_xfercfg; + tmp_xfercfg.valid = true; + tmp_xfercfg.swtrig = true; + tmp_xfercfg.intA = true; + tmp_xfercfg.byteWidth = (uint8_t)sizeof(uint32_t); + tmp_xfercfg.srcInc = 0; + tmp_xfercfg.dstInc = 0; + tmp_xfercfg.transferCount = 1; + tmp_xfercfg.reload = false; + tmp_xfercfg.clrtrig = false; + tmp_xfercfg.intB = false; + /* Create chained descriptor to transmit last word */ + DMA_CreateDescriptor(&s_spi_descriptor_table[instance], &tmp_xfercfg, &s_txDummy[instance].lastWord, + (uint32_t *)address, NULL); + /* Use common API to setup first descriptor */ + DMA_PrepareTransfer( + &xferConfig, &s_txDummy[instance].word, (uint32_t *)address, + ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (sizeof(uint16_t)) : (sizeof(uint8_t))), + ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (xfer->dataSize - 2U) : (xfer->dataSize - 1U)), + kDMA_StaticToStatic, &s_spi_descriptor_table[instance]); + /* Disable interrupts for first descriptor to avoid calling callback twice */ + xferConfig.xfercfg.intA = false; + xferConfig.xfercfg.intB = false; + result = DMA_SubmitTransfer(handle->txHandle, &xferConfig); + if (result != kStatus_Success) + { + return result; + } + } + else + { + DMA_PrepareTransfer( + &xferConfig, &s_txDummy[instance].word, (uint32_t *)address, + ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (sizeof(uint16_t)) : (sizeof(uint8_t))), + xfer->dataSize, kDMA_StaticToStatic, NULL); + result = DMA_SubmitTransfer(handle->txHandle, &xferConfig); + if (result != kStatus_Success) + { + return result; + } + } + } + + handle->txInProgress = true; + uint32_t tmpData = 0U; + uint32_t writeAddress = (uint32_t) & (base->FIFOWR) + 2UL; + XferToFifoWR(xfer, &tmpData); + SpiConfigToFifoWR(spi_config_p, &tmpData); + + /* Setup the control info. + * Halfword writes to just the control bits (offset 0xE22) doesn't push anything into the FIFO. + * And the data access type of control bits must be uint16_t, byte writes or halfword writes to FIFOWR + * will push the data and the current control bits into the FIFO. + */ + if (((xfer->configFlags & (uint32_t)kSPI_FrameAssert) != 0U) && + ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (xfer->dataSize == 2U) : (xfer->dataSize == 1U))) + { + *(uint16_t *)writeAddress = (uint16_t)(tmpData >> 16U); + } + else + { + /* Clear the SPI_FIFOWR_EOT_MASK bit when data is not the last. */ + tmpData &= (~(uint32_t)kSPI_FrameAssert); + *(uint16_t *)writeAddress = (uint16_t)(tmpData >> 16U); + } + + DMA_StartTransfer(handle->txHandle); + } + + return result; +} + +/*! + * brief Transfers a block of data using a DMA method. + * + * This function using polling way to do the first half transimission and using DMA way to + * do the srcond half transimission, the transfer mechanism is half-duplex. + * When do the second half transimission, code will return right away. When all data is transferred, + * the callback function is called. + * + * param base SPI base pointer + * param handle A pointer to the spi_master_dma_handle_t structure which stores the transfer state. + * param transfer A pointer to the spi_half_duplex_transfer_t structure. + * return status of status_t. + */ +status_t SPI_MasterHalfDuplexTransferDMA(SPI_Type *base, spi_dma_handle_t *handle, spi_half_duplex_transfer_t *xfer) +{ + assert((xfer != NULL) && (handle != NULL)); + spi_transfer_t tempXfer = {0}; + status_t status; + + if (xfer->isTransmitFirst) + { + tempXfer.txData = xfer->txData; + tempXfer.rxData = NULL; + tempXfer.dataSize = xfer->txDataSize; + } + else + { + tempXfer.txData = NULL; + tempXfer.rxData = xfer->rxData; + tempXfer.dataSize = xfer->rxDataSize; + } + /* If the pcs pin keep assert between transmit and receive. */ + if (xfer->isPcsAssertInTransfer) + { + tempXfer.configFlags = (xfer->configFlags) & (~(uint32_t)kSPI_FrameAssert); + } + else + { + tempXfer.configFlags = (xfer->configFlags) | (uint32_t)kSPI_FrameAssert; + } + + status = SPI_MasterTransferBlocking(base, &tempXfer); + if (status != kStatus_Success) + { + return status; + } + + if (xfer->isTransmitFirst) + { + tempXfer.txData = NULL; + tempXfer.rxData = xfer->rxData; + tempXfer.dataSize = xfer->rxDataSize; + } + else + { + tempXfer.txData = xfer->txData; + tempXfer.rxData = NULL; + tempXfer.dataSize = xfer->txDataSize; + } + tempXfer.configFlags = xfer->configFlags; + + status = SPI_MasterTransferDMA(base, handle, &tempXfer); + + return status; +} + +static void SPI_RxDMACallback(dma_handle_t *handle, void *userData, bool transferDone, uint32_t intmode) +{ + spi_dma_private_handle_t *privHandle = (spi_dma_private_handle_t *)userData; + spi_dma_handle_t *spiHandle = privHandle->handle; + SPI_Type *base = privHandle->base; + + /* change the state */ + spiHandle->rxInProgress = false; + + /* All finished, call the callback */ + if ((spiHandle->txInProgress == false) && (spiHandle->rxInProgress == false)) + { + spiHandle->state = (uint8_t)kSPI_Idle; + if (spiHandle->callback != NULL) + { + (spiHandle->callback)(base, spiHandle, kStatus_Success, spiHandle->userData); + } + } +} + +static void SPI_TxDMACallback(dma_handle_t *handle, void *userData, bool transferDone, uint32_t intmode) +{ + spi_dma_private_handle_t *privHandle = (spi_dma_private_handle_t *)userData; + spi_dma_handle_t *spiHandle = privHandle->handle; + SPI_Type *base = privHandle->base; + + /* change the state */ + spiHandle->txInProgress = false; + + /* All finished, call the callback */ + if ((spiHandle->txInProgress == false) && (spiHandle->rxInProgress == false)) + { + spiHandle->state = (uint8_t)kSPI_Idle; + if (spiHandle->callback != NULL) + { + (spiHandle->callback)(base, spiHandle, kStatus_Success, spiHandle->userData); + } + } +} + +/*! + * brief Abort a SPI transfer using DMA. + * + * param base SPI peripheral base address. + * param handle SPI DMA handle pointer. + */ +void SPI_MasterTransferAbortDMA(SPI_Type *base, spi_dma_handle_t *handle) +{ + assert(NULL != handle); + + /* Stop tx transfer first */ + DMA_AbortTransfer(handle->txHandle); + /* Then rx transfer */ + DMA_AbortTransfer(handle->rxHandle); + + /* Set the handle state */ + handle->txInProgress = false; + handle->rxInProgress = false; + handle->state = (uint8_t)kSPI_Idle; +} + +/*! + * brief Gets the master DMA transfer remaining bytes. + * + * This function gets the master DMA transfer remaining bytes. + * + * param base SPI peripheral base address. + * param handle A pointer to the spi_dma_handle_t structure which stores the transfer state. + * param count A number of bytes transferred by the non-blocking transaction. + * return status of status_t. + */ +status_t SPI_MasterTransferGetCountDMA(SPI_Type *base, spi_dma_handle_t *handle, size_t *count) +{ + assert(handle != NULL); + + if (NULL == count) + { + return kStatus_InvalidArgument; + } + + /* Catch when there is not an active transfer. */ + if (handle->state != (uint8_t)kSPI_Busy) + { + *count = 0; + return kStatus_NoTransferInProgress; + } + + size_t bytes; + + bytes = DMA_GetRemainingBytes(handle->rxHandle->base, handle->rxHandle->channel); + + *count = handle->transferSize - bytes; + + return kStatus_Success; +} diff --git a/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_spi_dma.h b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_spi_dma.h new file mode 100644 index 0000000000..614c37d791 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_spi_dma.h @@ -0,0 +1,208 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_SPI_DMA_H_ +#define _FSL_SPI_DMA_H_ + +#include "fsl_dma.h" +#include "fsl_spi.h" + +/*! + * @addtogroup spi_dma_driver + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief SPI DMA driver version 2.1.1. */ +#define FSL_SPI_DMA_DRIVER_VERSION (MAKE_VERSION(2, 1, 2)) +/*@}*/ + +typedef struct _spi_dma_handle spi_dma_handle_t; + +/*! @brief SPI DMA callback called at the end of transfer. */ +typedef void (*spi_dma_callback_t)(SPI_Type *base, spi_dma_handle_t *handle, status_t status, void *userData); + +/*! @brief SPI DMA transfer handle, users should not touch the content of the handle.*/ +struct _spi_dma_handle +{ + volatile bool txInProgress; /*!< Send transfer finished */ + volatile bool rxInProgress; /*!< Receive transfer finished */ + dma_handle_t *txHandle; /*!< DMA handler for SPI send */ + dma_handle_t *rxHandle; /*!< DMA handler for SPI receive */ + uint8_t bytesPerFrame; /*!< Bytes in a frame for SPI transfer */ + spi_dma_callback_t callback; /*!< Callback for SPI DMA transfer */ + void *userData; /*!< User Data for SPI DMA callback */ + uint32_t state; /*!< Internal state of SPI DMA transfer */ + size_t transferSize; /*!< Bytes need to be transfer */ +}; + +/******************************************************************************* + * APIs + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name DMA Transactional + * @{ + */ + +/*! + * @brief Initialize the SPI master DMA handle. + * + * This function initializes the SPI master DMA handle which can be used for other SPI master transactional APIs. + * Usually, for a specified SPI instance, user need only call this API once to get the initialized handle. + * + * @param base SPI peripheral base address. + * @param handle SPI handle pointer. + * @param callback User callback function called at the end of a transfer. + * @param userData User data for callback. + * @param txHandle DMA handle pointer for SPI Tx, the handle shall be static allocated by users. + * @param rxHandle DMA handle pointer for SPI Rx, the handle shall be static allocated by users. + */ +status_t SPI_MasterTransferCreateHandleDMA(SPI_Type *base, + spi_dma_handle_t *handle, + spi_dma_callback_t callback, + void *userData, + dma_handle_t *txHandle, + dma_handle_t *rxHandle); + +/*! + * @brief Perform a non-blocking SPI transfer using DMA. + * + * @note This interface returned immediately after transfer initiates, users should call + * SPI_GetTransferStatus to poll the transfer status to check whether SPI transfer finished. + * + * @param base SPI peripheral base address. + * @param handle SPI DMA handle pointer. + * @param xfer Pointer to dma transfer structure. + * @retval kStatus_Success Successfully start a transfer. + * @retval kStatus_InvalidArgument Input argument is invalid. + * @retval kStatus_SPI_Busy SPI is not idle, is running another transfer. + */ +status_t SPI_MasterTransferDMA(SPI_Type *base, spi_dma_handle_t *handle, spi_transfer_t *xfer); + +/*! + * @brief Transfers a block of data using a DMA method. + * + * This function using polling way to do the first half transimission and using DMA way to + * do the srcond half transimission, the transfer mechanism is half-duplex. + * When do the second half transimission, code will return right away. When all data is transferred, + * the callback function is called. + * + * @param base SPI base pointer + * @param handle A pointer to the spi_master_dma_handle_t structure which stores the transfer state. + * @param xfer A pointer to the spi_half_duplex_transfer_t structure. + * @return status of status_t. + */ +status_t SPI_MasterHalfDuplexTransferDMA(SPI_Type *base, spi_dma_handle_t *handle, spi_half_duplex_transfer_t *xfer); + +/*! + * @brief Initialize the SPI slave DMA handle. + * + * This function initializes the SPI slave DMA handle which can be used for other SPI master transactional APIs. + * Usually, for a specified SPI instance, user need only call this API once to get the initialized handle. + * + * @param base SPI peripheral base address. + * @param handle SPI handle pointer. + * @param callback User callback function called at the end of a transfer. + * @param userData User data for callback. + * @param txHandle DMA handle pointer for SPI Tx, the handle shall be static allocated by users. + * @param rxHandle DMA handle pointer for SPI Rx, the handle shall be static allocated by users. + */ +static inline status_t SPI_SlaveTransferCreateHandleDMA(SPI_Type *base, + spi_dma_handle_t *handle, + spi_dma_callback_t callback, + void *userData, + dma_handle_t *txHandle, + dma_handle_t *rxHandle) +{ + return SPI_MasterTransferCreateHandleDMA(base, handle, callback, userData, txHandle, rxHandle); +} + +/*! + * @brief Perform a non-blocking SPI transfer using DMA. + * + * @note This interface returned immediately after transfer initiates, users should call + * SPI_GetTransferStatus to poll the transfer status to check whether SPI transfer finished. + * + * @param base SPI peripheral base address. + * @param handle SPI DMA handle pointer. + * @param xfer Pointer to dma transfer structure. + * @retval kStatus_Success Successfully start a transfer. + * @retval kStatus_InvalidArgument Input argument is invalid. + * @retval kStatus_SPI_Busy SPI is not idle, is running another transfer. + */ +static inline status_t SPI_SlaveTransferDMA(SPI_Type *base, spi_dma_handle_t *handle, spi_transfer_t *xfer) +{ + return SPI_MasterTransferDMA(base, handle, xfer); +} + +/*! + * @brief Abort a SPI transfer using DMA. + * + * @param base SPI peripheral base address. + * @param handle SPI DMA handle pointer. + */ +void SPI_MasterTransferAbortDMA(SPI_Type *base, spi_dma_handle_t *handle); + +/*! + * @brief Gets the master DMA transfer remaining bytes. + * + * This function gets the master DMA transfer remaining bytes. + * + * @param base SPI peripheral base address. + * @param handle A pointer to the spi_dma_handle_t structure which stores the transfer state. + * @param count A number of bytes transferred by the non-blocking transaction. + * @return status of status_t. + */ +status_t SPI_MasterTransferGetCountDMA(SPI_Type *base, spi_dma_handle_t *handle, size_t *count); + +/*! + * @brief Abort a SPI transfer using DMA. + * + * @param base SPI peripheral base address. + * @param handle SPI DMA handle pointer. + */ +static inline void SPI_SlaveTransferAbortDMA(SPI_Type *base, spi_dma_handle_t *handle) +{ + SPI_MasterTransferAbortDMA(base, handle); +} + +/*! + * @brief Gets the slave DMA transfer remaining bytes. + * + * This function gets the slave DMA transfer remaining bytes. + * + * @param base SPI peripheral base address. + * @param handle A pointer to the spi_dma_handle_t structure which stores the transfer state. + * @param count A number of bytes transferred by the non-blocking transaction. + * @return status of status_t. + */ +static inline status_t SPI_SlaveTransferGetCountDMA(SPI_Type *base, spi_dma_handle_t *handle, size_t *count) +{ + return SPI_MasterTransferGetCountDMA(base, handle, count); +} + +/*! @} */ + +#if defined(__cplusplus) +} +#endif + +/*! @} */ + +#endif /* _FSL_SPI_DMA_H_*/ diff --git a/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_sysctl.c b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_sysctl.c new file mode 100644 index 0000000000..1d0dd9ccf6 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_sysctl.c @@ -0,0 +1,203 @@ +/* + * Copyright 2019 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_sysctl.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.sysctl" +#endif + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Get the instance. + * + * @param base SYSCTL peripheral base address. + * @return Instance number. + */ +static uint32_t SYSCTL_GetInstance(SYSCTL_Type *base); + +/*! + * @brief Enable SYSCTL write protect + * + * @param base SYSCTL peripheral base address. + * @param regAddr register address + * @param value value to write. + */ +static void SYSCTL_UpdateRegister(SYSCTL_Type *base, volatile uint32_t *regAddr, uint32_t value); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief SYSCTL base address array name */ +static SYSCTL_Type *const s_sysctlBase[] = SYSCTL_BASE_PTRS; +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief SYSCTL clock array name */ +static const clock_ip_name_t s_sysctlClock[] = SYSCTL_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/******************************************************************************* + * Code + ******************************************************************************/ +static void SYSCTL_UpdateRegister(SYSCTL_Type *base, volatile uint32_t *regAddr, uint32_t value) +{ + base->UPDATELCKOUT &= ~SYSCTL_UPDATELCKOUT_UPDATELCKOUT_MASK; + *regAddr = value; + base->UPDATELCKOUT |= SYSCTL_UPDATELCKOUT_UPDATELCKOUT_MASK; +} + +static uint32_t SYSCTL_GetInstance(SYSCTL_Type *base) +{ + uint8_t instance = 0; + + while ((instance < ARRAY_SIZE(s_sysctlBase)) && (s_sysctlBase[instance] != base)) + { + instance++; + } + + assert(instance < ARRAY_SIZE(s_sysctlBase)); + + return instance; +} + +/*! + * @brief SYSCTL initial + * + * @param base Base address of the SYSCTL peripheral. + */ +void SYSCTL_Init(SYSCTL_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable SYSCTL clock. */ + CLOCK_EnableClock(s_sysctlClock[SYSCTL_GetInstance(base)]); +#endif +} + +/*! + * @brief SYSCTL deinit + * + * @param base Base address of the SYSCTL peripheral. + */ +void SYSCTL_Deinit(SYSCTL_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Disable SYSCTL clock. */ + CLOCK_DisableClock(s_sysctlClock[SYSCTL_GetInstance(base)]); +#endif +} + +/*! + * @brief SYSCTL share set configure for separate signal + * + * @param base Base address of the SYSCTL peripheral + * @param flexCommIndex index of flexcomm,reference _sysctl_share_src + * @param setIndex share set for sck, reference _sysctl_share_set_index + * + */ +void SYSCTL_SetShareSet(SYSCTL_Type *base, uint32_t flexCommIndex, sysctl_fcctrlsel_signal_t signal, uint32_t set) +{ + uint32_t tempReg = base->FCCTRLSEL[flexCommIndex]; + + tempReg &= ~((uint32_t)SYSCTL_FCCTRLSEL_SCKINSEL_MASK << (uint32_t)signal); + tempReg |= (set + 1U) << (uint32_t)signal; + + SYSCTL_UpdateRegister(base, &base->FCCTRLSEL[flexCommIndex], tempReg); +} + +/*! + * @brief SYSCTL share set configure for flexcomm + * + * @param base Base address of the SYSCTL peripheral. + * @param flexCommIndex index of flexcomm, reference _sysctl_share_src + * @param sckSet share set for sck,reference _sysctl_share_set_index + * @param wsSet share set for ws, reference _sysctl_share_set_index + * @param dataInSet share set for data in, reference _sysctl_share_set_index + * @param dataOutSet share set for data out, reference _sysctl_share_set_index + * + */ +void SYSCTL_SetFlexcommShareSet( + SYSCTL_Type *base, uint32_t flexCommIndex, uint32_t sckSet, uint32_t wsSet, uint32_t dataInSet, uint32_t dataOutSet) +{ + uint32_t tempReg = base->FCCTRLSEL[flexCommIndex]; + + tempReg &= ~(SYSCTL_FCCTRLSEL_SCKINSEL_MASK | SYSCTL_FCCTRLSEL_WSINSEL_MASK | SYSCTL_FCCTRLSEL_DATAINSEL_MASK | + SYSCTL_FCCTRLSEL_DATAOUTSEL_MASK); + tempReg |= SYSCTL_FCCTRLSEL_SCKINSEL(sckSet + 1U) | SYSCTL_FCCTRLSEL_WSINSEL(wsSet + 1U) | + SYSCTL_FCCTRLSEL_DATAINSEL(dataInSet + 1U) | SYSCTL_FCCTRLSEL_DATAOUTSEL(dataOutSet + 1U); + + SYSCTL_UpdateRegister(base, &base->FCCTRLSEL[flexCommIndex], tempReg); +} + +/*! + * @brief SYSCTL share set source configure + * + * @param base Base address of the SYSCTL peripheral + * @param setIndex index of share set, reference _sysctl_share_set_index + * @param sckShareSrc sck source for this share set,reference _sysctl_share_src + * @param wsShareSrc ws source for this share set,reference _sysctl_share_src + * @param dataInShareSrc data in source for this share set,reference _sysctl_share_src + * @param dataOutShareSrc data out source for this share set,reference _sysctl_dataout_mask + * + */ +void SYSCTL_SetShareSetSrc(SYSCTL_Type *base, + uint32_t setIndex, + uint32_t sckShareSrc, + uint32_t wsShareSrc, + uint32_t dataInShareSrc, + uint32_t dataOutShareSrc) +{ + uint32_t tempReg = base->SHAREDCTRLSET[setIndex]; + + /* WS,SCK,DATA IN */ + tempReg &= ~(SYSCTL_SHAREDCTRLSET_SHAREDSCKSEL_MASK | SYSCTL_SHAREDCTRLSET_SHAREDWSSEL_MASK | + SYSCTL_SHAREDCTRLSET_SHAREDDATASEL_MASK); + tempReg |= SYSCTL_SHAREDCTRLSET_SHAREDSCKSEL(sckShareSrc) | SYSCTL_SHAREDCTRLSET_SHAREDWSSEL(wsShareSrc) | + SYSCTL_SHAREDCTRLSET_SHAREDDATASEL(dataInShareSrc); + + /* data out */ + tempReg &= ~(SYSCTL_SHAREDCTRLSET_FC0DATAOUTEN_MASK | SYSCTL_SHAREDCTRLSET_FC1DATAOUTEN_MASK | + SYSCTL_SHAREDCTRLSET_FC2DATAOUTEN_MASK | SYSCTL_SHAREDCTRLSET_FC6DATAOUTEN_MASK | + SYSCTL_SHAREDCTRLSET_FC7DATAOUTEN_MASK); + tempReg |= dataOutShareSrc; + + SYSCTL_UpdateRegister(base, &base->SHAREDCTRLSET[setIndex], tempReg); +} + +/*! + * @brief SYSCTL sck source configure + * + * @param base Base address of the SYSCTL peripheral + * @param setIndex index of share set, reference _sysctl_share_set_index + * @param sckShareSrc sck source fro this share set,reference _sysctl_share_src + * + */ +void SYSCTL_SetShareSignalSrc(SYSCTL_Type *base, + uint32_t setIndex, + sysctl_sharedctrlset_signal_t signal, + uint32_t shareSrc) +{ + uint32_t tempReg = base->SHAREDCTRLSET[setIndex]; + + if (signal == kSYSCTL_SharedCtrlSignalDataOut) + { + tempReg |= 1UL << ((uint32_t)signal + shareSrc); + } + else + { + tempReg &= ~((uint32_t)SYSCTL_SHAREDCTRLSET_SHAREDSCKSEL_MASK << (uint32_t)signal); + tempReg |= shareSrc << (uint32_t)signal; + } + + SYSCTL_UpdateRegister(base, &base->SHAREDCTRLSET[setIndex], tempReg); +} diff --git a/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_sysctl.h b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_sysctl.h new file mode 100644 index 0000000000..0a1be88469 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_sysctl.h @@ -0,0 +1,186 @@ +/* + * Copyright 2019 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_SYSCTL_H_ +#define _FSL_SYSCTL_H_ + +#include "fsl_common.h" +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! + * @addtogroup sysctl + * @{ + */ + +/*! @file */ +/*! @file fsl_sysctl.h */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief Group sysctl driver version for SDK */ +#define FSL_SYSCTL_DRIVER_VERSION (MAKE_VERSION(2, 0, 5)) /*!< Version 2.0.5. */ +/*@}*/ + +/*! @brief SYSCTL share set*/ +enum _sysctl_share_set_index +{ + kSYSCTL_ShareSet0 = 0, /*!< share set 0 */ + kSYSCTL_ShareSet1 = 1, /*!< share set 1 */ +}; + +/*! @brief SYSCTL flexcomm signal */ +typedef enum _sysctl_fcctrlsel_signal +{ + kSYSCTL_FlexcommSignalSCK = SYSCTL_FCCTRLSEL_SCKINSEL_SHIFT, /*!< SCK signal */ + kSYSCTL_FlexcommSignalWS = SYSCTL_FCCTRLSEL_WSINSEL_SHIFT, /*!< WS signal */ + kSYSCTL_FlexcommSignalDataIn = SYSCTL_FCCTRLSEL_DATAINSEL_SHIFT, /*!< Data in signal */ + kSYSCTL_FlexcommSignalDataOut = SYSCTL_FCCTRLSEL_DATAOUTSEL_SHIFT, /*!< Data out signal */ +} sysctl_fcctrlsel_signal_t; + +/*! @brief SYSCTL flexcomm index*/ +enum _sysctl_share_src +{ + kSYSCTL_Flexcomm0 = 0, /*!< share set 0 */ + kSYSCTL_Flexcomm1 = 1, /*!< share set 1 */ + kSYSCTL_Flexcomm2 = 2, /*!< share set 2 */ + kSYSCTL_Flexcomm4 = 4, /*!< share set 4 */ + kSYSCTL_Flexcomm5 = 5, /*!< share set 5 */ + kSYSCTL_Flexcomm6 = 6, /*!< share set 6 */ + kSYSCTL_Flexcomm7 = 7, /*!< share set 7 */ +}; + +/*! @brief SYSCTL shared data out mask */ +enum _sysctl_dataout_mask +{ + kSYSCTL_Flexcomm0DataOut = SYSCTL_SHAREDCTRLSET_FC0DATAOUTEN_MASK, /*!< share set 0 */ + kSYSCTL_Flexcomm1DataOut = SYSCTL_SHAREDCTRLSET_FC1DATAOUTEN_MASK, /*!< share set 1 */ + kSYSCTL_Flexcomm2DataOut = SYSCTL_SHAREDCTRLSET_FC2DATAOUTEN_MASK, /*!< share set 2 */ + kSYSCTL_Flexcomm4DataOut = SYSCTL_SHAREDCTRLSET_FC4DATAOUTEN_MASK, /*!< share set 4 */ + kSYSCTL_Flexcomm5DataOut = SYSCTL_SHAREDCTRLSET_FC5DATAOUTEN_MASK, /*!< share set 5 */ + kSYSCTL_Flexcomm6DataOut = SYSCTL_SHAREDCTRLSET_FC6DATAOUTEN_MASK, /*!< share set 6 */ + kSYSCTL_Flexcomm7DataOut = SYSCTL_SHAREDCTRLSET_FC7DATAOUTEN_MASK, /*!< share set 7 */ +}; + +/*! @brief SYSCTL flexcomm signal */ +typedef enum _sysctl_sharedctrlset_signal +{ + kSYSCTL_SharedCtrlSignalSCK = SYSCTL_SHAREDCTRLSET_SHAREDSCKSEL_SHIFT, /*!< SCK signal */ + kSYSCTL_SharedCtrlSignalWS = SYSCTL_SHAREDCTRLSET_SHAREDWSSEL_SHIFT, /*!< WS signal */ + kSYSCTL_SharedCtrlSignalDataIn = SYSCTL_SHAREDCTRLSET_SHAREDDATASEL_SHIFT, /*!< Data in signal */ + kSYSCTL_SharedCtrlSignalDataOut = SYSCTL_SHAREDCTRLSET_FC0DATAOUTEN_SHIFT, /*!< Data out signal */ +} sysctl_sharedctrlset_signal_t; +/******************************************************************************* + * API + ******************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief SYSCTL initial + * + * @param base Base address of the SYSCTL peripheral. + */ +void SYSCTL_Init(SYSCTL_Type *base); + +/*! + * @brief SYSCTL deinit + * + * @param base Base address of the SYSCTL peripheral. + */ +void SYSCTL_Deinit(SYSCTL_Type *base); + +/* @} */ + +/*! + * @name SYSCTL share signal configure + * @{ + */ + +/*! + * @brief SYSCTL share set configure for flexcomm + * + * @param base Base address of the SYSCTL peripheral. + * @param flexCommIndex index of flexcomm, reference _sysctl_share_src + * @param sckSet share set for sck,reference _sysctl_share_set_index + * @param wsSet share set for ws, reference _sysctl_share_set_index + * @param dataInSet share set for data in, reference _sysctl_share_set_index + * @param dataOutSet share set for data out, reference _sysctl_dataout_mask + * + */ +void SYSCTL_SetFlexcommShareSet(SYSCTL_Type *base, + uint32_t flexCommIndex, + uint32_t sckSet, + uint32_t wsSet, + uint32_t dataInSet, + uint32_t dataOutSet); + +/*! + * @brief SYSCTL share set configure for separate signal + * + * @param base Base address of the SYSCTL peripheral + * @param flexCommIndex index of flexcomm,reference _sysctl_share_src + * @param signal FCCTRLSEL signal shift + * @param set share set for sck, reference _sysctl_share_set_index + * + */ +void SYSCTL_SetShareSet(SYSCTL_Type *base, uint32_t flexCommIndex, sysctl_fcctrlsel_signal_t signal, uint32_t set); + +/*! + * @brief SYSCTL share set source configure + * + * @param base Base address of the SYSCTL peripheral + * @param setIndex index of share set, reference _sysctl_share_set_index + * @param sckShareSrc sck source for this share set,reference _sysctl_share_src + * @param wsShareSrc ws source for this share set,reference _sysctl_share_src + * @param dataInShareSrc data in source for this share set,reference _sysctl_share_src + * @param dataOutShareSrc data out source for this share set,reference _sysctl_dataout_mask + * + */ +void SYSCTL_SetShareSetSrc(SYSCTL_Type *base, + uint32_t setIndex, + uint32_t sckShareSrc, + uint32_t wsShareSrc, + uint32_t dataInShareSrc, + uint32_t dataOutShareSrc); + +/*! + * @brief SYSCTL sck source configure + * + * @param base Base address of the SYSCTL peripheral + * @param setIndex index of share set, reference _sysctl_share_set_index + * @param signal FCCTRLSEL signal shift + * @param shareSrc sck source fro this share set,reference _sysctl_share_src + * + */ +void SYSCTL_SetShareSignalSrc(SYSCTL_Type *base, + uint32_t setIndex, + sysctl_sharedctrlset_signal_t signal, + uint32_t shareSrc); + +/* @} */ + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* _FSL_SYSCTL_H_ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_usart.c b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_usart.c new file mode 100644 index 0000000000..3286174f27 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_usart.c @@ -0,0 +1,1206 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_usart.h" +#include "fsl_device_registers.h" +#include "fsl_flexcomm.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.flexcomm_usart" +#endif + +/*! + * @brief Used for conversion from `flexcomm_usart_irq_handler_t` to `flexcomm_irq_handler_t` + */ +typedef union usart_to_flexcomm +{ + flexcomm_usart_irq_handler_t usart_master_handler; + flexcomm_irq_handler_t flexcomm_handler; +} usart_to_flexcomm_t; + +enum +{ + kUSART_TxIdle, /* TX idle. */ + kUSART_TxBusy, /* TX busy. */ + kUSART_RxIdle, /* RX idle. */ + kUSART_RxBusy /* RX busy. */ +}; + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/*! @brief IRQ name array */ +static const IRQn_Type s_usartIRQ[] = USART_IRQS; + +/*! @brief Array to map USART instance number to base address. */ +static const uint32_t s_usartBaseAddrs[FSL_FEATURE_SOC_USART_COUNT] = USART_BASE_ADDRS; + +/******************************************************************************* + * Code + ******************************************************************************/ + +/* Get the index corresponding to the USART */ +/*! brief Returns instance number for USART peripheral base address. */ +uint32_t USART_GetInstance(USART_Type *base) +{ + uint32_t i; + + for (i = 0; i < (uint32_t)FSL_FEATURE_SOC_USART_COUNT; i++) + { + if ((uint32_t)base == s_usartBaseAddrs[i]) + { + break; + } + } + + assert(i < (uint32_t)FSL_FEATURE_SOC_USART_COUNT); + return i; +} + +/*! + * brief Get the length of received data in RX ring buffer. + * + * param handle USART handle pointer. + * return Length of received data in RX ring buffer. + */ +size_t USART_TransferGetRxRingBufferLength(usart_handle_t *handle) +{ + size_t size; + + /* Check arguments */ + assert(NULL != handle); + uint16_t rxRingBufferHead = handle->rxRingBufferHead; + uint16_t rxRingBufferTail = handle->rxRingBufferTail; + + if (rxRingBufferTail > rxRingBufferHead) + { + size = (size_t)rxRingBufferHead + handle->rxRingBufferSize - (size_t)rxRingBufferTail; + } + else + { + size = (size_t)rxRingBufferHead - (size_t)rxRingBufferTail; + } + return size; +} + +static bool USART_TransferIsRxRingBufferFull(usart_handle_t *handle) +{ + bool full; + + /* Check arguments */ + assert(NULL != handle); + + if (USART_TransferGetRxRingBufferLength(handle) == (handle->rxRingBufferSize - 1U)) + { + full = true; + } + else + { + full = false; + } + return full; +} + +/*! + * brief Sets up the RX ring buffer. + * + * This function sets up the RX ring buffer to a specific USART handle. + * + * When the RX ring buffer is used, data received are stored into the ring buffer even when the + * user doesn't call the USART_TransferReceiveNonBlocking() API. If there is already data received + * in the ring buffer, the user can get the received data from the ring buffer directly. + * + * note When using the RX ring buffer, one byte is reserved for internal use. In other + * words, if p ringBufferSize is 32, then only 31 bytes are used for saving data. + * + * param base USART peripheral base address. + * param handle USART handle pointer. + * param ringBuffer Start address of the ring buffer for background receiving. Pass NULL to disable the ring buffer. + * param ringBufferSize size of the ring buffer. + */ +void USART_TransferStartRingBuffer(USART_Type *base, usart_handle_t *handle, uint8_t *ringBuffer, size_t ringBufferSize) +{ + /* Check arguments */ + assert(NULL != base); + assert(NULL != handle); + assert(NULL != ringBuffer); + + /* Setup the ringbuffer address */ + handle->rxRingBuffer = ringBuffer; + handle->rxRingBufferSize = ringBufferSize; + handle->rxRingBufferHead = 0U; + handle->rxRingBufferTail = 0U; + /* ring buffer is ready we can start receiving data */ + base->FIFOINTENSET = USART_FIFOINTENSET_RXLVL_MASK | USART_FIFOINTENSET_RXERR_MASK; +} + +/*! + * brief Aborts the background transfer and uninstalls the ring buffer. + * + * This function aborts the background transfer and uninstalls the ring buffer. + * + * param base USART peripheral base address. + * param handle USART handle pointer. + */ +void USART_TransferStopRingBuffer(USART_Type *base, usart_handle_t *handle) +{ + /* Check arguments */ + assert(NULL != base); + assert(NULL != handle); + + if (handle->rxState == (uint8_t)kUSART_RxIdle) + { + base->FIFOINTENCLR = USART_FIFOINTENCLR_RXLVL_MASK | USART_FIFOINTENCLR_RXERR_MASK; + } + handle->rxRingBuffer = NULL; + handle->rxRingBufferSize = 0U; + handle->rxRingBufferHead = 0U; + handle->rxRingBufferTail = 0U; +} + +/*! + * brief Initializes a USART instance with user configuration structure and peripheral clock. + * + * This function configures the USART module with the user-defined settings. The user can configure the configuration + * structure and also get the default configuration by using the USART_GetDefaultConfig() function. + * Example below shows how to use this API to configure USART. + * code + * usart_config_t usartConfig; + * usartConfig.baudRate_Bps = 115200U; + * usartConfig.parityMode = kUSART_ParityDisabled; + * usartConfig.stopBitCount = kUSART_OneStopBit; + * USART_Init(USART1, &usartConfig, 20000000U); + * endcode + * + * param base USART peripheral base address. + * param config Pointer to user-defined configuration structure. + * param srcClock_Hz USART clock source frequency in HZ. + * retval kStatus_USART_BaudrateNotSupport Baudrate is not support in current clock source. + * retval kStatus_InvalidArgument USART base address is not valid + * retval kStatus_Success Status USART initialize succeed + */ +status_t USART_Init(USART_Type *base, const usart_config_t *config, uint32_t srcClock_Hz) +{ + int result; + + /* check arguments */ + assert(!((NULL == base) || (NULL == config) || (0U == srcClock_Hz))); + if ((NULL == base) || (NULL == config) || (0U == srcClock_Hz)) + { + return kStatus_InvalidArgument; + } + + /* initialize flexcomm to USART mode */ + result = FLEXCOMM_Init(base, FLEXCOMM_PERIPH_USART); + if (kStatus_Success != result) + { + return result; + } + + if (config->enableTx) + { + /* empty and enable txFIFO */ + base->FIFOCFG |= USART_FIFOCFG_EMPTYTX_MASK | USART_FIFOCFG_ENABLETX_MASK; + /* setup trigger level */ + base->FIFOTRIG &= ~(USART_FIFOTRIG_TXLVL_MASK); + base->FIFOTRIG |= USART_FIFOTRIG_TXLVL(config->txWatermark); + /* enable trigger interrupt */ + base->FIFOTRIG |= USART_FIFOTRIG_TXLVLENA_MASK; + } + + /* empty and enable rxFIFO */ + if (config->enableRx) + { + base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK | USART_FIFOCFG_ENABLERX_MASK; + /* setup trigger level */ + base->FIFOTRIG &= ~(USART_FIFOTRIG_RXLVL_MASK); + base->FIFOTRIG |= USART_FIFOTRIG_RXLVL(config->rxWatermark); + /* enable trigger interrupt */ + base->FIFOTRIG |= USART_FIFOTRIG_RXLVLENA_MASK; + } + /* setup configuration and enable USART */ + base->CFG = USART_CFG_PARITYSEL(config->parityMode) | USART_CFG_STOPLEN(config->stopBitCount) | + USART_CFG_DATALEN(config->bitCountPerChar) | USART_CFG_LOOP(config->loopback) | + USART_CFG_SYNCEN((uint32_t)config->syncMode >> 1) | USART_CFG_SYNCMST((uint8_t)config->syncMode) | + USART_CFG_CLKPOL(config->clockPolarity) | USART_CFG_MODE32K(config->enableMode32k) | + USART_CFG_CTSEN(config->enableHardwareFlowControl) | USART_CFG_ENABLE_MASK; + + /* Setup baudrate */ + if (config->enableMode32k) + { + if ((9600U % config->baudRate_Bps) == 0U) + { + base->BRG = 9600U / config->baudRate_Bps; + } + else + { + return kStatus_USART_BaudrateNotSupport; + } + } + else + { + result = USART_SetBaudRate(base, config->baudRate_Bps, srcClock_Hz); + if (kStatus_Success != result) + { + return result; + } + } + /* Setting continuous Clock configuration. used for synchronous mode. */ + USART_EnableContinuousSCLK(base, config->enableContinuousSCLK); + + return kStatus_Success; +} + +/*! + * brief Deinitializes a USART instance. + * + * This function waits for TX complete, disables TX and RX, and disables the USART clock. + * + * param base USART peripheral base address. + */ +void USART_Deinit(USART_Type *base) +{ + /* Check arguments */ + assert(NULL != base); + while (0U == (base->STAT & USART_STAT_TXIDLE_MASK)) + { + } + /* Disable interrupts, disable dma requests, disable peripheral */ + base->FIFOINTENCLR = USART_FIFOINTENCLR_TXERR_MASK | USART_FIFOINTENCLR_RXERR_MASK | USART_FIFOINTENCLR_TXLVL_MASK | + USART_FIFOINTENCLR_RXLVL_MASK; + base->FIFOCFG &= ~(USART_FIFOCFG_DMATX_MASK | USART_FIFOCFG_DMARX_MASK); + base->CFG &= ~(USART_CFG_ENABLE_MASK); +} + +/*! + * brief Gets the default configuration structure. + * + * This function initializes the USART configuration structure to a default value. The default + * values are: + * usartConfig->baudRate_Bps = 115200U; + * usartConfig->parityMode = kUSART_ParityDisabled; + * usartConfig->stopBitCount = kUSART_OneStopBit; + * usartConfig->bitCountPerChar = kUSART_8BitsPerChar; + * usartConfig->loopback = false; + * usartConfig->enableTx = false; + * usartConfig->enableRx = false; + * + * param config Pointer to configuration structure. + */ +void USART_GetDefaultConfig(usart_config_t *config) +{ + /* Check arguments */ + assert(NULL != config); + + /* Initializes the configure structure to zero. */ + (void)memset(config, 0, sizeof(*config)); + + /* Set always all members ! */ + config->baudRate_Bps = 115200U; + config->parityMode = kUSART_ParityDisabled; + config->stopBitCount = kUSART_OneStopBit; + config->bitCountPerChar = kUSART_8BitsPerChar; + config->loopback = false; + config->enableRx = false; + config->enableTx = false; + config->enableMode32k = false; + config->txWatermark = kUSART_TxFifo0; + config->rxWatermark = kUSART_RxFifo1; + config->syncMode = kUSART_SyncModeDisabled; + config->enableContinuousSCLK = false; + config->clockPolarity = kUSART_RxSampleOnFallingEdge; + config->enableHardwareFlowControl = false; +} + +/*! + * brief Sets the USART instance baud rate. + * + * This function configures the USART module baud rate. This function is used to update + * the USART module baud rate after the USART module is initialized by the USART_Init. + * code + * USART_SetBaudRate(USART1, 115200U, 20000000U); + * endcode + * + * param base USART peripheral base address. + * param baudrate_Bps USART baudrate to be set. + * param srcClock_Hz USART clock source frequency in HZ. + * retval kStatus_USART_BaudrateNotSupport Baudrate is not support in current clock source. + * retval kStatus_Success Set baudrate succeed. + * retval kStatus_InvalidArgument One or more arguments are invalid. + */ +status_t USART_SetBaudRate(USART_Type *base, uint32_t baudrate_Bps, uint32_t srcClock_Hz) +{ + uint32_t best_diff = (uint32_t)-1, best_osrval = 0xf, best_brgval = (uint32_t)-1; + uint32_t osrval, brgval, diff, baudrate; + + /* check arguments */ + assert(!((NULL == base) || (0U == baudrate_Bps) || (0U == srcClock_Hz))); + if ((NULL == base) || (0U == baudrate_Bps) || (0U == srcClock_Hz)) + { + return kStatus_InvalidArgument; + } + + /* If synchronous master mode is enabled, only configure the BRG value. */ + if ((base->CFG & USART_CFG_SYNCEN_MASK) != 0U) + { + if ((base->CFG & USART_CFG_SYNCMST_MASK) != 0U) + { + brgval = srcClock_Hz / baudrate_Bps; + base->BRG = brgval - 1U; + } + } + else + { + /* + * Smaller values of OSR can make the sampling position within a data bit less accurate and may + * potentially cause more noise errors or incorrect data. + */ + for (osrval = best_osrval; osrval >= 8U; osrval--) + { + brgval = (((srcClock_Hz * 10U) / ((osrval + 1U) * baudrate_Bps)) - 5U) / 10U; + if (brgval > 0xFFFFU) + { + continue; + } + baudrate = srcClock_Hz / ((osrval + 1U) * (brgval + 1U)); + diff = (baudrate_Bps < baudrate) ? (baudrate - baudrate_Bps) : (baudrate_Bps - baudrate); + if (diff < best_diff) + { + best_diff = diff; + best_osrval = osrval; + best_brgval = brgval; + } + } + + /* Check to see if actual baud rate is within 3% of desired baud rate + * based on the best calculated OSR and BRG value */ + baudrate = srcClock_Hz / ((best_osrval + 1U) * (best_brgval + 1U)); + diff = (baudrate_Bps < baudrate) ? (baudrate - baudrate_Bps) : (baudrate_Bps - baudrate); + if (diff > ((baudrate_Bps / 100U) * 3U)) + { + return kStatus_USART_BaudrateNotSupport; + } + + /* value over range */ + if (best_brgval > 0xFFFFU) + { + return kStatus_USART_BaudrateNotSupport; + } + + base->OSR = best_osrval; + base->BRG = best_brgval; + } + + return kStatus_Success; +} + +/*! + * brief Enable 32 kHz mode which USART uses clock from the RTC oscillator as the clock source. + * + * Please note that in order to use a 32 kHz clock to operate USART properly, the RTC oscillator + * and its 32 kHz output must be manully enabled by user, by calling RTC_Init and setting + * SYSCON_RTCOSCCTRL_EN bit to 1. + * And in 32kHz clocking mode the USART can only work at 9600 baudrate or at the baudrate that + * 9600 can evenly divide, eg: 4800, 3200. + * + * param base USART peripheral base address. + * param baudRate_Bps USART baudrate to be set.. + * param enableMode32k true is 32k mode, false is normal mode. + * param srcClock_Hz USART clock source frequency in HZ. + * retval kStatus_USART_BaudrateNotSupport Baudrate is not support in current clock source. + * retval kStatus_Success Set baudrate succeed. + * retval kStatus_InvalidArgument One or more arguments are invalid. + */ +status_t USART_Enable32kMode(USART_Type *base, uint32_t baudRate_Bps, bool enableMode32k, uint32_t srcClock_Hz) +{ + status_t result = kStatus_Success; + base->CFG &= ~(USART_CFG_ENABLE_MASK); + if (enableMode32k) + { + base->CFG |= USART_CFG_MODE32K_MASK; + if ((9600U % baudRate_Bps) == 0U) + { + base->BRG = 9600U / baudRate_Bps - 1U; + } + else + { + return kStatus_USART_BaudrateNotSupport; + } + } + else + { + base->CFG &= ~(USART_CFG_MODE32K_MASK); + result = USART_SetBaudRate(base, baudRate_Bps, srcClock_Hz); + if (kStatus_Success != result) + { + return result; + } + } + base->CFG |= USART_CFG_ENABLE_MASK; + return result; +} + +/*! + * brief Enable 9-bit data mode for USART. + * + * This function set the 9-bit mode for USART module. The 9th bit is not used for parity thus can be modified by user. + * + * param base USART peripheral base address. + * param enable true to enable, false to disable. + */ +void USART_Enable9bitMode(USART_Type *base, bool enable) +{ + assert(base != NULL); + + uint32_t temp = 0U; + + if (enable) + { + /* Set USART 9-bit mode, disable parity. */ + temp = base->CFG & ~((uint32_t)USART_CFG_DATALEN_MASK | (uint32_t)USART_CFG_PARITYSEL_MASK); + temp |= (uint32_t)USART_CFG_DATALEN(0x2U); + base->CFG = temp; + } + else + { + /* Set USART to 8-bit mode. */ + base->CFG &= ~((uint32_t)USART_CFG_DATALEN_MASK); + base->CFG |= (uint32_t)USART_CFG_DATALEN(0x1U); + } +} + +/*! + * brief Transmit an address frame in 9-bit data mode. + * + * param base USART peripheral base address. + * param address USART slave address. + */ +void USART_SendAddress(USART_Type *base, uint8_t address) +{ + assert(base != NULL); + base->FIFOWR = ((uint32_t)address | 0x100UL); +} + +/*! + * brief Writes to the TX register using a blocking method. + * + * This function polls the TX register, waits for the TX register to be empty or for the TX FIFO + * to have room and writes data to the TX buffer. + * + * param base USART peripheral base address. + * param data Start address of the data to write. + * param length Size of the data to write. + * retval kStatus_USART_Timeout Transmission timed out and was aborted. + * retval kStatus_InvalidArgument Invalid argument. + * retval kStatus_Success Successfully wrote all data. + */ +status_t USART_WriteBlocking(USART_Type *base, const uint8_t *data, size_t length) +{ + /* Check arguments */ + assert(!((NULL == base) || (NULL == data))); +#if UART_RETRY_TIMES + uint32_t waitTimes; +#endif + if ((NULL == base) || (NULL == data)) + { + return kStatus_InvalidArgument; + } + /* Check whether txFIFO is enabled */ + if (0U == (base->FIFOCFG & USART_FIFOCFG_ENABLETX_MASK)) + { + return kStatus_InvalidArgument; + } + for (; length > 0U; length--) + { + /* Loop until txFIFO get some space for new data */ +#if UART_RETRY_TIMES + waitTimes = UART_RETRY_TIMES; + while ((0U == (base->FIFOSTAT & USART_FIFOSTAT_TXNOTFULL_MASK)) && (--waitTimes != 0U)) +#else + while (0U == (base->FIFOSTAT & USART_FIFOSTAT_TXNOTFULL_MASK)) +#endif + { + } +#if UART_RETRY_TIMES + if (0U == waitTimes) + { + return kStatus_USART_Timeout; + } +#endif + base->FIFOWR = *data; + data++; + } + /* Wait to finish transfer */ +#if UART_RETRY_TIMES + waitTimes = UART_RETRY_TIMES; + while ((0U == (base->STAT & USART_STAT_TXIDLE_MASK)) && (--waitTimes != 0U)) +#else + while (0U == (base->STAT & USART_STAT_TXIDLE_MASK)) +#endif + { + } +#if UART_RETRY_TIMES + if (0U == waitTimes) + { + return kStatus_USART_Timeout; + } +#endif + return kStatus_Success; +} + +/*! + * brief Read RX data register using a blocking method. + * + * This function polls the RX register, waits for the RX register to be full or for RX FIFO to + * have data and read data from the TX register. + * + * param base USART peripheral base address. + * param data Start address of the buffer to store the received data. + * param length Size of the buffer. + * retval kStatus_USART_FramingError Receiver overrun happened while receiving data. + * retval kStatus_USART_ParityError Noise error happened while receiving data. + * retval kStatus_USART_NoiseError Framing error happened while receiving data. + * retval kStatus_USART_RxError Overflow or underflow rxFIFO happened. + * retval kStatus_USART_Timeout Transmission timed out and was aborted. + * retval kStatus_Success Successfully received all data. + */ +status_t USART_ReadBlocking(USART_Type *base, uint8_t *data, size_t length) +{ + uint32_t statusFlag; + status_t status = kStatus_Success; +#if UART_RETRY_TIMES + uint32_t waitTimes; +#endif + + /* check arguments */ + assert(!((NULL == base) || (NULL == data))); + if ((NULL == base) || (NULL == data)) + { + return kStatus_InvalidArgument; + } + + /* Check whether rxFIFO is enabled */ + if ((base->FIFOCFG & USART_FIFOCFG_ENABLERX_MASK) == 0U) + { + return kStatus_Fail; + } + for (; length > 0U; length--) + { + /* loop until rxFIFO have some data to read */ +#if UART_RETRY_TIMES + waitTimes = UART_RETRY_TIMES; + while (((base->FIFOSTAT & USART_FIFOSTAT_RXNOTEMPTY_MASK) == 0U) && (--waitTimes != 0U)) +#else + while ((base->FIFOSTAT & USART_FIFOSTAT_RXNOTEMPTY_MASK) == 0U) +#endif + { + } +#if UART_RETRY_TIMES + if (waitTimes == 0U) + { + status = kStatus_USART_Timeout; + break; + } +#endif + /* check rxFIFO statusFlag */ + if ((base->FIFOSTAT & USART_FIFOSTAT_RXERR_MASK) != 0U) + { + base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK; + base->FIFOSTAT |= USART_FIFOSTAT_RXERR_MASK; + status = kStatus_USART_RxError; + break; + } + /* check receive statusFlag */ + statusFlag = base->STAT; + /* Clear all status flags */ + base->STAT |= statusFlag; + if ((statusFlag & USART_STAT_PARITYERRINT_MASK) != 0U) + { + status = kStatus_USART_ParityError; + } + if ((statusFlag & USART_STAT_FRAMERRINT_MASK) != 0U) + { + status = kStatus_USART_FramingError; + } + if ((statusFlag & USART_STAT_RXNOISEINT_MASK) != 0U) + { + status = kStatus_USART_NoiseError; + } + + if (kStatus_Success == status) + { + *data = (uint8_t)base->FIFORD; + data++; + } + else + { + break; + } + } + return status; +} + +/*! + * brief Initializes the USART handle. + * + * This function initializes the USART handle which can be used for other USART + * transactional APIs. Usually, for a specified USART instance, + * call this API once to get the initialized handle. + * + * param base USART peripheral base address. + * param handle USART handle pointer. + * param callback The callback function. + * param userData The parameter of the callback function. + */ +status_t USART_TransferCreateHandle(USART_Type *base, + usart_handle_t *handle, + usart_transfer_callback_t callback, + void *userData) +{ + /* Check 'base' */ + assert(!((NULL == base) || (NULL == handle))); + + uint32_t instance = 0; + usart_to_flexcomm_t handler; + handler.usart_master_handler = USART_TransferHandleIRQ; + + if ((NULL == base) || (NULL == handle)) + { + return kStatus_InvalidArgument; + } + + instance = USART_GetInstance(base); + + (void)memset(handle, 0, sizeof(*handle)); + /* Set the TX/RX state. */ + handle->rxState = (uint8_t)kUSART_RxIdle; + handle->txState = (uint8_t)kUSART_TxIdle; + /* Set the callback and user data. */ + handle->callback = callback; + handle->userData = userData; + handle->rxWatermark = (uint8_t)USART_FIFOTRIG_RXLVL_GET(base); + handle->txWatermark = (uint8_t)USART_FIFOTRIG_TXLVL_GET(base); + + FLEXCOMM_SetIRQHandler(base, handler.flexcomm_handler, handle); + + /* Enable interrupt in NVIC. */ + (void)EnableIRQ(s_usartIRQ[instance]); + + return kStatus_Success; +} + +/*! + * brief Transmits a buffer of data using the interrupt method. + * + * This function sends data using an interrupt method. This is a non-blocking function, which + * returns directly without waiting for all data to be written to the TX register. When + * all data is written to the TX register in the IRQ handler, the USART driver calls the callback + * function and passes the ref kStatus_USART_TxIdle as status parameter. + * + * param base USART peripheral base address. + * param handle USART handle pointer. + * param xfer USART transfer structure. See #usart_transfer_t. + * retval kStatus_Success Successfully start the data transmission. + * retval kStatus_USART_TxBusy Previous transmission still not finished, data not all written to TX register yet. + * retval kStatus_InvalidArgument Invalid argument. + */ +status_t USART_TransferSendNonBlocking(USART_Type *base, usart_handle_t *handle, usart_transfer_t *xfer) +{ + /* Check arguments */ + assert(!((NULL == base) || (NULL == handle) || (NULL == xfer))); + if ((NULL == base) || (NULL == handle) || (NULL == xfer)) + { + return kStatus_InvalidArgument; + } + /* Check xfer members */ + assert(!((0U == xfer->dataSize) || (NULL == xfer->txData))); + if ((0U == xfer->dataSize) || (NULL == xfer->txData)) + { + return kStatus_InvalidArgument; + } + + /* Return error if current TX busy. */ + if ((uint8_t)kUSART_TxBusy == handle->txState) + { + return kStatus_USART_TxBusy; + } + else + { + /* Disable IRQ when configuring transfer handle, in case interrupt occurs during the process and messes up the + * handle value. */ + uint32_t interruptMask = USART_GetEnabledInterrupts(base); + USART_DisableInterrupts(base, interruptMask); + handle->txData = xfer->txData; + handle->txDataSize = xfer->dataSize; + handle->txDataSizeAll = xfer->dataSize; + handle->txState = (uint8_t)kUSART_TxBusy; + /* Enable transmiter interrupt and the previously disabled interrupt. */ + USART_EnableInterrupts(base, interruptMask | (uint32_t)kUSART_TxLevelInterruptEnable); + } + return kStatus_Success; +} + +/*! + * brief Aborts the interrupt-driven data transmit. + * + * This function aborts the interrupt driven data sending. The user can get the remainBtyes to find out + * how many bytes are still not sent out. + * + * param base USART peripheral base address. + * param handle USART handle pointer. + */ +void USART_TransferAbortSend(USART_Type *base, usart_handle_t *handle) +{ + assert(NULL != handle); + + /* Disable interrupts */ + USART_DisableInterrupts(base, (uint32_t)kUSART_TxLevelInterruptEnable); + /* Empty txFIFO */ + base->FIFOCFG |= USART_FIFOCFG_EMPTYTX_MASK; + + handle->txDataSize = 0U; + handle->txState = (uint8_t)kUSART_TxIdle; +} + +/*! + * brief Get the number of bytes that have been sent out to bus. + * + * This function gets the number of bytes that have been sent out to bus by interrupt method. + * + * param base USART peripheral base address. + * param handle USART handle pointer. + * param count Send bytes count. + * retval kStatus_NoTransferInProgress No send in progress. + * retval kStatus_InvalidArgument Parameter is invalid. + * retval kStatus_Success Get successfully through the parameter \p count; + */ +status_t USART_TransferGetSendCount(USART_Type *base, usart_handle_t *handle, uint32_t *count) +{ + assert(NULL != handle); + assert(NULL != count); + + if ((uint8_t)kUSART_TxIdle == handle->txState) + { + return kStatus_NoTransferInProgress; + } + + *count = handle->txDataSizeAll - handle->txDataSize - + ((base->FIFOSTAT & USART_FIFOSTAT_TXLVL_MASK) >> USART_FIFOSTAT_TXLVL_SHIFT); + + return kStatus_Success; +} + +/*! + * brief Receives a buffer of data using an interrupt method. + * + * This function receives data using an interrupt method. This is a non-blocking function, which + * returns without waiting for all data to be received. + * If the RX ring buffer is used and not empty, the data in the ring buffer is copied and + * the parameter p receivedBytes shows how many bytes are copied from the ring buffer. + * After copying, if the data in the ring buffer is not enough to read, the receive + * request is saved by the USART driver. When the new data arrives, the receive request + * is serviced first. When all data is received, the USART driver notifies the upper layer + * through a callback function and passes the status parameter ref kStatus_USART_RxIdle. + * For example, the upper layer needs 10 bytes but there are only 5 bytes in the ring buffer. + * The 5 bytes are copied to the xfer->data and this function returns with the + * parameter p receivedBytes set to 5. For the left 5 bytes, newly arrived data is + * saved from the xfer->data[5]. When 5 bytes are received, the USART driver notifies the upper layer. + * If the RX ring buffer is not enabled, this function enables the RX and RX interrupt + * to receive data to the xfer->data. When all data is received, the upper layer is notified. + * + * param base USART peripheral base address. + * param handle USART handle pointer. + * param xfer USART transfer structure, see #usart_transfer_t. + * param receivedBytes Bytes received from the ring buffer directly. + * retval kStatus_Success Successfully queue the transfer into transmit queue. + * retval kStatus_USART_RxBusy Previous receive request is not finished. + * retval kStatus_InvalidArgument Invalid argument. + */ +status_t USART_TransferReceiveNonBlocking(USART_Type *base, + usart_handle_t *handle, + usart_transfer_t *xfer, + size_t *receivedBytes) +{ + uint32_t i; + /* How many bytes to copy from ring buffer to user memory. */ + size_t bytesToCopy = 0U; + /* How many bytes to receive. */ + size_t bytesToReceive; + /* How many bytes currently have received. */ + size_t bytesCurrentReceived; + uint32_t interruptMask = 0U; + + /* Check arguments */ + assert(!((NULL == base) || (NULL == handle) || (NULL == xfer))); + if ((NULL == base) || (NULL == handle) || (NULL == xfer)) + { + return kStatus_InvalidArgument; + } + /* Check xfer members */ + assert(!((0U == xfer->dataSize) || (NULL == xfer->rxData))); + if ((0U == xfer->dataSize) || (NULL == xfer->rxData)) + { + return kStatus_InvalidArgument; + } + + /* Enable address detect when address match is enabled. */ + if ((base->CFG & (uint32_t)USART_CFG_AUTOADDR_MASK) != 0U) + { + base->CTL |= (uint32_t)USART_CTL_ADDRDET_MASK; + } + + /* How to get data: + 1. If RX ring buffer is not enabled, then save xfer->data and xfer->dataSize + to uart handle, enable interrupt to store received data to xfer->data. When + all data received, trigger callback. + 2. If RX ring buffer is enabled and not empty, get data from ring buffer first. + If there are enough data in ring buffer, copy them to xfer->data and return. + If there are not enough data in ring buffer, copy all of them to xfer->data, + save the xfer->data remained empty space to uart handle, receive data + to this empty space and trigger callback when finished. */ + if ((uint8_t)kUSART_RxBusy == handle->rxState) + { + return kStatus_USART_RxBusy; + } + else + { + bytesToReceive = xfer->dataSize; + bytesCurrentReceived = 0U; + /* If RX ring buffer is used. */ + if (handle->rxRingBuffer != NULL) + { + /* Disable IRQ, protect ring buffer. */ + interruptMask = USART_GetEnabledInterrupts(base); + USART_DisableInterrupts(base, interruptMask); + + /* How many bytes in RX ring buffer currently. */ + bytesToCopy = USART_TransferGetRxRingBufferLength(handle); + if (bytesToCopy != 0U) + { + bytesToCopy = MIN(bytesToReceive, bytesToCopy); + bytesToReceive -= bytesToCopy; + /* Copy data from ring buffer to user memory. */ + for (i = 0U; i < bytesToCopy; i++) + { + xfer->rxData[bytesCurrentReceived++] = handle->rxRingBuffer[handle->rxRingBufferTail]; + /* Wrap to 0. Not use modulo (%) because it might be large and slow. */ + if ((size_t)handle->rxRingBufferTail + 1U == handle->rxRingBufferSize) + { + handle->rxRingBufferTail = 0U; + } + else + { + handle->rxRingBufferTail++; + } + } + } + /* If ring buffer does not have enough data, still need to read more data. */ + if (bytesToReceive != 0U) + { + /* No data in ring buffer, save the request to UART handle. */ + handle->rxData = xfer->rxData + bytesCurrentReceived; + handle->rxDataSize = bytesToReceive; + handle->rxDataSizeAll = xfer->dataSize; + handle->rxState = (uint8_t)kUSART_RxBusy; + } + /* Re-enable IRQ. */ + USART_EnableInterrupts(base, interruptMask); + /* Call user callback since all data are received. */ + if (0U == bytesToReceive) + { + if (handle->callback != NULL) + { + handle->callback(base, handle, kStatus_USART_RxIdle, handle->userData); + } + } + } + /* Ring buffer not used. */ + else + { + /* Disable IRQ when configuring transfer handle, in case interrupt occurs during the process and messes up + * the handle value. */ + interruptMask = USART_GetEnabledInterrupts(base); + USART_DisableInterrupts(base, interruptMask); + handle->rxData = xfer->rxData + bytesCurrentReceived; + handle->rxDataSize = bytesToReceive; + handle->rxDataSizeAll = bytesToReceive; + handle->rxState = (uint8_t)kUSART_RxBusy; + + /* Enable RX interrupt. */ + base->FIFOINTENSET = USART_FIFOINTENSET_RXLVL_MASK; + /* Re-enable IRQ. */ + USART_EnableInterrupts(base, interruptMask); + } + /* Return the how many bytes have read. */ + if (receivedBytes != NULL) + { + *receivedBytes = bytesCurrentReceived; + } + } + return kStatus_Success; +} + +/*! + * brief Aborts the interrupt-driven data receiving. + * + * This function aborts the interrupt-driven data receiving. The user can get the remainBytes to find out + * how many bytes not received yet. + * + * param base USART peripheral base address. + * param handle USART handle pointer. + */ +void USART_TransferAbortReceive(USART_Type *base, usart_handle_t *handle) +{ + assert(NULL != handle); + + /* Only abort the receive to handle->rxData, the RX ring buffer is still working. */ + if (NULL == handle->rxRingBuffer) + { + /* Disable interrupts */ + USART_DisableInterrupts(base, (uint32_t)kUSART_RxLevelInterruptEnable); + /* Empty rxFIFO */ + base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK; + } + + handle->rxDataSize = 0U; + handle->rxState = (uint8_t)kUSART_RxIdle; +} + +/*! + * brief Get the number of bytes that have been received. + * + * This function gets the number of bytes that have been received. + * + * param base USART peripheral base address. + * param handle USART handle pointer. + * param count Receive bytes count. + * retval kStatus_NoTransferInProgress No receive in progress. + * retval kStatus_InvalidArgument Parameter is invalid. + * retval kStatus_Success Get successfully through the parameter \p count; + */ +status_t USART_TransferGetReceiveCount(USART_Type *base, usart_handle_t *handle, uint32_t *count) +{ + assert(NULL != handle); + assert(NULL != count); + + if ((uint8_t)kUSART_RxIdle == handle->rxState) + { + return kStatus_NoTransferInProgress; + } + + *count = handle->rxDataSizeAll - handle->rxDataSize; + + return kStatus_Success; +} + +/*! + * brief USART IRQ handle function. + * + * This function handles the USART transmit and receive IRQ request. + * + * param base USART peripheral base address. + * param handle USART handle pointer. + */ +void USART_TransferHandleIRQ(USART_Type *base, usart_handle_t *handle) +{ + /* Check arguments */ + assert((NULL != base) && (NULL != handle)); + + bool receiveEnabled = ((handle->rxDataSize != 0U) || (handle->rxRingBuffer != NULL)); + bool sendEnabled = (handle->txDataSize != 0U); + uint8_t rxdata; + size_t tmpsize; + + /* If RX overrun. */ + if ((base->FIFOSTAT & USART_FIFOSTAT_RXERR_MASK) != 0U) + { + /* Clear rx error state. */ + base->FIFOSTAT |= USART_FIFOSTAT_RXERR_MASK; + /* clear rxFIFO */ + base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK; + /* Trigger callback. */ + if (handle->callback != NULL) + { + handle->callback(base, handle, kStatus_USART_RxError, handle->userData); + } + } + /* TX under run, happens when slave is in synchronous mode and the data is not written in tx register in time. */ + if ((base->FIFOSTAT & USART_FIFOSTAT_TXERR_MASK) != 0U) + { + /* Clear tx error state. */ + base->FIFOSTAT |= USART_FIFOSTAT_TXERR_MASK; + /* Trigger callback. */ + if (handle->callback != NULL) + { + handle->callback(base, handle, kStatus_USART_TxError, handle->userData); + } + } + /* If noise error. */ + if ((base->STAT & USART_STAT_RXNOISEINT_MASK) != 0U) + { + /* Clear rx error state. */ + base->STAT |= USART_STAT_RXNOISEINT_MASK; + /* clear rxFIFO */ + base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK; + /* Trigger callback. */ + if (handle->callback != NULL) + { + handle->callback(base, handle, kStatus_USART_NoiseError, handle->userData); + } + } + /* If framing error. */ + if ((base->STAT & USART_STAT_FRAMERRINT_MASK) != 0U) + { + /* Clear rx error state. */ + base->STAT |= USART_STAT_FRAMERRINT_MASK; + /* clear rxFIFO */ + base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK; + /* Trigger callback. */ + if (handle->callback != NULL) + { + handle->callback(base, handle, kStatus_USART_FramingError, handle->userData); + } + } + /* If parity error. */ + if ((base->STAT & USART_STAT_PARITYERRINT_MASK) != 0U) + { + /* Clear rx error state. */ + base->STAT |= USART_STAT_PARITYERRINT_MASK; + /* clear rxFIFO */ + base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK; + /* Trigger callback. */ + if (handle->callback != NULL) + { + handle->callback(base, handle, kStatus_USART_ParityError, handle->userData); + } + } + while ((receiveEnabled && ((base->FIFOSTAT & USART_FIFOSTAT_RXNOTEMPTY_MASK) != 0U)) || + (sendEnabled && ((base->FIFOSTAT & USART_FIFOSTAT_TXNOTFULL_MASK) != 0U))) + { + /* Receive data */ + if (receiveEnabled && ((base->FIFOSTAT & USART_FIFOSTAT_RXNOTEMPTY_MASK) != 0U)) + { + /* Clear address detect when RXFIFO has data. */ + base->CTL &= ~(uint32_t)USART_CTL_ADDRDET_MASK; + /* Receive to app bufffer if app buffer is present */ + if (handle->rxDataSize != 0U) + { + rxdata = (uint8_t)base->FIFORD; + *handle->rxData = rxdata; + handle->rxDataSize--; + handle->rxData++; + receiveEnabled = ((handle->rxDataSize != 0U) || (handle->rxRingBuffer != NULL)); + if (0U == handle->rxDataSize) + { + if (NULL == handle->rxRingBuffer) + { + base->FIFOINTENCLR = USART_FIFOINTENCLR_RXLVL_MASK | USART_FIFOINTENSET_RXERR_MASK; + } + handle->rxState = (uint8_t)kUSART_RxIdle; + if (handle->callback != NULL) + { + handle->callback(base, handle, kStatus_USART_RxIdle, handle->userData); + } + } + } + /* Otherwise receive to ring buffer if ring buffer is present */ + else + { + if (handle->rxRingBuffer != NULL) + { + /* If RX ring buffer is full, trigger callback to notify over run. */ + if (USART_TransferIsRxRingBufferFull(handle)) + { + if (handle->callback != NULL) + { + handle->callback(base, handle, kStatus_USART_RxRingBufferOverrun, handle->userData); + } + } + /* If ring buffer is still full after callback function, the oldest data is overridden. */ + if (USART_TransferIsRxRingBufferFull(handle)) + { + /* Increase handle->rxRingBufferTail to make room for new data. */ + if ((size_t)handle->rxRingBufferTail + 1U == handle->rxRingBufferSize) + { + handle->rxRingBufferTail = 0U; + } + else + { + handle->rxRingBufferTail++; + } + } + /* Read data. */ + rxdata = (uint8_t)base->FIFORD; + handle->rxRingBuffer[handle->rxRingBufferHead] = rxdata; + /* Increase handle->rxRingBufferHead. */ + if ((size_t)handle->rxRingBufferHead + 1U == handle->rxRingBufferSize) + { + handle->rxRingBufferHead = 0U; + } + else + { + handle->rxRingBufferHead++; + } + } + } + } + /* Send data */ + if (sendEnabled && ((base->FIFOSTAT & USART_FIFOSTAT_TXNOTFULL_MASK) != 0U)) + { + base->FIFOWR = *handle->txData; + handle->txDataSize--; + handle->txData++; + sendEnabled = handle->txDataSize != 0U; + if (!sendEnabled) + { + base->FIFOINTENCLR = USART_FIFOINTENCLR_TXLVL_MASK; + + base->INTENSET = USART_INTENSET_TXIDLEEN_MASK; + } + } + } + + /* Tx idle and the interrupt is enabled. */ + if ((0U != (base->INTENSET & USART_INTENSET_TXIDLEEN_MASK)) && (0U != (base->INTSTAT & USART_INTSTAT_TXIDLE_MASK))) + { + /* Set txState to idle only when all data has been sent out to bus. */ + handle->txState = (uint8_t)kUSART_TxIdle; + /* Disable tx idle interrupt */ + base->INTENCLR = USART_INTENCLR_TXIDLECLR_MASK; + + /* Trigger callback. */ + if (handle->callback != NULL) + { + handle->callback(base, handle, kStatus_USART_TxIdle, handle->userData); + } + } + + /* ring buffer is not used */ + if (NULL == handle->rxRingBuffer) + { + tmpsize = handle->rxDataSize; + + /* restore if rx transfer ends and rxLevel is different from default value */ + if ((tmpsize == 0U) && (USART_FIFOTRIG_RXLVL_GET(base) != handle->rxWatermark)) + { + base->FIFOTRIG = + (base->FIFOTRIG & (~USART_FIFOTRIG_RXLVL_MASK)) | USART_FIFOTRIG_RXLVL(handle->rxWatermark); + } + /* decrease level if rx transfer is bellow */ + if ((tmpsize != 0U) && (tmpsize < (USART_FIFOTRIG_RXLVL_GET(base) + 1U))) + { + base->FIFOTRIG = (base->FIFOTRIG & (~USART_FIFOTRIG_RXLVL_MASK)) | (USART_FIFOTRIG_RXLVL(tmpsize - 1U)); + } + } +} diff --git a/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_usart.h b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_usart.h new file mode 100644 index 0000000000..ef4715c4c5 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_usart.h @@ -0,0 +1,903 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2022NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_USART_H_ +#define _FSL_USART_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup usart_driver + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief USART driver version. */ +#define FSL_USART_DRIVER_VERSION (MAKE_VERSION(2, 7, 0)) +/*@}*/ + +#define USART_FIFOTRIG_TXLVL_GET(base) (((base)->FIFOTRIG & USART_FIFOTRIG_TXLVL_MASK) >> USART_FIFOTRIG_TXLVL_SHIFT) +#define USART_FIFOTRIG_RXLVL_GET(base) (((base)->FIFOTRIG & USART_FIFOTRIG_RXLVL_MASK) >> USART_FIFOTRIG_RXLVL_SHIFT) + +/*! @brief Retry times for waiting flag. */ +#ifndef UART_RETRY_TIMES +#define UART_RETRY_TIMES 0U /* Defining to zero means to keep waiting for the flag until it is assert/deassert. */ +#endif + +/*! @brief Error codes for the USART driver. */ +enum +{ + kStatus_USART_TxBusy = MAKE_STATUS(kStatusGroup_LPC_USART, 0), /*!< Transmitter is busy. */ + kStatus_USART_RxBusy = MAKE_STATUS(kStatusGroup_LPC_USART, 1), /*!< Receiver is busy. */ + kStatus_USART_TxIdle = MAKE_STATUS(kStatusGroup_LPC_USART, 2), /*!< USART transmitter is idle. */ + kStatus_USART_RxIdle = MAKE_STATUS(kStatusGroup_LPC_USART, 3), /*!< USART receiver is idle. */ + kStatus_USART_TxError = MAKE_STATUS(kStatusGroup_LPC_USART, 7), /*!< Error happens on txFIFO. */ + kStatus_USART_RxError = MAKE_STATUS(kStatusGroup_LPC_USART, 9), /*!< Error happens on rxFIFO. */ + kStatus_USART_RxRingBufferOverrun = MAKE_STATUS(kStatusGroup_LPC_USART, 8), /*!< Error happens on rx ring buffer */ + kStatus_USART_NoiseError = MAKE_STATUS(kStatusGroup_LPC_USART, 10), /*!< USART noise error. */ + kStatus_USART_FramingError = MAKE_STATUS(kStatusGroup_LPC_USART, 11), /*!< USART framing error. */ + kStatus_USART_ParityError = MAKE_STATUS(kStatusGroup_LPC_USART, 12), /*!< USART parity error. */ + kStatus_USART_BaudrateNotSupport = + MAKE_STATUS(kStatusGroup_LPC_USART, 13), /*!< Baudrate is not support in current clock source */ +#if UART_RETRY_TIMES + kStatus_USART_Timeout = MAKE_STATUS(kStatusGroup_LPC_USART, 14), /*!< USART time out. */ +#endif +}; + +/*! @brief USART synchronous mode. */ +typedef enum _usart_sync_mode +{ + kUSART_SyncModeDisabled = 0x0U, /*!< Asynchronous mode. */ + kUSART_SyncModeSlave = 0x2U, /*!< Synchronous slave mode. */ + kUSART_SyncModeMaster = 0x3U, /*!< Synchronous master mode. */ +} usart_sync_mode_t; + +/*! @brief USART parity mode. */ +typedef enum _usart_parity_mode +{ + kUSART_ParityDisabled = 0x0U, /*!< Parity disabled */ + kUSART_ParityEven = 0x2U, /*!< Parity enabled, type even, bit setting: PE|PT = 10 */ + kUSART_ParityOdd = 0x3U, /*!< Parity enabled, type odd, bit setting: PE|PT = 11 */ +} usart_parity_mode_t; + +/*! @brief USART stop bit count. */ +typedef enum _usart_stop_bit_count +{ + kUSART_OneStopBit = 0U, /*!< One stop bit */ + kUSART_TwoStopBit = 1U, /*!< Two stop bits */ +} usart_stop_bit_count_t; + +/*! @brief USART data size. */ +typedef enum _usart_data_len +{ + kUSART_7BitsPerChar = 0U, /*!< Seven bit mode */ + kUSART_8BitsPerChar = 1U, /*!< Eight bit mode */ +} usart_data_len_t; + +/*! @brief USART clock polarity configuration, used in sync mode.*/ +typedef enum _usart_clock_polarity +{ + kUSART_RxSampleOnFallingEdge = 0x0U, /*!< Un_RXD is sampled on the falling edge of SCLK. */ + kUSART_RxSampleOnRisingEdge = 0x1U, /*!< Un_RXD is sampled on the rising edge of SCLK. */ +} usart_clock_polarity_t; + +/*! @brief txFIFO watermark values */ +typedef enum _usart_txfifo_watermark +{ + kUSART_TxFifo0 = 0, /*!< USART tx watermark is empty */ + kUSART_TxFifo1 = 1, /*!< USART tx watermark at 1 item */ + kUSART_TxFifo2 = 2, /*!< USART tx watermark at 2 items */ + kUSART_TxFifo3 = 3, /*!< USART tx watermark at 3 items */ + kUSART_TxFifo4 = 4, /*!< USART tx watermark at 4 items */ + kUSART_TxFifo5 = 5, /*!< USART tx watermark at 5 items */ + kUSART_TxFifo6 = 6, /*!< USART tx watermark at 6 items */ + kUSART_TxFifo7 = 7, /*!< USART tx watermark at 7 items */ +} usart_txfifo_watermark_t; + +/*! @brief rxFIFO watermark values */ +typedef enum _usart_rxfifo_watermark +{ + kUSART_RxFifo1 = 0, /*!< USART rx watermark at 1 item */ + kUSART_RxFifo2 = 1, /*!< USART rx watermark at 2 items */ + kUSART_RxFifo3 = 2, /*!< USART rx watermark at 3 items */ + kUSART_RxFifo4 = 3, /*!< USART rx watermark at 4 items */ + kUSART_RxFifo5 = 4, /*!< USART rx watermark at 5 items */ + kUSART_RxFifo6 = 5, /*!< USART rx watermark at 6 items */ + kUSART_RxFifo7 = 6, /*!< USART rx watermark at 7 items */ + kUSART_RxFifo8 = 7, /*!< USART rx watermark at 8 items */ +} usart_rxfifo_watermark_t; + +/*! + * @brief USART interrupt configuration structure, default settings all disabled. + */ +enum _usart_interrupt_enable +{ + kUSART_TxErrorInterruptEnable = (USART_FIFOINTENSET_TXERR_MASK), + kUSART_RxErrorInterruptEnable = (USART_FIFOINTENSET_RXERR_MASK), + kUSART_TxLevelInterruptEnable = (USART_FIFOINTENSET_TXLVL_MASK), + kUSART_RxLevelInterruptEnable = (USART_FIFOINTENSET_RXLVL_MASK), + kUSART_TxIdleInterruptEnable = (USART_INTENSET_TXIDLEEN_MASK << 16U), /*!< Transmitter idle. */ + kUSART_CtsChangeInterruptEnable = + (USART_INTENSET_DELTACTSEN_MASK << 16U), /*!< Change in the state of the CTS input. */ + kUSART_RxBreakChangeInterruptEnable = + (USART_INTENSET_DELTARXBRKEN_MASK), /*!< Break condition asserted or deasserted. */ + kUSART_RxStartInterruptEnable = (USART_INTENSET_STARTEN_MASK), /*!< Rx start bit detected. */ + kUSART_FramingErrorInterruptEnable = (USART_INTENSET_FRAMERREN_MASK), /*!< Framing error detected. */ + kUSART_ParityErrorInterruptEnable = (USART_INTENSET_PARITYERREN_MASK), /*!< Parity error detected. */ + kUSART_NoiseErrorInterruptEnable = (USART_INTENSET_RXNOISEEN_MASK), /*!< Noise error detected. */ + kUSART_AutoBaudErrorInterruptEnable = (USART_INTENSET_ABERREN_MASK), /*!< Auto baudrate error detected. */ + + kUSART_AllInterruptEnables = + kUSART_TxErrorInterruptEnable | kUSART_RxErrorInterruptEnable | kUSART_TxLevelInterruptEnable | + kUSART_RxLevelInterruptEnable | kUSART_TxIdleInterruptEnable | kUSART_CtsChangeInterruptEnable | + kUSART_RxBreakChangeInterruptEnable | kUSART_RxStartInterruptEnable | kUSART_FramingErrorInterruptEnable | + kUSART_ParityErrorInterruptEnable | kUSART_NoiseErrorInterruptEnable | kUSART_AutoBaudErrorInterruptEnable, +}; + +/*! + * @brief USART status flags. + * + * This provides constants for the USART status flags for use in the USART functions. + */ +enum _usart_flags +{ + kUSART_TxError = (USART_FIFOSTAT_TXERR_MASK), /*!< TEERR bit, sets if TX buffer is error */ + kUSART_RxError = (USART_FIFOSTAT_RXERR_MASK), /*!< RXERR bit, sets if RX buffer is error */ + kUSART_TxFifoEmptyFlag = (USART_FIFOSTAT_TXEMPTY_MASK), /*!< TXEMPTY bit, sets if TX buffer is empty */ + kUSART_TxFifoNotFullFlag = (USART_FIFOSTAT_TXNOTFULL_MASK), /*!< TXNOTFULL bit, sets if TX buffer is not full */ + kUSART_RxFifoNotEmptyFlag = (USART_FIFOSTAT_RXNOTEMPTY_MASK), /*!< RXNOEMPTY bit, sets if RX buffer is not empty */ + kUSART_RxFifoFullFlag = (USART_FIFOSTAT_RXFULL_MASK), /*!< RXFULL bit, sets if RX buffer is full */ + kUSART_RxIdleFlag = (USART_STAT_RXIDLE_MASK << 16U), /*!< Receiver idle. */ + kUSART_TxIdleFlag = (USART_STAT_TXIDLE_MASK << 16U), /*!< Transmitter idle. */ + kUSART_CtsAssertFlag = (USART_STAT_CTS_MASK << 16U), /*!< CTS signal high. */ + kUSART_CtsChangeFlag = (USART_STAT_DELTACTS_MASK << 16U), /*!< CTS signal changed interrupt status. */ + kUSART_BreakDetectFlag = (USART_STAT_RXBRK_MASK), /*!< Break detected. Self cleared when rx pin goes high again. */ + kUSART_BreakDetectChangeFlag = (USART_STAT_DELTARXBRK_MASK), /*!< Break detect change interrupt flag. A change in + the state of receiver break detection. */ + kUSART_RxStartFlag = (USART_STAT_START_MASK), /*!< Rx start bit detected interrupt flag. */ + kUSART_FramingErrorFlag = (USART_STAT_FRAMERRINT_MASK), /*!< Framing error interrupt flag. */ + kUSART_ParityErrorFlag = (USART_STAT_PARITYERRINT_MASK), /*!< parity error interrupt flag. */ + kUSART_NoiseErrorFlag = (USART_STAT_RXNOISEINT_MASK), /*!< Noise error interrupt flag. */ + kUSART_AutobaudErrorFlag = (USART_STAT_ABERR_MASK), /*!< Auto baudrate error interrupt flag, caused by the baudrate + counter timeout before the end of start bit. */ + + kUSART_AllClearFlags = kUSART_TxError | kUSART_RxError | kUSART_CtsChangeFlag | kUSART_BreakDetectChangeFlag | + kUSART_RxStartFlag | kUSART_FramingErrorFlag | kUSART_ParityErrorFlag | + kUSART_NoiseErrorFlag | kUSART_AutobaudErrorFlag, +}; + +/*! @brief USART configuration structure. */ +typedef struct _usart_config +{ + uint32_t baudRate_Bps; /*!< USART baud rate */ + usart_parity_mode_t parityMode; /*!< Parity mode, disabled (default), even, odd */ + usart_stop_bit_count_t stopBitCount; /*!< Number of stop bits, 1 stop bit (default) or 2 stop bits */ + usart_data_len_t bitCountPerChar; /*!< Data length - 7 bit, 8 bit */ + bool loopback; /*!< Enable peripheral loopback */ + bool enableRx; /*!< Enable RX */ + bool enableTx; /*!< Enable TX */ + bool enableContinuousSCLK; /*!< USART continuous Clock generation enable in synchronous master mode. */ + bool enableMode32k; /*!< USART uses 32 kHz clock from the RTC oscillator as the clock source. */ + bool enableHardwareFlowControl; /*!< Enable hardware control RTS/CTS */ + usart_txfifo_watermark_t txWatermark; /*!< txFIFO watermark */ + usart_rxfifo_watermark_t rxWatermark; /*!< rxFIFO watermark */ + usart_sync_mode_t syncMode; /*!< Transfer mode select - asynchronous, synchronous master, synchronous slave. */ + usart_clock_polarity_t clockPolarity; /*!< Selects the clock polarity and sampling edge in synchronous mode. */ +} usart_config_t; + +/*! @brief USART transfer structure. */ +typedef struct _usart_transfer +{ + /* + * Use separate TX and RX data pointer, because TX data is const data. + * The member data is kept for backward compatibility. + */ + union + { + uint8_t *data; /*!< The buffer of data to be transfer.*/ + uint8_t *rxData; /*!< The buffer to receive data. */ + const uint8_t *txData; /*!< The buffer of data to be sent. */ + }; + size_t dataSize; /*!< The byte count to be transfer. */ +} usart_transfer_t; + +/* Forward declaration of the handle typedef. */ +typedef struct _usart_handle usart_handle_t; + +/*! @brief USART transfer callback function. */ +typedef void (*usart_transfer_callback_t)(USART_Type *base, usart_handle_t *handle, status_t status, void *userData); + +/*! @brief USART handle structure. */ +struct _usart_handle +{ + const uint8_t *volatile txData; /*!< Address of remaining data to send. */ + volatile size_t txDataSize; /*!< Size of the remaining data to send. */ + size_t txDataSizeAll; /*!< Size of the data to send out. */ + uint8_t *volatile rxData; /*!< Address of remaining data to receive. */ + volatile size_t rxDataSize; /*!< Size of the remaining data to receive. */ + size_t rxDataSizeAll; /*!< Size of the data to receive. */ + + uint8_t *rxRingBuffer; /*!< Start address of the receiver ring buffer. */ + size_t rxRingBufferSize; /*!< Size of the ring buffer. */ + volatile uint16_t rxRingBufferHead; /*!< Index for the driver to store received data into ring buffer. */ + volatile uint16_t rxRingBufferTail; /*!< Index for the user to get data from the ring buffer. */ + + usart_transfer_callback_t callback; /*!< Callback function. */ + void *userData; /*!< USART callback function parameter.*/ + + volatile uint8_t txState; /*!< TX transfer state. */ + volatile uint8_t rxState; /*!< RX transfer state */ + + uint8_t txWatermark; /*!< txFIFO watermark */ + uint8_t rxWatermark; /*!< rxFIFO watermark */ +}; + +/*! @brief Typedef for usart interrupt handler. */ +typedef void (*flexcomm_usart_irq_handler_t)(USART_Type *base, usart_handle_t *handle); + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* _cplusplus */ + +/*! @brief Returns instance number for USART peripheral base address. */ +uint32_t USART_GetInstance(USART_Type *base); + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Initializes a USART instance with user configuration structure and peripheral clock. + * + * This function configures the USART module with the user-defined settings. The user can configure the configuration + * structure and also get the default configuration by using the USART_GetDefaultConfig() function. + * Example below shows how to use this API to configure USART. + * @code + * usart_config_t usartConfig; + * usartConfig.baudRate_Bps = 115200U; + * usartConfig.parityMode = kUSART_ParityDisabled; + * usartConfig.stopBitCount = kUSART_OneStopBit; + * USART_Init(USART1, &usartConfig, 20000000U); + * @endcode + * + * @param base USART peripheral base address. + * @param config Pointer to user-defined configuration structure. + * @param srcClock_Hz USART clock source frequency in HZ. + * @retval kStatus_USART_BaudrateNotSupport Baudrate is not support in current clock source. + * @retval kStatus_InvalidArgument USART base address is not valid + * @retval kStatus_Success Status USART initialize succeed + */ +status_t USART_Init(USART_Type *base, const usart_config_t *config, uint32_t srcClock_Hz); + +/*! + * @brief Deinitializes a USART instance. + * + * This function waits for TX complete, disables TX and RX, and disables the USART clock. + * + * @param base USART peripheral base address. + */ +void USART_Deinit(USART_Type *base); + +/*! + * @brief Gets the default configuration structure. + * + * This function initializes the USART configuration structure to a default value. The default + * values are: + * usartConfig->baudRate_Bps = 115200U; + * usartConfig->parityMode = kUSART_ParityDisabled; + * usartConfig->stopBitCount = kUSART_OneStopBit; + * usartConfig->bitCountPerChar = kUSART_8BitsPerChar; + * usartConfig->loopback = false; + * usartConfig->enableTx = false; + * usartConfig->enableRx = false; + * + * @param config Pointer to configuration structure. + */ +void USART_GetDefaultConfig(usart_config_t *config); + +/*! + * @brief Sets the USART instance baud rate. + * + * This function configures the USART module baud rate. This function is used to update + * the USART module baud rate after the USART module is initialized by the USART_Init. + * @code + * USART_SetBaudRate(USART1, 115200U, 20000000U); + * @endcode + * + * @param base USART peripheral base address. + * @param baudrate_Bps USART baudrate to be set. + * @param srcClock_Hz USART clock source frequency in HZ. + * @retval kStatus_USART_BaudrateNotSupport Baudrate is not support in current clock source. + * @retval kStatus_Success Set baudrate succeed. + * @retval kStatus_InvalidArgument One or more arguments are invalid. + */ +status_t USART_SetBaudRate(USART_Type *base, uint32_t baudrate_Bps, uint32_t srcClock_Hz); + +/*! + * @brief Enable 32 kHz mode which USART uses clock from the RTC oscillator as the clock source + * + * Please note that in order to use a 32 kHz clock to operate USART properly, the RTC oscillator + * and its 32 kHz output must be manully enabled by user, by calling RTC_Init and setting + * SYSCON_RTCOSCCTRL_EN bit to 1. + * And in 32kHz clocking mode the USART can only work at 9600 baudrate or at the baudrate that + * 9600 can evenly divide, eg: 4800, 3200. + * + * @param base USART peripheral base address. + * @param baudRate_Bps USART baudrate to be set.. + * @param enableMode32k true is 32k mode, false is normal mode. + * @param srcClock_Hz USART clock source frequency in HZ. + * @retval kStatus_USART_BaudrateNotSupport Baudrate is not support in current clock source. + * @retval kStatus_Success Set baudrate succeed. + * @retval kStatus_InvalidArgument One or more arguments are invalid. + */ +status_t USART_Enable32kMode(USART_Type *base, uint32_t baudRate_Bps, bool enableMode32k, uint32_t srcClock_Hz); + +/*! + * @brief Enable 9-bit data mode for USART. + * + * This function set the 9-bit mode for USART module. The 9th bit is not used for parity thus can be modified by user. + * + * @param base USART peripheral base address. + * @param enable true to enable, false to disable. + */ +void USART_Enable9bitMode(USART_Type *base, bool enable); + +/*! + * @brief Set the USART slave address. + * + * This function configures the address for USART module that works as slave in 9-bit data mode. When the address + * detection is enabled, the frame it receices with MSB being 1 is considered as an address frame, otherwise it is + * considered as data frame. Once the address frame matches slave's own addresses, this slave is addressed. This + * address frame and its following data frames are stored in the receive buffer, otherwise the frames will be discarded. + * To un-address a slave, just send an address frame with unmatched address. + * + * @note Any USART instance joined in the multi-slave system can work as slave. The position of the address mark is the + * same as the parity bit when parity is enabled for 8 bit and 9 bit data formats. + * + * @param base USART peripheral base address. + * @param address USART slave address. + */ +static inline void USART_SetMatchAddress(USART_Type *base, uint8_t address) +{ + /* Configure match address. */ + base->ADDR = (uint32_t)address; +} + +/*! + * @brief Enable the USART match address feature. + * + * @param base USART peripheral base address. + * @param match true to enable match address, false to disable. + */ +static inline void USART_EnableMatchAddress(USART_Type *base, bool match) +{ + /* Configure match address enable bit. */ + if (match) + { + base->CFG |= (uint32_t)USART_CFG_AUTOADDR_MASK; + base->CTL |= (uint32_t)USART_CTL_ADDRDET_MASK; + } + else + { + base->CFG &= ~(uint32_t)USART_CFG_AUTOADDR_MASK; + base->CTL &= ~(uint32_t)USART_CTL_ADDRDET_MASK; + } +} + +/* @} */ + +/*! + * @name Status + * @{ + */ + +/*! + * @brief Get USART status flags. + * + * This function get all USART status flags, the flags are returned as the logical + * OR value of the enumerators @ref _usart_flags. To check a specific status, + * compare the return value with enumerators in @ref _usart_flags. + * For example, to check whether the TX is empty: + * @code + * if (kUSART_TxFifoNotFullFlag & USART_GetStatusFlags(USART1)) + * { + * ... + * } + * @endcode + * + * @param base USART peripheral base address. + * @return USART status flags which are ORed by the enumerators in the _usart_flags. + */ +static inline uint32_t USART_GetStatusFlags(USART_Type *base) +{ + return (base->FIFOSTAT & 0xFFUL) | (base->STAT & 0xFFUL) << 16U | (base->STAT & 0xFFFF00UL); +} + +/*! + * @brief Clear USART status flags. + * + * This function clear supported USART status flags + * Flags that can be cleared or set are: + * kUSART_TxError + * kUSART_RxError + * For example: + * @code + * USART_ClearStatusFlags(USART1, kUSART_TxError | kUSART_RxError) + * @endcode + * + * @param base USART peripheral base address. + * @param mask status flags to be cleared. + */ +static inline void USART_ClearStatusFlags(USART_Type *base, uint32_t mask) +{ + mask &= (uint32_t)kUSART_AllClearFlags; + /* Clear the clearable status in STAT register. */ + base->STAT = (mask & 0xFFFF00UL) | ((mask & 0xFF0000UL) >> 16U); + /* Only TXERR, RXERR fields support write. Remaining fields should be set to zero */ + base->FIFOSTAT = mask & (USART_FIFOSTAT_TXERR_MASK | USART_FIFOSTAT_RXERR_MASK); +} + +/* @} */ + +/*! + * @name Interrupts + * @{ + */ +/*! + * @brief Enables USART interrupts according to the provided mask. + * + * This function enables the USART interrupts according to the provided mask. The mask + * is a logical OR of enumeration members. See @ref _usart_interrupt_enable. + * For example, to enable TX empty interrupt and RX full interrupt: + * @code + * USART_EnableInterrupts(USART1, kUSART_TxLevelInterruptEnable | kUSART_RxLevelInterruptEnable); + * @endcode + * + * @param base USART peripheral base address. + * @param mask The interrupts to enable. Logical OR of @ref _usart_interrupt_enable. + */ +static inline void USART_EnableInterrupts(USART_Type *base, uint32_t mask) +{ + mask &= (uint32_t)kUSART_AllInterruptEnables; + base->INTENSET = (mask & 0x1FF00UL) | ((mask & 0xFF0000UL) >> 16U); + base->FIFOINTENSET = mask & 0xFUL; +} + +/*! + * @brief Disables USART interrupts according to a provided mask. + * + * This function disables the USART interrupts according to a provided mask. The mask + * is a logical OR of enumeration members. See @ref _usart_interrupt_enable. + * This example shows how to disable the TX empty interrupt and RX full interrupt: + * @code + * USART_DisableInterrupts(USART1, kUSART_TxLevelInterruptEnable | kUSART_RxLevelInterruptEnable); + * @endcode + * + * @param base USART peripheral base address. + * @param mask The interrupts to disable. Logical OR of @ref _usart_interrupt_enable. + */ +static inline void USART_DisableInterrupts(USART_Type *base, uint32_t mask) +{ + mask &= (uint32_t)kUSART_AllInterruptEnables; + base->INTENCLR = (mask & 0x1FF00UL) | ((mask & 0xFF0000UL) >> 16U); + base->FIFOINTENCLR = mask & 0xFUL; +} + +/*! + * @brief Returns enabled USART interrupts. + * + * This function returns the enabled USART interrupts. + * + * @param base USART peripheral base address. + */ +static inline uint32_t USART_GetEnabledInterrupts(USART_Type *base) +{ + return (base->INTENSET & 0x1FF00UL) | ((base->INTENSET & 0xFFUL) << 16UL) | (base->FIFOINTENSET & 0xFUL); +} + +/*! + * @brief Enable DMA for Tx + */ +static inline void USART_EnableTxDMA(USART_Type *base, bool enable) +{ + if (enable) + { + base->FIFOCFG |= USART_FIFOCFG_DMATX_MASK; + } + else + { + base->FIFOCFG &= ~(USART_FIFOCFG_DMATX_MASK); + } +} + +/*! + * @brief Enable DMA for Rx + */ +static inline void USART_EnableRxDMA(USART_Type *base, bool enable) +{ + if (enable) + { + base->FIFOCFG |= USART_FIFOCFG_DMARX_MASK; + } + else + { + base->FIFOCFG &= ~(USART_FIFOCFG_DMARX_MASK); + } +} + +/*! + * @brief Enable CTS. + * This function will determine whether CTS is used for flow control. + * + * @param base USART peripheral base address. + * @param enable Enable CTS or not, true for enable and false for disable. + */ +static inline void USART_EnableCTS(USART_Type *base, bool enable) +{ + if (enable) + { + base->CFG |= USART_CFG_CTSEN_MASK; + } + else + { + base->CFG &= ~USART_CFG_CTSEN_MASK; + } +} + +/*! + * @brief Continuous Clock generation. + * By default, SCLK is only output while data is being transmitted in synchronous mode. + * Enable this funciton, SCLK will run continuously in synchronous mode, allowing + * characters to be received on Un_RxD independently from transmission on Un_TXD). + * + * @param base USART peripheral base address. + * @param enable Enable Continuous Clock generation mode or not, true for enable and false for disable. + */ +static inline void USART_EnableContinuousSCLK(USART_Type *base, bool enable) +{ + if (enable) + { + base->CTL |= USART_CTL_CC_MASK; + } + else + { + base->CTL &= ~USART_CTL_CC_MASK; + } +} + +/*! + * @brief Enable Continuous Clock generation bit auto clear. + * While enable this cuntion, the Continuous Clock bit is automatically cleared when a complete + * character has been received. This bit is cleared at the same time. + * + * @param base USART peripheral base address. + * @param enable Enable auto clear or not, true for enable and false for disable. + */ +static inline void USART_EnableAutoClearSCLK(USART_Type *base, bool enable) +{ + if (enable) + { + base->CTL |= USART_CTL_CLRCCONRX_MASK; + } + else + { + base->CTL &= ~USART_CTL_CLRCCONRX_MASK; + } +} + +/*! + * @brief Sets the rx FIFO watermark. + * + * @param base USART peripheral base address. + * @param water Rx FIFO watermark. + */ +static inline void USART_SetRxFifoWatermark(USART_Type *base, uint8_t water) +{ + assert(water <= (USART_FIFOTRIG_RXLVL_MASK >> USART_FIFOTRIG_RXLVL_SHIFT)); + base->FIFOTRIG = (base->FIFOTRIG & ~USART_FIFOTRIG_RXLVL_MASK) | USART_FIFOTRIG_RXLVL(water); +} + +/*! + * @brief Sets the tx FIFO watermark. + * + * @param base USART peripheral base address. + * @param water Tx FIFO watermark. + */ +static inline void USART_SetTxFifoWatermark(USART_Type *base, uint8_t water) +{ + assert(water <= (USART_FIFOTRIG_TXLVL_MASK >> USART_FIFOTRIG_TXLVL_SHIFT)); + base->FIFOTRIG = (base->FIFOTRIG & ~USART_FIFOTRIG_TXLVL_MASK) | USART_FIFOTRIG_TXLVL(water); +} +/* @} */ + +/*! + * @name Bus Operations + * @{ + */ + +/*! + * @brief Writes to the FIFOWR register. + * + * This function writes data to the txFIFO directly. The upper layer must ensure + * that txFIFO has space for data to write before calling this function. + * + * @param base USART peripheral base address. + * @param data The byte to write. + */ +static inline void USART_WriteByte(USART_Type *base, uint8_t data) +{ + base->FIFOWR = data; +} + +/*! + * @brief Reads the FIFORD register directly. + * + * This function reads data from the rxFIFO directly. The upper layer must + * ensure that the rxFIFO is not empty before calling this function. + * + * @param base USART peripheral base address. + * @return The byte read from USART data register. + */ +static inline uint8_t USART_ReadByte(USART_Type *base) +{ + return (uint8_t)base->FIFORD; +} + +/*! + * @brief Gets the rx FIFO data count. + * + * @param base USART peripheral base address. + * @return rx FIFO data count. + */ +static inline uint8_t USART_GetRxFifoCount(USART_Type *base) +{ + return (uint8_t)((base->FIFOSTAT & USART_FIFOSTAT_RXLVL_MASK) >> USART_FIFOSTAT_RXLVL_SHIFT); +} + +/*! + * @brief Gets the tx FIFO data count. + * + * @param base USART peripheral base address. + * @return tx FIFO data count. + */ +static inline uint8_t USART_GetTxFifoCount(USART_Type *base) +{ + return (uint8_t)((base->FIFOSTAT & USART_FIFOSTAT_TXLVL_MASK) >> USART_FIFOSTAT_TXLVL_SHIFT); +} + +/*! + * @brief Transmit an address frame in 9-bit data mode. + * + * @param base USART peripheral base address. + * @param address USART slave address. + */ +void USART_SendAddress(USART_Type *base, uint8_t address); + +/*! + * @brief Writes to the TX register using a blocking method. + * + * This function polls the TX register, waits for the TX register to be empty or for the TX FIFO + * to have room and writes data to the TX buffer. + * + * @param base USART peripheral base address. + * @param data Start address of the data to write. + * @param length Size of the data to write. + * @retval kStatus_USART_Timeout Transmission timed out and was aborted. + * @retval kStatus_InvalidArgument Invalid argument. + * @retval kStatus_Success Successfully wrote all data. + */ +status_t USART_WriteBlocking(USART_Type *base, const uint8_t *data, size_t length); + +/*! + * @brief Read RX data register using a blocking method. + * + * This function polls the RX register, waits for the RX register to be full or for RX FIFO to + * have data and read data from the TX register. + * + * @param base USART peripheral base address. + * @param data Start address of the buffer to store the received data. + * @param length Size of the buffer. + * @retval kStatus_USART_FramingError Receiver overrun happened while receiving data. + * @retval kStatus_USART_ParityError Noise error happened while receiving data. + * @retval kStatus_USART_NoiseError Framing error happened while receiving data. + * @retval kStatus_USART_RxError Overflow or underflow rxFIFO happened. + * @retval kStatus_USART_Timeout Transmission timed out and was aborted. + * @retval kStatus_Success Successfully received all data. + */ +status_t USART_ReadBlocking(USART_Type *base, uint8_t *data, size_t length); + +/* @} */ + +/*! + * @name Transactional + * @{ + */ + +/*! + * @brief Initializes the USART handle. + * + * This function initializes the USART handle which can be used for other USART + * transactional APIs. Usually, for a specified USART instance, + * call this API once to get the initialized handle. + * + * @param base USART peripheral base address. + * @param handle USART handle pointer. + * @param callback The callback function. + * @param userData The parameter of the callback function. + */ +status_t USART_TransferCreateHandle(USART_Type *base, + usart_handle_t *handle, + usart_transfer_callback_t callback, + void *userData); + +/*! + * @brief Transmits a buffer of data using the interrupt method. + * + * This function sends data using an interrupt method. This is a non-blocking function, which + * returns directly without waiting for all data to be written to the TX register. When + * all data is written to the TX register in the IRQ handler, the USART driver calls the callback + * function and passes the @ref kStatus_USART_TxIdle as status parameter. + * + * @param base USART peripheral base address. + * @param handle USART handle pointer. + * @param xfer USART transfer structure. See #usart_transfer_t. + * @retval kStatus_Success Successfully start the data transmission. + * @retval kStatus_USART_TxBusy Previous transmission still not finished, data not all written to TX register yet. + * @retval kStatus_InvalidArgument Invalid argument. + */ +status_t USART_TransferSendNonBlocking(USART_Type *base, usart_handle_t *handle, usart_transfer_t *xfer); + +/*! + * @brief Sets up the RX ring buffer. + * + * This function sets up the RX ring buffer to a specific USART handle. + * + * When the RX ring buffer is used, data received are stored into the ring buffer even when the + * user doesn't call the USART_TransferReceiveNonBlocking() API. If there is already data received + * in the ring buffer, the user can get the received data from the ring buffer directly. + * + * @note When using the RX ring buffer, one byte is reserved for internal use. In other + * words, if @p ringBufferSize is 32, then only 31 bytes are used for saving data. + * + * @param base USART peripheral base address. + * @param handle USART handle pointer. + * @param ringBuffer Start address of the ring buffer for background receiving. Pass NULL to disable the ring buffer. + * @param ringBufferSize size of the ring buffer. + */ +void USART_TransferStartRingBuffer(USART_Type *base, + usart_handle_t *handle, + uint8_t *ringBuffer, + size_t ringBufferSize); + +/*! + * @brief Aborts the background transfer and uninstalls the ring buffer. + * + * This function aborts the background transfer and uninstalls the ring buffer. + * + * @param base USART peripheral base address. + * @param handle USART handle pointer. + */ +void USART_TransferStopRingBuffer(USART_Type *base, usart_handle_t *handle); + +/*! + * @brief Get the length of received data in RX ring buffer. + * + * @param handle USART handle pointer. + * @return Length of received data in RX ring buffer. + */ +size_t USART_TransferGetRxRingBufferLength(usart_handle_t *handle); + +/*! + * @brief Aborts the interrupt-driven data transmit. + * + * This function aborts the interrupt driven data sending. The user can get the remainBtyes to find out + * how many bytes are still not sent out. + * + * @param base USART peripheral base address. + * @param handle USART handle pointer. + */ +void USART_TransferAbortSend(USART_Type *base, usart_handle_t *handle); + +/*! + * @brief Get the number of bytes that have been sent out to bus. + * + * This function gets the number of bytes that have been sent out to bus by interrupt method. + * + * @param base USART peripheral base address. + * @param handle USART handle pointer. + * @param count Send bytes count. + * @retval kStatus_NoTransferInProgress No send in progress. + * @retval kStatus_InvalidArgument Parameter is invalid. + * @retval kStatus_Success Get successfully through the parameter \p count; + */ +status_t USART_TransferGetSendCount(USART_Type *base, usart_handle_t *handle, uint32_t *count); + +/*! + * @brief Receives a buffer of data using an interrupt method. + * + * This function receives data using an interrupt method. This is a non-blocking function, which + * returns without waiting for all data to be received. + * If the RX ring buffer is used and not empty, the data in the ring buffer is copied and + * the parameter @p receivedBytes shows how many bytes are copied from the ring buffer. + * After copying, if the data in the ring buffer is not enough to read, the receive + * request is saved by the USART driver. When the new data arrives, the receive request + * is serviced first. When all data is received, the USART driver notifies the upper layer + * through a callback function and passes the status parameter @ref kStatus_USART_RxIdle. + * For example, the upper layer needs 10 bytes but there are only 5 bytes in the ring buffer. + * The 5 bytes are copied to the xfer->data and this function returns with the + * parameter @p receivedBytes set to 5. For the left 5 bytes, newly arrived data is + * saved from the xfer->data[5]. When 5 bytes are received, the USART driver notifies the upper layer. + * If the RX ring buffer is not enabled, this function enables the RX and RX interrupt + * to receive data to the xfer->data. When all data is received, the upper layer is notified. + * + * @param base USART peripheral base address. + * @param handle USART handle pointer. + * @param xfer USART transfer structure, see #usart_transfer_t. + * @param receivedBytes Bytes received from the ring buffer directly. + * @retval kStatus_Success Successfully queue the transfer into transmit queue. + * @retval kStatus_USART_RxBusy Previous receive request is not finished. + * @retval kStatus_InvalidArgument Invalid argument. + */ +status_t USART_TransferReceiveNonBlocking(USART_Type *base, + usart_handle_t *handle, + usart_transfer_t *xfer, + size_t *receivedBytes); + +/*! + * @brief Aborts the interrupt-driven data receiving. + * + * This function aborts the interrupt-driven data receiving. The user can get the remainBytes to find out + * how many bytes not received yet. + * + * @param base USART peripheral base address. + * @param handle USART handle pointer. + */ +void USART_TransferAbortReceive(USART_Type *base, usart_handle_t *handle); + +/*! + * @brief Get the number of bytes that have been received. + * + * This function gets the number of bytes that have been received. + * + * @param base USART peripheral base address. + * @param handle USART handle pointer. + * @param count Receive bytes count. + * @retval kStatus_NoTransferInProgress No receive in progress. + * @retval kStatus_InvalidArgument Parameter is invalid. + * @retval kStatus_Success Get successfully through the parameter \p count; + */ +status_t USART_TransferGetReceiveCount(USART_Type *base, usart_handle_t *handle, uint32_t *count); + +/*! + * @brief USART IRQ handle function. + * + * This function handles the USART transmit and receive IRQ request. + * + * @param base USART peripheral base address. + * @param handle USART handle pointer. + */ +void USART_TransferHandleIRQ(USART_Type *base, usart_handle_t *handle); + +/* @} */ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_USART_H_ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_usart_dma.c b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_usart_dma.c new file mode 100644 index 0000000000..60c2d5284c --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_usart_dma.c @@ -0,0 +1,392 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_usart.h" +#include "fsl_device_registers.h" +#include "fsl_dma.h" +#include "fsl_flexcomm.h" +#include "fsl_usart_dma.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.flexcomm_usart_dma" +#endif + +/******************************************************************************* + * Definitions + ******************************************************************************/ +enum +{ + kUSART_TxIdle, /* TX idle. */ + kUSART_TxBusy, /* TX busy. */ + kUSART_RxIdle, /* RX idle. */ + kUSART_RxBusy /* RX busy. */ +}; + +/*! @brief Typedef for usart DMA interrupt handler. */ +typedef void (*flexcomm_usart_dma_irq_handler_t)(USART_Type *base, usart_dma_handle_t *handle); + +/*base, false); + + /* Enable tx idle interrupt */ + usartPrivateHandle->base->INTENSET = USART_INTENSET_TXIDLEEN_MASK; +} + +static void USART_TransferReceiveDMACallback(dma_handle_t *handle, void *param, bool transferDone, uint32_t intmode) +{ + assert(handle != NULL); + assert(param != NULL); + + usart_dma_private_handle_t *usartPrivateHandle = (usart_dma_private_handle_t *)param; + + /* Disable UART RX DMA. */ + USART_EnableRxDMA(usartPrivateHandle->base, false); + + usartPrivateHandle->handle->rxState = (uint8_t)kUSART_RxIdle; + + if (usartPrivateHandle->handle->callback != NULL) + { + usartPrivateHandle->handle->callback(usartPrivateHandle->base, usartPrivateHandle->handle, kStatus_USART_RxIdle, + usartPrivateHandle->handle->userData); + } +} + +/*! + * brief Initializes the USART handle which is used in transactional functions. + * param base USART peripheral base address. + * param handle Pointer to usart_dma_handle_t structure. + * param callback Callback function. + * param userData User data. + * param txDmaHandle User-requested DMA handle for TX DMA transfer. + * param rxDmaHandle User-requested DMA handle for RX DMA transfer. + */ +status_t USART_TransferCreateHandleDMA(USART_Type *base, + usart_dma_handle_t *handle, + usart_dma_transfer_callback_t callback, + void *userData, + dma_handle_t *txDmaHandle, + dma_handle_t *rxDmaHandle) +{ + uint32_t instance = 0; + + /* check 'base' */ + assert(!(NULL == base)); + if (NULL == base) + { + return kStatus_InvalidArgument; + } + /* check 'handle' */ + assert(!(NULL == handle)); + if (NULL == handle) + { + return kStatus_InvalidArgument; + } + + instance = USART_GetInstance(base); + + (void)memset(handle, 0, sizeof(*handle)); + /* assign 'base' and 'handle' */ + s_dmaPrivateHandle[instance].base = base; + s_dmaPrivateHandle[instance].handle = handle; + + /* set tx/rx 'idle' state */ + handle->rxState = (uint8_t)kUSART_RxIdle; + handle->txState = (uint8_t)kUSART_TxIdle; + + handle->callback = callback; + handle->userData = userData; + + handle->rxDmaHandle = rxDmaHandle; + handle->txDmaHandle = txDmaHandle; + + /* Set USART_TransferDMAHandleIRQ as DMA IRQ handler */ + usart_dma_to_flexcomm_t handler; + handler.usart_dma_handler = USART_TransferDMAHandleIRQ; + FLEXCOMM_SetIRQHandler(base, handler.flexcomm_handler, handle); + /* Enable NVIC IRQ. */ + (void)EnableIRQ(s_usartIRQ[instance]); + + /* Configure TX. */ + if (txDmaHandle != NULL) + { + DMA_SetCallback(txDmaHandle, USART_TransferSendDMACallback, &s_dmaPrivateHandle[instance]); + } + + /* Configure RX. */ + if (rxDmaHandle != NULL) + { + DMA_SetCallback(rxDmaHandle, USART_TransferReceiveDMACallback, &s_dmaPrivateHandle[instance]); + } + + return kStatus_Success; +} + +/*! + * brief Sends data using DMA. + * + * This function sends data using DMA. This is a non-blocking function, which returns + * right away. When all data is sent, the send callback function is called. + * + * param base USART peripheral base address. + * param handle USART handle pointer. + * param xfer USART DMA transfer structure. See #usart_transfer_t. + * retval kStatus_Success if succeed, others failed. + * retval kStatus_USART_TxBusy Previous transfer on going. + * retval kStatus_InvalidArgument Invalid argument. + */ +status_t USART_TransferSendDMA(USART_Type *base, usart_dma_handle_t *handle, usart_transfer_t *xfer) +{ + assert(handle != NULL); + assert(handle->txDmaHandle != NULL); + assert(xfer != NULL); + assert(xfer->data != NULL); + assert(xfer->dataSize != 0U); + + dma_transfer_config_t xferConfig; + status_t status; + uint32_t address = (uint32_t)&base->FIFOWR; + + /* If previous TX not finished. */ + if ((uint8_t)kUSART_TxBusy == handle->txState) + { + status = kStatus_USART_TxBusy; + } + else + { + handle->txState = (uint8_t)kUSART_TxBusy; + handle->txDataSizeAll = xfer->dataSize; + + /* Enable DMA request from txFIFO */ + USART_EnableTxDMA(base, true); + + /* Prepare transfer. */ + DMA_PrepareTransfer(&xferConfig, xfer->data, (uint32_t *)address, sizeof(uint8_t), xfer->dataSize, + kDMA_MemoryToPeripheral, NULL); + + /* Submit transfer. */ + (void)DMA_SubmitTransfer(handle->txDmaHandle, &xferConfig); + DMA_StartTransfer(handle->txDmaHandle); + + status = kStatus_Success; + } + + return status; +} + +/*! + * brief Receives data using DMA. + * + * This function receives data using DMA. This is a non-blocking function, which returns + * right away. When all data is received, the receive callback function is called. + * + * param base USART peripheral base address. + * param handle Pointer to usart_dma_handle_t structure. + * param xfer USART DMA transfer structure. See #usart_transfer_t. + * retval kStatus_Success if succeed, others failed. + * retval kStatus_USART_RxBusy Previous transfer on going. + * retval kStatus_InvalidArgument Invalid argument. + */ +status_t USART_TransferReceiveDMA(USART_Type *base, usart_dma_handle_t *handle, usart_transfer_t *xfer) +{ + assert(handle != NULL); + assert(handle->rxDmaHandle != NULL); + assert(xfer != NULL); + assert(xfer->data != NULL); + assert(xfer->dataSize != 0U); + + dma_transfer_config_t xferConfig; + status_t status; + uint32_t address = (uint32_t)&base->FIFORD; + + /* If previous RX not finished. */ + if ((uint8_t)kUSART_RxBusy == handle->rxState) + { + status = kStatus_USART_RxBusy; + } + else + { + handle->rxState = (uint8_t)kUSART_RxBusy; + handle->rxDataSizeAll = xfer->dataSize; + + /* Enable DMA request from rxFIFO */ + USART_EnableRxDMA(base, true); + + /* Prepare transfer. */ + DMA_PrepareTransfer(&xferConfig, (uint32_t *)address, xfer->data, sizeof(uint8_t), xfer->dataSize, + kDMA_PeripheralToMemory, NULL); + + /* Submit transfer. */ + (void)DMA_SubmitTransfer(handle->rxDmaHandle, &xferConfig); + DMA_StartTransfer(handle->rxDmaHandle); + + status = kStatus_Success; + } + + return status; +} + +/*! + * brief Aborts the sent data using DMA. + * + * This function aborts send data using DMA. + * + * param base USART peripheral base address + * param handle Pointer to usart_dma_handle_t structure + */ +void USART_TransferAbortSendDMA(USART_Type *base, usart_dma_handle_t *handle) +{ + assert(NULL != handle); + assert(NULL != handle->txDmaHandle); + + /* Stop transfer. */ + DMA_AbortTransfer(handle->txDmaHandle); + handle->txState = (uint8_t)kUSART_TxIdle; +} + +/*! + * brief Aborts the received data using DMA. + * + * This function aborts the received data using DMA. + * + * param base USART peripheral base address + * param handle Pointer to usart_dma_handle_t structure + */ +void USART_TransferAbortReceiveDMA(USART_Type *base, usart_dma_handle_t *handle) +{ + assert(NULL != handle); + assert(NULL != handle->rxDmaHandle); + + /* Stop transfer. */ + DMA_AbortTransfer(handle->rxDmaHandle); + handle->rxState = (uint8_t)kUSART_RxIdle; +} + +/*! + * brief Get the number of bytes that have been received. + * + * This function gets the number of bytes that have been received. + * + * param base USART peripheral base address. + * param handle USART handle pointer. + * param count Receive bytes count. + * retval kStatus_NoTransferInProgress No receive in progress. + * retval kStatus_InvalidArgument Parameter is invalid. + * retval kStatus_Success Get successfully through the parameter \p count; + */ +status_t USART_TransferGetReceiveCountDMA(USART_Type *base, usart_dma_handle_t *handle, uint32_t *count) +{ + assert(NULL != handle); + assert(NULL != handle->rxDmaHandle); + assert(NULL != count); + + if ((uint8_t)kUSART_RxIdle == handle->rxState) + { + return kStatus_NoTransferInProgress; + } + + *count = handle->rxDataSizeAll - DMA_GetRemainingBytes(handle->rxDmaHandle->base, handle->rxDmaHandle->channel); + + return kStatus_Success; +} + +/*! + * brief Get the number of bytes that have been sent. + * + * This function gets the number of bytes that have been sent. + * + * param base USART peripheral base address. + * param handle USART handle pointer. + * param count Sent bytes count. + * retval kStatus_NoTransferInProgress No receive in progress. + * retval kStatus_InvalidArgument Parameter is invalid. + * retval kStatus_Success Get successfully through the parameter \p count; + */ +status_t USART_TransferGetSendCountDMA(USART_Type *base, usart_dma_handle_t *handle, uint32_t *count) +{ + assert(NULL != handle); + assert(NULL != handle->txDmaHandle); + assert(NULL != count); + + if ((uint8_t)kUSART_TxIdle == handle->txState) + { + return kStatus_NoTransferInProgress; + } + + *count = handle->txDataSizeAll - DMA_GetRemainingBytes(handle->txDmaHandle->base, handle->txDmaHandle->channel); + + return kStatus_Success; +} + +void USART_TransferDMAHandleIRQ(USART_Type *base, usart_dma_handle_t *handle) +{ + /* Check arguments */ + assert((NULL != base) && (NULL != handle)); + + /* Tx idle interrupt happens means that all the tx data have been sent out to bus, set the tx state to idle */ + handle->txState = (uint8_t)kUSART_TxIdle; + + /* Disable tx idle interrupt */ + base->INTENCLR = USART_INTENCLR_TXIDLECLR_MASK; + + /* Invoke callback */ + if (handle->callback != NULL) + { + handle->callback(base, handle, kStatus_USART_TxIdle, handle->userData); + } +} diff --git a/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_usart_dma.h b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_usart_dma.h new file mode 100644 index 0000000000..2166803b5f --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_usart_dma.h @@ -0,0 +1,175 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_USART_DMA_H_ +#define _FSL_USART_DMA_H_ + +#include "fsl_common.h" +#include "fsl_dma.h" +#include "fsl_usart.h" + +/*! + * @addtogroup usart_dma_driver + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief USART dma driver version. */ +#define FSL_USART_DMA_DRIVER_VERSION (MAKE_VERSION(2, 6, 0)) +/*@}*/ + +/* Forward declaration of the handle typedef. */ +typedef struct _usart_dma_handle usart_dma_handle_t; + +/*! @brief UART transfer callback function. */ +typedef void (*usart_dma_transfer_callback_t)(USART_Type *base, + usart_dma_handle_t *handle, + status_t status, + void *userData); + +/*! + * @brief UART DMA handle + */ +struct _usart_dma_handle +{ + USART_Type *base; /*!< UART peripheral base address. */ + + usart_dma_transfer_callback_t callback; /*!< Callback function. */ + void *userData; /*!< UART callback function parameter.*/ + size_t rxDataSizeAll; /*!< Size of the data to receive. */ + size_t txDataSizeAll; /*!< Size of the data to send out. */ + + dma_handle_t *txDmaHandle; /*!< The DMA TX channel used. */ + dma_handle_t *rxDmaHandle; /*!< The DMA RX channel used. */ + + volatile uint8_t txState; /*!< TX transfer state. */ + volatile uint8_t rxState; /*!< RX transfer state */ +}; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* _cplusplus */ + +/*! + * @name DMA transactional + * @{ + */ + +/*! + * @brief Initializes the USART handle which is used in transactional functions. + * @param base USART peripheral base address. + * @param handle Pointer to usart_dma_handle_t structure. + * @param callback Callback function. + * @param userData User data. + * @param txDmaHandle User-requested DMA handle for TX DMA transfer. + * @param rxDmaHandle User-requested DMA handle for RX DMA transfer. + */ +status_t USART_TransferCreateHandleDMA(USART_Type *base, + usart_dma_handle_t *handle, + usart_dma_transfer_callback_t callback, + void *userData, + dma_handle_t *txDmaHandle, + dma_handle_t *rxDmaHandle); + +/*! + * @brief Sends data using DMA. + * + * This function sends data using DMA. This is a non-blocking function, which returns + * right away. When all data is sent, the send callback function is called. + * + * @param base USART peripheral base address. + * @param handle USART handle pointer. + * @param xfer USART DMA transfer structure. See #usart_transfer_t. + * @retval kStatus_Success if succeed, others failed. + * @retval kStatus_USART_TxBusy Previous transfer on going. + * @retval kStatus_InvalidArgument Invalid argument. + */ +status_t USART_TransferSendDMA(USART_Type *base, usart_dma_handle_t *handle, usart_transfer_t *xfer); + +/*! + * @brief Receives data using DMA. + * + * This function receives data using DMA. This is a non-blocking function, which returns + * right away. When all data is received, the receive callback function is called. + * + * @param base USART peripheral base address. + * @param handle Pointer to usart_dma_handle_t structure. + * @param xfer USART DMA transfer structure. See #usart_transfer_t. + * @retval kStatus_Success if succeed, others failed. + * @retval kStatus_USART_RxBusy Previous transfer on going. + * @retval kStatus_InvalidArgument Invalid argument. + */ +status_t USART_TransferReceiveDMA(USART_Type *base, usart_dma_handle_t *handle, usart_transfer_t *xfer); + +/*! + * @brief Aborts the sent data using DMA. + * + * This function aborts send data using DMA. + * + * @param base USART peripheral base address + * @param handle Pointer to usart_dma_handle_t structure + */ +void USART_TransferAbortSendDMA(USART_Type *base, usart_dma_handle_t *handle); + +/*! + * @brief Aborts the received data using DMA. + * + * This function aborts the received data using DMA. + * + * @param base USART peripheral base address + * @param handle Pointer to usart_dma_handle_t structure + */ +void USART_TransferAbortReceiveDMA(USART_Type *base, usart_dma_handle_t *handle); + +/*! + * @brief Get the number of bytes that have been received. + * + * This function gets the number of bytes that have been received. + * + * @param base USART peripheral base address. + * @param handle USART handle pointer. + * @param count Receive bytes count. + * @retval kStatus_NoTransferInProgress No receive in progress. + * @retval kStatus_InvalidArgument Parameter is invalid. + * @retval kStatus_Success Get successfully through the parameter \p count; + */ +status_t USART_TransferGetReceiveCountDMA(USART_Type *base, usart_dma_handle_t *handle, uint32_t *count); + +/*! + * @brief Get the number of bytes that have been sent. + * + * This function gets the number of bytes that have been sent. + * + * @param base USART peripheral base address. + * @param handle USART handle pointer. + * @param count Sent bytes count. + * @retval kStatus_NoTransferInProgress No receive in progress. + * @retval kStatus_InvalidArgument Parameter is invalid. + * @retval kStatus_Success Get successfully through the parameter \p count; + */ +status_t USART_TransferGetSendCountDMA(USART_Type *base, usart_dma_handle_t *handle, uint32_t *count); + +/* @} */ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_USART_DMA_H_ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_utick.c b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_utick.c new file mode 100644 index 0000000000..0eea419cd3 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_utick.c @@ -0,0 +1,230 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2019, 2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_utick.h" +#if !(defined(FSL_FEATURE_UTICK_HAS_NO_PDCFG) && FSL_FEATURE_UTICK_HAS_NO_PDCFG) +#include "fsl_power.h" +#endif +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.utick" +#endif + +/* Typedef for interrupt handler. */ +typedef void (*utick_isr_t)(UTICK_Type *base, utick_callback_t cb); + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Gets the instance from the base address + * + * @param base UTICK peripheral base address + * + * @return The UTICK instance + */ +static uint32_t UTICK_GetInstance(UTICK_Type *base); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/* Array of UTICK handle. */ +static utick_callback_t s_utickHandle[FSL_FEATURE_SOC_UTICK_COUNT]; +/* Array of UTICK peripheral base address. */ +static UTICK_Type *const s_utickBases[] = UTICK_BASE_PTRS; +/* Array of UTICK IRQ number. */ +static const IRQn_Type s_utickIRQ[] = UTICK_IRQS; +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/* Array of UTICK clock name. */ +static const clock_ip_name_t s_utickClock[] = UTICK_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if !(defined(FSL_FEATURE_UTICK_HAS_NO_RESET) && FSL_FEATURE_UTICK_HAS_NO_RESET) +/*! @brief Pointers to UTICK resets for each instance. */ +static const reset_ip_name_t s_utickResets[] = UTICK_RSTS; +#endif + +/* UTICK ISR for transactional APIs. */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +static utick_isr_t s_utickIsr = (utick_isr_t)DefaultISR; +#else +static utick_isr_t s_utickIsr; +#endif + +/******************************************************************************* + * Code + ******************************************************************************/ +static uint32_t UTICK_GetInstance(UTICK_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_utickBases); instance++) + { + if (s_utickBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_utickBases)); + + return instance; +} + +/*! + * brief Starts UTICK. + * + * This function starts a repeat/onetime countdown with an optional callback + * + * param base UTICK peripheral base address. + * param mode UTICK timer mode (ie kUTICK_onetime or kUTICK_repeat) + * param count UTICK timer mode (ie kUTICK_onetime or kUTICK_repeat) + * param cb UTICK callback (can be left as NULL if none, otherwise should be a void func(void)) + * return none + */ +void UTICK_SetTick(UTICK_Type *base, utick_mode_t mode, uint32_t count, utick_callback_t cb) +{ + uint32_t instance; + + /* Get instance from peripheral base address. */ + instance = UTICK_GetInstance(base); + + /* Save the handle in global variables to support the double weak mechanism. */ + s_utickHandle[instance] = cb; +#if ((defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) && \ + !(defined(FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS) && FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS)) + EnableDeepSleepIRQ(s_utickIRQ[instance]); +#else + (void)EnableIRQ(s_utickIRQ[instance]); +#endif /* FSL_FEATURE_SOC_SYSCON_COUNT && !FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS */ + base->CTRL = count | UTICK_CTRL_REPEAT(mode); +} + +/*! + * brief Initializes an UTICK by turning its bus clock on + * + */ +void UTICK_Init(UTICK_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable utick clock */ + CLOCK_EnableClock(s_utickClock[UTICK_GetInstance(base)]); +#endif + +#if !(defined(FSL_FEATURE_UTICK_HAS_NO_RESET) && FSL_FEATURE_UTICK_HAS_NO_RESET) + RESET_PeripheralReset(s_utickResets[UTICK_GetInstance(base)]); +#endif + +#if !(defined(FSL_FEATURE_UTICK_HAS_NO_PDCFG) && FSL_FEATURE_UTICK_HAS_NO_PDCFG) + /* Power up Watchdog oscillator*/ + POWER_DisablePD(kPDRUNCFG_PD_WDT_OSC); +#endif + + s_utickIsr = UTICK_HandleIRQ; +} + +/*! + * brief Deinitializes a UTICK instance. + * + * This function shuts down Utick bus clock + * + * param base UTICK peripheral base address. + */ +void UTICK_Deinit(UTICK_Type *base) +{ + /* Turn off utick */ + base->CTRL = 0; +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Disable utick clock */ + CLOCK_DisableClock(s_utickClock[UTICK_GetInstance(base)]); +#endif +} + +/*! + * brief Get Status Flags. + * + * This returns the status flag + * + * param base UTICK peripheral base address. + * return status register value + */ +uint32_t UTICK_GetStatusFlags(UTICK_Type *base) +{ + return (base->STAT); +} + +/*! + * brief Clear Status Interrupt Flags. + * + * This clears intr status flag + * + * param base UTICK peripheral base address. + * return none + */ +void UTICK_ClearStatusFlags(UTICK_Type *base) +{ + base->STAT = UTICK_STAT_INTR_MASK; +} + +/*! + * brief UTICK Interrupt Service Handler. + * + * This function handles the interrupt and refers to the callback array in the driver to callback user (as per request + * in UTICK_SetTick()). + * if no user callback is scheduled, the interrupt will simply be cleared. + * + * param base UTICK peripheral base address. + * param cb callback scheduled for this instance of UTICK + * return none + */ +void UTICK_HandleIRQ(UTICK_Type *base, utick_callback_t cb) +{ + UTICK_ClearStatusFlags(base); + if (cb != NULL) + { + cb(); + } +} + +#if defined(UTICK0) +void UTICK0_DriverIRQHandler(void); +void UTICK0_DriverIRQHandler(void) +{ + s_utickIsr(UTICK0, s_utickHandle[0]); + SDK_ISR_EXIT_BARRIER; +} +#endif +#if defined(UTICK1) +void UTICK1_DriverIRQHandler(void); +void UTICK1_DriverIRQHandler(void) +{ + s_utickIsr(UTICK1, s_utickHandle[1]); + SDK_ISR_EXIT_BARRIER; +} +#endif +#if defined(UTICK2) +void UTICK2_DriverIRQHandler(void); +void UTICK2_DriverIRQHandler(void) +{ + s_utickIsr(UTICK2, s_utickHandle[2]); + SDK_ISR_EXIT_BARRIER; +} +#endif +#if defined(UTICK) +void UTICK_DriverIRQHandler(void); +void UTICK_DriverIRQHandler(void) +{ + s_utickIsr(UTICK, s_utickHandle[0]); + SDK_ISR_EXIT_BARRIER; +} +#endif diff --git a/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_utick.h b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_utick.h new file mode 100644 index 0000000000..48c7d6b86d --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_utick.h @@ -0,0 +1,118 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2019, 2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_UTICK_H_ +#define _FSL_UTICK_H_ + +#include "fsl_common.h" +/*! + * @addtogroup utick + * @{ + */ + +/*! @file*/ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief UTICK driver version 2.0.5. */ +#define FSL_UTICK_DRIVER_VERSION (MAKE_VERSION(2, 0, 5)) +/*@}*/ + +/*! @brief UTICK timer operational mode. */ +typedef enum _utick_mode +{ + kUTICK_Onetime = 0x0U, /*!< Trigger once*/ + kUTICK_Repeat = 0x1U, /*!< Trigger repeatedly */ +} utick_mode_t; + +/*! @brief UTICK callback function. */ +typedef void (*utick_callback_t)(void); + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* _cplusplus */ + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Initializes an UTICK by turning its bus clock on + * + */ +void UTICK_Init(UTICK_Type *base); + +/*! + * @brief Deinitializes a UTICK instance. + * + * This function shuts down Utick bus clock + * + * @param base UTICK peripheral base address. + */ +void UTICK_Deinit(UTICK_Type *base); +/*! + * @brief Get Status Flags. + * + * This returns the status flag + * + * @param base UTICK peripheral base address. + * @return status register value + */ +uint32_t UTICK_GetStatusFlags(UTICK_Type *base); +/*! + * @brief Clear Status Interrupt Flags. + * + * This clears intr status flag + * + * @param base UTICK peripheral base address. + * @return none + */ +void UTICK_ClearStatusFlags(UTICK_Type *base); + +/*! + * @brief Starts UTICK. + * + * This function starts a repeat/onetime countdown with an optional callback + * + * @param base UTICK peripheral base address. + * @param mode UTICK timer mode (ie kUTICK_onetime or kUTICK_repeat) + * @param count UTICK timer mode (ie kUTICK_onetime or kUTICK_repeat) + * @param cb UTICK callback (can be left as NULL if none, otherwise should be a void func(void)) + * @return none + */ +void UTICK_SetTick(UTICK_Type *base, utick_mode_t mode, uint32_t count, utick_callback_t cb); +/*! + * @brief UTICK Interrupt Service Handler. + * + * This function handles the interrupt and refers to the callback array in the driver to callback user (as per request + * in UTICK_SetTick()). + * if no user callback is scheduled, the interrupt will simply be cleared. + * + * @param base UTICK peripheral base address. + * @param cb callback scheduled for this instance of UTICK + * @return none + */ +void UTICK_HandleIRQ(UTICK_Type *base, utick_callback_t cb); + +/* @} */ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_UTICK_H_ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_wwdt.c b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_wwdt.c new file mode 100644 index 0000000000..6680148acf --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_wwdt.c @@ -0,0 +1,275 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_wwdt.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.wwdt" +#endif + +#define FREQUENCY_3MHZ (3000000U) +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/*! + * @brief Gets the instance from the base address + * + * @param base WWDT peripheral base address + * + * @return The WWDT instance + */ +static uint32_t WWDT_GetInstance(WWDT_Type *base); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Pointers to WWDT bases for each instance. */ +static WWDT_Type *const s_wwdtBases[] = WWDT_BASE_PTRS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Pointers to WWDT clocks for each instance. */ +static const clock_ip_name_t s_wwdtClocks[] = WWDT_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) +#if !(defined(FSL_FEATURE_WWDT_HAS_NO_RESET) && FSL_FEATURE_WWDT_HAS_NO_RESET) +/*! @brief Pointers to WWDT resets for each instance. */ +static const reset_ip_name_t s_wwdtResets[] = WWDT_RSTS; +#endif +#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ + +/******************************************************************************* + * Code + ******************************************************************************/ +static uint32_t WWDT_GetInstance(WWDT_Type *base) +{ + uint32_t instance; + uint32_t wwdtArrayCount = (sizeof(s_wwdtBases) / sizeof(s_wwdtBases[0])); + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < wwdtArrayCount; instance++) + { + if (s_wwdtBases[instance] == base) + { + break; + } + } + + assert(instance < wwdtArrayCount); + + return instance; +} + +/******************************************************************************* + * Code + ******************************************************************************/ + +/*! + * brief Initializes WWDT configure structure. + * + * This function initializes the WWDT configure structure to default value. The default + * value are: + * code + * config->enableWwdt = true; + * config->enableWatchdogReset = false; + * config->enableWatchdogProtect = false; + * config->enableLockOscillator = false; + * config->windowValue = 0xFFFFFFU; + * config->timeoutValue = 0xFFFFFFU; + * config->warningValue = 0; + * endcode + * + * param config Pointer to WWDT config structure. + * see wwdt_config_t + */ +void WWDT_GetDefaultConfig(wwdt_config_t *config) +{ + assert(NULL != config); + + /* Initializes the configure structure to zero. */ + (void)memset(config, 0, sizeof(*config)); + + /* Enable the watch dog */ + config->enableWwdt = true; + /* Disable the watchdog timeout reset */ + config->enableWatchdogReset = false; + /* Disable the watchdog protection for updating the timeout value */ + config->enableWatchdogProtect = false; +#if !(defined(FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK) && FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK) + /* Do not lock the watchdog oscillator */ + config->enableLockOscillator = false; +#endif + /* Windowing is not in effect */ + config->windowValue = 0xFFFFFFU; + /* Set the timeout value to the max */ + config->timeoutValue = 0xFFFFFFU; + /* No warning is provided */ + config->warningValue = 0; + /* Set clock frequency. */ + config->clockFreq_Hz = 0U; +} + +/*! + * brief Initializes the WWDT. + * + * This function initializes the WWDT. When called, the WWDT runs according to the configuration. + * + * Example: + * code + * wwdt_config_t config; + * WWDT_GetDefaultConfig(&config); + * config.timeoutValue = 0x7ffU; + * WWDT_Init(wwdt_base,&config); + * endcode + * + * param base WWDT peripheral base address + * param config The configuration of WWDT + */ +void WWDT_Init(WWDT_Type *base, const wwdt_config_t *config) +{ + assert(NULL != config); + + uint32_t value = 0U; + uint32_t DelayUs = 0U; + uint32_t primaskValue = 0U; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable the WWDT clock */ + CLOCK_EnableClock(s_wwdtClocks[WWDT_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) +#if !(defined(FSL_FEATURE_WWDT_HAS_NO_RESET) && FSL_FEATURE_WWDT_HAS_NO_RESET) + /* Reset the module. */ + RESET_PeripheralReset(s_wwdtResets[WWDT_GetInstance(base)]); +#endif + +#if defined(FSL_FEATURE_WWDT_WDTRESET_FROM_PMC) && (FSL_FEATURE_WWDT_WDTRESET_FROM_PMC) + /* PMC RESETCAUSE: set bit to clear it by write 1. */ + PMC->RESETCAUSE = PMC_RESETCAUSE_WDTRESET_MASK; + /* Enable the watchdog reset event to affect the system in the Power Management Controller */ + PMC->CTRL |= PMC_CTRL_WDTRESETENABLE_MASK; +#endif /*FSL_FEATURE_WWDT_WDTRESET_FROM_PMC*/ + +#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ + +#if !(defined(FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK) && FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK) + value = WWDT_MOD_WDEN(config->enableWwdt) | WWDT_MOD_WDRESET(config->enableWatchdogReset) | + WWDT_MOD_LOCK(config->enableLockOscillator); +#else + value = WWDT_MOD_WDEN(config->enableWwdt) | WWDT_MOD_WDRESET(config->enableWatchdogReset); +#endif + /* Clear legacy flag in the MOD register by software writing a "1" to this bit field.. */ + if (0U != (base->MOD & WWDT_MOD_WDINT_MASK)) + { + value |= WWDT_MOD_WDINT_MASK; + } + /* Set configuration */ + primaskValue = DisableGlobalIRQ(); + base->TC = WWDT_TC_COUNT(config->timeoutValue); + base->MOD = value; + base->WINDOW = WWDT_WINDOW_WINDOW(config->windowValue); + base->WARNINT = WWDT_WARNINT_WARNINT(config->warningValue); + /* Refreshes the WWDT timer. */ + base->FEED = WWDT_FIRST_WORD_OF_REFRESH; + base->FEED = WWDT_SECOND_WORD_OF_REFRESH; + EnableGlobalIRQ(primaskValue); + /* Read counter value to wait wwdt timer start*/ + if (config->enableWwdt) + { + while (base->TV == 0xFFUL) + { + } + } + + /* This WDPROTECT bit can be set once by software and is only cleared by a reset */ + if (config->enableWatchdogProtect && (0U == (base->MOD & WWDT_MOD_WDPROTECT_MASK))) + { + /* The config->clockFreq_Hz must be set in order to config the delay time. */ + assert(0U != config->clockFreq_Hz); + + /* Set the WDPROTECT bit after the Feed Sequence (0xAA, 0x55) with 3 WDCLK delay */ + DelayUs = FREQUENCY_3MHZ / config->clockFreq_Hz + 1U; + SDK_DelayAtLeastUs(DelayUs, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); + + base->MOD |= WWDT_MOD_WDPROTECT(1U); + } +} + +/*! + * brief Shuts down the WWDT. + * + * This function shuts down the WWDT. + * + * param base WWDT peripheral base address + */ +void WWDT_Deinit(WWDT_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Disable the WWDT clock */ + CLOCK_DisableClock(s_wwdtClocks[WWDT_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/*! + * brief Refreshes the WWDT timer. + * + * This function feeds the WWDT. + * This function should be called before WWDT timer is in timeout. Otherwise, a reset is asserted. + * + * param base WWDT peripheral base address + */ +void WWDT_Refresh(WWDT_Type *base) +{ + uint32_t primaskValue = 0U; + + /* Disable the global interrupt to protect refresh sequence */ + primaskValue = DisableGlobalIRQ(); + base->FEED = WWDT_FIRST_WORD_OF_REFRESH; + base->FEED = WWDT_SECOND_WORD_OF_REFRESH; + EnableGlobalIRQ(primaskValue); +} + +/*! + * brief Clear WWDT flag. + * + * This function clears WWDT status flag. + * + * Example for clearing warning flag: + * code + * WWDT_ClearStatusFlags(wwdt_base, kWWDT_WarningFlag); + * endcode + * param base WWDT peripheral base address + * param mask The status flags to clear. This is a logical OR of members of the + * enumeration ::_wwdt_status_flags_t + */ +void WWDT_ClearStatusFlags(WWDT_Type *base, uint32_t mask) +{ + /* Clear the WDINT bit so that we don't accidentally clear it */ + uint32_t reg = (base->MOD & (~WWDT_MOD_WDINT_MASK)); + + /* Clear timeout by writing a zero */ + if (0U != (mask & (uint32_t)kWWDT_TimeoutFlag)) + { + reg &= ~WWDT_MOD_WDTOF_MASK; +#if defined(FSL_FEATURE_WWDT_WDTRESET_FROM_PMC) && (FSL_FEATURE_WWDT_WDTRESET_FROM_PMC) + /* PMC RESETCAUSE: set bit to clear it */ + PMC->RESETCAUSE = PMC_RESETCAUSE_WDTRESET_MASK; +#endif /*FSL_FEATURE_WWDT_WDTRESET_FROM_PMC*/ + } + + /* Clear warning interrupt flag by writing a one */ + if (0U != (mask & (uint32_t)kWWDT_WarningFlag)) + { + reg |= WWDT_MOD_WDINT_MASK; + } + + base->MOD = reg; +} diff --git a/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_wwdt.h b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_wwdt.h new file mode 100644 index 0000000000..2546253496 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/drivers/fsl_wwdt.h @@ -0,0 +1,276 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_WWDT_H_ +#define _FSL_WWDT_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup wwdt + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + *******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief Defines WWDT driver version. */ +#define FSL_WWDT_DRIVER_VERSION (MAKE_VERSION(2, 1, 9)) +/*@}*/ + +/*! @name Refresh sequence */ +/*@{*/ +#define WWDT_FIRST_WORD_OF_REFRESH (0xAAU) /*!< First word of refresh sequence */ +#define WWDT_SECOND_WORD_OF_REFRESH (0x55U) /*!< Second word of refresh sequence */ +/*@}*/ + +/*! @brief Describes WWDT configuration structure. */ +typedef struct _wwdt_config +{ + bool enableWwdt; /*!< Enables or disables WWDT */ + bool enableWatchdogReset; /*!< true: Watchdog timeout will cause a chip reset + false: Watchdog timeout will not cause a chip reset */ + bool enableWatchdogProtect; /*!< true: Enable watchdog protect i.e timeout value can only be + changed after counter is below warning & window values + false: Disable watchdog protect; timeout value can be changed + at any time */ +#if !(defined(FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK) && FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK) + bool enableLockOscillator; /*!< true: Disabling or powering down the watchdog oscillator is prevented + Once set, this bit can only be cleared by a reset + false: Do not lock oscillator */ +#endif + uint32_t windowValue; /*!< Window value, set this to 0xFFFFFF if windowing is not in effect */ + uint32_t timeoutValue; /*!< Timeout value */ + uint32_t warningValue; /*!< Watchdog time counter value that will generate a + warning interrupt. Set this to 0 for no warning */ + uint32_t clockFreq_Hz; /*!< Watchdog clock source frequency. */ +} wwdt_config_t; + +/*! + * @brief WWDT status flags. + * + * This structure contains the WWDT status flags for use in the WWDT functions. + */ +enum _wwdt_status_flags_t +{ + kWWDT_TimeoutFlag = WWDT_MOD_WDTOF_MASK, /*!< Time-out flag, set when the timer times out */ + kWWDT_WarningFlag = WWDT_MOD_WDINT_MASK /*!< Warning interrupt flag, set when timer is below the value WDWARNINT */ +}; + +/******************************************************************************* + * API + *******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/*! + * @name WWDT Initialization and De-initialization + * @{ + */ + +/*! + * @brief Initializes WWDT configure structure. + * + * This function initializes the WWDT configure structure to default value. The default + * value are: + * @code + * config->enableWwdt = true; + * config->enableWatchdogReset = false; + * config->enableWatchdogProtect = false; + * config->enableLockOscillator = false; + * config->windowValue = 0xFFFFFFU; + * config->timeoutValue = 0xFFFFFFU; + * config->warningValue = 0; + * @endcode + * + * @param config Pointer to WWDT config structure. + * @see wwdt_config_t + */ +void WWDT_GetDefaultConfig(wwdt_config_t *config); + +/*! + * @brief Initializes the WWDT. + * + * This function initializes the WWDT. When called, the WWDT runs according to the configuration. + * + * Example: + * @code + * wwdt_config_t config; + * WWDT_GetDefaultConfig(&config); + * config.timeoutValue = 0x7ffU; + * WWDT_Init(wwdt_base,&config); + * @endcode + * + * @param base WWDT peripheral base address + * @param config The configuration of WWDT + */ +void WWDT_Init(WWDT_Type *base, const wwdt_config_t *config); + +/*! + * @brief Shuts down the WWDT. + * + * This function shuts down the WWDT. + * + * @param base WWDT peripheral base address + */ +void WWDT_Deinit(WWDT_Type *base); + +/* @} */ + +/*! + * @name WWDT Functional Operation + * @{ + */ + +/*! + * @brief Enables the WWDT module. + * + * This function write value into WWDT_MOD register to enable the WWDT, it is a write-once bit; + * once this bit is set to one and a watchdog feed is performed, the watchdog timer will run + * permanently. + * + * @param base WWDT peripheral base address + */ +static inline void WWDT_Enable(WWDT_Type *base) +{ + base->MOD |= WWDT_MOD_WDEN_MASK; +} + +/*! + * @brief Disables the WWDT module. + * @deprecated Do not use this function. It will be deleted in next release version, for + * once the bit field of WDEN written with a 1, it can not be re-written with a 0. + * + * This function write value into WWDT_MOD register to disable the WWDT. + * + * @param base WWDT peripheral base address + */ +static inline void WWDT_Disable(WWDT_Type *base) +{ + base->MOD &= ~WWDT_MOD_WDEN_MASK; +} + +/*! + * @brief Gets all WWDT status flags. + * + * This function gets all status flags. + * + * Example for getting Timeout Flag: + * @code + * uint32_t status; + * status = WWDT_GetStatusFlags(wwdt_base) & kWWDT_TimeoutFlag; + * @endcode + * @param base WWDT peripheral base address + * @return The status flags. This is the logical OR of members of the + * enumeration ::_wwdt_status_flags_t + */ +static inline uint32_t WWDT_GetStatusFlags(WWDT_Type *base) +{ +#if defined(FSL_FEATURE_WWDT_WDTRESET_FROM_PMC) && (FSL_FEATURE_WWDT_WDTRESET_FROM_PMC) + uint32_t status; + /* WDTOF is not set in case of WD reset - get info from PMC instead */ + status = (base->MOD & (WWDT_MOD_WDTOF_MASK | WWDT_MOD_WDINT_MASK)); + if (PMC->RESETCAUSE & PMC_RESETCAUSE_WDTRESET_MASK) + { + status |= kWWDT_TimeoutFlag; + } + return status; +#else + return (base->MOD & (WWDT_MOD_WDTOF_MASK | WWDT_MOD_WDINT_MASK)); +#endif /*FSL_FEATURE_WWDT_WDTRESET_FROM_PMC*/ +} + +/*! + * @brief Clear WWDT flag. + * + * This function clears WWDT status flag. + * + * Example for clearing warning flag: + * @code + * WWDT_ClearStatusFlags(wwdt_base, kWWDT_WarningFlag); + * @endcode + * @param base WWDT peripheral base address + * @param mask The status flags to clear. This is a logical OR of members of the + * enumeration ::_wwdt_status_flags_t + */ +void WWDT_ClearStatusFlags(WWDT_Type *base, uint32_t mask); + +/*! + * @brief Set the WWDT warning value. + * + * The WDWARNINT register determines the watchdog timer counter value that will generate a watchdog + * interrupt. When the watchdog timer counter is no longer greater than the value defined by + * WARNINT, an interrupt will be generated after the subsequent WDCLK. + * + * @param base WWDT peripheral base address + * @param warningValue WWDT warning value. + */ +static inline void WWDT_SetWarningValue(WWDT_Type *base, uint32_t warningValue) +{ + base->WARNINT = WWDT_WARNINT_WARNINT(warningValue); +} + +/*! + * @brief Set the WWDT timeout value. + * + * This function sets the timeout value. Every time a feed sequence occurs the value in the TC + * register is loaded into the Watchdog timer. Writing a value below 0xFF will cause 0xFF to be + * loaded into the TC register. Thus the minimum time-out interval is TWDCLK*256*4. + * If enableWatchdogProtect flag is true in wwdt_config_t config structure, any attempt to change + * the timeout value before the watchdog counter is below the warning and window values + * will cause a watchdog reset and set the WDTOF flag. + * + * @param base WWDT peripheral base address + * @param timeoutCount WWDT timeout value, count of WWDT clock tick. + */ +static inline void WWDT_SetTimeoutValue(WWDT_Type *base, uint32_t timeoutCount) +{ + base->TC = WWDT_TC_COUNT(timeoutCount); +} + +/*! + * @brief Sets the WWDT window value. + * + * The WINDOW register determines the highest TV value allowed when a watchdog feed is performed. + * If a feed sequence occurs when timer value is greater than the value in WINDOW, a watchdog + * event will occur. To disable windowing, set windowValue to 0xFFFFFF (maximum possible timer + * value) so windowing is not in effect. + * + * @param base WWDT peripheral base address + * @param windowValue WWDT window value. + */ +static inline void WWDT_SetWindowValue(WWDT_Type *base, uint32_t windowValue) +{ + base->WINDOW = WWDT_WINDOW_WINDOW(windowValue); +} + +/*! + * @brief Refreshes the WWDT timer. + * + * This function feeds the WWDT. + * This function should be called before WWDT timer is in timeout. Otherwise, a reset is asserted. + * + * @param base WWDT peripheral base address + */ +void WWDT_Refresh(WWDT_Type *base); + +/*@}*/ + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +/*! @}*/ + +#endif /* _FSL_WWDT_H_ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/fsl_device_registers.h b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/fsl_device_registers.h new file mode 100644 index 0000000000..8244295823 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/fsl_device_registers.h @@ -0,0 +1,36 @@ +/* + * Copyright 2014-2016 Freescale Semiconductor, Inc. + * Copyright 2016-2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef __FSL_DEVICE_REGISTERS_H__ +#define __FSL_DEVICE_REGISTERS_H__ + +/* + * Include the cpu specific register header files. + * + * The CPU macro should be declared in the project or makefile. + */ +#if (defined(CPU_LPC55S16JBD100) || defined(CPU_LPC55S16JBD64) || defined(CPU_LPC55S16JEV59) || \ + defined(CPU_LPC55S16JEV98)) + +#define LPC55S16_SERIES + +/* CMSIS-style register definitions */ +#include "LPC55S16.h" +/* CPU specific feature definitions */ +#include "LPC55S16_features.h" + +#else + #error "No valid CPU defined!" +#endif + +#endif /* __FSL_DEVICE_REGISTERS_H__ */ + +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/gcc/LPC55S16_flash.ld b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/gcc/LPC55S16_flash.ld new file mode 100644 index 0000000000..1897ad1137 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/gcc/LPC55S16_flash.ld @@ -0,0 +1,215 @@ +/* +** ################################################################### +** Processors: LPC55S16JBD100 +** LPC55S16JBD64 +** LPC55S16JEV59 +** LPC55S16JEV98 +** +** Compiler: GNU C Compiler +** Reference manual: LPC55S1x/LPC551x User manual Rev.0.6 15 November 2019 +** Version: rev. 1.1, 2019-12-03 +** Build: b220622 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2022 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + + + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0800; + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x00000000, LENGTH = 0x00000200 + m_text (RX) : ORIGIN = 0x00000200, LENGTH = 0x0003CE00 + m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00010000 + m_sramx (RW) : ORIGIN = 0x04000000, LENGTH = 0x00004000 + m_usb_sram (RW) : ORIGIN = 0x20010000, LENGTH = 0x00004000 +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into internal flash */ + .interrupts : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + /* The program code and other data goes into internal flash */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(.ramfunc*) /* for functions in ram */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + m_usb_bdt (NOLOAD) : + { + . = ALIGN(512); + *(m_usb_bdt) + } > m_usb_sram + + m_usb_global (NOLOAD) : + { + *(m_usb_global) + } > m_usb_sram + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") +} + diff --git a/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/gcc/LPC55S16_ram.ld b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/gcc/LPC55S16_ram.ld new file mode 100644 index 0000000000..02635a696b --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/gcc/LPC55S16_ram.ld @@ -0,0 +1,214 @@ +/* +** ################################################################### +** Processors: LPC55S16JBD100 +** LPC55S16JBD64 +** LPC55S16JEV59 +** LPC55S16JEV98 +** +** Compiler: GNU C Compiler +** Reference manual: LPC55S1x/LPC551x User manual Rev.0.6 15 November 2019 +** Version: rev. 1.1, 2019-12-03 +** Build: b220622 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2022 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + + + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0800; + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x20000000, LENGTH = 0x00000200 + m_text (RX) : ORIGIN = 0x20000200, LENGTH = 0x0000FE00 + m_data (RW) : ORIGIN = 0x04000000, LENGTH = 0x00004000 + m_usb_sram (RW) : ORIGIN = 0x20010000, LENGTH = 0x00004000 +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into internal flash */ + .interrupts : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + /* The program code and other data goes into internal flash */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(.ramfunc*) /* for functions in ram */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + m_usb_bdt (NOLOAD) : + { + . = ALIGN(512); + *(m_usb_bdt) + } > m_usb_sram + + m_usb_global (NOLOAD) : + { + *(m_usb_global) + } > m_usb_sram + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") +} + diff --git a/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/gcc/startup_LPC55S16.S b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/gcc/startup_LPC55S16.S new file mode 100644 index 0000000000..7b13cdcceb --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/gcc/startup_LPC55S16.S @@ -0,0 +1,895 @@ +/* --------------------------------------------------------------------------*/ +/* @file: startup_LPC55S16.s */ +/* @purpose: CMSIS Cortex-M33 Core Device Startup File */ +/* LPC55S16 */ +/* @version: 1.1 */ +/* @date: 2019-12-3 */ +/* --------------------------------------------------------------------------*/ +/* */ +/* Copyright 1997-2016 Freescale Semiconductor, Inc. */ +/* Copyright 2016-2021 NXP */ +/* All rights reserved. */ +/* */ +/* SPDX-License-Identifier: BSD-3-Clause */ +/*****************************************************************************/ +/* Version: GCC for ARM Embedded Processors */ +/*****************************************************************************/ + + + .syntax unified + .arch armv8-m.main + + .section .isr_vector, "a" + .align 2 + .globl __Vectors +__Vectors: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long NMI_Handler /* NMI Handler*/ + .long HardFault_Handler /* Hard Fault Handler*/ + .long MemManage_Handler /* MPU Fault Handler*/ + .long BusFault_Handler /* Bus Fault Handler*/ + .long UsageFault_Handler /* Usage Fault Handler*/ + .long SecureFault_Handler /* Secure Fault Handler*/ + .long 0 /* Reserved*/ + .long 0 /* Reserved*/ + .long 0 /* Reserved*/ + .long SVC_Handler /* SVCall Handler*/ + .long DebugMon_Handler /* Debug Monitor Handler*/ + .long 0 /* Reserved*/ + .long PendSV_Handler /* PendSV Handler*/ + .long SysTick_Handler /* SysTick Handler*/ + + /* External Interrupts */ + .long WDT_BOD_IRQHandler /* Windowed watchdog timer, Brownout detect, Flash interrupt */ + .long DMA0_IRQHandler /* DMA0 controller */ + .long GINT0_IRQHandler /* GPIO group 0 */ + .long GINT1_IRQHandler /* GPIO group 1 */ + .long PIN_INT0_IRQHandler /* Pin interrupt 0 or pattern match engine slice 0 */ + .long PIN_INT1_IRQHandler /* Pin interrupt 1or pattern match engine slice 1 */ + .long PIN_INT2_IRQHandler /* Pin interrupt 2 or pattern match engine slice 2 */ + .long PIN_INT3_IRQHandler /* Pin interrupt 3 or pattern match engine slice 3 */ + .long UTICK0_IRQHandler /* Micro-tick Timer */ + .long MRT0_IRQHandler /* Multi-rate timer */ + .long CTIMER0_IRQHandler /* Standard counter/timer CTIMER0 */ + .long CTIMER1_IRQHandler /* Standard counter/timer CTIMER1 */ + .long SCT0_IRQHandler /* SCTimer/PWM */ + .long CTIMER3_IRQHandler /* Standard counter/timer CTIMER3 */ + .long FLEXCOMM0_IRQHandler /* Flexcomm Interface 0 (USART, SPI, I2C, I2S, FLEXCOMM) */ + .long FLEXCOMM1_IRQHandler /* Flexcomm Interface 1 (USART, SPI, I2C, I2S, FLEXCOMM) */ + .long FLEXCOMM2_IRQHandler /* Flexcomm Interface 2 (USART, SPI, I2C, I2S, FLEXCOMM) */ + .long FLEXCOMM3_IRQHandler /* Flexcomm Interface 3 (USART, SPI, I2C, I2S, FLEXCOMM) */ + .long FLEXCOMM4_IRQHandler /* Flexcomm Interface 4 (USART, SPI, I2C, I2S, FLEXCOMM) */ + .long FLEXCOMM5_IRQHandler /* Flexcomm Interface 5 (USART, SPI, I2C, I2S, FLEXCOMM) */ + .long FLEXCOMM6_IRQHandler /* Flexcomm Interface 6 (USART, SPI, I2C, I2S, FLEXCOMM) */ + .long FLEXCOMM7_IRQHandler /* Flexcomm Interface 7 (USART, SPI, I2C, I2S, FLEXCOMM) */ + .long ADC0_IRQHandler /* ADC0 */ + .long Reserved39_IRQHandler /* Reserved interrupt */ + .long ACMP_IRQHandler /* ACMP interrupts */ + .long Reserved41_IRQHandler /* Reserved interrupt */ + .long Reserved42_IRQHandler /* Reserved interrupt */ + .long USB0_NEEDCLK_IRQHandler /* USB Activity Wake-up Interrupt */ + .long USB0_IRQHandler /* USB device */ + .long RTC_IRQHandler /* RTC alarm and wake-up interrupts */ + .long Reserved46_IRQHandler /* Reserved interrupt */ + .long Reserved47_IRQHandler /* Reserved interrupt */ + .long PIN_INT4_IRQHandler /* Pin interrupt 4 or pattern match engine slice 4 int */ + .long PIN_INT5_IRQHandler /* Pin interrupt 5 or pattern match engine slice 5 int */ + .long PIN_INT6_IRQHandler /* Pin interrupt 6 or pattern match engine slice 6 int */ + .long PIN_INT7_IRQHandler /* Pin interrupt 7 or pattern match engine slice 7 int */ + .long CTIMER2_IRQHandler /* Standard counter/timer CTIMER2 */ + .long CTIMER4_IRQHandler /* Standard counter/timer CTIMER4 */ + .long OS_EVENT_IRQHandler /* OS_EVENT_TIMER and OS_EVENT_WAKEUP interrupts */ + .long Reserved55_IRQHandler /* Reserved interrupt */ + .long Reserved56_IRQHandler /* Reserved interrupt */ + .long Reserved57_IRQHandler /* Reserved interrupt */ + .long Reserved58_IRQHandler /* Reserved interrupt */ + .long CAN0_IRQ0_IRQHandler /* CAN0 interrupt0 */ + .long CAN0_IRQ1_IRQHandler /* CAN0 interrupt1 */ + .long Reserved61_IRQHandler /* Reserved interrupt */ + .long USB1_PHY_IRQHandler /* USB1_PHY */ + .long USB1_IRQHandler /* USB1 interrupt */ + .long USB1_NEEDCLK_IRQHandler /* USB1 activity */ + .long SEC_HYPERVISOR_CALL_IRQHandler /* SEC_HYPERVISOR_CALL interrupt */ + .long SEC_GPIO_INT0_IRQ0_IRQHandler /* SEC_GPIO_INT0_IRQ0 interrupt */ + .long SEC_GPIO_INT0_IRQ1_IRQHandler /* SEC_GPIO_INT0_IRQ1 interrupt */ + .long PLU_IRQHandler /* PLU interrupt */ + .long SEC_VIO_IRQHandler /* SEC_VIO interrupt */ + .long HASHCRYPT_IRQHandler /* SHA interrupt */ + .long CASER_IRQHandler /* CASPER interrupt */ + .long PUF_IRQHandler /* PUF interrupt */ + .long Reserved73_IRQHandler /* Reserved interrupt */ + .long DMA1_IRQHandler /* DMA1 interrupt */ + .long FLEXCOMM8_IRQHandler /* Flexcomm Interface 8 (SPI, , FLEXCOMM) */ + .long CDOG_IRQHandler /* CDOG interrupt */ + + .size __Vectors, . - __Vectors + + .text + .thumb + +/* Reset Handler */ + .thumb_func + .align 2 + .globl Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + cpsid i /* Mask interrupts */ + .equ VTOR, 0xE000ED08 + ldr r0, =VTOR + ldr r1, =__Vectors + str r1, [r0] + ldr r2, [r1] + msr msp, r2 + ldr R0, =__StackLimit + msr msplim, R0 +#ifndef __NO_SYSTEM_INIT + ldr r0,=SystemInit + blx r0 +#endif +/* Loop to copy data from read only memory to RAM. The ranges + * of copy from/to are specified by following symbols evaluated in + * linker script. + * __etext: End of code section, i.e., begin of data sections to copy from. + * __data_start__/__data_end__: RAM address range that data should be + * copied to. Both must be aligned to 4 bytes boundary. */ + + ldr r1, =__etext + ldr r2, =__data_start__ + ldr r3, =__data_end__ + +#if 1 +/* Here are two copies of loop implemenations. First one favors code size + * and the second one favors performance. Default uses the first one. + * Change to "#if 0" to use the second one */ +.LC0: + cmp r2, r3 + ittt lt + ldrlt r0, [r1], #4 + strlt r0, [r2], #4 + blt .LC0 +#else + subs r3, r2 + ble .LC1 +.LC0: + subs r3, #4 + ldr r0, [r1, r3] + str r0, [r2, r3] + bgt .LC0 +.LC1: +#endif + +#ifdef __STARTUP_CLEAR_BSS +/* This part of work usually is done in C library startup code. Otherwise, + * define this macro to enable it in this startup. + * + * Loop to zero out BSS section, which uses following symbols + * in linker script: + * __bss_start__: start of BSS section. Must align to 4 + * __bss_end__: end of BSS section. Must align to 4 + */ + ldr r1, =__bss_start__ + ldr r2, =__bss_end__ + + movs r0, 0 +.LC2: + cmp r1, r2 + itt lt + strlt r0, [r1], #4 + blt .LC2 +#endif /* __STARTUP_CLEAR_BSS */ + +/* Add stack / heap initializaiton */ + movs r0, 0 + ldr r1, =__HeapBase + ldr r2, =__HeapLimit +.LC3: + cmp r1, r2 + itt lt + strlt r0, [r1], #4 + blt .LC3 + + ldr r1, =__StackLimit + ldr r2, =__StackTop +.LC4: + cmp r1, r2 + itt lt + strlt r0, [r1], #4 + blt .LC4 +/*End of stack / heap initializaiton */ + cpsie i /* Unmask interrupts */ + +#ifndef __START +#define __START _start +#endif +#ifndef __ATOLLIC__ + ldr r0,=__START + blx r0 +#else + ldr r0,=__libc_init_array + blx r0 + ldr r0,=main + bx r0 +#endif + .pool + .size Reset_Handler, . - Reset_Handler + + .align 1 + .thumb_func + .weak DefaultISR + .type DefaultISR, %function +DefaultISR: + b DefaultISR + .size DefaultISR, . - DefaultISR + + .align 1 + .thumb_func + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + ldr r0,=NMI_Handler + bx r0 + .size NMI_Handler, . - NMI_Handler + + .align 1 + .thumb_func + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + ldr r0,=HardFault_Handler + bx r0 + .size HardFault_Handler, . - HardFault_Handler + + .align 1 + .thumb_func + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + ldr r0,=SVC_Handler + bx r0 + .size SVC_Handler, . - SVC_Handler + + .align 1 + .thumb_func + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + ldr r0,=PendSV_Handler + bx r0 + .size PendSV_Handler, . - PendSV_Handler + + .align 1 + .thumb_func + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + ldr r0,=SysTick_Handler + bx r0 + .size SysTick_Handler, . - SysTick_Handler + + .align 1 + .thumb_func + .weak WDT_BOD_IRQHandler + .type WDT_BOD_IRQHandler, %function +WDT_BOD_IRQHandler: + ldr r0,=WDT_BOD_DriverIRQHandler + bx r0 + .size WDT_BOD_IRQHandler, . - WDT_BOD_IRQHandler + + .align 1 + .thumb_func + .weak DMA0_IRQHandler + .type DMA0_IRQHandler, %function +DMA0_IRQHandler: + ldr r0,=DMA0_DriverIRQHandler + bx r0 + .size DMA0_IRQHandler, . - DMA0_IRQHandler + + .align 1 + .thumb_func + .weak GINT0_IRQHandler + .type GINT0_IRQHandler, %function +GINT0_IRQHandler: + ldr r0,=GINT0_DriverIRQHandler + bx r0 + .size GINT0_IRQHandler, . - GINT0_IRQHandler + + .align 1 + .thumb_func + .weak GINT1_IRQHandler + .type GINT1_IRQHandler, %function +GINT1_IRQHandler: + ldr r0,=GINT1_DriverIRQHandler + bx r0 + .size GINT1_IRQHandler, . - GINT1_IRQHandler + + .align 1 + .thumb_func + .weak PIN_INT0_IRQHandler + .type PIN_INT0_IRQHandler, %function +PIN_INT0_IRQHandler: + ldr r0,=PIN_INT0_DriverIRQHandler + bx r0 + .size PIN_INT0_IRQHandler, . - PIN_INT0_IRQHandler + + .align 1 + .thumb_func + .weak PIN_INT1_IRQHandler + .type PIN_INT1_IRQHandler, %function +PIN_INT1_IRQHandler: + ldr r0,=PIN_INT1_DriverIRQHandler + bx r0 + .size PIN_INT1_IRQHandler, . - PIN_INT1_IRQHandler + + .align 1 + .thumb_func + .weak PIN_INT2_IRQHandler + .type PIN_INT2_IRQHandler, %function +PIN_INT2_IRQHandler: + ldr r0,=PIN_INT2_DriverIRQHandler + bx r0 + .size PIN_INT2_IRQHandler, . - PIN_INT2_IRQHandler + + .align 1 + .thumb_func + .weak PIN_INT3_IRQHandler + .type PIN_INT3_IRQHandler, %function +PIN_INT3_IRQHandler: + ldr r0,=PIN_INT3_DriverIRQHandler + bx r0 + .size PIN_INT3_IRQHandler, . - PIN_INT3_IRQHandler + + .align 1 + .thumb_func + .weak UTICK0_IRQHandler + .type UTICK0_IRQHandler, %function +UTICK0_IRQHandler: + ldr r0,=UTICK0_DriverIRQHandler + bx r0 + .size UTICK0_IRQHandler, . - UTICK0_IRQHandler + + .align 1 + .thumb_func + .weak MRT0_IRQHandler + .type MRT0_IRQHandler, %function +MRT0_IRQHandler: + ldr r0,=MRT0_DriverIRQHandler + bx r0 + .size MRT0_IRQHandler, . - MRT0_IRQHandler + + .align 1 + .thumb_func + .weak CTIMER0_IRQHandler + .type CTIMER0_IRQHandler, %function +CTIMER0_IRQHandler: + ldr r0,=CTIMER0_DriverIRQHandler + bx r0 + .size CTIMER0_IRQHandler, . - CTIMER0_IRQHandler + + .align 1 + .thumb_func + .weak CTIMER1_IRQHandler + .type CTIMER1_IRQHandler, %function +CTIMER1_IRQHandler: + ldr r0,=CTIMER1_DriverIRQHandler + bx r0 + .size CTIMER1_IRQHandler, . - CTIMER1_IRQHandler + + .align 1 + .thumb_func + .weak SCT0_IRQHandler + .type SCT0_IRQHandler, %function +SCT0_IRQHandler: + ldr r0,=SCT0_DriverIRQHandler + bx r0 + .size SCT0_IRQHandler, . - SCT0_IRQHandler + + .align 1 + .thumb_func + .weak CTIMER3_IRQHandler + .type CTIMER3_IRQHandler, %function +CTIMER3_IRQHandler: + ldr r0,=CTIMER3_DriverIRQHandler + bx r0 + .size CTIMER3_IRQHandler, . - CTIMER3_IRQHandler + + .align 1 + .thumb_func + .weak FLEXCOMM0_IRQHandler + .type FLEXCOMM0_IRQHandler, %function +FLEXCOMM0_IRQHandler: + ldr r0,=FLEXCOMM0_DriverIRQHandler + bx r0 + .size FLEXCOMM0_IRQHandler, . - FLEXCOMM0_IRQHandler + + .align 1 + .thumb_func + .weak FLEXCOMM1_IRQHandler + .type FLEXCOMM1_IRQHandler, %function +FLEXCOMM1_IRQHandler: + ldr r0,=FLEXCOMM1_DriverIRQHandler + bx r0 + .size FLEXCOMM1_IRQHandler, . - FLEXCOMM1_IRQHandler + + .align 1 + .thumb_func + .weak FLEXCOMM2_IRQHandler + .type FLEXCOMM2_IRQHandler, %function +FLEXCOMM2_IRQHandler: + ldr r0,=FLEXCOMM2_DriverIRQHandler + bx r0 + .size FLEXCOMM2_IRQHandler, . - FLEXCOMM2_IRQHandler + + .align 1 + .thumb_func + .weak FLEXCOMM3_IRQHandler + .type FLEXCOMM3_IRQHandler, %function +FLEXCOMM3_IRQHandler: + ldr r0,=FLEXCOMM3_DriverIRQHandler + bx r0 + .size FLEXCOMM3_IRQHandler, . - FLEXCOMM3_IRQHandler + + .align 1 + .thumb_func + .weak FLEXCOMM4_IRQHandler + .type FLEXCOMM4_IRQHandler, %function +FLEXCOMM4_IRQHandler: + ldr r0,=FLEXCOMM4_DriverIRQHandler + bx r0 + .size FLEXCOMM4_IRQHandler, . - FLEXCOMM4_IRQHandler + + .align 1 + .thumb_func + .weak FLEXCOMM5_IRQHandler + .type FLEXCOMM5_IRQHandler, %function +FLEXCOMM5_IRQHandler: + ldr r0,=FLEXCOMM5_DriverIRQHandler + bx r0 + .size FLEXCOMM5_IRQHandler, . - FLEXCOMM5_IRQHandler + + .align 1 + .thumb_func + .weak FLEXCOMM6_IRQHandler + .type FLEXCOMM6_IRQHandler, %function +FLEXCOMM6_IRQHandler: + ldr r0,=FLEXCOMM6_DriverIRQHandler + bx r0 + .size FLEXCOMM6_IRQHandler, . - FLEXCOMM6_IRQHandler + + .align 1 + .thumb_func + .weak FLEXCOMM7_IRQHandler + .type FLEXCOMM7_IRQHandler, %function +FLEXCOMM7_IRQHandler: + ldr r0,=FLEXCOMM7_DriverIRQHandler + bx r0 + .size FLEXCOMM7_IRQHandler, . - FLEXCOMM7_IRQHandler + + .align 1 + .thumb_func + .weak ADC0_IRQHandler + .type ADC0_IRQHandler, %function +ADC0_IRQHandler: + ldr r0,=ADC0_DriverIRQHandler + bx r0 + .size ADC0_IRQHandler, . - ADC0_IRQHandler + + .align 1 + .thumb_func + .weak Reserved39_IRQHandler + .type Reserved39_IRQHandler, %function +Reserved39_IRQHandler: + ldr r0,=Reserved39_DriverIRQHandler + bx r0 + .size Reserved39_IRQHandler, . - Reserved39_IRQHandler + + .align 1 + .thumb_func + .weak ACMP_IRQHandler + .type ACMP_IRQHandler, %function +ACMP_IRQHandler: + ldr r0,=ACMP_DriverIRQHandler + bx r0 + .size ACMP_IRQHandler, . - ACMP_IRQHandler + + .align 1 + .thumb_func + .weak Reserved41_IRQHandler + .type Reserved41_IRQHandler, %function +Reserved41_IRQHandler: + ldr r0,=Reserved41_DriverIRQHandler + bx r0 + .size Reserved41_IRQHandler, . - Reserved41_IRQHandler + + .align 1 + .thumb_func + .weak Reserved42_IRQHandler + .type Reserved42_IRQHandler, %function +Reserved42_IRQHandler: + ldr r0,=Reserved42_DriverIRQHandler + bx r0 + .size Reserved42_IRQHandler, . - Reserved42_IRQHandler + + .align 1 + .thumb_func + .weak USB0_NEEDCLK_IRQHandler + .type USB0_NEEDCLK_IRQHandler, %function +USB0_NEEDCLK_IRQHandler: + ldr r0,=USB0_NEEDCLK_DriverIRQHandler + bx r0 + .size USB0_NEEDCLK_IRQHandler, . - USB0_NEEDCLK_IRQHandler + + .align 1 + .thumb_func + .weak USB0_IRQHandler + .type USB0_IRQHandler, %function +USB0_IRQHandler: + ldr r0,=USB0_DriverIRQHandler + bx r0 + .size USB0_IRQHandler, . - USB0_IRQHandler + + .align 1 + .thumb_func + .weak RTC_IRQHandler + .type RTC_IRQHandler, %function +RTC_IRQHandler: + ldr r0,=RTC_DriverIRQHandler + bx r0 + .size RTC_IRQHandler, . - RTC_IRQHandler + + .align 1 + .thumb_func + .weak Reserved46_IRQHandler + .type Reserved46_IRQHandler, %function +Reserved46_IRQHandler: + ldr r0,=Reserved46_DriverIRQHandler + bx r0 + .size Reserved46_IRQHandler, . - Reserved46_IRQHandler + + .align 1 + .thumb_func + .weak Reserved47_IRQHandler + .type Reserved47_IRQHandler, %function +Reserved47_IRQHandler: + ldr r0,=Reserved47_DriverIRQHandler + bx r0 + .size Reserved47_IRQHandler, . - Reserved47_IRQHandler + + .align 1 + .thumb_func + .weak PIN_INT4_IRQHandler + .type PIN_INT4_IRQHandler, %function +PIN_INT4_IRQHandler: + ldr r0,=PIN_INT4_DriverIRQHandler + bx r0 + .size PIN_INT4_IRQHandler, . - PIN_INT4_IRQHandler + + .align 1 + .thumb_func + .weak PIN_INT5_IRQHandler + .type PIN_INT5_IRQHandler, %function +PIN_INT5_IRQHandler: + ldr r0,=PIN_INT5_DriverIRQHandler + bx r0 + .size PIN_INT5_IRQHandler, . - PIN_INT5_IRQHandler + + .align 1 + .thumb_func + .weak PIN_INT6_IRQHandler + .type PIN_INT6_IRQHandler, %function +PIN_INT6_IRQHandler: + ldr r0,=PIN_INT6_DriverIRQHandler + bx r0 + .size PIN_INT6_IRQHandler, . - PIN_INT6_IRQHandler + + .align 1 + .thumb_func + .weak PIN_INT7_IRQHandler + .type PIN_INT7_IRQHandler, %function +PIN_INT7_IRQHandler: + ldr r0,=PIN_INT7_DriverIRQHandler + bx r0 + .size PIN_INT7_IRQHandler, . - PIN_INT7_IRQHandler + + .align 1 + .thumb_func + .weak CTIMER2_IRQHandler + .type CTIMER2_IRQHandler, %function +CTIMER2_IRQHandler: + ldr r0,=CTIMER2_DriverIRQHandler + bx r0 + .size CTIMER2_IRQHandler, . - CTIMER2_IRQHandler + + .align 1 + .thumb_func + .weak CTIMER4_IRQHandler + .type CTIMER4_IRQHandler, %function +CTIMER4_IRQHandler: + ldr r0,=CTIMER4_DriverIRQHandler + bx r0 + .size CTIMER4_IRQHandler, . - CTIMER4_IRQHandler + + .align 1 + .thumb_func + .weak OS_EVENT_IRQHandler + .type OS_EVENT_IRQHandler, %function +OS_EVENT_IRQHandler: + ldr r0,=OS_EVENT_DriverIRQHandler + bx r0 + .size OS_EVENT_IRQHandler, . - OS_EVENT_IRQHandler + + .align 1 + .thumb_func + .weak Reserved55_IRQHandler + .type Reserved55_IRQHandler, %function +Reserved55_IRQHandler: + ldr r0,=Reserved55_DriverIRQHandler + bx r0 + .size Reserved55_IRQHandler, . - Reserved55_IRQHandler + + .align 1 + .thumb_func + .weak Reserved56_IRQHandler + .type Reserved56_IRQHandler, %function +Reserved56_IRQHandler: + ldr r0,=Reserved56_DriverIRQHandler + bx r0 + .size Reserved56_IRQHandler, . - Reserved56_IRQHandler + + .align 1 + .thumb_func + .weak Reserved57_IRQHandler + .type Reserved57_IRQHandler, %function +Reserved57_IRQHandler: + ldr r0,=Reserved57_DriverIRQHandler + bx r0 + .size Reserved57_IRQHandler, . - Reserved57_IRQHandler + + .align 1 + .thumb_func + .weak Reserved58_IRQHandler + .type Reserved58_IRQHandler, %function +Reserved58_IRQHandler: + ldr r0,=Reserved58_DriverIRQHandler + bx r0 + .size Reserved58_IRQHandler, . - Reserved58_IRQHandler + + .align 1 + .thumb_func + .weak CAN0_IRQ0_IRQHandler + .type CAN0_IRQ0_IRQHandler, %function +CAN0_IRQ0_IRQHandler: + ldr r0,=CAN0_IRQ0_DriverIRQHandler + bx r0 + .size CAN0_IRQ0_IRQHandler, . - CAN0_IRQ0_IRQHandler + + .align 1 + .thumb_func + .weak CAN0_IRQ1_IRQHandler + .type CAN0_IRQ1_IRQHandler, %function +CAN0_IRQ1_IRQHandler: + ldr r0,=CAN0_IRQ1_DriverIRQHandler + bx r0 + .size CAN0_IRQ1_IRQHandler, . - CAN0_IRQ1_IRQHandler + + .align 1 + .thumb_func + .weak Reserved61_IRQHandler + .type Reserved61_IRQHandler, %function +Reserved61_IRQHandler: + ldr r0,=Reserved61_DriverIRQHandler + bx r0 + .size Reserved61_IRQHandler, . - Reserved61_IRQHandler + + .align 1 + .thumb_func + .weak USB1_PHY_IRQHandler + .type USB1_PHY_IRQHandler, %function +USB1_PHY_IRQHandler: + ldr r0,=USB1_PHY_DriverIRQHandler + bx r0 + .size USB1_PHY_IRQHandler, . - USB1_PHY_IRQHandler + + .align 1 + .thumb_func + .weak USB1_IRQHandler + .type USB1_IRQHandler, %function +USB1_IRQHandler: + ldr r0,=USB1_DriverIRQHandler + bx r0 + .size USB1_IRQHandler, . - USB1_IRQHandler + + .align 1 + .thumb_func + .weak USB1_NEEDCLK_IRQHandler + .type USB1_NEEDCLK_IRQHandler, %function +USB1_NEEDCLK_IRQHandler: + ldr r0,=USB1_NEEDCLK_DriverIRQHandler + bx r0 + .size USB1_NEEDCLK_IRQHandler, . - USB1_NEEDCLK_IRQHandler + + .align 1 + .thumb_func + .weak SEC_HYPERVISOR_CALL_IRQHandler + .type SEC_HYPERVISOR_CALL_IRQHandler, %function +SEC_HYPERVISOR_CALL_IRQHandler: + ldr r0,=SEC_HYPERVISOR_CALL_DriverIRQHandler + bx r0 + .size SEC_HYPERVISOR_CALL_IRQHandler, . - SEC_HYPERVISOR_CALL_IRQHandler + + .align 1 + .thumb_func + .weak SEC_GPIO_INT0_IRQ0_IRQHandler + .type SEC_GPIO_INT0_IRQ0_IRQHandler, %function +SEC_GPIO_INT0_IRQ0_IRQHandler: + ldr r0,=SEC_GPIO_INT0_IRQ0_DriverIRQHandler + bx r0 + .size SEC_GPIO_INT0_IRQ0_IRQHandler, . - SEC_GPIO_INT0_IRQ0_IRQHandler + + .align 1 + .thumb_func + .weak SEC_GPIO_INT0_IRQ1_IRQHandler + .type SEC_GPIO_INT0_IRQ1_IRQHandler, %function +SEC_GPIO_INT0_IRQ1_IRQHandler: + ldr r0,=SEC_GPIO_INT0_IRQ1_DriverIRQHandler + bx r0 + .size SEC_GPIO_INT0_IRQ1_IRQHandler, . - SEC_GPIO_INT0_IRQ1_IRQHandler + + .align 1 + .thumb_func + .weak PLU_IRQHandler + .type PLU_IRQHandler, %function +PLU_IRQHandler: + ldr r0,=PLU_DriverIRQHandler + bx r0 + .size PLU_IRQHandler, . - PLU_IRQHandler + + .align 1 + .thumb_func + .weak SEC_VIO_IRQHandler + .type SEC_VIO_IRQHandler, %function +SEC_VIO_IRQHandler: + ldr r0,=SEC_VIO_DriverIRQHandler + bx r0 + .size SEC_VIO_IRQHandler, . - SEC_VIO_IRQHandler + + .align 1 + .thumb_func + .weak HASHCRYPT_IRQHandler + .type HASHCRYPT_IRQHandler, %function +HASHCRYPT_IRQHandler: + ldr r0,=HASHCRYPT_DriverIRQHandler + bx r0 + .size HASHCRYPT_IRQHandler, . - HASHCRYPT_IRQHandler + + .align 1 + .thumb_func + .weak CASER_IRQHandler + .type CASER_IRQHandler, %function +CASER_IRQHandler: + ldr r0,=CASER_DriverIRQHandler + bx r0 + .size CASER_IRQHandler, . - CASER_IRQHandler + + .align 1 + .thumb_func + .weak PUF_IRQHandler + .type PUF_IRQHandler, %function +PUF_IRQHandler: + ldr r0,=PUF_DriverIRQHandler + bx r0 + .size PUF_IRQHandler, . - PUF_IRQHandler + + .align 1 + .thumb_func + .weak Reserved73_IRQHandler + .type Reserved73_IRQHandler, %function +Reserved73_IRQHandler: + ldr r0,=Reserved73_DriverIRQHandler + bx r0 + .size Reserved73_IRQHandler, . - Reserved73_IRQHandler + + .align 1 + .thumb_func + .weak DMA1_IRQHandler + .type DMA1_IRQHandler, %function +DMA1_IRQHandler: + ldr r0,=DMA1_DriverIRQHandler + bx r0 + .size DMA1_IRQHandler, . - DMA1_IRQHandler + + .align 1 + .thumb_func + .weak FLEXCOMM8_IRQHandler + .type FLEXCOMM8_IRQHandler, %function +FLEXCOMM8_IRQHandler: + ldr r0,=FLEXCOMM8_DriverIRQHandler + bx r0 + .size FLEXCOMM8_IRQHandler, . - FLEXCOMM8_IRQHandler + + .align 1 + .thumb_func + .weak CDOG_IRQHandler + .type CDOG_IRQHandler, %function +CDOG_IRQHandler: + ldr r0,=CDOG_DriverIRQHandler + bx r0 + .size CDOG_IRQHandler, . - CDOG_IRQHandler + +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_irq_handler handler_name + .weak \handler_name + .set \handler_name, DefaultISR + .endm +/* Exception Handlers */ + def_irq_handler MemManage_Handler + def_irq_handler BusFault_Handler + def_irq_handler UsageFault_Handler + def_irq_handler SecureFault_Handler + def_irq_handler DebugMon_Handler + def_irq_handler WDT_BOD_DriverIRQHandler + def_irq_handler DMA0_DriverIRQHandler + def_irq_handler GINT0_DriverIRQHandler + def_irq_handler GINT1_DriverIRQHandler + def_irq_handler PIN_INT0_DriverIRQHandler + def_irq_handler PIN_INT1_DriverIRQHandler + def_irq_handler PIN_INT2_DriverIRQHandler + def_irq_handler PIN_INT3_DriverIRQHandler + def_irq_handler UTICK0_DriverIRQHandler + def_irq_handler MRT0_DriverIRQHandler + def_irq_handler CTIMER0_DriverIRQHandler + def_irq_handler CTIMER1_DriverIRQHandler + def_irq_handler SCT0_DriverIRQHandler + def_irq_handler CTIMER3_DriverIRQHandler + def_irq_handler FLEXCOMM0_DriverIRQHandler + def_irq_handler FLEXCOMM1_DriverIRQHandler + def_irq_handler FLEXCOMM2_DriverIRQHandler + def_irq_handler FLEXCOMM3_DriverIRQHandler + def_irq_handler FLEXCOMM4_DriverIRQHandler + def_irq_handler FLEXCOMM5_DriverIRQHandler + def_irq_handler FLEXCOMM6_DriverIRQHandler + def_irq_handler FLEXCOMM7_DriverIRQHandler + def_irq_handler ADC0_DriverIRQHandler + def_irq_handler Reserved39_DriverIRQHandler + def_irq_handler ACMP_DriverIRQHandler + def_irq_handler Reserved41_DriverIRQHandler + def_irq_handler Reserved42_DriverIRQHandler + def_irq_handler USB0_NEEDCLK_DriverIRQHandler + def_irq_handler USB0_DriverIRQHandler + def_irq_handler RTC_DriverIRQHandler + def_irq_handler Reserved46_DriverIRQHandler + def_irq_handler Reserved47_DriverIRQHandler + def_irq_handler PIN_INT4_DriverIRQHandler + def_irq_handler PIN_INT5_DriverIRQHandler + def_irq_handler PIN_INT6_DriverIRQHandler + def_irq_handler PIN_INT7_DriverIRQHandler + def_irq_handler CTIMER2_DriverIRQHandler + def_irq_handler CTIMER4_DriverIRQHandler + def_irq_handler OS_EVENT_DriverIRQHandler + def_irq_handler Reserved55_DriverIRQHandler + def_irq_handler Reserved56_DriverIRQHandler + def_irq_handler Reserved57_DriverIRQHandler + def_irq_handler Reserved58_DriverIRQHandler + def_irq_handler CAN0_IRQ0_DriverIRQHandler + def_irq_handler CAN0_IRQ1_DriverIRQHandler + def_irq_handler Reserved61_DriverIRQHandler + def_irq_handler USB1_PHY_DriverIRQHandler + def_irq_handler USB1_DriverIRQHandler + def_irq_handler USB1_NEEDCLK_DriverIRQHandler + def_irq_handler SEC_HYPERVISOR_CALL_DriverIRQHandler + def_irq_handler SEC_GPIO_INT0_IRQ0_DriverIRQHandler + def_irq_handler SEC_GPIO_INT0_IRQ1_DriverIRQHandler + def_irq_handler PLU_DriverIRQHandler + def_irq_handler SEC_VIO_DriverIRQHandler + def_irq_handler HASHCRYPT_DriverIRQHandler + def_irq_handler CASER_DriverIRQHandler + def_irq_handler PUF_DriverIRQHandler + def_irq_handler Reserved73_DriverIRQHandler + def_irq_handler DMA1_DriverIRQHandler + def_irq_handler FLEXCOMM8_DriverIRQHandler + def_irq_handler CDOG_DriverIRQHandler + + .end diff --git a/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/iar/LPC55S16_flash.icf b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/iar/LPC55S16_flash.icf new file mode 100644 index 0000000000..1fa04c399b --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/iar/LPC55S16_flash.icf @@ -0,0 +1,101 @@ +/* +** ################################################################### +** Processors: LPC55S16JBD100 +** LPC55S16JBD64 +** LPC55S16JEV59 +** LPC55S16JEV98 +** +** Compiler: IAR ANSI C/C++ Compiler for ARM +** Reference manual: LPC55S1x/LPC551x User manual Rev.0.6 15 November 2019 +** Version: rev. 1.1, 2019-12-03 +** Build: b220622 +** +** Abstract: +** Linker file for the IAR ANSI C/C++ Compiler for ARM +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2022 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + + +/* USB BDT size */ +define symbol usb_bdt_size = 0x0; +/* Stack and Heap Sizes */ +if (isdefinedsymbol(__stack_size__)) { + define symbol __size_cstack__ = __stack_size__; +} else { + define symbol __size_cstack__ = 0x0400; +} + +if (isdefinedsymbol(__heap_size__)) { + define symbol __size_heap__ = __heap_size__; +} else { + define symbol __size_heap__ = 0x0400; +} + +define symbol m_interrupts_start = 0x00000000; +define symbol m_interrupts_end = 0x000001FF; + +define symbol m_text_start = 0x00000200; +define symbol m_text_end = 0x0003CFFF; + +define symbol m_data_start = 0x20000000; +define symbol m_data_end = 0x2000FFFF; + +define symbol m_sramx_start = 0x04000000; +define symbol m_sramx_end = 0x04003FFF; + +define symbol m_usb_sram_start = 0x20010000; +define symbol m_usb_sram_end = 0x20013FFF; + +define memory mem with size = 4G; + +define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end] + | mem:[from m_text_start to m_text_end]; +define region DATA_region = mem:[from m_data_start to m_data_end-__size_cstack__]; +define region CSTACK_region = mem:[from m_data_end-__size_cstack__+1 to m_data_end]; +if (isdefinedsymbol(__use_shmem__)) { + define region rpmsg_sh_mem_region = mem:[from rpmsg_sh_mem_start to rpmsg_sh_mem_end]; +} + +define block CSTACK with alignment = 8, size = __size_cstack__ { }; +define block HEAP with alignment = 8, size = __size_heap__ { }; +define block RW { readwrite }; +define block ZI { zi }; + +/* regions for USB */ +define region USB_BDT_region = mem:[from m_usb_sram_start to m_usb_sram_start + usb_bdt_size - 1]; +define region USB_SRAM_region = mem:[from m_usb_sram_start + usb_bdt_size to m_usb_sram_end]; +place in USB_BDT_region { section m_usb_bdt }; +place in USB_SRAM_region { section m_usb_global }; + +initialize by copy { readwrite, section .textrw }; + +if (isdefinedsymbol(__USE_DLIB_PERTHREAD)) +{ + /* Required in a multi-threaded application */ + initialize by copy with packing = none { section __DLIB_PERTHREAD }; +} + +do not initialize { section .noinit, section m_usb_bdt, section m_usb_global }; +if (isdefinedsymbol(__use_shmem__)) { + do not initialize { section rpmsg_sh_mem_section }; +} + +place at address mem: m_interrupts_start { readonly section .intvec }; +place in TEXT_region { readonly }; +place in DATA_region { block RW }; +place in DATA_region { block ZI }; +place in DATA_region { last block HEAP }; +place in CSTACK_region { block CSTACK }; + + + diff --git a/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/iar/LPC55S16_ram.icf b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/iar/LPC55S16_ram.icf new file mode 100644 index 0000000000..2f7306acbc --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/iar/LPC55S16_ram.icf @@ -0,0 +1,98 @@ +/* +** ################################################################### +** Processors: LPC55S16JBD100 +** LPC55S16JBD64 +** LPC55S16JEV59 +** LPC55S16JEV98 +** +** Compiler: IAR ANSI C/C++ Compiler for ARM +** Reference manual: LPC55S1x/LPC551x User manual Rev.0.6 15 November 2019 +** Version: rev. 1.1, 2019-12-03 +** Build: b220622 +** +** Abstract: +** Linker file for the IAR ANSI C/C++ Compiler for ARM +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2022 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + + +/* USB BDT size */ +define symbol usb_bdt_size = 0x0; +/* Stack and Heap Sizes */ +if (isdefinedsymbol(__stack_size__)) { + define symbol __size_cstack__ = __stack_size__; +} else { + define symbol __size_cstack__ = 0x0400; +} + +if (isdefinedsymbol(__heap_size__)) { + define symbol __size_heap__ = __heap_size__; +} else { + define symbol __size_heap__ = 0x0400; +} + +define symbol m_interrupts_start = 0x20000000; +define symbol m_interrupts_end = 0x200001FF; + +define symbol m_text_start = 0x20000200; +define symbol m_text_end = 0x2000FFFF; + +define symbol m_data_start = 0x04000000; +define symbol m_data_end = 0x04003FFF; + +define symbol m_usb_sram_start = 0x20010000; +define symbol m_usb_sram_end = 0x20013FFF; + +define memory mem with size = 4G; + +define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end] + | mem:[from m_text_start to m_text_end]; +define region DATA_region = mem:[from m_data_start to m_data_end-__size_cstack__]; +define region CSTACK_region = mem:[from m_data_end-__size_cstack__+1 to m_data_end]; +if (isdefinedsymbol(__use_shmem__)) { + define region rpmsg_sh_mem_region = mem:[from rpmsg_sh_mem_start to rpmsg_sh_mem_end]; +} + +define block CSTACK with alignment = 8, size = __size_cstack__ { }; +define block HEAP with alignment = 8, size = __size_heap__ { }; +define block RW { readwrite }; +define block ZI { zi }; + +/* regions for USB */ +define region USB_BDT_region = mem:[from m_usb_sram_start to m_usb_sram_start + usb_bdt_size - 1]; +define region USB_SRAM_region = mem:[from m_usb_sram_start + usb_bdt_size to m_usb_sram_end]; +place in USB_BDT_region { section m_usb_bdt }; +place in USB_SRAM_region { section m_usb_global }; + +initialize by copy { readwrite, section .textrw }; + +if (isdefinedsymbol(__USE_DLIB_PERTHREAD)) +{ + /* Required in a multi-threaded application */ + initialize by copy with packing = none { section __DLIB_PERTHREAD }; +} + +do not initialize { section .noinit, section m_usb_bdt, section m_usb_global }; +if (isdefinedsymbol(__use_shmem__)) { + do not initialize { section rpmsg_sh_mem_section }; +} + +place at address mem: m_interrupts_start { readonly section .intvec }; +place in TEXT_region { readonly }; +place in DATA_region { block RW }; +place in DATA_region { block ZI }; +place in DATA_region { last block HEAP }; +place in CSTACK_region { block CSTACK }; + + + diff --git a/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/iar/startup_LPC55S16.s b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/iar/startup_LPC55S16.s new file mode 100644 index 0000000000..7a592dc667 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/iar/startup_LPC55S16.s @@ -0,0 +1,643 @@ +;/***************************************************************************** +; * @file: startup_LPC55S16.s +; * @purpose: CMSIS Cortex-M33 Core Device Startup File +; * LPC55S16 +; * @version: 1.1 +; * @date: 2019-12-3 +; *---------------------------------------------------------------------------- +; * +; Copyright 1997-2016 Freescale Semiconductor, Inc. +; Copyright 2016-2021 NXP +; All rights reserved. +; +; SPDX-License-Identifier: BSD-3-Clause +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + PUBLIC __vector_table_0x1c + PUBLIC __Vectors + PUBLIC __Vectors_End + PUBLIC __Vectors_Size + + DATA + +__iar_init$$done: ; The vector table is not needed + ; until after copy initialization is done + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler + + DCD NMI_Handler + DCD HardFault_Handler + DCD MemManage_Handler + DCD BusFault_Handler + DCD UsageFault_Handler +__vector_table_0x1c + DCD SecureFault_Handler + DCD 0 + DCD 0 + DCD 0 + DCD SVC_Handler + DCD DebugMon_Handler + DCD 0 + DCD PendSV_Handler + DCD SysTick_Handler + + ; External Interrupts + DCD WDT_BOD_IRQHandler ; Windowed watchdog timer, Brownout detect, Flash interrupt + DCD DMA0_IRQHandler ; DMA0 controller + DCD GINT0_IRQHandler ; GPIO group 0 + DCD GINT1_IRQHandler ; GPIO group 1 + DCD PIN_INT0_IRQHandler ; Pin interrupt 0 or pattern match engine slice 0 + DCD PIN_INT1_IRQHandler ; Pin interrupt 1or pattern match engine slice 1 + DCD PIN_INT2_IRQHandler ; Pin interrupt 2 or pattern match engine slice 2 + DCD PIN_INT3_IRQHandler ; Pin interrupt 3 or pattern match engine slice 3 + DCD UTICK0_IRQHandler ; Micro-tick Timer + DCD MRT0_IRQHandler ; Multi-rate timer + DCD CTIMER0_IRQHandler ; Standard counter/timer CTIMER0 + DCD CTIMER1_IRQHandler ; Standard counter/timer CTIMER1 + DCD SCT0_IRQHandler ; SCTimer/PWM + DCD CTIMER3_IRQHandler ; Standard counter/timer CTIMER3 + DCD FLEXCOMM0_IRQHandler ; Flexcomm Interface 0 (USART, SPI, I2C, I2S, FLEXCOMM) + DCD FLEXCOMM1_IRQHandler ; Flexcomm Interface 1 (USART, SPI, I2C, I2S, FLEXCOMM) + DCD FLEXCOMM2_IRQHandler ; Flexcomm Interface 2 (USART, SPI, I2C, I2S, FLEXCOMM) + DCD FLEXCOMM3_IRQHandler ; Flexcomm Interface 3 (USART, SPI, I2C, I2S, FLEXCOMM) + DCD FLEXCOMM4_IRQHandler ; Flexcomm Interface 4 (USART, SPI, I2C, I2S, FLEXCOMM) + DCD FLEXCOMM5_IRQHandler ; Flexcomm Interface 5 (USART, SPI, I2C, I2S, FLEXCOMM) + DCD FLEXCOMM6_IRQHandler ; Flexcomm Interface 6 (USART, SPI, I2C, I2S, FLEXCOMM) + DCD FLEXCOMM7_IRQHandler ; Flexcomm Interface 7 (USART, SPI, I2C, I2S, FLEXCOMM) + DCD ADC0_IRQHandler ; ADC0 + DCD Reserved39_IRQHandler ; Reserved interrupt + DCD ACMP_IRQHandler ; ACMP interrupts + DCD Reserved41_IRQHandler ; Reserved interrupt + DCD Reserved42_IRQHandler ; Reserved interrupt + DCD USB0_NEEDCLK_IRQHandler ; USB Activity Wake-up Interrupt + DCD USB0_IRQHandler ; USB device + DCD RTC_IRQHandler ; RTC alarm and wake-up interrupts + DCD Reserved46_IRQHandler ; Reserved interrupt + DCD Reserved47_IRQHandler ; Reserved interrupt + DCD PIN_INT4_IRQHandler ; Pin interrupt 4 or pattern match engine slice 4 int + DCD PIN_INT5_IRQHandler ; Pin interrupt 5 or pattern match engine slice 5 int + DCD PIN_INT6_IRQHandler ; Pin interrupt 6 or pattern match engine slice 6 int + DCD PIN_INT7_IRQHandler ; Pin interrupt 7 or pattern match engine slice 7 int + DCD CTIMER2_IRQHandler ; Standard counter/timer CTIMER2 + DCD CTIMER4_IRQHandler ; Standard counter/timer CTIMER4 + DCD OS_EVENT_IRQHandler ; OS_EVENT_TIMER and OS_EVENT_WAKEUP interrupts + DCD Reserved55_IRQHandler ; Reserved interrupt + DCD Reserved56_IRQHandler ; Reserved interrupt + DCD Reserved57_IRQHandler ; Reserved interrupt + DCD Reserved58_IRQHandler ; Reserved interrupt + DCD CAN0_IRQ0_IRQHandler ; CAN0 interrupt0 + DCD CAN0_IRQ1_IRQHandler ; CAN0 interrupt1 + DCD Reserved61_IRQHandler ; Reserved interrupt + DCD USB1_PHY_IRQHandler ; USB1_PHY + DCD USB1_IRQHandler ; USB1 interrupt + DCD USB1_NEEDCLK_IRQHandler ; USB1 activity + DCD SEC_HYPERVISOR_CALL_IRQHandler ; SEC_HYPERVISOR_CALL interrupt + DCD SEC_GPIO_INT0_IRQ0_IRQHandler ; SEC_GPIO_INT0_IRQ0 interrupt + DCD SEC_GPIO_INT0_IRQ1_IRQHandler ; SEC_GPIO_INT0_IRQ1 interrupt + DCD PLU_IRQHandler ; PLU interrupt + DCD SEC_VIO_IRQHandler ; SEC_VIO interrupt + DCD HASHCRYPT_IRQHandler ; SHA interrupt + DCD CASER_IRQHandler ; CASPER interrupt + DCD PUF_IRQHandler ; PUF interrupt + DCD Reserved73_IRQHandler ; Reserved interrupt + DCD DMA1_IRQHandler ; DMA1 interrupt + DCD FLEXCOMM8_IRQHandler ; Flexcomm Interface 8 (SPI, , FLEXCOMM) + DCD CDOG_IRQHandler ; CDOG interrupt +__Vectors_End + + +__Vectors EQU __vector_table +__Vectors_Size EQU __Vectors_End - __Vectors + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + CPSID I ; Mask interrupts + LDR R0, =0xE000ED08 + LDR R1, =__vector_table + STR R1, [R0] + LDR R2, [R1] + MSR MSP, R2 + LDR R0, =sfb(CSTACK) + MSR MSPLIM, R0 + CPSIE I ; Unmask interrupts + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B . + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B . + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +MemManage_Handler + B . + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +BusFault_Handler + B . + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UsageFault_Handler + B . + + PUBWEAK SecureFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SecureFault_Handler + B . + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B . + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DebugMon_Handler + B . + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B . + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B . + + PUBWEAK WDT_BOD_IRQHandler + PUBWEAK WDT_BOD_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +WDT_BOD_IRQHandler + LDR R0, =WDT_BOD_DriverIRQHandler + BX R0 + PUBWEAK DMA0_IRQHandler + PUBWEAK DMA0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA0_IRQHandler + LDR R0, =DMA0_DriverIRQHandler + BX R0 + PUBWEAK GINT0_IRQHandler + PUBWEAK GINT0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +GINT0_IRQHandler + LDR R0, =GINT0_DriverIRQHandler + BX R0 + PUBWEAK GINT1_IRQHandler + PUBWEAK GINT1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +GINT1_IRQHandler + LDR R0, =GINT1_DriverIRQHandler + BX R0 + PUBWEAK PIN_INT0_IRQHandler + PUBWEAK PIN_INT0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +PIN_INT0_IRQHandler + LDR R0, =PIN_INT0_DriverIRQHandler + BX R0 + PUBWEAK PIN_INT1_IRQHandler + PUBWEAK PIN_INT1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +PIN_INT1_IRQHandler + LDR R0, =PIN_INT1_DriverIRQHandler + BX R0 + PUBWEAK PIN_INT2_IRQHandler + PUBWEAK PIN_INT2_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +PIN_INT2_IRQHandler + LDR R0, =PIN_INT2_DriverIRQHandler + BX R0 + PUBWEAK PIN_INT3_IRQHandler + PUBWEAK PIN_INT3_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +PIN_INT3_IRQHandler + LDR R0, =PIN_INT3_DriverIRQHandler + BX R0 + PUBWEAK UTICK0_IRQHandler + PUBWEAK UTICK0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +UTICK0_IRQHandler + LDR R0, =UTICK0_DriverIRQHandler + BX R0 + PUBWEAK MRT0_IRQHandler + PUBWEAK MRT0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +MRT0_IRQHandler + LDR R0, =MRT0_DriverIRQHandler + BX R0 + PUBWEAK CTIMER0_IRQHandler + PUBWEAK CTIMER0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +CTIMER0_IRQHandler + LDR R0, =CTIMER0_DriverIRQHandler + BX R0 + PUBWEAK CTIMER1_IRQHandler + PUBWEAK CTIMER1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +CTIMER1_IRQHandler + LDR R0, =CTIMER1_DriverIRQHandler + BX R0 + PUBWEAK SCT0_IRQHandler + PUBWEAK SCT0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +SCT0_IRQHandler + LDR R0, =SCT0_DriverIRQHandler + BX R0 + PUBWEAK CTIMER3_IRQHandler + PUBWEAK CTIMER3_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +CTIMER3_IRQHandler + LDR R0, =CTIMER3_DriverIRQHandler + BX R0 + PUBWEAK FLEXCOMM0_IRQHandler + PUBWEAK FLEXCOMM0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXCOMM0_IRQHandler + LDR R0, =FLEXCOMM0_DriverIRQHandler + BX R0 + PUBWEAK FLEXCOMM1_IRQHandler + PUBWEAK FLEXCOMM1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXCOMM1_IRQHandler + LDR R0, =FLEXCOMM1_DriverIRQHandler + BX R0 + PUBWEAK FLEXCOMM2_IRQHandler + PUBWEAK FLEXCOMM2_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXCOMM2_IRQHandler + LDR R0, =FLEXCOMM2_DriverIRQHandler + BX R0 + PUBWEAK FLEXCOMM3_IRQHandler + PUBWEAK FLEXCOMM3_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXCOMM3_IRQHandler + LDR R0, =FLEXCOMM3_DriverIRQHandler + BX R0 + PUBWEAK FLEXCOMM4_IRQHandler + PUBWEAK FLEXCOMM4_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXCOMM4_IRQHandler + LDR R0, =FLEXCOMM4_DriverIRQHandler + BX R0 + PUBWEAK FLEXCOMM5_IRQHandler + PUBWEAK FLEXCOMM5_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXCOMM5_IRQHandler + LDR R0, =FLEXCOMM5_DriverIRQHandler + BX R0 + PUBWEAK FLEXCOMM6_IRQHandler + PUBWEAK FLEXCOMM6_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXCOMM6_IRQHandler + LDR R0, =FLEXCOMM6_DriverIRQHandler + BX R0 + PUBWEAK FLEXCOMM7_IRQHandler + PUBWEAK FLEXCOMM7_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXCOMM7_IRQHandler + LDR R0, =FLEXCOMM7_DriverIRQHandler + BX R0 + PUBWEAK ADC0_IRQHandler + PUBWEAK ADC0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +ADC0_IRQHandler + LDR R0, =ADC0_DriverIRQHandler + BX R0 + PUBWEAK Reserved39_IRQHandler + PUBWEAK Reserved39_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +Reserved39_IRQHandler + LDR R0, =Reserved39_DriverIRQHandler + BX R0 + PUBWEAK ACMP_IRQHandler + PUBWEAK ACMP_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +ACMP_IRQHandler + LDR R0, =ACMP_DriverIRQHandler + BX R0 + PUBWEAK Reserved41_IRQHandler + PUBWEAK Reserved41_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +Reserved41_IRQHandler + LDR R0, =Reserved41_DriverIRQHandler + BX R0 + PUBWEAK Reserved42_IRQHandler + PUBWEAK Reserved42_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +Reserved42_IRQHandler + LDR R0, =Reserved42_DriverIRQHandler + BX R0 + PUBWEAK USB0_NEEDCLK_IRQHandler + PUBWEAK USB0_NEEDCLK_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +USB0_NEEDCLK_IRQHandler + LDR R0, =USB0_NEEDCLK_DriverIRQHandler + BX R0 + PUBWEAK USB0_IRQHandler + PUBWEAK USB0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +USB0_IRQHandler + LDR R0, =USB0_DriverIRQHandler + BX R0 + PUBWEAK RTC_IRQHandler + PUBWEAK RTC_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +RTC_IRQHandler + LDR R0, =RTC_DriverIRQHandler + BX R0 + PUBWEAK Reserved46_IRQHandler + PUBWEAK Reserved46_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +Reserved46_IRQHandler + LDR R0, =Reserved46_DriverIRQHandler + BX R0 + PUBWEAK Reserved47_IRQHandler + PUBWEAK Reserved47_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +Reserved47_IRQHandler + LDR R0, =Reserved47_DriverIRQHandler + BX R0 + PUBWEAK PIN_INT4_IRQHandler + PUBWEAK PIN_INT4_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +PIN_INT4_IRQHandler + LDR R0, =PIN_INT4_DriverIRQHandler + BX R0 + PUBWEAK PIN_INT5_IRQHandler + PUBWEAK PIN_INT5_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +PIN_INT5_IRQHandler + LDR R0, =PIN_INT5_DriverIRQHandler + BX R0 + PUBWEAK PIN_INT6_IRQHandler + PUBWEAK PIN_INT6_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +PIN_INT6_IRQHandler + LDR R0, =PIN_INT6_DriverIRQHandler + BX R0 + PUBWEAK PIN_INT7_IRQHandler + PUBWEAK PIN_INT7_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +PIN_INT7_IRQHandler + LDR R0, =PIN_INT7_DriverIRQHandler + BX R0 + PUBWEAK CTIMER2_IRQHandler + PUBWEAK CTIMER2_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +CTIMER2_IRQHandler + LDR R0, =CTIMER2_DriverIRQHandler + BX R0 + PUBWEAK CTIMER4_IRQHandler + PUBWEAK CTIMER4_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +CTIMER4_IRQHandler + LDR R0, =CTIMER4_DriverIRQHandler + BX R0 + PUBWEAK OS_EVENT_IRQHandler + PUBWEAK OS_EVENT_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +OS_EVENT_IRQHandler + LDR R0, =OS_EVENT_DriverIRQHandler + BX R0 + PUBWEAK Reserved55_IRQHandler + PUBWEAK Reserved55_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +Reserved55_IRQHandler + LDR R0, =Reserved55_DriverIRQHandler + BX R0 + PUBWEAK Reserved56_IRQHandler + PUBWEAK Reserved56_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +Reserved56_IRQHandler + LDR R0, =Reserved56_DriverIRQHandler + BX R0 + PUBWEAK Reserved57_IRQHandler + PUBWEAK Reserved57_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +Reserved57_IRQHandler + LDR R0, =Reserved57_DriverIRQHandler + BX R0 + PUBWEAK Reserved58_IRQHandler + PUBWEAK Reserved58_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +Reserved58_IRQHandler + LDR R0, =Reserved58_DriverIRQHandler + BX R0 + PUBWEAK CAN0_IRQ0_IRQHandler + PUBWEAK CAN0_IRQ0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +CAN0_IRQ0_IRQHandler + LDR R0, =CAN0_IRQ0_DriverIRQHandler + BX R0 + PUBWEAK CAN0_IRQ1_IRQHandler + PUBWEAK CAN0_IRQ1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +CAN0_IRQ1_IRQHandler + LDR R0, =CAN0_IRQ1_DriverIRQHandler + BX R0 + PUBWEAK Reserved61_IRQHandler + PUBWEAK Reserved61_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +Reserved61_IRQHandler + LDR R0, =Reserved61_DriverIRQHandler + BX R0 + PUBWEAK USB1_PHY_IRQHandler + PUBWEAK USB1_PHY_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +USB1_PHY_IRQHandler + LDR R0, =USB1_PHY_DriverIRQHandler + BX R0 + PUBWEAK USB1_IRQHandler + PUBWEAK USB1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +USB1_IRQHandler + LDR R0, =USB1_DriverIRQHandler + BX R0 + PUBWEAK USB1_NEEDCLK_IRQHandler + PUBWEAK USB1_NEEDCLK_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +USB1_NEEDCLK_IRQHandler + LDR R0, =USB1_NEEDCLK_DriverIRQHandler + BX R0 + PUBWEAK SEC_HYPERVISOR_CALL_IRQHandler + PUBWEAK SEC_HYPERVISOR_CALL_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +SEC_HYPERVISOR_CALL_IRQHandler + LDR R0, =SEC_HYPERVISOR_CALL_DriverIRQHandler + BX R0 + PUBWEAK SEC_GPIO_INT0_IRQ0_IRQHandler + PUBWEAK SEC_GPIO_INT0_IRQ0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +SEC_GPIO_INT0_IRQ0_IRQHandler + LDR R0, =SEC_GPIO_INT0_IRQ0_DriverIRQHandler + BX R0 + PUBWEAK SEC_GPIO_INT0_IRQ1_IRQHandler + PUBWEAK SEC_GPIO_INT0_IRQ1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +SEC_GPIO_INT0_IRQ1_IRQHandler + LDR R0, =SEC_GPIO_INT0_IRQ1_DriverIRQHandler + BX R0 + PUBWEAK PLU_IRQHandler + PUBWEAK PLU_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +PLU_IRQHandler + LDR R0, =PLU_DriverIRQHandler + BX R0 + PUBWEAK SEC_VIO_IRQHandler + PUBWEAK SEC_VIO_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +SEC_VIO_IRQHandler + LDR R0, =SEC_VIO_DriverIRQHandler + BX R0 + PUBWEAK HASHCRYPT_IRQHandler + PUBWEAK HASHCRYPT_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +HASHCRYPT_IRQHandler + LDR R0, =HASHCRYPT_DriverIRQHandler + BX R0 + PUBWEAK CASER_IRQHandler + PUBWEAK CASER_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +CASER_IRQHandler + LDR R0, =CASER_DriverIRQHandler + BX R0 + PUBWEAK PUF_IRQHandler + PUBWEAK PUF_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +PUF_IRQHandler + LDR R0, =PUF_DriverIRQHandler + BX R0 + PUBWEAK Reserved73_IRQHandler + PUBWEAK Reserved73_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +Reserved73_IRQHandler + LDR R0, =Reserved73_DriverIRQHandler + BX R0 + PUBWEAK DMA1_IRQHandler + PUBWEAK DMA1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA1_IRQHandler + LDR R0, =DMA1_DriverIRQHandler + BX R0 + PUBWEAK FLEXCOMM8_IRQHandler + PUBWEAK FLEXCOMM8_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXCOMM8_IRQHandler + LDR R0, =FLEXCOMM8_DriverIRQHandler + BX R0 + PUBWEAK CDOG_IRQHandler + PUBWEAK CDOG_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +CDOG_IRQHandler + LDR R0, =CDOG_DriverIRQHandler + BX R0 +WDT_BOD_DriverIRQHandler +DMA0_DriverIRQHandler +GINT0_DriverIRQHandler +GINT1_DriverIRQHandler +PIN_INT0_DriverIRQHandler +PIN_INT1_DriverIRQHandler +PIN_INT2_DriverIRQHandler +PIN_INT3_DriverIRQHandler +UTICK0_DriverIRQHandler +MRT0_DriverIRQHandler +CTIMER0_DriverIRQHandler +CTIMER1_DriverIRQHandler +SCT0_DriverIRQHandler +CTIMER3_DriverIRQHandler +FLEXCOMM0_DriverIRQHandler +FLEXCOMM1_DriverIRQHandler +FLEXCOMM2_DriverIRQHandler +FLEXCOMM3_DriverIRQHandler +FLEXCOMM4_DriverIRQHandler +FLEXCOMM5_DriverIRQHandler +FLEXCOMM6_DriverIRQHandler +FLEXCOMM7_DriverIRQHandler +ADC0_DriverIRQHandler +Reserved39_DriverIRQHandler +ACMP_DriverIRQHandler +Reserved41_DriverIRQHandler +Reserved42_DriverIRQHandler +USB0_NEEDCLK_DriverIRQHandler +USB0_DriverIRQHandler +RTC_DriverIRQHandler +Reserved46_DriverIRQHandler +Reserved47_DriverIRQHandler +PIN_INT4_DriverIRQHandler +PIN_INT5_DriverIRQHandler +PIN_INT6_DriverIRQHandler +PIN_INT7_DriverIRQHandler +CTIMER2_DriverIRQHandler +CTIMER4_DriverIRQHandler +OS_EVENT_DriverIRQHandler +Reserved55_DriverIRQHandler +Reserved56_DriverIRQHandler +Reserved57_DriverIRQHandler +Reserved58_DriverIRQHandler +CAN0_IRQ0_DriverIRQHandler +CAN0_IRQ1_DriverIRQHandler +Reserved61_DriverIRQHandler +USB1_PHY_DriverIRQHandler +USB1_DriverIRQHandler +USB1_NEEDCLK_DriverIRQHandler +SEC_HYPERVISOR_CALL_DriverIRQHandler +SEC_GPIO_INT0_IRQ0_DriverIRQHandler +SEC_GPIO_INT0_IRQ1_DriverIRQHandler +PLU_DriverIRQHandler +SEC_VIO_DriverIRQHandler +HASHCRYPT_DriverIRQHandler +CASER_DriverIRQHandler +PUF_DriverIRQHandler +Reserved73_DriverIRQHandler +DMA1_DriverIRQHandler +FLEXCOMM8_DriverIRQHandler +CDOG_DriverIRQHandler +DefaultISR + B . + + END diff --git a/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/system_LPC55S16.c b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/system_LPC55S16.c new file mode 100644 index 0000000000..f9e725a140 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/system_LPC55S16.c @@ -0,0 +1,392 @@ +/* +** ################################################################### +** Processors: LPC55S16JBD100 +** LPC55S16JBD64 +** LPC55S16JEV98 +** +** Compilers: GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** Keil ARM C/C++ Compiler +** MCUXpresso Compiler +** +** Reference manual: LPC55S1x/LPC551x User manual Rev.0.6 15 November 2019 +** Version: rev. 1.1, 2019-12-03 +** Build: b220117 +** +** Abstract: +** Provides a system configuration function and a global variable that +** contains the system frequency. It configures the device and initializes +** the oscillator (PLL) that is part of the microcontroller device. +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2022 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2018-08-22) +** Initial version based on v0.2UM +** - rev. 1.1 (2019-12-03) +** Initial version based on v0.6UM +** +** ################################################################### +*/ + +/*! + * @file LPC55S16 + * @version 1.1 + * @date 2019-12-03 + * @brief Device specific configuration file for LPC55S16 (implementation file) + * + * Provides a system configuration function and a global variable that contains + * the system frequency. It configures the device and initializes the oscillator + * (PLL) that is part of the microcontroller device. + */ + +#include +#include "fsl_device_registers.h" + +/* PLL0 SSCG control1 */ +#define PLL_SSCG_MD_FRACT_P 0U +#define PLL_SSCG_MD_INT_P 25U +#define PLL_SSCG_MD_FRACT_M (0x1FFFFFFUL << PLL_SSCG_MD_FRACT_P) +#define PLL_SSCG_MD_INT_M ((uint64_t)0xFFUL << PLL_SSCG_MD_INT_P) + +/* Get predivider (N) from PLL0 NDEC setting */ +static uint32_t findPll0PreDiv(void) +{ + uint32_t preDiv = 1UL; + + /* Direct input is not used? */ + if ((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPREDIV_MASK) == 0UL) + { + preDiv = SYSCON->PLL0NDEC & SYSCON_PLL0NDEC_NDIV_MASK; + if (preDiv == 0UL) + { + preDiv = 1UL; + } + } + return preDiv; +} + +/* Get postdivider (P) from PLL0 PDEC setting */ +static uint32_t findPll0PostDiv(void) +{ + uint32_t postDiv = 1; + + if ((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPOSTDIV_MASK) == 0UL) + { + if ((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPOSTDIV2_MASK) != 0UL) + { + postDiv = SYSCON->PLL0PDEC & SYSCON_PLL0PDEC_PDIV_MASK; + } + else + { + postDiv = 2UL * (SYSCON->PLL0PDEC & SYSCON_PLL0PDEC_PDIV_MASK); + } + if (postDiv == 0UL) + { + postDiv = 2UL; + } + } + return postDiv; +} + +/* Get multiplier (M) from PLL0 SSCG and SEL_EXT settings */ +static float findPll0MMult(void) +{ + float mMult = 1.0F; + float mMult_fract; + uint32_t mMult_int; + + if ((SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_SEL_EXT_MASK) != 0UL) + { + mMult = (float)(uint32_t)((SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_MDIV_EXT_MASK) >> SYSCON_PLL0SSCG1_MDIV_EXT_SHIFT); + } + else + { + mMult_int = ((SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_MD_MBS_MASK) << 7U); + mMult_int = mMult_int | ((SYSCON->PLL0SSCG0) >> PLL_SSCG_MD_INT_P); + mMult_fract = ((float)(uint32_t)((SYSCON->PLL0SSCG0) & PLL_SSCG_MD_FRACT_M) / + (float)(uint32_t)(1UL << PLL_SSCG_MD_INT_P)); + mMult = (float)mMult_int + mMult_fract; + } + if (0ULL == ((uint64_t)mMult)) + { + mMult = 1.0F; + } + return mMult; +} + +/* Get predivider (N) from PLL1 NDEC setting */ +static uint32_t findPll1PreDiv(void) +{ + uint32_t preDiv = 1UL; + + /* Direct input is not used? */ + if ((SYSCON->PLL1CTRL & SYSCON_PLL1CTRL_BYPASSPREDIV_MASK) == 0UL) + { + preDiv = SYSCON->PLL1NDEC & SYSCON_PLL1NDEC_NDIV_MASK; + if (preDiv == 0UL) + { + preDiv = 1UL; + } + } + return preDiv; +} + +/* Get postdivider (P) from PLL1 PDEC setting */ +static uint32_t findPll1PostDiv(void) +{ + uint32_t postDiv = 1UL; + + if ((SYSCON->PLL1CTRL & SYSCON_PLL1CTRL_BYPASSPOSTDIV_MASK) == 0UL) + { + if ((SYSCON->PLL1CTRL & SYSCON_PLL1CTRL_BYPASSPOSTDIV2_MASK) != 0UL) + { + postDiv = SYSCON->PLL1PDEC & SYSCON_PLL1PDEC_PDIV_MASK; + } + else + { + postDiv = 2UL * (SYSCON->PLL1PDEC & SYSCON_PLL1PDEC_PDIV_MASK); + } + if (postDiv == 0UL) + { + postDiv = 2UL; + } + } + return postDiv; +} + +/* Get multiplier (M) from PLL1 MDEC settings */ +static uint32_t findPll1MMult(void) +{ + uint32_t mMult = 1UL; + + mMult = SYSCON->PLL1MDEC & SYSCON_PLL1MDEC_MDIV_MASK; + + if (mMult == 0UL) + { + mMult = 1UL; + } + return mMult; +} + +/* Get FRO 12M Clk */ +/*! brief Return Frequency of FRO 12MHz + * return Frequency of FRO 12MHz + */ +static uint32_t GetFro12MFreq(void) +{ + return ((ANACTRL->FRO192M_CTRL & ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_MASK) != 0UL) ? 12000000U : 0U; +} + +/* Get FRO 1M Clk */ +/*! brief Return Frequency of FRO 1MHz + * return Frequency of FRO 1MHz + */ +static uint32_t GetFro1MFreq(void) +{ + return ((SYSCON->CLOCK_CTRL & SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_MASK) != 0UL) ? 1000000U : 0U; +} + +/* Get EXT OSC Clk */ +/*! brief Return Frequency of External Clock + * return Frequency of External Clock. If no external clock is used returns 0. + */ +static uint32_t GetExtClkFreq(void) +{ + return ((ANACTRL->XO32M_CTRL & ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK) != 0UL) ? CLK_CLK_IN : 0U; +} + +/* Get HF FRO Clk */ +/*! brief Return Frequency of High-Freq output of FRO + * return Frequency of High-Freq output of FRO + */ +static uint32_t GetFroHfFreq(void) +{ + return ((ANACTRL->FRO192M_CTRL & ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK) != 0UL) ? 96000000U : 0U; +} + +/* Get RTC OSC Clk */ +/*! brief Return Frequency of 32kHz osc + * return Frequency of 32kHz osc + */ +static uint32_t GetOsc32KFreq(void) +{ + return ((0UL == (PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_FRO32K_MASK)) && (0UL == (PMC->RTCOSC32K & PMC_RTCOSC32K_SEL_MASK))) ? + CLK_RTC_32K_CLK : + ((0UL == (PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_XTAL32K_MASK)) && ((PMC->RTCOSC32K & PMC_RTCOSC32K_SEL_MASK) != 0UL)) ? + CLK_RTC_32K_CLK : + 0U; +} + + + +/* ---------------------------------------------------------------------------- + -- Core clock + ---------------------------------------------------------------------------- */ + +uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK; + +/* ---------------------------------------------------------------------------- + -- SystemInit() + ---------------------------------------------------------------------------- */ + +__attribute__ ((weak)) void SystemInit (void) { +#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) + SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access in Secure mode */ + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + SCB_NS->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access in Non-secure mode */ + #endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */ + + SCB->CPACR |= ((3UL << 0*2) | (3UL << 1*2)); /* set CP0, CP1 Full Access in Secure mode (enable PowerQuad) */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + SCB_NS->CPACR |= ((3UL << 0*2) | (3UL << 1*2)); /* set CP0, CP1 Full Access in Normal mode (enable PowerQuad) */ +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + SCB->NSACR |= ((3UL << 0) | (3UL << 10)); /* enable CP0, CP1, CP10, CP11 Non-secure Access */ + +#if defined(__MCUXPRESSO) + extern void(*const g_pfnVectors[]) (void); + SCB->VTOR = (uint32_t) &g_pfnVectors; +#else + extern void *__Vectors; + SCB->VTOR = (uint32_t) &__Vectors; +#endif + SYSCON->TRACECLKDIV = 0; +/* Optionally enable RAM banks that may be off by default at reset */ +#if !defined(DONT_ENABLE_DISABLED_RAMBANKS) + SYSCON->AHBCLKCTRLSET[0] = SYSCON_AHBCLKCTRL0_SRAM_CTRL1_MASK | SYSCON_AHBCLKCTRL0_SRAM_CTRL2_MASK; +#endif + /* Following code is to reset PUF to remove over consumption */ + /* Enable PUF register clock to access register */ + SYSCON->AHBCLKCTRLSET[2] = SYSCON_AHBCLKCTRL2_PUF_MASK; + /* Release PUF reset */ + SYSCON->PRESETCTRLCLR[2] = SYSCON_PRESETCTRL2_PUF_RST_MASK; + /* Enable PUF SRAM */ + PUF_SRAM_CTRL->CFG |= PUF_SRAM_CTRL_CFG_ENABLE_MASK | PUF_SRAM_CTRL_CFG_CKGATING_MASK; + /* Disable PUF register clock. */ + // Delaying the line of code below until the PUF State Machine execution is completed: + // Shutting down the clock to early will prevent the state machine from reaching the end. + // => Wait for status bit in PUF Controller Registers before stop PUF clock. + while ((PUF_SRAM_CTRL->INT_STATUS & PUF_SRAM_CTRL_INT_STATUS_READY_MASK) == 0UL) + { + } + SYSCON->AHBCLKCTRLCLR[2] = SYSCON_AHBCLKCTRL2_PUF_MASK; + SystemInitHook(); +} + +/* ---------------------------------------------------------------------------- + -- SystemCoreClockUpdate() + ---------------------------------------------------------------------------- */ + +void SystemCoreClockUpdate (void) { + uint32_t clkRate = 0; + uint32_t prediv, postdiv; + uint64_t workRate; + uint64_t workRate1; + + switch (SYSCON->MAINCLKSELB & SYSCON_MAINCLKSELB_SEL_MASK) + { + case 0x00: /* MAINCLKSELA clock (main_clk_a)*/ + switch (SYSCON->MAINCLKSELA & SYSCON_MAINCLKSELA_SEL_MASK) + { + case 0x00: /* FRO 12 MHz (fro_12m) */ + clkRate = GetFro12MFreq(); + break; + case 0x01: /* CLKIN (clk_in) */ + clkRate = GetExtClkFreq(); + break; + case 0x02: /* Fro 1MHz (fro_1m) */ + clkRate = GetFro1MFreq(); + break; + default: /* = 0x03 = FRO 96 MHz (fro_hf) */ + clkRate = GetFroHfFreq(); + break; + } + break; + case 0x01: /* PLL0 clock (pll0_clk)*/ + switch (SYSCON->PLL0CLKSEL & SYSCON_PLL0CLKSEL_SEL_MASK) + { + case 0x00: /* FRO 12 MHz (fro_12m) */ + clkRate = GetFro12MFreq(); + break; + case 0x01: /* CLKIN (clk_in) */ + clkRate = GetExtClkFreq(); + break; + case 0x02: /* Fro 1MHz (fro_1m) */ + clkRate = GetFro1MFreq(); + break; + case 0x03: /* RTC oscillator 32 kHz output (32k_clk) */ + clkRate = GetOsc32KFreq(); + break; + default: + clkRate = 0UL; + break; + } + if (((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPLL_MASK) == 0UL) && ((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_CLKEN_MASK) != 0UL) && ((PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_PLL0_MASK) == 0UL) && ((PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_PLL0_SSCG_MASK) == 0UL)) + { + prediv = findPll0PreDiv(); + postdiv = findPll0PostDiv(); + /* Adjust input clock */ + clkRate = clkRate / prediv; + /* MDEC used for rate */ + workRate = (uint64_t)clkRate * (uint64_t)findPll0MMult(); + clkRate = (uint32_t)(workRate / ((uint64_t)postdiv)); + } + break; + case 0x02: /* PLL1 clock (pll1_clk)*/ + switch (SYSCON->PLL1CLKSEL & SYSCON_PLL1CLKSEL_SEL_MASK) + { + case 0x00: /* FRO 12 MHz (fro_12m) */ + clkRate = GetFro12MFreq(); + break; + case 0x01: /* CLKIN (clk_in) */ + clkRate = GetExtClkFreq(); + break; + case 0x02: /* Fro 1MHz (fro_1m) */ + clkRate = GetFro1MFreq(); + break; + case 0x03: /* RTC oscillator 32 kHz output (32k_clk) */ + clkRate = GetOsc32KFreq(); + break; + default: + clkRate = 0UL; + break; + } + if (((SYSCON->PLL1CTRL & SYSCON_PLL1CTRL_BYPASSPLL_MASK) == 0UL) && ((SYSCON->PLL1CTRL & SYSCON_PLL1CTRL_CLKEN_MASK) != 0UL) && ((PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_PLL1_MASK) == 0UL)) + { + /* PLL is not in bypass mode, get pre-divider, post-divider, and M divider */ + prediv = findPll1PreDiv(); + postdiv = findPll1PostDiv(); + /* Adjust input clock */ + clkRate = clkRate / prediv; + + /* MDEC used for rate */ + workRate1 = (uint64_t)clkRate * (uint64_t)findPll1MMult(); + clkRate = (uint32_t)(workRate1 / ((uint64_t)postdiv)); + } + break; + case 0x03: /* RTC oscillator 32 kHz output (32k_clk) */ + clkRate = GetOsc32KFreq(); + break; + default: + clkRate = 0UL; + break; + } + SystemCoreClock = clkRate / ((SYSCON->AHBCLKDIV & 0xFFUL) + 1UL); +} + +/* ---------------------------------------------------------------------------- + -- SystemInitHook() + ---------------------------------------------------------------------------- */ + +__attribute__ ((weak)) void SystemInitHook (void) { + /* Void implementation of the weak function. */ +} diff --git a/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/system_LPC55S16.h b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/system_LPC55S16.h new file mode 100644 index 0000000000..ecfd4b244a --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S16/LPC55S16/system_LPC55S16.h @@ -0,0 +1,112 @@ +/* +** ################################################################### +** Processors: LPC55S16JBD100 +** LPC55S16JBD64 +** LPC55S16JEV98 +** +** Compilers: GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** Keil ARM C/C++ Compiler +** MCUXpresso Compiler +** +** Reference manual: LPC55S1x/LPC551x User manual Rev.0.6 15 November 2019 +** Version: rev. 1.1, 2019-12-03 +** Build: b220117 +** +** Abstract: +** Provides a system configuration function and a global variable that +** contains the system frequency. It configures the device and initializes +** the oscillator (PLL) that is part of the microcontroller device. +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2022 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2018-08-22) +** Initial version based on v0.2UM +** - rev. 1.1 (2019-12-03) +** Initial version based on v0.6UM +** +** ################################################################### +*/ + +/*! + * @file LPC55S16 + * @version 1.1 + * @date 2019-12-03 + * @brief Device specific configuration file for LPC55S16 (header file) + * + * Provides a system configuration function and a global variable that contains + * the system frequency. It configures the device and initializes the oscillator + * (PLL) that is part of the microcontroller device. + */ + +#ifndef _SYSTEM_LPC55S16_H_ +#define _SYSTEM_LPC55S16_H_ /**< Symbol preventing repeated inclusion */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +#define DEFAULT_SYSTEM_CLOCK 12000000u /* Default System clock value */ +#define CLK_RTC_32K_CLK 32768u /* RTC oscillator 32 kHz output (32k_clk */ +#define CLK_FRO_12MHZ 12000000u /* FRO 12 MHz (fro_12m) */ +#define CLK_FRO_48MHZ 48000000u /* FRO 48 MHz (fro_48m) */ +#define CLK_FRO_96MHZ 96000000u /* FRO 96 MHz (fro_96m) */ +#define CLK_CLK_IN 16000000u /* Default CLK_IN pin clock */ + + +/** + * @brief System clock frequency (core clock) + * + * The system clock frequency supplied to the SysTick timer and the processor + * core clock. This variable can be used by the user application to setup the + * SysTick timer or configure other parameters. It may also be used by debugger to + * query the frequency of the debug timer or configure the trace clock speed + * SystemCoreClock is initialized with a correct predefined value. + */ +extern uint32_t SystemCoreClock; + +/** + * @brief Setup the microcontroller system. + * + * Typically this function configures the oscillator (PLL) that is part of the + * microcontroller device. For systems with variable clock speed it also updates + * the variable SystemCoreClock. SystemInit is called from startup_device file. + */ +void SystemInit (void); + +/** + * @brief Updates the SystemCoreClock variable. + * + * It must be called whenever the core clock is changed during program + * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates + * the current core clock. + */ +void SystemCoreClockUpdate (void); + +/** + * @brief SystemInit function hook. + * + * This weak function allows to call specific initialization code during the + * SystemInit() execution.This can be used when an application specific code needs + * to be called as close to the reset entry as possible (for example the Multicore + * Manager MCMGR_EarlyInit() function call). + * NOTE: No global r/w variables can be used in this hook function because the + * initialization of these variables happens after this function. + */ +void SystemInitHook (void); + +#ifdef __cplusplus +} +#endif + +#endif /* _SYSTEM_LPC55S16_H_ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S16/SConscript b/bsp/lpc55sxx/Libraries/LPC55S16/SConscript new file mode 100644 index 0000000000..3ec55349f1 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S16/SConscript @@ -0,0 +1,51 @@ +Import('rtconfig') +from building import * + +cwd = GetCurrentDir() +path = [cwd + '/../CMSIS/Core/Include',cwd + '/components/codec', cwd + '/LPC55S16', cwd + '/LPC55S16/drivers', cwd + '/middleware/sdmmc/inc', cwd + '/middleware/sdmmc/port'] +src = Split(''' + LPC55S16/system_LPC55S16.c + ''') + +if rtconfig.PLATFORM in ['gcc']: + src += ['LPC55S16/gcc/startup_LPC55S16.S'] +elif rtconfig.PLATFORM in ['armcc', 'armclang']: + src += ['LPC55S16/arm/startup_LPC55S16.s'] +elif rtconfig.PLATFORM in ['iccarm']: + src += ['LPC55S16/iar/startup_LPC55S16.s'] + +src += ['LPC55S16/drivers/fsl_anactrl.c'] +src += ['LPC55S16/drivers/fsl_clock.c'] +src += ['LPC55S16/drivers/fsl_cmp.c'] +src += ['LPC55S16/drivers/fsl_common.c'] +src += ['LPC55S16/drivers/fsl_common_arm.c'] +src += ['LPC55S16/drivers/fsl_crc.c'] +src += ['LPC55S16/drivers/fsl_ctimer.c'] +src += ['LPC55S16/drivers/fsl_flexcomm.c'] +src += ['LPC55S16/drivers/fsl_dma.c'] +src += ['LPC55S16/drivers/fsl_gint.c'] +src += ['LPC55S16/drivers/fsl_gpio.c'] +src += ['LPC55S16/drivers/fsl_i2c.c'] +src += ['LPC55S16/drivers/fsl_i2c_dma.c'] +src += ['LPC55S16/drivers/fsl_i2s.c'] +src += ['LPC55S16/drivers/fsl_i2s_dma.c'] +src += ['LPC55S16/drivers/fsl_inputmux.c'] +src += ['LPC55S16/drivers/fsl_lpadc.c'] +src += ['LPC55S16/drivers/fsl_mrt.c'] +src += ['LPC55S16/drivers/fsl_ostimer.c'] +src += ['LPC55S16/drivers/fsl_pint.c'] +src += ['LPC55S16/drivers/fsl_power.c'] +src += ['LPC55S16/drivers/fsl_reset.c'] +src += ['LPC55S16/drivers/fsl_sctimer.c'] +src += ['LPC55S16/drivers/fsl_spi.c'] +src += ['LPC55S16/drivers/fsl_spi_dma.c'] +src += ['LPC55S16/drivers/fsl_sysctl.c'] +src += ['LPC55S16/drivers/fsl_usart.c'] +src += ['LPC55S16/drivers/fsl_usart_dma.c'] +src += ['LPC55S16/drivers/fsl_utick.c'] +src += ['LPC55S16/drivers/fsl_wwdt.c'] + + +group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path) + +Return('group') diff --git a/bsp/lpc55sxx/lpc55s16_nxp_evk/.config b/bsp/lpc55sxx/lpc55s16_nxp_evk/.config new file mode 100644 index 0000000000..93b1478d24 --- /dev/null +++ b/bsp/lpc55sxx/lpc55s16_nxp_evk/.config @@ -0,0 +1,758 @@ +# +# Automatically generated file; DO NOT EDIT. +# RT-Thread Configuration +# +CONFIG_SOC_LPC55S6x=y + +# +# RT-Thread Kernel +# +CONFIG_RT_NAME_MAX=8 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_SMP is not set +CONFIG_RT_ALIGN_SIZE=4 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=100 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_HOOK_USING_FUNC_PTR=y +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=256 +CONFIG_RT_USING_TIMER_SOFT=y +CONFIG_RT_TIMER_THREAD_PRIO=4 +CONFIG_RT_TIMER_THREAD_STACK_SIZE=512 + +# +# kservice optimization +# +# CONFIG_RT_KSERVICE_USING_STDLIB is not set +# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set +# CONFIG_RT_USING_TINY_FFS is not set +# CONFIG_RT_KPRINTF_USING_LONGLONG is not set +CONFIG_RT_DEBUG=y +# CONFIG_RT_DEBUG_COLOR is not set +# CONFIG_RT_DEBUG_INIT_CONFIG is not set +# CONFIG_RT_DEBUG_THREAD_CONFIG is not set +# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set +# CONFIG_RT_DEBUG_IPC_CONFIG is not set +# CONFIG_RT_DEBUG_TIMER_CONFIG is not set +# CONFIG_RT_DEBUG_IRQ_CONFIG is not set +# CONFIG_RT_DEBUG_MEM_CONFIG is not set +# CONFIG_RT_DEBUG_SLAB_CONFIG is not set +# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set +# CONFIG_RT_DEBUG_MODULE_CONFIG is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_SIGNALS is not set + +# +# Memory Management +# +CONFIG_RT_USING_MEMPOOL=y +CONFIG_RT_USING_SMALL_MEM=y +# CONFIG_RT_USING_SLAB is not set +# CONFIG_RT_USING_MEMHEAP is not set +CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y +# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set +# CONFIG_RT_USING_SLAB_AS_HEAP is not set +# CONFIG_RT_USING_USERHEAP is not set +# CONFIG_RT_USING_NOHEAP is not set +# CONFIG_RT_USING_MEMTRACE is not set +# CONFIG_RT_USING_HEAP_ISR is not set +CONFIG_RT_USING_HEAP=y + +# +# Kernel Device Object +# +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_INTERRUPT_INFO is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=128 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart0" +CONFIG_RT_VER_NUM=0x40101 +CONFIG_ARCH_ARM=y +CONFIG_RT_USING_CPU_FFS=y +CONFIG_ARCH_ARM_CORTEX_M=y +CONFIG_ARCH_ARM_CORTEX_FPU=y +CONFIG_ARCH_ARM_CORTEX_SECURE=y +CONFIG_ARCH_ARM_CORTEX_M33=y +# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 +# CONFIG_RT_USING_LEGACY is not set +CONFIG_RT_USING_MSH=y +CONFIG_RT_USING_FINSH=y +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=4096 +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_CMD_SIZE=80 +CONFIG_MSH_USING_BUILT_IN_COMMANDS=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_ARG_MAX=10 +# CONFIG_RT_USING_DFS is not set +# CONFIG_RT_USING_FAL is not set +# CONFIG_RT_USING_LWP is not set + +# +# Device Drivers +# +CONFIG_RT_USING_DEVICE_IPC=y +# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set +CONFIG_RT_USING_SERIAL=y +CONFIG_RT_USING_SERIAL_V1=y +# CONFIG_RT_USING_SERIAL_V2 is not set +CONFIG_RT_SERIAL_USING_DMA=y +CONFIG_RT_SERIAL_RB_BUFSZ=64 +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_HWTIMER is not set +# CONFIG_RT_USING_CPUTIME is not set +# CONFIG_RT_USING_I2C is not set +# CONFIG_RT_USING_PHY is not set +CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_DAC is not set +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_PM is not set +# CONFIG_RT_USING_RTC is not set +# CONFIG_RT_USING_SDIO is not set +# CONFIG_RT_USING_SPI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_AUDIO is not set +# CONFIG_RT_USING_SENSOR is not set +# CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_HWCRYPTO is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set +# CONFIG_RT_USING_WIFI is not set + +# +# Using USB +# +# CONFIG_RT_USING_USB is not set +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set + +# +# C/C++ and POSIX layer +# +CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 + +# +# POSIX (Portable Operating System Interface) layer +# +# CONFIG_RT_USING_POSIX_FS is not set +# CONFIG_RT_USING_POSIX_DELAY is not set +# CONFIG_RT_USING_POSIX_CLOCK is not set +# CONFIG_RT_USING_POSIX_TIMER is not set +# CONFIG_RT_USING_PTHREADS is not set +# CONFIG_RT_USING_MODULE is not set + +# +# Interprocess Communication (IPC) +# +# CONFIG_RT_USING_POSIX_PIPE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set + +# +# Socket is in the 'Network' category +# +# CONFIG_RT_USING_CPLUSPLUS is not set + +# +# Network +# +# CONFIG_RT_USING_SAL is not set +# CONFIG_RT_USING_NETDEV is not set +# CONFIG_RT_USING_LWIP is not set +# CONFIG_RT_USING_AT is not set + +# +# Utilities +# +# CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set +# CONFIG_RT_USING_VAR_EXPORT is not set +# CONFIG_RT_USING_RT_LINK is not set +# CONFIG_RT_USING_VBUS is not set + +# +# RT-Thread Utestcases +# +# CONFIG_RT_USING_UTESTCASES is not set + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_LWIP is not set +# CONFIG_PKG_USING_LORAWAN_DRIVER is not set +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_LIBMODBUS is not set +# CONFIG_PKG_USING_FREEMODBUS is not set +# CONFIG_PKG_USING_NANOPB is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# CONFIG_PKG_USING_RW007 is not set +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set +# CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_ATSRV_SOCKET is not set +# CONFIG_PKG_USING_WIZNET is not set +# CONFIG_PKG_USING_ZB_COORDINATOR is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set +# CONFIG_PKG_USING_EZ_IOT_OS is not set +# CONFIG_PKG_USING_IOTSHARP_SDK is not set +# CONFIG_PKG_USING_NIMBLE is not set +# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set +# CONFIG_PKG_USING_OTA_DOWNLOADER is not set +# CONFIG_PKG_USING_IPMSG is not set +# CONFIG_PKG_USING_LSSDP is not set +# CONFIG_PKG_USING_AIRKISS_OPEN is not set +# CONFIG_PKG_USING_LIBRWS is not set +# CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set +# CONFIG_PKG_USING_NMEALIB is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set +# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set +# CONFIG_PKG_USING_WAYZ_IOTKIT is not set +# CONFIG_PKG_USING_MAVLINK is not set +# CONFIG_PKG_USING_BSAL is not set +# CONFIG_PKG_USING_AGILE_MODBUS is not set +# CONFIG_PKG_USING_AGILE_FTP is not set +# CONFIG_PKG_USING_EMBEDDEDPROTO is not set +# CONFIG_PKG_USING_RT_LINK_HW is not set +# CONFIG_PKG_USING_LORA_PKT_FWD is not set +# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set +# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set +# CONFIG_PKG_USING_HM is not set +# CONFIG_PKG_USING_SMALL_MODBUS is not set +# CONFIG_PKG_USING_NET_SERVER is not set +# CONFIG_PKG_USING_ZFTP is not set + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_LIBSODIUM is not set +# CONFIG_PKG_USING_LIBHYDROGEN is not set +# CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set +# CONFIG_PKG_USING_YD_CRYPTO is not set + +# +# language packages +# + +# +# JSON: JavaScript Object Notation, a lightweight data-interchange format +# +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_RAPIDJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set +# CONFIG_PKG_USING_PARSON is not set + +# +# XML: Extensible Markup Language +# +# CONFIG_PKG_USING_SIMPLE_XML is not set +# CONFIG_PKG_USING_EZXML is not set +# CONFIG_PKG_USING_LUATOS_SOC is not set +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set +# CONFIG_PKG_USING_PIKASCRIPT is not set +# CONFIG_PKG_USING_RTT_RUST is not set + +# +# multimedia packages +# + +# +# LVGL: powerful and easy-to-use embedded GUI library +# +# CONFIG_PKG_USING_LVGL is not set +# CONFIG_PKG_USING_LITTLEVGL2RTT is not set +# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set +# CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set + +# +# u8g2: a monochrome graphic library +# +# CONFIG_PKG_USING_U8G2_OFFICIAL is not set +# CONFIG_PKG_USING_U8G2 is not set +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set +# CONFIG_PKG_USING_STEMWIN is not set +# CONFIG_PKG_USING_WAVPLAYER is not set +# CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_PDFGEN is not set +# CONFIG_PKG_USING_HELIX is not set +# CONFIG_PKG_USING_AZUREGUIX is not set +# CONFIG_PKG_USING_TOUCHGFX2RTT is not set +# CONFIG_PKG_USING_NUEMWIN is not set +# CONFIG_PKG_USING_MP3PLAYER is not set +# CONFIG_PKG_USING_TINYJPEG is not set +# CONFIG_PKG_USING_UGUI is not set + +# +# PainterEngine: A cross-platform graphics application framework written in C language +# +# CONFIG_PKG_USING_PAINTERENGINE is not set +# CONFIG_PKG_USING_PAINTERENGINE_AUX is not set +# CONFIG_PKG_USING_MCURSES is not set +# CONFIG_PKG_USING_TERMBOX is not set +# CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_GUIENGINE is not set + +# +# tools packages +# +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_SEGGER_RTT is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_ULOG_FILE is not set +# CONFIG_PKG_USING_LOGMGR is not set +# CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_MEMORYPERF is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_GPS_RMC is not set +# CONFIG_PKG_USING_URLENCODE is not set +# CONFIG_PKG_USING_UMCN is not set +# CONFIG_PKG_USING_LWRB2RTT is not set +# CONFIG_PKG_USING_CPU_USAGE is not set +# CONFIG_PKG_USING_GBK2UTF8 is not set +# CONFIG_PKG_USING_VCONSOLE is not set +# CONFIG_PKG_USING_KDB is not set +# CONFIG_PKG_USING_WAMR is not set +# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set +# CONFIG_PKG_USING_LWLOG is not set +# CONFIG_PKG_USING_ANV_TRACE is not set +# CONFIG_PKG_USING_ANV_MEMLEAK is not set +# CONFIG_PKG_USING_ANV_TESTSUIT is not set +# CONFIG_PKG_USING_ANV_BENCH is not set +# CONFIG_PKG_USING_DEVMEM is not set +# CONFIG_PKG_USING_REGEX is not set +# CONFIG_PKG_USING_MEM_SANDBOX is not set +# CONFIG_PKG_USING_SOLAR_TERMS is not set +# CONFIG_PKG_USING_GAN_ZHI is not set +# CONFIG_PKG_USING_FDT is not set +# CONFIG_PKG_USING_CBOX is not set +# CONFIG_PKG_USING_SNOWFLAKE is not set +# CONFIG_PKG_USING_HASH_MATCH is not set +# CONFIG_PKG_USING_FIRE_PID_CURVE is not set +# CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set + +# +# system packages +# + +# +# enhanced kernel services +# +# CONFIG_PKG_USING_RT_MEMCPY_CM is not set +# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set +# CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set + +# +# acceleration: Assembly language or algorithmic acceleration packages +# +# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set +# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set +# CONFIG_PKG_USING_QFPLIB_M3 is not set + +# +# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard +# +# CONFIG_PKG_USING_CMSIS_5 is not set +# CONFIG_PKG_USING_CMSIS_RTOS1 is not set +# CONFIG_PKG_USING_CMSIS_RTOS2 is not set + +# +# Micrium: Micrium software products porting for RT-Thread +# +# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_UCOSII_WRAPPER is not set +# CONFIG_PKG_USING_UC_CRC is not set +# CONFIG_PKG_USING_UC_CLK is not set +# CONFIG_PKG_USING_UC_COMMON is not set +# CONFIG_PKG_USING_UC_MODBUS is not set +# CONFIG_PKG_USING_RTDUINO is not set +# CONFIG_PKG_USING_FREERTOS_WRAPPER is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_PERF_COUNTER is not set +# CONFIG_PKG_USING_FLASHDB is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_DFS_JFFS2 is not set +# CONFIG_PKG_USING_DFS_UFFS is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set +# CONFIG_PKG_USING_PPOOL is not set +# CONFIG_PKG_USING_OPENAMP is not set +# CONFIG_PKG_USING_LPM is not set +# CONFIG_PKG_USING_TLSF is not set +# CONFIG_PKG_USING_EVENT_RECORDER is not set +# CONFIG_PKG_USING_ARM_2D is not set +# CONFIG_PKG_USING_MCUBOOT is not set +# CONFIG_PKG_USING_TINYUSB is not set +# CONFIG_PKG_USING_CHERRYUSB is not set +# CONFIG_PKG_USING_KMULTI_RTIMER is not set +# CONFIG_PKG_USING_TFDB is not set +# CONFIG_PKG_USING_QPC is not set + +# +# peripheral libraries and drivers +# +# CONFIG_PKG_USING_SENSORS_DRIVERS is not set +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_ADT74XX is not set +# CONFIG_PKG_USING_AS7341 is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_ESP_IDF is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_SX12XX is not set +# CONFIG_PKG_USING_SIGNAL_LED is not set +# CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set +# CONFIG_PKG_USING_WM_LIBRARIES is not set + +# +# Kendryte SDK +# +# CONFIG_PKG_USING_K210_SDK is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set +# CONFIG_PKG_USING_INFRARED is not set +# CONFIG_PKG_USING_MULTI_INFRARED is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set +# CONFIG_PKG_USING_AT24CXX is not set +# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set +# CONFIG_PKG_USING_AD7746 is not set +# CONFIG_PKG_USING_PCA9685 is not set +# CONFIG_PKG_USING_I2C_TOOLS is not set +# CONFIG_PKG_USING_NRF24L01 is not set +# CONFIG_PKG_USING_TOUCH_DRIVERS is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_WS2812B is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set +# CONFIG_PKG_USING_MAX7219 is not set +# CONFIG_PKG_USING_BEEP is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_PKG_USING_QLED is not set +# CONFIG_PKG_USING_PAJ7620 is not set +# CONFIG_PKG_USING_AGILE_CONSOLE is not set +# CONFIG_PKG_USING_LD3320 is not set +# CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set +# CONFIG_PKG_USING_SSD1306 is not set +# CONFIG_PKG_USING_QKEY is not set +# CONFIG_PKG_USING_RS485 is not set +# CONFIG_PKG_USING_RS232 is not set +# CONFIG_PKG_USING_NES is not set +# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set +# CONFIG_PKG_USING_VDEVICE is not set +# CONFIG_PKG_USING_SGM706 is not set +# CONFIG_PKG_USING_STM32WB55_SDK is not set +# CONFIG_PKG_USING_RDA58XX is not set +# CONFIG_PKG_USING_LIBNFC is not set +# CONFIG_PKG_USING_MFOC is not set +# CONFIG_PKG_USING_TMC51XX is not set +# CONFIG_PKG_USING_TCA9534 is not set +# CONFIG_PKG_USING_KOBUKI is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_MICRO_ROS is not set +# CONFIG_PKG_USING_MCP23008 is not set +# CONFIG_PKG_USING_BLUETRUM_SDK is not set +# CONFIG_PKG_USING_MISAKA_AT24CXX is not set +# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set +# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set +# CONFIG_PKG_USING_BL_MCU_SDK is not set +# CONFIG_PKG_USING_SOFT_SERIAL is not set +# CONFIG_PKG_USING_MB85RS16 is not set +# CONFIG_PKG_USING_CW2015 is not set +# CONFIG_PKG_USING_RFM300 is not set +# CONFIG_PKG_USING_IO_INPUT_FILTER is not set +# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set + +# +# AI packages +# +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_QUEST is not set +# CONFIG_PKG_USING_NAXOS is not set + +# +# miscellaneous packages +# + +# +# project laboratory +# + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set + +# +# entertainment: terminal games and other interesting software packages +# +# CONFIG_PKG_USING_CMATRIX is not set +# CONFIG_PKG_USING_SL is not set +# CONFIG_PKG_USING_CAL is not set +# CONFIG_PKG_USING_ACLOCK is not set +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_SNAKE is not set +# CONFIG_PKG_USING_TETRIS is not set +# CONFIG_PKG_USING_DONUT is not set +# CONFIG_PKG_USING_COWSAY is not set +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_LZMA is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_MINIZIP is not set +# CONFIG_PKG_USING_HEATSHRINK is not set +# CONFIG_PKG_USING_DSTR is not set +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set +# CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set +# CONFIG_PKG_USING_KI is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_CRCLIB is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_STATE_MACHINE is not set +# CONFIG_PKG_USING_DESIGN_PATTERN is not set +# CONFIG_PKG_USING_CONTROLLER is not set +# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set +# CONFIG_PKG_USING_MFBD is not set +# CONFIG_PKG_USING_SLCAN2RTT is not set +# CONFIG_PKG_USING_SOEM is not set +# CONFIG_PKG_USING_QPARAM is not set + +# +# Privated Packages of RealThread +# +# CONFIG_PKG_USING_CODEC is not set +# CONFIG_PKG_USING_PLAYER is not set +# CONFIG_PKG_USING_MPLAYER is not set +# CONFIG_PKG_USING_PERSIMMON_SRC is not set +# CONFIG_PKG_USING_JS_PERSIMMON is not set +# CONFIG_PKG_USING_JERRYSCRIPT_WIN32 is not set + +# +# Network Utilities +# +# CONFIG_PKG_USING_WICED is not set +# CONFIG_PKG_USING_CLOUDSDK is not set +# CONFIG_PKG_USING_POWER_MANAGER is not set +# CONFIG_PKG_USING_RT_OTA is not set +# CONFIG_PKG_USING_RTINSIGHT is not set +# CONFIG_PKG_USING_SMARTCONFIG is not set +# CONFIG_PKG_USING_RTX is not set +# CONFIG_RT_USING_TESTCASE is not set +# CONFIG_PKG_USING_NGHTTP2 is not set +# CONFIG_PKG_USING_AVS is not set +# CONFIG_PKG_USING_ALI_LINKKIT is not set +# CONFIG_PKG_USING_STS is not set +# CONFIG_PKG_USING_DLMS is not set +# CONFIG_PKG_USING_AUDIO_FRAMEWORK is not set +# CONFIG_PKG_USING_ZBAR is not set +# CONFIG_PKG_USING_MCF is not set +# CONFIG_PKG_USING_URPC is not set +# CONFIG_PKG_USING_DCM is not set +# CONFIG_PKG_USING_EMQ is not set +# CONFIG_PKG_USING_CFGM is not set +# CONFIG_PKG_USING_RT_CMSIS_DAP is not set +# CONFIG_PKG_USING_SMODULE is not set +# CONFIG_PKG_USING_SNFD is not set +# CONFIG_PKG_USING_UDBD is not set +# CONFIG_PKG_USING_BENCHMARK is not set +# CONFIG_PKG_USING_UBJSON is not set +# CONFIG_PKG_USING_DATATYPE is not set +# CONFIG_PKG_USING_FASTFS is not set +# CONFIG_PKG_USING_RIL is not set +# CONFIG_PKG_USING_WATCH_DCM_SVC is not set +# CONFIG_PKG_USING_WATCH_APP_FWK is not set +# CONFIG_PKG_USING_GUI_TEST is not set +# CONFIG_PKG_USING_PMEM is not set +# CONFIG_PKG_USING_LWRDP is not set +# CONFIG_PKG_USING_MASAN is not set +# CONFIG_PKG_USING_BSDIFF_LIB is not set +# CONFIG_PKG_USING_PRC_DIFF is not set + +# +# RT-Thread Smart +# +# CONFIG_PKG_USING_UKERNEL is not set +# CONFIG_PKG_USING_TRACE_AGENT is not set +CONFIG_SOC_LPC55S6X_SERIES=y + +# +# Hardware Drivers Config +# +CONFIG_SOC_LPC55S6X=y + +# +# On-chip Peripheral Drivers +# +# CONFIG_BSP_USING_DMA is not set +CONFIG_BSP_USING_PIN=y +CONFIG_BSP_USING_UART=y +CONFIG_BSP_USING_UART0=y +# CONFIG_HW_UART0_BAUDRATE_9600 is not set +CONFIG_HW_UART0_BAUDRATE_115200=y +# CONFIG_BSP_USING_UART2 is not set +# CONFIG_BSP_USING_I2C is not set +# CONFIG_BSP_USING_SPI is not set +# CONFIG_BSP_USING_ADC is not set +# CONFIG_BSP_USING_SDIO is not set +# CONFIG_BSP_USING_RTC is not set +# CONFIG_BSP_USING_WDT is not set +# CONFIG_BSP_USING_HWTIMER is not set +# CONFIG_BSP_USING_PWM is not set + +# +# Onboard Peripheral Drivers +# +CONFIG_BSP_USING_LED=y +CONFIG_BSP_USING_KEY=y +# CONFIG_BSP_USING_MMA8562 is not set + +# +# Board extended module Drivers +# diff --git a/bsp/lpc55sxx/lpc55s16_nxp_evk/Kconfig b/bsp/lpc55sxx/lpc55s16_nxp_evk/Kconfig new file mode 100644 index 0000000000..855fdc554b --- /dev/null +++ b/bsp/lpc55sxx/lpc55s16_nxp_evk/Kconfig @@ -0,0 +1,27 @@ +mainmenu "RT-Thread Configuration" + +config BSP_DIR + string + option env="BSP_ROOT" + default "." + +config RTT_DIR + string + option env="RTT_ROOT" + default "../../.." + +config PKGS_DIR + string + option env="PKGS_ROOT" + default "packages" + +config SOC_LPC55S16 + bool + select ARCH_ARM_CORTEX_M33 + select ARCH_ARM_CORTEX_SECURE + default y + +source "$RTT_DIR/Kconfig" +source "$PKGS_DIR/Kconfig" +source "../Libraries/Kconfig" +source "board/Kconfig" diff --git a/bsp/lpc55sxx/lpc55s16_nxp_evk/README.md b/bsp/lpc55sxx/lpc55s16_nxp_evk/README.md new file mode 100644 index 0000000000..0e6c96a477 --- /dev/null +++ b/bsp/lpc55sxx/lpc55s16_nxp_evk/README.md @@ -0,0 +1,124 @@ +# LPC55S16-EVK 板级支持包 + +## 1. 简介(Introduction) + +LPC55S16 是由恩智浦NXP半导体推出的基于Cortex-M33内核的高性能单片机 +包括如下硬件特性： + +| 硬件 | 描述 | +| -- | -- | +|芯片型号| LPC5516/LPC55S16 全系列 | +|CPU| Cortex-M33 , with FPU | +|主频| 150MHz | + +## 2. 硬件开发环境(Hardware development system) + +开发板（EVK） + +![开发板示意图](./figures/board.png) + + + +## 3. 编译说明 + +支持IDE: + +* MDK5: V5.16 +* IAR: 9.30.1 + +1) 下载源码 + +```bash + git clone https://github.com/RT-Thread/rt-thread.git +``` + +2) 配置工程并准备env + +（Linux/Mac） + +```bash + cd rt-thread/bsp/lpc55S16_evk + scons --menuconfig + source ~/.env/env.sh + pkgs --upgrade +``` + +（Windows） + +>在[RT-Thread官网][1]下载ENV工具包 + +3) 配置芯片型号 + +（Linux/Mac） + +```bash + scons --menuconfig +``` + +（Windows(ENV环境中)） + +```bash + menuconfig +``` + +在menuconfig页面配置并选择对应的芯片型号，若开发环境为MDK/IAR，则需要生成工程 + +4) 生成工程 + +IAR: + +```bash +scons --target=iar +``` + +MDK5: + +```bash +scons --target=mdk5 +``` + +## 3. 烧写及执行 + +烧写可以使用仿真器 ISP等多种方式 此处不再赘述 + +### 3.1 运行结果 + +如果编译 & 烧写无误，会在Flexcomm0串口*上看到RT-Thread的启动logo信息： + +```bash + \ | / +- RT - Thread Operating System + / | \ 4.0.1 build Jul 30 2019 + 2006 - 2019 Copyright by rt-thread team +uising armclang, version: 6120001 +msh /> +``` + + +## 4. 驱动支持情况及计划 + +| 驱动 | 支持情况 | 备注 | +| ---------- | :------: | :--------------------------: | +| UART | 支持 | UART0/2 | +| GPIO | 支持 | 自动根据芯片型号选择引脚布局 | +| SPI | 支持 | 支持High Speed SPI | +| USB Device | 不支持 | 暂不支持 | +| USB Host | 不支持 | 暂不支持 | +| Windowed WatchDog | 不支持 | 支持 | +| ADC | 不支持 | 暂不支持 | +| I2C | 支持 | 可配合MMA8562 | +| RTC | 支持 | RTC时钟自动配置 | + +## 5.进阶使用 + +此 BSP 默认只开启了串口 0 的功能，如果需使用更多高级外设功能，需要利用 ENV 工具对 BSP 进行配置， 步骤如下： + +1. 在 bsp 下打开 env 工具。 +2. 输入 menuconfig 命令配置工程，配置好之后保存退出。 +3. 输入 pkgs --update 命令更新软件包。 +4. 输入 scons --target=mdk5/iar 命令重新生成工程。 + +## 6. 联系人信息 + +维护人: +alex.yang@nxp.com diff --git a/bsp/lpc55sxx/lpc55s16_nxp_evk/SConscript b/bsp/lpc55sxx/lpc55s16_nxp_evk/SConscript new file mode 100644 index 0000000000..c7ef7659ec --- /dev/null +++ b/bsp/lpc55sxx/lpc55s16_nxp_evk/SConscript @@ -0,0 +1,14 @@ +# for module compiling +import os +from building import * + +cwd = GetCurrentDir() +objs = [] +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') diff --git a/bsp/lpc55sxx/lpc55s16_nxp_evk/SConstruct b/bsp/lpc55sxx/lpc55s16_nxp_evk/SConstruct new file mode 100644 index 0000000000..91e65db7a6 --- /dev/null +++ b/bsp/lpc55sxx/lpc55s16_nxp_evk/SConstruct @@ -0,0 +1,67 @@ +import os +import sys +import rtconfig + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +try: + from building import * +except: + print('Cannot found RT-Thread root directory, please check RTT_ROOT') + print(RTT_ROOT) + exit(-1) + +TARGET = 'rtthread.' + rtconfig.TARGET_EXT + +if rtconfig.PLATFORM == 'armcc': + env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS, + CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS, + # overwrite cflags, because cflags has '--C99' + CXXCOM = '$CXX -o $TARGET --cpp -c $CXXFLAGS $_CCCOMCOM $SOURCES') +else: + env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS, + CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS, + CXXCOM = '$CXX -o $TARGET -c $CXXFLAGS $_CCCOMCOM $SOURCES') + +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) + +if rtconfig.PLATFORM in ['iccarm']: + env.Replace(CCCOM = ['$CC $CFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES']) + env.Replace(ARFLAGS = ['']) + env.Replace(LINKCOM = env["LINKCOM"] + ' --map rtthread.map') + +Export('RTT_ROOT') +Export('rtconfig') + +SDK_ROOT = os.path.abspath('./') + +if os.path.exists(SDK_ROOT + '/Libraries'): + libraries_path_prefix = SDK_ROOT + '/Libraries' +else: + libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/Libraries' + +SDK_LIB = libraries_path_prefix +Export('SDK_LIB') + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) + +objs.extend(SConscript(os.path.join(libraries_path_prefix, 'drivers', 'SConscript'))) + +# include cmsis +objs.extend(SConscript(os.path.join(libraries_path_prefix, rtconfig.BSP_LIBRARY_TYPE, 'SConscript'))) + +# make a building +DoBuilding(TARGET, objs) diff --git a/bsp/lpc55sxx/lpc55s16_nxp_evk/applications/SConscript b/bsp/lpc55sxx/lpc55s16_nxp_evk/applications/SConscript new file mode 100644 index 0000000000..2588714bbe --- /dev/null +++ b/bsp/lpc55sxx/lpc55s16_nxp_evk/applications/SConscript @@ -0,0 +1,19 @@ +import rtconfig +from building import * + +cwd = GetCurrentDir() +src = Glob('main.c') +CPPPATH = [cwd] + +# add for startup script +if rtconfig.PLATFORM in ['gcc']: + CPPDEFINES = ['__START=entry'] +else: + CPPDEFINES = [] + +if GetDepend('BSP_USING_SDIO'): + src += ['mnt.c'] + +group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES=CPPDEFINES) + +Return('group') diff --git a/bsp/lpc55sxx/lpc55s16_nxp_evk/applications/main.c b/bsp/lpc55sxx/lpc55s16_nxp_evk/applications/main.c new file mode 100644 index 0000000000..41a19db8f3 --- /dev/null +++ b/bsp/lpc55sxx/lpc55s16_nxp_evk/applications/main.c @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2019-2020, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-10-24 Magicoe first version + * 2020-01-10 Kevin/Karl Add PS demo + * 2020-09-21 supperthomas fix the main.c + * + */ + +#include +#include "drv_pin.h" + +/* defined the LED pin: GPIO1_IO4 */ +/* GPIO1_4 is Blue LED */ +#define LEDB_PIN GET_PINS(1, 6) + + +int main(void) +{ +#if defined(__CC_ARM) + rt_kprintf("using armcc, version: %d\n", __ARMCC_VERSION); +#elif defined(__clang__) + rt_kprintf("using armclang, version: %d\n", __ARMCC_VERSION); +#elif defined(__ICCARM__) + rt_kprintf("using iccarm, version: %d\n", __VER__); +#elif defined(__GNUC__) + rt_kprintf("using gcc, version: %d.%d\n", __GNUC__, __GNUC_MINOR__); +#endif + + rt_pin_mode(LEDB_PIN, PIN_MODE_OUTPUT); /* Set GPIO as Output */ + while (1) + { + rt_pin_write(LEDB_PIN, PIN_HIGH); /* Set GPIO output 1 */ + rt_thread_mdelay(500); /* Delay 500mS */ + rt_pin_write(LEDB_PIN, PIN_LOW); /* Set GPIO output 0 */ + rt_thread_mdelay(500); /* Delay 500mS */ + } +} + +// end file diff --git a/bsp/lpc55sxx/lpc55s16_nxp_evk/applications/mnt.c b/bsp/lpc55sxx/lpc55s16_nxp_evk/applications/mnt.c new file mode 100644 index 0000000000..a849c04619 --- /dev/null +++ b/bsp/lpc55sxx/lpc55s16_nxp_evk/applications/mnt.c @@ -0,0 +1,32 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * sdio filesystem support + * Change Logs: + * Date Author Notes + * 2021-10-10 supperthomas first version + */ +#include "dfs_fs.h" +#include +#include + +#ifdef BSP_USING_SDIO + +/** + * @brief SDIO filesystem init + * @param void + * @retval 0: filesystem init success, -1: filesystem init failed + */ + +static int sdio_fs_init(void) +{ + int result = 0; + dfs_mount("sdcard0", "/", "elm", 0, 0); + return result; +} + +INIT_ENV_EXPORT(sdio_fs_init); + +#endif /* BSP_USING_SDIO */ diff --git a/bsp/lpc55sxx/lpc55s16_nxp_evk/applications/tfm_ps.c b/bsp/lpc55sxx/lpc55s16_nxp_evk/applications/tfm_ps.c new file mode 100644 index 0000000000..2c99e47402 --- /dev/null +++ b/bsp/lpc55sxx/lpc55s16_nxp_evk/applications/tfm_ps.c @@ -0,0 +1,110 @@ +/* + * Copyright (c) 2019-2020, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-01-10 Kevin/Karl Add PS demo + * + */ + +#include +#include +#include "tfm_ns_lock.h" +#include "psa_protected_storage.h" + +#define TEST_UID_A 2U +#define ASSET_A "THEQUICKBROWNFOXJUMPSOVERALAZYDOG" +#define ASSET_A_SIZE (sizeof( ASSET_A ) - 1) +#define RESETDATA "THISIS" +#define RESETDATA_SIZE (sizeof( RESETDATA ) - 1) +#define READ_LENGTH (ASSET_A_SIZE > RESETDATA_SIZE ? \ + ASSET_A_SIZE : RESETDATA_SIZE) + +void protected_storage_demo_thread(void * parameters) +{ + psa_ps_status_t status; + const psa_ps_uid_t uid = TEST_UID_A; + const psa_ps_create_flags_t flags = PSA_PS_FLAG_NONE; + uint8_t write_data[] = ASSET_A; + const uint32_t data_length = ASSET_A_SIZE; + uint8_t rewrite_data[] = RESETDATA; + const uint32_t reset_data_length = RESETDATA_SIZE; + uint8_t get_data[READ_LENGTH]; + uint32_t counter = 0; + + tfm_ns_lock_init(); + + for ( ; ; ) + { + /* Call TF-M protected storage service and set the asset. */ + status = psa_ps_set(uid, data_length, write_data, flags); + if (status != PSA_PS_SUCCESS) + { + rt_kprintf("[Protected Storage Asset A Set Round %ld] Fail\r\n", counter); + for( ; ; ); + } + + rt_kprintf("[Protected Storage Asset A Set Round %ld] Success\r\n", counter); + + /* Read the asset. */ + status = psa_ps_get(uid, 0, data_length, get_data); + if (status != PSA_PS_SUCCESS) + { + rt_kprintf("[Protected Storage Asset A Get Round %ld] Fail\r\n", counter); + for ( ; ; ); + } + + rt_kprintf("[Protected Storage Asset A Get Round %ld] Success\r\n", counter); + + /* Check the read data. */ + if (memcmp(write_data, get_data, sizeof(write_data) - 1) != 0) + { + rt_kprintf("[Protected Storage Asset A Get Round %ld] Get the wrong data\r\n", counter); + for ( ; ; ); + } + + /* Change the asset. */ + status = psa_ps_set(uid, reset_data_length, rewrite_data, flags); + if (status != PSA_PS_SUCCESS) + { + rt_kprintf("[Protected Storage Asset A Reset Round %ld] Fail\r\n", counter); + } + + rt_kprintf("[Protected Storage Asset A Reset Round %ld] Success\r\n", counter); + + /* Read the asset. */ + status = psa_ps_get(uid, 0, reset_data_length, get_data); + if (status != PSA_PS_SUCCESS) + { + rt_kprintf("[Protected Storage Asset A Get Round %ld] Fail\r\n", counter); + for ( ; ; ); + } + + rt_kprintf("[Protected Storage Asset A Get Round %ld] Success\r\n", counter); + + /* Check the read data. */ + if (memcmp(rewrite_data, get_data, sizeof(rewrite_data) - 1) != 0) + { + rt_kprintf("[Protected Storage Asset A Get Round %ld] Get the wrong data\r\n", counter); + for ( ; ; ); + } + + /* Remove the asset. */ + status = psa_ps_remove(uid); + if (status != PSA_PS_SUCCESS) + { + rt_kprintf("[Protected Storage Asset A Remove Round %ld] Fail\r\n", counter); + for ( ; ; ); + } + + rt_kprintf("[Protected Storage Asset A Remove Round %ld] Success\r\n\n", counter); + + /* Wait for a second. */ + rt_thread_mdelay(1000); + counter++; + } +} + +// end file diff --git a/bsp/lpc55sxx/lpc55s16_nxp_evk/board/Kconfig b/bsp/lpc55sxx/lpc55s16_nxp_evk/board/Kconfig new file mode 100644 index 0000000000..fd23ae69ce --- /dev/null +++ b/bsp/lpc55sxx/lpc55s16_nxp_evk/board/Kconfig @@ -0,0 +1,224 @@ +menu "Hardware Drivers Config" + +config SOC_LPC55S16 + bool + select SOC_LPC55S16_SERIES + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN + default y + +menu "On-chip Peripheral Drivers" + + config BSP_USING_DMA + bool "Enable DMA" + select RT_USING_DMA + default n + + config BSP_USING_PIN + bool "Enable GPIO" + select RT_USING_PIN + default y + + menuconfig BSP_USING_UART + config BSP_USING_UART + bool "Enable UART" + select RT_USING_UART + default y + + if BSP_USING_UART + config BSP_USING_UART0 + bool "Enable Flexcomm0 as UART" + default y + if BSP_USING_UART0 + choice + prompt "Select UART0 badurate" + default HW_UART0_BAUDRATE_115200 + + config HW_UART0_BAUDRATE_9600 + bool "Badurate 9600" + + config HW_UART0_BAUDRATE_115200 + bool "Badurate 115200" + endchoice + endif + + config BSP_USING_UART2 + bool "Enable Flexcomm2 as UART" + default n + if BSP_USING_UART2 + choice + prompt "Select UART2 badurate" + default HW_UART2_BAUDRATE_115200 + + config HW_UART2_BAUDRATE_9600 + bool "Badurate 9600" + + config HW_UART2_BAUDRATE_115200 + bool "Badurate 115200" + endchoice + endif + endif + + + menuconfig BSP_USING_I2C + config BSP_USING_I2C + bool "Enable I2C" + select RT_USING_I2C + default y + + if BSP_USING_I2C + config BSP_USING_I2C1 + bool "Enable Flexcomm1 I2C" + default y + if BSP_USING_I2C1 + choice + prompt "Select I2C1 badurate" + default HW_I2C1_BAUDRATE_100kHZ + + config HW_I2C1_BAUDRATE_100kHZ + bool "Badurate 100kHZ" + + config HW_I2C1_BAUDRATE_400kHZ + bool "Badurate 400kHZ" + endchoice + endif + + config BSP_USING_I2C4 + bool "Enable Flexcomm4 I2C" + default y + if BSP_USING_I2C4 + choice + prompt "Select I2C4 badurate" + default HW_I2C4_BAUDRATE_100kHZ + + config HW_I2C4_BAUDRATE_100kHZ + bool "Badurate 100kHZ" + + config HW_I2C4_BAUDRATE_400kHZ + bool "Badurate 400kHZ" + endchoice + endif + endif + + menuconfig BSP_USING_SPI + config BSP_USING_SPI + bool "Enable SPI" + select RT_USING_SPI + default y + + if BSP_USING_SPI + config BSP_USING_SPI3 + bool "Enable Flexcomm3 as SPI" + default n + + config BSP_USING_SPI8 + bool "Enable Flexcomm8 as High Speed SPI" + default y + endif + + menuconfig BSP_USING_ADC + config BSP_USING_ADC + bool "Enable ADC Channel" + select RT_USING_ADC + default y + + if BSP_USING_ADC + config BSP_USING_ADC0_CH0 + bool "Enable ADC0 Channel0" + default y + + config BSP_USING_ADC0_CH1 + bool "Enable ADC0 Channel1" + default n + endif + + config BSP_USING_SDIO + bool "Enable SDIO SD Card Interface" + select RT_USING_SDIO + select RT_USING_DFS + select RT_USING_DFS_ELMFAT + default y + + config BSP_USING_RTC + bool "Enable RTC" + select RT_USING_RTC + default y + + config BSP_USING_WDT + bool "Enable WatchDog" + select RT_USING_WDT + default n + + menuconfig BSP_USING_HWTIMER + config BSP_USING_HWTIMER + bool "Enable Timer" + select RT_USING_HWTIMER + default y + + if BSP_USING_HWTIMER + config BSP_USING_CTIMER0 + bool "Enable CIMER0" + default y + + config BSP_USING_CTIMER1 + bool "Enable CIMER1" + default n + + config BSP_USING_CTIMER3 + bool "Enable CIMER3" + default n + + config BSP_USING_CTIMER4 + bool "Enable CIMER4" + default n + endif + + menuconfig BSP_USING_PWM + config BSP_USING_PWM + bool "Enable PWM" + select RT_USING_PWM + default y + + if BSP_USING_PWM + config BSP_USING_CTIMER2_MAT0 + bool "Enable CIMER2 Match0 as PWM output" + default y + + config BSP_USING_CTIMER2_MAT1 + bool "Enable CIMER2 Match1 as PWM output" + default n + + config BSP_USING_CTIMER2_MAT2 + bool "Enable CIMER2 Match2 as PWM output" + default n + endif +endmenu + +menu "Onboard Peripheral Drivers" + config BSP_USING_LED + bool "Enable RGB LED" + select RT_USING_LED + default y + + config BSP_USING_KEY + bool "Enable Button " + select RT_USING_KEY + default y + + config BSP_USING_MMA8562 + bool "Enable MMA8562" + select BSP_USING_I2C4 + default y + if BSP_USING_MMA8562 + config BSP_USING_MMA8562I2C + string "the device name for 3-Axis Sensor" + default "i2c4" + endif + +endmenu + +menu "Board extended module Drivers" + +endmenu + +endmenu diff --git a/bsp/lpc55sxx/lpc55s16_nxp_evk/board/MCUX_Config/board/clock_config.c b/bsp/lpc55sxx/lpc55s16_nxp_evk/board/MCUX_Config/board/clock_config.c new file mode 100644 index 0000000000..fa158a2e20 --- /dev/null +++ b/bsp/lpc55sxx/lpc55s16_nxp_evk/board/MCUX_Config/board/clock_config.c @@ -0,0 +1,380 @@ +/* + * Copyright 2017-2018 ,2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ +/* + * How to set up clock using clock driver functions: + * + * 1. Setup clock sources. + * + * 2. Set up wait states of the flash. + * + * 3. Set up all dividers. + * + * 4. Set up all selectors to provide selected clocks. + */ + +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Clocks v7.0 +processor: LPC55S16 +package_id: LPC55S16JBD100 +mcu_data: ksdk2_0 +processor_version: 9.0.0 +board: LPCXpresso55S16 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ + +#include "fsl_power.h" +#include "fsl_clock.h" +#include "clock_config.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ +/* System clock frequency. */ +extern uint32_t SystemCoreClock; + +/******************************************************************************* + ************************ BOARD_InitBootClocks function ************************ + ******************************************************************************/ +void BOARD_InitBootClocks(void) +{ + BOARD_BootClockPLL150M(); +} + +/******************************************************************************* + ******************** Configuration BOARD_BootClockFRO12M ********************** + ******************************************************************************/ +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!Configuration +name: BOARD_BootClockFRO12M +outputs: +- {id: FRO_12MHz_clock.outFreq, value: 12 MHz} +- {id: System_clock.outFreq, value: 12 MHz} +settings: +- {id: ANALOG_CONTROL_FRO192M_CTRL_ENDI_FRO_96M_CFG, value: Enable} +sources: +- {id: ANACTRL.fro_hf.outFreq, value: 96 MHz} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ + +/******************************************************************************* + * Variables for BOARD_BootClockFRO12M configuration + ******************************************************************************/ +/******************************************************************************* + * Code for BOARD_BootClockFRO12M configuration + ******************************************************************************/ +void BOARD_BootClockFRO12M(void) +{ +#ifndef SDK_SECONDARY_CORE + /*!< Set up the clock sources */ + /*!< Configure FRO192M */ + POWER_DisablePD(kPDRUNCFG_PD_FRO192M); /*!< Ensure FRO is on */ + CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */ + CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */ + + CLOCK_SetupFROClocking(96000000U); /* Enable FRO HF(96MHz) output */ + + POWER_SetVoltageForFreq(12000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */ + CLOCK_SetFLASHAccessCyclesForFreq(12000000U); /*!< Set FLASH wait states for core */ + + /*!< Set up dividers */ + CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */ + + /*!< Set up clock selectors - Attach clocks to the peripheries */ + CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO12M */ + + /*< Set SystemCoreClock variable. */ + SystemCoreClock = BOARD_BOOTCLOCKFRO12M_CORE_CLOCK; +#endif +} + +/******************************************************************************* + ******************* Configuration BOARD_BootClockFROHF96M ********************* + ******************************************************************************/ +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!Configuration +name: BOARD_BootClockFROHF96M +outputs: +- {id: FRO_12MHz_clock.outFreq, value: 12 MHz} +- {id: System_clock.outFreq, value: 96 MHz} +settings: +- {id: ANALOG_CONTROL_FRO192M_CTRL_ENDI_FRO_96M_CFG, value: Enable} +- {id: SYSCON.MAINCLKSELA.sel, value: ANACTRL.fro_hf_clk} +sources: +- {id: ANACTRL.fro_hf.outFreq, value: 96 MHz} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ + +/******************************************************************************* + * Variables for BOARD_BootClockFROHF96M configuration + ******************************************************************************/ +/******************************************************************************* + * Code for BOARD_BootClockFROHF96M configuration + ******************************************************************************/ +void BOARD_BootClockFROHF96M(void) +{ +#ifndef SDK_SECONDARY_CORE + /*!< Set up the clock sources */ + /*!< Configure FRO192M */ + POWER_DisablePD(kPDRUNCFG_PD_FRO192M); /*!< Ensure FRO is on */ + CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */ + CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */ + + CLOCK_SetupFROClocking(96000000U); /* Enable FRO HF(96MHz) output */ + + POWER_SetVoltageForFreq(96000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */ + CLOCK_SetFLASHAccessCyclesForFreq(96000000U); /*!< Set FLASH wait states for core */ + + /*!< Set up dividers */ + CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */ + + /*!< Set up clock selectors - Attach clocks to the peripheries */ + CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO_HF */ + + /*< Set SystemCoreClock variable. */ + SystemCoreClock = BOARD_BOOTCLOCKFROHF96M_CORE_CLOCK; +#endif +} + +/******************************************************************************* + ******************** Configuration BOARD_BootClockPLL100M ********************* + ******************************************************************************/ +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!Configuration +name: BOARD_BootClockPLL100M +outputs: +- {id: FRO_12MHz_clock.outFreq, value: 12 MHz} +- {id: System_clock.outFreq, value: 100 MHz} +settings: +- {id: PLL0_Mode, value: Normal} +- {id: ANALOG_CONTROL_FRO192M_CTRL_ENDI_FRO_96M_CFG, value: Enable} +- {id: ENABLE_CLKIN_ENA, value: Enabled} +- {id: ENABLE_SYSTEM_CLK_OUT, value: Enabled} +- {id: SYSCON.MAINCLKSELB.sel, value: SYSCON.PLL0_BYPASS} +- {id: SYSCON.PLL0CLKSEL.sel, value: SYSCON.CLK_IN_EN} +- {id: SYSCON.PLL0M_MULT.scale, value: '100', locked: true} +- {id: SYSCON.PLL0N_DIV.scale, value: '4', locked: true} +- {id: SYSCON.PLL0_PDEC.scale, value: '4', locked: true} +sources: +- {id: ANACTRL.fro_hf.outFreq, value: 96 MHz} +- {id: SYSCON.XTAL32M.outFreq, value: 16 MHz, enabled: true} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ + +/******************************************************************************* + * Variables for BOARD_BootClockPLL100M configuration + ******************************************************************************/ +/******************************************************************************* + * Code for BOARD_BootClockPLL100M configuration + ******************************************************************************/ +void BOARD_BootClockPLL100M(void) +{ +#ifndef SDK_SECONDARY_CORE + /*!< Set up the clock sources */ + /*!< Configure FRO192M */ + POWER_DisablePD(kPDRUNCFG_PD_FRO192M); /*!< Ensure FRO is on */ + CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */ + CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */ + + CLOCK_SetupFROClocking(96000000U); /* Enable FRO HF(96MHz) output */ + + /*!< Configure XTAL32M */ + POWER_DisablePD(kPDRUNCFG_PD_XTAL32M); /* Ensure XTAL32M is powered */ + POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M); /* Ensure XTAL32M is powered */ + CLOCK_SetupExtClocking(16000000U); /* Enable clk_in clock */ + SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK; /* Enable clk_in from XTAL32M clock */ + ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK; /* Enable High speed Crystal oscillator output to system */ + + POWER_SetVoltageForFreq(100000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */ + CLOCK_SetFLASHAccessCyclesForFreq(100000000U); /*!< Set FLASH wait states for core */ + + /*!< Set up PLL */ + CLOCK_AttachClk(kEXT_CLK_to_PLL0); /*!< Switch PLL0CLKSEL to EXT_CLK */ + POWER_DisablePD(kPDRUNCFG_PD_PLL0); /* Ensure PLL is on */ + POWER_DisablePD(kPDRUNCFG_PD_PLL0_SSCG); + const pll_setup_t pll0Setup = { + .pllctrl = SYSCON_PLL0CTRL_CLKEN_MASK | SYSCON_PLL0CTRL_SELI(53U) | SYSCON_PLL0CTRL_SELP(26U), + .pllndec = SYSCON_PLL0NDEC_NDIV(4U), + .pllpdec = SYSCON_PLL0PDEC_PDIV(2U), + .pllsscg = {0x0U,(SYSCON_PLL0SSCG1_MDIV_EXT(100U) | SYSCON_PLL0SSCG1_SEL_EXT_MASK)}, + .pllRate = 100000000U, + .flags = PLL_SETUPFLAG_WAITLOCK + }; + CLOCK_SetPLL0Freq(&pll0Setup); /*!< Configure PLL0 to the desired values */ + + /*!< Set up dividers */ + CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */ + + /*!< Set up clock selectors - Attach clocks to the peripheries */ + CLOCK_AttachClk(kPLL0_to_MAIN_CLK); /*!< Switch MAIN_CLK to PLL0 */ + + /*< Set SystemCoreClock variable. */ + SystemCoreClock = BOARD_BOOTCLOCKPLL100M_CORE_CLOCK; +#endif +} + +/******************************************************************************* + ******************** Configuration BOARD_BootClockPLL150M ********************* + ******************************************************************************/ +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!Configuration +name: BOARD_BootClockPLL150M +called_from_default_init: true +outputs: +- {id: FRO_12MHz_clock.outFreq, value: 12 MHz} +- {id: System_clock.outFreq, value: 150 MHz} +settings: +- {id: PLL0_Mode, value: Normal} +- {id: ENABLE_CLKIN_ENA, value: Enabled} +- {id: ENABLE_SYSTEM_CLK_OUT, value: Enabled} +- {id: SYSCON.MAINCLKSELB.sel, value: SYSCON.PLL0_BYPASS} +- {id: SYSCON.PLL0CLKSEL.sel, value: SYSCON.CLK_IN_EN} +- {id: SYSCON.PLL0M_MULT.scale, value: '150', locked: true} +- {id: SYSCON.PLL0N_DIV.scale, value: '8', locked: true} +- {id: SYSCON.PLL0_PDEC.scale, value: '2', locked: true} +sources: +- {id: SYSCON.XTAL32M.outFreq, value: 16 MHz, enabled: true} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ + +/******************************************************************************* + * Variables for BOARD_BootClockPLL150M configuration + ******************************************************************************/ +/******************************************************************************* + * Code for BOARD_BootClockPLL150M configuration + ******************************************************************************/ +void BOARD_BootClockPLL150M(void) +{ +#ifndef SDK_SECONDARY_CORE + /*!< Set up the clock sources */ + /*!< Configure FRO192M */ + POWER_DisablePD(kPDRUNCFG_PD_FRO192M); /*!< Ensure FRO is on */ + CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */ + CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */ + + /*!< Configure XTAL32M */ + POWER_DisablePD(kPDRUNCFG_PD_XTAL32M); /* Ensure XTAL32M is powered */ + POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M); /* Ensure XTAL32M is powered */ + CLOCK_SetupExtClocking(16000000U); /* Enable clk_in clock */ + SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK; /* Enable clk_in from XTAL32M clock */ + ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK; /* Enable High speed Crystal oscillator output to system */ + + POWER_SetVoltageForFreq(150000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */ + CLOCK_SetFLASHAccessCyclesForFreq(150000000U); /*!< Set FLASH wait states for core */ + + /*!< Set up PLL */ + CLOCK_AttachClk(kEXT_CLK_to_PLL0); /*!< Switch PLL0CLKSEL to EXT_CLK */ + POWER_DisablePD(kPDRUNCFG_PD_PLL0); /* Ensure PLL is on */ + POWER_DisablePD(kPDRUNCFG_PD_PLL0_SSCG); + const pll_setup_t pll0Setup = { + .pllctrl = SYSCON_PLL0CTRL_CLKEN_MASK | SYSCON_PLL0CTRL_SELI(53U) | SYSCON_PLL0CTRL_SELP(31U), + .pllndec = SYSCON_PLL0NDEC_NDIV(8U), + .pllpdec = SYSCON_PLL0PDEC_PDIV(1U), + .pllsscg = {0x0U,(SYSCON_PLL0SSCG1_MDIV_EXT(150U) | SYSCON_PLL0SSCG1_SEL_EXT_MASK)}, + .pllRate = 150000000U, + .flags = PLL_SETUPFLAG_WAITLOCK + }; + CLOCK_SetPLL0Freq(&pll0Setup); /*!< Configure PLL0 to the desired values */ + + /*!< Set up dividers */ + CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */ + + /*!< Set up clock selectors - Attach clocks to the peripheries */ + CLOCK_AttachClk(kPLL0_to_MAIN_CLK); /*!< Switch MAIN_CLK to PLL0 */ + + /*< Set SystemCoreClock variable. */ + SystemCoreClock = BOARD_BOOTCLOCKPLL150M_CORE_CLOCK; +#endif +} + +/******************************************************************************* + ******************* Configuration BOARD_BootClockPLL1_150M ******************** + ******************************************************************************/ +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!Configuration +name: BOARD_BootClockPLL1_150M +outputs: +- {id: FRO_12MHz_clock.outFreq, value: 12 MHz} +- {id: System_clock.outFreq, value: 150 MHz} +settings: +- {id: PLL1_Mode, value: Normal} +- {id: ENABLE_CLKIN_ENA, value: Enabled} +- {id: ENABLE_SYSTEM_CLK_OUT, value: Enabled} +- {id: SYSCON.MAINCLKSELB.sel, value: SYSCON.PLL1_BYPASS} +- {id: SYSCON.PLL1CLKSEL.sel, value: SYSCON.CLK_IN_EN} +- {id: SYSCON.PLL1M_MULT.scale, value: '150', locked: true} +- {id: SYSCON.PLL1N_DIV.scale, value: '8', locked: true} +- {id: SYSCON.PLL1_PDEC.scale, value: '2', locked: true} +sources: +- {id: SYSCON.XTAL32M.outFreq, value: 16 MHz, enabled: true} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ + +/******************************************************************************* + * Variables for BOARD_BootClockPLL1_150M configuration + ******************************************************************************/ +/******************************************************************************* + * Code for BOARD_BootClockPLL1_150M configuration + ******************************************************************************/ +void BOARD_BootClockPLL1_150M(void) +{ +#ifndef SDK_SECONDARY_CORE + /*!< Set up the clock sources */ + /*!< Configure FRO192M */ + POWER_DisablePD(kPDRUNCFG_PD_FRO192M); /*!< Ensure FRO is on */ + CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */ + CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */ + + /*!< Configure XTAL32M */ + POWER_DisablePD(kPDRUNCFG_PD_XTAL32M); /* Ensure XTAL32M is powered */ + POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M); /* Ensure XTAL32M is powered */ + CLOCK_SetupExtClocking(16000000U); /* Enable clk_in clock */ + SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK; /* Enable clk_in from XTAL32M clock */ + ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK; /* Enable High speed Crystal oscillator output to system */ + + POWER_SetVoltageForFreq(150000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */ + CLOCK_SetFLASHAccessCyclesForFreq(150000000U); /*!< Set FLASH wait states for core */ + + /*!< Set up PLL1 */ + CLOCK_AttachClk(kEXT_CLK_to_PLL1); /*!< Switch PLL1CLKSEL to EXT_CLK */ + POWER_DisablePD(kPDRUNCFG_PD_PLL1); /* Ensure PLL is on */ + const pll_setup_t pll1Setup = { + .pllctrl = SYSCON_PLL1CTRL_CLKEN_MASK | SYSCON_PLL1CTRL_SELI(53U) | SYSCON_PLL1CTRL_SELP(31U), + .pllndec = SYSCON_PLL1NDEC_NDIV(8U), + .pllpdec = SYSCON_PLL1PDEC_PDIV(1U), + .pllmdec = SYSCON_PLL1MDEC_MDIV(150U), + .pllRate = 150000000U, + .flags = PLL_SETUPFLAG_WAITLOCK + }; + CLOCK_SetPLL1Freq(&pll1Setup); /*!< Configure PLL1 to the desired values */ + + /*!< Set up dividers */ + CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */ + + /*!< Set up clock selectors - Attach clocks to the peripheries */ + CLOCK_AttachClk(kPLL1_to_MAIN_CLK); /*!< Switch MAIN_CLK to PLL1 */ + + /*< Set SystemCoreClock variable. */ + SystemCoreClock = BOARD_BOOTCLOCKPLL1_150M_CORE_CLOCK; +#endif +} + diff --git a/bsp/lpc55sxx/lpc55s16_nxp_evk/board/MCUX_Config/board/clock_config.h b/bsp/lpc55sxx/lpc55s16_nxp_evk/board/MCUX_Config/board/clock_config.h new file mode 100644 index 0000000000..f5a8ec7d75 --- /dev/null +++ b/bsp/lpc55sxx/lpc55s16_nxp_evk/board/MCUX_Config/board/clock_config.h @@ -0,0 +1,173 @@ +/* + * Copyright 2017-2018 ,2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +#include "fsl_common.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define BOARD_XTAL0_CLK_HZ 16000000U /*!< Board xtal frequency in Hz */ +#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32K frequency in Hz */ + +/******************************************************************************* + ************************ BOARD_InitBootClocks function ************************ + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes default configuration of clocks. + * + */ +void BOARD_InitBootClocks(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ******************** Configuration BOARD_BootClockFRO12M ********************** + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockFRO12M configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKFRO12M_CORE_CLOCK 12000000U /*!< Core clock frequency: 12000000Hz */ + + +/******************************************************************************* + * API for BOARD_BootClockFRO12M configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockFRO12M(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ******************* Configuration BOARD_BootClockFROHF96M ********************* + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockFROHF96M configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKFROHF96M_CORE_CLOCK 96000000U /*!< Core clock frequency: 96000000Hz */ + + +/******************************************************************************* + * API for BOARD_BootClockFROHF96M configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockFROHF96M(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ******************** Configuration BOARD_BootClockPLL100M ********************* + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockPLL100M configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKPLL100M_CORE_CLOCK 100000000U /*!< Core clock frequency: 100000000Hz */ + + +/******************************************************************************* + * API for BOARD_BootClockPLL100M configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockPLL100M(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ******************** Configuration BOARD_BootClockPLL150M ********************* + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockPLL150M configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKPLL150M_CORE_CLOCK 150000000U /*!< Core clock frequency: 150000000Hz */ + + +/******************************************************************************* + * API for BOARD_BootClockPLL150M configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockPLL150M(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ******************* Configuration BOARD_BootClockPLL1_150M ******************** + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockPLL1_150M configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKPLL1_150M_CORE_CLOCK 150000000U /*!< Core clock frequency: 150000000Hz */ + + +/******************************************************************************* + * API for BOARD_BootClockPLL1_150M configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockPLL1_150M(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */ + diff --git a/bsp/lpc55sxx/lpc55s16_nxp_evk/board/MCUX_Config/board/pin_mux.c b/bsp/lpc55sxx/lpc55s16_nxp_evk/board/MCUX_Config/board/pin_mux.c new file mode 100644 index 0000000000..93236b51ea --- /dev/null +++ b/bsp/lpc55sxx/lpc55s16_nxp_evk/board/MCUX_Config/board/pin_mux.c @@ -0,0 +1,118 @@ +/* + * Copyright 2017-2020 ,2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +/* clang-format off */ +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v9.0 +processor: LPC55S16 +package_id: LPC55S16JBD100 +mcu_data: ksdk2_0 +processor_version: 9.0.0 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ +/* clang-format on */ + +#include "fsl_common.h" +#include "fsl_iocon.h" +#include "pin_mux.h" + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitBootPins + * Description : Calls initialization functions. + * + * END ****************************************************************************************************************/ +void BOARD_InitBootPins(void) +{ + BOARD_InitPins(); +} + +/* clang-format off */ +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitPins: +- options: {callFromInitBoot: 'true', coreID: cm33_core0, enableClock: 'true'} +- pin_list: + - {pin_num: '92', peripheral: FLEXCOMM0, signal: RXD_SDA_MOSI_DATA, pin_signal: PIO0_29/FC0_RXD_SDA_MOSI_DATA/CTIMER2_MAT3/SCT0_OUT8/CMP0_OUT/PLU_OUT2/SECURE_GPIO0_29, + mode: inactive, slew_rate: standard, invert: disabled, open_drain: disabled} + - {pin_num: '94', peripheral: FLEXCOMM0, signal: TXD_SCL_MISO_WS, pin_signal: PIO0_30/FC0_TXD_SCL_MISO_WS/CTIMER0_MAT0/SCT0_OUT9/SECURE_GPIO0_30, mode: inactive, + slew_rate: standard, invert: disabled, open_drain: disabled} + - {pin_num: '21', peripheral: SWD, signal: SWO, pin_signal: PIO0_10/FC6_SCK/CT_INP10/CTIMER2_MAT0/FC1_TXD_SCL_MISO_WS/SCT0_OUT2/SWO/SECURE_GPIO0_10/ADC0_1, mode: inactive, + slew_rate: standard, invert: disabled, open_drain: disabled, asw: disabled} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ +/* clang-format on */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +/* Function assigned for the Cortex-M33 */ +void BOARD_InitPins(void) +{ + /* Enables the clock for the I/O controller.: Enable Clock. */ + CLOCK_EnableClock(kCLOCK_Iocon); + + const uint32_t port0_pin10_config = (/* Pin is configured as SWO */ + IOCON_PIO_FUNC6 | + /* No addition pin function */ + IOCON_PIO_MODE_INACT | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI | + /* Analog switch is open (disabled) */ + IOCON_PIO_ASW_DI); + /* PORT0 PIN10 (coords: 21) is configured as SWO */ + IOCON_PinMuxSet(IOCON, 0U, 10U, port0_pin10_config); + + const uint32_t port0_pin29_config = (/* Pin is configured as FC0_RXD_SDA_MOSI_DATA */ + IOCON_PIO_FUNC1 | + /* No addition pin function */ + IOCON_PIO_MODE_INACT | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT0 PIN29 (coords: 92) is configured as FC0_RXD_SDA_MOSI_DATA */ + IOCON_PinMuxSet(IOCON, 0U, 29U, port0_pin29_config); + + const uint32_t port0_pin30_config = (/* Pin is configured as FC0_TXD_SCL_MISO_WS */ + IOCON_PIO_FUNC1 | + /* No addition pin function */ + IOCON_PIO_MODE_INACT | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT0 PIN30 (coords: 94) is configured as FC0_TXD_SCL_MISO_WS */ + IOCON_PinMuxSet(IOCON, 0U, 30U, port0_pin30_config); +} +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/bsp/lpc55sxx/lpc55s16_nxp_evk/board/MCUX_Config/board/pin_mux.h b/bsp/lpc55sxx/lpc55s16_nxp_evk/board/MCUX_Config/board/pin_mux.h new file mode 100644 index 0000000000..0bc2d0e2da --- /dev/null +++ b/bsp/lpc55sxx/lpc55s16_nxp_evk/board/MCUX_Config/board/pin_mux.h @@ -0,0 +1,61 @@ +/* + * Copyright 2017-2020 ,2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +#ifndef _PIN_MUX_H_ +#define _PIN_MUX_H_ + +/*! + * @addtogroup pin_mux + * @{ + */ + +/*********************************************************************************************************************** + * API + **********************************************************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Calls initialization functions. + * + */ +void BOARD_InitBootPins(void); + +#define IOCON_PIO_ASW_DI 0x00u /*!<@brief Analog switch is open (disabled) */ +#define IOCON_PIO_DIGITAL_EN 0x0100u /*!<@brief Enables digital function */ +#define IOCON_PIO_FUNC1 0x01u /*!<@brief Selects pin function 1 */ +#define IOCON_PIO_FUNC6 0x06u /*!<@brief Selects pin function 6 */ +#define IOCON_PIO_INV_DI 0x00u /*!<@brief Input function is not inverted */ +#define IOCON_PIO_MODE_INACT 0x00u /*!<@brief No addition pin function */ +#define IOCON_PIO_OPENDRAIN_DI 0x00u /*!<@brief Open drain is disabled */ +#define IOCON_PIO_SLEW_STANDARD 0x00u /*!<@brief Standard mode, output slew rate control is enabled */ + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitPins(void); /* Function assigned for the Cortex-M33 */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif /* _PIN_MUX_H_ */ + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/bsp/lpc55sxx/lpc55s16_nxp_evk/board/SConscript b/bsp/lpc55sxx/lpc55s16_nxp_evk/board/SConscript new file mode 100644 index 0000000000..5c740fb347 --- /dev/null +++ b/bsp/lpc55sxx/lpc55s16_nxp_evk/board/SConscript @@ -0,0 +1,16 @@ +from building import * + +cwd = GetCurrentDir() + +# add the general drivers. +src = Split(""" +board.c +MCUX_Config/board/clock_config.c +MCUX_Config/board/pin_mux.c +""") + +CPPPATH = [cwd,cwd + '/MCUX_Config/board'] +CPPDEFINES = ['DEBUG'] +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES=CPPDEFINES) + +Return('group') diff --git a/bsp/lpc55sxx/lpc55s16_nxp_evk/board/board.c b/bsp/lpc55sxx/lpc55s16_nxp_evk/board/board.c new file mode 100644 index 0000000000..612dd1f159 --- /dev/null +++ b/bsp/lpc55sxx/lpc55s16_nxp_evk/board/board.c @@ -0,0 +1,138 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2019-2020, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2009-01-05 Bernard first implementation + * 2010-02-04 Magicoe ported to LPC17xx + * 2010-05-02 Aozima update CMSIS to 130 + * 2017-08-02 XiaoYang porting to LPC54608 bsp + * 2019-08-05 Magicoe porting to LPC55S69-EVK bsp + * 2020-01-01 Karl Add PKG_USING_TFM support + */ + +#include +#include + +#include "board.h" +#include "clock_config.h" +#include "drv_uart.h" + +/** + * This is the timer interrupt service routine. + * + */ +void SysTick_Handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + rt_tick_increase(); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +/** + * This function will initial LPC55Sxx board. + */ +void rt_hw_board_init() +{ + /* Hardware Initialization */ + BOARD_InitPins(); + + CLOCK_EnableClock(kCLOCK_InputMux); + + CLOCK_EnableClock(kCLOCK_Gpio0); + CLOCK_EnableClock(kCLOCK_Gpio1); + + GPIO_PortInit(GPIO, 0); + GPIO_PortInit(GPIO, 1); + + /* NVIC Configuration */ +#define NVIC_VTOR_MASK 0x3FFFFF80 +#ifdef VECT_TAB_RAM + /* Set the Vector Table base location at 0x10000000 */ + SCB->VTOR = (0x10000000 & NVIC_VTOR_MASK); +#else /* VECT_TAB_FLASH */ + +#ifdef PKG_USING_TFM + /* Set the Vector Table base location at 0x00020000 when RTT with TF-M*/ + SCB->VTOR = (0x00020000 & NVIC_VTOR_MASK); +#else + /* Set the Vector Table base location at 0x00000000 */ + SCB->VTOR = (0x00000000 & NVIC_VTOR_MASK); +#endif +#endif + +#ifndef PKG_USING_TFM + /* This init has finished in secure side of TF-M */ + BOARD_BootClockPLL150M(); +#endif + //BOARD_BootClockFROHF96M(); + + SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND); + /* set pend exception priority */ + NVIC_SetPriority(PendSV_IRQn, (1 << __NVIC_PRIO_BITS) - 1); + + /*init uart device*/ + rt_hw_uart_init(); + +#if defined(RT_USING_CONSOLE) && defined(RT_USING_DEVICE) + rt_console_set_device(RT_CONSOLE_DEVICE_NAME); +#endif + +#ifdef RT_USING_COMPONENTS_INIT + /* initialization board with RT-Thread Components */ + rt_components_board_init(); +#endif + +#ifdef RT_USING_HEAP + rt_kprintf("sram heap, begin: 0x%p, end: 0x%p\n", HEAP_BEGIN, HEAP_END); + rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END); +#endif +} + +/** + * This function will called when memory fault. + */ +void MemManage_Handler(void) +{ + extern void HardFault_Handler(void); + + rt_kprintf("Memory Fault!\n"); + HardFault_Handler(); +} + +void rt_hw_us_delay(rt_uint32_t us) +{ + rt_uint32_t ticks; + rt_uint32_t told, tnow, tcnt = 0; + rt_uint32_t reload = SysTick->LOAD; + + ticks = us * reload / (1000000 / RT_TICK_PER_SECOND); + told = SysTick->VAL; + while (1) + { + tnow = SysTick->VAL; + if (tnow != told) + { + if (tnow < told) + { + tcnt += told - tnow; + } + else + { + tcnt += reload - tnow + told; + } + told = tnow; + if (tcnt >= ticks) + { + break; + } + } + } +} diff --git a/bsp/lpc55sxx/lpc55s16_nxp_evk/board/board.h b/bsp/lpc55sxx/lpc55s16_nxp_evk/board/board.h new file mode 100644 index 0000000000..208d73c8f3 --- /dev/null +++ b/bsp/lpc55sxx/lpc55s16_nxp_evk/board/board.h @@ -0,0 +1,71 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2009-09-22 Bernard add board.h to this bsp + * 2010-02-04 Magicoe add board.h to LPC176x bsp + * 2013-12-18 Bernard porting to LPC4088 bsp + * 2017-08-02 XiaoYang porting to LPC54608 bsp + */ + +#ifndef __BOARD_H__ +#define __BOARD_H__ + + +#include + +#include + +#include "clock_config.h" +#include "fsl_common.h" +#include "fsl_reset.h" +#include "fsl_gpio.h" +#include "fsl_iocon.h" +#include "pin_mux.h" + +// + +// +#if defined(__ARMCC_VERSION) +extern int Image$$ARM_LIB_HEAP$$ZI$$Base; +extern int Image$$ARM_LIB_STACK$$ZI$$Base; +#define HEAP_BEGIN ((void *)&Image$$ARM_LIB_HEAP$$ZI$$Base) +#define HEAP_END ((void*)&Image$$ARM_LIB_STACK$$ZI$$Base) +#elif defined(__ICCARM__) +#pragma section="HEAP" +#define HEAP_BEGIN (__segment_end("HEAP")) +#elif defined(__GNUC__) +extern int __HeapBase; +extern int __HeapLimit; +#define HEAP_BEGIN ((void *)&__HeapBase) +#define HEAP_END ((void *)&__HeapLimit) +#endif + +void rt_hw_board_init(void); + +#define BOARD_SDIF_BASEADDR SDIF +#define BOARD_SDIF_CLKSRC kCLOCK_SDio +#define BOARD_SDIF_CLK_FREQ CLOCK_GetFreq(kCLOCK_SDio) +#define BOARD_SDIF_CLK_ATTACH kMAIN_CLK_to_SDIO_CLK +#define BOARD_SDIF_IRQ SDIO_IRQn +#define BOARD_MMC_VCC_SUPPLY kMMC_VoltageWindows270to360 +#define BOARD_SD_CARD_DETECT_PIN 17 +#define BOARD_SD_CARD_DETECT_PORT 0 +#define BOARD_SD_CARD_DETECT_GPIO GPIO +#define BOARD_SD_DETECT_TYPE kSDMMCHOST_DetectCardByHostCD + +#define BOARD_SDIF_CD_GPIO_INIT() \ + { \ + CLOCK_EnableClock(kCLOCK_Gpio2); \ + GPIO_PinInit(BOARD_SD_CARD_DETECT_GPIO, BOARD_SD_CARD_DETECT_PORT, BOARD_SD_CARD_DETECT_PIN, \ + &(gpio_pin_config_t){kGPIO_DigitalInput, 0U}); \ + } +#define BOARD_SDIF_CD_STATUS() \ + GPIO_PinRead(BOARD_SD_CARD_DETECT_GPIO, BOARD_SD_CARD_DETECT_PORT, BOARD_SD_CARD_DETECT_PIN) + +#endif + + diff --git a/bsp/lpc55sxx/lpc55s16_nxp_evk/board/linker_scripts/LPC55S16_flash.icf b/bsp/lpc55sxx/lpc55s16_nxp_evk/board/linker_scripts/LPC55S16_flash.icf new file mode 100644 index 0000000000..1fa04c399b --- /dev/null +++ b/bsp/lpc55sxx/lpc55s16_nxp_evk/board/linker_scripts/LPC55S16_flash.icf @@ -0,0 +1,101 @@ +/* +** ################################################################### +** Processors: LPC55S16JBD100 +** LPC55S16JBD64 +** LPC55S16JEV59 +** LPC55S16JEV98 +** +** Compiler: IAR ANSI C/C++ Compiler for ARM +** Reference manual: LPC55S1x/LPC551x User manual Rev.0.6 15 November 2019 +** Version: rev. 1.1, 2019-12-03 +** Build: b220622 +** +** Abstract: +** Linker file for the IAR ANSI C/C++ Compiler for ARM +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2022 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + + +/* USB BDT size */ +define symbol usb_bdt_size = 0x0; +/* Stack and Heap Sizes */ +if (isdefinedsymbol(__stack_size__)) { + define symbol __size_cstack__ = __stack_size__; +} else { + define symbol __size_cstack__ = 0x0400; +} + +if (isdefinedsymbol(__heap_size__)) { + define symbol __size_heap__ = __heap_size__; +} else { + define symbol __size_heap__ = 0x0400; +} + +define symbol m_interrupts_start = 0x00000000; +define symbol m_interrupts_end = 0x000001FF; + +define symbol m_text_start = 0x00000200; +define symbol m_text_end = 0x0003CFFF; + +define symbol m_data_start = 0x20000000; +define symbol m_data_end = 0x2000FFFF; + +define symbol m_sramx_start = 0x04000000; +define symbol m_sramx_end = 0x04003FFF; + +define symbol m_usb_sram_start = 0x20010000; +define symbol m_usb_sram_end = 0x20013FFF; + +define memory mem with size = 4G; + +define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end] + | mem:[from m_text_start to m_text_end]; +define region DATA_region = mem:[from m_data_start to m_data_end-__size_cstack__]; +define region CSTACK_region = mem:[from m_data_end-__size_cstack__+1 to m_data_end]; +if (isdefinedsymbol(__use_shmem__)) { + define region rpmsg_sh_mem_region = mem:[from rpmsg_sh_mem_start to rpmsg_sh_mem_end]; +} + +define block CSTACK with alignment = 8, size = __size_cstack__ { }; +define block HEAP with alignment = 8, size = __size_heap__ { }; +define block RW { readwrite }; +define block ZI { zi }; + +/* regions for USB */ +define region USB_BDT_region = mem:[from m_usb_sram_start to m_usb_sram_start + usb_bdt_size - 1]; +define region USB_SRAM_region = mem:[from m_usb_sram_start + usb_bdt_size to m_usb_sram_end]; +place in USB_BDT_region { section m_usb_bdt }; +place in USB_SRAM_region { section m_usb_global }; + +initialize by copy { readwrite, section .textrw }; + +if (isdefinedsymbol(__USE_DLIB_PERTHREAD)) +{ + /* Required in a multi-threaded application */ + initialize by copy with packing = none { section __DLIB_PERTHREAD }; +} + +do not initialize { section .noinit, section m_usb_bdt, section m_usb_global }; +if (isdefinedsymbol(__use_shmem__)) { + do not initialize { section rpmsg_sh_mem_section }; +} + +place at address mem: m_interrupts_start { readonly section .intvec }; +place in TEXT_region { readonly }; +place in DATA_region { block RW }; +place in DATA_region { block ZI }; +place in DATA_region { last block HEAP }; +place in CSTACK_region { block CSTACK }; + + + diff --git a/bsp/lpc55sxx/lpc55s16_nxp_evk/board/linker_scripts/LPC55S16_flash.ld b/bsp/lpc55sxx/lpc55s16_nxp_evk/board/linker_scripts/LPC55S16_flash.ld new file mode 100644 index 0000000000..1897ad1137 --- /dev/null +++ b/bsp/lpc55sxx/lpc55s16_nxp_evk/board/linker_scripts/LPC55S16_flash.ld @@ -0,0 +1,215 @@ +/* +** ################################################################### +** Processors: LPC55S16JBD100 +** LPC55S16JBD64 +** LPC55S16JEV59 +** LPC55S16JEV98 +** +** Compiler: GNU C Compiler +** Reference manual: LPC55S1x/LPC551x User manual Rev.0.6 15 November 2019 +** Version: rev. 1.1, 2019-12-03 +** Build: b220622 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2022 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + + + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0800; + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x00000000, LENGTH = 0x00000200 + m_text (RX) : ORIGIN = 0x00000200, LENGTH = 0x0003CE00 + m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00010000 + m_sramx (RW) : ORIGIN = 0x04000000, LENGTH = 0x00004000 + m_usb_sram (RW) : ORIGIN = 0x20010000, LENGTH = 0x00004000 +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into internal flash */ + .interrupts : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + /* The program code and other data goes into internal flash */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(.ramfunc*) /* for functions in ram */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + m_usb_bdt (NOLOAD) : + { + . = ALIGN(512); + *(m_usb_bdt) + } > m_usb_sram + + m_usb_global (NOLOAD) : + { + *(m_usb_global) + } > m_usb_sram + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") +} + diff --git a/bsp/lpc55sxx/lpc55s16_nxp_evk/board/linker_scripts/LPC55S16_flash.scf b/bsp/lpc55sxx/lpc55s16_nxp_evk/board/linker_scripts/LPC55S16_flash.scf new file mode 100644 index 0000000000..99d6a233a2 --- /dev/null +++ b/bsp/lpc55sxx/lpc55s16_nxp_evk/board/linker_scripts/LPC55S16_flash.scf @@ -0,0 +1,86 @@ +#!armclang --target=arm-arm-none-eabi -march=armv8-m.main -E -x c +/* +** ################################################################### +** Processors: LPC55S16JBD100 +** LPC55S16JBD64 +** LPC55S16JEV59 +** LPC55S16JEV98 +** +** Compiler: Keil ARM C/C++ Compiler +** Reference manual: LPC55S1x/LPC551x User manual Rev.0.6 15 November 2019 +** Version: rev. 1.1, 2019-12-03 +** Build: b220622 +** +** Abstract: +** Linker file for the Keil ARM C/C++ Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2022 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + + +/* USB BDT size */ +#define usb_bdt_size 0x0 +/* Sizes */ +#if (defined(__stack_size__)) + #define Stack_Size __stack_size__ +#else + #define Stack_Size 0x0400 +#endif + +#if (defined(__heap_size__)) + #define Heap_Size __heap_size__ +#else + #define Heap_Size 0x0400 +#endif + +#define m_interrupts_start 0x00000000 +#define m_interrupts_size 0x00000200 + +#define m_text_start 0x00000200 +#define m_text_size 0x0003CE00 + +#define m_data_start 0x20000000 +#define m_data_size 0x00010000 + +#define m_sramx_start 0x04000000 +#define m_sramx_size 0x00004000 + +#define m_usb_sram_start 0x20010000 +#define m_usb_sram_size 0x00004000 + +LR_m_text m_interrupts_start m_interrupts_size+m_text_size { ; load region size_region + + VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address + * (.isr_vector,+FIRST) + } + + ER_m_text m_text_start FIXED m_text_size { ; load address = execution address + * (InRoot$$Sections) + .ANY (+RO) + } + + RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data + .ANY (+RW +ZI) + } + ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up + } + ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down + } + + RW_m_usb_bdt m_usb_sram_start UNINIT usb_bdt_size { + * (*m_usb_bdt) + } + + RW_m_usb_ram (m_usb_sram_start + usb_bdt_size) UNINIT (m_usb_sram_size - usb_bdt_size) { + * (*m_usb_global) + } +} diff --git a/bsp/lpc55sxx/lpc55s16_nxp_evk/figures/board.png b/bsp/lpc55sxx/lpc55s16_nxp_evk/figures/board.png new file mode 100644 index 0000000000000000000000000000000000000000..3914ed4e721bf13d064ae72bf7d7aad966b1e9f8 GIT binary patch literal 453829 zcmb4qV{|4#*XwYyhU zSDn*+PVL$irlcT=1dj&~005ArrNmSK0I=DAD=BOem0;rxQIQdtB zG#8c^1_0_}5Z;ZT{?*~^q_iCY0CcDS6tFEbVmAQbt4LZ*Sj|oU{NvD*K)d-eV#{~O zr~Qd{JS}ZC-qehdm6f%?YT|o>Nvz2jHfw`Pk9p*`wEA-g z^_t7B^70uQ$wj;3A7o^#q(=ljHww6SUjbL^PZw{G-f!LB+ugQb*N=p`+b#c#ePFD+ z0)777_#aHsY8&kJzYqTh6Rh)w0sX%X4E}#L;Op>4-r_rR!7J4B-!8U2RE4f{>PXsd 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### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + rtthread-lpc55s16 + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 0 + 0 + 1 + + 8 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 4 + + + + + + + + + + + Segger\JL2CM3.dll + + + + 0 + JL2CM3 + -U723308249 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(6BA02477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO7 -FD20000000 -FC1000 -FN2 -FF0LPC551XX_256.FLM -FS00 -FL040000 -FP0($$Device:LPC55S16JBD100$arm\LPC551XX_256.FLM) -FF1LPC551XX_S_256.FLM -FS110000000 -FL140000 -FP1($$Device:LPC55S16JBD100$arm\LPC551XX_S_256.FLM) + + + 0 + UL2V8M + UL2V8M(-S0 -C0 -P0 -FD20000000 -FC1000 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### uVision Project, (C) Keil Software
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0 + 0 + 0 + 0 + 3 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + + --target=arm-arm-none-eabi + __STDC_LIMIT_MACROS, RT_USING_ARMLIBC, RT_USING_LIBC, __CLK_TCK=RT_TICK_PER_SECOND, __RTTHREAD__, DEBUG + + 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..\Libraries\drivers\drv_led.c + + + drv_pin.c + 1 + ..\Libraries\drivers\drv_pin.c + + + drv_uart.c + 1 + ..\Libraries\drivers\drv_uart.c + + + + + Finsh + + + shell.c + 1 + ..\..\..\components\finsh\shell.c + + + msh.c + 1 + ..\..\..\components\finsh\msh.c + + + msh_parse.c + 1 + ..\..\..\components\finsh\msh_parse.c + + + cmd.c + 1 + ..\..\..\components\finsh\cmd.c + + + + + Kernel + + + clock.c + 1 + ..\..\..\src\clock.c + + + components.c + 1 + ..\..\..\src\components.c + + + device.c + 1 + ..\..\..\src\device.c + + + idle.c + 1 + ..\..\..\src\idle.c + + + ipc.c + 1 + ..\..\..\src\ipc.c + + + irq.c + 1 + ..\..\..\src\irq.c + + + kservice.c + 1 + ..\..\..\src\kservice.c + + + mem.c + 1 + ..\..\..\src\mem.c + + + mempool.c + 1 + ..\..\..\src\mempool.c + + + object.c + 1 + ..\..\..\src\object.c + + + scheduler.c + 1 + ..\..\..\src\scheduler.c + + + thread.c + 1 + ..\..\..\src\thread.c + + + timer.c + 1 + ..\..\..\src\timer.c + + + + + Libraries + + + startup_LPC55S16.s + 2 + ..\Libraries\LPC55S16\LPC55S16\arm\startup_LPC55S16.s + + + fsl_sysctl.c + 1 + ..\Libraries\LPC55S16\LPC55S16\drivers\fsl_sysctl.c + + + fsl_mrt.c + 1 + ..\Libraries\LPC55S16\LPC55S16\drivers\fsl_mrt.c + + + fsl_i2s.c + 1 + ..\Libraries\LPC55S16\LPC55S16\drivers\fsl_i2s.c + + + fsl_inputmux.c + 1 + ..\Libraries\LPC55S16\LPC55S16\drivers\fsl_inputmux.c + + + system_LPC55S16.c + 1 + ..\Libraries\LPC55S16\LPC55S16\system_LPC55S16.c + + + fsl_utick.c + 1 + ..\Libraries\LPC55S16\LPC55S16\drivers\fsl_utick.c + + + fsl_i2c_dma.c + 1 + ..\Libraries\LPC55S16\LPC55S16\drivers\fsl_i2c_dma.c + + + fsl_spi.c + 1 + ..\Libraries\LPC55S16\LPC55S16\drivers\fsl_spi.c + + + fsl_clock.c + 1 + ..\Libraries\LPC55S16\LPC55S16\drivers\fsl_clock.c + + + fsl_pint.c + 1 + ..\Libraries\LPC55S16\LPC55S16\drivers\fsl_pint.c + + + fsl_flexcomm.c + 1 + ..\Libraries\LPC55S16\LPC55S16\drivers\fsl_flexcomm.c + + + fsl_sctimer.c + 1 + ..\Libraries\LPC55S16\LPC55S16\drivers\fsl_sctimer.c + + + fsl_gint.c + 1 + ..\Libraries\LPC55S16\LPC55S16\drivers\fsl_gint.c + + + fsl_crc.c + 1 + ..\Libraries\LPC55S16\LPC55S16\drivers\fsl_crc.c + + + fsl_dma.c + 1 + ..\Libraries\LPC55S16\LPC55S16\drivers\fsl_dma.c + + + fsl_spi_dma.c + 1 + ..\Libraries\LPC55S16\LPC55S16\drivers\fsl_spi_dma.c + + + fsl_gpio.c + 1 + ..\Libraries\LPC55S16\LPC55S16\drivers\fsl_gpio.c + + + fsl_i2c.c + 1 + ..\Libraries\LPC55S16\LPC55S16\drivers\fsl_i2c.c + + + fsl_usart.c + 1 + ..\Libraries\LPC55S16\LPC55S16\drivers\fsl_usart.c + + + fsl_reset.c + 1 + ..\Libraries\LPC55S16\LPC55S16\drivers\fsl_reset.c + + + fsl_common.c + 1 + ..\Libraries\LPC55S16\LPC55S16\drivers\fsl_common.c + + + fsl_power.c + 1 + ..\Libraries\LPC55S16\LPC55S16\drivers\fsl_power.c + + + fsl_cmp.c + 1 + ..\Libraries\LPC55S16\LPC55S16\drivers\fsl_cmp.c + + + fsl_ctimer.c + 1 + ..\Libraries\LPC55S16\LPC55S16\drivers\fsl_ctimer.c + + + fsl_i2s_dma.c + 1 + ..\Libraries\LPC55S16\LPC55S16\drivers\fsl_i2s_dma.c + + + fsl_common_arm.c + 1 + ..\Libraries\LPC55S16\LPC55S16\drivers\fsl_common_arm.c + + + fsl_usart_dma.c + 1 + ..\Libraries\LPC55S16\LPC55S16\drivers\fsl_usart_dma.c + + + fsl_anactrl.c + 1 + ..\Libraries\LPC55S16\LPC55S16\drivers\fsl_anactrl.c + + + fsl_lpadc.c + 1 + ..\Libraries\LPC55S16\LPC55S16\drivers\fsl_lpadc.c + + + fsl_wwdt.c + 1 + ..\Libraries\LPC55S16\LPC55S16\drivers\fsl_wwdt.c + + + fsl_ostimer.c + 1 + ..\Libraries\LPC55S16\LPC55S16\drivers\fsl_ostimer.c + + + + + + + + + + + + + + + + + template + 1 + + + + + diff --git a/bsp/lpc55sxx/lpc55s16_nxp_evk/rtconfig.h b/bsp/lpc55sxx/lpc55s16_nxp_evk/rtconfig.h new file mode 100644 index 0000000000..ee346cfc42 --- /dev/null +++ b/bsp/lpc55sxx/lpc55s16_nxp_evk/rtconfig.h @@ -0,0 +1,216 @@ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ + +/* Automatically generated file; DO NOT EDIT. */ +/* RT-Thread Configuration */ + +#define SOC_LPC55S6x + +/* RT-Thread Kernel */ + +#define RT_NAME_MAX 8 +#define RT_ALIGN_SIZE 4 +#define RT_THREAD_PRIORITY_32 +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 100 +#define RT_USING_OVERFLOW_CHECK +#define RT_USING_HOOK +#define RT_HOOK_USING_FUNC_PTR +#define RT_USING_IDLE_HOOK +#define RT_IDLE_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 256 +#define RT_USING_TIMER_SOFT +#define RT_TIMER_THREAD_PRIO 4 +#define RT_TIMER_THREAD_STACK_SIZE 512 + +/* kservice optimization */ + +#define RT_DEBUG + +/* Inter-Thread communication */ + +#define RT_USING_SEMAPHORE +#define RT_USING_MUTEX +#define RT_USING_EVENT +#define RT_USING_MAILBOX +#define RT_USING_MESSAGEQUEUE + +/* Memory Management */ + +#define RT_USING_MEMPOOL +#define RT_USING_SMALL_MEM +#define RT_USING_SMALL_MEM_AS_HEAP +#define RT_USING_HEAP + +/* Kernel Device Object */ + +#define RT_USING_DEVICE +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLE_DEVICE_NAME "uart0" +#define RT_VER_NUM 0x40101 +#define ARCH_ARM +#define RT_USING_CPU_FFS +#define ARCH_ARM_CORTEX_M +#define ARCH_ARM_CORTEX_FPU +#define ARCH_ARM_CORTEX_SECURE +#define ARCH_ARM_CORTEX_M33 + +/* RT-Thread Components */ + +#define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 2048 +#define RT_MAIN_THREAD_PRIORITY 10 +#define RT_USING_MSH +#define RT_USING_FINSH +#define FINSH_USING_MSH +#define FINSH_THREAD_NAME "tshell" +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 4096 +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 5 +#define FINSH_USING_SYMTAB +#define FINSH_CMD_SIZE 80 +#define MSH_USING_BUILT_IN_COMMANDS +#define FINSH_USING_DESCRIPTION +#define FINSH_ARG_MAX 10 + +/* Device Drivers */ + +#define RT_USING_DEVICE_IPC +#define RT_USING_SERIAL +#define RT_USING_SERIAL_V1 +#define RT_SERIAL_USING_DMA +#define RT_SERIAL_RB_BUFSZ 64 +#define RT_USING_PIN + +/* Using USB */ + + +/* C/C++ and POSIX layer */ + +#define RT_LIBC_DEFAULT_TIMEZONE 8 + +/* POSIX (Portable Operating System Interface) layer */ + + +/* Interprocess Communication (IPC) */ + + +/* Socket is in the 'Network' category */ + + +/* Network */ + + +/* Utilities */ + + +/* RT-Thread Utestcases */ + + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + + +/* Wi-Fi */ + +/* Marvell WiFi */ + + +/* Wiced WiFi */ + + +/* IoT Cloud */ + + +/* security packages */ + + +/* language packages */ + +/* JSON: JavaScript Object Notation, a lightweight data-interchange format */ + + +/* XML: Extensible Markup Language */ + + +/* multimedia packages */ + +/* LVGL: powerful and easy-to-use embedded GUI library */ + + +/* u8g2: a monochrome graphic library */ + + +/* PainterEngine: A cross-platform graphics application framework written in C language */ + + +/* tools packages */ + + +/* system packages */ + +/* enhanced kernel services */ + + +/* acceleration: Assembly language or algorithmic acceleration packages */ + + +/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */ + + +/* Micrium: Micrium software products porting for RT-Thread */ + + +/* peripheral libraries and drivers */ + + +/* Kendryte SDK */ + + +/* AI packages */ + + +/* miscellaneous packages */ + +/* project laboratory */ + +/* samples: kernel and components samples */ + + +/* entertainment: terminal games and other interesting software packages */ + + +/* Privated Packages of RealThread */ + + +/* Network Utilities */ + + +/* RT-Thread Smart */ + +#define SOC_LPC55S6X_SERIES + +/* Hardware Drivers Config */ + +#define SOC_LPC55S6X + +/* On-chip Peripheral Drivers */ + +#define BSP_USING_PIN +#define BSP_USING_UART +#define BSP_USING_UART0 +#define HW_UART0_BAUDRATE_115200 + +/* Onboard Peripheral Drivers */ + +#define BSP_USING_LED +#define BSP_USING_KEY + +/* Board extended module Drivers */ + + +#endif diff --git a/bsp/lpc55sxx/lpc55s16_nxp_evk/rtconfig.py b/bsp/lpc55sxx/lpc55s16_nxp_evk/rtconfig.py new file mode 100644 index 0000000000..61ba4da031 --- /dev/null +++ b/bsp/lpc55sxx/lpc55s16_nxp_evk/rtconfig.py @@ -0,0 +1,162 @@ +import os +import sys + +# toolchains options +ARCH='arm' +CPU='cortex-m33' +CROSS_TOOL='gcc' +BOARD_NAME = 'lpcxpresso' +BSP_LIBRARY_TYPE = 'LPC55S16' + +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') + +# cross_tool provides the cross compiler +# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR +if CROSS_TOOL == 'gcc': + PLATFORM = 'gcc' + EXEC_PATH = r'C:\Users\XXYYZZ' +elif CROSS_TOOL == 'keil': + PLATFORM = 'armcc' + EXEC_PATH = r'C:/Keil_v5' +elif CROSS_TOOL == 'iar': + PLATFORM = 'iccarm' + EXEC_PATH = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.3' + +if os.getenv('RTT_EXEC_PATH'): + EXEC_PATH = os.getenv('RTT_EXEC_PATH') + +BUILD = 'debug' +#BUILD = 'release' + +if PLATFORM == 'gcc': + PREFIX = 'arm-none-eabi-' + CC = PREFIX + 'gcc' + CXX = PREFIX + 'g++' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + LINK = PREFIX + 'gcc' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + STRIP = PREFIX + 'strip' + + DEVICE = ' -mcpu=' + CPU + ' -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections' + CFLAGS = DEVICE + ' -Wall -D__FPU_PRESENT -eentry' + AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb -D__START=entry' + LFLAGS = DEVICE + ' -lm -lgcc -lc' + ' -nostartfiles -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T board/linker_scripts/LPC55S16_flash.ld' + + CPATH = '' + LPATH = '' + + if BUILD == 'debug': + CFLAGS += ' -gdwarf-2' + AFLAGS += ' -gdwarf-2' + CFLAGS += ' -O0' + else: + CFLAGS += ' -O2 -Os' + + POST_ACTION = OBJCPY + ' -O binary --remove-section=.boot_data --remove-section=.image_vertor_table --remove-section=.ncache $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' + + # module setting + CXXFLAGS = ' -Woverloaded-virtual -fno-exceptions -fno-rtti ' + M_CFLAGS = CFLAGS + ' -mlong-calls -fPIC ' + M_CXXFLAGS = CXXFLAGS + ' -mlong-calls -fPIC' + M_LFLAGS = DEVICE + CXXFLAGS + ' -Wl,--gc-sections,-z,max-page-size=0x4' +\ + ' -shared -fPIC -nostartfiles -static-libgcc' + M_POST_ACTION = STRIP + ' -R .hash $TARGET\n' + SIZE + ' $TARGET \n' + +elif PLATFORM == 'armcc': + # toolchains + CC = 'armcc' + CXX = 'armcc' + AS = 'armasm' + AR = 'armar' + LINK = 'armlink' + TARGET_EXT = 'axf' + + DEVICE = ' --cpu ' + CPU + '.fp.sp' + CFLAGS = DEVICE + ' --apcs=interwork' + AFLAGS = DEVICE + LFLAGS = DEVICE + ' --libpath "' + EXEC_PATH + '/ARM/ARMCC/lib" --info sizes --info totals --info unused --info veneers --list rtthread.map --scatter "./LPC55S16_flash.scf" ' + + LFLAGS += ' --keep *.o(.rti_fn.*) --keep *.o(FSymTab) --keep *.o(VSymTab)' + + CFLAGS += ' --diag_suppress=66,1296,186,6134' + CFLAGS += ' -I' + EXEC_PATH + '/ARM/RV31/INC' + LFLAGS += ' --libpath ' + EXEC_PATH + '/ARM/RV31/LIB' + + EXEC_PATH += '/arm/bin40/' + + if BUILD == 'debug': + CFLAGS += ' -g -O0' + AFLAGS += ' -g' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + CFLAGS += ' --c99' + + POST_ACTION = 'fromelf -z $TARGET' + # POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' + +elif PLATFORM == 'iccarm': + CC = 'iccarm' + CXX = 'iccarm' + AS = 'iasmarm' + AR = 'iarchive' + LINK = 'ilinkarm' + TARGET_EXT = 'out' + + DEVICE = ' -D__FPU_PRESENT' + + CFLAGS = DEVICE + CFLAGS += ' --diag_suppress Pa050' + CFLAGS += ' --no_cse' + CFLAGS += ' --no_unroll' + CFLAGS += ' --no_inline' + CFLAGS += ' --no_code_motion' + CFLAGS += ' --no_tbaa' + CFLAGS += ' --no_clustering' + CFLAGS += ' --no_scheduling' + CFLAGS += ' --debug' + CFLAGS += ' --endian=little' + CFLAGS += ' --cpu=' + CPU + CFLAGS += ' -e' + CFLAGS += ' --fpu=None' + CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' + CFLAGS += ' -Ol' + CFLAGS += ' --use_c++_inline' + + AFLAGS = '' + AFLAGS += ' -s+' + AFLAGS += ' -w+' + AFLAGS += ' -r' + AFLAGS += ' --cpu ' + CPU + AFLAGS += ' --fpu None' + + if BUILD == 'debug': + CFLAGS += ' --debug' + CFLAGS += ' -On' + else: + CFLAGS += ' -Oh' + + LFLAGS = ' --config "board/linker_scripts/LPC55S16_flash.icf"' + LFLAGS += ' --redirect _Printf=_PrintfTiny' + LFLAGS += ' --redirect _Scanf=_ScanfSmall' + LFLAGS += ' --entry __iar_program_start' + + CXXFLAGS = CFLAGS + + EXEC_PATH = EXEC_PATH + '/arm/bin/' + POST_ACTION = 'ielftool --bin $TARGET rtthread.bin' + +def dist_handle(BSP_ROOT, dist_dir): + cwd_path = os.getcwd() + sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) + from sdk_dist import dist_do_building + dist_do_building(BSP_ROOT, dist_dir) + diff --git a/bsp/lpc55sxx/lpc55s16_nxp_evk/template.uvoptx b/bsp/lpc55sxx/lpc55s16_nxp_evk/template.uvoptx new file mode 100644 index 0000000000..f6c6bc586c --- /dev/null +++ b/bsp/lpc55sxx/lpc55s16_nxp_evk/template.uvoptx @@ -0,0 +1,179 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + rtthread-lpc55s16 + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 0 + 0 + 1 + + 0 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 13 + + + + + + + + + + + BIN\UL2V8M.DLL + + + + 0 + UL2V8M + UL2V8M(-S0 -C0 -P0 -FD20000000 -FC1000 -FN2 -FF0LPC551XX_256 -FS00 -FL040000 -FF1LPC551XX_S_256 -FS110000000 -FL140000 -FP0($$Device:LPC55S16JBD100$arm\LPC551XX_256.FLM) -FP1($$Device:LPC55S16JBD100$arm\LPC551XX_S_256.FLM)) + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + 1 + 1 + 0 + 2 + 5000000 + + + + + diff --git a/bsp/lpc55sxx/lpc55s16_nxp_evk/template.uvprojx b/bsp/lpc55sxx/lpc55s16_nxp_evk/template.uvprojx new file mode 100644 index 0000000000..9a2fa12898 --- /dev/null +++ b/bsp/lpc55sxx/lpc55s16_nxp_evk/template.uvprojx @@ -0,0 +1,400 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + rtthread-lpc55s16 + 0x4 + ARM-ADS + 6160000::V6.16::ARMCLANG + 1 + + + LPC55S16JBD100 + NXP + NXP.LPC55S16_DFP.14.0.0 + https://mcuxpresso.nxp.com/cmsis_pack/repo/ + IRAM(0x10000000,0x03d800) IRAM2(0x20000000,0x010000) IROM(0x03000000,0x020000) IROM2(0x13000000,0x020000) XRAM(0x04000000,0x4000) XRAM2(0x14000000,0x4000) XRAM3(0x30000000,0x010000) XROM(0x00000000,0x03d800) CPUTYPE("Cortex-M33") FPU3(SFPU) DSP TZ CLOCK(12000000) ELITTLE + + + UL2V8M(-S0 -C0 -P0 -FD20000000 -FC1000 -FN2 -FF0LPC551XX_256 -FS00 -FL040000 -FF1LPC551XX_S_256 -FS110000000 -FL140000 -FP0($$Device:LPC55S16JBD100$arm\LPC551XX_256.FLM) -FP1($$Device:LPC55S16JBD100$arm\LPC551XX_S_256.FLM)) + 0 + $$Device:LPC55S16JBD100$fsl_device_registers.h + + + + + + + + + + $$Device:LPC55S16JBD100$LPC55S16.xml + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\ + rtthread + 1 + 0 + 0 + 1 + 1 + .\build\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + + + + SARMV8M.DLL + -MPU + TCM.DLL + -pCM33 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4102 + + 1 + BIN\UL2V8M.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M33" + + 0 + 0 + 0 + 1 + 1 + 1 + 0 + 2 + 0 + 0 + 1 + 1 + 16 + 0 + 0 + 0 + 0 + 4 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x10000000 + 0x3d800 + + + 1 + 0x3000000 + 0x20000 + + + 1 + 0x4000000 + 0x4000 + + + 1 + 0x0 + 0x3d800 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x3000000 + 0x20000 + + + 1 + 0x13000000 + 0x20000 + + + 0 + 0x4000000 + 0x4000 + + + 0 + 0x14000000 + 0x4000 + + + 0 + 0x30000000 + 0x10000 + + + 0 + 0x10000000 + 0x3d800 + + + 0 + 0x20000000 + 0x10000 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 3 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + + --target=arm-arm-none-eabi + CPU_LPC55S16JBD100, ARM_MATH_CM33, RT_USING_ARM_LIBC + + + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + + -x assembler-with-cpp + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x02000000 + + .\board\linker_scripts\LPC55S16_flash.scf + + + --keep *.o(.rti_fn.*) --keep *.o(FSymTab) --keep *.o(VSymTab) + + + + + + + + + + + + + + + + + + template + 1 + + + + + -- GitLab

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