From c58c5b51c565f394cf75596534801ba6c5a2799e Mon Sep 17 00:00:00 2001 From: William Wang Date: Tue, 3 May 2022 15:37:57 +0800 Subject: [PATCH] arch: update southlake cpuss peripheral address CPUSS Peripheral, 0x1f_0000_0000, 0x1f_0fff_ffff Detailed address map: device, address_begin, address_end CLINT, 0x1f_0000_0000, 0x1f_0000_ffff BEU, 0x1f_0001_0000, 0x1f_0001_ffff Debug Module, 0x1f_0002_0000, 0x1f_0002_0fff MMPMA, 0x1f_0003_0000, 0x1f_0003_0fff L3CacheCtrl, 0x1f_0004_0000, 0x1f_0004_1fff reserved PLIC, 0x1f_0c00_0000, 0x1f_0fff_ffff Address map in tests to be updated --- am/src/nemu/include/nemu.h | 8 +++----- am/src/nemu/isa/riscv/vme.c | 10 ++++++++-- am/src/xs/isa/riscv/clint.c | 2 +- 3 files changed, 12 insertions(+), 8 deletions(-) diff --git a/am/src/nemu/include/nemu.h b/am/src/nemu/include/nemu.h index d9fe82a5..92bd3854 100644 --- a/am/src/nemu/include/nemu.h +++ b/am/src/nemu/include/nemu.h @@ -25,8 +25,9 @@ # define SCREEN_ADDR 0x40001000 # define SYNC_ADDR 0x40001004 # define FB_ADDR 0x50000000 -#elif defined(__ARCH_RISCV64_SOUTHLAKE) || defined(__ARCH_RISCV64_SOUTHLAKE_FLASH) -# define RTC_ADDR 0x3800bff8 +#elif defined(__ARCH_RISCV64_XS_SOUTHLAKE) || defined(__ARCH_RISCV64_XS_SOUTHLAKE_FLASH) +# define RTC_ADDR 0x1f0000bff8 +// CLINT 0x1f00000000 #else # define SERIAL_PORT 0xa10003f8 # define KBD_ADDR 0xa1000060 @@ -43,9 +44,6 @@ # define AUDIO_SBUF_ADDR 0xa0800000 #endif -#define MMIO_BASE 0xa0000000 -#define MMIO_SIZE 0x10000000 - extern char _pmem_start, _pmem_end; #define NEMU_PADDR_SPACE \ diff --git a/am/src/nemu/isa/riscv/vme.c b/am/src/nemu/isa/riscv/vme.c index 59c4deed..bf9d4364 100644 --- a/am/src/nemu/isa/riscv/vme.c +++ b/am/src/nemu/isa/riscv/vme.c @@ -17,8 +17,14 @@ static const _Area segments[] = { // Kernel memory mappings RANGE_LEN(CLINT_MMIO, 0x10000), // clint/timer RANGE_LEN(FB_ADDR, 0x400000), // vmem RANGE_LEN(SCREEN_ADDR,0x1000), // vmem - RANGE_LEN(0x3c000000, 0x4000000), // PLIC - RANGE_LEN(0xc0000000, 0x100000), // page table test allocates from this position + RANGE_LEN(0x3c000000, 0x4000000), // PLIC + RANGE_LEN(0xc0000000, 0x100000), // page table test allocates from this position +#elif defined(__ARCH_RISCV64_XS_SOUTHLAKE) || defined(__ARCH_RISCV64_XS_SOUTHLAKE_FLASH) + RANGE_LEN(0x200000000, 0x8000000), // PMEM + RANGE_LEN(0x1f40600000, 0x1000), // uart + RANGE_LEN(CLINT_MMIO, 0x10000), // clint/timer + RANGE_LEN(0x1f0c000000, 0x4000000), // PLIC + RANGE_LEN(0x2040000000, 0x100000), // page table test allocates from this position #else NEMU_PADDR_SPACE, #if __riscv_xlen == 64 diff --git a/am/src/xs/isa/riscv/clint.c b/am/src/xs/isa/riscv/clint.c index f5864b37..f8e9814a 100644 --- a/am/src/xs/isa/riscv/clint.c +++ b/am/src/xs/isa/riscv/clint.c @@ -9,7 +9,7 @@ typedef struct { ClintInfo timer_handle; -#if defined(__ARCH_RISCV64_NOOP) || defined(__ARCH_RISCV64_XS) +#if defined(__ARCH_RISCV64_NOOP) || defined(__ARCH_RISCV64_XS) || defined(__ARCH_RISCV64_XS_SOUTHLAKE) || defined(__ARCH_RISCV64_XS_SOUTHLAKE_FLASH) #define CLINT_MMIO (RTC_ADDR - 0xbff8) #define TIME_INC 0x80000 #else -- GitLab