From 909b6aed767860eea3b18af7adfe2037776b868e Mon Sep 17 00:00:00 2001
From: Zihao Yu <yuzihao@ict.ac.cn>
Date: Mon, 9 Sep 2019 09:52:16 +0800
Subject: [PATCH] riscv32-noop,cte: use S-mode CSR to match NOOP

---
 am/src/riscv32/noop/cte.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/am/src/riscv32/noop/cte.c b/am/src/riscv32/noop/cte.c
index 1aecb2a5..500e0b61 100644
--- a/am/src/riscv32/noop/cte.c
+++ b/am/src/riscv32/noop/cte.c
@@ -20,7 +20,7 @@ _Context* __am_irq_handle(_Context *c) {
       case 2:
         if (__am_illegal_instr(c)) c->epc += 4;
         break;
-      case 11:
+      case 9:
         ev.event = (c->GPR1 == -1) ? _EVENT_YIELD : _EVENT_SYSCALL;
         c->epc += 4;
         break;
@@ -42,7 +42,7 @@ extern void __am_asm_trap(void);
 
 int _cte_init(_Context*(*handler)(_Event, _Context*)) {
   // initialize exception entry
-  asm volatile("csrw mtvec, %0" : : "r"(__am_asm_trap));
+  asm volatile("csrw stvec, %0" : : "r"(__am_asm_trap));
 
   // register event handler
   user_handler = handler;
-- 
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