1. 02 7月, 2022 1 次提交
  2. 30 6月, 2022 1 次提交
  3. 29 6月, 2022 2 次提交
  4. 28 6月, 2022 1 次提交
  5. 27 6月, 2022 3 次提交
    • Y
      dp2: add a pipeline for load/store (#1597) · fa9d712c
      Yinan Xu 提交于
      * dp2: add a pipeline for load/store
      Load/store Dispatch2 has a bad timing because it requires the fuType
      to disguish the out ports. This brings timing issues because the
      instruction has to read busyTable after the port arbitration.
      This commit adds a pipeline in dp2Ls, which may cause performance
      degradation. Instructions are dispatched according to out, and at
      the next cycle it will leave dp2.
      * bump difftest trying to fix vcs
    • W
      dcache: do not access plru when refill (#1591) · 92816bbc
      William Wang 提交于
      * dcache: do not access plru when refill
      Now we have accessed plru when load miss, we should not access plru
      when refill
      * dcache: not not access plru when miss queue full
      It will help avoid invalid plru access when miss queue full
    • Z
  6. 26 6月, 2022 1 次提交
    • L
      l2tlb: add counter to ptw-filter to avoid l2tlb deadlock & sync sfence to mmu (#1599) · fa9f9690
      Lemover 提交于
      fix some bugs.
      1. fix l2tlb dead-lock bug
      l2tlb won't merge requests at same addr. It will be blocked when having too many requests.
      PtwFilter has a bug that will send too many requests. Add a counter to avoid that.
      2. fix sfence sync at mmu
      different modules in mmu may get sfence at different latency, which will lost requests or some requests have no receiver.
      Sync the sfence latency manually to avoid the bug.
      * mmu.filter: add counter not to send to many req to l2tlb
      * mmu.filter: fix bug that forget counter signal when block issue and deq
      * mmu: set sfence/csr delay to 2 cycle, must sync in mmu
  7. 25 6月, 2022 4 次提交
    • L
      l2tlb: delay one cycle when read from sram (#1596) · 6c4dcc2d
      Lemover 提交于
      now the l2tlb page cache are divided into:
      1. stageReq: input && read sram valid && will block when sram write
      2. stageDelay: get sram data and delay one cycle
      3. stageCheck: check hit and ecc result
      4. stageResp: output
    • L
      tlb: divide v-select into two cycle for timing optimization (#1598) · 445d5c05
      Lemover 提交于
      dtlb has 128 entries stored in sram. 128 sets, 1 ways.
      advantage: large volume & 1 ways means no tag match logic at data select path
      disadvantage: 128 sets means long latency at valid select, which is a Vec-Register.
      Optimization: divide valid select into two-cycles
    • Y
      freelist: optimize timing of read and writing (#1593) · 5ef86c38
      Yinan Xu 提交于
      This commit optimizes the timing of freelist by changing the updating
      function of headPtr and tailPtr.
      We maintains an one-hot representation of headPtr and further uses it to
      read the free registers from the list, which should be better than the
      previous implementation where headPtr is used to indexed into the queue.
      The update of tailPtr and the freelist is delayed by one cycle to
      optimize the timing. Because freelist allocates new registers in the
      next cycle iff there are more than RenameWidth free registers in this
      cycle. The freed registers in this cycle will never be used in the next
      cycle. Thus, we can delay the updating of queue data to the next cycle.
      We also move the update of tailPtr to the next cycle, since PopCount
      takes a long timing and we move the last adder to the next cycle. Now
      the adder works parallely with PopCount. That is, the updating of
      tailPtr is pipelined.
    • J
      Merge pull request #1587 from OpenXiangShan/chisel-db · b54c2fd9
      Jiawei Lin 提交于
      Added chisel-db to dump hw data into a database automatically
  8. 24 6月, 2022 1 次提交
  9. 22 6月, 2022 1 次提交
    • Y
      core: add buffers for function units across int/fp (#1590) · 5010f3fb
      Yinan Xu 提交于
      This commit adds a buffer after the function unit that operate across
      the integer block and the floating-point block, such as f2i and i2f.
      For example, previously the out.ready of f2i depends on whether
      mul/div/csr/jump has a valid instruction out, since f2i has lower
      priority than them. This ready back-propagates from the integer function
      units to the floating-point function units, and finally to the
      floating-point reservation stations (since f2i is fully pipelined).
      We add a buffer after the function unit to break this ready
      back-propagation. It incurs one more cycle of execution latency, but we
      leave it not-fully-optimized for now.
      Timing can be further optimized if we separates the int writeback and fp
      writeback in function units. In the current version, the ready of f2i
      affects the ready of f2f pipelines, which is unnecessary. This is the
      future work.
  10. 21 6月, 2022 1 次提交
  11. 20 6月, 2022 2 次提交
  12. 18 6月, 2022 2 次提交
    • Y
      decode: do not set lsrc of LUI for better timing (#1586) · a19215dd
      Yinan Xu 提交于
      This commit changes the lsrc/psrc of LUI in dispatch instead of
      decode to optimize the timing of lsrc in DecodeStage, which is
      critical for rename table.
      lsrc/ldest should be directly get from instr for the timing. Fused
      instructions change lsrc/ldest now, which will be optimized later.
    • W
      perfcnt: keep strict regularity of perf counter name (#1585) · d18dc7e6
      wakafa 提交于
      * buspmu: avoid inner space in perf-cnt name
      * perfcnt: judge regularity of perfname
      * perfcnt: fix some irregular perfname
      * bump huancun
  13. 17 6月, 2022 1 次提交
  14. 11 6月, 2022 1 次提交
  15. 09 6月, 2022 5 次提交
  16. 08 6月, 2022 2 次提交
  17. 06 6月, 2022 4 次提交
  18. 02 6月, 2022 1 次提交
    • L
      ittage: we should write new target when alloc · 3b7c55f8
      Lingrui98 提交于
      Previous logic checked the value of old_ctr to select between old target and
      new target when updating ittage table. However, when we need to alloc a new
      entry, the value of old_ctr is X because we do not reset ittage table. So we
      would definitely write an X to the target field, which is the output of the
      mux, as the selector is X.
  19. 31 5月, 2022 2 次提交
  20. 29 5月, 2022 1 次提交
  21. 27 5月, 2022 1 次提交
    • Y
      soc: fix implementation of rtc_clock (#1565) · 88ca983f
      Yinan Xu 提交于
      Previously we made a mistake to connect rtc_clock to rtcTick for CLINT.
      rtcTick should be on io_clock clock domain and asserted only one
      clock cycle in io_clock for every cycle in rtc_clock. We add sampling
      registers in this commit to fix this.
  22. 26 5月, 2022 1 次提交
  23. 25 5月, 2022 1 次提交