diff --git a/src/main/scala/xiangshan/backend/roq/Roq.scala b/src/main/scala/xiangshan/backend/roq/Roq.scala
index 2219ffc5466a5082bb81acfbd61364175100670f..06f1fa5c3c7a1a4ae4a72a0833d9224d6838dedc 100644
--- a/src/main/scala/xiangshan/backend/roq/Roq.scala
+++ b/src/main/scala/xiangshan/backend/roq/Roq.scala
@@ -367,7 +367,8 @@ class Roq(numWbPorts: Int) extends XSModule with HasCircularQueuePtrHelper {
   val commit_block = VecInit((0 until CommitWidth).map(i => !commit_w(i) || commit_exception(i) || writebackData.io.rdata(i).flushPipe))
   for (i <- 0 until CommitWidth) {
     // defaults: state === s_idle and instructions commit
-    val isBlocked = if (i != 0) Cat(commit_block.take(i)).orR || intrEnable else false.B
+    // when intrBitSetReg, allow only one instruction to commit at each clock cycle
+    val isBlocked = if (i != 0) Cat(commit_block.take(i)).orR || intrBitSetReg else false.B
     io.commits.valid(i) := commit_v(i) && commit_w(i) && !isBlocked && !commit_exception(i)
     io.commits.info(i)  := dispatchData.io.rdata(i)