diff --git a/src/main/scala/xiangshan/frontend/Bim.scala b/src/main/scala/xiangshan/frontend/Bim.scala index d449f146b0daa98d153dbfb9b603352abbcb763f..f9a1461028c2eec6153c9df1bef827e6c80cfffe 100644 --- a/src/main/scala/xiangshan/frontend/Bim.scala +++ b/src/main/scala/xiangshan/frontend/Bim.scala @@ -35,8 +35,8 @@ class BIM extends BasePredictor with BimParams { val bimAddr = new TableAddr(log2Up(BimSize), BimBanks) - val bankAlignedPC = bankAligned(io.pc.bits) - val pcLatch = RegEnable(bankAlignedPC, io.pc.valid) + val if1_bankAlignedPC = bankAligned(io.pc.bits) + val if2_pc = RegEnable(if1_bankAlignedPC, io.pc.valid) val bim = List.fill(BimBanks) { Module(new SRAMTemplate(UInt(2.W), set = nRows, shouldReset = false, holdRead = true)) @@ -48,34 +48,34 @@ class BIM extends BasePredictor with BimParams { when (resetRow === (nRows-1).U) { doing_reset := false.B } // this bank means cache bank - val startsAtOddBank = bankInGroup(bankAlignedPC)(0) + val if1_startsAtOddBank = bankInGroup(if1_bankAlignedPC)(0) - val realMask = Mux(startsAtOddBank, + val if1_realMask = Mux(if1_startsAtOddBank, Cat(io.inMask(bankWidth-1,0), io.inMask(PredictWidth-1, bankWidth)), io.inMask) - val isInNextRow = VecInit((0 until BimBanks).map(i => Mux(startsAtOddBank, (i < bankWidth).B, false.B))) + val if1_isInNextRow = VecInit((0 until BimBanks).map(i => Mux(if1_startsAtOddBank, (i < bankWidth).B, false.B))) - val baseRow = bimAddr.getBankIdx(bankAlignedPC) + val if1_baseRow = bimAddr.getBankIdx(if1_bankAlignedPC) - val realRow = VecInit((0 until BimBanks).map(b => Mux(isInNextRow(b), (baseRow+1.U)(log2Up(nRows)-1, 0), baseRow))) + val if1_realRow = VecInit((0 until BimBanks).map(b => Mux(if1_isInNextRow(b), (if1_baseRow+1.U)(log2Up(nRows)-1, 0), if1_baseRow))) - val realRowLatch = VecInit(realRow.map(RegEnable(_, enable=io.pc.valid))) + val if2_realRow = VecInit(if1_realRow.map(RegEnable(_, enable=io.pc.valid))) for (b <- 0 until BimBanks) { - bim(b).io.r.req.valid := realMask(b) && io.pc.valid - bim(b).io.r.req.bits.setIdx := realRow(b) + bim(b).io.r.req.valid := if1_realMask(b) && io.pc.valid + bim(b).io.r.req.bits.setIdx := if1_realRow(b) } - val bimRead = VecInit(bim.map(_.io.r.resp.data(0))) + val if2_bimRead = VecInit(bim.map(_.io.r.resp.data(0))) - val startsAtOddBankLatch = bankInGroup(pcLatch)(0) + val if2_startsAtOddBank = bankInGroup(if2_pc)(0) for (b <- 0 until BimBanks) { - val realBank = (if (b < bankWidth) Mux(startsAtOddBankLatch, (b+bankWidth).U, b.U) - else Mux(startsAtOddBankLatch, (b-bankWidth).U, b.U)) - val ctr = bimRead(realBank) + val realBank = (if (b < bankWidth) Mux(if2_startsAtOddBank, (b+bankWidth).U, b.U) + else Mux(if2_startsAtOddBank, (b-bankWidth).U, b.U)) + val ctr = if2_bimRead(realBank) io.resp.ctrs(b) := ctr io.meta.ctrs(b) := ctr } diff --git a/src/main/scala/xiangshan/frontend/Btb.scala b/src/main/scala/xiangshan/frontend/Btb.scala index 2eb400ec4bb991f30784e8bb63ea7ef8e7fc4e0c..1ae94b05f53ba5ed12c86c844179c3441a1a92ea 100644 --- a/src/main/scala/xiangshan/frontend/Btb.scala +++ b/src/main/scala/xiangshan/frontend/Btb.scala @@ -72,9 +72,9 @@ class BTB extends BasePredictor with BTBParams{ override val io = IO(new BTBIO) val btbAddr = new TableAddr(log2Up(BtbSize/BtbWays), BtbBanks) - val bankAlignedPC = bankAligned(io.pc.bits) + val if1_bankAlignedPC = bankAligned(io.pc.bits) - val pcLatch = RegEnable(bankAlignedPC, io.pc.valid) + val if2_pc = RegEnable(if1_bankAlignedPC, io.pc.valid) val data = List.fill(BtbWays) { List.fill(BtbBanks) { @@ -91,61 +91,61 @@ class BTB extends BasePredictor with BTBParams{ // BTB read requests // this bank means cache bank - val startsAtOddBank = bankInGroup(bankAlignedPC)(0) + val if1_startsAtOddBank = bankInGroup(if1_bankAlignedPC)(0) - val baseBank = btbAddr.getBank(bankAlignedPC) + val if1_baseBank = btbAddr.getBank(if1_bankAlignedPC) - val realMask = Mux(startsAtOddBank, + val if1_realMask = Mux(if1_startsAtOddBank, Cat(io.inMask(bankWidth-1,0), io.inMask(PredictWidth-1, bankWidth)), io.inMask) - val realMaskLatch = RegEnable(realMask, io.pc.valid) + val if2_realMask = RegEnable(if1_realMask, io.pc.valid) - val isInNextRow = VecInit((0 until BtbBanks).map(i => Mux(startsAtOddBank, (i < bankWidth).B, false.B))) + val if1_isInNextRow = VecInit((0 until BtbBanks).map(i => Mux(if1_startsAtOddBank, (i < bankWidth).B, false.B))) - val baseRow = btbAddr.getBankIdx(bankAlignedPC) + val if1_baseRow = btbAddr.getBankIdx(if1_bankAlignedPC) - val nextRowStartsUp = baseRow.andR + val if1_nextRowStartsUp = if1_baseRow.andR - val realRow = VecInit((0 until BtbBanks).map(b => Mux(isInNextRow(b), (baseRow+1.U)(log2Up(nRows)-1, 0), baseRow))) + val if1_realRow = VecInit((0 until BtbBanks).map(b => Mux(if1_isInNextRow(b), (if1_baseRow+1.U)(log2Up(nRows)-1, 0), if1_baseRow))) - val realRowLatch = VecInit(realRow.map(RegEnable(_, enable=io.pc.valid))) + val if2_realRow = VecInit(if1_realRow.map(RegEnable(_, enable=io.pc.valid))) for (w <- 0 until BtbWays) { for (b <- 0 until BtbBanks) { - meta(w)(b).io.r.req.valid := realMask(b) && io.pc.valid - meta(w)(b).io.r.req.bits.setIdx := realRow(b) - data(w)(b).io.r.req.valid := realMask(b) && io.pc.valid - data(w)(b).io.r.req.bits.setIdx := realRow(b) + meta(w)(b).io.r.req.valid := if1_realMask(b) && io.pc.valid + meta(w)(b).io.r.req.bits.setIdx := if1_realRow(b) + data(w)(b).io.r.req.valid := if1_realMask(b) && io.pc.valid + data(w)(b).io.r.req.bits.setIdx := if1_realRow(b) } } for (b <- 0 to 1) { edata(b).io.r.req.valid := io.pc.valid - val row = if (b == 0) { Mux(startsAtOddBank, realRow(bankWidth), realRow(0)) } - else { Mux(startsAtOddBank, realRow(0), realRow(bankWidth))} + val row = if (b == 0) { Mux(if1_startsAtOddBank, if1_realRow(bankWidth), if1_realRow(0)) } + else { Mux(if1_startsAtOddBank, if1_realRow(0), if1_realRow(bankWidth))} edata(b).io.r.req.bits.setIdx := row } // Entries read from SRAM - val metaRead = VecInit((0 until BtbWays).map(w => VecInit((0 until BtbBanks).map( b => meta(w)(b).io.r.resp.data(0))))) - val dataRead = VecInit((0 until BtbWays).map(w => VecInit((0 until BtbBanks).map( b => data(w)(b).io.r.resp.data(0))))) - val edataRead = VecInit((0 to 1).map(i => edata(i).io.r.resp.data(0))) + val if2_metaRead = VecInit((0 until BtbWays).map(w => VecInit((0 until BtbBanks).map( b => meta(w)(b).io.r.resp.data(0))))) + val if2_dataRead = VecInit((0 until BtbWays).map(w => VecInit((0 until BtbBanks).map( b => data(w)(b).io.r.resp.data(0))))) + val if2_edataRead = VecInit((0 to 1).map(i => edata(i).io.r.resp.data(0))) - val baseBankLatch = btbAddr.getBank(pcLatch) - val startsAtOddBankLatch = bankInGroup(pcLatch)(0) - val baseTag = btbAddr.getTag(pcLatch) + val if2_baseBank = btbAddr.getBank(if2_pc) + val if2_startsAtOddBank = bankInGroup(if2_pc)(0) + val if2_baseTag = btbAddr.getTag(if2_pc) - val tagIncremented = VecInit((0 until BtbBanks).map(b => RegEnable(isInNextRow(b.U) && nextRowStartsUp, io.pc.valid))) - val realTags = VecInit((0 until BtbBanks).map(b => Mux(tagIncremented(b), baseTag + 1.U, baseTag))) + val if2_tagIncremented = VecInit((0 until BtbBanks).map(b => RegEnable(if1_isInNextRow(b.U) && if1_nextRowStartsUp, io.pc.valid))) + val if2_realTags = VecInit((0 until BtbBanks).map(b => Mux(if2_tagIncremented(b), if2_baseTag + 1.U, if2_baseTag))) - val totalHits = VecInit((0 until BtbBanks).map( b => + val if2_totalHits = VecInit((0 until BtbBanks).map( b => VecInit((0 until BtbWays).map( w => // This should correspond to the real mask from last valid cycle! - metaRead(w)(b).tag === realTags(b) && metaRead(w)(b).valid && realMaskLatch(b) + if2_metaRead(w)(b).tag === if2_realTags(b) && if2_metaRead(w)(b).valid && if2_realMask(b) )) )) - val bankHits = VecInit(totalHits.map(_.reduce(_||_))) - val bankHitWays = VecInit(totalHits.map(PriorityEncoder(_))) + val if2_bankHits = VecInit(if2_totalHits.map(_.reduce(_||_))) + val if2_bankHitWays = VecInit(if2_totalHits.map(PriorityEncoder(_))) def allocWay(valids: UInt, meta_tags: UInt, req_tag: UInt) = { @@ -167,30 +167,30 @@ class BTB extends BasePredictor with BTBParams{ } } val allocWays = VecInit((0 until BtbBanks).map(b => - allocWay(VecInit(metaRead.map(w => w(b).valid)).asUInt, - VecInit(metaRead.map(w => w(b).tag)).asUInt, - realTags(b)))) + allocWay(VecInit(if2_metaRead.map(w => w(b).valid)).asUInt, + VecInit(if2_metaRead.map(w => w(b).tag)).asUInt, + if2_realTags(b)))) val writeWay = VecInit((0 until BtbBanks).map( - b => Mux(bankHits(b), bankHitWays(b), allocWays(b)) + b => Mux(if2_bankHits(b), if2_bankHitWays(b), allocWays(b)) )) for (b <- 0 until BtbBanks) { - val realBank = (if (b < bankWidth) Mux(startsAtOddBankLatch, (b+bankWidth).U, b.U) - else Mux(startsAtOddBankLatch, (b-bankWidth).U, b.U)) - val meta_entry = metaRead(bankHitWays(realBank))(realBank) - val data_entry = dataRead(bankHitWays(realBank))(realBank) - val edataBank = (if (b < bankWidth) Mux(startsAtOddBankLatch, 1.U, 0.U) - else Mux(startsAtOddBankLatch, 0.U, 1.U)) + val realBank = (if (b < bankWidth) Mux(if2_startsAtOddBank, (b+bankWidth).U, b.U) + else Mux(if2_startsAtOddBank, (b-bankWidth).U, b.U)) + val meta_entry = if2_metaRead(if2_bankHitWays(realBank))(realBank) + val data_entry = if2_dataRead(if2_bankHitWays(realBank))(realBank) + val edataBank = (if (b < bankWidth) Mux(if2_startsAtOddBank, 1.U, 0.U) + else Mux(if2_startsAtOddBank, 0.U, 1.U)) // Use real pc to calculate the target - io.resp.targets(b) := Mux(data_entry.extended, edataRead(edataBank), (pcLatch.asSInt + (b << 1).S + data_entry.offset).asUInt) - io.resp.hits(b) := bankHits(realBank) + io.resp.targets(b) := Mux(data_entry.extended, if2_edataRead(edataBank), (if2_pc.asSInt + (b << 1).S + data_entry.offset).asUInt) + io.resp.hits(b) := if2_bankHits(realBank) io.resp.types(b) := meta_entry.btbType io.resp.isRVC(b) := meta_entry.isRVC io.meta.writeWay(b) := writeWay(realBank) - io.meta.hitJal(b) := bankHits(realBank) && meta_entry.btbType === BTBtype.J + io.meta.hitJal(b) := if2_bankHits(realBank) && meta_entry.btbType === BTBtype.J } def pdInfoToBTBtype(pd: PreDecodeInfo) = { @@ -244,35 +244,35 @@ class BTB extends BasePredictor with BTBParams{ XSDebug("isInNextRow: ") (0 until BtbBanks).foreach(i => { - XSDebug(false, true.B, "%d ", isInNextRow(i)) + XSDebug(false, true.B, "%d ", if1_isInNextRow(i)) if (i == BtbBanks-1) { XSDebug(false, true.B, "\n") } }) val validLatch = RegNext(io.pc.valid) - XSDebug(io.pc.valid, "read: pc=0x%x, baseBank=%d, realMask=%b\n", bankAlignedPC, baseBank, realMask) + XSDebug(io.pc.valid, "read: pc=0x%x, baseBank=%d, realMask=%b\n", if1_bankAlignedPC, if1_baseBank, if1_realMask) XSDebug(validLatch, "read_resp: pc=0x%x, readIdx=%d-------------------------------\n", - pcLatch, btbAddr.getIdx(pcLatch)) + if2_pc, btbAddr.getIdx(if2_pc)) if (debug_verbose) { for (i <- 0 until BtbBanks){ for (j <- 0 until BtbWays) { XSDebug(validLatch, "read_resp[w=%d][b=%d][r=%d] is valid(%d) mask(%d), tag=0x%x, offset=0x%x, type=%d, isExtend=%d, isRVC=%d\n", - j.U, i.U, realRowLatch(i), metaRead(j)(i).valid, realMaskLatch(i), metaRead(j)(i).tag, dataRead(j)(i).offset, metaRead(j)(i).btbType, dataRead(j)(i).extended, metaRead(j)(i).isRVC) + j.U, i.U, if2_realRow(i), if2_metaRead(j)(i).valid, if2_realMask(i), if2_metaRead(j)(i).tag, if2_dataRead(j)(i).offset, if2_metaRead(j)(i).btbType, if2_dataRead(j)(i).extended, if2_metaRead(j)(i).isRVC) } } } // e.g: baseBank == 5 => (5, 6,..., 15, 0, 1, 2, 3, 4) - val bankIdxInOrder = VecInit((0 until BtbBanks).map(b => (baseBankLatch +& b.U)(log2Up(BtbBanks)-1,0))) + val bankIdxInOrder = VecInit((0 until BtbBanks).map(b => (if2_baseBank +& b.U)(log2Up(BtbBanks)-1,0))) for (i <- 0 until BtbBanks) { val idx = bankIdxInOrder(i) - XSDebug(validLatch && bankHits(bankIdxInOrder(i)), "resp(%d): bank(%d) hits, tgt=%x, isRVC=%d, type=%d\n", + XSDebug(validLatch && if2_bankHits(bankIdxInOrder(i)), "resp(%d): bank(%d) hits, tgt=%x, isRVC=%d, type=%d\n", i.U, idx, io.resp.targets(i), io.resp.isRVC(i), io.resp.types(i)) } XSDebug(updateValid, "update_req: cycle=%d, pc=0x%x, target=0x%x, misPred=%d, offset=%x, extended=%d, way=%d, bank=%d, row=0x%x\n", u.brInfo.debug_btb_cycle, u.pc, new_target, u.isMisPred, new_offset, new_extended, updateWay, updateBankIdx, updateRow) for (i <- 0 until BtbBanks) { // Conflict when not hit and allocating a valid entry - val conflict = metaRead(allocWays(i))(i).valid && !bankHits(i) + val conflict = if2_metaRead(allocWays(i))(i).valid && !if2_bankHits(i) XSDebug(conflict, "bank(%d) is trying to allocate a valid way(%d)\n", i.U, allocWays(i)) // There is another circumstance when a branch is on its way to update while another // branch chose the same way to udpate, then after the first branch is wrote in, diff --git a/src/main/scala/xiangshan/frontend/Tage.scala b/src/main/scala/xiangshan/frontend/Tage.scala index 1a4f21f38c6a231d7ab087f7bb60e8664d98e32d..934c7b35a0b3aae74076bcf2a6195ce59c65e68a 100644 --- a/src/main/scala/xiangshan/frontend/Tage.scala +++ b/src/main/scala/xiangshan/frontend/Tage.scala @@ -121,26 +121,26 @@ class TageTable(val nRows: Int, val histLen: Int, val tagLen: Int, val uBitPerio val tageEntrySz = 1 + tagLen + TageCtrBits - val bankAlignedPC = bankAligned(io.req.bits.pc) + val if2_bankAlignedPC = bankAligned(io.req.bits.pc) // this bank means cache bank - val startsAtOddBank = bankInGroup(bankAlignedPC)(0) + val if2_startsAtOddBank = bankInGroup(if2_bankAlignedPC)(0) // use real address to index // val unhashed_idxes = VecInit((0 until TageBanks).map(b => ((io.req.bits.pc >> 1.U) + b.U) >> log2Up(TageBanks).U)) - val unhashed_idx = Wire(Vec(2, UInt((log2Ceil(nRows)+tagLen).W))) + val if2_unhashed_idx = Wire(Vec(2, UInt((log2Ceil(nRows)+tagLen).W))) // the first bank idx always correspond with pc - unhashed_idx(0) := io.req.bits.pc >> (1+log2Ceil(TageBanks)) + if2_unhashed_idx(0) := io.req.bits.pc >> (1+log2Ceil(TageBanks)) // when pc is at odd bank, the second bank is at the next idx - unhashed_idx(1) := unhashed_idx(0) + startsAtOddBank + if2_unhashed_idx(1) := if2_unhashed_idx(0) + if2_startsAtOddBank - // val idxes_and_tags = (0 until TageBanks).map(b => compute_tag_and_hash(unhashed_idxes(b.U), io.req.bits.hist)) - // val (idx, tag) = compute_tag_and_hash(unhashed_idx, io.req.bits.hist) - val idxes_and_tags = unhashed_idx.map(compute_tag_and_hash(_, io.req.bits.hist)) - // val idxes = VecInit(idxes_and_tags.map(_._1)) - // val tags = VecInit(idxes_and_tags.map(_._2)) + // val idxes_and_tags = (0 until TageBanks).map(b => compute_tag_and_hash(if2_unhashed_idxes(b.U), io.req.bits.hist)) + // val (idx, tag) = compute_tag_and_hash(if2_unhashed_idx, io.req.bits.hist) + val if2_idxes_and_tags = if2_unhashed_idx.map(compute_tag_and_hash(_, io.req.bits.hist)) + // val idxes = VecInit(if2_idxes_and_tags.map(_._1)) + // val tags = VecInit(if2_idxes_and_tags.map(_._2)) - val idxes_latch = RegEnable(VecInit(idxes_and_tags.map(_._1)), io.req.valid) - val tags_latch = RegEnable(VecInit(idxes_and_tags.map(_._2)), io.req.valid) - // and_tags_latch = RegEnable(idxes_and_tags, enable=io.req.valid) + val if3_idxes = RegEnable(VecInit(if2_idxes_and_tags.map(_._1)), io.req.valid) + val if3_tags = RegEnable(VecInit(if2_idxes_and_tags.map(_._2)), io.req.valid) + // and_if3_tags = RegEnable(if2_idxes_and_tags, enable=io.req.valid) // val idxLatch = RegEnable(idx, enable=io.req.valid) // val tagLatch = RegEnable(tag, enable=io.req.valid) @@ -175,59 +175,59 @@ class TageTable(val nRows: Int, val histLen: Int, val tagLen: Int, val uBitPerio val lo_us = List.fill(TageBanks)(Module(new HL_Bank(nRows))) val table = List.fill(TageBanks)(Module(new SRAMTemplate(new TageEntry, set=nRows, shouldReset=false, holdRead=true, singlePort=false))) - val hi_us_r = WireInit(0.U.asTypeOf(Vec(TageBanks, Bool()))) - val lo_us_r = WireInit(0.U.asTypeOf(Vec(TageBanks, Bool()))) - val table_r = WireInit(0.U.asTypeOf(Vec(TageBanks, new TageEntry))) + val if3_hi_us_r = WireInit(0.U.asTypeOf(Vec(TageBanks, Bool()))) + val if3_lo_us_r = WireInit(0.U.asTypeOf(Vec(TageBanks, Bool()))) + val if3_table_r = WireInit(0.U.asTypeOf(Vec(TageBanks, new TageEntry))) - val baseBank = io.req.bits.pc(log2Up(TageBanks), 1) - val baseBankLatch = RegEnable(baseBank, enable=io.req.valid) + val if2_baseBank = io.req.bits.pc(log2Up(TageBanks), 1) + val if3_baseBank = RegEnable(if2_baseBank, enable=io.req.valid) - val bankIdxInOrder = VecInit((0 until TageBanks).map(b => (baseBankLatch +& b.U)(log2Up(TageBanks)-1, 0))) + val if3_bankIdxInOrder = VecInit((0 until TageBanks).map(b => (if3_baseBank +& b.U)(log2Up(TageBanks)-1, 0))) - val realMask = Mux(startsAtOddBank, + val if2_realMask = Mux(if2_startsAtOddBank, Cat(io.req.bits.mask(bankWidth-1,0), io.req.bits.mask(PredictWidth-1, bankWidth)), io.req.bits.mask) - val maskLatch = RegEnable(realMask, enable=io.req.valid) + val if3_realMask = RegEnable(if2_realMask, enable=io.req.valid) (0 until TageBanks).map( b => { - val idxes = VecInit(idxes_and_tags.map(_._1)) - val idx = (if (b < bankWidth) Mux(startsAtOddBank, idxes(1), idxes(0)) - else Mux(startsAtOddBank, idxes(0), idxes(1))) - hi_us(b).io.r.req.valid := io.req.valid && realMask(b) + val idxes = VecInit(if2_idxes_and_tags.map(_._1)) + val idx = (if (b < bankWidth) Mux(if2_startsAtOddBank, idxes(1), idxes(0)) + else Mux(if2_startsAtOddBank, idxes(0), idxes(1))) + hi_us(b).io.r.req.valid := io.req.valid && if2_realMask(b) hi_us(b).io.r.req.bits.setIdx := idx - lo_us(b).io.r.req.valid := io.req.valid && realMask(b) + lo_us(b).io.r.req.valid := io.req.valid && if2_realMask(b) lo_us(b).io.r.req.bits.setIdx := idx table(b).reset := reset.asBool - table(b).io.r.req.valid := io.req.valid && realMask(b) + table(b).io.r.req.valid := io.req.valid && if2_realMask(b) table(b).io.r.req.bits.setIdx := idx - hi_us_r(b) := hi_us(b).io.r.resp.data - lo_us_r(b) := lo_us(b).io.r.resp.data - table_r(b) := table(b).io.r.resp.data(0) + if3_hi_us_r(b) := hi_us(b).io.r.resp.data + if3_lo_us_r(b) := lo_us(b).io.r.resp.data + if3_table_r(b) := table(b).io.r.resp.data(0) } ) - val startsAtOddBankLatch = RegEnable(startsAtOddBank, io.req.valid) + val if3_startsAtOddBank = RegEnable(if2_startsAtOddBank, io.req.valid) - val req_rhits = VecInit((0 until TageBanks).map(b => { - val tag = (if (b < bankWidth) Mux(startsAtOddBank, tags_latch(1), tags_latch(0)) - else Mux(startsAtOddBank, tags_latch(0), tags_latch(1))) - val bank = (if (b < bankWidth) Mux(startsAtOddBankLatch, (b+bankWidth).U, b.U) - else Mux(startsAtOddBankLatch, (b-bankWidth).U, b.U)) - table_r(bank).valid && table_r(bank).tag === tag + val if3_req_rhits = VecInit((0 until TageBanks).map(b => { + val tag = (if (b < bankWidth) Mux(if3_startsAtOddBank, if3_tags(1), if3_tags(0)) + else Mux(if3_startsAtOddBank, if3_tags(0), if3_tags(1))) + val bank = (if (b < bankWidth) Mux(if3_startsAtOddBank, (b+bankWidth).U, b.U) + else Mux(if3_startsAtOddBank, (b-bankWidth).U, b.U)) + if3_table_r(bank).valid && if3_table_r(bank).tag === tag })) (0 until TageBanks).map(b => { - val bank = (if (b < bankWidth) Mux(startsAtOddBankLatch, (b+bankWidth).U, b.U) - else Mux(startsAtOddBankLatch, (b-bankWidth).U, b.U)) - io.resp(b).valid := req_rhits(b) && maskLatch(b) - io.resp(b).bits.ctr := table_r(bank).ctr - io.resp(b).bits.u := Cat(hi_us_r(bank),lo_us_r(bank)) + val bank = (if (b < bankWidth) Mux(if3_startsAtOddBank, (b+bankWidth).U, b.U) + else Mux(if3_startsAtOddBank, (b-bankWidth).U, b.U)) + io.resp(b).valid := if3_req_rhits(b) && if3_realMask(b) + io.resp(b).bits.ctr := if3_table_r(bank).ctr + io.resp(b).bits.u := Cat(if3_hi_us_r(bank),if3_lo_us_r(bank)) }) @@ -292,7 +292,7 @@ class TageTable(val nRows: Int, val histLen: Int, val tagLen: Int, val uBitPerio // when (RegNext(wrbypass_rhit)) { // for (b <- 0 until TageBanks) { // when (RegNext(wrbypass_rctr_hits(b.U + baseBank))) { - // io.resp(b).bits.ctr := rhit_ctrs(bankIdxInOrder(b)) + // io.resp(b).bits.ctr := rhit_ctrs(if3_bankIdxInOrder(b)) // } // } // } @@ -335,17 +335,17 @@ class TageTable(val nRows: Int, val histLen: Int, val tagLen: Int, val uBitPerio val u = io.update val b = PriorityEncoder(u.mask) val ub = PriorityEncoder(u.uMask) - val idx = idxes_and_tags.map(_._1) - val tag = idxes_and_tags.map(_._2) + val idx = if2_idxes_and_tags.map(_._1) + val tag = if2_idxes_and_tags.map(_._2) XSDebug(io.req.valid, "tableReq: pc=0x%x, hist=%x, idx=(%d,%d), tag=(%x,%x), baseBank=%d, mask=%b, realMask=%b\n", - io.req.bits.pc, io.req.bits.hist, idx(0), idx(1), tag(0), tag(1), baseBank, io.req.bits.mask, realMask) + io.req.bits.pc, io.req.bits.hist, idx(0), idx(1), tag(0), tag(1), if2_baseBank, io.req.bits.mask, if2_realMask) for (i <- 0 until TageBanks) { - XSDebug(RegNext(io.req.valid) && req_rhits(i), "TageTableResp[%d]: idx=(%d,%d), hit:%d, ctr:%d, u:%d\n", - i.U, idxes_latch(0), idxes_latch(1), req_rhits(i), io.resp(i).bits.ctr, io.resp(i).bits.u) + XSDebug(RegNext(io.req.valid) && if3_req_rhits(i), "TageTableResp[%d]: idx=(%d,%d), hit:%d, ctr:%d, u:%d\n", + i.U, if3_idxes(0), if3_idxes(1), if3_req_rhits(i), io.resp(i).bits.ctr, io.resp(i).bits.u) } - XSDebug(RegNext(io.req.valid), "TageTableResp: hits:%b, maskLatch is %b\n", req_rhits.asUInt, maskLatch) - XSDebug(RegNext(io.req.valid) && !req_rhits.reduce(_||_), "TageTableResp: no hits!\n") + XSDebug(RegNext(io.req.valid), "TageTableResp: hits:%b, maskLatch is %b\n", if3_req_rhits.asUInt, if3_realMask) + XSDebug(RegNext(io.req.valid) && !if3_req_rhits.reduce(_||_), "TageTableResp: no hits!\n") XSDebug(io.update.mask.reduce(_||_), "update Table: pc:%x, fetchIdx:%d, hist:%x, bank:%d, taken:%d, alloc:%d, oldCtr:%d\n", u.pc, u.fetchIdx, u.hist, b, u.taken(b), u.alloc(b), u.oldCtr(b))