From f8ddc8b4fa3c8560c987a5168e3c5a9a0bfac31e Mon Sep 17 00:00:00 2001
From: Allen <njuallen@foxmail.com>
Date: Thu, 17 Sep 2020 20:29:58 +0800
Subject: [PATCH] PTW: use l1BusDataWidth.

---
 src/main/scala/xiangshan/cache/ptw.scala | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/main/scala/xiangshan/cache/ptw.scala b/src/main/scala/xiangshan/cache/ptw.scala
index 9f5211cca..178a00bb8 100644
--- a/src/main/scala/xiangshan/cache/ptw.scala
+++ b/src/main/scala/xiangshan/cache/ptw.scala
@@ -317,8 +317,8 @@ class PTWImp(outer: PTW) extends PtwModule(outer){
   val pteRead =  edge.Get(
     fromSource = 0.U/*id*/,
     // toAddress  = memAddr(log2Up(CacheLineSize / 2 / 8) - 1, 0),
-    toAddress  = Cat(memAddr(PAddrBits - 1, log2Up(CacheLineSize/2/8)), 0.U(log2Up(CacheLineSize/2/8).W)),
-    lgSize     = log2Up((CacheLineSize/2)/8).U
+    toAddress  = Cat(memAddr(PAddrBits - 1, log2Up(l1BusDataWidth/8)), 0.U(log2Up(l1BusDataWidth/8).W)),
+    lgSize     = log2Up(l1BusDataWidth/8).U
   )._2
   mem.a.bits  := pteRead
   mem.a.valid := state === state_req && 
@@ -328,7 +328,7 @@ class PTWImp(outer: PTW) extends PtwModule(outer){
   mem.d.ready := state === state_wait_resp
 
   val memAddrLatch = RegEnable(memAddr, mem.a.valid)
-  memRdata := (mem.d.bits.data >> (memAddrLatch(4,3) << log2Up(XLEN)))(XLEN - 1, 0)
+  memRdata := (mem.d.bits.data >> (memAddrLatch(log2Up(l1BusDataWidth/8) - 1, log2Up(XLEN/8)) << log2Up(XLEN)))(XLEN - 1, 0)
 
   /*
    * resp
@@ -435,4 +435,4 @@ class PTWImp(outer: PTW) extends PtwModule(outer){
 
   XSDebug(memReqFire, p"mem req fire addr:0x${Hexadecimal(memAddr)}\n")
   XSDebug(memRespFire, p"mem resp fire rdata:0x${Hexadecimal(mem.d.bits.data)} Pte:${memPte}\n")
-}
\ No newline at end of file
+}
-- 
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