diff --git a/src/main/scala/xiangshan/backend/MemBlock.scala b/src/main/scala/xiangshan/backend/MemBlock.scala
index 395de2da77fab860b359b46c5c9127213eef6741..c7b202c95ce168c42bad8a3de3032b7bb6e723bf 100644
--- a/src/main/scala/xiangshan/backend/MemBlock.scala
+++ b/src/main/scala/xiangshan/backend/MemBlock.scala
@@ -283,6 +283,9 @@ class MemBlockImp(outer: MemBlock) extends LazyModuleImp(outer)
     stu.io.stin        <> rs.io.deq
     stu.io.lsq         <> lsq.io.storeIn(i)
 
+    // Lsq to load unit's rs
+    rs.io.stIssuePtr := lsq.io.issuePtrExt
+
     // sync issue info to rs
     lsq.io.storeIssue(i).valid := rs.io.deq.valid
     lsq.io.storeIssue(i).bits := rs.io.deq.bits
diff --git a/src/main/scala/xiangshan/backend/issue/ReservationStation.scala b/src/main/scala/xiangshan/backend/issue/ReservationStation.scala
index 350c47b4131a47ddc707018b54beb1be1b06c259..5f8d90c80ef079455eb2afc39f532fc97755eb65 100644
--- a/src/main/scala/xiangshan/backend/issue/ReservationStation.scala
+++ b/src/main/scala/xiangshan/backend/issue/ReservationStation.scala
@@ -105,7 +105,7 @@ class ReservationStation
     val deq = DecoupledIO(new ExuInput)
     val srcRegValue = Input(Vec(srcNum, UInt(srcLen.W)))
 
-    val stIssuePtr = if (exuCfg == Exu.ldExeUnitCfg) Input(new SqPtr()) else null
+    val stIssuePtr = if (exuCfg == Exu.ldExeUnitCfg || exuCfg == Exu.stExeUnitCfg) Input(new SqPtr()) else null
 
     val fpRegValue = if (exuCfg == Exu.stExeUnitCfg) Input(UInt(srcLen.W)) else null
     val jumpPc = if(exuCfg == Exu.jumpExeUnitCfg) Input(UInt(VAddrBits.W)) else null
@@ -160,7 +160,7 @@ class ReservationStation
     c.valid := i.valid
     c.bits  := i.bits.uop
   }
-  if (exuCfg == Exu.ldExeUnitCfg) {
+  if (exuCfg == Exu.ldExeUnitCfg || exuCfg == Exu.stExeUnitCfg) {
     ctrl.io.stIssuePtr := RegNext(io.stIssuePtr)
   }
 
@@ -476,7 +476,7 @@ class ReservationStationCtrl
     val listen = Output(Vec(srcNum, Vec(iqSize, Vec(fastPortsCnt + slowPortsCnt, Bool()))))
     val enqSrcReady = Output(Vec(srcNum, Bool()))
 
-    val stIssuePtr = if (exuCfg == Exu.ldExeUnitCfg) Input(new SqPtr()) else null
+    val stIssuePtr = if (exuCfg == Exu.ldExeUnitCfg || exuCfg == Exu.stExeUnitCfg) Input(new SqPtr()) else null
   })
 
   val selValid = io.sel.valid
@@ -547,7 +547,7 @@ class ReservationStationCtrl
 
   // load wait store
   io.readyVec := srcQueueWire.map(Cat(_).andR)
-  if (exuCfg == Exu.ldExeUnitCfg) {
+  if (exuCfg == Exu.ldExeUnitCfg || exuCfg == Exu.stExeUnitCfg) {
     val ldWait = Reg(Vec(iqSize, Bool()))
     val sqIdx  = Reg(Vec(iqSize, new SqPtr()))
     ldWait.zip(sqIdx).map{ case (lw, sq) =>