From efcb3cd399278481f661d6c225dac2322173e8ea Mon Sep 17 00:00:00 2001
From: JinYue <jinyue20s@ict.ac.cn>
Date: Fri, 17 Sep 2021 20:39:00 +0800
Subject: [PATCH] ICache: fix fencei not connected

---
 src/main/scala/xiangshan/frontend/Frontend.scala | 2 ++
 src/main/scala/xiangshan/frontend/ICache.scala   | 9 ++++++++-
 2 files changed, 10 insertions(+), 1 deletion(-)

diff --git a/src/main/scala/xiangshan/frontend/Frontend.scala b/src/main/scala/xiangshan/frontend/Frontend.scala
index 4a517baff..c4320cb0a 100644
--- a/src/main/scala/xiangshan/frontend/Frontend.scala
+++ b/src/main/scala/xiangshan/frontend/Frontend.scala
@@ -78,6 +78,8 @@ class FrontendImp (outer: Frontend) extends LazyModuleImp(outer)
   val instrUncache = outer.instrUncache.module
   val icache       = outer.icache.module
 
+  icache.io.fencei := RegNext(io.fencei)
+
   val needFlush = io.backend.toFtq.stage3Redirect.valid
 
   //IFU-Ftq
diff --git a/src/main/scala/xiangshan/frontend/ICache.scala b/src/main/scala/xiangshan/frontend/ICache.scala
index bcafcbcc2..62815ae3c 100644
--- a/src/main/scala/xiangshan/frontend/ICache.scala
+++ b/src/main/scala/xiangshan/frontend/ICache.scala
@@ -127,6 +127,7 @@ class ICacheMetaArray(implicit p: Parameters) extends ICacheArray
     val write    = Flipped(DecoupledIO(new ICacheMetaWriteBundle))
     val read     = Flipped(DecoupledIO(new ICacheReadBundle))
     val readResp = Output(new ICacheMetaRespBundle)
+    val fencei   = Input(Bool())
   }}
 
   io.read.ready := !io.write.valid
@@ -165,6 +166,8 @@ class ICacheMetaArray(implicit p: Parameters) extends ICacheArray
     validArray := validArray.bitSet(validPtr, true.B)
   }
 
+  when(io.fencei){ validArray := 0.U }
+
   (io.readResp.tags zip tagArrays).map    {case (io, sram) => io  := sram.io.r.resp.asTypeOf(Vec(nWays, UInt(tagBits.W)))}
   (io.readResp.valid zip validMetas).map  {case (io, reg)   => io := reg.asTypeOf(Vec(nWays,Bool()))}
 
@@ -377,6 +380,7 @@ class ICacheMissQueue(edge: TLEdgeOut)(implicit p: Parameters) extends ICacheMis
     val data_write  = DecoupledIO(new ICacheDataWriteBundle)
 
     val flush       = Input(Bool())
+    val fencei       = Input(Bool())
 
   })
 
@@ -392,7 +396,7 @@ class ICacheMissQueue(edge: TLEdgeOut)(implicit p: Parameters) extends ICacheMis
     val entry = Module(new ICacheMissEntry(edge))
 
     entry.io.id := i.U(1.W)
-    entry.io.flush := io.flush
+    entry.io.flush := io.flush || io.fencei
 
     // entry req
     entry.io.req.valid := io.req(i).valid
@@ -435,6 +439,7 @@ class ICacheIO(implicit p: Parameters) extends ICacheBundle
   val metaRead    = new ICacheCommonReadBundle(isMeta = true)
   val dataRead    = new ICacheCommonReadBundle(isMeta = false)
   val missQueue   = new ICacheMissBundle
+  val fencei      = Input(Bool())
 }
 
 class ICache()(implicit p: Parameters) extends LazyModule with HasICacheParameters {
@@ -475,6 +480,8 @@ class ICacheImp(outer: ICache) extends LazyModuleImp(outer) with HasICacheParame
   }  
 
   missQueue.io.flush := io.missQueue.flush
+  missQueue.io.fencei := io.fencei
+  metaArray.io.fencei := io.fencei
   bus.a <> missQueue.io.mem_acquire  
   missQueue.io.mem_grant      <> bus.d
 
-- 
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