From eb6496c53bed52d592e2c74a6317fd0ac65e872d Mon Sep 17 00:00:00 2001 From: Lingrui98 Date: Thu, 18 Aug 2022 14:13:36 +0800 Subject: [PATCH] ras: initialize write_bypass_valid to deal with unexpectable x states --- src/main/scala/xiangshan/frontend/RAS.scala | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/main/scala/xiangshan/frontend/RAS.scala b/src/main/scala/xiangshan/frontend/RAS.scala index 98b12dda5..c3af9366e 100644 --- a/src/main/scala/xiangshan/frontend/RAS.scala +++ b/src/main/scala/xiangshan/frontend/RAS.scala @@ -74,8 +74,8 @@ class RAS(implicit p: Parameters) extends BasePredictor { val wen = WireInit(false.B) val write_bypass_entry = Reg(new RASEntry()) - val write_bypass_ptr = Reg(UInt(log2Up(rasSize).W)) - val write_bypass_valid = Reg(Bool()) + val write_bypass_ptr = RegInit(0.U(log2Up(rasSize).W)) + val write_bypass_valid = RegInit(false.B) when (wen) { write_bypass_valid := true.B }.elsewhen (write_bypass_valid) { -- GitLab