diff --git a/src/main/scala/xiangshan/frontend/SC.scala b/src/main/scala/xiangshan/frontend/SC.scala
index 8b0c9fc0d17dba1c72d84d5624d9f5c9b227b5d3..8d9cab338dab0dfbf7807cdfd7c6929e699f3875 100644
--- a/src/main/scala/xiangshan/frontend/SC.scala
+++ b/src/main/scala/xiangshan/frontend/SC.scala
@@ -244,12 +244,12 @@ trait HasSC extends HasSCParameter { this: Tage =>
       }
     }
     for (i <- 0 until SCNTables) {
-      scTables(i).io.update.mask := scUpdateMask(i)
-      scTables(i).io.update.tagePreds := scUpdateTagePreds
-      scTables(i).io.update.takens    := scUpdateTakens
-      scTables(i).io.update.oldCtrs   := VecInit(scUpdateOldCtrs.map(_(i)))
-      scTables(i).io.update.pc := u.ftqPC
-      scTables(i).io.update.hist := updateHist
+      scTables(i).io.update.mask := RegNext(scUpdateMask(i))
+      scTables(i).io.update.tagePreds := RegNext(scUpdateTagePreds)
+      scTables(i).io.update.takens    := RegNext(scUpdateTakens)
+      scTables(i).io.update.oldCtrs   := RegNext(VecInit(scUpdateOldCtrs.map(_(i))))
+      scTables(i).io.update.pc := RegNext(u.ftqPC)
+      scTables(i).io.update.hist := RegNext(updateHist)
     }
   }
 }
\ No newline at end of file
diff --git a/src/main/scala/xiangshan/frontend/Tage.scala b/src/main/scala/xiangshan/frontend/Tage.scala
index 749719355b219def4d0942bec21ce2180713e78e..5e480a7f5dfc2ce64524db4b6a20a3d665697060 100644
--- a/src/main/scala/xiangshan/frontend/Tage.scala
+++ b/src/main/scala/xiangshan/frontend/Tage.scala
@@ -495,17 +495,17 @@ class Tage extends BaseTage {
 
   for (i <- 0 until TageNTables) {
     for (w <- 0 until TageBanks) {
-      tables(i).io.update.mask(w) := updateMask(i)(w)
-      tables(i).io.update.taken(w) := updateTaken(i)(w)
-      tables(i).io.update.alloc(w) := updateAlloc(i)(w)
-      tables(i).io.update.oldCtr(w) := updateOldCtr(i)(w)
-
-      tables(i).io.update.uMask(w) := updateUMask(i)(w)
-      tables(i).io.update.u(w) := updateU(i)(w)
-      tables(i).io.update.pc := packetAligned(u.ftqPC) + (w << instOffsetBits).U
+      tables(i).io.update.mask(w) := RegNext(updateMask(i)(w))
+      tables(i).io.update.taken(w) := RegNext(updateTaken(i)(w))
+      tables(i).io.update.alloc(w) := RegNext(updateAlloc(i)(w))
+      tables(i).io.update.oldCtr(w) := RegNext(updateOldCtr(i)(w))
+
+      tables(i).io.update.uMask(w) := RegNext(updateUMask(i)(w))
+      tables(i).io.update.u(w) := RegNext(updateU(i)(w))
+      tables(i).io.update.pc := RegNext(packetAligned(u.ftqPC) + (w << instOffsetBits).U)
     }
     // use fetch pc instead of instruction pc
-    tables(i).io.update.hist := updateHist
+    tables(i).io.update.hist := RegNext(updateHist)
   }