From e98a8bc712ec81cd6d2b3767c55aa8fd7711482e Mon Sep 17 00:00:00 2001 From: JinYue Date: Tue, 27 Jul 2021 13:12:52 +0800 Subject: [PATCH] fix 3 bugs while running coremark * FTB: fix getJmpOffset function * Ftq: fix set_replay_status_between function * IFU: toFtq.valid only holds 1 cycle --- src/main/scala/xiangshan/decoupled-frontend/FTB.scala | 2 +- src/main/scala/xiangshan/decoupled-frontend/IFU.scala | 3 ++- src/main/scala/xiangshan/decoupled-frontend/NewFtq.scala | 2 +- 3 files changed, 4 insertions(+), 3 deletions(-) diff --git a/src/main/scala/xiangshan/decoupled-frontend/FTB.scala b/src/main/scala/xiangshan/decoupled-frontend/FTB.scala index 234b41607..98ca8ff06 100644 --- a/src/main/scala/xiangshan/decoupled-frontend/FTB.scala +++ b/src/main/scala/xiangshan/decoupled-frontend/FTB.scala @@ -67,7 +67,7 @@ class FTBEntry (implicit p: Parameters) extends XSBundle with FTBParams { // (taken_mask, target) // } - def getJmpOffset(pc: UInt) = Cat(1.U(1.W), pftAddr(4,1)) - Mux(last_is_rvc, 2.U, 4.U) - pc(4,1) + def getJmpOffset(pc: UInt) = Cat(1.U(1.W), pftAddr(4,1)) - Mux(last_is_rvc, 1.U, 2.U) - pc(4,1) def isJal = !isJalr } diff --git a/src/main/scala/xiangshan/decoupled-frontend/IFU.scala b/src/main/scala/xiangshan/decoupled-frontend/IFU.scala index fa03227c3..7a2d3ac7b 100644 --- a/src/main/scala/xiangshan/decoupled-frontend/IFU.scala +++ b/src/main/scala/xiangshan/decoupled-frontend/IFU.scala @@ -404,8 +404,9 @@ class NewIFU(implicit p: Parameters) extends XSModule with Temperary with HasICa io.toIbuffer.bits.ftqOffset.zipWithIndex.map{case(a, i) => a.bits := i.U; a.valid := preDecoderOut.takens(i)} io.toIbuffer.bits.foldpc := preDecoderOut.pc.map(i => XORFold(i(VAddrBits-1,1), MemPredPCWidth)) + val finishFetchMaskReg = RegNext(((f2_valid && f2_hit) || miss_all_fix) && !f1_fire) - toFtq.pdWb.valid := (f2_valid && f2_hit) || miss_all_fix + toFtq.pdWb.valid := !finishFetchMaskReg & ((f2_valid && f2_hit) || miss_all_fix) toFtq.pdWb.bits.pc := preDecoderOut.pc toFtq.pdWb.bits.pd := preDecoderOut.pd toFtq.pdWb.bits.pd.zipWithIndex.map{case(instr,i) => instr.valid := f2_predecode_valids(i)} diff --git a/src/main/scala/xiangshan/decoupled-frontend/NewFtq.scala b/src/main/scala/xiangshan/decoupled-frontend/NewFtq.scala index ddeb9c26b..b3c60818d 100644 --- a/src/main/scala/xiangshan/decoupled-frontend/NewFtq.scala +++ b/src/main/scala/xiangshan/decoupled-frontend/NewFtq.scala @@ -384,7 +384,7 @@ class Ftq(implicit p: Parameters) extends XSModule with HasCircularQueuePtrHelpe } val set_fetch_status_between = set_status_between(entry_fetch_status)(_, _, _) val set_commit_status_between = set_status_between(commitStateQueue)(_, _, _) - val set_replay_status_between = set_status_between(entry_fetch_status)(_, _, _) + val set_replay_status_between = set_status_between(entry_replay_status)(_, _, _) when (enq_fire) { val enqIdx = bpuPtr.value -- GitLab