From e8747464d298b42afdf9de44f5562bd1bb649a7d Mon Sep 17 00:00:00 2001 From: Jenius Date: Mon, 6 Jun 2022 21:09:05 +0800 Subject: [PATCH] discard iprefetch req when resource busy --- src/main/scala/xiangshan/frontend/NewFtq.scala | 1 + src/main/scala/xiangshan/frontend/icache/IPrefetch.scala | 6 ++++-- 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/src/main/scala/xiangshan/frontend/NewFtq.scala b/src/main/scala/xiangshan/frontend/NewFtq.scala index e8d36b850..961f4284c 100644 --- a/src/main/scala/xiangshan/frontend/NewFtq.scala +++ b/src/main/scala/xiangshan/frontend/NewFtq.scala @@ -1014,6 +1014,7 @@ class Ftq(implicit p: Parameters) extends XSModule with HasCircularQueuePtrHelpe } XSError(isBefore(bpuPtr, prefetchPtr) && !isFull(bpuPtr, prefetchPtr), "\nprefetchPtr is before bpuPtr!\n") + XSError(isBefore(prefetchPtr, ifuPtr) && !isFull(ifuPtr, prefetchPtr), "\nifuPtr is before prefetchPtr!\n") } else { io.toPrefetch.req <> DontCare diff --git a/src/main/scala/xiangshan/frontend/icache/IPrefetch.scala b/src/main/scala/xiangshan/frontend/icache/IPrefetch.scala index 934fd1476..f7f8201db 100644 --- a/src/main/scala/xiangshan/frontend/icache/IPrefetch.scala +++ b/src/main/scala/xiangshan/frontend/icache/IPrefetch.scala @@ -89,6 +89,8 @@ class IPrefetchPipe(implicit p: Parameters) extends IPrefetchModule val p0_valid = fromFtq.req.valid val p0_vaddr = addrAlign(fromFtq.req.bits.target, blockBytes, VAddrBits) p0_fire := p0_valid && p1_ready && toITLB.fire() && !fromITLB.bits.miss && toIMeta.ready && enableBit + //discard req when source not ready + // p0_discard := p0_valid && ((toITLB.fire() && fromITLB.bits.miss) || !toIMeta.ready || !enableBit) toIMeta.valid := p0_valid toIMeta.bits.vSetIdx(0) := get_idx(p0_vaddr) @@ -108,7 +110,7 @@ class IPrefetchPipe(implicit p: Parameters) extends IPrefetchModule fromITLB.ready := true.B - fromFtq.req.ready := (!enableBit || (enableBit && p3_ready)) && toIMeta.ready //&& GTimer() > 500.U + fromFtq.req.ready := true.B //(!enableBit || (enableBit && p3_ready)) && toIMeta.ready //&& GTimer() > 500.U /** Prefetch Stage 1: cache probe filter */ val p1_valid = generatePipeControl(lastFire = p0_fire, thisFire = p1_fire || p1_discard, thisFlush = false.B, lastFlush = false.B) @@ -178,7 +180,7 @@ class IPrefetchPipe(implicit p: Parameters) extends IPrefetchModule val p3_hit_dir = VecInit((0 until nPrefetchEntries).map(i => prefetch_dir(i).valid && prefetch_dir(i).paddr === p3_paddr )).reduce(_||_) - p3_discard := p3_hit_dir || p3_check_in_mshr + p3_discard := p3_hit_dir || p3_check_in_mshr || (p3_valid && enableBit && !toMissUnit.enqReq.ready) toMissUnit.enqReq.valid := p3_valid && enableBit && !p3_discard toMissUnit.enqReq.bits.paddr := p3_paddr -- GitLab