diff --git a/src/main/scala/xiangshan/backend/fu/CSR.scala b/src/main/scala/xiangshan/backend/fu/CSR.scala
index 62ae40090db81d22fa32536a3813ff804c45f788..f80ac03b1665f05f0eee85c83d7f025d69ecaa16 100644
--- a/src/main/scala/xiangshan/backend/fu/CSR.scala
+++ b/src/main/scala/xiangshan/backend/fu/CSR.scala
@@ -236,7 +236,7 @@ class CSR extends FunctionUnit with HasCSRConst
   val mimpid = RegInit(UInt(XLEN.W), 0.U) // provides a unique encoding of the version of the processor implementation
   val mhartNo = hartId()
   val mhartid = RegInit(UInt(XLEN.W), mhartNo.asUInt) // the hardware thread running the code
-  val mstatus = RegInit(UInt(XLEN.W), "h00001800".U)  // another option: "h8000c0100".U
+  val mstatus = RegInit(UInt(XLEN.W), 0.U)
 
   // mstatus Value Table
   // | sd   |