diff --git a/src/main/scala/noop/Bundle.scala b/src/main/scala/noop/Bundle.scala
index 7ba2734fd8b1e2c88f8656b03adc27b8856153e2..d8cf0abb52fbbe24008f424abf2cbbcdab49bdba 100644
--- a/src/main/scala/noop/Bundle.scala
+++ b/src/main/scala/noop/Bundle.scala
@@ -52,7 +52,6 @@ class BranchIO extends Bundle {
 
 class CommitIO extends Bundle with HasFuType {
   val pc = Output(UInt(32.W))
-  val npc = Output(UInt(32.W))
   val ctrl = new CtrlPathIO
   val isMMIO = Output(Bool())
   val commits = Output(Vec(FuTypeNum, new WriteBackIO))
diff --git a/src/main/scala/noop/EXU.scala b/src/main/scala/noop/EXU.scala
index 5ad6f29888d8e4b4f9f0546cec5293944568c313..66873407125b15daf14b973e20e8ad862af2429f 100644
--- a/src/main/scala/noop/EXU.scala
+++ b/src/main/scala/noop/EXU.scala
@@ -58,7 +58,6 @@ class EXU(implicit val p: NOOPConfig) extends Module with HasFuType {
   csr.io.out.ready := true.B
 
   io.out.bits.br <> Mux(csr.io.csrjmp.isTaken, csr.io.csrjmp, bru.io.branch)
-  io.out.bits.npc := io.in.bits.npc
 
   io.out.bits.ctrl := DontCare
   (io.out.bits.ctrl, io.in.bits.ctrl) match { case (o, i) =>
diff --git a/src/main/scala/noop/WBU.scala b/src/main/scala/noop/WBU.scala
index b398febd1a1c93cff4f0ac567e454f19bfae6c3b..87781b0b3cfee3eea3dc6903ab5062185cf558ec 100644
--- a/src/main/scala/noop/WBU.scala
+++ b/src/main/scala/noop/WBU.scala
@@ -17,7 +17,7 @@ class WBU(implicit val p: NOOPConfig) extends Module {
   io.in.ready := true.B
 
   io.brOut <> io.in.bits.br
-  io.brOut.isTaken := io.in.bits.br.isTaken && io.in.valid && (io.in.bits.br.target =/= io.in.bits.npc)
+  io.brOut.isTaken := io.in.bits.br.isTaken && io.in.valid
 
   BoringUtils.addSource(io.in.valid, "perfCntCondMinstret")
   if (!p.FPGAPlatform) {
diff --git a/src/main/scala/noop/fu/BRU.scala b/src/main/scala/noop/fu/BRU.scala
index e65cd0478a4829a89694055b3a8f8a807aec89b1..8a4068894adbf6205b8261bec0bb48afbd7e2243 100644
--- a/src/main/scala/noop/fu/BRU.scala
+++ b/src/main/scala/noop/fu/BRU.scala
@@ -93,8 +93,7 @@ class BRU extends Module with HasBRUOpType {
   val target = Mux(func === BruJalr || func === BruRet, src1, io.pc) + io.offset
   io.branch.target := Mux(!taken && isBranch(func), io.pc + 4.U, target)
   // with branch predictor, this is actually to fix the wrong prediction
-  // to improve timing, we move the prediction checking to WBU statge
-  io.branch.isTaken := valid
+  io.branch.isTaken := valid && (io.branch.target =/= io.npc)
   io.out.bits := io.pc + 4.U
 
   io.in.ready := true.B