From e4ecf3b0a36f368cd3213afdf1309fd1339c409f Mon Sep 17 00:00:00 2001 From: JinYue Date: Mon, 13 Sep 2021 17:52:35 +0800 Subject: [PATCH] ICache: fix physical tag bug * Using get_phy_tag function instead of get_tag * This bug happens when using VIPT ICache and setting lage set number --- src/main/scala/xiangshan/cache/L1Cache.scala | 1 + src/main/scala/xiangshan/frontend/ICache.scala | 2 +- src/main/scala/xiangshan/frontend/IFU.scala | 2 +- 3 files changed, 3 insertions(+), 2 deletions(-) diff --git a/src/main/scala/xiangshan/cache/L1Cache.scala b/src/main/scala/xiangshan/cache/L1Cache.scala index 13c162d0d..06690eb8b 100644 --- a/src/main/scala/xiangshan/cache/L1Cache.scala +++ b/src/main/scala/xiangshan/cache/L1Cache.scala @@ -81,6 +81,7 @@ trait HasL1CacheParameters extends HasXSParameter def offsetlsb = wordOffBits def get_tag(addr: UInt) = (addr >> untagBits).asUInt() + def get_phy_tag(paddr: UInt) = (paddr >> pgUntagBits).asUInt() def get_idx(addr: UInt) = addr(untagBits-1, blockOffBits) def get_block(addr: UInt) = addr >> blockOffBits def get_block_addr(addr: UInt) = (addr >> blockOffBits) << blockOffBits diff --git a/src/main/scala/xiangshan/frontend/ICache.scala b/src/main/scala/xiangshan/frontend/ICache.scala index bcafcbcc2..3d853de12 100644 --- a/src/main/scala/xiangshan/frontend/ICache.scala +++ b/src/main/scala/xiangshan/frontend/ICache.scala @@ -268,7 +268,7 @@ class ICacheMissEntry(edge: TLEdgeOut)(implicit p: Parameters) extends ICacheMis //req register val req = Reg(new ICacheMissReq) val req_idx = req.vSetIdx //virtual index - val req_tag = get_tag(req.addr) //physical tag + val req_tag = get_phy_tag(req.addr) //physical tag val req_waymask = req.waymask val (_, _, refill_done, refill_address_inc) = edge.addr_inc(io.mem_grant) diff --git a/src/main/scala/xiangshan/frontend/IFU.scala b/src/main/scala/xiangshan/frontend/IFU.scala index bc85e18c4..d8d9287f2 100644 --- a/src/main/scala/xiangshan/frontend/IFU.scala +++ b/src/main/scala/xiangshan/frontend/IFU.scala @@ -194,7 +194,7 @@ class NewIFU(implicit p: Parameters) extends XSModule with HasICacheParameters tlbRespAllValid := tlbRespValid(0) && (tlbRespValid(1) || !f1_doubleLine) val f1_pAddrs = tlbRespPAddr //TODO: Temporary assignment - val f1_pTags = VecInit(f1_pAddrs.map(get_tag(_))) + val f1_pTags = VecInit(f1_pAddrs.map(get_phy_tag(_))) val (f1_tags, f1_cacheline_valid, f1_datas) = (meta_resp.tags, meta_resp.valid, data_resp.datas) val bank0_hit_vec = VecInit(f1_tags(0).zipWithIndex.map{ case(way_tag,i) => f1_cacheline_valid(0)(i) && way_tag === f1_pTags(0) }) val bank1_hit_vec = VecInit(f1_tags(1).zipWithIndex.map{ case(way_tag,i) => f1_cacheline_valid(1)(i) && way_tag === f1_pTags(1) }) -- GitLab