From e2e1147668363a0e3da3537ceb8fa87e7d9bf0a2 Mon Sep 17 00:00:00 2001
From: William Wang <zeweiwang@outlook.com>
Date: Thu, 28 Jan 2021 14:47:27 +0800
Subject: [PATCH] Sbuffer: delay sbuffer to dcache req for one cycle

* Now we use a full cycle to get a copy of data from buffer
---
 .../xiangshan/mem/sbuffer/NewSbuffer.scala    | 30 +++++++++++--------
 1 file changed, 18 insertions(+), 12 deletions(-)

diff --git a/src/main/scala/xiangshan/mem/sbuffer/NewSbuffer.scala b/src/main/scala/xiangshan/mem/sbuffer/NewSbuffer.scala
index 37b9d9a45..61de24985 100644
--- a/src/main/scala/xiangshan/mem/sbuffer/NewSbuffer.scala
+++ b/src/main/scala/xiangshan/mem/sbuffer/NewSbuffer.scala
@@ -150,7 +150,7 @@ class NewSbuffer extends XSModule with HasSbufferCst {
   // sbuffer entry count
   val invalidCount = RegInit(StoreBufferSize.U((log2Up(StoreBufferSize) + 1).W))
   val validCount = RegInit(0.U((log2Up(StoreBufferSize) + 1).W))
-  val full = invalidCount === 0.U
+  val full = invalidCount === 0.U // full = TODO: validCount(log2Up(StoreBufferSize))
 
   val bufferRead  = VecInit((0 until StoreBufferSize).map(i => buffer(i)))
   val stateRead   = VecInit((0 until StoreBufferSize).map(i => stateVec(i)))
@@ -244,7 +244,7 @@ class NewSbuffer extends XSModule with HasSbufferCst {
     when(canMerge(0)){
       mergeWordReq(io.in(0).bits, mergeIdx(0), firstWord)
       XSDebug(p"merge req 0 to line [${mergeIdx(0)}]\n")
-    }.elsewhen(firstCanInsert){
+    }.otherwise{
       wordReqToBufLine(io.in(0).bits, tags(0), firstInsertIdx, firstWord, true.B)
       XSDebug(p"insert req 0 to line[$firstInsertIdx]\n")
     }
@@ -255,7 +255,7 @@ class NewSbuffer extends XSModule with HasSbufferCst {
     when(canMerge(1)){
       mergeWordReq(io.in(1).bits, mergeIdx(1), secondWord)
       XSDebug(p"merge req 1 to line [${mergeIdx(1)}]\n")
-    }.elsewhen(secondCanInsert){
+    }.otherwise{
       wordReqToBufLine(io.in(1).bits, tags(1), secondInsertIdx, secondWord, !sameTag)
       XSDebug(p"insert req 1 to line[$secondInsertIdx]\n")
     }
@@ -350,18 +350,24 @@ class NewSbuffer extends XSModule with HasSbufferCst {
   val prepareMask = stateVec.map(s => s === s_prepare)
   val (prepareIdx, prepareEn) = PriorityEncoderWithFlag(prepareMask)
 
-
-  io.dcache.req.valid := prepareEn
-
-  io.dcache.req.bits.addr := getAddr(tagRead(prepareIdx))
-  io.dcache.req.bits.data := bufferRead(prepareIdx).data
-  io.dcache.req.bits.mask := bufferRead(prepareIdx).mask
-  io.dcache.req.bits.cmd := MemoryOpConstants.M_XWR
-  io.dcache.req.bits.meta := DontCare
-  io.dcache.req.bits.meta.id := prepareIdx
+  val dcacheReqValid = RegInit(false.B)
+  val dcacheCandidate = Reg(new DCacheLineReq)
   when(io.dcache.req.fire()){
+    dcacheReqValid := false.B
+  }
+  when(prepareEn && (!dcacheReqValid || io.dcache.req.fire())) {
+    dcacheCandidate.addr := getAddr(tagRead(prepareIdx))
+    dcacheCandidate.data := bufferRead(prepareIdx).data
+    dcacheCandidate.mask := bufferRead(prepareIdx).mask
+    dcacheCandidate.cmd := MemoryOpConstants.M_XWR
+    dcacheCandidate.meta := DontCare
+    dcacheCandidate.meta.id := prepareIdx
     stateVec(prepareIdx) := s_inflight
+    dcacheReqValid := true.B
   }
+
+  io.dcache.req.valid := dcacheReqValid
+  io.dcache.req.bits := dcacheCandidate
 //  evictionEntry.ready := io.dcache.req.ready
 
   XSDebug(io.dcache.req.fire(),
-- 
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