From d4fcfc3e7a8aca88f4bd880456c36ef650dd10f2 Mon Sep 17 00:00:00 2001 From: Guokai Chen Date: Sun, 23 Jul 2023 12:13:45 +0800 Subject: [PATCH] FTQ: fix debug cfi check condition (#2198) --- src/main/scala/xiangshan/frontend/NewFtq.scala | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/main/scala/xiangshan/frontend/NewFtq.scala b/src/main/scala/xiangshan/frontend/NewFtq.scala index a1100798b..699d45911 100644 --- a/src/main/scala/xiangshan/frontend/NewFtq.scala +++ b/src/main/scala/xiangshan/frontend/NewFtq.scala @@ -1149,12 +1149,13 @@ class Ftq(implicit p: Parameters) extends XSModule with HasCircularQueuePtrHelpe } val commit_state = RegNext(commitStateQueue(commPtr.value)) val can_commit_cfi = WireInit(cfiIndex_vec(commPtr.value)) + val do_commit_cfi = WireInit(cfiIndex_vec(do_commit_ptr.value)) // //when (commitStateQueue(commPtr.value)(can_commit_cfi.bits) =/= c_commited) { // can_commit_cfi.valid := false.B //} val commit_cfi = RegNext(can_commit_cfi) - val debug_cfi = RegNext(commitStateQueue(commPtr.value)(can_commit_cfi.bits) =/= c_commited && can_commit_cfi.valid) + val debug_cfi = commitStateQueue(do_commit_ptr.value)(do_commit_cfi.bits) =/= c_commited && do_commit_cfi.valid val commit_mispredict : Vec[Bool] = VecInit((RegNext(mispredict_vec(commPtr.value)) zip commit_state).map { case (mis, state) => mis && state === c_commited -- GitLab