From d0be71e238bc4de81e6a619bac32a5759b671d71 Mon Sep 17 00:00:00 2001 From: zhanglinjuan Date: Sat, 20 Feb 2021 14:55:55 +0800 Subject: [PATCH] MissQueue: fix bug that st may cover should_refill_data when mering a ld --- src/main/scala/xiangshan/cache/MissQueue.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/xiangshan/cache/MissQueue.scala b/src/main/scala/xiangshan/cache/MissQueue.scala index 90ee25708..f094991cf 100644 --- a/src/main/scala/xiangshan/cache/MissQueue.scala +++ b/src/main/scala/xiangshan/cache/MissQueue.scala @@ -195,7 +195,7 @@ class MissEntry(edge: TLEdgeOut) extends DCacheModule req := io.req } - should_refill_data := io.req.source === LOAD_SOURCE.U + should_refill_data := should_refill_data || io.req.source === LOAD_SOURCE.U } -- GitLab