diff --git a/src/main/scala/xiangshan/cache/MissQueue.scala b/src/main/scala/xiangshan/cache/MissQueue.scala
index 90ee25708e72f073d15b22036696172b04691758..f094991cf54793718d2c9bdf405d4a5e0ae6bf0d 100644
--- a/src/main/scala/xiangshan/cache/MissQueue.scala
+++ b/src/main/scala/xiangshan/cache/MissQueue.scala
@@ -195,7 +195,7 @@ class MissEntry(edge: TLEdgeOut) extends DCacheModule
       req := io.req
     }
 
-    should_refill_data := io.req.source === LOAD_SOURCE.U
+    should_refill_data := should_refill_data || io.req.source === LOAD_SOURCE.U
   }