diff --git a/src/main/scala/xiangshan/backend/decode/DecodeStage.scala b/src/main/scala/xiangshan/backend/decode/DecodeStage.scala
index 649e3204ed81801f7a3fa1a41462c49b6f2a1ad6..ac1a221d8c55d2548ad9318bf0445f4c4f29c1fa 100644
--- a/src/main/scala/xiangshan/backend/decode/DecodeStage.scala
+++ b/src/main/scala/xiangshan/backend/decode/DecodeStage.scala
@@ -48,7 +48,7 @@ class DecodeStage(implicit p: Parameters) extends XSModule
   })
 
   private val v0Idx = 0
-  private val vconfigIdx = VECTOR_VCONFIG
+  private val vconfigIdx = VCONFIG_IDX
 
   val decoderComp = Module(new DecodeUnitComp)
   val decoders = Seq.fill(DecodeWidth - 1)(Module(new DecodeUnit))
diff --git a/src/main/scala/xiangshan/backend/decode/DecodeUnitComp.scala b/src/main/scala/xiangshan/backend/decode/DecodeUnitComp.scala
index 6a3eeb823f18cac6ba2c4d3075d67ee6a20cdf4b..91a5cdb08144107550749e101c3e6679b816e4da 100644
--- a/src/main/scala/xiangshan/backend/decode/DecodeUnitComp.scala
+++ b/src/main/scala/xiangshan/backend/decode/DecodeUnitComp.scala
@@ -38,7 +38,7 @@ trait VectorConstants {
   val MAX_VLMUL = 8
   val FP_TMP_REG_MV = 32
   val VECTOR_TMP_REG_LMUL = 32 // 32~38  ->  7
-  val VECTOR_VCONFIG = 39
+  val VCONFIG_IDX = 39
 }
 
 class DecodeUnitCompIO(implicit p: Parameters) extends XSBundle {
@@ -167,13 +167,13 @@ class DecodeUnitComp()(implicit p : Parameters) extends XSModule with DecodeUnit
           csBundle(0).flushPipe := false.B
           csBundle(0).rfWen := true.B
           csBundle(0).vecWen := false.B
-          csBundle(1).ldest := VECTOR_VCONFIG.U
+          csBundle(1).ldest := VCONFIG_IDX.U
         }.elsewhen(src1 =/= 0.U) {
-          csBundle(0).ldest := VECTOR_VCONFIG.U
+          csBundle(0).ldest := VCONFIG_IDX.U
         }.elsewhen(VSETOpType.isVsetvli(decodedInsts_u.fuOpType)) {
           csBundle(0).fuType := FuType.vsetfwf.U
           csBundle(0).srcType(0) := SrcType.vp
-          csBundle(0).lsrc(0) := VECTOR_VCONFIG.U
+          csBundle(0).lsrc(0) := VCONFIG_IDX.U
         }.elsewhen(VSETOpType.isVsetvl(decodedInsts_u.fuOpType)) {
           csBundle(0).srcType(0) := SrcType.reg
           csBundle(0).srcType(1) := SrcType.imm
@@ -195,10 +195,10 @@ class DecodeUnitComp()(implicit p : Parameters) extends XSModule with DecodeUnit
           csBundle(0).flushPipe := false.B
           csBundle(1).fuType := FuType.vsetfwf.U
           csBundle(1).srcType(0) := SrcType.vp
-          csBundle(1).lsrc(0) := VECTOR_VCONFIG.U
+          csBundle(1).lsrc(0) := VCONFIG_IDX.U
           csBundle(1).srcType(1) := SrcType.fp
           csBundle(1).lsrc(1) := FP_TMP_REG_MV.U
-          csBundle(1).ldest := VECTOR_VCONFIG.U
+          csBundle(1).ldest := VCONFIG_IDX.U
         }
       }
     }