diff --git a/src/test/scala/device/SimMMIOTest.scala b/src/test/scala/device/SimMMIOTest.scala
new file mode 100644
index 0000000000000000000000000000000000000000..1e47fc0a6bd509092f17ca6ff8987b9f047bd33a
--- /dev/null
+++ b/src/test/scala/device/SimMMIOTest.scala
@@ -0,0 +1,43 @@
+package device
+
+import chipsalliance.rocketchip.config._
+import chisel3._
+import chiseltest._
+import freechips.rocketchip.amba.axi4.{AXI4Deinterleaver, AXI4UserYanker, AXI4Xbar}
+import org.scalatest.{FlatSpec, Matchers}
+import freechips.rocketchip.tilelink._
+import freechips.rocketchip.diplomacy._
+import top.SimMMIO
+import utils.DebugIdentityNode
+
+class SimMMIOTestTop()(implicit p: Parameters) extends LazyModule {
+
+  val addressSet = AddressSet(0x40600000L, 0xf)
+
+  val fuzz = LazyModule(new TLFuzzer(nOperations = 10, inFlight = 1, overrideAddress = Some(addressSet)))
+  val simMMIO = LazyModule(new SimMMIO())
+
+  simMMIO.axiBus :=
+    AXI4UserYanker() :=
+    TLToAXI4() :=
+    DebugIdentityNode() :=
+    fuzz.node
+
+  lazy val module = new LazyModuleImp(this){
+    val finished = IO(Output(Bool()))
+    finished := fuzz.module.io.finished
+  }
+}
+
+class SimMMIOTest extends FlatSpec with ChiselScalatestTester with Matchers {
+  it should "run" in {
+    implicit val p = Parameters.empty
+    test(LazyModule(new SimMMIOTestTop()).module){c =>
+      while (!c.finished.peek().litToBoolean){
+        c.clock.step(1)
+      }
+    }
+  }
+}
+
+