From bf16ffe44d9d7f7facbef440879f166a6ac6224c Mon Sep 17 00:00:00 2001
From: LinJiawei <linjiav@outlook.com>
Date: Sun, 10 May 2020 10:06:54 +0800
Subject: [PATCH] [FMA] fix a bug in stage 2

---
 src/main/scala/fpu/fma/FMA.scala | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/main/scala/fpu/fma/FMA.scala b/src/main/scala/fpu/fma/FMA.scala
index fa39f2f2e..bb96115c1 100644
--- a/src/main/scala/fpu/fma/FMA.scala
+++ b/src/main/scala/fpu/fma/FMA.scala
@@ -167,7 +167,7 @@ class FMA extends FPUSubModule with HasPipelineReg {
     0.U(1.W), // sign bit
     ShiftRightJam(s1_aMant, Mux(s1_discardProdMant, 0.U, s1_expDiff.asUInt()), ADD_WIDTH+3)
   )
-  val alignedAMantNeg = (~alignedAMant).asUInt()
+  val alignedAMantNeg = -alignedAMant
   val effSub = s1_prodSign ^ s1_aSign
 
   val mul_prod = mult.io.carry.tail(1) + mult.io.sum.tail(1)
-- 
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