From bec36597f1c6d64c9598b7840d898c2b04426eef Mon Sep 17 00:00:00 2001 From: LinJiawei Date: Thu, 30 Jul 2020 23:25:30 +0800 Subject: [PATCH] Brq: fix 'sel-lo' bug --- src/main/scala/xiangshan/backend/brq/Brq.scala | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/src/main/scala/xiangshan/backend/brq/Brq.scala b/src/main/scala/xiangshan/backend/brq/Brq.scala index 9450307b9..35566226b 100644 --- a/src/main/scala/xiangshan/backend/brq/Brq.scala +++ b/src/main/scala/xiangshan/backend/brq/Brq.scala @@ -122,14 +122,20 @@ class Brq extends XSModule { } val headIdxMaskHi = headIdxMaskHiVec.asUInt() val headIdxMaskLo = (~headIdxMaskHi).asUInt() + + val skipMaskHi = headIdxMaskHi & skipMask + val skipMaskLo = headIdxMaskLo & skipMask + val commitIdxHi, commitIdxLo, commitIdx = Wire(UInt(BrqSize.W)) - commitIdxHi := PriorityEncoder(~(headIdxMaskHi & skipMask)) - commitIdxLo := PriorityEncoder(~(headIdxMaskLo & skipMask)) + commitIdxHi := PriorityEncoder(~skipMaskHi) + commitIdxLo := PriorityEncoder(~skipMaskLo) + + val useLo = (skipMaskHi | headIdxMaskLo) === Fill(BrqSize, 1.U(1.W)) commitIdx := Mux(stateQueue(commitIdxHi).isWb && brQueue(commitIdxHi).misPred, commitIdxHi, - Mux(stateQueue(commitIdxLo).isWb && brQueue(commitIdxLo).misPred, + Mux(useLo && stateQueue(commitIdxLo).isWb && brQueue(commitIdxLo).misPred, commitIdxLo, headIdx ) -- GitLab