From beb0d8c1324e3f84bc799eecd3d2937649c80250 Mon Sep 17 00:00:00 2001
From: Yinan Xu <xuyinan1997@gmail.com>
Date: Thu, 6 Aug 2020 17:36:56 +0800
Subject: [PATCH] dtlb: add random miss

---
 src/main/scala/xiangshan/cache/dtlb.scala | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/main/scala/xiangshan/cache/dtlb.scala b/src/main/scala/xiangshan/cache/dtlb.scala
index 925b8e48c..68353d317 100644
--- a/src/main/scala/xiangshan/cache/dtlb.scala
+++ b/src/main/scala/xiangshan/cache/dtlb.scala
@@ -32,6 +32,6 @@ class Dtlb extends XSModule {
   (0 until LoadPipelineWidth + StorePipelineWidth).map(i => {
     io.lsu(i).resp.valid := io.lsu(i).req.valid
     io.lsu(i).resp.bits.paddr := io.lsu(i).req.bits.vaddr
-    io.lsu(i).resp.bits.miss := false.B
+    io.lsu(i).resp.bits.miss := LFSR64()(3, 0) === 0.U
   })
 }
-- 
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