From be340b144562708a47e156e65dcbe18da38109cc Mon Sep 17 00:00:00 2001 From: Jiawei Lin Date: Mon, 13 Dec 2021 09:09:54 +0800 Subject: [PATCH] SoC: insert more buffers into mmio path (#1329) * SoC: add axi4spliter * pmp: add apply method to reduce loc * pma: add PMA used in axi4's spliter * Fix package import * pma: re-write tl-pma, put tl-pma into AXI4Spliter * pma: add memory mapped pma * soc: rm dma port, rm axi4spliter, mv mmpma out of spliter * csr: clear mstatus.mprv when mstatus.mpp != ModeM at xret * csr: fix write mask for mstatus, mepc and sepc This commit fixes the write mask for mstatus, mepc and sepc. According to the RISC-V instruction manual, for RV64 systems, the SXL and UXL fields are WARL fields that control the value of XLEN for S-mode and U-mode, respectively. For RV64 systems, if S-mode is not supported, then SXL is hardwired to zero. For RV64 systems, if U-mode is not supported, then UXL is hardwired to zero. Besides, mepc[0] and sepc[0] should be hardwired to zero. * wb,load: delay load fp for one cycle * csr: add mconfigptr, but hardwire to 0 now * bump huancun * csr: add *BE to mstatusStruct which are hardwired to 0 * Remove unused files * csr: fix bug of xret clear mprv * bump difftest * ci: add unit test, xret clear mstatus.mprv when xpp is not M * bump ready-to-run * mem,atomics: delay exception info for one cycle * SoC: insert more buffers into mmio path * SoC: insert buffer between l3_xbar and l3_banked_xbar * Optimze l3->ddr path * Bump huancun Co-authored-by: ZhangZifei Co-authored-by: Yinan Xu Co-authored-by: wangkaifan --- huancun | 2 +- src/main/scala/system/SoC.scala | 11 +++++++++-- src/main/scala/xiangshan/XSTile.scala | 12 +++++++----- 3 files changed, 17 insertions(+), 8 deletions(-) diff --git a/huancun b/huancun index a84196c0f..65291aa85 160000 --- a/huancun +++ b/huancun @@ -1 +1 @@ -Subproject commit a84196c0f525aaa5422cd1cfe0ed1e729b5f7c8f +Subproject commit 65291aa8554d6d2e6c76a204df680cca36ba3e55 diff --git a/src/main/scala/system/SoC.scala b/src/main/scala/system/SoC.scala index 0dac9cd37..71f205691 100644 --- a/src/main/scala/system/SoC.scala +++ b/src/main/scala/system/SoC.scala @@ -114,6 +114,8 @@ trait HaveSlaveAXI4Port { AXI4ToTL() := AXI4UserYanker(Some(1)) := AXI4Fragmenter() := + AXI4Buffer() := + AXI4Buffer() := AXI4IdIndexer(1) := l3FrontendAXI4Node errorDevice.node := error_xbar @@ -163,10 +165,12 @@ trait HaveAXI4MemPort { peripheralXbar memAXI4SlaveNode := + AXI4Buffer() := AXI4IdIndexer(idBits = 14) := AXI4UserYanker() := AXI4Deinterleaver(L3BlockSize) := TLToAXI4() := + TLSourceShrinker(64) := TLWidthWidget(L3OuterBusWidth / 8) := TLEdgeBuffer(_ => true, Some("MemXbar_to_DDR_buffer")) := mem_xbar @@ -206,9 +210,12 @@ trait HaveAXI4PeripheralPort { this: BaseSoC => AXI4IdIndexer(idBits = 2) := AXI4Buffer() := AXI4Buffer() := + AXI4Buffer() := + AXI4Buffer() := AXI4UserYanker() := AXI4Deinterleaver(8) := TLToAXI4() := + TLBuffer() := peripheralXbar val peripheral = InModuleBody { @@ -238,7 +245,7 @@ class SoCMisc()(implicit p: Parameters) extends BaseSoC } for(port <- peripheral_ports) { - peripheralXbar := TLBuffer.chainNode(1, Some("L2_to_L3_peripheral_buffer")) := port + peripheralXbar := TLBuffer.chainNode(2, Some("L2_to_L3_peripheral_buffer")) := port } for ((core_out, i) <- core_to_l3_ports.zipWithIndex){ @@ -247,7 +254,7 @@ class SoCMisc()(implicit p: Parameters) extends BaseSoC TLBuffer() := core_out } - l3_banked_xbar := l3_xbar + l3_banked_xbar := TLBuffer() := l3_xbar val clint = LazyModule(new CLINT(CLINTParams(0x38000000L), 8)) clint.node := peripheralXbar diff --git a/src/main/scala/xiangshan/XSTile.scala b/src/main/scala/xiangshan/XSTile.scala index 5f97b2479..51cc30172 100644 --- a/src/main/scala/xiangshan/XSTile.scala +++ b/src/main/scala/xiangshan/XSTile.scala @@ -42,6 +42,7 @@ class XSTileMisc()(implicit p: Parameters) extends LazyModule { val l1_xbar = TLXbar() val mmio_xbar = TLXbar() + val mmio_port = TLIdentityNode() // to L3 val memory_port = TLIdentityNode() val beu = LazyModule(new BusErrorUnit( new XSL1BusErrors(), BusErrorUnitParams(0x38010000), new GenericLogicalTreeNode @@ -63,9 +64,10 @@ class XSTileMisc()(implicit p: Parameters) extends LazyModule memory_port := l1_xbar } - mmio_xbar := TLBuffer() := i_mmio_port - mmio_xbar := TLBuffer() := d_mmio_port - beu.node := TLBuffer() := mmio_xbar + mmio_xbar := TLBuffer.chainNode(2) := i_mmio_port + mmio_xbar := TLBuffer.chainNode(2) := d_mmio_port + beu.node := TLBuffer.chainNode(1) := mmio_xbar + mmio_port := TLBuffer() := mmio_xbar lazy val module = new LazyModuleImp(this){ val beu_errors = IO(Input(chiselTypeOf(beu.module.io.errors))) @@ -87,7 +89,7 @@ class XSTile()(implicit p: Parameters) extends LazyModule // public ports val memory_port = misc.memory_port - val uncache = misc.mmio_xbar + val uncache = misc.mmio_port val clint_int_sink = core.clint_int_sink val plic_int_sink = core.plic_int_sink val debug_int_sink = core.debug_int_sink @@ -112,7 +114,7 @@ class XSTile()(implicit p: Parameters) extends LazyModule } l2cache match { case Some(l2) => - misc.l2_binder.get :*= l2.node :*= misc.l1_xbar + misc.l2_binder.get :*= l2.node :*= TLBuffer() :*= misc.l1_xbar case None => } -- GitLab