diff --git a/src/main/scala/xiangshan/frontend/IFU.scala b/src/main/scala/xiangshan/frontend/IFU.scala
index 13188c50deaf952f3e04037b3a8e15820792138e..3b95b02c661b4d03dd653a2dd9f79dcfd2830243 100644
--- a/src/main/scala/xiangshan/frontend/IFU.scala
+++ b/src/main/scala/xiangshan/frontend/IFU.scala
@@ -666,11 +666,10 @@ class NewIFU(implicit p: Parameters) extends XSModule
   checkFlushWb.bits.jalTarget         := wb_check_result.fixedTarget(ParallelPriorityEncoder(VecInit(wb_pd.zip(wb_instr_valid).map{case (pd, v) => v && pd.isJal })))
   checkFlushWb.bits.instrRange        := wb_instr_range.asTypeOf(Vec(PredictWidth, Bool()))
 
-  toFtq.pdWb := Mux(f3_req_is_mmio, mmioFlushWb,  checkFlushWb)
+  toFtq.pdWb := Mux(wb_valid, checkFlushWb,  mmioFlushWb)
 
   wb_redirect := checkFlushWb.bits.misOffset.valid && wb_valid
 
-
   /*write back flush type*/
   val checkFaultType = wb_check_result.faultType
   val checkJalFault =  wb_valid && checkFaultType.map(_.isjalFault).reduce(_||_)