diff --git a/src/main/scala/xiangshan/v2backend/Scheduler.scala b/src/main/scala/xiangshan/v2backend/Scheduler.scala
index f0b82799088af25f0f8632870580129099ca2bee..795c808b295ae93e7e571dd463b45d3ebc79e17b 100644
--- a/src/main/scala/xiangshan/v2backend/Scheduler.scala
+++ b/src/main/scala/xiangshan/v2backend/Scheduler.scala
@@ -194,7 +194,14 @@ class SchedulerMemImp(override val wrapper: Scheduler)(implicit params: SchdBloc
     stdIQ.io.enq.zip(staIQ.io.enq).foreach { case (stdIQEnq, staIQEnq) =>
       stdIQEnq.valid := staIQEnq.valid
       stdIQEnq.bits  := staIQEnq.bits
+      // Store data reuses store addr src(1) in dispatch2iq
+      // [dispatch2iq] --src*------src*(0)--> [staIQ]
+      //                       \
+      //                        ---src*(1)--> [stdIQ]
+      // Since the src(1) of sta is easier to get, stdIQEnq.bits.src*(0) is assigned to staIQEnq.bits.src*(1)
+      // instead of dispatch2Iq.io.out(x).bits.src*(1)
       stdIQEnq.bits.srcState(0) := staIQEnq.bits.srcState(1)
+      stdIQEnq.bits.srcType(0) := staIQEnq.bits.srcType(1)
       stdIQEnq.bits.psrc(0) := staIQEnq.bits.psrc(1)
       stdIQEnq.bits.sqIdx := staIQEnq.bits.sqIdx
     }