From b3b1e5c7f6321511357b4dca5853eb4d3259c7c0 Mon Sep 17 00:00:00 2001
From: LinJiawei <linjiawei20s@ict.ac.cn>
Date: Fri, 25 Mar 2022 15:26:08 +0800
Subject: [PATCH] Makefile: also gen time.log when make verilog

---
 Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Makefile b/Makefile
index 3058af975..54fccfd30 100644
--- a/Makefile
+++ b/Makefile
@@ -54,7 +54,7 @@ help:
 
 $(TOP_V): $(SCALA_FILE)
 	mkdir -p $(@D)
-	mill -i XiangShan.runMain $(FPGATOP) -td $(@D)                      \
+	$(TIME_CMD) mill -i XiangShan.runMain $(FPGATOP) -td $(@D)		\
 		--config $(CONFIG) --full-stacktrace --output-file $(@F)    \
 		--infer-rw --repl-seq-mem -c:$(FPGATOP):-o:$(@D)/$(@F).conf \
 		--gen-mem-verilog full --num-cores $(NUM_CORES)             \
-- 
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