From b211808bd227ebf2fe423a5c0b49e7a706fd1769 Mon Sep 17 00:00:00 2001
From: happy-lx <54952983+happy-lx@users.noreply.github.com>
Date: Mon, 5 Dec 2022 12:22:42 +0800
Subject: [PATCH] ROB, difftest: add robidx support (#1845)

* bump difftest and wire extra signals (robidx, lqidx, sqidx etc)
from ROB to difftest
---
 difftest                                       |  2 +-
 src/main/scala/xiangshan/backend/rob/Rob.scala | 12 ++++++++++++
 2 files changed, 13 insertions(+), 1 deletion(-)

diff --git a/difftest b/difftest
index f2c202466..9fa45204d 160000
--- a/difftest
+++ b/difftest
@@ -1 +1 @@
-Subproject commit f2c2024668a9011815f24f5684267aec87abd1f8
+Subproject commit 9fa45204da3bb274cd494448f7c84c9e2fca02d8
diff --git a/src/main/scala/xiangshan/backend/rob/Rob.scala b/src/main/scala/xiangshan/backend/rob/Rob.scala
index 3670620cd..fcfe7aaff 100644
--- a/src/main/scala/xiangshan/backend/rob/Rob.scala
+++ b/src/main/scala/xiangshan/backend/rob/Rob.scala
@@ -481,6 +481,10 @@ class RobImp(outer: Rob)(implicit p: Parameters) extends LazyModuleImp(outer)
       debug_microOp(wbIdx).debugInfo.issueTime := wb.bits.uop.debugInfo.issueTime
       debug_microOp(wbIdx).debugInfo.writebackTime := wb.bits.uop.debugInfo.writebackTime
 
+      // debug for lqidx and sqidx
+      debug_microOp(wbIdx).lqIdx := wb.bits.uop.lqIdx
+      debug_microOp(wbIdx).sqIdx := wb.bits.uop.sqIdx
+      
       val debug_Uop = debug_microOp(wbIdx)
       XSInfo(true.B,
         p"writebacked pc 0x${Hexadecimal(debug_Uop.cf.pc)} wen ${debug_Uop.ctrl.rfWen} " +
@@ -1009,6 +1013,9 @@ class RobImp(outer: Rob)(implicit p: Parameters) extends LazyModuleImp(outer)
   if (env.EnableDifftest) {
     for (i <- 0 until CommitWidth) {
       val difftest = Module(new DifftestInstrCommit)
+      // assgin default value
+      difftest.io := DontCare
+
       difftest.io.clock    := clock
       difftest.io.coreid   := io.hartId
       difftest.io.index    := i.U
@@ -1020,6 +1027,11 @@ class RobImp(outer: Rob)(implicit p: Parameters) extends LazyModuleImp(outer)
       difftest.io.valid    := RegNext(RegNext(RegNext(io.commits.commitValid(i) && io.commits.isCommit)))
       difftest.io.pc       := RegNext(RegNext(RegNext(SignExt(uop.cf.pc, XLEN))))
       difftest.io.instr    := RegNext(RegNext(RegNext(uop.cf.instr)))
+      difftest.io.robIdx   := RegNext(RegNext(RegNext(ZeroExt(ptr, 10))))
+      difftest.io.lqIdx    := RegNext(RegNext(RegNext(ZeroExt(uop.lqIdx.value, 7))))
+      difftest.io.sqIdx    := RegNext(RegNext(RegNext(ZeroExt(uop.sqIdx.value, 7))))
+      difftest.io.isLoad   := RegNext(RegNext(RegNext(io.commits.info(i).commitType === CommitType.LOAD)))
+      difftest.io.isStore  := RegNext(RegNext(RegNext(io.commits.info(i).commitType === CommitType.STORE)))
       difftest.io.special  := RegNext(RegNext(RegNext(CommitType.isFused(io.commits.info(i).commitType))))
       // when committing an eliminated move instruction,
       // we must make sure that skip is properly set to false (output from EXU is random value)
-- 
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