From af5cf0d1007267d950e8c5df350edfc7db257f60 Mon Sep 17 00:00:00 2001
From: Yinan Xu <xuyinan1997@gmail.com>
Date: Tue, 24 Nov 2020 10:12:25 +0800
Subject: [PATCH] Regfile: use regfile_160x64_10w16r_sim for blackbox module
 name

---
 src/main/scala/xiangshan/backend/regfile/Regfile.scala | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/main/scala/xiangshan/backend/regfile/Regfile.scala b/src/main/scala/xiangshan/backend/regfile/Regfile.scala
index e7ab2049a..04e833a76 100644
--- a/src/main/scala/xiangshan/backend/regfile/Regfile.scala
+++ b/src/main/scala/xiangshan/backend/regfile/Regfile.scala
@@ -62,7 +62,7 @@ class Regfile
     )
   } else {
 
-	val regfile = Module(new RegfileBlackBox)
+	val regfile = Module(new regfile_160x64_10w16r_sim)
 
 	regfile.io.clk := this.clock
 	regfile.io.gpr := hasZero.B
@@ -143,7 +143,7 @@ class Regfile
 
 }
 
-class RegfileBlackBox extends BlackBox with HasBlackBoxResource {
+class regfile_160x64_10w16r_sim extends BlackBox with HasBlackBoxResource {
 
   val io = IO(new Bundle{
 	val clk = Input(Clock())
-- 
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