diff --git a/src/main/scala/xiangshan/backend/regfile/Regfile.scala b/src/main/scala/xiangshan/backend/regfile/Regfile.scala
index e7ab2049a0099980b1eab7563bf839a6e040f26a..04e833a76f5836fd8ae057760db21eab1ae367b9 100644
--- a/src/main/scala/xiangshan/backend/regfile/Regfile.scala
+++ b/src/main/scala/xiangshan/backend/regfile/Regfile.scala
@@ -62,7 +62,7 @@ class Regfile
     )
   } else {
 
-	val regfile = Module(new RegfileBlackBox)
+	val regfile = Module(new regfile_160x64_10w16r_sim)
 
 	regfile.io.clk := this.clock
 	regfile.io.gpr := hasZero.B
@@ -143,7 +143,7 @@ class Regfile
 
 }
 
-class RegfileBlackBox extends BlackBox with HasBlackBoxResource {
+class regfile_160x64_10w16r_sim extends BlackBox with HasBlackBoxResource {
 
   val io = IO(new Bundle{
 	val clk = Input(Clock())