diff --git a/src/main/scala/xiangshan/frontend/FTB.scala b/src/main/scala/xiangshan/frontend/FTB.scala
index 8feb1b1662c9c16c61b7f7c66275b39960db14f2..2b66718cbc23df05caca334489bb247b315d17dc 100644
--- a/src/main/scala/xiangshan/frontend/FTB.scala
+++ b/src/main/scala/xiangshan/frontend/FTB.scala
@@ -295,6 +295,9 @@ class FTB(implicit p: Parameters) extends BasePredictor with FTBParams with BPUU
       val update_write_data = Flipped(Valid(new FTBEntryWithTag))
       val update_write_way = Input(UInt(log2Ceil(numWays).W))
       val update_write_alloc = Input(Bool())
+
+      val try_to_write_way = Flipped(Valid(UInt(log2Ceil(numWays).W)))
+      val try_to_write_pc = Input(UInt(VAddrBits.W))
     })
 
     // Extract holdRead logic to fix bug that update read override predict read result
@@ -342,10 +345,20 @@ class FTB(implicit p: Parameters) extends BasePredictor with FTBParams with BPUU
     val touch_set = Seq.fill(1)(Wire(UInt(log2Ceil(numSets).W)))
     val touch_way = Seq.fill(1)(Wire(Valid(UInt(log2Ceil(numWays).W))))
 
-    touch_set(0) := req_idx
+    val write_set = Wire(UInt(log2Ceil(numSets).W))
+    val write_way = Wire(Valid(UInt(log2Ceil(numWays).W)))
+
+    val read_set = Wire(UInt(log2Ceil(numSets).W))
+    val read_way = Wire(Valid(UInt(log2Ceil(numWays).W)))
+
+    read_set := req_idx
+    read_way.valid := hit
+    read_way.bits  := hit_way
+
+    touch_set(0) := Mux(write_way.valid, write_set, read_set)
 
-    touch_way(0).valid := hit
-    touch_way(0).bits := hit_way
+    touch_way(0).valid := write_way.valid || read_way.valid
+    touch_way(0).bits := Mux(write_way.valid, write_way.bits, read_way.bits)
 
     replacer.access(touch_set, touch_way)
 
@@ -411,6 +424,14 @@ class FTB(implicit p: Parameters) extends BasePredictor with FTBParams with BPUU
 
     ftb.io.w.apply(u_valid, u_data, u_idx, u_mask)
 
+    // for replacer
+    write_set := Mux(u_valid, u_idx, ftbAddr.getIdx(io.try_to_write_pc))
+    write_way.valid := u_valid || io.try_to_write_way.valid
+    write_way.bits := Mux(u_valid,
+      Mux(io.update_write_alloc, allocWriteWay, io.update_write_way),
+      io.try_to_write_way.bits
+    )
+
     // print hit entry info
     Mux1H(total_hits, ftb.io.r.resp.data).display(true.B)
   } // FTBBank
@@ -502,6 +523,11 @@ class FTB(implicit p: Parameters) extends BasePredictor with FTBParams with BPUU
   ftbBank.io.update_access := u_valid && !u_meta.hit
   ftbBank.io.s1_fire := io.s1_fire
 
+  // for replacer
+  ftbBank.io.try_to_write_way.valid := RegNext(io.update.valid) && u_meta.hit
+  ftbBank.io.try_to_write_way.bits := u_meta.writeWay
+  ftbBank.io.try_to_write_pc := update.pc
+
   XSDebug("req_v=%b, req_pc=%x, ready=%b (resp at next cycle)\n", io.s0_fire, s0_pc, ftbBank.io.req_pc.ready)
   XSDebug("s2_hit=%b, hit_way=%b\n", s2_hit, writeWay.asUInt)
   XSDebug("s2_br_taken_mask=%b, s2_real_taken_mask=%b\n",