From a2b3dd86b054d32b0b88fc7cc466bc726d2eaf80 Mon Sep 17 00:00:00 2001 From: LinJiawei Date: Wed, 5 Aug 2020 11:01:32 +0800 Subject: [PATCH] Brq: fix replay bug --- src/main/scala/xiangshan/backend/brq/Brq.scala | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/src/main/scala/xiangshan/backend/brq/Brq.scala b/src/main/scala/xiangshan/backend/brq/Brq.scala index 051017a36..16de7d4bb 100644 --- a/src/main/scala/xiangshan/backend/brq/Brq.scala +++ b/src/main/scala/xiangshan/backend/brq/Brq.scala @@ -182,7 +182,7 @@ class Brq extends XSModule { io.redirect.valid := commitValid && commitIsMisPred && !io.roqRedirect.valid && - !(io.memRedirect.valid && io.redirect.bits.needFlush(io.memRedirect)) + !io.redirect.bits.needFlush(io.memRedirect) io.redirect.bits := commitEntry.exuOut.redirect io.out.valid := commitValid @@ -238,13 +238,15 @@ class Brq extends XSModule { val ptr = BrqPtr(brQueue(i).ptrFlag, i.U) when( (io.redirect.valid && ptr.needBrFlush(io.redirect.bits.brTag)) || - (io.memRedirect.valid && ptr.needBrFlush(io.memRedirect.bits.brTag)) + (s.isWb && brQueue(i).exuOut.uop.needFlush(io.memRedirect)) ){ s := s_idle } }) - tailPtr := io.redirect.bits.brTag + true.B - } // replay: do nothing + when(io.redirect.valid){ // Only Br Mispred reset tailPtr, replay does not + tailPtr := io.redirect.bits.brTag + true.B + } + } -- GitLab