diff --git a/block-inclusivecache-sifive b/block-inclusivecache-sifive
index f3049304ceb2dba734d390dc5e3612654e894688..cfd003e9140c958926bece6ea3cf9782c0930d5a 160000
--- a/block-inclusivecache-sifive
+++ b/block-inclusivecache-sifive
@@ -1 +1 @@
-Subproject commit f3049304ceb2dba734d390dc5e3612654e894688
+Subproject commit cfd003e9140c958926bece6ea3cf9782c0930d5a
diff --git a/src/main/scala/system/SoC.scala b/src/main/scala/system/SoC.scala
index 471273f52a0145ca1de1855479604e268a39ce88..054464916801001f626d47a5cf5a5bb3ed7052ad 100644
--- a/src/main/scala/system/SoC.scala
+++ b/src/main/scala/system/SoC.scala
@@ -76,6 +76,7 @@ class XSSoc()(implicit p: Parameters) extends LazyModule with HasSoCParameter {
       sets = L2NSets,
       blockBytes = L2BlockSize,
       beatBytes = L1BusWidth / 8, // beatBytes = l1BusDataWidth / 8
+      replacement = "plru",
       cacheName = s"L2",
       enablePerf = env.EnablePerfDebug && !env.FPGAPlatform
     ),
@@ -97,6 +98,7 @@ class XSSoc()(implicit p: Parameters) extends LazyModule with HasSoCParameter {
       sets = L3NSets,
       blockBytes = L3BlockSize,
       beatBytes = L2BusWidth / 8,
+      replacement = "plru",
       cacheName = "L3",
       enablePerf = env.EnablePerfDebug && !env.FPGAPlatform
     ),