From 9cba68b6fbfdbfebc415bcb1e5378d7d35d1681e Mon Sep 17 00:00:00 2001 From: Yinan Xu Date: Sat, 27 Feb 2021 22:43:04 +0800 Subject: [PATCH] rs: fix replay delay to avoid deadlock (#604) * intWb: set wb.valid when !fpwen to allow writeback if !fpwen and !rfwen * rs: fix replay delay to avoid deadlock * load: fix tlb feedback --- .../xiangshan/backend/issue/ReservationStation.scala | 10 ++-------- 1 file changed, 2 insertions(+), 8 deletions(-) diff --git a/src/main/scala/xiangshan/backend/issue/ReservationStation.scala b/src/main/scala/xiangshan/backend/issue/ReservationStation.scala index 098bf49f8..b336e4024 100644 --- a/src/main/scala/xiangshan/backend/issue/ReservationStation.scala +++ b/src/main/scala/xiangshan/backend/issue/ReservationStation.scala @@ -199,13 +199,7 @@ class ReservationStationSelect val fastPortsCnt = fastPortsCfg.size val slowPortsCnt = slowPortsCfg.size require(nonBlocked==fastWakeup) - val delayMap = Map( - 0 -> 5, - 1 -> 10, - 2 -> 40, - 3 -> 40 - ) - def replayDelay(times: UInt) = ParallelMux((0 until 4).map( i => (i.U === times, delayMap(i).U))) + val replayDelay = VecInit(Seq(5, 10, 40, 40).map(_.U(6.W))) val io = IO(new Bundle { val redirect = Flipped(ValidIO(new Redirect)) @@ -248,7 +242,7 @@ class ReservationStationSelect val indexQueue = RegInit(VecInit((0 until iqSize).map(_.U(iqIdxWidth.W)))) val validQueue = VecInit(stateQueue.map(_ === s_valid)) val emptyQueue = VecInit(stateQueue.map(_ === s_idle)) - val countQueue = Reg(Vec(iqSize, UInt(log2Up(delayMap(3)).W))) + val countQueue = Reg(Vec(iqSize, UInt(replayDelay(3).getWidth.W))) val cntCountQueue = Reg(Vec(iqSize, UInt(2.W))) val validIdxQueue = widthMap(i => validQueue(indexQueue(i))) val readyIdxQueue = widthMap(i => validQueue(indexQueue(i)) && io.readyVec(indexQueue(i))) -- GitLab