From 9b6529a71933e23931fdb35d9bc17a11c941a733 Mon Sep 17 00:00:00 2001
From: BigWhiteDog <legend.z@foxmail.com>
Date: Thu, 21 Jan 2021 14:25:32 +0800
Subject: [PATCH] fix bug in amo test,  but it can't run with store test

---
 src/test/scala/cache/L1DTest/CoreAgent.scala       | 2 +-
 src/test/scala/cache/L1DTest/CoreTransatcion.scala | 2 +-
 src/test/scala/cache/L1DTest/L1DTest.scala         | 4 ++--
 3 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/test/scala/cache/L1DTest/CoreAgent.scala b/src/test/scala/cache/L1DTest/CoreAgent.scala
index 8a9c23710..4f125f756 100644
--- a/src/test/scala/cache/L1DTest/CoreAgent.scala
+++ b/src/test/scala/cache/L1DTest/CoreAgent.scala
@@ -156,7 +156,7 @@ class CoreAgent(ID: Int, name: String, addrStateMap: mutable.Map[BigInt, AddrSta
           val aid = allocId.get
           //alloc & issue
           amoPortReqMessage = Some(nextAMO.get.issueReq(BigInt(aid)))
-          amoIdMap(BigInt(aid))
+          amoIdMap(BigInt(aid)) = nextAMO.get
         }
       }
     }
diff --git a/src/test/scala/cache/L1DTest/CoreTransatcion.scala b/src/test/scala/cache/L1DTest/CoreTransatcion.scala
index 4fd272ec0..909c998f4 100644
--- a/src/test/scala/cache/L1DTest/CoreTransatcion.scala
+++ b/src/test/scala/cache/L1DTest/CoreTransatcion.scala
@@ -131,7 +131,7 @@ class DCacheAMOCallerTrans extends DCacheAMOTrans with TLCCallerTrans {
         mask = mask,
       )
     )
-    reqIssued = Some(true)
+    reqIssued = Some(false)
   }
 
   def issueReq(allodId: BigInt = 0): LitDCacheWordReq = {
diff --git a/src/test/scala/cache/L1DTest/L1DTest.scala b/src/test/scala/cache/L1DTest/L1DTest.scala
index 599971563..a5aefc105 100644
--- a/src/test/scala/cache/L1DTest/L1DTest.scala
+++ b/src/test/scala/cache/L1DTest/L1DTest.scala
@@ -64,7 +64,7 @@ class L1DCacheTest extends AnyFlatSpec with ChiselScalatestTester with Matchers
 
     val rand = new Random(0xbeef)
     val addr_pool = {
-      for (_ <- 0 until 64) yield BigInt(rand.nextInt(0xfffff) << 6) | 0x80000000L.U.litValue()
+      for (_ <- 0 until 256) yield BigInt(rand.nextInt(0xfffff) << 6) | 0x80000000L.U.litValue()
     }.distinct.toList // align to block size
     val addr_list_len = addr_pool.length
     println(f"addr pool length: $addr_list_len")
@@ -114,7 +114,7 @@ class L1DCacheTest extends AnyFlatSpec with ChiselScalatestTester with Matchers
         c.io.slaveIO.DChannel.valid.poke(false.B)
 
 
-        val total_clock = 500
+        val total_clock = 50000
 
         c.reset.poke(true.B)
         c.clock.step(100)
-- 
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