diff --git a/src/main/scala/xiangshan/cache/mmu/TLB.scala b/src/main/scala/xiangshan/cache/mmu/TLB.scala
index c901bb2972ce234bbcfac0a77386d97095ab6b4c..90e304bdd89fb4baeb9e3757f28bf947d8695966 100644
--- a/src/main/scala/xiangshan/cache/mmu/TLB.scala
+++ b/src/main/scala/xiangshan/cache/mmu/TLB.scala
@@ -184,6 +184,7 @@ class TLB(Width: Int, Block: Seq[Boolean], q: TLBParameters)(implicit p: Paramet
   def handle_nonblock(idx: Int): Unit = {
     io.requestor(idx).resp.valid := req_out_v(idx)
     io.requestor(idx).req.ready := io.requestor(idx).resp.ready // should always be true
+    XSError(!io.requestor(idx).resp.ready, s"${q.name} port ${idx} is non-block, resp.ready must be true.B")
 
     val ptw_just_back = ptw.resp.fire && ptw.resp.bits.entry.hit(get_pn(req_out(idx).vaddr), asid = io.csr.satp.asid, allType = true)
     io.ptw.req(idx).valid :=  RegNext(req_out_v(idx) && missVec(idx) && !ptw_just_back, false.B) // TODO: remove the regnext, timing
diff --git a/src/main/scala/xiangshan/cache/mmu/TLBStorage.scala b/src/main/scala/xiangshan/cache/mmu/TLBStorage.scala
index 81f4be3eb456ed554fa4f966a25e7b007bbacefe..d1a8896184a6bf779b5c7913c79073d80f7e8bb2 100644
--- a/src/main/scala/xiangshan/cache/mmu/TLBStorage.scala
+++ b/src/main/scala/xiangshan/cache/mmu/TLBStorage.scala
@@ -83,6 +83,9 @@ class TLBFA(
     v(io.w.bits.wayIdx) := true.B
     entries(io.w.bits.wayIdx).apply(io.w.bits.data, io.csr.satp.asid, io.w.bits.data_replenish)
   }
+  // write assert, shoulg not duplicate with the existing entries
+  val w_hit_vec = VecInit(entries.zip(v).map{case (e, vi) => e.hit(io.w.bits.data.entry.tag, io.csr.satp.asid) && vi })
+  XSError(io.w.valid && Cat(w_hit_vec).orR, s"${parentName} refill, duplicate with existing entries")
 
   val refill_vpn_reg = RegNext(io.w.bits.data.entry.tag)
   val refill_wayIdx_reg = RegNext(io.w.bits.wayIdx)
@@ -302,7 +305,7 @@ class TlbStorageWrapper(ports: Int, q: TLBParameters)(implicit p: Parameters) ex
 
 // TODO: wrap Normal page and super page together, wrap the declare & refill dirty codes
   val normalPage = TlbStorage(
-    parentName = q.name + "_storage",
+    parentName = q.name + "_np_storage",
     associative = q.normalAssociative,
     ports = ports,
     nSets = q.normalNSets,
@@ -312,7 +315,7 @@ class TlbStorageWrapper(ports: Int, q: TLBParameters)(implicit p: Parameters) ex
     superPage = false
   )
   val superPage = TlbStorage(
-    parentName = q.name + "_storage",
+    parentName = q.name + "_sp_storage",
     associative = q.superAssociative,
     ports = ports,
     nSets = q.superNSets,
diff --git a/src/main/scala/xiangshan/mem/pipeline/AtomicsUnit.scala b/src/main/scala/xiangshan/mem/pipeline/AtomicsUnit.scala
index 53218336df2e55404005754f0692b01073b92021..e3ac52012506ab4e608f9ac7d9d01dcb9b1743a6 100644
--- a/src/main/scala/xiangshan/mem/pipeline/AtomicsUnit.scala
+++ b/src/main/scala/xiangshan/mem/pipeline/AtomicsUnit.scala
@@ -86,7 +86,7 @@ class AtomicsUnit(implicit p: Parameters) extends XSModule with MemoryOpConstant
 
   io.dtlb.req.valid    := false.B
   io.dtlb.req.bits     := DontCare
-  io.dtlb.resp.ready   := false.B
+  io.dtlb.resp.ready   := true.B
 
   io.flush_sbuffer.valid := false.B
 
@@ -125,7 +125,6 @@ class AtomicsUnit(implicit p: Parameters) extends XSModule with MemoryOpConstant
     // keep firing until tlb hit
     io.dtlb.req.valid       := true.B
     io.dtlb.req.bits.vaddr  := in.src(0)
-    io.dtlb.resp.ready      := true.B
     val is_lr = in.uop.ctrl.fuOpType === LSUOpType.lr_w || in.uop.ctrl.fuOpType === LSUOpType.lr_d
     io.dtlb.req.bits.cmd    := Mux(is_lr, TlbCmd.atom_read, TlbCmd.atom_write)
     io.dtlb.req.bits.debug.robIdx := in.uop.robIdx