diff --git a/src/main/scala/xiangshan/frontend/icache/ReleaseUnit.scala b/src/main/scala/xiangshan/frontend/icache/ReleaseUnit.scala
index a5643a340a87d74a75b6d72d03d81645bcbbf913..730745dfd80122846cd768766c4433abf269ce10 100644
--- a/src/main/scala/xiangshan/frontend/icache/ReleaseUnit.scala
+++ b/src/main/scala/xiangshan/frontend/icache/ReleaseUnit.scala
@@ -39,7 +39,7 @@ class ICacheReleaseBundle(implicit p: Parameters) extends  ICacheBundle{
   val req = Vec(2, Flipped(DecoupledIO(new ReleaseReq)))
 }
 
-class RealeaseEntry(edge: TLEdgeOut)(implicit p: Parameters) extends ICacheModule
+class ReleaseEntry(edge: TLEdgeOut)(implicit p: Parameters) extends ICacheModule
 {
   val io = IO(new Bundle {
     val id = Input(UInt())
@@ -149,7 +149,7 @@ class ReleaseUnit(edge: TLEdgeOut)(implicit p: Parameters) extends ICacheModule
   io.mem_release.bits  := DontCare
   io.mem_grant.ready   := false.B
 
-  val entry = Module(new RealeaseEntry(edge))
+  val entry = Module(new ReleaseEntry(edge))
 
   entry.io.id := 0.U
 
@@ -165,4 +165,4 @@ class ReleaseUnit(edge: TLEdgeOut)(implicit p: Parameters) extends ICacheModule
   io.mem_release <> entry.io.mem_release
   io.finish := entry.io.finish
 
-}
\ No newline at end of file
+}