From 90f3858e6a0d293de9449fe9a312e55c4a2ef4b3 Mon Sep 17 00:00:00 2001 From: Yinan Xu Date: Thu, 10 Sep 2020 17:50:31 +0800 Subject: [PATCH] csr: flushPipe when satp is written --- src/main/scala/xiangshan/backend/roq/Roq.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/xiangshan/backend/roq/Roq.scala b/src/main/scala/xiangshan/backend/roq/Roq.scala index 9d718c5c8..c59e82980 100644 --- a/src/main/scala/xiangshan/backend/roq/Roq.scala +++ b/src/main/scala/xiangshan/backend/roq/Roq.scala @@ -89,7 +89,7 @@ class Roq extends XSModule { val wbIdx = wbIdxExt.tail(1) writebacked(wbIdx) := true.B microOp(wbIdx).cf.exceptionVec := io.exeWbResults(i).bits.uop.cf.exceptionVec - microOp(wbIdx).ctrl.flushPipe := io.exeWbResults(i).bits.uop.ctrl.flushPipe + microOp(wbIdx).ctrl.flushPipe := io.exeWbResults(i).bits.uop.ctrl.flushPipe exuData(wbIdx) := io.exeWbResults(i).bits.data exuDebug(wbIdx) := io.exeWbResults(i).bits.debug -- GitLab