diff --git a/src/main/scala/utils/BitUtils.scala b/src/main/scala/utils/BitUtils.scala
index 9ab3e7a6fb7a29b8b0be87602985138f76afeef0..c2e5baf8f39791ee5898dcd3b8266d2f41d3e8d0 100644
--- a/src/main/scala/utils/BitUtils.scala
+++ b/src/main/scala/utils/BitUtils.scala
@@ -116,3 +116,16 @@ object GenMask {
 object UIntToMask {
   def apply(ptr: UInt, length: Integer) = UIntToOH(ptr)(length - 1, 0) - 1.U
 }
+
+object GetEvenBits {
+  def apply(input: UInt): UInt = {
+    VecInit((0 until input.getWidth/2).map(i => {input(2*i)})).asUInt
+  }
+}
+
+
+object GetOddBits {
+  def apply(input: UInt): UInt = {
+    VecInit((0 until input.getWidth/2).map(i => {input(2*i+1)})).asUInt
+  }
+}
\ No newline at end of file
diff --git a/src/main/scala/xiangshan/mem/sbuffer/NewSbuffer.scala b/src/main/scala/xiangshan/mem/sbuffer/NewSbuffer.scala
index 61de249858e263a1c2ae6d7c5bf86859662a2a0a..505087f21f39bdcc3df67d96a778422e27b78a1f 100644
--- a/src/main/scala/xiangshan/mem/sbuffer/NewSbuffer.scala
+++ b/src/main/scala/xiangshan/mem/sbuffer/NewSbuffer.scala
@@ -195,14 +195,24 @@ class NewSbuffer extends XSModule with HasSbufferCst {
   // firstInsert: the first invalid entry
   // if first entry canMerge or second entry has the same tag with the first entry , secondInsert equal the first invalid entry, otherwise, the second invalid entry
   val invalidMask = stateRead.map(s => s === s_invalid)
-  val firstInsertMask = PriorityEncoderOH(invalidMask)
-  val secondInsertMask = Wire(Vec(StoreBufferSize, Bool()))
-  for (i <- 0 until StoreBufferSize){
-    secondInsertMask(i) := Mux(canMerge(0) || sameTag, firstInsertMask(i), invalidMask(i) - firstInsertMask(i))
+  val evenInvalidMask = GetEvenBits(VecInit(invalidMask).asUInt)
+  val oddInvalidMask = GetOddBits(VecInit(invalidMask).asUInt)
+
+  val (evenRawInsertIdx, evenCanInsert) = PriorityEncoderWithFlag(evenInvalidMask)
+  val (oddRawInsertIdx, oddCanInsert) = PriorityEncoderWithFlag(oddInvalidMask)
+  val evenInsertIdx = Cat(evenRawInsertIdx, 0.U(1.W))
+  val oddInsertIdx = Cat(oddRawInsertIdx, 1.U(1.W))
+
+  val enbufferSelReg = RegInit(false.B)
+  when(io.in(0).valid) {
+    enbufferSelReg := ~enbufferSelReg
   }
 
-  val (firstInsertIdx, firstCanInsert) = PriorityEncoderWithFlag(invalidMask)
-  val (secondInsertIdx, secondCanInsert) = PriorityEncoderWithFlag(secondInsertMask)
+  val firstInsertIdx = Mux(enbufferSelReg, evenInsertIdx, oddInsertIdx)
+  val secondInsertIdx = Mux(~enbufferSelReg, evenInsertIdx, oddInsertIdx)
+
+  val firstCanInsert = Mux(enbufferSelReg, evenCanInsert, oddCanInsert)
+  val secondCanInsert = Mux(~enbufferSelReg, evenCanInsert, oddCanInsert)
 
   io.in(0).ready := firstCanInsert || canMerge(0)
   io.in(1).ready := (secondCanInsert || canMerge(1)) && !sameWord && io.in(0).ready