diff --git a/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala b/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala
index 8a165274fb42a0b3fee0f1790e98ba740b7681e6..fe2ec389daf3ff32312376c662544868a387898c 100644
--- a/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala
+++ b/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala
@@ -466,7 +466,9 @@ class LoadQueue extends XSModule with HasDCacheParameters with HasCircularQueueP
   val lastCycleRedirect = RegNext(io.brqRedirect)
 
   io.rollback := DontCare
-  io.rollback.valid := rollbackSelected.valid && (!lastCycleRedirect.valid || isAfter(lastCycleRedirect.bits.roqIdx, rollbackSelected.bits.roqIdx))
+  // Note that we use roqIdx - 1.U to flush the load instruction itself.
+  // Thus, here if last cycle's roqIdx equals to this cycle's roqIdx, it still triggers the redirect.
+  io.rollback.valid := rollbackSelected.valid && (!lastCycleRedirect.valid || !isAfter(rollbackSelected.bits.roqIdx, lastCycleRedirect.bits.roqIdx))
 
   io.rollback.bits.roqIdx := rollbackSelected.bits.roqIdx - 1.U
   io.rollback.bits.isReplay := true.B