From 83596a0378c16bb18fec2eb9b4f00f04c7b81039 Mon Sep 17 00:00:00 2001 From: Yinan Xu Date: Mon, 26 Apr 2021 11:03:46 +0800 Subject: [PATCH] uop,needRfRPort: ignore srcState by default (#784) --- src/main/scala/xiangshan/Bundle.scala | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/src/main/scala/xiangshan/Bundle.scala b/src/main/scala/xiangshan/Bundle.scala index 2ce982de7..b726912c4 100644 --- a/src/main/scala/xiangshan/Bundle.scala +++ b/src/main/scala/xiangshan/Bundle.scala @@ -303,13 +303,13 @@ class MicroOp(implicit p: Parameters) extends CfCtrl { val sqIdx = new SqPtr val diffTestDebugLrScValid = Bool() val debugInfo = new PerfDebugInfo - def needRfRPort(index: Int, rfType: Int) : Bool = { + def needRfRPort(index: Int, rfType: Int, ignoreState: Boolean = true) : Bool = { (index, rfType) match { - case (0, 0) => ctrl.src1Type === SrcType.reg && ctrl.lsrc1 =/= 0.U && src1State === SrcState.rdy - case (1, 0) => ctrl.src2Type === SrcType.reg && ctrl.lsrc2 =/= 0.U && src1State === SrcState.rdy - case (0, 1) => ctrl.src1Type === SrcType.fp && src1State === SrcState.rdy - case (1, 1) => ctrl.src2Type === SrcType.fp && src1State === SrcState.rdy - case (2, 1) => ctrl.src3Type === SrcType.fp && src1State === SrcState.rdy + case (0, 0) => ctrl.src1Type === SrcType.reg && ctrl.lsrc1 =/= 0.U && (src1State === SrcState.rdy || ignoreState.B) + case (1, 0) => ctrl.src2Type === SrcType.reg && ctrl.lsrc2 =/= 0.U && (src2State === SrcState.rdy || ignoreState.B) + case (0, 1) => ctrl.src1Type === SrcType.fp && (src1State === SrcState.rdy || ignoreState.B) + case (1, 1) => ctrl.src2Type === SrcType.fp && (src2State === SrcState.rdy || ignoreState.B) + case (2, 1) => ctrl.src3Type === SrcType.fp && (src3State === SrcState.rdy || ignoreState.B) case _ => false.B } } -- GitLab