From 7f93b3aad4cda611ec2dfe4bc915b0e76633bf21 Mon Sep 17 00:00:00 2001 From: Lingrui98 Date: Fri, 18 Dec 2020 11:06:33 +0800 Subject: [PATCH] tage: remove flush signal in req.valid --- src/main/scala/xiangshan/frontend/Tage.scala | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/main/scala/xiangshan/frontend/Tage.scala b/src/main/scala/xiangshan/frontend/Tage.scala index 89837258d..f4d6361ff 100644 --- a/src/main/scala/xiangshan/frontend/Tage.scala +++ b/src/main/scala/xiangshan/frontend/Tage.scala @@ -408,7 +408,7 @@ class Tage extends BaseTage { val tables = TableInfo.map { case (nRows, histLen, tagLen) => { val t = if(EnableBPD) Module(new TageTable(nRows, histLen, tagLen, UBitPeriod)) else Module(new FakeTageTable) - t.io.req.valid := io.pc.valid && !io.flush + t.io.req.valid := io.pc.valid t.io.req.bits.pc := io.pc.bits t.io.req.bits.hist := io.hist t.io.req.bits.mask := io.inMask @@ -420,7 +420,7 @@ class Tage extends BaseTage { case (nRows, ctrBits, histLen) => { val t = if (EnableSC) Module(new SCTable(nRows/TageBanks, ctrBits, histLen)) else Module(new FakeSCTable) val req = t.io.req - req.valid := io.pc.valid && !io.flush + req.valid := io.pc.valid req.bits.pc := io.pc.bits req.bits.hist := io.hist req.bits.mask := io.inMask -- GitLab